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-rw-r--r--drivers/pinctrl/Kconfig2
-rw-r--r--drivers/pinctrl/core.c4
-rw-r--r--drivers/pinctrl/pinconf.c4
-rw-r--r--drivers/pinctrl/pinctrl-bcm2835.c5
-rw-r--r--drivers/pinctrl/pinctrl-nomadik.c28
-rw-r--r--drivers/pinctrl/pinctrl-samsung.c10
-rw-r--r--drivers/pinctrl/pinctrl-sirf.c35
-rw-r--r--drivers/pinctrl/pinctrl-tegra.c2
-rw-r--r--drivers/pinctrl/pinctrl-tegra30.c24
-rw-r--r--drivers/pinctrl/pinctrl-xway.c2
-rw-r--r--drivers/pinctrl/spear/pinctrl-spear.c2
-rw-r--r--drivers/pinctrl/spear/pinctrl-spear1310.c365
-rw-r--r--drivers/pinctrl/spear/pinctrl-spear1340.c41
-rw-r--r--drivers/pinctrl/spear/pinctrl-spear320.c8
-rw-r--r--drivers/pinctrl/spear/pinctrl-spear3xx.h1
15 files changed, 409 insertions, 124 deletions
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index 7bf914df6e9..d96caefd914 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -179,11 +179,13 @@ config PINCTRL_COH901
179 179
180config PINCTRL_SAMSUNG 180config PINCTRL_SAMSUNG
181 bool "Samsung pinctrl driver" 181 bool "Samsung pinctrl driver"
182 depends on OF && GPIOLIB
182 select PINMUX 183 select PINMUX
183 select PINCONF 184 select PINCONF
184 185
185config PINCTRL_EXYNOS4 186config PINCTRL_EXYNOS4
186 bool "Pinctrl driver data for Exynos4 SoC" 187 bool "Pinctrl driver data for Exynos4 SoC"
188 depends on OF && GPIOLIB
187 select PINCTRL_SAMSUNG 189 select PINCTRL_SAMSUNG
188 190
189config PINCTRL_MVEBU 191config PINCTRL_MVEBU
diff --git a/drivers/pinctrl/core.c b/drivers/pinctrl/core.c
index 0f1ec9e8ff1..2e39c04fc16 100644
--- a/drivers/pinctrl/core.c
+++ b/drivers/pinctrl/core.c
@@ -1061,8 +1061,10 @@ static int pinctrl_groups_show(struct seq_file *s, void *what)
1061 seq_printf(s, "group: %s\n", gname); 1061 seq_printf(s, "group: %s\n", gname);
1062 for (i = 0; i < num_pins; i++) { 1062 for (i = 0; i < num_pins; i++) {
1063 pname = pin_get_name(pctldev, pins[i]); 1063 pname = pin_get_name(pctldev, pins[i]);
1064 if (WARN_ON(!pname)) 1064 if (WARN_ON(!pname)) {
1065 mutex_unlock(&pinctrl_mutex);
1065 return -EINVAL; 1066 return -EINVAL;
1067 }
1066 seq_printf(s, "pin %d (%s)\n", pins[i], pname); 1068 seq_printf(s, "pin %d (%s)\n", pins[i], pname);
1067 } 1069 }
1068 seq_puts(s, "\n"); 1070 seq_puts(s, "\n");
diff --git a/drivers/pinctrl/pinconf.c b/drivers/pinctrl/pinconf.c
index 43f474cdc11..baee2cc46a1 100644
--- a/drivers/pinctrl/pinconf.c
+++ b/drivers/pinctrl/pinconf.c
@@ -537,8 +537,6 @@ static int pinconf_groups_show(struct seq_file *s, void *what)
537 seq_puts(s, "Pin config settings per pin group\n"); 537 seq_puts(s, "Pin config settings per pin group\n");
538 seq_puts(s, "Format: group (name): configs\n"); 538 seq_puts(s, "Format: group (name): configs\n");
539 539
540 mutex_lock(&pinctrl_mutex);
541
542 while (selector < ngroups) { 540 while (selector < ngroups) {
543 const char *gname = pctlops->get_group_name(pctldev, selector); 541 const char *gname = pctlops->get_group_name(pctldev, selector);
544 542
@@ -549,8 +547,6 @@ static int pinconf_groups_show(struct seq_file *s, void *what)
549 selector++; 547 selector++;
550 } 548 }
551 549
552 mutex_unlock(&pinctrl_mutex);
553
554 return 0; 550 return 0;
555} 551}
556 552
diff --git a/drivers/pinctrl/pinctrl-bcm2835.c b/drivers/pinctrl/pinctrl-bcm2835.c
index a4adee633fa..7e9be18ec2d 100644
--- a/drivers/pinctrl/pinctrl-bcm2835.c
+++ b/drivers/pinctrl/pinctrl-bcm2835.c
@@ -29,7 +29,6 @@
29#include <linux/irq.h> 29#include <linux/irq.h>
30#include <linux/irqdesc.h> 30#include <linux/irqdesc.h>
31#include <linux/irqdomain.h> 31#include <linux/irqdomain.h>
32#include <linux/irq.h>
33#include <linux/module.h> 32#include <linux/module.h>
34#include <linux/of_address.h> 33#include <linux/of_address.h>
35#include <linux/of.h> 34#include <linux/of.h>
@@ -960,7 +959,7 @@ static int __devinit bcm2835_pinctrl_probe(struct platform_device *pdev)
960 return err; 959 return err;
961 } 960 }
962 961
963 pc->base = devm_request_and_ioremap(&pdev->dev, &iomem); 962 pc->base = devm_request_and_ioremap(dev, &iomem);
964 if (!pc->base) 963 if (!pc->base)
965 return -EADDRNOTAVAIL; 964 return -EADDRNOTAVAIL;
966 965
@@ -1032,7 +1031,7 @@ static int __devinit bcm2835_pinctrl_probe(struct platform_device *pdev)
1032 pc->pctl_dev = pinctrl_register(&bcm2835_pinctrl_desc, dev, pc); 1031 pc->pctl_dev = pinctrl_register(&bcm2835_pinctrl_desc, dev, pc);
1033 if (!pc->pctl_dev) { 1032 if (!pc->pctl_dev) {
1034 gpiochip_remove(&pc->gpio_chip); 1033 gpiochip_remove(&pc->gpio_chip);
1035 return PTR_ERR(pc->pctl_dev); 1034 return -EINVAL;
1036 } 1035 }
1037 1036
1038 pc->gpio_range = bcm2835_pinctrl_gpio_range; 1037 pc->gpio_range = bcm2835_pinctrl_gpio_range;
diff --git a/drivers/pinctrl/pinctrl-nomadik.c b/drivers/pinctrl/pinctrl-nomadik.c
index fec9c30133d..cf82d9ce4de 100644
--- a/drivers/pinctrl/pinctrl-nomadik.c
+++ b/drivers/pinctrl/pinctrl-nomadik.c
@@ -30,7 +30,20 @@
30#include <linux/pinctrl/pinconf.h> 30#include <linux/pinctrl/pinconf.h>
31/* Since we request GPIOs from ourself */ 31/* Since we request GPIOs from ourself */
32#include <linux/pinctrl/consumer.h> 32#include <linux/pinctrl/consumer.h>
33/*
34 * For the U8500 archs, use the PRCMU register interface, for the older
35 * Nomadik, provide some stubs. The functions using these will only be
36 * called on the U8500 series.
37 */
38#ifdef CONFIG_ARCH_U8500
33#include <linux/mfd/dbx500-prcmu.h> 39#include <linux/mfd/dbx500-prcmu.h>
40#else
41static inline u32 prcmu_read(unsigned int reg) {
42 return 0;
43}
44static inline void prcmu_write(unsigned int reg, u32 value) {}
45static inline void prcmu_write_masked(unsigned int reg, u32 mask, u32 value) {}
46#endif
34 47
35#include <asm/mach/irq.h> 48#include <asm/mach/irq.h>
36 49
@@ -1043,7 +1056,7 @@ static int nmk_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
1043 struct nmk_gpio_chip *nmk_chip = 1056 struct nmk_gpio_chip *nmk_chip =
1044 container_of(chip, struct nmk_gpio_chip, chip); 1057 container_of(chip, struct nmk_gpio_chip, chip);
1045 1058
1046 return irq_find_mapping(nmk_chip->domain, offset); 1059 return irq_create_mapping(nmk_chip->domain, offset);
1047} 1060}
1048 1061
1049#ifdef CONFIG_DEBUG_FS 1062#ifdef CONFIG_DEBUG_FS
@@ -1268,6 +1281,7 @@ static int __devinit nmk_gpio_probe(struct platform_device *dev)
1268 struct clk *clk; 1281 struct clk *clk;
1269 int secondary_irq; 1282 int secondary_irq;
1270 void __iomem *base; 1283 void __iomem *base;
1284 int irq_start = 0;
1271 int irq; 1285 int irq;
1272 int ret; 1286 int ret;
1273 1287
@@ -1371,19 +1385,11 @@ static int __devinit nmk_gpio_probe(struct platform_device *dev)
1371 1385
1372 platform_set_drvdata(dev, nmk_chip); 1386 platform_set_drvdata(dev, nmk_chip);
1373 1387
1374 if (np) { 1388 if (!np)
1375 /* The DT case will just grab a set of IRQ numbers */
1376 nmk_chip->domain = irq_domain_add_linear(np, NMK_GPIO_PER_CHIP,
1377 &nmk_gpio_irq_simple_ops, nmk_chip);
1378 } else {
1379 /* Non-DT legacy mode, use hardwired IRQ numbers */
1380 int irq_start;
1381
1382 irq_start = NOMADIK_GPIO_TO_IRQ(pdata->first_gpio); 1389 irq_start = NOMADIK_GPIO_TO_IRQ(pdata->first_gpio);
1383 nmk_chip->domain = irq_domain_add_simple(NULL, 1390 nmk_chip->domain = irq_domain_add_simple(np,
1384 NMK_GPIO_PER_CHIP, irq_start, 1391 NMK_GPIO_PER_CHIP, irq_start,
1385 &nmk_gpio_irq_simple_ops, nmk_chip); 1392 &nmk_gpio_irq_simple_ops, nmk_chip);
1386 }
1387 if (!nmk_chip->domain) { 1393 if (!nmk_chip->domain) {
1388 dev_err(&dev->dev, "failed to create irqdomain\n"); 1394 dev_err(&dev->dev, "failed to create irqdomain\n");
1389 ret = -ENOSYS; 1395 ret = -ENOSYS;
diff --git a/drivers/pinctrl/pinctrl-samsung.c b/drivers/pinctrl/pinctrl-samsung.c
index dd108a94acf..861cd5f04d5 100644
--- a/drivers/pinctrl/pinctrl-samsung.c
+++ b/drivers/pinctrl/pinctrl-samsung.c
@@ -513,7 +513,7 @@ static int samsung_gpio_direction_output(struct gpio_chip *gc, unsigned offset,
513 * Parse the pin names listed in the 'samsung,pins' property and convert it 513 * Parse the pin names listed in the 'samsung,pins' property and convert it
514 * into a list of gpio numbers are create a pin group from it. 514 * into a list of gpio numbers are create a pin group from it.
515 */ 515 */
516static int __init samsung_pinctrl_parse_dt_pins(struct platform_device *pdev, 516static int __devinit samsung_pinctrl_parse_dt_pins(struct platform_device *pdev,
517 struct device_node *cfg_np, struct pinctrl_desc *pctl, 517 struct device_node *cfg_np, struct pinctrl_desc *pctl,
518 unsigned int **pin_list, unsigned int *npins) 518 unsigned int **pin_list, unsigned int *npins)
519{ 519{
@@ -560,7 +560,7 @@ static int __init samsung_pinctrl_parse_dt_pins(struct platform_device *pdev,
560 * from device node of the pin-controller. A pin group is formed with all 560 * from device node of the pin-controller. A pin group is formed with all
561 * the pins listed in the "samsung,pins" property. 561 * the pins listed in the "samsung,pins" property.
562 */ 562 */
563static int __init samsung_pinctrl_parse_dt(struct platform_device *pdev, 563static int __devinit samsung_pinctrl_parse_dt(struct platform_device *pdev,
564 struct samsung_pinctrl_drv_data *drvdata) 564 struct samsung_pinctrl_drv_data *drvdata)
565{ 565{
566 struct device *dev = &pdev->dev; 566 struct device *dev = &pdev->dev;
@@ -655,7 +655,7 @@ static int __init samsung_pinctrl_parse_dt(struct platform_device *pdev,
655} 655}
656 656
657/* register the pinctrl interface with the pinctrl subsystem */ 657/* register the pinctrl interface with the pinctrl subsystem */
658static int __init samsung_pinctrl_register(struct platform_device *pdev, 658static int __devinit samsung_pinctrl_register(struct platform_device *pdev,
659 struct samsung_pinctrl_drv_data *drvdata) 659 struct samsung_pinctrl_drv_data *drvdata)
660{ 660{
661 struct pinctrl_desc *ctrldesc = &drvdata->pctl; 661 struct pinctrl_desc *ctrldesc = &drvdata->pctl;
@@ -729,7 +729,7 @@ static int __init samsung_pinctrl_register(struct platform_device *pdev,
729} 729}
730 730
731/* register the gpiolib interface with the gpiolib subsystem */ 731/* register the gpiolib interface with the gpiolib subsystem */
732static int __init samsung_gpiolib_register(struct platform_device *pdev, 732static int __devinit samsung_gpiolib_register(struct platform_device *pdev,
733 struct samsung_pinctrl_drv_data *drvdata) 733 struct samsung_pinctrl_drv_data *drvdata)
734{ 734{
735 struct gpio_chip *gc; 735 struct gpio_chip *gc;
@@ -762,7 +762,7 @@ static int __init samsung_gpiolib_register(struct platform_device *pdev,
762} 762}
763 763
764/* unregister the gpiolib interface with the gpiolib subsystem */ 764/* unregister the gpiolib interface with the gpiolib subsystem */
765static int __init samsung_gpiolib_unregister(struct platform_device *pdev, 765static int __devinit samsung_gpiolib_unregister(struct platform_device *pdev,
766 struct samsung_pinctrl_drv_data *drvdata) 766 struct samsung_pinctrl_drv_data *drvdata)
767{ 767{
768 int ret = gpiochip_remove(drvdata->gc); 768 int ret = gpiochip_remove(drvdata->gc);
diff --git a/drivers/pinctrl/pinctrl-sirf.c b/drivers/pinctrl/pinctrl-sirf.c
index 675497c1514..9ecacf3d0a7 100644
--- a/drivers/pinctrl/pinctrl-sirf.c
+++ b/drivers/pinctrl/pinctrl-sirf.c
@@ -1323,41 +1323,6 @@ static inline struct sirfsoc_gpio_bank *sirfsoc_gpio_to_bank(unsigned int gpio)
1323 return &sgpio_bank[gpio / SIRFSOC_GPIO_BANK_SIZE]; 1323 return &sgpio_bank[gpio / SIRFSOC_GPIO_BANK_SIZE];
1324} 1324}
1325 1325
1326void sirfsoc_gpio_set_pull(unsigned gpio, unsigned mode)
1327{
1328 struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(gpio);
1329 int idx = sirfsoc_gpio_to_offset(gpio);
1330 u32 val, offset;
1331 unsigned long flags;
1332
1333 offset = SIRFSOC_GPIO_CTRL(bank->id, idx);
1334
1335 spin_lock_irqsave(&sgpio_lock, flags);
1336
1337 val = readl(bank->chip.regs + offset);
1338
1339 switch (mode) {
1340 case SIRFSOC_GPIO_PULL_NONE:
1341 val &= ~SIRFSOC_GPIO_CTL_PULL_MASK;
1342 break;
1343 case SIRFSOC_GPIO_PULL_UP:
1344 val |= SIRFSOC_GPIO_CTL_PULL_MASK;
1345 val |= SIRFSOC_GPIO_CTL_PULL_HIGH;
1346 break;
1347 case SIRFSOC_GPIO_PULL_DOWN:
1348 val |= SIRFSOC_GPIO_CTL_PULL_MASK;
1349 val &= ~SIRFSOC_GPIO_CTL_PULL_HIGH;
1350 break;
1351 default:
1352 break;
1353 }
1354
1355 writel(val, bank->chip.regs + offset);
1356
1357 spin_unlock_irqrestore(&sgpio_lock, flags);
1358}
1359EXPORT_SYMBOL(sirfsoc_gpio_set_pull);
1360
1361static inline struct sirfsoc_gpio_bank *sirfsoc_irqchip_to_bank(struct gpio_chip *chip) 1326static inline struct sirfsoc_gpio_bank *sirfsoc_irqchip_to_bank(struct gpio_chip *chip)
1362{ 1327{
1363 return container_of(to_of_mm_gpio_chip(chip), struct sirfsoc_gpio_bank, chip); 1328 return container_of(to_of_mm_gpio_chip(chip), struct sirfsoc_gpio_bank, chip);
diff --git a/drivers/pinctrl/pinctrl-tegra.c b/drivers/pinctrl/pinctrl-tegra.c
index 729b686c3ad..7da0b371fd6 100644
--- a/drivers/pinctrl/pinctrl-tegra.c
+++ b/drivers/pinctrl/pinctrl-tegra.c
@@ -464,7 +464,7 @@ static int tegra_pinconf_reg(struct tegra_pmx *pmx,
464 *bank = g->drv_bank; 464 *bank = g->drv_bank;
465 *reg = g->drv_reg; 465 *reg = g->drv_reg;
466 *bit = g->lpmd_bit; 466 *bit = g->lpmd_bit;
467 *width = 1; 467 *width = 2;
468 break; 468 break;
469 case TEGRA_PINCONF_PARAM_DRIVE_DOWN_STRENGTH: 469 case TEGRA_PINCONF_PARAM_DRIVE_DOWN_STRENGTH:
470 *bank = g->drv_bank; 470 *bank = g->drv_bank;
diff --git a/drivers/pinctrl/pinctrl-tegra30.c b/drivers/pinctrl/pinctrl-tegra30.c
index 0386fdf0da1..7894f14c705 100644
--- a/drivers/pinctrl/pinctrl-tegra30.c
+++ b/drivers/pinctrl/pinctrl-tegra30.c
@@ -3345,10 +3345,10 @@ static const struct tegra_function tegra30_functions[] = {
3345 FUNCTION(vi_alt3), 3345 FUNCTION(vi_alt3),
3346}; 3346};
3347 3347
3348#define MUXCTL_REG_A 0x3000 3348#define DRV_PINGROUP_REG_A 0x868 /* bank 0 */
3349#define PINGROUP_REG_A 0x868 3349#define PINGROUP_REG_A 0x3000 /* bank 1 */
3350 3350
3351#define PINGROUP_REG_Y(r) ((r) - MUXCTL_REG_A) 3351#define PINGROUP_REG_Y(r) ((r) - PINGROUP_REG_A)
3352#define PINGROUP_REG_N(r) -1 3352#define PINGROUP_REG_N(r) -1
3353 3353
3354#define PINGROUP(pg_name, f0, f1, f2, f3, f_safe, r, od, ior) \ 3354#define PINGROUP(pg_name, f0, f1, f2, f3, f_safe, r, od, ior) \
@@ -3364,25 +3364,25 @@ static const struct tegra_function tegra30_functions[] = {
3364 }, \ 3364 }, \
3365 .func_safe = TEGRA_MUX_ ## f_safe, \ 3365 .func_safe = TEGRA_MUX_ ## f_safe, \
3366 .mux_reg = PINGROUP_REG_Y(r), \ 3366 .mux_reg = PINGROUP_REG_Y(r), \
3367 .mux_bank = 0, \ 3367 .mux_bank = 1, \
3368 .mux_bit = 0, \ 3368 .mux_bit = 0, \
3369 .pupd_reg = PINGROUP_REG_Y(r), \ 3369 .pupd_reg = PINGROUP_REG_Y(r), \
3370 .pupd_bank = 0, \ 3370 .pupd_bank = 1, \
3371 .pupd_bit = 2, \ 3371 .pupd_bit = 2, \
3372 .tri_reg = PINGROUP_REG_Y(r), \ 3372 .tri_reg = PINGROUP_REG_Y(r), \
3373 .tri_bank = 0, \ 3373 .tri_bank = 1, \
3374 .tri_bit = 4, \ 3374 .tri_bit = 4, \
3375 .einput_reg = PINGROUP_REG_Y(r), \ 3375 .einput_reg = PINGROUP_REG_Y(r), \
3376 .einput_bank = 0, \ 3376 .einput_bank = 1, \
3377 .einput_bit = 5, \ 3377 .einput_bit = 5, \
3378 .odrain_reg = PINGROUP_REG_##od(r), \ 3378 .odrain_reg = PINGROUP_REG_##od(r), \
3379 .odrain_bank = 0, \ 3379 .odrain_bank = 1, \
3380 .odrain_bit = 6, \ 3380 .odrain_bit = 6, \
3381 .lock_reg = PINGROUP_REG_Y(r), \ 3381 .lock_reg = PINGROUP_REG_Y(r), \
3382 .lock_bank = 0, \ 3382 .lock_bank = 1, \
3383 .lock_bit = 7, \ 3383 .lock_bit = 7, \
3384 .ioreset_reg = PINGROUP_REG_##ior(r), \ 3384 .ioreset_reg = PINGROUP_REG_##ior(r), \
3385 .ioreset_bank = 0, \ 3385 .ioreset_bank = 1, \
3386 .ioreset_bit = 8, \ 3386 .ioreset_bit = 8, \
3387 .drv_reg = -1, \ 3387 .drv_reg = -1, \
3388 } 3388 }
@@ -3401,8 +3401,8 @@ static const struct tegra_function tegra30_functions[] = {
3401 .odrain_reg = -1, \ 3401 .odrain_reg = -1, \
3402 .lock_reg = -1, \ 3402 .lock_reg = -1, \
3403 .ioreset_reg = -1, \ 3403 .ioreset_reg = -1, \
3404 .drv_reg = ((r) - PINGROUP_REG_A), \ 3404 .drv_reg = ((r) - DRV_PINGROUP_REG_A), \
3405 .drv_bank = 1, \ 3405 .drv_bank = 0, \
3406 .hsm_bit = hsm_b, \ 3406 .hsm_bit = hsm_b, \
3407 .schmitt_bit = schmitt_b, \ 3407 .schmitt_bit = schmitt_b, \
3408 .lpmd_bit = lpmd_b, \ 3408 .lpmd_bit = lpmd_b, \
diff --git a/drivers/pinctrl/pinctrl-xway.c b/drivers/pinctrl/pinctrl-xway.c
index f8d917d40c9..b9bcaec6622 100644
--- a/drivers/pinctrl/pinctrl-xway.c
+++ b/drivers/pinctrl/pinctrl-xway.c
@@ -17,8 +17,6 @@
17#include <linux/ioport.h> 17#include <linux/ioport.h>
18#include <linux/io.h> 18#include <linux/io.h>
19#include <linux/device.h> 19#include <linux/device.h>
20#include <linux/module.h>
21#include <linux/io.h>
22#include <linux/platform_device.h> 20#include <linux/platform_device.h>
23 21
24#include "pinctrl-lantiq.h" 22#include "pinctrl-lantiq.h"
diff --git a/drivers/pinctrl/spear/pinctrl-spear.c b/drivers/pinctrl/spear/pinctrl-spear.c
index 5d4f44f462f..b1fd6ee33c6 100644
--- a/drivers/pinctrl/spear/pinctrl-spear.c
+++ b/drivers/pinctrl/spear/pinctrl-spear.c
@@ -244,7 +244,7 @@ static int spear_pinctrl_endisable(struct pinctrl_dev *pctldev,
244 else 244 else
245 temp = ~muxreg->val; 245 temp = ~muxreg->val;
246 246
247 val |= temp; 247 val |= muxreg->mask & temp;
248 pmx_writel(pmx, val, muxreg->reg); 248 pmx_writel(pmx, val, muxreg->reg);
249 } 249 }
250 } 250 }
diff --git a/drivers/pinctrl/spear/pinctrl-spear1310.c b/drivers/pinctrl/spear/pinctrl-spear1310.c
index d6cca8c81b9..0436fc7895d 100644
--- a/drivers/pinctrl/spear/pinctrl-spear1310.c
+++ b/drivers/pinctrl/spear/pinctrl-spear1310.c
@@ -25,8 +25,8 @@ static const struct pinctrl_pin_desc spear1310_pins[] = {
25}; 25};
26 26
27/* registers */ 27/* registers */
28#define PERIP_CFG 0x32C 28#define PERIP_CFG 0x3B0
29 #define MCIF_SEL_SHIFT 3 29 #define MCIF_SEL_SHIFT 5
30 #define MCIF_SEL_SD (0x1 << MCIF_SEL_SHIFT) 30 #define MCIF_SEL_SD (0x1 << MCIF_SEL_SHIFT)
31 #define MCIF_SEL_CF (0x2 << MCIF_SEL_SHIFT) 31 #define MCIF_SEL_CF (0x2 << MCIF_SEL_SHIFT)
32 #define MCIF_SEL_XD (0x3 << MCIF_SEL_SHIFT) 32 #define MCIF_SEL_XD (0x3 << MCIF_SEL_SHIFT)
@@ -164,6 +164,10 @@ static const struct pinctrl_pin_desc spear1310_pins[] = {
164 #define PMX_SSP0_CS0_MASK (1 << 29) 164 #define PMX_SSP0_CS0_MASK (1 << 29)
165 #define PMX_SSP0_CS1_2_MASK (1 << 30) 165 #define PMX_SSP0_CS1_2_MASK (1 << 30)
166 166
167#define PAD_DIRECTION_SEL_0 0x65C
168#define PAD_DIRECTION_SEL_1 0x660
169#define PAD_DIRECTION_SEL_2 0x664
170
167/* combined macros */ 171/* combined macros */
168#define PMX_GMII_MASK (PMX_GMIICLK_MASK | \ 172#define PMX_GMII_MASK (PMX_GMIICLK_MASK | \
169 PMX_GMIICOL_CRS_XFERER_MIITXCLK_MASK | \ 173 PMX_GMIICOL_CRS_XFERER_MIITXCLK_MASK | \
@@ -237,6 +241,10 @@ static struct spear_muxreg i2c0_muxreg[] = {
237 .reg = PAD_FUNCTION_EN_0, 241 .reg = PAD_FUNCTION_EN_0,
238 .mask = PMX_I2C0_MASK, 242 .mask = PMX_I2C0_MASK,
239 .val = PMX_I2C0_MASK, 243 .val = PMX_I2C0_MASK,
244 }, {
245 .reg = PAD_DIRECTION_SEL_0,
246 .mask = PMX_I2C0_MASK,
247 .val = PMX_I2C0_MASK,
240 }, 248 },
241}; 249};
242 250
@@ -269,6 +277,10 @@ static struct spear_muxreg ssp0_muxreg[] = {
269 .reg = PAD_FUNCTION_EN_0, 277 .reg = PAD_FUNCTION_EN_0,
270 .mask = PMX_SSP0_MASK, 278 .mask = PMX_SSP0_MASK,
271 .val = PMX_SSP0_MASK, 279 .val = PMX_SSP0_MASK,
280 }, {
281 .reg = PAD_DIRECTION_SEL_0,
282 .mask = PMX_SSP0_MASK,
283 .val = PMX_SSP0_MASK,
272 }, 284 },
273}; 285};
274 286
@@ -294,6 +306,10 @@ static struct spear_muxreg ssp0_cs0_muxreg[] = {
294 .reg = PAD_FUNCTION_EN_2, 306 .reg = PAD_FUNCTION_EN_2,
295 .mask = PMX_SSP0_CS0_MASK, 307 .mask = PMX_SSP0_CS0_MASK,
296 .val = PMX_SSP0_CS0_MASK, 308 .val = PMX_SSP0_CS0_MASK,
309 }, {
310 .reg = PAD_DIRECTION_SEL_2,
311 .mask = PMX_SSP0_CS0_MASK,
312 .val = PMX_SSP0_CS0_MASK,
297 }, 313 },
298}; 314};
299 315
@@ -319,6 +335,10 @@ static struct spear_muxreg ssp0_cs1_2_muxreg[] = {
319 .reg = PAD_FUNCTION_EN_2, 335 .reg = PAD_FUNCTION_EN_2,
320 .mask = PMX_SSP0_CS1_2_MASK, 336 .mask = PMX_SSP0_CS1_2_MASK,
321 .val = PMX_SSP0_CS1_2_MASK, 337 .val = PMX_SSP0_CS1_2_MASK,
338 }, {
339 .reg = PAD_DIRECTION_SEL_2,
340 .mask = PMX_SSP0_CS1_2_MASK,
341 .val = PMX_SSP0_CS1_2_MASK,
322 }, 342 },
323}; 343};
324 344
@@ -352,6 +372,10 @@ static struct spear_muxreg i2s0_muxreg[] = {
352 .reg = PAD_FUNCTION_EN_0, 372 .reg = PAD_FUNCTION_EN_0,
353 .mask = PMX_I2S0_MASK, 373 .mask = PMX_I2S0_MASK,
354 .val = PMX_I2S0_MASK, 374 .val = PMX_I2S0_MASK,
375 }, {
376 .reg = PAD_DIRECTION_SEL_0,
377 .mask = PMX_I2S0_MASK,
378 .val = PMX_I2S0_MASK,
355 }, 379 },
356}; 380};
357 381
@@ -384,6 +408,10 @@ static struct spear_muxreg i2s1_muxreg[] = {
384 .reg = PAD_FUNCTION_EN_1, 408 .reg = PAD_FUNCTION_EN_1,
385 .mask = PMX_I2S1_MASK, 409 .mask = PMX_I2S1_MASK,
386 .val = PMX_I2S1_MASK, 410 .val = PMX_I2S1_MASK,
411 }, {
412 .reg = PAD_DIRECTION_SEL_1,
413 .mask = PMX_I2S1_MASK,
414 .val = PMX_I2S1_MASK,
387 }, 415 },
388}; 416};
389 417
@@ -418,6 +446,10 @@ static struct spear_muxreg clcd_muxreg[] = {
418 .reg = PAD_FUNCTION_EN_0, 446 .reg = PAD_FUNCTION_EN_0,
419 .mask = PMX_CLCD1_MASK, 447 .mask = PMX_CLCD1_MASK,
420 .val = PMX_CLCD1_MASK, 448 .val = PMX_CLCD1_MASK,
449 }, {
450 .reg = PAD_DIRECTION_SEL_0,
451 .mask = PMX_CLCD1_MASK,
452 .val = PMX_CLCD1_MASK,
421 }, 453 },
422}; 454};
423 455
@@ -443,6 +475,10 @@ static struct spear_muxreg clcd_high_res_muxreg[] = {
443 .reg = PAD_FUNCTION_EN_1, 475 .reg = PAD_FUNCTION_EN_1,
444 .mask = PMX_CLCD2_MASK, 476 .mask = PMX_CLCD2_MASK,
445 .val = PMX_CLCD2_MASK, 477 .val = PMX_CLCD2_MASK,
478 }, {
479 .reg = PAD_DIRECTION_SEL_1,
480 .mask = PMX_CLCD2_MASK,
481 .val = PMX_CLCD2_MASK,
446 }, 482 },
447}; 483};
448 484
@@ -461,7 +497,7 @@ static struct spear_pingroup clcd_high_res_pingroup = {
461 .nmodemuxs = ARRAY_SIZE(clcd_high_res_modemux), 497 .nmodemuxs = ARRAY_SIZE(clcd_high_res_modemux),
462}; 498};
463 499
464static const char *const clcd_grps[] = { "clcd_grp", "clcd_high_res" }; 500static const char *const clcd_grps[] = { "clcd_grp", "clcd_high_res_grp" };
465static struct spear_function clcd_function = { 501static struct spear_function clcd_function = {
466 .name = "clcd", 502 .name = "clcd",
467 .groups = clcd_grps, 503 .groups = clcd_grps,
@@ -479,6 +515,14 @@ static struct spear_muxreg arm_gpio_muxreg[] = {
479 .reg = PAD_FUNCTION_EN_1, 515 .reg = PAD_FUNCTION_EN_1,
480 .mask = PMX_EGPIO_1_GRP_MASK, 516 .mask = PMX_EGPIO_1_GRP_MASK,
481 .val = PMX_EGPIO_1_GRP_MASK, 517 .val = PMX_EGPIO_1_GRP_MASK,
518 }, {
519 .reg = PAD_DIRECTION_SEL_0,
520 .mask = PMX_EGPIO_0_GRP_MASK,
521 .val = PMX_EGPIO_0_GRP_MASK,
522 }, {
523 .reg = PAD_DIRECTION_SEL_1,
524 .mask = PMX_EGPIO_1_GRP_MASK,
525 .val = PMX_EGPIO_1_GRP_MASK,
482 }, 526 },
483}; 527};
484 528
@@ -511,6 +555,10 @@ static struct spear_muxreg smi_2_chips_muxreg[] = {
511 .reg = PAD_FUNCTION_EN_0, 555 .reg = PAD_FUNCTION_EN_0,
512 .mask = PMX_SMI_MASK, 556 .mask = PMX_SMI_MASK,
513 .val = PMX_SMI_MASK, 557 .val = PMX_SMI_MASK,
558 }, {
559 .reg = PAD_DIRECTION_SEL_0,
560 .mask = PMX_SMI_MASK,
561 .val = PMX_SMI_MASK,
514 }, 562 },
515}; 563};
516 564
@@ -539,6 +587,14 @@ static struct spear_muxreg smi_4_chips_muxreg[] = {
539 .reg = PAD_FUNCTION_EN_1, 587 .reg = PAD_FUNCTION_EN_1,
540 .mask = PMX_SMINCS2_MASK | PMX_SMINCS3_MASK, 588 .mask = PMX_SMINCS2_MASK | PMX_SMINCS3_MASK,
541 .val = PMX_SMINCS2_MASK | PMX_SMINCS3_MASK, 589 .val = PMX_SMINCS2_MASK | PMX_SMINCS3_MASK,
590 }, {
591 .reg = PAD_DIRECTION_SEL_0,
592 .mask = PMX_SMI_MASK,
593 .val = PMX_SMI_MASK,
594 }, {
595 .reg = PAD_DIRECTION_SEL_1,
596 .mask = PMX_SMINCS2_MASK | PMX_SMINCS3_MASK,
597 .val = PMX_SMINCS2_MASK | PMX_SMINCS3_MASK,
542 }, 598 },
543}; 599};
544 600
@@ -573,6 +629,10 @@ static struct spear_muxreg gmii_muxreg[] = {
573 .reg = PAD_FUNCTION_EN_0, 629 .reg = PAD_FUNCTION_EN_0,
574 .mask = PMX_GMII_MASK, 630 .mask = PMX_GMII_MASK,
575 .val = PMX_GMII_MASK, 631 .val = PMX_GMII_MASK,
632 }, {
633 .reg = PAD_DIRECTION_SEL_0,
634 .mask = PMX_GMII_MASK,
635 .val = PMX_GMII_MASK,
576 }, 636 },
577}; 637};
578 638
@@ -615,6 +675,18 @@ static struct spear_muxreg rgmii_muxreg[] = {
615 .reg = PAD_FUNCTION_EN_2, 675 .reg = PAD_FUNCTION_EN_2,
616 .mask = PMX_RGMII_REG2_MASK, 676 .mask = PMX_RGMII_REG2_MASK,
617 .val = 0, 677 .val = 0,
678 }, {
679 .reg = PAD_DIRECTION_SEL_0,
680 .mask = PMX_RGMII_REG0_MASK,
681 .val = PMX_RGMII_REG0_MASK,
682 }, {
683 .reg = PAD_DIRECTION_SEL_1,
684 .mask = PMX_RGMII_REG1_MASK,
685 .val = PMX_RGMII_REG1_MASK,
686 }, {
687 .reg = PAD_DIRECTION_SEL_2,
688 .mask = PMX_RGMII_REG2_MASK,
689 .val = PMX_RGMII_REG2_MASK,
618 }, 690 },
619}; 691};
620 692
@@ -649,6 +721,10 @@ static struct spear_muxreg smii_0_1_2_muxreg[] = {
649 .reg = PAD_FUNCTION_EN_1, 721 .reg = PAD_FUNCTION_EN_1,
650 .mask = PMX_SMII_0_1_2_MASK, 722 .mask = PMX_SMII_0_1_2_MASK,
651 .val = 0, 723 .val = 0,
724 }, {
725 .reg = PAD_DIRECTION_SEL_1,
726 .mask = PMX_SMII_0_1_2_MASK,
727 .val = PMX_SMII_0_1_2_MASK,
652 }, 728 },
653}; 729};
654 730
@@ -681,6 +757,10 @@ static struct spear_muxreg ras_mii_txclk_muxreg[] = {
681 .reg = PAD_FUNCTION_EN_1, 757 .reg = PAD_FUNCTION_EN_1,
682 .mask = PMX_NFCE2_MASK, 758 .mask = PMX_NFCE2_MASK,
683 .val = 0, 759 .val = 0,
760 }, {
761 .reg = PAD_DIRECTION_SEL_1,
762 .mask = PMX_NFCE2_MASK,
763 .val = PMX_NFCE2_MASK,
684 }, 764 },
685}; 765};
686 766
@@ -721,6 +801,14 @@ static struct spear_muxreg nand_8bit_muxreg[] = {
721 .reg = PAD_FUNCTION_EN_1, 801 .reg = PAD_FUNCTION_EN_1,
722 .mask = PMX_NAND8BIT_1_MASK, 802 .mask = PMX_NAND8BIT_1_MASK,
723 .val = PMX_NAND8BIT_1_MASK, 803 .val = PMX_NAND8BIT_1_MASK,
804 }, {
805 .reg = PAD_DIRECTION_SEL_0,
806 .mask = PMX_NAND8BIT_0_MASK,
807 .val = PMX_NAND8BIT_0_MASK,
808 }, {
809 .reg = PAD_DIRECTION_SEL_1,
810 .mask = PMX_NAND8BIT_1_MASK,
811 .val = PMX_NAND8BIT_1_MASK,
724 }, 812 },
725}; 813};
726 814
@@ -747,6 +835,10 @@ static struct spear_muxreg nand_16bit_muxreg[] = {
747 .reg = PAD_FUNCTION_EN_1, 835 .reg = PAD_FUNCTION_EN_1,
748 .mask = PMX_NAND16BIT_1_MASK, 836 .mask = PMX_NAND16BIT_1_MASK,
749 .val = PMX_NAND16BIT_1_MASK, 837 .val = PMX_NAND16BIT_1_MASK,
838 }, {
839 .reg = PAD_DIRECTION_SEL_1,
840 .mask = PMX_NAND16BIT_1_MASK,
841 .val = PMX_NAND16BIT_1_MASK,
750 }, 842 },
751}; 843};
752 844
@@ -772,6 +864,10 @@ static struct spear_muxreg nand_4_chips_muxreg[] = {
772 .reg = PAD_FUNCTION_EN_1, 864 .reg = PAD_FUNCTION_EN_1,
773 .mask = PMX_NAND_4CHIPS_MASK, 865 .mask = PMX_NAND_4CHIPS_MASK,
774 .val = PMX_NAND_4CHIPS_MASK, 866 .val = PMX_NAND_4CHIPS_MASK,
867 }, {
868 .reg = PAD_DIRECTION_SEL_1,
869 .mask = PMX_NAND_4CHIPS_MASK,
870 .val = PMX_NAND_4CHIPS_MASK,
775 }, 871 },
776}; 872};
777 873
@@ -833,6 +929,10 @@ static struct spear_muxreg keyboard_rowcol6_8_muxreg[] = {
833 .reg = PAD_FUNCTION_EN_1, 929 .reg = PAD_FUNCTION_EN_1,
834 .mask = PMX_KBD_ROWCOL68_MASK, 930 .mask = PMX_KBD_ROWCOL68_MASK,
835 .val = PMX_KBD_ROWCOL68_MASK, 931 .val = PMX_KBD_ROWCOL68_MASK,
932 }, {
933 .reg = PAD_DIRECTION_SEL_1,
934 .mask = PMX_KBD_ROWCOL68_MASK,
935 .val = PMX_KBD_ROWCOL68_MASK,
836 }, 936 },
837}; 937};
838 938
@@ -866,6 +966,10 @@ static struct spear_muxreg uart0_muxreg[] = {
866 .reg = PAD_FUNCTION_EN_0, 966 .reg = PAD_FUNCTION_EN_0,
867 .mask = PMX_UART0_MASK, 967 .mask = PMX_UART0_MASK,
868 .val = PMX_UART0_MASK, 968 .val = PMX_UART0_MASK,
969 }, {
970 .reg = PAD_DIRECTION_SEL_0,
971 .mask = PMX_UART0_MASK,
972 .val = PMX_UART0_MASK,
869 }, 973 },
870}; 974};
871 975
@@ -891,6 +995,10 @@ static struct spear_muxreg uart0_modem_muxreg[] = {
891 .reg = PAD_FUNCTION_EN_1, 995 .reg = PAD_FUNCTION_EN_1,
892 .mask = PMX_UART0_MODEM_MASK, 996 .mask = PMX_UART0_MODEM_MASK,
893 .val = PMX_UART0_MODEM_MASK, 997 .val = PMX_UART0_MODEM_MASK,
998 }, {
999 .reg = PAD_DIRECTION_SEL_1,
1000 .mask = PMX_UART0_MODEM_MASK,
1001 .val = PMX_UART0_MODEM_MASK,
894 }, 1002 },
895}; 1003};
896 1004
@@ -923,6 +1031,10 @@ static struct spear_muxreg gpt0_tmr0_muxreg[] = {
923 .reg = PAD_FUNCTION_EN_1, 1031 .reg = PAD_FUNCTION_EN_1,
924 .mask = PMX_GPT0_TMR0_MASK, 1032 .mask = PMX_GPT0_TMR0_MASK,
925 .val = PMX_GPT0_TMR0_MASK, 1033 .val = PMX_GPT0_TMR0_MASK,
1034 }, {
1035 .reg = PAD_DIRECTION_SEL_1,
1036 .mask = PMX_GPT0_TMR0_MASK,
1037 .val = PMX_GPT0_TMR0_MASK,
926 }, 1038 },
927}; 1039};
928 1040
@@ -948,6 +1060,10 @@ static struct spear_muxreg gpt0_tmr1_muxreg[] = {
948 .reg = PAD_FUNCTION_EN_1, 1060 .reg = PAD_FUNCTION_EN_1,
949 .mask = PMX_GPT0_TMR1_MASK, 1061 .mask = PMX_GPT0_TMR1_MASK,
950 .val = PMX_GPT0_TMR1_MASK, 1062 .val = PMX_GPT0_TMR1_MASK,
1063 }, {
1064 .reg = PAD_DIRECTION_SEL_1,
1065 .mask = PMX_GPT0_TMR1_MASK,
1066 .val = PMX_GPT0_TMR1_MASK,
951 }, 1067 },
952}; 1068};
953 1069
@@ -980,6 +1096,10 @@ static struct spear_muxreg gpt1_tmr0_muxreg[] = {
980 .reg = PAD_FUNCTION_EN_1, 1096 .reg = PAD_FUNCTION_EN_1,
981 .mask = PMX_GPT1_TMR0_MASK, 1097 .mask = PMX_GPT1_TMR0_MASK,
982 .val = PMX_GPT1_TMR0_MASK, 1098 .val = PMX_GPT1_TMR0_MASK,
1099 }, {
1100 .reg = PAD_DIRECTION_SEL_1,
1101 .mask = PMX_GPT1_TMR0_MASK,
1102 .val = PMX_GPT1_TMR0_MASK,
983 }, 1103 },
984}; 1104};
985 1105
@@ -1005,6 +1125,10 @@ static struct spear_muxreg gpt1_tmr1_muxreg[] = {
1005 .reg = PAD_FUNCTION_EN_1, 1125 .reg = PAD_FUNCTION_EN_1,
1006 .mask = PMX_GPT1_TMR1_MASK, 1126 .mask = PMX_GPT1_TMR1_MASK,
1007 .val = PMX_GPT1_TMR1_MASK, 1127 .val = PMX_GPT1_TMR1_MASK,
1128 }, {
1129 .reg = PAD_DIRECTION_SEL_1,
1130 .mask = PMX_GPT1_TMR1_MASK,
1131 .val = PMX_GPT1_TMR1_MASK,
1008 }, 1132 },
1009}; 1133};
1010 1134
@@ -1049,6 +1173,20 @@ static const unsigned mcif_pins[] = { 86, 87, 88, 89, 90, 91, 92, 93, 213, 214,
1049 .reg = PAD_FUNCTION_EN_2, \ 1173 .reg = PAD_FUNCTION_EN_2, \
1050 .mask = PMX_MCIFALL_2_MASK, \ 1174 .mask = PMX_MCIFALL_2_MASK, \
1051 .val = PMX_MCIFALL_2_MASK, \ 1175 .val = PMX_MCIFALL_2_MASK, \
1176 }, { \
1177 .reg = PAD_DIRECTION_SEL_0, \
1178 .mask = PMX_MCI_DATA8_15_MASK, \
1179 .val = PMX_MCI_DATA8_15_MASK, \
1180 }, { \
1181 .reg = PAD_DIRECTION_SEL_1, \
1182 .mask = PMX_MCIFALL_1_MASK | PMX_NFWPRT1_MASK | \
1183 PMX_NFWPRT2_MASK, \
1184 .val = PMX_MCIFALL_1_MASK | PMX_NFWPRT1_MASK | \
1185 PMX_NFWPRT2_MASK, \
1186 }, { \
1187 .reg = PAD_DIRECTION_SEL_2, \
1188 .mask = PMX_MCIFALL_2_MASK, \
1189 .val = PMX_MCIFALL_2_MASK, \
1052 } 1190 }
1053 1191
1054/* sdhci device */ 1192/* sdhci device */
@@ -1154,6 +1292,10 @@ static struct spear_muxreg touch_xy_muxreg[] = {
1154 .reg = PAD_FUNCTION_EN_2, 1292 .reg = PAD_FUNCTION_EN_2,
1155 .mask = PMX_TOUCH_XY_MASK, 1293 .mask = PMX_TOUCH_XY_MASK,
1156 .val = PMX_TOUCH_XY_MASK, 1294 .val = PMX_TOUCH_XY_MASK,
1295 }, {
1296 .reg = PAD_DIRECTION_SEL_2,
1297 .mask = PMX_TOUCH_XY_MASK,
1298 .val = PMX_TOUCH_XY_MASK,
1157 }, 1299 },
1158}; 1300};
1159 1301
@@ -1187,6 +1329,10 @@ static struct spear_muxreg uart1_dis_i2c_muxreg[] = {
1187 .reg = PAD_FUNCTION_EN_0, 1329 .reg = PAD_FUNCTION_EN_0,
1188 .mask = PMX_I2C0_MASK, 1330 .mask = PMX_I2C0_MASK,
1189 .val = 0, 1331 .val = 0,
1332 }, {
1333 .reg = PAD_DIRECTION_SEL_0,
1334 .mask = PMX_I2C0_MASK,
1335 .val = PMX_I2C0_MASK,
1190 }, 1336 },
1191}; 1337};
1192 1338
@@ -1213,6 +1359,12 @@ static struct spear_muxreg uart1_dis_sd_muxreg[] = {
1213 .mask = PMX_MCIDATA1_MASK | 1359 .mask = PMX_MCIDATA1_MASK |
1214 PMX_MCIDATA2_MASK, 1360 PMX_MCIDATA2_MASK,
1215 .val = 0, 1361 .val = 0,
1362 }, {
1363 .reg = PAD_DIRECTION_SEL_1,
1364 .mask = PMX_MCIDATA1_MASK |
1365 PMX_MCIDATA2_MASK,
1366 .val = PMX_MCIDATA1_MASK |
1367 PMX_MCIDATA2_MASK,
1216 }, 1368 },
1217}; 1369};
1218 1370
@@ -1246,6 +1398,10 @@ static struct spear_muxreg uart2_3_muxreg[] = {
1246 .reg = PAD_FUNCTION_EN_0, 1398 .reg = PAD_FUNCTION_EN_0,
1247 .mask = PMX_I2S0_MASK, 1399 .mask = PMX_I2S0_MASK,
1248 .val = 0, 1400 .val = 0,
1401 }, {
1402 .reg = PAD_DIRECTION_SEL_0,
1403 .mask = PMX_I2S0_MASK,
1404 .val = PMX_I2S0_MASK,
1249 }, 1405 },
1250}; 1406};
1251 1407
@@ -1278,6 +1434,10 @@ static struct spear_muxreg uart4_muxreg[] = {
1278 .reg = PAD_FUNCTION_EN_0, 1434 .reg = PAD_FUNCTION_EN_0,
1279 .mask = PMX_I2S0_MASK | PMX_CLCD1_MASK, 1435 .mask = PMX_I2S0_MASK | PMX_CLCD1_MASK,
1280 .val = 0, 1436 .val = 0,
1437 }, {
1438 .reg = PAD_DIRECTION_SEL_0,
1439 .mask = PMX_I2S0_MASK | PMX_CLCD1_MASK,
1440 .val = PMX_I2S0_MASK | PMX_CLCD1_MASK,
1281 }, 1441 },
1282}; 1442};
1283 1443
@@ -1310,6 +1470,10 @@ static struct spear_muxreg uart5_muxreg[] = {
1310 .reg = PAD_FUNCTION_EN_0, 1470 .reg = PAD_FUNCTION_EN_0,
1311 .mask = PMX_CLCD1_MASK, 1471 .mask = PMX_CLCD1_MASK,
1312 .val = 0, 1472 .val = 0,
1473 }, {
1474 .reg = PAD_DIRECTION_SEL_0,
1475 .mask = PMX_CLCD1_MASK,
1476 .val = PMX_CLCD1_MASK,
1313 }, 1477 },
1314}; 1478};
1315 1479
@@ -1344,6 +1508,10 @@ static struct spear_muxreg rs485_0_1_tdm_0_1_muxreg[] = {
1344 .reg = PAD_FUNCTION_EN_0, 1508 .reg = PAD_FUNCTION_EN_0,
1345 .mask = PMX_CLCD1_MASK, 1509 .mask = PMX_CLCD1_MASK,
1346 .val = 0, 1510 .val = 0,
1511 }, {
1512 .reg = PAD_DIRECTION_SEL_0,
1513 .mask = PMX_CLCD1_MASK,
1514 .val = PMX_CLCD1_MASK,
1347 }, 1515 },
1348}; 1516};
1349 1517
@@ -1376,6 +1544,10 @@ static struct spear_muxreg i2c_1_2_muxreg[] = {
1376 .reg = PAD_FUNCTION_EN_0, 1544 .reg = PAD_FUNCTION_EN_0,
1377 .mask = PMX_CLCD1_MASK, 1545 .mask = PMX_CLCD1_MASK,
1378 .val = 0, 1546 .val = 0,
1547 }, {
1548 .reg = PAD_DIRECTION_SEL_0,
1549 .mask = PMX_CLCD1_MASK,
1550 .val = PMX_CLCD1_MASK,
1379 }, 1551 },
1380}; 1552};
1381 1553
@@ -1409,6 +1581,10 @@ static struct spear_muxreg i2c3_dis_smi_clcd_muxreg[] = {
1409 .reg = PAD_FUNCTION_EN_0, 1581 .reg = PAD_FUNCTION_EN_0,
1410 .mask = PMX_CLCD1_MASK | PMX_SMI_MASK, 1582 .mask = PMX_CLCD1_MASK | PMX_SMI_MASK,
1411 .val = 0, 1583 .val = 0,
1584 }, {
1585 .reg = PAD_DIRECTION_SEL_0,
1586 .mask = PMX_CLCD1_MASK | PMX_SMI_MASK,
1587 .val = PMX_CLCD1_MASK | PMX_SMI_MASK,
1412 }, 1588 },
1413}; 1589};
1414 1590
@@ -1435,6 +1611,10 @@ static struct spear_muxreg i2c3_dis_sd_i2s0_muxreg[] = {
1435 .reg = PAD_FUNCTION_EN_1, 1611 .reg = PAD_FUNCTION_EN_1,
1436 .mask = PMX_I2S1_MASK | PMX_MCIDATA3_MASK, 1612 .mask = PMX_I2S1_MASK | PMX_MCIDATA3_MASK,
1437 .val = 0, 1613 .val = 0,
1614 }, {
1615 .reg = PAD_DIRECTION_SEL_1,
1616 .mask = PMX_I2S1_MASK | PMX_MCIDATA3_MASK,
1617 .val = PMX_I2S1_MASK | PMX_MCIDATA3_MASK,
1438 }, 1618 },
1439}; 1619};
1440 1620
@@ -1469,6 +1649,10 @@ static struct spear_muxreg i2c_4_5_dis_smi_muxreg[] = {
1469 .reg = PAD_FUNCTION_EN_0, 1649 .reg = PAD_FUNCTION_EN_0,
1470 .mask = PMX_SMI_MASK, 1650 .mask = PMX_SMI_MASK,
1471 .val = 0, 1651 .val = 0,
1652 }, {
1653 .reg = PAD_DIRECTION_SEL_0,
1654 .mask = PMX_SMI_MASK,
1655 .val = PMX_SMI_MASK,
1472 }, 1656 },
1473}; 1657};
1474 1658
@@ -1499,6 +1683,14 @@ static struct spear_muxreg i2c4_dis_sd_muxreg[] = {
1499 .reg = PAD_FUNCTION_EN_2, 1683 .reg = PAD_FUNCTION_EN_2,
1500 .mask = PMX_MCIDATA5_MASK, 1684 .mask = PMX_MCIDATA5_MASK,
1501 .val = 0, 1685 .val = 0,
1686 }, {
1687 .reg = PAD_DIRECTION_SEL_1,
1688 .mask = PMX_MCIDATA4_MASK,
1689 .val = PMX_MCIDATA4_MASK,
1690 }, {
1691 .reg = PAD_DIRECTION_SEL_2,
1692 .mask = PMX_MCIDATA5_MASK,
1693 .val = PMX_MCIDATA5_MASK,
1502 }, 1694 },
1503}; 1695};
1504 1696
@@ -1526,6 +1718,12 @@ static struct spear_muxreg i2c5_dis_sd_muxreg[] = {
1526 .mask = PMX_MCIDATA6_MASK | 1718 .mask = PMX_MCIDATA6_MASK |
1527 PMX_MCIDATA7_MASK, 1719 PMX_MCIDATA7_MASK,
1528 .val = 0, 1720 .val = 0,
1721 }, {
1722 .reg = PAD_DIRECTION_SEL_2,
1723 .mask = PMX_MCIDATA6_MASK |
1724 PMX_MCIDATA7_MASK,
1725 .val = PMX_MCIDATA6_MASK |
1726 PMX_MCIDATA7_MASK,
1529 }, 1727 },
1530}; 1728};
1531 1729
@@ -1560,6 +1758,10 @@ static struct spear_muxreg i2c_6_7_dis_kbd_muxreg[] = {
1560 .reg = PAD_FUNCTION_EN_1, 1758 .reg = PAD_FUNCTION_EN_1,
1561 .mask = PMX_KBD_ROWCOL25_MASK, 1759 .mask = PMX_KBD_ROWCOL25_MASK,
1562 .val = 0, 1760 .val = 0,
1761 }, {
1762 .reg = PAD_DIRECTION_SEL_1,
1763 .mask = PMX_KBD_ROWCOL25_MASK,
1764 .val = PMX_KBD_ROWCOL25_MASK,
1563 }, 1765 },
1564}; 1766};
1565 1767
@@ -1587,6 +1789,12 @@ static struct spear_muxreg i2c6_dis_sd_muxreg[] = {
1587 .mask = PMX_MCIIORDRE_MASK | 1789 .mask = PMX_MCIIORDRE_MASK |
1588 PMX_MCIIOWRWE_MASK, 1790 PMX_MCIIOWRWE_MASK,
1589 .val = 0, 1791 .val = 0,
1792 }, {
1793 .reg = PAD_DIRECTION_SEL_2,
1794 .mask = PMX_MCIIORDRE_MASK |
1795 PMX_MCIIOWRWE_MASK,
1796 .val = PMX_MCIIORDRE_MASK |
1797 PMX_MCIIOWRWE_MASK,
1590 }, 1798 },
1591}; 1799};
1592 1800
@@ -1613,6 +1821,12 @@ static struct spear_muxreg i2c7_dis_sd_muxreg[] = {
1613 .mask = PMX_MCIRESETCF_MASK | 1821 .mask = PMX_MCIRESETCF_MASK |
1614 PMX_MCICS0CE_MASK, 1822 PMX_MCICS0CE_MASK,
1615 .val = 0, 1823 .val = 0,
1824 }, {
1825 .reg = PAD_DIRECTION_SEL_2,
1826 .mask = PMX_MCIRESETCF_MASK |
1827 PMX_MCICS0CE_MASK,
1828 .val = PMX_MCIRESETCF_MASK |
1829 PMX_MCICS0CE_MASK,
1616 }, 1830 },
1617}; 1831};
1618 1832
@@ -1651,6 +1865,14 @@ static struct spear_muxreg can0_dis_nor_muxreg[] = {
1651 .reg = PAD_FUNCTION_EN_1, 1865 .reg = PAD_FUNCTION_EN_1,
1652 .mask = PMX_NFRSTPWDWN3_MASK, 1866 .mask = PMX_NFRSTPWDWN3_MASK,
1653 .val = 0, 1867 .val = 0,
1868 }, {
1869 .reg = PAD_DIRECTION_SEL_0,
1870 .mask = PMX_NFRSTPWDWN2_MASK,
1871 .val = PMX_NFRSTPWDWN2_MASK,
1872 }, {
1873 .reg = PAD_DIRECTION_SEL_1,
1874 .mask = PMX_NFRSTPWDWN3_MASK,
1875 .val = PMX_NFRSTPWDWN3_MASK,
1654 }, 1876 },
1655}; 1877};
1656 1878
@@ -1677,6 +1899,10 @@ static struct spear_muxreg can0_dis_sd_muxreg[] = {
1677 .reg = PAD_FUNCTION_EN_2, 1899 .reg = PAD_FUNCTION_EN_2,
1678 .mask = PMX_MCICFINTR_MASK | PMX_MCIIORDY_MASK, 1900 .mask = PMX_MCICFINTR_MASK | PMX_MCIIORDY_MASK,
1679 .val = 0, 1901 .val = 0,
1902 }, {
1903 .reg = PAD_DIRECTION_SEL_2,
1904 .mask = PMX_MCICFINTR_MASK | PMX_MCIIORDY_MASK,
1905 .val = PMX_MCICFINTR_MASK | PMX_MCIIORDY_MASK,
1680 }, 1906 },
1681}; 1907};
1682 1908
@@ -1711,6 +1937,10 @@ static struct spear_muxreg can1_dis_sd_muxreg[] = {
1711 .reg = PAD_FUNCTION_EN_2, 1937 .reg = PAD_FUNCTION_EN_2,
1712 .mask = PMX_MCICS1_MASK | PMX_MCIDMAACK_MASK, 1938 .mask = PMX_MCICS1_MASK | PMX_MCIDMAACK_MASK,
1713 .val = 0, 1939 .val = 0,
1940 }, {
1941 .reg = PAD_DIRECTION_SEL_2,
1942 .mask = PMX_MCICS1_MASK | PMX_MCIDMAACK_MASK,
1943 .val = PMX_MCICS1_MASK | PMX_MCIDMAACK_MASK,
1714 }, 1944 },
1715}; 1945};
1716 1946
@@ -1737,6 +1967,10 @@ static struct spear_muxreg can1_dis_kbd_muxreg[] = {
1737 .reg = PAD_FUNCTION_EN_1, 1967 .reg = PAD_FUNCTION_EN_1,
1738 .mask = PMX_KBD_ROWCOL25_MASK, 1968 .mask = PMX_KBD_ROWCOL25_MASK,
1739 .val = 0, 1969 .val = 0,
1970 }, {
1971 .reg = PAD_DIRECTION_SEL_1,
1972 .mask = PMX_KBD_ROWCOL25_MASK,
1973 .val = PMX_KBD_ROWCOL25_MASK,
1740 }, 1974 },
1741}; 1975};
1742 1976
@@ -1763,29 +1997,64 @@ static struct spear_function can1_function = {
1763 .ngroups = ARRAY_SIZE(can1_grps), 1997 .ngroups = ARRAY_SIZE(can1_grps),
1764}; 1998};
1765 1999
1766/* Pad multiplexing for pci device */ 2000/* Pad multiplexing for (ras-ip) pci device */
1767static const unsigned pci_sata_pins[] = { 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 18, 2001static const unsigned pci_pins[] = { 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 18,
1768 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 2002 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36,
1769 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 2003 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54,
1770 55, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99 }; 2004 55, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99 };
1771#define PCI_SATA_MUXREG \
1772 { \
1773 .reg = PAD_FUNCTION_EN_0, \
1774 .mask = PMX_MCI_DATA8_15_MASK, \
1775 .val = 0, \
1776 }, { \
1777 .reg = PAD_FUNCTION_EN_1, \
1778 .mask = PMX_PCI_REG1_MASK, \
1779 .val = 0, \
1780 }, { \
1781 .reg = PAD_FUNCTION_EN_2, \
1782 .mask = PMX_PCI_REG2_MASK, \
1783 .val = 0, \
1784 }
1785 2005
1786/* pad multiplexing for pcie0 device */ 2006static struct spear_muxreg pci_muxreg[] = {
2007 {
2008 .reg = PAD_FUNCTION_EN_0,
2009 .mask = PMX_MCI_DATA8_15_MASK,
2010 .val = 0,
2011 }, {
2012 .reg = PAD_FUNCTION_EN_1,
2013 .mask = PMX_PCI_REG1_MASK,
2014 .val = 0,
2015 }, {
2016 .reg = PAD_FUNCTION_EN_2,
2017 .mask = PMX_PCI_REG2_MASK,
2018 .val = 0,
2019 }, {
2020 .reg = PAD_DIRECTION_SEL_0,
2021 .mask = PMX_MCI_DATA8_15_MASK,
2022 .val = PMX_MCI_DATA8_15_MASK,
2023 }, {
2024 .reg = PAD_DIRECTION_SEL_1,
2025 .mask = PMX_PCI_REG1_MASK,
2026 .val = PMX_PCI_REG1_MASK,
2027 }, {
2028 .reg = PAD_DIRECTION_SEL_2,
2029 .mask = PMX_PCI_REG2_MASK,
2030 .val = PMX_PCI_REG2_MASK,
2031 },
2032};
2033
2034static struct spear_modemux pci_modemux[] = {
2035 {
2036 .muxregs = pci_muxreg,
2037 .nmuxregs = ARRAY_SIZE(pci_muxreg),
2038 },
2039};
2040
2041static struct spear_pingroup pci_pingroup = {
2042 .name = "pci_grp",
2043 .pins = pci_pins,
2044 .npins = ARRAY_SIZE(pci_pins),
2045 .modemuxs = pci_modemux,
2046 .nmodemuxs = ARRAY_SIZE(pci_modemux),
2047};
2048
2049static const char *const pci_grps[] = { "pci_grp" };
2050static struct spear_function pci_function = {
2051 .name = "pci",
2052 .groups = pci_grps,
2053 .ngroups = ARRAY_SIZE(pci_grps),
2054};
2055
2056/* pad multiplexing for (fix-part) pcie0 device */
1787static struct spear_muxreg pcie0_muxreg[] = { 2057static struct spear_muxreg pcie0_muxreg[] = {
1788 PCI_SATA_MUXREG,
1789 { 2058 {
1790 .reg = PCIE_SATA_CFG, 2059 .reg = PCIE_SATA_CFG,
1791 .mask = PCIE_CFG_VAL(0), 2060 .mask = PCIE_CFG_VAL(0),
@@ -1802,15 +2071,12 @@ static struct spear_modemux pcie0_modemux[] = {
1802 2071
1803static struct spear_pingroup pcie0_pingroup = { 2072static struct spear_pingroup pcie0_pingroup = {
1804 .name = "pcie0_grp", 2073 .name = "pcie0_grp",
1805 .pins = pci_sata_pins,
1806 .npins = ARRAY_SIZE(pci_sata_pins),
1807 .modemuxs = pcie0_modemux, 2074 .modemuxs = pcie0_modemux,
1808 .nmodemuxs = ARRAY_SIZE(pcie0_modemux), 2075 .nmodemuxs = ARRAY_SIZE(pcie0_modemux),
1809}; 2076};
1810 2077
1811/* pad multiplexing for pcie1 device */ 2078/* pad multiplexing for (fix-part) pcie1 device */
1812static struct spear_muxreg pcie1_muxreg[] = { 2079static struct spear_muxreg pcie1_muxreg[] = {
1813 PCI_SATA_MUXREG,
1814 { 2080 {
1815 .reg = PCIE_SATA_CFG, 2081 .reg = PCIE_SATA_CFG,
1816 .mask = PCIE_CFG_VAL(1), 2082 .mask = PCIE_CFG_VAL(1),
@@ -1827,15 +2093,12 @@ static struct spear_modemux pcie1_modemux[] = {
1827 2093
1828static struct spear_pingroup pcie1_pingroup = { 2094static struct spear_pingroup pcie1_pingroup = {
1829 .name = "pcie1_grp", 2095 .name = "pcie1_grp",
1830 .pins = pci_sata_pins,
1831 .npins = ARRAY_SIZE(pci_sata_pins),
1832 .modemuxs = pcie1_modemux, 2096 .modemuxs = pcie1_modemux,
1833 .nmodemuxs = ARRAY_SIZE(pcie1_modemux), 2097 .nmodemuxs = ARRAY_SIZE(pcie1_modemux),
1834}; 2098};
1835 2099
1836/* pad multiplexing for pcie2 device */ 2100/* pad multiplexing for (fix-part) pcie2 device */
1837static struct spear_muxreg pcie2_muxreg[] = { 2101static struct spear_muxreg pcie2_muxreg[] = {
1838 PCI_SATA_MUXREG,
1839 { 2102 {
1840 .reg = PCIE_SATA_CFG, 2103 .reg = PCIE_SATA_CFG,
1841 .mask = PCIE_CFG_VAL(2), 2104 .mask = PCIE_CFG_VAL(2),
@@ -1852,22 +2115,20 @@ static struct spear_modemux pcie2_modemux[] = {
1852 2115
1853static struct spear_pingroup pcie2_pingroup = { 2116static struct spear_pingroup pcie2_pingroup = {
1854 .name = "pcie2_grp", 2117 .name = "pcie2_grp",
1855 .pins = pci_sata_pins,
1856 .npins = ARRAY_SIZE(pci_sata_pins),
1857 .modemuxs = pcie2_modemux, 2118 .modemuxs = pcie2_modemux,
1858 .nmodemuxs = ARRAY_SIZE(pcie2_modemux), 2119 .nmodemuxs = ARRAY_SIZE(pcie2_modemux),
1859}; 2120};
1860 2121
1861static const char *const pci_grps[] = { "pcie0_grp", "pcie1_grp", "pcie2_grp" }; 2122static const char *const pcie_grps[] = { "pcie0_grp", "pcie1_grp", "pcie2_grp"
1862static struct spear_function pci_function = { 2123};
1863 .name = "pci", 2124static struct spear_function pcie_function = {
1864 .groups = pci_grps, 2125 .name = "pci_express",
1865 .ngroups = ARRAY_SIZE(pci_grps), 2126 .groups = pcie_grps,
2127 .ngroups = ARRAY_SIZE(pcie_grps),
1866}; 2128};
1867 2129
1868/* pad multiplexing for sata0 device */ 2130/* pad multiplexing for sata0 device */
1869static struct spear_muxreg sata0_muxreg[] = { 2131static struct spear_muxreg sata0_muxreg[] = {
1870 PCI_SATA_MUXREG,
1871 { 2132 {
1872 .reg = PCIE_SATA_CFG, 2133 .reg = PCIE_SATA_CFG,
1873 .mask = SATA_CFG_VAL(0), 2134 .mask = SATA_CFG_VAL(0),
@@ -1884,15 +2145,12 @@ static struct spear_modemux sata0_modemux[] = {
1884 2145
1885static struct spear_pingroup sata0_pingroup = { 2146static struct spear_pingroup sata0_pingroup = {
1886 .name = "sata0_grp", 2147 .name = "sata0_grp",
1887 .pins = pci_sata_pins,
1888 .npins = ARRAY_SIZE(pci_sata_pins),
1889 .modemuxs = sata0_modemux, 2148 .modemuxs = sata0_modemux,
1890 .nmodemuxs = ARRAY_SIZE(sata0_modemux), 2149 .nmodemuxs = ARRAY_SIZE(sata0_modemux),
1891}; 2150};
1892 2151
1893/* pad multiplexing for sata1 device */ 2152/* pad multiplexing for sata1 device */
1894static struct spear_muxreg sata1_muxreg[] = { 2153static struct spear_muxreg sata1_muxreg[] = {
1895 PCI_SATA_MUXREG,
1896 { 2154 {
1897 .reg = PCIE_SATA_CFG, 2155 .reg = PCIE_SATA_CFG,
1898 .mask = SATA_CFG_VAL(1), 2156 .mask = SATA_CFG_VAL(1),
@@ -1909,15 +2167,12 @@ static struct spear_modemux sata1_modemux[] = {
1909 2167
1910static struct spear_pingroup sata1_pingroup = { 2168static struct spear_pingroup sata1_pingroup = {
1911 .name = "sata1_grp", 2169 .name = "sata1_grp",
1912 .pins = pci_sata_pins,
1913 .npins = ARRAY_SIZE(pci_sata_pins),
1914 .modemuxs = sata1_modemux, 2170 .modemuxs = sata1_modemux,
1915 .nmodemuxs = ARRAY_SIZE(sata1_modemux), 2171 .nmodemuxs = ARRAY_SIZE(sata1_modemux),
1916}; 2172};
1917 2173
1918/* pad multiplexing for sata2 device */ 2174/* pad multiplexing for sata2 device */
1919static struct spear_muxreg sata2_muxreg[] = { 2175static struct spear_muxreg sata2_muxreg[] = {
1920 PCI_SATA_MUXREG,
1921 { 2176 {
1922 .reg = PCIE_SATA_CFG, 2177 .reg = PCIE_SATA_CFG,
1923 .mask = SATA_CFG_VAL(2), 2178 .mask = SATA_CFG_VAL(2),
@@ -1934,8 +2189,6 @@ static struct spear_modemux sata2_modemux[] = {
1934 2189
1935static struct spear_pingroup sata2_pingroup = { 2190static struct spear_pingroup sata2_pingroup = {
1936 .name = "sata2_grp", 2191 .name = "sata2_grp",
1937 .pins = pci_sata_pins,
1938 .npins = ARRAY_SIZE(pci_sata_pins),
1939 .modemuxs = sata2_modemux, 2192 .modemuxs = sata2_modemux,
1940 .nmodemuxs = ARRAY_SIZE(sata2_modemux), 2193 .nmodemuxs = ARRAY_SIZE(sata2_modemux),
1941}; 2194};
@@ -1957,6 +2210,14 @@ static struct spear_muxreg ssp1_dis_kbd_muxreg[] = {
1957 PMX_KBD_COL0_MASK | PMX_NFIO8_15_MASK | PMX_NFCE1_MASK | 2210 PMX_KBD_COL0_MASK | PMX_NFIO8_15_MASK | PMX_NFCE1_MASK |
1958 PMX_NFCE2_MASK, 2211 PMX_NFCE2_MASK,
1959 .val = 0, 2212 .val = 0,
2213 }, {
2214 .reg = PAD_DIRECTION_SEL_1,
2215 .mask = PMX_KBD_ROWCOL25_MASK | PMX_KBD_COL1_MASK |
2216 PMX_KBD_COL0_MASK | PMX_NFIO8_15_MASK | PMX_NFCE1_MASK |
2217 PMX_NFCE2_MASK,
2218 .val = PMX_KBD_ROWCOL25_MASK | PMX_KBD_COL1_MASK |
2219 PMX_KBD_COL0_MASK | PMX_NFIO8_15_MASK | PMX_NFCE1_MASK |
2220 PMX_NFCE2_MASK,
1960 }, 2221 },
1961}; 2222};
1962 2223
@@ -1983,6 +2244,12 @@ static struct spear_muxreg ssp1_dis_sd_muxreg[] = {
1983 .mask = PMX_MCIADDR0ALE_MASK | PMX_MCIADDR2_MASK | 2244 .mask = PMX_MCIADDR0ALE_MASK | PMX_MCIADDR2_MASK |
1984 PMX_MCICECF_MASK | PMX_MCICEXD_MASK, 2245 PMX_MCICECF_MASK | PMX_MCICEXD_MASK,
1985 .val = 0, 2246 .val = 0,
2247 }, {
2248 .reg = PAD_DIRECTION_SEL_2,
2249 .mask = PMX_MCIADDR0ALE_MASK | PMX_MCIADDR2_MASK |
2250 PMX_MCICECF_MASK | PMX_MCICEXD_MASK,
2251 .val = PMX_MCIADDR0ALE_MASK | PMX_MCIADDR2_MASK |
2252 PMX_MCICECF_MASK | PMX_MCICEXD_MASK,
1986 }, 2253 },
1987}; 2254};
1988 2255
@@ -2017,6 +2284,12 @@ static struct spear_muxreg gpt64_muxreg[] = {
2017 .mask = PMX_MCICDCF1_MASK | PMX_MCICDCF2_MASK | PMX_MCICDXD_MASK 2284 .mask = PMX_MCICDCF1_MASK | PMX_MCICDCF2_MASK | PMX_MCICDXD_MASK
2018 | PMX_MCILEDS_MASK, 2285 | PMX_MCILEDS_MASK,
2019 .val = 0, 2286 .val = 0,
2287 }, {
2288 .reg = PAD_DIRECTION_SEL_2,
2289 .mask = PMX_MCICDCF1_MASK | PMX_MCICDCF2_MASK | PMX_MCICDXD_MASK
2290 | PMX_MCILEDS_MASK,
2291 .val = PMX_MCICDCF1_MASK | PMX_MCICDCF2_MASK | PMX_MCICDXD_MASK
2292 | PMX_MCILEDS_MASK,
2020 }, 2293 },
2021}; 2294};
2022 2295
@@ -2093,6 +2366,7 @@ static struct spear_pingroup *spear1310_pingroups[] = {
2093 &can0_dis_sd_pingroup, 2366 &can0_dis_sd_pingroup,
2094 &can1_dis_sd_pingroup, 2367 &can1_dis_sd_pingroup,
2095 &can1_dis_kbd_pingroup, 2368 &can1_dis_kbd_pingroup,
2369 &pci_pingroup,
2096 &pcie0_pingroup, 2370 &pcie0_pingroup,
2097 &pcie1_pingroup, 2371 &pcie1_pingroup,
2098 &pcie2_pingroup, 2372 &pcie2_pingroup,
@@ -2138,6 +2412,7 @@ static struct spear_function *spear1310_functions[] = {
2138 &can0_function, 2412 &can0_function,
2139 &can1_function, 2413 &can1_function,
2140 &pci_function, 2414 &pci_function,
2415 &pcie_function,
2141 &sata_function, 2416 &sata_function,
2142 &ssp1_function, 2417 &ssp1_function,
2143 &gpt64_function, 2418 &gpt64_function,
diff --git a/drivers/pinctrl/spear/pinctrl-spear1340.c b/drivers/pinctrl/spear/pinctrl-spear1340.c
index a0eb057e55b..0606b8cf3f2 100644
--- a/drivers/pinctrl/spear/pinctrl-spear1340.c
+++ b/drivers/pinctrl/spear/pinctrl-spear1340.c
@@ -213,7 +213,7 @@ static const struct pinctrl_pin_desc spear1340_pins[] = {
213 * Pad multiplexing for making all pads as gpio's. This is done to override the 213 * Pad multiplexing for making all pads as gpio's. This is done to override the
214 * values passed from bootloader and start from scratch. 214 * values passed from bootloader and start from scratch.
215 */ 215 */
216static const unsigned pads_as_gpio_pins[] = { 251 }; 216static const unsigned pads_as_gpio_pins[] = { 12, 88, 89, 251 };
217static struct spear_muxreg pads_as_gpio_muxreg[] = { 217static struct spear_muxreg pads_as_gpio_muxreg[] = {
218 { 218 {
219 .reg = PAD_FUNCTION_EN_1, 219 .reg = PAD_FUNCTION_EN_1,
@@ -1692,7 +1692,43 @@ static struct spear_pingroup clcd_pingroup = {
1692 .nmodemuxs = ARRAY_SIZE(clcd_modemux), 1692 .nmodemuxs = ARRAY_SIZE(clcd_modemux),
1693}; 1693};
1694 1694
1695static const char *const clcd_grps[] = { "clcd_grp" }; 1695/* Disable cld runtime to save panel damage */
1696static struct spear_muxreg clcd_sleep_muxreg[] = {
1697 {
1698 .reg = PAD_SHARED_IP_EN_1,
1699 .mask = ARM_TRACE_MASK | MIPHY_DBG_MASK,
1700 .val = 0,
1701 }, {
1702 .reg = PAD_FUNCTION_EN_5,
1703 .mask = CLCD_REG4_MASK | CLCD_AND_ARM_TRACE_REG4_MASK,
1704 .val = 0x0,
1705 }, {
1706 .reg = PAD_FUNCTION_EN_6,
1707 .mask = CLCD_AND_ARM_TRACE_REG5_MASK,
1708 .val = 0x0,
1709 }, {
1710 .reg = PAD_FUNCTION_EN_7,
1711 .mask = CLCD_AND_ARM_TRACE_REG6_MASK,
1712 .val = 0x0,
1713 },
1714};
1715
1716static struct spear_modemux clcd_sleep_modemux[] = {
1717 {
1718 .muxregs = clcd_sleep_muxreg,
1719 .nmuxregs = ARRAY_SIZE(clcd_sleep_muxreg),
1720 },
1721};
1722
1723static struct spear_pingroup clcd_sleep_pingroup = {
1724 .name = "clcd_sleep_grp",
1725 .pins = clcd_pins,
1726 .npins = ARRAY_SIZE(clcd_pins),
1727 .modemuxs = clcd_sleep_modemux,
1728 .nmodemuxs = ARRAY_SIZE(clcd_sleep_modemux),
1729};
1730
1731static const char *const clcd_grps[] = { "clcd_grp", "clcd_sleep_grp" };
1696static struct spear_function clcd_function = { 1732static struct spear_function clcd_function = {
1697 .name = "clcd", 1733 .name = "clcd",
1698 .groups = clcd_grps, 1734 .groups = clcd_grps,
@@ -1893,6 +1929,7 @@ static struct spear_pingroup *spear1340_pingroups[] = {
1893 &sdhci_pingroup, 1929 &sdhci_pingroup,
1894 &cf_pingroup, 1930 &cf_pingroup,
1895 &xd_pingroup, 1931 &xd_pingroup,
1932 &clcd_sleep_pingroup,
1896 &clcd_pingroup, 1933 &clcd_pingroup,
1897 &arm_trace_pingroup, 1934 &arm_trace_pingroup,
1898 &miphy_dbg_pingroup, 1935 &miphy_dbg_pingroup,
diff --git a/drivers/pinctrl/spear/pinctrl-spear320.c b/drivers/pinctrl/spear/pinctrl-spear320.c
index 020b1e0bdb3..ca47b0e5078 100644
--- a/drivers/pinctrl/spear/pinctrl-spear320.c
+++ b/drivers/pinctrl/spear/pinctrl-spear320.c
@@ -2240,6 +2240,10 @@ static struct spear_muxreg pwm2_pin_34_muxreg[] = {
2240 .mask = PMX_SSP_CS_MASK, 2240 .mask = PMX_SSP_CS_MASK,
2241 .val = 0, 2241 .val = 0,
2242 }, { 2242 }, {
2243 .reg = MODE_CONFIG_REG,
2244 .mask = PMX_PWM_MASK,
2245 .val = PMX_PWM_MASK,
2246 }, {
2243 .reg = IP_SEL_PAD_30_39_REG, 2247 .reg = IP_SEL_PAD_30_39_REG,
2244 .mask = PMX_PL_34_MASK, 2248 .mask = PMX_PL_34_MASK,
2245 .val = PMX_PWM2_PL_34_VAL, 2249 .val = PMX_PWM2_PL_34_VAL,
@@ -2956,9 +2960,9 @@ static struct spear_function mii2_function = {
2956}; 2960};
2957 2961
2958/* Pad multiplexing for cadence mii 1_2 as smii or rmii device */ 2962/* Pad multiplexing for cadence mii 1_2 as smii or rmii device */
2959static const unsigned smii0_1_pins[] = { 10, 11, 13, 14, 15, 16, 17, 18, 19, 20, 2963static const unsigned rmii0_1_pins[] = { 10, 11, 13, 14, 15, 16, 17, 18, 19, 20,
2960 21, 22, 23, 24, 25, 26, 27 }; 2964 21, 22, 23, 24, 25, 26, 27 };
2961static const unsigned rmii0_1_pins[] = { 10, 11, 21, 22, 23, 24, 25, 26, 27 }; 2965static const unsigned smii0_1_pins[] = { 10, 11, 21, 22, 23, 24, 25, 26, 27 };
2962static struct spear_muxreg mii0_1_muxreg[] = { 2966static struct spear_muxreg mii0_1_muxreg[] = {
2963 { 2967 {
2964 .reg = PMX_CONFIG_REG, 2968 .reg = PMX_CONFIG_REG,
diff --git a/drivers/pinctrl/spear/pinctrl-spear3xx.h b/drivers/pinctrl/spear/pinctrl-spear3xx.h
index 31f44347f17..7860b36053c 100644
--- a/drivers/pinctrl/spear/pinctrl-spear3xx.h
+++ b/drivers/pinctrl/spear/pinctrl-spear3xx.h
@@ -15,6 +15,7 @@
15#include "pinctrl-spear.h" 15#include "pinctrl-spear.h"
16 16
17/* pad mux declarations */ 17/* pad mux declarations */
18#define PMX_PWM_MASK (1 << 16)
18#define PMX_FIRDA_MASK (1 << 14) 19#define PMX_FIRDA_MASK (1 << 14)
19#define PMX_I2C_MASK (1 << 13) 20#define PMX_I2C_MASK (1 << 13)
20#define PMX_SSP_CS_MASK (1 << 12) 21#define PMX_SSP_CS_MASK (1 << 12)
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-05 16:16:51 -0500