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-rw-r--r--drivers/pinctrl/Kconfig29
-rw-r--r--drivers/pinctrl/Makefile8
-rw-r--r--drivers/pinctrl/core.c263
-rw-r--r--drivers/pinctrl/core.h12
-rw-r--r--drivers/pinctrl/devicetree.c249
-rw-r--r--drivers/pinctrl/devicetree.h35
-rw-r--r--drivers/pinctrl/pinconf.c52
-rw-r--r--drivers/pinctrl/pinconf.h17
-rw-r--r--drivers/pinctrl/pinctrl-coh901.c4
-rw-r--r--drivers/pinctrl/pinctrl-imx.c627
-rw-r--r--drivers/pinctrl/pinctrl-imx.h106
-rw-r--r--drivers/pinctrl/pinctrl-imx23.c305
-rw-r--r--drivers/pinctrl/pinctrl-imx28.c421
-rw-r--r--drivers/pinctrl/pinctrl-imx6q.c2331
-rw-r--r--drivers/pinctrl/pinctrl-mxs.c508
-rw-r--r--drivers/pinctrl/pinctrl-mxs.h91
-rw-r--r--drivers/pinctrl/pinctrl-pxa3xx.c24
-rw-r--r--drivers/pinctrl/pinctrl-sirf.c20
-rw-r--r--drivers/pinctrl/pinctrl-tegra.c245
-rw-r--r--drivers/pinctrl/pinctrl-u300.c20
-rw-r--r--drivers/pinctrl/pinmux.c93
-rw-r--r--drivers/pinctrl/pinmux.h18
22 files changed, 5301 insertions, 177 deletions
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index b25ac41f793..a54a93112cb 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -4,7 +4,6 @@
4 4
5config PINCTRL 5config PINCTRL
6 bool 6 bool
7 depends on EXPERIMENTAL
8 7
9if PINCTRL 8if PINCTRL
10 9
@@ -27,6 +26,19 @@ config DEBUG_PINCTRL
27 help 26 help
28 Say Y here to add some extra checks and diagnostics to PINCTRL calls. 27 Say Y here to add some extra checks and diagnostics to PINCTRL calls.
29 28
29config PINCTRL_IMX
30 bool
31 select PINMUX
32 select PINCONF
33
34config PINCTRL_IMX6Q
35 bool "IMX6Q pinctrl driver"
36 depends on OF
37 depends on SOC_IMX6Q
38 select PINCTRL_IMX
39 help
40 Say Y here to enable the imx6q pinctrl driver
41
30config PINCTRL_PXA3xx 42config PINCTRL_PXA3xx
31 bool 43 bool
32 select PINMUX 44 select PINMUX
@@ -37,6 +49,21 @@ config PINCTRL_MMP2
37 select PINCTRL_PXA3xx 49 select PINCTRL_PXA3xx
38 select PINCONF 50 select PINCONF
39 51
52config PINCTRL_MXS
53 bool
54
55config PINCTRL_IMX23
56 bool
57 select PINMUX
58 select PINCONF
59 select PINCTRL_MXS
60
61config PINCTRL_IMX28
62 bool
63 select PINMUX
64 select PINCONF
65 select PINCTRL_MXS
66
40config PINCTRL_PXA168 67config PINCTRL_PXA168
41 bool "PXA168 pin controller driver" 68 bool "PXA168 pin controller driver"
42 depends on ARCH_MMP 69 depends on ARCH_MMP
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index 2febd760805..c9b0be56ff4 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -5,9 +5,17 @@ ccflags-$(CONFIG_DEBUG_PINCTRL) += -DDEBUG
5obj-$(CONFIG_PINCTRL) += core.o 5obj-$(CONFIG_PINCTRL) += core.o
6obj-$(CONFIG_PINMUX) += pinmux.o 6obj-$(CONFIG_PINMUX) += pinmux.o
7obj-$(CONFIG_PINCONF) += pinconf.o 7obj-$(CONFIG_PINCONF) += pinconf.o
8ifeq ($(CONFIG_OF),y)
9obj-$(CONFIG_PINCTRL) += devicetree.o
10endif
8obj-$(CONFIG_GENERIC_PINCONF) += pinconf-generic.o 11obj-$(CONFIG_GENERIC_PINCONF) += pinconf-generic.o
12obj-$(CONFIG_PINCTRL_IMX) += pinctrl-imx.o
13obj-$(CONFIG_PINCTRL_IMX6Q) += pinctrl-imx6q.o
9obj-$(CONFIG_PINCTRL_PXA3xx) += pinctrl-pxa3xx.o 14obj-$(CONFIG_PINCTRL_PXA3xx) += pinctrl-pxa3xx.o
10obj-$(CONFIG_PINCTRL_MMP2) += pinctrl-mmp2.o 15obj-$(CONFIG_PINCTRL_MMP2) += pinctrl-mmp2.o
16obj-$(CONFIG_PINCTRL_MXS) += pinctrl-mxs.o
17obj-$(CONFIG_PINCTRL_IMX23) += pinctrl-imx23.o
18obj-$(CONFIG_PINCTRL_IMX28) += pinctrl-imx28.o
11obj-$(CONFIG_PINCTRL_PXA168) += pinctrl-pxa168.o 19obj-$(CONFIG_PINCTRL_PXA168) += pinctrl-pxa168.o
12obj-$(CONFIG_PINCTRL_PXA910) += pinctrl-pxa910.o 20obj-$(CONFIG_PINCTRL_PXA910) += pinctrl-pxa910.o
13obj-$(CONFIG_PINCTRL_SIRF) += pinctrl-sirf.o 21obj-$(CONFIG_PINCTRL_SIRF) += pinctrl-sirf.o
diff --git a/drivers/pinctrl/core.c b/drivers/pinctrl/core.c
index ec3b8cc188a..c3b331b74fa 100644
--- a/drivers/pinctrl/core.c
+++ b/drivers/pinctrl/core.c
@@ -23,9 +23,11 @@
23#include <linux/sysfs.h> 23#include <linux/sysfs.h>
24#include <linux/debugfs.h> 24#include <linux/debugfs.h>
25#include <linux/seq_file.h> 25#include <linux/seq_file.h>
26#include <linux/pinctrl/consumer.h>
26#include <linux/pinctrl/pinctrl.h> 27#include <linux/pinctrl/pinctrl.h>
27#include <linux/pinctrl/machine.h> 28#include <linux/pinctrl/machine.h>
28#include "core.h" 29#include "core.h"
30#include "devicetree.h"
29#include "pinmux.h" 31#include "pinmux.h"
30#include "pinconf.h" 32#include "pinconf.h"
31 33
@@ -41,11 +43,13 @@ struct pinctrl_maps {
41 unsigned num_maps; 43 unsigned num_maps;
42}; 44};
43 45
46static bool pinctrl_dummy_state;
47
44/* Mutex taken by all entry points */ 48/* Mutex taken by all entry points */
45DEFINE_MUTEX(pinctrl_mutex); 49DEFINE_MUTEX(pinctrl_mutex);
46 50
47/* Global list of pin control devices (struct pinctrl_dev) */ 51/* Global list of pin control devices (struct pinctrl_dev) */
48static LIST_HEAD(pinctrldev_list); 52LIST_HEAD(pinctrldev_list);
49 53
50/* List of pin controller handles (struct pinctrl) */ 54/* List of pin controller handles (struct pinctrl) */
51static LIST_HEAD(pinctrl_list); 55static LIST_HEAD(pinctrl_list);
@@ -59,6 +63,19 @@ static LIST_HEAD(pinctrl_maps);
59 _i_ < _maps_node_->num_maps; \ 63 _i_ < _maps_node_->num_maps; \
60 i++, _map_ = &_maps_node_->maps[_i_]) 64 i++, _map_ = &_maps_node_->maps[_i_])
61 65
66/**
67 * pinctrl_provide_dummies() - indicate if pinctrl provides dummy state support
68 *
69 * Usually this function is called by platforms without pinctrl driver support
70 * but run with some shared drivers using pinctrl APIs.
71 * After calling this function, the pinctrl core will return successfully
72 * with creating a dummy state for the driver to keep going smoothly.
73 */
74void pinctrl_provide_dummies(void)
75{
76 pinctrl_dummy_state = true;
77}
78
62const char *pinctrl_dev_get_name(struct pinctrl_dev *pctldev) 79const char *pinctrl_dev_get_name(struct pinctrl_dev *pctldev)
63{ 80{
64 /* We're not allowed to register devices without name */ 81 /* We're not allowed to register devices without name */
@@ -124,6 +141,25 @@ int pin_get_from_name(struct pinctrl_dev *pctldev, const char *name)
124} 141}
125 142
126/** 143/**
144 * pin_get_name_from_id() - look up a pin name from a pin id
145 * @pctldev: the pin control device to lookup the pin on
146 * @name: the name of the pin to look up
147 */
148const char *pin_get_name(struct pinctrl_dev *pctldev, const unsigned pin)
149{
150 const struct pin_desc *desc;
151
152 desc = pin_desc_get(pctldev, pin);
153 if (desc == NULL) {
154 dev_err(pctldev->dev, "failed to get pin(%d) name\n",
155 pin);
156 return NULL;
157 }
158
159 return desc->name;
160}
161
162/**
127 * pin_is_valid() - check if pin exists on controller 163 * pin_is_valid() - check if pin exists on controller
128 * @pctldev: the pin control device to check the pin on 164 * @pctldev: the pin control device to check the pin on
129 * @pin: pin to check, use the local pin controller index number 165 * @pin: pin to check, use the local pin controller index number
@@ -255,7 +291,8 @@ pinctrl_match_gpio_range(struct pinctrl_dev *pctldev, unsigned gpio)
255 * 291 *
256 * Find the pin controller handling a certain GPIO pin from the pinspace of 292 * Find the pin controller handling a certain GPIO pin from the pinspace of
257 * the GPIO subsystem, return the device and the matching GPIO range. Returns 293 * the GPIO subsystem, return the device and the matching GPIO range. Returns
258 * negative if the GPIO range could not be found in any device. 294 * -EPROBE_DEFER if the GPIO range could not be found in any device since it
295 * may still have not been registered.
259 */ 296 */
260static int pinctrl_get_device_gpio_range(unsigned gpio, 297static int pinctrl_get_device_gpio_range(unsigned gpio,
261 struct pinctrl_dev **outdev, 298 struct pinctrl_dev **outdev,
@@ -275,7 +312,7 @@ static int pinctrl_get_device_gpio_range(unsigned gpio,
275 } 312 }
276 } 313 }
277 314
278 return -EINVAL; 315 return -EPROBE_DEFER;
279} 316}
280 317
281/** 318/**
@@ -318,9 +355,10 @@ int pinctrl_get_group_selector(struct pinctrl_dev *pctldev,
318 const char *pin_group) 355 const char *pin_group)
319{ 356{
320 const struct pinctrl_ops *pctlops = pctldev->desc->pctlops; 357 const struct pinctrl_ops *pctlops = pctldev->desc->pctlops;
358 unsigned ngroups = pctlops->get_groups_count(pctldev);
321 unsigned group_selector = 0; 359 unsigned group_selector = 0;
322 360
323 while (pctlops->list_groups(pctldev, group_selector) >= 0) { 361 while (group_selector < ngroups) {
324 const char *gname = pctlops->get_group_name(pctldev, 362 const char *gname = pctlops->get_group_name(pctldev,
325 group_selector); 363 group_selector);
326 if (!strcmp(gname, pin_group)) { 364 if (!strcmp(gname, pin_group)) {
@@ -360,7 +398,7 @@ int pinctrl_request_gpio(unsigned gpio)
360 ret = pinctrl_get_device_gpio_range(gpio, &pctldev, &range); 398 ret = pinctrl_get_device_gpio_range(gpio, &pctldev, &range);
361 if (ret) { 399 if (ret) {
362 mutex_unlock(&pinctrl_mutex); 400 mutex_unlock(&pinctrl_mutex);
363 return -EINVAL; 401 return ret;
364 } 402 }
365 403
366 /* Convert to the pin controllers number space */ 404 /* Convert to the pin controllers number space */
@@ -516,11 +554,14 @@ static int add_setting(struct pinctrl *p, struct pinctrl_map const *map)
516 554
517 setting->pctldev = get_pinctrl_dev_from_devname(map->ctrl_dev_name); 555 setting->pctldev = get_pinctrl_dev_from_devname(map->ctrl_dev_name);
518 if (setting->pctldev == NULL) { 556 if (setting->pctldev == NULL) {
519 dev_err(p->dev, "unknown pinctrl device %s in map entry", 557 dev_info(p->dev, "unknown pinctrl device %s in map entry, deferring probe",
520 map->ctrl_dev_name); 558 map->ctrl_dev_name);
521 kfree(setting); 559 kfree(setting);
522 /* Eventually, this should trigger deferred probe */ 560 /*
523 return -ENODEV; 561 * OK let us guess that the driver is not there yet, and
562 * let's defer obtaining this pinctrl handle to later...
563 */
564 return -EPROBE_DEFER;
524 } 565 }
525 566
526 switch (map->type) { 567 switch (map->type) {
@@ -579,6 +620,13 @@ static struct pinctrl *create_pinctrl(struct device *dev)
579 } 620 }
580 p->dev = dev; 621 p->dev = dev;
581 INIT_LIST_HEAD(&p->states); 622 INIT_LIST_HEAD(&p->states);
623 INIT_LIST_HEAD(&p->dt_maps);
624
625 ret = pinctrl_dt_to_map(p);
626 if (ret < 0) {
627 kfree(p);
628 return ERR_PTR(ret);
629 }
582 630
583 devname = dev_name(dev); 631 devname = dev_name(dev);
584 632
@@ -662,6 +710,8 @@ static void pinctrl_put_locked(struct pinctrl *p, bool inlist)
662 kfree(state); 710 kfree(state);
663 } 711 }
664 712
713 pinctrl_dt_free_maps(p);
714
665 if (inlist) 715 if (inlist)
666 list_del(&p->node); 716 list_del(&p->node);
667 kfree(p); 717 kfree(p);
@@ -685,8 +735,18 @@ static struct pinctrl_state *pinctrl_lookup_state_locked(struct pinctrl *p,
685 struct pinctrl_state *state; 735 struct pinctrl_state *state;
686 736
687 state = find_state(p, name); 737 state = find_state(p, name);
688 if (!state) 738 if (!state) {
689 return ERR_PTR(-ENODEV); 739 if (pinctrl_dummy_state) {
740 /* create dummy state */
741 dev_dbg(p->dev, "using pinctrl dummy state (%s)\n",
742 name);
743 state = create_state(p, name);
744 if (IS_ERR(state))
745 return state;
746 } else {
747 return ERR_PTR(-ENODEV);
748 }
749 }
690 750
691 return state; 751 return state;
692} 752}
@@ -787,15 +847,63 @@ int pinctrl_select_state(struct pinctrl *p, struct pinctrl_state *state)
787} 847}
788EXPORT_SYMBOL_GPL(pinctrl_select_state); 848EXPORT_SYMBOL_GPL(pinctrl_select_state);
789 849
850static void devm_pinctrl_release(struct device *dev, void *res)
851{
852 pinctrl_put(*(struct pinctrl **)res);
853}
854
790/** 855/**
791 * pinctrl_register_mappings() - register a set of pin controller mappings 856 * struct devm_pinctrl_get() - Resource managed pinctrl_get()
792 * @maps: the pincontrol mappings table to register. This should probably be 857 * @dev: the device to obtain the handle for
793 * marked with __initdata so it can be discarded after boot. This 858 *
794 * function will perform a shallow copy for the mapping entries. 859 * If there is a need to explicitly destroy the returned struct pinctrl,
795 * @num_maps: the number of maps in the mapping table 860 * devm_pinctrl_put() should be used, rather than plain pinctrl_put().
796 */ 861 */
797int pinctrl_register_mappings(struct pinctrl_map const *maps, 862struct pinctrl *devm_pinctrl_get(struct device *dev)
798 unsigned num_maps) 863{
864 struct pinctrl **ptr, *p;
865
866 ptr = devres_alloc(devm_pinctrl_release, sizeof(*ptr), GFP_KERNEL);
867 if (!ptr)
868 return ERR_PTR(-ENOMEM);
869
870 p = pinctrl_get(dev);
871 if (!IS_ERR(p)) {
872 *ptr = p;
873 devres_add(dev, ptr);
874 } else {
875 devres_free(ptr);
876 }
877
878 return p;
879}
880EXPORT_SYMBOL_GPL(devm_pinctrl_get);
881
882static int devm_pinctrl_match(struct device *dev, void *res, void *data)
883{
884 struct pinctrl **p = res;
885
886 return *p == data;
887}
888
889/**
890 * devm_pinctrl_put() - Resource managed pinctrl_put()
891 * @p: the pinctrl handle to release
892 *
893 * Deallocate a struct pinctrl obtained via devm_pinctrl_get(). Normally
894 * this function will not need to be called and the resource management
895 * code will ensure that the resource is freed.
896 */
897void devm_pinctrl_put(struct pinctrl *p)
898{
899 WARN_ON(devres_destroy(p->dev, devm_pinctrl_release,
900 devm_pinctrl_match, p));
901 pinctrl_put(p);
902}
903EXPORT_SYMBOL_GPL(devm_pinctrl_put);
904
905int pinctrl_register_map(struct pinctrl_map const *maps, unsigned num_maps,
906 bool dup, bool locked)
799{ 907{
800 int i, ret; 908 int i, ret;
801 struct pinctrl_maps *maps_node; 909 struct pinctrl_maps *maps_node;
@@ -829,13 +937,13 @@ int pinctrl_register_mappings(struct pinctrl_map const *maps,
829 case PIN_MAP_TYPE_MUX_GROUP: 937 case PIN_MAP_TYPE_MUX_GROUP:
830 ret = pinmux_validate_map(&maps[i], i); 938 ret = pinmux_validate_map(&maps[i], i);
831 if (ret < 0) 939 if (ret < 0)
832 return 0; 940 return ret;
833 break; 941 break;
834 case PIN_MAP_TYPE_CONFIGS_PIN: 942 case PIN_MAP_TYPE_CONFIGS_PIN:
835 case PIN_MAP_TYPE_CONFIGS_GROUP: 943 case PIN_MAP_TYPE_CONFIGS_GROUP:
836 ret = pinconf_validate_map(&maps[i], i); 944 ret = pinconf_validate_map(&maps[i], i);
837 if (ret < 0) 945 if (ret < 0)
838 return 0; 946 return ret;
839 break; 947 break;
840 default: 948 default:
841 pr_err("failed to register map %s (%d): invalid type given\n", 949 pr_err("failed to register map %s (%d): invalid type given\n",
@@ -851,20 +959,52 @@ int pinctrl_register_mappings(struct pinctrl_map const *maps,
851 } 959 }
852 960
853 maps_node->num_maps = num_maps; 961 maps_node->num_maps = num_maps;
854 maps_node->maps = kmemdup(maps, sizeof(*maps) * num_maps, GFP_KERNEL); 962 if (dup) {
855 if (!maps_node->maps) { 963 maps_node->maps = kmemdup(maps, sizeof(*maps) * num_maps,
856 pr_err("failed to duplicate mapping table\n"); 964 GFP_KERNEL);
857 kfree(maps_node); 965 if (!maps_node->maps) {
858 return -ENOMEM; 966 pr_err("failed to duplicate mapping table\n");
967 kfree(maps_node);
968 return -ENOMEM;
969 }
970 } else {
971 maps_node->maps = maps;
859 } 972 }
860 973
861 mutex_lock(&pinctrl_mutex); 974 if (!locked)
975 mutex_lock(&pinctrl_mutex);
862 list_add_tail(&maps_node->node, &pinctrl_maps); 976 list_add_tail(&maps_node->node, &pinctrl_maps);
863 mutex_unlock(&pinctrl_mutex); 977 if (!locked)
978 mutex_unlock(&pinctrl_mutex);
864 979
865 return 0; 980 return 0;
866} 981}
867 982
983/**
984 * pinctrl_register_mappings() - register a set of pin controller mappings
985 * @maps: the pincontrol mappings table to register. This should probably be
986 * marked with __initdata so it can be discarded after boot. This
987 * function will perform a shallow copy for the mapping entries.
988 * @num_maps: the number of maps in the mapping table
989 */
990int pinctrl_register_mappings(struct pinctrl_map const *maps,
991 unsigned num_maps)
992{
993 return pinctrl_register_map(maps, num_maps, true, false);
994}
995
996void pinctrl_unregister_map(struct pinctrl_map const *map)
997{
998 struct pinctrl_maps *maps_node;
999
1000 list_for_each_entry(maps_node, &pinctrl_maps, node) {
1001 if (maps_node->maps == map) {
1002 list_del(&maps_node->node);
1003 return;
1004 }
1005 }
1006}
1007
868#ifdef CONFIG_DEBUG_FS 1008#ifdef CONFIG_DEBUG_FS
869 1009
870static int pinctrl_pins_show(struct seq_file *s, void *what) 1010static int pinctrl_pins_show(struct seq_file *s, void *what)
@@ -906,19 +1046,17 @@ static int pinctrl_groups_show(struct seq_file *s, void *what)
906{ 1046{
907 struct pinctrl_dev *pctldev = s->private; 1047 struct pinctrl_dev *pctldev = s->private;
908 const struct pinctrl_ops *ops = pctldev->desc->pctlops; 1048 const struct pinctrl_ops *ops = pctldev->desc->pctlops;
909 unsigned selector = 0; 1049 unsigned ngroups, selector = 0;
910
911 /* No grouping */
912 if (!ops)
913 return 0;
914 1050
1051 ngroups = ops->get_groups_count(pctldev);
915 mutex_lock(&pinctrl_mutex); 1052 mutex_lock(&pinctrl_mutex);
916 1053
917 seq_puts(s, "registered pin groups:\n"); 1054 seq_puts(s, "registered pin groups:\n");
918 while (ops->list_groups(pctldev, selector) >= 0) { 1055 while (selector < ngroups) {
919 const unsigned *pins; 1056 const unsigned *pins;
920 unsigned num_pins; 1057 unsigned num_pins;
921 const char *gname = ops->get_group_name(pctldev, selector); 1058 const char *gname = ops->get_group_name(pctldev, selector);
1059 const char *pname;
922 int ret; 1060 int ret;
923 int i; 1061 int i;
924 1062
@@ -928,10 +1066,14 @@ static int pinctrl_groups_show(struct seq_file *s, void *what)
928 seq_printf(s, "%s [ERROR GETTING PINS]\n", 1066 seq_printf(s, "%s [ERROR GETTING PINS]\n",
929 gname); 1067 gname);
930 else { 1068 else {
931 seq_printf(s, "group: %s, pins = [ ", gname); 1069 seq_printf(s, "group: %s\n", gname);
932 for (i = 0; i < num_pins; i++) 1070 for (i = 0; i < num_pins; i++) {
933 seq_printf(s, "%d ", pins[i]); 1071 pname = pin_get_name(pctldev, pins[i]);
934 seq_puts(s, "]\n"); 1072 if (WARN_ON(!pname))
1073 return -EINVAL;
1074 seq_printf(s, "pin %d (%s)\n", pins[i], pname);
1075 }
1076 seq_puts(s, "\n");
935 } 1077 }
936 selector++; 1078 selector++;
937 } 1079 }
@@ -1225,6 +1367,22 @@ static void pinctrl_remove_device_debugfs(struct pinctrl_dev *pctldev)
1225 1367
1226#endif 1368#endif
1227 1369
1370static int pinctrl_check_ops(struct pinctrl_dev *pctldev)
1371{
1372 const struct pinctrl_ops *ops = pctldev->desc->pctlops;
1373
1374 if (!ops ||
1375 !ops->get_groups_count ||
1376 !ops->get_group_name ||
1377 !ops->get_group_pins)
1378 return -EINVAL;
1379
1380 if (ops->dt_node_to_map && !ops->dt_free_map)
1381 return -EINVAL;
1382
1383 return 0;
1384}
1385
1228/** 1386/**
1229 * pinctrl_register() - register a pin controller device 1387 * pinctrl_register() - register a pin controller device
1230 * @pctldesc: descriptor for this pin controller 1388 * @pctldesc: descriptor for this pin controller
@@ -1256,32 +1414,32 @@ struct pinctrl_dev *pinctrl_register(struct pinctrl_desc *pctldesc,
1256 INIT_LIST_HEAD(&pctldev->gpio_ranges); 1414 INIT_LIST_HEAD(&pctldev->gpio_ranges);
1257 pctldev->dev = dev; 1415 pctldev->dev = dev;
1258 1416
1417 /* check core ops for sanity */
1418 ret = pinctrl_check_ops(pctldev);
1419 if (ret) {
1420 dev_err(dev, "pinctrl ops lacks necessary functions\n");
1421 goto out_err;
1422 }
1423
1259 /* If we're implementing pinmuxing, check the ops for sanity */ 1424 /* If we're implementing pinmuxing, check the ops for sanity */
1260 if (pctldesc->pmxops) { 1425 if (pctldesc->pmxops) {
1261 ret = pinmux_check_ops(pctldev); 1426 ret = pinmux_check_ops(pctldev);
1262 if (ret) { 1427 if (ret)
1263 pr_err("%s pinmux ops lacks necessary functions\n",
1264 pctldesc->name);
1265 goto out_err; 1428 goto out_err;
1266 }
1267 } 1429 }
1268 1430
1269 /* If we're implementing pinconfig, check the ops for sanity */ 1431 /* If we're implementing pinconfig, check the ops for sanity */
1270 if (pctldesc->confops) { 1432 if (pctldesc->confops) {
1271 ret = pinconf_check_ops(pctldev); 1433 ret = pinconf_check_ops(pctldev);
1272 if (ret) { 1434 if (ret)
1273 pr_err("%s pin config ops lacks necessary functions\n",
1274 pctldesc->name);
1275 goto out_err; 1435 goto out_err;
1276 }
1277 } 1436 }
1278 1437
1279 /* Register all the pins */ 1438 /* Register all the pins */
1280 pr_debug("try to register %d pins on %s...\n", 1439 dev_dbg(dev, "try to register %d pins ...\n", pctldesc->npins);
1281 pctldesc->npins, pctldesc->name);
1282 ret = pinctrl_register_pins(pctldev, pctldesc->pins, pctldesc->npins); 1440 ret = pinctrl_register_pins(pctldev, pctldesc->pins, pctldesc->npins);
1283 if (ret) { 1441 if (ret) {
1284 pr_err("error during pin registration\n"); 1442 dev_err(dev, "error during pin registration\n");
1285 pinctrl_free_pindescs(pctldev, pctldesc->pins, 1443 pinctrl_free_pindescs(pctldev, pctldesc->pins,
1286 pctldesc->npins); 1444 pctldesc->npins);
1287 goto out_err; 1445 goto out_err;
@@ -1296,8 +1454,15 @@ struct pinctrl_dev *pinctrl_register(struct pinctrl_desc *pctldesc,
1296 struct pinctrl_state *s = 1454 struct pinctrl_state *s =
1297 pinctrl_lookup_state_locked(pctldev->p, 1455 pinctrl_lookup_state_locked(pctldev->p,
1298 PINCTRL_STATE_DEFAULT); 1456 PINCTRL_STATE_DEFAULT);
1299 if (!IS_ERR(s)) 1457 if (IS_ERR(s)) {
1300 pinctrl_select_state_locked(pctldev->p, s); 1458 dev_dbg(dev, "failed to lookup the default state\n");
1459 } else {
1460 ret = pinctrl_select_state_locked(pctldev->p, s);
1461 if (ret) {
1462 dev_err(dev,
1463 "failed to select default state\n");
1464 }
1465 }
1301 } 1466 }
1302 1467
1303 mutex_unlock(&pinctrl_mutex); 1468 mutex_unlock(&pinctrl_mutex);
diff --git a/drivers/pinctrl/core.h b/drivers/pinctrl/core.h
index 17ecf651b12..1f40ff68a8c 100644
--- a/drivers/pinctrl/core.h
+++ b/drivers/pinctrl/core.h
@@ -52,12 +52,15 @@ struct pinctrl_dev {
52 * @dev: the device using this pin control handle 52 * @dev: the device using this pin control handle
53 * @states: a list of states for this device 53 * @states: a list of states for this device
54 * @state: the current state 54 * @state: the current state
55 * @dt_maps: the mapping table chunks dynamically parsed from device tree for
56 * this device, if any
55 */ 57 */
56struct pinctrl { 58struct pinctrl {
57 struct list_head node; 59 struct list_head node;
58 struct device *dev; 60 struct device *dev;
59 struct list_head states; 61 struct list_head states;
60 struct pinctrl_state *state; 62 struct pinctrl_state *state;
63 struct list_head dt_maps;
61}; 64};
62 65
63/** 66/**
@@ -100,7 +103,8 @@ struct pinctrl_setting_configs {
100 * struct pinctrl_setting - an individual mux or config setting 103 * struct pinctrl_setting - an individual mux or config setting
101 * @node: list node for struct pinctrl_settings's @settings field 104 * @node: list node for struct pinctrl_settings's @settings field
102 * @type: the type of setting 105 * @type: the type of setting
103 * @pctldev: pin control device handling to be programmed 106 * @pctldev: pin control device handling to be programmed. Not used for
107 * PIN_MAP_TYPE_DUMMY_STATE.
104 * @data: Data specific to the setting type 108 * @data: Data specific to the setting type
105 */ 109 */
106struct pinctrl_setting { 110struct pinctrl_setting {
@@ -144,6 +148,7 @@ struct pin_desc {
144 148
145struct pinctrl_dev *get_pinctrl_dev_from_devname(const char *dev_name); 149struct pinctrl_dev *get_pinctrl_dev_from_devname(const char *dev_name);
146int pin_get_from_name(struct pinctrl_dev *pctldev, const char *name); 150int pin_get_from_name(struct pinctrl_dev *pctldev, const char *name);
151const char *pin_get_name(struct pinctrl_dev *pctldev, const unsigned pin);
147int pinctrl_get_group_selector(struct pinctrl_dev *pctldev, 152int pinctrl_get_group_selector(struct pinctrl_dev *pctldev,
148 const char *pin_group); 153 const char *pin_group);
149 154
@@ -153,4 +158,9 @@ static inline struct pin_desc *pin_desc_get(struct pinctrl_dev *pctldev,
153 return radix_tree_lookup(&pctldev->pin_desc_tree, pin); 158 return radix_tree_lookup(&pctldev->pin_desc_tree, pin);
154} 159}
155 160
161int pinctrl_register_map(struct pinctrl_map const *maps, unsigned num_maps,
162 bool dup, bool locked);
163void pinctrl_unregister_map(struct pinctrl_map const *map);
164
156extern struct mutex pinctrl_mutex; 165extern struct mutex pinctrl_mutex;
166extern struct list_head pinctrldev_list;
diff --git a/drivers/pinctrl/devicetree.c b/drivers/pinctrl/devicetree.c
new file mode 100644
index 00000000000..fcb1de45473
--- /dev/null
+++ b/drivers/pinctrl/devicetree.c
@@ -0,0 +1,249 @@
1/*
2 * Device tree integration for the pin control subsystem
3 *
4 * Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program. If not, see <http://www.gnu.org/licenses/>.
17 */
18
19#include <linux/device.h>
20#include <linux/of.h>
21#include <linux/pinctrl/pinctrl.h>
22#include <linux/slab.h>
23
24#include "core.h"
25#include "devicetree.h"
26
27/**
28 * struct pinctrl_dt_map - mapping table chunk parsed from device tree
29 * @node: list node for struct pinctrl's @dt_maps field
30 * @pctldev: the pin controller that allocated this struct, and will free it
31 * @maps: the mapping table entries
32 */
33struct pinctrl_dt_map {
34 struct list_head node;
35 struct pinctrl_dev *pctldev;
36 struct pinctrl_map *map;
37 unsigned num_maps;
38};
39
40static void dt_free_map(struct pinctrl_dev *pctldev,
41 struct pinctrl_map *map, unsigned num_maps)
42{
43 if (pctldev) {
44 struct pinctrl_ops *ops = pctldev->desc->pctlops;
45 ops->dt_free_map(pctldev, map, num_maps);
46 } else {
47 /* There is no pctldev for PIN_MAP_TYPE_DUMMY_STATE */
48 kfree(map);
49 }
50}
51
52void pinctrl_dt_free_maps(struct pinctrl *p)
53{
54 struct pinctrl_dt_map *dt_map, *n1;
55
56 list_for_each_entry_safe(dt_map, n1, &p->dt_maps, node) {
57 pinctrl_unregister_map(dt_map->map);
58 list_del(&dt_map->node);
59 dt_free_map(dt_map->pctldev, dt_map->map,
60 dt_map->num_maps);
61 kfree(dt_map);
62 }
63
64 of_node_put(p->dev->of_node);
65}
66
67static int dt_remember_or_free_map(struct pinctrl *p, const char *statename,
68 struct pinctrl_dev *pctldev,
69 struct pinctrl_map *map, unsigned num_maps)
70{
71 int i;
72 struct pinctrl_dt_map *dt_map;
73
74 /* Initialize common mapping table entry fields */
75 for (i = 0; i < num_maps; i++) {
76 map[i].dev_name = dev_name(p->dev);
77 map[i].name = statename;
78 if (pctldev)
79 map[i].ctrl_dev_name = dev_name(pctldev->dev);
80 }
81
82 /* Remember the converted mapping table entries */
83 dt_map = kzalloc(sizeof(*dt_map), GFP_KERNEL);
84 if (!dt_map) {
85 dev_err(p->dev, "failed to alloc struct pinctrl_dt_map\n");
86 dt_free_map(pctldev, map, num_maps);
87 return -ENOMEM;
88 }
89
90 dt_map->pctldev = pctldev;
91 dt_map->map = map;
92 dt_map->num_maps = num_maps;
93 list_add_tail(&dt_map->node, &p->dt_maps);
94
95 return pinctrl_register_map(map, num_maps, false, true);
96}
97
98static struct pinctrl_dev *find_pinctrl_by_of_node(struct device_node *np)
99{
100 struct pinctrl_dev *pctldev;
101
102 list_for_each_entry(pctldev, &pinctrldev_list, node)
103 if (pctldev->dev->of_node == np)
104 return pctldev;
105
106 return NULL;
107}
108
109static int dt_to_map_one_config(struct pinctrl *p, const char *statename,
110 struct device_node *np_config)
111{
112 struct device_node *np_pctldev;
113 struct pinctrl_dev *pctldev;
114 struct pinctrl_ops *ops;
115 int ret;
116 struct pinctrl_map *map;
117 unsigned num_maps;
118
119 /* Find the pin controller containing np_config */
120 np_pctldev = of_node_get(np_config);
121 for (;;) {
122 np_pctldev = of_get_next_parent(np_pctldev);
123 if (!np_pctldev || of_node_is_root(np_pctldev)) {
124 dev_info(p->dev, "could not find pctldev for node %s, deferring probe\n",
125 np_config->full_name);
126 of_node_put(np_pctldev);
127 /* OK let's just assume this will appear later then */
128 return -EPROBE_DEFER;
129 }
130 pctldev = find_pinctrl_by_of_node(np_pctldev);
131 if (pctldev)
132 break;
133 }
134 of_node_put(np_pctldev);
135
136 /*
137 * Call pinctrl driver to parse device tree node, and
138 * generate mapping table entries
139 */
140 ops = pctldev->desc->pctlops;
141 if (!ops->dt_node_to_map) {
142 dev_err(p->dev, "pctldev %s doesn't support DT\n",
143 dev_name(pctldev->dev));
144 return -ENODEV;
145 }
146 ret = ops->dt_node_to_map(pctldev, np_config, &map, &num_maps);
147 if (ret < 0)
148 return ret;
149
150 /* Stash the mapping table chunk away for later use */
151 return dt_remember_or_free_map(p, statename, pctldev, map, num_maps);
152}
153
154static int dt_remember_dummy_state(struct pinctrl *p, const char *statename)
155{
156 struct pinctrl_map *map;
157
158 map = kzalloc(sizeof(*map), GFP_KERNEL);
159 if (!map) {
160 dev_err(p->dev, "failed to alloc struct pinctrl_map\n");
161 return -ENOMEM;
162 }
163
164 /* There is no pctldev for PIN_MAP_TYPE_DUMMY_STATE */
165 map->type = PIN_MAP_TYPE_DUMMY_STATE;
166
167 return dt_remember_or_free_map(p, statename, NULL, map, 1);
168}
169
170int pinctrl_dt_to_map(struct pinctrl *p)
171{
172 struct device_node *np = p->dev->of_node;
173 int state, ret;
174 char *propname;
175 struct property *prop;
176 const char *statename;
177 const __be32 *list;
178 int size, config;
179 phandle phandle;
180 struct device_node *np_config;
181
182 /* CONFIG_OF enabled, p->dev not instantiated from DT */
183 if (!np) {
184 dev_dbg(p->dev, "no of_node; not parsing pinctrl DT\n");
185 return 0;
186 }
187
188 /* We may store pointers to property names within the node */
189 of_node_get(np);
190
191 /* For each defined state ID */
192 for (state = 0; ; state++) {
193 /* Retrieve the pinctrl-* property */
194 propname = kasprintf(GFP_KERNEL, "pinctrl-%d", state);
195 prop = of_find_property(np, propname, &size);
196 kfree(propname);
197 if (!prop)
198 break;
199 list = prop->value;
200 size /= sizeof(*list);
201
202 /* Determine whether pinctrl-names property names the state */
203 ret = of_property_read_string_index(np, "pinctrl-names",
204 state, &statename);
205 /*
206 * If not, statename is just the integer state ID. But rather
207 * than dynamically allocate it and have to free it later,
208 * just point part way into the property name for the string.
209 */
210 if (ret < 0) {
211 /* strlen("pinctrl-") == 8 */
212 statename = prop->name + 8;
213 }
214
215 /* For every referenced pin configuration node in it */
216 for (config = 0; config < size; config++) {
217 phandle = be32_to_cpup(list++);
218
219 /* Look up the pin configuration node */
220 np_config = of_find_node_by_phandle(phandle);
221 if (!np_config) {
222 dev_err(p->dev,
223 "prop %s index %i invalid phandle\n",
224 prop->name, config);
225 ret = -EINVAL;
226 goto err;
227 }
228
229 /* Parse the node */
230 ret = dt_to_map_one_config(p, statename, np_config);
231 of_node_put(np_config);
232 if (ret < 0)
233 goto err;
234 }
235
236 /* No entries in DT? Generate a dummy state table entry */
237 if (!size) {
238 ret = dt_remember_dummy_state(p, statename);
239 if (ret < 0)
240 goto err;
241 }
242 }
243
244 return 0;
245
246err:
247 pinctrl_dt_free_maps(p);
248 return ret;
249}
diff --git a/drivers/pinctrl/devicetree.h b/drivers/pinctrl/devicetree.h
new file mode 100644
index 00000000000..760bc4960f5
--- /dev/null
+++ b/drivers/pinctrl/devicetree.h
@@ -0,0 +1,35 @@
1/*
2 * Internal interface to pinctrl device tree integration
3 *
4 * Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program. If not, see <http://www.gnu.org/licenses/>.
17 */
18
19#ifdef CONFIG_OF
20
21void pinctrl_dt_free_maps(struct pinctrl *p);
22int pinctrl_dt_to_map(struct pinctrl *p);
23
24#else
25
26static inline int pinctrl_dt_to_map(struct pinctrl *p)
27{
28 return 0;
29}
30
31static inline void pinctrl_dt_free_maps(struct pinctrl *p)
32{
33}
34
35#endif
diff --git a/drivers/pinctrl/pinconf.c b/drivers/pinctrl/pinconf.c
index 7321e860129..7ce139ef7e6 100644
--- a/drivers/pinctrl/pinconf.c
+++ b/drivers/pinctrl/pinconf.c
@@ -28,11 +28,17 @@ int pinconf_check_ops(struct pinctrl_dev *pctldev)
28 const struct pinconf_ops *ops = pctldev->desc->confops; 28 const struct pinconf_ops *ops = pctldev->desc->confops;
29 29
30 /* We must be able to read out pin status */ 30 /* We must be able to read out pin status */
31 if (!ops->pin_config_get && !ops->pin_config_group_get) 31 if (!ops->pin_config_get && !ops->pin_config_group_get) {
32 dev_err(pctldev->dev,
33 "pinconf must be able to read out pin status\n");
32 return -EINVAL; 34 return -EINVAL;
35 }
33 /* We have to be able to config the pins in SOME way */ 36 /* We have to be able to config the pins in SOME way */
34 if (!ops->pin_config_set && !ops->pin_config_group_set) 37 if (!ops->pin_config_set && !ops->pin_config_group_set) {
38 dev_err(pctldev->dev,
39 "pinconf has to be able to set a pins config\n");
35 return -EINVAL; 40 return -EINVAL;
41 }
36 return 0; 42 return 0;
37} 43}
38 44
@@ -379,8 +385,16 @@ int pinconf_apply_setting(struct pinctrl_setting const *setting)
379 385
380void pinconf_show_map(struct seq_file *s, struct pinctrl_map const *map) 386void pinconf_show_map(struct seq_file *s, struct pinctrl_map const *map)
381{ 387{
388 struct pinctrl_dev *pctldev;
389 const struct pinconf_ops *confops;
382 int i; 390 int i;
383 391
392 pctldev = get_pinctrl_dev_from_devname(map->ctrl_dev_name);
393 if (pctldev)
394 confops = pctldev->desc->confops;
395 else
396 confops = NULL;
397
384 switch (map->type) { 398 switch (map->type) {
385 case PIN_MAP_TYPE_CONFIGS_PIN: 399 case PIN_MAP_TYPE_CONFIGS_PIN:
386 seq_printf(s, "pin "); 400 seq_printf(s, "pin ");
@@ -394,8 +408,15 @@ void pinconf_show_map(struct seq_file *s, struct pinctrl_map const *map)
394 408
395 seq_printf(s, "%s\n", map->data.configs.group_or_pin); 409 seq_printf(s, "%s\n", map->data.configs.group_or_pin);
396 410
397 for (i = 0; i < map->data.configs.num_configs; i++) 411 for (i = 0; i < map->data.configs.num_configs; i++) {
398 seq_printf(s, "config %08lx\n", map->data.configs.configs[i]); 412 seq_printf(s, "config ");
413 if (confops && confops->pin_config_config_dbg_show)
414 confops->pin_config_config_dbg_show(pctldev, s,
415 map->data.configs.configs[i]);
416 else
417 seq_printf(s, "%08lx", map->data.configs.configs[i]);
418 seq_printf(s, "\n");
419 }
399} 420}
400 421
401void pinconf_show_setting(struct seq_file *s, 422void pinconf_show_setting(struct seq_file *s,
@@ -403,6 +424,7 @@ void pinconf_show_setting(struct seq_file *s,
403{ 424{
404 struct pinctrl_dev *pctldev = setting->pctldev; 425 struct pinctrl_dev *pctldev = setting->pctldev;
405 const struct pinctrl_ops *pctlops = pctldev->desc->pctlops; 426 const struct pinctrl_ops *pctlops = pctldev->desc->pctlops;
427 const struct pinconf_ops *confops = pctldev->desc->confops;
406 struct pin_desc *desc; 428 struct pin_desc *desc;
407 int i; 429 int i;
408 430
@@ -428,8 +450,15 @@ void pinconf_show_setting(struct seq_file *s,
428 * FIXME: We should really get the pin controler to dump the config 450 * FIXME: We should really get the pin controler to dump the config
429 * values, so they can be decoded to something meaningful. 451 * values, so they can be decoded to something meaningful.
430 */ 452 */
431 for (i = 0; i < setting->data.configs.num_configs; i++) 453 for (i = 0; i < setting->data.configs.num_configs; i++) {
432 seq_printf(s, " %08lx", setting->data.configs.configs[i]); 454 seq_printf(s, " ");
455 if (confops && confops->pin_config_config_dbg_show)
456 confops->pin_config_config_dbg_show(pctldev, s,
457 setting->data.configs.configs[i]);
458 else
459 seq_printf(s, "%08lx",
460 setting->data.configs.configs[i]);
461 }
433 462
434 seq_printf(s, "\n"); 463 seq_printf(s, "\n");
435} 464}
@@ -448,10 +477,14 @@ static void pinconf_dump_pin(struct pinctrl_dev *pctldev,
448static int pinconf_pins_show(struct seq_file *s, void *what) 477static int pinconf_pins_show(struct seq_file *s, void *what)
449{ 478{
450 struct pinctrl_dev *pctldev = s->private; 479 struct pinctrl_dev *pctldev = s->private;
480 const struct pinconf_ops *ops = pctldev->desc->confops;
451 unsigned i, pin; 481 unsigned i, pin;
452 482
483 if (!ops || !ops->pin_config_get)
484 return 0;
485
453 seq_puts(s, "Pin config settings per pin\n"); 486 seq_puts(s, "Pin config settings per pin\n");
454 seq_puts(s, "Format: pin (name): pinmux setting array\n"); 487 seq_puts(s, "Format: pin (name): configs\n");
455 488
456 mutex_lock(&pinctrl_mutex); 489 mutex_lock(&pinctrl_mutex);
457 490
@@ -495,17 +528,18 @@ static int pinconf_groups_show(struct seq_file *s, void *what)
495 struct pinctrl_dev *pctldev = s->private; 528 struct pinctrl_dev *pctldev = s->private;
496 const struct pinctrl_ops *pctlops = pctldev->desc->pctlops; 529 const struct pinctrl_ops *pctlops = pctldev->desc->pctlops;
497 const struct pinconf_ops *ops = pctldev->desc->confops; 530 const struct pinconf_ops *ops = pctldev->desc->confops;
531 unsigned ngroups = pctlops->get_groups_count(pctldev);
498 unsigned selector = 0; 532 unsigned selector = 0;
499 533
500 if (!ops || !ops->pin_config_group_get) 534 if (!ops || !ops->pin_config_group_get)
501 return 0; 535 return 0;
502 536
503 seq_puts(s, "Pin config settings per pin group\n"); 537 seq_puts(s, "Pin config settings per pin group\n");
504 seq_puts(s, "Format: group (name): pinmux setting array\n"); 538 seq_puts(s, "Format: group (name): configs\n");
505 539
506 mutex_lock(&pinctrl_mutex); 540 mutex_lock(&pinctrl_mutex);
507 541
508 while (pctlops->list_groups(pctldev, selector) >= 0) { 542 while (selector < ngroups) {
509 const char *gname = pctlops->get_group_name(pctldev, selector); 543 const char *gname = pctlops->get_group_name(pctldev, selector);
510 544
511 seq_printf(s, "%u (%s):", selector, gname); 545 seq_printf(s, "%u (%s):", selector, gname);
diff --git a/drivers/pinctrl/pinconf.h b/drivers/pinctrl/pinconf.h
index 54510de5e8c..e3ed8cb072a 100644
--- a/drivers/pinctrl/pinconf.h
+++ b/drivers/pinctrl/pinconf.h
@@ -19,11 +19,6 @@ int pinconf_map_to_setting(struct pinctrl_map const *map,
19 struct pinctrl_setting *setting); 19 struct pinctrl_setting *setting);
20void pinconf_free_setting(struct pinctrl_setting const *setting); 20void pinconf_free_setting(struct pinctrl_setting const *setting);
21int pinconf_apply_setting(struct pinctrl_setting const *setting); 21int pinconf_apply_setting(struct pinctrl_setting const *setting);
22void pinconf_show_map(struct seq_file *s, struct pinctrl_map const *map);
23void pinconf_show_setting(struct seq_file *s,
24 struct pinctrl_setting const *setting);
25void pinconf_init_device_debugfs(struct dentry *devroot,
26 struct pinctrl_dev *pctldev);
27 22
28/* 23/*
29 * You will only be interested in these if you're using PINCONF 24 * You will only be interested in these if you're using PINCONF
@@ -61,6 +56,18 @@ static inline int pinconf_apply_setting(struct pinctrl_setting const *setting)
61 return 0; 56 return 0;
62} 57}
63 58
59#endif
60
61#if defined(CONFIG_PINCONF) && defined(CONFIG_DEBUG_FS)
62
63void pinconf_show_map(struct seq_file *s, struct pinctrl_map const *map);
64void pinconf_show_setting(struct seq_file *s,
65 struct pinctrl_setting const *setting);
66void pinconf_init_device_debugfs(struct dentry *devroot,
67 struct pinctrl_dev *pctldev);
68
69#else
70
64static inline void pinconf_show_map(struct seq_file *s, 71static inline void pinconf_show_map(struct seq_file *s,
65 struct pinctrl_map const *map) 72 struct pinctrl_map const *map)
66{ 73{
diff --git a/drivers/pinctrl/pinctrl-coh901.c b/drivers/pinctrl/pinctrl-coh901.c
index 0797eba3e33..55697a5d748 100644
--- a/drivers/pinctrl/pinctrl-coh901.c
+++ b/drivers/pinctrl/pinctrl-coh901.c
@@ -174,7 +174,7 @@ struct u300_gpio_confdata {
174 174
175 175
176/* Initial configuration */ 176/* Initial configuration */
177static const struct __initdata u300_gpio_confdata 177static const struct __initconst u300_gpio_confdata
178bs335_gpio_config[BS335_GPIO_NUM_PORTS][U300_GPIO_PINS_PER_PORT] = { 178bs335_gpio_config[BS335_GPIO_NUM_PORTS][U300_GPIO_PINS_PER_PORT] = {
179 /* Port 0, pins 0-7 */ 179 /* Port 0, pins 0-7 */
180 { 180 {
@@ -255,7 +255,7 @@ bs335_gpio_config[BS335_GPIO_NUM_PORTS][U300_GPIO_PINS_PER_PORT] = {
255 } 255 }
256}; 256};
257 257
258static const struct __initdata u300_gpio_confdata 258static const struct __initconst u300_gpio_confdata
259bs365_gpio_config[BS365_GPIO_NUM_PORTS][U300_GPIO_PINS_PER_PORT] = { 259bs365_gpio_config[BS365_GPIO_NUM_PORTS][U300_GPIO_PINS_PER_PORT] = {
260 /* Port 0, pins 0-7 */ 260 /* Port 0, pins 0-7 */
261 { 261 {
diff --git a/drivers/pinctrl/pinctrl-imx.c b/drivers/pinctrl/pinctrl-imx.c
new file mode 100644
index 00000000000..8faf613ff1b
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-imx.c
@@ -0,0 +1,627 @@
1/*
2 * Core driver for the imx pin controller
3 *
4 * Copyright (C) 2012 Freescale Semiconductor, Inc.
5 * Copyright (C) 2012 Linaro Ltd.
6 *
7 * Author: Dong Aisheng <dong.aisheng@linaro.org>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 */
14
15#include <linux/err.h>
16#include <linux/init.h>
17#include <linux/io.h>
18#include <linux/module.h>
19#include <linux/of.h>
20#include <linux/of_device.h>
21#include <linux/pinctrl/machine.h>
22#include <linux/pinctrl/pinconf.h>
23#include <linux/pinctrl/pinctrl.h>
24#include <linux/pinctrl/pinmux.h>
25#include <linux/slab.h>
26
27#include "core.h"
28#include "pinctrl-imx.h"
29
30#define IMX_PMX_DUMP(info, p, m, c, n) \
31{ \
32 int i, j; \
33 printk("Format: Pin Mux Config\n"); \
34 for (i = 0; i < n; i++) { \
35 j = p[i]; \
36 printk("%s %d 0x%lx\n", \
37 info->pins[j].name, \
38 m[i], c[i]); \
39 } \
40}
41
42/* The bits in CONFIG cell defined in binding doc*/
43#define IMX_NO_PAD_CTL 0x80000000 /* no pin config need */
44#define IMX_PAD_SION 0x40000000 /* set SION */
45
46/**
47 * @dev: a pointer back to containing device
48 * @base: the offset to the controller in virtual memory
49 */
50struct imx_pinctrl {
51 struct device *dev;
52 struct pinctrl_dev *pctl;
53 void __iomem *base;
54 const struct imx_pinctrl_soc_info *info;
55};
56
57static const struct imx_pin_reg *imx_find_pin_reg(
58 const struct imx_pinctrl_soc_info *info,
59 unsigned pin, bool is_mux, unsigned mux)
60{
61 const struct imx_pin_reg *pin_reg = NULL;
62 int i;
63
64 for (i = 0; i < info->npin_regs; i++) {
65 pin_reg = &info->pin_regs[i];
66 if (pin_reg->pid != pin)
67 continue;
68 if (!is_mux)
69 break;
70 else if (pin_reg->mux_mode == (mux & IMX_MUX_MASK))
71 break;
72 }
73
74 if (!pin_reg) {
75 dev_err(info->dev, "Pin(%s): unable to find pin reg map\n",
76 info->pins[pin].name);
77 return NULL;
78 }
79
80 return pin_reg;
81}
82
83static const inline struct imx_pin_group *imx_pinctrl_find_group_by_name(
84 const struct imx_pinctrl_soc_info *info,
85 const char *name)
86{
87 const struct imx_pin_group *grp = NULL;
88 int i;
89
90 for (i = 0; i < info->ngroups; i++) {
91 if (!strcmp(info->groups[i].name, name)) {
92 grp = &info->groups[i];
93 break;
94 }
95 }
96
97 return grp;
98}
99
100static int imx_get_groups_count(struct pinctrl_dev *pctldev)
101{
102 struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
103 const struct imx_pinctrl_soc_info *info = ipctl->info;
104
105 return info->ngroups;
106}
107
108static const char *imx_get_group_name(struct pinctrl_dev *pctldev,
109 unsigned selector)
110{
111 struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
112 const struct imx_pinctrl_soc_info *info = ipctl->info;
113
114 return info->groups[selector].name;
115}
116
117static int imx_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
118 const unsigned **pins,
119 unsigned *npins)
120{
121 struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
122 const struct imx_pinctrl_soc_info *info = ipctl->info;
123
124 if (selector >= info->ngroups)
125 return -EINVAL;
126
127 *pins = info->groups[selector].pins;
128 *npins = info->groups[selector].npins;
129
130 return 0;
131}
132
133static void imx_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
134 unsigned offset)
135{
136 seq_printf(s, "%s", dev_name(pctldev->dev));
137}
138
139static int imx_dt_node_to_map(struct pinctrl_dev *pctldev,
140 struct device_node *np,
141 struct pinctrl_map **map, unsigned *num_maps)
142{
143 struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
144 const struct imx_pinctrl_soc_info *info = ipctl->info;
145 const struct imx_pin_group *grp;
146 struct pinctrl_map *new_map;
147 struct device_node *parent;
148 int map_num = 1;
149 int i;
150
151 /*
152 * first find the group of this node and check if we need create
153 * config maps for pins
154 */
155 grp = imx_pinctrl_find_group_by_name(info, np->name);
156 if (!grp) {
157 dev_err(info->dev, "unable to find group for node %s\n",
158 np->name);
159 return -EINVAL;
160 }
161
162 for (i = 0; i < grp->npins; i++) {
163 if (!(grp->configs[i] & IMX_NO_PAD_CTL))
164 map_num++;
165 }
166
167 new_map = kmalloc(sizeof(struct pinctrl_map) * map_num, GFP_KERNEL);
168 if (!new_map)
169 return -ENOMEM;
170
171 *map = new_map;
172 *num_maps = map_num;
173
174 /* create mux map */
175 parent = of_get_parent(np);
176 if (!parent)
177 return -EINVAL;
178 new_map[0].type = PIN_MAP_TYPE_MUX_GROUP;
179 new_map[0].data.mux.function = parent->name;
180 new_map[0].data.mux.group = np->name;
181 of_node_put(parent);
182
183 /* create config map */
184 new_map++;
185 for (i = 0; i < grp->npins; i++) {
186 if (!(grp->configs[i] & IMX_NO_PAD_CTL)) {
187 new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN;
188 new_map[i].data.configs.group_or_pin =
189 pin_get_name(pctldev, grp->pins[i]);
190 new_map[i].data.configs.configs = &grp->configs[i];
191 new_map[i].data.configs.num_configs = 1;
192 }
193 }
194
195 dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n",
196 new_map->data.mux.function, new_map->data.mux.group, map_num);
197
198 return 0;
199}
200
201static void imx_dt_free_map(struct pinctrl_dev *pctldev,
202 struct pinctrl_map *map, unsigned num_maps)
203{
204 int i;
205
206 for (i = 0; i < num_maps; i++)
207 kfree(map);
208}
209
210static struct pinctrl_ops imx_pctrl_ops = {
211 .get_groups_count = imx_get_groups_count,
212 .get_group_name = imx_get_group_name,
213 .get_group_pins = imx_get_group_pins,
214 .pin_dbg_show = imx_pin_dbg_show,
215 .dt_node_to_map = imx_dt_node_to_map,
216 .dt_free_map = imx_dt_free_map,
217
218};
219
220static int imx_pmx_enable(struct pinctrl_dev *pctldev, unsigned selector,
221 unsigned group)
222{
223 struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
224 const struct imx_pinctrl_soc_info *info = ipctl->info;
225 const struct imx_pin_reg *pin_reg;
226 const unsigned *pins, *mux;
227 unsigned int npins, pin_id;
228 int i;
229
230 /*
231 * Configure the mux mode for each pin in the group for a specific
232 * function.
233 */
234 pins = info->groups[group].pins;
235 npins = info->groups[group].npins;
236 mux = info->groups[group].mux_mode;
237
238 WARN_ON(!pins || !npins || !mux);
239
240 dev_dbg(ipctl->dev, "enable function %s group %s\n",
241 info->functions[selector].name, info->groups[group].name);
242
243 for (i = 0; i < npins; i++) {
244 pin_id = pins[i];
245
246 pin_reg = imx_find_pin_reg(info, pin_id, 1, mux[i]);
247 if (!pin_reg)
248 return -EINVAL;
249
250 if (!pin_reg->mux_reg) {
251 dev_err(ipctl->dev, "Pin(%s) does not support mux function\n",
252 info->pins[pin_id].name);
253 return -EINVAL;
254 }
255
256 writel(mux[i], ipctl->base + pin_reg->mux_reg);
257 dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%x\n",
258 pin_reg->mux_reg, mux[i]);
259
260 /* some pins also need select input setting, set it if found */
261 if (pin_reg->input_reg) {
262 writel(pin_reg->input_val, ipctl->base + pin_reg->input_reg);
263 dev_dbg(ipctl->dev,
264 "==>select_input: offset 0x%x val 0x%x\n",
265 pin_reg->input_reg, pin_reg->input_val);
266 }
267 }
268
269 return 0;
270}
271
272static void imx_pmx_disable(struct pinctrl_dev *pctldev, unsigned func_selector,
273 unsigned group_selector)
274{
275 /* nothing to do here */
276}
277
278static int imx_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
279{
280 struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
281 const struct imx_pinctrl_soc_info *info = ipctl->info;
282
283 return info->nfunctions;
284}
285
286static const char *imx_pmx_get_func_name(struct pinctrl_dev *pctldev,
287 unsigned selector)
288{
289 struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
290 const struct imx_pinctrl_soc_info *info = ipctl->info;
291
292 return info->functions[selector].name;
293}
294
295static int imx_pmx_get_groups(struct pinctrl_dev *pctldev, unsigned selector,
296 const char * const **groups,
297 unsigned * const num_groups)
298{
299 struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
300 const struct imx_pinctrl_soc_info *info = ipctl->info;
301
302 *groups = info->functions[selector].groups;
303 *num_groups = info->functions[selector].num_groups;
304
305 return 0;
306}
307
308static struct pinmux_ops imx_pmx_ops = {
309 .get_functions_count = imx_pmx_get_funcs_count,
310 .get_function_name = imx_pmx_get_func_name,
311 .get_function_groups = imx_pmx_get_groups,
312 .enable = imx_pmx_enable,
313 .disable = imx_pmx_disable,
314};
315
316static int imx_pinconf_get(struct pinctrl_dev *pctldev,
317 unsigned pin_id, unsigned long *config)
318{
319 struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
320 const struct imx_pinctrl_soc_info *info = ipctl->info;
321 const struct imx_pin_reg *pin_reg;
322
323 pin_reg = imx_find_pin_reg(info, pin_id, 0, 0);
324 if (!pin_reg)
325 return -EINVAL;
326
327 if (!pin_reg->conf_reg) {
328 dev_err(info->dev, "Pin(%s) does not support config function\n",
329 info->pins[pin_id].name);
330 return -EINVAL;
331 }
332
333 *config = readl(ipctl->base + pin_reg->conf_reg);
334
335 return 0;
336}
337
338static int imx_pinconf_set(struct pinctrl_dev *pctldev,
339 unsigned pin_id, unsigned long config)
340{
341 struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
342 const struct imx_pinctrl_soc_info *info = ipctl->info;
343 const struct imx_pin_reg *pin_reg;
344
345 pin_reg = imx_find_pin_reg(info, pin_id, 0, 0);
346 if (!pin_reg)
347 return -EINVAL;
348
349 if (!pin_reg->conf_reg) {
350 dev_err(info->dev, "Pin(%s) does not support config function\n",
351 info->pins[pin_id].name);
352 return -EINVAL;
353 }
354
355 dev_dbg(ipctl->dev, "pinconf set pin %s\n",
356 info->pins[pin_id].name);
357
358 writel(config, ipctl->base + pin_reg->conf_reg);
359 dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%lx\n",
360 pin_reg->conf_reg, config);
361
362 return 0;
363}
364
365static void imx_pinconf_dbg_show(struct pinctrl_dev *pctldev,
366 struct seq_file *s, unsigned pin_id)
367{
368 struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
369 const struct imx_pinctrl_soc_info *info = ipctl->info;
370 const struct imx_pin_reg *pin_reg;
371 unsigned long config;
372
373 pin_reg = imx_find_pin_reg(info, pin_id, 0, 0);
374 if (!pin_reg || !pin_reg->conf_reg) {
375 seq_printf(s, "N/A");
376 return;
377 }
378
379 config = readl(ipctl->base + pin_reg->conf_reg);
380 seq_printf(s, "0x%lx", config);
381}
382
383static void imx_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
384 struct seq_file *s, unsigned group)
385{
386 struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
387 const struct imx_pinctrl_soc_info *info = ipctl->info;
388 struct imx_pin_group *grp;
389 unsigned long config;
390 const char *name;
391 int i, ret;
392
393 if (group > info->ngroups)
394 return;
395
396 seq_printf(s, "\n");
397 grp = &info->groups[group];
398 for (i = 0; i < grp->npins; i++) {
399 name = pin_get_name(pctldev, grp->pins[i]);
400 ret = imx_pinconf_get(pctldev, grp->pins[i], &config);
401 if (ret)
402 return;
403 seq_printf(s, "%s: 0x%lx", name, config);
404 }
405}
406
407struct pinconf_ops imx_pinconf_ops = {
408 .pin_config_get = imx_pinconf_get,
409 .pin_config_set = imx_pinconf_set,
410 .pin_config_dbg_show = imx_pinconf_dbg_show,
411 .pin_config_group_dbg_show = imx_pinconf_group_dbg_show,
412};
413
414static struct pinctrl_desc imx_pinctrl_desc = {
415 .pctlops = &imx_pctrl_ops,
416 .pmxops = &imx_pmx_ops,
417 .confops = &imx_pinconf_ops,
418 .owner = THIS_MODULE,
419};
420
421/* decode pin id and mux from pin function id got from device tree*/
422static int imx_pinctrl_get_pin_id_and_mux(const struct imx_pinctrl_soc_info *info,
423 unsigned int pin_func_id, unsigned int *pin_id,
424 unsigned int *mux)
425{
426 if (pin_func_id > info->npin_regs)
427 return -EINVAL;
428
429 *pin_id = info->pin_regs[pin_func_id].pid;
430 *mux = info->pin_regs[pin_func_id].mux_mode;
431
432 return 0;
433}
434
435static int __devinit imx_pinctrl_parse_groups(struct device_node *np,
436 struct imx_pin_group *grp,
437 struct imx_pinctrl_soc_info *info,
438 u32 index)
439{
440 unsigned int pin_func_id;
441 int ret, size;
442 const const __be32 *list;
443 int i, j;
444 u32 config;
445
446 dev_dbg(info->dev, "group(%d): %s\n", index, np->name);
447
448 /* Initialise group */
449 grp->name = np->name;
450
451 /*
452 * the binding format is fsl,pins = <PIN_FUNC_ID CONFIG ...>,
453 * do sanity check and calculate pins number
454 */
455 list = of_get_property(np, "fsl,pins", &size);
456 /* we do not check return since it's safe node passed down */
457 size /= sizeof(*list);
458 if (!size || size % 2) {
459 dev_err(info->dev, "wrong pins number or pins and configs should be pairs\n");
460 return -EINVAL;
461 }
462
463 grp->npins = size / 2;
464 grp->pins = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned int),
465 GFP_KERNEL);
466 grp->mux_mode = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned int),
467 GFP_KERNEL);
468 grp->configs = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned long),
469 GFP_KERNEL);
470 for (i = 0, j = 0; i < size; i += 2, j++) {
471 pin_func_id = be32_to_cpu(*list++);
472 ret = imx_pinctrl_get_pin_id_and_mux(info, pin_func_id,
473 &grp->pins[j], &grp->mux_mode[j]);
474 if (ret) {
475 dev_err(info->dev, "get invalid pin function id\n");
476 return -EINVAL;
477 }
478 /* SION bit is in mux register */
479 config = be32_to_cpu(*list++);
480 if (config & IMX_PAD_SION)
481 grp->mux_mode[j] |= IOMUXC_CONFIG_SION;
482 grp->configs[j] = config & ~IMX_PAD_SION;
483 }
484
485#ifdef DEBUG
486 IMX_PMX_DUMP(info, grp->pins, grp->mux_mode, grp->configs, grp->npins);
487#endif
488 return 0;
489}
490
491static int __devinit imx_pinctrl_parse_functions(struct device_node *np,
492 struct imx_pinctrl_soc_info *info, u32 index)
493{
494 struct device_node *child;
495 struct imx_pmx_func *func;
496 struct imx_pin_group *grp;
497 int ret;
498 static u32 grp_index;
499 u32 i = 0;
500
501 dev_dbg(info->dev, "parse function(%d): %s\n", index, np->name);
502
503 func = &info->functions[index];
504
505 /* Initialise function */
506 func->name = np->name;
507 func->num_groups = of_get_child_count(np);
508 if (func->num_groups <= 0) {
509 dev_err(info->dev, "no groups defined\n");
510 return -EINVAL;
511 }
512 func->groups = devm_kzalloc(info->dev,
513 func->num_groups * sizeof(char *), GFP_KERNEL);
514
515 for_each_child_of_node(np, child) {
516 func->groups[i] = child->name;
517 grp = &info->groups[grp_index++];
518 ret = imx_pinctrl_parse_groups(child, grp, info, i++);
519 if (ret)
520 return ret;
521 }
522
523 return 0;
524}
525
526static int __devinit imx_pinctrl_probe_dt(struct platform_device *pdev,
527 struct imx_pinctrl_soc_info *info)
528{
529 struct device_node *np = pdev->dev.of_node;
530 struct device_node *child;
531 int ret;
532 u32 nfuncs = 0;
533 u32 i = 0;
534
535 if (!np)
536 return -ENODEV;
537
538 nfuncs = of_get_child_count(np);
539 if (nfuncs <= 0) {
540 dev_err(&pdev->dev, "no functions defined\n");
541 return -EINVAL;
542 }
543
544 info->nfunctions = nfuncs;
545 info->functions = devm_kzalloc(&pdev->dev, nfuncs * sizeof(struct imx_pmx_func),
546 GFP_KERNEL);
547 if (!info->functions)
548 return -ENOMEM;
549
550 info->ngroups = 0;
551 for_each_child_of_node(np, child)
552 info->ngroups += of_get_child_count(child);
553 info->groups = devm_kzalloc(&pdev->dev, info->ngroups * sizeof(struct imx_pin_group),
554 GFP_KERNEL);
555 if (!info->groups)
556 return -ENOMEM;
557
558 for_each_child_of_node(np, child) {
559 ret = imx_pinctrl_parse_functions(child, info, i++);
560 if (ret) {
561 dev_err(&pdev->dev, "failed to parse function\n");
562 return ret;
563 }
564 }
565
566 return 0;
567}
568
569int __devinit imx_pinctrl_probe(struct platform_device *pdev,
570 struct imx_pinctrl_soc_info *info)
571{
572 struct imx_pinctrl *ipctl;
573 struct resource *res;
574 int ret;
575
576 if (!info || !info->pins || !info->npins
577 || !info->pin_regs || !info->npin_regs) {
578 dev_err(&pdev->dev, "wrong pinctrl info\n");
579 return -EINVAL;
580 }
581 info->dev = &pdev->dev;
582
583 /* Create state holders etc for this driver */
584 ipctl = devm_kzalloc(&pdev->dev, sizeof(*ipctl), GFP_KERNEL);
585 if (!ipctl)
586 return -ENOMEM;
587
588 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
589 if (!res)
590 return -ENOENT;
591
592 ipctl->base = devm_request_and_ioremap(&pdev->dev, res);
593 if (!ipctl->base)
594 return -EBUSY;
595
596 imx_pinctrl_desc.name = dev_name(&pdev->dev);
597 imx_pinctrl_desc.pins = info->pins;
598 imx_pinctrl_desc.npins = info->npins;
599
600 ret = imx_pinctrl_probe_dt(pdev, info);
601 if (ret) {
602 dev_err(&pdev->dev, "fail to probe dt properties\n");
603 return ret;
604 }
605
606 ipctl->info = info;
607 ipctl->dev = info->dev;
608 platform_set_drvdata(pdev, ipctl);
609 ipctl->pctl = pinctrl_register(&imx_pinctrl_desc, &pdev->dev, ipctl);
610 if (!ipctl->pctl) {
611 dev_err(&pdev->dev, "could not register IMX pinctrl driver\n");
612 return -EINVAL;
613 }
614
615 dev_info(&pdev->dev, "initialized IMX pinctrl driver\n");
616
617 return 0;
618}
619
620int __devexit imx_pinctrl_remove(struct platform_device *pdev)
621{
622 struct imx_pinctrl *ipctl = platform_get_drvdata(pdev);
623
624 pinctrl_unregister(ipctl->pctl);
625
626 return 0;
627}
diff --git a/drivers/pinctrl/pinctrl-imx.h b/drivers/pinctrl/pinctrl-imx.h
new file mode 100644
index 00000000000..9b65e7828f1
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-imx.h
@@ -0,0 +1,106 @@
1/*
2 * IMX pinmux core definitions
3 *
4 * Copyright (C) 2012 Freescale Semiconductor, Inc.
5 * Copyright (C) 2012 Linaro Ltd.
6 *
7 * Author: Dong Aisheng <dong.aisheng@linaro.org>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 */
14
15#ifndef __DRIVERS_PINCTRL_IMX_H
16#define __DRIVERS_PINCTRL_IMX_H
17
18struct platform_device;
19
20/**
21 * struct imx_pin_group - describes an IMX pin group
22 * @name: the name of this specific pin group
23 * @pins: an array of discrete physical pins used in this group, taken
24 * from the driver-local pin enumeration space
25 * @npins: the number of pins in this group array, i.e. the number of
26 * elements in .pins so we can iterate over that array
27 * @mux_mode: the mux mode for each pin in this group. The size of this
28 * array is the same as pins.
29 * @configs: the config for each pin in this group. The size of this
30 * array is the same as pins.
31 */
32struct imx_pin_group {
33 const char *name;
34 unsigned int *pins;
35 unsigned npins;
36 unsigned int *mux_mode;
37 unsigned long *configs;
38};
39
40/**
41 * struct imx_pmx_func - describes IMX pinmux functions
42 * @name: the name of this specific function
43 * @groups: corresponding pin groups
44 * @num_groups: the number of groups
45 */
46struct imx_pmx_func {
47 const char *name;
48 const char **groups;
49 unsigned num_groups;
50};
51
52/**
53 * struct imx_pin_reg - describe a pin reg map
54 * The last 3 members are used for select input setting
55 * @pid: pin id
56 * @mux_reg: mux register offset
57 * @conf_reg: config register offset
58 * @mux_mode: mux mode
59 * @input_reg: select input register offset for this mux if any
60 * 0 if no select input setting needed.
61 * @input_val: the value set to select input register
62 */
63struct imx_pin_reg {
64 u16 pid;
65 u16 mux_reg;
66 u16 conf_reg;
67 u8 mux_mode;
68 u16 input_reg;
69 u8 input_val;
70};
71
72struct imx_pinctrl_soc_info {
73 struct device *dev;
74 const struct pinctrl_pin_desc *pins;
75 unsigned int npins;
76 const struct imx_pin_reg *pin_regs;
77 unsigned int npin_regs;
78 struct imx_pin_group *groups;
79 unsigned int ngroups;
80 struct imx_pmx_func *functions;
81 unsigned int nfunctions;
82};
83
84#define NO_MUX 0x0
85#define NO_PAD 0x0
86
87#define IMX_PIN_REG(id, conf, mux, mode, input, val) \
88 { \
89 .pid = id, \
90 .conf_reg = conf, \
91 .mux_reg = mux, \
92 .mux_mode = mode, \
93 .input_reg = input, \
94 .input_val = val, \
95 }
96
97#define IMX_PINCTRL_PIN(pin) PINCTRL_PIN(pin, #pin)
98
99#define PAD_CTL_MASK(len) ((1 << len) - 1)
100#define IMX_MUX_MASK 0x7
101#define IOMUXC_CONFIG_SION (0x1 << 4)
102
103int imx_pinctrl_probe(struct platform_device *pdev,
104 struct imx_pinctrl_soc_info *info);
105int imx_pinctrl_remove(struct platform_device *pdev);
106#endif /* __DRIVERS_PINCTRL_IMX_H */
diff --git a/drivers/pinctrl/pinctrl-imx23.c b/drivers/pinctrl/pinctrl-imx23.c
new file mode 100644
index 00000000000..75d3eff9429
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-imx23.c
@@ -0,0 +1,305 @@
1/*
2 * Copyright 2012 Freescale Semiconductor, Inc.
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12#include <linux/init.h>
13#include <linux/module.h>
14#include <linux/of_device.h>
15#include <linux/pinctrl/pinctrl.h>
16#include "pinctrl-mxs.h"
17
18enum imx23_pin_enum {
19 GPMI_D00 = PINID(0, 0),
20 GPMI_D01 = PINID(0, 1),
21 GPMI_D02 = PINID(0, 2),
22 GPMI_D03 = PINID(0, 3),
23 GPMI_D04 = PINID(0, 4),
24 GPMI_D05 = PINID(0, 5),
25 GPMI_D06 = PINID(0, 6),
26 GPMI_D07 = PINID(0, 7),
27 GPMI_D08 = PINID(0, 8),
28 GPMI_D09 = PINID(0, 9),
29 GPMI_D10 = PINID(0, 10),
30 GPMI_D11 = PINID(0, 11),
31 GPMI_D12 = PINID(0, 12),
32 GPMI_D13 = PINID(0, 13),
33 GPMI_D14 = PINID(0, 14),
34 GPMI_D15 = PINID(0, 15),
35 GPMI_CLE = PINID(0, 16),
36 GPMI_ALE = PINID(0, 17),
37 GPMI_CE2N = PINID(0, 18),
38 GPMI_RDY0 = PINID(0, 19),
39 GPMI_RDY1 = PINID(0, 20),
40 GPMI_RDY2 = PINID(0, 21),
41 GPMI_RDY3 = PINID(0, 22),
42 GPMI_WPN = PINID(0, 23),
43 GPMI_WRN = PINID(0, 24),
44 GPMI_RDN = PINID(0, 25),
45 AUART1_CTS = PINID(0, 26),
46 AUART1_RTS = PINID(0, 27),
47 AUART1_RX = PINID(0, 28),
48 AUART1_TX = PINID(0, 29),
49 I2C_SCL = PINID(0, 30),
50 I2C_SDA = PINID(0, 31),
51 LCD_D00 = PINID(1, 0),
52 LCD_D01 = PINID(1, 1),
53 LCD_D02 = PINID(1, 2),
54 LCD_D03 = PINID(1, 3),
55 LCD_D04 = PINID(1, 4),
56 LCD_D05 = PINID(1, 5),
57 LCD_D06 = PINID(1, 6),
58 LCD_D07 = PINID(1, 7),
59 LCD_D08 = PINID(1, 8),
60 LCD_D09 = PINID(1, 9),
61 LCD_D10 = PINID(1, 10),
62 LCD_D11 = PINID(1, 11),
63 LCD_D12 = PINID(1, 12),
64 LCD_D13 = PINID(1, 13),
65 LCD_D14 = PINID(1, 14),
66 LCD_D15 = PINID(1, 15),
67 LCD_D16 = PINID(1, 16),
68 LCD_D17 = PINID(1, 17),
69 LCD_RESET = PINID(1, 18),
70 LCD_RS = PINID(1, 19),
71 LCD_WR = PINID(1, 20),
72 LCD_CS = PINID(1, 21),
73 LCD_DOTCK = PINID(1, 22),
74 LCD_ENABLE = PINID(1, 23),
75 LCD_HSYNC = PINID(1, 24),
76 LCD_VSYNC = PINID(1, 25),
77 PWM0 = PINID(1, 26),
78 PWM1 = PINID(1, 27),
79 PWM2 = PINID(1, 28),
80 PWM3 = PINID(1, 29),
81 PWM4 = PINID(1, 30),
82 SSP1_CMD = PINID(2, 0),
83 SSP1_DETECT = PINID(2, 1),
84 SSP1_DATA0 = PINID(2, 2),
85 SSP1_DATA1 = PINID(2, 3),
86 SSP1_DATA2 = PINID(2, 4),
87 SSP1_DATA3 = PINID(2, 5),
88 SSP1_SCK = PINID(2, 6),
89 ROTARYA = PINID(2, 7),
90 ROTARYB = PINID(2, 8),
91 EMI_A00 = PINID(2, 9),
92 EMI_A01 = PINID(2, 10),
93 EMI_A02 = PINID(2, 11),
94 EMI_A03 = PINID(2, 12),
95 EMI_A04 = PINID(2, 13),
96 EMI_A05 = PINID(2, 14),
97 EMI_A06 = PINID(2, 15),
98 EMI_A07 = PINID(2, 16),
99 EMI_A08 = PINID(2, 17),
100 EMI_A09 = PINID(2, 18),
101 EMI_A10 = PINID(2, 19),
102 EMI_A11 = PINID(2, 20),
103 EMI_A12 = PINID(2, 21),
104 EMI_BA0 = PINID(2, 22),
105 EMI_BA1 = PINID(2, 23),
106 EMI_CASN = PINID(2, 24),
107 EMI_CE0N = PINID(2, 25),
108 EMI_CE1N = PINID(2, 26),
109 GPMI_CE1N = PINID(2, 27),
110 GPMI_CE0N = PINID(2, 28),
111 EMI_CKE = PINID(2, 29),
112 EMI_RASN = PINID(2, 30),
113 EMI_WEN = PINID(2, 31),
114 EMI_D00 = PINID(3, 0),
115 EMI_D01 = PINID(3, 1),
116 EMI_D02 = PINID(3, 2),
117 EMI_D03 = PINID(3, 3),
118 EMI_D04 = PINID(3, 4),
119 EMI_D05 = PINID(3, 5),
120 EMI_D06 = PINID(3, 6),
121 EMI_D07 = PINID(3, 7),
122 EMI_D08 = PINID(3, 8),
123 EMI_D09 = PINID(3, 9),
124 EMI_D10 = PINID(3, 10),
125 EMI_D11 = PINID(3, 11),
126 EMI_D12 = PINID(3, 12),
127 EMI_D13 = PINID(3, 13),
128 EMI_D14 = PINID(3, 14),
129 EMI_D15 = PINID(3, 15),
130 EMI_DQM0 = PINID(3, 16),
131 EMI_DQM1 = PINID(3, 17),
132 EMI_DQS0 = PINID(3, 18),
133 EMI_DQS1 = PINID(3, 19),
134 EMI_CLK = PINID(3, 20),
135 EMI_CLKN = PINID(3, 21),
136};
137
138static const struct pinctrl_pin_desc imx23_pins[] = {
139 MXS_PINCTRL_PIN(GPMI_D00),
140 MXS_PINCTRL_PIN(GPMI_D01),
141 MXS_PINCTRL_PIN(GPMI_D02),
142 MXS_PINCTRL_PIN(GPMI_D03),
143 MXS_PINCTRL_PIN(GPMI_D04),
144 MXS_PINCTRL_PIN(GPMI_D05),
145 MXS_PINCTRL_PIN(GPMI_D06),
146 MXS_PINCTRL_PIN(GPMI_D07),
147 MXS_PINCTRL_PIN(GPMI_D08),
148 MXS_PINCTRL_PIN(GPMI_D09),
149 MXS_PINCTRL_PIN(GPMI_D10),
150 MXS_PINCTRL_PIN(GPMI_D11),
151 MXS_PINCTRL_PIN(GPMI_D12),
152 MXS_PINCTRL_PIN(GPMI_D13),
153 MXS_PINCTRL_PIN(GPMI_D14),
154 MXS_PINCTRL_PIN(GPMI_D15),
155 MXS_PINCTRL_PIN(GPMI_CLE),
156 MXS_PINCTRL_PIN(GPMI_ALE),
157 MXS_PINCTRL_PIN(GPMI_CE2N),
158 MXS_PINCTRL_PIN(GPMI_RDY0),
159 MXS_PINCTRL_PIN(GPMI_RDY1),
160 MXS_PINCTRL_PIN(GPMI_RDY2),
161 MXS_PINCTRL_PIN(GPMI_RDY3),
162 MXS_PINCTRL_PIN(GPMI_WPN),
163 MXS_PINCTRL_PIN(GPMI_WRN),
164 MXS_PINCTRL_PIN(GPMI_RDN),
165 MXS_PINCTRL_PIN(AUART1_CTS),
166 MXS_PINCTRL_PIN(AUART1_RTS),
167 MXS_PINCTRL_PIN(AUART1_RX),
168 MXS_PINCTRL_PIN(AUART1_TX),
169 MXS_PINCTRL_PIN(I2C_SCL),
170 MXS_PINCTRL_PIN(I2C_SDA),
171 MXS_PINCTRL_PIN(LCD_D00),
172 MXS_PINCTRL_PIN(LCD_D01),
173 MXS_PINCTRL_PIN(LCD_D02),
174 MXS_PINCTRL_PIN(LCD_D03),
175 MXS_PINCTRL_PIN(LCD_D04),
176 MXS_PINCTRL_PIN(LCD_D05),
177 MXS_PINCTRL_PIN(LCD_D06),
178 MXS_PINCTRL_PIN(LCD_D07),
179 MXS_PINCTRL_PIN(LCD_D08),
180 MXS_PINCTRL_PIN(LCD_D09),
181 MXS_PINCTRL_PIN(LCD_D10),
182 MXS_PINCTRL_PIN(LCD_D11),
183 MXS_PINCTRL_PIN(LCD_D12),
184 MXS_PINCTRL_PIN(LCD_D13),
185 MXS_PINCTRL_PIN(LCD_D14),
186 MXS_PINCTRL_PIN(LCD_D15),
187 MXS_PINCTRL_PIN(LCD_D16),
188 MXS_PINCTRL_PIN(LCD_D17),
189 MXS_PINCTRL_PIN(LCD_RESET),
190 MXS_PINCTRL_PIN(LCD_RS),
191 MXS_PINCTRL_PIN(LCD_WR),
192 MXS_PINCTRL_PIN(LCD_CS),
193 MXS_PINCTRL_PIN(LCD_DOTCK),
194 MXS_PINCTRL_PIN(LCD_ENABLE),
195 MXS_PINCTRL_PIN(LCD_HSYNC),
196 MXS_PINCTRL_PIN(LCD_VSYNC),
197 MXS_PINCTRL_PIN(PWM0),
198 MXS_PINCTRL_PIN(PWM1),
199 MXS_PINCTRL_PIN(PWM2),
200 MXS_PINCTRL_PIN(PWM3),
201 MXS_PINCTRL_PIN(PWM4),
202 MXS_PINCTRL_PIN(SSP1_CMD),
203 MXS_PINCTRL_PIN(SSP1_DETECT),
204 MXS_PINCTRL_PIN(SSP1_DATA0),
205 MXS_PINCTRL_PIN(SSP1_DATA1),
206 MXS_PINCTRL_PIN(SSP1_DATA2),
207 MXS_PINCTRL_PIN(SSP1_DATA3),
208 MXS_PINCTRL_PIN(SSP1_SCK),
209 MXS_PINCTRL_PIN(ROTARYA),
210 MXS_PINCTRL_PIN(ROTARYB),
211 MXS_PINCTRL_PIN(EMI_A00),
212 MXS_PINCTRL_PIN(EMI_A01),
213 MXS_PINCTRL_PIN(EMI_A02),
214 MXS_PINCTRL_PIN(EMI_A03),
215 MXS_PINCTRL_PIN(EMI_A04),
216 MXS_PINCTRL_PIN(EMI_A05),
217 MXS_PINCTRL_PIN(EMI_A06),
218 MXS_PINCTRL_PIN(EMI_A07),
219 MXS_PINCTRL_PIN(EMI_A08),
220 MXS_PINCTRL_PIN(EMI_A09),
221 MXS_PINCTRL_PIN(EMI_A10),
222 MXS_PINCTRL_PIN(EMI_A11),
223 MXS_PINCTRL_PIN(EMI_A12),
224 MXS_PINCTRL_PIN(EMI_BA0),
225 MXS_PINCTRL_PIN(EMI_BA1),
226 MXS_PINCTRL_PIN(EMI_CASN),
227 MXS_PINCTRL_PIN(EMI_CE0N),
228 MXS_PINCTRL_PIN(EMI_CE1N),
229 MXS_PINCTRL_PIN(GPMI_CE1N),
230 MXS_PINCTRL_PIN(GPMI_CE0N),
231 MXS_PINCTRL_PIN(EMI_CKE),
232 MXS_PINCTRL_PIN(EMI_RASN),
233 MXS_PINCTRL_PIN(EMI_WEN),
234 MXS_PINCTRL_PIN(EMI_D00),
235 MXS_PINCTRL_PIN(EMI_D01),
236 MXS_PINCTRL_PIN(EMI_D02),
237 MXS_PINCTRL_PIN(EMI_D03),
238 MXS_PINCTRL_PIN(EMI_D04),
239 MXS_PINCTRL_PIN(EMI_D05),
240 MXS_PINCTRL_PIN(EMI_D06),
241 MXS_PINCTRL_PIN(EMI_D07),
242 MXS_PINCTRL_PIN(EMI_D08),
243 MXS_PINCTRL_PIN(EMI_D09),
244 MXS_PINCTRL_PIN(EMI_D10),
245 MXS_PINCTRL_PIN(EMI_D11),
246 MXS_PINCTRL_PIN(EMI_D12),
247 MXS_PINCTRL_PIN(EMI_D13),
248 MXS_PINCTRL_PIN(EMI_D14),
249 MXS_PINCTRL_PIN(EMI_D15),
250 MXS_PINCTRL_PIN(EMI_DQM0),
251 MXS_PINCTRL_PIN(EMI_DQM1),
252 MXS_PINCTRL_PIN(EMI_DQS0),
253 MXS_PINCTRL_PIN(EMI_DQS1),
254 MXS_PINCTRL_PIN(EMI_CLK),
255 MXS_PINCTRL_PIN(EMI_CLKN),
256};
257
258static struct mxs_regs imx23_regs = {
259 .muxsel = 0x100,
260 .drive = 0x200,
261 .pull = 0x400,
262};
263
264static struct mxs_pinctrl_soc_data imx23_pinctrl_data = {
265 .regs = &imx23_regs,
266 .pins = imx23_pins,
267 .npins = ARRAY_SIZE(imx23_pins),
268};
269
270static int __devinit imx23_pinctrl_probe(struct platform_device *pdev)
271{
272 return mxs_pinctrl_probe(pdev, &imx23_pinctrl_data);
273}
274
275static struct of_device_id imx23_pinctrl_of_match[] __devinitdata = {
276 { .compatible = "fsl,imx23-pinctrl", },
277 { /* sentinel */ }
278};
279MODULE_DEVICE_TABLE(of, imx23_pinctrl_of_match);
280
281static struct platform_driver imx23_pinctrl_driver = {
282 .driver = {
283 .name = "imx23-pinctrl",
284 .owner = THIS_MODULE,
285 .of_match_table = imx23_pinctrl_of_match,
286 },
287 .probe = imx23_pinctrl_probe,
288 .remove = __devexit_p(mxs_pinctrl_remove),
289};
290
291static int __init imx23_pinctrl_init(void)
292{
293 return platform_driver_register(&imx23_pinctrl_driver);
294}
295arch_initcall(imx23_pinctrl_init);
296
297static void __exit imx23_pinctrl_exit(void)
298{
299 platform_driver_unregister(&imx23_pinctrl_driver);
300}
301module_exit(imx23_pinctrl_exit);
302
303MODULE_AUTHOR("Shawn Guo <shawn.guo@linaro.org>");
304MODULE_DESCRIPTION("Freescale i.MX23 pinctrl driver");
305MODULE_LICENSE("GPL v2");
diff --git a/drivers/pinctrl/pinctrl-imx28.c b/drivers/pinctrl/pinctrl-imx28.c
new file mode 100644
index 00000000000..b973026811a
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-imx28.c
@@ -0,0 +1,421 @@
1/*
2 * Copyright 2012 Freescale Semiconductor, Inc.
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12#include <linux/init.h>
13#include <linux/module.h>
14#include <linux/of_device.h>
15#include <linux/pinctrl/pinctrl.h>
16#include "pinctrl-mxs.h"
17
18enum imx28_pin_enum {
19 GPMI_D00 = PINID(0, 0),
20 GPMI_D01 = PINID(0, 1),
21 GPMI_D02 = PINID(0, 2),
22 GPMI_D03 = PINID(0, 3),
23 GPMI_D04 = PINID(0, 4),
24 GPMI_D05 = PINID(0, 5),
25 GPMI_D06 = PINID(0, 6),
26 GPMI_D07 = PINID(0, 7),
27 GPMI_CE0N = PINID(0, 16),
28 GPMI_CE1N = PINID(0, 17),
29 GPMI_CE2N = PINID(0, 18),
30 GPMI_CE3N = PINID(0, 19),
31 GPMI_RDY0 = PINID(0, 20),
32 GPMI_RDY1 = PINID(0, 21),
33 GPMI_RDY2 = PINID(0, 22),
34 GPMI_RDY3 = PINID(0, 23),
35 GPMI_RDN = PINID(0, 24),
36 GPMI_WRN = PINID(0, 25),
37 GPMI_ALE = PINID(0, 26),
38 GPMI_CLE = PINID(0, 27),
39 GPMI_RESETN = PINID(0, 28),
40 LCD_D00 = PINID(1, 0),
41 LCD_D01 = PINID(1, 1),
42 LCD_D02 = PINID(1, 2),
43 LCD_D03 = PINID(1, 3),
44 LCD_D04 = PINID(1, 4),
45 LCD_D05 = PINID(1, 5),
46 LCD_D06 = PINID(1, 6),
47 LCD_D07 = PINID(1, 7),
48 LCD_D08 = PINID(1, 8),
49 LCD_D09 = PINID(1, 9),
50 LCD_D10 = PINID(1, 10),
51 LCD_D11 = PINID(1, 11),
52 LCD_D12 = PINID(1, 12),
53 LCD_D13 = PINID(1, 13),
54 LCD_D14 = PINID(1, 14),
55 LCD_D15 = PINID(1, 15),
56 LCD_D16 = PINID(1, 16),
57 LCD_D17 = PINID(1, 17),
58 LCD_D18 = PINID(1, 18),
59 LCD_D19 = PINID(1, 19),
60 LCD_D20 = PINID(1, 20),
61 LCD_D21 = PINID(1, 21),
62 LCD_D22 = PINID(1, 22),
63 LCD_D23 = PINID(1, 23),
64 LCD_RD_E = PINID(1, 24),
65 LCD_WR_RWN = PINID(1, 25),
66 LCD_RS = PINID(1, 26),
67 LCD_CS = PINID(1, 27),
68 LCD_VSYNC = PINID(1, 28),
69 LCD_HSYNC = PINID(1, 29),
70 LCD_DOTCLK = PINID(1, 30),
71 LCD_ENABLE = PINID(1, 31),
72 SSP0_DATA0 = PINID(2, 0),
73 SSP0_DATA1 = PINID(2, 1),
74 SSP0_DATA2 = PINID(2, 2),
75 SSP0_DATA3 = PINID(2, 3),
76 SSP0_DATA4 = PINID(2, 4),
77 SSP0_DATA5 = PINID(2, 5),
78 SSP0_DATA6 = PINID(2, 6),
79 SSP0_DATA7 = PINID(2, 7),
80 SSP0_CMD = PINID(2, 8),
81 SSP0_DETECT = PINID(2, 9),
82 SSP0_SCK = PINID(2, 10),
83 SSP1_SCK = PINID(2, 12),
84 SSP1_CMD = PINID(2, 13),
85 SSP1_DATA0 = PINID(2, 14),
86 SSP1_DATA3 = PINID(2, 15),
87 SSP2_SCK = PINID(2, 16),
88 SSP2_MOSI = PINID(2, 17),
89 SSP2_MISO = PINID(2, 18),
90 SSP2_SS0 = PINID(2, 19),
91 SSP2_SS1 = PINID(2, 20),
92 SSP2_SS2 = PINID(2, 21),
93 SSP3_SCK = PINID(2, 24),
94 SSP3_MOSI = PINID(2, 25),
95 SSP3_MISO = PINID(2, 26),
96 SSP3_SS0 = PINID(2, 27),
97 AUART0_RX = PINID(3, 0),
98 AUART0_TX = PINID(3, 1),
99 AUART0_CTS = PINID(3, 2),
100 AUART0_RTS = PINID(3, 3),
101 AUART1_RX = PINID(3, 4),
102 AUART1_TX = PINID(3, 5),
103 AUART1_CTS = PINID(3, 6),
104 AUART1_RTS = PINID(3, 7),
105 AUART2_RX = PINID(3, 8),
106 AUART2_TX = PINID(3, 9),
107 AUART2_CTS = PINID(3, 10),
108 AUART2_RTS = PINID(3, 11),
109 AUART3_RX = PINID(3, 12),
110 AUART3_TX = PINID(3, 13),
111 AUART3_CTS = PINID(3, 14),
112 AUART3_RTS = PINID(3, 15),
113 PWM0 = PINID(3, 16),
114 PWM1 = PINID(3, 17),
115 PWM2 = PINID(3, 18),
116 SAIF0_MCLK = PINID(3, 20),
117 SAIF0_LRCLK = PINID(3, 21),
118 SAIF0_BITCLK = PINID(3, 22),
119 SAIF0_SDATA0 = PINID(3, 23),
120 I2C0_SCL = PINID(3, 24),
121 I2C0_SDA = PINID(3, 25),
122 SAIF1_SDATA0 = PINID(3, 26),
123 SPDIF = PINID(3, 27),
124 PWM3 = PINID(3, 28),
125 PWM4 = PINID(3, 29),
126 LCD_RESET = PINID(3, 30),
127 ENET0_MDC = PINID(4, 0),
128 ENET0_MDIO = PINID(4, 1),
129 ENET0_RX_EN = PINID(4, 2),
130 ENET0_RXD0 = PINID(4, 3),
131 ENET0_RXD1 = PINID(4, 4),
132 ENET0_TX_CLK = PINID(4, 5),
133 ENET0_TX_EN = PINID(4, 6),
134 ENET0_TXD0 = PINID(4, 7),
135 ENET0_TXD1 = PINID(4, 8),
136 ENET0_RXD2 = PINID(4, 9),
137 ENET0_RXD3 = PINID(4, 10),
138 ENET0_TXD2 = PINID(4, 11),
139 ENET0_TXD3 = PINID(4, 12),
140 ENET0_RX_CLK = PINID(4, 13),
141 ENET0_COL = PINID(4, 14),
142 ENET0_CRS = PINID(4, 15),
143 ENET_CLK = PINID(4, 16),
144 JTAG_RTCK = PINID(4, 20),
145 EMI_D00 = PINID(5, 0),
146 EMI_D01 = PINID(5, 1),
147 EMI_D02 = PINID(5, 2),
148 EMI_D03 = PINID(5, 3),
149 EMI_D04 = PINID(5, 4),
150 EMI_D05 = PINID(5, 5),
151 EMI_D06 = PINID(5, 6),
152 EMI_D07 = PINID(5, 7),
153 EMI_D08 = PINID(5, 8),
154 EMI_D09 = PINID(5, 9),
155 EMI_D10 = PINID(5, 10),
156 EMI_D11 = PINID(5, 11),
157 EMI_D12 = PINID(5, 12),
158 EMI_D13 = PINID(5, 13),
159 EMI_D14 = PINID(5, 14),
160 EMI_D15 = PINID(5, 15),
161 EMI_ODT0 = PINID(5, 16),
162 EMI_DQM0 = PINID(5, 17),
163 EMI_ODT1 = PINID(5, 18),
164 EMI_DQM1 = PINID(5, 19),
165 EMI_DDR_OPEN_FB = PINID(5, 20),
166 EMI_CLK = PINID(5, 21),
167 EMI_DQS0 = PINID(5, 22),
168 EMI_DQS1 = PINID(5, 23),
169 EMI_DDR_OPEN = PINID(5, 26),
170 EMI_A00 = PINID(6, 0),
171 EMI_A01 = PINID(6, 1),
172 EMI_A02 = PINID(6, 2),
173 EMI_A03 = PINID(6, 3),
174 EMI_A04 = PINID(6, 4),
175 EMI_A05 = PINID(6, 5),
176 EMI_A06 = PINID(6, 6),
177 EMI_A07 = PINID(6, 7),
178 EMI_A08 = PINID(6, 8),
179 EMI_A09 = PINID(6, 9),
180 EMI_A10 = PINID(6, 10),
181 EMI_A11 = PINID(6, 11),
182 EMI_A12 = PINID(6, 12),
183 EMI_A13 = PINID(6, 13),
184 EMI_A14 = PINID(6, 14),
185 EMI_BA0 = PINID(6, 16),
186 EMI_BA1 = PINID(6, 17),
187 EMI_BA2 = PINID(6, 18),
188 EMI_CASN = PINID(6, 19),
189 EMI_RASN = PINID(6, 20),
190 EMI_WEN = PINID(6, 21),
191 EMI_CE0N = PINID(6, 22),
192 EMI_CE1N = PINID(6, 23),
193 EMI_CKE = PINID(6, 24),
194};
195
196static const struct pinctrl_pin_desc imx28_pins[] = {
197 MXS_PINCTRL_PIN(GPMI_D00),
198 MXS_PINCTRL_PIN(GPMI_D01),
199 MXS_PINCTRL_PIN(GPMI_D02),
200 MXS_PINCTRL_PIN(GPMI_D03),
201 MXS_PINCTRL_PIN(GPMI_D04),
202 MXS_PINCTRL_PIN(GPMI_D05),
203 MXS_PINCTRL_PIN(GPMI_D06),
204 MXS_PINCTRL_PIN(GPMI_D07),
205 MXS_PINCTRL_PIN(GPMI_CE0N),
206 MXS_PINCTRL_PIN(GPMI_CE1N),
207 MXS_PINCTRL_PIN(GPMI_CE2N),
208 MXS_PINCTRL_PIN(GPMI_CE3N),
209 MXS_PINCTRL_PIN(GPMI_RDY0),
210 MXS_PINCTRL_PIN(GPMI_RDY1),
211 MXS_PINCTRL_PIN(GPMI_RDY2),
212 MXS_PINCTRL_PIN(GPMI_RDY3),
213 MXS_PINCTRL_PIN(GPMI_RDN),
214 MXS_PINCTRL_PIN(GPMI_WRN),
215 MXS_PINCTRL_PIN(GPMI_ALE),
216 MXS_PINCTRL_PIN(GPMI_CLE),
217 MXS_PINCTRL_PIN(GPMI_RESETN),
218 MXS_PINCTRL_PIN(LCD_D00),
219 MXS_PINCTRL_PIN(LCD_D01),
220 MXS_PINCTRL_PIN(LCD_D02),
221 MXS_PINCTRL_PIN(LCD_D03),
222 MXS_PINCTRL_PIN(LCD_D04),
223 MXS_PINCTRL_PIN(LCD_D05),
224 MXS_PINCTRL_PIN(LCD_D06),
225 MXS_PINCTRL_PIN(LCD_D07),
226 MXS_PINCTRL_PIN(LCD_D08),
227 MXS_PINCTRL_PIN(LCD_D09),
228 MXS_PINCTRL_PIN(LCD_D10),
229 MXS_PINCTRL_PIN(LCD_D11),
230 MXS_PINCTRL_PIN(LCD_D12),
231 MXS_PINCTRL_PIN(LCD_D13),
232 MXS_PINCTRL_PIN(LCD_D14),
233 MXS_PINCTRL_PIN(LCD_D15),
234 MXS_PINCTRL_PIN(LCD_D16),
235 MXS_PINCTRL_PIN(LCD_D17),
236 MXS_PINCTRL_PIN(LCD_D18),
237 MXS_PINCTRL_PIN(LCD_D19),
238 MXS_PINCTRL_PIN(LCD_D20),
239 MXS_PINCTRL_PIN(LCD_D21),
240 MXS_PINCTRL_PIN(LCD_D22),
241 MXS_PINCTRL_PIN(LCD_D23),
242 MXS_PINCTRL_PIN(LCD_RD_E),
243 MXS_PINCTRL_PIN(LCD_WR_RWN),
244 MXS_PINCTRL_PIN(LCD_RS),
245 MXS_PINCTRL_PIN(LCD_CS),
246 MXS_PINCTRL_PIN(LCD_VSYNC),
247 MXS_PINCTRL_PIN(LCD_HSYNC),
248 MXS_PINCTRL_PIN(LCD_DOTCLK),
249 MXS_PINCTRL_PIN(LCD_ENABLE),
250 MXS_PINCTRL_PIN(SSP0_DATA0),
251 MXS_PINCTRL_PIN(SSP0_DATA1),
252 MXS_PINCTRL_PIN(SSP0_DATA2),
253 MXS_PINCTRL_PIN(SSP0_DATA3),
254 MXS_PINCTRL_PIN(SSP0_DATA4),
255 MXS_PINCTRL_PIN(SSP0_DATA5),
256 MXS_PINCTRL_PIN(SSP0_DATA6),
257 MXS_PINCTRL_PIN(SSP0_DATA7),
258 MXS_PINCTRL_PIN(SSP0_CMD),
259 MXS_PINCTRL_PIN(SSP0_DETECT),
260 MXS_PINCTRL_PIN(SSP0_SCK),
261 MXS_PINCTRL_PIN(SSP1_SCK),
262 MXS_PINCTRL_PIN(SSP1_CMD),
263 MXS_PINCTRL_PIN(SSP1_DATA0),
264 MXS_PINCTRL_PIN(SSP1_DATA3),
265 MXS_PINCTRL_PIN(SSP2_SCK),
266 MXS_PINCTRL_PIN(SSP2_MOSI),
267 MXS_PINCTRL_PIN(SSP2_MISO),
268 MXS_PINCTRL_PIN(SSP2_SS0),
269 MXS_PINCTRL_PIN(SSP2_SS1),
270 MXS_PINCTRL_PIN(SSP2_SS2),
271 MXS_PINCTRL_PIN(SSP3_SCK),
272 MXS_PINCTRL_PIN(SSP3_MOSI),
273 MXS_PINCTRL_PIN(SSP3_MISO),
274 MXS_PINCTRL_PIN(SSP3_SS0),
275 MXS_PINCTRL_PIN(AUART0_RX),
276 MXS_PINCTRL_PIN(AUART0_TX),
277 MXS_PINCTRL_PIN(AUART0_CTS),
278 MXS_PINCTRL_PIN(AUART0_RTS),
279 MXS_PINCTRL_PIN(AUART1_RX),
280 MXS_PINCTRL_PIN(AUART1_TX),
281 MXS_PINCTRL_PIN(AUART1_CTS),
282 MXS_PINCTRL_PIN(AUART1_RTS),
283 MXS_PINCTRL_PIN(AUART2_RX),
284 MXS_PINCTRL_PIN(AUART2_TX),
285 MXS_PINCTRL_PIN(AUART2_CTS),
286 MXS_PINCTRL_PIN(AUART2_RTS),
287 MXS_PINCTRL_PIN(AUART3_RX),
288 MXS_PINCTRL_PIN(AUART3_TX),
289 MXS_PINCTRL_PIN(AUART3_CTS),
290 MXS_PINCTRL_PIN(AUART3_RTS),
291 MXS_PINCTRL_PIN(PWM0),
292 MXS_PINCTRL_PIN(PWM1),
293 MXS_PINCTRL_PIN(PWM2),
294 MXS_PINCTRL_PIN(SAIF0_MCLK),
295 MXS_PINCTRL_PIN(SAIF0_LRCLK),
296 MXS_PINCTRL_PIN(SAIF0_BITCLK),
297 MXS_PINCTRL_PIN(SAIF0_SDATA0),
298 MXS_PINCTRL_PIN(I2C0_SCL),
299 MXS_PINCTRL_PIN(I2C0_SDA),
300 MXS_PINCTRL_PIN(SAIF1_SDATA0),
301 MXS_PINCTRL_PIN(SPDIF),
302 MXS_PINCTRL_PIN(PWM3),
303 MXS_PINCTRL_PIN(PWM4),
304 MXS_PINCTRL_PIN(LCD_RESET),
305 MXS_PINCTRL_PIN(ENET0_MDC),
306 MXS_PINCTRL_PIN(ENET0_MDIO),
307 MXS_PINCTRL_PIN(ENET0_RX_EN),
308 MXS_PINCTRL_PIN(ENET0_RXD0),
309 MXS_PINCTRL_PIN(ENET0_RXD1),
310 MXS_PINCTRL_PIN(ENET0_TX_CLK),
311 MXS_PINCTRL_PIN(ENET0_TX_EN),
312 MXS_PINCTRL_PIN(ENET0_TXD0),
313 MXS_PINCTRL_PIN(ENET0_TXD1),
314 MXS_PINCTRL_PIN(ENET0_RXD2),
315 MXS_PINCTRL_PIN(ENET0_RXD3),
316 MXS_PINCTRL_PIN(ENET0_TXD2),
317 MXS_PINCTRL_PIN(ENET0_TXD3),
318 MXS_PINCTRL_PIN(ENET0_RX_CLK),
319 MXS_PINCTRL_PIN(ENET0_COL),
320 MXS_PINCTRL_PIN(ENET0_CRS),
321 MXS_PINCTRL_PIN(ENET_CLK),
322 MXS_PINCTRL_PIN(JTAG_RTCK),
323 MXS_PINCTRL_PIN(EMI_D00),
324 MXS_PINCTRL_PIN(EMI_D01),
325 MXS_PINCTRL_PIN(EMI_D02),
326 MXS_PINCTRL_PIN(EMI_D03),
327 MXS_PINCTRL_PIN(EMI_D04),
328 MXS_PINCTRL_PIN(EMI_D05),
329 MXS_PINCTRL_PIN(EMI_D06),
330 MXS_PINCTRL_PIN(EMI_D07),
331 MXS_PINCTRL_PIN(EMI_D08),
332 MXS_PINCTRL_PIN(EMI_D09),
333 MXS_PINCTRL_PIN(EMI_D10),
334 MXS_PINCTRL_PIN(EMI_D11),
335 MXS_PINCTRL_PIN(EMI_D12),
336 MXS_PINCTRL_PIN(EMI_D13),
337 MXS_PINCTRL_PIN(EMI_D14),
338 MXS_PINCTRL_PIN(EMI_D15),
339 MXS_PINCTRL_PIN(EMI_ODT0),
340 MXS_PINCTRL_PIN(EMI_DQM0),
341 MXS_PINCTRL_PIN(EMI_ODT1),
342 MXS_PINCTRL_PIN(EMI_DQM1),
343 MXS_PINCTRL_PIN(EMI_DDR_OPEN_FB),
344 MXS_PINCTRL_PIN(EMI_CLK),
345 MXS_PINCTRL_PIN(EMI_DQS0),
346 MXS_PINCTRL_PIN(EMI_DQS1),
347 MXS_PINCTRL_PIN(EMI_DDR_OPEN),
348 MXS_PINCTRL_PIN(EMI_A00),
349 MXS_PINCTRL_PIN(EMI_A01),
350 MXS_PINCTRL_PIN(EMI_A02),
351 MXS_PINCTRL_PIN(EMI_A03),
352 MXS_PINCTRL_PIN(EMI_A04),
353 MXS_PINCTRL_PIN(EMI_A05),
354 MXS_PINCTRL_PIN(EMI_A06),
355 MXS_PINCTRL_PIN(EMI_A07),
356 MXS_PINCTRL_PIN(EMI_A08),
357 MXS_PINCTRL_PIN(EMI_A09),
358 MXS_PINCTRL_PIN(EMI_A10),
359 MXS_PINCTRL_PIN(EMI_A11),
360 MXS_PINCTRL_PIN(EMI_A12),
361 MXS_PINCTRL_PIN(EMI_A13),
362 MXS_PINCTRL_PIN(EMI_A14),
363 MXS_PINCTRL_PIN(EMI_BA0),
364 MXS_PINCTRL_PIN(EMI_BA1),
365 MXS_PINCTRL_PIN(EMI_BA2),
366 MXS_PINCTRL_PIN(EMI_CASN),
367 MXS_PINCTRL_PIN(EMI_RASN),
368 MXS_PINCTRL_PIN(EMI_WEN),
369 MXS_PINCTRL_PIN(EMI_CE0N),
370 MXS_PINCTRL_PIN(EMI_CE1N),
371 MXS_PINCTRL_PIN(EMI_CKE),
372};
373
374static struct mxs_regs imx28_regs = {
375 .muxsel = 0x100,
376 .drive = 0x300,
377 .pull = 0x600,
378};
379
380static struct mxs_pinctrl_soc_data imx28_pinctrl_data = {
381 .regs = &imx28_regs,
382 .pins = imx28_pins,
383 .npins = ARRAY_SIZE(imx28_pins),
384};
385
386static int __devinit imx28_pinctrl_probe(struct platform_device *pdev)
387{
388 return mxs_pinctrl_probe(pdev, &imx28_pinctrl_data);
389}
390
391static struct of_device_id imx28_pinctrl_of_match[] __devinitdata = {
392 { .compatible = "fsl,imx28-pinctrl", },
393 { /* sentinel */ }
394};
395MODULE_DEVICE_TABLE(of, imx28_pinctrl_of_match);
396
397static struct platform_driver imx28_pinctrl_driver = {
398 .driver = {
399 .name = "imx28-pinctrl",
400 .owner = THIS_MODULE,
401 .of_match_table = imx28_pinctrl_of_match,
402 },
403 .probe = imx28_pinctrl_probe,
404 .remove = __devexit_p(mxs_pinctrl_remove),
405};
406
407static int __init imx28_pinctrl_init(void)
408{
409 return platform_driver_register(&imx28_pinctrl_driver);
410}
411arch_initcall(imx28_pinctrl_init);
412
413static void __exit imx28_pinctrl_exit(void)
414{
415 platform_driver_unregister(&imx28_pinctrl_driver);
416}
417module_exit(imx28_pinctrl_exit);
418
419MODULE_AUTHOR("Shawn Guo <shawn.guo@linaro.org>");
420MODULE_DESCRIPTION("Freescale i.MX28 pinctrl driver");
421MODULE_LICENSE("GPL v2");
diff --git a/drivers/pinctrl/pinctrl-imx6q.c b/drivers/pinctrl/pinctrl-imx6q.c
new file mode 100644
index 00000000000..7737d4d71a3
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-imx6q.c
@@ -0,0 +1,2331 @@
1/*
2 * imx6q pinctrl driver based on imx pinmux core
3 *
4 * Copyright (C) 2012 Freescale Semiconductor, Inc.
5 * Copyright (C) 2012 Linaro, Inc.
6 *
7 * Author: Dong Aisheng <dong.aisheng@linaro.org>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 */
14
15#include <linux/err.h>
16#include <linux/init.h>
17#include <linux/io.h>
18#include <linux/module.h>
19#include <linux/of.h>
20#include <linux/of_device.h>
21#include <linux/pinctrl/pinctrl.h>
22
23#include "pinctrl-imx.h"
24
25enum imx6q_pads {
26 MX6Q_PAD_SD2_DAT1 = 0,
27 MX6Q_PAD_SD2_DAT2 = 1,
28 MX6Q_PAD_SD2_DAT0 = 2,
29 MX6Q_PAD_RGMII_TXC = 3,
30 MX6Q_PAD_RGMII_TD0 = 4,
31 MX6Q_PAD_RGMII_TD1 = 5,
32 MX6Q_PAD_RGMII_TD2 = 6,
33 MX6Q_PAD_RGMII_TD3 = 7,
34 MX6Q_PAD_RGMII_RX_CTL = 8,
35 MX6Q_PAD_RGMII_RD0 = 9,
36 MX6Q_PAD_RGMII_TX_CTL = 10,
37 MX6Q_PAD_RGMII_RD1 = 11,
38 MX6Q_PAD_RGMII_RD2 = 12,
39 MX6Q_PAD_RGMII_RD3 = 13,
40 MX6Q_PAD_RGMII_RXC = 14,
41 MX6Q_PAD_EIM_A25 = 15,
42 MX6Q_PAD_EIM_EB2 = 16,
43 MX6Q_PAD_EIM_D16 = 17,
44 MX6Q_PAD_EIM_D17 = 18,
45 MX6Q_PAD_EIM_D18 = 19,
46 MX6Q_PAD_EIM_D19 = 20,
47 MX6Q_PAD_EIM_D20 = 21,
48 MX6Q_PAD_EIM_D21 = 22,
49 MX6Q_PAD_EIM_D22 = 23,
50 MX6Q_PAD_EIM_D23 = 24,
51 MX6Q_PAD_EIM_EB3 = 25,
52 MX6Q_PAD_EIM_D24 = 26,
53 MX6Q_PAD_EIM_D25 = 27,
54 MX6Q_PAD_EIM_D26 = 28,
55 MX6Q_PAD_EIM_D27 = 29,
56 MX6Q_PAD_EIM_D28 = 30,
57 MX6Q_PAD_EIM_D29 = 31,
58 MX6Q_PAD_EIM_D30 = 32,
59 MX6Q_PAD_EIM_D31 = 33,
60 MX6Q_PAD_EIM_A24 = 34,
61 MX6Q_PAD_EIM_A23 = 35,
62 MX6Q_PAD_EIM_A22 = 36,
63 MX6Q_PAD_EIM_A21 = 37,
64 MX6Q_PAD_EIM_A20 = 38,
65 MX6Q_PAD_EIM_A19 = 39,
66 MX6Q_PAD_EIM_A18 = 40,
67 MX6Q_PAD_EIM_A17 = 41,
68 MX6Q_PAD_EIM_A16 = 42,
69 MX6Q_PAD_EIM_CS0 = 43,
70 MX6Q_PAD_EIM_CS1 = 44,
71 MX6Q_PAD_EIM_OE = 45,
72 MX6Q_PAD_EIM_RW = 46,
73 MX6Q_PAD_EIM_LBA = 47,
74 MX6Q_PAD_EIM_EB0 = 48,
75 MX6Q_PAD_EIM_EB1 = 49,
76 MX6Q_PAD_EIM_DA0 = 50,
77 MX6Q_PAD_EIM_DA1 = 51,
78 MX6Q_PAD_EIM_DA2 = 52,
79 MX6Q_PAD_EIM_DA3 = 53,
80 MX6Q_PAD_EIM_DA4 = 54,
81 MX6Q_PAD_EIM_DA5 = 55,
82 MX6Q_PAD_EIM_DA6 = 56,
83 MX6Q_PAD_EIM_DA7 = 57,
84 MX6Q_PAD_EIM_DA8 = 58,
85 MX6Q_PAD_EIM_DA9 = 59,
86 MX6Q_PAD_EIM_DA10 = 60,
87 MX6Q_PAD_EIM_DA11 = 61,
88 MX6Q_PAD_EIM_DA12 = 62,
89 MX6Q_PAD_EIM_DA13 = 63,
90 MX6Q_PAD_EIM_DA14 = 64,
91 MX6Q_PAD_EIM_DA15 = 65,
92 MX6Q_PAD_EIM_WAIT = 66,
93 MX6Q_PAD_EIM_BCLK = 67,
94 MX6Q_PAD_DI0_DISP_CLK = 68,
95 MX6Q_PAD_DI0_PIN15 = 69,
96 MX6Q_PAD_DI0_PIN2 = 70,
97 MX6Q_PAD_DI0_PIN3 = 71,
98 MX6Q_PAD_DI0_PIN4 = 72,
99 MX6Q_PAD_DISP0_DAT0 = 73,
100 MX6Q_PAD_DISP0_DAT1 = 74,
101 MX6Q_PAD_DISP0_DAT2 = 75,
102 MX6Q_PAD_DISP0_DAT3 = 76,
103 MX6Q_PAD_DISP0_DAT4 = 77,
104 MX6Q_PAD_DISP0_DAT5 = 78,
105 MX6Q_PAD_DISP0_DAT6 = 79,
106 MX6Q_PAD_DISP0_DAT7 = 80,
107 MX6Q_PAD_DISP0_DAT8 = 81,
108 MX6Q_PAD_DISP0_DAT9 = 82,
109 MX6Q_PAD_DISP0_DAT10 = 83,
110 MX6Q_PAD_DISP0_DAT11 = 84,
111 MX6Q_PAD_DISP0_DAT12 = 85,
112 MX6Q_PAD_DISP0_DAT13 = 86,
113 MX6Q_PAD_DISP0_DAT14 = 87,
114 MX6Q_PAD_DISP0_DAT15 = 88,
115 MX6Q_PAD_DISP0_DAT16 = 89,
116 MX6Q_PAD_DISP0_DAT17 = 90,
117 MX6Q_PAD_DISP0_DAT18 = 91,
118 MX6Q_PAD_DISP0_DAT19 = 92,
119 MX6Q_PAD_DISP0_DAT20 = 93,
120 MX6Q_PAD_DISP0_DAT21 = 94,
121 MX6Q_PAD_DISP0_DAT22 = 95,
122 MX6Q_PAD_DISP0_DAT23 = 96,
123 MX6Q_PAD_ENET_MDIO = 97,
124 MX6Q_PAD_ENET_REF_CLK = 98,
125 MX6Q_PAD_ENET_RX_ER = 99,
126 MX6Q_PAD_ENET_CRS_DV = 100,
127 MX6Q_PAD_ENET_RXD1 = 101,
128 MX6Q_PAD_ENET_RXD0 = 102,
129 MX6Q_PAD_ENET_TX_EN = 103,
130 MX6Q_PAD_ENET_TXD1 = 104,
131 MX6Q_PAD_ENET_TXD0 = 105,
132 MX6Q_PAD_ENET_MDC = 106,
133 MX6Q_PAD_DRAM_D40 = 107,
134 MX6Q_PAD_DRAM_D41 = 108,
135 MX6Q_PAD_DRAM_D42 = 109,
136 MX6Q_PAD_DRAM_D43 = 110,
137 MX6Q_PAD_DRAM_D44 = 111,
138 MX6Q_PAD_DRAM_D45 = 112,
139 MX6Q_PAD_DRAM_D46 = 113,
140 MX6Q_PAD_DRAM_D47 = 114,
141 MX6Q_PAD_DRAM_SDQS5 = 115,
142 MX6Q_PAD_DRAM_DQM5 = 116,
143 MX6Q_PAD_DRAM_D32 = 117,
144 MX6Q_PAD_DRAM_D33 = 118,
145 MX6Q_PAD_DRAM_D34 = 119,
146 MX6Q_PAD_DRAM_D35 = 120,
147 MX6Q_PAD_DRAM_D36 = 121,
148 MX6Q_PAD_DRAM_D37 = 122,
149 MX6Q_PAD_DRAM_D38 = 123,
150 MX6Q_PAD_DRAM_D39 = 124,
151 MX6Q_PAD_DRAM_DQM4 = 125,
152 MX6Q_PAD_DRAM_SDQS4 = 126,
153 MX6Q_PAD_DRAM_D24 = 127,
154 MX6Q_PAD_DRAM_D25 = 128,
155 MX6Q_PAD_DRAM_D26 = 129,
156 MX6Q_PAD_DRAM_D27 = 130,
157 MX6Q_PAD_DRAM_D28 = 131,
158 MX6Q_PAD_DRAM_D29 = 132,
159 MX6Q_PAD_DRAM_SDQS3 = 133,
160 MX6Q_PAD_DRAM_D30 = 134,
161 MX6Q_PAD_DRAM_D31 = 135,
162 MX6Q_PAD_DRAM_DQM3 = 136,
163 MX6Q_PAD_DRAM_D16 = 137,
164 MX6Q_PAD_DRAM_D17 = 138,
165 MX6Q_PAD_DRAM_D18 = 139,
166 MX6Q_PAD_DRAM_D19 = 140,
167 MX6Q_PAD_DRAM_D20 = 141,
168 MX6Q_PAD_DRAM_D21 = 142,
169 MX6Q_PAD_DRAM_D22 = 143,
170 MX6Q_PAD_DRAM_SDQS2 = 144,
171 MX6Q_PAD_DRAM_D23 = 145,
172 MX6Q_PAD_DRAM_DQM2 = 146,
173 MX6Q_PAD_DRAM_A0 = 147,
174 MX6Q_PAD_DRAM_A1 = 148,
175 MX6Q_PAD_DRAM_A2 = 149,
176 MX6Q_PAD_DRAM_A3 = 150,
177 MX6Q_PAD_DRAM_A4 = 151,
178 MX6Q_PAD_DRAM_A5 = 152,
179 MX6Q_PAD_DRAM_A6 = 153,
180 MX6Q_PAD_DRAM_A7 = 154,
181 MX6Q_PAD_DRAM_A8 = 155,
182 MX6Q_PAD_DRAM_A9 = 156,
183 MX6Q_PAD_DRAM_A10 = 157,
184 MX6Q_PAD_DRAM_A11 = 158,
185 MX6Q_PAD_DRAM_A12 = 159,
186 MX6Q_PAD_DRAM_A13 = 160,
187 MX6Q_PAD_DRAM_A14 = 161,
188 MX6Q_PAD_DRAM_A15 = 162,
189 MX6Q_PAD_DRAM_CAS = 163,
190 MX6Q_PAD_DRAM_CS0 = 164,
191 MX6Q_PAD_DRAM_CS1 = 165,
192 MX6Q_PAD_DRAM_RAS = 166,
193 MX6Q_PAD_DRAM_RESET = 167,
194 MX6Q_PAD_DRAM_SDBA0 = 168,
195 MX6Q_PAD_DRAM_SDBA1 = 169,
196 MX6Q_PAD_DRAM_SDCLK_0 = 170,
197 MX6Q_PAD_DRAM_SDBA2 = 171,
198 MX6Q_PAD_DRAM_SDCKE0 = 172,
199 MX6Q_PAD_DRAM_SDCLK_1 = 173,
200 MX6Q_PAD_DRAM_SDCKE1 = 174,
201 MX6Q_PAD_DRAM_SDODT0 = 175,
202 MX6Q_PAD_DRAM_SDODT1 = 176,
203 MX6Q_PAD_DRAM_SDWE = 177,
204 MX6Q_PAD_DRAM_D0 = 178,
205 MX6Q_PAD_DRAM_D1 = 179,
206 MX6Q_PAD_DRAM_D2 = 180,
207 MX6Q_PAD_DRAM_D3 = 181,
208 MX6Q_PAD_DRAM_D4 = 182,
209 MX6Q_PAD_DRAM_D5 = 183,
210 MX6Q_PAD_DRAM_SDQS0 = 184,
211 MX6Q_PAD_DRAM_D6 = 185,
212 MX6Q_PAD_DRAM_D7 = 186,
213 MX6Q_PAD_DRAM_DQM0 = 187,
214 MX6Q_PAD_DRAM_D8 = 188,
215 MX6Q_PAD_DRAM_D9 = 189,
216 MX6Q_PAD_DRAM_D10 = 190,
217 MX6Q_PAD_DRAM_D11 = 191,
218 MX6Q_PAD_DRAM_D12 = 192,
219 MX6Q_PAD_DRAM_D13 = 193,
220 MX6Q_PAD_DRAM_D14 = 194,
221 MX6Q_PAD_DRAM_SDQS1 = 195,
222 MX6Q_PAD_DRAM_D15 = 196,
223 MX6Q_PAD_DRAM_DQM1 = 197,
224 MX6Q_PAD_DRAM_D48 = 198,
225 MX6Q_PAD_DRAM_D49 = 199,
226 MX6Q_PAD_DRAM_D50 = 200,
227 MX6Q_PAD_DRAM_D51 = 201,
228 MX6Q_PAD_DRAM_D52 = 202,
229 MX6Q_PAD_DRAM_D53 = 203,
230 MX6Q_PAD_DRAM_D54 = 204,
231 MX6Q_PAD_DRAM_D55 = 205,
232 MX6Q_PAD_DRAM_SDQS6 = 206,
233 MX6Q_PAD_DRAM_DQM6 = 207,
234 MX6Q_PAD_DRAM_D56 = 208,
235 MX6Q_PAD_DRAM_SDQS7 = 209,
236 MX6Q_PAD_DRAM_D57 = 210,
237 MX6Q_PAD_DRAM_D58 = 211,
238 MX6Q_PAD_DRAM_D59 = 212,
239 MX6Q_PAD_DRAM_D60 = 213,
240 MX6Q_PAD_DRAM_DQM7 = 214,
241 MX6Q_PAD_DRAM_D61 = 215,
242 MX6Q_PAD_DRAM_D62 = 216,
243 MX6Q_PAD_DRAM_D63 = 217,
244 MX6Q_PAD_KEY_COL0 = 218,
245 MX6Q_PAD_KEY_ROW0 = 219,
246 MX6Q_PAD_KEY_COL1 = 220,
247 MX6Q_PAD_KEY_ROW1 = 221,
248 MX6Q_PAD_KEY_COL2 = 222,
249 MX6Q_PAD_KEY_ROW2 = 223,
250 MX6Q_PAD_KEY_COL3 = 224,
251 MX6Q_PAD_KEY_ROW3 = 225,
252 MX6Q_PAD_KEY_COL4 = 226,
253 MX6Q_PAD_KEY_ROW4 = 227,
254 MX6Q_PAD_GPIO_0 = 228,
255 MX6Q_PAD_GPIO_1 = 229,
256 MX6Q_PAD_GPIO_9 = 230,
257 MX6Q_PAD_GPIO_3 = 231,
258 MX6Q_PAD_GPIO_6 = 232,
259 MX6Q_PAD_GPIO_2 = 233,
260 MX6Q_PAD_GPIO_4 = 234,
261 MX6Q_PAD_GPIO_5 = 235,
262 MX6Q_PAD_GPIO_7 = 236,
263 MX6Q_PAD_GPIO_8 = 237,
264 MX6Q_PAD_GPIO_16 = 238,
265 MX6Q_PAD_GPIO_17 = 239,
266 MX6Q_PAD_GPIO_18 = 240,
267 MX6Q_PAD_GPIO_19 = 241,
268 MX6Q_PAD_CSI0_PIXCLK = 242,
269 MX6Q_PAD_CSI0_MCLK = 243,
270 MX6Q_PAD_CSI0_DATA_EN = 244,
271 MX6Q_PAD_CSI0_VSYNC = 245,
272 MX6Q_PAD_CSI0_DAT4 = 246,
273 MX6Q_PAD_CSI0_DAT5 = 247,
274 MX6Q_PAD_CSI0_DAT6 = 248,
275 MX6Q_PAD_CSI0_DAT7 = 249,
276 MX6Q_PAD_CSI0_DAT8 = 250,
277 MX6Q_PAD_CSI0_DAT9 = 251,
278 MX6Q_PAD_CSI0_DAT10 = 252,
279 MX6Q_PAD_CSI0_DAT11 = 253,
280 MX6Q_PAD_CSI0_DAT12 = 254,
281 MX6Q_PAD_CSI0_DAT13 = 255,
282 MX6Q_PAD_CSI0_DAT14 = 256,
283 MX6Q_PAD_CSI0_DAT15 = 257,
284 MX6Q_PAD_CSI0_DAT16 = 258,
285 MX6Q_PAD_CSI0_DAT17 = 259,
286 MX6Q_PAD_CSI0_DAT18 = 260,
287 MX6Q_PAD_CSI0_DAT19 = 261,
288 MX6Q_PAD_JTAG_TMS = 262,
289 MX6Q_PAD_JTAG_MOD = 263,
290 MX6Q_PAD_JTAG_TRSTB = 264,
291 MX6Q_PAD_JTAG_TDI = 265,
292 MX6Q_PAD_JTAG_TCK = 266,
293 MX6Q_PAD_JTAG_TDO = 267,
294 MX6Q_PAD_LVDS1_TX3_P = 268,
295 MX6Q_PAD_LVDS1_TX2_P = 269,
296 MX6Q_PAD_LVDS1_CLK_P = 270,
297 MX6Q_PAD_LVDS1_TX1_P = 271,
298 MX6Q_PAD_LVDS1_TX0_P = 272,
299 MX6Q_PAD_LVDS0_TX3_P = 273,
300 MX6Q_PAD_LVDS0_CLK_P = 274,
301 MX6Q_PAD_LVDS0_TX2_P = 275,
302 MX6Q_PAD_LVDS0_TX1_P = 276,
303 MX6Q_PAD_LVDS0_TX0_P = 277,
304 MX6Q_PAD_TAMPER = 278,
305 MX6Q_PAD_PMIC_ON_REQ = 279,
306 MX6Q_PAD_PMIC_STBY_REQ = 280,
307 MX6Q_PAD_POR_B = 281,
308 MX6Q_PAD_BOOT_MODE1 = 282,
309 MX6Q_PAD_RESET_IN_B = 283,
310 MX6Q_PAD_BOOT_MODE0 = 284,
311 MX6Q_PAD_TEST_MODE = 285,
312 MX6Q_PAD_SD3_DAT7 = 286,
313 MX6Q_PAD_SD3_DAT6 = 287,
314 MX6Q_PAD_SD3_DAT5 = 288,
315 MX6Q_PAD_SD3_DAT4 = 289,
316 MX6Q_PAD_SD3_CMD = 290,
317 MX6Q_PAD_SD3_CLK = 291,
318 MX6Q_PAD_SD3_DAT0 = 292,
319 MX6Q_PAD_SD3_DAT1 = 293,
320 MX6Q_PAD_SD3_DAT2 = 294,
321 MX6Q_PAD_SD3_DAT3 = 295,
322 MX6Q_PAD_SD3_RST = 296,
323 MX6Q_PAD_NANDF_CLE = 297,
324 MX6Q_PAD_NANDF_ALE = 298,
325 MX6Q_PAD_NANDF_WP_B = 299,
326 MX6Q_PAD_NANDF_RB0 = 300,
327 MX6Q_PAD_NANDF_CS0 = 301,
328 MX6Q_PAD_NANDF_CS1 = 302,
329 MX6Q_PAD_NANDF_CS2 = 303,
330 MX6Q_PAD_NANDF_CS3 = 304,
331 MX6Q_PAD_SD4_CMD = 305,
332 MX6Q_PAD_SD4_CLK = 306,
333 MX6Q_PAD_NANDF_D0 = 307,
334 MX6Q_PAD_NANDF_D1 = 308,
335 MX6Q_PAD_NANDF_D2 = 309,
336 MX6Q_PAD_NANDF_D3 = 310,
337 MX6Q_PAD_NANDF_D4 = 311,
338 MX6Q_PAD_NANDF_D5 = 312,
339 MX6Q_PAD_NANDF_D6 = 313,
340 MX6Q_PAD_NANDF_D7 = 314,
341 MX6Q_PAD_SD4_DAT0 = 315,
342 MX6Q_PAD_SD4_DAT1 = 316,
343 MX6Q_PAD_SD4_DAT2 = 317,
344 MX6Q_PAD_SD4_DAT3 = 318,
345 MX6Q_PAD_SD4_DAT4 = 319,
346 MX6Q_PAD_SD4_DAT5 = 320,
347 MX6Q_PAD_SD4_DAT6 = 321,
348 MX6Q_PAD_SD4_DAT7 = 322,
349 MX6Q_PAD_SD1_DAT1 = 323,
350 MX6Q_PAD_SD1_DAT0 = 324,
351 MX6Q_PAD_SD1_DAT3 = 325,
352 MX6Q_PAD_SD1_CMD = 326,
353 MX6Q_PAD_SD1_DAT2 = 327,
354 MX6Q_PAD_SD1_CLK = 328,
355 MX6Q_PAD_SD2_CLK = 329,
356 MX6Q_PAD_SD2_CMD = 330,
357 MX6Q_PAD_SD2_DAT3 = 331,
358};
359
360/* imx6q register maps */
361static struct imx_pin_reg imx6q_pin_regs[] = {
362 IMX_PIN_REG(MX6Q_PAD_SD2_DAT1, 0x0360, 0x004C, 0, 0x0000, 0), /* MX6Q_PAD_SD2_DAT1__USDHC2_DAT1 */
363 IMX_PIN_REG(MX6Q_PAD_SD2_DAT1, 0x0360, 0x004C, 1, 0x0834, 0), /* MX6Q_PAD_SD2_DAT1__ECSPI5_SS0 */
364 IMX_PIN_REG(MX6Q_PAD_SD2_DAT1, 0x0360, 0x004C, 2, 0x0000, 0), /* MX6Q_PAD_SD2_DAT1__WEIM_WEIM_CS_2 */
365 IMX_PIN_REG(MX6Q_PAD_SD2_DAT1, 0x0360, 0x004C, 3, 0x07C8, 0), /* MX6Q_PAD_SD2_DAT1__AUDMUX_AUD4_TXFS */
366 IMX_PIN_REG(MX6Q_PAD_SD2_DAT1, 0x0360, 0x004C, 4, 0x08F0, 0), /* MX6Q_PAD_SD2_DAT1__KPP_COL_7 */
367 IMX_PIN_REG(MX6Q_PAD_SD2_DAT1, 0x0360, 0x004C, 5, 0x0000, 0), /* MX6Q_PAD_SD2_DAT1__GPIO_1_14 */
368 IMX_PIN_REG(MX6Q_PAD_SD2_DAT1, 0x0360, 0x004C, 6, 0x0000, 0), /* MX6Q_PAD_SD2_DAT1__CCM_WAIT */
369 IMX_PIN_REG(MX6Q_PAD_SD2_DAT1, 0x0360, 0x004C, 7, 0x0000, 0), /* MX6Q_PAD_SD2_DAT1__ANATOP_TESTO_0 */
370 IMX_PIN_REG(MX6Q_PAD_SD2_DAT2, 0x0364, 0x0050, 0, 0x0000, 0), /* MX6Q_PAD_SD2_DAT2__USDHC2_DAT2 */
371 IMX_PIN_REG(MX6Q_PAD_SD2_DAT2, 0x0364, 0x0050, 1, 0x0838, 0), /* MX6Q_PAD_SD2_DAT2__ECSPI5_SS1 */
372 IMX_PIN_REG(MX6Q_PAD_SD2_DAT2, 0x0364, 0x0050, 2, 0x0000, 0), /* MX6Q_PAD_SD2_DAT2__WEIM_WEIM_CS_3 */
373 IMX_PIN_REG(MX6Q_PAD_SD2_DAT2, 0x0364, 0x0050, 3, 0x07B8, 0), /* MX6Q_PAD_SD2_DAT2__AUDMUX_AUD4_TXD */
374 IMX_PIN_REG(MX6Q_PAD_SD2_DAT2, 0x0364, 0x0050, 4, 0x08F8, 0), /* MX6Q_PAD_SD2_DAT2__KPP_ROW_6 */
375 IMX_PIN_REG(MX6Q_PAD_SD2_DAT2, 0x0364, 0x0050, 5, 0x0000, 0), /* MX6Q_PAD_SD2_DAT2__GPIO_1_13 */
376 IMX_PIN_REG(MX6Q_PAD_SD2_DAT2, 0x0364, 0x0050, 6, 0x0000, 0), /* MX6Q_PAD_SD2_DAT2__CCM_STOP */
377 IMX_PIN_REG(MX6Q_PAD_SD2_DAT2, 0x0364, 0x0050, 7, 0x0000, 0), /* MX6Q_PAD_SD2_DAT2__ANATOP_TESTO_1 */
378 IMX_PIN_REG(MX6Q_PAD_SD2_DAT0, 0x0368, 0x0054, 0, 0x0000, 0), /* MX6Q_PAD_SD2_DAT0__USDHC2_DAT0 */
379 IMX_PIN_REG(MX6Q_PAD_SD2_DAT0, 0x0368, 0x0054, 1, 0x082C, 0), /* MX6Q_PAD_SD2_DAT0__ECSPI5_MISO */
380 IMX_PIN_REG(MX6Q_PAD_SD2_DAT0, 0x0368, 0x0054, 3, 0x07B4, 0), /* MX6Q_PAD_SD2_DAT0__AUDMUX_AUD4_RXD */
381 IMX_PIN_REG(MX6Q_PAD_SD2_DAT0, 0x0368, 0x0054, 4, 0x08FC, 0), /* MX6Q_PAD_SD2_DAT0__KPP_ROW_7 */
382 IMX_PIN_REG(MX6Q_PAD_SD2_DAT0, 0x0368, 0x0054, 5, 0x0000, 0), /* MX6Q_PAD_SD2_DAT0__GPIO_1_15 */
383 IMX_PIN_REG(MX6Q_PAD_SD2_DAT0, 0x0368, 0x0054, 6, 0x0000, 0), /* MX6Q_PAD_SD2_DAT0__DCIC2_DCIC_OUT */
384 IMX_PIN_REG(MX6Q_PAD_SD2_DAT0, 0x0368, 0x0054, 7, 0x0000, 0), /* MX6Q_PAD_SD2_DAT0__TESTO_2 */
385 IMX_PIN_REG(MX6Q_PAD_RGMII_TXC, 0x036C, 0x0058, 0, 0x0000, 0), /* MX6Q_PAD_RGMII_TXC__USBOH3_H2_DATA */
386 IMX_PIN_REG(MX6Q_PAD_RGMII_TXC, 0x036C, 0x0058, 1, 0x0000, 0), /* MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC */
387 IMX_PIN_REG(MX6Q_PAD_RGMII_TXC, 0x036C, 0x0058, 2, 0x0918, 0), /* MX6Q_PAD_RGMII_TXC__SPDIF_SPDIF_EXTCLK */
388 IMX_PIN_REG(MX6Q_PAD_RGMII_TXC, 0x036C, 0x0058, 5, 0x0000, 0), /* MX6Q_PAD_RGMII_TXC__GPIO_6_19 */
389 IMX_PIN_REG(MX6Q_PAD_RGMII_TXC, 0x036C, 0x0058, 6, 0x0000, 0), /* MX6Q_PAD_RGMII_TXC__MIPI_CORE_DPHY_IN_0 */
390 IMX_PIN_REG(MX6Q_PAD_RGMII_TXC, 0x036C, 0x0058, 7, 0x0000, 0), /* MX6Q_PAD_RGMII_TXC__ANATOP_24M_OUT */
391 IMX_PIN_REG(MX6Q_PAD_RGMII_TD0, 0x0370, 0x005C, 0, 0x0000, 0), /* MX6Q_PAD_RGMII_TD0__MIPI_HSI_CRL_TX_RDY */
392 IMX_PIN_REG(MX6Q_PAD_RGMII_TD0, 0x0370, 0x005C, 1, 0x0000, 0), /* MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0 */
393 IMX_PIN_REG(MX6Q_PAD_RGMII_TD0, 0x0370, 0x005C, 5, 0x0000, 0), /* MX6Q_PAD_RGMII_TD0__GPIO_6_20 */
394 IMX_PIN_REG(MX6Q_PAD_RGMII_TD0, 0x0370, 0x005C, 6, 0x0000, 0), /* MX6Q_PAD_RGMII_TD0__MIPI_CORE_DPHY_IN_1 */
395 IMX_PIN_REG(MX6Q_PAD_RGMII_TD1, 0x0374, 0x0060, 0, 0x0000, 0), /* MX6Q_PAD_RGMII_TD1__MIPI_HSI_CRL_RX_FLG */
396 IMX_PIN_REG(MX6Q_PAD_RGMII_TD1, 0x0374, 0x0060, 1, 0x0000, 0), /* MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1 */
397 IMX_PIN_REG(MX6Q_PAD_RGMII_TD1, 0x0374, 0x0060, 5, 0x0000, 0), /* MX6Q_PAD_RGMII_TD1__GPIO_6_21 */
398 IMX_PIN_REG(MX6Q_PAD_RGMII_TD1, 0x0374, 0x0060, 6, 0x0000, 0), /* MX6Q_PAD_RGMII_TD1__MIPI_CORE_DPHY_IN_2 */
399 IMX_PIN_REG(MX6Q_PAD_RGMII_TD1, 0x0374, 0x0060, 7, 0x0000, 0), /* MX6Q_PAD_RGMII_TD1__CCM_PLL3_BYP */
400 IMX_PIN_REG(MX6Q_PAD_RGMII_TD2, 0x0378, 0x0064, 0, 0x0000, 0), /* MX6Q_PAD_RGMII_TD2__MIPI_HSI_CRL_RX_DTA */
401 IMX_PIN_REG(MX6Q_PAD_RGMII_TD2, 0x0378, 0x0064, 1, 0x0000, 0), /* MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2 */
402 IMX_PIN_REG(MX6Q_PAD_RGMII_TD2, 0x0378, 0x0064, 5, 0x0000, 0), /* MX6Q_PAD_RGMII_TD2__GPIO_6_22 */
403 IMX_PIN_REG(MX6Q_PAD_RGMII_TD2, 0x0378, 0x0064, 6, 0x0000, 0), /* MX6Q_PAD_RGMII_TD2__MIPI_CORE_DPHY_IN_3 */
404 IMX_PIN_REG(MX6Q_PAD_RGMII_TD2, 0x0378, 0x0064, 7, 0x0000, 0), /* MX6Q_PAD_RGMII_TD2__CCM_PLL2_BYP */
405 IMX_PIN_REG(MX6Q_PAD_RGMII_TD3, 0x037C, 0x0068, 0, 0x0000, 0), /* MX6Q_PAD_RGMII_TD3__MIPI_HSI_CRL_RX_WAK */
406 IMX_PIN_REG(MX6Q_PAD_RGMII_TD3, 0x037C, 0x0068, 1, 0x0000, 0), /* MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3 */
407 IMX_PIN_REG(MX6Q_PAD_RGMII_TD3, 0x037C, 0x0068, 5, 0x0000, 0), /* MX6Q_PAD_RGMII_TD3__GPIO_6_23 */
408 IMX_PIN_REG(MX6Q_PAD_RGMII_TD3, 0x037C, 0x0068, 6, 0x0000, 0), /* MX6Q_PAD_RGMII_TD3__MIPI_CORE_DPHY_IN_4 */
409 IMX_PIN_REG(MX6Q_PAD_RGMII_RX_CTL, 0x0380, 0x006C, 0, 0x0000, 0), /* MX6Q_PAD_RGMII_RX_CTL__USBOH3_H3_DATA */
410 IMX_PIN_REG(MX6Q_PAD_RGMII_RX_CTL, 0x0380, 0x006C, 1, 0x0858, 0), /* MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL */
411 IMX_PIN_REG(MX6Q_PAD_RGMII_RX_CTL, 0x0380, 0x006C, 5, 0x0000, 0), /* MX6Q_PAD_RGMII_RX_CTL__GPIO_6_24 */
412 IMX_PIN_REG(MX6Q_PAD_RGMII_RX_CTL, 0x0380, 0x006C, 6, 0x0000, 0), /* MX6Q_PAD_RGMII_RX_CTL__MIPI_DPHY_IN_5 */
413 IMX_PIN_REG(MX6Q_PAD_RGMII_RD0, 0x0384, 0x0070, 0, 0x0000, 0), /* MX6Q_PAD_RGMII_RD0__MIPI_HSI_CRL_RX_RDY */
414 IMX_PIN_REG(MX6Q_PAD_RGMII_RD0, 0x0384, 0x0070, 1, 0x0848, 0), /* MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0 */
415 IMX_PIN_REG(MX6Q_PAD_RGMII_RD0, 0x0384, 0x0070, 5, 0x0000, 0), /* MX6Q_PAD_RGMII_RD0__GPIO_6_25 */
416 IMX_PIN_REG(MX6Q_PAD_RGMII_RD0, 0x0384, 0x0070, 6, 0x0000, 0), /* MX6Q_PAD_RGMII_RD0__MIPI_CORE_DPHY_IN_6 */
417 IMX_PIN_REG(MX6Q_PAD_RGMII_TX_CTL, 0x0388, 0x0074, 0, 0x0000, 0), /* MX6Q_PAD_RGMII_TX_CTL__USBOH3_H2_STROBE */
418 IMX_PIN_REG(MX6Q_PAD_RGMII_TX_CTL, 0x0388, 0x0074, 1, 0x0000, 0), /* MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL */
419 IMX_PIN_REG(MX6Q_PAD_RGMII_TX_CTL, 0x0388, 0x0074, 5, 0x0000, 0), /* MX6Q_PAD_RGMII_TX_CTL__GPIO_6_26 */
420 IMX_PIN_REG(MX6Q_PAD_RGMII_TX_CTL, 0x0388, 0x0074, 6, 0x0000, 0), /* MX6Q_PAD_RGMII_TX_CTL__CORE_DPHY_IN_7 */
421 IMX_PIN_REG(MX6Q_PAD_RGMII_TX_CTL, 0x0388, 0x0074, 7, 0x083C, 0), /* MX6Q_PAD_RGMII_TX_CTL__ANATOP_REF_OUT */
422 IMX_PIN_REG(MX6Q_PAD_RGMII_RD1, 0x038C, 0x0078, 0, 0x0000, 0), /* MX6Q_PAD_RGMII_RD1__MIPI_HSI_CTRL_TX_FL */
423 IMX_PIN_REG(MX6Q_PAD_RGMII_RD1, 0x038C, 0x0078, 1, 0x084C, 0), /* MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1 */
424 IMX_PIN_REG(MX6Q_PAD_RGMII_RD1, 0x038C, 0x0078, 5, 0x0000, 0), /* MX6Q_PAD_RGMII_RD1__GPIO_6_27 */
425 IMX_PIN_REG(MX6Q_PAD_RGMII_RD1, 0x038C, 0x0078, 6, 0x0000, 0), /* MX6Q_PAD_RGMII_RD1__CORE_DPHY_TEST_IN_8 */
426 IMX_PIN_REG(MX6Q_PAD_RGMII_RD1, 0x038C, 0x0078, 7, 0x0000, 0), /* MX6Q_PAD_RGMII_RD1__SJC_FAIL */
427 IMX_PIN_REG(MX6Q_PAD_RGMII_RD2, 0x0390, 0x007C, 0, 0x0000, 0), /* MX6Q_PAD_RGMII_RD2__MIPI_HSI_CRL_TX_DTA */
428 IMX_PIN_REG(MX6Q_PAD_RGMII_RD2, 0x0390, 0x007C, 1, 0x0850, 0), /* MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2 */
429 IMX_PIN_REG(MX6Q_PAD_RGMII_RD2, 0x0390, 0x007C, 5, 0x0000, 0), /* MX6Q_PAD_RGMII_RD2__GPIO_6_28 */
430 IMX_PIN_REG(MX6Q_PAD_RGMII_RD2, 0x0390, 0x007C, 6, 0x0000, 0), /* MX6Q_PAD_RGMII_RD2__MIPI_CORE_DPHY_IN_9 */
431 IMX_PIN_REG(MX6Q_PAD_RGMII_RD3, 0x0394, 0x0080, 0, 0x0000, 0), /* MX6Q_PAD_RGMII_RD3__MIPI_HSI_CRL_TX_WAK */
432 IMX_PIN_REG(MX6Q_PAD_RGMII_RD3, 0x0394, 0x0080, 1, 0x0854, 0), /* MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3 */
433 IMX_PIN_REG(MX6Q_PAD_RGMII_RD3, 0x0394, 0x0080, 5, 0x0000, 0), /* MX6Q_PAD_RGMII_RD3__GPIO_6_29 */
434 IMX_PIN_REG(MX6Q_PAD_RGMII_RD3, 0x0394, 0x0080, 6, 0x0000, 0), /* MX6Q_PAD_RGMII_RD3__MIPI_CORE_DPHY_IN10 */
435 IMX_PIN_REG(MX6Q_PAD_RGMII_RXC, 0x0398, 0x0084, 0, 0x0000, 0), /* MX6Q_PAD_RGMII_RXC__USBOH3_H3_STROBE */
436 IMX_PIN_REG(MX6Q_PAD_RGMII_RXC, 0x0398, 0x0084, 1, 0x0844, 0), /* MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC */
437 IMX_PIN_REG(MX6Q_PAD_RGMII_RXC, 0x0398, 0x0084, 5, 0x0000, 0), /* MX6Q_PAD_RGMII_RXC__GPIO_6_30 */
438 IMX_PIN_REG(MX6Q_PAD_RGMII_RXC, 0x0398, 0x0084, 6, 0x0000, 0), /* MX6Q_PAD_RGMII_RXC__MIPI_CORE_DPHY_IN11 */
439 IMX_PIN_REG(MX6Q_PAD_EIM_A25, 0x039C, 0x0088, 0, 0x0000, 0), /* MX6Q_PAD_EIM_A25__WEIM_WEIM_A_25 */
440 IMX_PIN_REG(MX6Q_PAD_EIM_A25, 0x039C, 0x0088, 1, 0x0000, 0), /* MX6Q_PAD_EIM_A25__ECSPI4_SS1 */
441 IMX_PIN_REG(MX6Q_PAD_EIM_A25, 0x039C, 0x0088, 2, 0x0000, 0), /* MX6Q_PAD_EIM_A25__ECSPI2_RDY */
442 IMX_PIN_REG(MX6Q_PAD_EIM_A25, 0x039C, 0x0088, 3, 0x0000, 0), /* MX6Q_PAD_EIM_A25__IPU1_DI1_PIN12 */
443 IMX_PIN_REG(MX6Q_PAD_EIM_A25, 0x039C, 0x0088, 4, 0x0000, 0), /* MX6Q_PAD_EIM_A25__IPU1_DI0_D1_CS */
444 IMX_PIN_REG(MX6Q_PAD_EIM_A25, 0x039C, 0x0088, 5, 0x0000, 0), /* MX6Q_PAD_EIM_A25__GPIO_5_2 */
445 IMX_PIN_REG(MX6Q_PAD_EIM_A25, 0x039C, 0x0088, 6, 0x088C, 0), /* MX6Q_PAD_EIM_A25__HDMI_TX_CEC_LINE */
446 IMX_PIN_REG(MX6Q_PAD_EIM_A25, 0x039C, 0x0088, 7, 0x0000, 0), /* MX6Q_PAD_EIM_A25__PL301_PER1_HBURST_0 */
447 IMX_PIN_REG(MX6Q_PAD_EIM_EB2, 0x03A0, 0x008C, 0, 0x0000, 0), /* MX6Q_PAD_EIM_EB2__WEIM_WEIM_EB_2 */
448 IMX_PIN_REG(MX6Q_PAD_EIM_EB2, 0x03A0, 0x008C, 1, 0x0800, 0), /* MX6Q_PAD_EIM_EB2__ECSPI1_SS0 */
449 IMX_PIN_REG(MX6Q_PAD_EIM_EB2, 0x03A0, 0x008C, 2, 0x07EC, 0), /* MX6Q_PAD_EIM_EB2__CCM_DI1_EXT_CLK */
450 IMX_PIN_REG(MX6Q_PAD_EIM_EB2, 0x03A0, 0x008C, 3, 0x08D4, 0), /* MX6Q_PAD_EIM_EB2__IPU2_CSI1_D_19 */
451 IMX_PIN_REG(MX6Q_PAD_EIM_EB2, 0x03A0, 0x008C, 4, 0x0890, 0), /* MX6Q_PAD_EIM_EB2__HDMI_TX_DDC_SCL */
452 IMX_PIN_REG(MX6Q_PAD_EIM_EB2, 0x03A0, 0x008C, 5, 0x0000, 0), /* MX6Q_PAD_EIM_EB2__GPIO_2_30 */
453 IMX_PIN_REG(MX6Q_PAD_EIM_EB2, 0x03A0, 0x008C, 6, 0x08A0, 0), /* MX6Q_PAD_EIM_EB2__I2C2_SCL */
454 IMX_PIN_REG(MX6Q_PAD_EIM_EB2, 0x03A0, 0x008C, 7, 0x0000, 0), /* MX6Q_PAD_EIM_EB2__SRC_BT_CFG_30 */
455 IMX_PIN_REG(MX6Q_PAD_EIM_D16, 0x03A4, 0x0090, 0, 0x0000, 0), /* MX6Q_PAD_EIM_D16__WEIM_WEIM_D_16 */
456 IMX_PIN_REG(MX6Q_PAD_EIM_D16, 0x03A4, 0x0090, 1, 0x07F4, 0), /* MX6Q_PAD_EIM_D16__ECSPI1_SCLK */
457 IMX_PIN_REG(MX6Q_PAD_EIM_D16, 0x03A4, 0x0090, 2, 0x0000, 0), /* MX6Q_PAD_EIM_D16__IPU1_DI0_PIN5 */
458 IMX_PIN_REG(MX6Q_PAD_EIM_D16, 0x03A4, 0x0090, 3, 0x08D0, 0), /* MX6Q_PAD_EIM_D16__IPU2_CSI1_D_18 */
459 IMX_PIN_REG(MX6Q_PAD_EIM_D16, 0x03A4, 0x0090, 4, 0x0894, 0), /* MX6Q_PAD_EIM_D16__HDMI_TX_DDC_SDA */
460 IMX_PIN_REG(MX6Q_PAD_EIM_D16, 0x03A4, 0x0090, 5, 0x0000, 0), /* MX6Q_PAD_EIM_D16__GPIO_3_16 */
461 IMX_PIN_REG(MX6Q_PAD_EIM_D16, 0x03A4, 0x0090, 6, 0x08A4, 0), /* MX6Q_PAD_EIM_D16__I2C2_SDA */
462 IMX_PIN_REG(MX6Q_PAD_EIM_D17, 0x03A8, 0x0094, 0, 0x0000, 0), /* MX6Q_PAD_EIM_D17__WEIM_WEIM_D_17 */
463 IMX_PIN_REG(MX6Q_PAD_EIM_D17, 0x03A8, 0x0094, 1, 0x07F8, 0), /* MX6Q_PAD_EIM_D17__ECSPI1_MISO */
464 IMX_PIN_REG(MX6Q_PAD_EIM_D17, 0x03A8, 0x0094, 2, 0x0000, 0), /* MX6Q_PAD_EIM_D17__IPU1_DI0_PIN6 */
465 IMX_PIN_REG(MX6Q_PAD_EIM_D17, 0x03A8, 0x0094, 3, 0x08E0, 0), /* MX6Q_PAD_EIM_D17__IPU2_CSI1_PIXCLK */
466 IMX_PIN_REG(MX6Q_PAD_EIM_D17, 0x03A8, 0x0094, 4, 0x0000, 0), /* MX6Q_PAD_EIM_D17__DCIC1_DCIC_OUT */
467 IMX_PIN_REG(MX6Q_PAD_EIM_D17, 0x03A8, 0x0094, 5, 0x0000, 0), /* MX6Q_PAD_EIM_D17__GPIO_3_17 */
468 IMX_PIN_REG(MX6Q_PAD_EIM_D17, 0x03A8, 0x0094, 6, 0x08A8, 0), /* MX6Q_PAD_EIM_D17__I2C3_SCL */
469 IMX_PIN_REG(MX6Q_PAD_EIM_D17, 0x03A8, 0x0094, 7, 0x0000, 0), /* MX6Q_PAD_EIM_D17__PL301_PER1_HBURST_1 */
470 IMX_PIN_REG(MX6Q_PAD_EIM_D18, 0x03AC, 0x0098, 0, 0x0000, 0), /* MX6Q_PAD_EIM_D18__WEIM_WEIM_D_18 */
471 IMX_PIN_REG(MX6Q_PAD_EIM_D18, 0x03AC, 0x0098, 1, 0x07FC, 0), /* MX6Q_PAD_EIM_D18__ECSPI1_MOSI */
472 IMX_PIN_REG(MX6Q_PAD_EIM_D18, 0x03AC, 0x0098, 2, 0x0000, 0), /* MX6Q_PAD_EIM_D18__IPU1_DI0_PIN7 */
473 IMX_PIN_REG(MX6Q_PAD_EIM_D18, 0x03AC, 0x0098, 3, 0x08CC, 0), /* MX6Q_PAD_EIM_D18__IPU2_CSI1_D_17 */
474 IMX_PIN_REG(MX6Q_PAD_EIM_D18, 0x03AC, 0x0098, 4, 0x0000, 0), /* MX6Q_PAD_EIM_D18__IPU1_DI1_D0_CS */
475 IMX_PIN_REG(MX6Q_PAD_EIM_D18, 0x03AC, 0x0098, 5, 0x0000, 0), /* MX6Q_PAD_EIM_D18__GPIO_3_18 */
476 IMX_PIN_REG(MX6Q_PAD_EIM_D18, 0x03AC, 0x0098, 6, 0x08AC, 0), /* MX6Q_PAD_EIM_D18__I2C3_SDA */
477 IMX_PIN_REG(MX6Q_PAD_EIM_D18, 0x03AC, 0x0098, 7, 0x0000, 0), /* MX6Q_PAD_EIM_D18__PL301_PER1_HBURST_2 */
478 IMX_PIN_REG(MX6Q_PAD_EIM_D19, 0x03B0, 0x009C, 0, 0x0000, 0), /* MX6Q_PAD_EIM_D19__WEIM_WEIM_D_19 */
479 IMX_PIN_REG(MX6Q_PAD_EIM_D19, 0x03B0, 0x009C, 1, 0x0804, 0), /* MX6Q_PAD_EIM_D19__ECSPI1_SS1 */
480 IMX_PIN_REG(MX6Q_PAD_EIM_D19, 0x03B0, 0x009C, 2, 0x0000, 0), /* MX6Q_PAD_EIM_D19__IPU1_DI0_PIN8 */
481 IMX_PIN_REG(MX6Q_PAD_EIM_D19, 0x03B0, 0x009C, 3, 0x08C8, 0), /* MX6Q_PAD_EIM_D19__IPU2_CSI1_D_16 */
482 IMX_PIN_REG(MX6Q_PAD_EIM_D19, 0x03B0, 0x009C, 4, 0x091C, 0), /* MX6Q_PAD_EIM_D19__UART1_CTS */
483 IMX_PIN_REG(MX6Q_PAD_EIM_D19, 0x03B0, 0x009C, 5, 0x0000, 0), /* MX6Q_PAD_EIM_D19__GPIO_3_19 */
484 IMX_PIN_REG(MX6Q_PAD_EIM_D19, 0x03B0, 0x009C, 6, 0x0000, 0), /* MX6Q_PAD_EIM_D19__EPIT1_EPITO */
485 IMX_PIN_REG(MX6Q_PAD_EIM_D19, 0x03B0, 0x009C, 7, 0x0000, 0), /* MX6Q_PAD_EIM_D19__PL301_PER1_HRESP */
486 IMX_PIN_REG(MX6Q_PAD_EIM_D20, 0x03B4, 0x00A0, 0, 0x0000, 0), /* MX6Q_PAD_EIM_D20__WEIM_WEIM_D_20 */
487 IMX_PIN_REG(MX6Q_PAD_EIM_D20, 0x03B4, 0x00A0, 1, 0x0824, 0), /* MX6Q_PAD_EIM_D20__ECSPI4_SS0 */
488 IMX_PIN_REG(MX6Q_PAD_EIM_D20, 0x03B4, 0x00A0, 2, 0x0000, 0), /* MX6Q_PAD_EIM_D20__IPU1_DI0_PIN16 */
489 IMX_PIN_REG(MX6Q_PAD_EIM_D20, 0x03B4, 0x00A0, 3, 0x08C4, 0), /* MX6Q_PAD_EIM_D20__IPU2_CSI1_D_15 */
490 IMX_PIN_REG(MX6Q_PAD_EIM_D20, 0x03B4, 0x00A0, 4, 0x091C, 1), /* MX6Q_PAD_EIM_D20__UART1_RTS */
491 IMX_PIN_REG(MX6Q_PAD_EIM_D20, 0x03B4, 0x00A0, 5, 0x0000, 0), /* MX6Q_PAD_EIM_D20__GPIO_3_20 */
492 IMX_PIN_REG(MX6Q_PAD_EIM_D20, 0x03B4, 0x00A0, 6, 0x0000, 0), /* MX6Q_PAD_EIM_D20__EPIT2_EPITO */
493 IMX_PIN_REG(MX6Q_PAD_EIM_D21, 0x03B8, 0x00A4, 0, 0x0000, 0), /* MX6Q_PAD_EIM_D21__WEIM_WEIM_D_21 */
494 IMX_PIN_REG(MX6Q_PAD_EIM_D21, 0x03B8, 0x00A4, 1, 0x0000, 0), /* MX6Q_PAD_EIM_D21__ECSPI4_SCLK */
495 IMX_PIN_REG(MX6Q_PAD_EIM_D21, 0x03B8, 0x00A4, 2, 0x0000, 0), /* MX6Q_PAD_EIM_D21__IPU1_DI0_PIN17 */
496 IMX_PIN_REG(MX6Q_PAD_EIM_D21, 0x03B8, 0x00A4, 3, 0x08B4, 0), /* MX6Q_PAD_EIM_D21__IPU2_CSI1_D_11 */
497 IMX_PIN_REG(MX6Q_PAD_EIM_D21, 0x03B8, 0x00A4, 4, 0x0944, 0), /* MX6Q_PAD_EIM_D21__USBOH3_USBOTG_OC */
498 IMX_PIN_REG(MX6Q_PAD_EIM_D21, 0x03B8, 0x00A4, 5, 0x0000, 0), /* MX6Q_PAD_EIM_D21__GPIO_3_21 */
499 IMX_PIN_REG(MX6Q_PAD_EIM_D21, 0x03B8, 0x00A4, 6, 0x0898, 0), /* MX6Q_PAD_EIM_D21__I2C1_SCL */
500 IMX_PIN_REG(MX6Q_PAD_EIM_D21, 0x03B8, 0x00A4, 7, 0x0914, 0), /* MX6Q_PAD_EIM_D21__SPDIF_IN1 */
501 IMX_PIN_REG(MX6Q_PAD_EIM_D22, 0x03BC, 0x00A8, 0, 0x0000, 0), /* MX6Q_PAD_EIM_D22__WEIM_WEIM_D_22 */
502 IMX_PIN_REG(MX6Q_PAD_EIM_D22, 0x03BC, 0x00A8, 1, 0x0000, 0), /* MX6Q_PAD_EIM_D22__ECSPI4_MISO */
503 IMX_PIN_REG(MX6Q_PAD_EIM_D22, 0x03BC, 0x00A8, 2, 0x0000, 0), /* MX6Q_PAD_EIM_D22__IPU1_DI0_PIN1 */
504 IMX_PIN_REG(MX6Q_PAD_EIM_D22, 0x03BC, 0x00A8, 3, 0x08B0, 0), /* MX6Q_PAD_EIM_D22__IPU2_CSI1_D_10 */
505 IMX_PIN_REG(MX6Q_PAD_EIM_D22, 0x03BC, 0x00A8, 4, 0x0000, 0), /* MX6Q_PAD_EIM_D22__USBOH3_USBOTG_PWR */
506 IMX_PIN_REG(MX6Q_PAD_EIM_D22, 0x03BC, 0x00A8, 5, 0x0000, 0), /* MX6Q_PAD_EIM_D22__GPIO_3_22 */
507 IMX_PIN_REG(MX6Q_PAD_EIM_D22, 0x03BC, 0x00A8, 6, 0x0000, 0), /* MX6Q_PAD_EIM_D22__SPDIF_OUT1 */
508 IMX_PIN_REG(MX6Q_PAD_EIM_D22, 0x03BC, 0x00A8, 7, 0x0000, 0), /* MX6Q_PAD_EIM_D22__PL301_PER1_HWRITE */
509 IMX_PIN_REG(MX6Q_PAD_EIM_D23, 0x03C0, 0x00AC, 0, 0x0000, 0), /* MX6Q_PAD_EIM_D23__WEIM_WEIM_D_23 */
510 IMX_PIN_REG(MX6Q_PAD_EIM_D23, 0x03C0, 0x00AC, 1, 0x0000, 0), /* MX6Q_PAD_EIM_D23__IPU1_DI0_D0_CS */
511 IMX_PIN_REG(MX6Q_PAD_EIM_D23, 0x03C0, 0x00AC, 2, 0x092C, 0), /* MX6Q_PAD_EIM_D23__UART3_CTS */
512 IMX_PIN_REG(MX6Q_PAD_EIM_D23, 0x03C0, 0x00AC, 3, 0x0000, 0), /* MX6Q_PAD_EIM_D23__UART1_DCD */
513 IMX_PIN_REG(MX6Q_PAD_EIM_D23, 0x03C0, 0x00AC, 4, 0x08D8, 0), /* MX6Q_PAD_EIM_D23__IPU2_CSI1_DATA_EN */
514 IMX_PIN_REG(MX6Q_PAD_EIM_D23, 0x03C0, 0x00AC, 5, 0x0000, 0), /* MX6Q_PAD_EIM_D23__GPIO_3_23 */
515 IMX_PIN_REG(MX6Q_PAD_EIM_D23, 0x03C0, 0x00AC, 6, 0x0000, 0), /* MX6Q_PAD_EIM_D23__IPU1_DI1_PIN2 */
516 IMX_PIN_REG(MX6Q_PAD_EIM_D23, 0x03C0, 0x00AC, 7, 0x0000, 0), /* MX6Q_PAD_EIM_D23__IPU1_DI1_PIN14 */
517 IMX_PIN_REG(MX6Q_PAD_EIM_EB3, 0x03C4, 0x00B0, 0, 0x0000, 0), /* MX6Q_PAD_EIM_EB3__WEIM_WEIM_EB_3 */
518 IMX_PIN_REG(MX6Q_PAD_EIM_EB3, 0x03C4, 0x00B0, 1, 0x0000, 0), /* MX6Q_PAD_EIM_EB3__ECSPI4_RDY */
519 IMX_PIN_REG(MX6Q_PAD_EIM_EB3, 0x03C4, 0x00B0, 2, 0x092C, 1), /* MX6Q_PAD_EIM_EB3__UART3_RTS */
520 IMX_PIN_REG(MX6Q_PAD_EIM_EB3, 0x03C4, 0x00B0, 3, 0x0000, 0), /* MX6Q_PAD_EIM_EB3__UART1_RI */
521 IMX_PIN_REG(MX6Q_PAD_EIM_EB3, 0x03C4, 0x00B0, 4, 0x08DC, 0), /* MX6Q_PAD_EIM_EB3__IPU2_CSI1_HSYNC */
522 IMX_PIN_REG(MX6Q_PAD_EIM_EB3, 0x03C4, 0x00B0, 5, 0x0000, 0), /* MX6Q_PAD_EIM_EB3__GPIO_2_31 */
523 IMX_PIN_REG(MX6Q_PAD_EIM_EB3, 0x03C4, 0x00B0, 6, 0x0000, 0), /* MX6Q_PAD_EIM_EB3__IPU1_DI1_PIN3 */
524 IMX_PIN_REG(MX6Q_PAD_EIM_EB3, 0x03C4, 0x00B0, 7, 0x0000, 0), /* MX6Q_PAD_EIM_EB3__SRC_BT_CFG_31 */
525 IMX_PIN_REG(MX6Q_PAD_EIM_D24, 0x03C8, 0x00B4, 0, 0x0000, 0), /* MX6Q_PAD_EIM_D24__WEIM_WEIM_D_24 */
526 IMX_PIN_REG(MX6Q_PAD_EIM_D24, 0x03C8, 0x00B4, 1, 0x0000, 0), /* MX6Q_PAD_EIM_D24__ECSPI4_SS2 */
527 IMX_PIN_REG(MX6Q_PAD_EIM_D24, 0x03C8, 0x00B4, 2, 0x0000, 0), /* MX6Q_PAD_EIM_D24__UART3_TXD */
528 IMX_PIN_REG(MX6Q_PAD_EIM_D24, 0x03C8, 0x00B4, 3, 0x0808, 0), /* MX6Q_PAD_EIM_D24__ECSPI1_SS2 */
529 IMX_PIN_REG(MX6Q_PAD_EIM_D24, 0x03C8, 0x00B4, 4, 0x0000, 0), /* MX6Q_PAD_EIM_D24__ECSPI2_SS2 */
530 IMX_PIN_REG(MX6Q_PAD_EIM_D24, 0x03C8, 0x00B4, 5, 0x0000, 0), /* MX6Q_PAD_EIM_D24__GPIO_3_24 */
531 IMX_PIN_REG(MX6Q_PAD_EIM_D24, 0x03C8, 0x00B4, 6, 0x07D8, 0), /* MX6Q_PAD_EIM_D24__AUDMUX_AUD5_RXFS */
532 IMX_PIN_REG(MX6Q_PAD_EIM_D24, 0x03C8, 0x00B4, 7, 0x0000, 0), /* MX6Q_PAD_EIM_D24__UART1_DTR */
533 IMX_PIN_REG(MX6Q_PAD_EIM_D25, 0x03CC, 0x00B8, 0, 0x0000, 0), /* MX6Q_PAD_EIM_D25__WEIM_WEIM_D_25 */
534 IMX_PIN_REG(MX6Q_PAD_EIM_D25, 0x03CC, 0x00B8, 1, 0x0000, 0), /* MX6Q_PAD_EIM_D25__ECSPI4_SS3 */
535 IMX_PIN_REG(MX6Q_PAD_EIM_D25, 0x03CC, 0x00B8, 2, 0x0930, 1), /* MX6Q_PAD_EIM_D25__UART3_RXD */
536 IMX_PIN_REG(MX6Q_PAD_EIM_D25, 0x03CC, 0x00B8, 3, 0x080C, 0), /* MX6Q_PAD_EIM_D25__ECSPI1_SS3 */
537 IMX_PIN_REG(MX6Q_PAD_EIM_D25, 0x03CC, 0x00B8, 4, 0x0000, 0), /* MX6Q_PAD_EIM_D25__ECSPI2_SS3 */
538 IMX_PIN_REG(MX6Q_PAD_EIM_D25, 0x03CC, 0x00B8, 5, 0x0000, 0), /* MX6Q_PAD_EIM_D25__GPIO_3_25 */
539 IMX_PIN_REG(MX6Q_PAD_EIM_D25, 0x03CC, 0x00B8, 6, 0x07D4, 0), /* MX6Q_PAD_EIM_D25__AUDMUX_AUD5_RXC */
540 IMX_PIN_REG(MX6Q_PAD_EIM_D25, 0x03CC, 0x00B8, 7, 0x0000, 0), /* MX6Q_PAD_EIM_D25__UART1_DSR */
541 IMX_PIN_REG(MX6Q_PAD_EIM_D26, 0x03D0, 0x00BC, 0, 0x0000, 0), /* MX6Q_PAD_EIM_D26__WEIM_WEIM_D_26 */
542 IMX_PIN_REG(MX6Q_PAD_EIM_D26, 0x03D0, 0x00BC, 1, 0x0000, 0), /* MX6Q_PAD_EIM_D26__IPU1_DI1_PIN11 */
543 IMX_PIN_REG(MX6Q_PAD_EIM_D26, 0x03D0, 0x00BC, 2, 0x0000, 0), /* MX6Q_PAD_EIM_D26__IPU1_CSI0_D_1 */
544 IMX_PIN_REG(MX6Q_PAD_EIM_D26, 0x03D0, 0x00BC, 3, 0x08C0, 0), /* MX6Q_PAD_EIM_D26__IPU2_CSI1_D_14 */
545 IMX_PIN_REG(MX6Q_PAD_EIM_D26, 0x03D0, 0x00BC, 4, 0x0000, 0), /* MX6Q_PAD_EIM_D26__UART2_TXD */
546 IMX_PIN_REG(MX6Q_PAD_EIM_D26, 0x03D0, 0x00BC, 5, 0x0000, 0), /* MX6Q_PAD_EIM_D26__GPIO_3_26 */
547 IMX_PIN_REG(MX6Q_PAD_EIM_D26, 0x03D0, 0x00BC, 6, 0x0000, 0), /* MX6Q_PAD_EIM_D26__IPU1_SISG_2 */
548 IMX_PIN_REG(MX6Q_PAD_EIM_D26, 0x03D0, 0x00BC, 7, 0x0000, 0), /* MX6Q_PAD_EIM_D26__IPU1_DISP1_DAT_22 */
549 IMX_PIN_REG(MX6Q_PAD_EIM_D27, 0x03D4, 0x00C0, 0, 0x0000, 0), /* MX6Q_PAD_EIM_D27__WEIM_WEIM_D_27 */
550 IMX_PIN_REG(MX6Q_PAD_EIM_D27, 0x03D4, 0x00C0, 1, 0x0000, 0), /* MX6Q_PAD_EIM_D27__IPU1_DI1_PIN13 */
551 IMX_PIN_REG(MX6Q_PAD_EIM_D27, 0x03D4, 0x00C0, 2, 0x0000, 0), /* MX6Q_PAD_EIM_D27__IPU1_CSI0_D_0 */
552 IMX_PIN_REG(MX6Q_PAD_EIM_D27, 0x03D4, 0x00C0, 3, 0x08BC, 0), /* MX6Q_PAD_EIM_D27__IPU2_CSI1_D_13 */
553 IMX_PIN_REG(MX6Q_PAD_EIM_D27, 0x03D4, 0x00C0, 4, 0x0928, 1), /* MX6Q_PAD_EIM_D27__UART2_RXD */
554 IMX_PIN_REG(MX6Q_PAD_EIM_D27, 0x03D4, 0x00C0, 5, 0x0000, 0), /* MX6Q_PAD_EIM_D27__GPIO_3_27 */
555 IMX_PIN_REG(MX6Q_PAD_EIM_D27, 0x03D4, 0x00C0, 6, 0x0000, 0), /* MX6Q_PAD_EIM_D27__IPU1_SISG_3 */
556 IMX_PIN_REG(MX6Q_PAD_EIM_D27, 0x03D4, 0x00C0, 7, 0x0000, 0), /* MX6Q_PAD_EIM_D27__IPU1_DISP1_DAT_23 */
557 IMX_PIN_REG(MX6Q_PAD_EIM_D28, 0x03D8, 0x00C4, 0, 0x0000, 0), /* MX6Q_PAD_EIM_D28__WEIM_WEIM_D_28 */
558 IMX_PIN_REG(MX6Q_PAD_EIM_D28, 0x03D8, 0x00C4, 1, 0x089C, 0), /* MX6Q_PAD_EIM_D28__I2C1_SDA */
559 IMX_PIN_REG(MX6Q_PAD_EIM_D28, 0x03D8, 0x00C4, 2, 0x0000, 0), /* MX6Q_PAD_EIM_D28__ECSPI4_MOSI */
560 IMX_PIN_REG(MX6Q_PAD_EIM_D28, 0x03D8, 0x00C4, 3, 0x08B8, 0), /* MX6Q_PAD_EIM_D28__IPU2_CSI1_D_12 */
561 IMX_PIN_REG(MX6Q_PAD_EIM_D28, 0x03D8, 0x00C4, 4, 0x0924, 0), /* MX6Q_PAD_EIM_D28__UART2_CTS */
562 IMX_PIN_REG(MX6Q_PAD_EIM_D28, 0x03D8, 0x00C4, 5, 0x0000, 0), /* MX6Q_PAD_EIM_D28__GPIO_3_28 */
563 IMX_PIN_REG(MX6Q_PAD_EIM_D28, 0x03D8, 0x00C4, 6, 0x0000, 0), /* MX6Q_PAD_EIM_D28__IPU1_EXT_TRIG */
564 IMX_PIN_REG(MX6Q_PAD_EIM_D28, 0x03D8, 0x00C4, 7, 0x0000, 0), /* MX6Q_PAD_EIM_D28__IPU1_DI0_PIN13 */
565 IMX_PIN_REG(MX6Q_PAD_EIM_D29, 0x03DC, 0x00C8, 0, 0x0000, 0), /* MX6Q_PAD_EIM_D29__WEIM_WEIM_D_29 */
566 IMX_PIN_REG(MX6Q_PAD_EIM_D29, 0x03DC, 0x00C8, 1, 0x0000, 0), /* MX6Q_PAD_EIM_D29__IPU1_DI1_PIN15 */
567 IMX_PIN_REG(MX6Q_PAD_EIM_D29, 0x03DC, 0x00C8, 2, 0x0824, 1), /* MX6Q_PAD_EIM_D29__ECSPI4_SS0 */
568 IMX_PIN_REG(MX6Q_PAD_EIM_D29, 0x03DC, 0x00C8, 4, 0x0924, 1), /* MX6Q_PAD_EIM_D29__UART2_RTS */
569 IMX_PIN_REG(MX6Q_PAD_EIM_D29, 0x03DC, 0x00C8, 5, 0x0000, 0), /* MX6Q_PAD_EIM_D29__GPIO_3_29 */
570 IMX_PIN_REG(MX6Q_PAD_EIM_D29, 0x03DC, 0x00C8, 6, 0x08E4, 0), /* MX6Q_PAD_EIM_D29__IPU2_CSI1_VSYNC */
571 IMX_PIN_REG(MX6Q_PAD_EIM_D29, 0x03DC, 0x00C8, 7, 0x0000, 0), /* MX6Q_PAD_EIM_D29__IPU1_DI0_PIN14 */
572 IMX_PIN_REG(MX6Q_PAD_EIM_D30, 0x03E0, 0x00CC, 0, 0x0000, 0), /* MX6Q_PAD_EIM_D30__WEIM_WEIM_D_30 */
573 IMX_PIN_REG(MX6Q_PAD_EIM_D30, 0x03E0, 0x00CC, 1, 0x0000, 0), /* MX6Q_PAD_EIM_D30__IPU1_DISP1_DAT_21 */
574 IMX_PIN_REG(MX6Q_PAD_EIM_D30, 0x03E0, 0x00CC, 2, 0x0000, 0), /* MX6Q_PAD_EIM_D30__IPU1_DI0_PIN11 */
575 IMX_PIN_REG(MX6Q_PAD_EIM_D30, 0x03E0, 0x00CC, 3, 0x0000, 0), /* MX6Q_PAD_EIM_D30__IPU1_CSI0_D_3 */
576 IMX_PIN_REG(MX6Q_PAD_EIM_D30, 0x03E0, 0x00CC, 4, 0x092C, 2), /* MX6Q_PAD_EIM_D30__UART3_CTS */
577 IMX_PIN_REG(MX6Q_PAD_EIM_D30, 0x03E0, 0x00CC, 5, 0x0000, 0), /* MX6Q_PAD_EIM_D30__GPIO_3_30 */
578 IMX_PIN_REG(MX6Q_PAD_EIM_D30, 0x03E0, 0x00CC, 6, 0x0948, 0), /* MX6Q_PAD_EIM_D30__USBOH3_USBH1_OC */
579 IMX_PIN_REG(MX6Q_PAD_EIM_D30, 0x03E0, 0x00CC, 7, 0x0000, 0), /* MX6Q_PAD_EIM_D30__PL301_PER1_HPROT_0 */
580 IMX_PIN_REG(MX6Q_PAD_EIM_D31, 0x03E4, 0x00D0, 0, 0x0000, 0), /* MX6Q_PAD_EIM_D31__WEIM_WEIM_D_31 */
581 IMX_PIN_REG(MX6Q_PAD_EIM_D31, 0x03E4, 0x00D0, 1, 0x0000, 0), /* MX6Q_PAD_EIM_D31__IPU1_DISP1_DAT_20 */
582 IMX_PIN_REG(MX6Q_PAD_EIM_D31, 0x03E4, 0x00D0, 2, 0x0000, 0), /* MX6Q_PAD_EIM_D31__IPU1_DI0_PIN12 */
583 IMX_PIN_REG(MX6Q_PAD_EIM_D31, 0x03E4, 0x00D0, 3, 0x0000, 0), /* MX6Q_PAD_EIM_D31__IPU1_CSI0_D_2 */
584 IMX_PIN_REG(MX6Q_PAD_EIM_D31, 0x03E4, 0x00D0, 4, 0x092C, 3), /* MX6Q_PAD_EIM_D31__UART3_RTS */
585 IMX_PIN_REG(MX6Q_PAD_EIM_D31, 0x03E4, 0x00D0, 5, 0x0000, 0), /* MX6Q_PAD_EIM_D31__GPIO_3_31 */
586 IMX_PIN_REG(MX6Q_PAD_EIM_D31, 0x03E4, 0x00D0, 6, 0x0000, 0), /* MX6Q_PAD_EIM_D31__USBOH3_USBH1_PWR */
587 IMX_PIN_REG(MX6Q_PAD_EIM_D31, 0x03E4, 0x00D0, 7, 0x0000, 0), /* MX6Q_PAD_EIM_D31__PL301_PER1_HPROT_1 */
588 IMX_PIN_REG(MX6Q_PAD_EIM_A24, 0x03E8, 0x00D4, 0, 0x0000, 0), /* MX6Q_PAD_EIM_A24__WEIM_WEIM_A_24 */
589 IMX_PIN_REG(MX6Q_PAD_EIM_A24, 0x03E8, 0x00D4, 1, 0x0000, 0), /* MX6Q_PAD_EIM_A24__IPU1_DISP1_DAT_19 */
590 IMX_PIN_REG(MX6Q_PAD_EIM_A24, 0x03E8, 0x00D4, 2, 0x08D4, 1), /* MX6Q_PAD_EIM_A24__IPU2_CSI1_D_19 */
591 IMX_PIN_REG(MX6Q_PAD_EIM_A24, 0x03E8, 0x00D4, 3, 0x0000, 0), /* MX6Q_PAD_EIM_A24__IPU2_SISG_2 */
592 IMX_PIN_REG(MX6Q_PAD_EIM_A24, 0x03E8, 0x00D4, 4, 0x0000, 0), /* MX6Q_PAD_EIM_A24__IPU1_SISG_2 */
593 IMX_PIN_REG(MX6Q_PAD_EIM_A24, 0x03E8, 0x00D4, 5, 0x0000, 0), /* MX6Q_PAD_EIM_A24__GPIO_5_4 */
594 IMX_PIN_REG(MX6Q_PAD_EIM_A24, 0x03E8, 0x00D4, 6, 0x0000, 0), /* MX6Q_PAD_EIM_A24__PL301_PER1_HPROT_2 */
595 IMX_PIN_REG(MX6Q_PAD_EIM_A24, 0x03E8, 0x00D4, 7, 0x0000, 0), /* MX6Q_PAD_EIM_A24__SRC_BT_CFG_24 */
596 IMX_PIN_REG(MX6Q_PAD_EIM_A23, 0x03EC, 0x00D8, 0, 0x0000, 0), /* MX6Q_PAD_EIM_A23__WEIM_WEIM_A_23 */
597 IMX_PIN_REG(MX6Q_PAD_EIM_A23, 0x03EC, 0x00D8, 1, 0x0000, 0), /* MX6Q_PAD_EIM_A23__IPU1_DISP1_DAT_18 */
598 IMX_PIN_REG(MX6Q_PAD_EIM_A23, 0x03EC, 0x00D8, 2, 0x08D0, 1), /* MX6Q_PAD_EIM_A23__IPU2_CSI1_D_18 */
599 IMX_PIN_REG(MX6Q_PAD_EIM_A23, 0x03EC, 0x00D8, 3, 0x0000, 0), /* MX6Q_PAD_EIM_A23__IPU2_SISG_3 */
600 IMX_PIN_REG(MX6Q_PAD_EIM_A23, 0x03EC, 0x00D8, 4, 0x0000, 0), /* MX6Q_PAD_EIM_A23__IPU1_SISG_3 */
601 IMX_PIN_REG(MX6Q_PAD_EIM_A23, 0x03EC, 0x00D8, 5, 0x0000, 0), /* MX6Q_PAD_EIM_A23__GPIO_6_6 */
602 IMX_PIN_REG(MX6Q_PAD_EIM_A23, 0x03EC, 0x00D8, 6, 0x0000, 0), /* MX6Q_PAD_EIM_A23__PL301_PER1_HPROT_3 */
603 IMX_PIN_REG(MX6Q_PAD_EIM_A23, 0x03EC, 0x00D8, 7, 0x0000, 0), /* MX6Q_PAD_EIM_A23__SRC_BT_CFG_23 */
604 IMX_PIN_REG(MX6Q_PAD_EIM_A22, 0x03F0, 0x00DC, 0, 0x0000, 0), /* MX6Q_PAD_EIM_A22__WEIM_WEIM_A_22 */
605 IMX_PIN_REG(MX6Q_PAD_EIM_A22, 0x03F0, 0x00DC, 1, 0x0000, 0), /* MX6Q_PAD_EIM_A22__IPU1_DISP1_DAT_17 */
606 IMX_PIN_REG(MX6Q_PAD_EIM_A22, 0x03F0, 0x00DC, 2, 0x08CC, 1), /* MX6Q_PAD_EIM_A22__IPU2_CSI1_D_17 */
607 IMX_PIN_REG(MX6Q_PAD_EIM_A22, 0x03F0, 0x00DC, 5, 0x0000, 0), /* MX6Q_PAD_EIM_A22__GPIO_2_16 */
608 IMX_PIN_REG(MX6Q_PAD_EIM_A22, 0x03F0, 0x00DC, 6, 0x0000, 0), /* MX6Q_PAD_EIM_A22__TPSMP_HDATA_0 */
609 IMX_PIN_REG(MX6Q_PAD_EIM_A22, 0x03F0, 0x00DC, 7, 0x0000, 0), /* MX6Q_PAD_EIM_A22__SRC_BT_CFG_22 */
610 IMX_PIN_REG(MX6Q_PAD_EIM_A21, 0x03F4, 0x00E0, 0, 0x0000, 0), /* MX6Q_PAD_EIM_A21__WEIM_WEIM_A_21 */
611 IMX_PIN_REG(MX6Q_PAD_EIM_A21, 0x03F4, 0x00E0, 1, 0x0000, 0), /* MX6Q_PAD_EIM_A21__IPU1_DISP1_DAT_16 */
612 IMX_PIN_REG(MX6Q_PAD_EIM_A21, 0x03F4, 0x00E0, 2, 0x08C8, 1), /* MX6Q_PAD_EIM_A21__IPU2_CSI1_D_16 */
613 IMX_PIN_REG(MX6Q_PAD_EIM_A21, 0x03F4, 0x00E0, 3, 0x0000, 0), /* MX6Q_PAD_EIM_A21__RESERVED_RESERVED */
614 IMX_PIN_REG(MX6Q_PAD_EIM_A21, 0x03F4, 0x00E0, 4, 0x0000, 0), /* MX6Q_PAD_EIM_A21__MIPI_CORE_DPHY_OUT_18 */
615 IMX_PIN_REG(MX6Q_PAD_EIM_A21, 0x03F4, 0x00E0, 5, 0x0000, 0), /* MX6Q_PAD_EIM_A21__GPIO_2_17 */
616 IMX_PIN_REG(MX6Q_PAD_EIM_A21, 0x03F4, 0x00E0, 6, 0x0000, 0), /* MX6Q_PAD_EIM_A21__TPSMP_HDATA_1 */
617 IMX_PIN_REG(MX6Q_PAD_EIM_A21, 0x03F4, 0x00E0, 7, 0x0000, 0), /* MX6Q_PAD_EIM_A21__SRC_BT_CFG_21 */
618 IMX_PIN_REG(MX6Q_PAD_EIM_A20, 0x03F8, 0x00E4, 0, 0x0000, 0), /* MX6Q_PAD_EIM_A20__WEIM_WEIM_A_20 */
619 IMX_PIN_REG(MX6Q_PAD_EIM_A20, 0x03F8, 0x00E4, 1, 0x0000, 0), /* MX6Q_PAD_EIM_A20__IPU1_DISP1_DAT_15 */
620 IMX_PIN_REG(MX6Q_PAD_EIM_A20, 0x03F8, 0x00E4, 2, 0x08C4, 1), /* MX6Q_PAD_EIM_A20__IPU2_CSI1_D_15 */
621 IMX_PIN_REG(MX6Q_PAD_EIM_A20, 0x03F8, 0x00E4, 3, 0x0000, 0), /* MX6Q_PAD_EIM_A20__RESERVED_RESERVED */
622 IMX_PIN_REG(MX6Q_PAD_EIM_A20, 0x03F8, 0x00E4, 4, 0x0000, 0), /* MX6Q_PAD_EIM_A20__MIPI_CORE_DPHY_OUT_19 */
623 IMX_PIN_REG(MX6Q_PAD_EIM_A20, 0x03F8, 0x00E4, 5, 0x0000, 0), /* MX6Q_PAD_EIM_A20__GPIO_2_18 */
624 IMX_PIN_REG(MX6Q_PAD_EIM_A20, 0x03F8, 0x00E4, 6, 0x0000, 0), /* MX6Q_PAD_EIM_A20__TPSMP_HDATA_2 */
625 IMX_PIN_REG(MX6Q_PAD_EIM_A20, 0x03F8, 0x00E4, 7, 0x0000, 0), /* MX6Q_PAD_EIM_A20__SRC_BT_CFG_20 */
626 IMX_PIN_REG(MX6Q_PAD_EIM_A19, 0x03FC, 0x00E8, 0, 0x0000, 0), /* MX6Q_PAD_EIM_A19__WEIM_WEIM_A_19 */
627 IMX_PIN_REG(MX6Q_PAD_EIM_A19, 0x03FC, 0x00E8, 1, 0x0000, 0), /* MX6Q_PAD_EIM_A19__IPU1_DISP1_DAT_14 */
628 IMX_PIN_REG(MX6Q_PAD_EIM_A19, 0x03FC, 0x00E8, 2, 0x08C0, 1), /* MX6Q_PAD_EIM_A19__IPU2_CSI1_D_14 */
629 IMX_PIN_REG(MX6Q_PAD_EIM_A19, 0x03FC, 0x00E8, 3, 0x0000, 0), /* MX6Q_PAD_EIM_A19__RESERVED_RESERVED */
630 IMX_PIN_REG(MX6Q_PAD_EIM_A19, 0x03FC, 0x00E8, 4, 0x0000, 0), /* MX6Q_PAD_EIM_A19__MIPI_CORE_DPHY_OUT_20 */
631 IMX_PIN_REG(MX6Q_PAD_EIM_A19, 0x03FC, 0x00E8, 5, 0x0000, 0), /* MX6Q_PAD_EIM_A19__GPIO_2_19 */
632 IMX_PIN_REG(MX6Q_PAD_EIM_A19, 0x03FC, 0x00E8, 6, 0x0000, 0), /* MX6Q_PAD_EIM_A19__TPSMP_HDATA_3 */
633 IMX_PIN_REG(MX6Q_PAD_EIM_A19, 0x03FC, 0x00E8, 7, 0x0000, 0), /* MX6Q_PAD_EIM_A19__SRC_BT_CFG_19 */
634 IMX_PIN_REG(MX6Q_PAD_EIM_A18, 0x0400, 0x00EC, 0, 0x0000, 0), /* MX6Q_PAD_EIM_A18__WEIM_WEIM_A_18 */
635 IMX_PIN_REG(MX6Q_PAD_EIM_A18, 0x0400, 0x00EC, 1, 0x0000, 0), /* MX6Q_PAD_EIM_A18__IPU1_DISP1_DAT_13 */
636 IMX_PIN_REG(MX6Q_PAD_EIM_A18, 0x0400, 0x00EC, 2, 0x08BC, 1), /* MX6Q_PAD_EIM_A18__IPU2_CSI1_D_13 */
637 IMX_PIN_REG(MX6Q_PAD_EIM_A18, 0x0400, 0x00EC, 3, 0x0000, 0), /* MX6Q_PAD_EIM_A18__RESERVED_RESERVED */
638 IMX_PIN_REG(MX6Q_PAD_EIM_A18, 0x0400, 0x00EC, 4, 0x0000, 0), /* MX6Q_PAD_EIM_A18__MIPI_CORE_DPHY_OUT_21 */
639 IMX_PIN_REG(MX6Q_PAD_EIM_A18, 0x0400, 0x00EC, 5, 0x0000, 0), /* MX6Q_PAD_EIM_A18__GPIO_2_20 */
640 IMX_PIN_REG(MX6Q_PAD_EIM_A18, 0x0400, 0x00EC, 6, 0x0000, 0), /* MX6Q_PAD_EIM_A18__TPSMP_HDATA_4 */
641 IMX_PIN_REG(MX6Q_PAD_EIM_A18, 0x0400, 0x00EC, 7, 0x0000, 0), /* MX6Q_PAD_EIM_A18__SRC_BT_CFG_18 */
642 IMX_PIN_REG(MX6Q_PAD_EIM_A17, 0x0404, 0x00F0, 0, 0x0000, 0), /* MX6Q_PAD_EIM_A17__WEIM_WEIM_A_17 */
643 IMX_PIN_REG(MX6Q_PAD_EIM_A17, 0x0404, 0x00F0, 1, 0x0000, 0), /* MX6Q_PAD_EIM_A17__IPU1_DISP1_DAT_12 */
644 IMX_PIN_REG(MX6Q_PAD_EIM_A17, 0x0404, 0x00F0, 2, 0x08B8, 1), /* MX6Q_PAD_EIM_A17__IPU2_CSI1_D_12 */
645 IMX_PIN_REG(MX6Q_PAD_EIM_A17, 0x0404, 0x00F0, 3, 0x0000, 0), /* MX6Q_PAD_EIM_A17__RESERVED_RESERVED */
646 IMX_PIN_REG(MX6Q_PAD_EIM_A17, 0x0404, 0x00F0, 4, 0x0000, 0), /* MX6Q_PAD_EIM_A17__MIPI_CORE_DPHY_OUT_22 */
647 IMX_PIN_REG(MX6Q_PAD_EIM_A17, 0x0404, 0x00F0, 5, 0x0000, 0), /* MX6Q_PAD_EIM_A17__GPIO_2_21 */
648 IMX_PIN_REG(MX6Q_PAD_EIM_A17, 0x0404, 0x00F0, 6, 0x0000, 0), /* MX6Q_PAD_EIM_A17__TPSMP_HDATA_5 */
649 IMX_PIN_REG(MX6Q_PAD_EIM_A17, 0x0404, 0x00F0, 7, 0x0000, 0), /* MX6Q_PAD_EIM_A17__SRC_BT_CFG_17 */
650 IMX_PIN_REG(MX6Q_PAD_EIM_A16, 0x0408, 0x00F4, 0, 0x0000, 0), /* MX6Q_PAD_EIM_A16__WEIM_WEIM_A_16 */
651 IMX_PIN_REG(MX6Q_PAD_EIM_A16, 0x0408, 0x00F4, 1, 0x0000, 0), /* MX6Q_PAD_EIM_A16__IPU1_DI1_DISP_CLK */
652 IMX_PIN_REG(MX6Q_PAD_EIM_A16, 0x0408, 0x00F4, 2, 0x08E0, 1), /* MX6Q_PAD_EIM_A16__IPU2_CSI1_PIXCLK */
653 IMX_PIN_REG(MX6Q_PAD_EIM_A16, 0x0408, 0x00F4, 4, 0x0000, 0), /* MX6Q_PAD_EIM_A16__MIPI_CORE_DPHY_OUT_23 */
654 IMX_PIN_REG(MX6Q_PAD_EIM_A16, 0x0408, 0x00F4, 5, 0x0000, 0), /* MX6Q_PAD_EIM_A16__GPIO_2_22 */
655 IMX_PIN_REG(MX6Q_PAD_EIM_A16, 0x0408, 0x00F4, 6, 0x0000, 0), /* MX6Q_PAD_EIM_A16__TPSMP_HDATA_6 */
656 IMX_PIN_REG(MX6Q_PAD_EIM_A16, 0x0408, 0x00F4, 7, 0x0000, 0), /* MX6Q_PAD_EIM_A16__SRC_BT_CFG_16 */
657 IMX_PIN_REG(MX6Q_PAD_EIM_CS0, 0x040C, 0x00F8, 0, 0x0000, 0), /* MX6Q_PAD_EIM_CS0__WEIM_WEIM_CS_0 */
658 IMX_PIN_REG(MX6Q_PAD_EIM_CS0, 0x040C, 0x00F8, 1, 0x0000, 0), /* MX6Q_PAD_EIM_CS0__IPU1_DI1_PIN5 */
659 IMX_PIN_REG(MX6Q_PAD_EIM_CS0, 0x040C, 0x00F8, 2, 0x0810, 0), /* MX6Q_PAD_EIM_CS0__ECSPI2_SCLK */
660 IMX_PIN_REG(MX6Q_PAD_EIM_CS0, 0x040C, 0x00F8, 4, 0x0000, 0), /* MX6Q_PAD_EIM_CS0__MIPI_CORE_DPHY_OUT_24 */
661 IMX_PIN_REG(MX6Q_PAD_EIM_CS0, 0x040C, 0x00F8, 5, 0x0000, 0), /* MX6Q_PAD_EIM_CS0__GPIO_2_23 */
662 IMX_PIN_REG(MX6Q_PAD_EIM_CS0, 0x040C, 0x00F8, 6, 0x0000, 0), /* MX6Q_PAD_EIM_CS0__TPSMP_HDATA_7 */
663 IMX_PIN_REG(MX6Q_PAD_EIM_CS1, 0x0410, 0x00FC, 0, 0x0000, 0), /* MX6Q_PAD_EIM_CS1__WEIM_WEIM_CS_1 */
664 IMX_PIN_REG(MX6Q_PAD_EIM_CS1, 0x0410, 0x00FC, 1, 0x0000, 0), /* MX6Q_PAD_EIM_CS1__IPU1_DI1_PIN6 */
665 IMX_PIN_REG(MX6Q_PAD_EIM_CS1, 0x0410, 0x00FC, 2, 0x0818, 0), /* MX6Q_PAD_EIM_CS1__ECSPI2_MOSI */
666 IMX_PIN_REG(MX6Q_PAD_EIM_CS1, 0x0410, 0x00FC, 4, 0x0000, 0), /* MX6Q_PAD_EIM_CS1__MIPI_CORE_DPHY_OUT_25 */
667 IMX_PIN_REG(MX6Q_PAD_EIM_CS1, 0x0410, 0x00FC, 5, 0x0000, 0), /* MX6Q_PAD_EIM_CS1__GPIO_2_24 */
668 IMX_PIN_REG(MX6Q_PAD_EIM_CS1, 0x0410, 0x00FC, 6, 0x0000, 0), /* MX6Q_PAD_EIM_CS1__TPSMP_HDATA_8 */
669 IMX_PIN_REG(MX6Q_PAD_EIM_OE, 0x0414, 0x0100, 0, 0x0000, 0), /* MX6Q_PAD_EIM_OE__WEIM_WEIM_OE */
670 IMX_PIN_REG(MX6Q_PAD_EIM_OE, 0x0414, 0x0100, 1, 0x0000, 0), /* MX6Q_PAD_EIM_OE__IPU1_DI1_PIN7 */
671 IMX_PIN_REG(MX6Q_PAD_EIM_OE, 0x0414, 0x0100, 2, 0x0814, 0), /* MX6Q_PAD_EIM_OE__ECSPI2_MISO */
672 IMX_PIN_REG(MX6Q_PAD_EIM_OE, 0x0414, 0x0100, 4, 0x0000, 0), /* MX6Q_PAD_EIM_OE__MIPI_CORE_DPHY_OUT_26 */
673 IMX_PIN_REG(MX6Q_PAD_EIM_OE, 0x0414, 0x0100, 5, 0x0000, 0), /* MX6Q_PAD_EIM_OE__GPIO_2_25 */
674 IMX_PIN_REG(MX6Q_PAD_EIM_OE, 0x0414, 0x0100, 6, 0x0000, 0), /* MX6Q_PAD_EIM_OE__TPSMP_HDATA_9 */
675 IMX_PIN_REG(MX6Q_PAD_EIM_RW, 0x0418, 0x0104, 0, 0x0000, 0), /* MX6Q_PAD_EIM_RW__WEIM_WEIM_RW */
676 IMX_PIN_REG(MX6Q_PAD_EIM_RW, 0x0418, 0x0104, 1, 0x0000, 0), /* MX6Q_PAD_EIM_RW__IPU1_DI1_PIN8 */
677 IMX_PIN_REG(MX6Q_PAD_EIM_RW, 0x0418, 0x0104, 2, 0x081C, 0), /* MX6Q_PAD_EIM_RW__ECSPI2_SS0 */
678 IMX_PIN_REG(MX6Q_PAD_EIM_RW, 0x0418, 0x0104, 4, 0x0000, 0), /* MX6Q_PAD_EIM_RW__MIPI_CORE_DPHY_OUT_27 */
679 IMX_PIN_REG(MX6Q_PAD_EIM_RW, 0x0418, 0x0104, 5, 0x0000, 0), /* MX6Q_PAD_EIM_RW__GPIO_2_26 */
680 IMX_PIN_REG(MX6Q_PAD_EIM_RW, 0x0418, 0x0104, 6, 0x0000, 0), /* MX6Q_PAD_EIM_RW__TPSMP_HDATA_10 */
681 IMX_PIN_REG(MX6Q_PAD_EIM_RW, 0x0418, 0x0104, 7, 0x0000, 0), /* MX6Q_PAD_EIM_RW__SRC_BT_CFG_29 */
682 IMX_PIN_REG(MX6Q_PAD_EIM_LBA, 0x041C, 0x0108, 0, 0x0000, 0), /* MX6Q_PAD_EIM_LBA__WEIM_WEIM_LBA */
683 IMX_PIN_REG(MX6Q_PAD_EIM_LBA, 0x041C, 0x0108, 1, 0x0000, 0), /* MX6Q_PAD_EIM_LBA__IPU1_DI1_PIN17 */
684 IMX_PIN_REG(MX6Q_PAD_EIM_LBA, 0x041C, 0x0108, 2, 0x0820, 0), /* MX6Q_PAD_EIM_LBA__ECSPI2_SS1 */
685 IMX_PIN_REG(MX6Q_PAD_EIM_LBA, 0x041C, 0x0108, 5, 0x0000, 0), /* MX6Q_PAD_EIM_LBA__GPIO_2_27 */
686 IMX_PIN_REG(MX6Q_PAD_EIM_LBA, 0x041C, 0x0108, 6, 0x0000, 0), /* MX6Q_PAD_EIM_LBA__TPSMP_HDATA_11 */
687 IMX_PIN_REG(MX6Q_PAD_EIM_LBA, 0x041C, 0x0108, 7, 0x0000, 0), /* MX6Q_PAD_EIM_LBA__SRC_BT_CFG_26 */
688 IMX_PIN_REG(MX6Q_PAD_EIM_EB0, 0x0420, 0x010C, 0, 0x0000, 0), /* MX6Q_PAD_EIM_EB0__WEIM_WEIM_EB_0 */
689 IMX_PIN_REG(MX6Q_PAD_EIM_EB0, 0x0420, 0x010C, 1, 0x0000, 0), /* MX6Q_PAD_EIM_EB0__IPU1_DISP1_DAT_11 */
690 IMX_PIN_REG(MX6Q_PAD_EIM_EB0, 0x0420, 0x010C, 2, 0x08B4, 1), /* MX6Q_PAD_EIM_EB0__IPU2_CSI1_D_11 */
691 IMX_PIN_REG(MX6Q_PAD_EIM_EB0, 0x0420, 0x010C, 3, 0x0000, 0), /* MX6Q_PAD_EIM_EB0__MIPI_CORE_DPHY_OUT_0 */
692 IMX_PIN_REG(MX6Q_PAD_EIM_EB0, 0x0420, 0x010C, 4, 0x07F0, 0), /* MX6Q_PAD_EIM_EB0__CCM_PMIC_RDY */
693 IMX_PIN_REG(MX6Q_PAD_EIM_EB0, 0x0420, 0x010C, 5, 0x0000, 0), /* MX6Q_PAD_EIM_EB0__GPIO_2_28 */
694 IMX_PIN_REG(MX6Q_PAD_EIM_EB0, 0x0420, 0x010C, 6, 0x0000, 0), /* MX6Q_PAD_EIM_EB0__TPSMP_HDATA_12 */
695 IMX_PIN_REG(MX6Q_PAD_EIM_EB0, 0x0420, 0x010C, 7, 0x0000, 0), /* MX6Q_PAD_EIM_EB0__SRC_BT_CFG_27 */
696 IMX_PIN_REG(MX6Q_PAD_EIM_EB1, 0x0424, 0x0110, 0, 0x0000, 0), /* MX6Q_PAD_EIM_EB1__WEIM_WEIM_EB_1 */
697 IMX_PIN_REG(MX6Q_PAD_EIM_EB1, 0x0424, 0x0110, 1, 0x0000, 0), /* MX6Q_PAD_EIM_EB1__IPU1_DISP1_DAT_10 */
698 IMX_PIN_REG(MX6Q_PAD_EIM_EB1, 0x0424, 0x0110, 2, 0x08B0, 1), /* MX6Q_PAD_EIM_EB1__IPU2_CSI1_D_10 */
699 IMX_PIN_REG(MX6Q_PAD_EIM_EB1, 0x0424, 0x0110, 3, 0x0000, 0), /* MX6Q_PAD_EIM_EB1__MIPI_CORE_DPHY__OUT_1 */
700 IMX_PIN_REG(MX6Q_PAD_EIM_EB1, 0x0424, 0x0110, 5, 0x0000, 0), /* MX6Q_PAD_EIM_EB1__GPIO_2_29 */
701 IMX_PIN_REG(MX6Q_PAD_EIM_EB1, 0x0424, 0x0110, 6, 0x0000, 0), /* MX6Q_PAD_EIM_EB1__TPSMP_HDATA_13 */
702 IMX_PIN_REG(MX6Q_PAD_EIM_EB1, 0x0424, 0x0110, 7, 0x0000, 0), /* MX6Q_PAD_EIM_EB1__SRC_BT_CFG_28 */
703 IMX_PIN_REG(MX6Q_PAD_EIM_DA0, 0x0428, 0x0114, 0, 0x0000, 0), /* MX6Q_PAD_EIM_DA0__WEIM_WEIM_DA_A_0 */
704 IMX_PIN_REG(MX6Q_PAD_EIM_DA0, 0x0428, 0x0114, 1, 0x0000, 0), /* MX6Q_PAD_EIM_DA0__IPU1_DISP1_DAT_9 */
705 IMX_PIN_REG(MX6Q_PAD_EIM_DA0, 0x0428, 0x0114, 2, 0x0000, 0), /* MX6Q_PAD_EIM_DA0__IPU2_CSI1_D_9 */
706 IMX_PIN_REG(MX6Q_PAD_EIM_DA0, 0x0428, 0x0114, 3, 0x0000, 0), /* MX6Q_PAD_EIM_DA0__MIPI_CORE_DPHY__OUT_2 */
707 IMX_PIN_REG(MX6Q_PAD_EIM_DA0, 0x0428, 0x0114, 5, 0x0000, 0), /* MX6Q_PAD_EIM_DA0__GPIO_3_0 */
708 IMX_PIN_REG(MX6Q_PAD_EIM_DA0, 0x0428, 0x0114, 6, 0x0000, 0), /* MX6Q_PAD_EIM_DA0__TPSMP_HDATA_14 */
709 IMX_PIN_REG(MX6Q_PAD_EIM_DA0, 0x0428, 0x0114, 7, 0x0000, 0), /* MX6Q_PAD_EIM_DA0__SRC_BT_CFG_0 */
710 IMX_PIN_REG(MX6Q_PAD_EIM_DA1, 0x042C, 0x0118, 0, 0x0000, 0), /* MX6Q_PAD_EIM_DA1__WEIM_WEIM_DA_A_1 */
711 IMX_PIN_REG(MX6Q_PAD_EIM_DA1, 0x042C, 0x0118, 1, 0x0000, 0), /* MX6Q_PAD_EIM_DA1__IPU1_DISP1_DAT_8 */
712 IMX_PIN_REG(MX6Q_PAD_EIM_DA1, 0x042C, 0x0118, 2, 0x0000, 0), /* MX6Q_PAD_EIM_DA1__IPU2_CSI1_D_8 */
713 IMX_PIN_REG(MX6Q_PAD_EIM_DA1, 0x042C, 0x0118, 3, 0x0000, 0), /* MX6Q_PAD_EIM_DA1__MIPI_CORE_DPHY_OUT_3 */
714 IMX_PIN_REG(MX6Q_PAD_EIM_DA1, 0x042C, 0x0118, 4, 0x0000, 0), /* MX6Q_PAD_EIM_DA1__USBPHY1_TX_LS_MODE */
715 IMX_PIN_REG(MX6Q_PAD_EIM_DA1, 0x042C, 0x0118, 5, 0x0000, 0), /* MX6Q_PAD_EIM_DA1__GPIO_3_1 */
716 IMX_PIN_REG(MX6Q_PAD_EIM_DA1, 0x042C, 0x0118, 6, 0x0000, 0), /* MX6Q_PAD_EIM_DA1__TPSMP_HDATA_15 */
717 IMX_PIN_REG(MX6Q_PAD_EIM_DA1, 0x042C, 0x0118, 7, 0x0000, 0), /* MX6Q_PAD_EIM_DA1__SRC_BT_CFG_1 */
718 IMX_PIN_REG(MX6Q_PAD_EIM_DA2, 0x0430, 0x011C, 0, 0x0000, 0), /* MX6Q_PAD_EIM_DA2__WEIM_WEIM_DA_A_2 */
719 IMX_PIN_REG(MX6Q_PAD_EIM_DA2, 0x0430, 0x011C, 1, 0x0000, 0), /* MX6Q_PAD_EIM_DA2__IPU1_DISP1_DAT_7 */
720 IMX_PIN_REG(MX6Q_PAD_EIM_DA2, 0x0430, 0x011C, 2, 0x0000, 0), /* MX6Q_PAD_EIM_DA2__IPU2_CSI1_D_7 */
721 IMX_PIN_REG(MX6Q_PAD_EIM_DA2, 0x0430, 0x011C, 3, 0x0000, 0), /* MX6Q_PAD_EIM_DA2__MIPI_CORE_DPHY_OUT_4 */
722 IMX_PIN_REG(MX6Q_PAD_EIM_DA2, 0x0430, 0x011C, 4, 0x0000, 0), /* MX6Q_PAD_EIM_DA2__USBPHY1_TX_HS_MODE */
723 IMX_PIN_REG(MX6Q_PAD_EIM_DA2, 0x0430, 0x011C, 5, 0x0000, 0), /* MX6Q_PAD_EIM_DA2__GPIO_3_2 */
724 IMX_PIN_REG(MX6Q_PAD_EIM_DA2, 0x0430, 0x011C, 6, 0x0000, 0), /* MX6Q_PAD_EIM_DA2__TPSMP_HDATA_16 */
725 IMX_PIN_REG(MX6Q_PAD_EIM_DA2, 0x0430, 0x011C, 7, 0x0000, 0), /* MX6Q_PAD_EIM_DA2__SRC_BT_CFG_2 */
726 IMX_PIN_REG(MX6Q_PAD_EIM_DA3, 0x0434, 0x0120, 0, 0x0000, 0), /* MX6Q_PAD_EIM_DA3__WEIM_WEIM_DA_A_3 */
727 IMX_PIN_REG(MX6Q_PAD_EIM_DA3, 0x0434, 0x0120, 1, 0x0000, 0), /* MX6Q_PAD_EIM_DA3__IPU1_DISP1_DAT_6 */
728 IMX_PIN_REG(MX6Q_PAD_EIM_DA3, 0x0434, 0x0120, 2, 0x0000, 0), /* MX6Q_PAD_EIM_DA3__IPU2_CSI1_D_6 */
729 IMX_PIN_REG(MX6Q_PAD_EIM_DA3, 0x0434, 0x0120, 3, 0x0000, 0), /* MX6Q_PAD_EIM_DA3__MIPI_CORE_DPHY_OUT_5 */
730 IMX_PIN_REG(MX6Q_PAD_EIM_DA3, 0x0434, 0x0120, 4, 0x0000, 0), /* MX6Q_PAD_EIM_DA3__USBPHY1_TX_HIZ */
731 IMX_PIN_REG(MX6Q_PAD_EIM_DA3, 0x0434, 0x0120, 5, 0x0000, 0), /* MX6Q_PAD_EIM_DA3__GPIO_3_3 */
732 IMX_PIN_REG(MX6Q_PAD_EIM_DA3, 0x0434, 0x0120, 6, 0x0000, 0), /* MX6Q_PAD_EIM_DA3__TPSMP_HDATA_17 */
733 IMX_PIN_REG(MX6Q_PAD_EIM_DA3, 0x0434, 0x0120, 7, 0x0000, 0), /* MX6Q_PAD_EIM_DA3__SRC_BT_CFG_3 */
734 IMX_PIN_REG(MX6Q_PAD_EIM_DA4, 0x0438, 0x0124, 0, 0x0000, 0), /* MX6Q_PAD_EIM_DA4__WEIM_WEIM_DA_A_4 */
735 IMX_PIN_REG(MX6Q_PAD_EIM_DA4, 0x0438, 0x0124, 1, 0x0000, 0), /* MX6Q_PAD_EIM_DA4__IPU1_DISP1_DAT_5 */
736 IMX_PIN_REG(MX6Q_PAD_EIM_DA4, 0x0438, 0x0124, 2, 0x0000, 0), /* MX6Q_PAD_EIM_DA4__IPU2_CSI1_D_5 */
737 IMX_PIN_REG(MX6Q_PAD_EIM_DA4, 0x0438, 0x0124, 3, 0x0000, 0), /* MX6Q_PAD_EIM_DA4__MIPI_CORE_DPHY_OUT_6 */
738 IMX_PIN_REG(MX6Q_PAD_EIM_DA4, 0x0438, 0x0124, 4, 0x0000, 0), /* MX6Q_PAD_EIM_DA4__ANATOP_USBPHY1_TX_EN */
739 IMX_PIN_REG(MX6Q_PAD_EIM_DA4, 0x0438, 0x0124, 5, 0x0000, 0), /* MX6Q_PAD_EIM_DA4__GPIO_3_4 */
740 IMX_PIN_REG(MX6Q_PAD_EIM_DA4, 0x0438, 0x0124, 6, 0x0000, 0), /* MX6Q_PAD_EIM_DA4__TPSMP_HDATA_18 */
741 IMX_PIN_REG(MX6Q_PAD_EIM_DA4, 0x0438, 0x0124, 7, 0x0000, 0), /* MX6Q_PAD_EIM_DA4__SRC_BT_CFG_4 */
742 IMX_PIN_REG(MX6Q_PAD_EIM_DA5, 0x043C, 0x0128, 0, 0x0000, 0), /* MX6Q_PAD_EIM_DA5__WEIM_WEIM_DA_A_5 */
743 IMX_PIN_REG(MX6Q_PAD_EIM_DA5, 0x043C, 0x0128, 1, 0x0000, 0), /* MX6Q_PAD_EIM_DA5__IPU1_DISP1_DAT_4 */
744 IMX_PIN_REG(MX6Q_PAD_EIM_DA5, 0x043C, 0x0128, 2, 0x0000, 0), /* MX6Q_PAD_EIM_DA5__IPU2_CSI1_D_4 */
745 IMX_PIN_REG(MX6Q_PAD_EIM_DA5, 0x043C, 0x0128, 3, 0x0000, 0), /* MX6Q_PAD_EIM_DA5__MIPI_CORE_DPHY_OUT_7 */
746 IMX_PIN_REG(MX6Q_PAD_EIM_DA5, 0x043C, 0x0128, 4, 0x0000, 0), /* MX6Q_PAD_EIM_DA5__ANATOP_USBPHY1_TX_DP */
747 IMX_PIN_REG(MX6Q_PAD_EIM_DA5, 0x043C, 0x0128, 5, 0x0000, 0), /* MX6Q_PAD_EIM_DA5__GPIO_3_5 */
748 IMX_PIN_REG(MX6Q_PAD_EIM_DA5, 0x043C, 0x0128, 6, 0x0000, 0), /* MX6Q_PAD_EIM_DA5__TPSMP_HDATA_19 */
749 IMX_PIN_REG(MX6Q_PAD_EIM_DA5, 0x043C, 0x0128, 7, 0x0000, 0), /* MX6Q_PAD_EIM_DA5__SRC_BT_CFG_5 */
750 IMX_PIN_REG(MX6Q_PAD_EIM_DA6, 0x0440, 0x012C, 0, 0x0000, 0), /* MX6Q_PAD_EIM_DA6__WEIM_WEIM_DA_A_6 */
751 IMX_PIN_REG(MX6Q_PAD_EIM_DA6, 0x0440, 0x012C, 1, 0x0000, 0), /* MX6Q_PAD_EIM_DA6__IPU1_DISP1_DAT_3 */
752 IMX_PIN_REG(MX6Q_PAD_EIM_DA6, 0x0440, 0x012C, 2, 0x0000, 0), /* MX6Q_PAD_EIM_DA6__IPU2_CSI1_D_3 */
753 IMX_PIN_REG(MX6Q_PAD_EIM_DA6, 0x0440, 0x012C, 3, 0x0000, 0), /* MX6Q_PAD_EIM_DA6__MIPI_CORE_DPHY_OUT_8 */
754 IMX_PIN_REG(MX6Q_PAD_EIM_DA6, 0x0440, 0x012C, 4, 0x0000, 0), /* MX6Q_PAD_EIM_DA6__ANATOP_USBPHY1_TX_DN */
755 IMX_PIN_REG(MX6Q_PAD_EIM_DA6, 0x0440, 0x012C, 5, 0x0000, 0), /* MX6Q_PAD_EIM_DA6__GPIO_3_6 */
756 IMX_PIN_REG(MX6Q_PAD_EIM_DA6, 0x0440, 0x012C, 6, 0x0000, 0), /* MX6Q_PAD_EIM_DA6__TPSMP_HDATA_20 */
757 IMX_PIN_REG(MX6Q_PAD_EIM_DA6, 0x0440, 0x012C, 7, 0x0000, 0), /* MX6Q_PAD_EIM_DA6__SRC_BT_CFG_6 */
758 IMX_PIN_REG(MX6Q_PAD_EIM_DA7, 0x0444, 0x0130, 0, 0x0000, 0), /* MX6Q_PAD_EIM_DA7__WEIM_WEIM_DA_A_7 */
759 IMX_PIN_REG(MX6Q_PAD_EIM_DA7, 0x0444, 0x0130, 1, 0x0000, 0), /* MX6Q_PAD_EIM_DA7__IPU1_DISP1_DAT_2 */
760 IMX_PIN_REG(MX6Q_PAD_EIM_DA7, 0x0444, 0x0130, 2, 0x0000, 0), /* MX6Q_PAD_EIM_DA7__IPU2_CSI1_D_2 */
761 IMX_PIN_REG(MX6Q_PAD_EIM_DA7, 0x0444, 0x0130, 3, 0x0000, 0), /* MX6Q_PAD_EIM_DA7__MIPI_CORE_DPHY_OUT_9 */
762 IMX_PIN_REG(MX6Q_PAD_EIM_DA7, 0x0444, 0x0130, 5, 0x0000, 0), /* MX6Q_PAD_EIM_DA7__GPIO_3_7 */
763 IMX_PIN_REG(MX6Q_PAD_EIM_DA7, 0x0444, 0x0130, 6, 0x0000, 0), /* MX6Q_PAD_EIM_DA7__TPSMP_HDATA_21 */
764 IMX_PIN_REG(MX6Q_PAD_EIM_DA7, 0x0444, 0x0130, 7, 0x0000, 0), /* MX6Q_PAD_EIM_DA7__SRC_BT_CFG_7 */
765 IMX_PIN_REG(MX6Q_PAD_EIM_DA8, 0x0448, 0x0134, 0, 0x0000, 0), /* MX6Q_PAD_EIM_DA8__WEIM_WEIM_DA_A_8 */
766 IMX_PIN_REG(MX6Q_PAD_EIM_DA8, 0x0448, 0x0134, 1, 0x0000, 0), /* MX6Q_PAD_EIM_DA8__IPU1_DISP1_DAT_1 */
767 IMX_PIN_REG(MX6Q_PAD_EIM_DA8, 0x0448, 0x0134, 2, 0x0000, 0), /* MX6Q_PAD_EIM_DA8__IPU2_CSI1_D_1 */
768 IMX_PIN_REG(MX6Q_PAD_EIM_DA8, 0x0448, 0x0134, 3, 0x0000, 0), /* MX6Q_PAD_EIM_DA8__MIPI_CORE_DPHY_OUT_10 */
769 IMX_PIN_REG(MX6Q_PAD_EIM_DA8, 0x0448, 0x0134, 5, 0x0000, 0), /* MX6Q_PAD_EIM_DA8__GPIO_3_8 */
770 IMX_PIN_REG(MX6Q_PAD_EIM_DA8, 0x0448, 0x0134, 6, 0x0000, 0), /* MX6Q_PAD_EIM_DA8__TPSMP_HDATA_22 */
771 IMX_PIN_REG(MX6Q_PAD_EIM_DA8, 0x0448, 0x0134, 7, 0x0000, 0), /* MX6Q_PAD_EIM_DA8__SRC_BT_CFG_8 */
772 IMX_PIN_REG(MX6Q_PAD_EIM_DA9, 0x044C, 0x0138, 0, 0x0000, 0), /* MX6Q_PAD_EIM_DA9__WEIM_WEIM_DA_A_9 */
773 IMX_PIN_REG(MX6Q_PAD_EIM_DA9, 0x044C, 0x0138, 1, 0x0000, 0), /* MX6Q_PAD_EIM_DA9__IPU1_DISP1_DAT_0 */
774 IMX_PIN_REG(MX6Q_PAD_EIM_DA9, 0x044C, 0x0138, 2, 0x0000, 0), /* MX6Q_PAD_EIM_DA9__IPU2_CSI1_D_0 */
775 IMX_PIN_REG(MX6Q_PAD_EIM_DA9, 0x044C, 0x0138, 3, 0x0000, 0), /* MX6Q_PAD_EIM_DA9__MIPI_CORE_DPHY_OUT_11 */
776 IMX_PIN_REG(MX6Q_PAD_EIM_DA9, 0x044C, 0x0138, 5, 0x0000, 0), /* MX6Q_PAD_EIM_DA9__GPIO_3_9 */
777 IMX_PIN_REG(MX6Q_PAD_EIM_DA9, 0x044C, 0x0138, 6, 0x0000, 0), /* MX6Q_PAD_EIM_DA9__TPSMP_HDATA_23 */
778 IMX_PIN_REG(MX6Q_PAD_EIM_DA9, 0x044C, 0x0138, 7, 0x0000, 0), /* MX6Q_PAD_EIM_DA9__SRC_BT_CFG_9 */
779 IMX_PIN_REG(MX6Q_PAD_EIM_DA10, 0x0450, 0x013C, 0, 0x0000, 0), /* MX6Q_PAD_EIM_DA10__WEIM_WEIM_DA_A_10 */
780 IMX_PIN_REG(MX6Q_PAD_EIM_DA10, 0x0450, 0x013C, 1, 0x0000, 0), /* MX6Q_PAD_EIM_DA10__IPU1_DI1_PIN15 */
781 IMX_PIN_REG(MX6Q_PAD_EIM_DA10, 0x0450, 0x013C, 2, 0x08D8, 1), /* MX6Q_PAD_EIM_DA10__IPU2_CSI1_DATA_EN */
782 IMX_PIN_REG(MX6Q_PAD_EIM_DA10, 0x0450, 0x013C, 3, 0x0000, 0), /* MX6Q_PAD_EIM_DA10__MIPI_CORE_DPHY_OUT12 */
783 IMX_PIN_REG(MX6Q_PAD_EIM_DA10, 0x0450, 0x013C, 5, 0x0000, 0), /* MX6Q_PAD_EIM_DA10__GPIO_3_10 */
784 IMX_PIN_REG(MX6Q_PAD_EIM_DA10, 0x0450, 0x013C, 6, 0x0000, 0), /* MX6Q_PAD_EIM_DA10__TPSMP_HDATA_24 */
785 IMX_PIN_REG(MX6Q_PAD_EIM_DA10, 0x0450, 0x013C, 7, 0x0000, 0), /* MX6Q_PAD_EIM_DA10__SRC_BT_CFG_10 */
786 IMX_PIN_REG(MX6Q_PAD_EIM_DA11, 0x0454, 0x0140, 0, 0x0000, 0), /* MX6Q_PAD_EIM_DA11__WEIM_WEIM_DA_A_11 */
787 IMX_PIN_REG(MX6Q_PAD_EIM_DA11, 0x0454, 0x0140, 1, 0x0000, 0), /* MX6Q_PAD_EIM_DA11__IPU1_DI1_PIN2 */
788 IMX_PIN_REG(MX6Q_PAD_EIM_DA11, 0x0454, 0x0140, 2, 0x08DC, 1), /* MX6Q_PAD_EIM_DA11__IPU2_CSI1_HSYNC */
789 IMX_PIN_REG(MX6Q_PAD_EIM_DA11, 0x0454, 0x0140, 3, 0x0000, 0), /* MX6Q_PAD_EIM_DA11__MIPI_CORE_DPHY_OUT13 */
790 IMX_PIN_REG(MX6Q_PAD_EIM_DA11, 0x0454, 0x0140, 4, 0x0000, 0), /* MX6Q_PAD_EIM_DA11__SDMA_DBG_EVT_CHN_6 */
791 IMX_PIN_REG(MX6Q_PAD_EIM_DA11, 0x0454, 0x0140, 5, 0x0000, 0), /* MX6Q_PAD_EIM_DA11__GPIO_3_11 */
792 IMX_PIN_REG(MX6Q_PAD_EIM_DA11, 0x0454, 0x0140, 6, 0x0000, 0), /* MX6Q_PAD_EIM_DA11__TPSMP_HDATA_25 */
793 IMX_PIN_REG(MX6Q_PAD_EIM_DA11, 0x0454, 0x0140, 7, 0x0000, 0), /* MX6Q_PAD_EIM_DA11__SRC_BT_CFG_11 */
794 IMX_PIN_REG(MX6Q_PAD_EIM_DA12, 0x0458, 0x0144, 0, 0x0000, 0), /* MX6Q_PAD_EIM_DA12__WEIM_WEIM_DA_A_12 */
795 IMX_PIN_REG(MX6Q_PAD_EIM_DA12, 0x0458, 0x0144, 1, 0x0000, 0), /* MX6Q_PAD_EIM_DA12__IPU1_DI1_PIN3 */
796 IMX_PIN_REG(MX6Q_PAD_EIM_DA12, 0x0458, 0x0144, 2, 0x08E4, 1), /* MX6Q_PAD_EIM_DA12__IPU2_CSI1_VSYNC */
797 IMX_PIN_REG(MX6Q_PAD_EIM_DA12, 0x0458, 0x0144, 3, 0x0000, 0), /* MX6Q_PAD_EIM_DA12__MIPI_CORE_DPHY_OUT14 */
798 IMX_PIN_REG(MX6Q_PAD_EIM_DA12, 0x0458, 0x0144, 4, 0x0000, 0), /* MX6Q_PAD_EIM_DA12__SDMA_DEBUG_EVT_CHN_3 */
799 IMX_PIN_REG(MX6Q_PAD_EIM_DA12, 0x0458, 0x0144, 5, 0x0000, 0), /* MX6Q_PAD_EIM_DA12__GPIO_3_12 */
800 IMX_PIN_REG(MX6Q_PAD_EIM_DA12, 0x0458, 0x0144, 6, 0x0000, 0), /* MX6Q_PAD_EIM_DA12__TPSMP_HDATA_26 */
801 IMX_PIN_REG(MX6Q_PAD_EIM_DA12, 0x0458, 0x0144, 7, 0x0000, 0), /* MX6Q_PAD_EIM_DA12__SRC_BT_CFG_12 */
802 IMX_PIN_REG(MX6Q_PAD_EIM_DA13, 0x045C, 0x0148, 0, 0x0000, 0), /* MX6Q_PAD_EIM_DA13__WEIM_WEIM_DA_A_13 */
803 IMX_PIN_REG(MX6Q_PAD_EIM_DA13, 0x045C, 0x0148, 1, 0x0000, 0), /* MX6Q_PAD_EIM_DA13__IPU1_DI1_D0_CS */
804 IMX_PIN_REG(MX6Q_PAD_EIM_DA13, 0x045C, 0x0148, 2, 0x07EC, 1), /* MX6Q_PAD_EIM_DA13__CCM_DI1_EXT_CLK */
805 IMX_PIN_REG(MX6Q_PAD_EIM_DA13, 0x045C, 0x0148, 3, 0x0000, 0), /* MX6Q_PAD_EIM_DA13__MIPI_CORE_DPHY_OUT15 */
806 IMX_PIN_REG(MX6Q_PAD_EIM_DA13, 0x045C, 0x0148, 4, 0x0000, 0), /* MX6Q_PAD_EIM_DA13__SDMA_DEBUG_EVT_CHN_4 */
807 IMX_PIN_REG(MX6Q_PAD_EIM_DA13, 0x045C, 0x0148, 5, 0x0000, 0), /* MX6Q_PAD_EIM_DA13__GPIO_3_13 */
808 IMX_PIN_REG(MX6Q_PAD_EIM_DA13, 0x045C, 0x0148, 6, 0x0000, 0), /* MX6Q_PAD_EIM_DA13__TPSMP_HDATA_27 */
809 IMX_PIN_REG(MX6Q_PAD_EIM_DA13, 0x045C, 0x0148, 7, 0x0000, 0), /* MX6Q_PAD_EIM_DA13__SRC_BT_CFG_13 */
810 IMX_PIN_REG(MX6Q_PAD_EIM_DA14, 0x0460, 0x014C, 0, 0x0000, 0), /* MX6Q_PAD_EIM_DA14__WEIM_WEIM_DA_A_14 */
811 IMX_PIN_REG(MX6Q_PAD_EIM_DA14, 0x0460, 0x014C, 1, 0x0000, 0), /* MX6Q_PAD_EIM_DA14__IPU1_DI1_D1_CS */
812 IMX_PIN_REG(MX6Q_PAD_EIM_DA14, 0x0460, 0x014C, 2, 0x0000, 0), /* MX6Q_PAD_EIM_DA14__CCM_DI0_EXT_CLK */
813 IMX_PIN_REG(MX6Q_PAD_EIM_DA14, 0x0460, 0x014C, 3, 0x0000, 0), /* MX6Q_PAD_EIM_DA14__MIPI_CORE_DPHY_OUT16 */
814 IMX_PIN_REG(MX6Q_PAD_EIM_DA14, 0x0460, 0x014C, 4, 0x0000, 0), /* MX6Q_PAD_EIM_DA14__SDMA_DEBUG_EVT_CHN_5 */
815 IMX_PIN_REG(MX6Q_PAD_EIM_DA14, 0x0460, 0x014C, 5, 0x0000, 0), /* MX6Q_PAD_EIM_DA14__GPIO_3_14 */
816 IMX_PIN_REG(MX6Q_PAD_EIM_DA14, 0x0460, 0x014C, 6, 0x0000, 0), /* MX6Q_PAD_EIM_DA14__TPSMP_HDATA_28 */
817 IMX_PIN_REG(MX6Q_PAD_EIM_DA14, 0x0460, 0x014C, 7, 0x0000, 0), /* MX6Q_PAD_EIM_DA14__SRC_BT_CFG_14 */
818 IMX_PIN_REG(MX6Q_PAD_EIM_DA15, 0x0464, 0x0150, 0, 0x0000, 0), /* MX6Q_PAD_EIM_DA15__WEIM_WEIM_DA_A_15 */
819 IMX_PIN_REG(MX6Q_PAD_EIM_DA15, 0x0464, 0x0150, 1, 0x0000, 0), /* MX6Q_PAD_EIM_DA15__IPU1_DI1_PIN1 */
820 IMX_PIN_REG(MX6Q_PAD_EIM_DA15, 0x0464, 0x0150, 2, 0x0000, 0), /* MX6Q_PAD_EIM_DA15__IPU1_DI1_PIN4 */
821 IMX_PIN_REG(MX6Q_PAD_EIM_DA15, 0x0464, 0x0150, 3, 0x0000, 0), /* MX6Q_PAD_EIM_DA15__MIPI_CORE_DPHY_OUT17 */
822 IMX_PIN_REG(MX6Q_PAD_EIM_DA15, 0x0464, 0x0150, 5, 0x0000, 0), /* MX6Q_PAD_EIM_DA15__GPIO_3_15 */
823 IMX_PIN_REG(MX6Q_PAD_EIM_DA15, 0x0464, 0x0150, 6, 0x0000, 0), /* MX6Q_PAD_EIM_DA15__TPSMP_HDATA_29 */
824 IMX_PIN_REG(MX6Q_PAD_EIM_DA15, 0x0464, 0x0150, 7, 0x0000, 0), /* MX6Q_PAD_EIM_DA15__SRC_BT_CFG_15 */
825 IMX_PIN_REG(MX6Q_PAD_EIM_WAIT, 0x0468, 0x0154, 0, 0x0000, 0), /* MX6Q_PAD_EIM_WAIT__WEIM_WEIM_WAIT */
826 IMX_PIN_REG(MX6Q_PAD_EIM_WAIT, 0x0468, 0x0154, 1, 0x0000, 0), /* MX6Q_PAD_EIM_WAIT__WEIM_WEIM_DTACK_B */
827 IMX_PIN_REG(MX6Q_PAD_EIM_WAIT, 0x0468, 0x0154, 5, 0x0000, 0), /* MX6Q_PAD_EIM_WAIT__GPIO_5_0 */
828 IMX_PIN_REG(MX6Q_PAD_EIM_WAIT, 0x0468, 0x0154, 6, 0x0000, 0), /* MX6Q_PAD_EIM_WAIT__TPSMP_HDATA_30 */
829 IMX_PIN_REG(MX6Q_PAD_EIM_WAIT, 0x0468, 0x0154, 7, 0x0000, 0), /* MX6Q_PAD_EIM_WAIT__SRC_BT_CFG_25 */
830 IMX_PIN_REG(MX6Q_PAD_EIM_BCLK, 0x046C, 0x0158, 0, 0x0000, 0), /* MX6Q_PAD_EIM_BCLK__WEIM_WEIM_BCLK */
831 IMX_PIN_REG(MX6Q_PAD_EIM_BCLK, 0x046C, 0x0158, 1, 0x0000, 0), /* MX6Q_PAD_EIM_BCLK__IPU1_DI1_PIN16 */
832 IMX_PIN_REG(MX6Q_PAD_EIM_BCLK, 0x046C, 0x0158, 5, 0x0000, 0), /* MX6Q_PAD_EIM_BCLK__GPIO_6_31 */
833 IMX_PIN_REG(MX6Q_PAD_EIM_BCLK, 0x046C, 0x0158, 6, 0x0000, 0), /* MX6Q_PAD_EIM_BCLK__TPSMP_HDATA_31 */
834 IMX_PIN_REG(MX6Q_PAD_DI0_DISP_CLK, 0x0470, 0x015C, 0, 0x0000, 0), /* MX6Q_PAD_DI0_DISP_CLK__IPU1_DI0_DSP_CLK */
835 IMX_PIN_REG(MX6Q_PAD_DI0_DISP_CLK, 0x0470, 0x015C, 1, 0x0000, 0), /* MX6Q_PAD_DI0_DISP_CLK__IPU2_DI0_DSP_CLK */
836 IMX_PIN_REG(MX6Q_PAD_DI0_DISP_CLK, 0x0470, 0x015C, 3, 0x0000, 0), /* MX6Q_PAD_DI0_DISP_CLK__MIPI_CR_DPY_OT28 */
837 IMX_PIN_REG(MX6Q_PAD_DI0_DISP_CLK, 0x0470, 0x015C, 4, 0x0000, 0), /* MX6Q_PAD_DI0_DISP_CLK__SDMA_DBG_CR_STA0 */
838 IMX_PIN_REG(MX6Q_PAD_DI0_DISP_CLK, 0x0470, 0x015C, 5, 0x0000, 0), /* MX6Q_PAD_DI0_DISP_CLK__GPIO_4_16 */
839 IMX_PIN_REG(MX6Q_PAD_DI0_DISP_CLK, 0x0470, 0x015C, 6, 0x0000, 0), /* MX6Q_PAD_DI0_DISP_CLK__MMDC_DEBUG_0 */
840 IMX_PIN_REG(MX6Q_PAD_DI0_PIN15, 0x0474, 0x0160, 0, 0x0000, 0), /* MX6Q_PAD_DI0_PIN15__IPU1_DI0_PIN15 */
841 IMX_PIN_REG(MX6Q_PAD_DI0_PIN15, 0x0474, 0x0160, 1, 0x0000, 0), /* MX6Q_PAD_DI0_PIN15__IPU2_DI0_PIN15 */
842 IMX_PIN_REG(MX6Q_PAD_DI0_PIN15, 0x0474, 0x0160, 2, 0x0000, 0), /* MX6Q_PAD_DI0_PIN15__AUDMUX_AUD6_TXC */
843 IMX_PIN_REG(MX6Q_PAD_DI0_PIN15, 0x0474, 0x0160, 3, 0x0000, 0), /* MX6Q_PAD_DI0_PIN15__MIPI_CR_DPHY_OUT_29 */
844 IMX_PIN_REG(MX6Q_PAD_DI0_PIN15, 0x0474, 0x0160, 4, 0x0000, 0), /* MX6Q_PAD_DI0_PIN15__SDMA_DBG_CORE_STA_1 */
845 IMX_PIN_REG(MX6Q_PAD_DI0_PIN15, 0x0474, 0x0160, 5, 0x0000, 0), /* MX6Q_PAD_DI0_PIN15__GPIO_4_17 */
846 IMX_PIN_REG(MX6Q_PAD_DI0_PIN15, 0x0474, 0x0160, 6, 0x0000, 0), /* MX6Q_PAD_DI0_PIN15__MMDC_MMDC_DEBUG_1 */
847 IMX_PIN_REG(MX6Q_PAD_DI0_PIN2, 0x0478, 0x0164, 0, 0x0000, 0), /* MX6Q_PAD_DI0_PIN2__IPU1_DI0_PIN2 */
848 IMX_PIN_REG(MX6Q_PAD_DI0_PIN2, 0x0478, 0x0164, 1, 0x0000, 0), /* MX6Q_PAD_DI0_PIN2__IPU2_DI0_PIN2 */
849 IMX_PIN_REG(MX6Q_PAD_DI0_PIN2, 0x0478, 0x0164, 2, 0x0000, 0), /* MX6Q_PAD_DI0_PIN2__AUDMUX_AUD6_TXD */
850 IMX_PIN_REG(MX6Q_PAD_DI0_PIN2, 0x0478, 0x0164, 3, 0x0000, 0), /* MX6Q_PAD_DI0_PIN2__MIPI_CR_DPHY_OUT_30 */
851 IMX_PIN_REG(MX6Q_PAD_DI0_PIN2, 0x0478, 0x0164, 4, 0x0000, 0), /* MX6Q_PAD_DI0_PIN2__SDMA_DBG_CORE_STA_2 */
852 IMX_PIN_REG(MX6Q_PAD_DI0_PIN2, 0x0478, 0x0164, 5, 0x0000, 0), /* MX6Q_PAD_DI0_PIN2__GPIO_4_18 */
853 IMX_PIN_REG(MX6Q_PAD_DI0_PIN2, 0x0478, 0x0164, 6, 0x0000, 0), /* MX6Q_PAD_DI0_PIN2__MMDC_DEBUG_2 */
854 IMX_PIN_REG(MX6Q_PAD_DI0_PIN2, 0x0478, 0x0164, 7, 0x0000, 0), /* MX6Q_PAD_DI0_PIN2__PL301_PER1_HADDR_9 */
855 IMX_PIN_REG(MX6Q_PAD_DI0_PIN3, 0x047C, 0x0168, 0, 0x0000, 0), /* MX6Q_PAD_DI0_PIN3__IPU1_DI0_PIN3 */
856 IMX_PIN_REG(MX6Q_PAD_DI0_PIN3, 0x047C, 0x0168, 1, 0x0000, 0), /* MX6Q_PAD_DI0_PIN3__IPU2_DI0_PIN3 */
857 IMX_PIN_REG(MX6Q_PAD_DI0_PIN3, 0x047C, 0x0168, 2, 0x0000, 0), /* MX6Q_PAD_DI0_PIN3__AUDMUX_AUD6_TXFS */
858 IMX_PIN_REG(MX6Q_PAD_DI0_PIN3, 0x047C, 0x0168, 3, 0x0000, 0), /* MX6Q_PAD_DI0_PIN3__MIPI_CORE_DPHY_OUT31 */
859 IMX_PIN_REG(MX6Q_PAD_DI0_PIN3, 0x047C, 0x0168, 4, 0x0000, 0), /* MX6Q_PAD_DI0_PIN3__SDMA_DBG_CORE_STA_3 */
860 IMX_PIN_REG(MX6Q_PAD_DI0_PIN3, 0x047C, 0x0168, 5, 0x0000, 0), /* MX6Q_PAD_DI0_PIN3__GPIO_4_19 */
861 IMX_PIN_REG(MX6Q_PAD_DI0_PIN3, 0x047C, 0x0168, 6, 0x0000, 0), /* MX6Q_PAD_DI0_PIN3__MMDC_MMDC_DEBUG_3 */
862 IMX_PIN_REG(MX6Q_PAD_DI0_PIN3, 0x047C, 0x0168, 7, 0x0000, 0), /* MX6Q_PAD_DI0_PIN3__PL301_PER1_HADDR_10 */
863 IMX_PIN_REG(MX6Q_PAD_DI0_PIN4, 0x0480, 0x016C, 0, 0x0000, 0), /* MX6Q_PAD_DI0_PIN4__IPU1_DI0_PIN4 */
864 IMX_PIN_REG(MX6Q_PAD_DI0_PIN4, 0x0480, 0x016C, 1, 0x0000, 0), /* MX6Q_PAD_DI0_PIN4__IPU2_DI0_PIN4 */
865 IMX_PIN_REG(MX6Q_PAD_DI0_PIN4, 0x0480, 0x016C, 2, 0x0000, 0), /* MX6Q_PAD_DI0_PIN4__AUDMUX_AUD6_RXD */
866 IMX_PIN_REG(MX6Q_PAD_DI0_PIN4, 0x0480, 0x016C, 3, 0x094C, 0), /* MX6Q_PAD_DI0_PIN4__USDHC1_WP */
867 IMX_PIN_REG(MX6Q_PAD_DI0_PIN4, 0x0480, 0x016C, 4, 0x0000, 0), /* MX6Q_PAD_DI0_PIN4__SDMA_DEBUG_YIELD */
868 IMX_PIN_REG(MX6Q_PAD_DI0_PIN4, 0x0480, 0x016C, 5, 0x0000, 0), /* MX6Q_PAD_DI0_PIN4__GPIO_4_20 */
869 IMX_PIN_REG(MX6Q_PAD_DI0_PIN4, 0x0480, 0x016C, 6, 0x0000, 0), /* MX6Q_PAD_DI0_PIN4__MMDC_MMDC_DEBUG_4 */
870 IMX_PIN_REG(MX6Q_PAD_DI0_PIN4, 0x0480, 0x016C, 7, 0x0000, 0), /* MX6Q_PAD_DI0_PIN4__PL301_PER1_HADDR_11 */
871 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT0, 0x0484, 0x0170, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0 */
872 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT0, 0x0484, 0x0170, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT0__IPU2_DISP0_DAT_0 */
873 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT0, 0x0484, 0x0170, 2, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT0__ECSPI3_SCLK */
874 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT0, 0x0484, 0x0170, 3, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT0__USDHC1_USDHC_DBG_0 */
875 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT0, 0x0484, 0x0170, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT0__SDMA_DBG_CORE_RUN */
876 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT0, 0x0484, 0x0170, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT0__GPIO_4_21 */
877 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT0, 0x0484, 0x0170, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT0__MMDC_MMDC_DEBUG_5 */
878 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT1, 0x0488, 0x0174, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1 */
879 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT1, 0x0488, 0x0174, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT1__IPU2_DISP0_DAT_1 */
880 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT1, 0x0488, 0x0174, 2, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT1__ECSPI3_MOSI */
881 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT1, 0x0488, 0x0174, 3, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT1__USDHC1_USDHC_DBG_1 */
882 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT1, 0x0488, 0x0174, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT1__SDMA_DBG_EVT_CHNSL */
883 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT1, 0x0488, 0x0174, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT1__GPIO_4_22 */
884 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT1, 0x0488, 0x0174, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT1__MMDC_DEBUG_6 */
885 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT1, 0x0488, 0x0174, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT1__PL301_PER1_HADR_12 */
886 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT2, 0x048C, 0x0178, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2 */
887 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT2, 0x048C, 0x0178, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT2__IPU2_DISP0_DAT_2 */
888 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT2, 0x048C, 0x0178, 2, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT2__ECSPI3_MISO */
889 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT2, 0x048C, 0x0178, 3, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT2__USDHC1_USDHC_DBG_2 */
890 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT2, 0x048C, 0x0178, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT2__SDMA_DEBUG_MODE */
891 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT2, 0x048C, 0x0178, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT2__GPIO_4_23 */
892 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT2, 0x048C, 0x0178, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT2__MMDC_DEBUG_7 */
893 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT2, 0x048C, 0x0178, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT2__PL301_PER1_HADR_13 */
894 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT3, 0x0490, 0x017C, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3 */
895 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT3, 0x0490, 0x017C, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT3__IPU2_DISP0_DAT_3 */
896 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT3, 0x0490, 0x017C, 2, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT3__ECSPI3_SS0 */
897 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT3, 0x0490, 0x017C, 3, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT3__USDHC1_USDHC_DBG_3 */
898 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT3, 0x0490, 0x017C, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT3__SDMA_DBG_BUS_ERROR */
899 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT3, 0x0490, 0x017C, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT3__GPIO_4_24 */
900 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT3, 0x0490, 0x017C, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT3__MMDC_MMDC_DBG_8 */
901 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT3, 0x0490, 0x017C, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT3__PL301_PER1_HADR_14 */
902 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT4, 0x0494, 0x0180, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4 */
903 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT4, 0x0494, 0x0180, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT4__IPU2_DISP0_DAT_4 */
904 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT4, 0x0494, 0x0180, 2, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT4__ECSPI3_SS1 */
905 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT4, 0x0494, 0x0180, 3, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT4__USDHC1_USDHC_DBG_4 */
906 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT4, 0x0494, 0x0180, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT4__SDMA_DEBUG_BUS_RWB */
907 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT4, 0x0494, 0x0180, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT4__GPIO_4_25 */
908 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT4, 0x0494, 0x0180, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT4__MMDC_MMDC_DEBUG_9 */
909 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT4, 0x0494, 0x0180, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT4__PL301_PER1_HADR_15 */
910 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT5, 0x0498, 0x0184, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5 */
911 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT5, 0x0498, 0x0184, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT5__IPU2_DISP0_DAT_5 */
912 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT5, 0x0498, 0x0184, 2, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT5__ECSPI3_SS2 */
913 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT5, 0x0498, 0x0184, 3, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT5__AUDMUX_AUD6_RXFS */
914 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT5, 0x0498, 0x0184, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT5__SDMA_DBG_MCH_DMBUS */
915 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT5, 0x0498, 0x0184, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT5__GPIO_4_26 */
916 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT5, 0x0498, 0x0184, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT5__MMDC_DEBUG_10 */
917 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT5, 0x0498, 0x0184, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT5__PL301_PER1_HADR_16 */
918 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT6, 0x049C, 0x0188, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6 */
919 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT6, 0x049C, 0x0188, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT6__IPU2_DISP0_DAT_6 */
920 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT6, 0x049C, 0x0188, 2, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT6__ECSPI3_SS3 */
921 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT6, 0x049C, 0x0188, 3, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT6__AUDMUX_AUD6_RXC */
922 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT6, 0x049C, 0x0188, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT6__SDMA_DBG_RTBUF_WRT */
923 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT6, 0x049C, 0x0188, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT6__GPIO_4_27 */
924 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT6, 0x049C, 0x0188, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT6__MMDC_DEBUG_11 */
925 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT6, 0x049C, 0x0188, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT6__PL301_PER1_HADR_17 */
926 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT7, 0x04A0, 0x018C, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7 */
927 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT7, 0x04A0, 0x018C, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT7__IPU2_DISP0_DAT_7 */
928 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT7, 0x04A0, 0x018C, 2, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT7__ECSPI3_RDY */
929 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT7, 0x04A0, 0x018C, 3, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT7__USDHC1_USDHC_DBG_5 */
930 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT7, 0x04A0, 0x018C, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT7__SDMA_DBG_EVT_CHN_0 */
931 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT7, 0x04A0, 0x018C, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT7__GPIO_4_28 */
932 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT7, 0x04A0, 0x018C, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT7__MMDC_DEBUG_12 */
933 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT7, 0x04A0, 0x018C, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT7__PL301_PER1_HADR_18 */
934 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT8, 0x04A4, 0x0190, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8 */
935 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT8, 0x04A4, 0x0190, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT8__IPU2_DISP0_DAT_8 */
936 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT8, 0x04A4, 0x0190, 2, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT8__PWM1_PWMO */
937 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT8, 0x04A4, 0x0190, 3, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT8__WDOG1_WDOG_B */
938 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT8, 0x04A4, 0x0190, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT8__SDMA_DBG_EVT_CHN_1 */
939 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT8, 0x04A4, 0x0190, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT8__GPIO_4_29 */
940 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT8, 0x04A4, 0x0190, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT8__MMDC_DEBUG_13 */
941 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT8, 0x04A4, 0x0190, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT8__PL301_PER1_HADR_19 */
942 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT9, 0x04A8, 0x0194, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9 */
943 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT9, 0x04A8, 0x0194, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT9__IPU2_DISP0_DAT_9 */
944 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT9, 0x04A8, 0x0194, 2, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT9__PWM2_PWMO */
945 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT9, 0x04A8, 0x0194, 3, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT9__WDOG2_WDOG_B */
946 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT9, 0x04A8, 0x0194, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT9__SDMA_DBG_EVT_CHN_2 */
947 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT9, 0x04A8, 0x0194, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT9__GPIO_4_30 */
948 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT9, 0x04A8, 0x0194, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT9__MMDC_DEBUG_14 */
949 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT9, 0x04A8, 0x0194, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT9__PL301_PER1_HADR_20 */
950 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT10, 0x04AC, 0x0198, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10 */
951 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT10, 0x04AC, 0x0198, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT10__IPU2_DISP0_DAT_10 */
952 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT10, 0x04AC, 0x0198, 3, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT10__USDHC1_DBG_6 */
953 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT10, 0x04AC, 0x0198, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT10__SDMA_DBG_EVT_CHN3 */
954 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT10, 0x04AC, 0x0198, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT10__GPIO_4_31 */
955 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT10, 0x04AC, 0x0198, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT10__MMDC_DEBUG_15 */
956 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT10, 0x04AC, 0x0198, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT10__PL301_PER1_HADR21 */
957 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT11, 0x04B0, 0x019C, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11 */
958 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT11, 0x04B0, 0x019C, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT11__IPU2_DISP0_DAT_11 */
959 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT11, 0x04B0, 0x019C, 3, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT11__USDHC1_USDHC_DBG7 */
960 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT11, 0x04B0, 0x019C, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT11__SDMA_DBG_EVT_CHN4 */
961 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT11, 0x04B0, 0x019C, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT11__GPIO_5_5 */
962 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT11, 0x04B0, 0x019C, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT11__MMDC_DEBUG_16 */
963 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT11, 0x04B0, 0x019C, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT11__PL301_PER1_HADR22 */
964 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT12, 0x04B4, 0x01A0, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12 */
965 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT12, 0x04B4, 0x01A0, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT12__IPU2_DISP0_DAT_12 */
966 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT12, 0x04B4, 0x01A0, 3, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT12__RESERVED_RESERVED */
967 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT12, 0x04B4, 0x01A0, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT12__SDMA_DBG_EVT_CHN5 */
968 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT12, 0x04B4, 0x01A0, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT12__GPIO_5_6 */
969 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT12, 0x04B4, 0x01A0, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT12__MMDC_DEBUG_17 */
970 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT12, 0x04B4, 0x01A0, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT12__PL301_PER1_HADR23 */
971 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT13, 0x04B8, 0x01A4, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13 */
972 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT13, 0x04B8, 0x01A4, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT13__IPU2_DISP0_DAT_13 */
973 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT13, 0x04B8, 0x01A4, 3, 0x07D8, 1), /* MX6Q_PAD_DISP0_DAT13__AUDMUX_AUD5_RXFS */
974 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT13, 0x04B8, 0x01A4, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT13__SDMA_DBG_EVT_CHN0 */
975 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT13, 0x04B8, 0x01A4, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT13__GPIO_5_7 */
976 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT13, 0x04B8, 0x01A4, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT13__MMDC_DEBUG_18 */
977 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT13, 0x04B8, 0x01A4, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT13__PL301_PER1_HADR24 */
978 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT14, 0x04BC, 0x01A8, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14 */
979 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT14, 0x04BC, 0x01A8, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT14__IPU2_DISP0_DAT_14 */
980 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT14, 0x04BC, 0x01A8, 3, 0x07D4, 1), /* MX6Q_PAD_DISP0_DAT14__AUDMUX_AUD5_RXC */
981 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT14, 0x04BC, 0x01A8, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT14__SDMA_DBG_EVT_CHN1 */
982 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT14, 0x04BC, 0x01A8, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT14__GPIO_5_8 */
983 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT14, 0x04BC, 0x01A8, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT14__MMDC_DEBUG_19 */
984 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT15, 0x04C0, 0x01AC, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15 */
985 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT15, 0x04C0, 0x01AC, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT15__IPU2_DISP0_DAT_15 */
986 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT15, 0x04C0, 0x01AC, 2, 0x0804, 1), /* MX6Q_PAD_DISP0_DAT15__ECSPI1_SS1 */
987 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT15, 0x04C0, 0x01AC, 3, 0x0820, 1), /* MX6Q_PAD_DISP0_DAT15__ECSPI2_SS1 */
988 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT15, 0x04C0, 0x01AC, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT15__SDMA_DBG_EVT_CHN2 */
989 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT15, 0x04C0, 0x01AC, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT15__GPIO_5_9 */
990 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT15, 0x04C0, 0x01AC, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT15__MMDC_DEBUG_20 */
991 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT15, 0x04C0, 0x01AC, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT15__PL301_PER1_HADR25 */
992 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT16, 0x04C4, 0x01B0, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16 */
993 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT16, 0x04C4, 0x01B0, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT16__IPU2_DISP0_DAT_16 */
994 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT16, 0x04C4, 0x01B0, 2, 0x0818, 1), /* MX6Q_PAD_DISP0_DAT16__ECSPI2_MOSI */
995 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT16, 0x04C4, 0x01B0, 3, 0x07DC, 0), /* MX6Q_PAD_DISP0_DAT16__AUDMUX_AUD5_TXC */
996 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT16, 0x04C4, 0x01B0, 4, 0x090C, 0), /* MX6Q_PAD_DISP0_DAT16__SDMA_EXT_EVENT_0 */
997 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT16, 0x04C4, 0x01B0, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT16__GPIO_5_10 */
998 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT16, 0x04C4, 0x01B0, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT16__MMDC_DEBUG_21 */
999 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT16, 0x04C4, 0x01B0, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT16__PL301_PER1_HADR26 */
1000 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT17, 0x04C8, 0x01B4, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17 */
1001 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT17, 0x04C8, 0x01B4, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT17__IPU2_DISP0_DAT_17 */
1002 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT17, 0x04C8, 0x01B4, 2, 0x0814, 1), /* MX6Q_PAD_DISP0_DAT17__ECSPI2_MISO */
1003 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT17, 0x04C8, 0x01B4, 3, 0x07D0, 0), /* MX6Q_PAD_DISP0_DAT17__AUDMUX_AUD5_TXD */
1004 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT17, 0x04C8, 0x01B4, 4, 0x0910, 0), /* MX6Q_PAD_DISP0_DAT17__SDMA_EXT_EVENT_1 */
1005 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT17, 0x04C8, 0x01B4, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT17__GPIO_5_11 */
1006 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT17, 0x04C8, 0x01B4, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT17__MMDC_DEBUG_22 */
1007 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT17, 0x04C8, 0x01B4, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT17__PL301_PER1_HADR27 */
1008 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT18, 0x04CC, 0x01B8, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18 */
1009 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT18, 0x04CC, 0x01B8, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT18__IPU2_DISP0_DAT_18 */
1010 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT18, 0x04CC, 0x01B8, 2, 0x081C, 1), /* MX6Q_PAD_DISP0_DAT18__ECSPI2_SS0 */
1011 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT18, 0x04CC, 0x01B8, 3, 0x07E0, 0), /* MX6Q_PAD_DISP0_DAT18__AUDMUX_AUD5_TXFS */
1012 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT18, 0x04CC, 0x01B8, 4, 0x07C0, 0), /* MX6Q_PAD_DISP0_DAT18__AUDMUX_AUD4_RXFS */
1013 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT18, 0x04CC, 0x01B8, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT18__GPIO_5_12 */
1014 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT18, 0x04CC, 0x01B8, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT18__MMDC_DEBUG_23 */
1015 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT18, 0x04CC, 0x01B8, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT18__WEIM_WEIM_CS_2 */
1016 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT19, 0x04D0, 0x01BC, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19 */
1017 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT19, 0x04D0, 0x01BC, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT19__IPU2_DISP0_DAT_19 */
1018 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT19, 0x04D0, 0x01BC, 2, 0x0810, 1), /* MX6Q_PAD_DISP0_DAT19__ECSPI2_SCLK */
1019 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT19, 0x04D0, 0x01BC, 3, 0x07CC, 0), /* MX6Q_PAD_DISP0_DAT19__AUDMUX_AUD5_RXD */
1020 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT19, 0x04D0, 0x01BC, 4, 0x07BC, 0), /* MX6Q_PAD_DISP0_DAT19__AUDMUX_AUD4_RXC */
1021 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT19, 0x04D0, 0x01BC, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT19__GPIO_5_13 */
1022 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT19, 0x04D0, 0x01BC, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT19__MMDC_DEBUG_24 */
1023 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT19, 0x04D0, 0x01BC, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT19__WEIM_WEIM_CS_3 */
1024 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT20, 0x04D4, 0x01C0, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20 */
1025 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT20, 0x04D4, 0x01C0, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT20__IPU2_DISP0_DAT_20 */
1026 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT20, 0x04D4, 0x01C0, 2, 0x07F4, 1), /* MX6Q_PAD_DISP0_DAT20__ECSPI1_SCLK */
1027 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT20, 0x04D4, 0x01C0, 3, 0x07C4, 0), /* MX6Q_PAD_DISP0_DAT20__AUDMUX_AUD4_TXC */
1028 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT20, 0x04D4, 0x01C0, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT20__SDMA_DBG_EVT_CHN7 */
1029 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT20, 0x04D4, 0x01C0, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT20__GPIO_5_14 */
1030 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT20, 0x04D4, 0x01C0, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT20__MMDC_DEBUG_25 */
1031 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT20, 0x04D4, 0x01C0, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT20__PL301_PER1_HADR28 */
1032 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT21, 0x04D8, 0x01C4, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21 */
1033 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT21, 0x04D8, 0x01C4, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT21__IPU2_DISP0_DAT_21 */
1034 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT21, 0x04D8, 0x01C4, 2, 0x07FC, 1), /* MX6Q_PAD_DISP0_DAT21__ECSPI1_MOSI */
1035 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT21, 0x04D8, 0x01C4, 3, 0x07B8, 1), /* MX6Q_PAD_DISP0_DAT21__AUDMUX_AUD4_TXD */
1036 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT21, 0x04D8, 0x01C4, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT21__SDMA_DBG_BUS_DEV0 */
1037 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT21, 0x04D8, 0x01C4, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT21__GPIO_5_15 */
1038 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT21, 0x04D8, 0x01C4, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT21__MMDC_DEBUG_26 */
1039 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT21, 0x04D8, 0x01C4, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT21__PL301_PER1_HADR29 */
1040 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT22, 0x04DC, 0x01C8, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22 */
1041 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT22, 0x04DC, 0x01C8, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT22__IPU2_DISP0_DAT_22 */
1042 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT22, 0x04DC, 0x01C8, 2, 0x07F8, 1), /* MX6Q_PAD_DISP0_DAT22__ECSPI1_MISO */
1043 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT22, 0x04DC, 0x01C8, 3, 0x07C8, 1), /* MX6Q_PAD_DISP0_DAT22__AUDMUX_AUD4_TXFS */
1044 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT22, 0x04DC, 0x01C8, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT22__SDMA_DBG_BUS_DEV1 */
1045 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT22, 0x04DC, 0x01C8, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT22__GPIO_5_16 */
1046 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT22, 0x04DC, 0x01C8, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT22__MMDC_DEBUG_27 */
1047 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT22, 0x04DC, 0x01C8, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT22__PL301_PER1_HADR30 */
1048 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT23, 0x04E0, 0x01CC, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23 */
1049 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT23, 0x04E0, 0x01CC, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT23__IPU2_DISP0_DAT_23 */
1050 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT23, 0x04E0, 0x01CC, 2, 0x0800, 1), /* MX6Q_PAD_DISP0_DAT23__ECSPI1_SS0 */
1051 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT23, 0x04E0, 0x01CC, 3, 0x07B4, 1), /* MX6Q_PAD_DISP0_DAT23__AUDMUX_AUD4_RXD */
1052 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT23, 0x04E0, 0x01CC, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT23__SDMA_DBG_BUS_DEV2 */
1053 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT23, 0x04E0, 0x01CC, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT23__GPIO_5_17 */
1054 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT23, 0x04E0, 0x01CC, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT23__MMDC_DEBUG_28 */
1055 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT23, 0x04E0, 0x01CC, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT23__PL301_PER1_HADR31 */
1056 IMX_PIN_REG(MX6Q_PAD_ENET_MDIO, 0x04E4, 0x01D0, 0, 0x0000, 0), /* MX6Q_PAD_ENET_MDIO__RESERVED_RESERVED */
1057 IMX_PIN_REG(MX6Q_PAD_ENET_MDIO, 0x04E4, 0x01D0, 1, 0x0840, 0), /* MX6Q_PAD_ENET_MDIO__ENET_MDIO */
1058 IMX_PIN_REG(MX6Q_PAD_ENET_MDIO, 0x04E4, 0x01D0, 2, 0x086C, 0), /* MX6Q_PAD_ENET_MDIO__ESAI1_SCKR */
1059 IMX_PIN_REG(MX6Q_PAD_ENET_MDIO, 0x04E4, 0x01D0, 3, 0x0000, 0), /* MX6Q_PAD_ENET_MDIO__SDMA_DEBUG_BUS_DEV3 */
1060 IMX_PIN_REG(MX6Q_PAD_ENET_MDIO, 0x04E4, 0x01D0, 4, 0x0000, 0), /* MX6Q_PAD_ENET_MDIO__ENET_1588_EVT1_OUT */
1061 IMX_PIN_REG(MX6Q_PAD_ENET_MDIO, 0x04E4, 0x01D0, 5, 0x0000, 0), /* MX6Q_PAD_ENET_MDIO__GPIO_1_22 */
1062 IMX_PIN_REG(MX6Q_PAD_ENET_MDIO, 0x04E4, 0x01D0, 6, 0x0000, 0), /* MX6Q_PAD_ENET_MDIO__SPDIF_PLOCK */
1063 IMX_PIN_REG(MX6Q_PAD_ENET_REF_CLK, 0x04E8, 0x01D4, 0, 0x0000, 0), /* MX6Q_PAD_ENET_REF_CLK__RESERVED_RSRVED */
1064 IMX_PIN_REG(MX6Q_PAD_ENET_REF_CLK, 0x04E8, 0x01D4, 1, 0x0000, 0), /* MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK */
1065 IMX_PIN_REG(MX6Q_PAD_ENET_REF_CLK, 0x04E8, 0x01D4, 2, 0x085C, 0), /* MX6Q_PAD_ENET_REF_CLK__ESAI1_FSR */
1066 IMX_PIN_REG(MX6Q_PAD_ENET_REF_CLK, 0x04E8, 0x01D4, 3, 0x0000, 0), /* MX6Q_PAD_ENET_REF_CLK__SDMA_DBGBUS_DEV4 */
1067 IMX_PIN_REG(MX6Q_PAD_ENET_REF_CLK, 0x04E8, 0x01D4, 5, 0x0000, 0), /* MX6Q_PAD_ENET_REF_CLK__GPIO_1_23 */
1068 IMX_PIN_REG(MX6Q_PAD_ENET_REF_CLK, 0x04E8, 0x01D4, 6, 0x0000, 0), /* MX6Q_PAD_ENET_REF_CLK__SPDIF_SRCLK */
1069 IMX_PIN_REG(MX6Q_PAD_ENET_REF_CLK, 0x04E8, 0x01D4, 7, 0x0000, 0), /* MX6Q_PAD_ENET_REF_CLK__USBPHY1_RX_SQH */
1070 IMX_PIN_REG(MX6Q_PAD_ENET_RX_ER, 0x04EC, 0x01D8, 1, 0x0000, 0), /* MX6Q_PAD_ENET_RX_ER__ENET_RX_ER */
1071 IMX_PIN_REG(MX6Q_PAD_ENET_RX_ER, 0x04EC, 0x01D8, 2, 0x0864, 0), /* MX6Q_PAD_ENET_RX_ER__ESAI1_HCKR */
1072 IMX_PIN_REG(MX6Q_PAD_ENET_RX_ER, 0x04EC, 0x01D8, 3, 0x0914, 1), /* MX6Q_PAD_ENET_RX_ER__SPDIF_IN1 */
1073 IMX_PIN_REG(MX6Q_PAD_ENET_RX_ER, 0x04EC, 0x01D8, 4, 0x0000, 0), /* MX6Q_PAD_ENET_RX_ER__ENET_1588_EVT2_OUT */
1074 IMX_PIN_REG(MX6Q_PAD_ENET_RX_ER, 0x04EC, 0x01D8, 5, 0x0000, 0), /* MX6Q_PAD_ENET_RX_ER__GPIO_1_24 */
1075 IMX_PIN_REG(MX6Q_PAD_ENET_RX_ER, 0x04EC, 0x01D8, 6, 0x0000, 0), /* MX6Q_PAD_ENET_RX_ER__PHY_TDI */
1076 IMX_PIN_REG(MX6Q_PAD_ENET_RX_ER, 0x04EC, 0x01D8, 7, 0x0000, 0), /* MX6Q_PAD_ENET_RX_ER__USBPHY1_RX_HS_RXD */
1077 IMX_PIN_REG(MX6Q_PAD_ENET_CRS_DV, 0x04F0, 0x01DC, 0, 0x0000, 0), /* MX6Q_PAD_ENET_CRS_DV__RESERVED_RSRVED */
1078 IMX_PIN_REG(MX6Q_PAD_ENET_CRS_DV, 0x04F0, 0x01DC, 1, 0x0858, 1), /* MX6Q_PAD_ENET_CRS_DV__ENET_RX_EN */
1079 IMX_PIN_REG(MX6Q_PAD_ENET_CRS_DV, 0x04F0, 0x01DC, 2, 0x0870, 0), /* MX6Q_PAD_ENET_CRS_DV__ESAI1_SCKT */
1080 IMX_PIN_REG(MX6Q_PAD_ENET_CRS_DV, 0x04F0, 0x01DC, 3, 0x0918, 1), /* MX6Q_PAD_ENET_CRS_DV__SPDIF_EXTCLK */
1081 IMX_PIN_REG(MX6Q_PAD_ENET_CRS_DV, 0x04F0, 0x01DC, 5, 0x0000, 0), /* MX6Q_PAD_ENET_CRS_DV__GPIO_1_25 */
1082 IMX_PIN_REG(MX6Q_PAD_ENET_CRS_DV, 0x04F0, 0x01DC, 6, 0x0000, 0), /* MX6Q_PAD_ENET_CRS_DV__PHY_TDO */
1083 IMX_PIN_REG(MX6Q_PAD_ENET_CRS_DV, 0x04F0, 0x01DC, 7, 0x0000, 0), /* MX6Q_PAD_ENET_CRS_DV__USBPHY1_RX_FS_RXD */
1084 IMX_PIN_REG(MX6Q_PAD_ENET_RXD1, 0x04F4, 0x01E0, 0, 0x0908, 0), /* MX6Q_PAD_ENET_RXD1__MLB_MLBSIG */
1085 IMX_PIN_REG(MX6Q_PAD_ENET_RXD1, 0x04F4, 0x01E0, 1, 0x084C, 1), /* MX6Q_PAD_ENET_RXD1__ENET_RDATA_1 */
1086 IMX_PIN_REG(MX6Q_PAD_ENET_RXD1, 0x04F4, 0x01E0, 2, 0x0860, 0), /* MX6Q_PAD_ENET_RXD1__ESAI1_FST */
1087 IMX_PIN_REG(MX6Q_PAD_ENET_RXD1, 0x04F4, 0x01E0, 4, 0x0000, 0), /* MX6Q_PAD_ENET_RXD1__ENET_1588_EVT3_OUT */
1088 IMX_PIN_REG(MX6Q_PAD_ENET_RXD1, 0x04F4, 0x01E0, 5, 0x0000, 0), /* MX6Q_PAD_ENET_RXD1__GPIO_1_26 */
1089 IMX_PIN_REG(MX6Q_PAD_ENET_RXD1, 0x04F4, 0x01E0, 6, 0x0000, 0), /* MX6Q_PAD_ENET_RXD1__PHY_TCK */
1090 IMX_PIN_REG(MX6Q_PAD_ENET_RXD1, 0x04F4, 0x01E0, 7, 0x0000, 0), /* MX6Q_PAD_ENET_RXD1__USBPHY1_RX_DISCON */
1091 IMX_PIN_REG(MX6Q_PAD_ENET_RXD0, 0x04F8, 0x01E4, 0, 0x0000, 0), /* MX6Q_PAD_ENET_RXD0__OSC32K_32K_OUT */
1092 IMX_PIN_REG(MX6Q_PAD_ENET_RXD0, 0x04F8, 0x01E4, 1, 0x0848, 1), /* MX6Q_PAD_ENET_RXD0__ENET_RDATA_0 */
1093 IMX_PIN_REG(MX6Q_PAD_ENET_RXD0, 0x04F8, 0x01E4, 2, 0x0868, 0), /* MX6Q_PAD_ENET_RXD0__ESAI1_HCKT */
1094 IMX_PIN_REG(MX6Q_PAD_ENET_RXD0, 0x04F8, 0x01E4, 3, 0x0000, 0), /* MX6Q_PAD_ENET_RXD0__SPDIF_OUT1 */
1095 IMX_PIN_REG(MX6Q_PAD_ENET_RXD0, 0x04F8, 0x01E4, 5, 0x0000, 0), /* MX6Q_PAD_ENET_RXD0__GPIO_1_27 */
1096 IMX_PIN_REG(MX6Q_PAD_ENET_RXD0, 0x04F8, 0x01E4, 6, 0x0000, 0), /* MX6Q_PAD_ENET_RXD0__PHY_TMS */
1097 IMX_PIN_REG(MX6Q_PAD_ENET_RXD0, 0x04F8, 0x01E4, 7, 0x0000, 0), /* MX6Q_PAD_ENET_RXD0__USBPHY1_PLL_CK20DIV */
1098 IMX_PIN_REG(MX6Q_PAD_ENET_TX_EN, 0x04FC, 0x01E8, 0, 0x0000, 0), /* MX6Q_PAD_ENET_TX_EN__RESERVED_RSRVED */
1099 IMX_PIN_REG(MX6Q_PAD_ENET_TX_EN, 0x04FC, 0x01E8, 1, 0x0000, 0), /* MX6Q_PAD_ENET_TX_EN__ENET_TX_EN */
1100 IMX_PIN_REG(MX6Q_PAD_ENET_TX_EN, 0x04FC, 0x01E8, 2, 0x0880, 0), /* MX6Q_PAD_ENET_TX_EN__ESAI1_TX3_RX2 */
1101 IMX_PIN_REG(MX6Q_PAD_ENET_TX_EN, 0x04FC, 0x01E8, 5, 0x0000, 0), /* MX6Q_PAD_ENET_TX_EN__GPIO_1_28 */
1102 IMX_PIN_REG(MX6Q_PAD_ENET_TX_EN, 0x04FC, 0x01E8, 6, 0x0000, 0), /* MX6Q_PAD_ENET_TX_EN__SATA_PHY_TDI */
1103 IMX_PIN_REG(MX6Q_PAD_ENET_TX_EN, 0x04FC, 0x01E8, 7, 0x0000, 0), /* MX6Q_PAD_ENET_TX_EN__USBPHY2_RX_SQH */
1104 IMX_PIN_REG(MX6Q_PAD_ENET_TXD1, 0x0500, 0x01EC, 0, 0x0900, 0), /* MX6Q_PAD_ENET_TXD1__MLB_MLBCLK */
1105 IMX_PIN_REG(MX6Q_PAD_ENET_TXD1, 0x0500, 0x01EC, 1, 0x0000, 0), /* MX6Q_PAD_ENET_TXD1__ENET_TDATA_1 */
1106 IMX_PIN_REG(MX6Q_PAD_ENET_TXD1, 0x0500, 0x01EC, 2, 0x087C, 0), /* MX6Q_PAD_ENET_TXD1__ESAI1_TX2_RX3 */
1107 IMX_PIN_REG(MX6Q_PAD_ENET_TXD1, 0x0500, 0x01EC, 4, 0x0000, 0), /* MX6Q_PAD_ENET_TXD1__ENET_1588_EVENT0_IN */
1108 IMX_PIN_REG(MX6Q_PAD_ENET_TXD1, 0x0500, 0x01EC, 5, 0x0000, 0), /* MX6Q_PAD_ENET_TXD1__GPIO_1_29 */
1109 IMX_PIN_REG(MX6Q_PAD_ENET_TXD1, 0x0500, 0x01EC, 6, 0x0000, 0), /* MX6Q_PAD_ENET_TXD1__SATA_PHY_TDO */
1110 IMX_PIN_REG(MX6Q_PAD_ENET_TXD1, 0x0500, 0x01EC, 7, 0x0000, 0), /* MX6Q_PAD_ENET_TXD1__USBPHY2_RX_HS_RXD */
1111 IMX_PIN_REG(MX6Q_PAD_ENET_TXD0, 0x0504, 0x01F0, 0, 0x0000, 0), /* MX6Q_PAD_ENET_TXD0__RESERVED_RSRVED */
1112 IMX_PIN_REG(MX6Q_PAD_ENET_TXD0, 0x0504, 0x01F0, 1, 0x0000, 0), /* MX6Q_PAD_ENET_TXD0__ENET_TDATA_0 */
1113 IMX_PIN_REG(MX6Q_PAD_ENET_TXD0, 0x0504, 0x01F0, 2, 0x0884, 0), /* MX6Q_PAD_ENET_TXD0__ESAI1_TX4_RX1 */
1114 IMX_PIN_REG(MX6Q_PAD_ENET_TXD0, 0x0504, 0x01F0, 5, 0x0000, 0), /* MX6Q_PAD_ENET_TXD0__GPIO_1_30 */
1115 IMX_PIN_REG(MX6Q_PAD_ENET_TXD0, 0x0504, 0x01F0, 6, 0x0000, 0), /* MX6Q_PAD_ENET_TXD0__SATA_PHY_TCK */
1116 IMX_PIN_REG(MX6Q_PAD_ENET_TXD0, 0x0504, 0x01F0, 7, 0x0000, 0), /* MX6Q_PAD_ENET_TXD0__USBPHY2_RX_FS_RXD */
1117 IMX_PIN_REG(MX6Q_PAD_ENET_MDC, 0x0508, 0x01F4, 0, 0x0904, 0), /* MX6Q_PAD_ENET_MDC__MLB_MLBDAT */
1118 IMX_PIN_REG(MX6Q_PAD_ENET_MDC, 0x0508, 0x01F4, 1, 0x0000, 0), /* MX6Q_PAD_ENET_MDC__ENET_MDC */
1119 IMX_PIN_REG(MX6Q_PAD_ENET_MDC, 0x0508, 0x01F4, 2, 0x0888, 0), /* MX6Q_PAD_ENET_MDC__ESAI1_TX5_RX0 */
1120 IMX_PIN_REG(MX6Q_PAD_ENET_MDC, 0x0508, 0x01F4, 4, 0x0000, 0), /* MX6Q_PAD_ENET_MDC__ENET_1588_EVENT1_IN */
1121 IMX_PIN_REG(MX6Q_PAD_ENET_MDC, 0x0508, 0x01F4, 5, 0x0000, 0), /* MX6Q_PAD_ENET_MDC__GPIO_1_31 */
1122 IMX_PIN_REG(MX6Q_PAD_ENET_MDC, 0x0508, 0x01F4, 6, 0x0000, 0), /* MX6Q_PAD_ENET_MDC__SATA_PHY_TMS */
1123 IMX_PIN_REG(MX6Q_PAD_ENET_MDC, 0x0508, 0x01F4, 7, 0x0000, 0), /* MX6Q_PAD_ENET_MDC__USBPHY2_RX_DISCON */
1124 IMX_PIN_REG(MX6Q_PAD_DRAM_D40, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D40__MMDC_DRAM_D_40 */
1125 IMX_PIN_REG(MX6Q_PAD_DRAM_D41, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D41__MMDC_DRAM_D_41 */
1126 IMX_PIN_REG(MX6Q_PAD_DRAM_D42, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D42__MMDC_DRAM_D_42 */
1127 IMX_PIN_REG(MX6Q_PAD_DRAM_D43, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D43__MMDC_DRAM_D_43 */
1128 IMX_PIN_REG(MX6Q_PAD_DRAM_D44, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D44__MMDC_DRAM_D_44 */
1129 IMX_PIN_REG(MX6Q_PAD_DRAM_D45, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D45__MMDC_DRAM_D_45 */
1130 IMX_PIN_REG(MX6Q_PAD_DRAM_D46, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D46__MMDC_DRAM_D_46 */
1131 IMX_PIN_REG(MX6Q_PAD_DRAM_D47, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D47__MMDC_DRAM_D_47 */
1132 IMX_PIN_REG(MX6Q_PAD_DRAM_SDQS5, 0x050C, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDQS5__MMDC_DRAM_SDQS_5 */
1133 IMX_PIN_REG(MX6Q_PAD_DRAM_DQM5, 0x0510, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_DQM5__MMDC_DRAM_DQM_5 */
1134 IMX_PIN_REG(MX6Q_PAD_DRAM_D32, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D32__MMDC_DRAM_D_32 */
1135 IMX_PIN_REG(MX6Q_PAD_DRAM_D33, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D33__MMDC_DRAM_D_33 */
1136 IMX_PIN_REG(MX6Q_PAD_DRAM_D34, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D34__MMDC_DRAM_D_34 */
1137 IMX_PIN_REG(MX6Q_PAD_DRAM_D35, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D35__MMDC_DRAM_D_35 */
1138 IMX_PIN_REG(MX6Q_PAD_DRAM_D36, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D36__MMDC_DRAM_D_36 */
1139 IMX_PIN_REG(MX6Q_PAD_DRAM_D37, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D37__MMDC_DRAM_D_37 */
1140 IMX_PIN_REG(MX6Q_PAD_DRAM_D38, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D38__MMDC_DRAM_D_38 */
1141 IMX_PIN_REG(MX6Q_PAD_DRAM_D39, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D39__MMDC_DRAM_D_39 */
1142 IMX_PIN_REG(MX6Q_PAD_DRAM_DQM4, 0x0514, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_DQM4__MMDC_DRAM_DQM_4 */
1143 IMX_PIN_REG(MX6Q_PAD_DRAM_SDQS4, 0x0518, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDQS4__MMDC_DRAM_SDQS_4 */
1144 IMX_PIN_REG(MX6Q_PAD_DRAM_D24, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D24__MMDC_DRAM_D_24 */
1145 IMX_PIN_REG(MX6Q_PAD_DRAM_D25, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D25__MMDC_DRAM_D_25 */
1146 IMX_PIN_REG(MX6Q_PAD_DRAM_D26, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D26__MMDC_DRAM_D_26 */
1147 IMX_PIN_REG(MX6Q_PAD_DRAM_D27, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D27__MMDC_DRAM_D_27 */
1148 IMX_PIN_REG(MX6Q_PAD_DRAM_D28, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D28__MMDC_DRAM_D_28 */
1149 IMX_PIN_REG(MX6Q_PAD_DRAM_D29, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D29__MMDC_DRAM_D_29 */
1150 IMX_PIN_REG(MX6Q_PAD_DRAM_SDQS3, 0x051C, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDQS3__MMDC_DRAM_SDQS_3 */
1151 IMX_PIN_REG(MX6Q_PAD_DRAM_D30, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D30__MMDC_DRAM_D_30 */
1152 IMX_PIN_REG(MX6Q_PAD_DRAM_D31, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D31__MMDC_DRAM_D_31 */
1153 IMX_PIN_REG(MX6Q_PAD_DRAM_DQM3, 0x0520, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_DQM3__MMDC_DRAM_DQM_3 */
1154 IMX_PIN_REG(MX6Q_PAD_DRAM_D16, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D16__MMDC_DRAM_D_16 */
1155 IMX_PIN_REG(MX6Q_PAD_DRAM_D17, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D17__MMDC_DRAM_D_17 */
1156 IMX_PIN_REG(MX6Q_PAD_DRAM_D18, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D18__MMDC_DRAM_D_18 */
1157 IMX_PIN_REG(MX6Q_PAD_DRAM_D19, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D19__MMDC_DRAM_D_19 */
1158 IMX_PIN_REG(MX6Q_PAD_DRAM_D20, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D20__MMDC_DRAM_D_20 */
1159 IMX_PIN_REG(MX6Q_PAD_DRAM_D21, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D21__MMDC_DRAM_D_21 */
1160 IMX_PIN_REG(MX6Q_PAD_DRAM_D22, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D22__MMDC_DRAM_D_22 */
1161 IMX_PIN_REG(MX6Q_PAD_DRAM_SDQS2, 0x0524, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDQS2__MMDC_DRAM_SDQS_2 */
1162 IMX_PIN_REG(MX6Q_PAD_DRAM_D23, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D23__MMDC_DRAM_D_23 */
1163 IMX_PIN_REG(MX6Q_PAD_DRAM_DQM2, 0x0528, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_DQM2__MMDC_DRAM_DQM_2 */
1164 IMX_PIN_REG(MX6Q_PAD_DRAM_A0, 0x052C, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_A0__MMDC_DRAM_A_0 */
1165 IMX_PIN_REG(MX6Q_PAD_DRAM_A1, 0x0530, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_A1__MMDC_DRAM_A_1 */
1166 IMX_PIN_REG(MX6Q_PAD_DRAM_A2, 0x0534, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_A2__MMDC_DRAM_A_2 */
1167 IMX_PIN_REG(MX6Q_PAD_DRAM_A3, 0x0538, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_A3__MMDC_DRAM_A_3 */
1168 IMX_PIN_REG(MX6Q_PAD_DRAM_A4, 0x053C, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_A4__MMDC_DRAM_A_4 */
1169 IMX_PIN_REG(MX6Q_PAD_DRAM_A5, 0x0540, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_A5__MMDC_DRAM_A_5 */
1170 IMX_PIN_REG(MX6Q_PAD_DRAM_A6, 0x0544, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_A6__MMDC_DRAM_A_6 */
1171 IMX_PIN_REG(MX6Q_PAD_DRAM_A7, 0x0548, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_A7__MMDC_DRAM_A_7 */
1172 IMX_PIN_REG(MX6Q_PAD_DRAM_A8, 0x054C, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_A8__MMDC_DRAM_A_8 */
1173 IMX_PIN_REG(MX6Q_PAD_DRAM_A9, 0x0550, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_A9__MMDC_DRAM_A_9 */
1174 IMX_PIN_REG(MX6Q_PAD_DRAM_A10, 0x0554, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_A10__MMDC_DRAM_A_10 */
1175 IMX_PIN_REG(MX6Q_PAD_DRAM_A11, 0x0558, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_A11__MMDC_DRAM_A_11 */
1176 IMX_PIN_REG(MX6Q_PAD_DRAM_A12, 0x055C, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_A12__MMDC_DRAM_A_12 */
1177 IMX_PIN_REG(MX6Q_PAD_DRAM_A13, 0x0560, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_A13__MMDC_DRAM_A_13 */
1178 IMX_PIN_REG(MX6Q_PAD_DRAM_A14, 0x0564, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_A14__MMDC_DRAM_A_14 */
1179 IMX_PIN_REG(MX6Q_PAD_DRAM_A15, 0x0568, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_A15__MMDC_DRAM_A_15 */
1180 IMX_PIN_REG(MX6Q_PAD_DRAM_CAS, 0x056C, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_CAS__MMDC_DRAM_CAS */
1181 IMX_PIN_REG(MX6Q_PAD_DRAM_CS0, 0x0570, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_CS0__MMDC_DRAM_CS_0 */
1182 IMX_PIN_REG(MX6Q_PAD_DRAM_CS1, 0x0574, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_CS1__MMDC_DRAM_CS_1 */
1183 IMX_PIN_REG(MX6Q_PAD_DRAM_RAS, 0x0578, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_RAS__MMDC_DRAM_RAS */
1184 IMX_PIN_REG(MX6Q_PAD_DRAM_RESET, 0x057C, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_RESET__MMDC_DRAM_RESET */
1185 IMX_PIN_REG(MX6Q_PAD_DRAM_SDBA0, 0x0580, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDBA0__MMDC_DRAM_SDBA_0 */
1186 IMX_PIN_REG(MX6Q_PAD_DRAM_SDBA1, 0x0584, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDBA1__MMDC_DRAM_SDBA_1 */
1187 IMX_PIN_REG(MX6Q_PAD_DRAM_SDCLK_0, 0x0588, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDCLK_0__MMDC_DRAM_SDCLK0 */
1188 IMX_PIN_REG(MX6Q_PAD_DRAM_SDBA2, 0x058C, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDBA2__MMDC_DRAM_SDBA_2 */
1189 IMX_PIN_REG(MX6Q_PAD_DRAM_SDCKE0, 0x0590, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDCKE0__MMDC_DRAM_SDCKE_0 */
1190 IMX_PIN_REG(MX6Q_PAD_DRAM_SDCLK_1, 0x0594, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDCLK_1__MMDC_DRAM_SDCLK1 */
1191 IMX_PIN_REG(MX6Q_PAD_DRAM_SDCKE1, 0x0598, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDCKE1__MMDC_DRAM_SDCKE_1 */
1192 IMX_PIN_REG(MX6Q_PAD_DRAM_SDODT0, 0x059C, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDODT0__MMDC_DRAM_ODT_0 */
1193 IMX_PIN_REG(MX6Q_PAD_DRAM_SDODT1, 0x05A0, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDODT1__MMDC_DRAM_ODT_1 */
1194 IMX_PIN_REG(MX6Q_PAD_DRAM_SDWE, 0x05A4, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDWE__MMDC_DRAM_SDWE */
1195 IMX_PIN_REG(MX6Q_PAD_DRAM_D0, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D0__MMDC_DRAM_D_0 */
1196 IMX_PIN_REG(MX6Q_PAD_DRAM_D1, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D1__MMDC_DRAM_D_1 */
1197 IMX_PIN_REG(MX6Q_PAD_DRAM_D2, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D2__MMDC_DRAM_D_2 */
1198 IMX_PIN_REG(MX6Q_PAD_DRAM_D3, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D3__MMDC_DRAM_D_3 */
1199 IMX_PIN_REG(MX6Q_PAD_DRAM_D4, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D4__MMDC_DRAM_D_4 */
1200 IMX_PIN_REG(MX6Q_PAD_DRAM_D5, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D5__MMDC_DRAM_D_5 */
1201 IMX_PIN_REG(MX6Q_PAD_DRAM_SDQS0, 0x05A8, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDQS0__MMDC_DRAM_SDQS_0 */
1202 IMX_PIN_REG(MX6Q_PAD_DRAM_D6, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D6__MMDC_DRAM_D_6 */
1203 IMX_PIN_REG(MX6Q_PAD_DRAM_D7, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D7__MMDC_DRAM_D_7 */
1204 IMX_PIN_REG(MX6Q_PAD_DRAM_DQM0, 0x05AC, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_DQM0__MMDC_DRAM_DQM_0 */
1205 IMX_PIN_REG(MX6Q_PAD_DRAM_D8, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D8__MMDC_DRAM_D_8 */
1206 IMX_PIN_REG(MX6Q_PAD_DRAM_D9, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D9__MMDC_DRAM_D_9 */
1207 IMX_PIN_REG(MX6Q_PAD_DRAM_D10, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D10__MMDC_DRAM_D_10 */
1208 IMX_PIN_REG(MX6Q_PAD_DRAM_D11, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D11__MMDC_DRAM_D_11 */
1209 IMX_PIN_REG(MX6Q_PAD_DRAM_D12, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D12__MMDC_DRAM_D_12 */
1210 IMX_PIN_REG(MX6Q_PAD_DRAM_D13, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D13__MMDC_DRAM_D_13 */
1211 IMX_PIN_REG(MX6Q_PAD_DRAM_D14, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D14__MMDC_DRAM_D_14 */
1212 IMX_PIN_REG(MX6Q_PAD_DRAM_SDQS1, 0x05B0, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDQS1__MMDC_DRAM_SDQS_1 */
1213 IMX_PIN_REG(MX6Q_PAD_DRAM_D15, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D15__MMDC_DRAM_D_15 */
1214 IMX_PIN_REG(MX6Q_PAD_DRAM_DQM1, 0x05B4, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_DQM1__MMDC_DRAM_DQM_1 */
1215 IMX_PIN_REG(MX6Q_PAD_DRAM_D48, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D48__MMDC_DRAM_D_48 */
1216 IMX_PIN_REG(MX6Q_PAD_DRAM_D49, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D49__MMDC_DRAM_D_49 */
1217 IMX_PIN_REG(MX6Q_PAD_DRAM_D50, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D50__MMDC_DRAM_D_50 */
1218 IMX_PIN_REG(MX6Q_PAD_DRAM_D51, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D51__MMDC_DRAM_D_51 */
1219 IMX_PIN_REG(MX6Q_PAD_DRAM_D52, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D52__MMDC_DRAM_D_52 */
1220 IMX_PIN_REG(MX6Q_PAD_DRAM_D53, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D53__MMDC_DRAM_D_53 */
1221 IMX_PIN_REG(MX6Q_PAD_DRAM_D54, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D54__MMDC_DRAM_D_54 */
1222 IMX_PIN_REG(MX6Q_PAD_DRAM_D55, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D55__MMDC_DRAM_D_55 */
1223 IMX_PIN_REG(MX6Q_PAD_DRAM_SDQS6, 0x05B8, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDQS6__MMDC_DRAM_SDQS_6 */
1224 IMX_PIN_REG(MX6Q_PAD_DRAM_DQM6, 0x05BC, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_DQM6__MMDC_DRAM_DQM_6 */
1225 IMX_PIN_REG(MX6Q_PAD_DRAM_D56, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D56__MMDC_DRAM_D_56 */
1226 IMX_PIN_REG(MX6Q_PAD_DRAM_SDQS7, 0x05C0, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDQS7__MMDC_DRAM_SDQS_7 */
1227 IMX_PIN_REG(MX6Q_PAD_DRAM_D57, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D57__MMDC_DRAM_D_57 */
1228 IMX_PIN_REG(MX6Q_PAD_DRAM_D58, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D58__MMDC_DRAM_D_58 */
1229 IMX_PIN_REG(MX6Q_PAD_DRAM_D59, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D59__MMDC_DRAM_D_59 */
1230 IMX_PIN_REG(MX6Q_PAD_DRAM_D60, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D60__MMDC_DRAM_D_60 */
1231 IMX_PIN_REG(MX6Q_PAD_DRAM_DQM7, 0x05C4, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_DQM7__MMDC_DRAM_DQM_7 */
1232 IMX_PIN_REG(MX6Q_PAD_DRAM_D61, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D61__MMDC_DRAM_D_61 */
1233 IMX_PIN_REG(MX6Q_PAD_DRAM_D62, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D62__MMDC_DRAM_D_62 */
1234 IMX_PIN_REG(MX6Q_PAD_DRAM_D63, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D63__MMDC_DRAM_D_63 */
1235 IMX_PIN_REG(MX6Q_PAD_KEY_COL0, 0x05C8, 0x01F8, 0, 0x07F4, 2), /* MX6Q_PAD_KEY_COL0__ECSPI1_SCLK */
1236 IMX_PIN_REG(MX6Q_PAD_KEY_COL0, 0x05C8, 0x01F8, 1, 0x0854, 1), /* MX6Q_PAD_KEY_COL0__ENET_RDATA_3 */
1237 IMX_PIN_REG(MX6Q_PAD_KEY_COL0, 0x05C8, 0x01F8, 2, 0x07DC, 1), /* MX6Q_PAD_KEY_COL0__AUDMUX_AUD5_TXC */
1238 IMX_PIN_REG(MX6Q_PAD_KEY_COL0, 0x05C8, 0x01F8, 3, 0x0000, 0), /* MX6Q_PAD_KEY_COL0__KPP_COL_0 */
1239 IMX_PIN_REG(MX6Q_PAD_KEY_COL0, 0x05C8, 0x01F8, 4, 0x0000, 0), /* MX6Q_PAD_KEY_COL0__UART4_TXD */
1240 IMX_PIN_REG(MX6Q_PAD_KEY_COL0, 0x05C8, 0x01F8, 5, 0x0000, 0), /* MX6Q_PAD_KEY_COL0__GPIO_4_6 */
1241 IMX_PIN_REG(MX6Q_PAD_KEY_COL0, 0x05C8, 0x01F8, 6, 0x0000, 0), /* MX6Q_PAD_KEY_COL0__DCIC1_DCIC_OUT */
1242 IMX_PIN_REG(MX6Q_PAD_KEY_COL0, 0x05C8, 0x01F8, 7, 0x0000, 0), /* MX6Q_PAD_KEY_COL0__SRC_ANY_PU_RST */
1243 IMX_PIN_REG(MX6Q_PAD_KEY_ROW0, 0x05CC, 0x01FC, 0, 0x07FC, 2), /* MX6Q_PAD_KEY_ROW0__ECSPI1_MOSI */
1244 IMX_PIN_REG(MX6Q_PAD_KEY_ROW0, 0x05CC, 0x01FC, 1, 0x0000, 0), /* MX6Q_PAD_KEY_ROW0__ENET_TDATA_3 */
1245 IMX_PIN_REG(MX6Q_PAD_KEY_ROW0, 0x05CC, 0x01FC, 2, 0x07D0, 1), /* MX6Q_PAD_KEY_ROW0__AUDMUX_AUD5_TXD */
1246 IMX_PIN_REG(MX6Q_PAD_KEY_ROW0, 0x05CC, 0x01FC, 3, 0x0000, 0), /* MX6Q_PAD_KEY_ROW0__KPP_ROW_0 */
1247 IMX_PIN_REG(MX6Q_PAD_KEY_ROW0, 0x05CC, 0x01FC, 4, 0x0938, 1), /* MX6Q_PAD_KEY_ROW0__UART4_RXD */
1248 IMX_PIN_REG(MX6Q_PAD_KEY_ROW0, 0x05CC, 0x01FC, 5, 0x0000, 0), /* MX6Q_PAD_KEY_ROW0__GPIO_4_7 */
1249 IMX_PIN_REG(MX6Q_PAD_KEY_ROW0, 0x05CC, 0x01FC, 6, 0x0000, 0), /* MX6Q_PAD_KEY_ROW0__DCIC2_DCIC_OUT */
1250 IMX_PIN_REG(MX6Q_PAD_KEY_ROW0, 0x05CC, 0x01FC, 7, 0x0000, 0), /* MX6Q_PAD_KEY_ROW0__PL301_PER1_HADR_0 */
1251 IMX_PIN_REG(MX6Q_PAD_KEY_COL1, 0x05D0, 0x0200, 0, 0x07F8, 2), /* MX6Q_PAD_KEY_COL1__ECSPI1_MISO */
1252 IMX_PIN_REG(MX6Q_PAD_KEY_COL1, 0x05D0, 0x0200, 1, 0x0840, 1), /* MX6Q_PAD_KEY_COL1__ENET_MDIO */
1253 IMX_PIN_REG(MX6Q_PAD_KEY_COL1, 0x05D0, 0x0200, 2, 0x07E0, 1), /* MX6Q_PAD_KEY_COL1__AUDMUX_AUD5_TXFS */
1254 IMX_PIN_REG(MX6Q_PAD_KEY_COL1, 0x05D0, 0x0200, 3, 0x0000, 0), /* MX6Q_PAD_KEY_COL1__KPP_COL_1 */
1255 IMX_PIN_REG(MX6Q_PAD_KEY_COL1, 0x05D0, 0x0200, 4, 0x0000, 0), /* MX6Q_PAD_KEY_COL1__UART5_TXD */
1256 IMX_PIN_REG(MX6Q_PAD_KEY_COL1, 0x05D0, 0x0200, 5, 0x0000, 0), /* MX6Q_PAD_KEY_COL1__GPIO_4_8 */
1257 IMX_PIN_REG(MX6Q_PAD_KEY_COL1, 0x05D0, 0x0200, 6, 0x0000, 0), /* MX6Q_PAD_KEY_COL1__USDHC1_VSELECT */
1258 IMX_PIN_REG(MX6Q_PAD_KEY_COL1, 0x05D0, 0x0200, 7, 0x0000, 0), /* MX6Q_PAD_KEY_COL1__PL301MX_PER1_HADR_1 */
1259 IMX_PIN_REG(MX6Q_PAD_KEY_ROW1, 0x05D4, 0x0204, 0, 0x0800, 2), /* MX6Q_PAD_KEY_ROW1__ECSPI1_SS0 */
1260 IMX_PIN_REG(MX6Q_PAD_KEY_ROW1, 0x05D4, 0x0204, 1, 0x0000, 0), /* MX6Q_PAD_KEY_ROW1__ENET_COL */
1261 IMX_PIN_REG(MX6Q_PAD_KEY_ROW1, 0x05D4, 0x0204, 2, 0x07CC, 1), /* MX6Q_PAD_KEY_ROW1__AUDMUX_AUD5_RXD */
1262 IMX_PIN_REG(MX6Q_PAD_KEY_ROW1, 0x05D4, 0x0204, 3, 0x0000, 0), /* MX6Q_PAD_KEY_ROW1__KPP_ROW_1 */
1263 IMX_PIN_REG(MX6Q_PAD_KEY_ROW1, 0x05D4, 0x0204, 4, 0x0940, 1), /* MX6Q_PAD_KEY_ROW1__UART5_RXD */
1264 IMX_PIN_REG(MX6Q_PAD_KEY_ROW1, 0x05D4, 0x0204, 5, 0x0000, 0), /* MX6Q_PAD_KEY_ROW1__GPIO_4_9 */
1265 IMX_PIN_REG(MX6Q_PAD_KEY_ROW1, 0x05D4, 0x0204, 6, 0x0000, 0), /* MX6Q_PAD_KEY_ROW1__USDHC2_VSELECT */
1266 IMX_PIN_REG(MX6Q_PAD_KEY_ROW1, 0x05D4, 0x0204, 7, 0x0000, 0), /* MX6Q_PAD_KEY_ROW1__PL301_PER1_HADDR_2 */
1267 IMX_PIN_REG(MX6Q_PAD_KEY_COL2, 0x05D8, 0x0208, 0, 0x0804, 2), /* MX6Q_PAD_KEY_COL2__ECSPI1_SS1 */
1268 IMX_PIN_REG(MX6Q_PAD_KEY_COL2, 0x05D8, 0x0208, 1, 0x0850, 1), /* MX6Q_PAD_KEY_COL2__ENET_RDATA_2 */
1269 IMX_PIN_REG(MX6Q_PAD_KEY_COL2, 0x05D8, 0x0208, 2, 0x0000, 0), /* MX6Q_PAD_KEY_COL2__CAN1_TXCAN */
1270 IMX_PIN_REG(MX6Q_PAD_KEY_COL2, 0x05D8, 0x0208, 3, 0x0000, 0), /* MX6Q_PAD_KEY_COL2__KPP_COL_2 */
1271 IMX_PIN_REG(MX6Q_PAD_KEY_COL2, 0x05D8, 0x0208, 4, 0x0000, 0), /* MX6Q_PAD_KEY_COL2__ENET_MDC */
1272 IMX_PIN_REG(MX6Q_PAD_KEY_COL2, 0x05D8, 0x0208, 5, 0x0000, 0), /* MX6Q_PAD_KEY_COL2__GPIO_4_10 */
1273 IMX_PIN_REG(MX6Q_PAD_KEY_COL2, 0x05D8, 0x0208, 6, 0x0000, 0), /* MX6Q_PAD_KEY_COL2__USBOH3_H1_PWRCTL_WKP */
1274 IMX_PIN_REG(MX6Q_PAD_KEY_COL2, 0x05D8, 0x0208, 7, 0x0000, 0), /* MX6Q_PAD_KEY_COL2__PL301_PER1_HADDR_3 */
1275 IMX_PIN_REG(MX6Q_PAD_KEY_ROW2, 0x05DC, 0x020C, 0, 0x0808, 1), /* MX6Q_PAD_KEY_ROW2__ECSPI1_SS2 */
1276 IMX_PIN_REG(MX6Q_PAD_KEY_ROW2, 0x05DC, 0x020C, 1, 0x0000, 0), /* MX6Q_PAD_KEY_ROW2__ENET_TDATA_2 */
1277 IMX_PIN_REG(MX6Q_PAD_KEY_ROW2, 0x05DC, 0x020C, 2, 0x07E4, 0), /* MX6Q_PAD_KEY_ROW2__CAN1_RXCAN */
1278 IMX_PIN_REG(MX6Q_PAD_KEY_ROW2, 0x05DC, 0x020C, 3, 0x0000, 0), /* MX6Q_PAD_KEY_ROW2__KPP_ROW_2 */
1279 IMX_PIN_REG(MX6Q_PAD_KEY_ROW2, 0x05DC, 0x020C, 4, 0x0000, 0), /* MX6Q_PAD_KEY_ROW2__USDHC2_VSELECT */
1280 IMX_PIN_REG(MX6Q_PAD_KEY_ROW2, 0x05DC, 0x020C, 5, 0x0000, 0), /* MX6Q_PAD_KEY_ROW2__GPIO_4_11 */
1281 IMX_PIN_REG(MX6Q_PAD_KEY_ROW2, 0x05DC, 0x020C, 6, 0x088C, 1), /* MX6Q_PAD_KEY_ROW2__HDMI_TX_CEC_LINE */
1282 IMX_PIN_REG(MX6Q_PAD_KEY_ROW2, 0x05DC, 0x020C, 7, 0x0000, 0), /* MX6Q_PAD_KEY_ROW2__PL301_PER1_HADR_4 */
1283 IMX_PIN_REG(MX6Q_PAD_KEY_COL3, 0x05E0, 0x0210, 0, 0x080C, 1), /* MX6Q_PAD_KEY_COL3__ECSPI1_SS3 */
1284 IMX_PIN_REG(MX6Q_PAD_KEY_COL3, 0x05E0, 0x0210, 1, 0x0000, 0), /* MX6Q_PAD_KEY_COL3__ENET_CRS */
1285 IMX_PIN_REG(MX6Q_PAD_KEY_COL3, 0x05E0, 0x0210, 2, 0x0890, 1), /* MX6Q_PAD_KEY_COL3__HDMI_TX_DDC_SCL */
1286 IMX_PIN_REG(MX6Q_PAD_KEY_COL3, 0x05E0, 0x0210, 3, 0x0000, 0), /* MX6Q_PAD_KEY_COL3__KPP_COL_3 */
1287 IMX_PIN_REG(MX6Q_PAD_KEY_COL3, 0x05E0, 0x0210, 4, 0x08A0, 1), /* MX6Q_PAD_KEY_COL3__I2C2_SCL */
1288 IMX_PIN_REG(MX6Q_PAD_KEY_COL3, 0x05E0, 0x0210, 5, 0x0000, 0), /* MX6Q_PAD_KEY_COL3__GPIO_4_12 */
1289 IMX_PIN_REG(MX6Q_PAD_KEY_COL3, 0x05E0, 0x0210, 6, 0x0914, 2), /* MX6Q_PAD_KEY_COL3__SPDIF_IN1 */
1290 IMX_PIN_REG(MX6Q_PAD_KEY_COL3, 0x05E0, 0x0210, 7, 0x0000, 0), /* MX6Q_PAD_KEY_COL3__PL301_PER1_HADR_5 */
1291 IMX_PIN_REG(MX6Q_PAD_KEY_ROW3, 0x05E4, 0x0214, 0, 0x0000, 0), /* MX6Q_PAD_KEY_ROW3__OSC32K_32K_OUT */
1292 IMX_PIN_REG(MX6Q_PAD_KEY_ROW3, 0x05E4, 0x0214, 1, 0x07B0, 0), /* MX6Q_PAD_KEY_ROW3__ASRC_ASRC_EXT_CLK */
1293 IMX_PIN_REG(MX6Q_PAD_KEY_ROW3, 0x05E4, 0x0214, 2, 0x0894, 1), /* MX6Q_PAD_KEY_ROW3__HDMI_TX_DDC_SDA */
1294 IMX_PIN_REG(MX6Q_PAD_KEY_ROW3, 0x05E4, 0x0214, 3, 0x0000, 0), /* MX6Q_PAD_KEY_ROW3__KPP_ROW_3 */
1295 IMX_PIN_REG(MX6Q_PAD_KEY_ROW3, 0x05E4, 0x0214, 4, 0x08A4, 1), /* MX6Q_PAD_KEY_ROW3__I2C2_SDA */
1296 IMX_PIN_REG(MX6Q_PAD_KEY_ROW3, 0x05E4, 0x0214, 5, 0x0000, 0), /* MX6Q_PAD_KEY_ROW3__GPIO_4_13 */
1297 IMX_PIN_REG(MX6Q_PAD_KEY_ROW3, 0x05E4, 0x0214, 6, 0x0000, 0), /* MX6Q_PAD_KEY_ROW3__USDHC1_VSELECT */
1298 IMX_PIN_REG(MX6Q_PAD_KEY_ROW3, 0x05E4, 0x0214, 7, 0x0000, 0), /* MX6Q_PAD_KEY_ROW3__PL301_PER1_HADR_6 */
1299 IMX_PIN_REG(MX6Q_PAD_KEY_COL4, 0x05E8, 0x0218, 0, 0x0000, 0), /* MX6Q_PAD_KEY_COL4__CAN2_TXCAN */
1300 IMX_PIN_REG(MX6Q_PAD_KEY_COL4, 0x05E8, 0x0218, 1, 0x0000, 0), /* MX6Q_PAD_KEY_COL4__IPU1_SISG_4 */
1301 IMX_PIN_REG(MX6Q_PAD_KEY_COL4, 0x05E8, 0x0218, 2, 0x0944, 1), /* MX6Q_PAD_KEY_COL4__USBOH3_USBOTG_OC */
1302 IMX_PIN_REG(MX6Q_PAD_KEY_COL4, 0x05E8, 0x0218, 3, 0x0000, 0), /* MX6Q_PAD_KEY_COL4__KPP_COL_4 */
1303 IMX_PIN_REG(MX6Q_PAD_KEY_COL4, 0x05E8, 0x0218, 4, 0x093C, 0), /* MX6Q_PAD_KEY_COL4__UART5_RTS */
1304 IMX_PIN_REG(MX6Q_PAD_KEY_COL4, 0x05E8, 0x0218, 5, 0x0000, 0), /* MX6Q_PAD_KEY_COL4__GPIO_4_14 */
1305 IMX_PIN_REG(MX6Q_PAD_KEY_COL4, 0x05E8, 0x0218, 6, 0x0000, 0), /* MX6Q_PAD_KEY_COL4__MMDC_DEBUG_49 */
1306 IMX_PIN_REG(MX6Q_PAD_KEY_COL4, 0x05E8, 0x0218, 7, 0x0000, 0), /* MX6Q_PAD_KEY_COL4__PL301_PER1_HADDR_7 */
1307 IMX_PIN_REG(MX6Q_PAD_KEY_ROW4, 0x05EC, 0x021C, 0, 0x07E8, 0), /* MX6Q_PAD_KEY_ROW4__CAN2_RXCAN */
1308 IMX_PIN_REG(MX6Q_PAD_KEY_ROW4, 0x05EC, 0x021C, 1, 0x0000, 0), /* MX6Q_PAD_KEY_ROW4__IPU1_SISG_5 */
1309 IMX_PIN_REG(MX6Q_PAD_KEY_ROW4, 0x05EC, 0x021C, 2, 0x0000, 0), /* MX6Q_PAD_KEY_ROW4__USBOH3_USBOTG_PWR */
1310 IMX_PIN_REG(MX6Q_PAD_KEY_ROW4, 0x05EC, 0x021C, 3, 0x0000, 0), /* MX6Q_PAD_KEY_ROW4__KPP_ROW_4 */
1311 IMX_PIN_REG(MX6Q_PAD_KEY_ROW4, 0x05EC, 0x021C, 4, 0x093C, 1), /* MX6Q_PAD_KEY_ROW4__UART5_CTS */
1312 IMX_PIN_REG(MX6Q_PAD_KEY_ROW4, 0x05EC, 0x021C, 5, 0x0000, 0), /* MX6Q_PAD_KEY_ROW4__GPIO_4_15 */
1313 IMX_PIN_REG(MX6Q_PAD_KEY_ROW4, 0x05EC, 0x021C, 6, 0x0000, 0), /* MX6Q_PAD_KEY_ROW4__MMDC_DEBUG_50 */
1314 IMX_PIN_REG(MX6Q_PAD_KEY_ROW4, 0x05EC, 0x021C, 7, 0x0000, 0), /* MX6Q_PAD_KEY_ROW4__PL301_PER1_HADR_8 */
1315 IMX_PIN_REG(MX6Q_PAD_GPIO_0, 0x05F0, 0x0220, 0, 0x0000, 0), /* MX6Q_PAD_GPIO_0__CCM_CLKO */
1316 IMX_PIN_REG(MX6Q_PAD_GPIO_0, 0x05F0, 0x0220, 2, 0x08E8, 0), /* MX6Q_PAD_GPIO_0__KPP_COL_5 */
1317 IMX_PIN_REG(MX6Q_PAD_GPIO_0, 0x05F0, 0x0220, 3, 0x07B0, 1), /* MX6Q_PAD_GPIO_0__ASRC_ASRC_EXT_CLK */
1318 IMX_PIN_REG(MX6Q_PAD_GPIO_0, 0x05F0, 0x0220, 4, 0x0000, 0), /* MX6Q_PAD_GPIO_0__EPIT1_EPITO */
1319 IMX_PIN_REG(MX6Q_PAD_GPIO_0, 0x05F0, 0x0220, 5, 0x0000, 0), /* MX6Q_PAD_GPIO_0__GPIO_1_0 */
1320 IMX_PIN_REG(MX6Q_PAD_GPIO_0, 0x05F0, 0x0220, 6, 0x0000, 0), /* MX6Q_PAD_GPIO_0__USBOH3_USBH1_PWR */
1321 IMX_PIN_REG(MX6Q_PAD_GPIO_0, 0x05F0, 0x0220, 7, 0x0000, 0), /* MX6Q_PAD_GPIO_0__SNVS_HP_WRAP_SNVS_VIO5 */
1322 IMX_PIN_REG(MX6Q_PAD_GPIO_1, 0x05F4, 0x0224, 0, 0x086C, 1), /* MX6Q_PAD_GPIO_1__ESAI1_SCKR */
1323 IMX_PIN_REG(MX6Q_PAD_GPIO_1, 0x05F4, 0x0224, 1, 0x0000, 0), /* MX6Q_PAD_GPIO_1__WDOG2_WDOG_B */
1324 IMX_PIN_REG(MX6Q_PAD_GPIO_1, 0x05F4, 0x0224, 2, 0x08F4, 0), /* MX6Q_PAD_GPIO_1__KPP_ROW_5 */
1325 IMX_PIN_REG(MX6Q_PAD_GPIO_1, 0x05F4, 0x0224, 4, 0x0000, 0), /* MX6Q_PAD_GPIO_1__PWM2_PWMO */
1326 IMX_PIN_REG(MX6Q_PAD_GPIO_1, 0x05F4, 0x0224, 5, 0x0000, 0), /* MX6Q_PAD_GPIO_1__GPIO_1_1 */
1327 IMX_PIN_REG(MX6Q_PAD_GPIO_1, 0x05F4, 0x0224, 6, 0x0000, 0), /* MX6Q_PAD_GPIO_1__USDHC1_CD */
1328 IMX_PIN_REG(MX6Q_PAD_GPIO_1, 0x05F4, 0x0224, 7, 0x0000, 0), /* MX6Q_PAD_GPIO_1__SRC_TESTER_ACK */
1329 IMX_PIN_REG(MX6Q_PAD_GPIO_9, 0x05F8, 0x0228, 0, 0x085C, 1), /* MX6Q_PAD_GPIO_9__ESAI1_FSR */
1330 IMX_PIN_REG(MX6Q_PAD_GPIO_9, 0x05F8, 0x0228, 1, 0x0000, 0), /* MX6Q_PAD_GPIO_9__WDOG1_WDOG_B */
1331 IMX_PIN_REG(MX6Q_PAD_GPIO_9, 0x05F8, 0x0228, 2, 0x08EC, 0), /* MX6Q_PAD_GPIO_9__KPP_COL_6 */
1332 IMX_PIN_REG(MX6Q_PAD_GPIO_9, 0x05F8, 0x0228, 3, 0x0000, 0), /* MX6Q_PAD_GPIO_9__CCM_REF_EN_B */
1333 IMX_PIN_REG(MX6Q_PAD_GPIO_9, 0x05F8, 0x0228, 4, 0x0000, 0), /* MX6Q_PAD_GPIO_9__PWM1_PWMO */
1334 IMX_PIN_REG(MX6Q_PAD_GPIO_9, 0x05F8, 0x0228, 5, 0x0000, 0), /* MX6Q_PAD_GPIO_9__GPIO_1_9 */
1335 IMX_PIN_REG(MX6Q_PAD_GPIO_9, 0x05F8, 0x0228, 6, 0x094C, 1), /* MX6Q_PAD_GPIO_9__USDHC1_WP */
1336 IMX_PIN_REG(MX6Q_PAD_GPIO_9, 0x05F8, 0x0228, 7, 0x0000, 0), /* MX6Q_PAD_GPIO_9__SRC_EARLY_RST */
1337 IMX_PIN_REG(MX6Q_PAD_GPIO_3, 0x05FC, 0x022C, 0, 0x0864, 1), /* MX6Q_PAD_GPIO_3__ESAI1_HCKR */
1338 IMX_PIN_REG(MX6Q_PAD_GPIO_3, 0x05FC, 0x022C, 1, 0x0000, 0), /* MX6Q_PAD_GPIO_3__OBSERVE_MUX_INT_OUT0 */
1339 IMX_PIN_REG(MX6Q_PAD_GPIO_3, 0x05FC, 0x022C, 2, 0x08A8, 1), /* MX6Q_PAD_GPIO_3__I2C3_SCL */
1340 IMX_PIN_REG(MX6Q_PAD_GPIO_3, 0x05FC, 0x022C, 3, 0x0000, 0), /* MX6Q_PAD_GPIO_3__ANATOP_24M_OUT */
1341 IMX_PIN_REG(MX6Q_PAD_GPIO_3, 0x05FC, 0x022C, 4, 0x0000, 0), /* MX6Q_PAD_GPIO_3__CCM_CLKO2 */
1342 IMX_PIN_REG(MX6Q_PAD_GPIO_3, 0x05FC, 0x022C, 5, 0x0000, 0), /* MX6Q_PAD_GPIO_3__GPIO_1_3 */
1343 IMX_PIN_REG(MX6Q_PAD_GPIO_3, 0x05FC, 0x022C, 6, 0x0948, 1), /* MX6Q_PAD_GPIO_3__USBOH3_USBH1_OC */
1344 IMX_PIN_REG(MX6Q_PAD_GPIO_3, 0x05FC, 0x022C, 7, 0x0900, 1), /* MX6Q_PAD_GPIO_3__MLB_MLBCLK */
1345 IMX_PIN_REG(MX6Q_PAD_GPIO_6, 0x0600, 0x0230, 0, 0x0870, 1), /* MX6Q_PAD_GPIO_6__ESAI1_SCKT */
1346 IMX_PIN_REG(MX6Q_PAD_GPIO_6, 0x0600, 0x0230, 1, 0x0000, 0), /* MX6Q_PAD_GPIO_6__OBSERVE_MUX_INT_OUT1 */
1347 IMX_PIN_REG(MX6Q_PAD_GPIO_6, 0x0600, 0x0230, 2, 0x08AC, 1), /* MX6Q_PAD_GPIO_6__I2C3_SDA */
1348 IMX_PIN_REG(MX6Q_PAD_GPIO_6, 0x0600, 0x0230, 3, 0x0000, 0), /* MX6Q_PAD_GPIO_6__CCM_CCM_OUT_0 */
1349 IMX_PIN_REG(MX6Q_PAD_GPIO_6, 0x0600, 0x0230, 4, 0x0000, 0), /* MX6Q_PAD_GPIO_6__CSU_CSU_INT_DEB */
1350 IMX_PIN_REG(MX6Q_PAD_GPIO_6, 0x0600, 0x0230, 5, 0x0000, 0), /* MX6Q_PAD_GPIO_6__GPIO_1_6 */
1351 IMX_PIN_REG(MX6Q_PAD_GPIO_6, 0x0600, 0x0230, 6, 0x0000, 0), /* MX6Q_PAD_GPIO_6__USDHC2_LCTL */
1352 IMX_PIN_REG(MX6Q_PAD_GPIO_6, 0x0600, 0x0230, 7, 0x0908, 1), /* MX6Q_PAD_GPIO_6__MLB_MLBSIG */
1353 IMX_PIN_REG(MX6Q_PAD_GPIO_2, 0x0604, 0x0234, 0, 0x0860, 1), /* MX6Q_PAD_GPIO_2__ESAI1_FST */
1354 IMX_PIN_REG(MX6Q_PAD_GPIO_2, 0x0604, 0x0234, 1, 0x0000, 0), /* MX6Q_PAD_GPIO_2__OBSERVE_MUX_INT_OUT2 */
1355 IMX_PIN_REG(MX6Q_PAD_GPIO_2, 0x0604, 0x0234, 2, 0x08F8, 1), /* MX6Q_PAD_GPIO_2__KPP_ROW_6 */
1356 IMX_PIN_REG(MX6Q_PAD_GPIO_2, 0x0604, 0x0234, 3, 0x0000, 0), /* MX6Q_PAD_GPIO_2__CCM_CCM_OUT_1 */
1357 IMX_PIN_REG(MX6Q_PAD_GPIO_2, 0x0604, 0x0234, 4, 0x0000, 0), /* MX6Q_PAD_GPIO_2__CSU_CSU_ALARM_AUT_0 */
1358 IMX_PIN_REG(MX6Q_PAD_GPIO_2, 0x0604, 0x0234, 5, 0x0000, 0), /* MX6Q_PAD_GPIO_2__GPIO_1_2 */
1359 IMX_PIN_REG(MX6Q_PAD_GPIO_2, 0x0604, 0x0234, 6, 0x0000, 0), /* MX6Q_PAD_GPIO_2__USDHC2_WP */
1360 IMX_PIN_REG(MX6Q_PAD_GPIO_2, 0x0604, 0x0234, 7, 0x0904, 1), /* MX6Q_PAD_GPIO_2__MLB_MLBDAT */
1361 IMX_PIN_REG(MX6Q_PAD_GPIO_4, 0x0608, 0x0238, 0, 0x0868, 1), /* MX6Q_PAD_GPIO_4__ESAI1_HCKT */
1362 IMX_PIN_REG(MX6Q_PAD_GPIO_4, 0x0608, 0x0238, 1, 0x0000, 0), /* MX6Q_PAD_GPIO_4__OBSERVE_MUX_INT_OUT3 */
1363 IMX_PIN_REG(MX6Q_PAD_GPIO_4, 0x0608, 0x0238, 2, 0x08F0, 1), /* MX6Q_PAD_GPIO_4__KPP_COL_7 */
1364 IMX_PIN_REG(MX6Q_PAD_GPIO_4, 0x0608, 0x0238, 3, 0x0000, 0), /* MX6Q_PAD_GPIO_4__CCM_CCM_OUT_2 */
1365 IMX_PIN_REG(MX6Q_PAD_GPIO_4, 0x0608, 0x0238, 4, 0x0000, 0), /* MX6Q_PAD_GPIO_4__CSU_CSU_ALARM_AUT_1 */
1366 IMX_PIN_REG(MX6Q_PAD_GPIO_4, 0x0608, 0x0238, 5, 0x0000, 0), /* MX6Q_PAD_GPIO_4__GPIO_1_4 */
1367 IMX_PIN_REG(MX6Q_PAD_GPIO_4, 0x0608, 0x0238, 6, 0x0000, 0), /* MX6Q_PAD_GPIO_4__USDHC2_CD */
1368 IMX_PIN_REG(MX6Q_PAD_GPIO_4, 0x0608, 0x0238, 7, 0x0000, 0), /* MX6Q_PAD_GPIO_4__OCOTP_CRL_WRAR_FUSE_LA */
1369 IMX_PIN_REG(MX6Q_PAD_GPIO_5, 0x060C, 0x023C, 0, 0x087C, 1), /* MX6Q_PAD_GPIO_5__ESAI1_TX2_RX3 */
1370 IMX_PIN_REG(MX6Q_PAD_GPIO_5, 0x060C, 0x023C, 1, 0x0000, 0), /* MX6Q_PAD_GPIO_5__OBSERVE_MUX_INT_OUT4 */
1371 IMX_PIN_REG(MX6Q_PAD_GPIO_5, 0x060C, 0x023C, 2, 0x08FC, 1), /* MX6Q_PAD_GPIO_5__KPP_ROW_7 */
1372 IMX_PIN_REG(MX6Q_PAD_GPIO_5, 0x060C, 0x023C, 3, 0x0000, 0), /* MX6Q_PAD_GPIO_5__CCM_CLKO */
1373 IMX_PIN_REG(MX6Q_PAD_GPIO_5, 0x060C, 0x023C, 4, 0x0000, 0), /* MX6Q_PAD_GPIO_5__CSU_CSU_ALARM_AUT_2 */
1374 IMX_PIN_REG(MX6Q_PAD_GPIO_5, 0x060C, 0x023C, 5, 0x0000, 0), /* MX6Q_PAD_GPIO_5__GPIO_1_5 */
1375 IMX_PIN_REG(MX6Q_PAD_GPIO_5, 0x060C, 0x023C, 6, 0x08A8, 2), /* MX6Q_PAD_GPIO_5__I2C3_SCL */
1376 IMX_PIN_REG(MX6Q_PAD_GPIO_5, 0x060C, 0x023C, 7, 0x0000, 0), /* MX6Q_PAD_GPIO_5__CHEETAH_EVENTI */
1377 IMX_PIN_REG(MX6Q_PAD_GPIO_7, 0x0610, 0x0240, 0, 0x0884, 1), /* MX6Q_PAD_GPIO_7__ESAI1_TX4_RX1 */
1378 IMX_PIN_REG(MX6Q_PAD_GPIO_7, 0x0610, 0x0240, 1, 0x0000, 0), /* MX6Q_PAD_GPIO_7__ECSPI5_RDY */
1379 IMX_PIN_REG(MX6Q_PAD_GPIO_7, 0x0610, 0x0240, 2, 0x0000, 0), /* MX6Q_PAD_GPIO_7__EPIT1_EPITO */
1380 IMX_PIN_REG(MX6Q_PAD_GPIO_7, 0x0610, 0x0240, 3, 0x0000, 0), /* MX6Q_PAD_GPIO_7__CAN1_TXCAN */
1381 IMX_PIN_REG(MX6Q_PAD_GPIO_7, 0x0610, 0x0240, 4, 0x0000, 0), /* MX6Q_PAD_GPIO_7__UART2_TXD */
1382 IMX_PIN_REG(MX6Q_PAD_GPIO_7, 0x0610, 0x0240, 5, 0x0000, 0), /* MX6Q_PAD_GPIO_7__GPIO_1_7 */
1383 IMX_PIN_REG(MX6Q_PAD_GPIO_7, 0x0610, 0x0240, 6, 0x0000, 0), /* MX6Q_PAD_GPIO_7__SPDIF_PLOCK */
1384 IMX_PIN_REG(MX6Q_PAD_GPIO_7, 0x0610, 0x0240, 7, 0x0000, 0), /* MX6Q_PAD_GPIO_7__USBOH3_OTGUSB_HST_MODE */
1385 IMX_PIN_REG(MX6Q_PAD_GPIO_8, 0x0614, 0x0244, 0, 0x0888, 1), /* MX6Q_PAD_GPIO_8__ESAI1_TX5_RX0 */
1386 IMX_PIN_REG(MX6Q_PAD_GPIO_8, 0x0614, 0x0244, 1, 0x0000, 0), /* MX6Q_PAD_GPIO_8__ANATOP_ANATOP_32K_OUT */
1387 IMX_PIN_REG(MX6Q_PAD_GPIO_8, 0x0614, 0x0244, 2, 0x0000, 0), /* MX6Q_PAD_GPIO_8__EPIT2_EPITO */
1388 IMX_PIN_REG(MX6Q_PAD_GPIO_8, 0x0614, 0x0244, 3, 0x07E4, 1), /* MX6Q_PAD_GPIO_8__CAN1_RXCAN */
1389 IMX_PIN_REG(MX6Q_PAD_GPIO_8, 0x0614, 0x0244, 4, 0x0928, 3), /* MX6Q_PAD_GPIO_8__UART2_RXD */
1390 IMX_PIN_REG(MX6Q_PAD_GPIO_8, 0x0614, 0x0244, 5, 0x0000, 0), /* MX6Q_PAD_GPIO_8__GPIO_1_8 */
1391 IMX_PIN_REG(MX6Q_PAD_GPIO_8, 0x0614, 0x0244, 6, 0x0000, 0), /* MX6Q_PAD_GPIO_8__SPDIF_SRCLK */
1392 IMX_PIN_REG(MX6Q_PAD_GPIO_8, 0x0614, 0x0244, 7, 0x0000, 0), /* MX6Q_PAD_GPIO_8__USBOH3_OTG_PWRCTL_WAK */
1393 IMX_PIN_REG(MX6Q_PAD_GPIO_16, 0x0618, 0x0248, 0, 0x0880, 1), /* MX6Q_PAD_GPIO_16__ESAI1_TX3_RX2 */
1394 IMX_PIN_REG(MX6Q_PAD_GPIO_16, 0x0618, 0x0248, 1, 0x0000, 0), /* MX6Q_PAD_GPIO_16__ENET_1588_EVENT2_IN */
1395 IMX_PIN_REG(MX6Q_PAD_GPIO_16, 0x0618, 0x0248, 2, 0x083C, 1), /* MX6Q_PAD_GPIO_16__ENET_ETHERNET_REF_OUT */
1396 IMX_PIN_REG(MX6Q_PAD_GPIO_16, 0x0618, 0x0248, 3, 0x0000, 0), /* MX6Q_PAD_GPIO_16__USDHC1_LCTL */
1397 IMX_PIN_REG(MX6Q_PAD_GPIO_16, 0x0618, 0x0248, 4, 0x0914, 3), /* MX6Q_PAD_GPIO_16__SPDIF_IN1 */
1398 IMX_PIN_REG(MX6Q_PAD_GPIO_16, 0x0618, 0x0248, 5, 0x0000, 0), /* MX6Q_PAD_GPIO_16__GPIO_7_11 */
1399 IMX_PIN_REG(MX6Q_PAD_GPIO_16, 0x0618, 0x0248, 6, 0x08AC, 2), /* MX6Q_PAD_GPIO_16__I2C3_SDA */
1400 IMX_PIN_REG(MX6Q_PAD_GPIO_16, 0x0618, 0x0248, 7, 0x0000, 0), /* MX6Q_PAD_GPIO_16__SJC_DE_B */
1401 IMX_PIN_REG(MX6Q_PAD_GPIO_17, 0x061C, 0x024C, 0, 0x0874, 0), /* MX6Q_PAD_GPIO_17__ESAI1_TX0 */
1402 IMX_PIN_REG(MX6Q_PAD_GPIO_17, 0x061C, 0x024C, 1, 0x0000, 0), /* MX6Q_PAD_GPIO_17__ENET_1588_EVENT3_IN */
1403 IMX_PIN_REG(MX6Q_PAD_GPIO_17, 0x061C, 0x024C, 2, 0x07F0, 1), /* MX6Q_PAD_GPIO_17__CCM_PMIC_RDY */
1404 IMX_PIN_REG(MX6Q_PAD_GPIO_17, 0x061C, 0x024C, 3, 0x090C, 1), /* MX6Q_PAD_GPIO_17__SDMA_SDMA_EXT_EVENT_0 */
1405 IMX_PIN_REG(MX6Q_PAD_GPIO_17, 0x061C, 0x024C, 4, 0x0000, 0), /* MX6Q_PAD_GPIO_17__SPDIF_OUT1 */
1406 IMX_PIN_REG(MX6Q_PAD_GPIO_17, 0x061C, 0x024C, 5, 0x0000, 0), /* MX6Q_PAD_GPIO_17__GPIO_7_12 */
1407 IMX_PIN_REG(MX6Q_PAD_GPIO_17, 0x061C, 0x024C, 7, 0x0000, 0), /* MX6Q_PAD_GPIO_17__SJC_JTAG_ACT */
1408 IMX_PIN_REG(MX6Q_PAD_GPIO_18, 0x0620, 0x0250, 0, 0x0878, 0), /* MX6Q_PAD_GPIO_18__ESAI1_TX1 */
1409 IMX_PIN_REG(MX6Q_PAD_GPIO_18, 0x0620, 0x0250, 1, 0x0844, 1), /* MX6Q_PAD_GPIO_18__ENET_RX_CLK */
1410 IMX_PIN_REG(MX6Q_PAD_GPIO_18, 0x0620, 0x0250, 2, 0x0000, 0), /* MX6Q_PAD_GPIO_18__USDHC3_VSELECT */
1411 IMX_PIN_REG(MX6Q_PAD_GPIO_18, 0x0620, 0x0250, 3, 0x0910, 1), /* MX6Q_PAD_GPIO_18__SDMA_SDMA_EXT_EVENT_1 */
1412 IMX_PIN_REG(MX6Q_PAD_GPIO_18, 0x0620, 0x0250, 4, 0x07B0, 2), /* MX6Q_PAD_GPIO_18__ASRC_ASRC_EXT_CLK */
1413 IMX_PIN_REG(MX6Q_PAD_GPIO_18, 0x0620, 0x0250, 5, 0x0000, 0), /* MX6Q_PAD_GPIO_18__GPIO_7_13 */
1414 IMX_PIN_REG(MX6Q_PAD_GPIO_18, 0x0620, 0x0250, 6, 0x0000, 0), /* MX6Q_PAD_GPIO_18__SNVS_HP_WRA_SNVS_VIO5 */
1415 IMX_PIN_REG(MX6Q_PAD_GPIO_18, 0x0620, 0x0250, 7, 0x0000, 0), /* MX6Q_PAD_GPIO_18__SRC_SYSTEM_RST */
1416 IMX_PIN_REG(MX6Q_PAD_GPIO_19, 0x0624, 0x0254, 0, 0x08E8, 1), /* MX6Q_PAD_GPIO_19__KPP_COL_5 */
1417 IMX_PIN_REG(MX6Q_PAD_GPIO_19, 0x0624, 0x0254, 1, 0x0000, 0), /* MX6Q_PAD_GPIO_19__ENET_1588_EVENT0_OUT */
1418 IMX_PIN_REG(MX6Q_PAD_GPIO_19, 0x0624, 0x0254, 2, 0x0000, 0), /* MX6Q_PAD_GPIO_19__SPDIF_OUT1 */
1419 IMX_PIN_REG(MX6Q_PAD_GPIO_19, 0x0624, 0x0254, 3, 0x0000, 0), /* MX6Q_PAD_GPIO_19__CCM_CLKO */
1420 IMX_PIN_REG(MX6Q_PAD_GPIO_19, 0x0624, 0x0254, 4, 0x0000, 0), /* MX6Q_PAD_GPIO_19__ECSPI1_RDY */
1421 IMX_PIN_REG(MX6Q_PAD_GPIO_19, 0x0624, 0x0254, 5, 0x0000, 0), /* MX6Q_PAD_GPIO_19__GPIO_4_5 */
1422 IMX_PIN_REG(MX6Q_PAD_GPIO_19, 0x0624, 0x0254, 6, 0x0000, 0), /* MX6Q_PAD_GPIO_19__ENET_TX_ER */
1423 IMX_PIN_REG(MX6Q_PAD_GPIO_19, 0x0624, 0x0254, 7, 0x0000, 0), /* MX6Q_PAD_GPIO_19__SRC_INT_BOOT */
1424 IMX_PIN_REG(MX6Q_PAD_CSI0_PIXCLK, 0x0628, 0x0258, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK */
1425 IMX_PIN_REG(MX6Q_PAD_CSI0_PIXCLK, 0x0628, 0x0258, 2, 0x0000, 0), /* MX6Q_PAD_CSI0_PIXCLK__PCIE_CTRL_MUX_12 */
1426 IMX_PIN_REG(MX6Q_PAD_CSI0_PIXCLK, 0x0628, 0x0258, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_PIXCLK__SDMA_DEBUG_PC_0 */
1427 IMX_PIN_REG(MX6Q_PAD_CSI0_PIXCLK, 0x0628, 0x0258, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_PIXCLK__GPIO_5_18 */
1428 IMX_PIN_REG(MX6Q_PAD_CSI0_PIXCLK, 0x0628, 0x0258, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_PIXCLK___MMDC_DEBUG_29 */
1429 IMX_PIN_REG(MX6Q_PAD_CSI0_PIXCLK, 0x0628, 0x0258, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_PIXCLK__CHEETAH_EVENTO */
1430 IMX_PIN_REG(MX6Q_PAD_CSI0_MCLK, 0x062C, 0x025C, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC */
1431 IMX_PIN_REG(MX6Q_PAD_CSI0_MCLK, 0x062C, 0x025C, 2, 0x0000, 0), /* MX6Q_PAD_CSI0_MCLK__PCIE_CTRL_MUX_13 */
1432 IMX_PIN_REG(MX6Q_PAD_CSI0_MCLK, 0x062C, 0x025C, 3, 0x0000, 0), /* MX6Q_PAD_CSI0_MCLK__CCM_CLKO */
1433 IMX_PIN_REG(MX6Q_PAD_CSI0_MCLK, 0x062C, 0x025C, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_MCLK__SDMA_DEBUG_PC_1 */
1434 IMX_PIN_REG(MX6Q_PAD_CSI0_MCLK, 0x062C, 0x025C, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_MCLK__GPIO_5_19 */
1435 IMX_PIN_REG(MX6Q_PAD_CSI0_MCLK, 0x062C, 0x025C, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_MCLK__MMDC_MMDC_DEBUG_30 */
1436 IMX_PIN_REG(MX6Q_PAD_CSI0_MCLK, 0x062C, 0x025C, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_MCLK__CHEETAH_TRCTL */
1437 IMX_PIN_REG(MX6Q_PAD_CSI0_DATA_EN, 0x0630, 0x0260, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_DATA_EN__IPU1_CSI0_DA_EN */
1438 IMX_PIN_REG(MX6Q_PAD_CSI0_DATA_EN, 0x0630, 0x0260, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_DATA_EN__WEIM_WEIM_D_0 */
1439 IMX_PIN_REG(MX6Q_PAD_CSI0_DATA_EN, 0x0630, 0x0260, 2, 0x0000, 0), /* MX6Q_PAD_CSI0_DATA_EN__PCIE_CTRL_MUX_14 */
1440 IMX_PIN_REG(MX6Q_PAD_CSI0_DATA_EN, 0x0630, 0x0260, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_DATA_EN__SDMA_DEBUG_PC_2 */
1441 IMX_PIN_REG(MX6Q_PAD_CSI0_DATA_EN, 0x0630, 0x0260, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_DATA_EN__GPIO_5_20 */
1442 IMX_PIN_REG(MX6Q_PAD_CSI0_DATA_EN, 0x0630, 0x0260, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_DATA_EN__MMDC_DEBUG_31 */
1443 IMX_PIN_REG(MX6Q_PAD_CSI0_DATA_EN, 0x0630, 0x0260, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_DATA_EN__CHEETAH_TRCLK */
1444 IMX_PIN_REG(MX6Q_PAD_CSI0_VSYNC, 0x0634, 0x0264, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC */
1445 IMX_PIN_REG(MX6Q_PAD_CSI0_VSYNC, 0x0634, 0x0264, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_VSYNC__WEIM_WEIM_D_1 */
1446 IMX_PIN_REG(MX6Q_PAD_CSI0_VSYNC, 0x0634, 0x0264, 2, 0x0000, 0), /* MX6Q_PAD_CSI0_VSYNC__PCIE_CTRL_MUX_15 */
1447 IMX_PIN_REG(MX6Q_PAD_CSI0_VSYNC, 0x0634, 0x0264, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_VSYNC__SDMA_DEBUG_PC_3 */
1448 IMX_PIN_REG(MX6Q_PAD_CSI0_VSYNC, 0x0634, 0x0264, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_VSYNC__GPIO_5_21 */
1449 IMX_PIN_REG(MX6Q_PAD_CSI0_VSYNC, 0x0634, 0x0264, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_VSYNC__MMDC_DEBUG_32 */
1450 IMX_PIN_REG(MX6Q_PAD_CSI0_VSYNC, 0x0634, 0x0264, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_VSYNC__CHEETAH_TRACE_0 */
1451 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT4, 0x0638, 0x0268, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT4__IPU1_CSI0_D_4 */
1452 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT4, 0x0638, 0x0268, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT4__WEIM_WEIM_D_2 */
1453 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT4, 0x0638, 0x0268, 2, 0x07F4, 3), /* MX6Q_PAD_CSI0_DAT4__ECSPI1_SCLK */
1454 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT4, 0x0638, 0x0268, 3, 0x08E8, 2), /* MX6Q_PAD_CSI0_DAT4__KPP_COL_5 */
1455 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT4, 0x0638, 0x0268, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC */
1456 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT4, 0x0638, 0x0268, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT4__GPIO_5_22 */
1457 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT4, 0x0638, 0x0268, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT4__MMDC_DEBUG_43 */
1458 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT4, 0x0638, 0x0268, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT4__CHEETAH_TRACE_1 */
1459 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT5, 0x063C, 0x026C, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT5__IPU1_CSI0_D_5 */
1460 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT5, 0x063C, 0x026C, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT5__WEIM_WEIM_D_3 */
1461 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT5, 0x063C, 0x026C, 2, 0x07FC, 3), /* MX6Q_PAD_CSI0_DAT5__ECSPI1_MOSI */
1462 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT5, 0x063C, 0x026C, 3, 0x08F4, 1), /* MX6Q_PAD_CSI0_DAT5__KPP_ROW_5 */
1463 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT5, 0x063C, 0x026C, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD */
1464 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT5, 0x063C, 0x026C, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT5__GPIO_5_23 */
1465 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT5, 0x063C, 0x026C, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT5__MMDC_MMDC_DEBUG_44 */
1466 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT5, 0x063C, 0x026C, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT5__CHEETAH_TRACE_2 */
1467 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT6, 0x0640, 0x0270, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT6__IPU1_CSI0_D_6 */
1468 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT6, 0x0640, 0x0270, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT6__WEIM_WEIM_D_4 */
1469 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT6, 0x0640, 0x0270, 2, 0x07F8, 3), /* MX6Q_PAD_CSI0_DAT6__ECSPI1_MISO */
1470 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT6, 0x0640, 0x0270, 3, 0x08EC, 1), /* MX6Q_PAD_CSI0_DAT6__KPP_COL_6 */
1471 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT6, 0x0640, 0x0270, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS */
1472 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT6, 0x0640, 0x0270, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT6__GPIO_5_24 */
1473 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT6, 0x0640, 0x0270, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT6__MMDC_MMDC_DEBUG_45 */
1474 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT6, 0x0640, 0x0270, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT6__CHEETAH_TRACE_3 */
1475 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT7, 0x0644, 0x0274, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT7__IPU1_CSI0_D_7 */
1476 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT7, 0x0644, 0x0274, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT7__WEIM_WEIM_D_5 */
1477 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT7, 0x0644, 0x0274, 2, 0x0800, 3), /* MX6Q_PAD_CSI0_DAT7__ECSPI1_SS0 */
1478 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT7, 0x0644, 0x0274, 3, 0x08F8, 2), /* MX6Q_PAD_CSI0_DAT7__KPP_ROW_6 */
1479 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT7, 0x0644, 0x0274, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD */
1480 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT7, 0x0644, 0x0274, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT7__GPIO_5_25 */
1481 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT7, 0x0644, 0x0274, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT7__MMDC_MMDC_DEBUG_46 */
1482 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT7, 0x0644, 0x0274, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT7__CHEETAH_TRACE_4 */
1483 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT8, 0x0648, 0x0278, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT8__IPU1_CSI0_D_8 */
1484 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT8, 0x0648, 0x0278, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT8__WEIM_WEIM_D_6 */
1485 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT8, 0x0648, 0x0278, 2, 0x0810, 2), /* MX6Q_PAD_CSI0_DAT8__ECSPI2_SCLK */
1486 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT8, 0x0648, 0x0278, 3, 0x08F0, 2), /* MX6Q_PAD_CSI0_DAT8__KPP_COL_7 */
1487 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT8, 0x0648, 0x0278, 4, 0x089C, 1), /* MX6Q_PAD_CSI0_DAT8__I2C1_SDA */
1488 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT8, 0x0648, 0x0278, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT8__GPIO_5_26 */
1489 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT8, 0x0648, 0x0278, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT8__MMDC_MMDC_DEBUG_47 */
1490 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT8, 0x0648, 0x0278, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT8__CHEETAH_TRACE_5 */
1491 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT9, 0x064C, 0x027C, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT9__IPU1_CSI0_D_9 */
1492 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT9, 0x064C, 0x027C, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT9__WEIM_WEIM_D_7 */
1493 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT9, 0x064C, 0x027C, 2, 0x0818, 2), /* MX6Q_PAD_CSI0_DAT9__ECSPI2_MOSI */
1494 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT9, 0x064C, 0x027C, 3, 0x08FC, 2), /* MX6Q_PAD_CSI0_DAT9__KPP_ROW_7 */
1495 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT9, 0x064C, 0x027C, 4, 0x0898, 1), /* MX6Q_PAD_CSI0_DAT9__I2C1_SCL */
1496 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT9, 0x064C, 0x027C, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT9__GPIO_5_27 */
1497 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT9, 0x064C, 0x027C, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT9__MMDC_MMDC_DEBUG_48 */
1498 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT9, 0x064C, 0x027C, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT9__CHEETAH_TRACE_6 */
1499 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT10, 0x0650, 0x0280, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT10__IPU1_CSI0_D_10 */
1500 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT10, 0x0650, 0x0280, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT10__AUDMUX_AUD3_RXC */
1501 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT10, 0x0650, 0x0280, 2, 0x0814, 2), /* MX6Q_PAD_CSI0_DAT10__ECSPI2_MISO */
1502 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT10, 0x0650, 0x0280, 3, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT10__UART1_TXD */
1503 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT10, 0x0650, 0x0280, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT10__SDMA_DEBUG_PC_4 */
1504 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT10, 0x0650, 0x0280, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT10__GPIO_5_28 */
1505 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT10, 0x0650, 0x0280, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT10__MMDC_MMDC_DEBUG_33 */
1506 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT10, 0x0650, 0x0280, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT10__CHEETAH_TRACE_7 */
1507 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT11, 0x0654, 0x0284, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT11__IPU1_CSI0_D_11 */
1508 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT11, 0x0654, 0x0284, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT11__AUDMUX_AUD3_RXFS */
1509 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT11, 0x0654, 0x0284, 2, 0x081C, 2), /* MX6Q_PAD_CSI0_DAT11__ECSPI2_SS0 */
1510 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT11, 0x0654, 0x0284, 3, 0x0920, 1), /* MX6Q_PAD_CSI0_DAT11__UART1_RXD */
1511 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT11, 0x0654, 0x0284, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT11__SDMA_DEBUG_PC_5 */
1512 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT11, 0x0654, 0x0284, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT11__GPIO_5_29 */
1513 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT11, 0x0654, 0x0284, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT11__MMDC_MMDC_DEBUG_34 */
1514 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT11, 0x0654, 0x0284, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT11__CHEETAH_TRACE_8 */
1515 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT12, 0x0658, 0x0288, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT12__IPU1_CSI0_D_12 */
1516 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT12, 0x0658, 0x0288, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT12__WEIM_WEIM_D_8 */
1517 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT12, 0x0658, 0x0288, 2, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT12__PCIE_CTRL_MUX_16 */
1518 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT12, 0x0658, 0x0288, 3, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT12__UART4_TXD */
1519 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT12, 0x0658, 0x0288, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT12__SDMA_DEBUG_PC_6 */
1520 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT12, 0x0658, 0x0288, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT12__GPIO_5_30 */
1521 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT12, 0x0658, 0x0288, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT12__MMDC_MMDC_DEBUG_35 */
1522 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT12, 0x0658, 0x0288, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT12__CHEETAH_TRACE_9 */
1523 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT13, 0x065C, 0x028C, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT13__IPU1_CSI0_D_13 */
1524 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT13, 0x065C, 0x028C, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT13__WEIM_WEIM_D_9 */
1525 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT13, 0x065C, 0x028C, 2, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT13__PCIE_CTRL_MUX_17 */
1526 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT13, 0x065C, 0x028C, 3, 0x0938, 3), /* MX6Q_PAD_CSI0_DAT13__UART4_RXD */
1527 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT13, 0x065C, 0x028C, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT13__SDMA_DEBUG_PC_7 */
1528 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT13, 0x065C, 0x028C, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT13__GPIO_5_31 */
1529 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT13, 0x065C, 0x028C, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT13__MMDC_MMDC_DEBUG_36 */
1530 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT13, 0x065C, 0x028C, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT13__CHEETAH_TRACE_10 */
1531 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT14, 0x0660, 0x0290, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT14__IPU1_CSI0_D_14 */
1532 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT14, 0x0660, 0x0290, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT14__WEIM_WEIM_D_10 */
1533 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT14, 0x0660, 0x0290, 2, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT14__PCIE_CTRL_MUX_18 */
1534 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT14, 0x0660, 0x0290, 3, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT14__UART5_TXD */
1535 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT14, 0x0660, 0x0290, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT14__SDMA_DEBUG_PC_8 */
1536 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT14, 0x0660, 0x0290, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT14__GPIO_6_0 */
1537 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT14, 0x0660, 0x0290, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT14__MMDC_MMDC_DEBUG_37 */
1538 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT14, 0x0660, 0x0290, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT14__CHEETAH_TRACE_11 */
1539 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT15, 0x0664, 0x0294, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT15__IPU1_CSI0_D_15 */
1540 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT15, 0x0664, 0x0294, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT15__WEIM_WEIM_D_11 */
1541 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT15, 0x0664, 0x0294, 2, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT15__PCIE_CTRL_MUX_19 */
1542 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT15, 0x0664, 0x0294, 3, 0x0940, 3), /* MX6Q_PAD_CSI0_DAT15__UART5_RXD */
1543 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT15, 0x0664, 0x0294, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT15__SDMA_DEBUG_PC_9 */
1544 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT15, 0x0664, 0x0294, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT15__GPIO_6_1 */
1545 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT15, 0x0664, 0x0294, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT15__MMDC_MMDC_DEBUG_38 */
1546 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT15, 0x0664, 0x0294, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT15__CHEETAH_TRACE_12 */
1547 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT16, 0x0668, 0x0298, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT16__IPU1_CSI0_D_16 */
1548 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT16, 0x0668, 0x0298, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT16__WEIM_WEIM_D_12 */
1549 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT16, 0x0668, 0x0298, 2, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT16__PCIE_CTRL_MUX_20 */
1550 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT16, 0x0668, 0x0298, 3, 0x0934, 0), /* MX6Q_PAD_CSI0_DAT16__UART4_RTS */
1551 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT16, 0x0668, 0x0298, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT16__SDMA_DEBUG_PC_10 */
1552 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT16, 0x0668, 0x0298, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT16__GPIO_6_2 */
1553 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT16, 0x0668, 0x0298, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT16__MMDC_MMDC_DEBUG_39 */
1554 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT16, 0x0668, 0x0298, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT16__CHEETAH_TRACE_13 */
1555 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT17, 0x066C, 0x029C, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT17__IPU1_CSI0_D_17 */
1556 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT17, 0x066C, 0x029C, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT17__WEIM_WEIM_D_13 */
1557 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT17, 0x066C, 0x029C, 2, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT17__PCIE_CTRL_MUX_21 */
1558 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT17, 0x066C, 0x029C, 3, 0x0934, 1), /* MX6Q_PAD_CSI0_DAT17__UART4_CTS */
1559 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT17, 0x066C, 0x029C, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT17__SDMA_DEBUG_PC_11 */
1560 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT17, 0x066C, 0x029C, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT17__GPIO_6_3 */
1561 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT17, 0x066C, 0x029C, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT17__MMDC_MMDC_DEBUG_40 */
1562 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT17, 0x066C, 0x029C, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT17__CHEETAH_TRACE_14 */
1563 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT18, 0x0670, 0x02A0, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT18__IPU1_CSI0_D_18 */
1564 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT18, 0x0670, 0x02A0, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT18__WEIM_WEIM_D_14 */
1565 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT18, 0x0670, 0x02A0, 2, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT18__PCIE_CTRL_MUX_22 */
1566 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT18, 0x0670, 0x02A0, 3, 0x093C, 2), /* MX6Q_PAD_CSI0_DAT18__UART5_RTS */
1567 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT18, 0x0670, 0x02A0, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT18__SDMA_DEBUG_PC_12 */
1568 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT18, 0x0670, 0x02A0, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT18__GPIO_6_4 */
1569 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT18, 0x0670, 0x02A0, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT18__MMDC_MMDC_DEBUG_41 */
1570 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT18, 0x0670, 0x02A0, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT18__CHEETAH_TRACE_15 */
1571 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT19, 0x0674, 0x02A4, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT19__IPU1_CSI0_D_19 */
1572 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT19, 0x0674, 0x02A4, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT19__WEIM_WEIM_D_15 */
1573 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT19, 0x0674, 0x02A4, 2, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT19__PCIE_CTRL_MUX_23 */
1574 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT19, 0x0674, 0x02A4, 3, 0x093C, 3), /* MX6Q_PAD_CSI0_DAT19__UART5_CTS */
1575 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT19, 0x0674, 0x02A4, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT19__SDMA_DEBUG_PC_13 */
1576 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT19, 0x0674, 0x02A4, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT19__GPIO_6_5 */
1577 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT19, 0x0674, 0x02A4, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT19__MMDC_MMDC_DEBUG_42 */
1578 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT19, 0x0674, 0x02A4, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT19__ANATOP_TESTO_9 */
1579 IMX_PIN_REG(MX6Q_PAD_JTAG_TMS, 0x0678, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_JTAG_TMS__SJC_TMS */
1580 IMX_PIN_REG(MX6Q_PAD_JTAG_MOD, 0x067C, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_JTAG_MOD__SJC_MOD */
1581 IMX_PIN_REG(MX6Q_PAD_JTAG_TRSTB, 0x0680, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_JTAG_TRSTB__SJC_TRSTB */
1582 IMX_PIN_REG(MX6Q_PAD_JTAG_TDI, 0x0684, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_JTAG_TDI__SJC_TDI */
1583 IMX_PIN_REG(MX6Q_PAD_JTAG_TCK, 0x0688, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_JTAG_TCK__SJC_TCK */
1584 IMX_PIN_REG(MX6Q_PAD_JTAG_TDO, 0x068C, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_JTAG_TDO__SJC_TDO */
1585 IMX_PIN_REG(MX6Q_PAD_LVDS1_TX3_P, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 */
1586 IMX_PIN_REG(MX6Q_PAD_LVDS1_TX2_P, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 */
1587 IMX_PIN_REG(MX6Q_PAD_LVDS1_CLK_P, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK */
1588 IMX_PIN_REG(MX6Q_PAD_LVDS1_TX1_P, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 */
1589 IMX_PIN_REG(MX6Q_PAD_LVDS1_TX0_P, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 */
1590 IMX_PIN_REG(MX6Q_PAD_LVDS0_TX3_P, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 */
1591 IMX_PIN_REG(MX6Q_PAD_LVDS0_CLK_P, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK */
1592 IMX_PIN_REG(MX6Q_PAD_LVDS0_TX2_P, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 */
1593 IMX_PIN_REG(MX6Q_PAD_LVDS0_TX1_P, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 */
1594 IMX_PIN_REG(MX6Q_PAD_LVDS0_TX0_P, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 */
1595 IMX_PIN_REG(MX6Q_PAD_TAMPER, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_TAMPER__SNVS_LP_WRAP_SNVS_TD1 */
1596 IMX_PIN_REG(MX6Q_PAD_PMIC_ON_REQ, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_PMIC_ON_REQ__SNVS_LPWRAP_WKALM */
1597 IMX_PIN_REG(MX6Q_PAD_PMIC_STBY_REQ, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_PMIC_STBY_REQ__CCM_PMIC_STBYRQ */
1598 IMX_PIN_REG(MX6Q_PAD_POR_B, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_POR_B__SRC_POR_B */
1599 IMX_PIN_REG(MX6Q_PAD_BOOT_MODE1, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_BOOT_MODE1__SRC_BOOT_MODE_1 */
1600 IMX_PIN_REG(MX6Q_PAD_RESET_IN_B, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_RESET_IN_B__SRC_RESET_B */
1601 IMX_PIN_REG(MX6Q_PAD_BOOT_MODE0, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_BOOT_MODE0__SRC_BOOT_MODE_0 */
1602 IMX_PIN_REG(MX6Q_PAD_TEST_MODE, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_TEST_MODE__TCU_TEST_MODE */
1603 IMX_PIN_REG(MX6Q_PAD_SD3_DAT7, 0x0690, 0x02A8, 0, 0x0000, 0), /* MX6Q_PAD_SD3_DAT7__USDHC3_DAT7 */
1604 IMX_PIN_REG(MX6Q_PAD_SD3_DAT7, 0x0690, 0x02A8, 1, 0x0000, 0), /* MX6Q_PAD_SD3_DAT7__UART1_TXD */
1605 IMX_PIN_REG(MX6Q_PAD_SD3_DAT7, 0x0690, 0x02A8, 2, 0x0000, 0), /* MX6Q_PAD_SD3_DAT7__PCIE_CTRL_MUX_24 */
1606 IMX_PIN_REG(MX6Q_PAD_SD3_DAT7, 0x0690, 0x02A8, 3, 0x0000, 0), /* MX6Q_PAD_SD3_DAT7__USBOH3_UH3_DFD_OUT_0 */
1607 IMX_PIN_REG(MX6Q_PAD_SD3_DAT7, 0x0690, 0x02A8, 4, 0x0000, 0), /* MX6Q_PAD_SD3_DAT7__USBOH3_UH2_DFD_OUT_0 */
1608 IMX_PIN_REG(MX6Q_PAD_SD3_DAT7, 0x0690, 0x02A8, 5, 0x0000, 0), /* MX6Q_PAD_SD3_DAT7__GPIO_6_17 */
1609 IMX_PIN_REG(MX6Q_PAD_SD3_DAT7, 0x0690, 0x02A8, 6, 0x0000, 0), /* MX6Q_PAD_SD3_DAT7__MIPI_CORE_DPHY_IN_12 */
1610 IMX_PIN_REG(MX6Q_PAD_SD3_DAT7, 0x0690, 0x02A8, 7, 0x0000, 0), /* MX6Q_PAD_SD3_DAT7__USBPHY2_CLK20DIV */
1611 IMX_PIN_REG(MX6Q_PAD_SD3_DAT6, 0x0694, 0x02AC, 0, 0x0000, 0), /* MX6Q_PAD_SD3_DAT6__USDHC3_DAT6 */
1612 IMX_PIN_REG(MX6Q_PAD_SD3_DAT6, 0x0694, 0x02AC, 1, 0x0920, 3), /* MX6Q_PAD_SD3_DAT6__UART1_RXD */
1613 IMX_PIN_REG(MX6Q_PAD_SD3_DAT6, 0x0694, 0x02AC, 2, 0x0000, 0), /* MX6Q_PAD_SD3_DAT6__PCIE_CTRL_MUX_25 */
1614 IMX_PIN_REG(MX6Q_PAD_SD3_DAT6, 0x0694, 0x02AC, 3, 0x0000, 0), /* MX6Q_PAD_SD3_DAT6__USBOH3_UH3_DFD_OUT_1 */
1615 IMX_PIN_REG(MX6Q_PAD_SD3_DAT6, 0x0694, 0x02AC, 4, 0x0000, 0), /* MX6Q_PAD_SD3_DAT6__USBOH3_UH2_DFD_OUT_1 */
1616 IMX_PIN_REG(MX6Q_PAD_SD3_DAT6, 0x0694, 0x02AC, 5, 0x0000, 0), /* MX6Q_PAD_SD3_DAT6__GPIO_6_18 */
1617 IMX_PIN_REG(MX6Q_PAD_SD3_DAT6, 0x0694, 0x02AC, 6, 0x0000, 0), /* MX6Q_PAD_SD3_DAT6__MIPI_CORE_DPHY_IN_13 */
1618 IMX_PIN_REG(MX6Q_PAD_SD3_DAT6, 0x0694, 0x02AC, 7, 0x0000, 0), /* MX6Q_PAD_SD3_DAT6__ANATOP_TESTO_10 */
1619 IMX_PIN_REG(MX6Q_PAD_SD3_DAT5, 0x0698, 0x02B0, 0, 0x0000, 0), /* MX6Q_PAD_SD3_DAT5__USDHC3_DAT5 */
1620 IMX_PIN_REG(MX6Q_PAD_SD3_DAT5, 0x0698, 0x02B0, 1, 0x0000, 0), /* MX6Q_PAD_SD3_DAT5__UART2_TXD */
1621 IMX_PIN_REG(MX6Q_PAD_SD3_DAT5, 0x0698, 0x02B0, 2, 0x0000, 0), /* MX6Q_PAD_SD3_DAT5__PCIE_CTRL_MUX_26 */
1622 IMX_PIN_REG(MX6Q_PAD_SD3_DAT5, 0x0698, 0x02B0, 3, 0x0000, 0), /* MX6Q_PAD_SD3_DAT5__USBOH3_UH3_DFD_OUT_2 */
1623 IMX_PIN_REG(MX6Q_PAD_SD3_DAT5, 0x0698, 0x02B0, 4, 0x0000, 0), /* MX6Q_PAD_SD3_DAT5__USBOH3_UH2_DFD_OUT_2 */
1624 IMX_PIN_REG(MX6Q_PAD_SD3_DAT5, 0x0698, 0x02B0, 5, 0x0000, 0), /* MX6Q_PAD_SD3_DAT5__GPIO_7_0 */
1625 IMX_PIN_REG(MX6Q_PAD_SD3_DAT5, 0x0698, 0x02B0, 6, 0x0000, 0), /* MX6Q_PAD_SD3_DAT5__MIPI_CORE_DPHY_IN_14 */
1626 IMX_PIN_REG(MX6Q_PAD_SD3_DAT5, 0x0698, 0x02B0, 7, 0x0000, 0), /* MX6Q_PAD_SD3_DAT5__ANATOP_TESTO_11 */
1627 IMX_PIN_REG(MX6Q_PAD_SD3_DAT4, 0x069C, 0x02B4, 0, 0x0000, 0), /* MX6Q_PAD_SD3_DAT4__USDHC3_DAT4 */
1628 IMX_PIN_REG(MX6Q_PAD_SD3_DAT4, 0x069C, 0x02B4, 1, 0x0928, 5), /* MX6Q_PAD_SD3_DAT4__UART2_RXD */
1629 IMX_PIN_REG(MX6Q_PAD_SD3_DAT4, 0x069C, 0x02B4, 2, 0x0000, 0), /* MX6Q_PAD_SD3_DAT4__PCIE_CTRL_MUX_27 */
1630 IMX_PIN_REG(MX6Q_PAD_SD3_DAT4, 0x069C, 0x02B4, 3, 0x0000, 0), /* MX6Q_PAD_SD3_DAT4__USBOH3_UH3_DFD_OUT_3 */
1631 IMX_PIN_REG(MX6Q_PAD_SD3_DAT4, 0x069C, 0x02B4, 4, 0x0000, 0), /* MX6Q_PAD_SD3_DAT4__USBOH3_UH2_DFD_OUT_3 */
1632 IMX_PIN_REG(MX6Q_PAD_SD3_DAT4, 0x069C, 0x02B4, 5, 0x0000, 0), /* MX6Q_PAD_SD3_DAT4__GPIO_7_1 */
1633 IMX_PIN_REG(MX6Q_PAD_SD3_DAT4, 0x069C, 0x02B4, 6, 0x0000, 0), /* MX6Q_PAD_SD3_DAT4__MIPI_CORE_DPHY_IN_15 */
1634 IMX_PIN_REG(MX6Q_PAD_SD3_DAT4, 0x069C, 0x02B4, 7, 0x0000, 0), /* MX6Q_PAD_SD3_DAT4__ANATOP_TESTO_12 */
1635 IMX_PIN_REG(MX6Q_PAD_SD3_CMD, 0x06A0, 0x02B8, 0, 0x0000, 0), /* MX6Q_PAD_SD3_CMD__USDHC3_CMD */
1636 IMX_PIN_REG(MX6Q_PAD_SD3_CMD, 0x06A0, 0x02B8, 1, 0x0924, 2), /* MX6Q_PAD_SD3_CMD__UART2_CTS */
1637 IMX_PIN_REG(MX6Q_PAD_SD3_CMD, 0x06A0, 0x02B8, 2, 0x0000, 0), /* MX6Q_PAD_SD3_CMD__CAN1_TXCAN */
1638 IMX_PIN_REG(MX6Q_PAD_SD3_CMD, 0x06A0, 0x02B8, 3, 0x0000, 0), /* MX6Q_PAD_SD3_CMD__USBOH3_UH3_DFD_OUT_4 */
1639 IMX_PIN_REG(MX6Q_PAD_SD3_CMD, 0x06A0, 0x02B8, 4, 0x0000, 0), /* MX6Q_PAD_SD3_CMD__USBOH3_UH2_DFD_OUT_4 */
1640 IMX_PIN_REG(MX6Q_PAD_SD3_CMD, 0x06A0, 0x02B8, 5, 0x0000, 0), /* MX6Q_PAD_SD3_CMD__GPIO_7_2 */
1641 IMX_PIN_REG(MX6Q_PAD_SD3_CMD, 0x06A0, 0x02B8, 6, 0x0000, 0), /* MX6Q_PAD_SD3_CMD__MIPI_CORE_DPHY_IN_16 */
1642 IMX_PIN_REG(MX6Q_PAD_SD3_CMD, 0x06A0, 0x02B8, 7, 0x0000, 0), /* MX6Q_PAD_SD3_CMD__ANATOP_TESTO_13 */
1643 IMX_PIN_REG(MX6Q_PAD_SD3_CLK, 0x06A4, 0x02BC, 0, 0x0000, 0), /* MX6Q_PAD_SD3_CLK__USDHC3_CLK */
1644 IMX_PIN_REG(MX6Q_PAD_SD3_CLK, 0x06A4, 0x02BC, 1, 0x0924, 3), /* MX6Q_PAD_SD3_CLK__UART2_RTS */
1645 IMX_PIN_REG(MX6Q_PAD_SD3_CLK, 0x06A4, 0x02BC, 2, 0x07E4, 2), /* MX6Q_PAD_SD3_CLK__CAN1_RXCAN */
1646 IMX_PIN_REG(MX6Q_PAD_SD3_CLK, 0x06A4, 0x02BC, 3, 0x0000, 0), /* MX6Q_PAD_SD3_CLK__USBOH3_UH3_DFD_OUT_5 */
1647 IMX_PIN_REG(MX6Q_PAD_SD3_CLK, 0x06A4, 0x02BC, 4, 0x0000, 0), /* MX6Q_PAD_SD3_CLK__USBOH3_UH2_DFD_OUT_5 */
1648 IMX_PIN_REG(MX6Q_PAD_SD3_CLK, 0x06A4, 0x02BC, 5, 0x0000, 0), /* MX6Q_PAD_SD3_CLK__GPIO_7_3 */
1649 IMX_PIN_REG(MX6Q_PAD_SD3_CLK, 0x06A4, 0x02BC, 6, 0x0000, 0), /* MX6Q_PAD_SD3_CLK__MIPI_CORE_DPHY_IN_17 */
1650 IMX_PIN_REG(MX6Q_PAD_SD3_CLK, 0x06A4, 0x02BC, 7, 0x0000, 0), /* MX6Q_PAD_SD3_CLK__ANATOP_TESTO_14 */
1651 IMX_PIN_REG(MX6Q_PAD_SD3_DAT0, 0x06A8, 0x02C0, 0, 0x0000, 0), /* MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 */
1652 IMX_PIN_REG(MX6Q_PAD_SD3_DAT0, 0x06A8, 0x02C0, 1, 0x091C, 2), /* MX6Q_PAD_SD3_DAT0__UART1_CTS */
1653 IMX_PIN_REG(MX6Q_PAD_SD3_DAT0, 0x06A8, 0x02C0, 2, 0x0000, 0), /* MX6Q_PAD_SD3_DAT0__CAN2_TXCAN */
1654 IMX_PIN_REG(MX6Q_PAD_SD3_DAT0, 0x06A8, 0x02C0, 3, 0x0000, 0), /* MX6Q_PAD_SD3_DAT0__USBOH3_UH3_DFD_OUT_6 */
1655 IMX_PIN_REG(MX6Q_PAD_SD3_DAT0, 0x06A8, 0x02C0, 4, 0x0000, 0), /* MX6Q_PAD_SD3_DAT0__USBOH3_UH2_DFD_OUT_6 */
1656 IMX_PIN_REG(MX6Q_PAD_SD3_DAT0, 0x06A8, 0x02C0, 5, 0x0000, 0), /* MX6Q_PAD_SD3_DAT0__GPIO_7_4 */
1657 IMX_PIN_REG(MX6Q_PAD_SD3_DAT0, 0x06A8, 0x02C0, 6, 0x0000, 0), /* MX6Q_PAD_SD3_DAT0__MIPI_CORE_DPHY_IN_18 */
1658 IMX_PIN_REG(MX6Q_PAD_SD3_DAT0, 0x06A8, 0x02C0, 7, 0x0000, 0), /* MX6Q_PAD_SD3_DAT0__ANATOP_TESTO_15 */
1659 IMX_PIN_REG(MX6Q_PAD_SD3_DAT1, 0x06AC, 0x02C4, 0, 0x0000, 0), /* MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 */
1660 IMX_PIN_REG(MX6Q_PAD_SD3_DAT1, 0x06AC, 0x02C4, 1, 0x091C, 3), /* MX6Q_PAD_SD3_DAT1__UART1_RTS */
1661 IMX_PIN_REG(MX6Q_PAD_SD3_DAT1, 0x06AC, 0x02C4, 2, 0x07E8, 1), /* MX6Q_PAD_SD3_DAT1__CAN2_RXCAN */
1662 IMX_PIN_REG(MX6Q_PAD_SD3_DAT1, 0x06AC, 0x02C4, 3, 0x0000, 0), /* MX6Q_PAD_SD3_DAT1__USBOH3_UH3_DFD_OUT_7 */
1663 IMX_PIN_REG(MX6Q_PAD_SD3_DAT1, 0x06AC, 0x02C4, 4, 0x0000, 0), /* MX6Q_PAD_SD3_DAT1__USBOH3_UH2_DFD_OUT_7 */
1664 IMX_PIN_REG(MX6Q_PAD_SD3_DAT1, 0x06AC, 0x02C4, 5, 0x0000, 0), /* MX6Q_PAD_SD3_DAT1__GPIO_7_5 */
1665 IMX_PIN_REG(MX6Q_PAD_SD3_DAT1, 0x06AC, 0x02C4, 6, 0x0000, 0), /* MX6Q_PAD_SD3_DAT1__MIPI_CORE_DPHY_IN_19 */
1666 IMX_PIN_REG(MX6Q_PAD_SD3_DAT1, 0x06AC, 0x02C4, 7, 0x0000, 0), /* MX6Q_PAD_SD3_DAT1__ANATOP_TESTI_0 */
1667 IMX_PIN_REG(MX6Q_PAD_SD3_DAT2, 0x06B0, 0x02C8, 0, 0x0000, 0), /* MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 */
1668 IMX_PIN_REG(MX6Q_PAD_SD3_DAT2, 0x06B0, 0x02C8, 2, 0x0000, 0), /* MX6Q_PAD_SD3_DAT2__PCIE_CTRL_MUX_28 */
1669 IMX_PIN_REG(MX6Q_PAD_SD3_DAT2, 0x06B0, 0x02C8, 3, 0x0000, 0), /* MX6Q_PAD_SD3_DAT2__USBOH3_UH3_DFD_OUT_8 */
1670 IMX_PIN_REG(MX6Q_PAD_SD3_DAT2, 0x06B0, 0x02C8, 4, 0x0000, 0), /* MX6Q_PAD_SD3_DAT2__USBOH3_UH2_DFD_OUT_8 */
1671 IMX_PIN_REG(MX6Q_PAD_SD3_DAT2, 0x06B0, 0x02C8, 5, 0x0000, 0), /* MX6Q_PAD_SD3_DAT2__GPIO_7_6 */
1672 IMX_PIN_REG(MX6Q_PAD_SD3_DAT2, 0x06B0, 0x02C8, 6, 0x0000, 0), /* MX6Q_PAD_SD3_DAT2__MIPI_CORE_DPHY_IN_20 */
1673 IMX_PIN_REG(MX6Q_PAD_SD3_DAT2, 0x06B0, 0x02C8, 7, 0x0000, 0), /* MX6Q_PAD_SD3_DAT2__ANATOP_TESTI_1 */
1674 IMX_PIN_REG(MX6Q_PAD_SD3_DAT3, 0x06B4, 0x02CC, 0, 0x0000, 0), /* MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 */
1675 IMX_PIN_REG(MX6Q_PAD_SD3_DAT3, 0x06B4, 0x02CC, 1, 0x092C, 4), /* MX6Q_PAD_SD3_DAT3__UART3_CTS */
1676 IMX_PIN_REG(MX6Q_PAD_SD3_DAT3, 0x06B4, 0x02CC, 2, 0x0000, 0), /* MX6Q_PAD_SD3_DAT3__PCIE_CTRL_MUX_29 */
1677 IMX_PIN_REG(MX6Q_PAD_SD3_DAT3, 0x06B4, 0x02CC, 3, 0x0000, 0), /* MX6Q_PAD_SD3_DAT3__USBOH3_UH3_DFD_OUT_9 */
1678 IMX_PIN_REG(MX6Q_PAD_SD3_DAT3, 0x06B4, 0x02CC, 4, 0x0000, 0), /* MX6Q_PAD_SD3_DAT3__USBOH3_UH2_DFD_OUT_9 */
1679 IMX_PIN_REG(MX6Q_PAD_SD3_DAT3, 0x06B4, 0x02CC, 5, 0x0000, 0), /* MX6Q_PAD_SD3_DAT3__GPIO_7_7 */
1680 IMX_PIN_REG(MX6Q_PAD_SD3_DAT3, 0x06B4, 0x02CC, 6, 0x0000, 0), /* MX6Q_PAD_SD3_DAT3__MIPI_CORE_DPHY_IN_21 */
1681 IMX_PIN_REG(MX6Q_PAD_SD3_DAT3, 0x06B4, 0x02CC, 7, 0x0000, 0), /* MX6Q_PAD_SD3_DAT3__ANATOP_TESTI_2 */
1682 IMX_PIN_REG(MX6Q_PAD_SD3_RST, 0x06B8, 0x02D0, 0, 0x0000, 0), /* MX6Q_PAD_SD3_RST__USDHC3_RST */
1683 IMX_PIN_REG(MX6Q_PAD_SD3_RST, 0x06B8, 0x02D0, 1, 0x092C, 5), /* MX6Q_PAD_SD3_RST__UART3_RTS */
1684 IMX_PIN_REG(MX6Q_PAD_SD3_RST, 0x06B8, 0x02D0, 2, 0x0000, 0), /* MX6Q_PAD_SD3_RST__PCIE_CTRL_MUX_30 */
1685 IMX_PIN_REG(MX6Q_PAD_SD3_RST, 0x06B8, 0x02D0, 3, 0x0000, 0), /* MX6Q_PAD_SD3_RST__USBOH3_UH3_DFD_OUT_10 */
1686 IMX_PIN_REG(MX6Q_PAD_SD3_RST, 0x06B8, 0x02D0, 4, 0x0000, 0), /* MX6Q_PAD_SD3_RST__USBOH3_UH2_DFD_OUT_10 */
1687 IMX_PIN_REG(MX6Q_PAD_SD3_RST, 0x06B8, 0x02D0, 5, 0x0000, 0), /* MX6Q_PAD_SD3_RST__GPIO_7_8 */
1688 IMX_PIN_REG(MX6Q_PAD_SD3_RST, 0x06B8, 0x02D0, 6, 0x0000, 0), /* MX6Q_PAD_SD3_RST__MIPI_CORE_DPHY_IN_22 */
1689 IMX_PIN_REG(MX6Q_PAD_SD3_RST, 0x06B8, 0x02D0, 7, 0x0000, 0), /* MX6Q_PAD_SD3_RST__ANATOP_ANATOP_TESTI_3 */
1690 IMX_PIN_REG(MX6Q_PAD_NANDF_CLE, 0x06BC, 0x02D4, 0, 0x0000, 0), /* MX6Q_PAD_NANDF_CLE__RAWNAND_CLE */
1691 IMX_PIN_REG(MX6Q_PAD_NANDF_CLE, 0x06BC, 0x02D4, 1, 0x0000, 0), /* MX6Q_PAD_NANDF_CLE__IPU2_SISG_4 */
1692 IMX_PIN_REG(MX6Q_PAD_NANDF_CLE, 0x06BC, 0x02D4, 2, 0x0000, 0), /* MX6Q_PAD_NANDF_CLE__PCIE_CTRL_MUX_31 */
1693 IMX_PIN_REG(MX6Q_PAD_NANDF_CLE, 0x06BC, 0x02D4, 3, 0x0000, 0), /* MX6Q_PAD_NANDF_CLE__USBOH3_UH3_DFD_OT11 */
1694 IMX_PIN_REG(MX6Q_PAD_NANDF_CLE, 0x06BC, 0x02D4, 4, 0x0000, 0), /* MX6Q_PAD_NANDF_CLE__USBOH3_UH2_DFD_OT11 */
1695 IMX_PIN_REG(MX6Q_PAD_NANDF_CLE, 0x06BC, 0x02D4, 5, 0x0000, 0), /* MX6Q_PAD_NANDF_CLE__GPIO_6_7 */
1696 IMX_PIN_REG(MX6Q_PAD_NANDF_CLE, 0x06BC, 0x02D4, 6, 0x0000, 0), /* MX6Q_PAD_NANDF_CLE__MIPI_CORE_DPHY_IN23 */
1697 IMX_PIN_REG(MX6Q_PAD_NANDF_CLE, 0x06BC, 0x02D4, 7, 0x0000, 0), /* MX6Q_PAD_NANDF_CLE__TPSMP_HTRANS_0 */
1698 IMX_PIN_REG(MX6Q_PAD_NANDF_ALE, 0x06C0, 0x02D8, 0, 0x0000, 0), /* MX6Q_PAD_NANDF_ALE__RAWNAND_ALE */
1699 IMX_PIN_REG(MX6Q_PAD_NANDF_ALE, 0x06C0, 0x02D8, 1, 0x0000, 0), /* MX6Q_PAD_NANDF_ALE__USDHC4_RST */
1700 IMX_PIN_REG(MX6Q_PAD_NANDF_ALE, 0x06C0, 0x02D8, 2, 0x0000, 0), /* MX6Q_PAD_NANDF_ALE__PCIE_CTRL_MUX_0 */
1701 IMX_PIN_REG(MX6Q_PAD_NANDF_ALE, 0x06C0, 0x02D8, 3, 0x0000, 0), /* MX6Q_PAD_NANDF_ALE__USBOH3_UH3_DFD_OT12 */
1702 IMX_PIN_REG(MX6Q_PAD_NANDF_ALE, 0x06C0, 0x02D8, 4, 0x0000, 0), /* MX6Q_PAD_NANDF_ALE__USBOH3_UH2_DFD_OT12 */
1703 IMX_PIN_REG(MX6Q_PAD_NANDF_ALE, 0x06C0, 0x02D8, 5, 0x0000, 0), /* MX6Q_PAD_NANDF_ALE__GPIO_6_8 */
1704 IMX_PIN_REG(MX6Q_PAD_NANDF_ALE, 0x06C0, 0x02D8, 6, 0x0000, 0), /* MX6Q_PAD_NANDF_ALE__MIPI_CR_DPHY_IN_24 */
1705 IMX_PIN_REG(MX6Q_PAD_NANDF_ALE, 0x06C0, 0x02D8, 7, 0x0000, 0), /* MX6Q_PAD_NANDF_ALE__TPSMP_HTRANS_1 */
1706 IMX_PIN_REG(MX6Q_PAD_NANDF_WP_B, 0x06C4, 0x02DC, 0, 0x0000, 0), /* MX6Q_PAD_NANDF_WP_B__RAWNAND_RESETN */
1707 IMX_PIN_REG(MX6Q_PAD_NANDF_WP_B, 0x06C4, 0x02DC, 1, 0x0000, 0), /* MX6Q_PAD_NANDF_WP_B__IPU2_SISG_5 */
1708 IMX_PIN_REG(MX6Q_PAD_NANDF_WP_B, 0x06C4, 0x02DC, 2, 0x0000, 0), /* MX6Q_PAD_NANDF_WP_B__PCIE_CTRL__MUX_1 */
1709 IMX_PIN_REG(MX6Q_PAD_NANDF_WP_B, 0x06C4, 0x02DC, 3, 0x0000, 0), /* MX6Q_PAD_NANDF_WP_B__USBOH3_UH3_DFDOT13 */
1710 IMX_PIN_REG(MX6Q_PAD_NANDF_WP_B, 0x06C4, 0x02DC, 4, 0x0000, 0), /* MX6Q_PAD_NANDF_WP_B__USBOH3_UH2_DFDOT13 */
1711 IMX_PIN_REG(MX6Q_PAD_NANDF_WP_B, 0x06C4, 0x02DC, 5, 0x0000, 0), /* MX6Q_PAD_NANDF_WP_B__GPIO_6_9 */
1712 IMX_PIN_REG(MX6Q_PAD_NANDF_WP_B, 0x06C4, 0x02DC, 6, 0x0000, 0), /* MX6Q_PAD_NANDF_WP_B__MIPI_CR_DPHY_OUT32 */
1713 IMX_PIN_REG(MX6Q_PAD_NANDF_WP_B, 0x06C4, 0x02DC, 7, 0x0000, 0), /* MX6Q_PAD_NANDF_WP_B__PL301_PER1_HSIZE_0 */
1714 IMX_PIN_REG(MX6Q_PAD_NANDF_RB0, 0x06C8, 0x02E0, 0, 0x0000, 0), /* MX6Q_PAD_NANDF_RB0__RAWNAND_READY0 */
1715 IMX_PIN_REG(MX6Q_PAD_NANDF_RB0, 0x06C8, 0x02E0, 1, 0x0000, 0), /* MX6Q_PAD_NANDF_RB0__IPU2_DI0_PIN1 */
1716 IMX_PIN_REG(MX6Q_PAD_NANDF_RB0, 0x06C8, 0x02E0, 2, 0x0000, 0), /* MX6Q_PAD_NANDF_RB0__PCIE_CTRL_MUX_2 */
1717 IMX_PIN_REG(MX6Q_PAD_NANDF_RB0, 0x06C8, 0x02E0, 3, 0x0000, 0), /* MX6Q_PAD_NANDF_RB0__USBOH3_UH3_DFD_OT14 */
1718 IMX_PIN_REG(MX6Q_PAD_NANDF_RB0, 0x06C8, 0x02E0, 4, 0x0000, 0), /* MX6Q_PAD_NANDF_RB0__USBOH3_UH2_DFD_OT14 */
1719 IMX_PIN_REG(MX6Q_PAD_NANDF_RB0, 0x06C8, 0x02E0, 5, 0x0000, 0), /* MX6Q_PAD_NANDF_RB0__GPIO_6_10 */
1720 IMX_PIN_REG(MX6Q_PAD_NANDF_RB0, 0x06C8, 0x02E0, 6, 0x0000, 0), /* MX6Q_PAD_NANDF_RB0__MIPI_CR_DPHY_OUT_33 */
1721 IMX_PIN_REG(MX6Q_PAD_NANDF_RB0, 0x06C8, 0x02E0, 7, 0x0000, 0), /* MX6Q_PAD_NANDF_RB0__PL301_PER1_HSIZE_1 */
1722 IMX_PIN_REG(MX6Q_PAD_NANDF_CS0, 0x06CC, 0x02E4, 0, 0x0000, 0), /* MX6Q_PAD_NANDF_CS0__RAWNAND_CE0N */
1723 IMX_PIN_REG(MX6Q_PAD_NANDF_CS0, 0x06CC, 0x02E4, 3, 0x0000, 0), /* MX6Q_PAD_NANDF_CS0__USBOH3_UH3_DFD_OT15 */
1724 IMX_PIN_REG(MX6Q_PAD_NANDF_CS0, 0x06CC, 0x02E4, 4, 0x0000, 0), /* MX6Q_PAD_NANDF_CS0__USBOH3_UH2_DFD_OT15 */
1725 IMX_PIN_REG(MX6Q_PAD_NANDF_CS0, 0x06CC, 0x02E4, 5, 0x0000, 0), /* MX6Q_PAD_NANDF_CS0__GPIO_6_11 */
1726 IMX_PIN_REG(MX6Q_PAD_NANDF_CS0, 0x06CC, 0x02E4, 7, 0x0000, 0), /* MX6Q_PAD_NANDF_CS0__PL301_PER1_HSIZE_2 */
1727 IMX_PIN_REG(MX6Q_PAD_NANDF_CS1, 0x06D0, 0x02E8, 0, 0x0000, 0), /* MX6Q_PAD_NANDF_CS1__RAWNAND_CE1N */
1728 IMX_PIN_REG(MX6Q_PAD_NANDF_CS1, 0x06D0, 0x02E8, 1, 0x0000, 0), /* MX6Q_PAD_NANDF_CS1__USDHC4_VSELECT */
1729 IMX_PIN_REG(MX6Q_PAD_NANDF_CS1, 0x06D0, 0x02E8, 2, 0x0000, 0), /* MX6Q_PAD_NANDF_CS1__USDHC3_VSELECT */
1730 IMX_PIN_REG(MX6Q_PAD_NANDF_CS1, 0x06D0, 0x02E8, 4, 0x0000, 0), /* MX6Q_PAD_NANDF_CS1__PCIE_CTRL_MUX_3 */
1731 IMX_PIN_REG(MX6Q_PAD_NANDF_CS1, 0x06D0, 0x02E8, 5, 0x0000, 0), /* MX6Q_PAD_NANDF_CS1__GPIO_6_14 */
1732 IMX_PIN_REG(MX6Q_PAD_NANDF_CS1, 0x06D0, 0x02E8, 7, 0x0000, 0), /* MX6Q_PAD_NANDF_CS1__PL301_PER1_HRDYOUT */
1733 IMX_PIN_REG(MX6Q_PAD_NANDF_CS2, 0x06D4, 0x02EC, 0, 0x0000, 0), /* MX6Q_PAD_NANDF_CS2__RAWNAND_CE2N */
1734 IMX_PIN_REG(MX6Q_PAD_NANDF_CS2, 0x06D4, 0x02EC, 1, 0x0000, 0), /* MX6Q_PAD_NANDF_CS2__IPU1_SISG_0 */
1735 IMX_PIN_REG(MX6Q_PAD_NANDF_CS2, 0x06D4, 0x02EC, 2, 0x0874, 1), /* MX6Q_PAD_NANDF_CS2__ESAI1_TX0 */
1736 IMX_PIN_REG(MX6Q_PAD_NANDF_CS2, 0x06D4, 0x02EC, 3, 0x0000, 0), /* MX6Q_PAD_NANDF_CS2__WEIM_WEIM_CRE */
1737 IMX_PIN_REG(MX6Q_PAD_NANDF_CS2, 0x06D4, 0x02EC, 4, 0x0000, 0), /* MX6Q_PAD_NANDF_CS2__CCM_CLKO2 */
1738 IMX_PIN_REG(MX6Q_PAD_NANDF_CS2, 0x06D4, 0x02EC, 5, 0x0000, 0), /* MX6Q_PAD_NANDF_CS2__GPIO_6_15 */
1739 IMX_PIN_REG(MX6Q_PAD_NANDF_CS2, 0x06D4, 0x02EC, 6, 0x0000, 0), /* MX6Q_PAD_NANDF_CS2__IPU2_SISG_0 */
1740 IMX_PIN_REG(MX6Q_PAD_NANDF_CS3, 0x06D8, 0x02F0, 0, 0x0000, 0), /* MX6Q_PAD_NANDF_CS3__RAWNAND_CE3N */
1741 IMX_PIN_REG(MX6Q_PAD_NANDF_CS3, 0x06D8, 0x02F0, 1, 0x0000, 0), /* MX6Q_PAD_NANDF_CS3__IPU1_SISG_1 */
1742 IMX_PIN_REG(MX6Q_PAD_NANDF_CS3, 0x06D8, 0x02F0, 2, 0x0878, 1), /* MX6Q_PAD_NANDF_CS3__ESAI1_TX1 */
1743 IMX_PIN_REG(MX6Q_PAD_NANDF_CS3, 0x06D8, 0x02F0, 3, 0x0000, 0), /* MX6Q_PAD_NANDF_CS3__WEIM_WEIM_A_26 */
1744 IMX_PIN_REG(MX6Q_PAD_NANDF_CS3, 0x06D8, 0x02F0, 4, 0x0000, 0), /* MX6Q_PAD_NANDF_CS3__PCIE_CTRL_MUX_4 */
1745 IMX_PIN_REG(MX6Q_PAD_NANDF_CS3, 0x06D8, 0x02F0, 5, 0x0000, 0), /* MX6Q_PAD_NANDF_CS3__GPIO_6_16 */
1746 IMX_PIN_REG(MX6Q_PAD_NANDF_CS3, 0x06D8, 0x02F0, 6, 0x0000, 0), /* MX6Q_PAD_NANDF_CS3__IPU2_SISG_1 */
1747 IMX_PIN_REG(MX6Q_PAD_NANDF_CS3, 0x06D8, 0x02F0, 7, 0x0000, 0), /* MX6Q_PAD_NANDF_CS3__TPSMP_CLK */
1748 IMX_PIN_REG(MX6Q_PAD_SD4_CMD, 0x06DC, 0x02F4, 0, 0x0000, 0), /* MX6Q_PAD_SD4_CMD__USDHC4_CMD */
1749 IMX_PIN_REG(MX6Q_PAD_SD4_CMD, 0x06DC, 0x02F4, 1, 0x0000, 0), /* MX6Q_PAD_SD4_CMD__RAWNAND_RDN */
1750 IMX_PIN_REG(MX6Q_PAD_SD4_CMD, 0x06DC, 0x02F4, 2, 0x0000, 0), /* MX6Q_PAD_SD4_CMD__UART3_TXD */
1751 IMX_PIN_REG(MX6Q_PAD_SD4_CMD, 0x06DC, 0x02F4, 4, 0x0000, 0), /* MX6Q_PAD_SD4_CMD__PCIE_CTRL_MUX_5 */
1752 IMX_PIN_REG(MX6Q_PAD_SD4_CMD, 0x06DC, 0x02F4, 5, 0x0000, 0), /* MX6Q_PAD_SD4_CMD__GPIO_7_9 */
1753 IMX_PIN_REG(MX6Q_PAD_SD4_CMD, 0x06DC, 0x02F4, 7, 0x0000, 0), /* MX6Q_PAD_SD4_CMD__TPSMP_HDATA_DIR */
1754 IMX_PIN_REG(MX6Q_PAD_SD4_CLK, 0x06E0, 0x02F8, 0, 0x0000, 0), /* MX6Q_PAD_SD4_CLK__USDHC4_CLK */
1755 IMX_PIN_REG(MX6Q_PAD_SD4_CLK, 0x06E0, 0x02F8, 1, 0x0000, 0), /* MX6Q_PAD_SD4_CLK__RAWNAND_WRN */
1756 IMX_PIN_REG(MX6Q_PAD_SD4_CLK, 0x06E0, 0x02F8, 2, 0x0930, 3), /* MX6Q_PAD_SD4_CLK__UART3_RXD */
1757 IMX_PIN_REG(MX6Q_PAD_SD4_CLK, 0x06E0, 0x02F8, 4, 0x0000, 0), /* MX6Q_PAD_SD4_CLK__PCIE_CTRL_MUX_6 */
1758 IMX_PIN_REG(MX6Q_PAD_SD4_CLK, 0x06E0, 0x02F8, 5, 0x0000, 0), /* MX6Q_PAD_SD4_CLK__GPIO_7_10 */
1759 IMX_PIN_REG(MX6Q_PAD_NANDF_D0, 0x06E4, 0x02FC, 0, 0x0000, 0), /* MX6Q_PAD_NANDF_D0__RAWNAND_D0 */
1760 IMX_PIN_REG(MX6Q_PAD_NANDF_D0, 0x06E4, 0x02FC, 1, 0x0000, 0), /* MX6Q_PAD_NANDF_D0__USDHC1_DAT4 */
1761 IMX_PIN_REG(MX6Q_PAD_NANDF_D0, 0x06E4, 0x02FC, 2, 0x0000, 0), /* MX6Q_PAD_NANDF_D0__GPU3D_GPU_DBG_OUT_0 */
1762 IMX_PIN_REG(MX6Q_PAD_NANDF_D0, 0x06E4, 0x02FC, 3, 0x0000, 0), /* MX6Q_PAD_NANDF_D0__USBOH3_UH2_DFD_OUT16 */
1763 IMX_PIN_REG(MX6Q_PAD_NANDF_D0, 0x06E4, 0x02FC, 4, 0x0000, 0), /* MX6Q_PAD_NANDF_D0__USBOH3_UH3_DFD_OUT16 */
1764 IMX_PIN_REG(MX6Q_PAD_NANDF_D0, 0x06E4, 0x02FC, 5, 0x0000, 0), /* MX6Q_PAD_NANDF_D0__GPIO_2_0 */
1765 IMX_PIN_REG(MX6Q_PAD_NANDF_D0, 0x06E4, 0x02FC, 6, 0x0000, 0), /* MX6Q_PAD_NANDF_D0__IPU1_IPU_DIAG_BUS_0 */
1766 IMX_PIN_REG(MX6Q_PAD_NANDF_D0, 0x06E4, 0x02FC, 7, 0x0000, 0), /* MX6Q_PAD_NANDF_D0__IPU2_IPU_DIAG_BUS_0 */
1767 IMX_PIN_REG(MX6Q_PAD_NANDF_D1, 0x06E8, 0x0300, 0, 0x0000, 0), /* MX6Q_PAD_NANDF_D1__RAWNAND_D1 */
1768 IMX_PIN_REG(MX6Q_PAD_NANDF_D1, 0x06E8, 0x0300, 1, 0x0000, 0), /* MX6Q_PAD_NANDF_D1__USDHC1_DAT5 */
1769 IMX_PIN_REG(MX6Q_PAD_NANDF_D1, 0x06E8, 0x0300, 2, 0x0000, 0), /* MX6Q_PAD_NANDF_D1__GPU3D_GPU_DEBUG_OUT1 */
1770 IMX_PIN_REG(MX6Q_PAD_NANDF_D1, 0x06E8, 0x0300, 3, 0x0000, 0), /* MX6Q_PAD_NANDF_D1__USBOH3_UH2_DFD_OUT17 */
1771 IMX_PIN_REG(MX6Q_PAD_NANDF_D1, 0x06E8, 0x0300, 4, 0x0000, 0), /* MX6Q_PAD_NANDF_D1__USBOH3_UH3_DFD_OUT17 */
1772 IMX_PIN_REG(MX6Q_PAD_NANDF_D1, 0x06E8, 0x0300, 5, 0x0000, 0), /* MX6Q_PAD_NANDF_D1__GPIO_2_1 */
1773 IMX_PIN_REG(MX6Q_PAD_NANDF_D1, 0x06E8, 0x0300, 6, 0x0000, 0), /* MX6Q_PAD_NANDF_D1__IPU1_IPU_DIAG_BUS_1 */
1774 IMX_PIN_REG(MX6Q_PAD_NANDF_D1, 0x06E8, 0x0300, 7, 0x0000, 0), /* MX6Q_PAD_NANDF_D1__IPU2_IPU_DIAG_BUS_1 */
1775 IMX_PIN_REG(MX6Q_PAD_NANDF_D2, 0x06EC, 0x0304, 0, 0x0000, 0), /* MX6Q_PAD_NANDF_D2__RAWNAND_D2 */
1776 IMX_PIN_REG(MX6Q_PAD_NANDF_D2, 0x06EC, 0x0304, 1, 0x0000, 0), /* MX6Q_PAD_NANDF_D2__USDHC1_DAT6 */
1777 IMX_PIN_REG(MX6Q_PAD_NANDF_D2, 0x06EC, 0x0304, 2, 0x0000, 0), /* MX6Q_PAD_NANDF_D2__GPU3D_GPU_DBG_OUT_2 */
1778 IMX_PIN_REG(MX6Q_PAD_NANDF_D2, 0x06EC, 0x0304, 3, 0x0000, 0), /* MX6Q_PAD_NANDF_D2__USBOH3_UH2_DFD_OUT18 */
1779 IMX_PIN_REG(MX6Q_PAD_NANDF_D2, 0x06EC, 0x0304, 4, 0x0000, 0), /* MX6Q_PAD_NANDF_D2__USBOH3_UH3_DFD_OUT18 */
1780 IMX_PIN_REG(MX6Q_PAD_NANDF_D2, 0x06EC, 0x0304, 5, 0x0000, 0), /* MX6Q_PAD_NANDF_D2__GPIO_2_2 */
1781 IMX_PIN_REG(MX6Q_PAD_NANDF_D2, 0x06EC, 0x0304, 6, 0x0000, 0), /* MX6Q_PAD_NANDF_D2__IPU1_IPU_DIAG_BUS_2 */
1782 IMX_PIN_REG(MX6Q_PAD_NANDF_D2, 0x06EC, 0x0304, 7, 0x0000, 0), /* MX6Q_PAD_NANDF_D2__IPU2_IPU_DIAG_BUS_2 */
1783 IMX_PIN_REG(MX6Q_PAD_NANDF_D3, 0x06F0, 0x0308, 0, 0x0000, 0), /* MX6Q_PAD_NANDF_D3__RAWNAND_D3 */
1784 IMX_PIN_REG(MX6Q_PAD_NANDF_D3, 0x06F0, 0x0308, 1, 0x0000, 0), /* MX6Q_PAD_NANDF_D3__USDHC1_DAT7 */
1785 IMX_PIN_REG(MX6Q_PAD_NANDF_D3, 0x06F0, 0x0308, 2, 0x0000, 0), /* MX6Q_PAD_NANDF_D3__GPU3D_GPU_DBG_OUT_3 */
1786 IMX_PIN_REG(MX6Q_PAD_NANDF_D3, 0x06F0, 0x0308, 3, 0x0000, 0), /* MX6Q_PAD_NANDF_D3__USBOH3_UH2_DFD_OUT19 */
1787 IMX_PIN_REG(MX6Q_PAD_NANDF_D3, 0x06F0, 0x0308, 4, 0x0000, 0), /* MX6Q_PAD_NANDF_D3__USBOH3_UH3_DFD_OUT19 */
1788 IMX_PIN_REG(MX6Q_PAD_NANDF_D3, 0x06F0, 0x0308, 5, 0x0000, 0), /* MX6Q_PAD_NANDF_D3__GPIO_2_3 */
1789 IMX_PIN_REG(MX6Q_PAD_NANDF_D3, 0x06F0, 0x0308, 6, 0x0000, 0), /* MX6Q_PAD_NANDF_D3__IPU1_IPU_DIAG_BUS_3 */
1790 IMX_PIN_REG(MX6Q_PAD_NANDF_D3, 0x06F0, 0x0308, 7, 0x0000, 0), /* MX6Q_PAD_NANDF_D3__IPU2_IPU_DIAG_BUS_3 */
1791 IMX_PIN_REG(MX6Q_PAD_NANDF_D4, 0x06F4, 0x030C, 0, 0x0000, 0), /* MX6Q_PAD_NANDF_D4__RAWNAND_D4 */
1792 IMX_PIN_REG(MX6Q_PAD_NANDF_D4, 0x06F4, 0x030C, 1, 0x0000, 0), /* MX6Q_PAD_NANDF_D4__USDHC2_DAT4 */
1793 IMX_PIN_REG(MX6Q_PAD_NANDF_D4, 0x06F4, 0x030C, 2, 0x0000, 0), /* MX6Q_PAD_NANDF_D4__GPU3D_GPU_DBG_OUT_4 */
1794 IMX_PIN_REG(MX6Q_PAD_NANDF_D4, 0x06F4, 0x030C, 3, 0x0000, 0), /* MX6Q_PAD_NANDF_D4__USBOH3_UH2_DFD_OUT20 */
1795 IMX_PIN_REG(MX6Q_PAD_NANDF_D4, 0x06F4, 0x030C, 4, 0x0000, 0), /* MX6Q_PAD_NANDF_D4__USBOH3_UH3_DFD_OUT20 */
1796 IMX_PIN_REG(MX6Q_PAD_NANDF_D4, 0x06F4, 0x030C, 5, 0x0000, 0), /* MX6Q_PAD_NANDF_D4__GPIO_2_4 */
1797 IMX_PIN_REG(MX6Q_PAD_NANDF_D4, 0x06F4, 0x030C, 6, 0x0000, 0), /* MX6Q_PAD_NANDF_D4__IPU1_IPU_DIAG_BUS_4 */
1798 IMX_PIN_REG(MX6Q_PAD_NANDF_D4, 0x06F4, 0x030C, 7, 0x0000, 0), /* MX6Q_PAD_NANDF_D4__IPU2_IPU_DIAG_BUS_4 */
1799 IMX_PIN_REG(MX6Q_PAD_NANDF_D5, 0x06F8, 0x0310, 0, 0x0000, 0), /* MX6Q_PAD_NANDF_D5__RAWNAND_D5 */
1800 IMX_PIN_REG(MX6Q_PAD_NANDF_D5, 0x06F8, 0x0310, 1, 0x0000, 0), /* MX6Q_PAD_NANDF_D5__USDHC2_DAT5 */
1801 IMX_PIN_REG(MX6Q_PAD_NANDF_D5, 0x06F8, 0x0310, 2, 0x0000, 0), /* MX6Q_PAD_NANDF_D5__GPU3D_GPU_DBG_OUT_5 */
1802 IMX_PIN_REG(MX6Q_PAD_NANDF_D5, 0x06F8, 0x0310, 3, 0x0000, 0), /* MX6Q_PAD_NANDF_D5__USBOH3_UH2_DFD_OUT21 */
1803 IMX_PIN_REG(MX6Q_PAD_NANDF_D5, 0x06F8, 0x0310, 4, 0x0000, 0), /* MX6Q_PAD_NANDF_D5__USBOH3_UH3_DFD_OUT21 */
1804 IMX_PIN_REG(MX6Q_PAD_NANDF_D5, 0x06F8, 0x0310, 5, 0x0000, 0), /* MX6Q_PAD_NANDF_D5__GPIO_2_5 */
1805 IMX_PIN_REG(MX6Q_PAD_NANDF_D5, 0x06F8, 0x0310, 6, 0x0000, 0), /* MX6Q_PAD_NANDF_D5__IPU1_IPU_DIAG_BUS_5 */
1806 IMX_PIN_REG(MX6Q_PAD_NANDF_D5, 0x06F8, 0x0310, 7, 0x0000, 0), /* MX6Q_PAD_NANDF_D5__IPU2_IPU_DIAG_BUS_5 */
1807 IMX_PIN_REG(MX6Q_PAD_NANDF_D6, 0x06FC, 0x0314, 0, 0x0000, 0), /* MX6Q_PAD_NANDF_D6__RAWNAND_D6 */
1808 IMX_PIN_REG(MX6Q_PAD_NANDF_D6, 0x06FC, 0x0314, 1, 0x0000, 0), /* MX6Q_PAD_NANDF_D6__USDHC2_DAT6 */
1809 IMX_PIN_REG(MX6Q_PAD_NANDF_D6, 0x06FC, 0x0314, 2, 0x0000, 0), /* MX6Q_PAD_NANDF_D6__GPU3D_GPU_DBG_OUT_6 */
1810 IMX_PIN_REG(MX6Q_PAD_NANDF_D6, 0x06FC, 0x0314, 3, 0x0000, 0), /* MX6Q_PAD_NANDF_D6__USBOH3_UH2_DFD_OUT22 */
1811 IMX_PIN_REG(MX6Q_PAD_NANDF_D6, 0x06FC, 0x0314, 4, 0x0000, 0), /* MX6Q_PAD_NANDF_D6__USBOH3_UH3_DFD_OUT22 */
1812 IMX_PIN_REG(MX6Q_PAD_NANDF_D6, 0x06FC, 0x0314, 5, 0x0000, 0), /* MX6Q_PAD_NANDF_D6__GPIO_2_6 */
1813 IMX_PIN_REG(MX6Q_PAD_NANDF_D6, 0x06FC, 0x0314, 6, 0x0000, 0), /* MX6Q_PAD_NANDF_D6__IPU1_IPU_DIAG_BUS_6 */
1814 IMX_PIN_REG(MX6Q_PAD_NANDF_D6, 0x06FC, 0x0314, 7, 0x0000, 0), /* MX6Q_PAD_NANDF_D6__IPU2_IPU_DIAG_BUS_6 */
1815 IMX_PIN_REG(MX6Q_PAD_NANDF_D7, 0x0700, 0x0318, 0, 0x0000, 0), /* MX6Q_PAD_NANDF_D7__RAWNAND_D7 */
1816 IMX_PIN_REG(MX6Q_PAD_NANDF_D7, 0x0700, 0x0318, 1, 0x0000, 0), /* MX6Q_PAD_NANDF_D7__USDHC2_DAT7 */
1817 IMX_PIN_REG(MX6Q_PAD_NANDF_D7, 0x0700, 0x0318, 2, 0x0000, 0), /* MX6Q_PAD_NANDF_D7__GPU3D_GPU_DBG_OUT_7 */
1818 IMX_PIN_REG(MX6Q_PAD_NANDF_D7, 0x0700, 0x0318, 3, 0x0000, 0), /* MX6Q_PAD_NANDF_D7__USBOH3_UH2_DFD_OUT23 */
1819 IMX_PIN_REG(MX6Q_PAD_NANDF_D7, 0x0700, 0x0318, 4, 0x0000, 0), /* MX6Q_PAD_NANDF_D7__USBOH3_UH3_DFD_OUT23 */
1820 IMX_PIN_REG(MX6Q_PAD_NANDF_D7, 0x0700, 0x0318, 5, 0x0000, 0), /* MX6Q_PAD_NANDF_D7__GPIO_2_7 */
1821 IMX_PIN_REG(MX6Q_PAD_NANDF_D7, 0x0700, 0x0318, 6, 0x0000, 0), /* MX6Q_PAD_NANDF_D7__IPU1_IPU_DIAG_BUS_7 */
1822 IMX_PIN_REG(MX6Q_PAD_NANDF_D7, 0x0700, 0x0318, 7, 0x0000, 0), /* MX6Q_PAD_NANDF_D7__IPU2_IPU_DIAG_BUS_7 */
1823 IMX_PIN_REG(MX6Q_PAD_SD4_DAT0, 0x0704, 0x031C, 0, 0x0000, 0), /* MX6Q_PAD_SD4_DAT0__RAWNAND_D8 */
1824 IMX_PIN_REG(MX6Q_PAD_SD4_DAT0, 0x0704, 0x031C, 1, 0x0000, 0), /* MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 */
1825 IMX_PIN_REG(MX6Q_PAD_SD4_DAT0, 0x0704, 0x031C, 2, 0x0000, 0), /* MX6Q_PAD_SD4_DAT0__RAWNAND_DQS */
1826 IMX_PIN_REG(MX6Q_PAD_SD4_DAT0, 0x0704, 0x031C, 3, 0x0000, 0), /* MX6Q_PAD_SD4_DAT0__USBOH3_UH2_DFD_OUT24 */
1827 IMX_PIN_REG(MX6Q_PAD_SD4_DAT0, 0x0704, 0x031C, 4, 0x0000, 0), /* MX6Q_PAD_SD4_DAT0__USBOH3_UH3_DFD_OUT24 */
1828 IMX_PIN_REG(MX6Q_PAD_SD4_DAT0, 0x0704, 0x031C, 5, 0x0000, 0), /* MX6Q_PAD_SD4_DAT0__GPIO_2_8 */
1829 IMX_PIN_REG(MX6Q_PAD_SD4_DAT0, 0x0704, 0x031C, 6, 0x0000, 0), /* MX6Q_PAD_SD4_DAT0__IPU1_IPU_DIAG_BUS_8 */
1830 IMX_PIN_REG(MX6Q_PAD_SD4_DAT0, 0x0704, 0x031C, 7, 0x0000, 0), /* MX6Q_PAD_SD4_DAT0__IPU2_IPU_DIAG_BUS_8 */
1831 IMX_PIN_REG(MX6Q_PAD_SD4_DAT1, 0x0708, 0x0320, 0, 0x0000, 0), /* MX6Q_PAD_SD4_DAT1__RAWNAND_D9 */
1832 IMX_PIN_REG(MX6Q_PAD_SD4_DAT1, 0x0708, 0x0320, 1, 0x0000, 0), /* MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 */
1833 IMX_PIN_REG(MX6Q_PAD_SD4_DAT1, 0x0708, 0x0320, 2, 0x0000, 0), /* MX6Q_PAD_SD4_DAT1__PWM3_PWMO */
1834 IMX_PIN_REG(MX6Q_PAD_SD4_DAT1, 0x0708, 0x0320, 3, 0x0000, 0), /* MX6Q_PAD_SD4_DAT1__USBOH3_UH2_DFD_OUT25 */
1835 IMX_PIN_REG(MX6Q_PAD_SD4_DAT1, 0x0708, 0x0320, 4, 0x0000, 0), /* MX6Q_PAD_SD4_DAT1__USBOH3_UH3_DFD_OUT25 */
1836 IMX_PIN_REG(MX6Q_PAD_SD4_DAT1, 0x0708, 0x0320, 5, 0x0000, 0), /* MX6Q_PAD_SD4_DAT1__GPIO_2_9 */
1837 IMX_PIN_REG(MX6Q_PAD_SD4_DAT1, 0x0708, 0x0320, 6, 0x0000, 0), /* MX6Q_PAD_SD4_DAT1__IPU1_IPU_DIAG_BUS_9 */
1838 IMX_PIN_REG(MX6Q_PAD_SD4_DAT1, 0x0708, 0x0320, 7, 0x0000, 0), /* MX6Q_PAD_SD4_DAT1__IPU2_IPU_DIAG_BUS_9 */
1839 IMX_PIN_REG(MX6Q_PAD_SD4_DAT2, 0x070C, 0x0324, 0, 0x0000, 0), /* MX6Q_PAD_SD4_DAT2__RAWNAND_D10 */
1840 IMX_PIN_REG(MX6Q_PAD_SD4_DAT2, 0x070C, 0x0324, 1, 0x0000, 0), /* MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 */
1841 IMX_PIN_REG(MX6Q_PAD_SD4_DAT2, 0x070C, 0x0324, 2, 0x0000, 0), /* MX6Q_PAD_SD4_DAT2__PWM4_PWMO */
1842 IMX_PIN_REG(MX6Q_PAD_SD4_DAT2, 0x070C, 0x0324, 3, 0x0000, 0), /* MX6Q_PAD_SD4_DAT2__USBOH3_UH2_DFD_OUT26 */
1843 IMX_PIN_REG(MX6Q_PAD_SD4_DAT2, 0x070C, 0x0324, 4, 0x0000, 0), /* MX6Q_PAD_SD4_DAT2__USBOH3_UH3_DFD_OUT26 */
1844 IMX_PIN_REG(MX6Q_PAD_SD4_DAT2, 0x070C, 0x0324, 5, 0x0000, 0), /* MX6Q_PAD_SD4_DAT2__GPIO_2_10 */
1845 IMX_PIN_REG(MX6Q_PAD_SD4_DAT2, 0x070C, 0x0324, 6, 0x0000, 0), /* MX6Q_PAD_SD4_DAT2__IPU1_IPU_DIAG_BUS_10 */
1846 IMX_PIN_REG(MX6Q_PAD_SD4_DAT2, 0x070C, 0x0324, 7, 0x0000, 0), /* MX6Q_PAD_SD4_DAT2__IPU2_IPU_DIAG_BUS_10 */
1847 IMX_PIN_REG(MX6Q_PAD_SD4_DAT3, 0x0710, 0x0328, 0, 0x0000, 0), /* MX6Q_PAD_SD4_DAT3__RAWNAND_D11 */
1848 IMX_PIN_REG(MX6Q_PAD_SD4_DAT3, 0x0710, 0x0328, 1, 0x0000, 0), /* MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 */
1849 IMX_PIN_REG(MX6Q_PAD_SD4_DAT3, 0x0710, 0x0328, 3, 0x0000, 0), /* MX6Q_PAD_SD4_DAT3__USBOH3_UH2_DFD_OUT27 */
1850 IMX_PIN_REG(MX6Q_PAD_SD4_DAT3, 0x0710, 0x0328, 4, 0x0000, 0), /* MX6Q_PAD_SD4_DAT3__USBOH3_UH3_DFD_OUT27 */
1851 IMX_PIN_REG(MX6Q_PAD_SD4_DAT3, 0x0710, 0x0328, 5, 0x0000, 0), /* MX6Q_PAD_SD4_DAT3__GPIO_2_11 */
1852 IMX_PIN_REG(MX6Q_PAD_SD4_DAT3, 0x0710, 0x0328, 6, 0x0000, 0), /* MX6Q_PAD_SD4_DAT3__IPU1_IPU_DIAG_BUS_11 */
1853 IMX_PIN_REG(MX6Q_PAD_SD4_DAT3, 0x0710, 0x0328, 7, 0x0000, 0), /* MX6Q_PAD_SD4_DAT3__IPU2_IPU_DIAG_BUS_11 */
1854 IMX_PIN_REG(MX6Q_PAD_SD4_DAT4, 0x0714, 0x032C, 0, 0x0000, 0), /* MX6Q_PAD_SD4_DAT4__RAWNAND_D12 */
1855 IMX_PIN_REG(MX6Q_PAD_SD4_DAT4, 0x0714, 0x032C, 1, 0x0000, 0), /* MX6Q_PAD_SD4_DAT4__USDHC4_DAT4 */
1856 IMX_PIN_REG(MX6Q_PAD_SD4_DAT4, 0x0714, 0x032C, 2, 0x0928, 6), /* MX6Q_PAD_SD4_DAT4__UART2_RXD */
1857 IMX_PIN_REG(MX6Q_PAD_SD4_DAT4, 0x0714, 0x032C, 3, 0x0000, 0), /* MX6Q_PAD_SD4_DAT4__USBOH3_UH2_DFD_OUT28 */
1858 IMX_PIN_REG(MX6Q_PAD_SD4_DAT4, 0x0714, 0x032C, 4, 0x0000, 0), /* MX6Q_PAD_SD4_DAT4__USBOH3_UH3_DFD_OUT28 */
1859 IMX_PIN_REG(MX6Q_PAD_SD4_DAT4, 0x0714, 0x032C, 5, 0x0000, 0), /* MX6Q_PAD_SD4_DAT4__GPIO_2_12 */
1860 IMX_PIN_REG(MX6Q_PAD_SD4_DAT4, 0x0714, 0x032C, 6, 0x0000, 0), /* MX6Q_PAD_SD4_DAT4__IPU1_IPU_DIAG_BUS_12 */
1861 IMX_PIN_REG(MX6Q_PAD_SD4_DAT4, 0x0714, 0x032C, 7, 0x0000, 0), /* MX6Q_PAD_SD4_DAT4__IPU2_IPU_DIAG_BUS_12 */
1862 IMX_PIN_REG(MX6Q_PAD_SD4_DAT5, 0x0718, 0x0330, 0, 0x0000, 0), /* MX6Q_PAD_SD4_DAT5__RAWNAND_D13 */
1863 IMX_PIN_REG(MX6Q_PAD_SD4_DAT5, 0x0718, 0x0330, 1, 0x0000, 0), /* MX6Q_PAD_SD4_DAT5__USDHC4_DAT5 */
1864 IMX_PIN_REG(MX6Q_PAD_SD4_DAT5, 0x0718, 0x0330, 2, 0x0924, 4), /* MX6Q_PAD_SD4_DAT5__UART2_RTS */
1865 IMX_PIN_REG(MX6Q_PAD_SD4_DAT5, 0x0718, 0x0330, 3, 0x0000, 0), /* MX6Q_PAD_SD4_DAT5__USBOH3_UH2_DFD_OUT29 */
1866 IMX_PIN_REG(MX6Q_PAD_SD4_DAT5, 0x0718, 0x0330, 4, 0x0000, 0), /* MX6Q_PAD_SD4_DAT5__USBOH3_UH3_DFD_OUT29 */
1867 IMX_PIN_REG(MX6Q_PAD_SD4_DAT5, 0x0718, 0x0330, 5, 0x0000, 0), /* MX6Q_PAD_SD4_DAT5__GPIO_2_13 */
1868 IMX_PIN_REG(MX6Q_PAD_SD4_DAT5, 0x0718, 0x0330, 6, 0x0000, 0), /* MX6Q_PAD_SD4_DAT5__IPU1_IPU_DIAG_BUS_13 */
1869 IMX_PIN_REG(MX6Q_PAD_SD4_DAT5, 0x0718, 0x0330, 7, 0x0000, 0), /* MX6Q_PAD_SD4_DAT5__IPU2_IPU_DIAG_BUS_13 */
1870 IMX_PIN_REG(MX6Q_PAD_SD4_DAT6, 0x071C, 0x0334, 0, 0x0000, 0), /* MX6Q_PAD_SD4_DAT6__RAWNAND_D14 */
1871 IMX_PIN_REG(MX6Q_PAD_SD4_DAT6, 0x071C, 0x0334, 1, 0x0000, 0), /* MX6Q_PAD_SD4_DAT6__USDHC4_DAT6 */
1872 IMX_PIN_REG(MX6Q_PAD_SD4_DAT6, 0x071C, 0x0334, 2, 0x0924, 5), /* MX6Q_PAD_SD4_DAT6__UART2_CTS */
1873 IMX_PIN_REG(MX6Q_PAD_SD4_DAT6, 0x071C, 0x0334, 3, 0x0000, 0), /* MX6Q_PAD_SD4_DAT6__USBOH3_UH2_DFD_OUT30 */
1874 IMX_PIN_REG(MX6Q_PAD_SD4_DAT6, 0x071C, 0x0334, 4, 0x0000, 0), /* MX6Q_PAD_SD4_DAT6__USBOH3_UH3_DFD_OUT30 */
1875 IMX_PIN_REG(MX6Q_PAD_SD4_DAT6, 0x071C, 0x0334, 5, 0x0000, 0), /* MX6Q_PAD_SD4_DAT6__GPIO_2_14 */
1876 IMX_PIN_REG(MX6Q_PAD_SD4_DAT6, 0x071C, 0x0334, 6, 0x0000, 0), /* MX6Q_PAD_SD4_DAT6__IPU1_IPU_DIAG_BUS_14 */
1877 IMX_PIN_REG(MX6Q_PAD_SD4_DAT6, 0x071C, 0x0334, 7, 0x0000, 0), /* MX6Q_PAD_SD4_DAT6__IPU2_IPU_DIAG_BUS_14 */
1878 IMX_PIN_REG(MX6Q_PAD_SD4_DAT7, 0x0720, 0x0338, 0, 0x0000, 0), /* MX6Q_PAD_SD4_DAT7__RAWNAND_D15 */
1879 IMX_PIN_REG(MX6Q_PAD_SD4_DAT7, 0x0720, 0x0338, 1, 0x0000, 0), /* MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 */
1880 IMX_PIN_REG(MX6Q_PAD_SD4_DAT7, 0x0720, 0x0338, 2, 0x0000, 0), /* MX6Q_PAD_SD4_DAT7__UART2_TXD */
1881 IMX_PIN_REG(MX6Q_PAD_SD4_DAT7, 0x0720, 0x0338, 3, 0x0000, 0), /* MX6Q_PAD_SD4_DAT7__USBOH3_UH2_DFD_OUT31 */
1882 IMX_PIN_REG(MX6Q_PAD_SD4_DAT7, 0x0720, 0x0338, 4, 0x0000, 0), /* MX6Q_PAD_SD4_DAT7__USBOH3_UH3_DFD_OUT31 */
1883 IMX_PIN_REG(MX6Q_PAD_SD4_DAT7, 0x0720, 0x0338, 5, 0x0000, 0), /* MX6Q_PAD_SD4_DAT7__GPIO_2_15 */
1884 IMX_PIN_REG(MX6Q_PAD_SD4_DAT7, 0x0720, 0x0338, 6, 0x0000, 0), /* MX6Q_PAD_SD4_DAT7__IPU1_IPU_DIAG_BUS_15 */
1885 IMX_PIN_REG(MX6Q_PAD_SD4_DAT7, 0x0720, 0x0338, 7, 0x0000, 0), /* MX6Q_PAD_SD4_DAT7__IPU2_IPU_DIAG_BUS_15 */
1886 IMX_PIN_REG(MX6Q_PAD_SD1_DAT1, 0x0724, 0x033C, 0, 0x0000, 0), /* MX6Q_PAD_SD1_DAT1__USDHC1_DAT1 */
1887 IMX_PIN_REG(MX6Q_PAD_SD1_DAT1, 0x0724, 0x033C, 1, 0x0834, 1), /* MX6Q_PAD_SD1_DAT1__ECSPI5_SS0 */
1888 IMX_PIN_REG(MX6Q_PAD_SD1_DAT1, 0x0724, 0x033C, 2, 0x0000, 0), /* MX6Q_PAD_SD1_DAT1__PWM3_PWMO */
1889 IMX_PIN_REG(MX6Q_PAD_SD1_DAT1, 0x0724, 0x033C, 3, 0x0000, 0), /* MX6Q_PAD_SD1_DAT1__GPT_CAPIN2 */
1890 IMX_PIN_REG(MX6Q_PAD_SD1_DAT1, 0x0724, 0x033C, 4, 0x0000, 0), /* MX6Q_PAD_SD1_DAT1__PCIE_CTRL_MUX_7 */
1891 IMX_PIN_REG(MX6Q_PAD_SD1_DAT1, 0x0724, 0x033C, 5, 0x0000, 0), /* MX6Q_PAD_SD1_DAT1__GPIO_1_17 */
1892 IMX_PIN_REG(MX6Q_PAD_SD1_DAT1, 0x0724, 0x033C, 6, 0x0000, 0), /* MX6Q_PAD_SD1_DAT1__HDMI_TX_OPHYDTB_0 */
1893 IMX_PIN_REG(MX6Q_PAD_SD1_DAT1, 0x0724, 0x033C, 7, 0x0000, 0), /* MX6Q_PAD_SD1_DAT1__ANATOP_TESTO_8 */
1894 IMX_PIN_REG(MX6Q_PAD_SD1_DAT0, 0x0728, 0x0340, 0, 0x0000, 0), /* MX6Q_PAD_SD1_DAT0__USDHC1_DAT0 */
1895 IMX_PIN_REG(MX6Q_PAD_SD1_DAT0, 0x0728, 0x0340, 1, 0x082C, 1), /* MX6Q_PAD_SD1_DAT0__ECSPI5_MISO */
1896 IMX_PIN_REG(MX6Q_PAD_SD1_DAT0, 0x0728, 0x0340, 2, 0x0000, 0), /* MX6Q_PAD_SD1_DAT0__CAAM_WRAP_RNG_OSCOBS */
1897 IMX_PIN_REG(MX6Q_PAD_SD1_DAT0, 0x0728, 0x0340, 3, 0x0000, 0), /* MX6Q_PAD_SD1_DAT0__GPT_CAPIN1 */
1898 IMX_PIN_REG(MX6Q_PAD_SD1_DAT0, 0x0728, 0x0340, 4, 0x0000, 0), /* MX6Q_PAD_SD1_DAT0__PCIE_CTRL_MUX_8 */
1899 IMX_PIN_REG(MX6Q_PAD_SD1_DAT0, 0x0728, 0x0340, 5, 0x0000, 0), /* MX6Q_PAD_SD1_DAT0__GPIO_1_16 */
1900 IMX_PIN_REG(MX6Q_PAD_SD1_DAT0, 0x0728, 0x0340, 6, 0x0000, 0), /* MX6Q_PAD_SD1_DAT0__HDMI_TX_OPHYDTB_1 */
1901 IMX_PIN_REG(MX6Q_PAD_SD1_DAT0, 0x0728, 0x0340, 7, 0x0000, 0), /* MX6Q_PAD_SD1_DAT0__ANATOP_TESTO_7 */
1902 IMX_PIN_REG(MX6Q_PAD_SD1_DAT3, 0x072C, 0x0344, 0, 0x0000, 0), /* MX6Q_PAD_SD1_DAT3__USDHC1_DAT3 */
1903 IMX_PIN_REG(MX6Q_PAD_SD1_DAT3, 0x072C, 0x0344, 1, 0x0000, 0), /* MX6Q_PAD_SD1_DAT3__ECSPI5_SS2 */
1904 IMX_PIN_REG(MX6Q_PAD_SD1_DAT3, 0x072C, 0x0344, 2, 0x0000, 0), /* MX6Q_PAD_SD1_DAT3__GPT_CMPOUT3 */
1905 IMX_PIN_REG(MX6Q_PAD_SD1_DAT3, 0x072C, 0x0344, 3, 0x0000, 0), /* MX6Q_PAD_SD1_DAT3__PWM1_PWMO */
1906 IMX_PIN_REG(MX6Q_PAD_SD1_DAT3, 0x072C, 0x0344, 4, 0x0000, 0), /* MX6Q_PAD_SD1_DAT3__WDOG2_WDOG_B */
1907 IMX_PIN_REG(MX6Q_PAD_SD1_DAT3, 0x072C, 0x0344, 5, 0x0000, 0), /* MX6Q_PAD_SD1_DAT3__GPIO_1_21 */
1908 IMX_PIN_REG(MX6Q_PAD_SD1_DAT3, 0x072C, 0x0344, 6, 0x0000, 0), /* MX6Q_PAD_SD1_DAT3__WDOG2_WDOG_RST_B_DEB */
1909 IMX_PIN_REG(MX6Q_PAD_SD1_DAT3, 0x072C, 0x0344, 7, 0x0000, 0), /* MX6Q_PAD_SD1_DAT3__ANATOP_TESTO_6 */
1910 IMX_PIN_REG(MX6Q_PAD_SD1_CMD, 0x0730, 0x0348, 0, 0x0000, 0), /* MX6Q_PAD_SD1_CMD__USDHC1_CMD */
1911 IMX_PIN_REG(MX6Q_PAD_SD1_CMD, 0x0730, 0x0348, 1, 0x0830, 0), /* MX6Q_PAD_SD1_CMD__ECSPI5_MOSI */
1912 IMX_PIN_REG(MX6Q_PAD_SD1_CMD, 0x0730, 0x0348, 2, 0x0000, 0), /* MX6Q_PAD_SD1_CMD__PWM4_PWMO */
1913 IMX_PIN_REG(MX6Q_PAD_SD1_CMD, 0x0730, 0x0348, 3, 0x0000, 0), /* MX6Q_PAD_SD1_CMD__GPT_CMPOUT1 */
1914 IMX_PIN_REG(MX6Q_PAD_SD1_CMD, 0x0730, 0x0348, 5, 0x0000, 0), /* MX6Q_PAD_SD1_CMD__GPIO_1_18 */
1915 IMX_PIN_REG(MX6Q_PAD_SD1_CMD, 0x0730, 0x0348, 7, 0x0000, 0), /* MX6Q_PAD_SD1_CMD__ANATOP_TESTO_5 */
1916 IMX_PIN_REG(MX6Q_PAD_SD1_DAT2, 0x0734, 0x034C, 0, 0x0000, 0), /* MX6Q_PAD_SD1_DAT2__USDHC1_DAT2 */
1917 IMX_PIN_REG(MX6Q_PAD_SD1_DAT2, 0x0734, 0x034C, 1, 0x0838, 1), /* MX6Q_PAD_SD1_DAT2__ECSPI5_SS1 */
1918 IMX_PIN_REG(MX6Q_PAD_SD1_DAT2, 0x0734, 0x034C, 2, 0x0000, 0), /* MX6Q_PAD_SD1_DAT2__GPT_CMPOUT2 */
1919 IMX_PIN_REG(MX6Q_PAD_SD1_DAT2, 0x0734, 0x034C, 3, 0x0000, 0), /* MX6Q_PAD_SD1_DAT2__PWM2_PWMO */
1920 IMX_PIN_REG(MX6Q_PAD_SD1_DAT2, 0x0734, 0x034C, 4, 0x0000, 0), /* MX6Q_PAD_SD1_DAT2__WDOG1_WDOG_B */
1921 IMX_PIN_REG(MX6Q_PAD_SD1_DAT2, 0x0734, 0x034C, 5, 0x0000, 0), /* MX6Q_PAD_SD1_DAT2__GPIO_1_19 */
1922 IMX_PIN_REG(MX6Q_PAD_SD1_DAT2, 0x0734, 0x034C, 6, 0x0000, 0), /* MX6Q_PAD_SD1_DAT2__WDOG1_WDOG_RST_B_DEB */
1923 IMX_PIN_REG(MX6Q_PAD_SD1_DAT2, 0x0734, 0x034C, 7, 0x0000, 0), /* MX6Q_PAD_SD1_DAT2__ANATOP_TESTO_4 */
1924 IMX_PIN_REG(MX6Q_PAD_SD1_CLK, 0x0738, 0x0350, 0, 0x0000, 0), /* MX6Q_PAD_SD1_CLK__USDHC1_CLK */
1925 IMX_PIN_REG(MX6Q_PAD_SD1_CLK, 0x0738, 0x0350, 1, 0x0828, 0), /* MX6Q_PAD_SD1_CLK__ECSPI5_SCLK */
1926 IMX_PIN_REG(MX6Q_PAD_SD1_CLK, 0x0738, 0x0350, 2, 0x0000, 0), /* MX6Q_PAD_SD1_CLK__OSC32K_32K_OUT */
1927 IMX_PIN_REG(MX6Q_PAD_SD1_CLK, 0x0738, 0x0350, 3, 0x0000, 0), /* MX6Q_PAD_SD1_CLK__GPT_CLKIN */
1928 IMX_PIN_REG(MX6Q_PAD_SD1_CLK, 0x0738, 0x0350, 5, 0x0000, 0), /* MX6Q_PAD_SD1_CLK__GPIO_1_20 */
1929 IMX_PIN_REG(MX6Q_PAD_SD1_CLK, 0x0738, 0x0350, 6, 0x0000, 0), /* MX6Q_PAD_SD1_CLK__PHY_DTB_0 */
1930 IMX_PIN_REG(MX6Q_PAD_SD1_CLK, 0x0738, 0x0350, 7, 0x0000, 0), /* MX6Q_PAD_SD1_CLK__SATA_PHY_DTB_0 */
1931 IMX_PIN_REG(MX6Q_PAD_SD2_CLK, 0x073C, 0x0354, 0, 0x0000, 0), /* MX6Q_PAD_SD2_CLK__USDHC2_CLK */
1932 IMX_PIN_REG(MX6Q_PAD_SD2_CLK, 0x073C, 0x0354, 1, 0x0828, 1), /* MX6Q_PAD_SD2_CLK__ECSPI5_SCLK */
1933 IMX_PIN_REG(MX6Q_PAD_SD2_CLK, 0x073C, 0x0354, 2, 0x08E8, 3), /* MX6Q_PAD_SD2_CLK__KPP_COL_5 */
1934 IMX_PIN_REG(MX6Q_PAD_SD2_CLK, 0x073C, 0x0354, 3, 0x07C0, 1), /* MX6Q_PAD_SD2_CLK__AUDMUX_AUD4_RXFS */
1935 IMX_PIN_REG(MX6Q_PAD_SD2_CLK, 0x073C, 0x0354, 4, 0x0000, 0), /* MX6Q_PAD_SD2_CLK__PCIE_CTRL_MUX_9 */
1936 IMX_PIN_REG(MX6Q_PAD_SD2_CLK, 0x073C, 0x0354, 5, 0x0000, 0), /* MX6Q_PAD_SD2_CLK__GPIO_1_10 */
1937 IMX_PIN_REG(MX6Q_PAD_SD2_CLK, 0x073C, 0x0354, 6, 0x0000, 0), /* MX6Q_PAD_SD2_CLK__PHY_DTB_1 */
1938 IMX_PIN_REG(MX6Q_PAD_SD2_CLK, 0x073C, 0x0354, 7, 0x0000, 0), /* MX6Q_PAD_SD2_CLK__SATA_PHY_DTB_1 */
1939 IMX_PIN_REG(MX6Q_PAD_SD2_CMD, 0x0740, 0x0358, 0, 0x0000, 0), /* MX6Q_PAD_SD2_CMD__USDHC2_CMD */
1940 IMX_PIN_REG(MX6Q_PAD_SD2_CMD, 0x0740, 0x0358, 1, 0x0830, 1), /* MX6Q_PAD_SD2_CMD__ECSPI5_MOSI */
1941 IMX_PIN_REG(MX6Q_PAD_SD2_CMD, 0x0740, 0x0358, 2, 0x08F4, 2), /* MX6Q_PAD_SD2_CMD__KPP_ROW_5 */
1942 IMX_PIN_REG(MX6Q_PAD_SD2_CMD, 0x0740, 0x0358, 3, 0x07BC, 1), /* MX6Q_PAD_SD2_CMD__AUDMUX_AUD4_RXC */
1943 IMX_PIN_REG(MX6Q_PAD_SD2_CMD, 0x0740, 0x0358, 4, 0x0000, 0), /* MX6Q_PAD_SD2_CMD__PCIE_CTRL_MUX_10 */
1944 IMX_PIN_REG(MX6Q_PAD_SD2_CMD, 0x0740, 0x0358, 5, 0x0000, 0), /* MX6Q_PAD_SD2_CMD__GPIO_1_11 */
1945 IMX_PIN_REG(MX6Q_PAD_SD2_DAT3, 0x0744, 0x035C, 0, 0x0000, 0), /* MX6Q_PAD_SD2_DAT3__USDHC2_DAT3 */
1946 IMX_PIN_REG(MX6Q_PAD_SD2_DAT3, 0x0744, 0x035C, 1, 0x0000, 0), /* MX6Q_PAD_SD2_DAT3__ECSPI5_SS3 */
1947 IMX_PIN_REG(MX6Q_PAD_SD2_DAT3, 0x0744, 0x035C, 2, 0x08EC, 2), /* MX6Q_PAD_SD2_DAT3__KPP_COL_6 */
1948 IMX_PIN_REG(MX6Q_PAD_SD2_DAT3, 0x0744, 0x035C, 3, 0x07C4, 1), /* MX6Q_PAD_SD2_DAT3__AUDMUX_AUD4_TXC */
1949 IMX_PIN_REG(MX6Q_PAD_SD2_DAT3, 0x0744, 0x035C, 4, 0x0000, 0), /* MX6Q_PAD_SD2_DAT3__PCIE_CTRL_MUX_11 */
1950 IMX_PIN_REG(MX6Q_PAD_SD2_DAT3, 0x0744, 0x035C, 5, 0x0000, 0), /* MX6Q_PAD_SD2_DAT3__GPIO_1_12 */
1951 IMX_PIN_REG(MX6Q_PAD_SD2_DAT3, 0x0744, 0x035C, 6, 0x0000, 0), /* MX6Q_PAD_SD2_DAT3__SJC_DONE */
1952 IMX_PIN_REG(MX6Q_PAD_SD2_DAT3, 0x0744, 0x035C, 7, 0x0000, 0), /* MX6Q_PAD_SD2_DAT3__ANATOP_TESTO_3 */
1953};
1954
1955/* Pad names for the pinmux subsystem */
1956static const struct pinctrl_pin_desc imx6q_pinctrl_pads[] = {
1957 IMX_PINCTRL_PIN(MX6Q_PAD_SD2_DAT1),
1958 IMX_PINCTRL_PIN(MX6Q_PAD_SD2_DAT2),
1959 IMX_PINCTRL_PIN(MX6Q_PAD_SD2_DAT0),
1960 IMX_PINCTRL_PIN(MX6Q_PAD_RGMII_TXC),
1961 IMX_PINCTRL_PIN(MX6Q_PAD_RGMII_TD0),
1962 IMX_PINCTRL_PIN(MX6Q_PAD_RGMII_TD1),
1963 IMX_PINCTRL_PIN(MX6Q_PAD_RGMII_TD2),
1964 IMX_PINCTRL_PIN(MX6Q_PAD_RGMII_TD3),
1965 IMX_PINCTRL_PIN(MX6Q_PAD_RGMII_RX_CTL),
1966 IMX_PINCTRL_PIN(MX6Q_PAD_RGMII_RD0),
1967 IMX_PINCTRL_PIN(MX6Q_PAD_RGMII_TX_CTL),
1968 IMX_PINCTRL_PIN(MX6Q_PAD_RGMII_RD1),
1969 IMX_PINCTRL_PIN(MX6Q_PAD_RGMII_RD2),
1970 IMX_PINCTRL_PIN(MX6Q_PAD_RGMII_RD3),
1971 IMX_PINCTRL_PIN(MX6Q_PAD_RGMII_RXC),
1972 IMX_PINCTRL_PIN(MX6Q_PAD_EIM_A25),
1973 IMX_PINCTRL_PIN(MX6Q_PAD_EIM_EB2),
1974 IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D16),
1975 IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D17),
1976 IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D18),
1977 IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D19),
1978 IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D20),
1979 IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D21),
1980 IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D22),
1981 IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D23),
1982 IMX_PINCTRL_PIN(MX6Q_PAD_EIM_EB3),
1983 IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D24),
1984 IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D25),
1985 IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D26),
1986 IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D27),
1987 IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D28),
1988 IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D29),
1989 IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D30),
1990 IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D31),
1991 IMX_PINCTRL_PIN(MX6Q_PAD_EIM_A24),
1992 IMX_PINCTRL_PIN(MX6Q_PAD_EIM_A23),
1993 IMX_PINCTRL_PIN(MX6Q_PAD_EIM_A22),
1994 IMX_PINCTRL_PIN(MX6Q_PAD_EIM_A21),
1995 IMX_PINCTRL_PIN(MX6Q_PAD_EIM_A20),
1996 IMX_PINCTRL_PIN(MX6Q_PAD_EIM_A19),
1997 IMX_PINCTRL_PIN(MX6Q_PAD_EIM_A18),
1998 IMX_PINCTRL_PIN(MX6Q_PAD_EIM_A17),
1999 IMX_PINCTRL_PIN(MX6Q_PAD_EIM_A16),
2000 IMX_PINCTRL_PIN(MX6Q_PAD_EIM_CS0),
2001 IMX_PINCTRL_PIN(MX6Q_PAD_EIM_CS1),
2002 IMX_PINCTRL_PIN(MX6Q_PAD_EIM_OE),
2003 IMX_PINCTRL_PIN(MX6Q_PAD_EIM_RW),
2004 IMX_PINCTRL_PIN(MX6Q_PAD_EIM_LBA),
2005 IMX_PINCTRL_PIN(MX6Q_PAD_EIM_EB0),
2006 IMX_PINCTRL_PIN(MX6Q_PAD_EIM_EB1),
2007 IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA0),
2008 IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA1),
2009 IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA2),
2010 IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA3),
2011 IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA4),
2012 IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA5),
2013 IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA6),
2014 IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA7),
2015 IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA8),
2016 IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA9),
2017 IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA10),
2018 IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA11),
2019 IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA12),
2020 IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA13),
2021 IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA14),
2022 IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA15),
2023 IMX_PINCTRL_PIN(MX6Q_PAD_EIM_WAIT),
2024 IMX_PINCTRL_PIN(MX6Q_PAD_EIM_BCLK),
2025 IMX_PINCTRL_PIN(MX6Q_PAD_DI0_DISP_CLK),
2026 IMX_PINCTRL_PIN(MX6Q_PAD_DI0_PIN15),
2027 IMX_PINCTRL_PIN(MX6Q_PAD_DI0_PIN2),
2028 IMX_PINCTRL_PIN(MX6Q_PAD_DI0_PIN3),
2029 IMX_PINCTRL_PIN(MX6Q_PAD_DI0_PIN4),
2030 IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT0),
2031 IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT1),
2032 IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT2),
2033 IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT3),
2034 IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT4),
2035 IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT5),
2036 IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT6),
2037 IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT7),
2038 IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT8),
2039 IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT9),
2040 IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT10),
2041 IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT11),
2042 IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT12),
2043 IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT13),
2044 IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT14),
2045 IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT15),
2046 IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT16),
2047 IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT17),
2048 IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT18),
2049 IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT19),
2050 IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT20),
2051 IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT21),
2052 IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT22),
2053 IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT23),
2054 IMX_PINCTRL_PIN(MX6Q_PAD_ENET_MDIO),
2055 IMX_PINCTRL_PIN(MX6Q_PAD_ENET_REF_CLK),
2056 IMX_PINCTRL_PIN(MX6Q_PAD_ENET_RX_ER),
2057 IMX_PINCTRL_PIN(MX6Q_PAD_ENET_CRS_DV),
2058 IMX_PINCTRL_PIN(MX6Q_PAD_ENET_RXD1),
2059 IMX_PINCTRL_PIN(MX6Q_PAD_ENET_RXD0),
2060 IMX_PINCTRL_PIN(MX6Q_PAD_ENET_TX_EN),
2061 IMX_PINCTRL_PIN(MX6Q_PAD_ENET_TXD1),
2062 IMX_PINCTRL_PIN(MX6Q_PAD_ENET_TXD0),
2063 IMX_PINCTRL_PIN(MX6Q_PAD_ENET_MDC),
2064 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D40),
2065 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D41),
2066 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D42),
2067 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D43),
2068 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D44),
2069 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D45),
2070 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D46),
2071 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D47),
2072 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDQS5),
2073 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_DQM5),
2074 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D32),
2075 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D33),
2076 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D34),
2077 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D35),
2078 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D36),
2079 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D37),
2080 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D38),
2081 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D39),
2082 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_DQM4),
2083 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDQS4),
2084 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D24),
2085 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D25),
2086 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D26),
2087 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D27),
2088 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D28),
2089 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D29),
2090 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDQS3),
2091 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D30),
2092 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D31),
2093 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_DQM3),
2094 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D16),
2095 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D17),
2096 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D18),
2097 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D19),
2098 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D20),
2099 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D21),
2100 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D22),
2101 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDQS2),
2102 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D23),
2103 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_DQM2),
2104 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_A0),
2105 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_A1),
2106 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_A2),
2107 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_A3),
2108 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_A4),
2109 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_A5),
2110 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_A6),
2111 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_A7),
2112 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_A8),
2113 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_A9),
2114 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_A10),
2115 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_A11),
2116 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_A12),
2117 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_A13),
2118 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_A14),
2119 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_A15),
2120 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_CAS),
2121 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_CS0),
2122 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_CS1),
2123 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_RAS),
2124 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_RESET),
2125 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDBA0),
2126 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDBA1),
2127 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDCLK_0),
2128 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDBA2),
2129 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDCKE0),
2130 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDCLK_1),
2131 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDCKE1),
2132 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDODT0),
2133 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDODT1),
2134 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDWE),
2135 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D0),
2136 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D1),
2137 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D2),
2138 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D3),
2139 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D4),
2140 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D5),
2141 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDQS0),
2142 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D6),
2143 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D7),
2144 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_DQM0),
2145 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D8),
2146 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D9),
2147 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D10),
2148 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D11),
2149 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D12),
2150 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D13),
2151 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D14),
2152 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDQS1),
2153 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D15),
2154 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_DQM1),
2155 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D48),
2156 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D49),
2157 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D50),
2158 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D51),
2159 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D52),
2160 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D53),
2161 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D54),
2162 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D55),
2163 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDQS6),
2164 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_DQM6),
2165 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D56),
2166 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDQS7),
2167 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D57),
2168 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D58),
2169 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D59),
2170 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D60),
2171 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_DQM7),
2172 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D61),
2173 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D62),
2174 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D63),
2175 IMX_PINCTRL_PIN(MX6Q_PAD_KEY_COL0),
2176 IMX_PINCTRL_PIN(MX6Q_PAD_KEY_ROW0),
2177 IMX_PINCTRL_PIN(MX6Q_PAD_KEY_COL1),
2178 IMX_PINCTRL_PIN(MX6Q_PAD_KEY_ROW1),
2179 IMX_PINCTRL_PIN(MX6Q_PAD_KEY_COL2),
2180 IMX_PINCTRL_PIN(MX6Q_PAD_KEY_ROW2),
2181 IMX_PINCTRL_PIN(MX6Q_PAD_KEY_COL3),
2182 IMX_PINCTRL_PIN(MX6Q_PAD_KEY_ROW3),
2183 IMX_PINCTRL_PIN(MX6Q_PAD_KEY_COL4),
2184 IMX_PINCTRL_PIN(MX6Q_PAD_KEY_ROW4),
2185 IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_0),
2186 IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_1),
2187 IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_9),
2188 IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_3),
2189 IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_6),
2190 IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_2),
2191 IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_4),
2192 IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_5),
2193 IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_7),
2194 IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_8),
2195 IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_16),
2196 IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_17),
2197 IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_18),
2198 IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_19),
2199 IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_PIXCLK),
2200 IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_MCLK),
2201 IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DATA_EN),
2202 IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_VSYNC),
2203 IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT4),
2204 IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT5),
2205 IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT6),
2206 IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT7),
2207 IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT8),
2208 IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT9),
2209 IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT10),
2210 IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT11),
2211 IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT12),
2212 IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT13),
2213 IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT14),
2214 IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT15),
2215 IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT16),
2216 IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT17),
2217 IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT18),
2218 IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT19),
2219 IMX_PINCTRL_PIN(MX6Q_PAD_JTAG_TMS),
2220 IMX_PINCTRL_PIN(MX6Q_PAD_JTAG_MOD),
2221 IMX_PINCTRL_PIN(MX6Q_PAD_JTAG_TRSTB),
2222 IMX_PINCTRL_PIN(MX6Q_PAD_JTAG_TDI),
2223 IMX_PINCTRL_PIN(MX6Q_PAD_JTAG_TCK),
2224 IMX_PINCTRL_PIN(MX6Q_PAD_JTAG_TDO),
2225 IMX_PINCTRL_PIN(MX6Q_PAD_LVDS1_TX3_P),
2226 IMX_PINCTRL_PIN(MX6Q_PAD_LVDS1_TX2_P),
2227 IMX_PINCTRL_PIN(MX6Q_PAD_LVDS1_CLK_P),
2228 IMX_PINCTRL_PIN(MX6Q_PAD_LVDS1_TX1_P),
2229 IMX_PINCTRL_PIN(MX6Q_PAD_LVDS1_TX0_P),
2230 IMX_PINCTRL_PIN(MX6Q_PAD_LVDS0_TX3_P),
2231 IMX_PINCTRL_PIN(MX6Q_PAD_LVDS0_CLK_P),
2232 IMX_PINCTRL_PIN(MX6Q_PAD_LVDS0_TX2_P),
2233 IMX_PINCTRL_PIN(MX6Q_PAD_LVDS0_TX1_P),
2234 IMX_PINCTRL_PIN(MX6Q_PAD_LVDS0_TX0_P),
2235 IMX_PINCTRL_PIN(MX6Q_PAD_TAMPER),
2236 IMX_PINCTRL_PIN(MX6Q_PAD_PMIC_ON_REQ),
2237 IMX_PINCTRL_PIN(MX6Q_PAD_PMIC_STBY_REQ),
2238 IMX_PINCTRL_PIN(MX6Q_PAD_POR_B),
2239 IMX_PINCTRL_PIN(MX6Q_PAD_BOOT_MODE1),
2240 IMX_PINCTRL_PIN(MX6Q_PAD_RESET_IN_B),
2241 IMX_PINCTRL_PIN(MX6Q_PAD_BOOT_MODE0),
2242 IMX_PINCTRL_PIN(MX6Q_PAD_TEST_MODE),
2243 IMX_PINCTRL_PIN(MX6Q_PAD_SD3_DAT7),
2244 IMX_PINCTRL_PIN(MX6Q_PAD_SD3_DAT6),
2245 IMX_PINCTRL_PIN(MX6Q_PAD_SD3_DAT5),
2246 IMX_PINCTRL_PIN(MX6Q_PAD_SD3_DAT4),
2247 IMX_PINCTRL_PIN(MX6Q_PAD_SD3_CMD),
2248 IMX_PINCTRL_PIN(MX6Q_PAD_SD3_CLK),
2249 IMX_PINCTRL_PIN(MX6Q_PAD_SD3_DAT0),
2250 IMX_PINCTRL_PIN(MX6Q_PAD_SD3_DAT1),
2251 IMX_PINCTRL_PIN(MX6Q_PAD_SD3_DAT2),
2252 IMX_PINCTRL_PIN(MX6Q_PAD_SD3_DAT3),
2253 IMX_PINCTRL_PIN(MX6Q_PAD_SD3_RST),
2254 IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_CLE),
2255 IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_ALE),
2256 IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_WP_B),
2257 IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_RB0),
2258 IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_CS0),
2259 IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_CS1),
2260 IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_CS2),
2261 IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_CS3),
2262 IMX_PINCTRL_PIN(MX6Q_PAD_SD4_CMD),
2263 IMX_PINCTRL_PIN(MX6Q_PAD_SD4_CLK),
2264 IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_D0),
2265 IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_D1),
2266 IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_D2),
2267 IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_D3),
2268 IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_D4),
2269 IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_D5),
2270 IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_D6),
2271 IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_D7),
2272 IMX_PINCTRL_PIN(MX6Q_PAD_SD4_DAT0),
2273 IMX_PINCTRL_PIN(MX6Q_PAD_SD4_DAT1),
2274 IMX_PINCTRL_PIN(MX6Q_PAD_SD4_DAT2),
2275 IMX_PINCTRL_PIN(MX6Q_PAD_SD4_DAT3),
2276 IMX_PINCTRL_PIN(MX6Q_PAD_SD4_DAT4),
2277 IMX_PINCTRL_PIN(MX6Q_PAD_SD4_DAT5),
2278 IMX_PINCTRL_PIN(MX6Q_PAD_SD4_DAT6),
2279 IMX_PINCTRL_PIN(MX6Q_PAD_SD4_DAT7),
2280 IMX_PINCTRL_PIN(MX6Q_PAD_SD1_DAT1),
2281 IMX_PINCTRL_PIN(MX6Q_PAD_SD1_DAT0),
2282 IMX_PINCTRL_PIN(MX6Q_PAD_SD1_DAT3),
2283 IMX_PINCTRL_PIN(MX6Q_PAD_SD1_CMD),
2284 IMX_PINCTRL_PIN(MX6Q_PAD_SD1_DAT2),
2285 IMX_PINCTRL_PIN(MX6Q_PAD_SD1_CLK),
2286 IMX_PINCTRL_PIN(MX6Q_PAD_SD2_CLK),
2287 IMX_PINCTRL_PIN(MX6Q_PAD_SD2_CMD),
2288 IMX_PINCTRL_PIN(MX6Q_PAD_SD2_DAT3),
2289};
2290
2291static struct imx_pinctrl_soc_info imx6q_pinctrl_info = {
2292 .pins = imx6q_pinctrl_pads,
2293 .npins = ARRAY_SIZE(imx6q_pinctrl_pads),
2294 .pin_regs = imx6q_pin_regs,
2295 .npin_regs = ARRAY_SIZE(imx6q_pin_regs),
2296};
2297
2298static struct of_device_id imx6q_pinctrl_of_match[] __devinitdata = {
2299 { .compatible = "fsl,imx6q-iomuxc", },
2300 { /* sentinel */ }
2301};
2302
2303static int __devinit imx6q_pinctrl_probe(struct platform_device *pdev)
2304{
2305 return imx_pinctrl_probe(pdev, &imx6q_pinctrl_info);
2306}
2307
2308static struct platform_driver imx6q_pinctrl_driver = {
2309 .driver = {
2310 .name = "imx6q-pinctrl",
2311 .owner = THIS_MODULE,
2312 .of_match_table = of_match_ptr(imx6q_pinctrl_of_match),
2313 },
2314 .probe = imx6q_pinctrl_probe,
2315 .remove = __devexit_p(imx_pinctrl_remove),
2316};
2317
2318static int __init imx6q_pinctrl_init(void)
2319{
2320 return platform_driver_register(&imx6q_pinctrl_driver);
2321}
2322arch_initcall(imx6q_pinctrl_init);
2323
2324static void __exit imx6q_pinctrl_exit(void)
2325{
2326 platform_driver_unregister(&imx6q_pinctrl_driver);
2327}
2328module_exit(imx6q_pinctrl_exit);
2329MODULE_AUTHOR("Dong Aisheng <dong.aisheng@linaro.org>");
2330MODULE_DESCRIPTION("Freescale IMX6Q pinctrl driver");
2331MODULE_LICENSE("GPL v2");
diff --git a/drivers/pinctrl/pinctrl-mxs.c b/drivers/pinctrl/pinctrl-mxs.c
new file mode 100644
index 00000000000..93cd959971c
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-mxs.c
@@ -0,0 +1,508 @@
1/*
2 * Copyright 2012 Freescale Semiconductor, Inc.
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12#include <linux/err.h>
13#include <linux/init.h>
14#include <linux/io.h>
15#include <linux/module.h>
16#include <linux/of.h>
17#include <linux/of_address.h>
18#include <linux/pinctrl/machine.h>
19#include <linux/pinctrl/pinconf.h>
20#include <linux/pinctrl/pinctrl.h>
21#include <linux/pinctrl/pinmux.h>
22#include <linux/platform_device.h>
23#include <linux/slab.h>
24#include "core.h"
25#include "pinctrl-mxs.h"
26
27#define SUFFIX_LEN 4
28
29struct mxs_pinctrl_data {
30 struct device *dev;
31 struct pinctrl_dev *pctl;
32 void __iomem *base;
33 struct mxs_pinctrl_soc_data *soc;
34};
35
36static int mxs_get_groups_count(struct pinctrl_dev *pctldev)
37{
38 struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev);
39
40 return d->soc->ngroups;
41}
42
43static const char *mxs_get_group_name(struct pinctrl_dev *pctldev,
44 unsigned group)
45{
46 struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev);
47
48 return d->soc->groups[group].name;
49}
50
51static int mxs_get_group_pins(struct pinctrl_dev *pctldev, unsigned group,
52 const unsigned **pins, unsigned *num_pins)
53{
54 struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev);
55
56 *pins = d->soc->groups[group].pins;
57 *num_pins = d->soc->groups[group].npins;
58
59 return 0;
60}
61
62static void mxs_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
63 unsigned offset)
64{
65 seq_printf(s, " %s", dev_name(pctldev->dev));
66}
67
68static int mxs_dt_node_to_map(struct pinctrl_dev *pctldev,
69 struct device_node *np,
70 struct pinctrl_map **map, unsigned *num_maps)
71{
72 struct pinctrl_map *new_map;
73 char *group;
74 unsigned new_num;
75 unsigned long config = 0;
76 unsigned long *pconfig;
77 int length = strlen(np->name) + SUFFIX_LEN;
78 u32 val;
79 int ret;
80
81 ret = of_property_read_u32(np, "fsl,drive-strength", &val);
82 if (!ret)
83 config = val | MA_PRESENT;
84 ret = of_property_read_u32(np, "fsl,voltage", &val);
85 if (!ret)
86 config |= val << VOL_SHIFT | VOL_PRESENT;
87 ret = of_property_read_u32(np, "fsl,pull-up", &val);
88 if (!ret)
89 config |= val << PULL_SHIFT | PULL_PRESENT;
90
91 new_num = config ? 2 : 1;
92 new_map = kzalloc(sizeof(*new_map) * new_num, GFP_KERNEL);
93 if (!new_map)
94 return -ENOMEM;
95
96 new_map[0].type = PIN_MAP_TYPE_MUX_GROUP;
97 new_map[0].data.mux.function = np->name;
98
99 /* Compose group name */
100 group = kzalloc(length, GFP_KERNEL);
101 if (!group)
102 return -ENOMEM;
103 of_property_read_u32(np, "reg", &val);
104 snprintf(group, length, "%s.%d", np->name, val);
105 new_map[0].data.mux.group = group;
106
107 if (config) {
108 pconfig = kmemdup(&config, sizeof(config), GFP_KERNEL);
109 if (!pconfig) {
110 ret = -ENOMEM;
111 goto free;
112 }
113
114 new_map[1].type = PIN_MAP_TYPE_CONFIGS_GROUP;
115 new_map[1].data.configs.group_or_pin = group;
116 new_map[1].data.configs.configs = pconfig;
117 new_map[1].data.configs.num_configs = 1;
118 }
119
120 *map = new_map;
121 *num_maps = new_num;
122
123 return 0;
124
125free:
126 kfree(new_map);
127 return ret;
128}
129
130static void mxs_dt_free_map(struct pinctrl_dev *pctldev,
131 struct pinctrl_map *map, unsigned num_maps)
132{
133 int i;
134
135 for (i = 0; i < num_maps; i++) {
136 if (map[i].type == PIN_MAP_TYPE_MUX_GROUP)
137 kfree(map[i].data.mux.group);
138 if (map[i].type == PIN_MAP_TYPE_CONFIGS_GROUP)
139 kfree(map[i].data.configs.configs);
140 }
141
142 kfree(map);
143}
144
145static struct pinctrl_ops mxs_pinctrl_ops = {
146 .get_groups_count = mxs_get_groups_count,
147 .get_group_name = mxs_get_group_name,
148 .get_group_pins = mxs_get_group_pins,
149 .pin_dbg_show = mxs_pin_dbg_show,
150 .dt_node_to_map = mxs_dt_node_to_map,
151 .dt_free_map = mxs_dt_free_map,
152};
153
154static int mxs_pinctrl_get_funcs_count(struct pinctrl_dev *pctldev)
155{
156 struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev);
157
158 return d->soc->nfunctions;
159}
160
161static const char *mxs_pinctrl_get_func_name(struct pinctrl_dev *pctldev,
162 unsigned function)
163{
164 struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev);
165
166 return d->soc->functions[function].name;
167}
168
169static int mxs_pinctrl_get_func_groups(struct pinctrl_dev *pctldev,
170 unsigned group,
171 const char * const **groups,
172 unsigned * const num_groups)
173{
174 struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev);
175
176 *groups = d->soc->functions[group].groups;
177 *num_groups = d->soc->functions[group].ngroups;
178
179 return 0;
180}
181
182static int mxs_pinctrl_enable(struct pinctrl_dev *pctldev, unsigned selector,
183 unsigned group)
184{
185 struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev);
186 struct mxs_group *g = &d->soc->groups[group];
187 void __iomem *reg;
188 u8 bank, shift;
189 u16 pin;
190 int i;
191
192 for (i = 0; i < g->npins; i++) {
193 bank = PINID_TO_BANK(g->pins[i]);
194 pin = PINID_TO_PIN(g->pins[i]);
195 reg = d->base + d->soc->regs->muxsel;
196 reg += bank * 0x20 + pin / 16 * 0x10;
197 shift = pin % 16 * 2;
198
199 writel(0x3 << shift, reg + CLR);
200 writel(g->muxsel[i] << shift, reg + SET);
201 }
202
203 return 0;
204}
205
206static void mxs_pinctrl_disable(struct pinctrl_dev *pctldev,
207 unsigned function, unsigned group)
208{
209 /* Nothing to do here */
210}
211
212static struct pinmux_ops mxs_pinmux_ops = {
213 .get_functions_count = mxs_pinctrl_get_funcs_count,
214 .get_function_name = mxs_pinctrl_get_func_name,
215 .get_function_groups = mxs_pinctrl_get_func_groups,
216 .enable = mxs_pinctrl_enable,
217 .disable = mxs_pinctrl_disable,
218};
219
220static int mxs_pinconf_get(struct pinctrl_dev *pctldev,
221 unsigned pin, unsigned long *config)
222{
223 return -ENOTSUPP;
224}
225
226static int mxs_pinconf_set(struct pinctrl_dev *pctldev,
227 unsigned pin, unsigned long config)
228{
229 return -ENOTSUPP;
230}
231
232static int mxs_pinconf_group_get(struct pinctrl_dev *pctldev,
233 unsigned group, unsigned long *config)
234{
235 struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev);
236
237 *config = d->soc->groups[group].config;
238
239 return 0;
240}
241
242static int mxs_pinconf_group_set(struct pinctrl_dev *pctldev,
243 unsigned group, unsigned long config)
244{
245 struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev);
246 struct mxs_group *g = &d->soc->groups[group];
247 void __iomem *reg;
248 u8 ma, vol, pull, bank, shift;
249 u16 pin;
250 int i;
251
252 ma = CONFIG_TO_MA(config);
253 vol = CONFIG_TO_VOL(config);
254 pull = CONFIG_TO_PULL(config);
255
256 for (i = 0; i < g->npins; i++) {
257 bank = PINID_TO_BANK(g->pins[i]);
258 pin = PINID_TO_PIN(g->pins[i]);
259
260 /* drive */
261 reg = d->base + d->soc->regs->drive;
262 reg += bank * 0x40 + pin / 8 * 0x10;
263
264 /* mA */
265 if (config & MA_PRESENT) {
266 shift = pin % 8 * 4;
267 writel(0x3 << shift, reg + CLR);
268 writel(ma << shift, reg + SET);
269 }
270
271 /* vol */
272 if (config & VOL_PRESENT) {
273 shift = pin % 8 * 4 + 2;
274 if (vol)
275 writel(1 << shift, reg + SET);
276 else
277 writel(1 << shift, reg + CLR);
278 }
279
280 /* pull */
281 if (config & PULL_PRESENT) {
282 reg = d->base + d->soc->regs->pull;
283 reg += bank * 0x10;
284 shift = pin;
285 if (pull)
286 writel(1 << shift, reg + SET);
287 else
288 writel(1 << shift, reg + CLR);
289 }
290 }
291
292 /* cache the config value for mxs_pinconf_group_get() */
293 g->config = config;
294
295 return 0;
296}
297
298static void mxs_pinconf_dbg_show(struct pinctrl_dev *pctldev,
299 struct seq_file *s, unsigned pin)
300{
301 /* Not support */
302}
303
304static void mxs_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
305 struct seq_file *s, unsigned group)
306{
307 unsigned long config;
308
309 if (!mxs_pinconf_group_get(pctldev, group, &config))
310 seq_printf(s, "0x%lx", config);
311}
312
313struct pinconf_ops mxs_pinconf_ops = {
314 .pin_config_get = mxs_pinconf_get,
315 .pin_config_set = mxs_pinconf_set,
316 .pin_config_group_get = mxs_pinconf_group_get,
317 .pin_config_group_set = mxs_pinconf_group_set,
318 .pin_config_dbg_show = mxs_pinconf_dbg_show,
319 .pin_config_group_dbg_show = mxs_pinconf_group_dbg_show,
320};
321
322static struct pinctrl_desc mxs_pinctrl_desc = {
323 .pctlops = &mxs_pinctrl_ops,
324 .pmxops = &mxs_pinmux_ops,
325 .confops = &mxs_pinconf_ops,
326 .owner = THIS_MODULE,
327};
328
329static int __devinit mxs_pinctrl_parse_group(struct platform_device *pdev,
330 struct device_node *np, int idx,
331 const char **out_name)
332{
333 struct mxs_pinctrl_data *d = platform_get_drvdata(pdev);
334 struct mxs_group *g = &d->soc->groups[idx];
335 struct property *prop;
336 const char *propname = "fsl,pinmux-ids";
337 char *group;
338 int length = strlen(np->name) + SUFFIX_LEN;
339 int i;
340 u32 val;
341
342 group = devm_kzalloc(&pdev->dev, length, GFP_KERNEL);
343 if (!group)
344 return -ENOMEM;
345 of_property_read_u32(np, "reg", &val);
346 snprintf(group, length, "%s.%d", np->name, val);
347 g->name = group;
348
349 prop = of_find_property(np, propname, &length);
350 if (!prop)
351 return -EINVAL;
352 g->npins = length / sizeof(u32);
353
354 g->pins = devm_kzalloc(&pdev->dev, g->npins * sizeof(*g->pins),
355 GFP_KERNEL);
356 if (!g->pins)
357 return -ENOMEM;
358
359 g->muxsel = devm_kzalloc(&pdev->dev, g->npins * sizeof(*g->muxsel),
360 GFP_KERNEL);
361 if (!g->muxsel)
362 return -ENOMEM;
363
364 of_property_read_u32_array(np, propname, g->pins, g->npins);
365 for (i = 0; i < g->npins; i++) {
366 g->muxsel[i] = MUXID_TO_MUXSEL(g->pins[i]);
367 g->pins[i] = MUXID_TO_PINID(g->pins[i]);
368 }
369
370 *out_name = g->name;
371
372 return 0;
373}
374
375static int __devinit mxs_pinctrl_probe_dt(struct platform_device *pdev,
376 struct mxs_pinctrl_data *d)
377{
378 struct mxs_pinctrl_soc_data *soc = d->soc;
379 struct device_node *np = pdev->dev.of_node;
380 struct device_node *child;
381 struct mxs_function *f;
382 const char *fn, *fnull = "";
383 int i = 0, idxf = 0, idxg = 0;
384 int ret;
385 u32 val;
386
387 child = of_get_next_child(np, NULL);
388 if (!child) {
389 dev_err(&pdev->dev, "no group is defined\n");
390 return -ENOENT;
391 }
392
393 /* Count total functions and groups */
394 fn = fnull;
395 for_each_child_of_node(np, child) {
396 /* Skip pure pinconf node */
397 if (of_property_read_u32(child, "reg", &val))
398 continue;
399 if (strcmp(fn, child->name)) {
400 fn = child->name;
401 soc->nfunctions++;
402 }
403 soc->ngroups++;
404 }
405
406 soc->functions = devm_kzalloc(&pdev->dev, soc->nfunctions *
407 sizeof(*soc->functions), GFP_KERNEL);
408 if (!soc->functions)
409 return -ENOMEM;
410
411 soc->groups = devm_kzalloc(&pdev->dev, soc->ngroups *
412 sizeof(*soc->groups), GFP_KERNEL);
413 if (!soc->groups)
414 return -ENOMEM;
415
416 /* Count groups for each function */
417 fn = fnull;
418 f = &soc->functions[idxf];
419 for_each_child_of_node(np, child) {
420 if (of_property_read_u32(child, "reg", &val))
421 continue;
422 if (strcmp(fn, child->name)) {
423 f = &soc->functions[idxf++];
424 f->name = fn = child->name;
425 }
426 f->ngroups++;
427 };
428
429 /* Get groups for each function */
430 idxf = 0;
431 fn = fnull;
432 for_each_child_of_node(np, child) {
433 if (of_property_read_u32(child, "reg", &val))
434 continue;
435 if (strcmp(fn, child->name)) {
436 f = &soc->functions[idxf++];
437 f->groups = devm_kzalloc(&pdev->dev, f->ngroups *
438 sizeof(*f->groups),
439 GFP_KERNEL);
440 if (!f->groups)
441 return -ENOMEM;
442 fn = child->name;
443 i = 0;
444 }
445 ret = mxs_pinctrl_parse_group(pdev, child, idxg++,
446 &f->groups[i++]);
447 if (ret)
448 return ret;
449 }
450
451 return 0;
452}
453
454int __devinit mxs_pinctrl_probe(struct platform_device *pdev,
455 struct mxs_pinctrl_soc_data *soc)
456{
457 struct device_node *np = pdev->dev.of_node;
458 struct mxs_pinctrl_data *d;
459 int ret;
460
461 d = devm_kzalloc(&pdev->dev, sizeof(*d), GFP_KERNEL);
462 if (!d)
463 return -ENOMEM;
464
465 d->dev = &pdev->dev;
466 d->soc = soc;
467
468 d->base = of_iomap(np, 0);
469 if (!d->base)
470 return -EADDRNOTAVAIL;
471
472 mxs_pinctrl_desc.pins = d->soc->pins;
473 mxs_pinctrl_desc.npins = d->soc->npins;
474 mxs_pinctrl_desc.name = dev_name(&pdev->dev);
475
476 platform_set_drvdata(pdev, d);
477
478 ret = mxs_pinctrl_probe_dt(pdev, d);
479 if (ret) {
480 dev_err(&pdev->dev, "dt probe failed: %d\n", ret);
481 goto err;
482 }
483
484 d->pctl = pinctrl_register(&mxs_pinctrl_desc, &pdev->dev, d);
485 if (!d->pctl) {
486 dev_err(&pdev->dev, "Couldn't register MXS pinctrl driver\n");
487 ret = -EINVAL;
488 goto err;
489 }
490
491 return 0;
492
493err:
494 iounmap(d->base);
495 return ret;
496}
497EXPORT_SYMBOL_GPL(mxs_pinctrl_probe);
498
499int __devexit mxs_pinctrl_remove(struct platform_device *pdev)
500{
501 struct mxs_pinctrl_data *d = platform_get_drvdata(pdev);
502
503 pinctrl_unregister(d->pctl);
504 iounmap(d->base);
505
506 return 0;
507}
508EXPORT_SYMBOL_GPL(mxs_pinctrl_remove);
diff --git a/drivers/pinctrl/pinctrl-mxs.h b/drivers/pinctrl/pinctrl-mxs.h
new file mode 100644
index 00000000000..fdd88d0bae2
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-mxs.h
@@ -0,0 +1,91 @@
1/*
2 * Copyright 2012 Freescale Semiconductor, Inc.
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12#ifndef __PINCTRL_MXS_H
13#define __PINCTRL_MXS_H
14
15#include <linux/platform_device.h>
16#include <linux/pinctrl/pinctrl.h>
17
18#define SET 0x4
19#define CLR 0x8
20#define TOG 0xc
21
22#define MXS_PINCTRL_PIN(pin) PINCTRL_PIN(pin, #pin)
23#define PINID(bank, pin) ((bank) * 32 + (pin))
24
25/*
26 * pinmux-id bit field definitions
27 *
28 * bank: 15..12 (4)
29 * pin: 11..4 (8)
30 * muxsel: 3..0 (4)
31 */
32#define MUXID_TO_PINID(m) PINID((m) >> 12 & 0xf, (m) >> 4 & 0xff)
33#define MUXID_TO_MUXSEL(m) ((m) & 0xf)
34
35#define PINID_TO_BANK(p) ((p) >> 5)
36#define PINID_TO_PIN(p) ((p) % 32)
37
38/*
39 * pin config bit field definitions
40 *
41 * pull-up: 6..5 (2)
42 * voltage: 4..3 (2)
43 * mA: 2..0 (3)
44 *
45 * MSB of each field is presence bit for the config.
46 */
47#define PULL_PRESENT (1 << 6)
48#define PULL_SHIFT 5
49#define VOL_PRESENT (1 << 4)
50#define VOL_SHIFT 3
51#define MA_PRESENT (1 << 2)
52#define MA_SHIFT 0
53#define CONFIG_TO_PULL(c) ((c) >> PULL_SHIFT & 0x1)
54#define CONFIG_TO_VOL(c) ((c) >> VOL_SHIFT & 0x1)
55#define CONFIG_TO_MA(c) ((c) >> MA_SHIFT & 0x3)
56
57struct mxs_function {
58 const char *name;
59 const char **groups;
60 unsigned ngroups;
61};
62
63struct mxs_group {
64 const char *name;
65 unsigned int *pins;
66 unsigned npins;
67 u8 *muxsel;
68 u8 config;
69};
70
71struct mxs_regs {
72 u16 muxsel;
73 u16 drive;
74 u16 pull;
75};
76
77struct mxs_pinctrl_soc_data {
78 const struct mxs_regs *regs;
79 const struct pinctrl_pin_desc *pins;
80 unsigned npins;
81 struct mxs_function *functions;
82 unsigned nfunctions;
83 struct mxs_group *groups;
84 unsigned ngroups;
85};
86
87int mxs_pinctrl_probe(struct platform_device *pdev,
88 struct mxs_pinctrl_soc_data *soc);
89int mxs_pinctrl_remove(struct platform_device *pdev);
90
91#endif /* __PINCTRL_MXS_H */
diff --git a/drivers/pinctrl/pinctrl-pxa3xx.c b/drivers/pinctrl/pinctrl-pxa3xx.c
index 079dce0e93e..7644e42ac21 100644
--- a/drivers/pinctrl/pinctrl-pxa3xx.c
+++ b/drivers/pinctrl/pinctrl-pxa3xx.c
@@ -25,20 +25,18 @@ static struct pinctrl_gpio_range pxa3xx_pinctrl_gpio_range = {
25 .pin_base = 0, 25 .pin_base = 0,
26}; 26};
27 27
28static int pxa3xx_list_groups(struct pinctrl_dev *pctrldev, unsigned selector) 28static int pxa3xx_get_groups_count(struct pinctrl_dev *pctrldev)
29{ 29{
30 struct pxa3xx_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev); 30 struct pxa3xx_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev);
31 if (selector >= info->num_grps) 31
32 return -EINVAL; 32 return info->num_grps;
33 return 0;
34} 33}
35 34
36static const char *pxa3xx_get_group_name(struct pinctrl_dev *pctrldev, 35static const char *pxa3xx_get_group_name(struct pinctrl_dev *pctrldev,
37 unsigned selector) 36 unsigned selector)
38{ 37{
39 struct pxa3xx_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev); 38 struct pxa3xx_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev);
40 if (selector >= info->num_grps) 39
41 return NULL;
42 return info->grps[selector].name; 40 return info->grps[selector].name;
43} 41}
44 42
@@ -48,25 +46,23 @@ static int pxa3xx_get_group_pins(struct pinctrl_dev *pctrldev,
48 unsigned *num_pins) 46 unsigned *num_pins)
49{ 47{
50 struct pxa3xx_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev); 48 struct pxa3xx_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev);
51 if (selector >= info->num_grps) 49
52 return -EINVAL;
53 *pins = info->grps[selector].pins; 50 *pins = info->grps[selector].pins;
54 *num_pins = info->grps[selector].npins; 51 *num_pins = info->grps[selector].npins;
55 return 0; 52 return 0;
56} 53}
57 54
58static struct pinctrl_ops pxa3xx_pctrl_ops = { 55static struct pinctrl_ops pxa3xx_pctrl_ops = {
59 .list_groups = pxa3xx_list_groups, 56 .get_groups_count = pxa3xx_get_groups_count,
60 .get_group_name = pxa3xx_get_group_name, 57 .get_group_name = pxa3xx_get_group_name,
61 .get_group_pins = pxa3xx_get_group_pins, 58 .get_group_pins = pxa3xx_get_group_pins,
62}; 59};
63 60
64static int pxa3xx_pmx_list_func(struct pinctrl_dev *pctrldev, unsigned func) 61static int pxa3xx_pmx_get_funcs_count(struct pinctrl_dev *pctrldev)
65{ 62{
66 struct pxa3xx_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev); 63 struct pxa3xx_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev);
67 if (func >= info->num_funcs) 64
68 return -EINVAL; 65 return info->num_funcs;
69 return 0;
70} 66}
71 67
72static const char *pxa3xx_pmx_get_func_name(struct pinctrl_dev *pctrldev, 68static const char *pxa3xx_pmx_get_func_name(struct pinctrl_dev *pctrldev,
@@ -170,7 +166,7 @@ static int pxa3xx_pmx_request_gpio(struct pinctrl_dev *pctrldev,
170} 166}
171 167
172static struct pinmux_ops pxa3xx_pmx_ops = { 168static struct pinmux_ops pxa3xx_pmx_ops = {
173 .list_functions = pxa3xx_pmx_list_func, 169 .get_functions_count = pxa3xx_pmx_get_funcs_count,
174 .get_function_name = pxa3xx_pmx_get_func_name, 170 .get_function_name = pxa3xx_pmx_get_func_name,
175 .get_function_groups = pxa3xx_pmx_get_groups, 171 .get_function_groups = pxa3xx_pmx_get_groups,
176 .enable = pxa3xx_pmx_enable, 172 .enable = pxa3xx_pmx_enable,
diff --git a/drivers/pinctrl/pinctrl-sirf.c b/drivers/pinctrl/pinctrl-sirf.c
index 6b3534cc051..ba15b1a29e5 100644
--- a/drivers/pinctrl/pinctrl-sirf.c
+++ b/drivers/pinctrl/pinctrl-sirf.c
@@ -853,18 +853,14 @@ static const struct sirfsoc_pin_group sirfsoc_pin_groups[] = {
853 SIRFSOC_PIN_GROUP("gpsgrp", gps_pins), 853 SIRFSOC_PIN_GROUP("gpsgrp", gps_pins),
854}; 854};
855 855
856static int sirfsoc_list_groups(struct pinctrl_dev *pctldev, unsigned selector) 856static int sirfsoc_get_groups_count(struct pinctrl_dev *pctldev)
857{ 857{
858 if (selector >= ARRAY_SIZE(sirfsoc_pin_groups)) 858 return ARRAY_SIZE(sirfsoc_pin_groups);
859 return -EINVAL;
860 return 0;
861} 859}
862 860
863static const char *sirfsoc_get_group_name(struct pinctrl_dev *pctldev, 861static const char *sirfsoc_get_group_name(struct pinctrl_dev *pctldev,
864 unsigned selector) 862 unsigned selector)
865{ 863{
866 if (selector >= ARRAY_SIZE(sirfsoc_pin_groups))
867 return NULL;
868 return sirfsoc_pin_groups[selector].name; 864 return sirfsoc_pin_groups[selector].name;
869} 865}
870 866
@@ -872,8 +868,6 @@ static int sirfsoc_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector
872 const unsigned **pins, 868 const unsigned **pins,
873 unsigned *num_pins) 869 unsigned *num_pins)
874{ 870{
875 if (selector >= ARRAY_SIZE(sirfsoc_pin_groups))
876 return -EINVAL;
877 *pins = sirfsoc_pin_groups[selector].pins; 871 *pins = sirfsoc_pin_groups[selector].pins;
878 *num_pins = sirfsoc_pin_groups[selector].num_pins; 872 *num_pins = sirfsoc_pin_groups[selector].num_pins;
879 return 0; 873 return 0;
@@ -886,7 +880,7 @@ static void sirfsoc_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s
886} 880}
887 881
888static struct pinctrl_ops sirfsoc_pctrl_ops = { 882static struct pinctrl_ops sirfsoc_pctrl_ops = {
889 .list_groups = sirfsoc_list_groups, 883 .get_groups_count = sirfsoc_get_groups_count,
890 .get_group_name = sirfsoc_get_group_name, 884 .get_group_name = sirfsoc_get_group_name,
891 .get_group_pins = sirfsoc_get_group_pins, 885 .get_group_pins = sirfsoc_get_group_pins,
892 .pin_dbg_show = sirfsoc_pin_dbg_show, 886 .pin_dbg_show = sirfsoc_pin_dbg_show,
@@ -1033,11 +1027,9 @@ static void sirfsoc_pinmux_disable(struct pinctrl_dev *pmxdev, unsigned selector
1033 sirfsoc_pinmux_endisable(spmx, selector, false); 1027 sirfsoc_pinmux_endisable(spmx, selector, false);
1034} 1028}
1035 1029
1036static int sirfsoc_pinmux_list_funcs(struct pinctrl_dev *pmxdev, unsigned selector) 1030static int sirfsoc_pinmux_get_funcs_count(struct pinctrl_dev *pmxdev)
1037{ 1031{
1038 if (selector >= ARRAY_SIZE(sirfsoc_pmx_functions)) 1032 return ARRAY_SIZE(sirfsoc_pmx_functions);
1039 return -EINVAL;
1040 return 0;
1041} 1033}
1042 1034
1043static const char *sirfsoc_pinmux_get_func_name(struct pinctrl_dev *pctldev, 1035static const char *sirfsoc_pinmux_get_func_name(struct pinctrl_dev *pctldev,
@@ -1074,9 +1066,9 @@ static int sirfsoc_pinmux_request_gpio(struct pinctrl_dev *pmxdev,
1074} 1066}
1075 1067
1076static struct pinmux_ops sirfsoc_pinmux_ops = { 1068static struct pinmux_ops sirfsoc_pinmux_ops = {
1077 .list_functions = sirfsoc_pinmux_list_funcs,
1078 .enable = sirfsoc_pinmux_enable, 1069 .enable = sirfsoc_pinmux_enable,
1079 .disable = sirfsoc_pinmux_disable, 1070 .disable = sirfsoc_pinmux_disable,
1071 .get_functions_count = sirfsoc_pinmux_get_funcs_count,
1080 .get_function_name = sirfsoc_pinmux_get_func_name, 1072 .get_function_name = sirfsoc_pinmux_get_func_name,
1081 .get_function_groups = sirfsoc_pinmux_get_groups, 1073 .get_function_groups = sirfsoc_pinmux_get_groups,
1082 .gpio_request_enable = sirfsoc_pinmux_request_gpio, 1074 .gpio_request_enable = sirfsoc_pinmux_request_gpio,
diff --git a/drivers/pinctrl/pinctrl-tegra.c b/drivers/pinctrl/pinctrl-tegra.c
index 9b329688120..2c98fba01ca 100644
--- a/drivers/pinctrl/pinctrl-tegra.c
+++ b/drivers/pinctrl/pinctrl-tegra.c
@@ -23,9 +23,11 @@
23#include <linux/io.h> 23#include <linux/io.h>
24#include <linux/module.h> 24#include <linux/module.h>
25#include <linux/of_device.h> 25#include <linux/of_device.h>
26#include <linux/pinctrl/machine.h>
26#include <linux/pinctrl/pinctrl.h> 27#include <linux/pinctrl/pinctrl.h>
27#include <linux/pinctrl/pinmux.h> 28#include <linux/pinctrl/pinmux.h>
28#include <linux/pinctrl/pinconf.h> 29#include <linux/pinctrl/pinconf.h>
30#include <linux/slab.h>
29 31
30#include <mach/pinconf-tegra.h> 32#include <mach/pinconf-tegra.h>
31 33
@@ -53,15 +55,11 @@ static inline void pmx_writel(struct tegra_pmx *pmx, u32 val, u32 bank, u32 reg)
53 writel(val, pmx->regs[bank] + reg); 55 writel(val, pmx->regs[bank] + reg);
54} 56}
55 57
56static int tegra_pinctrl_list_groups(struct pinctrl_dev *pctldev, 58static int tegra_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
57 unsigned group)
58{ 59{
59 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); 60 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
60 61
61 if (group >= pmx->soc->ngroups) 62 return pmx->soc->ngroups;
62 return -EINVAL;
63
64 return 0;
65} 63}
66 64
67static const char *tegra_pinctrl_get_group_name(struct pinctrl_dev *pctldev, 65static const char *tegra_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
@@ -69,9 +67,6 @@ static const char *tegra_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
69{ 67{
70 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); 68 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
71 69
72 if (group >= pmx->soc->ngroups)
73 return NULL;
74
75 return pmx->soc->groups[group].name; 70 return pmx->soc->groups[group].name;
76} 71}
77 72
@@ -82,9 +77,6 @@ static int tegra_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
82{ 77{
83 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); 78 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
84 79
85 if (group >= pmx->soc->ngroups)
86 return -EINVAL;
87
88 *pins = pmx->soc->groups[group].pins; 80 *pins = pmx->soc->groups[group].pins;
89 *num_pins = pmx->soc->groups[group].npins; 81 *num_pins = pmx->soc->groups[group].npins;
90 82
@@ -98,22 +90,221 @@ static void tegra_pinctrl_pin_dbg_show(struct pinctrl_dev *pctldev,
98 seq_printf(s, " " DRIVER_NAME); 90 seq_printf(s, " " DRIVER_NAME);
99} 91}
100 92
93static int reserve_map(struct pinctrl_map **map, unsigned *reserved_maps,
94 unsigned *num_maps, unsigned reserve)
95{
96 unsigned old_num = *reserved_maps;
97 unsigned new_num = *num_maps + reserve;
98 struct pinctrl_map *new_map;
99
100 if (old_num >= new_num)
101 return 0;
102
103 new_map = krealloc(*map, sizeof(*new_map) * new_num, GFP_KERNEL);
104 if (!new_map)
105 return -ENOMEM;
106
107 memset(new_map + old_num, 0, (new_num - old_num) * sizeof(*new_map));
108
109 *map = new_map;
110 *reserved_maps = new_num;
111
112 return 0;
113}
114
115static int add_map_mux(struct pinctrl_map **map, unsigned *reserved_maps,
116 unsigned *num_maps, const char *group,
117 const char *function)
118{
119 if (*num_maps == *reserved_maps)
120 return -ENOSPC;
121
122 (*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP;
123 (*map)[*num_maps].data.mux.group = group;
124 (*map)[*num_maps].data.mux.function = function;
125 (*num_maps)++;
126
127 return 0;
128}
129
130static int add_map_configs(struct pinctrl_map **map, unsigned *reserved_maps,
131 unsigned *num_maps, const char *group,
132 unsigned long *configs, unsigned num_configs)
133{
134 unsigned long *dup_configs;
135
136 if (*num_maps == *reserved_maps)
137 return -ENOSPC;
138
139 dup_configs = kmemdup(configs, num_configs * sizeof(*dup_configs),
140 GFP_KERNEL);
141 if (!dup_configs)
142 return -ENOMEM;
143
144 (*map)[*num_maps].type = PIN_MAP_TYPE_CONFIGS_GROUP;
145 (*map)[*num_maps].data.configs.group_or_pin = group;
146 (*map)[*num_maps].data.configs.configs = dup_configs;
147 (*map)[*num_maps].data.configs.num_configs = num_configs;
148 (*num_maps)++;
149
150 return 0;
151}
152
153static int add_config(unsigned long **configs, unsigned *num_configs,
154 unsigned long config)
155{
156 unsigned old_num = *num_configs;
157 unsigned new_num = old_num + 1;
158 unsigned long *new_configs;
159
160 new_configs = krealloc(*configs, sizeof(*new_configs) * new_num,
161 GFP_KERNEL);
162 if (!new_configs)
163 return -ENOMEM;
164
165 new_configs[old_num] = config;
166
167 *configs = new_configs;
168 *num_configs = new_num;
169
170 return 0;
171}
172
173void tegra_pinctrl_dt_free_map(struct pinctrl_dev *pctldev,
174 struct pinctrl_map *map, unsigned num_maps)
175{
176 int i;
177
178 for (i = 0; i < num_maps; i++)
179 if (map[i].type == PIN_MAP_TYPE_CONFIGS_GROUP)
180 kfree(map[i].data.configs.configs);
181
182 kfree(map);
183}
184
185static const struct cfg_param {
186 const char *property;
187 enum tegra_pinconf_param param;
188} cfg_params[] = {
189 {"nvidia,pull", TEGRA_PINCONF_PARAM_PULL},
190 {"nvidia,tristate", TEGRA_PINCONF_PARAM_TRISTATE},
191 {"nvidia,enable-input", TEGRA_PINCONF_PARAM_ENABLE_INPUT},
192 {"nvidia,open-drain", TEGRA_PINCONF_PARAM_OPEN_DRAIN},
193 {"nvidia,lock", TEGRA_PINCONF_PARAM_LOCK},
194 {"nvidia,io-reset", TEGRA_PINCONF_PARAM_IORESET},
195 {"nvidia,high-speed-mode", TEGRA_PINCONF_PARAM_HIGH_SPEED_MODE},
196 {"nvidia,schmitt", TEGRA_PINCONF_PARAM_SCHMITT},
197 {"nvidia,low-power-mode", TEGRA_PINCONF_PARAM_LOW_POWER_MODE},
198 {"nvidia,pull-down-strength", TEGRA_PINCONF_PARAM_DRIVE_DOWN_STRENGTH},
199 {"nvidia,pull-up-strength", TEGRA_PINCONF_PARAM_DRIVE_UP_STRENGTH},
200 {"nvidia,slew-rate-falling", TEGRA_PINCONF_PARAM_SLEW_RATE_FALLING},
201 {"nvidia,slew-rate-rising", TEGRA_PINCONF_PARAM_SLEW_RATE_RISING},
202};
203
204int tegra_pinctrl_dt_subnode_to_map(struct device_node *np,
205 struct pinctrl_map **map,
206 unsigned *reserved_maps,
207 unsigned *num_maps)
208{
209 int ret, i;
210 const char *function;
211 u32 val;
212 unsigned long config;
213 unsigned long *configs = NULL;
214 unsigned num_configs = 0;
215 unsigned reserve;
216 struct property *prop;
217 const char *group;
218
219 ret = of_property_read_string(np, "nvidia,function", &function);
220 if (ret < 0)
221 function = NULL;
222
223 for (i = 0; i < ARRAY_SIZE(cfg_params); i++) {
224 ret = of_property_read_u32(np, cfg_params[i].property, &val);
225 if (!ret) {
226 config = TEGRA_PINCONF_PACK(cfg_params[i].param, val);
227 ret = add_config(&configs, &num_configs, config);
228 if (ret < 0)
229 goto exit;
230 }
231 }
232
233 reserve = 0;
234 if (function != NULL)
235 reserve++;
236 if (num_configs)
237 reserve++;
238 ret = of_property_count_strings(np, "nvidia,pins");
239 if (ret < 0)
240 goto exit;
241 reserve *= ret;
242
243 ret = reserve_map(map, reserved_maps, num_maps, reserve);
244 if (ret < 0)
245 goto exit;
246
247 of_property_for_each_string(np, "nvidia,pins", prop, group) {
248 if (function) {
249 ret = add_map_mux(map, reserved_maps, num_maps,
250 group, function);
251 if (ret < 0)
252 goto exit;
253 }
254
255 if (num_configs) {
256 ret = add_map_configs(map, reserved_maps, num_maps,
257 group, configs, num_configs);
258 if (ret < 0)
259 goto exit;
260 }
261 }
262
263 ret = 0;
264
265exit:
266 kfree(configs);
267 return ret;
268}
269
270int tegra_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
271 struct device_node *np_config,
272 struct pinctrl_map **map, unsigned *num_maps)
273{
274 unsigned reserved_maps;
275 struct device_node *np;
276 int ret;
277
278 reserved_maps = 0;
279 *map = NULL;
280 *num_maps = 0;
281
282 for_each_child_of_node(np_config, np) {
283 ret = tegra_pinctrl_dt_subnode_to_map(np, map, &reserved_maps,
284 num_maps);
285 if (ret < 0) {
286 tegra_pinctrl_dt_free_map(pctldev, *map, *num_maps);
287 return ret;
288 }
289 }
290
291 return 0;
292}
293
101static struct pinctrl_ops tegra_pinctrl_ops = { 294static struct pinctrl_ops tegra_pinctrl_ops = {
102 .list_groups = tegra_pinctrl_list_groups, 295 .get_groups_count = tegra_pinctrl_get_groups_count,
103 .get_group_name = tegra_pinctrl_get_group_name, 296 .get_group_name = tegra_pinctrl_get_group_name,
104 .get_group_pins = tegra_pinctrl_get_group_pins, 297 .get_group_pins = tegra_pinctrl_get_group_pins,
105 .pin_dbg_show = tegra_pinctrl_pin_dbg_show, 298 .pin_dbg_show = tegra_pinctrl_pin_dbg_show,
299 .dt_node_to_map = tegra_pinctrl_dt_node_to_map,
300 .dt_free_map = tegra_pinctrl_dt_free_map,
106}; 301};
107 302
108static int tegra_pinctrl_list_funcs(struct pinctrl_dev *pctldev, 303static int tegra_pinctrl_get_funcs_count(struct pinctrl_dev *pctldev)
109 unsigned function)
110{ 304{
111 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); 305 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
112 306
113 if (function >= pmx->soc->nfunctions) 307 return pmx->soc->nfunctions;
114 return -EINVAL;
115
116 return 0;
117} 308}
118 309
119static const char *tegra_pinctrl_get_func_name(struct pinctrl_dev *pctldev, 310static const char *tegra_pinctrl_get_func_name(struct pinctrl_dev *pctldev,
@@ -121,9 +312,6 @@ static const char *tegra_pinctrl_get_func_name(struct pinctrl_dev *pctldev,
121{ 312{
122 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); 313 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
123 314
124 if (function >= pmx->soc->nfunctions)
125 return NULL;
126
127 return pmx->soc->functions[function].name; 315 return pmx->soc->functions[function].name;
128} 316}
129 317
@@ -134,9 +322,6 @@ static int tegra_pinctrl_get_func_groups(struct pinctrl_dev *pctldev,
134{ 322{
135 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); 323 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
136 324
137 if (function >= pmx->soc->nfunctions)
138 return -EINVAL;
139
140 *groups = pmx->soc->functions[function].groups; 325 *groups = pmx->soc->functions[function].groups;
141 *num_groups = pmx->soc->functions[function].ngroups; 326 *num_groups = pmx->soc->functions[function].ngroups;
142 327
@@ -151,8 +336,6 @@ static int tegra_pinctrl_enable(struct pinctrl_dev *pctldev, unsigned function,
151 int i; 336 int i;
152 u32 val; 337 u32 val;
153 338
154 if (group >= pmx->soc->ngroups)
155 return -EINVAL;
156 g = &pmx->soc->groups[group]; 339 g = &pmx->soc->groups[group];
157 340
158 if (g->mux_reg < 0) 341 if (g->mux_reg < 0)
@@ -180,8 +363,6 @@ static void tegra_pinctrl_disable(struct pinctrl_dev *pctldev,
180 const struct tegra_pingroup *g; 363 const struct tegra_pingroup *g;
181 u32 val; 364 u32 val;
182 365
183 if (group >= pmx->soc->ngroups)
184 return;
185 g = &pmx->soc->groups[group]; 366 g = &pmx->soc->groups[group];
186 367
187 if (g->mux_reg < 0) 368 if (g->mux_reg < 0)
@@ -194,7 +375,7 @@ static void tegra_pinctrl_disable(struct pinctrl_dev *pctldev,
194} 375}
195 376
196static struct pinmux_ops tegra_pinmux_ops = { 377static struct pinmux_ops tegra_pinmux_ops = {
197 .list_functions = tegra_pinctrl_list_funcs, 378 .get_functions_count = tegra_pinctrl_get_funcs_count,
198 .get_function_name = tegra_pinctrl_get_func_name, 379 .get_function_name = tegra_pinctrl_get_func_name,
199 .get_function_groups = tegra_pinctrl_get_func_groups, 380 .get_function_groups = tegra_pinctrl_get_func_groups,
200 .enable = tegra_pinctrl_enable, 381 .enable = tegra_pinctrl_enable,
@@ -324,8 +505,6 @@ static int tegra_pinconf_group_get(struct pinctrl_dev *pctldev,
324 s16 reg; 505 s16 reg;
325 u32 val, mask; 506 u32 val, mask;
326 507
327 if (group >= pmx->soc->ngroups)
328 return -EINVAL;
329 g = &pmx->soc->groups[group]; 508 g = &pmx->soc->groups[group];
330 509
331 ret = tegra_pinconf_reg(pmx, g, param, &bank, &reg, &bit, &width); 510 ret = tegra_pinconf_reg(pmx, g, param, &bank, &reg, &bit, &width);
@@ -353,8 +532,6 @@ static int tegra_pinconf_group_set(struct pinctrl_dev *pctldev,
353 s16 reg; 532 s16 reg;
354 u32 val, mask; 533 u32 val, mask;
355 534
356 if (group >= pmx->soc->ngroups)
357 return -EINVAL;
358 g = &pmx->soc->groups[group]; 535 g = &pmx->soc->groups[group];
359 536
360 ret = tegra_pinconf_reg(pmx, g, param, &bank, &reg, &bit, &width); 537 ret = tegra_pinconf_reg(pmx, g, param, &bank, &reg, &bit, &width);
diff --git a/drivers/pinctrl/pinctrl-u300.c b/drivers/pinctrl/pinctrl-u300.c
index 26eb8ccd72d..05d029911be 100644
--- a/drivers/pinctrl/pinctrl-u300.c
+++ b/drivers/pinctrl/pinctrl-u300.c
@@ -836,18 +836,14 @@ static const struct u300_pin_group u300_pin_groups[] = {
836 }, 836 },
837}; 837};
838 838
839static int u300_list_groups(struct pinctrl_dev *pctldev, unsigned selector) 839static int u300_get_groups_count(struct pinctrl_dev *pctldev)
840{ 840{
841 if (selector >= ARRAY_SIZE(u300_pin_groups)) 841 return ARRAY_SIZE(u300_pin_groups);
842 return -EINVAL;
843 return 0;
844} 842}
845 843
846static const char *u300_get_group_name(struct pinctrl_dev *pctldev, 844static const char *u300_get_group_name(struct pinctrl_dev *pctldev,
847 unsigned selector) 845 unsigned selector)
848{ 846{
849 if (selector >= ARRAY_SIZE(u300_pin_groups))
850 return NULL;
851 return u300_pin_groups[selector].name; 847 return u300_pin_groups[selector].name;
852} 848}
853 849
@@ -855,8 +851,6 @@ static int u300_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
855 const unsigned **pins, 851 const unsigned **pins,
856 unsigned *num_pins) 852 unsigned *num_pins)
857{ 853{
858 if (selector >= ARRAY_SIZE(u300_pin_groups))
859 return -EINVAL;
860 *pins = u300_pin_groups[selector].pins; 854 *pins = u300_pin_groups[selector].pins;
861 *num_pins = u300_pin_groups[selector].num_pins; 855 *num_pins = u300_pin_groups[selector].num_pins;
862 return 0; 856 return 0;
@@ -869,7 +863,7 @@ static void u300_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
869} 863}
870 864
871static struct pinctrl_ops u300_pctrl_ops = { 865static struct pinctrl_ops u300_pctrl_ops = {
872 .list_groups = u300_list_groups, 866 .get_groups_count = u300_get_groups_count,
873 .get_group_name = u300_get_group_name, 867 .get_group_name = u300_get_group_name,
874 .get_group_pins = u300_get_group_pins, 868 .get_group_pins = u300_get_group_pins,
875 .pin_dbg_show = u300_pin_dbg_show, 869 .pin_dbg_show = u300_pin_dbg_show,
@@ -991,11 +985,9 @@ static void u300_pmx_disable(struct pinctrl_dev *pctldev, unsigned selector,
991 u300_pmx_endisable(upmx, selector, false); 985 u300_pmx_endisable(upmx, selector, false);
992} 986}
993 987
994static int u300_pmx_list_funcs(struct pinctrl_dev *pctldev, unsigned selector) 988static int u300_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
995{ 989{
996 if (selector >= ARRAY_SIZE(u300_pmx_functions)) 990 return ARRAY_SIZE(u300_pmx_functions);
997 return -EINVAL;
998 return 0;
999} 991}
1000 992
1001static const char *u300_pmx_get_func_name(struct pinctrl_dev *pctldev, 993static const char *u300_pmx_get_func_name(struct pinctrl_dev *pctldev,
@@ -1014,7 +1006,7 @@ static int u300_pmx_get_groups(struct pinctrl_dev *pctldev, unsigned selector,
1014} 1006}
1015 1007
1016static struct pinmux_ops u300_pmx_ops = { 1008static struct pinmux_ops u300_pmx_ops = {
1017 .list_functions = u300_pmx_list_funcs, 1009 .get_functions_count = u300_pmx_get_funcs_count,
1018 .get_function_name = u300_pmx_get_func_name, 1010 .get_function_name = u300_pmx_get_func_name,
1019 .get_function_groups = u300_pmx_get_groups, 1011 .get_function_groups = u300_pmx_get_groups,
1020 .enable = u300_pmx_enable, 1012 .enable = u300_pmx_enable,
diff --git a/drivers/pinctrl/pinmux.c b/drivers/pinctrl/pinmux.c
index 4e62783a573..220fa492c9f 100644
--- a/drivers/pinctrl/pinmux.c
+++ b/drivers/pinctrl/pinmux.c
@@ -33,22 +33,26 @@
33int pinmux_check_ops(struct pinctrl_dev *pctldev) 33int pinmux_check_ops(struct pinctrl_dev *pctldev)
34{ 34{
35 const struct pinmux_ops *ops = pctldev->desc->pmxops; 35 const struct pinmux_ops *ops = pctldev->desc->pmxops;
36 unsigned nfuncs;
36 unsigned selector = 0; 37 unsigned selector = 0;
37 38
38 /* Check that we implement required operations */ 39 /* Check that we implement required operations */
39 if (!ops->list_functions || 40 if (!ops ||
41 !ops->get_functions_count ||
40 !ops->get_function_name || 42 !ops->get_function_name ||
41 !ops->get_function_groups || 43 !ops->get_function_groups ||
42 !ops->enable || 44 !ops->enable ||
43 !ops->disable) 45 !ops->disable) {
46 dev_err(pctldev->dev, "pinmux ops lacks necessary functions\n");
44 return -EINVAL; 47 return -EINVAL;
45 48 }
46 /* Check that all functions registered have names */ 49 /* Check that all functions registered have names */
47 while (ops->list_functions(pctldev, selector) >= 0) { 50 nfuncs = ops->get_functions_count(pctldev);
51 while (selector < nfuncs) {
48 const char *fname = ops->get_function_name(pctldev, 52 const char *fname = ops->get_function_name(pctldev,
49 selector); 53 selector);
50 if (!fname) { 54 if (!fname) {
51 pr_err("pinmux ops has no name for function%u\n", 55 dev_err(pctldev->dev, "pinmux ops has no name for function%u\n",
52 selector); 56 selector);
53 return -EINVAL; 57 return -EINVAL;
54 } 58 }
@@ -85,20 +89,23 @@ static int pin_request(struct pinctrl_dev *pctldev,
85 const struct pinmux_ops *ops = pctldev->desc->pmxops; 89 const struct pinmux_ops *ops = pctldev->desc->pmxops;
86 int status = -EINVAL; 90 int status = -EINVAL;
87 91
88 dev_dbg(pctldev->dev, "request pin %d for %s\n", pin, owner);
89
90 desc = pin_desc_get(pctldev, pin); 92 desc = pin_desc_get(pctldev, pin);
91 if (desc == NULL) { 93 if (desc == NULL) {
92 dev_err(pctldev->dev, 94 dev_err(pctldev->dev,
93 "pin is not registered so it cannot be requested\n"); 95 "pin %d is not registered so it cannot be requested\n",
96 pin);
94 goto out; 97 goto out;
95 } 98 }
96 99
100 dev_dbg(pctldev->dev, "request pin %d (%s) for %s\n",
101 pin, desc->name, owner);
102
97 if (gpio_range) { 103 if (gpio_range) {
98 /* There's no need to support multiple GPIO requests */ 104 /* There's no need to support multiple GPIO requests */
99 if (desc->gpio_owner) { 105 if (desc->gpio_owner) {
100 dev_err(pctldev->dev, 106 dev_err(pctldev->dev,
101 "pin already requested\n"); 107 "pin %s already requested by %s; cannot claim for %s\n",
108 desc->name, desc->gpio_owner, owner);
102 goto out; 109 goto out;
103 } 110 }
104 111
@@ -106,7 +113,8 @@ static int pin_request(struct pinctrl_dev *pctldev,
106 } else { 113 } else {
107 if (desc->mux_usecount && strcmp(desc->mux_owner, owner)) { 114 if (desc->mux_usecount && strcmp(desc->mux_owner, owner)) {
108 dev_err(pctldev->dev, 115 dev_err(pctldev->dev,
109 "pin already requested\n"); 116 "pin %s already requested by %s; cannot claim for %s\n",
117 desc->name, desc->mux_owner, owner);
110 goto out; 118 goto out;
111 } 119 }
112 120
@@ -139,8 +147,7 @@ static int pin_request(struct pinctrl_dev *pctldev,
139 status = 0; 147 status = 0;
140 148
141 if (status) { 149 if (status) {
142 dev_err(pctldev->dev, "->request on device %s failed for pin %d\n", 150 dev_err(pctldev->dev, "request() failed for pin %d\n", pin);
143 pctldev->desc->name, pin);
144 module_put(pctldev->owner); 151 module_put(pctldev->owner);
145 } 152 }
146 153
@@ -157,7 +164,7 @@ out_free_pin:
157out: 164out:
158 if (status) 165 if (status)
159 dev_err(pctldev->dev, "pin-%d (%s) status %d\n", 166 dev_err(pctldev->dev, "pin-%d (%s) status %d\n",
160 pin, owner, status); 167 pin, owner, status);
161 168
162 return status; 169 return status;
163} 170}
@@ -287,10 +294,11 @@ static int pinmux_func_name_to_selector(struct pinctrl_dev *pctldev,
287 const char *function) 294 const char *function)
288{ 295{
289 const struct pinmux_ops *ops = pctldev->desc->pmxops; 296 const struct pinmux_ops *ops = pctldev->desc->pmxops;
297 unsigned nfuncs = ops->get_functions_count(pctldev);
290 unsigned selector = 0; 298 unsigned selector = 0;
291 299
292 /* See if this pctldev has this function */ 300 /* See if this pctldev has this function */
293 while (ops->list_functions(pctldev, selector) >= 0) { 301 while (selector < nfuncs) {
294 const char *fname = ops->get_function_name(pctldev, 302 const char *fname = ops->get_function_name(pctldev,
295 selector); 303 selector);
296 304
@@ -319,18 +327,32 @@ int pinmux_map_to_setting(struct pinctrl_map const *map,
319 const unsigned *pins; 327 const unsigned *pins;
320 unsigned num_pins; 328 unsigned num_pins;
321 329
322 setting->data.mux.func = 330 if (!pmxops) {
323 pinmux_func_name_to_selector(pctldev, map->data.mux.function); 331 dev_err(pctldev->dev, "does not support mux function\n");
324 if (setting->data.mux.func < 0) 332 return -EINVAL;
325 return setting->data.mux.func; 333 }
334
335 ret = pinmux_func_name_to_selector(pctldev, map->data.mux.function);
336 if (ret < 0) {
337 dev_err(pctldev->dev, "invalid function %s in map table\n",
338 map->data.mux.function);
339 return ret;
340 }
341 setting->data.mux.func = ret;
326 342
327 ret = pmxops->get_function_groups(pctldev, setting->data.mux.func, 343 ret = pmxops->get_function_groups(pctldev, setting->data.mux.func,
328 &groups, &num_groups); 344 &groups, &num_groups);
329 if (ret < 0) 345 if (ret < 0) {
346 dev_err(pctldev->dev, "can't query groups for function %s\n",
347 map->data.mux.function);
330 return ret; 348 return ret;
331 if (!num_groups) 349 }
350 if (!num_groups) {
351 dev_err(pctldev->dev,
352 "function %s can't be selected on any group\n",
353 map->data.mux.function);
332 return -EINVAL; 354 return -EINVAL;
333 355 }
334 if (map->data.mux.group) { 356 if (map->data.mux.group) {
335 bool found = false; 357 bool found = false;
336 group = map->data.mux.group; 358 group = map->data.mux.group;
@@ -340,15 +362,23 @@ int pinmux_map_to_setting(struct pinctrl_map const *map,
340 break; 362 break;
341 } 363 }
342 } 364 }
343 if (!found) 365 if (!found) {
366 dev_err(pctldev->dev,
367 "invalid group \"%s\" for function \"%s\"\n",
368 group, map->data.mux.function);
344 return -EINVAL; 369 return -EINVAL;
370 }
345 } else { 371 } else {
346 group = groups[0]; 372 group = groups[0];
347 } 373 }
348 374
349 setting->data.mux.group = pinctrl_get_group_selector(pctldev, group); 375 ret = pinctrl_get_group_selector(pctldev, group);
350 if (setting->data.mux.group < 0) 376 if (ret < 0) {
351 return setting->data.mux.group; 377 dev_err(pctldev->dev, "invalid group %s in map table\n",
378 map->data.mux.group);
379 return ret;
380 }
381 setting->data.mux.group = ret;
352 382
353 ret = pctlops->get_group_pins(pctldev, setting->data.mux.group, &pins, 383 ret = pctlops->get_group_pins(pctldev, setting->data.mux.group, &pins,
354 &num_pins); 384 &num_pins);
@@ -364,7 +394,7 @@ int pinmux_map_to_setting(struct pinctrl_map const *map,
364 ret = pin_request(pctldev, pins[i], map->dev_name, NULL); 394 ret = pin_request(pctldev, pins[i], map->dev_name, NULL);
365 if (ret) { 395 if (ret) {
366 dev_err(pctldev->dev, 396 dev_err(pctldev->dev,
367 "could not get request pin %d on device %s\n", 397 "could not request pin %d on device %s\n",
368 pins[i], pinctrl_dev_get_name(pctldev)); 398 pins[i], pinctrl_dev_get_name(pctldev));
369 /* On error release all taken pins */ 399 /* On error release all taken pins */
370 i--; /* this pin just failed */ 400 i--; /* this pin just failed */
@@ -477,11 +507,15 @@ static int pinmux_functions_show(struct seq_file *s, void *what)
477{ 507{
478 struct pinctrl_dev *pctldev = s->private; 508 struct pinctrl_dev *pctldev = s->private;
479 const struct pinmux_ops *pmxops = pctldev->desc->pmxops; 509 const struct pinmux_ops *pmxops = pctldev->desc->pmxops;
510 unsigned nfuncs;
480 unsigned func_selector = 0; 511 unsigned func_selector = 0;
481 512
482 mutex_lock(&pinctrl_mutex); 513 if (!pmxops)
514 return 0;
483 515
484 while (pmxops->list_functions(pctldev, func_selector) >= 0) { 516 mutex_lock(&pinctrl_mutex);
517 nfuncs = pmxops->get_functions_count(pctldev);
518 while (func_selector < nfuncs) {
485 const char *func = pmxops->get_function_name(pctldev, 519 const char *func = pmxops->get_function_name(pctldev,
486 func_selector); 520 func_selector);
487 const char * const *groups; 521 const char * const *groups;
@@ -515,6 +549,9 @@ static int pinmux_pins_show(struct seq_file *s, void *what)
515 const struct pinmux_ops *pmxops = pctldev->desc->pmxops; 549 const struct pinmux_ops *pmxops = pctldev->desc->pmxops;
516 unsigned i, pin; 550 unsigned i, pin;
517 551
552 if (!pmxops)
553 return 0;
554
518 seq_puts(s, "Pinmux settings per pin\n"); 555 seq_puts(s, "Pinmux settings per pin\n");
519 seq_puts(s, "Format: pin (name): mux_owner gpio_owner hog?\n"); 556 seq_puts(s, "Format: pin (name): mux_owner gpio_owner hog?\n");
520 557
diff --git a/drivers/pinctrl/pinmux.h b/drivers/pinctrl/pinmux.h
index 6fc47003e95..d1a98b1c9fc 100644
--- a/drivers/pinctrl/pinmux.h
+++ b/drivers/pinctrl/pinmux.h
@@ -31,12 +31,6 @@ void pinmux_free_setting(struct pinctrl_setting const *setting);
31int pinmux_enable_setting(struct pinctrl_setting const *setting); 31int pinmux_enable_setting(struct pinctrl_setting const *setting);
32void pinmux_disable_setting(struct pinctrl_setting const *setting); 32void pinmux_disable_setting(struct pinctrl_setting const *setting);
33 33
34void pinmux_show_map(struct seq_file *s, struct pinctrl_map const *map);
35void pinmux_show_setting(struct seq_file *s,
36 struct pinctrl_setting const *setting);
37void pinmux_init_device_debugfs(struct dentry *devroot,
38 struct pinctrl_dev *pctldev);
39
40#else 34#else
41 35
42static inline int pinmux_check_ops(struct pinctrl_dev *pctldev) 36static inline int pinmux_check_ops(struct pinctrl_dev *pctldev)
@@ -89,6 +83,18 @@ static inline void pinmux_disable_setting(
89{ 83{
90} 84}
91 85
86#endif
87
88#if defined(CONFIG_PINMUX) && defined(CONFIG_DEBUG_FS)
89
90void pinmux_show_map(struct seq_file *s, struct pinctrl_map const *map);
91void pinmux_show_setting(struct seq_file *s,
92 struct pinctrl_setting const *setting);
93void pinmux_init_device_debugfs(struct dentry *devroot,
94 struct pinctrl_dev *pctldev);
95
96#else
97
92static inline void pinmux_show_map(struct seq_file *s, 98static inline void pinmux_show_map(struct seq_file *s,
93 struct pinctrl_map const *map) 99 struct pinctrl_map const *map)
94{ 100{
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-07 22:46:20 -0500