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path: root/drivers/pci/quirks.c
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Diffstat (limited to 'drivers/pci/quirks.c')
-rw-r--r--drivers/pci/quirks.c31
1 files changed, 30 insertions, 1 deletions
diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
index f20d55368ed..92b9efe9bca 100644
--- a/drivers/pci/quirks.c
+++ b/drivers/pci/quirks.c
@@ -23,6 +23,7 @@
23#include <linux/acpi.h> 23#include <linux/acpi.h>
24#include <linux/kallsyms.h> 24#include <linux/kallsyms.h>
25#include <linux/dmi.h> 25#include <linux/dmi.h>
26#include <linux/pci-aspm.h>
26#include "pci.h" 27#include "pci.h"
27 28
28int isa_dma_bridge_buggy; 29int isa_dma_bridge_buggy;
@@ -1749,6 +1750,30 @@ static void __devinit quirk_e100_interrupt(struct pci_dev *dev)
1749} 1750}
1750DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, quirk_e100_interrupt); 1751DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, quirk_e100_interrupt);
1751 1752
1753/*
1754 * The 82575 and 82598 may experience data corruption issues when transitioning
1755 * out of L0S. To prevent this we need to disable L0S on the pci-e link
1756 */
1757static void __devinit quirk_disable_aspm_l0s(struct pci_dev *dev)
1758{
1759 dev_info(&dev->dev, "Disabling L0s\n");
1760 pci_disable_link_state(dev, PCIE_LINK_STATE_L0S);
1761}
1762DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a7, quirk_disable_aspm_l0s);
1763DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a9, quirk_disable_aspm_l0s);
1764DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10b6, quirk_disable_aspm_l0s);
1765DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c6, quirk_disable_aspm_l0s);
1766DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c7, quirk_disable_aspm_l0s);
1767DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c8, quirk_disable_aspm_l0s);
1768DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10d6, quirk_disable_aspm_l0s);
1769DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10db, quirk_disable_aspm_l0s);
1770DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10dd, quirk_disable_aspm_l0s);
1771DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10e1, quirk_disable_aspm_l0s);
1772DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10ec, quirk_disable_aspm_l0s);
1773DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f1, quirk_disable_aspm_l0s);
1774DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f4, quirk_disable_aspm_l0s);
1775DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1508, quirk_disable_aspm_l0s);
1776
1752static void __devinit fixup_rev1_53c810(struct pci_dev* dev) 1777static void __devinit fixup_rev1_53c810(struct pci_dev* dev)
1753{ 1778{
1754 /* rev 1 ncr53c810 chips don't set the class at all which means 1779 /* rev 1 ncr53c810 chips don't set the class at all which means
@@ -2097,7 +2122,7 @@ static void __devinit ht_disable_msi_mapping(struct pci_dev *dev)
2097 2122
2098 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS, 2123 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2099 &flags) == 0) { 2124 &flags) == 0) {
2100 dev_info(&dev->dev, "Enabling HT MSI Mapping\n"); 2125 dev_info(&dev->dev, "Disabling HT MSI Mapping\n");
2101 2126
2102 pci_write_config_byte(dev, pos + HT_MSI_FLAGS, 2127 pci_write_config_byte(dev, pos + HT_MSI_FLAGS,
2103 flags & ~HT_MSI_FLAGS_ENABLE); 2128 flags & ~HT_MSI_FLAGS_ENABLE);
@@ -2141,6 +2166,10 @@ static void __devinit nv_msi_ht_cap_quirk(struct pci_dev *dev)
2141 int pos; 2166 int pos;
2142 int found; 2167 int found;
2143 2168
2169 /* Enabling HT MSI mapping on this device breaks MCP51 */
2170 if (dev->device == 0x270)
2171 return;
2172
2144 /* check if there is HT MSI cap or enabled on this device */ 2173 /* check if there is HT MSI cap or enabled on this device */
2145 found = ht_check_msi_mapping(dev); 2174 found = ht_check_msi_mapping(dev);
2146 2175