diff options
Diffstat (limited to 'drivers/pci/pcie/aer/aerdrv_core.c')
-rw-r--r-- | drivers/pci/pcie/aer/aerdrv_core.c | 47 |
1 files changed, 10 insertions, 37 deletions
diff --git a/drivers/pci/pcie/aer/aerdrv_core.c b/drivers/pci/pcie/aer/aerdrv_core.c index ee5e7b5176d..dfc63d01f20 100644 --- a/drivers/pci/pcie/aer/aerdrv_core.c +++ b/drivers/pci/pcie/aer/aerdrv_core.c | |||
@@ -28,41 +28,15 @@ | |||
28 | static int forceload; | 28 | static int forceload; |
29 | module_param(forceload, bool, 0); | 29 | module_param(forceload, bool, 0); |
30 | 30 | ||
31 | #define PCI_CFG_SPACE_SIZE (0x100) | ||
32 | int pci_find_aer_capability(struct pci_dev *dev) | ||
33 | { | ||
34 | int pos; | ||
35 | u32 reg32 = 0; | ||
36 | |||
37 | /* Check if it's a pci-express device */ | ||
38 | pos = pci_find_capability(dev, PCI_CAP_ID_EXP); | ||
39 | if (!pos) | ||
40 | return 0; | ||
41 | |||
42 | /* Check if it supports pci-express AER */ | ||
43 | pos = PCI_CFG_SPACE_SIZE; | ||
44 | while (pos) { | ||
45 | if (pci_read_config_dword(dev, pos, ®32)) | ||
46 | return 0; | ||
47 | |||
48 | /* some broken boards return ~0 */ | ||
49 | if (reg32 == 0xffffffff) | ||
50 | return 0; | ||
51 | |||
52 | if (PCI_EXT_CAP_ID(reg32) == PCI_EXT_CAP_ID_ERR) | ||
53 | break; | ||
54 | |||
55 | pos = reg32 >> 20; | ||
56 | } | ||
57 | |||
58 | return pos; | ||
59 | } | ||
60 | |||
61 | int pci_enable_pcie_error_reporting(struct pci_dev *dev) | 31 | int pci_enable_pcie_error_reporting(struct pci_dev *dev) |
62 | { | 32 | { |
63 | u16 reg16 = 0; | 33 | u16 reg16 = 0; |
64 | int pos; | 34 | int pos; |
65 | 35 | ||
36 | pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR); | ||
37 | if (!pos) | ||
38 | return -EIO; | ||
39 | |||
66 | pos = pci_find_capability(dev, PCI_CAP_ID_EXP); | 40 | pos = pci_find_capability(dev, PCI_CAP_ID_EXP); |
67 | if (!pos) | 41 | if (!pos) |
68 | return -EIO; | 42 | return -EIO; |
@@ -102,7 +76,7 @@ int pci_cleanup_aer_uncorrect_error_status(struct pci_dev *dev) | |||
102 | int pos; | 76 | int pos; |
103 | u32 status, mask; | 77 | u32 status, mask; |
104 | 78 | ||
105 | pos = pci_find_aer_capability(dev); | 79 | pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR); |
106 | if (!pos) | 80 | if (!pos) |
107 | return -EIO; | 81 | return -EIO; |
108 | 82 | ||
@@ -123,7 +97,7 @@ int pci_cleanup_aer_correct_error_status(struct pci_dev *dev) | |||
123 | int pos; | 97 | int pos; |
124 | u32 status; | 98 | u32 status; |
125 | 99 | ||
126 | pos = pci_find_aer_capability(dev); | 100 | pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR); |
127 | if (!pos) | 101 | if (!pos) |
128 | return -EIO; | 102 | return -EIO; |
129 | 103 | ||
@@ -502,7 +476,7 @@ static void handle_error_source(struct pcie_device * aerdev, | |||
502 | * Correctable error does not need software intevention. | 476 | * Correctable error does not need software intevention. |
503 | * No need to go through error recovery process. | 477 | * No need to go through error recovery process. |
504 | */ | 478 | */ |
505 | pos = pci_find_aer_capability(dev); | 479 | pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR); |
506 | if (pos) | 480 | if (pos) |
507 | pci_write_config_dword(dev, pos + PCI_ERR_COR_STATUS, | 481 | pci_write_config_dword(dev, pos + PCI_ERR_COR_STATUS, |
508 | info.status); | 482 | info.status); |
@@ -542,7 +516,7 @@ void aer_enable_rootport(struct aer_rpc *rpc) | |||
542 | reg16 &= ~(SYSTEM_ERROR_INTR_ON_MESG_MASK); | 516 | reg16 &= ~(SYSTEM_ERROR_INTR_ON_MESG_MASK); |
543 | pci_write_config_word(pdev, pos + PCI_EXP_RTCTL, reg16); | 517 | pci_write_config_word(pdev, pos + PCI_EXP_RTCTL, reg16); |
544 | 518 | ||
545 | aer_pos = pci_find_aer_capability(pdev); | 519 | aer_pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ERR); |
546 | /* Clear error status */ | 520 | /* Clear error status */ |
547 | pci_read_config_dword(pdev, aer_pos + PCI_ERR_ROOT_STATUS, ®32); | 521 | pci_read_config_dword(pdev, aer_pos + PCI_ERR_ROOT_STATUS, ®32); |
548 | pci_write_config_dword(pdev, aer_pos + PCI_ERR_ROOT_STATUS, reg32); | 522 | pci_write_config_dword(pdev, aer_pos + PCI_ERR_ROOT_STATUS, reg32); |
@@ -579,7 +553,7 @@ static void disable_root_aer(struct aer_rpc *rpc) | |||
579 | u32 reg32; | 553 | u32 reg32; |
580 | int pos; | 554 | int pos; |
581 | 555 | ||
582 | pos = pci_find_aer_capability(pdev); | 556 | pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ERR); |
583 | /* Disable Root's interrupt in response to error messages */ | 557 | /* Disable Root's interrupt in response to error messages */ |
584 | pci_write_config_dword(pdev, pos + PCI_ERR_ROOT_COMMAND, 0); | 558 | pci_write_config_dword(pdev, pos + PCI_ERR_ROOT_COMMAND, 0); |
585 | 559 | ||
@@ -618,7 +592,7 @@ static int get_device_error_info(struct pci_dev *dev, struct aer_err_info *info) | |||
618 | { | 592 | { |
619 | int pos; | 593 | int pos; |
620 | 594 | ||
621 | pos = pci_find_aer_capability(dev); | 595 | pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR); |
622 | 596 | ||
623 | /* The device might not support AER */ | 597 | /* The device might not support AER */ |
624 | if (!pos) | 598 | if (!pos) |
@@ -755,7 +729,6 @@ int aer_init(struct pcie_device *dev) | |||
755 | return AER_SUCCESS; | 729 | return AER_SUCCESS; |
756 | } | 730 | } |
757 | 731 | ||
758 | EXPORT_SYMBOL_GPL(pci_find_aer_capability); | ||
759 | EXPORT_SYMBOL_GPL(pci_enable_pcie_error_reporting); | 732 | EXPORT_SYMBOL_GPL(pci_enable_pcie_error_reporting); |
760 | EXPORT_SYMBOL_GPL(pci_disable_pcie_error_reporting); | 733 | EXPORT_SYMBOL_GPL(pci_disable_pcie_error_reporting); |
761 | EXPORT_SYMBOL_GPL(pci_cleanup_aer_uncorrect_error_status); | 734 | EXPORT_SYMBOL_GPL(pci_cleanup_aer_uncorrect_error_status); |