diff options
Diffstat (limited to 'drivers/net/wireless/iwlwifi/iwl-agn.c')
-rw-r--r-- | drivers/net/wireless/iwlwifi/iwl-agn.c | 529 |
1 files changed, 137 insertions, 392 deletions
diff --git a/drivers/net/wireless/iwlwifi/iwl-agn.c b/drivers/net/wireless/iwlwifi/iwl-agn.c index 321b18b5913..60bfde75ce8 100644 --- a/drivers/net/wireless/iwlwifi/iwl-agn.c +++ b/drivers/net/wireless/iwlwifi/iwl-agn.c | |||
@@ -1,6 +1,6 @@ | |||
1 | /****************************************************************************** | 1 | /****************************************************************************** |
2 | * | 2 | * |
3 | * Copyright(c) 2003 - 2010 Intel Corporation. All rights reserved. | 3 | * Copyright(c) 2003 - 2011 Intel Corporation. All rights reserved. |
4 | * | 4 | * |
5 | * Portions of this file are derived from the ipw3945 project, as well | 5 | * Portions of this file are derived from the ipw3945 project, as well |
6 | * as portions of the ieee80211 subsystem header files. | 6 | * as portions of the ieee80211 subsystem header files. |
@@ -409,7 +409,7 @@ int iwl_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv, | |||
409 | * Tell nic where to find circular buffer of Tx Frame Descriptors for | 409 | * Tell nic where to find circular buffer of Tx Frame Descriptors for |
410 | * given Tx queue, and enable the DMA channel used for that queue. | 410 | * given Tx queue, and enable the DMA channel used for that queue. |
411 | * | 411 | * |
412 | * 4965 supports up to 16 Tx queues in DRAM, mapped to up to 8 Tx DMA | 412 | * supports up to 16 Tx queues in DRAM, mapped to up to 8 Tx DMA |
413 | * channels supported in hardware. | 413 | * channels supported in hardware. |
414 | */ | 414 | */ |
415 | int iwl_hw_tx_queue_init(struct iwl_priv *priv, | 415 | int iwl_hw_tx_queue_init(struct iwl_priv *priv, |
@@ -483,12 +483,14 @@ static void iwl_bg_bt_full_concurrency(struct work_struct *work) | |||
483 | container_of(work, struct iwl_priv, bt_full_concurrency); | 483 | container_of(work, struct iwl_priv, bt_full_concurrency); |
484 | struct iwl_rxon_context *ctx; | 484 | struct iwl_rxon_context *ctx; |
485 | 485 | ||
486 | mutex_lock(&priv->mutex); | ||
487 | |||
486 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | 488 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) |
487 | return; | 489 | goto out; |
488 | 490 | ||
489 | /* dont send host command if rf-kill is on */ | 491 | /* dont send host command if rf-kill is on */ |
490 | if (!iwl_is_ready_rf(priv)) | 492 | if (!iwl_is_ready_rf(priv)) |
491 | return; | 493 | goto out; |
492 | 494 | ||
493 | IWL_DEBUG_INFO(priv, "BT coex in %s mode\n", | 495 | IWL_DEBUG_INFO(priv, "BT coex in %s mode\n", |
494 | priv->bt_full_concurrent ? | 496 | priv->bt_full_concurrent ? |
@@ -498,15 +500,15 @@ static void iwl_bg_bt_full_concurrency(struct work_struct *work) | |||
498 | * LQ & RXON updated cmds must be sent before BT Config cmd | 500 | * LQ & RXON updated cmds must be sent before BT Config cmd |
499 | * to avoid 3-wire collisions | 501 | * to avoid 3-wire collisions |
500 | */ | 502 | */ |
501 | mutex_lock(&priv->mutex); | ||
502 | for_each_context(priv, ctx) { | 503 | for_each_context(priv, ctx) { |
503 | if (priv->cfg->ops->hcmd->set_rxon_chain) | 504 | if (priv->cfg->ops->hcmd->set_rxon_chain) |
504 | priv->cfg->ops->hcmd->set_rxon_chain(priv, ctx); | 505 | priv->cfg->ops->hcmd->set_rxon_chain(priv, ctx); |
505 | iwlcore_commit_rxon(priv, ctx); | 506 | iwlcore_commit_rxon(priv, ctx); |
506 | } | 507 | } |
507 | mutex_unlock(&priv->mutex); | ||
508 | 508 | ||
509 | priv->cfg->ops->hcmd->send_bt_config(priv); | 509 | priv->cfg->ops->hcmd->send_bt_config(priv); |
510 | out: | ||
511 | mutex_unlock(&priv->mutex); | ||
510 | } | 512 | } |
511 | 513 | ||
512 | /** | 514 | /** |
@@ -556,7 +558,7 @@ static void iwl_print_cont_event_trace(struct iwl_priv *priv, u32 base, | |||
556 | } | 558 | } |
557 | 559 | ||
558 | /* Set starting address; reads will auto-increment */ | 560 | /* Set starting address; reads will auto-increment */ |
559 | _iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, ptr); | 561 | iwl_write32(priv, HBUS_TARG_MEM_RADDR, ptr); |
560 | rmb(); | 562 | rmb(); |
561 | 563 | ||
562 | /* | 564 | /* |
@@ -564,13 +566,13 @@ static void iwl_print_cont_event_trace(struct iwl_priv *priv, u32 base, | |||
564 | * place event id # at far right for easier visual parsing. | 566 | * place event id # at far right for easier visual parsing. |
565 | */ | 567 | */ |
566 | for (i = 0; i < num_events; i++) { | 568 | for (i = 0; i < num_events; i++) { |
567 | ev = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT); | 569 | ev = iwl_read32(priv, HBUS_TARG_MEM_RDAT); |
568 | time = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT); | 570 | time = iwl_read32(priv, HBUS_TARG_MEM_RDAT); |
569 | if (mode == 0) { | 571 | if (mode == 0) { |
570 | trace_iwlwifi_dev_ucode_cont_event(priv, | 572 | trace_iwlwifi_dev_ucode_cont_event(priv, |
571 | 0, time, ev); | 573 | 0, time, ev); |
572 | } else { | 574 | } else { |
573 | data = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT); | 575 | data = iwl_read32(priv, HBUS_TARG_MEM_RDAT); |
574 | trace_iwlwifi_dev_ucode_cont_event(priv, | 576 | trace_iwlwifi_dev_ucode_cont_event(priv, |
575 | time, data, ev); | 577 | time, data, ev); |
576 | } | 578 | } |
@@ -588,10 +590,7 @@ static void iwl_continuous_event_trace(struct iwl_priv *priv) | |||
588 | u32 num_wraps; /* # times uCode wrapped to top of log */ | 590 | u32 num_wraps; /* # times uCode wrapped to top of log */ |
589 | u32 next_entry; /* index of next entry to be written by uCode */ | 591 | u32 next_entry; /* index of next entry to be written by uCode */ |
590 | 592 | ||
591 | if (priv->ucode_type == UCODE_INIT) | 593 | base = priv->device_pointers.error_event_table; |
592 | base = le32_to_cpu(priv->card_alive_init.error_event_table_ptr); | ||
593 | else | ||
594 | base = le32_to_cpu(priv->card_alive.log_event_table_ptr); | ||
595 | if (priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) { | 594 | if (priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) { |
596 | capacity = iwl_read_targ_mem(priv, base); | 595 | capacity = iwl_read_targ_mem(priv, base); |
597 | num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32))); | 596 | num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32))); |
@@ -845,191 +844,6 @@ static inline void iwl_synchronize_irq(struct iwl_priv *priv) | |||
845 | tasklet_kill(&priv->irq_tasklet); | 844 | tasklet_kill(&priv->irq_tasklet); |
846 | } | 845 | } |
847 | 846 | ||
848 | static void iwl_irq_tasklet_legacy(struct iwl_priv *priv) | ||
849 | { | ||
850 | u32 inta, handled = 0; | ||
851 | u32 inta_fh; | ||
852 | unsigned long flags; | ||
853 | u32 i; | ||
854 | #ifdef CONFIG_IWLWIFI_DEBUG | ||
855 | u32 inta_mask; | ||
856 | #endif | ||
857 | |||
858 | spin_lock_irqsave(&priv->lock, flags); | ||
859 | |||
860 | /* Ack/clear/reset pending uCode interrupts. | ||
861 | * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS, | ||
862 | * and will clear only when CSR_FH_INT_STATUS gets cleared. */ | ||
863 | inta = iwl_read32(priv, CSR_INT); | ||
864 | iwl_write32(priv, CSR_INT, inta); | ||
865 | |||
866 | /* Ack/clear/reset pending flow-handler (DMA) interrupts. | ||
867 | * Any new interrupts that happen after this, either while we're | ||
868 | * in this tasklet, or later, will show up in next ISR/tasklet. */ | ||
869 | inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS); | ||
870 | iwl_write32(priv, CSR_FH_INT_STATUS, inta_fh); | ||
871 | |||
872 | #ifdef CONFIG_IWLWIFI_DEBUG | ||
873 | if (iwl_get_debug_level(priv) & IWL_DL_ISR) { | ||
874 | /* just for debug */ | ||
875 | inta_mask = iwl_read32(priv, CSR_INT_MASK); | ||
876 | IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x, fh 0x%08x\n", | ||
877 | inta, inta_mask, inta_fh); | ||
878 | } | ||
879 | #endif | ||
880 | |||
881 | spin_unlock_irqrestore(&priv->lock, flags); | ||
882 | |||
883 | /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not | ||
884 | * atomic, make sure that inta covers all the interrupts that | ||
885 | * we've discovered, even if FH interrupt came in just after | ||
886 | * reading CSR_INT. */ | ||
887 | if (inta_fh & CSR49_FH_INT_RX_MASK) | ||
888 | inta |= CSR_INT_BIT_FH_RX; | ||
889 | if (inta_fh & CSR49_FH_INT_TX_MASK) | ||
890 | inta |= CSR_INT_BIT_FH_TX; | ||
891 | |||
892 | /* Now service all interrupt bits discovered above. */ | ||
893 | if (inta & CSR_INT_BIT_HW_ERR) { | ||
894 | IWL_ERR(priv, "Hardware error detected. Restarting.\n"); | ||
895 | |||
896 | /* Tell the device to stop sending interrupts */ | ||
897 | iwl_disable_interrupts(priv); | ||
898 | |||
899 | priv->isr_stats.hw++; | ||
900 | iwl_irq_handle_error(priv); | ||
901 | |||
902 | handled |= CSR_INT_BIT_HW_ERR; | ||
903 | |||
904 | return; | ||
905 | } | ||
906 | |||
907 | #ifdef CONFIG_IWLWIFI_DEBUG | ||
908 | if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) { | ||
909 | /* NIC fires this, but we don't use it, redundant with WAKEUP */ | ||
910 | if (inta & CSR_INT_BIT_SCD) { | ||
911 | IWL_DEBUG_ISR(priv, "Scheduler finished to transmit " | ||
912 | "the frame/frames.\n"); | ||
913 | priv->isr_stats.sch++; | ||
914 | } | ||
915 | |||
916 | /* Alive notification via Rx interrupt will do the real work */ | ||
917 | if (inta & CSR_INT_BIT_ALIVE) { | ||
918 | IWL_DEBUG_ISR(priv, "Alive interrupt\n"); | ||
919 | priv->isr_stats.alive++; | ||
920 | } | ||
921 | } | ||
922 | #endif | ||
923 | /* Safely ignore these bits for debug checks below */ | ||
924 | inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE); | ||
925 | |||
926 | /* HW RF KILL switch toggled */ | ||
927 | if (inta & CSR_INT_BIT_RF_KILL) { | ||
928 | int hw_rf_kill = 0; | ||
929 | if (!(iwl_read32(priv, CSR_GP_CNTRL) & | ||
930 | CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)) | ||
931 | hw_rf_kill = 1; | ||
932 | |||
933 | IWL_WARN(priv, "RF_KILL bit toggled to %s.\n", | ||
934 | hw_rf_kill ? "disable radio" : "enable radio"); | ||
935 | |||
936 | priv->isr_stats.rfkill++; | ||
937 | |||
938 | /* driver only loads ucode once setting the interface up. | ||
939 | * the driver allows loading the ucode even if the radio | ||
940 | * is killed. Hence update the killswitch state here. The | ||
941 | * rfkill handler will care about restarting if needed. | ||
942 | */ | ||
943 | if (!test_bit(STATUS_ALIVE, &priv->status)) { | ||
944 | if (hw_rf_kill) | ||
945 | set_bit(STATUS_RF_KILL_HW, &priv->status); | ||
946 | else | ||
947 | clear_bit(STATUS_RF_KILL_HW, &priv->status); | ||
948 | wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill); | ||
949 | } | ||
950 | |||
951 | handled |= CSR_INT_BIT_RF_KILL; | ||
952 | } | ||
953 | |||
954 | /* Chip got too hot and stopped itself */ | ||
955 | if (inta & CSR_INT_BIT_CT_KILL) { | ||
956 | IWL_ERR(priv, "Microcode CT kill error detected.\n"); | ||
957 | priv->isr_stats.ctkill++; | ||
958 | handled |= CSR_INT_BIT_CT_KILL; | ||
959 | } | ||
960 | |||
961 | /* Error detected by uCode */ | ||
962 | if (inta & CSR_INT_BIT_SW_ERR) { | ||
963 | IWL_ERR(priv, "Microcode SW error detected. " | ||
964 | " Restarting 0x%X.\n", inta); | ||
965 | priv->isr_stats.sw++; | ||
966 | iwl_irq_handle_error(priv); | ||
967 | handled |= CSR_INT_BIT_SW_ERR; | ||
968 | } | ||
969 | |||
970 | /* | ||
971 | * uCode wakes up after power-down sleep. | ||
972 | * Tell device about any new tx or host commands enqueued, | ||
973 | * and about any Rx buffers made available while asleep. | ||
974 | */ | ||
975 | if (inta & CSR_INT_BIT_WAKEUP) { | ||
976 | IWL_DEBUG_ISR(priv, "Wakeup interrupt\n"); | ||
977 | iwl_rx_queue_update_write_ptr(priv, &priv->rxq); | ||
978 | for (i = 0; i < priv->hw_params.max_txq_num; i++) | ||
979 | iwl_txq_update_write_ptr(priv, &priv->txq[i]); | ||
980 | priv->isr_stats.wakeup++; | ||
981 | handled |= CSR_INT_BIT_WAKEUP; | ||
982 | } | ||
983 | |||
984 | /* All uCode command responses, including Tx command responses, | ||
985 | * Rx "responses" (frame-received notification), and other | ||
986 | * notifications from uCode come through here*/ | ||
987 | if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) { | ||
988 | iwl_rx_handle(priv); | ||
989 | priv->isr_stats.rx++; | ||
990 | handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX); | ||
991 | } | ||
992 | |||
993 | /* This "Tx" DMA channel is used only for loading uCode */ | ||
994 | if (inta & CSR_INT_BIT_FH_TX) { | ||
995 | IWL_DEBUG_ISR(priv, "uCode load interrupt\n"); | ||
996 | priv->isr_stats.tx++; | ||
997 | handled |= CSR_INT_BIT_FH_TX; | ||
998 | /* Wake up uCode load routine, now that load is complete */ | ||
999 | priv->ucode_write_complete = 1; | ||
1000 | wake_up_interruptible(&priv->wait_command_queue); | ||
1001 | } | ||
1002 | |||
1003 | if (inta & ~handled) { | ||
1004 | IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled); | ||
1005 | priv->isr_stats.unhandled++; | ||
1006 | } | ||
1007 | |||
1008 | if (inta & ~(priv->inta_mask)) { | ||
1009 | IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n", | ||
1010 | inta & ~priv->inta_mask); | ||
1011 | IWL_WARN(priv, " with FH_INT = 0x%08x\n", inta_fh); | ||
1012 | } | ||
1013 | |||
1014 | /* Re-enable all interrupts */ | ||
1015 | /* only Re-enable if disabled by irq */ | ||
1016 | if (test_bit(STATUS_INT_ENABLED, &priv->status)) | ||
1017 | iwl_enable_interrupts(priv); | ||
1018 | /* Re-enable RF_KILL if it occurred */ | ||
1019 | else if (handled & CSR_INT_BIT_RF_KILL) | ||
1020 | iwl_enable_rfkill_int(priv); | ||
1021 | |||
1022 | #ifdef CONFIG_IWLWIFI_DEBUG | ||
1023 | if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) { | ||
1024 | inta = iwl_read32(priv, CSR_INT); | ||
1025 | inta_mask = iwl_read32(priv, CSR_INT_MASK); | ||
1026 | inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS); | ||
1027 | IWL_DEBUG_ISR(priv, "End inta 0x%08x, enabled 0x%08x, fh 0x%08x, " | ||
1028 | "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags); | ||
1029 | } | ||
1030 | #endif | ||
1031 | } | ||
1032 | |||
1033 | /* tasklet for iwlagn interrupt */ | 847 | /* tasklet for iwlagn interrupt */ |
1034 | static void iwl_irq_tasklet(struct iwl_priv *priv) | 848 | static void iwl_irq_tasklet(struct iwl_priv *priv) |
1035 | { | 849 | { |
@@ -1171,7 +985,7 @@ static void iwl_irq_tasklet(struct iwl_priv *priv) | |||
1171 | if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) { | 985 | if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) { |
1172 | handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX); | 986 | handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX); |
1173 | iwl_write32(priv, CSR_FH_INT_STATUS, | 987 | iwl_write32(priv, CSR_FH_INT_STATUS, |
1174 | CSR49_FH_INT_RX_MASK); | 988 | CSR_FH_INT_RX_MASK); |
1175 | } | 989 | } |
1176 | if (inta & CSR_INT_BIT_RX_PERIODIC) { | 990 | if (inta & CSR_INT_BIT_RX_PERIODIC) { |
1177 | handled |= CSR_INT_BIT_RX_PERIODIC; | 991 | handled |= CSR_INT_BIT_RX_PERIODIC; |
@@ -1209,7 +1023,7 @@ static void iwl_irq_tasklet(struct iwl_priv *priv) | |||
1209 | 1023 | ||
1210 | /* This "Tx" DMA channel is used only for loading uCode */ | 1024 | /* This "Tx" DMA channel is used only for loading uCode */ |
1211 | if (inta & CSR_INT_BIT_FH_TX) { | 1025 | if (inta & CSR_INT_BIT_FH_TX) { |
1212 | iwl_write32(priv, CSR_FH_INT_STATUS, CSR49_FH_INT_TX_MASK); | 1026 | iwl_write32(priv, CSR_FH_INT_STATUS, CSR_FH_INT_TX_MASK); |
1213 | IWL_DEBUG_ISR(priv, "uCode load interrupt\n"); | 1027 | IWL_DEBUG_ISR(priv, "uCode load interrupt\n"); |
1214 | priv->isr_stats.tx++; | 1028 | priv->isr_stats.tx++; |
1215 | handled |= CSR_INT_BIT_FH_TX; | 1029 | handled |= CSR_INT_BIT_FH_TX; |
@@ -1361,10 +1175,8 @@ static void iwl_dealloc_ucode_pci(struct iwl_priv *priv) | |||
1361 | { | 1175 | { |
1362 | iwl_free_fw_desc(priv->pci_dev, &priv->ucode_code); | 1176 | iwl_free_fw_desc(priv->pci_dev, &priv->ucode_code); |
1363 | iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data); | 1177 | iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data); |
1364 | iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data_backup); | ||
1365 | iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init); | 1178 | iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init); |
1366 | iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init_data); | 1179 | iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init_data); |
1367 | iwl_free_fw_desc(priv->pci_dev, &priv->ucode_boot); | ||
1368 | } | 1180 | } |
1369 | 1181 | ||
1370 | static void iwl_nic_start(struct iwl_priv *priv) | 1182 | static void iwl_nic_start(struct iwl_priv *priv) |
@@ -1376,7 +1188,7 @@ static void iwl_nic_start(struct iwl_priv *priv) | |||
1376 | struct iwlagn_ucode_capabilities { | 1188 | struct iwlagn_ucode_capabilities { |
1377 | u32 max_probe_length; | 1189 | u32 max_probe_length; |
1378 | u32 standard_phy_calibration_size; | 1190 | u32 standard_phy_calibration_size; |
1379 | bool pan; | 1191 | u32 flags; |
1380 | }; | 1192 | }; |
1381 | 1193 | ||
1382 | static void iwl_ucode_callback(const struct firmware *ucode_raw, void *context); | 1194 | static void iwl_ucode_callback(const struct firmware *ucode_raw, void *context); |
@@ -1422,8 +1234,8 @@ static int __must_check iwl_request_firmware(struct iwl_priv *priv, bool first) | |||
1422 | } | 1234 | } |
1423 | 1235 | ||
1424 | struct iwlagn_firmware_pieces { | 1236 | struct iwlagn_firmware_pieces { |
1425 | const void *inst, *data, *init, *init_data, *boot; | 1237 | const void *inst, *data, *init, *init_data; |
1426 | size_t inst_size, data_size, init_size, init_data_size, boot_size; | 1238 | size_t inst_size, data_size, init_size, init_data_size; |
1427 | 1239 | ||
1428 | u32 build; | 1240 | u32 build; |
1429 | 1241 | ||
@@ -1444,28 +1256,18 @@ static int iwlagn_load_legacy_firmware(struct iwl_priv *priv, | |||
1444 | 1256 | ||
1445 | switch (api_ver) { | 1257 | switch (api_ver) { |
1446 | default: | 1258 | default: |
1447 | /* | 1259 | hdr_size = 28; |
1448 | * 4965 doesn't revision the firmware file format | 1260 | if (ucode_raw->size < hdr_size) { |
1449 | * along with the API version, it always uses v1 | 1261 | IWL_ERR(priv, "File size too small!\n"); |
1450 | * file format. | 1262 | return -EINVAL; |
1451 | */ | ||
1452 | if ((priv->hw_rev & CSR_HW_REV_TYPE_MSK) != | ||
1453 | CSR_HW_REV_TYPE_4965) { | ||
1454 | hdr_size = 28; | ||
1455 | if (ucode_raw->size < hdr_size) { | ||
1456 | IWL_ERR(priv, "File size too small!\n"); | ||
1457 | return -EINVAL; | ||
1458 | } | ||
1459 | pieces->build = le32_to_cpu(ucode->u.v2.build); | ||
1460 | pieces->inst_size = le32_to_cpu(ucode->u.v2.inst_size); | ||
1461 | pieces->data_size = le32_to_cpu(ucode->u.v2.data_size); | ||
1462 | pieces->init_size = le32_to_cpu(ucode->u.v2.init_size); | ||
1463 | pieces->init_data_size = le32_to_cpu(ucode->u.v2.init_data_size); | ||
1464 | pieces->boot_size = le32_to_cpu(ucode->u.v2.boot_size); | ||
1465 | src = ucode->u.v2.data; | ||
1466 | break; | ||
1467 | } | 1263 | } |
1468 | /* fall through for 4965 */ | 1264 | pieces->build = le32_to_cpu(ucode->u.v2.build); |
1265 | pieces->inst_size = le32_to_cpu(ucode->u.v2.inst_size); | ||
1266 | pieces->data_size = le32_to_cpu(ucode->u.v2.data_size); | ||
1267 | pieces->init_size = le32_to_cpu(ucode->u.v2.init_size); | ||
1268 | pieces->init_data_size = le32_to_cpu(ucode->u.v2.init_data_size); | ||
1269 | src = ucode->u.v2.data; | ||
1270 | break; | ||
1469 | case 0: | 1271 | case 0: |
1470 | case 1: | 1272 | case 1: |
1471 | case 2: | 1273 | case 2: |
@@ -1479,7 +1281,6 @@ static int iwlagn_load_legacy_firmware(struct iwl_priv *priv, | |||
1479 | pieces->data_size = le32_to_cpu(ucode->u.v1.data_size); | 1281 | pieces->data_size = le32_to_cpu(ucode->u.v1.data_size); |
1480 | pieces->init_size = le32_to_cpu(ucode->u.v1.init_size); | 1282 | pieces->init_size = le32_to_cpu(ucode->u.v1.init_size); |
1481 | pieces->init_data_size = le32_to_cpu(ucode->u.v1.init_data_size); | 1283 | pieces->init_data_size = le32_to_cpu(ucode->u.v1.init_data_size); |
1482 | pieces->boot_size = le32_to_cpu(ucode->u.v1.boot_size); | ||
1483 | src = ucode->u.v1.data; | 1284 | src = ucode->u.v1.data; |
1484 | break; | 1285 | break; |
1485 | } | 1286 | } |
@@ -1487,7 +1288,7 @@ static int iwlagn_load_legacy_firmware(struct iwl_priv *priv, | |||
1487 | /* Verify size of file vs. image size info in file's header */ | 1288 | /* Verify size of file vs. image size info in file's header */ |
1488 | if (ucode_raw->size != hdr_size + pieces->inst_size + | 1289 | if (ucode_raw->size != hdr_size + pieces->inst_size + |
1489 | pieces->data_size + pieces->init_size + | 1290 | pieces->data_size + pieces->init_size + |
1490 | pieces->init_data_size + pieces->boot_size) { | 1291 | pieces->init_data_size) { |
1491 | 1292 | ||
1492 | IWL_ERR(priv, | 1293 | IWL_ERR(priv, |
1493 | "uCode file size %d does not match expected size\n", | 1294 | "uCode file size %d does not match expected size\n", |
@@ -1503,8 +1304,6 @@ static int iwlagn_load_legacy_firmware(struct iwl_priv *priv, | |||
1503 | src += pieces->init_size; | 1304 | src += pieces->init_size; |
1504 | pieces->init_data = src; | 1305 | pieces->init_data = src; |
1505 | src += pieces->init_data_size; | 1306 | src += pieces->init_data_size; |
1506 | pieces->boot = src; | ||
1507 | src += pieces->boot_size; | ||
1508 | 1307 | ||
1509 | return 0; | 1308 | return 0; |
1510 | } | 1309 | } |
@@ -1605,8 +1404,7 @@ static int iwlagn_load_firmware(struct iwl_priv *priv, | |||
1605 | pieces->init_data_size = tlv_len; | 1404 | pieces->init_data_size = tlv_len; |
1606 | break; | 1405 | break; |
1607 | case IWL_UCODE_TLV_BOOT: | 1406 | case IWL_UCODE_TLV_BOOT: |
1608 | pieces->boot = tlv_data; | 1407 | IWL_ERR(priv, "Found unexpected BOOT ucode\n"); |
1609 | pieces->boot_size = tlv_len; | ||
1610 | break; | 1408 | break; |
1611 | case IWL_UCODE_TLV_PROBE_MAX_LEN: | 1409 | case IWL_UCODE_TLV_PROBE_MAX_LEN: |
1612 | if (tlv_len != sizeof(u32)) | 1410 | if (tlv_len != sizeof(u32)) |
@@ -1617,7 +1415,23 @@ static int iwlagn_load_firmware(struct iwl_priv *priv, | |||
1617 | case IWL_UCODE_TLV_PAN: | 1415 | case IWL_UCODE_TLV_PAN: |
1618 | if (tlv_len) | 1416 | if (tlv_len) |
1619 | goto invalid_tlv_len; | 1417 | goto invalid_tlv_len; |
1620 | capa->pan = true; | 1418 | capa->flags |= IWL_UCODE_TLV_FLAGS_PAN; |
1419 | break; | ||
1420 | case IWL_UCODE_TLV_FLAGS: | ||
1421 | /* must be at least one u32 */ | ||
1422 | if (tlv_len < sizeof(u32)) | ||
1423 | goto invalid_tlv_len; | ||
1424 | /* and a proper number of u32s */ | ||
1425 | if (tlv_len % sizeof(u32)) | ||
1426 | goto invalid_tlv_len; | ||
1427 | /* | ||
1428 | * This driver only reads the first u32 as | ||
1429 | * right now no more features are defined, | ||
1430 | * if that changes then either the driver | ||
1431 | * will not work with the new firmware, or | ||
1432 | * it'll not take advantage of new features. | ||
1433 | */ | ||
1434 | capa->flags = le32_to_cpup((__le32 *)tlv_data); | ||
1621 | break; | 1435 | break; |
1622 | case IWL_UCODE_TLV_INIT_EVTLOG_PTR: | 1436 | case IWL_UCODE_TLV_INIT_EVTLOG_PTR: |
1623 | if (tlv_len != sizeof(u32)) | 1437 | if (tlv_len != sizeof(u32)) |
@@ -1806,8 +1620,6 @@ static void iwl_ucode_callback(const struct firmware *ucode_raw, void *context) | |||
1806 | pieces.init_size); | 1620 | pieces.init_size); |
1807 | IWL_DEBUG_INFO(priv, "f/w package hdr init data size = %Zd\n", | 1621 | IWL_DEBUG_INFO(priv, "f/w package hdr init data size = %Zd\n", |
1808 | pieces.init_data_size); | 1622 | pieces.init_data_size); |
1809 | IWL_DEBUG_INFO(priv, "f/w package hdr boot inst size = %Zd\n", | ||
1810 | pieces.boot_size); | ||
1811 | 1623 | ||
1812 | /* Verify that uCode images will fit in card's SRAM */ | 1624 | /* Verify that uCode images will fit in card's SRAM */ |
1813 | if (pieces.inst_size > priv->hw_params.max_inst_size) { | 1625 | if (pieces.inst_size > priv->hw_params.max_inst_size) { |
@@ -1834,12 +1646,6 @@ static void iwl_ucode_callback(const struct firmware *ucode_raw, void *context) | |||
1834 | goto try_again; | 1646 | goto try_again; |
1835 | } | 1647 | } |
1836 | 1648 | ||
1837 | if (pieces.boot_size > priv->hw_params.max_bsm_size) { | ||
1838 | IWL_ERR(priv, "uCode boot instr len %Zd too large to fit in\n", | ||
1839 | pieces.boot_size); | ||
1840 | goto try_again; | ||
1841 | } | ||
1842 | |||
1843 | /* Allocate ucode buffers for card's bus-master loading ... */ | 1649 | /* Allocate ucode buffers for card's bus-master loading ... */ |
1844 | 1650 | ||
1845 | /* Runtime instructions and 2 copies of data: | 1651 | /* Runtime instructions and 2 copies of data: |
@@ -1851,11 +1657,7 @@ static void iwl_ucode_callback(const struct firmware *ucode_raw, void *context) | |||
1851 | priv->ucode_data.len = pieces.data_size; | 1657 | priv->ucode_data.len = pieces.data_size; |
1852 | iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data); | 1658 | iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data); |
1853 | 1659 | ||
1854 | priv->ucode_data_backup.len = pieces.data_size; | 1660 | if (!priv->ucode_code.v_addr || !priv->ucode_data.v_addr) |
1855 | iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data_backup); | ||
1856 | |||
1857 | if (!priv->ucode_code.v_addr || !priv->ucode_data.v_addr || | ||
1858 | !priv->ucode_data_backup.v_addr) | ||
1859 | goto err_pci_alloc; | 1661 | goto err_pci_alloc; |
1860 | 1662 | ||
1861 | /* Initialization instructions and data */ | 1663 | /* Initialization instructions and data */ |
@@ -1870,15 +1672,6 @@ static void iwl_ucode_callback(const struct firmware *ucode_raw, void *context) | |||
1870 | goto err_pci_alloc; | 1672 | goto err_pci_alloc; |
1871 | } | 1673 | } |
1872 | 1674 | ||
1873 | /* Bootstrap (instructions only, no data) */ | ||
1874 | if (pieces.boot_size) { | ||
1875 | priv->ucode_boot.len = pieces.boot_size; | ||
1876 | iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_boot); | ||
1877 | |||
1878 | if (!priv->ucode_boot.v_addr) | ||
1879 | goto err_pci_alloc; | ||
1880 | } | ||
1881 | |||
1882 | /* Now that we can no longer fail, copy information */ | 1675 | /* Now that we can no longer fail, copy information */ |
1883 | 1676 | ||
1884 | /* | 1677 | /* |
@@ -1901,12 +1694,21 @@ static void iwl_ucode_callback(const struct firmware *ucode_raw, void *context) | |||
1901 | priv->cfg->base_params->max_event_log_size; | 1694 | priv->cfg->base_params->max_event_log_size; |
1902 | priv->_agn.inst_errlog_ptr = pieces.inst_errlog_ptr; | 1695 | priv->_agn.inst_errlog_ptr = pieces.inst_errlog_ptr; |
1903 | 1696 | ||
1904 | if (ucode_capa.pan) { | 1697 | if (ucode_capa.flags & IWL_UCODE_TLV_FLAGS_PAN) { |
1905 | priv->valid_contexts |= BIT(IWL_RXON_CTX_PAN); | 1698 | priv->valid_contexts |= BIT(IWL_RXON_CTX_PAN); |
1906 | priv->sta_key_max_num = STA_KEY_MAX_NUM_PAN; | 1699 | priv->sta_key_max_num = STA_KEY_MAX_NUM_PAN; |
1907 | } else | 1700 | } else |
1908 | priv->sta_key_max_num = STA_KEY_MAX_NUM; | 1701 | priv->sta_key_max_num = STA_KEY_MAX_NUM; |
1909 | 1702 | ||
1703 | if (priv->valid_contexts != BIT(IWL_RXON_CTX_BSS)) | ||
1704 | priv->cmd_queue = IWL_IPAN_CMD_QUEUE_NUM; | ||
1705 | else | ||
1706 | priv->cmd_queue = IWL_DEFAULT_CMD_QUEUE_NUM; | ||
1707 | |||
1708 | if (ucode_capa.flags & IWL_UCODE_TLV_FLAGS_BTSTATS || | ||
1709 | (priv->cfg->bt_params && priv->cfg->bt_params->bt_statistics)) | ||
1710 | priv->bt_statistics = true; | ||
1711 | |||
1910 | /* Copy images into buffers for card's bus-master reads ... */ | 1712 | /* Copy images into buffers for card's bus-master reads ... */ |
1911 | 1713 | ||
1912 | /* Runtime instructions (first block of data in file) */ | 1714 | /* Runtime instructions (first block of data in file) */ |
@@ -1924,7 +1726,6 @@ static void iwl_ucode_callback(const struct firmware *ucode_raw, void *context) | |||
1924 | IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode data len %Zd\n", | 1726 | IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode data len %Zd\n", |
1925 | pieces.data_size); | 1727 | pieces.data_size); |
1926 | memcpy(priv->ucode_data.v_addr, pieces.data, pieces.data_size); | 1728 | memcpy(priv->ucode_data.v_addr, pieces.data, pieces.data_size); |
1927 | memcpy(priv->ucode_data_backup.v_addr, pieces.data, pieces.data_size); | ||
1928 | 1729 | ||
1929 | /* Initialization instructions */ | 1730 | /* Initialization instructions */ |
1930 | if (pieces.init_size) { | 1731 | if (pieces.init_size) { |
@@ -1941,11 +1742,6 @@ static void iwl_ucode_callback(const struct firmware *ucode_raw, void *context) | |||
1941 | pieces.init_data_size); | 1742 | pieces.init_data_size); |
1942 | } | 1743 | } |
1943 | 1744 | ||
1944 | /* Bootstrap instructions */ | ||
1945 | IWL_DEBUG_INFO(priv, "Copying (but not loading) boot instr len %Zd\n", | ||
1946 | pieces.boot_size); | ||
1947 | memcpy(priv->ucode_boot.v_addr, pieces.boot, pieces.boot_size); | ||
1948 | |||
1949 | /* | 1745 | /* |
1950 | * figure out the offset of chain noise reset and gain commands | 1746 | * figure out the offset of chain noise reset and gain commands |
1951 | * base on the size of standard phy calibration commands table size | 1747 | * base on the size of standard phy calibration commands table size |
@@ -2077,12 +1873,11 @@ void iwl_dump_nic_error_log(struct iwl_priv *priv) | |||
2077 | u32 blink1, blink2, ilink1, ilink2; | 1873 | u32 blink1, blink2, ilink1, ilink2; |
2078 | u32 pc, hcmd; | 1874 | u32 pc, hcmd; |
2079 | 1875 | ||
1876 | base = priv->device_pointers.error_event_table; | ||
2080 | if (priv->ucode_type == UCODE_INIT) { | 1877 | if (priv->ucode_type == UCODE_INIT) { |
2081 | base = le32_to_cpu(priv->card_alive_init.error_event_table_ptr); | ||
2082 | if (!base) | 1878 | if (!base) |
2083 | base = priv->_agn.init_errlog_ptr; | 1879 | base = priv->_agn.init_errlog_ptr; |
2084 | } else { | 1880 | } else { |
2085 | base = le32_to_cpu(priv->card_alive.error_event_table_ptr); | ||
2086 | if (!base) | 1881 | if (!base) |
2087 | base = priv->_agn.inst_errlog_ptr; | 1882 | base = priv->_agn.inst_errlog_ptr; |
2088 | } | 1883 | } |
@@ -2147,12 +1942,11 @@ static int iwl_print_event_log(struct iwl_priv *priv, u32 start_idx, | |||
2147 | if (num_events == 0) | 1942 | if (num_events == 0) |
2148 | return pos; | 1943 | return pos; |
2149 | 1944 | ||
1945 | base = priv->device_pointers.log_event_table; | ||
2150 | if (priv->ucode_type == UCODE_INIT) { | 1946 | if (priv->ucode_type == UCODE_INIT) { |
2151 | base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr); | ||
2152 | if (!base) | 1947 | if (!base) |
2153 | base = priv->_agn.init_evtlog_ptr; | 1948 | base = priv->_agn.init_evtlog_ptr; |
2154 | } else { | 1949 | } else { |
2155 | base = le32_to_cpu(priv->card_alive.log_event_table_ptr); | ||
2156 | if (!base) | 1950 | if (!base) |
2157 | base = priv->_agn.inst_evtlog_ptr; | 1951 | base = priv->_agn.inst_evtlog_ptr; |
2158 | } | 1952 | } |
@@ -2169,14 +1963,14 @@ static int iwl_print_event_log(struct iwl_priv *priv, u32 start_idx, | |||
2169 | iwl_grab_nic_access(priv); | 1963 | iwl_grab_nic_access(priv); |
2170 | 1964 | ||
2171 | /* Set starting address; reads will auto-increment */ | 1965 | /* Set starting address; reads will auto-increment */ |
2172 | _iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, ptr); | 1966 | iwl_write32(priv, HBUS_TARG_MEM_RADDR, ptr); |
2173 | rmb(); | 1967 | rmb(); |
2174 | 1968 | ||
2175 | /* "time" is actually "data" for mode 0 (no timestamp). | 1969 | /* "time" is actually "data" for mode 0 (no timestamp). |
2176 | * place event id # at far right for easier visual parsing. */ | 1970 | * place event id # at far right for easier visual parsing. */ |
2177 | for (i = 0; i < num_events; i++) { | 1971 | for (i = 0; i < num_events; i++) { |
2178 | ev = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT); | 1972 | ev = iwl_read32(priv, HBUS_TARG_MEM_RDAT); |
2179 | time = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT); | 1973 | time = iwl_read32(priv, HBUS_TARG_MEM_RDAT); |
2180 | if (mode == 0) { | 1974 | if (mode == 0) { |
2181 | /* data, ev */ | 1975 | /* data, ev */ |
2182 | if (bufsz) { | 1976 | if (bufsz) { |
@@ -2190,7 +1984,7 @@ static int iwl_print_event_log(struct iwl_priv *priv, u32 start_idx, | |||
2190 | time, ev); | 1984 | time, ev); |
2191 | } | 1985 | } |
2192 | } else { | 1986 | } else { |
2193 | data = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT); | 1987 | data = iwl_read32(priv, HBUS_TARG_MEM_RDAT); |
2194 | if (bufsz) { | 1988 | if (bufsz) { |
2195 | pos += scnprintf(*buf + pos, bufsz - pos, | 1989 | pos += scnprintf(*buf + pos, bufsz - pos, |
2196 | "EVT_LOGT:%010u:0x%08x:%04u\n", | 1990 | "EVT_LOGT:%010u:0x%08x:%04u\n", |
@@ -2261,13 +2055,12 @@ int iwl_dump_nic_event_log(struct iwl_priv *priv, bool full_log, | |||
2261 | int pos = 0; | 2055 | int pos = 0; |
2262 | size_t bufsz = 0; | 2056 | size_t bufsz = 0; |
2263 | 2057 | ||
2058 | base = priv->device_pointers.log_event_table; | ||
2264 | if (priv->ucode_type == UCODE_INIT) { | 2059 | if (priv->ucode_type == UCODE_INIT) { |
2265 | base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr); | ||
2266 | logsize = priv->_agn.init_evtlog_size; | 2060 | logsize = priv->_agn.init_evtlog_size; |
2267 | if (!base) | 2061 | if (!base) |
2268 | base = priv->_agn.init_evtlog_ptr; | 2062 | base = priv->_agn.init_evtlog_ptr; |
2269 | } else { | 2063 | } else { |
2270 | base = le32_to_cpu(priv->card_alive.log_event_table_ptr); | ||
2271 | logsize = priv->_agn.inst_evtlog_size; | 2064 | logsize = priv->_agn.inst_evtlog_size; |
2272 | if (!base) | 2065 | if (!base) |
2273 | base = priv->_agn.inst_evtlog_ptr; | 2066 | base = priv->_agn.inst_evtlog_ptr; |
@@ -2433,14 +2226,14 @@ static void iwl_alive_start(struct iwl_priv *priv) | |||
2433 | /* Initialize uCode has loaded Runtime uCode ... verify inst image. | 2226 | /* Initialize uCode has loaded Runtime uCode ... verify inst image. |
2434 | * This is a paranoid check, because we would not have gotten the | 2227 | * This is a paranoid check, because we would not have gotten the |
2435 | * "runtime" alive if code weren't properly loaded. */ | 2228 | * "runtime" alive if code weren't properly loaded. */ |
2436 | if (iwl_verify_ucode(priv)) { | 2229 | if (iwl_verify_ucode(priv, &priv->ucode_code)) { |
2437 | /* Runtime instruction load was bad; | 2230 | /* Runtime instruction load was bad; |
2438 | * take it all the way back down so we can try again */ | 2231 | * take it all the way back down so we can try again */ |
2439 | IWL_DEBUG_INFO(priv, "Bad runtime uCode load.\n"); | 2232 | IWL_DEBUG_INFO(priv, "Bad runtime uCode load.\n"); |
2440 | goto restart; | 2233 | goto restart; |
2441 | } | 2234 | } |
2442 | 2235 | ||
2443 | ret = priv->cfg->ops->lib->alive_notify(priv); | 2236 | ret = iwlagn_alive_notify(priv); |
2444 | if (ret) { | 2237 | if (ret) { |
2445 | IWL_WARN(priv, | 2238 | IWL_WARN(priv, |
2446 | "Could not complete ALIVE transition [ntf]: %d\n", ret); | 2239 | "Could not complete ALIVE transition [ntf]: %d\n", ret); |
@@ -2537,7 +2330,7 @@ static void iwl_cancel_deferred_work(struct iwl_priv *priv); | |||
2537 | static void __iwl_down(struct iwl_priv *priv) | 2330 | static void __iwl_down(struct iwl_priv *priv) |
2538 | { | 2331 | { |
2539 | unsigned long flags; | 2332 | unsigned long flags; |
2540 | int exit_pending = test_bit(STATUS_EXIT_PENDING, &priv->status); | 2333 | int exit_pending; |
2541 | 2334 | ||
2542 | IWL_DEBUG_INFO(priv, DRV_NAME " is going down\n"); | 2335 | IWL_DEBUG_INFO(priv, DRV_NAME " is going down\n"); |
2543 | 2336 | ||
@@ -2563,9 +2356,6 @@ static void __iwl_down(struct iwl_priv *priv) | |||
2563 | priv->bt_full_concurrent = false; | 2356 | priv->bt_full_concurrent = false; |
2564 | priv->bt_ci_compliance = 0; | 2357 | priv->bt_ci_compliance = 0; |
2565 | 2358 | ||
2566 | /* Unblock any waiting calls */ | ||
2567 | wake_up_interruptible_all(&priv->wait_command_queue); | ||
2568 | |||
2569 | /* Wipe out the EXIT_PENDING status bit if we are not actually | 2359 | /* Wipe out the EXIT_PENDING status bit if we are not actually |
2570 | * exiting the module */ | 2360 | * exiting the module */ |
2571 | if (!exit_pending) | 2361 | if (!exit_pending) |
@@ -2607,8 +2397,7 @@ static void __iwl_down(struct iwl_priv *priv) | |||
2607 | STATUS_EXIT_PENDING; | 2397 | STATUS_EXIT_PENDING; |
2608 | 2398 | ||
2609 | /* device going down, Stop using ICT table */ | 2399 | /* device going down, Stop using ICT table */ |
2610 | if (priv->cfg->ops->lib->isr_ops.disable) | 2400 | iwl_disable_ict(priv); |
2611 | priv->cfg->ops->lib->isr_ops.disable(priv); | ||
2612 | 2401 | ||
2613 | iwlagn_txq_ctx_stop(priv); | 2402 | iwlagn_txq_ctx_stop(priv); |
2614 | iwlagn_rxq_stop(priv); | 2403 | iwlagn_rxq_stop(priv); |
@@ -2624,8 +2413,6 @@ static void __iwl_down(struct iwl_priv *priv) | |||
2624 | iwl_apm_stop(priv); | 2413 | iwl_apm_stop(priv); |
2625 | 2414 | ||
2626 | exit: | 2415 | exit: |
2627 | memset(&priv->card_alive, 0, sizeof(struct iwl_alive_resp)); | ||
2628 | |||
2629 | dev_kfree_skb(priv->beacon_skb); | 2416 | dev_kfree_skb(priv->beacon_skb); |
2630 | priv->beacon_skb = NULL; | 2417 | priv->beacon_skb = NULL; |
2631 | 2418 | ||
@@ -2704,11 +2491,6 @@ static int __iwl_up(struct iwl_priv *priv) | |||
2704 | return -EIO; | 2491 | return -EIO; |
2705 | } | 2492 | } |
2706 | 2493 | ||
2707 | if (!priv->ucode_data_backup.v_addr || !priv->ucode_data.v_addr) { | ||
2708 | IWL_ERR(priv, "ucode not available for device bringup\n"); | ||
2709 | return -EIO; | ||
2710 | } | ||
2711 | |||
2712 | for_each_context(priv, ctx) { | 2494 | for_each_context(priv, ctx) { |
2713 | ret = iwlagn_alloc_bcast_station(priv, ctx); | 2495 | ret = iwlagn_alloc_bcast_station(priv, ctx); |
2714 | if (ret) { | 2496 | if (ret) { |
@@ -2740,12 +2522,6 @@ static int __iwl_up(struct iwl_priv *priv) | |||
2740 | 2522 | ||
2741 | iwl_write32(priv, CSR_INT, 0xFFFFFFFF); | 2523 | iwl_write32(priv, CSR_INT, 0xFFFFFFFF); |
2742 | 2524 | ||
2743 | /* must be initialised before iwl_hw_nic_init */ | ||
2744 | if (priv->valid_contexts != BIT(IWL_RXON_CTX_BSS)) | ||
2745 | priv->cmd_queue = IWL_IPAN_CMD_QUEUE_NUM; | ||
2746 | else | ||
2747 | priv->cmd_queue = IWL_DEFAULT_CMD_QUEUE_NUM; | ||
2748 | |||
2749 | ret = iwlagn_hw_nic_init(priv); | 2525 | ret = iwlagn_hw_nic_init(priv); |
2750 | if (ret) { | 2526 | if (ret) { |
2751 | IWL_ERR(priv, "Unable to init nic\n"); | 2527 | IWL_ERR(priv, "Unable to init nic\n"); |
@@ -2765,18 +2541,12 @@ static int __iwl_up(struct iwl_priv *priv) | |||
2765 | iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); | 2541 | iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); |
2766 | iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); | 2542 | iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); |
2767 | 2543 | ||
2768 | /* Copy original ucode data image from disk into backup cache. | ||
2769 | * This will be used to initialize the on-board processor's | ||
2770 | * data SRAM for a clean start when the runtime program first loads. */ | ||
2771 | memcpy(priv->ucode_data_backup.v_addr, priv->ucode_data.v_addr, | ||
2772 | priv->ucode_data.len); | ||
2773 | |||
2774 | for (i = 0; i < MAX_HW_RESTARTS; i++) { | 2544 | for (i = 0; i < MAX_HW_RESTARTS; i++) { |
2775 | 2545 | ||
2776 | /* load bootstrap state machine, | 2546 | /* load bootstrap state machine, |
2777 | * load bootstrap program into processor's memory, | 2547 | * load bootstrap program into processor's memory, |
2778 | * prepare to load the "initialize" uCode */ | 2548 | * prepare to load the "initialize" uCode */ |
2779 | ret = priv->cfg->ops->lib->load_ucode(priv); | 2549 | ret = iwlagn_load_ucode(priv); |
2780 | 2550 | ||
2781 | if (ret) { | 2551 | if (ret) { |
2782 | IWL_ERR(priv, "Unable to set up bootstrap uCode: %d\n", | 2552 | IWL_ERR(priv, "Unable to set up bootstrap uCode: %d\n", |
@@ -2814,11 +2584,14 @@ static void iwl_bg_init_alive_start(struct work_struct *data) | |||
2814 | struct iwl_priv *priv = | 2584 | struct iwl_priv *priv = |
2815 | container_of(data, struct iwl_priv, init_alive_start.work); | 2585 | container_of(data, struct iwl_priv, init_alive_start.work); |
2816 | 2586 | ||
2817 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | 2587 | mutex_lock(&priv->mutex); |
2588 | |||
2589 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) { | ||
2590 | mutex_unlock(&priv->mutex); | ||
2818 | return; | 2591 | return; |
2592 | } | ||
2819 | 2593 | ||
2820 | mutex_lock(&priv->mutex); | 2594 | iwlagn_init_alive_start(priv); |
2821 | priv->cfg->ops->lib->init_alive_start(priv); | ||
2822 | mutex_unlock(&priv->mutex); | 2595 | mutex_unlock(&priv->mutex); |
2823 | } | 2596 | } |
2824 | 2597 | ||
@@ -2827,15 +2600,15 @@ static void iwl_bg_alive_start(struct work_struct *data) | |||
2827 | struct iwl_priv *priv = | 2600 | struct iwl_priv *priv = |
2828 | container_of(data, struct iwl_priv, alive_start.work); | 2601 | container_of(data, struct iwl_priv, alive_start.work); |
2829 | 2602 | ||
2603 | mutex_lock(&priv->mutex); | ||
2830 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | 2604 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) |
2831 | return; | 2605 | goto unlock; |
2832 | 2606 | ||
2833 | /* enable dram interrupt */ | 2607 | /* enable dram interrupt */ |
2834 | if (priv->cfg->ops->lib->isr_ops.reset) | 2608 | iwl_reset_ict(priv); |
2835 | priv->cfg->ops->lib->isr_ops.reset(priv); | ||
2836 | 2609 | ||
2837 | mutex_lock(&priv->mutex); | ||
2838 | iwl_alive_start(priv); | 2610 | iwl_alive_start(priv); |
2611 | unlock: | ||
2839 | mutex_unlock(&priv->mutex); | 2612 | mutex_unlock(&priv->mutex); |
2840 | } | 2613 | } |
2841 | 2614 | ||
@@ -3063,6 +2836,9 @@ static int iwl_mac_setup_register(struct iwl_priv *priv, | |||
3063 | hw->flags |= IEEE80211_HW_SUPPORTS_DYNAMIC_SMPS | | 2836 | hw->flags |= IEEE80211_HW_SUPPORTS_DYNAMIC_SMPS | |
3064 | IEEE80211_HW_SUPPORTS_STATIC_SMPS; | 2837 | IEEE80211_HW_SUPPORTS_STATIC_SMPS; |
3065 | 2838 | ||
2839 | if (capa->flags & IWL_UCODE_TLV_FLAGS_MFP) | ||
2840 | hw->flags |= IEEE80211_HW_MFP_CAPABLE; | ||
2841 | |||
3066 | hw->sta_data_size = sizeof(struct iwl_station_priv); | 2842 | hw->sta_data_size = sizeof(struct iwl_station_priv); |
3067 | hw->vif_data_size = sizeof(struct iwl_vif_priv); | 2843 | hw->vif_data_size = sizeof(struct iwl_vif_priv); |
3068 | 2844 | ||
@@ -3112,7 +2888,7 @@ static int iwl_mac_setup_register(struct iwl_priv *priv, | |||
3112 | } | 2888 | } |
3113 | 2889 | ||
3114 | 2890 | ||
3115 | int iwlagn_mac_start(struct ieee80211_hw *hw) | 2891 | static int iwlagn_mac_start(struct ieee80211_hw *hw) |
3116 | { | 2892 | { |
3117 | struct iwl_priv *priv = hw->priv; | 2893 | struct iwl_priv *priv = hw->priv; |
3118 | int ret; | 2894 | int ret; |
@@ -3153,7 +2929,7 @@ out: | |||
3153 | return 0; | 2929 | return 0; |
3154 | } | 2930 | } |
3155 | 2931 | ||
3156 | void iwlagn_mac_stop(struct ieee80211_hw *hw) | 2932 | static void iwlagn_mac_stop(struct ieee80211_hw *hw) |
3157 | { | 2933 | { |
3158 | struct iwl_priv *priv = hw->priv; | 2934 | struct iwl_priv *priv = hw->priv; |
3159 | 2935 | ||
@@ -3176,7 +2952,7 @@ void iwlagn_mac_stop(struct ieee80211_hw *hw) | |||
3176 | IWL_DEBUG_MAC80211(priv, "leave\n"); | 2952 | IWL_DEBUG_MAC80211(priv, "leave\n"); |
3177 | } | 2953 | } |
3178 | 2954 | ||
3179 | void iwlagn_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb) | 2955 | static void iwlagn_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb) |
3180 | { | 2956 | { |
3181 | struct iwl_priv *priv = hw->priv; | 2957 | struct iwl_priv *priv = hw->priv; |
3182 | 2958 | ||
@@ -3191,11 +2967,11 @@ void iwlagn_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb) | |||
3191 | IWL_DEBUG_MACDUMP(priv, "leave\n"); | 2967 | IWL_DEBUG_MACDUMP(priv, "leave\n"); |
3192 | } | 2968 | } |
3193 | 2969 | ||
3194 | void iwlagn_mac_update_tkip_key(struct ieee80211_hw *hw, | 2970 | static void iwlagn_mac_update_tkip_key(struct ieee80211_hw *hw, |
3195 | struct ieee80211_vif *vif, | 2971 | struct ieee80211_vif *vif, |
3196 | struct ieee80211_key_conf *keyconf, | 2972 | struct ieee80211_key_conf *keyconf, |
3197 | struct ieee80211_sta *sta, | 2973 | struct ieee80211_sta *sta, |
3198 | u32 iv32, u16 *phase1key) | 2974 | u32 iv32, u16 *phase1key) |
3199 | { | 2975 | { |
3200 | struct iwl_priv *priv = hw->priv; | 2976 | struct iwl_priv *priv = hw->priv; |
3201 | struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv; | 2977 | struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv; |
@@ -3208,9 +2984,10 @@ void iwlagn_mac_update_tkip_key(struct ieee80211_hw *hw, | |||
3208 | IWL_DEBUG_MAC80211(priv, "leave\n"); | 2984 | IWL_DEBUG_MAC80211(priv, "leave\n"); |
3209 | } | 2985 | } |
3210 | 2986 | ||
3211 | int iwlagn_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd, | 2987 | static int iwlagn_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd, |
3212 | struct ieee80211_vif *vif, struct ieee80211_sta *sta, | 2988 | struct ieee80211_vif *vif, |
3213 | struct ieee80211_key_conf *key) | 2989 | struct ieee80211_sta *sta, |
2990 | struct ieee80211_key_conf *key) | ||
3214 | { | 2991 | { |
3215 | struct iwl_priv *priv = hw->priv; | 2992 | struct iwl_priv *priv = hw->priv; |
3216 | struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv; | 2993 | struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv; |
@@ -3285,11 +3062,11 @@ int iwlagn_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd, | |||
3285 | return ret; | 3062 | return ret; |
3286 | } | 3063 | } |
3287 | 3064 | ||
3288 | int iwlagn_mac_ampdu_action(struct ieee80211_hw *hw, | 3065 | static int iwlagn_mac_ampdu_action(struct ieee80211_hw *hw, |
3289 | struct ieee80211_vif *vif, | 3066 | struct ieee80211_vif *vif, |
3290 | enum ieee80211_ampdu_mlme_action action, | 3067 | enum ieee80211_ampdu_mlme_action action, |
3291 | struct ieee80211_sta *sta, u16 tid, u16 *ssn, | 3068 | struct ieee80211_sta *sta, u16 tid, u16 *ssn, |
3292 | u8 buf_size) | 3069 | u8 buf_size) |
3293 | { | 3070 | { |
3294 | struct iwl_priv *priv = hw->priv; | 3071 | struct iwl_priv *priv = hw->priv; |
3295 | int ret = -EINVAL; | 3072 | int ret = -EINVAL; |
@@ -3348,6 +3125,10 @@ int iwlagn_mac_ampdu_action(struct ieee80211_hw *hw, | |||
3348 | } | 3125 | } |
3349 | break; | 3126 | break; |
3350 | case IEEE80211_AMPDU_TX_OPERATIONAL: | 3127 | case IEEE80211_AMPDU_TX_OPERATIONAL: |
3128 | buf_size = min_t(int, buf_size, LINK_QUAL_AGG_FRAME_LIMIT_DEF); | ||
3129 | |||
3130 | iwlagn_txq_agg_queue_setup(priv, sta, tid, buf_size); | ||
3131 | |||
3351 | /* | 3132 | /* |
3352 | * If the limit is 0, then it wasn't initialised yet, | 3133 | * If the limit is 0, then it wasn't initialised yet, |
3353 | * use the default. We can do that since we take the | 3134 | * use the default. We can do that since we take the |
@@ -3392,9 +3173,9 @@ int iwlagn_mac_ampdu_action(struct ieee80211_hw *hw, | |||
3392 | return ret; | 3173 | return ret; |
3393 | } | 3174 | } |
3394 | 3175 | ||
3395 | int iwlagn_mac_sta_add(struct ieee80211_hw *hw, | 3176 | static int iwlagn_mac_sta_add(struct ieee80211_hw *hw, |
3396 | struct ieee80211_vif *vif, | 3177 | struct ieee80211_vif *vif, |
3397 | struct ieee80211_sta *sta) | 3178 | struct ieee80211_sta *sta) |
3398 | { | 3179 | { |
3399 | struct iwl_priv *priv = hw->priv; | 3180 | struct iwl_priv *priv = hw->priv; |
3400 | struct iwl_station_priv *sta_priv = (void *)sta->drv_priv; | 3181 | struct iwl_station_priv *sta_priv = (void *)sta->drv_priv; |
@@ -3435,8 +3216,8 @@ int iwlagn_mac_sta_add(struct ieee80211_hw *hw, | |||
3435 | return 0; | 3216 | return 0; |
3436 | } | 3217 | } |
3437 | 3218 | ||
3438 | void iwlagn_mac_channel_switch(struct ieee80211_hw *hw, | 3219 | static void iwlagn_mac_channel_switch(struct ieee80211_hw *hw, |
3439 | struct ieee80211_channel_switch *ch_switch) | 3220 | struct ieee80211_channel_switch *ch_switch) |
3440 | { | 3221 | { |
3441 | struct iwl_priv *priv = hw->priv; | 3222 | struct iwl_priv *priv = hw->priv; |
3442 | const struct iwl_channel_info *ch_info; | 3223 | const struct iwl_channel_info *ch_info; |
@@ -3457,21 +3238,22 @@ void iwlagn_mac_channel_switch(struct ieee80211_hw *hw, | |||
3457 | 3238 | ||
3458 | IWL_DEBUG_MAC80211(priv, "enter\n"); | 3239 | IWL_DEBUG_MAC80211(priv, "enter\n"); |
3459 | 3240 | ||
3241 | mutex_lock(&priv->mutex); | ||
3242 | |||
3460 | if (iwl_is_rfkill(priv)) | 3243 | if (iwl_is_rfkill(priv)) |
3461 | goto out_exit; | 3244 | goto out; |
3462 | 3245 | ||
3463 | if (test_bit(STATUS_EXIT_PENDING, &priv->status) || | 3246 | if (test_bit(STATUS_EXIT_PENDING, &priv->status) || |
3464 | test_bit(STATUS_SCANNING, &priv->status)) | 3247 | test_bit(STATUS_SCANNING, &priv->status)) |
3465 | goto out_exit; | 3248 | goto out; |
3466 | 3249 | ||
3467 | if (!iwl_is_associated_ctx(ctx)) | 3250 | if (!iwl_is_associated_ctx(ctx)) |
3468 | goto out_exit; | 3251 | goto out; |
3469 | 3252 | ||
3470 | /* channel switch in progress */ | 3253 | /* channel switch in progress */ |
3471 | if (priv->switch_rxon.switch_in_progress == true) | 3254 | if (priv->switch_rxon.switch_in_progress == true) |
3472 | goto out_exit; | 3255 | goto out; |
3473 | 3256 | ||
3474 | mutex_lock(&priv->mutex); | ||
3475 | if (priv->cfg->ops->lib->set_channel_switch) { | 3257 | if (priv->cfg->ops->lib->set_channel_switch) { |
3476 | 3258 | ||
3477 | ch = channel->hw_value; | 3259 | ch = channel->hw_value; |
@@ -3527,16 +3309,15 @@ void iwlagn_mac_channel_switch(struct ieee80211_hw *hw, | |||
3527 | } | 3309 | } |
3528 | out: | 3310 | out: |
3529 | mutex_unlock(&priv->mutex); | 3311 | mutex_unlock(&priv->mutex); |
3530 | out_exit: | ||
3531 | if (!priv->switch_rxon.switch_in_progress) | 3312 | if (!priv->switch_rxon.switch_in_progress) |
3532 | ieee80211_chswitch_done(ctx->vif, false); | 3313 | ieee80211_chswitch_done(ctx->vif, false); |
3533 | IWL_DEBUG_MAC80211(priv, "leave\n"); | 3314 | IWL_DEBUG_MAC80211(priv, "leave\n"); |
3534 | } | 3315 | } |
3535 | 3316 | ||
3536 | void iwlagn_configure_filter(struct ieee80211_hw *hw, | 3317 | static void iwlagn_configure_filter(struct ieee80211_hw *hw, |
3537 | unsigned int changed_flags, | 3318 | unsigned int changed_flags, |
3538 | unsigned int *total_flags, | 3319 | unsigned int *total_flags, |
3539 | u64 multicast) | 3320 | u64 multicast) |
3540 | { | 3321 | { |
3541 | struct iwl_priv *priv = hw->priv; | 3322 | struct iwl_priv *priv = hw->priv; |
3542 | __le32 filter_or = 0, filter_nand = 0; | 3323 | __le32 filter_or = 0, filter_nand = 0; |
@@ -3583,7 +3364,7 @@ void iwlagn_configure_filter(struct ieee80211_hw *hw, | |||
3583 | FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL; | 3364 | FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL; |
3584 | } | 3365 | } |
3585 | 3366 | ||
3586 | void iwlagn_mac_flush(struct ieee80211_hw *hw, bool drop) | 3367 | static void iwlagn_mac_flush(struct ieee80211_hw *hw, bool drop) |
3587 | { | 3368 | { |
3588 | struct iwl_priv *priv = hw->priv; | 3369 | struct iwl_priv *priv = hw->priv; |
3589 | 3370 | ||
@@ -3750,12 +3531,8 @@ static void iwl_setup_deferred_work(struct iwl_priv *priv) | |||
3750 | priv->watchdog.data = (unsigned long)priv; | 3531 | priv->watchdog.data = (unsigned long)priv; |
3751 | priv->watchdog.function = iwl_bg_watchdog; | 3532 | priv->watchdog.function = iwl_bg_watchdog; |
3752 | 3533 | ||
3753 | if (!priv->cfg->base_params->use_isr_legacy) | 3534 | tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long)) |
3754 | tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long)) | 3535 | iwl_irq_tasklet, (unsigned long)priv); |
3755 | iwl_irq_tasklet, (unsigned long)priv); | ||
3756 | else | ||
3757 | tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long)) | ||
3758 | iwl_irq_tasklet_legacy, (unsigned long)priv); | ||
3759 | } | 3536 | } |
3760 | 3537 | ||
3761 | static void iwl_cancel_deferred_work(struct iwl_priv *priv) | 3538 | static void iwl_cancel_deferred_work(struct iwl_priv *priv) |
@@ -3808,7 +3585,6 @@ static int iwl_init_drv(struct iwl_priv *priv) | |||
3808 | INIT_LIST_HEAD(&priv->free_frames); | 3585 | INIT_LIST_HEAD(&priv->free_frames); |
3809 | 3586 | ||
3810 | mutex_init(&priv->mutex); | 3587 | mutex_init(&priv->mutex); |
3811 | mutex_init(&priv->sync_cmd_mutex); | ||
3812 | 3588 | ||
3813 | priv->ieee_channels = NULL; | 3589 | priv->ieee_channels = NULL; |
3814 | priv->ieee_rates = NULL; | 3590 | priv->ieee_rates = NULL; |
@@ -3907,12 +3683,13 @@ struct ieee80211_ops iwlagn_hw_ops = { | |||
3907 | .offchannel_tx_cancel_wait = iwl_mac_offchannel_tx_cancel_wait, | 3683 | .offchannel_tx_cancel_wait = iwl_mac_offchannel_tx_cancel_wait, |
3908 | }; | 3684 | }; |
3909 | 3685 | ||
3910 | static void iwl_hw_detect(struct iwl_priv *priv) | 3686 | static u32 iwl_hw_detect(struct iwl_priv *priv) |
3911 | { | 3687 | { |
3912 | priv->hw_rev = _iwl_read32(priv, CSR_HW_REV); | 3688 | u8 rev_id; |
3913 | priv->hw_wa_rev = _iwl_read32(priv, CSR_HW_REV_WA_REG); | 3689 | |
3914 | priv->rev_id = priv->pci_dev->revision; | 3690 | pci_read_config_byte(priv->pci_dev, PCI_REVISION_ID, &rev_id); |
3915 | IWL_DEBUG_INFO(priv, "HW Revision ID = 0x%X\n", priv->rev_id); | 3691 | IWL_DEBUG_INFO(priv, "HW Revision ID = 0x%X\n", rev_id); |
3692 | return iwl_read32(priv, CSR_HW_REV); | ||
3916 | } | 3693 | } |
3917 | 3694 | ||
3918 | static int iwl_set_hw_params(struct iwl_priv *priv) | 3695 | static int iwl_set_hw_params(struct iwl_priv *priv) |
@@ -3963,19 +3740,12 @@ static int iwl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) | |||
3963 | struct iwl_cfg *cfg = (struct iwl_cfg *)(ent->driver_data); | 3740 | struct iwl_cfg *cfg = (struct iwl_cfg *)(ent->driver_data); |
3964 | unsigned long flags; | 3741 | unsigned long flags; |
3965 | u16 pci_cmd, num_mac; | 3742 | u16 pci_cmd, num_mac; |
3743 | u32 hw_rev; | ||
3966 | 3744 | ||
3967 | /************************ | 3745 | /************************ |
3968 | * 1. Allocating HW data | 3746 | * 1. Allocating HW data |
3969 | ************************/ | 3747 | ************************/ |
3970 | 3748 | ||
3971 | /* Disabling hardware scan means that mac80211 will perform scans | ||
3972 | * "the hard way", rather than using device's scan. */ | ||
3973 | if (cfg->mod_params->disable_hw_scan) { | ||
3974 | dev_printk(KERN_DEBUG, &(pdev->dev), | ||
3975 | "sw scan support is deprecated\n"); | ||
3976 | iwlagn_hw_ops.hw_scan = NULL; | ||
3977 | } | ||
3978 | |||
3979 | hw = iwl_alloc_all(cfg); | 3749 | hw = iwl_alloc_all(cfg); |
3980 | if (!hw) { | 3750 | if (!hw) { |
3981 | err = -ENOMEM; | 3751 | err = -ENOMEM; |
@@ -4116,9 +3886,9 @@ static int iwl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) | |||
4116 | */ | 3886 | */ |
4117 | iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET); | 3887 | iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET); |
4118 | 3888 | ||
4119 | iwl_hw_detect(priv); | 3889 | hw_rev = iwl_hw_detect(priv); |
4120 | IWL_INFO(priv, "Detected %s, REV=0x%X\n", | 3890 | IWL_INFO(priv, "Detected %s, REV=0x%X\n", |
4121 | priv->cfg->name, priv->hw_rev); | 3891 | priv->cfg->name, hw_rev); |
4122 | 3892 | ||
4123 | /* We disable the RETRY_TIMEOUT register (0x41) to keep | 3893 | /* We disable the RETRY_TIMEOUT register (0x41) to keep |
4124 | * PCI Tx retries from interfering with C3 CPU state */ | 3894 | * PCI Tx retries from interfering with C3 CPU state */ |
@@ -4134,7 +3904,7 @@ static int iwl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) | |||
4134 | * 4. Read EEPROM | 3904 | * 4. Read EEPROM |
4135 | *****************/ | 3905 | *****************/ |
4136 | /* Read the EEPROM */ | 3906 | /* Read the EEPROM */ |
4137 | err = iwl_eeprom_init(priv); | 3907 | err = iwl_eeprom_init(priv, hw_rev); |
4138 | if (err) { | 3908 | if (err) { |
4139 | IWL_ERR(priv, "Unable to init EEPROM\n"); | 3909 | IWL_ERR(priv, "Unable to init EEPROM\n"); |
4140 | goto out_iounmap; | 3910 | goto out_iounmap; |
@@ -4186,10 +3956,9 @@ static int iwl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) | |||
4186 | 3956 | ||
4187 | pci_enable_msi(priv->pci_dev); | 3957 | pci_enable_msi(priv->pci_dev); |
4188 | 3958 | ||
4189 | if (priv->cfg->ops->lib->isr_ops.alloc) | 3959 | iwl_alloc_isr_ict(priv); |
4190 | priv->cfg->ops->lib->isr_ops.alloc(priv); | ||
4191 | 3960 | ||
4192 | err = request_irq(priv->pci_dev->irq, priv->cfg->ops->lib->isr_ops.isr, | 3961 | err = request_irq(priv->pci_dev->irq, iwl_isr_ict, |
4193 | IRQF_SHARED, DRV_NAME, priv); | 3962 | IRQF_SHARED, DRV_NAME, priv); |
4194 | if (err) { | 3963 | if (err) { |
4195 | IWL_ERR(priv, "Error allocating IRQ %d\n", priv->pci_dev->irq); | 3964 | IWL_ERR(priv, "Error allocating IRQ %d\n", priv->pci_dev->irq); |
@@ -4236,8 +4005,7 @@ static int iwl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) | |||
4236 | destroy_workqueue(priv->workqueue); | 4005 | destroy_workqueue(priv->workqueue); |
4237 | priv->workqueue = NULL; | 4006 | priv->workqueue = NULL; |
4238 | free_irq(priv->pci_dev->irq, priv); | 4007 | free_irq(priv->pci_dev->irq, priv); |
4239 | if (priv->cfg->ops->lib->isr_ops.free) | 4008 | iwl_free_isr_ict(priv); |
4240 | priv->cfg->ops->lib->isr_ops.free(priv); | ||
4241 | out_disable_msi: | 4009 | out_disable_msi: |
4242 | pci_disable_msi(priv->pci_dev); | 4010 | pci_disable_msi(priv->pci_dev); |
4243 | iwl_uninit_drv(priv); | 4011 | iwl_uninit_drv(priv); |
@@ -4335,8 +4103,7 @@ static void __devexit iwl_pci_remove(struct pci_dev *pdev) | |||
4335 | 4103 | ||
4336 | iwl_uninit_drv(priv); | 4104 | iwl_uninit_drv(priv); |
4337 | 4105 | ||
4338 | if (priv->cfg->ops->lib->isr_ops.free) | 4106 | iwl_free_isr_ict(priv); |
4339 | priv->cfg->ops->lib->isr_ops.free(priv); | ||
4340 | 4107 | ||
4341 | dev_kfree_skb(priv->beacon_skb); | 4108 | dev_kfree_skb(priv->beacon_skb); |
4342 | 4109 | ||
@@ -4585,43 +4352,21 @@ module_exit(iwl_exit); | |||
4585 | module_init(iwl_init); | 4352 | module_init(iwl_init); |
4586 | 4353 | ||
4587 | #ifdef CONFIG_IWLWIFI_DEBUG | 4354 | #ifdef CONFIG_IWLWIFI_DEBUG |
4588 | module_param_named(debug50, iwl_debug_level, uint, S_IRUGO); | ||
4589 | MODULE_PARM_DESC(debug50, "50XX debug output mask (deprecated)"); | ||
4590 | module_param_named(debug, iwl_debug_level, uint, S_IRUGO | S_IWUSR); | 4355 | module_param_named(debug, iwl_debug_level, uint, S_IRUGO | S_IWUSR); |
4591 | MODULE_PARM_DESC(debug, "debug output mask"); | 4356 | MODULE_PARM_DESC(debug, "debug output mask"); |
4592 | #endif | 4357 | #endif |
4593 | 4358 | ||
4594 | module_param_named(swcrypto50, iwlagn_mod_params.sw_crypto, bool, S_IRUGO); | ||
4595 | MODULE_PARM_DESC(swcrypto50, | ||
4596 | "using crypto in software (default 0 [hardware]) (deprecated)"); | ||
4597 | module_param_named(swcrypto, iwlagn_mod_params.sw_crypto, int, S_IRUGO); | 4359 | module_param_named(swcrypto, iwlagn_mod_params.sw_crypto, int, S_IRUGO); |
4598 | MODULE_PARM_DESC(swcrypto, "using crypto in software (default 0 [hardware])"); | 4360 | MODULE_PARM_DESC(swcrypto, "using crypto in software (default 0 [hardware])"); |
4599 | module_param_named(queues_num50, | ||
4600 | iwlagn_mod_params.num_of_queues, int, S_IRUGO); | ||
4601 | MODULE_PARM_DESC(queues_num50, | ||
4602 | "number of hw queues in 50xx series (deprecated)"); | ||
4603 | module_param_named(queues_num, iwlagn_mod_params.num_of_queues, int, S_IRUGO); | 4361 | module_param_named(queues_num, iwlagn_mod_params.num_of_queues, int, S_IRUGO); |
4604 | MODULE_PARM_DESC(queues_num, "number of hw queues."); | 4362 | MODULE_PARM_DESC(queues_num, "number of hw queues."); |
4605 | module_param_named(11n_disable50, iwlagn_mod_params.disable_11n, int, S_IRUGO); | ||
4606 | MODULE_PARM_DESC(11n_disable50, "disable 50XX 11n functionality (deprecated)"); | ||
4607 | module_param_named(11n_disable, iwlagn_mod_params.disable_11n, int, S_IRUGO); | 4363 | module_param_named(11n_disable, iwlagn_mod_params.disable_11n, int, S_IRUGO); |
4608 | MODULE_PARM_DESC(11n_disable, "disable 11n functionality"); | 4364 | MODULE_PARM_DESC(11n_disable, "disable 11n functionality"); |
4609 | module_param_named(amsdu_size_8K50, iwlagn_mod_params.amsdu_size_8K, | ||
4610 | int, S_IRUGO); | ||
4611 | MODULE_PARM_DESC(amsdu_size_8K50, | ||
4612 | "enable 8K amsdu size in 50XX series (deprecated)"); | ||
4613 | module_param_named(amsdu_size_8K, iwlagn_mod_params.amsdu_size_8K, | 4365 | module_param_named(amsdu_size_8K, iwlagn_mod_params.amsdu_size_8K, |
4614 | int, S_IRUGO); | 4366 | int, S_IRUGO); |
4615 | MODULE_PARM_DESC(amsdu_size_8K, "enable 8K amsdu size"); | 4367 | MODULE_PARM_DESC(amsdu_size_8K, "enable 8K amsdu size"); |
4616 | module_param_named(fw_restart50, iwlagn_mod_params.restart_fw, int, S_IRUGO); | ||
4617 | MODULE_PARM_DESC(fw_restart50, | ||
4618 | "restart firmware in case of error (deprecated)"); | ||
4619 | module_param_named(fw_restart, iwlagn_mod_params.restart_fw, int, S_IRUGO); | 4368 | module_param_named(fw_restart, iwlagn_mod_params.restart_fw, int, S_IRUGO); |
4620 | MODULE_PARM_DESC(fw_restart, "restart firmware in case of error"); | 4369 | MODULE_PARM_DESC(fw_restart, "restart firmware in case of error"); |
4621 | module_param_named( | ||
4622 | disable_hw_scan, iwlagn_mod_params.disable_hw_scan, int, S_IRUGO); | ||
4623 | MODULE_PARM_DESC(disable_hw_scan, | ||
4624 | "disable hardware scanning (default 0) (deprecated)"); | ||
4625 | 4370 | ||
4626 | module_param_named(ucode_alternative, iwlagn_wanted_ucode_alternative, int, | 4371 | module_param_named(ucode_alternative, iwlagn_wanted_ucode_alternative, int, |
4627 | S_IRUGO); | 4372 | S_IRUGO); |