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-rw-r--r--drivers/net/wireless/ath/ath.h1
-rw-r--r--drivers/net/wireless/ath/ath9k/ar5008_phy.c45
-rw-r--r--drivers/net/wireless/ath/ath9k/ar9002_calib.c43
-rw-r--r--drivers/net/wireless/ath/ath9k/ar9003_hw.c90
-rw-r--r--drivers/net/wireless/ath/ath9k/ar9485_initvals.h925
-rw-r--r--drivers/net/wireless/ath/ath9k/ath9k.h4
-rw-r--r--drivers/net/wireless/ath/ath9k/beacon.c97
-rw-r--r--drivers/net/wireless/ath/ath9k/debug.c94
-rw-r--r--drivers/net/wireless/ath/ath9k/eeprom_9287.c6
-rw-r--r--drivers/net/wireless/ath/ath9k/eeprom_def.c7
-rw-r--r--drivers/net/wireless/ath/ath9k/gpio.c14
-rw-r--r--drivers/net/wireless/ath/ath9k/hif_usb.c9
-rw-r--r--drivers/net/wireless/ath/ath9k/htc.h2
-rw-r--r--drivers/net/wireless/ath/ath9k/htc_drv_beacon.c9
-rw-r--r--drivers/net/wireless/ath/ath9k/htc_drv_init.c33
-rw-r--r--drivers/net/wireless/ath/ath9k/hw.c181
-rw-r--r--drivers/net/wireless/ath/ath9k/hw.h61
-rw-r--r--drivers/net/wireless/ath/ath9k/init.c53
-rw-r--r--drivers/net/wireless/ath/ath9k/mac.c116
-rw-r--r--drivers/net/wireless/ath/ath9k/main.c16
-rw-r--r--drivers/net/wireless/ath/ath9k/phy.h14
-rw-r--r--drivers/net/wireless/ath/ath9k/rc.c2
-rw-r--r--drivers/net/wireless/ath/ath9k/reg.h1
-rw-r--r--drivers/net/wireless/ath/ath9k/xmit.c33
-rw-r--r--drivers/net/wireless/ath/carl9170/usb.c2
-rw-r--r--drivers/net/wireless/ath/key.c32
26 files changed, 436 insertions, 1454 deletions
diff --git a/drivers/net/wireless/ath/ath.h b/drivers/net/wireless/ath/ath.h
index a6c6a466000..6d7105b7e8f 100644
--- a/drivers/net/wireless/ath/ath.h
+++ b/drivers/net/wireless/ath/ath.h
@@ -119,6 +119,7 @@ struct ath_ops {
119 void (*write)(void *, u32 val, u32 reg_offset); 119 void (*write)(void *, u32 val, u32 reg_offset);
120 void (*enable_write_buffer)(void *); 120 void (*enable_write_buffer)(void *);
121 void (*write_flush) (void *); 121 void (*write_flush) (void *);
122 u32 (*rmw)(void *, u32 reg_offset, u32 set, u32 clr);
122}; 123};
123 124
124struct ath_common; 125struct ath_common;
diff --git a/drivers/net/wireless/ath/ath9k/ar5008_phy.c b/drivers/net/wireless/ath/ath9k/ar5008_phy.c
index ffcf44a4058..4361704fe0d 100644
--- a/drivers/net/wireless/ath/ath9k/ar5008_phy.c
+++ b/drivers/net/wireless/ath/ath9k/ar5008_phy.c
@@ -44,6 +44,34 @@ static const int m1ThreshExt_off = 127;
44static const int m2ThreshExt_off = 127; 44static const int m2ThreshExt_off = 127;
45 45
46 46
47static void ar5008_rf_bank_setup(u32 *bank, struct ar5416IniArray *array,
48 int col)
49{
50 int i;
51
52 for (i = 0; i < array->ia_rows; i++)
53 bank[i] = INI_RA(array, i, col);
54}
55
56
57#define REG_WRITE_RF_ARRAY(iniarray, regData, regWr) \
58 ar5008_write_rf_array(ah, iniarray, regData, &(regWr))
59
60static void ar5008_write_rf_array(struct ath_hw *ah, struct ar5416IniArray *array,
61 u32 *data, unsigned int *writecnt)
62{
63 int r;
64
65 ENABLE_REGWRITE_BUFFER(ah);
66
67 for (r = 0; r < array->ia_rows; r++) {
68 REG_WRITE(ah, INI_RA(array, r, 0), data[r]);
69 DO_DELAY(*writecnt);
70 }
71
72 REGWRITE_BUFFER_FLUSH(ah);
73}
74
47/** 75/**
48 * ar5008_hw_phy_modify_rx_buffer() - perform analog swizzling of parameters 76 * ar5008_hw_phy_modify_rx_buffer() - perform analog swizzling of parameters
49 * @rfbuf: 77 * @rfbuf:
@@ -530,16 +558,16 @@ static bool ar5008_hw_set_rf_regs(struct ath_hw *ah,
530 eepMinorRev = ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV); 558 eepMinorRev = ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV);
531 559
532 /* Setup Bank 0 Write */ 560 /* Setup Bank 0 Write */
533 RF_BANK_SETUP(ah->analogBank0Data, &ah->iniBank0, 1); 561 ar5008_rf_bank_setup(ah->analogBank0Data, &ah->iniBank0, 1);
534 562
535 /* Setup Bank 1 Write */ 563 /* Setup Bank 1 Write */
536 RF_BANK_SETUP(ah->analogBank1Data, &ah->iniBank1, 1); 564 ar5008_rf_bank_setup(ah->analogBank1Data, &ah->iniBank1, 1);
537 565
538 /* Setup Bank 2 Write */ 566 /* Setup Bank 2 Write */
539 RF_BANK_SETUP(ah->analogBank2Data, &ah->iniBank2, 1); 567 ar5008_rf_bank_setup(ah->analogBank2Data, &ah->iniBank2, 1);
540 568
541 /* Setup Bank 6 Write */ 569 /* Setup Bank 6 Write */
542 RF_BANK_SETUP(ah->analogBank3Data, &ah->iniBank3, 570 ar5008_rf_bank_setup(ah->analogBank3Data, &ah->iniBank3,
543 modesIndex); 571 modesIndex);
544 { 572 {
545 int i; 573 int i;
@@ -569,7 +597,7 @@ static bool ar5008_hw_set_rf_regs(struct ath_hw *ah,
569 } 597 }
570 598
571 /* Setup Bank 7 Setup */ 599 /* Setup Bank 7 Setup */
572 RF_BANK_SETUP(ah->analogBank7Data, &ah->iniBank7, 1); 600 ar5008_rf_bank_setup(ah->analogBank7Data, &ah->iniBank7, 1);
573 601
574 /* Write Analog registers */ 602 /* Write Analog registers */
575 REG_WRITE_RF_ARRAY(&ah->iniBank0, ah->analogBank0Data, 603 REG_WRITE_RF_ARRAY(&ah->iniBank0, ah->analogBank0Data,
@@ -729,6 +757,7 @@ static int ar5008_hw_process_ini(struct ath_hw *ah,
729 struct ath9k_channel *chan) 757 struct ath9k_channel *chan)
730{ 758{
731 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); 759 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
760 struct ath_common *common = ath9k_hw_common(ah);
732 int i, regWrites = 0; 761 int i, regWrites = 0;
733 struct ieee80211_channel *channel = chan->chan; 762 struct ieee80211_channel *channel = chan->chan;
734 u32 modesIndex, freqIndex; 763 u32 modesIndex, freqIndex;
@@ -805,7 +834,8 @@ static int ar5008_hw_process_ini(struct ath_hw *ah,
805 REG_WRITE(ah, reg, val); 834 REG_WRITE(ah, reg, val);
806 835
807 if (reg >= 0x7800 && reg < 0x78a0 836 if (reg >= 0x7800 && reg < 0x78a0
808 && ah->config.analog_shiftreg) { 837 && ah->config.analog_shiftreg
838 && (common->bus_ops->ath_bus_type != ATH_USB)) {
809 udelay(100); 839 udelay(100);
810 } 840 }
811 841
@@ -835,7 +865,8 @@ static int ar5008_hw_process_ini(struct ath_hw *ah,
835 REG_WRITE(ah, reg, val); 865 REG_WRITE(ah, reg, val);
836 866
837 if (reg >= 0x7800 && reg < 0x78a0 867 if (reg >= 0x7800 && reg < 0x78a0
838 && ah->config.analog_shiftreg) { 868 && ah->config.analog_shiftreg
869 && (common->bus_ops->ath_bus_type != ATH_USB)) {
839 udelay(100); 870 udelay(100);
840 } 871 }
841 872
diff --git a/drivers/net/wireless/ath/ath9k/ar9002_calib.c b/drivers/net/wireless/ath/ath9k/ar9002_calib.c
index 76388c6d669..cb611b287b3 100644
--- a/drivers/net/wireless/ath/ath9k/ar9002_calib.c
+++ b/drivers/net/wireless/ath/ath9k/ar9002_calib.c
@@ -26,6 +26,27 @@ enum ar9002_cal_types {
26 IQ_MISMATCH_CAL = BIT(2), 26 IQ_MISMATCH_CAL = BIT(2),
27}; 27};
28 28
29static bool ar9002_hw_is_cal_supported(struct ath_hw *ah,
30 struct ath9k_channel *chan,
31 enum ar9002_cal_types cal_type)
32{
33 bool supported = false;
34 switch (ah->supp_cals & cal_type) {
35 case IQ_MISMATCH_CAL:
36 /* Run IQ Mismatch for non-CCK only */
37 if (!IS_CHAN_B(chan))
38 supported = true;
39 break;
40 case ADC_GAIN_CAL:
41 case ADC_DC_CAL:
42 /* Run ADC Gain Cal for non-CCK & non 2GHz-HT20 only */
43 if (!IS_CHAN_B(chan) &&
44 !(IS_CHAN_2GHZ(chan) && IS_CHAN_HT20(chan)))
45 supported = true;
46 break;
47 }
48 return supported;
49}
29 50
30static void ar9002_hw_setup_calibration(struct ath_hw *ah, 51static void ar9002_hw_setup_calibration(struct ath_hw *ah,
31 struct ath9k_cal_list *currCal) 52 struct ath9k_cal_list *currCal)
@@ -858,26 +879,32 @@ static bool ar9002_hw_init_cal(struct ath_hw *ah, struct ath9k_channel *chan)
858 if (AR_SREV_9100(ah) || AR_SREV_9160_10_OR_LATER(ah)) { 879 if (AR_SREV_9100(ah) || AR_SREV_9160_10_OR_LATER(ah)) {
859 ah->supp_cals = IQ_MISMATCH_CAL; 880 ah->supp_cals = IQ_MISMATCH_CAL;
860 881
861 if (AR_SREV_9160_10_OR_LATER(ah) && 882 if (AR_SREV_9160_10_OR_LATER(ah))
862 !(IS_CHAN_2GHZ(chan) && IS_CHAN_HT20(chan))) {
863 ah->supp_cals |= ADC_GAIN_CAL | ADC_DC_CAL; 883 ah->supp_cals |= ADC_GAIN_CAL | ADC_DC_CAL;
864 884
885 if (AR_SREV_9287(ah))
886 ah->supp_cals &= ~ADC_GAIN_CAL;
865 887
888 if (ar9002_hw_is_cal_supported(ah, chan, ADC_GAIN_CAL)) {
866 INIT_CAL(&ah->adcgain_caldata); 889 INIT_CAL(&ah->adcgain_caldata);
867 INSERT_CAL(ah, &ah->adcgain_caldata); 890 INSERT_CAL(ah, &ah->adcgain_caldata);
868 ath_dbg(common, ATH_DBG_CALIBRATE, 891 ath_dbg(common, ATH_DBG_CALIBRATE,
869 "enabling ADC Gain Calibration.\n"); 892 "enabling ADC Gain Calibration.\n");
893 }
870 894
895 if (ar9002_hw_is_cal_supported(ah, chan, ADC_DC_CAL)) {
871 INIT_CAL(&ah->adcdc_caldata); 896 INIT_CAL(&ah->adcdc_caldata);
872 INSERT_CAL(ah, &ah->adcdc_caldata); 897 INSERT_CAL(ah, &ah->adcdc_caldata);
873 ath_dbg(common, ATH_DBG_CALIBRATE, 898 ath_dbg(common, ATH_DBG_CALIBRATE,
874 "enabling ADC DC Calibration.\n"); 899 "enabling ADC DC Calibration.\n");
875 } 900 }
876 901
877 INIT_CAL(&ah->iq_caldata); 902 if (ar9002_hw_is_cal_supported(ah, chan, IQ_MISMATCH_CAL)) {
878 INSERT_CAL(ah, &ah->iq_caldata); 903 INIT_CAL(&ah->iq_caldata);
879 ath_dbg(common, ATH_DBG_CALIBRATE, 904 INSERT_CAL(ah, &ah->iq_caldata);
880 "enabling IQ Calibration.\n"); 905 ath_dbg(common, ATH_DBG_CALIBRATE,
906 "enabling IQ Calibration.\n");
907 }
881 908
882 ah->cal_list_curr = ah->cal_list; 909 ah->cal_list_curr = ah->cal_list;
883 910
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_hw.c b/drivers/net/wireless/ath/ath9k/ar9003_hw.c
index 7f5de6e4448..3daf3df0248 100644
--- a/drivers/net/wireless/ath/ath9k/ar9003_hw.c
+++ b/drivers/net/wireless/ath/ath9k/ar9003_hw.c
@@ -88,66 +88,6 @@ static void ar9003_hw_init_mode_regs(struct ath_hw *ah)
88 ar9485_1_1_pcie_phy_clkreq_disable_L1, 88 ar9485_1_1_pcie_phy_clkreq_disable_L1,
89 ARRAY_SIZE(ar9485_1_1_pcie_phy_clkreq_disable_L1), 89 ARRAY_SIZE(ar9485_1_1_pcie_phy_clkreq_disable_L1),
90 2); 90 2);
91 } else if (AR_SREV_9485(ah)) {
92 /* mac */
93 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
94 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
95 ar9485_1_0_mac_core,
96 ARRAY_SIZE(ar9485_1_0_mac_core), 2);
97 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
98 ar9485_1_0_mac_postamble,
99 ARRAY_SIZE(ar9485_1_0_mac_postamble), 5);
100
101 /* bb */
102 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], ar9485_1_0,
103 ARRAY_SIZE(ar9485_1_0), 2);
104 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
105 ar9485_1_0_baseband_core,
106 ARRAY_SIZE(ar9485_1_0_baseband_core), 2);
107 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
108 ar9485_1_0_baseband_postamble,
109 ARRAY_SIZE(ar9485_1_0_baseband_postamble), 5);
110
111 /* radio */
112 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
113 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
114 ar9485_1_0_radio_core,
115 ARRAY_SIZE(ar9485_1_0_radio_core), 2);
116 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
117 ar9485_1_0_radio_postamble,
118 ARRAY_SIZE(ar9485_1_0_radio_postamble), 2);
119
120 /* soc */
121 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
122 ar9485_1_0_soc_preamble,
123 ARRAY_SIZE(ar9485_1_0_soc_preamble), 2);
124 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
125 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST], NULL, 0, 0);
126
127 /* rx/tx gain */
128 INIT_INI_ARRAY(&ah->iniModesRxGain,
129 ar9485Common_rx_gain_1_0,
130 ARRAY_SIZE(ar9485Common_rx_gain_1_0), 2);
131 INIT_INI_ARRAY(&ah->iniModesTxGain,
132 ar9485Modes_lowest_ob_db_tx_gain_1_0,
133 ARRAY_SIZE(ar9485Modes_lowest_ob_db_tx_gain_1_0),
134 5);
135
136 /* Load PCIE SERDES settings from INI */
137
138 /* Awake Setting */
139
140 INIT_INI_ARRAY(&ah->iniPcieSerdes,
141 ar9485_1_0_pcie_phy_pll_on_clkreq_disable_L1,
142 ARRAY_SIZE(ar9485_1_0_pcie_phy_pll_on_clkreq_disable_L1),
143 2);
144
145 /* Sleep Setting */
146
147 INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
148 ar9485_1_0_pcie_phy_pll_on_clkreq_disable_L1,
149 ARRAY_SIZE(ar9485_1_0_pcie_phy_pll_on_clkreq_disable_L1),
150 2);
151 } else { 91 } else {
152 /* mac */ 92 /* mac */
153 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0); 93 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
@@ -228,11 +168,6 @@ static void ar9003_tx_gain_table_apply(struct ath_hw *ah)
228 ar9485_modes_lowest_ob_db_tx_gain_1_1, 168 ar9485_modes_lowest_ob_db_tx_gain_1_1,
229 ARRAY_SIZE(ar9485_modes_lowest_ob_db_tx_gain_1_1), 169 ARRAY_SIZE(ar9485_modes_lowest_ob_db_tx_gain_1_1),
230 5); 170 5);
231 else if (AR_SREV_9485(ah))
232 INIT_INI_ARRAY(&ah->iniModesTxGain,
233 ar9485Modes_lowest_ob_db_tx_gain_1_0,
234 ARRAY_SIZE(ar9485Modes_lowest_ob_db_tx_gain_1_0),
235 5);
236 else 171 else
237 INIT_INI_ARRAY(&ah->iniModesTxGain, 172 INIT_INI_ARRAY(&ah->iniModesTxGain,
238 ar9300Modes_lowest_ob_db_tx_gain_table_2p2, 173 ar9300Modes_lowest_ob_db_tx_gain_table_2p2,
@@ -245,11 +180,6 @@ static void ar9003_tx_gain_table_apply(struct ath_hw *ah)
245 ar9485Modes_high_ob_db_tx_gain_1_1, 180 ar9485Modes_high_ob_db_tx_gain_1_1,
246 ARRAY_SIZE(ar9485Modes_high_ob_db_tx_gain_1_1), 181 ARRAY_SIZE(ar9485Modes_high_ob_db_tx_gain_1_1),
247 5); 182 5);
248 else if (AR_SREV_9485(ah))
249 INIT_INI_ARRAY(&ah->iniModesTxGain,
250 ar9485Modes_high_ob_db_tx_gain_1_0,
251 ARRAY_SIZE(ar9485Modes_high_ob_db_tx_gain_1_0),
252 5);
253 else 183 else
254 INIT_INI_ARRAY(&ah->iniModesTxGain, 184 INIT_INI_ARRAY(&ah->iniModesTxGain,
255 ar9300Modes_high_ob_db_tx_gain_table_2p2, 185 ar9300Modes_high_ob_db_tx_gain_table_2p2,
@@ -262,11 +192,6 @@ static void ar9003_tx_gain_table_apply(struct ath_hw *ah)
262 ar9485Modes_low_ob_db_tx_gain_1_1, 192 ar9485Modes_low_ob_db_tx_gain_1_1,
263 ARRAY_SIZE(ar9485Modes_low_ob_db_tx_gain_1_1), 193 ARRAY_SIZE(ar9485Modes_low_ob_db_tx_gain_1_1),
264 5); 194 5);
265 else if (AR_SREV_9485(ah))
266 INIT_INI_ARRAY(&ah->iniModesTxGain,
267 ar9485Modes_low_ob_db_tx_gain_1_0,
268 ARRAY_SIZE(ar9485Modes_low_ob_db_tx_gain_1_0),
269 5);
270 else 195 else
271 INIT_INI_ARRAY(&ah->iniModesTxGain, 196 INIT_INI_ARRAY(&ah->iniModesTxGain,
272 ar9300Modes_low_ob_db_tx_gain_table_2p2, 197 ar9300Modes_low_ob_db_tx_gain_table_2p2,
@@ -279,11 +204,6 @@ static void ar9003_tx_gain_table_apply(struct ath_hw *ah)
279 ar9485Modes_high_power_tx_gain_1_1, 204 ar9485Modes_high_power_tx_gain_1_1,
280 ARRAY_SIZE(ar9485Modes_high_power_tx_gain_1_1), 205 ARRAY_SIZE(ar9485Modes_high_power_tx_gain_1_1),
281 5); 206 5);
282 else if (AR_SREV_9485(ah))
283 INIT_INI_ARRAY(&ah->iniModesTxGain,
284 ar9485Modes_high_power_tx_gain_1_0,
285 ARRAY_SIZE(ar9485Modes_high_power_tx_gain_1_0),
286 5);
287 else 207 else
288 INIT_INI_ARRAY(&ah->iniModesTxGain, 208 INIT_INI_ARRAY(&ah->iniModesTxGain,
289 ar9300Modes_high_power_tx_gain_table_2p2, 209 ar9300Modes_high_power_tx_gain_table_2p2,
@@ -303,11 +223,6 @@ static void ar9003_rx_gain_table_apply(struct ath_hw *ah)
303 ar9485_common_rx_gain_1_1, 223 ar9485_common_rx_gain_1_1,
304 ARRAY_SIZE(ar9485_common_rx_gain_1_1), 224 ARRAY_SIZE(ar9485_common_rx_gain_1_1),
305 2); 225 2);
306 else if (AR_SREV_9485(ah))
307 INIT_INI_ARRAY(&ah->iniModesRxGain,
308 ar9485Common_rx_gain_1_0,
309 ARRAY_SIZE(ar9485Common_rx_gain_1_0),
310 2);
311 else 226 else
312 INIT_INI_ARRAY(&ah->iniModesRxGain, 227 INIT_INI_ARRAY(&ah->iniModesRxGain,
313 ar9300Common_rx_gain_table_2p2, 228 ar9300Common_rx_gain_table_2p2,
@@ -320,11 +235,6 @@ static void ar9003_rx_gain_table_apply(struct ath_hw *ah)
320 ar9485Common_wo_xlna_rx_gain_1_1, 235 ar9485Common_wo_xlna_rx_gain_1_1,
321 ARRAY_SIZE(ar9485Common_wo_xlna_rx_gain_1_1), 236 ARRAY_SIZE(ar9485Common_wo_xlna_rx_gain_1_1),
322 2); 237 2);
323 else if (AR_SREV_9485(ah))
324 INIT_INI_ARRAY(&ah->iniModesRxGain,
325 ar9485Common_wo_xlna_rx_gain_1_0,
326 ARRAY_SIZE(ar9485Common_wo_xlna_rx_gain_1_0),
327 2);
328 else 238 else
329 INIT_INI_ARRAY(&ah->iniModesRxGain, 239 INIT_INI_ARRAY(&ah->iniModesRxGain,
330 ar9300Common_wo_xlna_rx_gain_table_2p2, 240 ar9300Common_wo_xlna_rx_gain_table_2p2,
diff --git a/drivers/net/wireless/ath/ath9k/ar9485_initvals.h b/drivers/net/wireless/ath/ath9k/ar9485_initvals.h
index 71cc0a3a29f..f91f73e50d0 100644
--- a/drivers/net/wireless/ath/ath9k/ar9485_initvals.h
+++ b/drivers/net/wireless/ath/ath9k/ar9485_initvals.h
@@ -17,931 +17,6 @@
17#ifndef INITVALS_9485_H 17#ifndef INITVALS_9485_H
18#define INITVALS_9485_H 18#define INITVALS_9485_H
19 19
20static const u32 ar9485Common_1_0[][2] = {
21 /* Addr allmodes */
22 {0x00007010, 0x00000022},
23 {0x00007020, 0x00000000},
24 {0x00007034, 0x00000002},
25 {0x00007038, 0x000004c2},
26};
27
28static const u32 ar9485_1_0_mac_postamble[][5] = {
29 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
30 {0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160},
31 {0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c},
32 {0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38},
33 {0x00008014, 0x03e803e8, 0x07d007d0, 0x10801600, 0x08400b00},
34 {0x0000801c, 0x128d8027, 0x128d804f, 0x12e00057, 0x12e0002b},
35 {0x00008120, 0x08f04800, 0x08f04800, 0x08f04810, 0x08f04810},
36 {0x000081d0, 0x00003210, 0x00003210, 0x0000320a, 0x0000320a},
37 {0x00008318, 0x00003e80, 0x00007d00, 0x00006880, 0x00003440},
38};
39
40static const u32 ar9485_1_0_pcie_phy_pll_on_clkreq_disable_L1[][2] = {
41 /* Addr allmodes */
42 {0x00018c00, 0x10212e5e},
43 {0x00018c04, 0x000801d8},
44 {0x00018c08, 0x0000580c},
45};
46
47static const u32 ar9485Common_wo_xlna_rx_gain_1_0[][2] = {
48 /* Addr allmodes */
49 {0x0000a000, 0x00010000},
50 {0x0000a004, 0x00030002},
51 {0x0000a008, 0x00050004},
52 {0x0000a00c, 0x00810080},
53 {0x0000a010, 0x01800082},
54 {0x0000a014, 0x01820181},
55 {0x0000a018, 0x01840183},
56 {0x0000a01c, 0x01880185},
57 {0x0000a020, 0x018a0189},
58 {0x0000a024, 0x02850284},
59 {0x0000a028, 0x02890288},
60 {0x0000a02c, 0x03850384},
61 {0x0000a030, 0x03890388},
62 {0x0000a034, 0x038b038a},
63 {0x0000a038, 0x038d038c},
64 {0x0000a03c, 0x03910390},
65 {0x0000a040, 0x03930392},
66 {0x0000a044, 0x03950394},
67 {0x0000a048, 0x00000396},
68 {0x0000a04c, 0x00000000},
69 {0x0000a050, 0x00000000},
70 {0x0000a054, 0x00000000},
71 {0x0000a058, 0x00000000},
72 {0x0000a05c, 0x00000000},
73 {0x0000a060, 0x00000000},
74 {0x0000a064, 0x00000000},
75 {0x0000a068, 0x00000000},
76 {0x0000a06c, 0x00000000},
77 {0x0000a070, 0x00000000},
78 {0x0000a074, 0x00000000},
79 {0x0000a078, 0x00000000},
80 {0x0000a07c, 0x00000000},
81 {0x0000a080, 0x28282828},
82 {0x0000a084, 0x28282828},
83 {0x0000a088, 0x28282828},
84 {0x0000a08c, 0x28282828},
85 {0x0000a090, 0x28282828},
86 {0x0000a094, 0x21212128},
87 {0x0000a098, 0x171c1c1c},
88 {0x0000a09c, 0x02020212},
89 {0x0000a0a0, 0x00000202},
90 {0x0000a0a4, 0x00000000},
91 {0x0000a0a8, 0x00000000},
92 {0x0000a0ac, 0x00000000},
93 {0x0000a0b0, 0x00000000},
94 {0x0000a0b4, 0x00000000},
95 {0x0000a0b8, 0x00000000},
96 {0x0000a0bc, 0x00000000},
97 {0x0000a0c0, 0x001f0000},
98 {0x0000a0c4, 0x111f1100},
99 {0x0000a0c8, 0x111d111e},
100 {0x0000a0cc, 0x111b111c},
101 {0x0000a0d0, 0x22032204},
102 {0x0000a0d4, 0x22012202},
103 {0x0000a0d8, 0x221f2200},
104 {0x0000a0dc, 0x221d221e},
105 {0x0000a0e0, 0x33013302},
106 {0x0000a0e4, 0x331f3300},
107 {0x0000a0e8, 0x4402331e},
108 {0x0000a0ec, 0x44004401},
109 {0x0000a0f0, 0x441e441f},
110 {0x0000a0f4, 0x55015502},
111 {0x0000a0f8, 0x551f5500},
112 {0x0000a0fc, 0x6602551e},
113 {0x0000a100, 0x66006601},
114 {0x0000a104, 0x661e661f},
115 {0x0000a108, 0x7703661d},
116 {0x0000a10c, 0x77017702},
117 {0x0000a110, 0x00007700},
118 {0x0000a114, 0x00000000},
119 {0x0000a118, 0x00000000},
120 {0x0000a11c, 0x00000000},
121 {0x0000a120, 0x00000000},
122 {0x0000a124, 0x00000000},
123 {0x0000a128, 0x00000000},
124 {0x0000a12c, 0x00000000},
125 {0x0000a130, 0x00000000},
126 {0x0000a134, 0x00000000},
127 {0x0000a138, 0x00000000},
128 {0x0000a13c, 0x00000000},
129 {0x0000a140, 0x001f0000},
130 {0x0000a144, 0x111f1100},
131 {0x0000a148, 0x111d111e},
132 {0x0000a14c, 0x111b111c},
133 {0x0000a150, 0x22032204},
134 {0x0000a154, 0x22012202},
135 {0x0000a158, 0x221f2200},
136 {0x0000a15c, 0x221d221e},
137 {0x0000a160, 0x33013302},
138 {0x0000a164, 0x331f3300},
139 {0x0000a168, 0x4402331e},
140 {0x0000a16c, 0x44004401},
141 {0x0000a170, 0x441e441f},
142 {0x0000a174, 0x55015502},
143 {0x0000a178, 0x551f5500},
144 {0x0000a17c, 0x6602551e},
145 {0x0000a180, 0x66006601},
146 {0x0000a184, 0x661e661f},
147 {0x0000a188, 0x7703661d},
148 {0x0000a18c, 0x77017702},
149 {0x0000a190, 0x00007700},
150 {0x0000a194, 0x00000000},
151 {0x0000a198, 0x00000000},
152 {0x0000a19c, 0x00000000},
153 {0x0000a1a0, 0x00000000},
154 {0x0000a1a4, 0x00000000},
155 {0x0000a1a8, 0x00000000},
156 {0x0000a1ac, 0x00000000},
157 {0x0000a1b0, 0x00000000},
158 {0x0000a1b4, 0x00000000},
159 {0x0000a1b8, 0x00000000},
160 {0x0000a1bc, 0x00000000},
161 {0x0000a1c0, 0x00000000},
162 {0x0000a1c4, 0x00000000},
163 {0x0000a1c8, 0x00000000},
164 {0x0000a1cc, 0x00000000},
165 {0x0000a1d0, 0x00000000},
166 {0x0000a1d4, 0x00000000},
167 {0x0000a1d8, 0x00000000},
168 {0x0000a1dc, 0x00000000},
169 {0x0000a1e0, 0x00000000},
170 {0x0000a1e4, 0x00000000},
171 {0x0000a1e8, 0x00000000},
172 {0x0000a1ec, 0x00000000},
173 {0x0000a1f0, 0x00000396},
174 {0x0000a1f4, 0x00000396},
175 {0x0000a1f8, 0x00000396},
176 {0x0000a1fc, 0x00000296},
177};
178
179static const u32 ar9485Modes_high_power_tx_gain_1_0[][5] = {
180 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
181 {0x0000a410, 0x000050d9, 0x000050d9, 0x000050d8, 0x000050d8},
182 {0x0000a500, 0x00022200, 0x00022200, 0x00000000, 0x00000000},
183 {0x0000a504, 0x05062002, 0x05062002, 0x04000002, 0x04000002},
184 {0x0000a508, 0x0c002e00, 0x0c002e00, 0x08000004, 0x08000004},
185 {0x0000a50c, 0x11062202, 0x11062202, 0x0d000200, 0x0d000200},
186 {0x0000a510, 0x17022e00, 0x17022e00, 0x11000202, 0x11000202},
187 {0x0000a514, 0x1d000ec2, 0x1d000ec2, 0x15000400, 0x15000400},
188 {0x0000a518, 0x25020ec0, 0x25020ec0, 0x19000402, 0x19000402},
189 {0x0000a51c, 0x2b020ec3, 0x2b020ec3, 0x1d000404, 0x1d000404},
190 {0x0000a520, 0x2f001f04, 0x2f001f04, 0x21000603, 0x21000603},
191 {0x0000a524, 0x35001fc4, 0x35001fc4, 0x25000605, 0x25000605},
192 {0x0000a528, 0x3c022f04, 0x3c022f04, 0x2a000a03, 0x2a000a03},
193 {0x0000a52c, 0x41023e85, 0x41023e85, 0x2c000a04, 0x2c000a04},
194 {0x0000a530, 0x48023ec6, 0x48023ec6, 0x2e000a20, 0x2e000a20},
195 {0x0000a534, 0x4d023f01, 0x4d023f01, 0x34000e20, 0x34000e20},
196 {0x0000a538, 0x53023f4b, 0x53023f4b, 0x38000e22, 0x38000e22},
197 {0x0000a53c, 0x5a027f09, 0x5a027f09, 0x3c000e24, 0x3c000e24},
198 {0x0000a540, 0x5f027fc9, 0x5f027fc9, 0x40000e26, 0x40000e26},
199 {0x0000a544, 0x6502feca, 0x6502feca, 0x43001640, 0x43001640},
200 {0x0000a548, 0x6b02ff4a, 0x6b02ff4a, 0x46001660, 0x46001660},
201 {0x0000a54c, 0x7203feca, 0x7203feca, 0x49001861, 0x49001861},
202 {0x0000a550, 0x7703ff0b, 0x7703ff0b, 0x4c001a81, 0x4c001a81},
203 {0x0000a554, 0x7d06ffcb, 0x7d06ffcb, 0x4f001a83, 0x4f001a83},
204 {0x0000a558, 0x8407ff0b, 0x8407ff0b, 0x54001c85, 0x54001c85},
205 {0x0000a55c, 0x8907ffcb, 0x8907ffcb, 0x58001ce5, 0x58001ce5},
206 {0x0000a560, 0x900fff0b, 0x900fff0b, 0x5b001ce9, 0x5b001ce9},
207 {0x0000a564, 0x960fffcb, 0x960fffcb, 0x60001eeb, 0x60001eeb},
208 {0x0000a568, 0x9c1fff0b, 0x9c1fff0b, 0x60001eeb, 0x60001eeb},
209 {0x0000a56c, 0x9c1fff0b, 0x9c1fff0b, 0x60001eeb, 0x60001eeb},
210 {0x0000a570, 0x9c1fff0b, 0x9c1fff0b, 0x60001eeb, 0x60001eeb},
211 {0x0000a574, 0x9c1fff0b, 0x9c1fff0b, 0x60001eeb, 0x60001eeb},
212 {0x0000a578, 0x9c1fff0b, 0x9c1fff0b, 0x60001eeb, 0x60001eeb},
213 {0x0000a57c, 0x9c1fff0b, 0x9c1fff0b, 0x60001eeb, 0x60001eeb},
214 {0x00016044, 0x05b6b2db, 0x05b6b2db, 0x05b6b2db, 0x05b6b2db},
215};
216
217static const u32 ar9485_1_0[][2] = {
218 /* Addr allmodes */
219 {0x0000a580, 0x00000000},
220 {0x0000a584, 0x00000000},
221 {0x0000a588, 0x00000000},
222 {0x0000a58c, 0x00000000},
223 {0x0000a590, 0x00000000},
224 {0x0000a594, 0x00000000},
225 {0x0000a598, 0x00000000},
226 {0x0000a59c, 0x00000000},
227 {0x0000a5a0, 0x00000000},
228 {0x0000a5a4, 0x00000000},
229 {0x0000a5a8, 0x00000000},
230 {0x0000a5ac, 0x00000000},
231 {0x0000a5b0, 0x00000000},
232 {0x0000a5b4, 0x00000000},
233 {0x0000a5b8, 0x00000000},
234 {0x0000a5bc, 0x00000000},
235};
236
237static const u32 ar9485_1_0_radio_core[][2] = {
238 /* Addr allmodes */
239 {0x00016000, 0x36db6db6},
240 {0x00016004, 0x6db6db40},
241 {0x00016008, 0x73800000},
242 {0x0001600c, 0x00000000},
243 {0x00016040, 0x7f80fff8},
244 {0x00016048, 0x6c92426e},
245 {0x0001604c, 0x000f0278},
246 {0x00016050, 0x6db6db6c},
247 {0x00016054, 0x6db60000},
248 {0x00016080, 0x00080000},
249 {0x00016084, 0x0e48048c},
250 {0x00016088, 0x14214514},
251 {0x0001608c, 0x119f081e},
252 {0x00016090, 0x24926490},
253 {0x00016098, 0xd28b3330},
254 {0x000160a0, 0xc2108ffe},
255 {0x000160a4, 0x812fc370},
256 {0x000160a8, 0x423c8000},
257 {0x000160b4, 0x92480040},
258 {0x000160c0, 0x006db6db},
259 {0x000160c4, 0x0186db60},
260 {0x000160c8, 0x6db6db6c},
261 {0x000160cc, 0x6de6fbe0},
262 {0x000160d0, 0xf7dfcf3c},
263 {0x00016100, 0x04cb0001},
264 {0x00016104, 0xfff80015},
265 {0x00016108, 0x00080010},
266 {0x00016144, 0x01884080},
267 {0x00016148, 0x00008040},
268 {0x00016180, 0x08453333},
269 {0x00016184, 0x18e82f01},
270 {0x00016188, 0x00000000},
271 {0x0001618c, 0x00000000},
272 {0x00016240, 0x08400000},
273 {0x00016244, 0x1bf90f00},
274 {0x00016248, 0x00000000},
275 {0x0001624c, 0x00000000},
276 {0x00016280, 0x01000015},
277 {0x00016284, 0x00d30000},
278 {0x00016288, 0x00318000},
279 {0x0001628c, 0x50000000},
280 {0x00016290, 0x4b96210f},
281 {0x00016380, 0x00000000},
282 {0x00016384, 0x00000000},
283 {0x00016388, 0x00800700},
284 {0x0001638c, 0x00800700},
285 {0x00016390, 0x00800700},
286 {0x00016394, 0x00000000},
287 {0x00016398, 0x00000000},
288 {0x0001639c, 0x00000000},
289 {0x000163a0, 0x00000001},
290 {0x000163a4, 0x00000001},
291 {0x000163a8, 0x00000000},
292 {0x000163ac, 0x00000000},
293 {0x000163b0, 0x00000000},
294 {0x000163b4, 0x00000000},
295 {0x000163b8, 0x00000000},
296 {0x000163bc, 0x00000000},
297 {0x000163c0, 0x000000a0},
298 {0x000163c4, 0x000c0000},
299 {0x000163c8, 0x14021402},
300 {0x000163cc, 0x00001402},
301 {0x000163d0, 0x00000000},
302 {0x000163d4, 0x00000000},
303 {0x00016c40, 0x1319c178},
304 {0x00016c44, 0x10000000},
305};
306
307static const u32 ar9485Modes_lowest_ob_db_tx_gain_1_0[][5] = {
308 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
309 {0x0000a410, 0x000050d9, 0x000050d9, 0x000050d8, 0x000050d8},
310 {0x0000a500, 0x00022200, 0x00022200, 0x00000000, 0x00000000},
311 {0x0000a504, 0x05062002, 0x05062002, 0x04000002, 0x04000002},
312 {0x0000a508, 0x0c002e00, 0x0c002e00, 0x08000004, 0x08000004},
313 {0x0000a50c, 0x11062202, 0x11062202, 0x0d000200, 0x0d000200},
314 {0x0000a510, 0x17022e00, 0x17022e00, 0x11000202, 0x11000202},
315 {0x0000a514, 0x1d000ec2, 0x1d000ec2, 0x15000400, 0x15000400},
316 {0x0000a518, 0x25020ec0, 0x25020ec0, 0x19000402, 0x19000402},
317 {0x0000a51c, 0x2b020ec3, 0x2b020ec3, 0x1d000404, 0x1d000404},
318 {0x0000a520, 0x2f001f04, 0x2f001f04, 0x21000603, 0x21000603},
319 {0x0000a524, 0x35001fc4, 0x35001fc4, 0x25000605, 0x25000605},
320 {0x0000a528, 0x3c022f04, 0x3c022f04, 0x2a000a03, 0x2a000a03},
321 {0x0000a52c, 0x41023e85, 0x41023e85, 0x2c000a04, 0x2c000a04},
322 {0x0000a530, 0x48023ec6, 0x48023ec6, 0x2e000a20, 0x2e000a20},
323 {0x0000a534, 0x4d023f01, 0x4d023f01, 0x34000e20, 0x34000e20},
324 {0x0000a538, 0x53023f4b, 0x53023f4b, 0x38000e22, 0x38000e22},
325 {0x0000a53c, 0x5a027f09, 0x5a027f09, 0x3c000e24, 0x3c000e24},
326 {0x0000a540, 0x5f027fc9, 0x5f027fc9, 0x40000e26, 0x40000e26},
327 {0x0000a544, 0x6502feca, 0x6502feca, 0x43001640, 0x43001640},
328 {0x0000a548, 0x6b02ff4a, 0x6b02ff4a, 0x46001660, 0x46001660},
329 {0x0000a54c, 0x7203feca, 0x7203feca, 0x49001861, 0x49001861},
330 {0x0000a550, 0x7703ff0b, 0x7703ff0b, 0x4c001a81, 0x4c001a81},
331 {0x0000a554, 0x7d06ffcb, 0x7d06ffcb, 0x4f001a83, 0x4f001a83},
332 {0x0000a558, 0x8407ff0b, 0x8407ff0b, 0x54001c85, 0x54001c85},
333 {0x0000a55c, 0x8907ffcb, 0x8907ffcb, 0x58001ce5, 0x58001ce5},
334 {0x0000a560, 0x900fff0b, 0x900fff0b, 0x5b001ce9, 0x5b001ce9},
335 {0x0000a564, 0x960fffcb, 0x960fffcb, 0x60001eeb, 0x60001eeb},
336 {0x0000a568, 0x9c1fff0b, 0x9c1fff0b, 0x60001eeb, 0x60001eeb},
337 {0x0000a56c, 0x9c1fff0b, 0x9c1fff0b, 0x60001eeb, 0x60001eeb},
338 {0x0000a570, 0x9c1fff0b, 0x9c1fff0b, 0x60001eeb, 0x60001eeb},
339 {0x0000a574, 0x9c1fff0b, 0x9c1fff0b, 0x60001eeb, 0x60001eeb},
340 {0x0000a578, 0x9c1fff0b, 0x9c1fff0b, 0x60001eeb, 0x60001eeb},
341 {0x0000a57c, 0x9c1fff0b, 0x9c1fff0b, 0x60001eeb, 0x60001eeb},
342 {0x00016044, 0x05b6b2db, 0x05b6b2db, 0x05b6b2db, 0x05b6b2db},
343};
344
345static const u32 ar9485_1_0_baseband_core[][2] = {
346 /* Addr allmodes */
347 {0x00009800, 0xafe68e30},
348 {0x00009804, 0xfd14e000},
349 {0x00009808, 0x9c0a8f6b},
350 {0x0000980c, 0x04800000},
351 {0x00009814, 0x9280c00a},
352 {0x00009818, 0x00000000},
353 {0x0000981c, 0x00020028},
354 {0x00009834, 0x5f3ca3de},
355 {0x00009838, 0x0108ecff},
356 {0x0000983c, 0x14750600},
357 {0x00009880, 0x201fff00},
358 {0x00009884, 0x00001042},
359 {0x000098a4, 0x00200400},
360 {0x000098b0, 0x52440bbe},
361 {0x000098bc, 0x00000002},
362 {0x000098d0, 0x004b6a8e},
363 {0x000098d4, 0x00000820},
364 {0x000098dc, 0x00000000},
365 {0x000098f0, 0x00000000},
366 {0x000098f4, 0x00000000},
367 {0x00009c04, 0x00000000},
368 {0x00009c08, 0x03200000},
369 {0x00009c0c, 0x00000000},
370 {0x00009c10, 0x00000000},
371 {0x00009c14, 0x00046384},
372 {0x00009c18, 0x05b6b440},
373 {0x00009c1c, 0x00b6b440},
374 {0x00009d00, 0xc080a333},
375 {0x00009d04, 0x40206c10},
376 {0x00009d08, 0x009c4060},
377 {0x00009d0c, 0x1883800a},
378 {0x00009d10, 0x01834061},
379 {0x00009d14, 0x00c00400},
380 {0x00009d18, 0x00000000},
381 {0x00009d1c, 0x00000000},
382 {0x00009e08, 0x0038233c},
383 {0x00009e24, 0x990bb515},
384 {0x00009e28, 0x0a6f0000},
385 {0x00009e30, 0x06336f77},
386 {0x00009e34, 0x6af6532f},
387 {0x00009e38, 0x0cc80c00},
388 {0x00009e40, 0x0d261820},
389 {0x00009e4c, 0x00001004},
390 {0x00009e50, 0x00ff03f1},
391 {0x00009fc0, 0x80be4788},
392 {0x00009fc4, 0x0001efb5},
393 {0x00009fcc, 0x40000014},
394 {0x0000a20c, 0x00000000},
395 {0x0000a210, 0x00000000},
396 {0x0000a220, 0x00000000},
397 {0x0000a224, 0x00000000},
398 {0x0000a228, 0x10002310},
399 {0x0000a23c, 0x00000000},
400 {0x0000a244, 0x0c000000},
401 {0x0000a2a0, 0x00000001},
402 {0x0000a2c0, 0x00000001},
403 {0x0000a2c8, 0x00000000},
404 {0x0000a2cc, 0x18c43433},
405 {0x0000a2d4, 0x00000000},
406 {0x0000a2dc, 0x00000000},
407 {0x0000a2e0, 0x00000000},
408 {0x0000a2e4, 0x00000000},
409 {0x0000a2e8, 0x00000000},
410 {0x0000a2ec, 0x00000000},
411 {0x0000a2f0, 0x00000000},
412 {0x0000a2f4, 0x00000000},
413 {0x0000a2f8, 0x00000000},
414 {0x0000a344, 0x00000000},
415 {0x0000a34c, 0x00000000},
416 {0x0000a350, 0x0000a000},
417 {0x0000a364, 0x00000000},
418 {0x0000a370, 0x00000000},
419 {0x0000a390, 0x00000001},
420 {0x0000a394, 0x00000444},
421 {0x0000a398, 0x001f0e0f},
422 {0x0000a39c, 0x0075393f},
423 {0x0000a3a0, 0xb79f6427},
424 {0x0000a3a4, 0x00000000},
425 {0x0000a3a8, 0xaaaaaaaa},
426 {0x0000a3ac, 0x3c466478},
427 {0x0000a3c0, 0x20202020},
428 {0x0000a3c4, 0x22222220},
429 {0x0000a3c8, 0x20200020},
430 {0x0000a3cc, 0x20202020},
431 {0x0000a3d0, 0x20202020},
432 {0x0000a3d4, 0x20202020},
433 {0x0000a3d8, 0x20202020},
434 {0x0000a3dc, 0x20202020},
435 {0x0000a3e0, 0x20202020},
436 {0x0000a3e4, 0x20202020},
437 {0x0000a3e8, 0x20202020},
438 {0x0000a3ec, 0x20202020},
439 {0x0000a3f0, 0x00000000},
440 {0x0000a3f4, 0x00000006},
441 {0x0000a3f8, 0x0cdbd380},
442 {0x0000a3fc, 0x000f0f01},
443 {0x0000a400, 0x8fa91f01},
444 {0x0000a404, 0x00000000},
445 {0x0000a408, 0x0e79e5c6},
446 {0x0000a40c, 0x00820820},
447 {0x0000a414, 0x1ce739ce},
448 {0x0000a418, 0x2d0011ce},
449 {0x0000a41c, 0x1ce739ce},
450 {0x0000a420, 0x000001ce},
451 {0x0000a424, 0x1ce739ce},
452 {0x0000a428, 0x000001ce},
453 {0x0000a42c, 0x1ce739ce},
454 {0x0000a430, 0x1ce739ce},
455 {0x0000a434, 0x00000000},
456 {0x0000a438, 0x00001801},
457 {0x0000a43c, 0x00000000},
458 {0x0000a440, 0x00000000},
459 {0x0000a444, 0x00000000},
460 {0x0000a448, 0x04000000},
461 {0x0000a44c, 0x00000001},
462 {0x0000a450, 0x00010000},
463 {0x0000a458, 0x00000000},
464 {0x0000a5c4, 0x3fad9d74},
465 {0x0000a5c8, 0x0048060a},
466 {0x0000a5cc, 0x00000637},
467 {0x0000a760, 0x03020100},
468 {0x0000a764, 0x09080504},
469 {0x0000a768, 0x0d0c0b0a},
470 {0x0000a76c, 0x13121110},
471 {0x0000a770, 0x31301514},
472 {0x0000a774, 0x35343332},
473 {0x0000a778, 0x00000036},
474 {0x0000a780, 0x00000838},
475 {0x0000a7c0, 0x00000000},
476 {0x0000a7c4, 0xfffffffc},
477 {0x0000a7c8, 0x00000000},
478 {0x0000a7cc, 0x00000000},
479 {0x0000a7d0, 0x00000000},
480 {0x0000a7d4, 0x00000004},
481 {0x0000a7dc, 0x00000001},
482};
483
484static const u32 ar9485Modes_high_ob_db_tx_gain_1_0[][5] = {
485 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
486 {0x0000a410, 0x000050d9, 0x000050d9, 0x000050d8, 0x000050d8},
487 {0x0000a500, 0x00022200, 0x00022200, 0x00000000, 0x00000000},
488 {0x0000a504, 0x05062002, 0x05062002, 0x04000002, 0x04000002},
489 {0x0000a508, 0x0c002e00, 0x0c002e00, 0x08000004, 0x08000004},
490 {0x0000a50c, 0x11062202, 0x11062202, 0x0d000200, 0x0d000200},
491 {0x0000a510, 0x17022e00, 0x17022e00, 0x11000202, 0x11000202},
492 {0x0000a514, 0x1d000ec2, 0x1d000ec2, 0x15000400, 0x15000400},
493 {0x0000a518, 0x25020ec0, 0x25020ec0, 0x19000402, 0x19000402},
494 {0x0000a51c, 0x2b020ec3, 0x2b020ec3, 0x1d000404, 0x1d000404},
495 {0x0000a520, 0x2f001f04, 0x2f001f04, 0x21000603, 0x21000603},
496 {0x0000a524, 0x35001fc4, 0x35001fc4, 0x25000605, 0x25000605},
497 {0x0000a528, 0x3c022f04, 0x3c022f04, 0x2a000a03, 0x2a000a03},
498 {0x0000a52c, 0x41023e85, 0x41023e85, 0x2c000a04, 0x2c000a04},
499 {0x0000a530, 0x48023ec6, 0x48023ec6, 0x2e000a20, 0x2e000a20},
500 {0x0000a534, 0x4d023f01, 0x4d023f01, 0x34000e20, 0x34000e20},
501 {0x0000a538, 0x53023f4b, 0x53023f4b, 0x38000e22, 0x38000e22},
502 {0x0000a53c, 0x5a027f09, 0x5a027f09, 0x3c000e24, 0x3c000e24},
503 {0x0000a540, 0x5f027fc9, 0x5f027fc9, 0x40000e26, 0x40000e26},
504 {0x0000a544, 0x6502feca, 0x6502feca, 0x43001640, 0x43001640},
505 {0x0000a548, 0x6b02ff4a, 0x6b02ff4a, 0x46001660, 0x46001660},
506 {0x0000a54c, 0x7203feca, 0x7203feca, 0x49001861, 0x49001861},
507 {0x0000a550, 0x7703ff0b, 0x7703ff0b, 0x4c001a81, 0x4c001a81},
508 {0x0000a554, 0x7d06ffcb, 0x7d06ffcb, 0x4f001a83, 0x4f001a83},
509 {0x0000a558, 0x8407ff0b, 0x8407ff0b, 0x54001c85, 0x54001c85},
510 {0x0000a55c, 0x8907ffcb, 0x8907ffcb, 0x58001ce5, 0x58001ce5},
511 {0x0000a560, 0x900fff0b, 0x900fff0b, 0x5b001ce9, 0x5b001ce9},
512 {0x0000a564, 0x960fffcb, 0x960fffcb, 0x60001eeb, 0x60001eeb},
513 {0x0000a568, 0x9c1fff0b, 0x9c1fff0b, 0x60001eeb, 0x60001eeb},
514 {0x0000a56c, 0x9c1fff0b, 0x9c1fff0b, 0x60001eeb, 0x60001eeb},
515 {0x0000a570, 0x9c1fff0b, 0x9c1fff0b, 0x60001eeb, 0x60001eeb},
516 {0x0000a574, 0x9c1fff0b, 0x9c1fff0b, 0x60001eeb, 0x60001eeb},
517 {0x0000a578, 0x9c1fff0b, 0x9c1fff0b, 0x60001eeb, 0x60001eeb},
518 {0x0000a57c, 0x9c1fff0b, 0x9c1fff0b, 0x60001eeb, 0x60001eeb},
519 {0x00016044, 0x05b6b2db, 0x05b6b2db, 0x05b6b2db, 0x05b6b2db},
520};
521
522static const u32 ar9485Common_rx_gain_1_0[][2] = {
523 /* Addr allmodes */
524 {0x0000a000, 0x00010000},
525 {0x0000a004, 0x00030002},
526 {0x0000a008, 0x00050004},
527 {0x0000a00c, 0x00810080},
528 {0x0000a010, 0x01800082},
529 {0x0000a014, 0x01820181},
530 {0x0000a018, 0x01840183},
531 {0x0000a01c, 0x01880185},
532 {0x0000a020, 0x018a0189},
533 {0x0000a024, 0x02850284},
534 {0x0000a028, 0x02890288},
535 {0x0000a02c, 0x03850384},
536 {0x0000a030, 0x03890388},
537 {0x0000a034, 0x038b038a},
538 {0x0000a038, 0x038d038c},
539 {0x0000a03c, 0x03910390},
540 {0x0000a040, 0x03930392},
541 {0x0000a044, 0x03950394},
542 {0x0000a048, 0x00000396},
543 {0x0000a04c, 0x00000000},
544 {0x0000a050, 0x00000000},
545 {0x0000a054, 0x00000000},
546 {0x0000a058, 0x00000000},
547 {0x0000a05c, 0x00000000},
548 {0x0000a060, 0x00000000},
549 {0x0000a064, 0x00000000},
550 {0x0000a068, 0x00000000},
551 {0x0000a06c, 0x00000000},
552 {0x0000a070, 0x00000000},
553 {0x0000a074, 0x00000000},
554 {0x0000a078, 0x00000000},
555 {0x0000a07c, 0x00000000},
556 {0x0000a080, 0x28282828},
557 {0x0000a084, 0x28282828},
558 {0x0000a088, 0x28282828},
559 {0x0000a08c, 0x28282828},
560 {0x0000a090, 0x28282828},
561 {0x0000a094, 0x21212128},
562 {0x0000a098, 0x171c1c1c},
563 {0x0000a09c, 0x02020212},
564 {0x0000a0a0, 0x00000202},
565 {0x0000a0a4, 0x00000000},
566 {0x0000a0a8, 0x00000000},
567 {0x0000a0ac, 0x00000000},
568 {0x0000a0b0, 0x00000000},
569 {0x0000a0b4, 0x00000000},
570 {0x0000a0b8, 0x00000000},
571 {0x0000a0bc, 0x00000000},
572 {0x0000a0c0, 0x001f0000},
573 {0x0000a0c4, 0x111f1100},
574 {0x0000a0c8, 0x111d111e},
575 {0x0000a0cc, 0x111b111c},
576 {0x0000a0d0, 0x22032204},
577 {0x0000a0d4, 0x22012202},
578 {0x0000a0d8, 0x221f2200},
579 {0x0000a0dc, 0x221d221e},
580 {0x0000a0e0, 0x33013302},
581 {0x0000a0e4, 0x331f3300},
582 {0x0000a0e8, 0x4402331e},
583 {0x0000a0ec, 0x44004401},
584 {0x0000a0f0, 0x441e441f},
585 {0x0000a0f4, 0x55015502},
586 {0x0000a0f8, 0x551f5500},
587 {0x0000a0fc, 0x6602551e},
588 {0x0000a100, 0x66006601},
589 {0x0000a104, 0x661e661f},
590 {0x0000a108, 0x7703661d},
591 {0x0000a10c, 0x77017702},
592 {0x0000a110, 0x00007700},
593 {0x0000a114, 0x00000000},
594 {0x0000a118, 0x00000000},
595 {0x0000a11c, 0x00000000},
596 {0x0000a120, 0x00000000},
597 {0x0000a124, 0x00000000},
598 {0x0000a128, 0x00000000},
599 {0x0000a12c, 0x00000000},
600 {0x0000a130, 0x00000000},
601 {0x0000a134, 0x00000000},
602 {0x0000a138, 0x00000000},
603 {0x0000a13c, 0x00000000},
604 {0x0000a140, 0x001f0000},
605 {0x0000a144, 0x111f1100},
606 {0x0000a148, 0x111d111e},
607 {0x0000a14c, 0x111b111c},
608 {0x0000a150, 0x22032204},
609 {0x0000a154, 0x22012202},
610 {0x0000a158, 0x221f2200},
611 {0x0000a15c, 0x221d221e},
612 {0x0000a160, 0x33013302},
613 {0x0000a164, 0x331f3300},
614 {0x0000a168, 0x4402331e},
615 {0x0000a16c, 0x44004401},
616 {0x0000a170, 0x441e441f},
617 {0x0000a174, 0x55015502},
618 {0x0000a178, 0x551f5500},
619 {0x0000a17c, 0x6602551e},
620 {0x0000a180, 0x66006601},
621 {0x0000a184, 0x661e661f},
622 {0x0000a188, 0x7703661d},
623 {0x0000a18c, 0x77017702},
624 {0x0000a190, 0x00007700},
625 {0x0000a194, 0x00000000},
626 {0x0000a198, 0x00000000},
627 {0x0000a19c, 0x00000000},
628 {0x0000a1a0, 0x00000000},
629 {0x0000a1a4, 0x00000000},
630 {0x0000a1a8, 0x00000000},
631 {0x0000a1ac, 0x00000000},
632 {0x0000a1b0, 0x00000000},
633 {0x0000a1b4, 0x00000000},
634 {0x0000a1b8, 0x00000000},
635 {0x0000a1bc, 0x00000000},
636 {0x0000a1c0, 0x00000000},
637 {0x0000a1c4, 0x00000000},
638 {0x0000a1c8, 0x00000000},
639 {0x0000a1cc, 0x00000000},
640 {0x0000a1d0, 0x00000000},
641 {0x0000a1d4, 0x00000000},
642 {0x0000a1d8, 0x00000000},
643 {0x0000a1dc, 0x00000000},
644 {0x0000a1e0, 0x00000000},
645 {0x0000a1e4, 0x00000000},
646 {0x0000a1e8, 0x00000000},
647 {0x0000a1ec, 0x00000000},
648 {0x0000a1f0, 0x00000396},
649 {0x0000a1f4, 0x00000396},
650 {0x0000a1f8, 0x00000396},
651 {0x0000a1fc, 0x00000296},
652};
653
654static const u32 ar9485_1_0_pcie_phy_pll_on_clkreq_enable_L1[][2] = {
655 /* Addr allmodes */
656 {0x00018c00, 0x10252e5e},
657 {0x00018c04, 0x000801d8},
658 {0x00018c08, 0x0000580c},
659};
660
661static const u32 ar9485_1_0_pcie_phy_clkreq_enable_L1[][2] = {
662 /* Addr allmodes */
663 {0x00018c00, 0x10253e5e},
664 {0x00018c04, 0x000801d8},
665 {0x00018c08, 0x0000580c},
666};
667
668static const u32 ar9485_1_0_soc_preamble[][2] = {
669 /* Addr allmodes */
670 {0x00004090, 0x00aa10aa},
671 {0x000040a4, 0x00a0c9c9},
672 {0x00007048, 0x00000004},
673};
674
675static const u32 ar9485_fast_clock_1_0_baseband_postamble[][3] = {
676 /* Addr 5G_HT20 5G_HT40 */
677 {0x00009e00, 0x03721821, 0x03721821},
678 {0x0000a230, 0x0000400b, 0x00004016},
679 {0x0000a254, 0x00000898, 0x00001130},
680};
681
682static const u32 ar9485_1_0_baseband_postamble[][5] = {
683 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
684 {0x00009810, 0xd00a8005, 0xd00a8005, 0xd00a8005, 0xd00a8005},
685 {0x00009820, 0x206a002e, 0x206a002e, 0x206a002e, 0x206a002e},
686 {0x00009824, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0},
687 {0x00009828, 0x06903081, 0x06903081, 0x06903881, 0x06903881},
688 {0x0000982c, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4},
689 {0x00009830, 0x0000059c, 0x0000059c, 0x0000059c, 0x0000059c},
690 {0x00009c00, 0x00000044, 0x00000044, 0x00000044, 0x00000044},
691 {0x00009e00, 0x0372161e, 0x0372161e, 0x037216a0, 0x037216a0},
692 {0x00009e04, 0x00182020, 0x00182020, 0x00182020, 0x00182020},
693 {0x00009e0c, 0x6c4000e2, 0x6d4000e2, 0x6d4000e2, 0x6c4000e2},
694 {0x00009e10, 0x7ec88d2e, 0x7ec88d2e, 0x7ec80d2e, 0x7ec80d2e},
695 {0x00009e14, 0x31395d5e, 0x3139605e, 0x3139605e, 0x31395d5e},
696 {0x00009e18, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
697 {0x00009e1c, 0x0001cf9c, 0x0001cf9c, 0x00021f9c, 0x00021f9c},
698 {0x00009e20, 0x000003b5, 0x000003b5, 0x000003ce, 0x000003ce},
699 {0x00009e2c, 0x0000001c, 0x0000001c, 0x00000021, 0x00000021},
700 {0x00009e3c, 0xcf946220, 0xcf946220, 0xcf946222, 0xcf946222},
701 {0x00009e44, 0x02321e27, 0x02321e27, 0x02282324, 0x02282324},
702 {0x00009e48, 0x5030201a, 0x5030201a, 0x50302010, 0x50302010},
703 {0x00009fc8, 0x0003f000, 0x0003f000, 0x0001a000, 0x0001a000},
704 {0x0000a204, 0x01303fc0, 0x01303fc4, 0x01303fc4, 0x01303fc0},
705 {0x0000a208, 0x00000104, 0x00000104, 0x00000004, 0x00000004},
706 {0x0000a230, 0x0000400a, 0x00004014, 0x00004016, 0x0000400b},
707 {0x0000a234, 0x10000fff, 0x10000fff, 0x10000fff, 0x10000fff},
708 {0x0000a238, 0xffb81018, 0xffb81018, 0xffb81018, 0xffb81018},
709 {0x0000a250, 0x00000000, 0x00000000, 0x00000210, 0x00000108},
710 {0x0000a254, 0x000007d0, 0x00000fa0, 0x00001130, 0x00000898},
711 {0x0000a258, 0x02020002, 0x02020002, 0x02020002, 0x02020002},
712 {0x0000a25c, 0x01000e0e, 0x01000e0e, 0x01000e0e, 0x01000e0e},
713 {0x0000a260, 0x3a021501, 0x3a021501, 0x3a021501, 0x3a021501},
714 {0x0000a264, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e},
715 {0x0000a280, 0x00000007, 0x00000007, 0x0000000b, 0x0000000b},
716 {0x0000a284, 0x00000000, 0x00000000, 0x000002a0, 0x000002a0},
717 {0x0000a288, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
718 {0x0000a28c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
719 {0x0000a2c4, 0x00158d18, 0x00158d18, 0x00158d18, 0x00158d18},
720 {0x0000a2d0, 0x00071981, 0x00071981, 0x00071981, 0x00071982},
721 {0x0000a2d8, 0xf999a83a, 0xf999a83a, 0xf999a83a, 0xf999a83a},
722 {0x0000a358, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
723 {0x0000be04, 0x00802020, 0x00802020, 0x00802020, 0x00802020},
724 {0x0000be18, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
725};
726
727static const u32 ar9485Modes_low_ob_db_tx_gain_1_0[][5] = {
728 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
729 {0x0000a410, 0x000050d9, 0x000050d9, 0x000050d8, 0x000050d8},
730 {0x0000a500, 0x00022200, 0x00022200, 0x00000000, 0x00000000},
731 {0x0000a504, 0x05062002, 0x05062002, 0x04000002, 0x04000002},
732 {0x0000a508, 0x0c002e00, 0x0c002e00, 0x08000004, 0x08000004},
733 {0x0000a50c, 0x11062202, 0x11062202, 0x0d000200, 0x0d000200},
734 {0x0000a510, 0x17022e00, 0x17022e00, 0x11000202, 0x11000202},
735 {0x0000a514, 0x1d000ec2, 0x1d000ec2, 0x15000400, 0x15000400},
736 {0x0000a518, 0x25020ec0, 0x25020ec0, 0x19000402, 0x19000402},
737 {0x0000a51c, 0x2b020ec3, 0x2b020ec3, 0x1d000404, 0x1d000404},
738 {0x0000a520, 0x2f001f04, 0x2f001f04, 0x21000603, 0x21000603},
739 {0x0000a524, 0x35001fc4, 0x35001fc4, 0x25000605, 0x25000605},
740 {0x0000a528, 0x3c022f04, 0x3c022f04, 0x2a000a03, 0x2a000a03},
741 {0x0000a52c, 0x41023e85, 0x41023e85, 0x2c000a04, 0x2c000a04},
742 {0x0000a530, 0x48023ec6, 0x48023ec6, 0x2e000a20, 0x2e000a20},
743 {0x0000a534, 0x4d023f01, 0x4d023f01, 0x34000e20, 0x34000e20},
744 {0x0000a538, 0x53023f4b, 0x53023f4b, 0x38000e22, 0x38000e22},
745 {0x0000a53c, 0x5a027f09, 0x5a027f09, 0x3c000e24, 0x3c000e24},
746 {0x0000a540, 0x5f027fc9, 0x5f027fc9, 0x40000e26, 0x40000e26},
747 {0x0000a544, 0x6502feca, 0x6502feca, 0x43001640, 0x43001640},
748 {0x0000a548, 0x6b02ff4a, 0x6b02ff4a, 0x46001660, 0x46001660},
749 {0x0000a54c, 0x7203feca, 0x7203feca, 0x49001861, 0x49001861},
750 {0x0000a550, 0x7703ff0b, 0x7703ff0b, 0x4c001a81, 0x4c001a81},
751 {0x0000a554, 0x7d06ffcb, 0x7d06ffcb, 0x4f001a83, 0x4f001a83},
752 {0x0000a558, 0x8407ff0b, 0x8407ff0b, 0x54001c85, 0x54001c85},
753 {0x0000a55c, 0x8907ffcb, 0x8907ffcb, 0x58001ce5, 0x58001ce5},
754 {0x0000a560, 0x900fff0b, 0x900fff0b, 0x5b001ce9, 0x5b001ce9},
755 {0x0000a564, 0x960fffcb, 0x960fffcb, 0x60001eeb, 0x60001eeb},
756 {0x0000a568, 0x9c1fff0b, 0x9c1fff0b, 0x60001eeb, 0x60001eeb},
757 {0x0000a56c, 0x9c1fff0b, 0x9c1fff0b, 0x60001eeb, 0x60001eeb},
758 {0x0000a570, 0x9c1fff0b, 0x9c1fff0b, 0x60001eeb, 0x60001eeb},
759 {0x0000a574, 0x9c1fff0b, 0x9c1fff0b, 0x60001eeb, 0x60001eeb},
760 {0x0000a578, 0x9c1fff0b, 0x9c1fff0b, 0x60001eeb, 0x60001eeb},
761 {0x0000a57c, 0x9c1fff0b, 0x9c1fff0b, 0x60001eeb, 0x60001eeb},
762 {0x00016044, 0x05b6b2db, 0x05b6b2db, 0x05b6b2db, 0x05b6b2db},
763};
764
765static const u32 ar9485_1_0_pcie_phy_clkreq_disable_L1[][2] = {
766 /* Addr allmodes */
767 {0x00018c00, 0x10213e5e},
768 {0x00018c04, 0x000801d8},
769 {0x00018c08, 0x0000580c},
770};
771
772static const u32 ar9485_1_0_radio_postamble[][2] = {
773 /* Addr allmodes */
774 {0x0001609c, 0x0b283f31},
775 {0x000160ac, 0x24611800},
776 {0x000160b0, 0x03284f3e},
777 {0x0001610c, 0x00170000},
778 {0x00016140, 0x10804008},
779};
780
781static const u32 ar9485_1_0_mac_core[][2] = {
782 /* Addr allmodes */
783 {0x00000008, 0x00000000},
784 {0x00000030, 0x00020085},
785 {0x00000034, 0x00000005},
786 {0x00000040, 0x00000000},
787 {0x00000044, 0x00000000},
788 {0x00000048, 0x00000008},
789 {0x0000004c, 0x00000010},
790 {0x00000050, 0x00000000},
791 {0x00001040, 0x002ffc0f},
792 {0x00001044, 0x002ffc0f},
793 {0x00001048, 0x002ffc0f},
794 {0x0000104c, 0x002ffc0f},
795 {0x00001050, 0x002ffc0f},
796 {0x00001054, 0x002ffc0f},
797 {0x00001058, 0x002ffc0f},
798 {0x0000105c, 0x002ffc0f},
799 {0x00001060, 0x002ffc0f},
800 {0x00001064, 0x002ffc0f},
801 {0x000010f0, 0x00000100},
802 {0x00001270, 0x00000000},
803 {0x000012b0, 0x00000000},
804 {0x000012f0, 0x00000000},
805 {0x0000143c, 0x00000000},
806 {0x0000147c, 0x00000000},
807 {0x00008000, 0x00000000},
808 {0x00008004, 0x00000000},
809 {0x00008008, 0x00000000},
810 {0x0000800c, 0x00000000},
811 {0x00008018, 0x00000000},
812 {0x00008020, 0x00000000},
813 {0x00008038, 0x00000000},
814 {0x0000803c, 0x00000000},
815 {0x00008040, 0x00000000},
816 {0x00008044, 0x00000000},
817 {0x00008048, 0x00000000},
818 {0x0000804c, 0xffffffff},
819 {0x00008054, 0x00000000},
820 {0x00008058, 0x00000000},
821 {0x0000805c, 0x000fc78f},
822 {0x00008060, 0x0000000f},
823 {0x00008064, 0x00000000},
824 {0x00008070, 0x00000310},
825 {0x00008074, 0x00000020},
826 {0x00008078, 0x00000000},
827 {0x0000809c, 0x0000000f},
828 {0x000080a0, 0x00000000},
829 {0x000080a4, 0x02ff0000},
830 {0x000080a8, 0x0e070605},
831 {0x000080ac, 0x0000000d},
832 {0x000080b0, 0x00000000},
833 {0x000080b4, 0x00000000},
834 {0x000080b8, 0x00000000},
835 {0x000080bc, 0x00000000},
836 {0x000080c0, 0x2a800000},
837 {0x000080c4, 0x06900168},
838 {0x000080c8, 0x13881c20},
839 {0x000080cc, 0x01f40000},
840 {0x000080d0, 0x00252500},
841 {0x000080d4, 0x00a00000},
842 {0x000080d8, 0x00400000},
843 {0x000080dc, 0x00000000},
844 {0x000080e0, 0xffffffff},
845 {0x000080e4, 0x0000ffff},
846 {0x000080e8, 0x3f3f3f3f},
847 {0x000080ec, 0x00000000},
848 {0x000080f0, 0x00000000},
849 {0x000080f4, 0x00000000},
850 {0x000080fc, 0x00020000},
851 {0x00008100, 0x00000000},
852 {0x00008108, 0x00000052},
853 {0x0000810c, 0x00000000},
854 {0x00008110, 0x00000000},
855 {0x00008114, 0x000007ff},
856 {0x00008118, 0x000000aa},
857 {0x0000811c, 0x00003210},
858 {0x00008124, 0x00000000},
859 {0x00008128, 0x00000000},
860 {0x0000812c, 0x00000000},
861 {0x00008130, 0x00000000},
862 {0x00008134, 0x00000000},
863 {0x00008138, 0x00000000},
864 {0x0000813c, 0x0000ffff},
865 {0x00008144, 0xffffffff},
866 {0x00008168, 0x00000000},
867 {0x0000816c, 0x00000000},
868 {0x00008170, 0x18486200},
869 {0x00008174, 0x33332210},
870 {0x00008178, 0x00000000},
871 {0x0000817c, 0x00020000},
872 {0x000081c0, 0x00000000},
873 {0x000081c4, 0x33332210},
874 {0x000081c8, 0x00000000},
875 {0x000081cc, 0x00000000},
876 {0x000081d4, 0x00000000},
877 {0x000081ec, 0x00000000},
878 {0x000081f0, 0x00000000},
879 {0x000081f4, 0x00000000},
880 {0x000081f8, 0x00000000},
881 {0x000081fc, 0x00000000},
882 {0x00008240, 0x00100000},
883 {0x00008244, 0x0010f400},
884 {0x00008248, 0x00000800},
885 {0x0000824c, 0x0001e800},
886 {0x00008250, 0x00000000},
887 {0x00008254, 0x00000000},
888 {0x00008258, 0x00000000},
889 {0x0000825c, 0x40000000},
890 {0x00008260, 0x00080922},
891 {0x00008264, 0x9ca00010},
892 {0x00008268, 0xffffffff},
893 {0x0000826c, 0x0000ffff},
894 {0x00008270, 0x00000000},
895 {0x00008274, 0x40000000},
896 {0x00008278, 0x003e4180},
897 {0x0000827c, 0x00000004},
898 {0x00008284, 0x0000002c},
899 {0x00008288, 0x0000002c},
900 {0x0000828c, 0x000000ff},
901 {0x00008294, 0x00000000},
902 {0x00008298, 0x00000000},
903 {0x0000829c, 0x00000000},
904 {0x00008300, 0x00000140},
905 {0x00008314, 0x00000000},
906 {0x0000831c, 0x0000010d},
907 {0x00008328, 0x00000000},
908 {0x0000832c, 0x00000007},
909 {0x00008330, 0x00000302},
910 {0x00008334, 0x00000700},
911 {0x00008338, 0x00ff0000},
912 {0x0000833c, 0x02400000},
913 {0x00008340, 0x000107ff},
914 {0x00008344, 0xa248105b},
915 {0x00008348, 0x008f0000},
916 {0x0000835c, 0x00000000},
917 {0x00008360, 0xffffffff},
918 {0x00008364, 0xffffffff},
919 {0x00008368, 0x00000000},
920 {0x00008370, 0x00000000},
921 {0x00008374, 0x000000ff},
922 {0x00008378, 0x00000000},
923 {0x0000837c, 0x00000000},
924 {0x00008380, 0xffffffff},
925 {0x00008384, 0xffffffff},
926 {0x00008390, 0xffffffff},
927 {0x00008394, 0xffffffff},
928 {0x00008398, 0x00000000},
929 {0x0000839c, 0x00000000},
930 {0x000083a0, 0x00000000},
931 {0x000083a4, 0x0000fa14},
932 {0x000083a8, 0x000f0c00},
933 {0x000083ac, 0x33332210},
934 {0x000083b0, 0x33332210},
935 {0x000083b4, 0x33332210},
936 {0x000083b8, 0x33332210},
937 {0x000083bc, 0x00000000},
938 {0x000083c0, 0x00000000},
939 {0x000083c4, 0x00000000},
940 {0x000083c8, 0x00000000},
941 {0x000083cc, 0x00000200},
942 {0x000083d0, 0x000301ff},
943};
944
945static const u32 ar9485_1_1_mac_core[][2] = { 20static const u32 ar9485_1_1_mac_core[][2] = {
946 /* Addr allmodes */ 21 /* Addr allmodes */
947 {0x00000008, 0x00000000}, 22 {0x00000008, 0x00000000},
diff --git a/drivers/net/wireless/ath/ath9k/ath9k.h b/drivers/net/wireless/ath/ath9k/ath9k.h
index 099bd4183ad..7c91ba4dce4 100644
--- a/drivers/net/wireless/ath/ath9k/ath9k.h
+++ b/drivers/net/wireless/ath/ath9k/ath9k.h
@@ -362,7 +362,7 @@ struct ath_vif {
362 * number of BSSIDs) if a given beacon does not go out even after waiting this 362 * number of BSSIDs) if a given beacon does not go out even after waiting this
363 * number of beacon intervals, the game's up. 363 * number of beacon intervals, the game's up.
364 */ 364 */
365#define BSTUCK_THRESH (9 * ATH_BCBUF) 365#define BSTUCK_THRESH 9
366#define ATH_BCBUF 4 366#define ATH_BCBUF 4
367#define ATH_DEFAULT_BINTVAL 100 /* TU */ 367#define ATH_DEFAULT_BINTVAL 100 /* TU */
368#define ATH_DEFAULT_BMISS_LIMIT 10 368#define ATH_DEFAULT_BMISS_LIMIT 10
@@ -386,7 +386,7 @@ struct ath_beacon {
386 u32 beaconq; 386 u32 beaconq;
387 u32 bmisscnt; 387 u32 bmisscnt;
388 u32 ast_be_xmit; 388 u32 ast_be_xmit;
389 u64 bc_tstamp; 389 u32 bc_tstamp;
390 struct ieee80211_vif *bslot[ATH_BCBUF]; 390 struct ieee80211_vif *bslot[ATH_BCBUF];
391 int slottime; 391 int slottime;
392 int slotupdate; 392 int slotupdate;
diff --git a/drivers/net/wireless/ath/ath9k/beacon.c b/drivers/net/wireless/ath/ath9k/beacon.c
index 6d2a545fc35..74f33bc193f 100644
--- a/drivers/net/wireless/ath/ath9k/beacon.c
+++ b/drivers/net/wireless/ath/ath9k/beacon.c
@@ -57,8 +57,8 @@ int ath_beaconq_config(struct ath_softc *sc)
57 57
58/* 58/*
59 * Associates the beacon frame buffer with a transmit descriptor. Will set 59 * Associates the beacon frame buffer with a transmit descriptor. Will set
60 * up all required antenna switch parameters, rate codes, and channel flags. 60 * up rate codes, and channel flags. Beacons are always sent out at the
61 * Beacons are always sent out at the lowest rate, and are not retried. 61 * lowest rate, and are not retried.
62*/ 62*/
63static void ath_beacon_setup(struct ath_softc *sc, struct ath_vif *avp, 63static void ath_beacon_setup(struct ath_softc *sc, struct ath_vif *avp,
64 struct ath_buf *bf, int rateidx) 64 struct ath_buf *bf, int rateidx)
@@ -68,7 +68,7 @@ static void ath_beacon_setup(struct ath_softc *sc, struct ath_vif *avp,
68 struct ath_common *common = ath9k_hw_common(ah); 68 struct ath_common *common = ath9k_hw_common(ah);
69 struct ath_desc *ds; 69 struct ath_desc *ds;
70 struct ath9k_11n_rate_series series[4]; 70 struct ath9k_11n_rate_series series[4];
71 int flags, antenna, ctsrate = 0, ctsduration = 0; 71 int flags, ctsrate = 0, ctsduration = 0;
72 struct ieee80211_supported_band *sband; 72 struct ieee80211_supported_band *sband;
73 u8 rate = 0; 73 u8 rate = 0;
74 74
@@ -76,12 +76,6 @@ static void ath_beacon_setup(struct ath_softc *sc, struct ath_vif *avp,
76 flags = ATH9K_TXDESC_NOACK; 76 flags = ATH9K_TXDESC_NOACK;
77 77
78 ds->ds_link = 0; 78 ds->ds_link = 0;
79 /*
80 * Switch antenna every beacon.
81 * Should only switch every beacon period, not for every SWBA
82 * XXX assumes two antennae
83 */
84 antenna = ((sc->beacon.ast_be_xmit / sc->nbcnvifs) & 1 ? 2 : 1);
85 79
86 sband = &sc->sbands[common->hw->conf.channel->band]; 80 sband = &sc->sbands[common->hw->conf.channel->band];
87 rate = sband->bitrates[rateidx].hw_value; 81 rate = sband->bitrates[rateidx].hw_value;
@@ -278,7 +272,7 @@ int ath_beacon_alloc(struct ath_softc *sc, struct ieee80211_vif *vif)
278 return -ENOMEM; 272 return -ENOMEM;
279 273
280 tstamp = ((struct ieee80211_mgmt *)skb->data)->u.beacon.timestamp; 274 tstamp = ((struct ieee80211_mgmt *)skb->data)->u.beacon.timestamp;
281 sc->beacon.bc_tstamp = le64_to_cpu(tstamp); 275 sc->beacon.bc_tstamp = (u32) le64_to_cpu(tstamp);
282 /* Calculate a TSF adjustment factor required for staggered beacons. */ 276 /* Calculate a TSF adjustment factor required for staggered beacons. */
283 if (avp->av_bslot > 0) { 277 if (avp->av_bslot > 0) {
284 u64 tsfadjust; 278 u64 tsfadjust;
@@ -294,8 +288,8 @@ int ath_beacon_alloc(struct ath_softc *sc, struct ieee80211_vif *vif)
294 * adjustment. Other slots are adjusted to get the timestamp 288 * adjustment. Other slots are adjusted to get the timestamp
295 * close to the TBTT for the BSS. 289 * close to the TBTT for the BSS.
296 */ 290 */
297 tsfadjust = intval * avp->av_bslot / ATH_BCBUF; 291 tsfadjust = TU_TO_USEC(intval * avp->av_bslot) / ATH_BCBUF;
298 avp->tsf_adjust = cpu_to_le64(TU_TO_USEC(tsfadjust)); 292 avp->tsf_adjust = cpu_to_le64(tsfadjust);
299 293
300 ath_dbg(common, ATH_DBG_BEACON, 294 ath_dbg(common, ATH_DBG_BEACON,
301 "stagger beacons, bslot %d intval %u tsfadjust %llu\n", 295 "stagger beacons, bslot %d intval %u tsfadjust %llu\n",
@@ -369,12 +363,13 @@ void ath_beacon_tasklet(unsigned long data)
369 if (ath9k_hw_numtxpending(ah, sc->beacon.beaconq) != 0) { 363 if (ath9k_hw_numtxpending(ah, sc->beacon.beaconq) != 0) {
370 sc->beacon.bmisscnt++; 364 sc->beacon.bmisscnt++;
371 365
372 if (sc->beacon.bmisscnt < BSTUCK_THRESH) { 366 if (sc->beacon.bmisscnt < BSTUCK_THRESH * sc->nbcnvifs) {
373 ath_dbg(common, ATH_DBG_BSTUCK, 367 ath_dbg(common, ATH_DBG_BSTUCK,
374 "missed %u consecutive beacons\n", 368 "missed %u consecutive beacons\n",
375 sc->beacon.bmisscnt); 369 sc->beacon.bmisscnt);
376 ath9k_hw_stop_dma_queue(ah, sc->beacon.beaconq); 370 ath9k_hw_stop_dma_queue(ah, sc->beacon.beaconq);
377 ath9k_hw_bstuck_nfcal(ah); 371 if (sc->beacon.bmisscnt > 3)
372 ath9k_hw_bstuck_nfcal(ah);
378 } else if (sc->beacon.bmisscnt >= BSTUCK_THRESH) { 373 } else if (sc->beacon.bmisscnt >= BSTUCK_THRESH) {
379 ath_dbg(common, ATH_DBG_BSTUCK, 374 ath_dbg(common, ATH_DBG_BSTUCK,
380 "beacon is officially stuck\n"); 375 "beacon is officially stuck\n");
@@ -385,13 +380,6 @@ void ath_beacon_tasklet(unsigned long data)
385 return; 380 return;
386 } 381 }
387 382
388 if (sc->beacon.bmisscnt != 0) {
389 ath_dbg(common, ATH_DBG_BSTUCK,
390 "resume beacon xmit after %u misses\n",
391 sc->beacon.bmisscnt);
392 sc->beacon.bmisscnt = 0;
393 }
394
395 /* 383 /*
396 * Generate beacon frames. we are sending frames 384 * Generate beacon frames. we are sending frames
397 * staggered so calculate the slot for this frame based 385 * staggered so calculate the slot for this frame based
@@ -401,8 +389,9 @@ void ath_beacon_tasklet(unsigned long data)
401 intval = cur_conf->beacon_interval ? : ATH_DEFAULT_BINTVAL; 389 intval = cur_conf->beacon_interval ? : ATH_DEFAULT_BINTVAL;
402 390
403 tsf = ath9k_hw_gettsf64(ah); 391 tsf = ath9k_hw_gettsf64(ah);
404 tsftu = TSF_TO_TU(tsf>>32, tsf); 392 tsf += TU_TO_USEC(ah->config.sw_beacon_response_time);
405 slot = ((tsftu % intval) * ATH_BCBUF) / intval; 393 tsftu = TSF_TO_TU((tsf * ATH_BCBUF) >>32, tsf * ATH_BCBUF);
394 slot = (tsftu % (intval * ATH_BCBUF)) / intval;
406 /* 395 /*
407 * Reverse the slot order to get slot 0 on the TBTT offset that does 396 * Reverse the slot order to get slot 0 on the TBTT offset that does
408 * not require TSF adjustment and other slots adding 397 * not require TSF adjustment and other slots adding
@@ -415,7 +404,7 @@ void ath_beacon_tasklet(unsigned long data)
415 404
416 ath_dbg(common, ATH_DBG_BEACON, 405 ath_dbg(common, ATH_DBG_BEACON,
417 "slot %d [tsf %llu tsftu %u intval %u] vif %p\n", 406 "slot %d [tsf %llu tsftu %u intval %u] vif %p\n",
418 slot, tsf, tsftu, intval, vif); 407 slot, tsf, tsftu / ATH_BCBUF, intval, vif);
419 408
420 bfaddr = 0; 409 bfaddr = 0;
421 if (vif) { 410 if (vif) {
@@ -424,6 +413,13 @@ void ath_beacon_tasklet(unsigned long data)
424 bfaddr = bf->bf_daddr; 413 bfaddr = bf->bf_daddr;
425 bc = 1; 414 bc = 1;
426 } 415 }
416
417 if (sc->beacon.bmisscnt != 0) {
418 ath_dbg(common, ATH_DBG_BSTUCK,
419 "resume beacon xmit after %u misses\n",
420 sc->beacon.bmisscnt);
421 sc->beacon.bmisscnt = 0;
422 }
427 } 423 }
428 424
429 /* 425 /*
@@ -463,13 +459,17 @@ static void ath9k_beacon_init(struct ath_softc *sc,
463 u32 next_beacon, 459 u32 next_beacon,
464 u32 beacon_period) 460 u32 beacon_period)
465{ 461{
466 if (beacon_period & ATH9K_BEACON_RESET_TSF) 462 if (sc->sc_flags & SC_OP_TSF_RESET) {
467 ath9k_ps_wakeup(sc); 463 ath9k_ps_wakeup(sc);
464 ath9k_hw_reset_tsf(sc->sc_ah);
465 }
468 466
469 ath9k_hw_beaconinit(sc->sc_ah, next_beacon, beacon_period); 467 ath9k_hw_beaconinit(sc->sc_ah, next_beacon, beacon_period);
470 468
471 if (beacon_period & ATH9K_BEACON_RESET_TSF) 469 if (sc->sc_flags & SC_OP_TSF_RESET) {
472 ath9k_ps_restore(sc); 470 ath9k_ps_restore(sc);
471 sc->sc_flags &= ~SC_OP_TSF_RESET;
472 }
473} 473}
474 474
475/* 475/*
@@ -484,18 +484,14 @@ static void ath_beacon_config_ap(struct ath_softc *sc,
484 u32 nexttbtt, intval; 484 u32 nexttbtt, intval;
485 485
486 /* NB: the beacon interval is kept internally in TU's */ 486 /* NB: the beacon interval is kept internally in TU's */
487 intval = conf->beacon_interval & ATH9K_BEACON_PERIOD; 487 intval = TU_TO_USEC(conf->beacon_interval & ATH9K_BEACON_PERIOD);
488 intval /= ATH_BCBUF; /* for staggered beacons */ 488 intval /= ATH_BCBUF; /* for staggered beacons */
489 nexttbtt = intval; 489 nexttbtt = intval;
490 490
491 if (sc->sc_flags & SC_OP_TSF_RESET)
492 intval |= ATH9K_BEACON_RESET_TSF;
493
494 /* 491 /*
495 * In AP mode we enable the beacon timers and SWBA interrupts to 492 * In AP mode we enable the beacon timers and SWBA interrupts to
496 * prepare beacon frames. 493 * prepare beacon frames.
497 */ 494 */
498 intval |= ATH9K_BEACON_ENA;
499 ah->imask |= ATH9K_INT_SWBA; 495 ah->imask |= ATH9K_INT_SWBA;
500 ath_beaconq_config(sc); 496 ath_beaconq_config(sc);
501 497
@@ -505,11 +501,6 @@ static void ath_beacon_config_ap(struct ath_softc *sc,
505 ath9k_beacon_init(sc, nexttbtt, intval); 501 ath9k_beacon_init(sc, nexttbtt, intval);
506 sc->beacon.bmisscnt = 0; 502 sc->beacon.bmisscnt = 0;
507 ath9k_hw_set_interrupts(ah, ah->imask); 503 ath9k_hw_set_interrupts(ah, ah->imask);
508
509 /* Clear the reset TSF flag, so that subsequent beacon updation
510 will not reset the HW TSF. */
511
512 sc->sc_flags &= ~SC_OP_TSF_RESET;
513} 504}
514 505
515/* 506/*
@@ -643,25 +634,20 @@ static void ath_beacon_config_adhoc(struct ath_softc *sc,
643{ 634{
644 struct ath_hw *ah = sc->sc_ah; 635 struct ath_hw *ah = sc->sc_ah;
645 struct ath_common *common = ath9k_hw_common(ah); 636 struct ath_common *common = ath9k_hw_common(ah);
646 u64 tsf; 637 u32 tsf, delta, intval, nexttbtt;
647 u32 tsftu, intval, nexttbtt; 638
648 639 tsf = ath9k_hw_gettsf32(ah) + TU_TO_USEC(FUDGE);
649 intval = conf->beacon_interval & ATH9K_BEACON_PERIOD; 640 intval = TU_TO_USEC(conf->beacon_interval & ATH9K_BEACON_PERIOD);
650 641
651 642 if (!sc->beacon.bc_tstamp)
652 /* Pull nexttbtt forward to reflect the current TSF */ 643 nexttbtt = tsf + intval;
653 644 else {
654 nexttbtt = TSF_TO_TU(sc->beacon.bc_tstamp >> 32, sc->beacon.bc_tstamp); 645 if (tsf > sc->beacon.bc_tstamp)
655 if (nexttbtt == 0) 646 delta = (tsf - sc->beacon.bc_tstamp);
656 nexttbtt = intval; 647 else
657 else if (intval) 648 delta = (tsf + 1 + (~0U - sc->beacon.bc_tstamp));
658 nexttbtt = roundup(nexttbtt, intval); 649 nexttbtt = tsf + roundup(delta, intval);
659 650 }
660 tsf = ath9k_hw_gettsf64(ah);
661 tsftu = TSF_TO_TU((u32)(tsf>>32), (u32)tsf) + FUDGE;
662 do {
663 nexttbtt += intval;
664 } while (nexttbtt < tsftu);
665 651
666 ath_dbg(common, ATH_DBG_BEACON, 652 ath_dbg(common, ATH_DBG_BEACON,
667 "IBSS nexttbtt %u intval %u (%u)\n", 653 "IBSS nexttbtt %u intval %u (%u)\n",
@@ -672,7 +658,6 @@ static void ath_beacon_config_adhoc(struct ath_softc *sc,
672 * if we need to manually prepare beacon frames. Otherwise we use a 658 * if we need to manually prepare beacon frames. Otherwise we use a
673 * self-linked tx descriptor and let the hardware deal with things. 659 * self-linked tx descriptor and let the hardware deal with things.
674 */ 660 */
675 intval |= ATH9K_BEACON_ENA;
676 ah->imask |= ATH9K_INT_SWBA; 661 ah->imask |= ATH9K_INT_SWBA;
677 662
678 ath_beaconq_config(sc); 663 ath_beaconq_config(sc);
diff --git a/drivers/net/wireless/ath/ath9k/debug.c b/drivers/net/wireless/ath/ath9k/debug.c
index 8df5a92a20f..a762cadb3ab 100644
--- a/drivers/net/wireless/ath/ath9k/debug.c
+++ b/drivers/net/wireless/ath/ath9k/debug.c
@@ -1088,67 +1088,43 @@ int ath9k_init_debug(struct ath_hw *ah)
1088 return -ENOMEM; 1088 return -ENOMEM;
1089 1089
1090#ifdef CONFIG_ATH_DEBUG 1090#ifdef CONFIG_ATH_DEBUG
1091 if (!debugfs_create_file("debug", S_IRUSR | S_IWUSR, 1091 debugfs_create_file("debug", S_IRUSR | S_IWUSR, sc->debug.debugfs_phy,
1092 sc->debug.debugfs_phy, sc, &fops_debug)) 1092 sc, &fops_debug);
1093 goto err;
1094#endif 1093#endif
1095 1094 debugfs_create_file("dma", S_IRUSR, sc->debug.debugfs_phy, sc,
1096 if (!debugfs_create_file("dma", S_IRUSR, sc->debug.debugfs_phy, 1095 &fops_dma);
1097 sc, &fops_dma)) 1096 debugfs_create_file("interrupt", S_IRUSR, sc->debug.debugfs_phy, sc,
1098 goto err; 1097 &fops_interrupt);
1099 1098 debugfs_create_file("wiphy", S_IRUSR | S_IWUSR, sc->debug.debugfs_phy,
1100 if (!debugfs_create_file("interrupt", S_IRUSR, sc->debug.debugfs_phy, 1099 sc, &fops_wiphy);
1101 sc, &fops_interrupt)) 1100 debugfs_create_file("xmit", S_IRUSR, sc->debug.debugfs_phy, sc,
1102 goto err; 1101 &fops_xmit);
1103 1102 debugfs_create_file("stations", S_IRUSR, sc->debug.debugfs_phy, sc,
1104 if (!debugfs_create_file("wiphy", S_IRUSR | S_IWUSR, 1103 &fops_stations);
1105 sc->debug.debugfs_phy, sc, &fops_wiphy)) 1104 debugfs_create_file("misc", S_IRUSR, sc->debug.debugfs_phy, sc,
1106 goto err; 1105 &fops_misc);
1107 1106 debugfs_create_file("recv", S_IRUSR, sc->debug.debugfs_phy, sc,
1108 if (!debugfs_create_file("xmit", S_IRUSR, sc->debug.debugfs_phy, 1107 &fops_recv);
1109 sc, &fops_xmit)) 1108 debugfs_create_file("rx_chainmask", S_IRUSR | S_IWUSR,
1110 goto err; 1109 sc->debug.debugfs_phy, sc, &fops_rx_chainmask);
1111 1110 debugfs_create_file("tx_chainmask", S_IRUSR | S_IWUSR,
1112 if (!debugfs_create_file("stations", S_IRUSR, sc->debug.debugfs_phy, 1111 sc->debug.debugfs_phy, sc, &fops_tx_chainmask);
1113 sc, &fops_stations)) 1112 debugfs_create_file("regidx", S_IRUSR | S_IWUSR, sc->debug.debugfs_phy,
1114 goto err; 1113 sc, &fops_regidx);
1115 1114 debugfs_create_file("regval", S_IRUSR | S_IWUSR, sc->debug.debugfs_phy,
1116 if (!debugfs_create_file("misc", S_IRUSR, sc->debug.debugfs_phy, 1115 sc, &fops_regval);
1117 sc, &fops_misc)) 1116 debugfs_create_bool("ignore_extcca", S_IRUSR | S_IWUSR,
1118 goto err; 1117 sc->debug.debugfs_phy,
1119 1118 &ah->config.cwm_ignore_extcca);
1120 if (!debugfs_create_file("recv", S_IRUSR, sc->debug.debugfs_phy, 1119 debugfs_create_file("regdump", S_IRUSR, sc->debug.debugfs_phy, sc,
1121 sc, &fops_recv)) 1120 &fops_regdump);
1122 goto err; 1121
1123 1122 debugfs_create_u32("gpio_mask", S_IRUSR | S_IWUSR,
1124 if (!debugfs_create_file("rx_chainmask", S_IRUSR | S_IWUSR, 1123 sc->debug.debugfs_phy, &sc->sc_ah->gpio_mask);
1125 sc->debug.debugfs_phy, sc, &fops_rx_chainmask)) 1124
1126 goto err; 1125 debugfs_create_u32("gpio_val", S_IRUSR | S_IWUSR,
1127 1126 sc->debug.debugfs_phy, &sc->sc_ah->gpio_val);
1128 if (!debugfs_create_file("tx_chainmask", S_IRUSR | S_IWUSR,
1129 sc->debug.debugfs_phy, sc, &fops_tx_chainmask))
1130 goto err;
1131
1132 if (!debugfs_create_file("regidx", S_IRUSR | S_IWUSR,
1133 sc->debug.debugfs_phy, sc, &fops_regidx))
1134 goto err;
1135
1136 if (!debugfs_create_file("regval", S_IRUSR | S_IWUSR,
1137 sc->debug.debugfs_phy, sc, &fops_regval))
1138 goto err;
1139
1140 if (!debugfs_create_bool("ignore_extcca", S_IRUSR | S_IWUSR,
1141 sc->debug.debugfs_phy, &ah->config.cwm_ignore_extcca))
1142 goto err;
1143
1144 if (!debugfs_create_file("regdump", S_IRUSR, sc->debug.debugfs_phy,
1145 sc, &fops_regdump))
1146 goto err;
1147 1127
1148 sc->debug.regidx = 0; 1128 sc->debug.regidx = 0;
1149 return 0; 1129 return 0;
1150err:
1151 debugfs_remove_recursive(sc->debug.debugfs_phy);
1152 sc->debug.debugfs_phy = NULL;
1153 return -ENOMEM;
1154} 1130}
diff --git a/drivers/net/wireless/ath/ath9k/eeprom_9287.c b/drivers/net/wireless/ath/ath9k/eeprom_9287.c
index 8cd8333cc08..2f0712ea49a 100644
--- a/drivers/net/wireless/ath/ath9k/eeprom_9287.c
+++ b/drivers/net/wireless/ath/ath9k/eeprom_9287.c
@@ -392,6 +392,8 @@ static void ath9k_hw_set_ar9287_power_cal_table(struct ath_hw *ah,
392 numXpdGain); 392 numXpdGain);
393 } 393 }
394 394
395 ENABLE_REGWRITE_BUFFER(ah);
396
395 if (i == 0) { 397 if (i == 0) {
396 if (!ath9k_hw_ar9287_get_eeprom(ah, 398 if (!ath9k_hw_ar9287_get_eeprom(ah,
397 EEP_OL_PWRCTRL)) { 399 EEP_OL_PWRCTRL)) {
@@ -442,6 +444,7 @@ static void ath9k_hw_set_ar9287_power_cal_table(struct ath_hw *ah,
442 regOffset += 4; 444 regOffset += 4;
443 } 445 }
444 } 446 }
447 REGWRITE_BUFFER_FLUSH(ah);
445 } 448 }
446 } 449 }
447 450
@@ -757,6 +760,8 @@ static void ath9k_hw_ar9287_set_txpower(struct ath_hw *ah,
757 ratesArray[i] -= AR9287_PWR_TABLE_OFFSET_DB * 2; 760 ratesArray[i] -= AR9287_PWR_TABLE_OFFSET_DB * 2;
758 } 761 }
759 762
763 ENABLE_REGWRITE_BUFFER(ah);
764
760 /* OFDM power per rate */ 765 /* OFDM power per rate */
761 REG_WRITE(ah, AR_PHY_POWER_TX_RATE1, 766 REG_WRITE(ah, AR_PHY_POWER_TX_RATE1,
762 ATH9K_POW_SM(ratesArray[rate18mb], 24) 767 ATH9K_POW_SM(ratesArray[rate18mb], 24)
@@ -840,6 +845,7 @@ static void ath9k_hw_ar9287_set_txpower(struct ath_hw *ah,
840 | ATH9K_POW_SM(ratesArray[rateDupOfdm], 8) 845 | ATH9K_POW_SM(ratesArray[rateDupOfdm], 8)
841 | ATH9K_POW_SM(ratesArray[rateDupCck], 0)); 846 | ATH9K_POW_SM(ratesArray[rateDupCck], 0));
842 } 847 }
848 REGWRITE_BUFFER_FLUSH(ah);
843} 849}
844 850
845static void ath9k_hw_ar9287_set_addac(struct ath_hw *ah, 851static void ath9k_hw_ar9287_set_addac(struct ath_hw *ah,
diff --git a/drivers/net/wireless/ath/ath9k/eeprom_def.c b/drivers/net/wireless/ath/ath9k/eeprom_def.c
index fccd87df730..995949ddd63 100644
--- a/drivers/net/wireless/ath/ath9k/eeprom_def.c
+++ b/drivers/net/wireless/ath/ath9k/eeprom_def.c
@@ -799,6 +799,8 @@ static void ath9k_hw_set_def_power_cal_table(struct ath_hw *ah,
799 pwr_table_offset, 799 pwr_table_offset,
800 &diff); 800 &diff);
801 801
802 ENABLE_REGWRITE_BUFFER(ah);
803
802 if ((i == 0) || AR_SREV_5416_20_OR_LATER(ah)) { 804 if ((i == 0) || AR_SREV_5416_20_OR_LATER(ah)) {
803 if (OLC_FOR_AR9280_20_LATER) { 805 if (OLC_FOR_AR9280_20_LATER) {
804 REG_WRITE(ah, 806 REG_WRITE(ah,
@@ -847,6 +849,7 @@ static void ath9k_hw_set_def_power_cal_table(struct ath_hw *ah,
847 849
848 regOffset += 4; 850 regOffset += 4;
849 } 851 }
852 REGWRITE_BUFFER_FLUSH(ah);
850 } 853 }
851 } 854 }
852 855
@@ -1205,6 +1208,8 @@ static void ath9k_hw_def_set_txpower(struct ath_hw *ah,
1205 } 1208 }
1206 } 1209 }
1207 1210
1211 ENABLE_REGWRITE_BUFFER(ah);
1212
1208 REG_WRITE(ah, AR_PHY_POWER_TX_RATE1, 1213 REG_WRITE(ah, AR_PHY_POWER_TX_RATE1,
1209 ATH9K_POW_SM(ratesArray[rate18mb], 24) 1214 ATH9K_POW_SM(ratesArray[rate18mb], 24)
1210 | ATH9K_POW_SM(ratesArray[rate12mb], 16) 1215 | ATH9K_POW_SM(ratesArray[rate12mb], 16)
@@ -1291,6 +1296,8 @@ static void ath9k_hw_def_set_txpower(struct ath_hw *ah,
1291 REG_WRITE(ah, AR_PHY_POWER_TX_SUB, 1296 REG_WRITE(ah, AR_PHY_POWER_TX_SUB,
1292 ATH9K_POW_SM(pModal->pwrDecreaseFor3Chain, 6) 1297 ATH9K_POW_SM(pModal->pwrDecreaseFor3Chain, 6)
1293 | ATH9K_POW_SM(pModal->pwrDecreaseFor2Chain, 0)); 1298 | ATH9K_POW_SM(pModal->pwrDecreaseFor2Chain, 0));
1299
1300 REGWRITE_BUFFER_FLUSH(ah);
1294} 1301}
1295 1302
1296static u16 ath9k_hw_def_get_spur_channel(struct ath_hw *ah, u16 i, bool is2GHz) 1303static u16 ath9k_hw_def_get_spur_channel(struct ath_hw *ah, u16 i, bool is2GHz)
diff --git a/drivers/net/wireless/ath/ath9k/gpio.c b/drivers/net/wireless/ath/ath9k/gpio.c
index 0fb8f8ac275..44a0a886124 100644
--- a/drivers/net/wireless/ath/ath9k/gpio.c
+++ b/drivers/net/wireless/ath/ath9k/gpio.c
@@ -41,12 +41,14 @@ void ath_init_leds(struct ath_softc *sc)
41{ 41{
42 int ret; 42 int ret;
43 43
44 if (AR_SREV_9287(sc->sc_ah)) 44 if (sc->sc_ah->led_pin < 0) {
45 sc->sc_ah->led_pin = ATH_LED_PIN_9287; 45 if (AR_SREV_9287(sc->sc_ah))
46 else if (AR_SREV_9485(sc->sc_ah)) 46 sc->sc_ah->led_pin = ATH_LED_PIN_9287;
47 sc->sc_ah->led_pin = ATH_LED_PIN_9485; 47 else if (AR_SREV_9485(sc->sc_ah))
48 else 48 sc->sc_ah->led_pin = ATH_LED_PIN_9485;
49 sc->sc_ah->led_pin = ATH_LED_PIN_DEF; 49 else
50 sc->sc_ah->led_pin = ATH_LED_PIN_DEF;
51 }
50 52
51 /* Configure gpio 1 for output */ 53 /* Configure gpio 1 for output */
52 ath9k_hw_cfg_output(sc->sc_ah, sc->sc_ah->led_pin, 54 ath9k_hw_cfg_output(sc->sc_ah, sc->sc_ah->led_pin,
diff --git a/drivers/net/wireless/ath/ath9k/hif_usb.c b/drivers/net/wireless/ath/ath9k/hif_usb.c
index 7dc20489f2e..f1b8af64569 100644
--- a/drivers/net/wireless/ath/ath9k/hif_usb.c
+++ b/drivers/net/wireless/ath/ath9k/hif_usb.c
@@ -222,8 +222,9 @@ static int __hif_usb_tx(struct hif_device_usb *hif_dev)
222 struct tx_buf *tx_buf = NULL; 222 struct tx_buf *tx_buf = NULL;
223 struct sk_buff *nskb = NULL; 223 struct sk_buff *nskb = NULL;
224 int ret = 0, i; 224 int ret = 0, i;
225 u16 *hdr, tx_skb_cnt = 0; 225 u16 tx_skb_cnt = 0;
226 u8 *buf; 226 u8 *buf;
227 __le16 *hdr;
227 228
228 if (hif_dev->tx.tx_skb_cnt == 0) 229 if (hif_dev->tx.tx_skb_cnt == 0)
229 return 0; 230 return 0;
@@ -248,9 +249,9 @@ static int __hif_usb_tx(struct hif_device_usb *hif_dev)
248 249
249 buf = tx_buf->buf; 250 buf = tx_buf->buf;
250 buf += tx_buf->offset; 251 buf += tx_buf->offset;
251 hdr = (u16 *)buf; 252 hdr = (__le16 *)buf;
252 *hdr++ = nskb->len; 253 *hdr++ = cpu_to_le16(nskb->len);
253 *hdr++ = ATH_USB_TX_STREAM_MODE_TAG; 254 *hdr++ = cpu_to_le16(ATH_USB_TX_STREAM_MODE_TAG);
254 buf += 4; 255 buf += 4;
255 memcpy(buf, nskb->data, nskb->len); 256 memcpy(buf, nskb->data, nskb->len);
256 tx_buf->len = nskb->len + 4; 257 tx_buf->len = nskb->len + 4;
diff --git a/drivers/net/wireless/ath/ath9k/htc.h b/drivers/net/wireless/ath/ath9k/htc.h
index 753a245c5ad..ec47be94b74 100644
--- a/drivers/net/wireless/ath/ath9k/htc.h
+++ b/drivers/net/wireless/ath/ath9k/htc.h
@@ -328,7 +328,7 @@ struct ath9k_debug {
328#endif /* CONFIG_ATH9K_HTC_DEBUGFS */ 328#endif /* CONFIG_ATH9K_HTC_DEBUGFS */
329 329
330#define ATH_LED_PIN_DEF 1 330#define ATH_LED_PIN_DEF 1
331#define ATH_LED_PIN_9287 8 331#define ATH_LED_PIN_9287 10
332#define ATH_LED_PIN_9271 15 332#define ATH_LED_PIN_9271 15
333#define ATH_LED_PIN_7010 12 333#define ATH_LED_PIN_7010 12
334#define ATH_LED_ON_DURATION_IDLE 350 /* in msecs */ 334#define ATH_LED_ON_DURATION_IDLE 350 /* in msecs */
diff --git a/drivers/net/wireless/ath/ath9k/htc_drv_beacon.c b/drivers/net/wireless/ath/ath9k/htc_drv_beacon.c
index 8d1d8792436..8f56158e588 100644
--- a/drivers/net/wireless/ath/ath9k/htc_drv_beacon.c
+++ b/drivers/net/wireless/ath/ath9k/htc_drv_beacon.c
@@ -155,7 +155,7 @@ static void ath9k_htc_beacon_config_ap(struct ath9k_htc_priv *priv,
155 nexttbtt = intval; 155 nexttbtt = intval;
156 156
157 if (priv->op_flags & OP_TSF_RESET) { 157 if (priv->op_flags & OP_TSF_RESET) {
158 intval |= ATH9K_BEACON_RESET_TSF; 158 ath9k_hw_reset_tsf(priv->ah);
159 priv->op_flags &= ~OP_TSF_RESET; 159 priv->op_flags &= ~OP_TSF_RESET;
160 } else { 160 } else {
161 /* 161 /*
@@ -168,8 +168,6 @@ static void ath9k_htc_beacon_config_ap(struct ath9k_htc_priv *priv,
168 } while (nexttbtt < tsftu); 168 } while (nexttbtt < tsftu);
169 } 169 }
170 170
171 intval |= ATH9K_BEACON_ENA;
172
173 if (priv->op_flags & OP_ENABLE_BEACON) 171 if (priv->op_flags & OP_ENABLE_BEACON)
174 imask |= ATH9K_INT_SWBA; 172 imask |= ATH9K_INT_SWBA;
175 173
@@ -178,7 +176,7 @@ static void ath9k_htc_beacon_config_ap(struct ath9k_htc_priv *priv,
178 bss_conf->beacon_interval, nexttbtt, imask); 176 bss_conf->beacon_interval, nexttbtt, imask);
179 177
180 WMI_CMD(WMI_DISABLE_INTR_CMDID); 178 WMI_CMD(WMI_DISABLE_INTR_CMDID);
181 ath9k_hw_beaconinit(priv->ah, nexttbtt, intval); 179 ath9k_hw_beaconinit(priv->ah, TU_TO_USEC(nexttbtt), TU_TO_USEC(intval));
182 priv->bmiss_cnt = 0; 180 priv->bmiss_cnt = 0;
183 htc_imask = cpu_to_be32(imask); 181 htc_imask = cpu_to_be32(imask);
184 WMI_CMD_BUF(WMI_ENABLE_INTR_CMDID, &htc_imask); 182 WMI_CMD_BUF(WMI_ENABLE_INTR_CMDID, &htc_imask);
@@ -207,7 +205,6 @@ static void ath9k_htc_beacon_config_adhoc(struct ath9k_htc_priv *priv,
207 nexttbtt += intval; 205 nexttbtt += intval;
208 } while (nexttbtt < tsftu); 206 } while (nexttbtt < tsftu);
209 207
210 intval |= ATH9K_BEACON_ENA;
211 if (priv->op_flags & OP_ENABLE_BEACON) 208 if (priv->op_flags & OP_ENABLE_BEACON)
212 imask |= ATH9K_INT_SWBA; 209 imask |= ATH9K_INT_SWBA;
213 210
@@ -216,7 +213,7 @@ static void ath9k_htc_beacon_config_adhoc(struct ath9k_htc_priv *priv,
216 bss_conf->beacon_interval, nexttbtt, imask); 213 bss_conf->beacon_interval, nexttbtt, imask);
217 214
218 WMI_CMD(WMI_DISABLE_INTR_CMDID); 215 WMI_CMD(WMI_DISABLE_INTR_CMDID);
219 ath9k_hw_beaconinit(priv->ah, nexttbtt, intval); 216 ath9k_hw_beaconinit(priv->ah, TU_TO_USEC(nexttbtt), TU_TO_USEC(intval));
220 priv->bmiss_cnt = 0; 217 priv->bmiss_cnt = 0;
221 htc_imask = cpu_to_be32(imask); 218 htc_imask = cpu_to_be32(imask);
222 WMI_CMD_BUF(WMI_ENABLE_INTR_CMDID, &htc_imask); 219 WMI_CMD_BUF(WMI_ENABLE_INTR_CMDID, &htc_imask);
diff --git a/drivers/net/wireless/ath/ath9k/htc_drv_init.c b/drivers/net/wireless/ath/ath9k/htc_drv_init.c
index fc67c937e17..8303b34bdc9 100644
--- a/drivers/net/wireless/ath/ath9k/htc_drv_init.c
+++ b/drivers/net/wireless/ath/ath9k/htc_drv_init.c
@@ -430,13 +430,16 @@ static void ath9k_regwrite_flush(void *hw_priv)
430 mutex_unlock(&priv->wmi->multi_write_mutex); 430 mutex_unlock(&priv->wmi->multi_write_mutex);
431} 431}
432 432
433static const struct ath_ops ath9k_common_ops = { 433static u32 ath9k_reg_rmw(void *hw_priv, u32 reg_offset, u32 set, u32 clr)
434 .read = ath9k_regread, 434{
435 .multi_read = ath9k_multi_regread, 435 u32 val;
436 .write = ath9k_regwrite, 436
437 .enable_write_buffer = ath9k_enable_regwrite_buffer, 437 val = ath9k_regread(hw_priv, reg_offset);
438 .write_flush = ath9k_regwrite_flush, 438 val &= ~clr;
439}; 439 val |= set;
440 ath9k_regwrite(hw_priv, val, reg_offset);
441 return val;
442}
440 443
441static void ath_usb_read_cachesize(struct ath_common *common, int *csz) 444static void ath_usb_read_cachesize(struct ath_common *common, int *csz)
442{ 445{
@@ -561,13 +564,7 @@ static void ath9k_init_crypto(struct ath9k_htc_priv *priv)
561 int i = 0; 564 int i = 0;
562 565
563 /* Get the hardware key cache size. */ 566 /* Get the hardware key cache size. */
564 common->keymax = priv->ah->caps.keycache_size; 567 common->keymax = AR_KEYTABLE_SIZE;
565 if (common->keymax > ATH_KEYMAX) {
566 ath_dbg(common, ATH_DBG_ANY,
567 "Warning, using only %u entries in %u key cache\n",
568 ATH_KEYMAX, common->keymax);
569 common->keymax = ATH_KEYMAX;
570 }
571 568
572 if (priv->ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) 569 if (priv->ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA)
573 common->crypt_caps |= ATH_CRYPT_CAP_MIC_COMBINED; 570 common->crypt_caps |= ATH_CRYPT_CAP_MIC_COMBINED;
@@ -658,10 +655,16 @@ static int ath9k_init_priv(struct ath9k_htc_priv *priv,
658 ah->hw_version.subsysid = 0; /* FIXME */ 655 ah->hw_version.subsysid = 0; /* FIXME */
659 ah->hw_version.usbdev = drv_info; 656 ah->hw_version.usbdev = drv_info;
660 ah->ah_flags |= AH_USE_EEPROM; 657 ah->ah_flags |= AH_USE_EEPROM;
658 ah->reg_ops.read = ath9k_regread;
659 ah->reg_ops.multi_read = ath9k_multi_regread;
660 ah->reg_ops.write = ath9k_regwrite;
661 ah->reg_ops.enable_write_buffer = ath9k_enable_regwrite_buffer;
662 ah->reg_ops.write_flush = ath9k_regwrite_flush;
663 ah->reg_ops.rmw = ath9k_reg_rmw;
661 priv->ah = ah; 664 priv->ah = ah;
662 665
663 common = ath9k_hw_common(ah); 666 common = ath9k_hw_common(ah);
664 common->ops = &ath9k_common_ops; 667 common->ops = &ah->reg_ops;
665 common->bus_ops = &ath9k_usb_bus_ops; 668 common->bus_ops = &ath9k_usb_bus_ops;
666 common->ah = ah; 669 common->ah = ah;
667 common->hw = priv->hw; 670 common->hw = priv->hw;
diff --git a/drivers/net/wireless/ath/ath9k/hw.c b/drivers/net/wireless/ath/ath9k/hw.c
index 338b07502f1..298f4d6cbdb 100644
--- a/drivers/net/wireless/ath/ath9k/hw.c
+++ b/drivers/net/wireless/ath/ath9k/hw.c
@@ -130,6 +130,20 @@ bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
130} 130}
131EXPORT_SYMBOL(ath9k_hw_wait); 131EXPORT_SYMBOL(ath9k_hw_wait);
132 132
133void ath9k_hw_write_array(struct ath_hw *ah, struct ar5416IniArray *array,
134 int column, unsigned int *writecnt)
135{
136 int r;
137
138 ENABLE_REGWRITE_BUFFER(ah);
139 for (r = 0; r < array->ia_rows; r++) {
140 REG_WRITE(ah, INI_RA(array, r, 0),
141 INI_RA(array, r, column));
142 DO_DELAY(*writecnt);
143 }
144 REGWRITE_BUFFER_FLUSH(ah);
145}
146
133u32 ath9k_hw_reverse_bits(u32 val, u32 n) 147u32 ath9k_hw_reverse_bits(u32 val, u32 n)
134{ 148{
135 u32 retval; 149 u32 retval;
@@ -364,11 +378,6 @@ static void ath9k_hw_init_config(struct ath_hw *ah)
364 ah->config.spurchans[i][1] = AR_NO_SPUR; 378 ah->config.spurchans[i][1] = AR_NO_SPUR;
365 } 379 }
366 380
367 if (ah->hw_version.devid != AR2427_DEVID_PCIE)
368 ah->config.ht_enable = 1;
369 else
370 ah->config.ht_enable = 0;
371
372 /* PAPRD needs some more work to be enabled */ 381 /* PAPRD needs some more work to be enabled */
373 ah->config.paprd_disable = 1; 382 ah->config.paprd_disable = 1;
374 383
@@ -410,6 +419,8 @@ static void ath9k_hw_init_defaults(struct ath_hw *ah)
410 ah->sta_id1_defaults = 419 ah->sta_id1_defaults =
411 AR_STA_ID1_CRPT_MIC_ENABLE | 420 AR_STA_ID1_CRPT_MIC_ENABLE |
412 AR_STA_ID1_MCAST_KSRCH; 421 AR_STA_ID1_MCAST_KSRCH;
422 if (AR_SREV_9100(ah))
423 ah->sta_id1_defaults |= AR_STA_ID1_AR9100_BA_FIX;
413 ah->enable_32kHz_clock = DONT_USE_32KHZ; 424 ah->enable_32kHz_clock = DONT_USE_32KHZ;
414 ah->slottime = 20; 425 ah->slottime = 20;
415 ah->globaltxtimeout = (u32) -1; 426 ah->globaltxtimeout = (u32) -1;
@@ -673,14 +684,14 @@ static void ath9k_hw_init_qos(struct ath_hw *ah)
673 684
674unsigned long ar9003_get_pll_sqsum_dvc(struct ath_hw *ah) 685unsigned long ar9003_get_pll_sqsum_dvc(struct ath_hw *ah)
675{ 686{
676 REG_WRITE(ah, PLL3, (REG_READ(ah, PLL3) & ~(PLL3_DO_MEAS_MASK))); 687 REG_CLR_BIT(ah, PLL3, PLL3_DO_MEAS_MASK);
677 udelay(100); 688 udelay(100);
678 REG_WRITE(ah, PLL3, (REG_READ(ah, PLL3) | PLL3_DO_MEAS_MASK)); 689 REG_SET_BIT(ah, PLL3, PLL3_DO_MEAS_MASK);
679 690
680 while ((REG_READ(ah, PLL4) & PLL4_MEAS_DONE) == 0) 691 while ((REG_READ(ah, PLL4) & PLL4_MEAS_DONE) == 0)
681 udelay(100); 692 udelay(100);
682 693
683 return (REG_READ(ah, PLL3) & SQSUM_DVC_MASK) >> 3; 694 return (REG_READ(ah, PLL3) & SQSUM_DVC_MASK) >> 3;
684} 695}
685EXPORT_SYMBOL(ar9003_get_pll_sqsum_dvc); 696EXPORT_SYMBOL(ar9003_get_pll_sqsum_dvc);
686 697
@@ -830,8 +841,7 @@ void ath9k_hw_init_global_settings(struct ath_hw *ah)
830 ah->misc_mode); 841 ah->misc_mode);
831 842
832 if (ah->misc_mode != 0) 843 if (ah->misc_mode != 0)
833 REG_WRITE(ah, AR_PCU_MISC, 844 REG_SET_BIT(ah, AR_PCU_MISC, ah->misc_mode);
834 REG_READ(ah, AR_PCU_MISC) | ah->misc_mode);
835 845
836 if (conf->channel && conf->channel->band == IEEE80211_BAND_5GHZ) 846 if (conf->channel && conf->channel->band == IEEE80211_BAND_5GHZ)
837 sifstime = 16; 847 sifstime = 16;
@@ -899,23 +909,19 @@ u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan)
899static inline void ath9k_hw_set_dma(struct ath_hw *ah) 909static inline void ath9k_hw_set_dma(struct ath_hw *ah)
900{ 910{
901 struct ath_common *common = ath9k_hw_common(ah); 911 struct ath_common *common = ath9k_hw_common(ah);
902 u32 regval;
903 912
904 ENABLE_REGWRITE_BUFFER(ah); 913 ENABLE_REGWRITE_BUFFER(ah);
905 914
906 /* 915 /*
907 * set AHB_MODE not to do cacheline prefetches 916 * set AHB_MODE not to do cacheline prefetches
908 */ 917 */
909 if (!AR_SREV_9300_20_OR_LATER(ah)) { 918 if (!AR_SREV_9300_20_OR_LATER(ah))
910 regval = REG_READ(ah, AR_AHB_MODE); 919 REG_SET_BIT(ah, AR_AHB_MODE, AR_AHB_PREFETCH_RD_EN);
911 REG_WRITE(ah, AR_AHB_MODE, regval | AR_AHB_PREFETCH_RD_EN);
912 }
913 920
914 /* 921 /*
915 * let mac dma reads be in 128 byte chunks 922 * let mac dma reads be in 128 byte chunks
916 */ 923 */
917 regval = REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK; 924 REG_RMW(ah, AR_TXCFG, AR_TXCFG_DMASZ_128B, AR_TXCFG_DMASZ_MASK);
918 REG_WRITE(ah, AR_TXCFG, regval | AR_TXCFG_DMASZ_128B);
919 925
920 REGWRITE_BUFFER_FLUSH(ah); 926 REGWRITE_BUFFER_FLUSH(ah);
921 927
@@ -932,8 +938,7 @@ static inline void ath9k_hw_set_dma(struct ath_hw *ah)
932 /* 938 /*
933 * let mac dma writes be in 128 byte chunks 939 * let mac dma writes be in 128 byte chunks
934 */ 940 */
935 regval = REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_DMASZ_MASK; 941 REG_RMW(ah, AR_RXCFG, AR_RXCFG_DMASZ_128B, AR_RXCFG_DMASZ_MASK);
936 REG_WRITE(ah, AR_RXCFG, regval | AR_RXCFG_DMASZ_128B);
937 942
938 /* 943 /*
939 * Setup receive FIFO threshold to hold off TX activities 944 * Setup receive FIFO threshold to hold off TX activities
@@ -972,30 +977,27 @@ static inline void ath9k_hw_set_dma(struct ath_hw *ah)
972 977
973static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode) 978static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode)
974{ 979{
975 u32 val; 980 u32 mask = AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC;
981 u32 set = AR_STA_ID1_KSRCH_MODE;
976 982
977 val = REG_READ(ah, AR_STA_ID1);
978 val &= ~(AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC);
979 switch (opmode) { 983 switch (opmode) {
980 case NL80211_IFTYPE_AP:
981 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_STA_AP
982 | AR_STA_ID1_KSRCH_MODE);
983 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
984 break;
985 case NL80211_IFTYPE_ADHOC: 984 case NL80211_IFTYPE_ADHOC:
986 case NL80211_IFTYPE_MESH_POINT: 985 case NL80211_IFTYPE_MESH_POINT:
987 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_ADHOC 986 set |= AR_STA_ID1_ADHOC;
988 | AR_STA_ID1_KSRCH_MODE);
989 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION); 987 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
990 break; 988 break;
989 case NL80211_IFTYPE_AP:
990 set |= AR_STA_ID1_STA_AP;
991 /* fall through */
991 case NL80211_IFTYPE_STATION: 992 case NL80211_IFTYPE_STATION:
992 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE); 993 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
993 break; 994 break;
994 default: 995 default:
995 if (ah->is_monitoring) 996 if (!ah->is_monitoring)
996 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE); 997 set = 0;
997 break; 998 break;
998 } 999 }
1000 REG_RMW(ah, AR_STA_ID1, set, mask);
999} 1001}
1000 1002
1001void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled, 1003void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled,
@@ -1021,10 +1023,8 @@ static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
1021 u32 tmpReg; 1023 u32 tmpReg;
1022 1024
1023 if (AR_SREV_9100(ah)) { 1025 if (AR_SREV_9100(ah)) {
1024 u32 val = REG_READ(ah, AR_RTC_DERIVED_CLK); 1026 REG_RMW_FIELD(ah, AR_RTC_DERIVED_CLK,
1025 val &= ~AR_RTC_DERIVED_CLK_PERIOD; 1027 AR_RTC_DERIVED_CLK_PERIOD, 1);
1026 val |= SM(1, AR_RTC_DERIVED_CLK_PERIOD);
1027 REG_WRITE(ah, AR_RTC_DERIVED_CLK, val);
1028 (void)REG_READ(ah, AR_RTC_DERIVED_CLK); 1028 (void)REG_READ(ah, AR_RTC_DERIVED_CLK);
1029 } 1029 }
1030 1030
@@ -1212,6 +1212,20 @@ static bool ath9k_hw_channel_change(struct ath_hw *ah,
1212 return true; 1212 return true;
1213} 1213}
1214 1214
1215static void ath9k_hw_apply_gpio_override(struct ath_hw *ah)
1216{
1217 u32 gpio_mask = ah->gpio_mask;
1218 int i;
1219
1220 for (i = 0; gpio_mask; i++, gpio_mask >>= 1) {
1221 if (!(gpio_mask & 1))
1222 continue;
1223
1224 ath9k_hw_cfg_output(ah, i, AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1225 ath9k_hw_set_gpio(ah, i, !!(ah->gpio_val & BIT(i)));
1226 }
1227}
1228
1215bool ath9k_hw_check_alive(struct ath_hw *ah) 1229bool ath9k_hw_check_alive(struct ath_hw *ah)
1216{ 1230{
1217 int count = 50; 1231 int count = 50;
@@ -1418,7 +1432,7 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
1418 REGWRITE_BUFFER_FLUSH(ah); 1432 REGWRITE_BUFFER_FLUSH(ah);
1419 1433
1420 ah->intr_txqs = 0; 1434 ah->intr_txqs = 0;
1421 for (i = 0; i < ah->caps.total_queues; i++) 1435 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1422 ath9k_hw_resettxqueue(ah, i); 1436 ath9k_hw_resettxqueue(ah, i);
1423 1437
1424 ath9k_hw_init_interrupt_masks(ah, ah->opmode); 1438 ath9k_hw_init_interrupt_masks(ah, ah->opmode);
@@ -1435,8 +1449,7 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
1435 ar9002_hw_enable_wep_aggregation(ah); 1449 ar9002_hw_enable_wep_aggregation(ah);
1436 } 1450 }
1437 1451
1438 REG_WRITE(ah, AR_STA_ID1, 1452 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PRESERVE_SEQNUM);
1439 REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PRESERVE_SEQNUM);
1440 1453
1441 ath9k_hw_set_dma(ah); 1454 ath9k_hw_set_dma(ah);
1442 1455
@@ -1500,6 +1513,8 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
1500 if (AR_SREV_9300_20_OR_LATER(ah)) 1513 if (AR_SREV_9300_20_OR_LATER(ah))
1501 ar9003_hw_bb_watchdog_config(ah); 1514 ar9003_hw_bb_watchdog_config(ah);
1502 1515
1516 ath9k_hw_apply_gpio_override(ah);
1517
1503 return 0; 1518 return 0;
1504} 1519}
1505EXPORT_SYMBOL(ath9k_hw_reset); 1520EXPORT_SYMBOL(ath9k_hw_reset);
@@ -1679,21 +1694,15 @@ void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
1679 case NL80211_IFTYPE_MESH_POINT: 1694 case NL80211_IFTYPE_MESH_POINT:
1680 REG_SET_BIT(ah, AR_TXCFG, 1695 REG_SET_BIT(ah, AR_TXCFG,
1681 AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY); 1696 AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
1682 REG_WRITE(ah, AR_NEXT_NDP_TIMER, 1697 REG_WRITE(ah, AR_NEXT_NDP_TIMER, next_beacon +
1683 TU_TO_USEC(next_beacon + 1698 TU_TO_USEC(ah->atim_window ? ah->atim_window : 1));
1684 (ah->atim_window ? ah->
1685 atim_window : 1)));
1686 flags |= AR_NDP_TIMER_EN; 1699 flags |= AR_NDP_TIMER_EN;
1687 case NL80211_IFTYPE_AP: 1700 case NL80211_IFTYPE_AP:
1688 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon)); 1701 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, next_beacon);
1689 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, 1702 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, next_beacon -
1690 TU_TO_USEC(next_beacon - 1703 TU_TO_USEC(ah->config.dma_beacon_response_time));
1691 ah->config. 1704 REG_WRITE(ah, AR_NEXT_SWBA, next_beacon -
1692 dma_beacon_response_time)); 1705 TU_TO_USEC(ah->config.sw_beacon_response_time));
1693 REG_WRITE(ah, AR_NEXT_SWBA,
1694 TU_TO_USEC(next_beacon -
1695 ah->config.
1696 sw_beacon_response_time));
1697 flags |= 1706 flags |=
1698 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN; 1707 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
1699 break; 1708 break;
@@ -1705,18 +1714,13 @@ void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
1705 break; 1714 break;
1706 } 1715 }
1707 1716
1708 REG_WRITE(ah, AR_BEACON_PERIOD, TU_TO_USEC(beacon_period)); 1717 REG_WRITE(ah, AR_BEACON_PERIOD, beacon_period);
1709 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, TU_TO_USEC(beacon_period)); 1718 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, beacon_period);
1710 REG_WRITE(ah, AR_SWBA_PERIOD, TU_TO_USEC(beacon_period)); 1719 REG_WRITE(ah, AR_SWBA_PERIOD, beacon_period);
1711 REG_WRITE(ah, AR_NDP_PERIOD, TU_TO_USEC(beacon_period)); 1720 REG_WRITE(ah, AR_NDP_PERIOD, beacon_period);
1712 1721
1713 REGWRITE_BUFFER_FLUSH(ah); 1722 REGWRITE_BUFFER_FLUSH(ah);
1714 1723
1715 beacon_period &= ~ATH9K_BEACON_ENA;
1716 if (beacon_period & ATH9K_BEACON_RESET_TSF) {
1717 ath9k_hw_reset_tsf(ah);
1718 }
1719
1720 REG_SET_BIT(ah, AR_TIMER_MODE, flags); 1724 REG_SET_BIT(ah, AR_TIMER_MODE, flags);
1721} 1725}
1722EXPORT_SYMBOL(ath9k_hw_beaconinit); 1726EXPORT_SYMBOL(ath9k_hw_beaconinit);
@@ -1851,6 +1855,8 @@ int ath9k_hw_fill_cap_info(struct ath_hw *ah)
1851 !(AR_SREV_9271(ah))) 1855 !(AR_SREV_9271(ah)))
1852 /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */ 1856 /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */
1853 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7; 1857 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7;
1858 else if (AR_SREV_9100(ah))
1859 pCap->rx_chainmask = 0x7;
1854 else 1860 else
1855 /* Use rx_chainmask from EEPROM. */ 1861 /* Use rx_chainmask from EEPROM. */
1856 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK); 1862 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK);
@@ -1869,28 +1875,11 @@ int ath9k_hw_fill_cap_info(struct ath_hw *ah)
1869 1875
1870 common->crypt_caps |= ATH_CRYPT_CAP_CIPHER_AESCCM; 1876 common->crypt_caps |= ATH_CRYPT_CAP_CIPHER_AESCCM;
1871 1877
1872 if (ah->config.ht_enable) 1878 if (ah->hw_version.devid != AR2427_DEVID_PCIE)
1873 pCap->hw_caps |= ATH9K_HW_CAP_HT; 1879 pCap->hw_caps |= ATH9K_HW_CAP_HT;
1874 else 1880 else
1875 pCap->hw_caps &= ~ATH9K_HW_CAP_HT; 1881 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
1876 1882
1877 if (capField & AR_EEPROM_EEPCAP_MAXQCU)
1878 pCap->total_queues =
1879 MS(capField, AR_EEPROM_EEPCAP_MAXQCU);
1880 else
1881 pCap->total_queues = ATH9K_NUM_TX_QUEUES;
1882
1883 if (capField & AR_EEPROM_EEPCAP_KC_ENTRIES)
1884 pCap->keycache_size =
1885 1 << MS(capField, AR_EEPROM_EEPCAP_KC_ENTRIES);
1886 else
1887 pCap->keycache_size = AR_KEYTABLE_SIZE;
1888
1889 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
1890 pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD >> 1;
1891 else
1892 pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD;
1893
1894 if (AR_SREV_9271(ah)) 1883 if (AR_SREV_9271(ah))
1895 pCap->num_gpio_pins = AR9271_NUM_GPIO; 1884 pCap->num_gpio_pins = AR9271_NUM_GPIO;
1896 else if (AR_DEVID_7010(ah)) 1885 else if (AR_DEVID_7010(ah))
@@ -1909,8 +1898,6 @@ int ath9k_hw_fill_cap_info(struct ath_hw *ah)
1909 pCap->rts_aggr_limit = (8 * 1024); 1898 pCap->rts_aggr_limit = (8 * 1024);
1910 } 1899 }
1911 1900
1912 pCap->hw_caps |= ATH9K_HW_CAP_ENHANCEDPM;
1913
1914#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE) 1901#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
1915 ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT); 1902 ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT);
1916 if (ah->rfsilent & EEP_RFSILENT_ENABLED) { 1903 if (ah->rfsilent & EEP_RFSILENT_ENABLED) {
@@ -1932,23 +1919,6 @@ int ath9k_hw_fill_cap_info(struct ath_hw *ah)
1932 else 1919 else
1933 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS; 1920 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
1934 1921
1935 if (regulatory->current_rd_ext & (1 << REG_EXT_JAPAN_MIDBAND)) {
1936 pCap->reg_cap =
1937 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
1938 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN |
1939 AR_EEPROM_EEREGCAP_EN_KK_U2 |
1940 AR_EEPROM_EEREGCAP_EN_KK_MIDBAND;
1941 } else {
1942 pCap->reg_cap =
1943 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
1944 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN;
1945 }
1946
1947 /* Advertise midband for AR5416 with FCC midband set in eeprom */
1948 if (regulatory->current_rd_ext & (1 << REG_EXT_FCC_MIDBAND) &&
1949 AR_SREV_5416(ah))
1950 pCap->reg_cap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND;
1951
1952 if (AR_SREV_9280_20_OR_LATER(ah) && common->btcoex_enabled) { 1922 if (AR_SREV_9280_20_OR_LATER(ah) && common->btcoex_enabled) {
1953 btcoex_hw->btactive_gpio = ATH_BTACTIVE_GPIO; 1923 btcoex_hw->btactive_gpio = ATH_BTACTIVE_GPIO;
1954 btcoex_hw->wlanactive_gpio = ATH_WLANACTIVE_GPIO; 1924 btcoex_hw->wlanactive_gpio = ATH_WLANACTIVE_GPIO;
@@ -2195,11 +2165,9 @@ void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
2195 REG_WRITE(ah, AR_PHY_ERR, phybits); 2165 REG_WRITE(ah, AR_PHY_ERR, phybits);
2196 2166
2197 if (phybits) 2167 if (phybits)
2198 REG_WRITE(ah, AR_RXCFG, 2168 REG_SET_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA);
2199 REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA);
2200 else 2169 else
2201 REG_WRITE(ah, AR_RXCFG, 2170 REG_CLR_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA);
2202 REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_ZLFDMA);
2203 2171
2204 REGWRITE_BUFFER_FLUSH(ah); 2172 REGWRITE_BUFFER_FLUSH(ah);
2205} 2173}
@@ -2375,10 +2343,11 @@ static u32 rightmost_index(struct ath_gen_timer_table *timer_table, u32 *mask)
2375 return timer_table->gen_timer_index[b]; 2343 return timer_table->gen_timer_index[b];
2376} 2344}
2377 2345
2378static u32 ath9k_hw_gettsf32(struct ath_hw *ah) 2346u32 ath9k_hw_gettsf32(struct ath_hw *ah)
2379{ 2347{
2380 return REG_READ(ah, AR_TSF_L32); 2348 return REG_READ(ah, AR_TSF_L32);
2381} 2349}
2350EXPORT_SYMBOL(ath9k_hw_gettsf32);
2382 2351
2383struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah, 2352struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
2384 void (*trigger)(void *), 2353 void (*trigger)(void *),
diff --git a/drivers/net/wireless/ath/ath9k/hw.h b/drivers/net/wireless/ath/ath9k/hw.h
index 6650fd48415..4cc320bdf0a 100644
--- a/drivers/net/wireless/ath/ath9k/hw.h
+++ b/drivers/net/wireless/ath/ath9k/hw.h
@@ -65,53 +65,49 @@
65 65
66/* Register read/write primitives */ 66/* Register read/write primitives */
67#define REG_WRITE(_ah, _reg, _val) \ 67#define REG_WRITE(_ah, _reg, _val) \
68 ath9k_hw_common(_ah)->ops->write((_ah), (_val), (_reg)) 68 (_ah)->reg_ops.write((_ah), (_val), (_reg))
69 69
70#define REG_READ(_ah, _reg) \ 70#define REG_READ(_ah, _reg) \
71 ath9k_hw_common(_ah)->ops->read((_ah), (_reg)) 71 (_ah)->reg_ops.read((_ah), (_reg))
72 72
73#define REG_READ_MULTI(_ah, _addr, _val, _cnt) \ 73#define REG_READ_MULTI(_ah, _addr, _val, _cnt) \
74 ath9k_hw_common(_ah)->ops->multi_read((_ah), (_addr), (_val), (_cnt)) 74 (_ah)->reg_ops.multi_read((_ah), (_addr), (_val), (_cnt))
75
76#define REG_RMW(_ah, _reg, _set, _clr) \
77 (_ah)->reg_ops.rmw((_ah), (_reg), (_set), (_clr))
75 78
76#define ENABLE_REGWRITE_BUFFER(_ah) \ 79#define ENABLE_REGWRITE_BUFFER(_ah) \
77 do { \ 80 do { \
78 if (ath9k_hw_common(_ah)->ops->enable_write_buffer) \ 81 if ((_ah)->reg_ops.enable_write_buffer) \
79 ath9k_hw_common(_ah)->ops->enable_write_buffer((_ah)); \ 82 (_ah)->reg_ops.enable_write_buffer((_ah)); \
80 } while (0) 83 } while (0)
81 84
82#define REGWRITE_BUFFER_FLUSH(_ah) \ 85#define REGWRITE_BUFFER_FLUSH(_ah) \
83 do { \ 86 do { \
84 if (ath9k_hw_common(_ah)->ops->write_flush) \ 87 if ((_ah)->reg_ops.write_flush) \
85 ath9k_hw_common(_ah)->ops->write_flush((_ah)); \ 88 (_ah)->reg_ops.write_flush((_ah)); \
86 } while (0) 89 } while (0)
87 90
88#define SM(_v, _f) (((_v) << _f##_S) & _f) 91#define SM(_v, _f) (((_v) << _f##_S) & _f)
89#define MS(_v, _f) (((_v) & _f) >> _f##_S) 92#define MS(_v, _f) (((_v) & _f) >> _f##_S)
90#define REG_RMW(_a, _r, _set, _clr) \
91 REG_WRITE(_a, _r, (REG_READ(_a, _r) & ~(_clr)) | (_set))
92#define REG_RMW_FIELD(_a, _r, _f, _v) \ 93#define REG_RMW_FIELD(_a, _r, _f, _v) \
93 REG_WRITE(_a, _r, \ 94 REG_RMW(_a, _r, (((_v) << _f##_S) & _f), (_f))
94 (REG_READ(_a, _r) & ~_f) | (((_v) << _f##_S) & _f))
95#define REG_READ_FIELD(_a, _r, _f) \ 95#define REG_READ_FIELD(_a, _r, _f) \
96 (((REG_READ(_a, _r) & _f) >> _f##_S)) 96 (((REG_READ(_a, _r) & _f) >> _f##_S))
97#define REG_SET_BIT(_a, _r, _f) \ 97#define REG_SET_BIT(_a, _r, _f) \
98 REG_WRITE(_a, _r, REG_READ(_a, _r) | (_f)) 98 REG_RMW(_a, _r, (_f), 0)
99#define REG_CLR_BIT(_a, _r, _f) \ 99#define REG_CLR_BIT(_a, _r, _f) \
100 REG_WRITE(_a, _r, REG_READ(_a, _r) & ~(_f)) 100 REG_RMW(_a, _r, 0, (_f))
101 101
102#define DO_DELAY(x) do { \ 102#define DO_DELAY(x) do { \
103 if ((++(x) % 64) == 0) \ 103 if (((++(x) % 64) == 0) && \
104 udelay(1); \ 104 (ath9k_hw_common(ah)->bus_ops->ath_bus_type \
105 != ATH_USB)) \
106 udelay(1); \
105 } while (0) 107 } while (0)
106 108
107#define REG_WRITE_ARRAY(iniarray, column, regWr) do { \ 109#define REG_WRITE_ARRAY(iniarray, column, regWr) \
108 int r; \ 110 ath9k_hw_write_array(ah, iniarray, column, &(regWr))
109 for (r = 0; r < ((iniarray)->ia_rows); r++) { \
110 REG_WRITE(ah, INI_RA((iniarray), (r), 0), \
111 INI_RA((iniarray), r, (column))); \
112 DO_DELAY(regWr); \
113 } \
114 } while (0)
115 111
116#define AR_GPIO_OUTPUT_MUX_AS_OUTPUT 0 112#define AR_GPIO_OUTPUT_MUX_AS_OUTPUT 0
117#define AR_GPIO_OUTPUT_MUX_AS_PCIE_ATTENTION_LED 1 113#define AR_GPIO_OUTPUT_MUX_AS_PCIE_ATTENTION_LED 1
@@ -178,7 +174,6 @@ enum ath9k_hw_caps {
178 ATH9K_HW_CAP_HT = BIT(0), 174 ATH9K_HW_CAP_HT = BIT(0),
179 ATH9K_HW_CAP_RFSILENT = BIT(1), 175 ATH9K_HW_CAP_RFSILENT = BIT(1),
180 ATH9K_HW_CAP_CST = BIT(2), 176 ATH9K_HW_CAP_CST = BIT(2),
181 ATH9K_HW_CAP_ENHANCEDPM = BIT(3),
182 ATH9K_HW_CAP_AUTOSLEEP = BIT(4), 177 ATH9K_HW_CAP_AUTOSLEEP = BIT(4),
183 ATH9K_HW_CAP_4KB_SPLITTRANS = BIT(5), 178 ATH9K_HW_CAP_4KB_SPLITTRANS = BIT(5),
184 ATH9K_HW_CAP_EDMA = BIT(6), 179 ATH9K_HW_CAP_EDMA = BIT(6),
@@ -195,8 +190,6 @@ enum ath9k_hw_caps {
195 190
196struct ath9k_hw_capabilities { 191struct ath9k_hw_capabilities {
197 u32 hw_caps; /* ATH9K_HW_CAP_* from ath9k_hw_caps */ 192 u32 hw_caps; /* ATH9K_HW_CAP_* from ath9k_hw_caps */
198 u16 total_queues;
199 u16 keycache_size;
200 u16 low_5ghz_chan, high_5ghz_chan; 193 u16 low_5ghz_chan, high_5ghz_chan;
201 u16 low_2ghz_chan, high_2ghz_chan; 194 u16 low_2ghz_chan, high_2ghz_chan;
202 u16 rts_aggr_limit; 195 u16 rts_aggr_limit;
@@ -204,8 +197,6 @@ struct ath9k_hw_capabilities {
204 u8 rx_chainmask; 197 u8 rx_chainmask;
205 u8 max_txchains; 198 u8 max_txchains;
206 u8 max_rxchains; 199 u8 max_rxchains;
207 u16 tx_triglevel_max;
208 u16 reg_cap;
209 u8 num_gpio_pins; 200 u8 num_gpio_pins;
210 u8 rx_hp_qdepth; 201 u8 rx_hp_qdepth;
211 u8 rx_lp_qdepth; 202 u8 rx_lp_qdepth;
@@ -227,7 +218,6 @@ struct ath9k_ops_config {
227 u8 pcie_clock_req; 218 u8 pcie_clock_req;
228 u32 pcie_waen; 219 u32 pcie_waen;
229 u8 analog_shiftreg; 220 u8 analog_shiftreg;
230 u8 ht_enable;
231 u8 paprd_disable; 221 u8 paprd_disable;
232 u32 ofdm_trig_low; 222 u32 ofdm_trig_low;
233 u32 ofdm_trig_high; 223 u32 ofdm_trig_high;
@@ -412,8 +402,6 @@ struct ath9k_beacon_state {
412 u32 bs_nextdtim; 402 u32 bs_nextdtim;
413 u32 bs_intval; 403 u32 bs_intval;
414#define ATH9K_BEACON_PERIOD 0x0000ffff 404#define ATH9K_BEACON_PERIOD 0x0000ffff
415#define ATH9K_BEACON_ENA 0x00800000
416#define ATH9K_BEACON_RESET_TSF 0x01000000
417#define ATH9K_TSFOOR_THRESHOLD 0x00004240 /* 16k us */ 405#define ATH9K_TSFOOR_THRESHOLD 0x00004240 /* 16k us */
418 u32 bs_dtimperiod; 406 u32 bs_dtimperiod;
419 u16 bs_cfpperiod; 407 u16 bs_cfpperiod;
@@ -655,6 +643,8 @@ struct ath_nf_limits {
655#define AH_UNPLUGGED 0x2 /* The card has been physically removed. */ 643#define AH_UNPLUGGED 0x2 /* The card has been physically removed. */
656 644
657struct ath_hw { 645struct ath_hw {
646 struct ath_ops reg_ops;
647
658 struct ieee80211_hw *hw; 648 struct ieee80211_hw *hw;
659 struct ath_common common; 649 struct ath_common common;
660 struct ath9k_hw_version hw_version; 650 struct ath9k_hw_version hw_version;
@@ -794,7 +784,9 @@ struct ath_hw {
794 u32 originalGain[22]; 784 u32 originalGain[22];
795 int initPDADC; 785 int initPDADC;
796 int PDADCdelta; 786 int PDADCdelta;
797 u8 led_pin; 787 int led_pin;
788 u32 gpio_mask;
789 u32 gpio_val;
798 790
799 struct ar5416IniArray iniModes; 791 struct ar5416IniArray iniModes;
800 struct ar5416IniArray iniCommon; 792 struct ar5416IniArray iniCommon;
@@ -907,6 +899,8 @@ void ath9k_hw_antdiv_comb_conf_set(struct ath_hw *ah,
907 899
908/* General Operation */ 900/* General Operation */
909bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout); 901bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout);
902void ath9k_hw_write_array(struct ath_hw *ah, struct ar5416IniArray *array,
903 int column, unsigned int *writecnt);
910u32 ath9k_hw_reverse_bits(u32 val, u32 n); 904u32 ath9k_hw_reverse_bits(u32 val, u32 n);
911bool ath9k_get_channel_edges(struct ath_hw *ah, u16 flags, u16 *low, u16 *high); 905bool ath9k_get_channel_edges(struct ath_hw *ah, u16 flags, u16 *low, u16 *high);
912u16 ath9k_hw_computetxtime(struct ath_hw *ah, 906u16 ath9k_hw_computetxtime(struct ath_hw *ah,
@@ -924,6 +918,7 @@ void ath9k_hw_setopmode(struct ath_hw *ah);
924void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1); 918void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1);
925void ath9k_hw_setbssidmask(struct ath_hw *ah); 919void ath9k_hw_setbssidmask(struct ath_hw *ah);
926void ath9k_hw_write_associd(struct ath_hw *ah); 920void ath9k_hw_write_associd(struct ath_hw *ah);
921u32 ath9k_hw_gettsf32(struct ath_hw *ah);
927u64 ath9k_hw_gettsf64(struct ath_hw *ah); 922u64 ath9k_hw_gettsf64(struct ath_hw *ah);
928void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64); 923void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64);
929void ath9k_hw_reset_tsf(struct ath_hw *ah); 924void ath9k_hw_reset_tsf(struct ath_hw *ah);
diff --git a/drivers/net/wireless/ath/ath9k/init.c b/drivers/net/wireless/ath/ath9k/init.c
index 79aec983279..1ac8318d82a 100644
--- a/drivers/net/wireless/ath/ath9k/init.c
+++ b/drivers/net/wireless/ath/ath9k/init.c
@@ -15,6 +15,7 @@
15 */ 15 */
16 16
17#include <linux/slab.h> 17#include <linux/slab.h>
18#include <linux/ath9k_platform.h>
18 19
19#include "ath9k.h" 20#include "ath9k.h"
20 21
@@ -195,10 +196,27 @@ static unsigned int ath9k_ioread32(void *hw_priv, u32 reg_offset)
195 return val; 196 return val;
196} 197}
197 198
198static const struct ath_ops ath9k_common_ops = { 199static unsigned int ath9k_reg_rmw(void *hw_priv, u32 reg_offset, u32 set, u32 clr)
199 .read = ath9k_ioread32, 200{
200 .write = ath9k_iowrite32, 201 struct ath_hw *ah = (struct ath_hw *) hw_priv;
201}; 202 struct ath_common *common = ath9k_hw_common(ah);
203 struct ath_softc *sc = (struct ath_softc *) common->priv;
204 unsigned long uninitialized_var(flags);
205 u32 val;
206
207 if (ah->config.serialize_regmode == SER_REG_MODE_ON)
208 spin_lock_irqsave(&sc->sc_serial_rw, flags);
209
210 val = ioread32(sc->mem + reg_offset);
211 val &= ~clr;
212 val |= set;
213 iowrite32(val, sc->mem + reg_offset);
214
215 if (ah->config.serialize_regmode == SER_REG_MODE_ON)
216 spin_unlock_irqrestore(&sc->sc_serial_rw, flags);
217
218 return val;
219}
202 220
203/**************************/ 221/**************************/
204/* Initialization */ 222/* Initialization */
@@ -389,13 +407,7 @@ void ath9k_init_crypto(struct ath_softc *sc)
389 int i = 0; 407 int i = 0;
390 408
391 /* Get the hardware key cache size. */ 409 /* Get the hardware key cache size. */
392 common->keymax = sc->sc_ah->caps.keycache_size; 410 common->keymax = AR_KEYTABLE_SIZE;
393 if (common->keymax > ATH_KEYMAX) {
394 ath_dbg(common, ATH_DBG_ANY,
395 "Warning, using only %u entries in %u key cache\n",
396 ATH_KEYMAX, common->keymax);
397 common->keymax = ATH_KEYMAX;
398 }
399 411
400 /* 412 /*
401 * Reset the key cache since some parts do not 413 * Reset the key cache since some parts do not
@@ -537,6 +549,7 @@ static void ath9k_init_misc(struct ath_softc *sc)
537static int ath9k_init_softc(u16 devid, struct ath_softc *sc, u16 subsysid, 549static int ath9k_init_softc(u16 devid, struct ath_softc *sc, u16 subsysid,
538 const struct ath_bus_ops *bus_ops) 550 const struct ath_bus_ops *bus_ops)
539{ 551{
552 struct ath9k_platform_data *pdata = sc->dev->platform_data;
540 struct ath_hw *ah = NULL; 553 struct ath_hw *ah = NULL;
541 struct ath_common *common; 554 struct ath_common *common;
542 int ret = 0, i; 555 int ret = 0, i;
@@ -549,13 +562,22 @@ static int ath9k_init_softc(u16 devid, struct ath_softc *sc, u16 subsysid,
549 ah->hw = sc->hw; 562 ah->hw = sc->hw;
550 ah->hw_version.devid = devid; 563 ah->hw_version.devid = devid;
551 ah->hw_version.subsysid = subsysid; 564 ah->hw_version.subsysid = subsysid;
565 ah->reg_ops.read = ath9k_ioread32;
566 ah->reg_ops.write = ath9k_iowrite32;
567 ah->reg_ops.rmw = ath9k_reg_rmw;
552 sc->sc_ah = ah; 568 sc->sc_ah = ah;
553 569
554 if (!sc->dev->platform_data) 570 if (!pdata) {
555 ah->ah_flags |= AH_USE_EEPROM; 571 ah->ah_flags |= AH_USE_EEPROM;
572 sc->sc_ah->led_pin = -1;
573 } else {
574 sc->sc_ah->gpio_mask = pdata->gpio_mask;
575 sc->sc_ah->gpio_val = pdata->gpio_val;
576 sc->sc_ah->led_pin = pdata->led_pin;
577 }
556 578
557 common = ath9k_hw_common(ah); 579 common = ath9k_hw_common(ah);
558 common->ops = &ath9k_common_ops; 580 common->ops = &ah->reg_ops;
559 common->bus_ops = bus_ops; 581 common->bus_ops = bus_ops;
560 common->ah = ah; 582 common->ah = ah;
561 common->hw = sc->hw; 583 common->hw = sc->hw;
@@ -587,6 +609,9 @@ static int ath9k_init_softc(u16 devid, struct ath_softc *sc, u16 subsysid,
587 if (ret) 609 if (ret)
588 goto err_hw; 610 goto err_hw;
589 611
612 if (pdata && pdata->macaddr)
613 memcpy(common->macaddr, pdata->macaddr, ETH_ALEN);
614
590 ret = ath9k_init_queues(sc); 615 ret = ath9k_init_queues(sc);
591 if (ret) 616 if (ret)
592 goto err_queues; 617 goto err_queues;
@@ -679,6 +704,8 @@ void ath9k_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw)
679 if (AR_SREV_5416(sc->sc_ah)) 704 if (AR_SREV_5416(sc->sc_ah))
680 hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT; 705 hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
681 706
707 hw->wiphy->flags |= WIPHY_FLAG_IBSS_RSN;
708
682 hw->queues = 4; 709 hw->queues = 4;
683 hw->max_rates = 4; 710 hw->max_rates = 4;
684 hw->channel_change_time = 5000; 711 hw->channel_change_time = 5000;
diff --git a/drivers/net/wireless/ath/ath9k/mac.c b/drivers/net/wireless/ath/ath9k/mac.c
index cb5d81426d5..05efcfbeead 100644
--- a/drivers/net/wireless/ath/ath9k/mac.c
+++ b/drivers/net/wireless/ath/ath9k/mac.c
@@ -209,15 +209,8 @@ bool ath9k_hw_set_txq_props(struct ath_hw *ah, int q,
209{ 209{
210 u32 cw; 210 u32 cw;
211 struct ath_common *common = ath9k_hw_common(ah); 211 struct ath_common *common = ath9k_hw_common(ah);
212 struct ath9k_hw_capabilities *pCap = &ah->caps;
213 struct ath9k_tx_queue_info *qi; 212 struct ath9k_tx_queue_info *qi;
214 213
215 if (q >= pCap->total_queues) {
216 ath_dbg(common, ATH_DBG_QUEUE,
217 "Set TXQ properties, invalid queue: %u\n", q);
218 return false;
219 }
220
221 qi = &ah->txq[q]; 214 qi = &ah->txq[q];
222 if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) { 215 if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) {
223 ath_dbg(common, ATH_DBG_QUEUE, 216 ath_dbg(common, ATH_DBG_QUEUE,
@@ -280,15 +273,8 @@ bool ath9k_hw_get_txq_props(struct ath_hw *ah, int q,
280 struct ath9k_tx_queue_info *qinfo) 273 struct ath9k_tx_queue_info *qinfo)
281{ 274{
282 struct ath_common *common = ath9k_hw_common(ah); 275 struct ath_common *common = ath9k_hw_common(ah);
283 struct ath9k_hw_capabilities *pCap = &ah->caps;
284 struct ath9k_tx_queue_info *qi; 276 struct ath9k_tx_queue_info *qi;
285 277
286 if (q >= pCap->total_queues) {
287 ath_dbg(common, ATH_DBG_QUEUE,
288 "Get TXQ properties, invalid queue: %u\n", q);
289 return false;
290 }
291
292 qi = &ah->txq[q]; 278 qi = &ah->txq[q];
293 if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) { 279 if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) {
294 ath_dbg(common, ATH_DBG_QUEUE, 280 ath_dbg(common, ATH_DBG_QUEUE,
@@ -320,28 +306,27 @@ int ath9k_hw_setuptxqueue(struct ath_hw *ah, enum ath9k_tx_queue type,
320{ 306{
321 struct ath_common *common = ath9k_hw_common(ah); 307 struct ath_common *common = ath9k_hw_common(ah);
322 struct ath9k_tx_queue_info *qi; 308 struct ath9k_tx_queue_info *qi;
323 struct ath9k_hw_capabilities *pCap = &ah->caps;
324 int q; 309 int q;
325 310
326 switch (type) { 311 switch (type) {
327 case ATH9K_TX_QUEUE_BEACON: 312 case ATH9K_TX_QUEUE_BEACON:
328 q = pCap->total_queues - 1; 313 q = ATH9K_NUM_TX_QUEUES - 1;
329 break; 314 break;
330 case ATH9K_TX_QUEUE_CAB: 315 case ATH9K_TX_QUEUE_CAB:
331 q = pCap->total_queues - 2; 316 q = ATH9K_NUM_TX_QUEUES - 2;
332 break; 317 break;
333 case ATH9K_TX_QUEUE_PSPOLL: 318 case ATH9K_TX_QUEUE_PSPOLL:
334 q = 1; 319 q = 1;
335 break; 320 break;
336 case ATH9K_TX_QUEUE_UAPSD: 321 case ATH9K_TX_QUEUE_UAPSD:
337 q = pCap->total_queues - 3; 322 q = ATH9K_NUM_TX_QUEUES - 3;
338 break; 323 break;
339 case ATH9K_TX_QUEUE_DATA: 324 case ATH9K_TX_QUEUE_DATA:
340 for (q = 0; q < pCap->total_queues; q++) 325 for (q = 0; q < ATH9K_NUM_TX_QUEUES; q++)
341 if (ah->txq[q].tqi_type == 326 if (ah->txq[q].tqi_type ==
342 ATH9K_TX_QUEUE_INACTIVE) 327 ATH9K_TX_QUEUE_INACTIVE)
343 break; 328 break;
344 if (q == pCap->total_queues) { 329 if (q == ATH9K_NUM_TX_QUEUES) {
345 ath_err(common, "No available TX queue\n"); 330 ath_err(common, "No available TX queue\n");
346 return -1; 331 return -1;
347 } 332 }
@@ -382,15 +367,9 @@ EXPORT_SYMBOL(ath9k_hw_setuptxqueue);
382 367
383bool ath9k_hw_releasetxqueue(struct ath_hw *ah, u32 q) 368bool ath9k_hw_releasetxqueue(struct ath_hw *ah, u32 q)
384{ 369{
385 struct ath9k_hw_capabilities *pCap = &ah->caps;
386 struct ath_common *common = ath9k_hw_common(ah); 370 struct ath_common *common = ath9k_hw_common(ah);
387 struct ath9k_tx_queue_info *qi; 371 struct ath9k_tx_queue_info *qi;
388 372
389 if (q >= pCap->total_queues) {
390 ath_dbg(common, ATH_DBG_QUEUE,
391 "Release TXQ, invalid queue: %u\n", q);
392 return false;
393 }
394 qi = &ah->txq[q]; 373 qi = &ah->txq[q];
395 if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) { 374 if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) {
396 ath_dbg(common, ATH_DBG_QUEUE, 375 ath_dbg(common, ATH_DBG_QUEUE,
@@ -414,18 +393,11 @@ EXPORT_SYMBOL(ath9k_hw_releasetxqueue);
414 393
415bool ath9k_hw_resettxqueue(struct ath_hw *ah, u32 q) 394bool ath9k_hw_resettxqueue(struct ath_hw *ah, u32 q)
416{ 395{
417 struct ath9k_hw_capabilities *pCap = &ah->caps;
418 struct ath_common *common = ath9k_hw_common(ah); 396 struct ath_common *common = ath9k_hw_common(ah);
419 struct ath9k_channel *chan = ah->curchan; 397 struct ath9k_channel *chan = ah->curchan;
420 struct ath9k_tx_queue_info *qi; 398 struct ath9k_tx_queue_info *qi;
421 u32 cwMin, chanCwMin, value; 399 u32 cwMin, chanCwMin, value;
422 400
423 if (q >= pCap->total_queues) {
424 ath_dbg(common, ATH_DBG_QUEUE,
425 "Reset TXQ, invalid queue: %u\n", q);
426 return false;
427 }
428
429 qi = &ah->txq[q]; 401 qi = &ah->txq[q];
430 if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) { 402 if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) {
431 ath_dbg(common, ATH_DBG_QUEUE, 403 ath_dbg(common, ATH_DBG_QUEUE,
@@ -465,10 +437,9 @@ bool ath9k_hw_resettxqueue(struct ath_hw *ah, u32 q)
465 REG_WRITE(ah, AR_QCBRCFG(q), 437 REG_WRITE(ah, AR_QCBRCFG(q),
466 SM(qi->tqi_cbrPeriod, AR_Q_CBRCFG_INTERVAL) | 438 SM(qi->tqi_cbrPeriod, AR_Q_CBRCFG_INTERVAL) |
467 SM(qi->tqi_cbrOverflowLimit, AR_Q_CBRCFG_OVF_THRESH)); 439 SM(qi->tqi_cbrOverflowLimit, AR_Q_CBRCFG_OVF_THRESH));
468 REG_WRITE(ah, AR_QMISC(q), 440 REG_SET_BIT(ah, AR_QMISC(q), AR_Q_MISC_FSP_CBR |
469 REG_READ(ah, AR_QMISC(q)) | AR_Q_MISC_FSP_CBR | 441 (qi->tqi_cbrOverflowLimit ?
470 (qi->tqi_cbrOverflowLimit ? 442 AR_Q_MISC_CBR_EXP_CNTR_LIMIT_EN : 0));
471 AR_Q_MISC_CBR_EXP_CNTR_LIMIT_EN : 0));
472 } 443 }
473 if (qi->tqi_readyTime && (qi->tqi_type != ATH9K_TX_QUEUE_CAB)) { 444 if (qi->tqi_readyTime && (qi->tqi_type != ATH9K_TX_QUEUE_CAB)) {
474 REG_WRITE(ah, AR_QRDYTIMECFG(q), 445 REG_WRITE(ah, AR_QRDYTIMECFG(q),
@@ -481,40 +452,31 @@ bool ath9k_hw_resettxqueue(struct ath_hw *ah, u32 q)
481 (qi->tqi_burstTime ? AR_D_CHNTIME_EN : 0)); 452 (qi->tqi_burstTime ? AR_D_CHNTIME_EN : 0));
482 453
483 if (qi->tqi_burstTime 454 if (qi->tqi_burstTime
484 && (qi->tqi_qflags & TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE)) { 455 && (qi->tqi_qflags & TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE))
485 REG_WRITE(ah, AR_QMISC(q), 456 REG_SET_BIT(ah, AR_QMISC(q), AR_Q_MISC_RDYTIME_EXP_POLICY);
486 REG_READ(ah, AR_QMISC(q)) |
487 AR_Q_MISC_RDYTIME_EXP_POLICY);
488
489 }
490 457
491 if (qi->tqi_qflags & TXQ_FLAG_BACKOFF_DISABLE) { 458 if (qi->tqi_qflags & TXQ_FLAG_BACKOFF_DISABLE)
492 REG_WRITE(ah, AR_DMISC(q), 459 REG_SET_BIT(ah, AR_DMISC(q), AR_D_MISC_POST_FR_BKOFF_DIS);
493 REG_READ(ah, AR_DMISC(q)) |
494 AR_D_MISC_POST_FR_BKOFF_DIS);
495 }
496 460
497 REGWRITE_BUFFER_FLUSH(ah); 461 REGWRITE_BUFFER_FLUSH(ah);
498 462
499 if (qi->tqi_qflags & TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE) { 463 if (qi->tqi_qflags & TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE)
500 REG_WRITE(ah, AR_DMISC(q), 464 REG_SET_BIT(ah, AR_DMISC(q), AR_D_MISC_FRAG_BKOFF_EN);
501 REG_READ(ah, AR_DMISC(q)) | 465
502 AR_D_MISC_FRAG_BKOFF_EN);
503 }
504 switch (qi->tqi_type) { 466 switch (qi->tqi_type) {
505 case ATH9K_TX_QUEUE_BEACON: 467 case ATH9K_TX_QUEUE_BEACON:
506 ENABLE_REGWRITE_BUFFER(ah); 468 ENABLE_REGWRITE_BUFFER(ah);
507 469
508 REG_WRITE(ah, AR_QMISC(q), REG_READ(ah, AR_QMISC(q)) 470 REG_SET_BIT(ah, AR_QMISC(q),
509 | AR_Q_MISC_FSP_DBA_GATED 471 AR_Q_MISC_FSP_DBA_GATED
510 | AR_Q_MISC_BEACON_USE 472 | AR_Q_MISC_BEACON_USE
511 | AR_Q_MISC_CBR_INCR_DIS1); 473 | AR_Q_MISC_CBR_INCR_DIS1);
512 474
513 REG_WRITE(ah, AR_DMISC(q), REG_READ(ah, AR_DMISC(q)) 475 REG_SET_BIT(ah, AR_DMISC(q),
514 | (AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL << 476 (AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL <<
515 AR_D_MISC_ARB_LOCKOUT_CNTRL_S) 477 AR_D_MISC_ARB_LOCKOUT_CNTRL_S)
516 | AR_D_MISC_BEACON_USE 478 | AR_D_MISC_BEACON_USE
517 | AR_D_MISC_POST_FR_BKOFF_DIS); 479 | AR_D_MISC_POST_FR_BKOFF_DIS);
518 480
519 REGWRITE_BUFFER_FLUSH(ah); 481 REGWRITE_BUFFER_FLUSH(ah);
520 482
@@ -533,41 +495,38 @@ bool ath9k_hw_resettxqueue(struct ath_hw *ah, u32 q)
533 case ATH9K_TX_QUEUE_CAB: 495 case ATH9K_TX_QUEUE_CAB:
534 ENABLE_REGWRITE_BUFFER(ah); 496 ENABLE_REGWRITE_BUFFER(ah);
535 497
536 REG_WRITE(ah, AR_QMISC(q), REG_READ(ah, AR_QMISC(q)) 498 REG_SET_BIT(ah, AR_QMISC(q),
537 | AR_Q_MISC_FSP_DBA_GATED 499 AR_Q_MISC_FSP_DBA_GATED
538 | AR_Q_MISC_CBR_INCR_DIS1 500 | AR_Q_MISC_CBR_INCR_DIS1
539 | AR_Q_MISC_CBR_INCR_DIS0); 501 | AR_Q_MISC_CBR_INCR_DIS0);
540 value = (qi->tqi_readyTime - 502 value = (qi->tqi_readyTime -
541 (ah->config.sw_beacon_response_time - 503 (ah->config.sw_beacon_response_time -
542 ah->config.dma_beacon_response_time) - 504 ah->config.dma_beacon_response_time) -
543 ah->config.additional_swba_backoff) * 1024; 505 ah->config.additional_swba_backoff) * 1024;
544 REG_WRITE(ah, AR_QRDYTIMECFG(q), 506 REG_WRITE(ah, AR_QRDYTIMECFG(q),
545 value | AR_Q_RDYTIMECFG_EN); 507 value | AR_Q_RDYTIMECFG_EN);
546 REG_WRITE(ah, AR_DMISC(q), REG_READ(ah, AR_DMISC(q)) 508 REG_SET_BIT(ah, AR_DMISC(q),
547 | (AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL << 509 (AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL <<
548 AR_D_MISC_ARB_LOCKOUT_CNTRL_S)); 510 AR_D_MISC_ARB_LOCKOUT_CNTRL_S));
549 511
550 REGWRITE_BUFFER_FLUSH(ah); 512 REGWRITE_BUFFER_FLUSH(ah);
551 513
552 break; 514 break;
553 case ATH9K_TX_QUEUE_PSPOLL: 515 case ATH9K_TX_QUEUE_PSPOLL:
554 REG_WRITE(ah, AR_QMISC(q), 516 REG_SET_BIT(ah, AR_QMISC(q), AR_Q_MISC_CBR_INCR_DIS1);
555 REG_READ(ah, AR_QMISC(q)) | AR_Q_MISC_CBR_INCR_DIS1);
556 break; 517 break;
557 case ATH9K_TX_QUEUE_UAPSD: 518 case ATH9K_TX_QUEUE_UAPSD:
558 REG_WRITE(ah, AR_DMISC(q), REG_READ(ah, AR_DMISC(q)) | 519 REG_SET_BIT(ah, AR_DMISC(q), AR_D_MISC_POST_FR_BKOFF_DIS);
559 AR_D_MISC_POST_FR_BKOFF_DIS);
560 break; 520 break;
561 default: 521 default:
562 break; 522 break;
563 } 523 }
564 524
565 if (qi->tqi_intFlags & ATH9K_TXQ_USE_LOCKOUT_BKOFF_DIS) { 525 if (qi->tqi_intFlags & ATH9K_TXQ_USE_LOCKOUT_BKOFF_DIS) {
566 REG_WRITE(ah, AR_DMISC(q), 526 REG_SET_BIT(ah, AR_DMISC(q),
567 REG_READ(ah, AR_DMISC(q)) | 527 SM(AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL,
568 SM(AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL, 528 AR_D_MISC_ARB_LOCKOUT_CNTRL) |
569 AR_D_MISC_ARB_LOCKOUT_CNTRL) | 529 AR_D_MISC_POST_FR_BKOFF_DIS);
570 AR_D_MISC_POST_FR_BKOFF_DIS);
571 } 530 }
572 531
573 if (AR_SREV_9300_20_OR_LATER(ah)) 532 if (AR_SREV_9300_20_OR_LATER(ah))
@@ -866,7 +825,7 @@ void ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints)
866 struct ath_common *common = ath9k_hw_common(ah); 825 struct ath_common *common = ath9k_hw_common(ah);
867 826
868 if (!(ints & ATH9K_INT_GLOBAL)) 827 if (!(ints & ATH9K_INT_GLOBAL))
869 ath9k_hw_enable_interrupts(ah); 828 ath9k_hw_disable_interrupts(ah);
870 829
871 ath_dbg(common, ATH_DBG_INTERRUPT, "0x%x => 0x%x\n", omask, ints); 830 ath_dbg(common, ATH_DBG_INTERRUPT, "0x%x => 0x%x\n", omask, ints);
872 831
@@ -944,7 +903,8 @@ void ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints)
944 REG_CLR_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER); 903 REG_CLR_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
945 } 904 }
946 905
947 ath9k_hw_enable_interrupts(ah); 906 if (ints & ATH9K_INT_GLOBAL)
907 ath9k_hw_enable_interrupts(ah);
948 908
949 return; 909 return;
950} 910}
diff --git a/drivers/net/wireless/ath/ath9k/main.c b/drivers/net/wireless/ath/ath9k/main.c
index 115f162c617..3c5de73dcb4 100644
--- a/drivers/net/wireless/ath/ath9k/main.c
+++ b/drivers/net/wireless/ath/ath9k/main.c
@@ -1845,6 +1845,20 @@ static int ath9k_set_key(struct ieee80211_hw *hw,
1845 if (ath9k_modparam_nohwcrypt) 1845 if (ath9k_modparam_nohwcrypt)
1846 return -ENOSPC; 1846 return -ENOSPC;
1847 1847
1848 if (vif->type == NL80211_IFTYPE_ADHOC &&
1849 (key->cipher == WLAN_CIPHER_SUITE_TKIP ||
1850 key->cipher == WLAN_CIPHER_SUITE_CCMP) &&
1851 !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
1852 /*
1853 * For now, disable hw crypto for the RSN IBSS group keys. This
1854 * could be optimized in the future to use a modified key cache
1855 * design to support per-STA RX GTK, but until that gets
1856 * implemented, use of software crypto for group addressed
1857 * frames is a acceptable to allow RSN IBSS to be used.
1858 */
1859 return -EOPNOTSUPP;
1860 }
1861
1848 mutex_lock(&sc->mutex); 1862 mutex_lock(&sc->mutex);
1849 ath9k_ps_wakeup(sc); 1863 ath9k_ps_wakeup(sc);
1850 ath_dbg(common, ATH_DBG_CONFIG, "Set HW Key\n"); 1864 ath_dbg(common, ATH_DBG_CONFIG, "Set HW Key\n");
@@ -2160,6 +2174,8 @@ static void ath9k_flush(struct ieee80211_hw *hw, bool drop)
2160 if (!ath_drain_all_txq(sc, false)) 2174 if (!ath_drain_all_txq(sc, false))
2161 ath_reset(sc, false); 2175 ath_reset(sc, false);
2162 2176
2177 ieee80211_wake_queues(hw);
2178
2163out: 2179out:
2164 ieee80211_queue_delayed_work(hw, &sc->tx_complete_work, 0); 2180 ieee80211_queue_delayed_work(hw, &sc->tx_complete_work, 0);
2165 mutex_unlock(&sc->mutex); 2181 mutex_unlock(&sc->mutex);
diff --git a/drivers/net/wireless/ath/ath9k/phy.h b/drivers/net/wireless/ath/ath9k/phy.h
index 5e3d7496986..f50e2c29f71 100644
--- a/drivers/net/wireless/ath/ath9k/phy.h
+++ b/drivers/net/wireless/ath/ath9k/phy.h
@@ -38,25 +38,11 @@
38#define AR_PHY_CLC_Q0 0x0000ffd0 38#define AR_PHY_CLC_Q0 0x0000ffd0
39#define AR_PHY_CLC_Q0_S 5 39#define AR_PHY_CLC_Q0_S 5
40 40
41#define REG_WRITE_RF_ARRAY(iniarray, regData, regWr) do { \
42 int r; \
43 for (r = 0; r < ((iniarray)->ia_rows); r++) { \
44 REG_WRITE(ah, INI_RA((iniarray), r, 0), (regData)[r]); \
45 DO_DELAY(regWr); \
46 } \
47 } while (0)
48
49#define ANTSWAP_AB 0x0001 41#define ANTSWAP_AB 0x0001
50#define REDUCE_CHAIN_0 0x00000050 42#define REDUCE_CHAIN_0 0x00000050
51#define REDUCE_CHAIN_1 0x00000051 43#define REDUCE_CHAIN_1 0x00000051
52#define AR_PHY_CHIP_ID 0x9818 44#define AR_PHY_CHIP_ID 0x9818
53 45
54#define RF_BANK_SETUP(_bank, _iniarray, _col) do { \
55 int i; \
56 for (i = 0; i < (_iniarray)->ia_rows; i++) \
57 (_bank)[i] = INI_RA((_iniarray), i, _col);; \
58 } while (0)
59
60#define AR_PHY_TIMING11_SPUR_FREQ_SD 0x3FF00000 46#define AR_PHY_TIMING11_SPUR_FREQ_SD 0x3FF00000
61#define AR_PHY_TIMING11_SPUR_FREQ_SD_S 20 47#define AR_PHY_TIMING11_SPUR_FREQ_SD_S 20
62 48
diff --git a/drivers/net/wireless/ath/ath9k/rc.c b/drivers/net/wireless/ath/ath9k/rc.c
index 960d717ca7c..a3241cd089b 100644
--- a/drivers/net/wireless/ath/ath9k/rc.c
+++ b/drivers/net/wireless/ath/ath9k/rc.c
@@ -1328,7 +1328,7 @@ static void ath_tx_status(void *priv, struct ieee80211_supported_band *sband,
1328 1328
1329 hdr = (struct ieee80211_hdr *)skb->data; 1329 hdr = (struct ieee80211_hdr *)skb->data;
1330 fc = hdr->frame_control; 1330 fc = hdr->frame_control;
1331 for (i = 0; i < IEEE80211_TX_MAX_RATES; i++) { 1331 for (i = 0; i < sc->hw->max_rates; i++) {
1332 struct ieee80211_tx_rate *rate = &tx_info->status.rates[i]; 1332 struct ieee80211_tx_rate *rate = &tx_info->status.rates[i];
1333 if (!rate->count) 1333 if (!rate->count)
1334 break; 1334 break;
diff --git a/drivers/net/wireless/ath/ath9k/reg.h b/drivers/net/wireless/ath/ath9k/reg.h
index 8fa8acfde62..693d543937b 100644
--- a/drivers/net/wireless/ath/ath9k/reg.h
+++ b/drivers/net/wireless/ath/ath9k/reg.h
@@ -1396,6 +1396,7 @@ enum {
1396#define AR_STA_ID1_PCF 0x00100000 1396#define AR_STA_ID1_PCF 0x00100000
1397#define AR_STA_ID1_USE_DEFANT 0x00200000 1397#define AR_STA_ID1_USE_DEFANT 0x00200000
1398#define AR_STA_ID1_DEFANT_UPDATE 0x00400000 1398#define AR_STA_ID1_DEFANT_UPDATE 0x00400000
1399#define AR_STA_ID1_AR9100_BA_FIX 0x00400000
1399#define AR_STA_ID1_RTS_USE_DEF 0x00800000 1400#define AR_STA_ID1_RTS_USE_DEF 0x00800000
1400#define AR_STA_ID1_ACKCTS_6MB 0x01000000 1401#define AR_STA_ID1_ACKCTS_6MB 0x01000000
1401#define AR_STA_ID1_BASE_RATE_11B 0x02000000 1402#define AR_STA_ID1_BASE_RATE_11B 0x02000000
diff --git a/drivers/net/wireless/ath/ath9k/xmit.c b/drivers/net/wireless/ath/ath9k/xmit.c
index ef22096d40c..5943bdc4c8f 100644
--- a/drivers/net/wireless/ath/ath9k/xmit.c
+++ b/drivers/net/wireless/ath/ath9k/xmit.c
@@ -1725,8 +1725,8 @@ static void ath_tx_start_dma(struct ath_softc *sc, struct ath_buf *bf,
1725 u8 tidno; 1725 u8 tidno;
1726 1726
1727 spin_lock_bh(&txctl->txq->axq_lock); 1727 spin_lock_bh(&txctl->txq->axq_lock);
1728 1728 if ((sc->sc_flags & SC_OP_TXAGGR) && txctl->an &&
1729 if (ieee80211_is_data_qos(hdr->frame_control) && txctl->an) { 1729 ieee80211_is_data_qos(hdr->frame_control)) {
1730 tidno = ieee80211_get_qos_ctl(hdr)[0] & 1730 tidno = ieee80211_get_qos_ctl(hdr)[0] &
1731 IEEE80211_QOS_CTL_TID_MASK; 1731 IEEE80211_QOS_CTL_TID_MASK;
1732 tid = ATH_AN_2_TID(txctl->an, tidno); 1732 tid = ATH_AN_2_TID(txctl->an, tidno);
@@ -1980,7 +1980,7 @@ static void ath_tx_rc_status(struct ath_softc *sc, struct ath_buf *bf,
1980 if (ieee80211_is_data(hdr->frame_control) && 1980 if (ieee80211_is_data(hdr->frame_control) &&
1981 (ts->ts_flags & (ATH9K_TX_DATA_UNDERRUN | 1981 (ts->ts_flags & (ATH9K_TX_DATA_UNDERRUN |
1982 ATH9K_TX_DELIM_UNDERRUN)) && 1982 ATH9K_TX_DELIM_UNDERRUN)) &&
1983 ah->tx_trig_level >= sc->sc_ah->caps.tx_triglevel_max) 1983 ah->tx_trig_level >= sc->sc_ah->config.max_txtrig_level)
1984 tx_info->status.rates[tx_rateindex].count = 1984 tx_info->status.rates[tx_rateindex].count =
1985 hw->max_rate_tries; 1985 hw->max_rate_tries;
1986 } 1986 }
@@ -2144,33 +2144,6 @@ static void ath_tx_complete_poll_work(struct work_struct *work)
2144 } else { 2144 } else {
2145 txq->axq_tx_inprogress = true; 2145 txq->axq_tx_inprogress = true;
2146 } 2146 }
2147 } else {
2148 /* If the queue has pending buffers, then it
2149 * should be doing tx work (and have axq_depth).
2150 * Shouldn't get to this state I think..but
2151 * we do.
2152 */
2153 if (!(sc->sc_flags & (SC_OP_OFFCHANNEL)) &&
2154 (txq->pending_frames > 0 ||
2155 !list_empty(&txq->axq_acq) ||
2156 txq->stopped)) {
2157 ath_err(ath9k_hw_common(sc->sc_ah),
2158 "txq: %p axq_qnum: %u,"
2159 " mac80211_qnum: %i"
2160 " axq_link: %p"
2161 " pending frames: %i"
2162 " axq_acq empty: %i"
2163 " stopped: %i"
2164 " axq_depth: 0 Attempting to"
2165 " restart tx logic.\n",
2166 txq, txq->axq_qnum,
2167 txq->mac80211_qnum,
2168 txq->axq_link,
2169 txq->pending_frames,
2170 list_empty(&txq->axq_acq),
2171 txq->stopped);
2172 ath_txq_schedule(sc, txq);
2173 }
2174 } 2147 }
2175 spin_unlock_bh(&txq->axq_lock); 2148 spin_unlock_bh(&txq->axq_lock);
2176 } 2149 }
diff --git a/drivers/net/wireless/ath/carl9170/usb.c b/drivers/net/wireless/ath/carl9170/usb.c
index 537732e5964..f82c400be28 100644
--- a/drivers/net/wireless/ath/carl9170/usb.c
+++ b/drivers/net/wireless/ath/carl9170/usb.c
@@ -118,6 +118,8 @@ static struct usb_device_id carl9170_usb_ids[] = {
118 { USB_DEVICE(0x057c, 0x8402) }, 118 { USB_DEVICE(0x057c, 0x8402) },
119 /* Qwest/Actiontec 802AIN Wireless N USB Network Adapter */ 119 /* Qwest/Actiontec 802AIN Wireless N USB Network Adapter */
120 { USB_DEVICE(0x1668, 0x1200) }, 120 { USB_DEVICE(0x1668, 0x1200) },
121 /* Airlive X.USB a/b/g/n */
122 { USB_DEVICE(0x1b75, 0x9170) },
121 123
122 /* terminate */ 124 /* terminate */
123 {} 125 {}
diff --git a/drivers/net/wireless/ath/key.c b/drivers/net/wireless/ath/key.c
index 37b8e115375..0d4f39cbdca 100644
--- a/drivers/net/wireless/ath/key.c
+++ b/drivers/net/wireless/ath/key.c
@@ -23,6 +23,14 @@
23 23
24#define REG_READ (common->ops->read) 24#define REG_READ (common->ops->read)
25#define REG_WRITE(_ah, _reg, _val) (common->ops->write)(_ah, _val, _reg) 25#define REG_WRITE(_ah, _reg, _val) (common->ops->write)(_ah, _val, _reg)
26#define ENABLE_REGWRITE_BUFFER(_ah) \
27 if (common->ops->enable_write_buffer) \
28 common->ops->enable_write_buffer((_ah));
29
30#define REGWRITE_BUFFER_FLUSH(_ah) \
31 if (common->ops->write_flush) \
32 common->ops->write_flush((_ah));
33
26 34
27#define IEEE80211_WEP_NKID 4 /* number of key ids */ 35#define IEEE80211_WEP_NKID 4 /* number of key ids */
28 36
@@ -42,6 +50,8 @@ bool ath_hw_keyreset(struct ath_common *common, u16 entry)
42 50
43 keyType = REG_READ(ah, AR_KEYTABLE_TYPE(entry)); 51 keyType = REG_READ(ah, AR_KEYTABLE_TYPE(entry));
44 52
53 ENABLE_REGWRITE_BUFFER(ah);
54
45 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), 0); 55 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), 0);
46 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), 0); 56 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), 0);
47 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), 0); 57 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), 0);
@@ -66,6 +76,8 @@ bool ath_hw_keyreset(struct ath_common *common, u16 entry)
66 76
67 } 77 }
68 78
79 REGWRITE_BUFFER_FLUSH(ah);
80
69 return true; 81 return true;
70} 82}
71EXPORT_SYMBOL(ath_hw_keyreset); 83EXPORT_SYMBOL(ath_hw_keyreset);
@@ -104,9 +116,13 @@ static bool ath_hw_keysetmac(struct ath_common *common,
104 } else { 116 } else {
105 macLo = macHi = 0; 117 macLo = macHi = 0;
106 } 118 }
119 ENABLE_REGWRITE_BUFFER(ah);
120
107 REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), macLo); 121 REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), macLo);
108 REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), macHi | unicast_flag); 122 REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), macHi | unicast_flag);
109 123
124 REGWRITE_BUFFER_FLUSH(ah);
125
110 return true; 126 return true;
111} 127}
112 128
@@ -223,6 +239,8 @@ static bool ath_hw_set_keycache_entry(struct ath_common *common, u16 entry,
223 mic3 = get_unaligned_le16(k->kv_txmic + 0) & 0xffff; 239 mic3 = get_unaligned_le16(k->kv_txmic + 0) & 0xffff;
224 mic4 = get_unaligned_le32(k->kv_txmic + 4); 240 mic4 = get_unaligned_le32(k->kv_txmic + 4);
225 241
242 ENABLE_REGWRITE_BUFFER(ah);
243
226 /* Write RX[31:0] and TX[31:16] */ 244 /* Write RX[31:0] and TX[31:16] */
227 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0); 245 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
228 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), mic1); 246 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), mic1);
@@ -236,6 +254,8 @@ static bool ath_hw_set_keycache_entry(struct ath_common *common, u16 entry,
236 REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry), 254 REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
237 AR_KEYTABLE_TYPE_CLR); 255 AR_KEYTABLE_TYPE_CLR);
238 256
257 REGWRITE_BUFFER_FLUSH(ah);
258
239 } else { 259 } else {
240 /* 260 /*
241 * TKIP uses four key cache entries (two for group 261 * TKIP uses four key cache entries (two for group
@@ -258,6 +278,8 @@ static bool ath_hw_set_keycache_entry(struct ath_common *common, u16 entry,
258 mic0 = get_unaligned_le32(k->kv_mic + 0); 278 mic0 = get_unaligned_le32(k->kv_mic + 0);
259 mic2 = get_unaligned_le32(k->kv_mic + 4); 279 mic2 = get_unaligned_le32(k->kv_mic + 4);
260 280
281 ENABLE_REGWRITE_BUFFER(ah);
282
261 /* Write MIC key[31:0] */ 283 /* Write MIC key[31:0] */
262 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0); 284 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
263 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0); 285 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
@@ -270,8 +292,12 @@ static bool ath_hw_set_keycache_entry(struct ath_common *common, u16 entry,
270 REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), 0); 292 REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), 0);
271 REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry), 293 REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
272 AR_KEYTABLE_TYPE_CLR); 294 AR_KEYTABLE_TYPE_CLR);
295
296 REGWRITE_BUFFER_FLUSH(ah);
273 } 297 }
274 298
299 ENABLE_REGWRITE_BUFFER(ah);
300
275 /* MAC address registers are reserved for the MIC entry */ 301 /* MAC address registers are reserved for the MIC entry */
276 REG_WRITE(ah, AR_KEYTABLE_MAC0(micentry), 0); 302 REG_WRITE(ah, AR_KEYTABLE_MAC0(micentry), 0);
277 REG_WRITE(ah, AR_KEYTABLE_MAC1(micentry), 0); 303 REG_WRITE(ah, AR_KEYTABLE_MAC1(micentry), 0);
@@ -283,7 +309,11 @@ static bool ath_hw_set_keycache_entry(struct ath_common *common, u16 entry,
283 */ 309 */
284 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0); 310 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
285 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1); 311 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
312
313 REGWRITE_BUFFER_FLUSH(ah);
286 } else { 314 } else {
315 ENABLE_REGWRITE_BUFFER(ah);
316
287 /* Write key[47:0] */ 317 /* Write key[47:0] */
288 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0); 318 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
289 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1); 319 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
@@ -296,6 +326,8 @@ static bool ath_hw_set_keycache_entry(struct ath_common *common, u16 entry,
296 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4); 326 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
297 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType); 327 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
298 328
329 REGWRITE_BUFFER_FLUSH(ah);
330
299 /* Write MAC address for the entry */ 331 /* Write MAC address for the entry */
300 (void) ath_hw_keysetmac(common, entry, mac); 332 (void) ath_hw_keysetmac(common, entry, mac);
301 } 333 }
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-23 19:27:58 -0400