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path: root/drivers/net/wireless/ath9k/hw.c
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-rw-r--r--drivers/net/wireless/ath9k/hw.c1487
1 files changed, 689 insertions, 798 deletions
diff --git a/drivers/net/wireless/ath9k/hw.c b/drivers/net/wireless/ath9k/hw.c
index 34474edefc9..cad8e39c201 100644
--- a/drivers/net/wireless/ath9k/hw.c
+++ b/drivers/net/wireless/ath9k/hw.c
@@ -17,84 +17,74 @@
17#include <linux/io.h> 17#include <linux/io.h>
18#include <asm/unaligned.h> 18#include <asm/unaligned.h>
19 19
20#include "core.h" 20#include "ath9k.h"
21#include "hw.h"
22#include "reg.h"
23#include "phy.h"
24#include "initvals.h" 21#include "initvals.h"
25 22
26static const u8 CLOCK_RATE[] = { 40, 80, 22, 44, 88, 40 }; 23static int btcoex_enable;
24module_param(btcoex_enable, bool, 0);
25MODULE_PARM_DESC(btcoex_enable, "Enable Bluetooth coexistence support");
27 26
28extern struct hal_percal_data iq_cal_multi_sample; 27#define ATH9K_CLOCK_RATE_CCK 22
29extern struct hal_percal_data iq_cal_single_sample; 28#define ATH9K_CLOCK_RATE_5GHZ_OFDM 40
30extern struct hal_percal_data adc_gain_cal_multi_sample; 29#define ATH9K_CLOCK_RATE_2GHZ_OFDM 44
31extern struct hal_percal_data adc_gain_cal_single_sample;
32extern struct hal_percal_data adc_dc_cal_multi_sample;
33extern struct hal_percal_data adc_dc_cal_single_sample;
34extern struct hal_percal_data adc_init_dc_cal;
35 30
36static bool ath9k_hw_set_reset_reg(struct ath_hal *ah, u32 type); 31static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
37static void ath9k_hw_set_regs(struct ath_hal *ah, struct ath9k_channel *chan, 32static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan,
38 enum ath9k_ht_macmode macmode); 33 enum ath9k_ht_macmode macmode);
39static u32 ath9k_hw_ini_fixup(struct ath_hal *ah, 34static u32 ath9k_hw_ini_fixup(struct ath_hw *ah,
40 struct ar5416_eeprom_def *pEepData, 35 struct ar5416_eeprom_def *pEepData,
41 u32 reg, u32 value); 36 u32 reg, u32 value);
42static void ath9k_hw_9280_spur_mitigate(struct ath_hal *ah, struct ath9k_channel *chan); 37static void ath9k_hw_9280_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan);
43static void ath9k_hw_spur_mitigate(struct ath_hal *ah, struct ath9k_channel *chan); 38static void ath9k_hw_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan);
44 39
45/********************/ 40/********************/
46/* Helper Functions */ 41/* Helper Functions */
47/********************/ 42/********************/
48 43
49static u32 ath9k_hw_mac_usec(struct ath_hal *ah, u32 clks) 44static u32 ath9k_hw_mac_usec(struct ath_hw *ah, u32 clks)
50{ 45{
51 if (ah->ah_curchan != NULL) 46 struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
52 return clks / CLOCK_RATE[ath9k_hw_chan2wmode(ah, ah->ah_curchan)]; 47
53 else 48 if (!ah->curchan) /* should really check for CCK instead */
54 return clks / CLOCK_RATE[ATH9K_MODE_11B]; 49 return clks / ATH9K_CLOCK_RATE_CCK;
50 if (conf->channel->band == IEEE80211_BAND_2GHZ)
51 return clks / ATH9K_CLOCK_RATE_2GHZ_OFDM;
52
53 return clks / ATH9K_CLOCK_RATE_5GHZ_OFDM;
55} 54}
56 55
57static u32 ath9k_hw_mac_to_usec(struct ath_hal *ah, u32 clks) 56static u32 ath9k_hw_mac_to_usec(struct ath_hw *ah, u32 clks)
58{ 57{
59 struct ath9k_channel *chan = ah->ah_curchan; 58 struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
60 59
61 if (chan && IS_CHAN_HT40(chan)) 60 if (conf_is_ht40(conf))
62 return ath9k_hw_mac_usec(ah, clks) / 2; 61 return ath9k_hw_mac_usec(ah, clks) / 2;
63 else 62 else
64 return ath9k_hw_mac_usec(ah, clks); 63 return ath9k_hw_mac_usec(ah, clks);
65} 64}
66 65
67static u32 ath9k_hw_mac_clks(struct ath_hal *ah, u32 usecs) 66static u32 ath9k_hw_mac_clks(struct ath_hw *ah, u32 usecs)
68{ 67{
69 if (ah->ah_curchan != NULL) 68 struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
70 return usecs * CLOCK_RATE[ath9k_hw_chan2wmode(ah, 69
71 ah->ah_curchan)]; 70 if (!ah->curchan) /* should really check for CCK instead */
72 else 71 return usecs *ATH9K_CLOCK_RATE_CCK;
73 return usecs * CLOCK_RATE[ATH9K_MODE_11B]; 72 if (conf->channel->band == IEEE80211_BAND_2GHZ)
73 return usecs *ATH9K_CLOCK_RATE_2GHZ_OFDM;
74 return usecs *ATH9K_CLOCK_RATE_5GHZ_OFDM;
74} 75}
75 76
76static u32 ath9k_hw_mac_to_clks(struct ath_hal *ah, u32 usecs) 77static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs)
77{ 78{
78 struct ath9k_channel *chan = ah->ah_curchan; 79 struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
79 80
80 if (chan && IS_CHAN_HT40(chan)) 81 if (conf_is_ht40(conf))
81 return ath9k_hw_mac_clks(ah, usecs) * 2; 82 return ath9k_hw_mac_clks(ah, usecs) * 2;
82 else 83 else
83 return ath9k_hw_mac_clks(ah, usecs); 84 return ath9k_hw_mac_clks(ah, usecs);
84} 85}
85 86
86enum wireless_mode ath9k_hw_chan2wmode(struct ath_hal *ah, 87bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val)
87 const struct ath9k_channel *chan)
88{
89 if (IS_CHAN_B(chan))
90 return ATH9K_MODE_11B;
91 if (IS_CHAN_G(chan))
92 return ATH9K_MODE_11G;
93
94 return ATH9K_MODE_11A;
95}
96
97bool ath9k_hw_wait(struct ath_hal *ah, u32 reg, u32 mask, u32 val)
98{ 88{
99 int i; 89 int i;
100 90
@@ -124,11 +114,11 @@ u32 ath9k_hw_reverse_bits(u32 val, u32 n)
124 return retval; 114 return retval;
125} 115}
126 116
127bool ath9k_get_channel_edges(struct ath_hal *ah, 117bool ath9k_get_channel_edges(struct ath_hw *ah,
128 u16 flags, u16 *low, 118 u16 flags, u16 *low,
129 u16 *high) 119 u16 *high)
130{ 120{
131 struct ath9k_hw_capabilities *pCap = &ah->ah_caps; 121 struct ath9k_hw_capabilities *pCap = &ah->caps;
132 122
133 if (flags & CHANNEL_5GHZ) { 123 if (flags & CHANNEL_5GHZ) {
134 *low = pCap->low_5ghz_chan; 124 *low = pCap->low_5ghz_chan;
@@ -143,7 +133,7 @@ bool ath9k_get_channel_edges(struct ath_hal *ah,
143 return false; 133 return false;
144} 134}
145 135
146u16 ath9k_hw_computetxtime(struct ath_hal *ah, 136u16 ath9k_hw_computetxtime(struct ath_hw *ah,
147 struct ath_rate_table *rates, 137 struct ath_rate_table *rates,
148 u32 frameLen, u16 rateix, 138 u32 frameLen, u16 rateix,
149 bool shortPreamble) 139 bool shortPreamble)
@@ -165,15 +155,15 @@ u16 ath9k_hw_computetxtime(struct ath_hal *ah,
165 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps); 155 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
166 break; 156 break;
167 case WLAN_RC_PHY_OFDM: 157 case WLAN_RC_PHY_OFDM:
168 if (ah->ah_curchan && IS_CHAN_QUARTER_RATE(ah->ah_curchan)) { 158 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) {
169 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000; 159 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
170 numBits = OFDM_PLCP_BITS + (frameLen << 3); 160 numBits = OFDM_PLCP_BITS + (frameLen << 3);
171 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol); 161 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
172 txTime = OFDM_SIFS_TIME_QUARTER 162 txTime = OFDM_SIFS_TIME_QUARTER
173 + OFDM_PREAMBLE_TIME_QUARTER 163 + OFDM_PREAMBLE_TIME_QUARTER
174 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER); 164 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
175 } else if (ah->ah_curchan && 165 } else if (ah->curchan &&
176 IS_CHAN_HALF_RATE(ah->ah_curchan)) { 166 IS_CHAN_HALF_RATE(ah->curchan)) {
177 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000; 167 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
178 numBits = OFDM_PLCP_BITS + (frameLen << 3); 168 numBits = OFDM_PLCP_BITS + (frameLen << 3);
179 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol); 169 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
@@ -199,52 +189,11 @@ u16 ath9k_hw_computetxtime(struct ath_hal *ah,
199 return txTime; 189 return txTime;
200} 190}
201 191
202u32 ath9k_hw_mhz2ieee(struct ath_hal *ah, u32 freq, u32 flags) 192void ath9k_hw_get_channel_centers(struct ath_hw *ah,
203{
204 if (flags & CHANNEL_2GHZ) {
205 if (freq == 2484)
206 return 14;
207 if (freq < 2484)
208 return (freq - 2407) / 5;
209 else
210 return 15 + ((freq - 2512) / 20);
211 } else if (flags & CHANNEL_5GHZ) {
212 if (ath9k_regd_is_public_safety_sku(ah) &&
213 IS_CHAN_IN_PUBLIC_SAFETY_BAND(freq)) {
214 return ((freq * 10) +
215 (((freq % 5) == 2) ? 5 : 0) - 49400) / 5;
216 } else if ((flags & CHANNEL_A) && (freq <= 5000)) {
217 return (freq - 4000) / 5;
218 } else {
219 return (freq - 5000) / 5;
220 }
221 } else {
222 if (freq == 2484)
223 return 14;
224 if (freq < 2484)
225 return (freq - 2407) / 5;
226 if (freq < 5000) {
227 if (ath9k_regd_is_public_safety_sku(ah)
228 && IS_CHAN_IN_PUBLIC_SAFETY_BAND(freq)) {
229 return ((freq * 10) +
230 (((freq % 5) ==
231 2) ? 5 : 0) - 49400) / 5;
232 } else if (freq > 4900) {
233 return (freq - 4000) / 5;
234 } else {
235 return 15 + ((freq - 2512) / 20);
236 }
237 }
238 return (freq - 5000) / 5;
239 }
240}
241
242void ath9k_hw_get_channel_centers(struct ath_hal *ah,
243 struct ath9k_channel *chan, 193 struct ath9k_channel *chan,
244 struct chan_centers *centers) 194 struct chan_centers *centers)
245{ 195{
246 int8_t extoff; 196 int8_t extoff;
247 struct ath_hal_5416 *ahp = AH5416(ah);
248 197
249 if (!IS_CHAN_HT40(chan)) { 198 if (!IS_CHAN_HT40(chan)) {
250 centers->ctl_center = centers->ext_center = 199 centers->ctl_center = centers->ext_center =
@@ -267,16 +216,15 @@ void ath9k_hw_get_channel_centers(struct ath_hal *ah,
267 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT); 216 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
268 centers->ext_center = 217 centers->ext_center =
269 centers->synth_center + (extoff * 218 centers->synth_center + (extoff *
270 ((ahp->ah_extprotspacing == ATH9K_HT_EXTPROTSPACING_20) ? 219 ((ah->extprotspacing == ATH9K_HT_EXTPROTSPACING_20) ?
271 HT40_CHANNEL_CENTER_SHIFT : 15)); 220 HT40_CHANNEL_CENTER_SHIFT : 15));
272
273} 221}
274 222
275/******************/ 223/******************/
276/* Chip Revisions */ 224/* Chip Revisions */
277/******************/ 225/******************/
278 226
279static void ath9k_hw_read_revisions(struct ath_hal *ah) 227static void ath9k_hw_read_revisions(struct ath_hw *ah)
280{ 228{
281 u32 val; 229 u32 val;
282 230
@@ -284,21 +232,22 @@ static void ath9k_hw_read_revisions(struct ath_hal *ah)
284 232
285 if (val == 0xFF) { 233 if (val == 0xFF) {
286 val = REG_READ(ah, AR_SREV); 234 val = REG_READ(ah, AR_SREV);
287 ah->ah_macVersion = (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S; 235 ah->hw_version.macVersion =
288 ah->ah_macRev = MS(val, AR_SREV_REVISION2); 236 (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
289 ah->ah_isPciExpress = (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1; 237 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
238 ah->is_pciexpress = (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
290 } else { 239 } else {
291 if (!AR_SREV_9100(ah)) 240 if (!AR_SREV_9100(ah))
292 ah->ah_macVersion = MS(val, AR_SREV_VERSION); 241 ah->hw_version.macVersion = MS(val, AR_SREV_VERSION);
293 242
294 ah->ah_macRev = val & AR_SREV_REVISION; 243 ah->hw_version.macRev = val & AR_SREV_REVISION;
295 244
296 if (ah->ah_macVersion == AR_SREV_VERSION_5416_PCIE) 245 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE)
297 ah->ah_isPciExpress = true; 246 ah->is_pciexpress = true;
298 } 247 }
299} 248}
300 249
301static int ath9k_hw_get_radiorev(struct ath_hal *ah) 250static int ath9k_hw_get_radiorev(struct ath_hw *ah)
302{ 251{
303 u32 val; 252 u32 val;
304 int i; 253 int i;
@@ -317,9 +266,9 @@ static int ath9k_hw_get_radiorev(struct ath_hal *ah)
317/* HW Attach, Detach, Init Routines */ 266/* HW Attach, Detach, Init Routines */
318/************************************/ 267/************************************/
319 268
320static void ath9k_hw_disablepcie(struct ath_hal *ah) 269static void ath9k_hw_disablepcie(struct ath_hw *ah)
321{ 270{
322 if (!AR_SREV_9100(ah)) 271 if (AR_SREV_9100(ah))
323 return; 272 return;
324 273
325 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00); 274 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
@@ -335,7 +284,7 @@ static void ath9k_hw_disablepcie(struct ath_hal *ah)
335 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000); 284 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
336} 285}
337 286
338static bool ath9k_hw_chip_test(struct ath_hal *ah) 287static bool ath9k_hw_chip_test(struct ath_hw *ah)
339{ 288{
340 u32 regAddr[2] = { AR_STA_ID0, AR_PHY_BASE + (8 << 2) }; 289 u32 regAddr[2] = { AR_STA_ID0, AR_PHY_BASE + (8 << 2) };
341 u32 regHold[2]; 290 u32 regHold[2];
@@ -377,6 +326,7 @@ static bool ath9k_hw_chip_test(struct ath_hal *ah)
377 REG_WRITE(ah, regAddr[i], regHold[i]); 326 REG_WRITE(ah, regAddr[i], regHold[i]);
378 } 327 }
379 udelay(100); 328 udelay(100);
329
380 return true; 330 return true;
381} 331}
382 332
@@ -389,6 +339,8 @@ static const char *ath9k_hw_devname(u16 devid)
389 return "Atheros 5418"; 339 return "Atheros 5418";
390 case AR9160_DEVID_PCI: 340 case AR9160_DEVID_PCI:
391 return "Atheros 9160"; 341 return "Atheros 9160";
342 case AR5416_AR9100_DEVID:
343 return "Atheros 9100";
392 case AR9280_DEVID_PCI: 344 case AR9280_DEVID_PCI:
393 case AR9280_DEVID_PCIE: 345 case AR9280_DEVID_PCIE:
394 return "Atheros 9280"; 346 return "Atheros 9280";
@@ -399,99 +351,91 @@ static const char *ath9k_hw_devname(u16 devid)
399 return NULL; 351 return NULL;
400} 352}
401 353
402static void ath9k_hw_set_defaults(struct ath_hal *ah) 354static void ath9k_hw_set_defaults(struct ath_hw *ah)
403{ 355{
404 int i; 356 int i;
405 357
406 ah->ah_config.dma_beacon_response_time = 2; 358 ah->config.dma_beacon_response_time = 2;
407 ah->ah_config.sw_beacon_response_time = 10; 359 ah->config.sw_beacon_response_time = 10;
408 ah->ah_config.additional_swba_backoff = 0; 360 ah->config.additional_swba_backoff = 0;
409 ah->ah_config.ack_6mb = 0x0; 361 ah->config.ack_6mb = 0x0;
410 ah->ah_config.cwm_ignore_extcca = 0; 362 ah->config.cwm_ignore_extcca = 0;
411 ah->ah_config.pcie_powersave_enable = 0; 363 ah->config.pcie_powersave_enable = 0;
412 ah->ah_config.pcie_l1skp_enable = 0; 364 ah->config.pcie_l1skp_enable = 0;
413 ah->ah_config.pcie_clock_req = 0; 365 ah->config.pcie_clock_req = 0;
414 ah->ah_config.pcie_power_reset = 0x100; 366 ah->config.pcie_power_reset = 0x100;
415 ah->ah_config.pcie_restore = 0; 367 ah->config.pcie_restore = 0;
416 ah->ah_config.pcie_waen = 0; 368 ah->config.pcie_waen = 0;
417 ah->ah_config.analog_shiftreg = 1; 369 ah->config.analog_shiftreg = 1;
418 ah->ah_config.ht_enable = 1; 370 ah->config.ht_enable = 1;
419 ah->ah_config.ofdm_trig_low = 200; 371 ah->config.ofdm_trig_low = 200;
420 ah->ah_config.ofdm_trig_high = 500; 372 ah->config.ofdm_trig_high = 500;
421 ah->ah_config.cck_trig_high = 200; 373 ah->config.cck_trig_high = 200;
422 ah->ah_config.cck_trig_low = 100; 374 ah->config.cck_trig_low = 100;
423 ah->ah_config.enable_ani = 1; 375 ah->config.enable_ani = 1;
424 ah->ah_config.noise_immunity_level = 4; 376 ah->config.noise_immunity_level = 4;
425 ah->ah_config.ofdm_weaksignal_det = 1; 377 ah->config.ofdm_weaksignal_det = 1;
426 ah->ah_config.cck_weaksignal_thr = 0; 378 ah->config.cck_weaksignal_thr = 0;
427 ah->ah_config.spur_immunity_level = 2; 379 ah->config.spur_immunity_level = 2;
428 ah->ah_config.firstep_level = 0; 380 ah->config.firstep_level = 0;
429 ah->ah_config.rssi_thr_high = 40; 381 ah->config.rssi_thr_high = 40;
430 ah->ah_config.rssi_thr_low = 7; 382 ah->config.rssi_thr_low = 7;
431 ah->ah_config.diversity_control = 0; 383 ah->config.diversity_control = 0;
432 ah->ah_config.antenna_switch_swap = 0; 384 ah->config.antenna_switch_swap = 0;
433 385
434 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) { 386 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
435 ah->ah_config.spurchans[i][0] = AR_NO_SPUR; 387 ah->config.spurchans[i][0] = AR_NO_SPUR;
436 ah->ah_config.spurchans[i][1] = AR_NO_SPUR; 388 ah->config.spurchans[i][1] = AR_NO_SPUR;
437 } 389 }
438 390
439 ah->ah_config.intr_mitigation = 1; 391 ah->config.intr_mitigation = 1;
440} 392}
441 393
442static struct ath_hal_5416 *ath9k_hw_newstate(u16 devid, 394static struct ath_hw *ath9k_hw_newstate(u16 devid, struct ath_softc *sc,
443 struct ath_softc *sc, 395 int *status)
444 void __iomem *mem,
445 int *status)
446{ 396{
447 static const u8 defbssidmask[ETH_ALEN] = 397 struct ath_hw *ah;
448 { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
449 struct ath_hal_5416 *ahp;
450 struct ath_hal *ah;
451 398
452 ahp = kzalloc(sizeof(struct ath_hal_5416), GFP_KERNEL); 399 ah = kzalloc(sizeof(struct ath_hw), GFP_KERNEL);
453 if (ahp == NULL) { 400 if (ah == NULL) {
454 DPRINTF(sc, ATH_DBG_FATAL, 401 DPRINTF(sc, ATH_DBG_FATAL,
455 "Cannot allocate memory for state block\n"); 402 "Cannot allocate memory for state block\n");
456 *status = -ENOMEM; 403 *status = -ENOMEM;
457 return NULL; 404 return NULL;
458 } 405 }
459 406
460 ah = &ahp->ah;
461 ah->ah_sc = sc; 407 ah->ah_sc = sc;
462 ah->ah_sh = mem; 408 ah->hw_version.magic = AR5416_MAGIC;
463 ah->ah_magic = AR5416_MAGIC; 409 ah->regulatory.country_code = CTRY_DEFAULT;
464 ah->ah_countryCode = CTRY_DEFAULT; 410 ah->hw_version.devid = devid;
465 ah->ah_devid = devid; 411 ah->hw_version.subvendorid = 0;
466 ah->ah_subvendorid = 0;
467 412
468 ah->ah_flags = 0; 413 ah->ah_flags = 0;
469 if ((devid == AR5416_AR9100_DEVID)) 414 if ((devid == AR5416_AR9100_DEVID))
470 ah->ah_macVersion = AR_SREV_VERSION_9100; 415 ah->hw_version.macVersion = AR_SREV_VERSION_9100;
471 if (!AR_SREV_9100(ah)) 416 if (!AR_SREV_9100(ah))
472 ah->ah_flags = AH_USE_EEPROM; 417 ah->ah_flags = AH_USE_EEPROM;
473 418
474 ah->ah_powerLimit = MAX_RATE_POWER; 419 ah->regulatory.power_limit = MAX_RATE_POWER;
475 ah->ah_tpScale = ATH9K_TP_SCALE_MAX; 420 ah->regulatory.tp_scale = ATH9K_TP_SCALE_MAX;
476 ahp->ah_atimWindow = 0; 421 ah->atim_window = 0;
477 ahp->ah_diversityControl = ah->ah_config.diversity_control; 422 ah->diversity_control = ah->config.diversity_control;
478 ahp->ah_antennaSwitchSwap = 423 ah->antenna_switch_swap =
479 ah->ah_config.antenna_switch_swap; 424 ah->config.antenna_switch_swap;
480 ahp->ah_staId1Defaults = AR_STA_ID1_CRPT_MIC_ENABLE; 425 ah->sta_id1_defaults = AR_STA_ID1_CRPT_MIC_ENABLE;
481 ahp->ah_beaconInterval = 100; 426 ah->beacon_interval = 100;
482 ahp->ah_enable32kHzClock = DONT_USE_32KHZ; 427 ah->enable_32kHz_clock = DONT_USE_32KHZ;
483 ahp->ah_slottime = (u32) -1; 428 ah->slottime = (u32) -1;
484 ahp->ah_acktimeout = (u32) -1; 429 ah->acktimeout = (u32) -1;
485 ahp->ah_ctstimeout = (u32) -1; 430 ah->ctstimeout = (u32) -1;
486 ahp->ah_globaltxtimeout = (u32) -1; 431 ah->globaltxtimeout = (u32) -1;
487 memcpy(&ahp->ah_bssidmask, defbssidmask, ETH_ALEN); 432
488 433 ah->gbeacon_rate = 0;
489 ahp->ah_gBeaconRate = 0;
490 434
491 return ahp; 435 return ah;
492} 436}
493 437
494static int ath9k_hw_rfattach(struct ath_hal *ah) 438static int ath9k_hw_rfattach(struct ath_hw *ah)
495{ 439{
496 bool rfStatus = false; 440 bool rfStatus = false;
497 int ecode = 0; 441 int ecode = 0;
@@ -506,7 +450,7 @@ static int ath9k_hw_rfattach(struct ath_hal *ah)
506 return 0; 450 return 0;
507} 451}
508 452
509static int ath9k_hw_rf_claim(struct ath_hal *ah) 453static int ath9k_hw_rf_claim(struct ath_hw *ah)
510{ 454{
511 u32 val; 455 u32 val;
512 456
@@ -526,88 +470,87 @@ static int ath9k_hw_rf_claim(struct ath_hal *ah)
526 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL, 470 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
527 "5G Radio Chip Rev 0x%02X is not " 471 "5G Radio Chip Rev 0x%02X is not "
528 "supported by this driver\n", 472 "supported by this driver\n",
529 ah->ah_analog5GhzRev); 473 ah->hw_version.analog5GhzRev);
530 return -EOPNOTSUPP; 474 return -EOPNOTSUPP;
531 } 475 }
532 476
533 ah->ah_analog5GhzRev = val; 477 ah->hw_version.analog5GhzRev = val;
534 478
535 return 0; 479 return 0;
536} 480}
537 481
538static int ath9k_hw_init_macaddr(struct ath_hal *ah) 482static int ath9k_hw_init_macaddr(struct ath_hw *ah)
539{ 483{
540 u32 sum; 484 u32 sum;
541 int i; 485 int i;
542 u16 eeval; 486 u16 eeval;
543 struct ath_hal_5416 *ahp = AH5416(ah);
544 487
545 sum = 0; 488 sum = 0;
546 for (i = 0; i < 3; i++) { 489 for (i = 0; i < 3; i++) {
547 eeval = ath9k_hw_get_eeprom(ah, AR_EEPROM_MAC(i)); 490 eeval = ah->eep_ops->get_eeprom(ah, AR_EEPROM_MAC(i));
548 sum += eeval; 491 sum += eeval;
549 ahp->ah_macaddr[2 * i] = eeval >> 8; 492 ah->macaddr[2 * i] = eeval >> 8;
550 ahp->ah_macaddr[2 * i + 1] = eeval & 0xff; 493 ah->macaddr[2 * i + 1] = eeval & 0xff;
551 } 494 }
552 if (sum == 0 || sum == 0xffff * 3) { 495 if (sum == 0 || sum == 0xffff * 3) {
553 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, 496 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
554 "mac address read failed: %pM\n", 497 "mac address read failed: %pM\n",
555 ahp->ah_macaddr); 498 ah->macaddr);
556 return -EADDRNOTAVAIL; 499 return -EADDRNOTAVAIL;
557 } 500 }
558 501
559 return 0; 502 return 0;
560} 503}
561 504
562static void ath9k_hw_init_rxgain_ini(struct ath_hal *ah) 505static void ath9k_hw_init_rxgain_ini(struct ath_hw *ah)
563{ 506{
564 u32 rxgain_type; 507 u32 rxgain_type;
565 struct ath_hal_5416 *ahp = AH5416(ah);
566 508
567 if (ath9k_hw_get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_17) { 509 if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_17) {
568 rxgain_type = ath9k_hw_get_eeprom(ah, EEP_RXGAIN_TYPE); 510 rxgain_type = ah->eep_ops->get_eeprom(ah, EEP_RXGAIN_TYPE);
569 511
570 if (rxgain_type == AR5416_EEP_RXGAIN_13DB_BACKOFF) 512 if (rxgain_type == AR5416_EEP_RXGAIN_13DB_BACKOFF)
571 INIT_INI_ARRAY(&ahp->ah_iniModesRxGain, 513 INIT_INI_ARRAY(&ah->iniModesRxGain,
572 ar9280Modes_backoff_13db_rxgain_9280_2, 514 ar9280Modes_backoff_13db_rxgain_9280_2,
573 ARRAY_SIZE(ar9280Modes_backoff_13db_rxgain_9280_2), 6); 515 ARRAY_SIZE(ar9280Modes_backoff_13db_rxgain_9280_2), 6);
574 else if (rxgain_type == AR5416_EEP_RXGAIN_23DB_BACKOFF) 516 else if (rxgain_type == AR5416_EEP_RXGAIN_23DB_BACKOFF)
575 INIT_INI_ARRAY(&ahp->ah_iniModesRxGain, 517 INIT_INI_ARRAY(&ah->iniModesRxGain,
576 ar9280Modes_backoff_23db_rxgain_9280_2, 518 ar9280Modes_backoff_23db_rxgain_9280_2,
577 ARRAY_SIZE(ar9280Modes_backoff_23db_rxgain_9280_2), 6); 519 ARRAY_SIZE(ar9280Modes_backoff_23db_rxgain_9280_2), 6);
578 else 520 else
579 INIT_INI_ARRAY(&ahp->ah_iniModesRxGain, 521 INIT_INI_ARRAY(&ah->iniModesRxGain,
580 ar9280Modes_original_rxgain_9280_2, 522 ar9280Modes_original_rxgain_9280_2,
581 ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6); 523 ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
582 } else 524 } else {
583 INIT_INI_ARRAY(&ahp->ah_iniModesRxGain, 525 INIT_INI_ARRAY(&ah->iniModesRxGain,
584 ar9280Modes_original_rxgain_9280_2, 526 ar9280Modes_original_rxgain_9280_2,
585 ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6); 527 ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
528 }
586} 529}
587 530
588static void ath9k_hw_init_txgain_ini(struct ath_hal *ah) 531static void ath9k_hw_init_txgain_ini(struct ath_hw *ah)
589{ 532{
590 u32 txgain_type; 533 u32 txgain_type;
591 struct ath_hal_5416 *ahp = AH5416(ah);
592 534
593 if (ath9k_hw_get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_19) { 535 if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_19) {
594 txgain_type = ath9k_hw_get_eeprom(ah, EEP_TXGAIN_TYPE); 536 txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE);
595 537
596 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER) 538 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER)
597 INIT_INI_ARRAY(&ahp->ah_iniModesTxGain, 539 INIT_INI_ARRAY(&ah->iniModesTxGain,
598 ar9280Modes_high_power_tx_gain_9280_2, 540 ar9280Modes_high_power_tx_gain_9280_2,
599 ARRAY_SIZE(ar9280Modes_high_power_tx_gain_9280_2), 6); 541 ARRAY_SIZE(ar9280Modes_high_power_tx_gain_9280_2), 6);
600 else 542 else
601 INIT_INI_ARRAY(&ahp->ah_iniModesTxGain, 543 INIT_INI_ARRAY(&ah->iniModesTxGain,
602 ar9280Modes_original_tx_gain_9280_2, 544 ar9280Modes_original_tx_gain_9280_2,
603 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6); 545 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
604 } else 546 } else {
605 INIT_INI_ARRAY(&ahp->ah_iniModesTxGain, 547 INIT_INI_ARRAY(&ah->iniModesTxGain,
606 ar9280Modes_original_tx_gain_9280_2, 548 ar9280Modes_original_tx_gain_9280_2,
607 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6); 549 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
550 }
608} 551}
609 552
610static int ath9k_hw_post_attach(struct ath_hal *ah) 553static int ath9k_hw_post_attach(struct ath_hw *ah)
611{ 554{
612 int ecode; 555 int ecode;
613 556
@@ -636,237 +579,234 @@ static int ath9k_hw_post_attach(struct ath_hal *ah)
636 return 0; 579 return 0;
637} 580}
638 581
639static struct ath_hal *ath9k_hw_do_attach(u16 devid, struct ath_softc *sc, 582static struct ath_hw *ath9k_hw_do_attach(u16 devid, struct ath_softc *sc,
640 void __iomem *mem, int *status) 583 int *status)
641{ 584{
642 struct ath_hal_5416 *ahp; 585 struct ath_hw *ah;
643 struct ath_hal *ah;
644 int ecode; 586 int ecode;
645 u32 i, j; 587 u32 i, j;
646 588
647 ahp = ath9k_hw_newstate(devid, sc, mem, status); 589 ah = ath9k_hw_newstate(devid, sc, status);
648 if (ahp == NULL) 590 if (ah == NULL)
649 return NULL; 591 return NULL;
650 592
651 ah = &ahp->ah;
652
653 ath9k_hw_set_defaults(ah); 593 ath9k_hw_set_defaults(ah);
654 594
655 if (ah->ah_config.intr_mitigation != 0) 595 if (ah->config.intr_mitigation != 0)
656 ahp->ah_intrMitigation = true; 596 ah->intr_mitigation = true;
657 597
658 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) { 598 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
659 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "Couldn't reset chip\n"); 599 DPRINTF(sc, ATH_DBG_RESET, "Couldn't reset chip\n");
660 ecode = -EIO; 600 ecode = -EIO;
661 goto bad; 601 goto bad;
662 } 602 }
663 603
664 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) { 604 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
665 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "Couldn't wakeup chip\n"); 605 DPRINTF(sc, ATH_DBG_RESET, "Couldn't wakeup chip\n");
666 ecode = -EIO; 606 ecode = -EIO;
667 goto bad; 607 goto bad;
668 } 608 }
669 609
670 if (ah->ah_config.serialize_regmode == SER_REG_MODE_AUTO) { 610 if (ah->config.serialize_regmode == SER_REG_MODE_AUTO) {
671 if (ah->ah_macVersion == AR_SREV_VERSION_5416_PCI) { 611 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI) {
672 ah->ah_config.serialize_regmode = 612 ah->config.serialize_regmode =
673 SER_REG_MODE_ON; 613 SER_REG_MODE_ON;
674 } else { 614 } else {
675 ah->ah_config.serialize_regmode = 615 ah->config.serialize_regmode =
676 SER_REG_MODE_OFF; 616 SER_REG_MODE_OFF;
677 } 617 }
678 } 618 }
679 619
680 DPRINTF(ah->ah_sc, ATH_DBG_RESET, 620 DPRINTF(sc, ATH_DBG_RESET, "serialize_regmode is %d\n",
681 "serialize_regmode is %d\n", 621 ah->config.serialize_regmode);
682 ah->ah_config.serialize_regmode);
683 622
684 if ((ah->ah_macVersion != AR_SREV_VERSION_5416_PCI) && 623 if ((ah->hw_version.macVersion != AR_SREV_VERSION_5416_PCI) &&
685 (ah->ah_macVersion != AR_SREV_VERSION_5416_PCIE) && 624 (ah->hw_version.macVersion != AR_SREV_VERSION_5416_PCIE) &&
686 (ah->ah_macVersion != AR_SREV_VERSION_9160) && 625 (ah->hw_version.macVersion != AR_SREV_VERSION_9160) &&
687 (!AR_SREV_9100(ah)) && (!AR_SREV_9280(ah)) && (!AR_SREV_9285(ah))) { 626 (!AR_SREV_9100(ah)) && (!AR_SREV_9280(ah)) && (!AR_SREV_9285(ah))) {
688 DPRINTF(ah->ah_sc, ATH_DBG_RESET, 627 DPRINTF(sc, ATH_DBG_RESET,
689 "Mac Chip Rev 0x%02x.%x is not supported by " 628 "Mac Chip Rev 0x%02x.%x is not supported by "
690 "this driver\n", ah->ah_macVersion, ah->ah_macRev); 629 "this driver\n", ah->hw_version.macVersion,
630 ah->hw_version.macRev);
691 ecode = -EOPNOTSUPP; 631 ecode = -EOPNOTSUPP;
692 goto bad; 632 goto bad;
693 } 633 }
694 634
695 if (AR_SREV_9100(ah)) { 635 if (AR_SREV_9100(ah)) {
696 ahp->ah_iqCalData.calData = &iq_cal_multi_sample; 636 ah->iq_caldata.calData = &iq_cal_multi_sample;
697 ahp->ah_suppCals = IQ_MISMATCH_CAL; 637 ah->supp_cals = IQ_MISMATCH_CAL;
698 ah->ah_isPciExpress = false; 638 ah->is_pciexpress = false;
699 } 639 }
700 ah->ah_phyRev = REG_READ(ah, AR_PHY_CHIP_ID); 640 ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
701 641
702 if (AR_SREV_9160_10_OR_LATER(ah)) { 642 if (AR_SREV_9160_10_OR_LATER(ah)) {
703 if (AR_SREV_9280_10_OR_LATER(ah)) { 643 if (AR_SREV_9280_10_OR_LATER(ah)) {
704 ahp->ah_iqCalData.calData = &iq_cal_single_sample; 644 ah->iq_caldata.calData = &iq_cal_single_sample;
705 ahp->ah_adcGainCalData.calData = 645 ah->adcgain_caldata.calData =
706 &adc_gain_cal_single_sample; 646 &adc_gain_cal_single_sample;
707 ahp->ah_adcDcCalData.calData = 647 ah->adcdc_caldata.calData =
708 &adc_dc_cal_single_sample; 648 &adc_dc_cal_single_sample;
709 ahp->ah_adcDcCalInitData.calData = 649 ah->adcdc_calinitdata.calData =
710 &adc_init_dc_cal; 650 &adc_init_dc_cal;
711 } else { 651 } else {
712 ahp->ah_iqCalData.calData = &iq_cal_multi_sample; 652 ah->iq_caldata.calData = &iq_cal_multi_sample;
713 ahp->ah_adcGainCalData.calData = 653 ah->adcgain_caldata.calData =
714 &adc_gain_cal_multi_sample; 654 &adc_gain_cal_multi_sample;
715 ahp->ah_adcDcCalData.calData = 655 ah->adcdc_caldata.calData =
716 &adc_dc_cal_multi_sample; 656 &adc_dc_cal_multi_sample;
717 ahp->ah_adcDcCalInitData.calData = 657 ah->adcdc_calinitdata.calData =
718 &adc_init_dc_cal; 658 &adc_init_dc_cal;
719 } 659 }
720 ahp->ah_suppCals = ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL; 660 ah->supp_cals = ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL;
721 } 661 }
722 662
723 if (AR_SREV_9160(ah)) { 663 if (AR_SREV_9160(ah)) {
724 ah->ah_config.enable_ani = 1; 664 ah->config.enable_ani = 1;
725 ahp->ah_ani_function = (ATH9K_ANI_SPUR_IMMUNITY_LEVEL | 665 ah->ani_function = (ATH9K_ANI_SPUR_IMMUNITY_LEVEL |
726 ATH9K_ANI_FIRSTEP_LEVEL); 666 ATH9K_ANI_FIRSTEP_LEVEL);
727 } else { 667 } else {
728 ahp->ah_ani_function = ATH9K_ANI_ALL; 668 ah->ani_function = ATH9K_ANI_ALL;
729 if (AR_SREV_9280_10_OR_LATER(ah)) { 669 if (AR_SREV_9280_10_OR_LATER(ah)) {
730 ahp->ah_ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL; 670 ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
731 } 671 }
732 } 672 }
733 673
734 DPRINTF(ah->ah_sc, ATH_DBG_RESET, 674 DPRINTF(sc, ATH_DBG_RESET,
735 "This Mac Chip Rev 0x%02x.%x is \n", 675 "This Mac Chip Rev 0x%02x.%x is \n",
736 ah->ah_macVersion, ah->ah_macRev); 676 ah->hw_version.macVersion, ah->hw_version.macRev);
737 677
738 if (AR_SREV_9285_12_OR_LATER(ah)) { 678 if (AR_SREV_9285_12_OR_LATER(ah)) {
739 INIT_INI_ARRAY(&ahp->ah_iniModes, ar9285Modes_9285_1_2, 679 INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285_1_2,
740 ARRAY_SIZE(ar9285Modes_9285_1_2), 6); 680 ARRAY_SIZE(ar9285Modes_9285_1_2), 6);
741 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar9285Common_9285_1_2, 681 INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285_1_2,
742 ARRAY_SIZE(ar9285Common_9285_1_2), 2); 682 ARRAY_SIZE(ar9285Common_9285_1_2), 2);
743 683
744 if (ah->ah_config.pcie_clock_req) { 684 if (ah->config.pcie_clock_req) {
745 INIT_INI_ARRAY(&ahp->ah_iniPcieSerdes, 685 INIT_INI_ARRAY(&ah->iniPcieSerdes,
746 ar9285PciePhy_clkreq_off_L1_9285_1_2, 686 ar9285PciePhy_clkreq_off_L1_9285_1_2,
747 ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285_1_2), 2); 687 ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285_1_2), 2);
748 } else { 688 } else {
749 INIT_INI_ARRAY(&ahp->ah_iniPcieSerdes, 689 INIT_INI_ARRAY(&ah->iniPcieSerdes,
750 ar9285PciePhy_clkreq_always_on_L1_9285_1_2, 690 ar9285PciePhy_clkreq_always_on_L1_9285_1_2,
751 ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285_1_2), 691 ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285_1_2),
752 2); 692 2);
753 } 693 }
754 } else if (AR_SREV_9285_10_OR_LATER(ah)) { 694 } else if (AR_SREV_9285_10_OR_LATER(ah)) {
755 INIT_INI_ARRAY(&ahp->ah_iniModes, ar9285Modes_9285, 695 INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285,
756 ARRAY_SIZE(ar9285Modes_9285), 6); 696 ARRAY_SIZE(ar9285Modes_9285), 6);
757 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar9285Common_9285, 697 INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285,
758 ARRAY_SIZE(ar9285Common_9285), 2); 698 ARRAY_SIZE(ar9285Common_9285), 2);
759 699
760 if (ah->ah_config.pcie_clock_req) { 700 if (ah->config.pcie_clock_req) {
761 INIT_INI_ARRAY(&ahp->ah_iniPcieSerdes, 701 INIT_INI_ARRAY(&ah->iniPcieSerdes,
762 ar9285PciePhy_clkreq_off_L1_9285, 702 ar9285PciePhy_clkreq_off_L1_9285,
763 ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285), 2); 703 ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285), 2);
764 } else { 704 } else {
765 INIT_INI_ARRAY(&ahp->ah_iniPcieSerdes, 705 INIT_INI_ARRAY(&ah->iniPcieSerdes,
766 ar9285PciePhy_clkreq_always_on_L1_9285, 706 ar9285PciePhy_clkreq_always_on_L1_9285,
767 ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285), 2); 707 ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285), 2);
768 } 708 }
769 } else if (AR_SREV_9280_20_OR_LATER(ah)) { 709 } else if (AR_SREV_9280_20_OR_LATER(ah)) {
770 INIT_INI_ARRAY(&ahp->ah_iniModes, ar9280Modes_9280_2, 710 INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280_2,
771 ARRAY_SIZE(ar9280Modes_9280_2), 6); 711 ARRAY_SIZE(ar9280Modes_9280_2), 6);
772 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar9280Common_9280_2, 712 INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280_2,
773 ARRAY_SIZE(ar9280Common_9280_2), 2); 713 ARRAY_SIZE(ar9280Common_9280_2), 2);
774 714
775 if (ah->ah_config.pcie_clock_req) { 715 if (ah->config.pcie_clock_req) {
776 INIT_INI_ARRAY(&ahp->ah_iniPcieSerdes, 716 INIT_INI_ARRAY(&ah->iniPcieSerdes,
777 ar9280PciePhy_clkreq_off_L1_9280, 717 ar9280PciePhy_clkreq_off_L1_9280,
778 ARRAY_SIZE(ar9280PciePhy_clkreq_off_L1_9280),2); 718 ARRAY_SIZE(ar9280PciePhy_clkreq_off_L1_9280),2);
779 } else { 719 } else {
780 INIT_INI_ARRAY(&ahp->ah_iniPcieSerdes, 720 INIT_INI_ARRAY(&ah->iniPcieSerdes,
781 ar9280PciePhy_clkreq_always_on_L1_9280, 721 ar9280PciePhy_clkreq_always_on_L1_9280,
782 ARRAY_SIZE(ar9280PciePhy_clkreq_always_on_L1_9280), 2); 722 ARRAY_SIZE(ar9280PciePhy_clkreq_always_on_L1_9280), 2);
783 } 723 }
784 INIT_INI_ARRAY(&ahp->ah_iniModesAdditional, 724 INIT_INI_ARRAY(&ah->iniModesAdditional,
785 ar9280Modes_fast_clock_9280_2, 725 ar9280Modes_fast_clock_9280_2,
786 ARRAY_SIZE(ar9280Modes_fast_clock_9280_2), 3); 726 ARRAY_SIZE(ar9280Modes_fast_clock_9280_2), 3);
787 } else if (AR_SREV_9280_10_OR_LATER(ah)) { 727 } else if (AR_SREV_9280_10_OR_LATER(ah)) {
788 INIT_INI_ARRAY(&ahp->ah_iniModes, ar9280Modes_9280, 728 INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280,
789 ARRAY_SIZE(ar9280Modes_9280), 6); 729 ARRAY_SIZE(ar9280Modes_9280), 6);
790 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar9280Common_9280, 730 INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280,
791 ARRAY_SIZE(ar9280Common_9280), 2); 731 ARRAY_SIZE(ar9280Common_9280), 2);
792 } else if (AR_SREV_9160_10_OR_LATER(ah)) { 732 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
793 INIT_INI_ARRAY(&ahp->ah_iniModes, ar5416Modes_9160, 733 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9160,
794 ARRAY_SIZE(ar5416Modes_9160), 6); 734 ARRAY_SIZE(ar5416Modes_9160), 6);
795 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar5416Common_9160, 735 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9160,
796 ARRAY_SIZE(ar5416Common_9160), 2); 736 ARRAY_SIZE(ar5416Common_9160), 2);
797 INIT_INI_ARRAY(&ahp->ah_iniBank0, ar5416Bank0_9160, 737 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9160,
798 ARRAY_SIZE(ar5416Bank0_9160), 2); 738 ARRAY_SIZE(ar5416Bank0_9160), 2);
799 INIT_INI_ARRAY(&ahp->ah_iniBB_RfGain, ar5416BB_RfGain_9160, 739 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9160,
800 ARRAY_SIZE(ar5416BB_RfGain_9160), 3); 740 ARRAY_SIZE(ar5416BB_RfGain_9160), 3);
801 INIT_INI_ARRAY(&ahp->ah_iniBank1, ar5416Bank1_9160, 741 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9160,
802 ARRAY_SIZE(ar5416Bank1_9160), 2); 742 ARRAY_SIZE(ar5416Bank1_9160), 2);
803 INIT_INI_ARRAY(&ahp->ah_iniBank2, ar5416Bank2_9160, 743 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9160,
804 ARRAY_SIZE(ar5416Bank2_9160), 2); 744 ARRAY_SIZE(ar5416Bank2_9160), 2);
805 INIT_INI_ARRAY(&ahp->ah_iniBank3, ar5416Bank3_9160, 745 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9160,
806 ARRAY_SIZE(ar5416Bank3_9160), 3); 746 ARRAY_SIZE(ar5416Bank3_9160), 3);
807 INIT_INI_ARRAY(&ahp->ah_iniBank6, ar5416Bank6_9160, 747 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9160,
808 ARRAY_SIZE(ar5416Bank6_9160), 3); 748 ARRAY_SIZE(ar5416Bank6_9160), 3);
809 INIT_INI_ARRAY(&ahp->ah_iniBank6TPC, ar5416Bank6TPC_9160, 749 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9160,
810 ARRAY_SIZE(ar5416Bank6TPC_9160), 3); 750 ARRAY_SIZE(ar5416Bank6TPC_9160), 3);
811 INIT_INI_ARRAY(&ahp->ah_iniBank7, ar5416Bank7_9160, 751 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9160,
812 ARRAY_SIZE(ar5416Bank7_9160), 2); 752 ARRAY_SIZE(ar5416Bank7_9160), 2);
813 if (AR_SREV_9160_11(ah)) { 753 if (AR_SREV_9160_11(ah)) {
814 INIT_INI_ARRAY(&ahp->ah_iniAddac, 754 INIT_INI_ARRAY(&ah->iniAddac,
815 ar5416Addac_91601_1, 755 ar5416Addac_91601_1,
816 ARRAY_SIZE(ar5416Addac_91601_1), 2); 756 ARRAY_SIZE(ar5416Addac_91601_1), 2);
817 } else { 757 } else {
818 INIT_INI_ARRAY(&ahp->ah_iniAddac, ar5416Addac_9160, 758 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9160,
819 ARRAY_SIZE(ar5416Addac_9160), 2); 759 ARRAY_SIZE(ar5416Addac_9160), 2);
820 } 760 }
821 } else if (AR_SREV_9100_OR_LATER(ah)) { 761 } else if (AR_SREV_9100_OR_LATER(ah)) {
822 INIT_INI_ARRAY(&ahp->ah_iniModes, ar5416Modes_9100, 762 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9100,
823 ARRAY_SIZE(ar5416Modes_9100), 6); 763 ARRAY_SIZE(ar5416Modes_9100), 6);
824 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar5416Common_9100, 764 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9100,
825 ARRAY_SIZE(ar5416Common_9100), 2); 765 ARRAY_SIZE(ar5416Common_9100), 2);
826 INIT_INI_ARRAY(&ahp->ah_iniBank0, ar5416Bank0_9100, 766 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9100,
827 ARRAY_SIZE(ar5416Bank0_9100), 2); 767 ARRAY_SIZE(ar5416Bank0_9100), 2);
828 INIT_INI_ARRAY(&ahp->ah_iniBB_RfGain, ar5416BB_RfGain_9100, 768 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9100,
829 ARRAY_SIZE(ar5416BB_RfGain_9100), 3); 769 ARRAY_SIZE(ar5416BB_RfGain_9100), 3);
830 INIT_INI_ARRAY(&ahp->ah_iniBank1, ar5416Bank1_9100, 770 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9100,
831 ARRAY_SIZE(ar5416Bank1_9100), 2); 771 ARRAY_SIZE(ar5416Bank1_9100), 2);
832 INIT_INI_ARRAY(&ahp->ah_iniBank2, ar5416Bank2_9100, 772 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9100,
833 ARRAY_SIZE(ar5416Bank2_9100), 2); 773 ARRAY_SIZE(ar5416Bank2_9100), 2);
834 INIT_INI_ARRAY(&ahp->ah_iniBank3, ar5416Bank3_9100, 774 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9100,
835 ARRAY_SIZE(ar5416Bank3_9100), 3); 775 ARRAY_SIZE(ar5416Bank3_9100), 3);
836 INIT_INI_ARRAY(&ahp->ah_iniBank6, ar5416Bank6_9100, 776 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9100,
837 ARRAY_SIZE(ar5416Bank6_9100), 3); 777 ARRAY_SIZE(ar5416Bank6_9100), 3);
838 INIT_INI_ARRAY(&ahp->ah_iniBank6TPC, ar5416Bank6TPC_9100, 778 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9100,
839 ARRAY_SIZE(ar5416Bank6TPC_9100), 3); 779 ARRAY_SIZE(ar5416Bank6TPC_9100), 3);
840 INIT_INI_ARRAY(&ahp->ah_iniBank7, ar5416Bank7_9100, 780 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9100,
841 ARRAY_SIZE(ar5416Bank7_9100), 2); 781 ARRAY_SIZE(ar5416Bank7_9100), 2);
842 INIT_INI_ARRAY(&ahp->ah_iniAddac, ar5416Addac_9100, 782 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9100,
843 ARRAY_SIZE(ar5416Addac_9100), 2); 783 ARRAY_SIZE(ar5416Addac_9100), 2);
844 } else { 784 } else {
845 INIT_INI_ARRAY(&ahp->ah_iniModes, ar5416Modes, 785 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes,
846 ARRAY_SIZE(ar5416Modes), 6); 786 ARRAY_SIZE(ar5416Modes), 6);
847 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar5416Common, 787 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common,
848 ARRAY_SIZE(ar5416Common), 2); 788 ARRAY_SIZE(ar5416Common), 2);
849 INIT_INI_ARRAY(&ahp->ah_iniBank0, ar5416Bank0, 789 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0,
850 ARRAY_SIZE(ar5416Bank0), 2); 790 ARRAY_SIZE(ar5416Bank0), 2);
851 INIT_INI_ARRAY(&ahp->ah_iniBB_RfGain, ar5416BB_RfGain, 791 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain,
852 ARRAY_SIZE(ar5416BB_RfGain), 3); 792 ARRAY_SIZE(ar5416BB_RfGain), 3);
853 INIT_INI_ARRAY(&ahp->ah_iniBank1, ar5416Bank1, 793 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1,
854 ARRAY_SIZE(ar5416Bank1), 2); 794 ARRAY_SIZE(ar5416Bank1), 2);
855 INIT_INI_ARRAY(&ahp->ah_iniBank2, ar5416Bank2, 795 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2,
856 ARRAY_SIZE(ar5416Bank2), 2); 796 ARRAY_SIZE(ar5416Bank2), 2);
857 INIT_INI_ARRAY(&ahp->ah_iniBank3, ar5416Bank3, 797 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3,
858 ARRAY_SIZE(ar5416Bank3), 3); 798 ARRAY_SIZE(ar5416Bank3), 3);
859 INIT_INI_ARRAY(&ahp->ah_iniBank6, ar5416Bank6, 799 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6,
860 ARRAY_SIZE(ar5416Bank6), 3); 800 ARRAY_SIZE(ar5416Bank6), 3);
861 INIT_INI_ARRAY(&ahp->ah_iniBank6TPC, ar5416Bank6TPC, 801 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC,
862 ARRAY_SIZE(ar5416Bank6TPC), 3); 802 ARRAY_SIZE(ar5416Bank6TPC), 3);
863 INIT_INI_ARRAY(&ahp->ah_iniBank7, ar5416Bank7, 803 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7,
864 ARRAY_SIZE(ar5416Bank7), 2); 804 ARRAY_SIZE(ar5416Bank7), 2);
865 INIT_INI_ARRAY(&ahp->ah_iniAddac, ar5416Addac, 805 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac,
866 ARRAY_SIZE(ar5416Addac), 2); 806 ARRAY_SIZE(ar5416Addac), 2);
867 } 807 }
868 808
869 if (ah->ah_isPciExpress) 809 if (ah->is_pciexpress)
870 ath9k_hw_configpcipowersave(ah, 0); 810 ath9k_hw_configpcipowersave(ah, 0);
871 else 811 else
872 ath9k_hw_disablepcie(ah); 812 ath9k_hw_disablepcie(ah);
@@ -883,23 +823,23 @@ static struct ath_hal *ath9k_hw_do_attach(u16 devid, struct ath_softc *sc,
883 if (AR_SREV_9280_20(ah)) 823 if (AR_SREV_9280_20(ah))
884 ath9k_hw_init_txgain_ini(ah); 824 ath9k_hw_init_txgain_ini(ah);
885 825
886 if (ah->ah_devid == AR9280_DEVID_PCI) { 826 if (ah->hw_version.devid == AR9280_DEVID_PCI) {
887 for (i = 0; i < ahp->ah_iniModes.ia_rows; i++) { 827 for (i = 0; i < ah->iniModes.ia_rows; i++) {
888 u32 reg = INI_RA(&ahp->ah_iniModes, i, 0); 828 u32 reg = INI_RA(&ah->iniModes, i, 0);
889 829
890 for (j = 1; j < ahp->ah_iniModes.ia_columns; j++) { 830 for (j = 1; j < ah->iniModes.ia_columns; j++) {
891 u32 val = INI_RA(&ahp->ah_iniModes, i, j); 831 u32 val = INI_RA(&ah->iniModes, i, j);
892 832
893 INI_RA(&ahp->ah_iniModes, i, j) = 833 INI_RA(&ah->iniModes, i, j) =
894 ath9k_hw_ini_fixup(ah, 834 ath9k_hw_ini_fixup(ah,
895 &ahp->ah_eeprom.def, 835 &ah->eeprom.def,
896 reg, val); 836 reg, val);
897 } 837 }
898 } 838 }
899 } 839 }
900 840
901 if (!ath9k_hw_fill_cap_info(ah)) { 841 if (!ath9k_hw_fill_cap_info(ah)) {
902 DPRINTF(ah->ah_sc, ATH_DBG_RESET, 842 DPRINTF(sc, ATH_DBG_RESET,
903 "failed ath9k_hw_fill_cap_info\n"); 843 "failed ath9k_hw_fill_cap_info\n");
904 ecode = -EINVAL; 844 ecode = -EINVAL;
905 goto bad; 845 goto bad;
@@ -907,29 +847,29 @@ static struct ath_hal *ath9k_hw_do_attach(u16 devid, struct ath_softc *sc,
907 847
908 ecode = ath9k_hw_init_macaddr(ah); 848 ecode = ath9k_hw_init_macaddr(ah);
909 if (ecode != 0) { 849 if (ecode != 0) {
910 DPRINTF(ah->ah_sc, ATH_DBG_RESET, 850 DPRINTF(sc, ATH_DBG_RESET,
911 "failed initializing mac address\n"); 851 "failed initializing mac address\n");
912 goto bad; 852 goto bad;
913 } 853 }
914 854
915 if (AR_SREV_9285(ah)) 855 if (AR_SREV_9285(ah))
916 ah->ah_txTrigLevel = (AR_FTRIG_256B >> AR_FTRIG_S); 856 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S);
917 else 857 else
918 ah->ah_txTrigLevel = (AR_FTRIG_512B >> AR_FTRIG_S); 858 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S);
919 859
920 ath9k_init_nfcal_hist_buffer(ah); 860 ath9k_init_nfcal_hist_buffer(ah);
921 861
922 return ah; 862 return ah;
923bad: 863bad:
924 if (ahp) 864 if (ah)
925 ath9k_hw_detach((struct ath_hal *) ahp); 865 ath9k_hw_detach(ah);
926 if (status) 866 if (status)
927 *status = ecode; 867 *status = ecode;
928 868
929 return NULL; 869 return NULL;
930} 870}
931 871
932static void ath9k_hw_init_bb(struct ath_hal *ah, 872static void ath9k_hw_init_bb(struct ath_hw *ah,
933 struct ath9k_channel *chan) 873 struct ath9k_channel *chan)
934{ 874{
935 u32 synthDelay; 875 u32 synthDelay;
@@ -945,7 +885,7 @@ static void ath9k_hw_init_bb(struct ath_hal *ah,
945 udelay(synthDelay + BASE_ACTIVATE_DELAY); 885 udelay(synthDelay + BASE_ACTIVATE_DELAY);
946} 886}
947 887
948static void ath9k_hw_init_qos(struct ath_hal *ah) 888static void ath9k_hw_init_qos(struct ath_hw *ah)
949{ 889{
950 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa); 890 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
951 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210); 891 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
@@ -962,7 +902,7 @@ static void ath9k_hw_init_qos(struct ath_hal *ah)
962 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF); 902 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
963} 903}
964 904
965static void ath9k_hw_init_pll(struct ath_hal *ah, 905static void ath9k_hw_init_pll(struct ath_hw *ah,
966 struct ath9k_channel *chan) 906 struct ath9k_channel *chan)
967{ 907{
968 u32 pll; 908 u32 pll;
@@ -1023,27 +963,26 @@ static void ath9k_hw_init_pll(struct ath_hal *ah,
1023 pll |= SM(0xb, AR_RTC_PLL_DIV); 963 pll |= SM(0xb, AR_RTC_PLL_DIV);
1024 } 964 }
1025 } 965 }
1026 REG_WRITE(ah, (u16) (AR_RTC_PLL_CONTROL), pll); 966 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
1027 967
1028 udelay(RTC_PLL_SETTLE_DELAY); 968 udelay(RTC_PLL_SETTLE_DELAY);
1029 969
1030 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK); 970 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
1031} 971}
1032 972
1033static void ath9k_hw_init_chain_masks(struct ath_hal *ah) 973static void ath9k_hw_init_chain_masks(struct ath_hw *ah)
1034{ 974{
1035 struct ath_hal_5416 *ahp = AH5416(ah);
1036 int rx_chainmask, tx_chainmask; 975 int rx_chainmask, tx_chainmask;
1037 976
1038 rx_chainmask = ahp->ah_rxchainmask; 977 rx_chainmask = ah->rxchainmask;
1039 tx_chainmask = ahp->ah_txchainmask; 978 tx_chainmask = ah->txchainmask;
1040 979
1041 switch (rx_chainmask) { 980 switch (rx_chainmask) {
1042 case 0x5: 981 case 0x5:
1043 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP, 982 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
1044 AR_PHY_SWAP_ALT_CHAIN); 983 AR_PHY_SWAP_ALT_CHAIN);
1045 case 0x3: 984 case 0x3:
1046 if (((ah)->ah_macVersion <= AR_SREV_VERSION_9160)) { 985 if (((ah)->hw_version.macVersion <= AR_SREV_VERSION_9160)) {
1047 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, 0x7); 986 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, 0x7);
1048 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, 0x7); 987 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, 0x7);
1049 break; 988 break;
@@ -1068,28 +1007,26 @@ static void ath9k_hw_init_chain_masks(struct ath_hal *ah)
1068 REG_READ(ah, AR_PHY_ANALOG_SWAP) | 0x00000001); 1007 REG_READ(ah, AR_PHY_ANALOG_SWAP) | 0x00000001);
1069} 1008}
1070 1009
1071static void ath9k_hw_init_interrupt_masks(struct ath_hal *ah, 1010static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
1072 enum nl80211_iftype opmode) 1011 enum nl80211_iftype opmode)
1073{ 1012{
1074 struct ath_hal_5416 *ahp = AH5416(ah); 1013 ah->mask_reg = AR_IMR_TXERR |
1075
1076 ahp->ah_maskReg = AR_IMR_TXERR |
1077 AR_IMR_TXURN | 1014 AR_IMR_TXURN |
1078 AR_IMR_RXERR | 1015 AR_IMR_RXERR |
1079 AR_IMR_RXORN | 1016 AR_IMR_RXORN |
1080 AR_IMR_BCNMISC; 1017 AR_IMR_BCNMISC;
1081 1018
1082 if (ahp->ah_intrMitigation) 1019 if (ah->intr_mitigation)
1083 ahp->ah_maskReg |= AR_IMR_RXINTM | AR_IMR_RXMINTR; 1020 ah->mask_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
1084 else 1021 else
1085 ahp->ah_maskReg |= AR_IMR_RXOK; 1022 ah->mask_reg |= AR_IMR_RXOK;
1086 1023
1087 ahp->ah_maskReg |= AR_IMR_TXOK; 1024 ah->mask_reg |= AR_IMR_TXOK;
1088 1025
1089 if (opmode == NL80211_IFTYPE_AP) 1026 if (opmode == NL80211_IFTYPE_AP)
1090 ahp->ah_maskReg |= AR_IMR_MIB; 1027 ah->mask_reg |= AR_IMR_MIB;
1091 1028
1092 REG_WRITE(ah, AR_IMR, ahp->ah_maskReg); 1029 REG_WRITE(ah, AR_IMR, ah->mask_reg);
1093 REG_WRITE(ah, AR_IMR_S2, REG_READ(ah, AR_IMR_S2) | AR_IMR_S2_GTT); 1030 REG_WRITE(ah, AR_IMR_S2, REG_READ(ah, AR_IMR_S2) | AR_IMR_S2_GTT);
1094 1031
1095 if (!AR_SREV_9100(ah)) { 1032 if (!AR_SREV_9100(ah)) {
@@ -1099,72 +1036,64 @@ static void ath9k_hw_init_interrupt_masks(struct ath_hal *ah,
1099 } 1036 }
1100} 1037}
1101 1038
1102static bool ath9k_hw_set_ack_timeout(struct ath_hal *ah, u32 us) 1039static bool ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us)
1103{ 1040{
1104 struct ath_hal_5416 *ahp = AH5416(ah);
1105
1106 if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_ACK))) { 1041 if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_ACK))) {
1107 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad ack timeout %u\n", us); 1042 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad ack timeout %u\n", us);
1108 ahp->ah_acktimeout = (u32) -1; 1043 ah->acktimeout = (u32) -1;
1109 return false; 1044 return false;
1110 } else { 1045 } else {
1111 REG_RMW_FIELD(ah, AR_TIME_OUT, 1046 REG_RMW_FIELD(ah, AR_TIME_OUT,
1112 AR_TIME_OUT_ACK, ath9k_hw_mac_to_clks(ah, us)); 1047 AR_TIME_OUT_ACK, ath9k_hw_mac_to_clks(ah, us));
1113 ahp->ah_acktimeout = us; 1048 ah->acktimeout = us;
1114 return true; 1049 return true;
1115 } 1050 }
1116} 1051}
1117 1052
1118static bool ath9k_hw_set_cts_timeout(struct ath_hal *ah, u32 us) 1053static bool ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
1119{ 1054{
1120 struct ath_hal_5416 *ahp = AH5416(ah);
1121
1122 if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_CTS))) { 1055 if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_CTS))) {
1123 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad cts timeout %u\n", us); 1056 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad cts timeout %u\n", us);
1124 ahp->ah_ctstimeout = (u32) -1; 1057 ah->ctstimeout = (u32) -1;
1125 return false; 1058 return false;
1126 } else { 1059 } else {
1127 REG_RMW_FIELD(ah, AR_TIME_OUT, 1060 REG_RMW_FIELD(ah, AR_TIME_OUT,
1128 AR_TIME_OUT_CTS, ath9k_hw_mac_to_clks(ah, us)); 1061 AR_TIME_OUT_CTS, ath9k_hw_mac_to_clks(ah, us));
1129 ahp->ah_ctstimeout = us; 1062 ah->ctstimeout = us;
1130 return true; 1063 return true;
1131 } 1064 }
1132} 1065}
1133 1066
1134static bool ath9k_hw_set_global_txtimeout(struct ath_hal *ah, u32 tu) 1067static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
1135{ 1068{
1136 struct ath_hal_5416 *ahp = AH5416(ah);
1137
1138 if (tu > 0xFFFF) { 1069 if (tu > 0xFFFF) {
1139 DPRINTF(ah->ah_sc, ATH_DBG_XMIT, 1070 DPRINTF(ah->ah_sc, ATH_DBG_XMIT,
1140 "bad global tx timeout %u\n", tu); 1071 "bad global tx timeout %u\n", tu);
1141 ahp->ah_globaltxtimeout = (u32) -1; 1072 ah->globaltxtimeout = (u32) -1;
1142 return false; 1073 return false;
1143 } else { 1074 } else {
1144 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu); 1075 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
1145 ahp->ah_globaltxtimeout = tu; 1076 ah->globaltxtimeout = tu;
1146 return true; 1077 return true;
1147 } 1078 }
1148} 1079}
1149 1080
1150static void ath9k_hw_init_user_settings(struct ath_hal *ah) 1081static void ath9k_hw_init_user_settings(struct ath_hw *ah)
1151{ 1082{
1152 struct ath_hal_5416 *ahp = AH5416(ah); 1083 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "ah->misc_mode 0x%x\n",
1153 1084 ah->misc_mode);
1154 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "ahp->ah_miscMode 0x%x\n",
1155 ahp->ah_miscMode);
1156 1085
1157 if (ahp->ah_miscMode != 0) 1086 if (ah->misc_mode != 0)
1158 REG_WRITE(ah, AR_PCU_MISC, 1087 REG_WRITE(ah, AR_PCU_MISC,
1159 REG_READ(ah, AR_PCU_MISC) | ahp->ah_miscMode); 1088 REG_READ(ah, AR_PCU_MISC) | ah->misc_mode);
1160 if (ahp->ah_slottime != (u32) -1) 1089 if (ah->slottime != (u32) -1)
1161 ath9k_hw_setslottime(ah, ahp->ah_slottime); 1090 ath9k_hw_setslottime(ah, ah->slottime);
1162 if (ahp->ah_acktimeout != (u32) -1) 1091 if (ah->acktimeout != (u32) -1)
1163 ath9k_hw_set_ack_timeout(ah, ahp->ah_acktimeout); 1092 ath9k_hw_set_ack_timeout(ah, ah->acktimeout);
1164 if (ahp->ah_ctstimeout != (u32) -1) 1093 if (ah->ctstimeout != (u32) -1)
1165 ath9k_hw_set_cts_timeout(ah, ahp->ah_ctstimeout); 1094 ath9k_hw_set_cts_timeout(ah, ah->ctstimeout);
1166 if (ahp->ah_globaltxtimeout != (u32) -1) 1095 if (ah->globaltxtimeout != (u32) -1)
1167 ath9k_hw_set_global_txtimeout(ah, ahp->ah_globaltxtimeout); 1096 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout);
1168} 1097}
1169 1098
1170const char *ath9k_hw_probe(u16 vendorid, u16 devid) 1099const char *ath9k_hw_probe(u16 vendorid, u16 devid)
@@ -1173,7 +1102,7 @@ const char *ath9k_hw_probe(u16 vendorid, u16 devid)
1173 ath9k_hw_devname(devid) : NULL; 1102 ath9k_hw_devname(devid) : NULL;
1174} 1103}
1175 1104
1176void ath9k_hw_detach(struct ath_hal *ah) 1105void ath9k_hw_detach(struct ath_hw *ah)
1177{ 1106{
1178 if (!AR_SREV_9100(ah)) 1107 if (!AR_SREV_9100(ah))
1179 ath9k_hw_ani_detach(ah); 1108 ath9k_hw_ani_detach(ah);
@@ -1183,19 +1112,19 @@ void ath9k_hw_detach(struct ath_hal *ah)
1183 kfree(ah); 1112 kfree(ah);
1184} 1113}
1185 1114
1186struct ath_hal *ath9k_hw_attach(u16 devid, struct ath_softc *sc, 1115struct ath_hw *ath9k_hw_attach(u16 devid, struct ath_softc *sc, int *error)
1187 void __iomem *mem, int *error)
1188{ 1116{
1189 struct ath_hal *ah = NULL; 1117 struct ath_hw *ah = NULL;
1190 1118
1191 switch (devid) { 1119 switch (devid) {
1192 case AR5416_DEVID_PCI: 1120 case AR5416_DEVID_PCI:
1193 case AR5416_DEVID_PCIE: 1121 case AR5416_DEVID_PCIE:
1122 case AR5416_AR9100_DEVID:
1194 case AR9160_DEVID_PCI: 1123 case AR9160_DEVID_PCI:
1195 case AR9280_DEVID_PCI: 1124 case AR9280_DEVID_PCI:
1196 case AR9280_DEVID_PCIE: 1125 case AR9280_DEVID_PCIE:
1197 case AR9285_DEVID_PCIE: 1126 case AR9285_DEVID_PCIE:
1198 ah = ath9k_hw_do_attach(devid, sc, mem, error); 1127 ah = ath9k_hw_do_attach(devid, sc, error);
1199 break; 1128 break;
1200 default: 1129 default:
1201 *error = -ENXIO; 1130 *error = -ENXIO;
@@ -1209,7 +1138,7 @@ struct ath_hal *ath9k_hw_attach(u16 devid, struct ath_softc *sc,
1209/* INI */ 1138/* INI */
1210/*******/ 1139/*******/
1211 1140
1212static void ath9k_hw_override_ini(struct ath_hal *ah, 1141static void ath9k_hw_override_ini(struct ath_hw *ah,
1213 struct ath9k_channel *chan) 1142 struct ath9k_channel *chan)
1214{ 1143{
1215 /* 1144 /*
@@ -1227,13 +1156,13 @@ static void ath9k_hw_override_ini(struct ath_hal *ah,
1227 REG_WRITE(ah, 0x9800 + (651 << 2), 0x11); 1156 REG_WRITE(ah, 0x9800 + (651 << 2), 0x11);
1228} 1157}
1229 1158
1230static u32 ath9k_hw_def_ini_fixup(struct ath_hal *ah, 1159static u32 ath9k_hw_def_ini_fixup(struct ath_hw *ah,
1231 struct ar5416_eeprom_def *pEepData, 1160 struct ar5416_eeprom_def *pEepData,
1232 u32 reg, u32 value) 1161 u32 reg, u32 value)
1233{ 1162{
1234 struct base_eep_header *pBase = &(pEepData->baseEepHeader); 1163 struct base_eep_header *pBase = &(pEepData->baseEepHeader);
1235 1164
1236 switch (ah->ah_devid) { 1165 switch (ah->hw_version.devid) {
1237 case AR9280_DEVID_PCI: 1166 case AR9280_DEVID_PCI:
1238 if (reg == 0x7894) { 1167 if (reg == 0x7894) {
1239 DPRINTF(ah->ah_sc, ATH_DBG_ANY, 1168 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
@@ -1261,24 +1190,22 @@ static u32 ath9k_hw_def_ini_fixup(struct ath_hal *ah,
1261 return value; 1190 return value;
1262} 1191}
1263 1192
1264static u32 ath9k_hw_ini_fixup(struct ath_hal *ah, 1193static u32 ath9k_hw_ini_fixup(struct ath_hw *ah,
1265 struct ar5416_eeprom_def *pEepData, 1194 struct ar5416_eeprom_def *pEepData,
1266 u32 reg, u32 value) 1195 u32 reg, u32 value)
1267{ 1196{
1268 struct ath_hal_5416 *ahp = AH5416(ah); 1197 if (ah->eep_map == EEP_MAP_4KBITS)
1269
1270 if (ahp->ah_eep_map == EEP_MAP_4KBITS)
1271 return value; 1198 return value;
1272 else 1199 else
1273 return ath9k_hw_def_ini_fixup(ah, pEepData, reg, value); 1200 return ath9k_hw_def_ini_fixup(ah, pEepData, reg, value);
1274} 1201}
1275 1202
1276static int ath9k_hw_process_ini(struct ath_hal *ah, 1203static int ath9k_hw_process_ini(struct ath_hw *ah,
1277 struct ath9k_channel *chan, 1204 struct ath9k_channel *chan,
1278 enum ath9k_ht_macmode macmode) 1205 enum ath9k_ht_macmode macmode)
1279{ 1206{
1280 int i, regWrites = 0; 1207 int i, regWrites = 0;
1281 struct ath_hal_5416 *ahp = AH5416(ah); 1208 struct ieee80211_channel *channel = chan->chan;
1282 u32 modesIndex, freqIndex; 1209 u32 modesIndex, freqIndex;
1283 int status; 1210 int status;
1284 1211
@@ -1310,40 +1237,38 @@ static int ath9k_hw_process_ini(struct ath_hal *ah,
1310 } 1237 }
1311 1238
1312 REG_WRITE(ah, AR_PHY(0), 0x00000007); 1239 REG_WRITE(ah, AR_PHY(0), 0x00000007);
1313
1314 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO); 1240 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO);
1315 1241 ah->eep_ops->set_addac(ah, chan);
1316 ath9k_hw_set_addac(ah, chan);
1317 1242
1318 if (AR_SREV_5416_V22_OR_LATER(ah)) { 1243 if (AR_SREV_5416_V22_OR_LATER(ah)) {
1319 REG_WRITE_ARRAY(&ahp->ah_iniAddac, 1, regWrites); 1244 REG_WRITE_ARRAY(&ah->iniAddac, 1, regWrites);
1320 } else { 1245 } else {
1321 struct ar5416IniArray temp; 1246 struct ar5416IniArray temp;
1322 u32 addacSize = 1247 u32 addacSize =
1323 sizeof(u32) * ahp->ah_iniAddac.ia_rows * 1248 sizeof(u32) * ah->iniAddac.ia_rows *
1324 ahp->ah_iniAddac.ia_columns; 1249 ah->iniAddac.ia_columns;
1325 1250
1326 memcpy(ahp->ah_addac5416_21, 1251 memcpy(ah->addac5416_21,
1327 ahp->ah_iniAddac.ia_array, addacSize); 1252 ah->iniAddac.ia_array, addacSize);
1328 1253
1329 (ahp->ah_addac5416_21)[31 * ahp->ah_iniAddac.ia_columns + 1] = 0; 1254 (ah->addac5416_21)[31 * ah->iniAddac.ia_columns + 1] = 0;
1330 1255
1331 temp.ia_array = ahp->ah_addac5416_21; 1256 temp.ia_array = ah->addac5416_21;
1332 temp.ia_columns = ahp->ah_iniAddac.ia_columns; 1257 temp.ia_columns = ah->iniAddac.ia_columns;
1333 temp.ia_rows = ahp->ah_iniAddac.ia_rows; 1258 temp.ia_rows = ah->iniAddac.ia_rows;
1334 REG_WRITE_ARRAY(&temp, 1, regWrites); 1259 REG_WRITE_ARRAY(&temp, 1, regWrites);
1335 } 1260 }
1336 1261
1337 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC); 1262 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC);
1338 1263
1339 for (i = 0; i < ahp->ah_iniModes.ia_rows; i++) { 1264 for (i = 0; i < ah->iniModes.ia_rows; i++) {
1340 u32 reg = INI_RA(&ahp->ah_iniModes, i, 0); 1265 u32 reg = INI_RA(&ah->iniModes, i, 0);
1341 u32 val = INI_RA(&ahp->ah_iniModes, i, modesIndex); 1266 u32 val = INI_RA(&ah->iniModes, i, modesIndex);
1342 1267
1343 REG_WRITE(ah, reg, val); 1268 REG_WRITE(ah, reg, val);
1344 1269
1345 if (reg >= 0x7800 && reg < 0x78a0 1270 if (reg >= 0x7800 && reg < 0x78a0
1346 && ah->ah_config.analog_shiftreg) { 1271 && ah->config.analog_shiftreg) {
1347 udelay(100); 1272 udelay(100);
1348 } 1273 }
1349 1274
@@ -1351,19 +1276,19 @@ static int ath9k_hw_process_ini(struct ath_hal *ah,
1351 } 1276 }
1352 1277
1353 if (AR_SREV_9280(ah)) 1278 if (AR_SREV_9280(ah))
1354 REG_WRITE_ARRAY(&ahp->ah_iniModesRxGain, modesIndex, regWrites); 1279 REG_WRITE_ARRAY(&ah->iniModesRxGain, modesIndex, regWrites);
1355 1280
1356 if (AR_SREV_9280(ah)) 1281 if (AR_SREV_9280(ah))
1357 REG_WRITE_ARRAY(&ahp->ah_iniModesTxGain, modesIndex, regWrites); 1282 REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites);
1358 1283
1359 for (i = 0; i < ahp->ah_iniCommon.ia_rows; i++) { 1284 for (i = 0; i < ah->iniCommon.ia_rows; i++) {
1360 u32 reg = INI_RA(&ahp->ah_iniCommon, i, 0); 1285 u32 reg = INI_RA(&ah->iniCommon, i, 0);
1361 u32 val = INI_RA(&ahp->ah_iniCommon, i, 1); 1286 u32 val = INI_RA(&ah->iniCommon, i, 1);
1362 1287
1363 REG_WRITE(ah, reg, val); 1288 REG_WRITE(ah, reg, val);
1364 1289
1365 if (reg >= 0x7800 && reg < 0x78a0 1290 if (reg >= 0x7800 && reg < 0x78a0
1366 && ah->ah_config.analog_shiftreg) { 1291 && ah->config.analog_shiftreg) {
1367 udelay(100); 1292 udelay(100);
1368 } 1293 }
1369 1294
@@ -1373,7 +1298,7 @@ static int ath9k_hw_process_ini(struct ath_hal *ah,
1373 ath9k_hw_write_regs(ah, modesIndex, freqIndex, regWrites); 1298 ath9k_hw_write_regs(ah, modesIndex, freqIndex, regWrites);
1374 1299
1375 if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan)) { 1300 if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan)) {
1376 REG_WRITE_ARRAY(&ahp->ah_iniModesAdditional, modesIndex, 1301 REG_WRITE_ARRAY(&ah->iniModesAdditional, modesIndex,
1377 regWrites); 1302 regWrites);
1378 } 1303 }
1379 1304
@@ -1381,13 +1306,12 @@ static int ath9k_hw_process_ini(struct ath_hal *ah,
1381 ath9k_hw_set_regs(ah, chan, macmode); 1306 ath9k_hw_set_regs(ah, chan, macmode);
1382 ath9k_hw_init_chain_masks(ah); 1307 ath9k_hw_init_chain_masks(ah);
1383 1308
1384 status = ath9k_hw_set_txpower(ah, chan, 1309 status = ah->eep_ops->set_txpower(ah, chan,
1385 ath9k_regd_get_ctl(ah, chan), 1310 ath9k_regd_get_ctl(ah, chan),
1386 ath9k_regd_get_antenna_allowed(ah, 1311 channel->max_antenna_gain * 2,
1387 chan), 1312 channel->max_power * 2,
1388 chan->maxRegTxPower * 2, 1313 min((u32) MAX_RATE_POWER,
1389 min((u32) MAX_RATE_POWER, 1314 (u32) ah->regulatory.power_limit));
1390 (u32) ah->ah_powerLimit));
1391 if (status != 0) { 1315 if (status != 0) {
1392 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT, 1316 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
1393 "error init'ing transmit power\n"); 1317 "error init'ing transmit power\n");
@@ -1407,7 +1331,7 @@ static int ath9k_hw_process_ini(struct ath_hal *ah,
1407/* Reset and Channel Switching Routines */ 1331/* Reset and Channel Switching Routines */
1408/****************************************/ 1332/****************************************/
1409 1333
1410static void ath9k_hw_set_rfmode(struct ath_hal *ah, struct ath9k_channel *chan) 1334static void ath9k_hw_set_rfmode(struct ath_hw *ah, struct ath9k_channel *chan)
1411{ 1335{
1412 u32 rfMode = 0; 1336 u32 rfMode = 0;
1413 1337
@@ -1427,12 +1351,12 @@ static void ath9k_hw_set_rfmode(struct ath_hal *ah, struct ath9k_channel *chan)
1427 REG_WRITE(ah, AR_PHY_MODE, rfMode); 1351 REG_WRITE(ah, AR_PHY_MODE, rfMode);
1428} 1352}
1429 1353
1430static void ath9k_hw_mark_phy_inactive(struct ath_hal *ah) 1354static void ath9k_hw_mark_phy_inactive(struct ath_hw *ah)
1431{ 1355{
1432 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS); 1356 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
1433} 1357}
1434 1358
1435static inline void ath9k_hw_set_dma(struct ath_hal *ah) 1359static inline void ath9k_hw_set_dma(struct ath_hw *ah)
1436{ 1360{
1437 u32 regval; 1361 u32 regval;
1438 1362
@@ -1442,7 +1366,7 @@ static inline void ath9k_hw_set_dma(struct ath_hal *ah)
1442 regval = REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK; 1366 regval = REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK;
1443 REG_WRITE(ah, AR_TXCFG, regval | AR_TXCFG_DMASZ_128B); 1367 REG_WRITE(ah, AR_TXCFG, regval | AR_TXCFG_DMASZ_128B);
1444 1368
1445 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->ah_txTrigLevel); 1369 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level);
1446 1370
1447 regval = REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_DMASZ_MASK; 1371 regval = REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_DMASZ_MASK;
1448 REG_WRITE(ah, AR_RXCFG, regval | AR_RXCFG_DMASZ_128B); 1372 REG_WRITE(ah, AR_RXCFG, regval | AR_RXCFG_DMASZ_128B);
@@ -1458,7 +1382,7 @@ static inline void ath9k_hw_set_dma(struct ath_hal *ah)
1458 } 1382 }
1459} 1383}
1460 1384
1461static void ath9k_hw_set_operating_mode(struct ath_hal *ah, int opmode) 1385static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode)
1462{ 1386{
1463 u32 val; 1387 u32 val;
1464 1388
@@ -1482,7 +1406,7 @@ static void ath9k_hw_set_operating_mode(struct ath_hal *ah, int opmode)
1482 } 1406 }
1483} 1407}
1484 1408
1485static inline void ath9k_hw_get_delta_slope_vals(struct ath_hal *ah, 1409static inline void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah,
1486 u32 coef_scaled, 1410 u32 coef_scaled,
1487 u32 *coef_mantissa, 1411 u32 *coef_mantissa,
1488 u32 *coef_exponent) 1412 u32 *coef_exponent)
@@ -1501,7 +1425,7 @@ static inline void ath9k_hw_get_delta_slope_vals(struct ath_hal *ah,
1501 *coef_exponent = coef_exp - 16; 1425 *coef_exponent = coef_exp - 16;
1502} 1426}
1503 1427
1504static void ath9k_hw_set_delta_slope(struct ath_hal *ah, 1428static void ath9k_hw_set_delta_slope(struct ath_hw *ah,
1505 struct ath9k_channel *chan) 1429 struct ath9k_channel *chan)
1506{ 1430{
1507 u32 coef_scaled, ds_coef_exp, ds_coef_man; 1431 u32 coef_scaled, ds_coef_exp, ds_coef_man;
@@ -1535,7 +1459,7 @@ static void ath9k_hw_set_delta_slope(struct ath_hal *ah,
1535 AR_PHY_HALFGI_DSC_EXP, ds_coef_exp); 1459 AR_PHY_HALFGI_DSC_EXP, ds_coef_exp);
1536} 1460}
1537 1461
1538static bool ath9k_hw_set_reset(struct ath_hal *ah, int type) 1462static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
1539{ 1463{
1540 u32 rst_flags; 1464 u32 rst_flags;
1541 u32 tmpReg; 1465 u32 tmpReg;
@@ -1562,11 +1486,11 @@ static bool ath9k_hw_set_reset(struct ath_hal *ah, int type)
1562 rst_flags |= AR_RTC_RC_MAC_COLD; 1486 rst_flags |= AR_RTC_RC_MAC_COLD;
1563 } 1487 }
1564 1488
1565 REG_WRITE(ah, (u16) (AR_RTC_RC), rst_flags); 1489 REG_WRITE(ah, AR_RTC_RC, rst_flags);
1566 udelay(50); 1490 udelay(50);
1567 1491
1568 REG_WRITE(ah, (u16) (AR_RTC_RC), 0); 1492 REG_WRITE(ah, AR_RTC_RC, 0);
1569 if (!ath9k_hw_wait(ah, (u16) (AR_RTC_RC), AR_RTC_RC_M, 0)) { 1493 if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0)) {
1570 DPRINTF(ah->ah_sc, ATH_DBG_RESET, 1494 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
1571 "RTC stuck in MAC reset\n"); 1495 "RTC stuck in MAC reset\n");
1572 return false; 1496 return false;
@@ -1583,13 +1507,13 @@ static bool ath9k_hw_set_reset(struct ath_hal *ah, int type)
1583 return true; 1507 return true;
1584} 1508}
1585 1509
1586static bool ath9k_hw_set_reset_power_on(struct ath_hal *ah) 1510static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
1587{ 1511{
1588 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN | 1512 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1589 AR_RTC_FORCE_WAKE_ON_INT); 1513 AR_RTC_FORCE_WAKE_ON_INT);
1590 1514
1591 REG_WRITE(ah, (u16) (AR_RTC_RESET), 0); 1515 REG_WRITE(ah, AR_RTC_RESET, 0);
1592 REG_WRITE(ah, (u16) (AR_RTC_RESET), 1); 1516 REG_WRITE(ah, AR_RTC_RESET, 1);
1593 1517
1594 if (!ath9k_hw_wait(ah, 1518 if (!ath9k_hw_wait(ah,
1595 AR_RTC_STATUS, 1519 AR_RTC_STATUS,
@@ -1604,7 +1528,7 @@ static bool ath9k_hw_set_reset_power_on(struct ath_hal *ah)
1604 return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM); 1528 return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
1605} 1529}
1606 1530
1607static bool ath9k_hw_set_reset_reg(struct ath_hal *ah, u32 type) 1531static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)
1608{ 1532{
1609 REG_WRITE(ah, AR_RTC_FORCE_WAKE, 1533 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1610 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT); 1534 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
@@ -1622,12 +1546,11 @@ static bool ath9k_hw_set_reset_reg(struct ath_hal *ah, u32 type)
1622 } 1546 }
1623} 1547}
1624 1548
1625static void ath9k_hw_set_regs(struct ath_hal *ah, struct ath9k_channel *chan, 1549static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan,
1626 enum ath9k_ht_macmode macmode) 1550 enum ath9k_ht_macmode macmode)
1627{ 1551{
1628 u32 phymode; 1552 u32 phymode;
1629 u32 enableDacFifo = 0; 1553 u32 enableDacFifo = 0;
1630 struct ath_hal_5416 *ahp = AH5416(ah);
1631 1554
1632 if (AR_SREV_9285_10_OR_LATER(ah)) 1555 if (AR_SREV_9285_10_OR_LATER(ah))
1633 enableDacFifo = (REG_READ(ah, AR_PHY_TURBO) & 1556 enableDacFifo = (REG_READ(ah, AR_PHY_TURBO) &
@@ -1643,7 +1566,7 @@ static void ath9k_hw_set_regs(struct ath_hal *ah, struct ath9k_channel *chan,
1643 (chan->chanmode == CHANNEL_G_HT40PLUS)) 1566 (chan->chanmode == CHANNEL_G_HT40PLUS))
1644 phymode |= AR_PHY_FC_DYN2040_PRI_CH; 1567 phymode |= AR_PHY_FC_DYN2040_PRI_CH;
1645 1568
1646 if (ahp->ah_extprotspacing == ATH9K_HT_EXTPROTSPACING_25) 1569 if (ah->extprotspacing == ATH9K_HT_EXTPROTSPACING_25)
1647 phymode |= AR_PHY_FC_DYN2040_EXT_CH; 1570 phymode |= AR_PHY_FC_DYN2040_EXT_CH;
1648 } 1571 }
1649 REG_WRITE(ah, AR_PHY_TURBO, phymode); 1572 REG_WRITE(ah, AR_PHY_TURBO, phymode);
@@ -1654,54 +1577,27 @@ static void ath9k_hw_set_regs(struct ath_hal *ah, struct ath9k_channel *chan,
1654 REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S); 1577 REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
1655} 1578}
1656 1579
1657static bool ath9k_hw_chip_reset(struct ath_hal *ah, 1580static bool ath9k_hw_chip_reset(struct ath_hw *ah,
1658 struct ath9k_channel *chan) 1581 struct ath9k_channel *chan)
1659{ 1582{
1660 struct ath_hal_5416 *ahp = AH5416(ah);
1661
1662 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM)) 1583 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
1663 return false; 1584 return false;
1664 1585
1665 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) 1586 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1666 return false; 1587 return false;
1667 1588
1668 ahp->ah_chipFullSleep = false; 1589 ah->chip_fullsleep = false;
1669
1670 ath9k_hw_init_pll(ah, chan); 1590 ath9k_hw_init_pll(ah, chan);
1671
1672 ath9k_hw_set_rfmode(ah, chan); 1591 ath9k_hw_set_rfmode(ah, chan);
1673 1592
1674 return true; 1593 return true;
1675} 1594}
1676 1595
1677static struct ath9k_channel *ath9k_hw_check_chan(struct ath_hal *ah, 1596static bool ath9k_hw_channel_change(struct ath_hw *ah,
1678 struct ath9k_channel *chan)
1679{
1680 if (!(IS_CHAN_2GHZ(chan) ^ IS_CHAN_5GHZ(chan))) {
1681 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
1682 "invalid channel %u/0x%x; not marked as "
1683 "2GHz or 5GHz\n", chan->channel, chan->channelFlags);
1684 return NULL;
1685 }
1686
1687 if (!IS_CHAN_OFDM(chan) &&
1688 !IS_CHAN_B(chan) &&
1689 !IS_CHAN_HT20(chan) &&
1690 !IS_CHAN_HT40(chan)) {
1691 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
1692 "invalid channel %u/0x%x; not marked as "
1693 "OFDM or CCK or HT20 or HT40PLUS or HT40MINUS\n",
1694 chan->channel, chan->channelFlags);
1695 return NULL;
1696 }
1697
1698 return ath9k_regd_check_channel(ah, chan);
1699}
1700
1701static bool ath9k_hw_channel_change(struct ath_hal *ah,
1702 struct ath9k_channel *chan, 1597 struct ath9k_channel *chan,
1703 enum ath9k_ht_macmode macmode) 1598 enum ath9k_ht_macmode macmode)
1704{ 1599{
1600 struct ieee80211_channel *channel = chan->chan;
1705 u32 synthDelay, qnum; 1601 u32 synthDelay, qnum;
1706 1602
1707 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) { 1603 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
@@ -1736,12 +1632,12 @@ static bool ath9k_hw_channel_change(struct ath_hal *ah,
1736 } 1632 }
1737 } 1633 }
1738 1634
1739 if (ath9k_hw_set_txpower(ah, chan, 1635 if (ah->eep_ops->set_txpower(ah, chan,
1740 ath9k_regd_get_ctl(ah, chan), 1636 ath9k_regd_get_ctl(ah, chan),
1741 ath9k_regd_get_antenna_allowed(ah, chan), 1637 channel->max_antenna_gain * 2,
1742 chan->maxRegTxPower * 2, 1638 channel->max_power * 2,
1743 min((u32) MAX_RATE_POWER, 1639 min((u32) MAX_RATE_POWER,
1744 (u32) ah->ah_powerLimit)) != 0) { 1640 (u32) ah->regulatory.power_limit)) != 0) {
1745 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, 1641 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
1746 "error init'ing transmit power\n"); 1642 "error init'ing transmit power\n");
1747 return false; 1643 return false;
@@ -1771,7 +1667,7 @@ static bool ath9k_hw_channel_change(struct ath_hal *ah,
1771 return true; 1667 return true;
1772} 1668}
1773 1669
1774static void ath9k_hw_9280_spur_mitigate(struct ath_hal *ah, struct ath9k_channel *chan) 1670static void ath9k_hw_9280_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan)
1775{ 1671{
1776 int bb_spur = AR_NO_SPUR; 1672 int bb_spur = AR_NO_SPUR;
1777 int freq; 1673 int freq;
@@ -1805,9 +1701,9 @@ static void ath9k_hw_9280_spur_mitigate(struct ath_hal *ah, struct ath9k_channel
1805 ath9k_hw_get_channel_centers(ah, chan, &centers); 1701 ath9k_hw_get_channel_centers(ah, chan, &centers);
1806 freq = centers.synth_center; 1702 freq = centers.synth_center;
1807 1703
1808 ah->ah_config.spurmode = SPUR_ENABLE_EEPROM; 1704 ah->config.spurmode = SPUR_ENABLE_EEPROM;
1809 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) { 1705 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
1810 cur_bb_spur = ath9k_hw_eeprom_get_spur_chan(ah, i, is2GHz); 1706 cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz);
1811 1707
1812 if (is2GHz) 1708 if (is2GHz)
1813 cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_2GHZ; 1709 cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_2GHZ;
@@ -1918,9 +1814,9 @@ static void ath9k_hw_9280_spur_mitigate(struct ath_hal *ah, struct ath9k_channel
1918 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) { 1814 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
1919 1815
1920 /* workaround for gcc bug #37014 */ 1816 /* workaround for gcc bug #37014 */
1921 volatile int tmp = abs(cur_vit_mask - bin); 1817 volatile int tmp_v = abs(cur_vit_mask - bin);
1922 1818
1923 if (tmp < 75) 1819 if (tmp_v < 75)
1924 mask_amt = 1; 1820 mask_amt = 1;
1925 else 1821 else
1926 mask_amt = 0; 1822 mask_amt = 0;
@@ -2021,7 +1917,7 @@ static void ath9k_hw_9280_spur_mitigate(struct ath_hal *ah, struct ath9k_channel
2021 REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask); 1917 REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
2022} 1918}
2023 1919
2024static void ath9k_hw_spur_mitigate(struct ath_hal *ah, struct ath9k_channel *chan) 1920static void ath9k_hw_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan)
2025{ 1921{
2026 int bb_spur = AR_NO_SPUR; 1922 int bb_spur = AR_NO_SPUR;
2027 int bin, cur_bin; 1923 int bin, cur_bin;
@@ -2050,7 +1946,7 @@ static void ath9k_hw_spur_mitigate(struct ath_hal *ah, struct ath9k_channel *cha
2050 memset(&mask_p, 0, sizeof(int8_t) * 123); 1946 memset(&mask_p, 0, sizeof(int8_t) * 123);
2051 1947
2052 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) { 1948 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
2053 cur_bb_spur = ath9k_hw_eeprom_get_spur_chan(ah, i, is2GHz); 1949 cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz);
2054 if (AR_NO_SPUR == cur_bb_spur) 1950 if (AR_NO_SPUR == cur_bb_spur)
2055 break; 1951 break;
2056 cur_bb_spur = cur_bb_spur - (chan->channel * 10); 1952 cur_bb_spur = cur_bb_spur - (chan->channel * 10);
@@ -2119,9 +2015,9 @@ static void ath9k_hw_spur_mitigate(struct ath_hal *ah, struct ath9k_channel *cha
2119 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) { 2015 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
2120 2016
2121 /* workaround for gcc bug #37014 */ 2017 /* workaround for gcc bug #37014 */
2122 volatile int tmp = abs(cur_vit_mask - bin); 2018 volatile int tmp_v = abs(cur_vit_mask - bin);
2123 2019
2124 if (tmp < 75) 2020 if (tmp_v < 75)
2125 mask_amt = 1; 2021 mask_amt = 1;
2126 else 2022 else
2127 mask_amt = 0; 2023 mask_amt = 0;
@@ -2222,58 +2118,47 @@ static void ath9k_hw_spur_mitigate(struct ath_hal *ah, struct ath9k_channel *cha
2222 REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask); 2118 REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
2223} 2119}
2224 2120
2225bool ath9k_hw_reset(struct ath_hal *ah, struct ath9k_channel *chan, 2121int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
2226 enum ath9k_ht_macmode macmode, 2122 bool bChannelChange)
2227 u8 txchainmask, u8 rxchainmask,
2228 enum ath9k_ht_extprotspacing extprotspacing,
2229 bool bChannelChange, int *status)
2230{ 2123{
2231 u32 saveLedState; 2124 u32 saveLedState;
2232 struct ath_hal_5416 *ahp = AH5416(ah); 2125 struct ath_softc *sc = ah->ah_sc;
2233 struct ath9k_channel *curchan = ah->ah_curchan; 2126 struct ath9k_channel *curchan = ah->curchan;
2234 u32 saveDefAntenna; 2127 u32 saveDefAntenna;
2235 u32 macStaId1; 2128 u32 macStaId1;
2236 int ecode; 2129 int i, rx_chainmask, r;
2237 int i, rx_chainmask;
2238
2239 ahp->ah_extprotspacing = extprotspacing;
2240 ahp->ah_txchainmask = txchainmask;
2241 ahp->ah_rxchainmask = rxchainmask;
2242 2130
2243 if (AR_SREV_9280(ah)) { 2131 ah->extprotspacing = sc->ht_extprotspacing;
2244 ahp->ah_txchainmask &= 0x3; 2132 ah->txchainmask = sc->tx_chainmask;
2245 ahp->ah_rxchainmask &= 0x3; 2133 ah->rxchainmask = sc->rx_chainmask;
2246 }
2247 2134
2248 if (ath9k_hw_check_chan(ah, chan) == NULL) { 2135 if (AR_SREV_9285(ah)) {
2249 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL, 2136 ah->txchainmask &= 0x1;
2250 "invalid channel %u/0x%x; no mapping\n", 2137 ah->rxchainmask &= 0x1;
2251 chan->channel, chan->channelFlags); 2138 } else if (AR_SREV_9280(ah)) {
2252 ecode = -EINVAL; 2139 ah->txchainmask &= 0x3;
2253 goto bad; 2140 ah->rxchainmask &= 0x3;
2254 } 2141 }
2255 2142
2256 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) { 2143 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
2257 ecode = -EIO; 2144 return -EIO;
2258 goto bad;
2259 }
2260 2145
2261 if (curchan) 2146 if (curchan)
2262 ath9k_hw_getnf(ah, curchan); 2147 ath9k_hw_getnf(ah, curchan);
2263 2148
2264 if (bChannelChange && 2149 if (bChannelChange &&
2265 (ahp->ah_chipFullSleep != true) && 2150 (ah->chip_fullsleep != true) &&
2266 (ah->ah_curchan != NULL) && 2151 (ah->curchan != NULL) &&
2267 (chan->channel != ah->ah_curchan->channel) && 2152 (chan->channel != ah->curchan->channel) &&
2268 ((chan->channelFlags & CHANNEL_ALL) == 2153 ((chan->channelFlags & CHANNEL_ALL) ==
2269 (ah->ah_curchan->channelFlags & CHANNEL_ALL)) && 2154 (ah->curchan->channelFlags & CHANNEL_ALL)) &&
2270 (!AR_SREV_9280(ah) || (!IS_CHAN_A_5MHZ_SPACED(chan) && 2155 (!AR_SREV_9280(ah) || (!IS_CHAN_A_5MHZ_SPACED(chan) &&
2271 !IS_CHAN_A_5MHZ_SPACED(ah->ah_curchan)))) { 2156 !IS_CHAN_A_5MHZ_SPACED(ah->curchan)))) {
2272 2157
2273 if (ath9k_hw_channel_change(ah, chan, macmode)) { 2158 if (ath9k_hw_channel_change(ah, chan, sc->tx_chan_width)) {
2274 ath9k_hw_loadnf(ah, ah->ah_curchan); 2159 ath9k_hw_loadnf(ah, ah->curchan);
2275 ath9k_hw_start_nfcal(ah); 2160 ath9k_hw_start_nfcal(ah);
2276 return true; 2161 return 0;
2277 } 2162 }
2278 } 2163 }
2279 2164
@@ -2291,28 +2176,32 @@ bool ath9k_hw_reset(struct ath_hal *ah, struct ath9k_channel *chan,
2291 2176
2292 if (!ath9k_hw_chip_reset(ah, chan)) { 2177 if (!ath9k_hw_chip_reset(ah, chan)) {
2293 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "chip reset failed\n"); 2178 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "chip reset failed\n");
2294 ecode = -EINVAL; 2179 return -EINVAL;
2295 goto bad;
2296 } 2180 }
2297 2181
2298 if (AR_SREV_9280(ah)) { 2182 if (AR_SREV_9280_10_OR_LATER(ah))
2299 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, 2183 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
2300 AR_GPIO_JTAG_DISABLE);
2301 2184
2302 if (test_bit(ATH9K_MODE_11A, ah->ah_caps.wireless_modes)) { 2185 r = ath9k_hw_process_ini(ah, chan, sc->tx_chan_width);
2303 if (IS_CHAN_5GHZ(chan)) 2186 if (r)
2304 ath9k_hw_set_gpio(ah, 9, 0); 2187 return r;
2305 else
2306 ath9k_hw_set_gpio(ah, 9, 1);
2307 }
2308 ath9k_hw_cfg_output(ah, 9, AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
2309 }
2310 2188
2311 ecode = ath9k_hw_process_ini(ah, chan, macmode); 2189 /* Setup MFP options for CCMP */
2312 if (ecode != 0) { 2190 if (AR_SREV_9280_20_OR_LATER(ah)) {
2313 ecode = -EINVAL; 2191 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt
2314 goto bad; 2192 * frames when constructing CCMP AAD. */
2315 } 2193 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT,
2194 0xc7ff);
2195 ah->sw_mgmt_crypto = false;
2196 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
2197 /* Disable hardware crypto for management frames */
2198 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2,
2199 AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE);
2200 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
2201 AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT);
2202 ah->sw_mgmt_crypto = true;
2203 } else
2204 ah->sw_mgmt_crypto = true;
2316 2205
2317 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan)) 2206 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
2318 ath9k_hw_set_delta_slope(ah, chan); 2207 ath9k_hw_set_delta_slope(ah, chan);
@@ -2322,61 +2211,56 @@ bool ath9k_hw_reset(struct ath_hal *ah, struct ath9k_channel *chan,
2322 else 2211 else
2323 ath9k_hw_spur_mitigate(ah, chan); 2212 ath9k_hw_spur_mitigate(ah, chan);
2324 2213
2325 if (!ath9k_hw_eeprom_set_board_values(ah, chan)) { 2214 if (!ah->eep_ops->set_board_values(ah, chan)) {
2326 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, 2215 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
2327 "error setting board options\n"); 2216 "error setting board options\n");
2328 ecode = -EIO; 2217 return -EIO;
2329 goto bad;
2330 } 2218 }
2331 2219
2332 ath9k_hw_decrease_chain_power(ah, chan); 2220 ath9k_hw_decrease_chain_power(ah, chan);
2333 2221
2334 REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(ahp->ah_macaddr)); 2222 REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(ah->macaddr));
2335 REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(ahp->ah_macaddr + 4) 2223 REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(ah->macaddr + 4)
2336 | macStaId1 2224 | macStaId1
2337 | AR_STA_ID1_RTS_USE_DEF 2225 | AR_STA_ID1_RTS_USE_DEF
2338 | (ah->ah_config. 2226 | (ah->config.
2339 ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0) 2227 ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0)
2340 | ahp->ah_staId1Defaults); 2228 | ah->sta_id1_defaults);
2341 ath9k_hw_set_operating_mode(ah, ah->ah_opmode); 2229 ath9k_hw_set_operating_mode(ah, ah->opmode);
2342 2230
2343 REG_WRITE(ah, AR_BSSMSKL, get_unaligned_le32(ahp->ah_bssidmask)); 2231 REG_WRITE(ah, AR_BSSMSKL, get_unaligned_le32(sc->bssidmask));
2344 REG_WRITE(ah, AR_BSSMSKU, get_unaligned_le16(ahp->ah_bssidmask + 4)); 2232 REG_WRITE(ah, AR_BSSMSKU, get_unaligned_le16(sc->bssidmask + 4));
2345 2233
2346 REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna); 2234 REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
2347 2235
2348 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(ahp->ah_bssid)); 2236 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(sc->curbssid));
2349 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(ahp->ah_bssid + 4) | 2237 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(sc->curbssid + 4) |
2350 ((ahp->ah_assocId & 0x3fff) << AR_BSS_ID1_AID_S)); 2238 ((sc->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
2351 2239
2352 REG_WRITE(ah, AR_ISR, ~0); 2240 REG_WRITE(ah, AR_ISR, ~0);
2353 2241
2354 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR); 2242 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
2355 2243
2356 if (AR_SREV_9280_10_OR_LATER(ah)) { 2244 if (AR_SREV_9280_10_OR_LATER(ah)) {
2357 if (!(ath9k_hw_ar9280_set_channel(ah, chan))) { 2245 if (!(ath9k_hw_ar9280_set_channel(ah, chan)))
2358 ecode = -EIO; 2246 return -EIO;
2359 goto bad;
2360 }
2361 } else { 2247 } else {
2362 if (!(ath9k_hw_set_channel(ah, chan))) { 2248 if (!(ath9k_hw_set_channel(ah, chan)))
2363 ecode = -EIO; 2249 return -EIO;
2364 goto bad;
2365 }
2366 } 2250 }
2367 2251
2368 for (i = 0; i < AR_NUM_DCU; i++) 2252 for (i = 0; i < AR_NUM_DCU; i++)
2369 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i); 2253 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
2370 2254
2371 ahp->ah_intrTxqs = 0; 2255 ah->intr_txqs = 0;
2372 for (i = 0; i < ah->ah_caps.total_queues; i++) 2256 for (i = 0; i < ah->caps.total_queues; i++)
2373 ath9k_hw_resettxqueue(ah, i); 2257 ath9k_hw_resettxqueue(ah, i);
2374 2258
2375 ath9k_hw_init_interrupt_masks(ah, ah->ah_opmode); 2259 ath9k_hw_init_interrupt_masks(ah, ah->opmode);
2376 ath9k_hw_init_qos(ah); 2260 ath9k_hw_init_qos(ah);
2377 2261
2378#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE) 2262#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2379 if (ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT) 2263 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
2380 ath9k_enable_rfkill(ah); 2264 ath9k_enable_rfkill(ah);
2381#endif 2265#endif
2382 ath9k_hw_init_user_settings(ah); 2266 ath9k_hw_init_user_settings(ah);
@@ -2388,7 +2272,7 @@ bool ath9k_hw_reset(struct ath_hal *ah, struct ath9k_channel *chan,
2388 2272
2389 REG_WRITE(ah, AR_OBS, 8); 2273 REG_WRITE(ah, AR_OBS, 8);
2390 2274
2391 if (ahp->ah_intrMitigation) { 2275 if (ah->intr_mitigation) {
2392 2276
2393 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500); 2277 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
2394 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000); 2278 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
@@ -2396,12 +2280,10 @@ bool ath9k_hw_reset(struct ath_hal *ah, struct ath9k_channel *chan,
2396 2280
2397 ath9k_hw_init_bb(ah, chan); 2281 ath9k_hw_init_bb(ah, chan);
2398 2282
2399 if (!ath9k_hw_init_cal(ah, chan)){ 2283 if (!ath9k_hw_init_cal(ah, chan))
2400 ecode = -EIO;; 2284 return -EIO;;
2401 goto bad;
2402 }
2403 2285
2404 rx_chainmask = ahp->ah_rxchainmask; 2286 rx_chainmask = ah->rxchainmask;
2405 if ((rx_chainmask == 0x5) || (rx_chainmask == 0x3)) { 2287 if ((rx_chainmask == 0x5) || (rx_chainmask == 0x3)) {
2406 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask); 2288 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
2407 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask); 2289 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
@@ -2428,22 +2310,18 @@ bool ath9k_hw_reset(struct ath_hal *ah, struct ath9k_channel *chan,
2428#endif 2310#endif
2429 } 2311 }
2430 2312
2431 return true; 2313 return 0;
2432bad:
2433 if (status)
2434 *status = ecode;
2435 return false;
2436} 2314}
2437 2315
2438/************************/ 2316/************************/
2439/* Key Cache Management */ 2317/* Key Cache Management */
2440/************************/ 2318/************************/
2441 2319
2442bool ath9k_hw_keyreset(struct ath_hal *ah, u16 entry) 2320bool ath9k_hw_keyreset(struct ath_hw *ah, u16 entry)
2443{ 2321{
2444 u32 keyType; 2322 u32 keyType;
2445 2323
2446 if (entry >= ah->ah_caps.keycache_size) { 2324 if (entry >= ah->caps.keycache_size) {
2447 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE, 2325 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
2448 "entry %u out of range\n", entry); 2326 "entry %u out of range\n", entry);
2449 return false; 2327 return false;
@@ -2470,17 +2348,17 @@ bool ath9k_hw_keyreset(struct ath_hal *ah, u16 entry)
2470 2348
2471 } 2349 }
2472 2350
2473 if (ah->ah_curchan == NULL) 2351 if (ah->curchan == NULL)
2474 return true; 2352 return true;
2475 2353
2476 return true; 2354 return true;
2477} 2355}
2478 2356
2479bool ath9k_hw_keysetmac(struct ath_hal *ah, u16 entry, const u8 *mac) 2357bool ath9k_hw_keysetmac(struct ath_hw *ah, u16 entry, const u8 *mac)
2480{ 2358{
2481 u32 macHi, macLo; 2359 u32 macHi, macLo;
2482 2360
2483 if (entry >= ah->ah_caps.keycache_size) { 2361 if (entry >= ah->caps.keycache_size) {
2484 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE, 2362 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
2485 "entry %u out of range\n", entry); 2363 "entry %u out of range\n", entry);
2486 return false; 2364 return false;
@@ -2504,17 +2382,16 @@ bool ath9k_hw_keysetmac(struct ath_hal *ah, u16 entry, const u8 *mac)
2504 return true; 2382 return true;
2505} 2383}
2506 2384
2507bool ath9k_hw_set_keycache_entry(struct ath_hal *ah, u16 entry, 2385bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry,
2508 const struct ath9k_keyval *k, 2386 const struct ath9k_keyval *k,
2509 const u8 *mac, int xorKey) 2387 const u8 *mac, int xorKey)
2510{ 2388{
2511 const struct ath9k_hw_capabilities *pCap = &ah->ah_caps; 2389 const struct ath9k_hw_capabilities *pCap = &ah->caps;
2512 u32 key0, key1, key2, key3, key4; 2390 u32 key0, key1, key2, key3, key4;
2513 u32 keyType; 2391 u32 keyType;
2514 u32 xorMask = xorKey ? 2392 u32 xorMask = xorKey ?
2515 (ATH9K_KEY_XOR << 24 | ATH9K_KEY_XOR << 16 | ATH9K_KEY_XOR << 8 2393 (ATH9K_KEY_XOR << 24 | ATH9K_KEY_XOR << 16 | ATH9K_KEY_XOR << 8
2516 | ATH9K_KEY_XOR) : 0; 2394 | ATH9K_KEY_XOR) : 0;
2517 struct ath_hal_5416 *ahp = AH5416(ah);
2518 2395
2519 if (entry >= pCap->keycache_size) { 2396 if (entry >= pCap->keycache_size) {
2520 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE, 2397 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
@@ -2530,7 +2407,7 @@ bool ath9k_hw_set_keycache_entry(struct ath_hal *ah, u16 entry,
2530 if (!(pCap->hw_caps & ATH9K_HW_CAP_CIPHER_AESCCM)) { 2407 if (!(pCap->hw_caps & ATH9K_HW_CAP_CIPHER_AESCCM)) {
2531 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE, 2408 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
2532 "AES-CCM not supported by mac rev 0x%x\n", 2409 "AES-CCM not supported by mac rev 0x%x\n",
2533 ah->ah_macRev); 2410 ah->hw_version.macRev);
2534 return false; 2411 return false;
2535 } 2412 }
2536 keyType = AR_KEYTABLE_TYPE_CCM; 2413 keyType = AR_KEYTABLE_TYPE_CCM;
@@ -2585,7 +2462,7 @@ bool ath9k_hw_set_keycache_entry(struct ath_hal *ah, u16 entry,
2585 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType); 2462 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
2586 (void) ath9k_hw_keysetmac(ah, entry, mac); 2463 (void) ath9k_hw_keysetmac(ah, entry, mac);
2587 2464
2588 if (ahp->ah_miscMode & AR_PCU_MIC_NEW_LOC_ENA) { 2465 if (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) {
2589 u32 mic0, mic1, mic2, mic3, mic4; 2466 u32 mic0, mic1, mic2, mic3, mic4;
2590 2467
2591 mic0 = get_unaligned_le32(k->kv_mic + 0); 2468 mic0 = get_unaligned_le32(k->kv_mic + 0);
@@ -2629,15 +2506,15 @@ bool ath9k_hw_set_keycache_entry(struct ath_hal *ah, u16 entry,
2629 (void) ath9k_hw_keysetmac(ah, entry, mac); 2506 (void) ath9k_hw_keysetmac(ah, entry, mac);
2630 } 2507 }
2631 2508
2632 if (ah->ah_curchan == NULL) 2509 if (ah->curchan == NULL)
2633 return true; 2510 return true;
2634 2511
2635 return true; 2512 return true;
2636} 2513}
2637 2514
2638bool ath9k_hw_keyisvalid(struct ath_hal *ah, u16 entry) 2515bool ath9k_hw_keyisvalid(struct ath_hw *ah, u16 entry)
2639{ 2516{
2640 if (entry < ah->ah_caps.keycache_size) { 2517 if (entry < ah->caps.keycache_size) {
2641 u32 val = REG_READ(ah, AR_KEYTABLE_MAC1(entry)); 2518 u32 val = REG_READ(ah, AR_KEYTABLE_MAC1(entry));
2642 if (val & AR_KEYTABLE_VALID) 2519 if (val & AR_KEYTABLE_VALID)
2643 return true; 2520 return true;
@@ -2649,7 +2526,7 @@ bool ath9k_hw_keyisvalid(struct ath_hal *ah, u16 entry)
2649/* Power Management (Chipset) */ 2526/* Power Management (Chipset) */
2650/******************************/ 2527/******************************/
2651 2528
2652static void ath9k_set_power_sleep(struct ath_hal *ah, int setChip) 2529static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip)
2653{ 2530{
2654 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); 2531 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2655 if (setChip) { 2532 if (setChip) {
@@ -2658,16 +2535,16 @@ static void ath9k_set_power_sleep(struct ath_hal *ah, int setChip)
2658 if (!AR_SREV_9100(ah)) 2535 if (!AR_SREV_9100(ah))
2659 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF); 2536 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
2660 2537
2661 REG_CLR_BIT(ah, (u16) (AR_RTC_RESET), 2538 REG_CLR_BIT(ah, (AR_RTC_RESET),
2662 AR_RTC_RESET_EN); 2539 AR_RTC_RESET_EN);
2663 } 2540 }
2664} 2541}
2665 2542
2666static void ath9k_set_power_network_sleep(struct ath_hal *ah, int setChip) 2543static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip)
2667{ 2544{
2668 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); 2545 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2669 if (setChip) { 2546 if (setChip) {
2670 struct ath9k_hw_capabilities *pCap = &ah->ah_caps; 2547 struct ath9k_hw_capabilities *pCap = &ah->caps;
2671 2548
2672 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) { 2549 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2673 REG_WRITE(ah, AR_RTC_FORCE_WAKE, 2550 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
@@ -2679,8 +2556,7 @@ static void ath9k_set_power_network_sleep(struct ath_hal *ah, int setChip)
2679 } 2556 }
2680} 2557}
2681 2558
2682static bool ath9k_hw_set_power_awake(struct ath_hal *ah, 2559static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip)
2683 int setChip)
2684{ 2560{
2685 u32 val; 2561 u32 val;
2686 int i; 2562 int i;
@@ -2721,20 +2597,18 @@ static bool ath9k_hw_set_power_awake(struct ath_hal *ah,
2721 return true; 2597 return true;
2722} 2598}
2723 2599
2724bool ath9k_hw_setpower(struct ath_hal *ah, 2600bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
2725 enum ath9k_power_mode mode)
2726{ 2601{
2727 struct ath_hal_5416 *ahp = AH5416(ah); 2602 int status = true, setChip = true;
2728 static const char *modes[] = { 2603 static const char *modes[] = {
2729 "AWAKE", 2604 "AWAKE",
2730 "FULL-SLEEP", 2605 "FULL-SLEEP",
2731 "NETWORK SLEEP", 2606 "NETWORK SLEEP",
2732 "UNDEFINED" 2607 "UNDEFINED"
2733 }; 2608 };
2734 int status = true, setChip = true;
2735 2609
2736 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT, "%s -> %s (%s)\n", 2610 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT, "%s -> %s (%s)\n",
2737 modes[ahp->ah_powerMode], modes[mode], 2611 modes[ah->power_mode], modes[mode],
2738 setChip ? "set chip " : ""); 2612 setChip ? "set chip " : "");
2739 2613
2740 switch (mode) { 2614 switch (mode) {
@@ -2743,7 +2617,7 @@ bool ath9k_hw_setpower(struct ath_hal *ah,
2743 break; 2617 break;
2744 case ATH9K_PM_FULL_SLEEP: 2618 case ATH9K_PM_FULL_SLEEP:
2745 ath9k_set_power_sleep(ah, setChip); 2619 ath9k_set_power_sleep(ah, setChip);
2746 ahp->ah_chipFullSleep = true; 2620 ah->chip_fullsleep = true;
2747 break; 2621 break;
2748 case ATH9K_PM_NETWORK_SLEEP: 2622 case ATH9K_PM_NETWORK_SLEEP:
2749 ath9k_set_power_network_sleep(ah, setChip); 2623 ath9k_set_power_network_sleep(ah, setChip);
@@ -2753,41 +2627,57 @@ bool ath9k_hw_setpower(struct ath_hal *ah,
2753 "Unknown power mode %u\n", mode); 2627 "Unknown power mode %u\n", mode);
2754 return false; 2628 return false;
2755 } 2629 }
2756 ahp->ah_powerMode = mode; 2630 ah->power_mode = mode;
2757 2631
2758 return status; 2632 return status;
2759} 2633}
2760 2634
2761void ath9k_hw_configpcipowersave(struct ath_hal *ah, int restore) 2635/*
2636 * Helper for ASPM support.
2637 *
2638 * Disable PLL when in L0s as well as receiver clock when in L1.
2639 * This power saving option must be enabled through the SerDes.
2640 *
2641 * Programming the SerDes must go through the same 288 bit serial shift
2642 * register as the other analog registers. Hence the 9 writes.
2643 */
2644void ath9k_hw_configpcipowersave(struct ath_hw *ah, int restore)
2762{ 2645{
2763 struct ath_hal_5416 *ahp = AH5416(ah);
2764 u8 i; 2646 u8 i;
2765 2647
2766 if (ah->ah_isPciExpress != true) 2648 if (ah->is_pciexpress != true)
2767 return; 2649 return;
2768 2650
2769 if (ah->ah_config.pcie_powersave_enable == 2) 2651 /* Do not touch SerDes registers */
2652 if (ah->config.pcie_powersave_enable == 2)
2770 return; 2653 return;
2771 2654
2655 /* Nothing to do on restore for 11N */
2772 if (restore) 2656 if (restore)
2773 return; 2657 return;
2774 2658
2775 if (AR_SREV_9280_20_OR_LATER(ah)) { 2659 if (AR_SREV_9280_20_OR_LATER(ah)) {
2776 for (i = 0; i < ahp->ah_iniPcieSerdes.ia_rows; i++) { 2660 /*
2777 REG_WRITE(ah, INI_RA(&ahp->ah_iniPcieSerdes, i, 0), 2661 * AR9280 2.0 or later chips use SerDes values from the
2778 INI_RA(&ahp->ah_iniPcieSerdes, i, 1)); 2662 * initvals.h initialized depending on chipset during
2663 * ath9k_hw_do_attach()
2664 */
2665 for (i = 0; i < ah->iniPcieSerdes.ia_rows; i++) {
2666 REG_WRITE(ah, INI_RA(&ah->iniPcieSerdes, i, 0),
2667 INI_RA(&ah->iniPcieSerdes, i, 1));
2779 } 2668 }
2780 udelay(1000);
2781 } else if (AR_SREV_9280(ah) && 2669 } else if (AR_SREV_9280(ah) &&
2782 (ah->ah_macRev == AR_SREV_REVISION_9280_10)) { 2670 (ah->hw_version.macRev == AR_SREV_REVISION_9280_10)) {
2783 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fd00); 2671 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fd00);
2784 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924); 2672 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
2785 2673
2674 /* RX shut off when elecidle is asserted */
2786 REG_WRITE(ah, AR_PCIE_SERDES, 0xa8000019); 2675 REG_WRITE(ah, AR_PCIE_SERDES, 0xa8000019);
2787 REG_WRITE(ah, AR_PCIE_SERDES, 0x13160820); 2676 REG_WRITE(ah, AR_PCIE_SERDES, 0x13160820);
2788 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980560); 2677 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980560);
2789 2678
2790 if (ah->ah_config.pcie_clock_req) 2679 /* Shut off CLKREQ active in L1 */
2680 if (ah->config.pcie_clock_req)
2791 REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffc); 2681 REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffc);
2792 else 2682 else
2793 REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffd); 2683 REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffd);
@@ -2796,42 +2686,59 @@ void ath9k_hw_configpcipowersave(struct ath_hal *ah, int restore)
2796 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554); 2686 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
2797 REG_WRITE(ah, AR_PCIE_SERDES, 0x00043007); 2687 REG_WRITE(ah, AR_PCIE_SERDES, 0x00043007);
2798 2688
2689 /* Load the new settings */
2799 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000); 2690 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
2800 2691
2801 udelay(1000);
2802 } else { 2692 } else {
2803 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00); 2693 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
2804 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924); 2694 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
2695
2696 /* RX shut off when elecidle is asserted */
2805 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000039); 2697 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000039);
2806 REG_WRITE(ah, AR_PCIE_SERDES, 0x53160824); 2698 REG_WRITE(ah, AR_PCIE_SERDES, 0x53160824);
2807 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980579); 2699 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980579);
2700
2701 /*
2702 * Ignore ah->ah_config.pcie_clock_req setting for
2703 * pre-AR9280 11n
2704 */
2808 REG_WRITE(ah, AR_PCIE_SERDES, 0x001defff); 2705 REG_WRITE(ah, AR_PCIE_SERDES, 0x001defff);
2706
2809 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40); 2707 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
2810 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554); 2708 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
2811 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e3007); 2709 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e3007);
2710
2711 /* Load the new settings */
2812 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000); 2712 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
2813 } 2713 }
2814 2714
2715 udelay(1000);
2716
2717 /* set bit 19 to allow forcing of pcie core into L1 state */
2815 REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA); 2718 REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
2816 2719
2817 if (ah->ah_config.pcie_waen) { 2720 /* Several PCIe massages to ensure proper behaviour */
2818 REG_WRITE(ah, AR_WA, ah->ah_config.pcie_waen); 2721 if (ah->config.pcie_waen) {
2722 REG_WRITE(ah, AR_WA, ah->config.pcie_waen);
2819 } else { 2723 } else {
2820 if (AR_SREV_9285(ah)) 2724 if (AR_SREV_9285(ah))
2821 REG_WRITE(ah, AR_WA, AR9285_WA_DEFAULT); 2725 REG_WRITE(ah, AR_WA, AR9285_WA_DEFAULT);
2726 /*
2727 * On AR9280 chips bit 22 of 0x4004 needs to be set to
2728 * otherwise card may disappear.
2729 */
2822 else if (AR_SREV_9280(ah)) 2730 else if (AR_SREV_9280(ah))
2823 REG_WRITE(ah, AR_WA, AR9280_WA_DEFAULT); 2731 REG_WRITE(ah, AR_WA, AR9280_WA_DEFAULT);
2824 else 2732 else
2825 REG_WRITE(ah, AR_WA, AR_WA_DEFAULT); 2733 REG_WRITE(ah, AR_WA, AR_WA_DEFAULT);
2826 } 2734 }
2827
2828} 2735}
2829 2736
2830/**********************/ 2737/**********************/
2831/* Interrupt Handling */ 2738/* Interrupt Handling */
2832/**********************/ 2739/**********************/
2833 2740
2834bool ath9k_hw_intrpend(struct ath_hal *ah) 2741bool ath9k_hw_intrpend(struct ath_hw *ah)
2835{ 2742{
2836 u32 host_isr; 2743 u32 host_isr;
2837 2744
@@ -2850,14 +2757,13 @@ bool ath9k_hw_intrpend(struct ath_hal *ah)
2850 return false; 2757 return false;
2851} 2758}
2852 2759
2853bool ath9k_hw_getisr(struct ath_hal *ah, enum ath9k_int *masked) 2760bool ath9k_hw_getisr(struct ath_hw *ah, enum ath9k_int *masked)
2854{ 2761{
2855 u32 isr = 0; 2762 u32 isr = 0;
2856 u32 mask2 = 0; 2763 u32 mask2 = 0;
2857 struct ath9k_hw_capabilities *pCap = &ah->ah_caps; 2764 struct ath9k_hw_capabilities *pCap = &ah->caps;
2858 u32 sync_cause = 0; 2765 u32 sync_cause = 0;
2859 bool fatal_int = false; 2766 bool fatal_int = false;
2860 struct ath_hal_5416 *ahp = AH5416(ah);
2861 2767
2862 if (!AR_SREV_9100(ah)) { 2768 if (!AR_SREV_9100(ah)) {
2863 if (REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) { 2769 if (REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) {
@@ -2905,7 +2811,7 @@ bool ath9k_hw_getisr(struct ath_hal *ah, enum ath9k_int *masked)
2905 2811
2906 *masked = isr & ATH9K_INT_COMMON; 2812 *masked = isr & ATH9K_INT_COMMON;
2907 2813
2908 if (ahp->ah_intrMitigation) { 2814 if (ah->intr_mitigation) {
2909 if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM)) 2815 if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM))
2910 *masked |= ATH9K_INT_RX; 2816 *masked |= ATH9K_INT_RX;
2911 } 2817 }
@@ -2920,12 +2826,12 @@ bool ath9k_hw_getisr(struct ath_hal *ah, enum ath9k_int *masked)
2920 *masked |= ATH9K_INT_TX; 2826 *masked |= ATH9K_INT_TX;
2921 2827
2922 s0_s = REG_READ(ah, AR_ISR_S0_S); 2828 s0_s = REG_READ(ah, AR_ISR_S0_S);
2923 ahp->ah_intrTxqs |= MS(s0_s, AR_ISR_S0_QCU_TXOK); 2829 ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXOK);
2924 ahp->ah_intrTxqs |= MS(s0_s, AR_ISR_S0_QCU_TXDESC); 2830 ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXDESC);
2925 2831
2926 s1_s = REG_READ(ah, AR_ISR_S1_S); 2832 s1_s = REG_READ(ah, AR_ISR_S1_S);
2927 ahp->ah_intrTxqs |= MS(s1_s, AR_ISR_S1_QCU_TXERR); 2833 ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXERR);
2928 ahp->ah_intrTxqs |= MS(s1_s, AR_ISR_S1_QCU_TXEOL); 2834 ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXEOL);
2929 } 2835 }
2930 2836
2931 if (isr & AR_ISR_RXORN) { 2837 if (isr & AR_ISR_RXORN) {
@@ -2982,17 +2888,16 @@ bool ath9k_hw_getisr(struct ath_hal *ah, enum ath9k_int *masked)
2982 return true; 2888 return true;
2983} 2889}
2984 2890
2985enum ath9k_int ath9k_hw_intrget(struct ath_hal *ah) 2891enum ath9k_int ath9k_hw_intrget(struct ath_hw *ah)
2986{ 2892{
2987 return AH5416(ah)->ah_maskReg; 2893 return ah->mask_reg;
2988} 2894}
2989 2895
2990enum ath9k_int ath9k_hw_set_interrupts(struct ath_hal *ah, enum ath9k_int ints) 2896enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints)
2991{ 2897{
2992 struct ath_hal_5416 *ahp = AH5416(ah); 2898 u32 omask = ah->mask_reg;
2993 u32 omask = ahp->ah_maskReg;
2994 u32 mask, mask2; 2899 u32 mask, mask2;
2995 struct ath9k_hw_capabilities *pCap = &ah->ah_caps; 2900 struct ath9k_hw_capabilities *pCap = &ah->caps;
2996 2901
2997 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "0x%x => 0x%x\n", omask, ints); 2902 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "0x%x => 0x%x\n", omask, ints);
2998 2903
@@ -3013,18 +2918,18 @@ enum ath9k_int ath9k_hw_set_interrupts(struct ath_hal *ah, enum ath9k_int ints)
3013 mask2 = 0; 2918 mask2 = 0;
3014 2919
3015 if (ints & ATH9K_INT_TX) { 2920 if (ints & ATH9K_INT_TX) {
3016 if (ahp->ah_txOkInterruptMask) 2921 if (ah->txok_interrupt_mask)
3017 mask |= AR_IMR_TXOK; 2922 mask |= AR_IMR_TXOK;
3018 if (ahp->ah_txDescInterruptMask) 2923 if (ah->txdesc_interrupt_mask)
3019 mask |= AR_IMR_TXDESC; 2924 mask |= AR_IMR_TXDESC;
3020 if (ahp->ah_txErrInterruptMask) 2925 if (ah->txerr_interrupt_mask)
3021 mask |= AR_IMR_TXERR; 2926 mask |= AR_IMR_TXERR;
3022 if (ahp->ah_txEolInterruptMask) 2927 if (ah->txeol_interrupt_mask)
3023 mask |= AR_IMR_TXEOL; 2928 mask |= AR_IMR_TXEOL;
3024 } 2929 }
3025 if (ints & ATH9K_INT_RX) { 2930 if (ints & ATH9K_INT_RX) {
3026 mask |= AR_IMR_RXERR; 2931 mask |= AR_IMR_RXERR;
3027 if (ahp->ah_intrMitigation) 2932 if (ah->intr_mitigation)
3028 mask |= AR_IMR_RXMINTR | AR_IMR_RXINTM; 2933 mask |= AR_IMR_RXMINTR | AR_IMR_RXINTM;
3029 else 2934 else
3030 mask |= AR_IMR_RXOK | AR_IMR_RXDESC; 2935 mask |= AR_IMR_RXOK | AR_IMR_RXDESC;
@@ -3062,7 +2967,7 @@ enum ath9k_int ath9k_hw_set_interrupts(struct ath_hal *ah, enum ath9k_int ints)
3062 AR_IMR_S2_TSFOOR | 2967 AR_IMR_S2_TSFOOR |
3063 AR_IMR_S2_GTT | AR_IMR_S2_CST); 2968 AR_IMR_S2_GTT | AR_IMR_S2_CST);
3064 REG_WRITE(ah, AR_IMR_S2, mask | mask2); 2969 REG_WRITE(ah, AR_IMR_S2, mask | mask2);
3065 ahp->ah_maskReg = ints; 2970 ah->mask_reg = ints;
3066 2971
3067 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) { 2972 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
3068 if (ints & ATH9K_INT_TIM_TIMER) 2973 if (ints & ATH9K_INT_TIM_TIMER)
@@ -3096,14 +3001,13 @@ enum ath9k_int ath9k_hw_set_interrupts(struct ath_hal *ah, enum ath9k_int ints)
3096/* Beacon Handling */ 3001/* Beacon Handling */
3097/*******************/ 3002/*******************/
3098 3003
3099void ath9k_hw_beaconinit(struct ath_hal *ah, u32 next_beacon, u32 beacon_period) 3004void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
3100{ 3005{
3101 struct ath_hal_5416 *ahp = AH5416(ah);
3102 int flags = 0; 3006 int flags = 0;
3103 3007
3104 ahp->ah_beaconInterval = beacon_period; 3008 ah->beacon_interval = beacon_period;
3105 3009
3106 switch (ah->ah_opmode) { 3010 switch (ah->opmode) {
3107 case NL80211_IFTYPE_STATION: 3011 case NL80211_IFTYPE_STATION:
3108 case NL80211_IFTYPE_MONITOR: 3012 case NL80211_IFTYPE_MONITOR:
3109 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon)); 3013 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
@@ -3116,18 +3020,18 @@ void ath9k_hw_beaconinit(struct ath_hal *ah, u32 next_beacon, u32 beacon_period)
3116 AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY); 3020 AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
3117 REG_WRITE(ah, AR_NEXT_NDP_TIMER, 3021 REG_WRITE(ah, AR_NEXT_NDP_TIMER,
3118 TU_TO_USEC(next_beacon + 3022 TU_TO_USEC(next_beacon +
3119 (ahp->ah_atimWindow ? ahp-> 3023 (ah->atim_window ? ah->
3120 ah_atimWindow : 1))); 3024 atim_window : 1)));
3121 flags |= AR_NDP_TIMER_EN; 3025 flags |= AR_NDP_TIMER_EN;
3122 case NL80211_IFTYPE_AP: 3026 case NL80211_IFTYPE_AP:
3123 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon)); 3027 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
3124 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, 3028 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT,
3125 TU_TO_USEC(next_beacon - 3029 TU_TO_USEC(next_beacon -
3126 ah->ah_config. 3030 ah->config.
3127 dma_beacon_response_time)); 3031 dma_beacon_response_time));
3128 REG_WRITE(ah, AR_NEXT_SWBA, 3032 REG_WRITE(ah, AR_NEXT_SWBA,
3129 TU_TO_USEC(next_beacon - 3033 TU_TO_USEC(next_beacon -
3130 ah->ah_config. 3034 ah->config.
3131 sw_beacon_response_time)); 3035 sw_beacon_response_time));
3132 flags |= 3036 flags |=
3133 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN; 3037 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
@@ -3135,7 +3039,7 @@ void ath9k_hw_beaconinit(struct ath_hal *ah, u32 next_beacon, u32 beacon_period)
3135 default: 3039 default:
3136 DPRINTF(ah->ah_sc, ATH_DBG_BEACON, 3040 DPRINTF(ah->ah_sc, ATH_DBG_BEACON,
3137 "%s: unsupported opmode: %d\n", 3041 "%s: unsupported opmode: %d\n",
3138 __func__, ah->ah_opmode); 3042 __func__, ah->opmode);
3139 return; 3043 return;
3140 break; 3044 break;
3141 } 3045 }
@@ -3154,11 +3058,11 @@ void ath9k_hw_beaconinit(struct ath_hal *ah, u32 next_beacon, u32 beacon_period)
3154 REG_SET_BIT(ah, AR_TIMER_MODE, flags); 3058 REG_SET_BIT(ah, AR_TIMER_MODE, flags);
3155} 3059}
3156 3060
3157void ath9k_hw_set_sta_beacon_timers(struct ath_hal *ah, 3061void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
3158 const struct ath9k_beacon_state *bs) 3062 const struct ath9k_beacon_state *bs)
3159{ 3063{
3160 u32 nextTbtt, beaconintval, dtimperiod, beacontimeout; 3064 u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
3161 struct ath9k_hw_capabilities *pCap = &ah->ah_caps; 3065 struct ath9k_hw_capabilities *pCap = &ah->caps;
3162 3066
3163 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt)); 3067 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt));
3164 3068
@@ -3218,37 +3122,37 @@ void ath9k_hw_set_sta_beacon_timers(struct ath_hal *ah,
3218/* HW Capabilities */ 3122/* HW Capabilities */
3219/*******************/ 3123/*******************/
3220 3124
3221bool ath9k_hw_fill_cap_info(struct ath_hal *ah) 3125bool ath9k_hw_fill_cap_info(struct ath_hw *ah)
3222{ 3126{
3223 struct ath_hal_5416 *ahp = AH5416(ah); 3127 struct ath9k_hw_capabilities *pCap = &ah->caps;
3224 struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
3225 u16 capField = 0, eeval; 3128 u16 capField = 0, eeval;
3226 3129
3227 eeval = ath9k_hw_get_eeprom(ah, EEP_REG_0); 3130 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
3228 3131
3229 ah->ah_currentRD = eeval; 3132 ah->regulatory.current_rd = eeval;
3230 3133
3231 eeval = ath9k_hw_get_eeprom(ah, EEP_REG_1); 3134 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_1);
3232 ah->ah_currentRDExt = eeval; 3135 ah->regulatory.current_rd_ext = eeval;
3233 3136
3234 capField = ath9k_hw_get_eeprom(ah, EEP_OP_CAP); 3137 capField = ah->eep_ops->get_eeprom(ah, EEP_OP_CAP);
3235 3138
3236 if (ah->ah_opmode != NL80211_IFTYPE_AP && 3139 if (ah->opmode != NL80211_IFTYPE_AP &&
3237 ah->ah_subvendorid == AR_SUBVENDOR_ID_NEW_A) { 3140 ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) {
3238 if (ah->ah_currentRD == 0x64 || ah->ah_currentRD == 0x65) 3141 if (ah->regulatory.current_rd == 0x64 ||
3239 ah->ah_currentRD += 5; 3142 ah->regulatory.current_rd == 0x65)
3240 else if (ah->ah_currentRD == 0x41) 3143 ah->regulatory.current_rd += 5;
3241 ah->ah_currentRD = 0x43; 3144 else if (ah->regulatory.current_rd == 0x41)
3145 ah->regulatory.current_rd = 0x43;
3242 DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY, 3146 DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY,
3243 "regdomain mapped to 0x%x\n", ah->ah_currentRD); 3147 "regdomain mapped to 0x%x\n", ah->regulatory.current_rd);
3244 } 3148 }
3245 3149
3246 eeval = ath9k_hw_get_eeprom(ah, EEP_OP_MODE); 3150 eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE);
3247 bitmap_zero(pCap->wireless_modes, ATH9K_MODE_MAX); 3151 bitmap_zero(pCap->wireless_modes, ATH9K_MODE_MAX);
3248 3152
3249 if (eeval & AR5416_OPFLAGS_11A) { 3153 if (eeval & AR5416_OPFLAGS_11A) {
3250 set_bit(ATH9K_MODE_11A, pCap->wireless_modes); 3154 set_bit(ATH9K_MODE_11A, pCap->wireless_modes);
3251 if (ah->ah_config.ht_enable) { 3155 if (ah->config.ht_enable) {
3252 if (!(eeval & AR5416_OPFLAGS_N_5G_HT20)) 3156 if (!(eeval & AR5416_OPFLAGS_N_5G_HT20))
3253 set_bit(ATH9K_MODE_11NA_HT20, 3157 set_bit(ATH9K_MODE_11NA_HT20,
3254 pCap->wireless_modes); 3158 pCap->wireless_modes);
@@ -3264,7 +3168,7 @@ bool ath9k_hw_fill_cap_info(struct ath_hal *ah)
3264 if (eeval & AR5416_OPFLAGS_11G) { 3168 if (eeval & AR5416_OPFLAGS_11G) {
3265 set_bit(ATH9K_MODE_11B, pCap->wireless_modes); 3169 set_bit(ATH9K_MODE_11B, pCap->wireless_modes);
3266 set_bit(ATH9K_MODE_11G, pCap->wireless_modes); 3170 set_bit(ATH9K_MODE_11G, pCap->wireless_modes);
3267 if (ah->ah_config.ht_enable) { 3171 if (ah->config.ht_enable) {
3268 if (!(eeval & AR5416_OPFLAGS_N_2G_HT20)) 3172 if (!(eeval & AR5416_OPFLAGS_N_2G_HT20))
3269 set_bit(ATH9K_MODE_11NG_HT20, 3173 set_bit(ATH9K_MODE_11NG_HT20,
3270 pCap->wireless_modes); 3174 pCap->wireless_modes);
@@ -3277,18 +3181,18 @@ bool ath9k_hw_fill_cap_info(struct ath_hal *ah)
3277 } 3181 }
3278 } 3182 }
3279 3183
3280 pCap->tx_chainmask = ath9k_hw_get_eeprom(ah, EEP_TX_MASK); 3184 pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK);
3281 if ((ah->ah_isPciExpress) 3185 if ((ah->is_pciexpress)
3282 || (eeval & AR5416_OPFLAGS_11A)) { 3186 || (eeval & AR5416_OPFLAGS_11A)) {
3283 pCap->rx_chainmask = 3187 pCap->rx_chainmask =
3284 ath9k_hw_get_eeprom(ah, EEP_RX_MASK); 3188 ah->eep_ops->get_eeprom(ah, EEP_RX_MASK);
3285 } else { 3189 } else {
3286 pCap->rx_chainmask = 3190 pCap->rx_chainmask =
3287 (ath9k_hw_gpio_get(ah, 0)) ? 0x5 : 0x7; 3191 (ath9k_hw_gpio_get(ah, 0)) ? 0x5 : 0x7;
3288 } 3192 }
3289 3193
3290 if (!(AR_SREV_9280(ah) && (ah->ah_macRev == 0))) 3194 if (!(AR_SREV_9280(ah) && (ah->hw_version.macRev == 0)))
3291 ahp->ah_miscMode |= AR_PCU_MIC_NEW_LOC_ENA; 3195 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
3292 3196
3293 pCap->low_2ghz_chan = 2312; 3197 pCap->low_2ghz_chan = 2312;
3294 pCap->high_2ghz_chan = 2732; 3198 pCap->high_2ghz_chan = 2732;
@@ -3306,7 +3210,7 @@ bool ath9k_hw_fill_cap_info(struct ath_hal *ah)
3306 3210
3307 pCap->hw_caps |= ATH9K_HW_CAP_CHAN_SPREAD; 3211 pCap->hw_caps |= ATH9K_HW_CAP_CHAN_SPREAD;
3308 3212
3309 if (ah->ah_config.ht_enable) 3213 if (ah->config.ht_enable)
3310 pCap->hw_caps |= ATH9K_HW_CAP_HT; 3214 pCap->hw_caps |= ATH9K_HW_CAP_HT;
3311 else 3215 else
3312 pCap->hw_caps &= ~ATH9K_HW_CAP_HT; 3216 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
@@ -3332,7 +3236,9 @@ bool ath9k_hw_fill_cap_info(struct ath_hal *ah)
3332 pCap->num_mr_retries = 4; 3236 pCap->num_mr_retries = 4;
3333 pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD; 3237 pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD;
3334 3238
3335 if (AR_SREV_9280_10_OR_LATER(ah)) 3239 if (AR_SREV_9285_10_OR_LATER(ah))
3240 pCap->num_gpio_pins = AR9285_NUM_GPIO;
3241 else if (AR_SREV_9280_10_OR_LATER(ah))
3336 pCap->num_gpio_pins = AR928X_NUM_GPIO; 3242 pCap->num_gpio_pins = AR928X_NUM_GPIO;
3337 else 3243 else
3338 pCap->num_gpio_pins = AR_NUM_GPIO; 3244 pCap->num_gpio_pins = AR_NUM_GPIO;
@@ -3355,22 +3261,22 @@ bool ath9k_hw_fill_cap_info(struct ath_hal *ah)
3355 pCap->hw_caps |= ATH9K_HW_CAP_ENHANCEDPM; 3261 pCap->hw_caps |= ATH9K_HW_CAP_ENHANCEDPM;
3356 3262
3357#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE) 3263#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
3358 ah->ah_rfsilent = ath9k_hw_get_eeprom(ah, EEP_RF_SILENT); 3264 ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT);
3359 if (ah->ah_rfsilent & EEP_RFSILENT_ENABLED) { 3265 if (ah->rfsilent & EEP_RFSILENT_ENABLED) {
3360 ah->ah_rfkill_gpio = 3266 ah->rfkill_gpio =
3361 MS(ah->ah_rfsilent, EEP_RFSILENT_GPIO_SEL); 3267 MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL);
3362 ah->ah_rfkill_polarity = 3268 ah->rfkill_polarity =
3363 MS(ah->ah_rfsilent, EEP_RFSILENT_POLARITY); 3269 MS(ah->rfsilent, EEP_RFSILENT_POLARITY);
3364 3270
3365 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT; 3271 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
3366 } 3272 }
3367#endif 3273#endif
3368 3274
3369 if ((ah->ah_macVersion == AR_SREV_VERSION_5416_PCI) || 3275 if ((ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI) ||
3370 (ah->ah_macVersion == AR_SREV_VERSION_5416_PCIE) || 3276 (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE) ||
3371 (ah->ah_macVersion == AR_SREV_VERSION_9160) || 3277 (ah->hw_version.macVersion == AR_SREV_VERSION_9160) ||
3372 (ah->ah_macVersion == AR_SREV_VERSION_9100) || 3278 (ah->hw_version.macVersion == AR_SREV_VERSION_9100) ||
3373 (ah->ah_macVersion == AR_SREV_VERSION_9280)) 3279 (ah->hw_version.macVersion == AR_SREV_VERSION_9280))
3374 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP; 3280 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
3375 else 3281 else
3376 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP; 3282 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP;
@@ -3380,7 +3286,7 @@ bool ath9k_hw_fill_cap_info(struct ath_hal *ah)
3380 else 3286 else
3381 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS; 3287 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
3382 3288
3383 if (ah->ah_currentRDExt & (1 << REG_EXT_JAPAN_MIDBAND)) { 3289 if (ah->regulatory.current_rd_ext & (1 << REG_EXT_JAPAN_MIDBAND)) {
3384 pCap->reg_cap = 3290 pCap->reg_cap =
3385 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A | 3291 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
3386 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN | 3292 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN |
@@ -3395,18 +3301,23 @@ bool ath9k_hw_fill_cap_info(struct ath_hal *ah)
3395 pCap->reg_cap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND; 3301 pCap->reg_cap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND;
3396 3302
3397 pCap->num_antcfg_5ghz = 3303 pCap->num_antcfg_5ghz =
3398 ath9k_hw_get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_5GHZ); 3304 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_5GHZ);
3399 pCap->num_antcfg_2ghz = 3305 pCap->num_antcfg_2ghz =
3400 ath9k_hw_get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_2GHZ); 3306 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_2GHZ);
3307
3308 if (AR_SREV_9280_10_OR_LATER(ah) && btcoex_enable) {
3309 pCap->hw_caps |= ATH9K_HW_CAP_BT_COEX;
3310 ah->btactive_gpio = 6;
3311 ah->wlanactive_gpio = 5;
3312 }
3401 3313
3402 return true; 3314 return true;
3403} 3315}
3404 3316
3405bool ath9k_hw_getcapability(struct ath_hal *ah, enum ath9k_capability_type type, 3317bool ath9k_hw_getcapability(struct ath_hw *ah, enum ath9k_capability_type type,
3406 u32 capability, u32 *result) 3318 u32 capability, u32 *result)
3407{ 3319{
3408 struct ath_hal_5416 *ahp = AH5416(ah); 3320 const struct ath9k_hw_capabilities *pCap = &ah->caps;
3409 const struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
3410 3321
3411 switch (type) { 3322 switch (type) {
3412 case ATH9K_CAP_CIPHER: 3323 case ATH9K_CAP_CIPHER:
@@ -3426,17 +3337,17 @@ bool ath9k_hw_getcapability(struct ath_hal *ah, enum ath9k_capability_type type,
3426 case 0: 3337 case 0:
3427 return true; 3338 return true;
3428 case 1: 3339 case 1:
3429 return (ahp->ah_staId1Defaults & 3340 return (ah->sta_id1_defaults &
3430 AR_STA_ID1_CRPT_MIC_ENABLE) ? true : 3341 AR_STA_ID1_CRPT_MIC_ENABLE) ? true :
3431 false; 3342 false;
3432 } 3343 }
3433 case ATH9K_CAP_TKIP_SPLIT: 3344 case ATH9K_CAP_TKIP_SPLIT:
3434 return (ahp->ah_miscMode & AR_PCU_MIC_NEW_LOC_ENA) ? 3345 return (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) ?
3435 false : true; 3346 false : true;
3436 case ATH9K_CAP_WME_TKIPMIC: 3347 case ATH9K_CAP_WME_TKIPMIC:
3437 return 0; 3348 return 0;
3438 case ATH9K_CAP_PHYCOUNTERS: 3349 case ATH9K_CAP_PHYCOUNTERS:
3439 return ahp->ah_hasHwPhyCounters ? 0 : -ENXIO; 3350 return ah->has_hw_phycounters ? 0 : -ENXIO;
3440 case ATH9K_CAP_DIVERSITY: 3351 case ATH9K_CAP_DIVERSITY:
3441 return (REG_READ(ah, AR_PHY_CCK_DETECT) & 3352 return (REG_READ(ah, AR_PHY_CCK_DETECT) &
3442 AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV) ? 3353 AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV) ?
@@ -3451,14 +3362,14 @@ bool ath9k_hw_getcapability(struct ath_hal *ah, enum ath9k_capability_type type,
3451 if (REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_ADHOC) { 3362 if (REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_ADHOC) {
3452 return false; 3363 return false;
3453 } else { 3364 } else {
3454 return (ahp->ah_staId1Defaults & 3365 return (ah->sta_id1_defaults &
3455 AR_STA_ID1_MCAST_KSRCH) ? true : 3366 AR_STA_ID1_MCAST_KSRCH) ? true :
3456 false; 3367 false;
3457 } 3368 }
3458 } 3369 }
3459 return false; 3370 return false;
3460 case ATH9K_CAP_TSF_ADJUST: 3371 case ATH9K_CAP_TSF_ADJUST:
3461 return (ahp->ah_miscMode & AR_PCU_TX_ADD_TSF) ? 3372 return (ah->misc_mode & AR_PCU_TX_ADD_TSF) ?
3462 true : false; 3373 true : false;
3463 case ATH9K_CAP_RFSILENT: 3374 case ATH9K_CAP_RFSILENT:
3464 if (capability == 3) 3375 if (capability == 3)
@@ -3474,13 +3385,13 @@ bool ath9k_hw_getcapability(struct ath_hal *ah, enum ath9k_capability_type type,
3474 case 0: 3385 case 0:
3475 return 0; 3386 return 0;
3476 case 1: 3387 case 1:
3477 *result = ah->ah_powerLimit; 3388 *result = ah->regulatory.power_limit;
3478 return 0; 3389 return 0;
3479 case 2: 3390 case 2:
3480 *result = ah->ah_maxPowerLevel; 3391 *result = ah->regulatory.max_power_level;
3481 return 0; 3392 return 0;
3482 case 3: 3393 case 3:
3483 *result = ah->ah_tpScale; 3394 *result = ah->regulatory.tp_scale;
3484 return 0; 3395 return 0;
3485 } 3396 }
3486 return false; 3397 return false;
@@ -3489,19 +3400,18 @@ bool ath9k_hw_getcapability(struct ath_hal *ah, enum ath9k_capability_type type,
3489 } 3400 }
3490} 3401}
3491 3402
3492bool ath9k_hw_setcapability(struct ath_hal *ah, enum ath9k_capability_type type, 3403bool ath9k_hw_setcapability(struct ath_hw *ah, enum ath9k_capability_type type,
3493 u32 capability, u32 setting, int *status) 3404 u32 capability, u32 setting, int *status)
3494{ 3405{
3495 struct ath_hal_5416 *ahp = AH5416(ah);
3496 u32 v; 3406 u32 v;
3497 3407
3498 switch (type) { 3408 switch (type) {
3499 case ATH9K_CAP_TKIP_MIC: 3409 case ATH9K_CAP_TKIP_MIC:
3500 if (setting) 3410 if (setting)
3501 ahp->ah_staId1Defaults |= 3411 ah->sta_id1_defaults |=
3502 AR_STA_ID1_CRPT_MIC_ENABLE; 3412 AR_STA_ID1_CRPT_MIC_ENABLE;
3503 else 3413 else
3504 ahp->ah_staId1Defaults &= 3414 ah->sta_id1_defaults &=
3505 ~AR_STA_ID1_CRPT_MIC_ENABLE; 3415 ~AR_STA_ID1_CRPT_MIC_ENABLE;
3506 return true; 3416 return true;
3507 case ATH9K_CAP_DIVERSITY: 3417 case ATH9K_CAP_DIVERSITY:
@@ -3514,15 +3424,15 @@ bool ath9k_hw_setcapability(struct ath_hal *ah, enum ath9k_capability_type type,
3514 return true; 3424 return true;
3515 case ATH9K_CAP_MCAST_KEYSRCH: 3425 case ATH9K_CAP_MCAST_KEYSRCH:
3516 if (setting) 3426 if (setting)
3517 ahp->ah_staId1Defaults |= AR_STA_ID1_MCAST_KSRCH; 3427 ah->sta_id1_defaults |= AR_STA_ID1_MCAST_KSRCH;
3518 else 3428 else
3519 ahp->ah_staId1Defaults &= ~AR_STA_ID1_MCAST_KSRCH; 3429 ah->sta_id1_defaults &= ~AR_STA_ID1_MCAST_KSRCH;
3520 return true; 3430 return true;
3521 case ATH9K_CAP_TSF_ADJUST: 3431 case ATH9K_CAP_TSF_ADJUST:
3522 if (setting) 3432 if (setting)
3523 ahp->ah_miscMode |= AR_PCU_TX_ADD_TSF; 3433 ah->misc_mode |= AR_PCU_TX_ADD_TSF;
3524 else 3434 else
3525 ahp->ah_miscMode &= ~AR_PCU_TX_ADD_TSF; 3435 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF;
3526 return true; 3436 return true;
3527 default: 3437 default:
3528 return false; 3438 return false;
@@ -3533,7 +3443,7 @@ bool ath9k_hw_setcapability(struct ath_hal *ah, enum ath9k_capability_type type,
3533/* GPIO / RFKILL / Antennae */ 3443/* GPIO / RFKILL / Antennae */
3534/****************************/ 3444/****************************/
3535 3445
3536static void ath9k_hw_gpio_cfg_output_mux(struct ath_hal *ah, 3446static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah,
3537 u32 gpio, u32 type) 3447 u32 gpio, u32 type)
3538{ 3448{
3539 int addr; 3449 int addr;
@@ -3561,11 +3471,11 @@ static void ath9k_hw_gpio_cfg_output_mux(struct ath_hal *ah,
3561 } 3471 }
3562} 3472}
3563 3473
3564void ath9k_hw_cfg_gpio_input(struct ath_hal *ah, u32 gpio) 3474void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio)
3565{ 3475{
3566 u32 gpio_shift; 3476 u32 gpio_shift;
3567 3477
3568 ASSERT(gpio < ah->ah_caps.num_gpio_pins); 3478 ASSERT(gpio < ah->caps.num_gpio_pins);
3569 3479
3570 gpio_shift = gpio << 1; 3480 gpio_shift = gpio << 1;
3571 3481
@@ -3575,22 +3485,23 @@ void ath9k_hw_cfg_gpio_input(struct ath_hal *ah, u32 gpio)
3575 (AR_GPIO_OE_OUT_DRV << gpio_shift)); 3485 (AR_GPIO_OE_OUT_DRV << gpio_shift));
3576} 3486}
3577 3487
3578u32 ath9k_hw_gpio_get(struct ath_hal *ah, u32 gpio) 3488u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
3579{ 3489{
3580 if (gpio >= ah->ah_caps.num_gpio_pins) 3490#define MS_REG_READ(x, y) \
3491 (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y)))
3492
3493 if (gpio >= ah->caps.num_gpio_pins)
3581 return 0xffffffff; 3494 return 0xffffffff;
3582 3495
3583 if (AR_SREV_9280_10_OR_LATER(ah)) { 3496 if (AR_SREV_9285_10_OR_LATER(ah))
3584 return (MS 3497 return MS_REG_READ(AR9285, gpio) != 0;
3585 (REG_READ(ah, AR_GPIO_IN_OUT), 3498 else if (AR_SREV_9280_10_OR_LATER(ah))
3586 AR928X_GPIO_IN_VAL) & AR_GPIO_BIT(gpio)) != 0; 3499 return MS_REG_READ(AR928X, gpio) != 0;
3587 } else { 3500 else
3588 return (MS(REG_READ(ah, AR_GPIO_IN_OUT), AR_GPIO_IN_VAL) & 3501 return MS_REG_READ(AR, gpio) != 0;
3589 AR_GPIO_BIT(gpio)) != 0;
3590 }
3591} 3502}
3592 3503
3593void ath9k_hw_cfg_output(struct ath_hal *ah, u32 gpio, 3504void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
3594 u32 ah_signal_type) 3505 u32 ah_signal_type)
3595{ 3506{
3596 u32 gpio_shift; 3507 u32 gpio_shift;
@@ -3605,14 +3516,14 @@ void ath9k_hw_cfg_output(struct ath_hal *ah, u32 gpio,
3605 (AR_GPIO_OE_OUT_DRV << gpio_shift)); 3516 (AR_GPIO_OE_OUT_DRV << gpio_shift));
3606} 3517}
3607 3518
3608void ath9k_hw_set_gpio(struct ath_hal *ah, u32 gpio, u32 val) 3519void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val)
3609{ 3520{
3610 REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio), 3521 REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
3611 AR_GPIO_BIT(gpio)); 3522 AR_GPIO_BIT(gpio));
3612} 3523}
3613 3524
3614#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE) 3525#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
3615void ath9k_enable_rfkill(struct ath_hal *ah) 3526void ath9k_enable_rfkill(struct ath_hw *ah)
3616{ 3527{
3617 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, 3528 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
3618 AR_GPIO_INPUT_EN_VAL_RFSILENT_BB); 3529 AR_GPIO_INPUT_EN_VAL_RFSILENT_BB);
@@ -3620,50 +3531,28 @@ void ath9k_enable_rfkill(struct ath_hal *ah)
3620 REG_CLR_BIT(ah, AR_GPIO_INPUT_MUX2, 3531 REG_CLR_BIT(ah, AR_GPIO_INPUT_MUX2,
3621 AR_GPIO_INPUT_MUX2_RFSILENT); 3532 AR_GPIO_INPUT_MUX2_RFSILENT);
3622 3533
3623 ath9k_hw_cfg_gpio_input(ah, ah->ah_rfkill_gpio); 3534 ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio);
3624 REG_SET_BIT(ah, AR_PHY_TEST, RFSILENT_BB); 3535 REG_SET_BIT(ah, AR_PHY_TEST, RFSILENT_BB);
3625} 3536}
3626#endif 3537#endif
3627 3538
3628int ath9k_hw_select_antconfig(struct ath_hal *ah, u32 cfg) 3539u32 ath9k_hw_getdefantenna(struct ath_hw *ah)
3629{
3630 struct ath9k_channel *chan = ah->ah_curchan;
3631 const struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
3632 u16 ant_config;
3633 u32 halNumAntConfig;
3634
3635 halNumAntConfig = IS_CHAN_2GHZ(chan) ?
3636 pCap->num_antcfg_2ghz : pCap->num_antcfg_5ghz;
3637
3638 if (cfg < halNumAntConfig) {
3639 if (!ath9k_hw_get_eeprom_antenna_cfg(ah, chan,
3640 cfg, &ant_config)) {
3641 REG_WRITE(ah, AR_PHY_SWITCH_COM, ant_config);
3642 return 0;
3643 }
3644 }
3645
3646 return -EINVAL;
3647}
3648
3649u32 ath9k_hw_getdefantenna(struct ath_hal *ah)
3650{ 3540{
3651 return REG_READ(ah, AR_DEF_ANTENNA) & 0x7; 3541 return REG_READ(ah, AR_DEF_ANTENNA) & 0x7;
3652} 3542}
3653 3543
3654void ath9k_hw_setantenna(struct ath_hal *ah, u32 antenna) 3544void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna)
3655{ 3545{
3656 REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7)); 3546 REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
3657} 3547}
3658 3548
3659bool ath9k_hw_setantennaswitch(struct ath_hal *ah, 3549bool ath9k_hw_setantennaswitch(struct ath_hw *ah,
3660 enum ath9k_ant_setting settings, 3550 enum ath9k_ant_setting settings,
3661 struct ath9k_channel *chan, 3551 struct ath9k_channel *chan,
3662 u8 *tx_chainmask, 3552 u8 *tx_chainmask,
3663 u8 *rx_chainmask, 3553 u8 *rx_chainmask,
3664 u8 *antenna_cfgd) 3554 u8 *antenna_cfgd)
3665{ 3555{
3666 struct ath_hal_5416 *ahp = AH5416(ah);
3667 static u8 tx_chainmask_cfg, rx_chainmask_cfg; 3556 static u8 tx_chainmask_cfg, rx_chainmask_cfg;
3668 3557
3669 if (AR_SREV_9280(ah)) { 3558 if (AR_SREV_9280(ah)) {
@@ -3680,7 +3569,7 @@ bool ath9k_hw_setantennaswitch(struct ath_hal *ah,
3680 *antenna_cfgd = true; 3569 *antenna_cfgd = true;
3681 break; 3570 break;
3682 case ATH9K_ANT_FIXED_B: 3571 case ATH9K_ANT_FIXED_B:
3683 if (ah->ah_caps.tx_chainmask > 3572 if (ah->caps.tx_chainmask >
3684 ATH9K_ANTENNA1_CHAINMASK) { 3573 ATH9K_ANTENNA1_CHAINMASK) {
3685 *tx_chainmask = ATH9K_ANTENNA1_CHAINMASK; 3574 *tx_chainmask = ATH9K_ANTENNA1_CHAINMASK;
3686 } 3575 }
@@ -3696,7 +3585,7 @@ bool ath9k_hw_setantennaswitch(struct ath_hal *ah,
3696 break; 3585 break;
3697 } 3586 }
3698 } else { 3587 } else {
3699 ahp->ah_diversityControl = settings; 3588 ah->diversity_control = settings;
3700 } 3589 }
3701 3590
3702 return true; 3591 return true;
@@ -3706,7 +3595,7 @@ bool ath9k_hw_setantennaswitch(struct ath_hal *ah,
3706/* General Operation */ 3595/* General Operation */
3707/*********************/ 3596/*********************/
3708 3597
3709u32 ath9k_hw_getrxfilter(struct ath_hal *ah) 3598u32 ath9k_hw_getrxfilter(struct ath_hw *ah)
3710{ 3599{
3711 u32 bits = REG_READ(ah, AR_RX_FILTER); 3600 u32 bits = REG_READ(ah, AR_RX_FILTER);
3712 u32 phybits = REG_READ(ah, AR_PHY_ERR); 3601 u32 phybits = REG_READ(ah, AR_PHY_ERR);
@@ -3719,7 +3608,7 @@ u32 ath9k_hw_getrxfilter(struct ath_hal *ah)
3719 return bits; 3608 return bits;
3720} 3609}
3721 3610
3722void ath9k_hw_setrxfilter(struct ath_hal *ah, u32 bits) 3611void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
3723{ 3612{
3724 u32 phybits; 3613 u32 phybits;
3725 3614
@@ -3739,12 +3628,12 @@ void ath9k_hw_setrxfilter(struct ath_hal *ah, u32 bits)
3739 REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_ZLFDMA); 3628 REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_ZLFDMA);
3740} 3629}
3741 3630
3742bool ath9k_hw_phy_disable(struct ath_hal *ah) 3631bool ath9k_hw_phy_disable(struct ath_hw *ah)
3743{ 3632{
3744 return ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM); 3633 return ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM);
3745} 3634}
3746 3635
3747bool ath9k_hw_disable(struct ath_hal *ah) 3636bool ath9k_hw_disable(struct ath_hw *ah)
3748{ 3637{
3749 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) 3638 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
3750 return false; 3639 return false;
@@ -3752,82 +3641,54 @@ bool ath9k_hw_disable(struct ath_hal *ah)
3752 return ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD); 3641 return ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD);
3753} 3642}
3754 3643
3755bool ath9k_hw_set_txpowerlimit(struct ath_hal *ah, u32 limit) 3644bool ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit)
3756{ 3645{
3757 struct ath9k_channel *chan = ah->ah_curchan; 3646 struct ath9k_channel *chan = ah->curchan;
3647 struct ieee80211_channel *channel = chan->chan;
3758 3648
3759 ah->ah_powerLimit = min(limit, (u32) MAX_RATE_POWER); 3649 ah->regulatory.power_limit = min(limit, (u32) MAX_RATE_POWER);
3760 3650
3761 if (ath9k_hw_set_txpower(ah, chan, 3651 if (ah->eep_ops->set_txpower(ah, chan,
3762 ath9k_regd_get_ctl(ah, chan), 3652 ath9k_regd_get_ctl(ah, chan),
3763 ath9k_regd_get_antenna_allowed(ah, chan), 3653 channel->max_antenna_gain * 2,
3764 chan->maxRegTxPower * 2, 3654 channel->max_power * 2,
3765 min((u32) MAX_RATE_POWER, 3655 min((u32) MAX_RATE_POWER,
3766 (u32) ah->ah_powerLimit)) != 0) 3656 (u32) ah->regulatory.power_limit)) != 0)
3767 return false; 3657 return false;
3768 3658
3769 return true; 3659 return true;
3770} 3660}
3771 3661
3772void ath9k_hw_getmac(struct ath_hal *ah, u8 *mac) 3662void ath9k_hw_setmac(struct ath_hw *ah, const u8 *mac)
3773{ 3663{
3774 struct ath_hal_5416 *ahp = AH5416(ah); 3664 memcpy(ah->macaddr, mac, ETH_ALEN);
3775
3776 memcpy(mac, ahp->ah_macaddr, ETH_ALEN);
3777} 3665}
3778 3666
3779bool ath9k_hw_setmac(struct ath_hal *ah, const u8 *mac) 3667void ath9k_hw_setopmode(struct ath_hw *ah)
3780{ 3668{
3781 struct ath_hal_5416 *ahp = AH5416(ah); 3669 ath9k_hw_set_operating_mode(ah, ah->opmode);
3782
3783 memcpy(ahp->ah_macaddr, mac, ETH_ALEN);
3784
3785 return true;
3786}
3787
3788void ath9k_hw_setopmode(struct ath_hal *ah)
3789{
3790 ath9k_hw_set_operating_mode(ah, ah->ah_opmode);
3791} 3670}
3792 3671
3793void ath9k_hw_setmcastfilter(struct ath_hal *ah, u32 filter0, u32 filter1) 3672void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1)
3794{ 3673{
3795 REG_WRITE(ah, AR_MCAST_FIL0, filter0); 3674 REG_WRITE(ah, AR_MCAST_FIL0, filter0);
3796 REG_WRITE(ah, AR_MCAST_FIL1, filter1); 3675 REG_WRITE(ah, AR_MCAST_FIL1, filter1);
3797} 3676}
3798 3677
3799void ath9k_hw_getbssidmask(struct ath_hal *ah, u8 *mask) 3678void ath9k_hw_setbssidmask(struct ath_softc *sc)
3800{ 3679{
3801 struct ath_hal_5416 *ahp = AH5416(ah); 3680 REG_WRITE(sc->sc_ah, AR_BSSMSKL, get_unaligned_le32(sc->bssidmask));
3802 3681 REG_WRITE(sc->sc_ah, AR_BSSMSKU, get_unaligned_le16(sc->bssidmask + 4));
3803 memcpy(mask, ahp->ah_bssidmask, ETH_ALEN);
3804} 3682}
3805 3683
3806bool ath9k_hw_setbssidmask(struct ath_hal *ah, const u8 *mask) 3684void ath9k_hw_write_associd(struct ath_softc *sc)
3807{ 3685{
3808 struct ath_hal_5416 *ahp = AH5416(ah); 3686 REG_WRITE(sc->sc_ah, AR_BSS_ID0, get_unaligned_le32(sc->curbssid));
3809 3687 REG_WRITE(sc->sc_ah, AR_BSS_ID1, get_unaligned_le16(sc->curbssid + 4) |
3810 memcpy(ahp->ah_bssidmask, mask, ETH_ALEN); 3688 ((sc->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
3811
3812 REG_WRITE(ah, AR_BSSMSKL, get_unaligned_le32(ahp->ah_bssidmask));
3813 REG_WRITE(ah, AR_BSSMSKU, get_unaligned_le16(ahp->ah_bssidmask + 4));
3814
3815 return true;
3816}
3817
3818void ath9k_hw_write_associd(struct ath_hal *ah, const u8 *bssid, u16 assocId)
3819{
3820 struct ath_hal_5416 *ahp = AH5416(ah);
3821
3822 memcpy(ahp->ah_bssid, bssid, ETH_ALEN);
3823 ahp->ah_assocId = assocId;
3824
3825 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(ahp->ah_bssid));
3826 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(ahp->ah_bssid + 4) |
3827 ((assocId & 0x3fff) << AR_BSS_ID1_AID_S));
3828} 3689}
3829 3690
3830u64 ath9k_hw_gettsf64(struct ath_hal *ah) 3691u64 ath9k_hw_gettsf64(struct ath_hw *ah)
3831{ 3692{
3832 u64 tsf; 3693 u64 tsf;
3833 3694
@@ -3837,7 +3698,14 @@ u64 ath9k_hw_gettsf64(struct ath_hal *ah)
3837 return tsf; 3698 return tsf;
3838} 3699}
3839 3700
3840void ath9k_hw_reset_tsf(struct ath_hal *ah) 3701void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64)
3702{
3703 REG_WRITE(ah, AR_TSF_L32, 0x00000000);
3704 REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff);
3705 REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff);
3706}
3707
3708void ath9k_hw_reset_tsf(struct ath_hw *ah)
3841{ 3709{
3842 int count; 3710 int count;
3843 3711
@@ -3854,42 +3722,65 @@ void ath9k_hw_reset_tsf(struct ath_hal *ah)
3854 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE); 3722 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
3855} 3723}
3856 3724
3857bool ath9k_hw_set_tsfadjust(struct ath_hal *ah, u32 setting) 3725bool ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting)
3858{ 3726{
3859 struct ath_hal_5416 *ahp = AH5416(ah);
3860
3861 if (setting) 3727 if (setting)
3862 ahp->ah_miscMode |= AR_PCU_TX_ADD_TSF; 3728 ah->misc_mode |= AR_PCU_TX_ADD_TSF;
3863 else 3729 else
3864 ahp->ah_miscMode &= ~AR_PCU_TX_ADD_TSF; 3730 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF;
3865 3731
3866 return true; 3732 return true;
3867} 3733}
3868 3734
3869bool ath9k_hw_setslottime(struct ath_hal *ah, u32 us) 3735bool ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
3870{ 3736{
3871 struct ath_hal_5416 *ahp = AH5416(ah);
3872
3873 if (us < ATH9K_SLOT_TIME_9 || us > ath9k_hw_mac_to_usec(ah, 0xffff)) { 3737 if (us < ATH9K_SLOT_TIME_9 || us > ath9k_hw_mac_to_usec(ah, 0xffff)) {
3874 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad slot time %u\n", us); 3738 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad slot time %u\n", us);
3875 ahp->ah_slottime = (u32) -1; 3739 ah->slottime = (u32) -1;
3876 return false; 3740 return false;
3877 } else { 3741 } else {
3878 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, ath9k_hw_mac_to_clks(ah, us)); 3742 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, ath9k_hw_mac_to_clks(ah, us));
3879 ahp->ah_slottime = us; 3743 ah->slottime = us;
3880 return true; 3744 return true;
3881 } 3745 }
3882} 3746}
3883 3747
3884void ath9k_hw_set11nmac2040(struct ath_hal *ah, enum ath9k_ht_macmode mode) 3748void ath9k_hw_set11nmac2040(struct ath_hw *ah, enum ath9k_ht_macmode mode)
3885{ 3749{
3886 u32 macmode; 3750 u32 macmode;
3887 3751
3888 if (mode == ATH9K_HT_MACMODE_2040 && 3752 if (mode == ATH9K_HT_MACMODE_2040 &&
3889 !ah->ah_config.cwm_ignore_extcca) 3753 !ah->config.cwm_ignore_extcca)
3890 macmode = AR_2040_JOINED_RX_CLEAR; 3754 macmode = AR_2040_JOINED_RX_CLEAR;
3891 else 3755 else
3892 macmode = 0; 3756 macmode = 0;
3893 3757
3894 REG_WRITE(ah, AR_2040_MODE, macmode); 3758 REG_WRITE(ah, AR_2040_MODE, macmode);
3895} 3759}
3760
3761/***************************/
3762/* Bluetooth Coexistence */
3763/***************************/
3764
3765void ath9k_hw_btcoex_enable(struct ath_hw *ah)
3766{
3767 /* connect bt_active to baseband */
3768 REG_CLR_BIT(ah, AR_GPIO_INPUT_EN_VAL,
3769 (AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_DEF |
3770 AR_GPIO_INPUT_EN_VAL_BT_FREQUENCY_DEF));
3771
3772 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
3773 AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB);
3774
3775 /* Set input mux for bt_active to gpio pin */
3776 REG_RMW_FIELD(ah, AR_GPIO_INPUT_MUX1,
3777 AR_GPIO_INPUT_MUX1_BT_ACTIVE,
3778 ah->btactive_gpio);
3779
3780 /* Configure the desired gpio port for input */
3781 ath9k_hw_cfg_gpio_input(ah, ah->btactive_gpio);
3782
3783 /* Configure the desired GPIO port for TX_FRAME output */
3784 ath9k_hw_cfg_output(ah, ah->wlanactive_gpio,
3785 AR_GPIO_OUTPUT_MUX_AS_TX_FRAME);
3786}
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-18 21:39:57 -0400