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path: root/drivers/net/wireless/ath9k/ani.c
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Diffstat (limited to 'drivers/net/wireless/ath9k/ani.c')
-rw-r--r--drivers/net/wireless/ath9k/ani.c281
1 files changed, 127 insertions, 154 deletions
diff --git a/drivers/net/wireless/ath9k/ani.c b/drivers/net/wireless/ath9k/ani.c
index 251e2d9a7a4..d4df7e611df 100644
--- a/drivers/net/wireless/ath9k/ani.c
+++ b/drivers/net/wireless/ath9k/ani.c
@@ -14,23 +14,19 @@
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */ 15 */
16 16
17#include "core.h" 17#include "ath9k.h"
18#include "hw.h"
19#include "reg.h"
20#include "phy.h"
21 18
22static int ath9k_hw_get_ani_channel_idx(struct ath_hal *ah, 19static int ath9k_hw_get_ani_channel_idx(struct ath_hw *ah,
23 struct ath9k_channel *chan) 20 struct ath9k_channel *chan)
24{ 21{
25 struct ath_hal_5416 *ahp = AH5416(ah);
26 int i; 22 int i;
27 23
28 for (i = 0; i < ARRAY_SIZE(ahp->ah_ani); i++) { 24 for (i = 0; i < ARRAY_SIZE(ah->ani); i++) {
29 if (ahp->ah_ani[i].c.channel == chan->channel) 25 if (ah->ani[i].c &&
26 ah->ani[i].c->channel == chan->channel)
30 return i; 27 return i;
31 if (ahp->ah_ani[i].c.channel == 0) { 28 if (ah->ani[i].c == NULL) {
32 ahp->ah_ani[i].c.channel = chan->channel; 29 ah->ani[i].c = chan;
33 ahp->ah_ani[i].c.channelFlags = chan->channelFlags;
34 return i; 30 return i;
35 } 31 }
36 } 32 }
@@ -41,41 +37,40 @@ static int ath9k_hw_get_ani_channel_idx(struct ath_hal *ah,
41 return 0; 37 return 0;
42} 38}
43 39
44static bool ath9k_hw_ani_control(struct ath_hal *ah, 40static bool ath9k_hw_ani_control(struct ath_hw *ah,
45 enum ath9k_ani_cmd cmd, int param) 41 enum ath9k_ani_cmd cmd, int param)
46{ 42{
47 struct ath_hal_5416 *ahp = AH5416(ah); 43 struct ar5416AniState *aniState = ah->curani;
48 struct ar5416AniState *aniState = ahp->ah_curani;
49 44
50 switch (cmd & ahp->ah_ani_function) { 45 switch (cmd & ah->ani_function) {
51 case ATH9K_ANI_NOISE_IMMUNITY_LEVEL:{ 46 case ATH9K_ANI_NOISE_IMMUNITY_LEVEL:{
52 u32 level = param; 47 u32 level = param;
53 48
54 if (level >= ARRAY_SIZE(ahp->ah_totalSizeDesired)) { 49 if (level >= ARRAY_SIZE(ah->totalSizeDesired)) {
55 DPRINTF(ah->ah_sc, ATH_DBG_ANI, 50 DPRINTF(ah->ah_sc, ATH_DBG_ANI,
56 "level out of range (%u > %u)\n", 51 "level out of range (%u > %u)\n",
57 level, 52 level,
58 (unsigned)ARRAY_SIZE(ahp->ah_totalSizeDesired)); 53 (unsigned)ARRAY_SIZE(ah->totalSizeDesired));
59 return false; 54 return false;
60 } 55 }
61 56
62 REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ, 57 REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ,
63 AR_PHY_DESIRED_SZ_TOT_DES, 58 AR_PHY_DESIRED_SZ_TOT_DES,
64 ahp->ah_totalSizeDesired[level]); 59 ah->totalSizeDesired[level]);
65 REG_RMW_FIELD(ah, AR_PHY_AGC_CTL1, 60 REG_RMW_FIELD(ah, AR_PHY_AGC_CTL1,
66 AR_PHY_AGC_CTL1_COARSE_LOW, 61 AR_PHY_AGC_CTL1_COARSE_LOW,
67 ahp->ah_coarseLow[level]); 62 ah->coarse_low[level]);
68 REG_RMW_FIELD(ah, AR_PHY_AGC_CTL1, 63 REG_RMW_FIELD(ah, AR_PHY_AGC_CTL1,
69 AR_PHY_AGC_CTL1_COARSE_HIGH, 64 AR_PHY_AGC_CTL1_COARSE_HIGH,
70 ahp->ah_coarseHigh[level]); 65 ah->coarse_high[level]);
71 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG, 66 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
72 AR_PHY_FIND_SIG_FIRPWR, 67 AR_PHY_FIND_SIG_FIRPWR,
73 ahp->ah_firpwr[level]); 68 ah->firpwr[level]);
74 69
75 if (level > aniState->noiseImmunityLevel) 70 if (level > aniState->noiseImmunityLevel)
76 ahp->ah_stats.ast_ani_niup++; 71 ah->stats.ast_ani_niup++;
77 else if (level < aniState->noiseImmunityLevel) 72 else if (level < aniState->noiseImmunityLevel)
78 ahp->ah_stats.ast_ani_nidown++; 73 ah->stats.ast_ani_nidown++;
79 aniState->noiseImmunityLevel = level; 74 aniState->noiseImmunityLevel = level;
80 break; 75 break;
81 } 76 }
@@ -129,9 +124,9 @@ static bool ath9k_hw_ani_control(struct ath_hal *ah,
129 124
130 if (!on != aniState->ofdmWeakSigDetectOff) { 125 if (!on != aniState->ofdmWeakSigDetectOff) {
131 if (on) 126 if (on)
132 ahp->ah_stats.ast_ani_ofdmon++; 127 ah->stats.ast_ani_ofdmon++;
133 else 128 else
134 ahp->ah_stats.ast_ani_ofdmoff++; 129 ah->stats.ast_ani_ofdmoff++;
135 aniState->ofdmWeakSigDetectOff = !on; 130 aniState->ofdmWeakSigDetectOff = !on;
136 } 131 }
137 break; 132 break;
@@ -145,9 +140,9 @@ static bool ath9k_hw_ani_control(struct ath_hal *ah,
145 weakSigThrCck[high]); 140 weakSigThrCck[high]);
146 if (high != aniState->cckWeakSigThreshold) { 141 if (high != aniState->cckWeakSigThreshold) {
147 if (high) 142 if (high)
148 ahp->ah_stats.ast_ani_cckhigh++; 143 ah->stats.ast_ani_cckhigh++;
149 else 144 else
150 ahp->ah_stats.ast_ani_ccklow++; 145 ah->stats.ast_ani_ccklow++;
151 aniState->cckWeakSigThreshold = high; 146 aniState->cckWeakSigThreshold = high;
152 } 147 }
153 break; 148 break;
@@ -167,9 +162,9 @@ static bool ath9k_hw_ani_control(struct ath_hal *ah,
167 AR_PHY_FIND_SIG_FIRSTEP, 162 AR_PHY_FIND_SIG_FIRSTEP,
168 firstep[level]); 163 firstep[level]);
169 if (level > aniState->firstepLevel) 164 if (level > aniState->firstepLevel)
170 ahp->ah_stats.ast_ani_stepup++; 165 ah->stats.ast_ani_stepup++;
171 else if (level < aniState->firstepLevel) 166 else if (level < aniState->firstepLevel)
172 ahp->ah_stats.ast_ani_stepdown++; 167 ah->stats.ast_ani_stepdown++;
173 aniState->firstepLevel = level; 168 aniState->firstepLevel = level;
174 break; 169 break;
175 } 170 }
@@ -190,9 +185,9 @@ static bool ath9k_hw_ani_control(struct ath_hal *ah,
190 AR_PHY_TIMING5_CYCPWR_THR1, 185 AR_PHY_TIMING5_CYCPWR_THR1,
191 cycpwrThr1[level]); 186 cycpwrThr1[level]);
192 if (level > aniState->spurImmunityLevel) 187 if (level > aniState->spurImmunityLevel)
193 ahp->ah_stats.ast_ani_spurup++; 188 ah->stats.ast_ani_spurup++;
194 else if (level < aniState->spurImmunityLevel) 189 else if (level < aniState->spurImmunityLevel)
195 ahp->ah_stats.ast_ani_spurdown++; 190 ah->stats.ast_ani_spurdown++;
196 aniState->spurImmunityLevel = level; 191 aniState->spurImmunityLevel = level;
197 break; 192 break;
198 } 193 }
@@ -223,7 +218,7 @@ static bool ath9k_hw_ani_control(struct ath_hal *ah,
223 return true; 218 return true;
224} 219}
225 220
226static void ath9k_hw_update_mibstats(struct ath_hal *ah, 221static void ath9k_hw_update_mibstats(struct ath_hw *ah,
227 struct ath9k_mib_stats *stats) 222 struct ath9k_mib_stats *stats)
228{ 223{
229 stats->ackrcv_bad += REG_READ(ah, AR_ACK_FAIL); 224 stats->ackrcv_bad += REG_READ(ah, AR_ACK_FAIL);
@@ -233,18 +228,17 @@ static void ath9k_hw_update_mibstats(struct ath_hal *ah,
233 stats->beacons += REG_READ(ah, AR_BEACON_CNT); 228 stats->beacons += REG_READ(ah, AR_BEACON_CNT);
234} 229}
235 230
236static void ath9k_ani_restart(struct ath_hal *ah) 231static void ath9k_ani_restart(struct ath_hw *ah)
237{ 232{
238 struct ath_hal_5416 *ahp = AH5416(ah);
239 struct ar5416AniState *aniState; 233 struct ar5416AniState *aniState;
240 234
241 if (!DO_ANI(ah)) 235 if (!DO_ANI(ah))
242 return; 236 return;
243 237
244 aniState = ahp->ah_curani; 238 aniState = ah->curani;
245 239
246 aniState->listenTime = 0; 240 aniState->listenTime = 0;
247 if (ahp->ah_hasHwPhyCounters) { 241 if (ah->has_hw_phycounters) {
248 if (aniState->ofdmTrigHigh > AR_PHY_COUNTMAX) { 242 if (aniState->ofdmTrigHigh > AR_PHY_COUNTMAX) {
249 aniState->ofdmPhyErrBase = 0; 243 aniState->ofdmPhyErrBase = 0;
250 DPRINTF(ah->ah_sc, ATH_DBG_ANI, 244 DPRINTF(ah->ah_sc, ATH_DBG_ANI,
@@ -270,24 +264,22 @@ static void ath9k_ani_restart(struct ath_hal *ah)
270 REG_WRITE(ah, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING); 264 REG_WRITE(ah, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING);
271 REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING); 265 REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING);
272 266
273 ath9k_hw_update_mibstats(ah, &ahp->ah_mibStats); 267 ath9k_hw_update_mibstats(ah, &ah->ah_mibStats);
274 } 268 }
275 aniState->ofdmPhyErrCount = 0; 269 aniState->ofdmPhyErrCount = 0;
276 aniState->cckPhyErrCount = 0; 270 aniState->cckPhyErrCount = 0;
277} 271}
278 272
279static void ath9k_hw_ani_ofdm_err_trigger(struct ath_hal *ah) 273static void ath9k_hw_ani_ofdm_err_trigger(struct ath_hw *ah)
280{ 274{
281 struct ath_hal_5416 *ahp = AH5416(ah); 275 struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
282 struct ath9k_channel *chan = ah->ah_curchan;
283 struct ar5416AniState *aniState; 276 struct ar5416AniState *aniState;
284 enum wireless_mode mode;
285 int32_t rssi; 277 int32_t rssi;
286 278
287 if (!DO_ANI(ah)) 279 if (!DO_ANI(ah))
288 return; 280 return;
289 281
290 aniState = ahp->ah_curani; 282 aniState = ah->curani;
291 283
292 if (aniState->noiseImmunityLevel < HAL_NOISE_IMMUNE_MAX) { 284 if (aniState->noiseImmunityLevel < HAL_NOISE_IMMUNE_MAX) {
293 if (ath9k_hw_ani_control(ah, ATH9K_ANI_NOISE_IMMUNITY_LEVEL, 285 if (ath9k_hw_ani_control(ah, ATH9K_ANI_NOISE_IMMUNITY_LEVEL,
@@ -303,14 +295,14 @@ static void ath9k_hw_ani_ofdm_err_trigger(struct ath_hal *ah)
303 } 295 }
304 } 296 }
305 297
306 if (ah->ah_opmode == NL80211_IFTYPE_AP) { 298 if (ah->opmode == NL80211_IFTYPE_AP) {
307 if (aniState->firstepLevel < HAL_FIRST_STEP_MAX) { 299 if (aniState->firstepLevel < HAL_FIRST_STEP_MAX) {
308 ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL, 300 ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL,
309 aniState->firstepLevel + 1); 301 aniState->firstepLevel + 1);
310 } 302 }
311 return; 303 return;
312 } 304 }
313 rssi = BEACON_RSSI(ahp); 305 rssi = BEACON_RSSI(ah);
314 if (rssi > aniState->rssiThrHigh) { 306 if (rssi > aniState->rssiThrHigh) {
315 if (!aniState->ofdmWeakSigDetectOff) { 307 if (!aniState->ofdmWeakSigDetectOff) {
316 if (ath9k_hw_ani_control(ah, 308 if (ath9k_hw_ani_control(ah,
@@ -336,8 +328,7 @@ static void ath9k_hw_ani_ofdm_err_trigger(struct ath_hal *ah)
336 aniState->firstepLevel + 1); 328 aniState->firstepLevel + 1);
337 return; 329 return;
338 } else { 330 } else {
339 mode = ath9k_hw_chan2wmode(ah, chan); 331 if (conf->channel->band == IEEE80211_BAND_2GHZ) {
340 if (mode == ATH9K_MODE_11G || mode == ATH9K_MODE_11B) {
341 if (!aniState->ofdmWeakSigDetectOff) 332 if (!aniState->ofdmWeakSigDetectOff)
342 ath9k_hw_ani_control(ah, 333 ath9k_hw_ani_control(ah,
343 ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION, 334 ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION,
@@ -350,39 +341,36 @@ static void ath9k_hw_ani_ofdm_err_trigger(struct ath_hal *ah)
350 } 341 }
351} 342}
352 343
353static void ath9k_hw_ani_cck_err_trigger(struct ath_hal *ah) 344static void ath9k_hw_ani_cck_err_trigger(struct ath_hw *ah)
354{ 345{
355 struct ath_hal_5416 *ahp = AH5416(ah); 346 struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
356 struct ath9k_channel *chan = ah->ah_curchan;
357 struct ar5416AniState *aniState; 347 struct ar5416AniState *aniState;
358 enum wireless_mode mode;
359 int32_t rssi; 348 int32_t rssi;
360 349
361 if (!DO_ANI(ah)) 350 if (!DO_ANI(ah))
362 return; 351 return;
363 352
364 aniState = ahp->ah_curani; 353 aniState = ah->curani;
365 if (aniState->noiseImmunityLevel < HAL_NOISE_IMMUNE_MAX) { 354 if (aniState->noiseImmunityLevel < HAL_NOISE_IMMUNE_MAX) {
366 if (ath9k_hw_ani_control(ah, ATH9K_ANI_NOISE_IMMUNITY_LEVEL, 355 if (ath9k_hw_ani_control(ah, ATH9K_ANI_NOISE_IMMUNITY_LEVEL,
367 aniState->noiseImmunityLevel + 1)) { 356 aniState->noiseImmunityLevel + 1)) {
368 return; 357 return;
369 } 358 }
370 } 359 }
371 if (ah->ah_opmode == NL80211_IFTYPE_AP) { 360 if (ah->opmode == NL80211_IFTYPE_AP) {
372 if (aniState->firstepLevel < HAL_FIRST_STEP_MAX) { 361 if (aniState->firstepLevel < HAL_FIRST_STEP_MAX) {
373 ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL, 362 ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL,
374 aniState->firstepLevel + 1); 363 aniState->firstepLevel + 1);
375 } 364 }
376 return; 365 return;
377 } 366 }
378 rssi = BEACON_RSSI(ahp); 367 rssi = BEACON_RSSI(ah);
379 if (rssi > aniState->rssiThrLow) { 368 if (rssi > aniState->rssiThrLow) {
380 if (aniState->firstepLevel < HAL_FIRST_STEP_MAX) 369 if (aniState->firstepLevel < HAL_FIRST_STEP_MAX)
381 ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL, 370 ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL,
382 aniState->firstepLevel + 1); 371 aniState->firstepLevel + 1);
383 } else { 372 } else {
384 mode = ath9k_hw_chan2wmode(ah, chan); 373 if (conf->channel->band == IEEE80211_BAND_2GHZ) {
385 if (mode == ATH9K_MODE_11G || mode == ATH9K_MODE_11B) {
386 if (aniState->firstepLevel > 0) 374 if (aniState->firstepLevel > 0)
387 ath9k_hw_ani_control(ah, 375 ath9k_hw_ani_control(ah,
388 ATH9K_ANI_FIRSTEP_LEVEL, 0); 376 ATH9K_ANI_FIRSTEP_LEVEL, 0);
@@ -390,22 +378,21 @@ static void ath9k_hw_ani_cck_err_trigger(struct ath_hal *ah)
390 } 378 }
391} 379}
392 380
393static void ath9k_hw_ani_lower_immunity(struct ath_hal *ah) 381static void ath9k_hw_ani_lower_immunity(struct ath_hw *ah)
394{ 382{
395 struct ath_hal_5416 *ahp = AH5416(ah);
396 struct ar5416AniState *aniState; 383 struct ar5416AniState *aniState;
397 int32_t rssi; 384 int32_t rssi;
398 385
399 aniState = ahp->ah_curani; 386 aniState = ah->curani;
400 387
401 if (ah->ah_opmode == NL80211_IFTYPE_AP) { 388 if (ah->opmode == NL80211_IFTYPE_AP) {
402 if (aniState->firstepLevel > 0) { 389 if (aniState->firstepLevel > 0) {
403 if (ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL, 390 if (ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL,
404 aniState->firstepLevel - 1)) 391 aniState->firstepLevel - 1))
405 return; 392 return;
406 } 393 }
407 } else { 394 } else {
408 rssi = BEACON_RSSI(ahp); 395 rssi = BEACON_RSSI(ah);
409 if (rssi > aniState->rssiThrHigh) { 396 if (rssi > aniState->rssiThrHigh) {
410 /* XXX: Handle me */ 397 /* XXX: Handle me */
411 } else if (rssi > aniState->rssiThrLow) { 398 } else if (rssi > aniState->rssiThrLow) {
@@ -444,9 +431,8 @@ static void ath9k_hw_ani_lower_immunity(struct ath_hal *ah)
444 } 431 }
445} 432}
446 433
447static int32_t ath9k_hw_ani_get_listen_time(struct ath_hal *ah) 434static int32_t ath9k_hw_ani_get_listen_time(struct ath_hw *ah)
448{ 435{
449 struct ath_hal_5416 *ahp = AH5416(ah);
450 struct ar5416AniState *aniState; 436 struct ar5416AniState *aniState;
451 u32 txFrameCount, rxFrameCount, cycleCount; 437 u32 txFrameCount, rxFrameCount, cycleCount;
452 int32_t listenTime; 438 int32_t listenTime;
@@ -455,11 +441,11 @@ static int32_t ath9k_hw_ani_get_listen_time(struct ath_hal *ah)
455 rxFrameCount = REG_READ(ah, AR_RFCNT); 441 rxFrameCount = REG_READ(ah, AR_RFCNT);
456 cycleCount = REG_READ(ah, AR_CCCNT); 442 cycleCount = REG_READ(ah, AR_CCCNT);
457 443
458 aniState = ahp->ah_curani; 444 aniState = ah->curani;
459 if (aniState->cycleCount == 0 || aniState->cycleCount > cycleCount) { 445 if (aniState->cycleCount == 0 || aniState->cycleCount > cycleCount) {
460 446
461 listenTime = 0; 447 listenTime = 0;
462 ahp->ah_stats.ast_ani_lzero++; 448 ah->stats.ast_ani_lzero++;
463 } else { 449 } else {
464 int32_t ccdelta = cycleCount - aniState->cycleCount; 450 int32_t ccdelta = cycleCount - aniState->cycleCount;
465 int32_t rfdelta = rxFrameCount - aniState->rxFrameCount; 451 int32_t rfdelta = rxFrameCount - aniState->rxFrameCount;
@@ -473,25 +459,24 @@ static int32_t ath9k_hw_ani_get_listen_time(struct ath_hal *ah)
473 return listenTime; 459 return listenTime;
474} 460}
475 461
476void ath9k_ani_reset(struct ath_hal *ah) 462void ath9k_ani_reset(struct ath_hw *ah)
477{ 463{
478 struct ath_hal_5416 *ahp = AH5416(ah);
479 struct ar5416AniState *aniState; 464 struct ar5416AniState *aniState;
480 struct ath9k_channel *chan = ah->ah_curchan; 465 struct ath9k_channel *chan = ah->curchan;
481 int index; 466 int index;
482 467
483 if (!DO_ANI(ah)) 468 if (!DO_ANI(ah))
484 return; 469 return;
485 470
486 index = ath9k_hw_get_ani_channel_idx(ah, chan); 471 index = ath9k_hw_get_ani_channel_idx(ah, chan);
487 aniState = &ahp->ah_ani[index]; 472 aniState = &ah->ani[index];
488 ahp->ah_curani = aniState; 473 ah->curani = aniState;
489 474
490 if (DO_ANI(ah) && ah->ah_opmode != NL80211_IFTYPE_STATION 475 if (DO_ANI(ah) && ah->opmode != NL80211_IFTYPE_STATION
491 && ah->ah_opmode != NL80211_IFTYPE_ADHOC) { 476 && ah->opmode != NL80211_IFTYPE_ADHOC) {
492 DPRINTF(ah->ah_sc, ATH_DBG_ANI, 477 DPRINTF(ah->ah_sc, ATH_DBG_ANI,
493 "Reset ANI state opmode %u\n", ah->ah_opmode); 478 "Reset ANI state opmode %u\n", ah->opmode);
494 ahp->ah_stats.ast_ani_reset++; 479 ah->stats.ast_ani_reset++;
495 480
496 ath9k_hw_ani_control(ah, ATH9K_ANI_NOISE_IMMUNITY_LEVEL, 0); 481 ath9k_hw_ani_control(ah, ATH9K_ANI_NOISE_IMMUNITY_LEVEL, 0);
497 ath9k_hw_ani_control(ah, ATH9K_ANI_SPUR_IMMUNITY_LEVEL, 0); 482 ath9k_hw_ani_control(ah, ATH9K_ANI_SPUR_IMMUNITY_LEVEL, 0);
@@ -504,15 +489,15 @@ void ath9k_ani_reset(struct ath_hal *ah)
504 ath9k_hw_setrxfilter(ah, ath9k_hw_getrxfilter(ah) | 489 ath9k_hw_setrxfilter(ah, ath9k_hw_getrxfilter(ah) |
505 ATH9K_RX_FILTER_PHYERR); 490 ATH9K_RX_FILTER_PHYERR);
506 491
507 if (ah->ah_opmode == NL80211_IFTYPE_AP) { 492 if (ah->opmode == NL80211_IFTYPE_AP) {
508 ahp->ah_curani->ofdmTrigHigh = 493 ah->curani->ofdmTrigHigh =
509 ah->ah_config.ofdm_trig_high; 494 ah->config.ofdm_trig_high;
510 ahp->ah_curani->ofdmTrigLow = 495 ah->curani->ofdmTrigLow =
511 ah->ah_config.ofdm_trig_low; 496 ah->config.ofdm_trig_low;
512 ahp->ah_curani->cckTrigHigh = 497 ah->curani->cckTrigHigh =
513 ah->ah_config.cck_trig_high; 498 ah->config.cck_trig_high;
514 ahp->ah_curani->cckTrigLow = 499 ah->curani->cckTrigLow =
515 ah->ah_config.cck_trig_low; 500 ah->config.cck_trig_low;
516 } 501 }
517 ath9k_ani_restart(ah); 502 ath9k_ani_restart(ah);
518 return; 503 return;
@@ -533,7 +518,7 @@ void ath9k_ani_reset(struct ath_hal *ah)
533 if (aniState->firstepLevel != 0) 518 if (aniState->firstepLevel != 0)
534 ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL, 519 ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL,
535 aniState->firstepLevel); 520 aniState->firstepLevel);
536 if (ahp->ah_hasHwPhyCounters) { 521 if (ah->has_hw_phycounters) {
537 ath9k_hw_setrxfilter(ah, ath9k_hw_getrxfilter(ah) & 522 ath9k_hw_setrxfilter(ah, ath9k_hw_getrxfilter(ah) &
538 ~ATH9K_RX_FILTER_PHYERR); 523 ~ATH9K_RX_FILTER_PHYERR);
539 ath9k_ani_restart(ah); 524 ath9k_ani_restart(ah);
@@ -547,31 +532,33 @@ void ath9k_ani_reset(struct ath_hal *ah)
547 } 532 }
548} 533}
549 534
550void ath9k_hw_ani_monitor(struct ath_hal *ah, 535void ath9k_hw_ani_monitor(struct ath_hw *ah,
551 const struct ath9k_node_stats *stats, 536 const struct ath9k_node_stats *stats,
552 struct ath9k_channel *chan) 537 struct ath9k_channel *chan)
553{ 538{
554 struct ath_hal_5416 *ahp = AH5416(ah);
555 struct ar5416AniState *aniState; 539 struct ar5416AniState *aniState;
556 int32_t listenTime; 540 int32_t listenTime;
557 541
558 aniState = ahp->ah_curani; 542 if (!DO_ANI(ah))
559 ahp->ah_stats.ast_nodestats = *stats; 543 return;
544
545 aniState = ah->curani;
546 ah->stats.ast_nodestats = *stats;
560 547
561 listenTime = ath9k_hw_ani_get_listen_time(ah); 548 listenTime = ath9k_hw_ani_get_listen_time(ah);
562 if (listenTime < 0) { 549 if (listenTime < 0) {
563 ahp->ah_stats.ast_ani_lneg++; 550 ah->stats.ast_ani_lneg++;
564 ath9k_ani_restart(ah); 551 ath9k_ani_restart(ah);
565 return; 552 return;
566 } 553 }
567 554
568 aniState->listenTime += listenTime; 555 aniState->listenTime += listenTime;
569 556
570 if (ahp->ah_hasHwPhyCounters) { 557 if (ah->has_hw_phycounters) {
571 u32 phyCnt1, phyCnt2; 558 u32 phyCnt1, phyCnt2;
572 u32 ofdmPhyErrCnt, cckPhyErrCnt; 559 u32 ofdmPhyErrCnt, cckPhyErrCnt;
573 560
574 ath9k_hw_update_mibstats(ah, &ahp->ah_mibStats); 561 ath9k_hw_update_mibstats(ah, &ah->ah_mibStats);
575 562
576 phyCnt1 = REG_READ(ah, AR_PHY_ERR_1); 563 phyCnt1 = REG_READ(ah, AR_PHY_ERR_1);
577 phyCnt2 = REG_READ(ah, AR_PHY_ERR_2); 564 phyCnt2 = REG_READ(ah, AR_PHY_ERR_2);
@@ -604,27 +591,24 @@ void ath9k_hw_ani_monitor(struct ath_hal *ah,
604 } 591 }
605 592
606 ofdmPhyErrCnt = phyCnt1 - aniState->ofdmPhyErrBase; 593 ofdmPhyErrCnt = phyCnt1 - aniState->ofdmPhyErrBase;
607 ahp->ah_stats.ast_ani_ofdmerrs += 594 ah->stats.ast_ani_ofdmerrs +=
608 ofdmPhyErrCnt - aniState->ofdmPhyErrCount; 595 ofdmPhyErrCnt - aniState->ofdmPhyErrCount;
609 aniState->ofdmPhyErrCount = ofdmPhyErrCnt; 596 aniState->ofdmPhyErrCount = ofdmPhyErrCnt;
610 597
611 cckPhyErrCnt = phyCnt2 - aniState->cckPhyErrBase; 598 cckPhyErrCnt = phyCnt2 - aniState->cckPhyErrBase;
612 ahp->ah_stats.ast_ani_cckerrs += 599 ah->stats.ast_ani_cckerrs +=
613 cckPhyErrCnt - aniState->cckPhyErrCount; 600 cckPhyErrCnt - aniState->cckPhyErrCount;
614 aniState->cckPhyErrCount = cckPhyErrCnt; 601 aniState->cckPhyErrCount = cckPhyErrCnt;
615 } 602 }
616 603
617 if (!DO_ANI(ah)) 604 if (aniState->listenTime > 5 * ah->aniperiod) {
618 return;
619
620 if (aniState->listenTime > 5 * ahp->ah_aniPeriod) {
621 if (aniState->ofdmPhyErrCount <= aniState->listenTime * 605 if (aniState->ofdmPhyErrCount <= aniState->listenTime *
622 aniState->ofdmTrigLow / 1000 && 606 aniState->ofdmTrigLow / 1000 &&
623 aniState->cckPhyErrCount <= aniState->listenTime * 607 aniState->cckPhyErrCount <= aniState->listenTime *
624 aniState->cckTrigLow / 1000) 608 aniState->cckTrigLow / 1000)
625 ath9k_hw_ani_lower_immunity(ah); 609 ath9k_hw_ani_lower_immunity(ah);
626 ath9k_ani_restart(ah); 610 ath9k_ani_restart(ah);
627 } else if (aniState->listenTime > ahp->ah_aniPeriod) { 611 } else if (aniState->listenTime > ah->aniperiod) {
628 if (aniState->ofdmPhyErrCount > aniState->listenTime * 612 if (aniState->ofdmPhyErrCount > aniState->listenTime *
629 aniState->ofdmTrigHigh / 1000) { 613 aniState->ofdmTrigHigh / 1000) {
630 ath9k_hw_ani_ofdm_err_trigger(ah); 614 ath9k_hw_ani_ofdm_err_trigger(ah);
@@ -638,20 +622,16 @@ void ath9k_hw_ani_monitor(struct ath_hal *ah,
638 } 622 }
639} 623}
640 624
641bool ath9k_hw_phycounters(struct ath_hal *ah) 625bool ath9k_hw_phycounters(struct ath_hw *ah)
642{ 626{
643 struct ath_hal_5416 *ahp = AH5416(ah); 627 return ah->has_hw_phycounters ? true : false;
644
645 return ahp->ah_hasHwPhyCounters ? true : false;
646} 628}
647 629
648void ath9k_enable_mib_counters(struct ath_hal *ah) 630void ath9k_enable_mib_counters(struct ath_hw *ah)
649{ 631{
650 struct ath_hal_5416 *ahp = AH5416(ah);
651
652 DPRINTF(ah->ah_sc, ATH_DBG_ANI, "Enable MIB counters\n"); 632 DPRINTF(ah->ah_sc, ATH_DBG_ANI, "Enable MIB counters\n");
653 633
654 ath9k_hw_update_mibstats(ah, &ahp->ah_mibStats); 634 ath9k_hw_update_mibstats(ah, &ah->ah_mibStats);
655 635
656 REG_WRITE(ah, AR_FILT_OFDM, 0); 636 REG_WRITE(ah, AR_FILT_OFDM, 0);
657 REG_WRITE(ah, AR_FILT_CCK, 0); 637 REG_WRITE(ah, AR_FILT_CCK, 0);
@@ -662,21 +642,19 @@ void ath9k_enable_mib_counters(struct ath_hal *ah)
662 REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING); 642 REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING);
663} 643}
664 644
665void ath9k_hw_disable_mib_counters(struct ath_hal *ah) 645void ath9k_hw_disable_mib_counters(struct ath_hw *ah)
666{ 646{
667 struct ath_hal_5416 *ahp = AH5416(ah);
668
669 DPRINTF(ah->ah_sc, ATH_DBG_ANI, "Disable MIB counters\n"); 647 DPRINTF(ah->ah_sc, ATH_DBG_ANI, "Disable MIB counters\n");
670 648
671 REG_WRITE(ah, AR_MIBC, AR_MIBC_FMC | AR_MIBC_CMC); 649 REG_WRITE(ah, AR_MIBC, AR_MIBC_FMC | AR_MIBC_CMC);
672 650
673 ath9k_hw_update_mibstats(ah, &ahp->ah_mibStats); 651 ath9k_hw_update_mibstats(ah, &ah->ah_mibStats);
674 652
675 REG_WRITE(ah, AR_FILT_OFDM, 0); 653 REG_WRITE(ah, AR_FILT_OFDM, 0);
676 REG_WRITE(ah, AR_FILT_CCK, 0); 654 REG_WRITE(ah, AR_FILT_CCK, 0);
677} 655}
678 656
679u32 ath9k_hw_GetMibCycleCountsPct(struct ath_hal *ah, 657u32 ath9k_hw_GetMibCycleCountsPct(struct ath_hw *ah,
680 u32 *rxc_pcnt, 658 u32 *rxc_pcnt,
681 u32 *rxf_pcnt, 659 u32 *rxf_pcnt,
682 u32 *txf_pcnt) 660 u32 *txf_pcnt)
@@ -721,10 +699,9 @@ u32 ath9k_hw_GetMibCycleCountsPct(struct ath_hal *ah,
721 * any of the MIB counters overflow/trigger so don't assume we're 699 * any of the MIB counters overflow/trigger so don't assume we're
722 * here because a PHY error counter triggered. 700 * here because a PHY error counter triggered.
723 */ 701 */
724void ath9k_hw_procmibevent(struct ath_hal *ah, 702void ath9k_hw_procmibevent(struct ath_hw *ah,
725 const struct ath9k_node_stats *stats) 703 const struct ath9k_node_stats *stats)
726{ 704{
727 struct ath_hal_5416 *ahp = AH5416(ah);
728 u32 phyCnt1, phyCnt2; 705 u32 phyCnt1, phyCnt2;
729 706
730 /* Reset these counters regardless */ 707 /* Reset these counters regardless */
@@ -734,8 +711,8 @@ void ath9k_hw_procmibevent(struct ath_hal *ah,
734 REG_WRITE(ah, AR_SLP_MIB_CTRL, AR_SLP_MIB_CLEAR); 711 REG_WRITE(ah, AR_SLP_MIB_CTRL, AR_SLP_MIB_CLEAR);
735 712
736 /* Clear the mib counters and save them in the stats */ 713 /* Clear the mib counters and save them in the stats */
737 ath9k_hw_update_mibstats(ah, &ahp->ah_mibStats); 714 ath9k_hw_update_mibstats(ah, &ah->ah_mibStats);
738 ahp->ah_stats.ast_nodestats = *stats; 715 ah->stats.ast_nodestats = *stats;
739 716
740 if (!DO_ANI(ah)) 717 if (!DO_ANI(ah))
741 return; 718 return;
@@ -745,17 +722,17 @@ void ath9k_hw_procmibevent(struct ath_hal *ah,
745 phyCnt2 = REG_READ(ah, AR_PHY_ERR_2); 722 phyCnt2 = REG_READ(ah, AR_PHY_ERR_2);
746 if (((phyCnt1 & AR_MIBCNT_INTRMASK) == AR_MIBCNT_INTRMASK) || 723 if (((phyCnt1 & AR_MIBCNT_INTRMASK) == AR_MIBCNT_INTRMASK) ||
747 ((phyCnt2 & AR_MIBCNT_INTRMASK) == AR_MIBCNT_INTRMASK)) { 724 ((phyCnt2 & AR_MIBCNT_INTRMASK) == AR_MIBCNT_INTRMASK)) {
748 struct ar5416AniState *aniState = ahp->ah_curani; 725 struct ar5416AniState *aniState = ah->curani;
749 u32 ofdmPhyErrCnt, cckPhyErrCnt; 726 u32 ofdmPhyErrCnt, cckPhyErrCnt;
750 727
751 /* NB: only use ast_ani_*errs with AH_PRIVATE_DIAG */ 728 /* NB: only use ast_ani_*errs with AH_PRIVATE_DIAG */
752 ofdmPhyErrCnt = phyCnt1 - aniState->ofdmPhyErrBase; 729 ofdmPhyErrCnt = phyCnt1 - aniState->ofdmPhyErrBase;
753 ahp->ah_stats.ast_ani_ofdmerrs += 730 ah->stats.ast_ani_ofdmerrs +=
754 ofdmPhyErrCnt - aniState->ofdmPhyErrCount; 731 ofdmPhyErrCnt - aniState->ofdmPhyErrCount;
755 aniState->ofdmPhyErrCount = ofdmPhyErrCnt; 732 aniState->ofdmPhyErrCount = ofdmPhyErrCnt;
756 733
757 cckPhyErrCnt = phyCnt2 - aniState->cckPhyErrBase; 734 cckPhyErrCnt = phyCnt2 - aniState->cckPhyErrBase;
758 ahp->ah_stats.ast_ani_cckerrs += 735 ah->stats.ast_ani_cckerrs +=
759 cckPhyErrCnt - aniState->cckPhyErrCount; 736 cckPhyErrCnt - aniState->cckPhyErrCount;
760 aniState->cckPhyErrCount = cckPhyErrCnt; 737 aniState->cckPhyErrCount = cckPhyErrCnt;
761 738
@@ -774,9 +751,8 @@ void ath9k_hw_procmibevent(struct ath_hal *ah,
774 } 751 }
775} 752}
776 753
777void ath9k_hw_ani_setup(struct ath_hal *ah) 754void ath9k_hw_ani_setup(struct ath_hw *ah)
778{ 755{
779 struct ath_hal_5416 *ahp = AH5416(ah);
780 int i; 756 int i;
781 757
782 const int totalSizeDesired[] = { -55, -55, -55, -55, -62 }; 758 const int totalSizeDesired[] = { -55, -55, -55, -55, -62 };
@@ -785,66 +761,63 @@ void ath9k_hw_ani_setup(struct ath_hal *ah)
785 const int firpwr[] = { -78, -78, -78, -78, -80 }; 761 const int firpwr[] = { -78, -78, -78, -78, -80 };
786 762
787 for (i = 0; i < 5; i++) { 763 for (i = 0; i < 5; i++) {
788 ahp->ah_totalSizeDesired[i] = totalSizeDesired[i]; 764 ah->totalSizeDesired[i] = totalSizeDesired[i];
789 ahp->ah_coarseHigh[i] = coarseHigh[i]; 765 ah->coarse_high[i] = coarseHigh[i];
790 ahp->ah_coarseLow[i] = coarseLow[i]; 766 ah->coarse_low[i] = coarseLow[i];
791 ahp->ah_firpwr[i] = firpwr[i]; 767 ah->firpwr[i] = firpwr[i];
792 } 768 }
793} 769}
794 770
795void ath9k_hw_ani_attach(struct ath_hal *ah) 771void ath9k_hw_ani_attach(struct ath_hw *ah)
796{ 772{
797 struct ath_hal_5416 *ahp = AH5416(ah);
798 int i; 773 int i;
799 774
800 DPRINTF(ah->ah_sc, ATH_DBG_ANI, "Attach ANI\n"); 775 DPRINTF(ah->ah_sc, ATH_DBG_ANI, "Attach ANI\n");
801 776
802 ahp->ah_hasHwPhyCounters = 1; 777 ah->has_hw_phycounters = 1;
803 778
804 memset(ahp->ah_ani, 0, sizeof(ahp->ah_ani)); 779 memset(ah->ani, 0, sizeof(ah->ani));
805 for (i = 0; i < ARRAY_SIZE(ahp->ah_ani); i++) { 780 for (i = 0; i < ARRAY_SIZE(ah->ani); i++) {
806 ahp->ah_ani[i].ofdmTrigHigh = ATH9K_ANI_OFDM_TRIG_HIGH; 781 ah->ani[i].ofdmTrigHigh = ATH9K_ANI_OFDM_TRIG_HIGH;
807 ahp->ah_ani[i].ofdmTrigLow = ATH9K_ANI_OFDM_TRIG_LOW; 782 ah->ani[i].ofdmTrigLow = ATH9K_ANI_OFDM_TRIG_LOW;
808 ahp->ah_ani[i].cckTrigHigh = ATH9K_ANI_CCK_TRIG_HIGH; 783 ah->ani[i].cckTrigHigh = ATH9K_ANI_CCK_TRIG_HIGH;
809 ahp->ah_ani[i].cckTrigLow = ATH9K_ANI_CCK_TRIG_LOW; 784 ah->ani[i].cckTrigLow = ATH9K_ANI_CCK_TRIG_LOW;
810 ahp->ah_ani[i].rssiThrHigh = ATH9K_ANI_RSSI_THR_HIGH; 785 ah->ani[i].rssiThrHigh = ATH9K_ANI_RSSI_THR_HIGH;
811 ahp->ah_ani[i].rssiThrLow = ATH9K_ANI_RSSI_THR_LOW; 786 ah->ani[i].rssiThrLow = ATH9K_ANI_RSSI_THR_LOW;
812 ahp->ah_ani[i].ofdmWeakSigDetectOff = 787 ah->ani[i].ofdmWeakSigDetectOff =
813 !ATH9K_ANI_USE_OFDM_WEAK_SIG; 788 !ATH9K_ANI_USE_OFDM_WEAK_SIG;
814 ahp->ah_ani[i].cckWeakSigThreshold = 789 ah->ani[i].cckWeakSigThreshold =
815 ATH9K_ANI_CCK_WEAK_SIG_THR; 790 ATH9K_ANI_CCK_WEAK_SIG_THR;
816 ahp->ah_ani[i].spurImmunityLevel = ATH9K_ANI_SPUR_IMMUNE_LVL; 791 ah->ani[i].spurImmunityLevel = ATH9K_ANI_SPUR_IMMUNE_LVL;
817 ahp->ah_ani[i].firstepLevel = ATH9K_ANI_FIRSTEP_LVL; 792 ah->ani[i].firstepLevel = ATH9K_ANI_FIRSTEP_LVL;
818 if (ahp->ah_hasHwPhyCounters) { 793 if (ah->has_hw_phycounters) {
819 ahp->ah_ani[i].ofdmPhyErrBase = 794 ah->ani[i].ofdmPhyErrBase =
820 AR_PHY_COUNTMAX - ATH9K_ANI_OFDM_TRIG_HIGH; 795 AR_PHY_COUNTMAX - ATH9K_ANI_OFDM_TRIG_HIGH;
821 ahp->ah_ani[i].cckPhyErrBase = 796 ah->ani[i].cckPhyErrBase =
822 AR_PHY_COUNTMAX - ATH9K_ANI_CCK_TRIG_HIGH; 797 AR_PHY_COUNTMAX - ATH9K_ANI_CCK_TRIG_HIGH;
823 } 798 }
824 } 799 }
825 if (ahp->ah_hasHwPhyCounters) { 800 if (ah->has_hw_phycounters) {
826 DPRINTF(ah->ah_sc, ATH_DBG_ANI, 801 DPRINTF(ah->ah_sc, ATH_DBG_ANI,
827 "Setting OfdmErrBase = 0x%08x\n", 802 "Setting OfdmErrBase = 0x%08x\n",
828 ahp->ah_ani[0].ofdmPhyErrBase); 803 ah->ani[0].ofdmPhyErrBase);
829 DPRINTF(ah->ah_sc, ATH_DBG_ANI, "Setting cckErrBase = 0x%08x\n", 804 DPRINTF(ah->ah_sc, ATH_DBG_ANI, "Setting cckErrBase = 0x%08x\n",
830 ahp->ah_ani[0].cckPhyErrBase); 805 ah->ani[0].cckPhyErrBase);
831 806
832 REG_WRITE(ah, AR_PHY_ERR_1, ahp->ah_ani[0].ofdmPhyErrBase); 807 REG_WRITE(ah, AR_PHY_ERR_1, ah->ani[0].ofdmPhyErrBase);
833 REG_WRITE(ah, AR_PHY_ERR_2, ahp->ah_ani[0].cckPhyErrBase); 808 REG_WRITE(ah, AR_PHY_ERR_2, ah->ani[0].cckPhyErrBase);
834 ath9k_enable_mib_counters(ah); 809 ath9k_enable_mib_counters(ah);
835 } 810 }
836 ahp->ah_aniPeriod = ATH9K_ANI_PERIOD; 811 ah->aniperiod = ATH9K_ANI_PERIOD;
837 if (ah->ah_config.enable_ani) 812 if (ah->config.enable_ani)
838 ahp->ah_procPhyErr |= HAL_PROCESS_ANI; 813 ah->proc_phyerr |= HAL_PROCESS_ANI;
839} 814}
840 815
841void ath9k_hw_ani_detach(struct ath_hal *ah) 816void ath9k_hw_ani_detach(struct ath_hw *ah)
842{ 817{
843 struct ath_hal_5416 *ahp = AH5416(ah);
844
845 DPRINTF(ah->ah_sc, ATH_DBG_ANI, "Detach ANI\n"); 818 DPRINTF(ah->ah_sc, ATH_DBG_ANI, "Detach ANI\n");
846 819
847 if (ahp->ah_hasHwPhyCounters) { 820 if (ah->has_hw_phycounters) {
848 ath9k_hw_disable_mib_counters(ah); 821 ath9k_hw_disable_mib_counters(ah);
849 REG_WRITE(ah, AR_PHY_ERR_1, 0); 822 REG_WRITE(ah, AR_PHY_ERR_1, 0);
850 REG_WRITE(ah, AR_PHY_ERR_2, 0); 823 REG_WRITE(ah, AR_PHY_ERR_2, 0);