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path: root/drivers/net/wireless/ath/ath9k/ar9003_hw.c
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Diffstat (limited to 'drivers/net/wireless/ath/ath9k/ar9003_hw.c')
-rw-r--r--drivers/net/wireless/ath/ath9k/ar9003_hw.c98
1 files changed, 4 insertions, 94 deletions
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_hw.c b/drivers/net/wireless/ath/ath9k/ar9003_hw.c
index 7f5de6e4448..aebaad97b19 100644
--- a/drivers/net/wireless/ath/ath9k/ar9003_hw.c
+++ b/drivers/net/wireless/ath/ath9k/ar9003_hw.c
@@ -66,8 +66,8 @@ static void ar9003_hw_init_mode_regs(struct ath_hw *ah)
66 66
67 /* rx/tx gain */ 67 /* rx/tx gain */
68 INIT_INI_ARRAY(&ah->iniModesRxGain, 68 INIT_INI_ARRAY(&ah->iniModesRxGain,
69 ar9485_common_rx_gain_1_1, 69 ar9485Common_wo_xlna_rx_gain_1_1,
70 ARRAY_SIZE(ar9485_common_rx_gain_1_1), 2); 70 ARRAY_SIZE(ar9485Common_wo_xlna_rx_gain_1_1), 2);
71 INIT_INI_ARRAY(&ah->iniModesTxGain, 71 INIT_INI_ARRAY(&ah->iniModesTxGain,
72 ar9485_modes_lowest_ob_db_tx_gain_1_1, 72 ar9485_modes_lowest_ob_db_tx_gain_1_1,
73 ARRAY_SIZE(ar9485_modes_lowest_ob_db_tx_gain_1_1), 73 ARRAY_SIZE(ar9485_modes_lowest_ob_db_tx_gain_1_1),
@@ -88,66 +88,6 @@ static void ar9003_hw_init_mode_regs(struct ath_hw *ah)
88 ar9485_1_1_pcie_phy_clkreq_disable_L1, 88 ar9485_1_1_pcie_phy_clkreq_disable_L1,
89 ARRAY_SIZE(ar9485_1_1_pcie_phy_clkreq_disable_L1), 89 ARRAY_SIZE(ar9485_1_1_pcie_phy_clkreq_disable_L1),
90 2); 90 2);
91 } else if (AR_SREV_9485(ah)) {
92 /* mac */
93 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
94 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
95 ar9485_1_0_mac_core,
96 ARRAY_SIZE(ar9485_1_0_mac_core), 2);
97 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
98 ar9485_1_0_mac_postamble,
99 ARRAY_SIZE(ar9485_1_0_mac_postamble), 5);
100
101 /* bb */
102 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], ar9485_1_0,
103 ARRAY_SIZE(ar9485_1_0), 2);
104 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
105 ar9485_1_0_baseband_core,
106 ARRAY_SIZE(ar9485_1_0_baseband_core), 2);
107 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
108 ar9485_1_0_baseband_postamble,
109 ARRAY_SIZE(ar9485_1_0_baseband_postamble), 5);
110
111 /* radio */
112 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
113 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
114 ar9485_1_0_radio_core,
115 ARRAY_SIZE(ar9485_1_0_radio_core), 2);
116 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
117 ar9485_1_0_radio_postamble,
118 ARRAY_SIZE(ar9485_1_0_radio_postamble), 2);
119
120 /* soc */
121 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
122 ar9485_1_0_soc_preamble,
123 ARRAY_SIZE(ar9485_1_0_soc_preamble), 2);
124 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
125 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST], NULL, 0, 0);
126
127 /* rx/tx gain */
128 INIT_INI_ARRAY(&ah->iniModesRxGain,
129 ar9485Common_rx_gain_1_0,
130 ARRAY_SIZE(ar9485Common_rx_gain_1_0), 2);
131 INIT_INI_ARRAY(&ah->iniModesTxGain,
132 ar9485Modes_lowest_ob_db_tx_gain_1_0,
133 ARRAY_SIZE(ar9485Modes_lowest_ob_db_tx_gain_1_0),
134 5);
135
136 /* Load PCIE SERDES settings from INI */
137
138 /* Awake Setting */
139
140 INIT_INI_ARRAY(&ah->iniPcieSerdes,
141 ar9485_1_0_pcie_phy_pll_on_clkreq_disable_L1,
142 ARRAY_SIZE(ar9485_1_0_pcie_phy_pll_on_clkreq_disable_L1),
143 2);
144
145 /* Sleep Setting */
146
147 INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
148 ar9485_1_0_pcie_phy_pll_on_clkreq_disable_L1,
149 ARRAY_SIZE(ar9485_1_0_pcie_phy_pll_on_clkreq_disable_L1),
150 2);
151 } else { 91 } else {
152 /* mac */ 92 /* mac */
153 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0); 93 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
@@ -228,11 +168,6 @@ static void ar9003_tx_gain_table_apply(struct ath_hw *ah)
228 ar9485_modes_lowest_ob_db_tx_gain_1_1, 168 ar9485_modes_lowest_ob_db_tx_gain_1_1,
229 ARRAY_SIZE(ar9485_modes_lowest_ob_db_tx_gain_1_1), 169 ARRAY_SIZE(ar9485_modes_lowest_ob_db_tx_gain_1_1),
230 5); 170 5);
231 else if (AR_SREV_9485(ah))
232 INIT_INI_ARRAY(&ah->iniModesTxGain,
233 ar9485Modes_lowest_ob_db_tx_gain_1_0,
234 ARRAY_SIZE(ar9485Modes_lowest_ob_db_tx_gain_1_0),
235 5);
236 else 171 else
237 INIT_INI_ARRAY(&ah->iniModesTxGain, 172 INIT_INI_ARRAY(&ah->iniModesTxGain,
238 ar9300Modes_lowest_ob_db_tx_gain_table_2p2, 173 ar9300Modes_lowest_ob_db_tx_gain_table_2p2,
@@ -245,11 +180,6 @@ static void ar9003_tx_gain_table_apply(struct ath_hw *ah)
245 ar9485Modes_high_ob_db_tx_gain_1_1, 180 ar9485Modes_high_ob_db_tx_gain_1_1,
246 ARRAY_SIZE(ar9485Modes_high_ob_db_tx_gain_1_1), 181 ARRAY_SIZE(ar9485Modes_high_ob_db_tx_gain_1_1),
247 5); 182 5);
248 else if (AR_SREV_9485(ah))
249 INIT_INI_ARRAY(&ah->iniModesTxGain,
250 ar9485Modes_high_ob_db_tx_gain_1_0,
251 ARRAY_SIZE(ar9485Modes_high_ob_db_tx_gain_1_0),
252 5);
253 else 183 else
254 INIT_INI_ARRAY(&ah->iniModesTxGain, 184 INIT_INI_ARRAY(&ah->iniModesTxGain,
255 ar9300Modes_high_ob_db_tx_gain_table_2p2, 185 ar9300Modes_high_ob_db_tx_gain_table_2p2,
@@ -262,11 +192,6 @@ static void ar9003_tx_gain_table_apply(struct ath_hw *ah)
262 ar9485Modes_low_ob_db_tx_gain_1_1, 192 ar9485Modes_low_ob_db_tx_gain_1_1,
263 ARRAY_SIZE(ar9485Modes_low_ob_db_tx_gain_1_1), 193 ARRAY_SIZE(ar9485Modes_low_ob_db_tx_gain_1_1),
264 5); 194 5);
265 else if (AR_SREV_9485(ah))
266 INIT_INI_ARRAY(&ah->iniModesTxGain,
267 ar9485Modes_low_ob_db_tx_gain_1_0,
268 ARRAY_SIZE(ar9485Modes_low_ob_db_tx_gain_1_0),
269 5);
270 else 195 else
271 INIT_INI_ARRAY(&ah->iniModesTxGain, 196 INIT_INI_ARRAY(&ah->iniModesTxGain,
272 ar9300Modes_low_ob_db_tx_gain_table_2p2, 197 ar9300Modes_low_ob_db_tx_gain_table_2p2,
@@ -279,11 +204,6 @@ static void ar9003_tx_gain_table_apply(struct ath_hw *ah)
279 ar9485Modes_high_power_tx_gain_1_1, 204 ar9485Modes_high_power_tx_gain_1_1,
280 ARRAY_SIZE(ar9485Modes_high_power_tx_gain_1_1), 205 ARRAY_SIZE(ar9485Modes_high_power_tx_gain_1_1),
281 5); 206 5);
282 else if (AR_SREV_9485(ah))
283 INIT_INI_ARRAY(&ah->iniModesTxGain,
284 ar9485Modes_high_power_tx_gain_1_0,
285 ARRAY_SIZE(ar9485Modes_high_power_tx_gain_1_0),
286 5);
287 else 207 else
288 INIT_INI_ARRAY(&ah->iniModesTxGain, 208 INIT_INI_ARRAY(&ah->iniModesTxGain,
289 ar9300Modes_high_power_tx_gain_table_2p2, 209 ar9300Modes_high_power_tx_gain_table_2p2,
@@ -300,13 +220,8 @@ static void ar9003_rx_gain_table_apply(struct ath_hw *ah)
300 default: 220 default:
301 if (AR_SREV_9485_11(ah)) 221 if (AR_SREV_9485_11(ah))
302 INIT_INI_ARRAY(&ah->iniModesRxGain, 222 INIT_INI_ARRAY(&ah->iniModesRxGain,
303 ar9485_common_rx_gain_1_1, 223 ar9485Common_wo_xlna_rx_gain_1_1,
304 ARRAY_SIZE(ar9485_common_rx_gain_1_1), 224 ARRAY_SIZE(ar9485Common_wo_xlna_rx_gain_1_1),
305 2);
306 else if (AR_SREV_9485(ah))
307 INIT_INI_ARRAY(&ah->iniModesRxGain,
308 ar9485Common_rx_gain_1_0,
309 ARRAY_SIZE(ar9485Common_rx_gain_1_0),
310 2); 225 2);
311 else 226 else
312 INIT_INI_ARRAY(&ah->iniModesRxGain, 227 INIT_INI_ARRAY(&ah->iniModesRxGain,
@@ -320,11 +235,6 @@ static void ar9003_rx_gain_table_apply(struct ath_hw *ah)
320 ar9485Common_wo_xlna_rx_gain_1_1, 235 ar9485Common_wo_xlna_rx_gain_1_1,
321 ARRAY_SIZE(ar9485Common_wo_xlna_rx_gain_1_1), 236 ARRAY_SIZE(ar9485Common_wo_xlna_rx_gain_1_1),
322 2); 237 2);
323 else if (AR_SREV_9485(ah))
324 INIT_INI_ARRAY(&ah->iniModesRxGain,
325 ar9485Common_wo_xlna_rx_gain_1_0,
326 ARRAY_SIZE(ar9485Common_wo_xlna_rx_gain_1_0),
327 2);
328 else 238 else
329 INIT_INI_ARRAY(&ah->iniModesRxGain, 239 INIT_INI_ARRAY(&ah->iniModesRxGain,
330 ar9300Common_wo_xlna_rx_gain_table_2p2, 240 ar9300Common_wo_xlna_rx_gain_table_2p2,
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-22 06:38:27 -0400