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-rw-r--r--drivers/net/wan/Kconfig31
-rw-r--r--drivers/net/wan/Makefile5
-rw-r--r--drivers/net/wan/pc300-falc-lh.h1238
-rw-r--r--drivers/net/wan/pc300.h436
-rw-r--r--drivers/net/wan/pc300_drv.c3670
-rw-r--r--drivers/net/wan/pc300_tty.c1079
6 files changed, 0 insertions, 6459 deletions
diff --git a/drivers/net/wan/Kconfig b/drivers/net/wan/Kconfig
index d70ede7a7f9..d58431e99f7 100644
--- a/drivers/net/wan/Kconfig
+++ b/drivers/net/wan/Kconfig
@@ -203,37 +203,6 @@ config WANXL_BUILD_FIRMWARE
203 203
204 You should never need this option, say N. 204 You should never need this option, say N.
205 205
206config PC300
207 tristate "Cyclades-PC300 support (RS-232/V.35, X.21, T1/E1 boards)"
208 depends on HDLC && PCI && BROKEN
209 ---help---
210 This driver is broken because of struct tty_driver change.
211
212 Driver for the Cyclades-PC300 synchronous communication boards.
213
214 These boards provide synchronous serial interfaces to your
215 Linux box (interfaces currently available are RS-232/V.35, X.21 and
216 T1/E1). If you wish to support Multilink PPP, please select the
217 option later and read the file README.mlppp provided by PC300
218 package.
219
220 To compile this as a module, choose M here: the module
221 will be called pc300.
222
223 If unsure, say N.
224
225config PC300_MLPPP
226 bool "Cyclades-PC300 MLPPP support"
227 depends on PC300 && PPP_MULTILINK && PPP_SYNC_TTY && HDLC_PPP
228 help
229 Multilink PPP over the PC300 synchronous communication boards.
230
231comment "Cyclades-PC300 MLPPP support is disabled."
232 depends on HDLC && PC300 && (PPP=n || !PPP_MULTILINK || PPP_SYNC_TTY=n || !HDLC_PPP)
233
234comment "Refer to the file README.mlppp, provided by PC300 package."
235 depends on HDLC && PC300 && (PPP=n || !PPP_MULTILINK || PPP_SYNC_TTY=n || !HDLC_PPP)
236
237config PC300TOO 206config PC300TOO
238 tristate "Cyclades PC300 RSV/X21 alternative support" 207 tristate "Cyclades PC300 RSV/X21 alternative support"
239 depends on HDLC && PCI 208 depends on HDLC && PCI
diff --git a/drivers/net/wan/Makefile b/drivers/net/wan/Makefile
index 19d14bc2835..eac709bed7a 100644
--- a/drivers/net/wan/Makefile
+++ b/drivers/net/wan/Makefile
@@ -17,10 +17,6 @@ obj-$(CONFIG_HDLC_FR) += hdlc_fr.o
17obj-$(CONFIG_HDLC_PPP) += hdlc_ppp.o 17obj-$(CONFIG_HDLC_PPP) += hdlc_ppp.o
18obj-$(CONFIG_HDLC_X25) += hdlc_x25.o 18obj-$(CONFIG_HDLC_X25) += hdlc_x25.o
19 19
20pc300-y := pc300_drv.o
21pc300-$(CONFIG_PC300_MLPPP) += pc300_tty.o
22pc300-objs := $(pc300-y)
23
24obj-$(CONFIG_HOSTESS_SV11) += z85230.o hostess_sv11.o 20obj-$(CONFIG_HOSTESS_SV11) += z85230.o hostess_sv11.o
25obj-$(CONFIG_SEALEVEL_4021) += z85230.o sealevel.o 21obj-$(CONFIG_SEALEVEL_4021) += z85230.o sealevel.o
26obj-$(CONFIG_COSA) += cosa.o 22obj-$(CONFIG_COSA) += cosa.o
@@ -35,7 +31,6 @@ obj-$(CONFIG_SDLA) += sdla.o
35obj-$(CONFIG_CYCLADES_SYNC) += cycx_drv.o cyclomx.o 31obj-$(CONFIG_CYCLADES_SYNC) += cycx_drv.o cyclomx.o
36obj-$(CONFIG_LAPBETHER) += lapbether.o 32obj-$(CONFIG_LAPBETHER) += lapbether.o
37obj-$(CONFIG_SBNI) += sbni.o 33obj-$(CONFIG_SBNI) += sbni.o
38obj-$(CONFIG_PC300) += pc300.o
39obj-$(CONFIG_N2) += n2.o 34obj-$(CONFIG_N2) += n2.o
40obj-$(CONFIG_C101) += c101.o 35obj-$(CONFIG_C101) += c101.o
41obj-$(CONFIG_WANXL) += wanxl.o 36obj-$(CONFIG_WANXL) += wanxl.o
diff --git a/drivers/net/wan/pc300-falc-lh.h b/drivers/net/wan/pc300-falc-lh.h
deleted file mode 100644
index 01ed23ca76c..00000000000
--- a/drivers/net/wan/pc300-falc-lh.h
+++ /dev/null
@@ -1,1238 +0,0 @@
1/*
2 * falc.h Description of the Siemens FALC T1/E1 framer.
3 *
4 * Author: Ivan Passos <ivan@cyclades.com>
5 *
6 * Copyright: (c) 2000-2001 Cyclades Corp.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * as published by the Free Software Foundation; either version
11 * 2 of the License, or (at your option) any later version.
12 *
13 * $Log: falc-lh.h,v $
14 * Revision 3.1 2001/06/15 12:41:10 regina
15 * upping major version number
16 *
17 * Revision 1.1.1.1 2001/06/13 20:24:47 daniela
18 * PC300 initial CVS version (3.4.0-pre1)
19 *
20 * Revision 1.1 2000/05/15 ivan
21 * Included DJA bits for the LIM2 register.
22 *
23 * Revision 1.0 2000/02/22 ivan
24 * Initial version.
25 *
26 */
27
28#ifndef _FALC_LH_H
29#define _FALC_LH_H
30
31#define NUM_OF_T1_CHANNELS 24
32#define NUM_OF_E1_CHANNELS 32
33
34/*>>>>>>>>>>>>>>>>> FALC Register Bits (Transmit Mode) <<<<<<<<<<<<<<<<<<< */
35
36/* CMDR (Command Register)
37 ---------------- E1 & T1 ------------------------------ */
38#define CMDR_RMC 0x80
39#define CMDR_RRES 0x40
40#define CMDR_XREP 0x20
41#define CMDR_XRES 0x10
42#define CMDR_XHF 0x08
43#define CMDR_XTF 0x04
44#define CMDR_XME 0x02
45#define CMDR_SRES 0x01
46
47/* MODE (Mode Register)
48 ----------------- E1 & T1 ----------------------------- */
49#define MODE_MDS2 0x80
50#define MODE_MDS1 0x40
51#define MODE_MDS0 0x20
52#define MODE_BRAC 0x10
53#define MODE_HRAC 0x08
54
55/* IPC (Interrupt Port Configuration)
56 ----------------- E1 & T1 ----------------------------- */
57#define IPC_VIS 0x80
58#define IPC_SCI 0x04
59#define IPC_IC1 0x02
60#define IPC_IC0 0x01
61
62/* CCR1 (Common Configuration Register 1)
63 ----------------- E1 & T1 ----------------------------- */
64#define CCR1_SFLG 0x80
65#define CCR1_XTS16RA 0x40
66#define CCR1_BRM 0x40
67#define CCR1_CASSYM 0x20
68#define CCR1_EDLX 0x20
69#define CCR1_EITS 0x10
70#define CCR1_ITF 0x08
71#define CCR1_RFT1 0x02
72#define CCR1_RFT0 0x01
73
74/* CCR3 (Common Configuration Register 3)
75 ---------------- E1 & T1 ------------------------------ */
76
77#define CCR3_PRE1 0x80
78#define CCR3_PRE0 0x40
79#define CCR3_EPT 0x20
80#define CCR3_RADD 0x10
81#define CCR3_RCRC 0x04
82#define CCR3_XCRC 0x02
83
84
85/* RTR1-4 (Receive Timeslot Register 1-4)
86 ---------------- E1 & T1 ------------------------------ */
87
88#define RTR1_TS0 0x80
89#define RTR1_TS1 0x40
90#define RTR1_TS2 0x20
91#define RTR1_TS3 0x10
92#define RTR1_TS4 0x08
93#define RTR1_TS5 0x04
94#define RTR1_TS6 0x02
95#define RTR1_TS7 0x01
96
97#define RTR2_TS8 0x80
98#define RTR2_TS9 0x40
99#define RTR2_TS10 0x20
100#define RTR2_TS11 0x10
101#define RTR2_TS12 0x08
102#define RTR2_TS13 0x04
103#define RTR2_TS14 0x02
104#define RTR2_TS15 0x01
105
106#define RTR3_TS16 0x80
107#define RTR3_TS17 0x40
108#define RTR3_TS18 0x20
109#define RTR3_TS19 0x10
110#define RTR3_TS20 0x08
111#define RTR3_TS21 0x04
112#define RTR3_TS22 0x02
113#define RTR3_TS23 0x01
114
115#define RTR4_TS24 0x80
116#define RTR4_TS25 0x40
117#define RTR4_TS26 0x20
118#define RTR4_TS27 0x10
119#define RTR4_TS28 0x08
120#define RTR4_TS29 0x04
121#define RTR4_TS30 0x02
122#define RTR4_TS31 0x01
123
124
125/* TTR1-4 (Transmit Timeslot Register 1-4)
126 ---------------- E1 & T1 ------------------------------ */
127
128#define TTR1_TS0 0x80
129#define TTR1_TS1 0x40
130#define TTR1_TS2 0x20
131#define TTR1_TS3 0x10
132#define TTR1_TS4 0x08
133#define TTR1_TS5 0x04
134#define TTR1_TS6 0x02
135#define TTR1_TS7 0x01
136
137#define TTR2_TS8 0x80
138#define TTR2_TS9 0x40
139#define TTR2_TS10 0x20
140#define TTR2_TS11 0x10
141#define TTR2_TS12 0x08
142#define TTR2_TS13 0x04
143#define TTR2_TS14 0x02
144#define TTR2_TS15 0x01
145
146#define TTR3_TS16 0x80
147#define TTR3_TS17 0x40
148#define TTR3_TS18 0x20
149#define TTR3_TS19 0x10
150#define TTR3_TS20 0x08
151#define TTR3_TS21 0x04
152#define TTR3_TS22 0x02
153#define TTR3_TS23 0x01
154
155#define TTR4_TS24 0x80
156#define TTR4_TS25 0x40
157#define TTR4_TS26 0x20
158#define TTR4_TS27 0x10
159#define TTR4_TS28 0x08
160#define TTR4_TS29 0x04
161#define TTR4_TS30 0x02
162#define TTR4_TS31 0x01
163
164
165
166/* IMR0-4 (Interrupt Mask Register 0-4)
167
168 ----------------- E1 & T1 ----------------------------- */
169
170#define IMR0_RME 0x80
171#define IMR0_RFS 0x40
172#define IMR0_T8MS 0x20
173#define IMR0_ISF 0x20
174#define IMR0_RMB 0x10
175#define IMR0_CASC 0x08
176#define IMR0_RSC 0x08
177#define IMR0_CRC6 0x04
178#define IMR0_CRC4 0x04
179#define IMR0_PDEN 0x02
180#define IMR0_RPF 0x01
181
182#define IMR1_CASE 0x80
183#define IMR1_RDO 0x40
184#define IMR1_ALLS 0x20
185#define IMR1_XDU 0x10
186#define IMR1_XMB 0x08
187#define IMR1_XLSC 0x02
188#define IMR1_XPR 0x01
189#define IMR1_LLBSC 0x80
190
191#define IMR2_FAR 0x80
192#define IMR2_LFA 0x40
193#define IMR2_MFAR 0x20
194#define IMR2_T400MS 0x10
195#define IMR2_LMFA 0x10
196#define IMR2_AIS 0x08
197#define IMR2_LOS 0x04
198#define IMR2_RAR 0x02
199#define IMR2_RA 0x01
200
201#define IMR3_ES 0x80
202#define IMR3_SEC 0x40
203#define IMR3_LMFA16 0x20
204#define IMR3_AIS16 0x10
205#define IMR3_RA16 0x08
206#define IMR3_API 0x04
207#define IMR3_XSLP 0x20
208#define IMR3_XSLN 0x10
209#define IMR3_LLBSC 0x08
210#define IMR3_XRS 0x04
211#define IMR3_SLN 0x02
212#define IMR3_SLP 0x01
213
214#define IMR4_LFA 0x80
215#define IMR4_FER 0x40
216#define IMR4_CER 0x20
217#define IMR4_AIS 0x10
218#define IMR4_LOS 0x08
219#define IMR4_CVE 0x04
220#define IMR4_SLIP 0x02
221#define IMR4_EBE 0x01
222
223/* FMR0-5 for E1 and T1 (Framer Mode Register ) */
224
225#define FMR0_XC1 0x80
226#define FMR0_XC0 0x40
227#define FMR0_RC1 0x20
228#define FMR0_RC0 0x10
229#define FMR0_EXTD 0x08
230#define FMR0_ALM 0x04
231#define E1_FMR0_FRS 0x02
232#define T1_FMR0_FRS 0x08
233#define FMR0_SRAF 0x04
234#define FMR0_EXLS 0x02
235#define FMR0_SIM 0x01
236
237#define FMR1_MFCS 0x80
238#define FMR1_AFR 0x40
239#define FMR1_ENSA 0x20
240#define FMR1_CTM 0x80
241#define FMR1_SIGM 0x40
242#define FMR1_EDL 0x20
243#define FMR1_PMOD 0x10
244#define FMR1_XFS 0x08
245#define FMR1_CRC 0x08
246#define FMR1_ECM 0x04
247#define FMR1_IMOD 0x02
248#define FMR1_XAIS 0x01
249
250#define FMR2_RFS1 0x80
251#define FMR2_RFS0 0x40
252#define FMR2_MCSP 0x40
253#define FMR2_RTM 0x20
254#define FMR2_SSP 0x20
255#define FMR2_DAIS 0x10
256#define FMR2_SAIS 0x08
257#define FMR2_PLB 0x04
258#define FMR2_AXRA 0x02
259#define FMR2_ALMF 0x01
260#define FMR2_EXZE 0x01
261
262#define LOOP_RTM 0x40
263#define LOOP_SFM 0x40
264#define LOOP_ECLB 0x20
265#define LOOP_CLA 0x1f
266
267/*--------------------- E1 ----------------------------*/
268#define FMR3_XLD 0x20
269#define FMR3_XLU 0x10
270
271/*--------------------- T1 ----------------------------*/
272#define FMR4_AIS3 0x80
273#define FMR4_TM 0x40
274#define FMR4_XRA 0x20
275#define FMR4_SSC1 0x10
276#define FMR4_SSC0 0x08
277#define FMR4_AUTO 0x04
278#define FMR4_FM1 0x02
279#define FMR4_FM0 0x01
280
281#define FMR5_SRS 0x80
282#define FMR5_EIBR 0x40
283#define FMR5_XLD 0x20
284#define FMR5_XLU 0x10
285
286
287/* LOOP (Channel Loop Back)
288
289 ------------------ E1 & T1 ---------------------------- */
290
291#define LOOP_SFM 0x40
292#define LOOP_ECLB 0x20
293#define LOOP_CLA4 0x10
294#define LOOP_CLA3 0x08
295#define LOOP_CLA2 0x04
296#define LOOP_CLA1 0x02
297#define LOOP_CLA0 0x01
298
299
300
301/* XSW (Transmit Service Word Pulseframe)
302
303 ------------------- E1 --------------------------- */
304
305#define XSW_XSIS 0x80
306#define XSW_XTM 0x40
307#define XSW_XRA 0x20
308#define XSW_XY0 0x10
309#define XSW_XY1 0x08
310#define XSW_XY2 0x04
311#define XSW_XY3 0x02
312#define XSW_XY4 0x01
313
314
315/* XSP (Transmit Spare Bits)
316
317 ------------------- E1 --------------------------- */
318
319#define XSP_XAP 0x80
320#define XSP_CASEN 0x40
321#define XSP_TT0 0x20
322#define XSP_EBP 0x10
323#define XSP_AXS 0x08
324#define XSP_XSIF 0x04
325#define XSP_XS13 0x02
326#define XSP_XS15 0x01
327
328
329/* XC0/1 (Transmit Control 0/1)
330 ------------------ E1 & T1 ---------------------------- */
331
332#define XC0_SA8E 0x80
333#define XC0_SA7E 0x40
334#define XC0_SA6E 0x20
335#define XC0_SA5E 0x10
336#define XC0_SA4E 0x08
337#define XC0_BRM 0x80
338#define XC0_MFBS 0x40
339#define XC0_SFRZ 0x10
340#define XC0_XCO2 0x04
341#define XC0_XCO1 0x02
342#define XC0_XCO0 0x01
343
344#define XC1_XTO5 0x20
345#define XC1_XTO4 0x10
346#define XC1_XTO3 0x08
347#define XC1_XTO2 0x04
348#define XC1_XTO1 0x02
349#define XC1_XTO0 0x01
350
351
352/* RC0/1 (Receive Control 0/1)
353 ------------------ E1 & T1 ---------------------------- */
354
355#define RC0_SICS 0x40
356#define RC0_CRCI 0x20
357#define RC0_XCRCI 0x10
358#define RC0_RDIS 0x08
359#define RC0_RCO2 0x04
360#define RC0_RCO1 0x02
361#define RC0_RCO0 0x01
362
363#define RC1_SWD 0x80
364#define RC1_ASY4 0x40
365#define RC1_RRAM 0x40
366#define RC1_RTO5 0x20
367#define RC1_RTO4 0x10
368#define RC1_RTO3 0x08
369#define RC1_RTO2 0x04
370#define RC1_RTO1 0x02
371#define RC1_RTO0 0x01
372
373
374
375/* XPM0-2 (Transmit Pulse Mask 0-2)
376 --------------------- E1 & T1 ------------------------- */
377
378#define XPM0_XP12 0x80
379#define XPM0_XP11 0x40
380#define XPM0_XP10 0x20
381#define XPM0_XP04 0x10
382#define XPM0_XP03 0x08
383#define XPM0_XP02 0x04
384#define XPM0_XP01 0x02
385#define XPM0_XP00 0x01
386
387#define XPM1_XP30 0x80
388#define XPM1_XP24 0x40
389#define XPM1_XP23 0x20
390#define XPM1_XP22 0x10
391#define XPM1_XP21 0x08
392#define XPM1_XP20 0x04
393#define XPM1_XP14 0x02
394#define XPM1_XP13 0x01
395
396#define XPM2_XLHP 0x80
397#define XPM2_XLT 0x40
398#define XPM2_DAXLT 0x20
399#define XPM2_XP34 0x08
400#define XPM2_XP33 0x04
401#define XPM2_XP32 0x02
402#define XPM2_XP31 0x01
403
404
405/* TSWM (Transparent Service Word Mask)
406 ------------------ E1 ---------------------------- */
407
408#define TSWM_TSIS 0x80
409#define TSWM_TSIF 0x40
410#define TSWM_TRA 0x20
411#define TSWM_TSA4 0x10
412#define TSWM_TSA5 0x08
413#define TSWM_TSA6 0x04
414#define TSWM_TSA7 0x02
415#define TSWM_TSA8 0x01
416
417/* IDLE <Idle Channel Code Register>
418
419 ------------------ E1 & T1 ----------------------- */
420
421#define IDLE_IDL7 0x80
422#define IDLE_IDL6 0x40
423#define IDLE_IDL5 0x20
424#define IDLE_IDL4 0x10
425#define IDLE_IDL3 0x08
426#define IDLE_IDL2 0x04
427#define IDLE_IDL1 0x02
428#define IDLE_IDL0 0x01
429
430
431/* XSA4-8 <Transmit SA4-8 Register(Read/Write) >
432 -------------------E1 ----------------------------- */
433
434#define XSA4_XS47 0x80
435#define XSA4_XS46 0x40
436#define XSA4_XS45 0x20
437#define XSA4_XS44 0x10
438#define XSA4_XS43 0x08
439#define XSA4_XS42 0x04
440#define XSA4_XS41 0x02
441#define XSA4_XS40 0x01
442
443#define XSA5_XS57 0x80
444#define XSA5_XS56 0x40
445#define XSA5_XS55 0x20
446#define XSA5_XS54 0x10
447#define XSA5_XS53 0x08
448#define XSA5_XS52 0x04
449#define XSA5_XS51 0x02
450#define XSA5_XS50 0x01
451
452#define XSA6_XS67 0x80
453#define XSA6_XS66 0x40
454#define XSA6_XS65 0x20
455#define XSA6_XS64 0x10
456#define XSA6_XS63 0x08
457#define XSA6_XS62 0x04
458#define XSA6_XS61 0x02
459#define XSA6_XS60 0x01
460
461#define XSA7_XS77 0x80
462#define XSA7_XS76 0x40
463#define XSA7_XS75 0x20
464#define XSA7_XS74 0x10
465#define XSA7_XS73 0x08
466#define XSA7_XS72 0x04
467#define XSA7_XS71 0x02
468#define XSA7_XS70 0x01
469
470#define XSA8_XS87 0x80
471#define XSA8_XS86 0x40
472#define XSA8_XS85 0x20
473#define XSA8_XS84 0x10
474#define XSA8_XS83 0x08
475#define XSA8_XS82 0x04
476#define XSA8_XS81 0x02
477#define XSA8_XS80 0x01
478
479
480/* XDL1-3 (Transmit DL-Bit Register1-3 (read/write))
481 ----------------------- T1 --------------------- */
482
483#define XDL1_XDL17 0x80
484#define XDL1_XDL16 0x40
485#define XDL1_XDL15 0x20
486#define XDL1_XDL14 0x10
487#define XDL1_XDL13 0x08
488#define XDL1_XDL12 0x04
489#define XDL1_XDL11 0x02
490#define XDL1_XDL10 0x01
491
492#define XDL2_XDL27 0x80
493#define XDL2_XDL26 0x40
494#define XDL2_XDL25 0x20
495#define XDL2_XDL24 0x10
496#define XDL2_XDL23 0x08
497#define XDL2_XDL22 0x04
498#define XDL2_XDL21 0x02
499#define XDL2_XDL20 0x01
500
501#define XDL3_XDL37 0x80
502#define XDL3_XDL36 0x40
503#define XDL3_XDL35 0x20
504#define XDL3_XDL34 0x10
505#define XDL3_XDL33 0x08
506#define XDL3_XDL32 0x04
507#define XDL3_XDL31 0x02
508#define XDL3_XDL30 0x01
509
510
511/* ICB1-4 (Idle Channel Register 1-4)
512 ------------------ E1 ---------------------------- */
513
514#define E1_ICB1_IC0 0x80
515#define E1_ICB1_IC1 0x40
516#define E1_ICB1_IC2 0x20
517#define E1_ICB1_IC3 0x10
518#define E1_ICB1_IC4 0x08
519#define E1_ICB1_IC5 0x04
520#define E1_ICB1_IC6 0x02
521#define E1_ICB1_IC7 0x01
522
523#define E1_ICB2_IC8 0x80
524#define E1_ICB2_IC9 0x40
525#define E1_ICB2_IC10 0x20
526#define E1_ICB2_IC11 0x10
527#define E1_ICB2_IC12 0x08
528#define E1_ICB2_IC13 0x04
529#define E1_ICB2_IC14 0x02
530#define E1_ICB2_IC15 0x01
531
532#define E1_ICB3_IC16 0x80
533#define E1_ICB3_IC17 0x40
534#define E1_ICB3_IC18 0x20
535#define E1_ICB3_IC19 0x10
536#define E1_ICB3_IC20 0x08
537#define E1_ICB3_IC21 0x04
538#define E1_ICB3_IC22 0x02
539#define E1_ICB3_IC23 0x01
540
541#define E1_ICB4_IC24 0x80
542#define E1_ICB4_IC25 0x40
543#define E1_ICB4_IC26 0x20
544#define E1_ICB4_IC27 0x10
545#define E1_ICB4_IC28 0x08
546#define E1_ICB4_IC29 0x04
547#define E1_ICB4_IC30 0x02
548#define E1_ICB4_IC31 0x01
549
550/* ICB1-4 (Idle Channel Register 1-4)
551 ------------------ T1 ---------------------------- */
552
553#define T1_ICB1_IC1 0x80
554#define T1_ICB1_IC2 0x40
555#define T1_ICB1_IC3 0x20
556#define T1_ICB1_IC4 0x10
557#define T1_ICB1_IC5 0x08
558#define T1_ICB1_IC6 0x04
559#define T1_ICB1_IC7 0x02
560#define T1_ICB1_IC8 0x01
561
562#define T1_ICB2_IC9 0x80
563#define T1_ICB2_IC10 0x40
564#define T1_ICB2_IC11 0x20
565#define T1_ICB2_IC12 0x10
566#define T1_ICB2_IC13 0x08
567#define T1_ICB2_IC14 0x04
568#define T1_ICB2_IC15 0x02
569#define T1_ICB2_IC16 0x01
570
571#define T1_ICB3_IC17 0x80
572#define T1_ICB3_IC18 0x40
573#define T1_ICB3_IC19 0x20
574#define T1_ICB3_IC20 0x10
575#define T1_ICB3_IC21 0x08
576#define T1_ICB3_IC22 0x04
577#define T1_ICB3_IC23 0x02
578#define T1_ICB3_IC24 0x01
579
580/* FMR3 (Framer Mode Register 3)
581 --------------------E1------------------------ */
582
583#define FMR3_CMI 0x08
584#define FMR3_SYNSA 0x04
585#define FMR3_CFRZ 0x02
586#define FMR3_EXTIW 0x01
587
588
589
590/* CCB1-3 (Clear Channel Register)
591 ------------------- T1 ----------------------- */
592
593#define CCB1_CH1 0x80
594#define CCB1_CH2 0x40
595#define CCB1_CH3 0x20
596#define CCB1_CH4 0x10
597#define CCB1_CH5 0x08
598#define CCB1_CH6 0x04
599#define CCB1_CH7 0x02
600#define CCB1_CH8 0x01
601
602#define CCB2_CH9 0x80
603#define CCB2_CH10 0x40
604#define CCB2_CH11 0x20
605#define CCB2_CH12 0x10
606#define CCB2_CH13 0x08
607#define CCB2_CH14 0x04
608#define CCB2_CH15 0x02
609#define CCB2_CH16 0x01
610
611#define CCB3_CH17 0x80
612#define CCB3_CH18 0x40
613#define CCB3_CH19 0x20
614#define CCB3_CH20 0x10
615#define CCB3_CH21 0x08
616#define CCB3_CH22 0x04
617#define CCB3_CH23 0x02
618#define CCB3_CH24 0x01
619
620
621/* LIM0/1 (Line Interface Mode 0/1)
622 ------------------- E1 & T1 --------------------------- */
623
624#define LIM0_XFB 0x80
625#define LIM0_XDOS 0x40
626#define LIM0_SCL1 0x20
627#define LIM0_SCL0 0x10
628#define LIM0_EQON 0x08
629#define LIM0_ELOS 0x04
630#define LIM0_LL 0x02
631#define LIM0_MAS 0x01
632
633#define LIM1_EFSC 0x80
634#define LIM1_RIL2 0x40
635#define LIM1_RIL1 0x20
636#define LIM1_RIL0 0x10
637#define LIM1_DCOC 0x08
638#define LIM1_JATT 0x04
639#define LIM1_RL 0x02
640#define LIM1_DRS 0x01
641
642
643/* PCDR (Pulse Count Detection Register(Read/Write))
644 ------------------ E1 & T1 ------------------------- */
645
646#define PCDR_PCD7 0x80
647#define PCDR_PCD6 0x40
648#define PCDR_PCD5 0x20
649#define PCDR_PCD4 0x10
650#define PCDR_PCD3 0x08
651#define PCDR_PCD2 0x04
652#define PCDR_PCD1 0x02
653#define PCDR_PCD0 0x01
654
655#define PCRR_PCR7 0x80
656#define PCRR_PCR6 0x40
657#define PCRR_PCR5 0x20
658#define PCRR_PCR4 0x10
659#define PCRR_PCR3 0x08
660#define PCRR_PCR2 0x04
661#define PCRR_PCR1 0x02
662#define PCRR_PCR0 0x01
663
664
665/* LIM2 (Line Interface Mode 2)
666
667 ------------------ E1 & T1 ---------------------------- */
668
669#define LIM2_DJA2 0x20
670#define LIM2_DJA1 0x10
671#define LIM2_LOS2 0x02
672#define LIM2_LOS1 0x01
673
674/* LCR1 (Loop Code Register 1) */
675
676#define LCR1_EPRM 0x80
677#define LCR1_XPRBS 0x40
678
679/* SIC1 (System Interface Control 1) */
680#define SIC1_SRSC 0x80
681#define SIC1_RBS1 0x20
682#define SIC1_RBS0 0x10
683#define SIC1_SXSC 0x08
684#define SIC1_XBS1 0x02
685#define SIC1_XBS0 0x01
686
687/* DEC (Disable Error Counter)
688 ------------------ E1 & T1 ---------------------------- */
689
690#define DEC_DCEC3 0x20
691#define DEC_DBEC 0x10
692#define DEC_DCEC1 0x08
693#define DEC_DCEC 0x08
694#define DEC_DEBC 0x04
695#define DEC_DCVC 0x02
696#define DEC_DFEC 0x01
697
698
699/* FALC Register Bits (Receive Mode)
700 ---------------------------------------------------------------------------- */
701
702
703/* FRS0/1 (Framer Receive Status Register 0/1)
704 ----------------- E1 & T1 ---------------------------------- */
705
706#define FRS0_LOS 0x80
707#define FRS0_AIS 0x40
708#define FRS0_LFA 0x20
709#define FRS0_RRA 0x10
710#define FRS0_API 0x08
711#define FRS0_NMF 0x04
712#define FRS0_LMFA 0x02
713#define FRS0_FSRF 0x01
714
715#define FRS1_TS16RA 0x40
716#define FRS1_TS16LOS 0x20
717#define FRS1_TS16AIS 0x10
718#define FRS1_TS16LFA 0x08
719#define FRS1_EXZD 0x80
720#define FRS1_LLBDD 0x10
721#define FRS1_LLBAD 0x08
722#define FRS1_XLS 0x02
723#define FRS1_XLO 0x01
724#define FRS1_PDEN 0x40
725
726/* FRS2/3 (Framer Receive Status Register 2/3)
727 ----------------- T1 ---------------------------------- */
728
729#define FRS2_ESC2 0x80
730#define FRS2_ESC1 0x40
731#define FRS2_ESC0 0x20
732
733#define FRS3_FEH5 0x20
734#define FRS3_FEH4 0x10
735#define FRS3_FEH3 0x08
736#define FRS3_FEH2 0x04
737#define FRS3_FEH1 0x02
738#define FRS3_FEH0 0x01
739
740
741/* RSW (Receive Service Word Pulseframe)
742 ----------------- E1 ------------------------------ */
743
744#define RSW_RSI 0x80
745#define RSW_RRA 0x20
746#define RSW_RYO 0x10
747#define RSW_RY1 0x08
748#define RSW_RY2 0x04
749#define RSW_RY3 0x02
750#define RSW_RY4 0x01
751
752
753/* RSP (Receive Spare Bits / Additional Status)
754 ---------------- E1 ------------------------------- */
755
756#define RSP_SI1 0x80
757#define RSP_SI2 0x40
758#define RSP_LLBDD 0x10
759#define RSP_LLBAD 0x08
760#define RSP_RSIF 0x04
761#define RSP_RS13 0x02
762#define RSP_RS15 0x01
763
764
765/* FECL (Framing Error Counter)
766 ---------------- E1 & T1 -------------------------- */
767
768#define FECL_FE7 0x80
769#define FECL_FE6 0x40
770#define FECL_FE5 0x20
771#define FECL_FE4 0x10
772#define FECL_FE3 0x08
773#define FECL_FE2 0x04
774#define FECL_FE1 0x02
775#define FECL_FE0 0x01
776
777#define FECH_FE15 0x80
778#define FECH_FE14 0x40
779#define FECH_FE13 0x20
780#define FECH_FE12 0x10
781#define FECH_FE11 0x08
782#define FECH_FE10 0x04
783#define FECH_FE9 0x02
784#define FECH_FE8 0x01
785
786
787/* CVCl (Code Violation Counter)
788 ----------------- E1 ------------------------- */
789
790#define CVCL_CV7 0x80
791#define CVCL_CV6 0x40
792#define CVCL_CV5 0x20
793#define CVCL_CV4 0x10
794#define CVCL_CV3 0x08
795#define CVCL_CV2 0x04
796#define CVCL_CV1 0x02
797#define CVCL_CV0 0x01
798
799#define CVCH_CV15 0x80
800#define CVCH_CV14 0x40
801#define CVCH_CV13 0x20
802#define CVCH_CV12 0x10
803#define CVCH_CV11 0x08
804#define CVCH_CV10 0x04
805#define CVCH_CV9 0x02
806#define CVCH_CV8 0x01
807
808
809/* CEC1-3L (CRC Error Counter)
810 ------------------ E1 ----------------------------- */
811
812#define CEC1L_CR7 0x80
813#define CEC1L_CR6 0x40
814#define CEC1L_CR5 0x20
815#define CEC1L_CR4 0x10
816#define CEC1L_CR3 0x08
817#define CEC1L_CR2 0x04
818#define CEC1L_CR1 0x02
819#define CEC1L_CR0 0x01
820
821#define CEC1H_CR15 0x80
822#define CEC1H_CR14 0x40
823#define CEC1H_CR13 0x20
824#define CEC1H_CR12 0x10
825#define CEC1H_CR11 0x08
826#define CEC1H_CR10 0x04
827#define CEC1H_CR9 0x02
828#define CEC1H_CR8 0x01
829
830#define CEC2L_CR7 0x80
831#define CEC2L_CR6 0x40
832#define CEC2L_CR5 0x20
833#define CEC2L_CR4 0x10
834#define CEC2L_CR3 0x08
835#define CEC2L_CR2 0x04
836#define CEC2L_CR1 0x02
837#define CEC2L_CR0 0x01
838
839#define CEC2H_CR15 0x80
840#define CEC2H_CR14 0x40
841#define CEC2H_CR13 0x20
842#define CEC2H_CR12 0x10
843#define CEC2H_CR11 0x08
844#define CEC2H_CR10 0x04
845#define CEC2H_CR9 0x02
846#define CEC2H_CR8 0x01
847
848#define CEC3L_CR7 0x80
849#define CEC3L_CR6 0x40
850#define CEC3L_CR5 0x20
851#define CEC3L_CR4 0x10
852#define CEC3L_CR3 0x08
853#define CEC3L_CR2 0x04
854#define CEC3L_CR1 0x02
855#define CEC3L_CR0 0x01
856
857#define CEC3H_CR15 0x80
858#define CEC3H_CR14 0x40
859#define CEC3H_CR13 0x20
860#define CEC3H_CR12 0x10
861#define CEC3H_CR11 0x08
862#define CEC3H_CR10 0x04
863#define CEC3H_CR9 0x02
864#define CEC3H_CR8 0x01
865
866
867/* CECL (CRC Error Counter)
868
869 ------------------ T1 ----------------------------- */
870
871#define CECL_CR7 0x80
872#define CECL_CR6 0x40
873#define CECL_CR5 0x20
874#define CECL_CR4 0x10
875#define CECL_CR3 0x08
876#define CECL_CR2 0x04
877#define CECL_CR1 0x02
878#define CECL_CR0 0x01
879
880#define CECH_CR15 0x80
881#define CECH_CR14 0x40
882#define CECH_CR13 0x20
883#define CECH_CR12 0x10
884#define CECH_CR11 0x08
885#define CECH_CR10 0x04
886#define CECH_CR9 0x02
887#define CECH_CR8 0x01
888
889/* EBCL (E Bit Error Counter)
890 ------------------- E1 & T1 ------------------------- */
891
892#define EBCL_EB7 0x80
893#define EBCL_EB6 0x40
894#define EBCL_EB5 0x20
895#define EBCL_EB4 0x10
896#define EBCL_EB3 0x08
897#define EBCL_EB2 0x04
898#define EBCL_EB1 0x02
899#define EBCL_EB0 0x01
900
901#define EBCH_EB15 0x80
902#define EBCH_EB14 0x40
903#define EBCH_EB13 0x20
904#define EBCH_EB12 0x10
905#define EBCH_EB11 0x08
906#define EBCH_EB10 0x04
907#define EBCH_EB9 0x02
908#define EBCH_EB8 0x01
909
910
911/* RSA4-8 (Receive Sa4-8-Bit Register)
912 -------------------- E1 --------------------------- */
913
914#define RSA4_RS47 0x80
915#define RSA4_RS46 0x40
916#define RSA4_RS45 0x20
917#define RSA4_RS44 0x10
918#define RSA4_RS43 0x08
919#define RSA4_RS42 0x04
920#define RSA4_RS41 0x02
921#define RSA4_RS40 0x01
922
923#define RSA5_RS57 0x80
924#define RSA5_RS56 0x40
925#define RSA5_RS55 0x20
926#define RSA5_RS54 0x10
927#define RSA5_RS53 0x08
928#define RSA5_RS52 0x04
929#define RSA5_RS51 0x02
930#define RSA5_RS50 0x01
931
932#define RSA6_RS67 0x80
933#define RSA6_RS66 0x40
934#define RSA6_RS65 0x20
935#define RSA6_RS64 0x10
936#define RSA6_RS63 0x08
937#define RSA6_RS62 0x04
938#define RSA6_RS61 0x02
939#define RSA6_RS60 0x01
940
941#define RSA7_RS77 0x80
942#define RSA7_RS76 0x40
943#define RSA7_RS75 0x20
944#define RSA7_RS74 0x10
945#define RSA7_RS73 0x08
946#define RSA7_RS72 0x04
947#define RSA7_RS71 0x02
948#define RSA7_RS70 0x01
949
950#define RSA8_RS87 0x80
951#define RSA8_RS86 0x40
952#define RSA8_RS85 0x20
953#define RSA8_RS84 0x10
954#define RSA8_RS83 0x08
955#define RSA8_RS82 0x04
956#define RSA8_RS81 0x02
957#define RSA8_RS80 0x01
958
959/* RSA6S (Receive Sa6 Bit Status Register)
960 ------------------------ T1 ------------------------- */
961
962#define RSA6S_SX 0x20
963#define RSA6S_SF 0x10
964#define RSA6S_SE 0x08
965#define RSA6S_SC 0x04
966#define RSA6S_SA 0x02
967#define RSA6S_S8 0x01
968
969
970/* RDL1-3 Receive DL-Bit Register1-3)
971 ------------------------ T1 ------------------------- */
972
973#define RDL1_RDL17 0x80
974#define RDL1_RDL16 0x40
975#define RDL1_RDL15 0x20
976#define RDL1_RDL14 0x10
977#define RDL1_RDL13 0x08
978#define RDL1_RDL12 0x04
979#define RDL1_RDL11 0x02
980#define RDL1_RDL10 0x01
981
982#define RDL2_RDL27 0x80
983#define RDL2_RDL26 0x40
984#define RDL2_RDL25 0x20
985#define RDL2_RDL24 0x10
986#define RDL2_RDL23 0x08
987#define RDL2_RDL22 0x04
988#define RDL2_RDL21 0x02
989#define RDL2_RDL20 0x01
990
991#define RDL3_RDL37 0x80
992#define RDL3_RDL36 0x40
993#define RDL3_RDL35 0x20
994#define RDL3_RDL34 0x10
995#define RDL3_RDL33 0x08
996#define RDL3_RDL32 0x04
997#define RDL3_RDL31 0x02
998#define RDL3_RDL30 0x01
999
1000
1001/* SIS (Signaling Status Register)
1002
1003 -------------------- E1 & T1 -------------------------- */
1004
1005#define SIS_XDOV 0x80
1006#define SIS_XFW 0x40
1007#define SIS_XREP 0x20
1008#define SIS_RLI 0x08
1009#define SIS_CEC 0x04
1010#define SIS_BOM 0x01
1011
1012
1013/* RSIS (Receive Signaling Status Register)
1014
1015 -------------------- E1 & T1 --------------------------- */
1016
1017#define RSIS_VFR 0x80
1018#define RSIS_RDO 0x40
1019#define RSIS_CRC16 0x20
1020#define RSIS_RAB 0x10
1021#define RSIS_HA1 0x08
1022#define RSIS_HA0 0x04
1023#define RSIS_HFR 0x02
1024#define RSIS_LA 0x01
1025
1026
1027/* RBCL/H (Receive Byte Count Low/High)
1028
1029 ------------------- E1 & T1 ----------------------- */
1030
1031#define RBCL_RBC7 0x80
1032#define RBCL_RBC6 0x40
1033#define RBCL_RBC5 0x20
1034#define RBCL_RBC4 0x10
1035#define RBCL_RBC3 0x08
1036#define RBCL_RBC2 0x04
1037#define RBCL_RBC1 0x02
1038#define RBCL_RBC0 0x01
1039
1040#define RBCH_OV 0x10
1041#define RBCH_RBC11 0x08
1042#define RBCH_RBC10 0x04
1043#define RBCH_RBC9 0x02
1044#define RBCH_RBC8 0x01
1045
1046
1047/* ISR1-3 (Interrupt Status Register 1-3)
1048
1049 ------------------ E1 & T1 ------------------------------ */
1050
1051#define FISR0_RME 0x80
1052#define FISR0_RFS 0x40
1053#define FISR0_T8MS 0x20
1054#define FISR0_ISF 0x20
1055#define FISR0_RMB 0x10
1056#define FISR0_CASC 0x08
1057#define FISR0_RSC 0x08
1058#define FISR0_CRC6 0x04
1059#define FISR0_CRC4 0x04
1060#define FISR0_PDEN 0x02
1061#define FISR0_RPF 0x01
1062
1063#define FISR1_CASE 0x80
1064#define FISR1_LLBSC 0x80
1065#define FISR1_RDO 0x40
1066#define FISR1_ALLS 0x20
1067#define FISR1_XDU 0x10
1068#define FISR1_XMB 0x08
1069#define FISR1_XLSC 0x02
1070#define FISR1_XPR 0x01
1071
1072#define FISR2_FAR 0x80
1073#define FISR2_LFA 0x40
1074#define FISR2_MFAR 0x20
1075#define FISR2_T400MS 0x10
1076#define FISR2_LMFA 0x10
1077#define FISR2_AIS 0x08
1078#define FISR2_LOS 0x04
1079#define FISR2_RAR 0x02
1080#define FISR2_RA 0x01
1081
1082#define FISR3_ES 0x80
1083#define FISR3_SEC 0x40
1084#define FISR3_LMFA16 0x20
1085#define FISR3_AIS16 0x10
1086#define FISR3_RA16 0x08
1087#define FISR3_API 0x04
1088#define FISR3_XSLP 0x20
1089#define FISR3_XSLN 0x10
1090#define FISR3_LLBSC 0x08
1091#define FISR3_XRS 0x04
1092#define FISR3_SLN 0x02
1093#define FISR3_SLP 0x01
1094
1095
1096/* GIS (Global Interrupt Status Register)
1097
1098 --------------------- E1 & T1 --------------------- */
1099
1100#define GIS_ISR3 0x08
1101#define GIS_ISR2 0x04
1102#define GIS_ISR1 0x02
1103#define GIS_ISR0 0x01
1104
1105
1106/* VSTR (Version Status Register)
1107
1108 --------------------- E1 & T1 --------------------- */
1109
1110#define VSTR_VN3 0x08
1111#define VSTR_VN2 0x04
1112#define VSTR_VN1 0x02
1113#define VSTR_VN0 0x01
1114
1115
1116/*>>>>>>>>>>>>>>>>>>>>> Local Control Structures <<<<<<<<<<<<<<<<<<<<<<<<< */
1117
1118/* Write-only Registers (E1/T1 control mode write registers) */
1119#define XFIFOH 0x00 /* Tx FIFO High Byte */
1120#define XFIFOL 0x01 /* Tx FIFO Low Byte */
1121#define CMDR 0x02 /* Command Reg */
1122#define DEC 0x60 /* Disable Error Counter */
1123#define TEST2 0x62 /* Manuf. Test Reg 2 */
1124#define XS(nbr) (0x70 + (nbr)) /* Tx CAS Reg (0 to 15) */
1125
1126/* Read-write Registers (E1/T1 status mode read registers) */
1127#define MODE 0x03 /* Mode Reg */
1128#define RAH1 0x04 /* Receive Address High 1 */
1129#define RAH2 0x05 /* Receive Address High 2 */
1130#define RAL1 0x06 /* Receive Address Low 1 */
1131#define RAL2 0x07 /* Receive Address Low 2 */
1132#define IPC 0x08 /* Interrupt Port Configuration */
1133#define CCR1 0x09 /* Common Configuration Reg 1 */
1134#define CCR3 0x0A /* Common Configuration Reg 3 */
1135#define PRE 0x0B /* Preamble Reg */
1136#define RTR1 0x0C /* Receive Timeslot Reg 1 */
1137#define RTR2 0x0D /* Receive Timeslot Reg 2 */
1138#define RTR3 0x0E /* Receive Timeslot Reg 3 */
1139#define RTR4 0x0F /* Receive Timeslot Reg 4 */
1140#define TTR1 0x10 /* Transmit Timeslot Reg 1 */
1141#define TTR2 0x11 /* Transmit Timeslot Reg 2 */
1142#define TTR3 0x12 /* Transmit Timeslot Reg 3 */
1143#define TTR4 0x13 /* Transmit Timeslot Reg 4 */
1144#define IMR0 0x14 /* Interrupt Mask Reg 0 */
1145#define IMR1 0x15 /* Interrupt Mask Reg 1 */
1146#define IMR2 0x16 /* Interrupt Mask Reg 2 */
1147#define IMR3 0x17 /* Interrupt Mask Reg 3 */
1148#define IMR4 0x18 /* Interrupt Mask Reg 4 */
1149#define IMR5 0x19 /* Interrupt Mask Reg 5 */
1150#define FMR0 0x1A /* Framer Mode Reigster 0 */
1151#define FMR1 0x1B /* Framer Mode Reigster 1 */
1152#define FMR2 0x1C /* Framer Mode Reigster 2 */
1153#define LOOP 0x1D /* Channel Loop Back */
1154#define XSW 0x1E /* Transmit Service Word */
1155#define FMR4 0x1E /* Framer Mode Reg 4 */
1156#define XSP 0x1F /* Transmit Spare Bits */
1157#define FMR5 0x1F /* Framer Mode Reg 5 */
1158#define XC0 0x20 /* Transmit Control 0 */
1159#define XC1 0x21 /* Transmit Control 1 */
1160#define RC0 0x22 /* Receive Control 0 */
1161#define RC1 0x23 /* Receive Control 1 */
1162#define XPM0 0x24 /* Transmit Pulse Mask 0 */
1163#define XPM1 0x25 /* Transmit Pulse Mask 1 */
1164#define XPM2 0x26 /* Transmit Pulse Mask 2 */
1165#define TSWM 0x27 /* Transparent Service Word Mask */
1166#define TEST1 0x28 /* Manuf. Test Reg 1 */
1167#define IDLE 0x29 /* Idle Channel Code */
1168#define XSA4 0x2A /* Transmit SA4 Bit Reg */
1169#define XDL1 0x2A /* Transmit DL-Bit Reg 2 */
1170#define XSA5 0x2B /* Transmit SA4 Bit Reg */
1171#define XDL2 0x2B /* Transmit DL-Bit Reg 2 */
1172#define XSA6 0x2C /* Transmit SA4 Bit Reg */
1173#define XDL3 0x2C /* Transmit DL-Bit Reg 2 */
1174#define XSA7 0x2D /* Transmit SA4 Bit Reg */
1175#define CCB1 0x2D /* Clear Channel Reg 1 */
1176#define XSA8 0x2E /* Transmit SA4 Bit Reg */
1177#define CCB2 0x2E /* Clear Channel Reg 2 */
1178#define FMR3 0x2F /* Framer Mode Reg. 3 */
1179#define CCB3 0x2F /* Clear Channel Reg 3 */
1180#define ICB1 0x30 /* Idle Channel Reg 1 */
1181#define ICB2 0x31 /* Idle Channel Reg 2 */
1182#define ICB3 0x32 /* Idle Channel Reg 3 */
1183#define ICB4 0x33 /* Idle Channel Reg 4 */
1184#define LIM0 0x34 /* Line Interface Mode 0 */
1185#define LIM1 0x35 /* Line Interface Mode 1 */
1186#define PCDR 0x36 /* Pulse Count Detection */
1187#define PCRR 0x37 /* Pulse Count Recovery */
1188#define LIM2 0x38 /* Line Interface Mode Reg 2 */
1189#define LCR1 0x39 /* Loop Code Reg 1 */
1190#define LCR2 0x3A /* Loop Code Reg 2 */
1191#define LCR3 0x3B /* Loop Code Reg 3 */
1192#define SIC1 0x3C /* System Interface Control 1 */
1193
1194/* Read-only Registers (E1/T1 control mode read registers) */
1195#define RFIFOH 0x00 /* Receive FIFO */
1196#define RFIFOL 0x01 /* Receive FIFO */
1197#define FRS0 0x4C /* Framer Receive Status 0 */
1198#define FRS1 0x4D /* Framer Receive Status 1 */
1199#define RSW 0x4E /* Receive Service Word */
1200#define FRS2 0x4E /* Framer Receive Status 2 */
1201#define RSP 0x4F /* Receive Spare Bits */
1202#define FRS3 0x4F /* Framer Receive Status 3 */
1203#define FECL 0x50 /* Framing Error Counter */
1204#define FECH 0x51 /* Framing Error Counter */
1205#define CVCL 0x52 /* Code Violation Counter */
1206#define CVCH 0x53 /* Code Violation Counter */
1207#define CECL 0x54 /* CRC Error Counter 1 */
1208#define CECH 0x55 /* CRC Error Counter 1 */
1209#define EBCL 0x56 /* E-Bit Error Counter */
1210#define EBCH 0x57 /* E-Bit Error Counter */
1211#define BECL 0x58 /* Bit Error Counter Low */
1212#define BECH 0x59 /* Bit Error Counter Low */
1213#define CEC3 0x5A /* CRC Error Counter 3 (16-bit) */
1214#define RSA4 0x5C /* Receive SA4 Bit Reg */
1215#define RDL1 0x5C /* Receive DL-Bit Reg 1 */
1216#define RSA5 0x5D /* Receive SA5 Bit Reg */
1217#define RDL2 0x5D /* Receive DL-Bit Reg 2 */
1218#define RSA6 0x5E /* Receive SA6 Bit Reg */
1219#define RDL3 0x5E /* Receive DL-Bit Reg 3 */
1220#define RSA7 0x5F /* Receive SA7 Bit Reg */
1221#define RSA8 0x60 /* Receive SA8 Bit Reg */
1222#define RSA6S 0x61 /* Receive SA6 Bit Status Reg */
1223#define TSR0 0x62 /* Manuf. Test Reg 0 */
1224#define TSR1 0x63 /* Manuf. Test Reg 1 */
1225#define SIS 0x64 /* Signaling Status Reg */
1226#define RSIS 0x65 /* Receive Signaling Status Reg */
1227#define RBCL 0x66 /* Receive Byte Control */
1228#define RBCH 0x67 /* Receive Byte Control */
1229#define FISR0 0x68 /* Interrupt Status Reg 0 */
1230#define FISR1 0x69 /* Interrupt Status Reg 1 */
1231#define FISR2 0x6A /* Interrupt Status Reg 2 */
1232#define FISR3 0x6B /* Interrupt Status Reg 3 */
1233#define GIS 0x6E /* Global Interrupt Status */
1234#define VSTR 0x6F /* Version Status */
1235#define RS(nbr) (0x70 + (nbr)) /* Rx CAS Reg (0 to 15) */
1236
1237#endif /* _FALC_LH_H */
1238
diff --git a/drivers/net/wan/pc300.h b/drivers/net/wan/pc300.h
deleted file mode 100644
index 2e4f84f6cad..00000000000
--- a/drivers/net/wan/pc300.h
+++ /dev/null
@@ -1,436 +0,0 @@
1/*
2 * pc300.h Cyclades-PC300(tm) Kernel API Definitions.
3 *
4 * Author: Ivan Passos <ivan@cyclades.com>
5 *
6 * Copyright: (c) 1999-2002 Cyclades Corp.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * as published by the Free Software Foundation; either version
11 * 2 of the License, or (at your option) any later version.
12 *
13 * $Log: pc300.h,v $
14 * Revision 3.12 2002/03/07 14:17:09 henrique
15 * License data fixed
16 *
17 * Revision 3.11 2002/01/28 21:09:39 daniela
18 * Included ';' after pc300hw.bus.
19 *
20 * Revision 3.10 2002/01/17 17:58:52 ivan
21 * Support for PC300-TE/M (PMC).
22 *
23 * Revision 3.9 2001/09/28 13:30:53 daniela
24 * Renamed dma_start routine to rx_dma_start.
25 *
26 * Revision 3.8 2001/09/24 13:03:45 daniela
27 * Fixed BOF interrupt treatment. Created dma_start routine.
28 *
29 * Revision 3.7 2001/08/10 17:19:58 daniela
30 * Fixed IOCTLs defines.
31 *
32 * Revision 3.6 2001/07/18 19:24:42 daniela
33 * Included kernel version.
34 *
35 * Revision 3.5 2001/07/05 18:38:08 daniela
36 * DMA transmission bug fix.
37 *
38 * Revision 3.4 2001/06/26 17:10:40 daniela
39 * New configuration parameters (line code, CRC calculation and clock).
40 *
41 * Revision 3.3 2001/06/22 13:13:02 regina
42 * MLPPP implementation
43 *
44 * Revision 3.2 2001/06/18 17:56:09 daniela
45 * Increased DEF_MTU and TX_QUEUE_LEN.
46 *
47 * Revision 3.1 2001/06/15 12:41:10 regina
48 * upping major version number
49 *
50 * Revision 1.1.1.1 2001/06/13 20:25:06 daniela
51 * PC300 initial CVS version (3.4.0-pre1)
52 *
53 * Revision 2.3 2001/03/05 daniela
54 * Created struct pc300conf, to provide the hardware information to pc300util.
55 * Inclusion of 'alloc_ramsize' field on structure 'pc300hw'.
56 *
57 * Revision 2.2 2000/12/22 daniela
58 * Structures and defines to support pc300util: statistics, status,
59 * loopback tests, trace.
60 *
61 * Revision 2.1 2000/09/28 ivan
62 * Inclusion of 'iophys' and 'iosize' fields on structure 'pc300hw', to
63 * allow release of I/O region at module unload.
64 * Changed location of include files.
65 *
66 * Revision 2.0 2000/03/27 ivan
67 * Added support for the PC300/TE cards.
68 *
69 * Revision 1.1 2000/01/31 ivan
70 * Replaced 'pc300[drv|sca].h' former PC300 driver include files.
71 *
72 * Revision 1.0 1999/12/16 ivan
73 * First official release.
74 * Inclusion of 'nchan' field on structure 'pc300hw', to allow variable
75 * number of ports per card.
76 * Inclusion of 'if_ptr' field on structure 'pc300dev'.
77 *
78 * Revision 0.6 1999/11/17 ivan
79 * Changed X.25-specific function names to comply with adopted convention.
80 *
81 * Revision 0.5 1999/11/16 Daniela Squassoni
82 * X.25 support.
83 *
84 * Revision 0.4 1999/11/15 ivan
85 * Inclusion of 'clock' field on structure 'pc300hw'.
86 *
87 * Revision 0.3 1999/11/10 ivan
88 * IOCTL name changing.
89 * Inclusion of driver function prototypes.
90 *
91 * Revision 0.2 1999/11/03 ivan
92 * Inclusion of 'tx_skb' and union 'ifu' on structure 'pc300dev'.
93 *
94 * Revision 0.1 1999/01/15 ivan
95 * Initial version.
96 *
97 */
98
99#ifndef _PC300_H
100#define _PC300_H
101
102#include <linux/hdlc.h>
103#include "hd64572.h"
104#include "pc300-falc-lh.h"
105
106#define PC300_PROTO_MLPPP 1
107
108#define PC300_MAXCHAN 2 /* Number of channels per card */
109
110#define PC300_RAMSIZE 0x40000 /* RAM window size (256Kb) */
111#define PC300_FALCSIZE 0x400 /* FALC window size (1Kb) */
112
113#define PC300_OSC_CLOCK 24576000
114#define PC300_PCI_CLOCK 33000000
115
116#define BD_DEF_LEN 0x0800 /* DMA buffer length (2KB) */
117#define DMA_TX_MEMSZ 0x8000 /* Total DMA Tx memory size (32KB/ch) */
118#define DMA_RX_MEMSZ 0x10000 /* Total DMA Rx memory size (64KB/ch) */
119
120#define N_DMA_TX_BUF (DMA_TX_MEMSZ / BD_DEF_LEN) /* DMA Tx buffers */
121#define N_DMA_RX_BUF (DMA_RX_MEMSZ / BD_DEF_LEN) /* DMA Rx buffers */
122
123/* DMA Buffer Offsets */
124#define DMA_TX_BASE ((N_DMA_TX_BUF + N_DMA_RX_BUF) * \
125 PC300_MAXCHAN * sizeof(pcsca_bd_t))
126#define DMA_RX_BASE (DMA_TX_BASE + PC300_MAXCHAN*DMA_TX_MEMSZ)
127
128/* DMA Descriptor Offsets */
129#define DMA_TX_BD_BASE 0x0000
130#define DMA_RX_BD_BASE (DMA_TX_BD_BASE + ((PC300_MAXCHAN*DMA_TX_MEMSZ / \
131 BD_DEF_LEN) * sizeof(pcsca_bd_t)))
132
133/* DMA Descriptor Macros */
134#define TX_BD_ADDR(chan, n) (DMA_TX_BD_BASE + \
135 ((N_DMA_TX_BUF*chan) + n) * sizeof(pcsca_bd_t))
136#define RX_BD_ADDR(chan, n) (DMA_RX_BD_BASE + \
137 ((N_DMA_RX_BUF*chan) + n) * sizeof(pcsca_bd_t))
138
139/* Macro to access the FALC registers (TE only) */
140#define F_REG(reg, chan) (0x200*(chan) + ((reg)<<2))
141
142/***************************************
143 * Memory access functions/macros *
144 * (required to support Alpha systems) *
145 ***************************************/
146#define cpc_writeb(port,val) {writeb((u8)(val),(port)); mb();}
147#define cpc_writew(port,val) {writew((ushort)(val),(port)); mb();}
148#define cpc_writel(port,val) {writel((u32)(val),(port)); mb();}
149
150#define cpc_readb(port) readb(port)
151#define cpc_readw(port) readw(port)
152#define cpc_readl(port) readl(port)
153
154/****** Data Structures *****************************************************/
155
156/*
157 * RUNTIME_9050 - PLX PCI9050-1 local configuration and shared runtime
158 * registers. This structure can be used to access the 9050 registers
159 * (memory mapped).
160 */
161struct RUNTIME_9050 {
162 u32 loc_addr_range[4]; /* 00-0Ch : Local Address Ranges */
163 u32 loc_rom_range; /* 10h : Local ROM Range */
164 u32 loc_addr_base[4]; /* 14-20h : Local Address Base Addrs */
165 u32 loc_rom_base; /* 24h : Local ROM Base */
166 u32 loc_bus_descr[4]; /* 28-34h : Local Bus Descriptors */
167 u32 rom_bus_descr; /* 38h : ROM Bus Descriptor */
168 u32 cs_base[4]; /* 3C-48h : Chip Select Base Addrs */
169 u32 intr_ctrl_stat; /* 4Ch : Interrupt Control/Status */
170 u32 init_ctrl; /* 50h : EEPROM ctrl, Init Ctrl, etc */
171};
172
173#define PLX_9050_LINT1_ENABLE 0x01
174#define PLX_9050_LINT1_POL 0x02
175#define PLX_9050_LINT1_STATUS 0x04
176#define PLX_9050_LINT2_ENABLE 0x08
177#define PLX_9050_LINT2_POL 0x10
178#define PLX_9050_LINT2_STATUS 0x20
179#define PLX_9050_INTR_ENABLE 0x40
180#define PLX_9050_SW_INTR 0x80
181
182/* Masks to access the init_ctrl PLX register */
183#define PC300_CLKSEL_MASK (0x00000004UL)
184#define PC300_CHMEDIA_MASK(chan) (0x00000020UL<<(chan*3))
185#define PC300_CTYPE_MASK (0x00000800UL)
186
187/* CPLD Registers (base addr = falcbase, TE only) */
188/* CPLD v. 0 */
189#define CPLD_REG1 0x140 /* Chip resets, DCD/CTS status */
190#define CPLD_REG2 0x144 /* Clock enable , LED control */
191/* CPLD v. 2 or higher */
192#define CPLD_V2_REG1 0x100 /* Chip resets, DCD/CTS status */
193#define CPLD_V2_REG2 0x104 /* Clock enable , LED control */
194#define CPLD_ID_REG 0x108 /* CPLD version */
195
196/* CPLD Register bit description: for the FALC bits, they should always be
197 set based on the channel (use (bit<<(2*ch)) to access the correct bit for
198 that channel) */
199#define CPLD_REG1_FALC_RESET 0x01
200#define CPLD_REG1_SCA_RESET 0x02
201#define CPLD_REG1_GLOBAL_CLK 0x08
202#define CPLD_REG1_FALC_DCD 0x10
203#define CPLD_REG1_FALC_CTS 0x20
204
205#define CPLD_REG2_FALC_TX_CLK 0x01
206#define CPLD_REG2_FALC_RX_CLK 0x02
207#define CPLD_REG2_FALC_LED1 0x10
208#define CPLD_REG2_FALC_LED2 0x20
209
210/* Structure with FALC-related fields (TE only) */
211#define PC300_FALC_MAXLOOP 0x0000ffff /* for falc_issue_cmd() */
212
213typedef struct falc {
214 u8 sync; /* If true FALC is synchronized */
215 u8 active; /* if TRUE then already active */
216 u8 loop_active; /* if TRUE a line loopback UP was received */
217 u8 loop_gen; /* if TRUE a line loopback UP was issued */
218
219 u8 num_channels;
220 u8 offset; /* 1 for T1, 0 for E1 */
221 u8 full_bandwidth;
222
223 u8 xmb_cause;
224 u8 multiframe_mode;
225
226 /* Statistics */
227 u16 pden; /* Pulse Density violation count */
228 u16 los; /* Loss of Signal count */
229 u16 losr; /* Loss of Signal recovery count */
230 u16 lfa; /* Loss of frame alignment count */
231 u16 farec; /* Frame Alignment Recovery count */
232 u16 lmfa; /* Loss of multiframe alignment count */
233 u16 ais; /* Remote Alarm indication Signal count */
234 u16 sec; /* One-second timer */
235 u16 es; /* Errored second */
236 u16 rai; /* remote alarm received */
237 u16 bec;
238 u16 fec;
239 u16 cvc;
240 u16 cec;
241 u16 ebc;
242
243 /* Status */
244 u8 red_alarm;
245 u8 blue_alarm;
246 u8 loss_fa;
247 u8 yellow_alarm;
248 u8 loss_mfa;
249 u8 prbs;
250} falc_t;
251
252typedef struct falc_status {
253 u8 sync; /* If true FALC is synchronized */
254 u8 red_alarm;
255 u8 blue_alarm;
256 u8 loss_fa;
257 u8 yellow_alarm;
258 u8 loss_mfa;
259 u8 prbs;
260} falc_status_t;
261
262typedef struct rsv_x21_status {
263 u8 dcd;
264 u8 dsr;
265 u8 cts;
266 u8 rts;
267 u8 dtr;
268} rsv_x21_status_t;
269
270typedef struct pc300stats {
271 int hw_type;
272 u32 line_on;
273 u32 line_off;
274 struct net_device_stats gen_stats;
275 falc_t te_stats;
276} pc300stats_t;
277
278typedef struct pc300status {
279 int hw_type;
280 rsv_x21_status_t gen_status;
281 falc_status_t te_status;
282} pc300status_t;
283
284typedef struct pc300loopback {
285 char loop_type;
286 char loop_on;
287} pc300loopback_t;
288
289typedef struct pc300patterntst {
290 char patrntst_on; /* 0 - off; 1 - on; 2 - read num_errors */
291 u16 num_errors;
292} pc300patterntst_t;
293
294typedef struct pc300dev {
295 struct pc300ch *chan;
296 u8 trace_on;
297 u32 line_on; /* DCD(X.21, RSV) / sync(TE) change counters */
298 u32 line_off;
299 char name[16];
300 struct net_device *dev;
301#ifdef CONFIG_PC300_MLPPP
302 void *cpc_tty; /* information to PC300 TTY driver */
303#endif
304}pc300dev_t;
305
306typedef struct pc300hw {
307 int type; /* RSV, X21, etc. */
308 int bus; /* Bus (PCI, PMC, etc.) */
309 int nchan; /* number of channels */
310 int irq; /* interrupt request level */
311 u32 clock; /* Board clock */
312 u8 cpld_id; /* CPLD ID (TE only) */
313 u16 cpld_reg1; /* CPLD reg 1 (TE only) */
314 u16 cpld_reg2; /* CPLD reg 2 (TE only) */
315 u16 gpioc_reg; /* PLX GPIOC reg */
316 u16 intctl_reg; /* PLX Int Ctrl/Status reg */
317 u32 iophys; /* PLX registers I/O base */
318 u32 iosize; /* PLX registers I/O size */
319 u32 plxphys; /* PLX registers MMIO base (physical) */
320 void __iomem * plxbase; /* PLX registers MMIO base (virtual) */
321 u32 plxsize; /* PLX registers MMIO size */
322 u32 scaphys; /* SCA registers MMIO base (physical) */
323 void __iomem * scabase; /* SCA registers MMIO base (virtual) */
324 u32 scasize; /* SCA registers MMIO size */
325 u32 ramphys; /* On-board RAM MMIO base (physical) */
326 void __iomem * rambase; /* On-board RAM MMIO base (virtual) */
327 u32 alloc_ramsize; /* RAM MMIO size allocated by the PCI bridge */
328 u32 ramsize; /* On-board RAM MMIO size */
329 u32 falcphys; /* FALC registers MMIO base (physical) */
330 void __iomem * falcbase;/* FALC registers MMIO base (virtual) */
331 u32 falcsize; /* FALC registers MMIO size */
332} pc300hw_t;
333
334typedef struct pc300chconf {
335 sync_serial_settings phys_settings; /* Clock type/rate (in bps),
336 loopback mode */
337 raw_hdlc_proto proto_settings; /* Encoding, parity (CRC) */
338 u32 media; /* HW media (RS232, V.35, etc.) */
339 u32 proto; /* Protocol (PPP, X.25, etc.) */
340
341 /* TE-specific parameters */
342 u8 lcode; /* Line Code (AMI, B8ZS, etc.) */
343 u8 fr_mode; /* Frame Mode (ESF, D4, etc.) */
344 u8 lbo; /* Line Build Out */
345 u8 rx_sens; /* Rx Sensitivity (long- or short-haul) */
346 u32 tslot_bitmap; /* bit[i]=1 => timeslot _i_ is active */
347} pc300chconf_t;
348
349typedef struct pc300ch {
350 struct pc300 *card;
351 int channel;
352 pc300dev_t d;
353 pc300chconf_t conf;
354 u8 tx_first_bd; /* First TX DMA block descr. w/ data */
355 u8 tx_next_bd; /* Next free TX DMA block descriptor */
356 u8 rx_first_bd; /* First free RX DMA block descriptor */
357 u8 rx_last_bd; /* Last free RX DMA block descriptor */
358 u8 nfree_tx_bd; /* Number of free TX DMA block descriptors */
359 falc_t falc; /* FALC structure (TE only) */
360} pc300ch_t;
361
362typedef struct pc300 {
363 pc300hw_t hw; /* hardware config. */
364 pc300ch_t chan[PC300_MAXCHAN];
365 spinlock_t card_lock;
366} pc300_t;
367
368typedef struct pc300conf {
369 pc300hw_t hw;
370 pc300chconf_t conf;
371} pc300conf_t;
372
373/* DEV ioctl() commands */
374#define N_SPPP_IOCTLS 2
375
376enum pc300_ioctl_cmds {
377 SIOCCPCRESERVED = (SIOCDEVPRIVATE + N_SPPP_IOCTLS),
378 SIOCGPC300CONF,
379 SIOCSPC300CONF,
380 SIOCGPC300STATUS,
381 SIOCGPC300FALCSTATUS,
382 SIOCGPC300UTILSTATS,
383 SIOCGPC300UTILSTATUS,
384 SIOCSPC300TRACE,
385 SIOCSPC300LOOPBACK,
386 SIOCSPC300PATTERNTEST,
387};
388
389/* Loopback types - PC300/TE boards */
390enum pc300_loopback_cmds {
391 PC300LOCLOOP = 1,
392 PC300REMLOOP,
393 PC300PAYLOADLOOP,
394 PC300GENLOOPUP,
395 PC300GENLOOPDOWN,
396};
397
398/* Control Constant Definitions */
399#define PC300_RSV 0x01
400#define PC300_X21 0x02
401#define PC300_TE 0x03
402
403#define PC300_PCI 0x00
404#define PC300_PMC 0x01
405
406#define PC300_LC_AMI 0x01
407#define PC300_LC_B8ZS 0x02
408#define PC300_LC_NRZ 0x03
409#define PC300_LC_HDB3 0x04
410
411/* Framing (T1) */
412#define PC300_FR_ESF 0x01
413#define PC300_FR_D4 0x02
414#define PC300_FR_ESF_JAPAN 0x03
415
416/* Framing (E1) */
417#define PC300_FR_MF_CRC4 0x04
418#define PC300_FR_MF_NON_CRC4 0x05
419#define PC300_FR_UNFRAMED 0x06
420
421#define PC300_LBO_0_DB 0x00
422#define PC300_LBO_7_5_DB 0x01
423#define PC300_LBO_15_DB 0x02
424#define PC300_LBO_22_5_DB 0x03
425
426#define PC300_RX_SENS_SH 0x01
427#define PC300_RX_SENS_LH 0x02
428
429#define PC300_TX_TIMEOUT (2*HZ)
430#define PC300_TX_QUEUE_LEN 100
431#define PC300_DEF_MTU 1600
432
433/* Function Prototypes */
434int cpc_open(struct net_device *dev);
435
436#endif /* _PC300_H */
diff --git a/drivers/net/wan/pc300_drv.c b/drivers/net/wan/pc300_drv.c
deleted file mode 100644
index cb0f8d932b0..00000000000
--- a/drivers/net/wan/pc300_drv.c
+++ /dev/null
@@ -1,3670 +0,0 @@
1#define USE_PCI_CLOCK
2static const char rcsid[] =
3"Revision: 3.4.5 Date: 2002/03/07 ";
4
5/*
6 * pc300.c Cyclades-PC300(tm) Driver.
7 *
8 * Author: Ivan Passos <ivan@cyclades.com>
9 * Maintainer: PC300 Maintainer <pc300@cyclades.com>
10 *
11 * Copyright: (c) 1999-2003 Cyclades Corp.
12 *
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License
15 * as published by the Free Software Foundation; either version
16 * 2 of the License, or (at your option) any later version.
17 *
18 * Using tabstop = 4.
19 *
20 * $Log: pc300_drv.c,v $
21 * Revision 3.23 2002/03/20 13:58:40 henrique
22 * Fixed ortographic mistakes
23 *
24 * Revision 3.22 2002/03/13 16:56:56 henrique
25 * Take out the debug messages
26 *
27 * Revision 3.21 2002/03/07 14:17:09 henrique
28 * License data fixed
29 *
30 * Revision 3.20 2002/01/17 17:58:52 ivan
31 * Support for PC300-TE/M (PMC).
32 *
33 * Revision 3.19 2002/01/03 17:08:47 daniela
34 * Enables DMA reception when the SCA-II disables it improperly.
35 *
36 * Revision 3.18 2001/12/03 18:47:50 daniela
37 * Esthetic changes.
38 *
39 * Revision 3.17 2001/10/19 16:50:13 henrique
40 * Patch to kernel 2.4.12 and new generic hdlc.
41 *
42 * Revision 3.16 2001/10/16 15:12:31 regina
43 * clear statistics
44 *
45 * Revision 3.11 to 3.15 2001/10/11 20:26:04 daniela
46 * More DMA fixes for noisy lines.
47 * Return the size of bad frames in dma_get_rx_frame_size, so that the Rx buffer
48 * descriptors can be cleaned by dma_buf_read (called in cpc_net_rx).
49 * Renamed dma_start routine to rx_dma_start. Improved Rx statistics.
50 * Fixed BOF interrupt treatment. Created dma_start routine.
51 * Changed min and max to cpc_min and cpc_max.
52 *
53 * Revision 3.10 2001/08/06 12:01:51 regina
54 * Fixed problem in DSR_DE bit.
55 *
56 * Revision 3.9 2001/07/18 19:27:26 daniela
57 * Added some history comments.
58 *
59 * Revision 3.8 2001/07/12 13:11:19 regina
60 * bug fix - DCD-OFF in pc300 tty driver
61 *
62 * Revision 3.3 to 3.7 2001/07/06 15:00:20 daniela
63 * Removing kernel 2.4.3 and previous support.
64 * DMA transmission bug fix.
65 * MTU check in cpc_net_rx fixed.
66 * Boot messages reviewed.
67 * New configuration parameters (line code, CRC calculation and clock).
68 *
69 * Revision 3.2 2001/06/22 13:13:02 regina
70 * MLPPP implementation. Changed the header of message trace to include
71 * the device name. New format : "hdlcX[R/T]: ".
72 * Default configuration changed.
73 *
74 * Revision 3.1 2001/06/15 regina
75 * in cpc_queue_xmit, netif_stop_queue is called if don't have free descriptor
76 * upping major version number
77 *
78 * Revision 1.1.1.1 2001/06/13 20:25:04 daniela
79 * PC300 initial CVS version (3.4.0-pre1)
80 *
81 * Revision 3.0.1.2 2001/06/08 daniela
82 * Did some changes in the DMA programming implementation to avoid the
83 * occurrence of a SCA-II bug when CDA is accessed during a DMA transfer.
84 *
85 * Revision 3.0.1.1 2001/05/02 daniela
86 * Added kernel 2.4.3 support.
87 *
88 * Revision 3.0.1.0 2001/03/13 daniela, henrique
89 * Added Frame Relay Support.
90 * Driver now uses HDLC generic driver to provide protocol support.
91 *
92 * Revision 3.0.0.8 2001/03/02 daniela
93 * Fixed ram size detection.
94 * Changed SIOCGPC300CONF ioctl, to give hw information to pc300util.
95 *
96 * Revision 3.0.0.7 2001/02/23 daniela
97 * netif_stop_queue called before the SCA-II transmition commands in
98 * cpc_queue_xmit, and with interrupts disabled to avoid race conditions with
99 * transmition interrupts.
100 * Fixed falc_check_status for Unframed E1.
101 *
102 * Revision 3.0.0.6 2000/12/13 daniela
103 * Implemented pc300util support: trace, statistics, status and loopback
104 * tests for the PC300 TE boards.
105 *
106 * Revision 3.0.0.5 2000/12/12 ivan
107 * Added support for Unframed E1.
108 * Implemented monitor mode.
109 * Fixed DCD sensitivity on the second channel.
110 * Driver now complies with new PCI kernel architecture.
111 *
112 * Revision 3.0.0.4 2000/09/28 ivan
113 * Implemented DCD sensitivity.
114 * Moved hardware-specific open to the end of cpc_open, to avoid race
115 * conditions with early reception interrupts.
116 * Included code for [request|release]_mem_region().
117 * Changed location of pc300.h .
118 * Minor code revision (contrib. of Jeff Garzik).
119 *
120 * Revision 3.0.0.3 2000/07/03 ivan
121 * Previous bugfix for the framing errors with external clock made X21
122 * boards stop working. This version fixes it.
123 *
124 * Revision 3.0.0.2 2000/06/23 ivan
125 * Revisited cpc_queue_xmit to prevent race conditions on Tx DMA buffer
126 * handling when Tx timeouts occur.
127 * Revisited Rx statistics.
128 * Fixed a bug in the SCA-II programming that would cause framing errors
129 * when external clock was configured.
130 *
131 * Revision 3.0.0.1 2000/05/26 ivan
132 * Added logic in the SCA interrupt handler so that no board can monopolize
133 * the driver.
134 * Request PLX I/O region, although driver doesn't use it, to avoid
135 * problems with other drivers accessing it.
136 *
137 * Revision 3.0.0.0 2000/05/15 ivan
138 * Did some changes in the DMA programming implementation to avoid the
139 * occurrence of a SCA-II bug in the second channel.
140 * Implemented workaround for PLX9050 bug that would cause a system lockup
141 * in certain systems, depending on the MMIO addresses allocated to the
142 * board.
143 * Fixed the FALC chip programming to avoid synchronization problems in the
144 * second channel (TE only).
145 * Implemented a cleaner and faster Tx DMA descriptor cleanup procedure in
146 * cpc_queue_xmit().
147 * Changed the built-in driver implementation so that the driver can use the
148 * general 'hdlcN' naming convention instead of proprietary device names.
149 * Driver load messages are now device-centric, instead of board-centric.
150 * Dynamic allocation of net_device structures.
151 * Code is now compliant with the new module interface (module_[init|exit]).
152 * Make use of the PCI helper functions to access PCI resources.
153 *
154 * Revision 2.0.0.0 2000/04/15 ivan
155 * Added support for the PC300/TE boards (T1/FT1/E1/FE1).
156 *
157 * Revision 1.1.0.0 2000/02/28 ivan
158 * Major changes in the driver architecture.
159 * Softnet compliancy implemented.
160 * Driver now reports physical instead of virtual memory addresses.
161 * Added cpc_change_mtu function.
162 *
163 * Revision 1.0.0.0 1999/12/16 ivan
164 * First official release.
165 * Support for 1- and 2-channel boards (which use distinct PCI Device ID's).
166 * Support for monolythic installation (i.e., drv built into the kernel).
167 * X.25 additional checking when lapb_[dis]connect_request returns an error.
168 * SCA programming now covers X.21 as well.
169 *
170 * Revision 0.3.1.0 1999/11/18 ivan
171 * Made X.25 support configuration-dependent (as it depends on external
172 * modules to work).
173 * Changed X.25-specific function names to comply with adopted convention.
174 * Fixed typos in X.25 functions that would cause compile errors (Daniela).
175 * Fixed bug in ch_config that would disable interrupts on a previously
176 * enabled channel if the other channel on the same board was enabled later.
177 *
178 * Revision 0.3.0.0 1999/11/16 daniela
179 * X.25 support.
180 *
181 * Revision 0.2.3.0 1999/11/15 ivan
182 * Function cpc_ch_status now provides more detailed information.
183 * Added support for X.21 clock configuration.
184 * Changed TNR1 setting in order to prevent Tx FIFO overaccesses by the SCA.
185 * Now using PCI clock instead of internal oscillator clock for the SCA.
186 *
187 * Revision 0.2.2.0 1999/11/10 ivan
188 * Changed the *_dma_buf_check functions so that they would print only
189 * the useful info instead of the whole buffer descriptor bank.
190 * Fixed bug in cpc_queue_xmit that would eventually crash the system
191 * in case of a packet drop.
192 * Implemented TX underrun handling.
193 * Improved SCA fine tuning to boost up its performance.
194 *
195 * Revision 0.2.1.0 1999/11/03 ivan
196 * Added functions *dma_buf_pt_init to allow independent initialization
197 * of the next-descr. and DMA buffer pointers on the DMA descriptors.
198 * Kernel buffer release and tbusy clearing is now done in the interrupt
199 * handler.
200 * Fixed bug in cpc_open that would cause an interface reopen to fail.
201 * Added a protocol-specific code section in cpc_net_rx.
202 * Removed printk level defs (they might be added back after the beta phase).
203 *
204 * Revision 0.2.0.0 1999/10/28 ivan
205 * Revisited the code so that new protocols can be easily added / supported.
206 *
207 * Revision 0.1.0.1 1999/10/20 ivan
208 * Mostly "esthetic" changes.
209 *
210 * Revision 0.1.0.0 1999/10/11 ivan
211 * Initial version.
212 *
213 */
214
215#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
216
217#include <linux/module.h>
218#include <linux/kernel.h>
219#include <linux/mm.h>
220#include <linux/ioport.h>
221#include <linux/pci.h>
222#include <linux/errno.h>
223#include <linux/string.h>
224#include <linux/init.h>
225#include <linux/delay.h>
226#include <linux/net.h>
227#include <linux/skbuff.h>
228#include <linux/if_arp.h>
229#include <linux/netdevice.h>
230#include <linux/etherdevice.h>
231#include <linux/spinlock.h>
232#include <linux/if.h>
233#include <linux/slab.h>
234#include <net/arp.h>
235
236#include <asm/io.h>
237#include <asm/uaccess.h>
238
239#include "pc300.h"
240
241#define CPC_LOCK(card,flags) \
242 do { \
243 spin_lock_irqsave(&card->card_lock, flags); \
244 } while (0)
245
246#define CPC_UNLOCK(card,flags) \
247 do { \
248 spin_unlock_irqrestore(&card->card_lock, flags); \
249 } while (0)
250
251#undef PC300_DEBUG_PCI
252#undef PC300_DEBUG_INTR
253#undef PC300_DEBUG_TX
254#undef PC300_DEBUG_RX
255#undef PC300_DEBUG_OTHER
256
257static DEFINE_PCI_DEVICE_TABLE(cpc_pci_dev_id) = {
258 /* PC300/RSV or PC300/X21, 2 chan */
259 {0x120e, 0x300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0x300},
260 /* PC300/RSV or PC300/X21, 1 chan */
261 {0x120e, 0x301, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0x301},
262 /* PC300/TE, 2 chan */
263 {0x120e, 0x310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0x310},
264 /* PC300/TE, 1 chan */
265 {0x120e, 0x311, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0x311},
266 /* PC300/TE-M, 2 chan */
267 {0x120e, 0x320, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0x320},
268 /* PC300/TE-M, 1 chan */
269 {0x120e, 0x321, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0x321},
270 /* End of table */
271 {0,},
272};
273MODULE_DEVICE_TABLE(pci, cpc_pci_dev_id);
274
275#ifndef cpc_min
276#define cpc_min(a,b) (((a)<(b))?(a):(b))
277#endif
278#ifndef cpc_max
279#define cpc_max(a,b) (((a)>(b))?(a):(b))
280#endif
281
282/* prototypes */
283static void tx_dma_buf_pt_init(pc300_t *, int);
284static void tx_dma_buf_init(pc300_t *, int);
285static void rx_dma_buf_pt_init(pc300_t *, int);
286static void rx_dma_buf_init(pc300_t *, int);
287static void tx_dma_buf_check(pc300_t *, int);
288static void rx_dma_buf_check(pc300_t *, int);
289static irqreturn_t cpc_intr(int, void *);
290static int clock_rate_calc(u32, u32, int *);
291static u32 detect_ram(pc300_t *);
292static void plx_init(pc300_t *);
293static void cpc_trace(struct net_device *, struct sk_buff *, char);
294static int cpc_attach(struct net_device *, unsigned short, unsigned short);
295static int cpc_close(struct net_device *dev);
296
297#ifdef CONFIG_PC300_MLPPP
298void cpc_tty_init(pc300dev_t * dev);
299void cpc_tty_unregister_service(pc300dev_t * pc300dev);
300void cpc_tty_receive(pc300dev_t * pc300dev);
301void cpc_tty_trigger_poll(pc300dev_t * pc300dev);
302#endif
303
304/************************/
305/*** DMA Routines ***/
306/************************/
307static void tx_dma_buf_pt_init(pc300_t * card, int ch)
308{
309 int i;
310 int ch_factor = ch * N_DMA_TX_BUF;
311 volatile pcsca_bd_t __iomem *ptdescr = (card->hw.rambase
312 + DMA_TX_BD_BASE + ch_factor * sizeof(pcsca_bd_t));
313
314 for (i = 0; i < N_DMA_TX_BUF; i++, ptdescr++) {
315 cpc_writel(&ptdescr->next, (u32)(DMA_TX_BD_BASE +
316 (ch_factor + ((i + 1) & (N_DMA_TX_BUF - 1))) * sizeof(pcsca_bd_t)));
317 cpc_writel(&ptdescr->ptbuf,
318 (u32)(DMA_TX_BASE + (ch_factor + i) * BD_DEF_LEN));
319 }
320}
321
322static void tx_dma_buf_init(pc300_t * card, int ch)
323{
324 int i;
325 int ch_factor = ch * N_DMA_TX_BUF;
326 volatile pcsca_bd_t __iomem *ptdescr = (card->hw.rambase
327 + DMA_TX_BD_BASE + ch_factor * sizeof(pcsca_bd_t));
328
329 for (i = 0; i < N_DMA_TX_BUF; i++, ptdescr++) {
330 memset_io(ptdescr, 0, sizeof(pcsca_bd_t));
331 cpc_writew(&ptdescr->len, 0);
332 cpc_writeb(&ptdescr->status, DST_OSB);
333 }
334 tx_dma_buf_pt_init(card, ch);
335}
336
337static void rx_dma_buf_pt_init(pc300_t * card, int ch)
338{
339 int i;
340 int ch_factor = ch * N_DMA_RX_BUF;
341 volatile pcsca_bd_t __iomem *ptdescr = (card->hw.rambase
342 + DMA_RX_BD_BASE + ch_factor * sizeof(pcsca_bd_t));
343
344 for (i = 0; i < N_DMA_RX_BUF; i++, ptdescr++) {
345 cpc_writel(&ptdescr->next, (u32)(DMA_RX_BD_BASE +
346 (ch_factor + ((i + 1) & (N_DMA_RX_BUF - 1))) * sizeof(pcsca_bd_t)));
347 cpc_writel(&ptdescr->ptbuf,
348 (u32)(DMA_RX_BASE + (ch_factor + i) * BD_DEF_LEN));
349 }
350}
351
352static void rx_dma_buf_init(pc300_t * card, int ch)
353{
354 int i;
355 int ch_factor = ch * N_DMA_RX_BUF;
356 volatile pcsca_bd_t __iomem *ptdescr = (card->hw.rambase
357 + DMA_RX_BD_BASE + ch_factor * sizeof(pcsca_bd_t));
358
359 for (i = 0; i < N_DMA_RX_BUF; i++, ptdescr++) {
360 memset_io(ptdescr, 0, sizeof(pcsca_bd_t));
361 cpc_writew(&ptdescr->len, 0);
362 cpc_writeb(&ptdescr->status, 0);
363 }
364 rx_dma_buf_pt_init(card, ch);
365}
366
367static void tx_dma_buf_check(pc300_t * card, int ch)
368{
369 volatile pcsca_bd_t __iomem *ptdescr;
370 int i;
371 u16 first_bd = card->chan[ch].tx_first_bd;
372 u16 next_bd = card->chan[ch].tx_next_bd;
373
374 printk("#CH%d: f_bd = %d(0x%08zx), n_bd = %d(0x%08zx)\n", ch,
375 first_bd, TX_BD_ADDR(ch, first_bd),
376 next_bd, TX_BD_ADDR(ch, next_bd));
377 for (i = first_bd,
378 ptdescr = (card->hw.rambase + TX_BD_ADDR(ch, first_bd));
379 i != ((next_bd + 1) & (N_DMA_TX_BUF - 1));
380 i = (i + 1) & (N_DMA_TX_BUF - 1),
381 ptdescr = (card->hw.rambase + TX_BD_ADDR(ch, i))) {
382 printk("\n CH%d TX%d: next=0x%x, ptbuf=0x%x, ST=0x%x, len=%d",
383 ch, i, cpc_readl(&ptdescr->next),
384 cpc_readl(&ptdescr->ptbuf),
385 cpc_readb(&ptdescr->status), cpc_readw(&ptdescr->len));
386 }
387 printk("\n");
388}
389
390#ifdef PC300_DEBUG_OTHER
391/* Show all TX buffer descriptors */
392static void tx1_dma_buf_check(pc300_t * card, int ch)
393{
394 volatile pcsca_bd_t __iomem *ptdescr;
395 int i;
396 u16 first_bd = card->chan[ch].tx_first_bd;
397 u16 next_bd = card->chan[ch].tx_next_bd;
398 u32 scabase = card->hw.scabase;
399
400 printk ("\nnfree_tx_bd = %d\n", card->chan[ch].nfree_tx_bd);
401 printk("#CH%d: f_bd = %d(0x%08x), n_bd = %d(0x%08x)\n", ch,
402 first_bd, TX_BD_ADDR(ch, first_bd),
403 next_bd, TX_BD_ADDR(ch, next_bd));
404 printk("TX_CDA=0x%08x, TX_EDA=0x%08x\n",
405 cpc_readl(scabase + DTX_REG(CDAL, ch)),
406 cpc_readl(scabase + DTX_REG(EDAL, ch)));
407 for (i = 0; i < N_DMA_TX_BUF; i++) {
408 ptdescr = (card->hw.rambase + TX_BD_ADDR(ch, i));
409 printk("\n CH%d TX%d: next=0x%x, ptbuf=0x%x, ST=0x%x, len=%d",
410 ch, i, cpc_readl(&ptdescr->next),
411 cpc_readl(&ptdescr->ptbuf),
412 cpc_readb(&ptdescr->status), cpc_readw(&ptdescr->len));
413 }
414 printk("\n");
415}
416#endif
417
418static void rx_dma_buf_check(pc300_t * card, int ch)
419{
420 volatile pcsca_bd_t __iomem *ptdescr;
421 int i;
422 u16 first_bd = card->chan[ch].rx_first_bd;
423 u16 last_bd = card->chan[ch].rx_last_bd;
424 int ch_factor;
425
426 ch_factor = ch * N_DMA_RX_BUF;
427 printk("#CH%d: f_bd = %d, l_bd = %d\n", ch, first_bd, last_bd);
428 for (i = 0, ptdescr = (card->hw.rambase +
429 DMA_RX_BD_BASE + ch_factor * sizeof(pcsca_bd_t));
430 i < N_DMA_RX_BUF; i++, ptdescr++) {
431 if (cpc_readb(&ptdescr->status) & DST_OSB)
432 printk ("\n CH%d RX%d: next=0x%x, ptbuf=0x%x, ST=0x%x, len=%d",
433 ch, i, cpc_readl(&ptdescr->next),
434 cpc_readl(&ptdescr->ptbuf),
435 cpc_readb(&ptdescr->status),
436 cpc_readw(&ptdescr->len));
437 }
438 printk("\n");
439}
440
441static int dma_get_rx_frame_size(pc300_t * card, int ch)
442{
443 volatile pcsca_bd_t __iomem *ptdescr;
444 u16 first_bd = card->chan[ch].rx_first_bd;
445 int rcvd = 0;
446 volatile u8 status;
447
448 ptdescr = (card->hw.rambase + RX_BD_ADDR(ch, first_bd));
449 while ((status = cpc_readb(&ptdescr->status)) & DST_OSB) {
450 rcvd += cpc_readw(&ptdescr->len);
451 first_bd = (first_bd + 1) & (N_DMA_RX_BUF - 1);
452 if ((status & DST_EOM) || (first_bd == card->chan[ch].rx_last_bd)) {
453 /* Return the size of a good frame or incomplete bad frame
454 * (dma_buf_read will clean the buffer descriptors in this case). */
455 return rcvd;
456 }
457 ptdescr = (card->hw.rambase + cpc_readl(&ptdescr->next));
458 }
459 return -1;
460}
461
462/*
463 * dma_buf_write: writes a frame to the Tx DMA buffers
464 * NOTE: this function writes one frame at a time.
465 */
466static int dma_buf_write(pc300_t *card, int ch, u8 *ptdata, int len)
467{
468 int i, nchar;
469 volatile pcsca_bd_t __iomem *ptdescr;
470 int tosend = len;
471 u8 nbuf = ((len - 1) / BD_DEF_LEN) + 1;
472
473 if (nbuf >= card->chan[ch].nfree_tx_bd) {
474 return -ENOMEM;
475 }
476
477 for (i = 0; i < nbuf; i++) {
478 ptdescr = (card->hw.rambase +
479 TX_BD_ADDR(ch, card->chan[ch].tx_next_bd));
480 nchar = cpc_min(BD_DEF_LEN, tosend);
481 if (cpc_readb(&ptdescr->status) & DST_OSB) {
482 memcpy_toio((card->hw.rambase + cpc_readl(&ptdescr->ptbuf)),
483 &ptdata[len - tosend], nchar);
484 cpc_writew(&ptdescr->len, nchar);
485 card->chan[ch].nfree_tx_bd--;
486 if ((i + 1) == nbuf) {
487 /* This must be the last BD to be used */
488 cpc_writeb(&ptdescr->status, DST_EOM);
489 } else {
490 cpc_writeb(&ptdescr->status, 0);
491 }
492 } else {
493 return -ENOMEM;
494 }
495 tosend -= nchar;
496 card->chan[ch].tx_next_bd =
497 (card->chan[ch].tx_next_bd + 1) & (N_DMA_TX_BUF - 1);
498 }
499 /* If it gets to here, it means we have sent the whole frame */
500 return 0;
501}
502
503/*
504 * dma_buf_read: reads a frame from the Rx DMA buffers
505 * NOTE: this function reads one frame at a time.
506 */
507static int dma_buf_read(pc300_t * card, int ch, struct sk_buff *skb)
508{
509 int nchar;
510 pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
511 volatile pcsca_bd_t __iomem *ptdescr;
512 int rcvd = 0;
513 volatile u8 status;
514
515 ptdescr = (card->hw.rambase +
516 RX_BD_ADDR(ch, chan->rx_first_bd));
517 while ((status = cpc_readb(&ptdescr->status)) & DST_OSB) {
518 nchar = cpc_readw(&ptdescr->len);
519 if ((status & (DST_OVR | DST_CRC | DST_RBIT | DST_SHRT | DST_ABT)) ||
520 (nchar > BD_DEF_LEN)) {
521
522 if (nchar > BD_DEF_LEN)
523 status |= DST_RBIT;
524 rcvd = -status;
525 /* Discard remaining descriptors used by the bad frame */
526 while (chan->rx_first_bd != chan->rx_last_bd) {
527 cpc_writeb(&ptdescr->status, 0);
528 chan->rx_first_bd = (chan->rx_first_bd+1) & (N_DMA_RX_BUF-1);
529 if (status & DST_EOM)
530 break;
531 ptdescr = (card->hw.rambase +
532 cpc_readl(&ptdescr->next));
533 status = cpc_readb(&ptdescr->status);
534 }
535 break;
536 }
537 if (nchar != 0) {
538 if (skb) {
539 memcpy_fromio(skb_put(skb, nchar),
540 (card->hw.rambase+cpc_readl(&ptdescr->ptbuf)),nchar);
541 }
542 rcvd += nchar;
543 }
544 cpc_writeb(&ptdescr->status, 0);
545 cpc_writeb(&ptdescr->len, 0);
546 chan->rx_first_bd = (chan->rx_first_bd + 1) & (N_DMA_RX_BUF - 1);
547
548 if (status & DST_EOM)
549 break;
550
551 ptdescr = (card->hw.rambase + cpc_readl(&ptdescr->next));
552 }
553
554 if (rcvd != 0) {
555 /* Update pointer */
556 chan->rx_last_bd = (chan->rx_first_bd - 1) & (N_DMA_RX_BUF - 1);
557 /* Update EDA */
558 cpc_writel(card->hw.scabase + DRX_REG(EDAL, ch),
559 RX_BD_ADDR(ch, chan->rx_last_bd));
560 }
561 return rcvd;
562}
563
564static void tx_dma_stop(pc300_t * card, int ch)
565{
566 void __iomem *scabase = card->hw.scabase;
567 u8 drr_ena_bit = 1 << (5 + 2 * ch);
568 u8 drr_rst_bit = 1 << (1 + 2 * ch);
569
570 /* Disable DMA */
571 cpc_writeb(scabase + DRR, drr_ena_bit);
572 cpc_writeb(scabase + DRR, drr_rst_bit & ~drr_ena_bit);
573}
574
575static void rx_dma_stop(pc300_t * card, int ch)
576{
577 void __iomem *scabase = card->hw.scabase;
578 u8 drr_ena_bit = 1 << (4 + 2 * ch);
579 u8 drr_rst_bit = 1 << (2 * ch);
580
581 /* Disable DMA */
582 cpc_writeb(scabase + DRR, drr_ena_bit);
583 cpc_writeb(scabase + DRR, drr_rst_bit & ~drr_ena_bit);
584}
585
586static void rx_dma_start(pc300_t * card, int ch)
587{
588 void __iomem *scabase = card->hw.scabase;
589 pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
590
591 /* Start DMA */
592 cpc_writel(scabase + DRX_REG(CDAL, ch),
593 RX_BD_ADDR(ch, chan->rx_first_bd));
594 if (cpc_readl(scabase + DRX_REG(CDAL,ch)) !=
595 RX_BD_ADDR(ch, chan->rx_first_bd)) {
596 cpc_writel(scabase + DRX_REG(CDAL, ch),
597 RX_BD_ADDR(ch, chan->rx_first_bd));
598 }
599 cpc_writel(scabase + DRX_REG(EDAL, ch),
600 RX_BD_ADDR(ch, chan->rx_last_bd));
601 cpc_writew(scabase + DRX_REG(BFLL, ch), BD_DEF_LEN);
602 cpc_writeb(scabase + DSR_RX(ch), DSR_DE);
603 if (!(cpc_readb(scabase + DSR_RX(ch)) & DSR_DE)) {
604 cpc_writeb(scabase + DSR_RX(ch), DSR_DE);
605 }
606}
607
608/*************************/
609/*** FALC Routines ***/
610/*************************/
611static void falc_issue_cmd(pc300_t *card, int ch, u8 cmd)
612{
613 void __iomem *falcbase = card->hw.falcbase;
614 unsigned long i = 0;
615
616 while (cpc_readb(falcbase + F_REG(SIS, ch)) & SIS_CEC) {
617 if (i++ >= PC300_FALC_MAXLOOP) {
618 printk("%s: FALC command locked(cmd=0x%x).\n",
619 card->chan[ch].d.name, cmd);
620 break;
621 }
622 }
623 cpc_writeb(falcbase + F_REG(CMDR, ch), cmd);
624}
625
626static void falc_intr_enable(pc300_t * card, int ch)
627{
628 pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
629 pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
630 falc_t *pfalc = (falc_t *) & chan->falc;
631 void __iomem *falcbase = card->hw.falcbase;
632
633 /* Interrupt pins are open-drain */
634 cpc_writeb(falcbase + F_REG(IPC, ch),
635 cpc_readb(falcbase + F_REG(IPC, ch)) & ~IPC_IC0);
636 /* Conters updated each second */
637 cpc_writeb(falcbase + F_REG(FMR1, ch),
638 cpc_readb(falcbase + F_REG(FMR1, ch)) | FMR1_ECM);
639 /* Enable SEC and ES interrupts */
640 cpc_writeb(falcbase + F_REG(IMR3, ch),
641 cpc_readb(falcbase + F_REG(IMR3, ch)) & ~(IMR3_SEC | IMR3_ES));
642 if (conf->fr_mode == PC300_FR_UNFRAMED) {
643 cpc_writeb(falcbase + F_REG(IMR4, ch),
644 cpc_readb(falcbase + F_REG(IMR4, ch)) & ~(IMR4_LOS));
645 } else {
646 cpc_writeb(falcbase + F_REG(IMR4, ch),
647 cpc_readb(falcbase + F_REG(IMR4, ch)) &
648 ~(IMR4_LFA | IMR4_AIS | IMR4_LOS | IMR4_SLIP));
649 }
650 if (conf->media == IF_IFACE_T1) {
651 cpc_writeb(falcbase + F_REG(IMR3, ch),
652 cpc_readb(falcbase + F_REG(IMR3, ch)) & ~IMR3_LLBSC);
653 } else {
654 cpc_writeb(falcbase + F_REG(IPC, ch),
655 cpc_readb(falcbase + F_REG(IPC, ch)) | IPC_SCI);
656 if (conf->fr_mode == PC300_FR_UNFRAMED) {
657 cpc_writeb(falcbase + F_REG(IMR2, ch),
658 cpc_readb(falcbase + F_REG(IMR2, ch)) & ~(IMR2_LOS));
659 } else {
660 cpc_writeb(falcbase + F_REG(IMR2, ch),
661 cpc_readb(falcbase + F_REG(IMR2, ch)) &
662 ~(IMR2_FAR | IMR2_LFA | IMR2_AIS | IMR2_LOS));
663 if (pfalc->multiframe_mode) {
664 cpc_writeb(falcbase + F_REG(IMR2, ch),
665 cpc_readb(falcbase + F_REG(IMR2, ch)) &
666 ~(IMR2_T400MS | IMR2_MFAR));
667 } else {
668 cpc_writeb(falcbase + F_REG(IMR2, ch),
669 cpc_readb(falcbase + F_REG(IMR2, ch)) |
670 IMR2_T400MS | IMR2_MFAR);
671 }
672 }
673 }
674}
675
676static void falc_open_timeslot(pc300_t * card, int ch, int timeslot)
677{
678 void __iomem *falcbase = card->hw.falcbase;
679 u8 tshf = card->chan[ch].falc.offset;
680
681 cpc_writeb(falcbase + F_REG((ICB1 + (timeslot - tshf) / 8), ch),
682 cpc_readb(falcbase + F_REG((ICB1 + (timeslot - tshf) / 8), ch)) &
683 ~(0x80 >> ((timeslot - tshf) & 0x07)));
684 cpc_writeb(falcbase + F_REG((TTR1 + timeslot / 8), ch),
685 cpc_readb(falcbase + F_REG((TTR1 + timeslot / 8), ch)) |
686 (0x80 >> (timeslot & 0x07)));
687 cpc_writeb(falcbase + F_REG((RTR1 + timeslot / 8), ch),
688 cpc_readb(falcbase + F_REG((RTR1 + timeslot / 8), ch)) |
689 (0x80 >> (timeslot & 0x07)));
690}
691
692static void falc_close_timeslot(pc300_t * card, int ch, int timeslot)
693{
694 void __iomem *falcbase = card->hw.falcbase;
695 u8 tshf = card->chan[ch].falc.offset;
696
697 cpc_writeb(falcbase + F_REG((ICB1 + (timeslot - tshf) / 8), ch),
698 cpc_readb(falcbase + F_REG((ICB1 + (timeslot - tshf) / 8), ch)) |
699 (0x80 >> ((timeslot - tshf) & 0x07)));
700 cpc_writeb(falcbase + F_REG((TTR1 + timeslot / 8), ch),
701 cpc_readb(falcbase + F_REG((TTR1 + timeslot / 8), ch)) &
702 ~(0x80 >> (timeslot & 0x07)));
703 cpc_writeb(falcbase + F_REG((RTR1 + timeslot / 8), ch),
704 cpc_readb(falcbase + F_REG((RTR1 + timeslot / 8), ch)) &
705 ~(0x80 >> (timeslot & 0x07)));
706}
707
708static void falc_close_all_timeslots(pc300_t * card, int ch)
709{
710 pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
711 pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
712 void __iomem *falcbase = card->hw.falcbase;
713
714 cpc_writeb(falcbase + F_REG(ICB1, ch), 0xff);
715 cpc_writeb(falcbase + F_REG(TTR1, ch), 0);
716 cpc_writeb(falcbase + F_REG(RTR1, ch), 0);
717 cpc_writeb(falcbase + F_REG(ICB2, ch), 0xff);
718 cpc_writeb(falcbase + F_REG(TTR2, ch), 0);
719 cpc_writeb(falcbase + F_REG(RTR2, ch), 0);
720 cpc_writeb(falcbase + F_REG(ICB3, ch), 0xff);
721 cpc_writeb(falcbase + F_REG(TTR3, ch), 0);
722 cpc_writeb(falcbase + F_REG(RTR3, ch), 0);
723 if (conf->media == IF_IFACE_E1) {
724 cpc_writeb(falcbase + F_REG(ICB4, ch), 0xff);
725 cpc_writeb(falcbase + F_REG(TTR4, ch), 0);
726 cpc_writeb(falcbase + F_REG(RTR4, ch), 0);
727 }
728}
729
730static void falc_open_all_timeslots(pc300_t * card, int ch)
731{
732 pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
733 pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
734 void __iomem *falcbase = card->hw.falcbase;
735
736 cpc_writeb(falcbase + F_REG(ICB1, ch), 0);
737 if (conf->fr_mode == PC300_FR_UNFRAMED) {
738 cpc_writeb(falcbase + F_REG(TTR1, ch), 0xff);
739 cpc_writeb(falcbase + F_REG(RTR1, ch), 0xff);
740 } else {
741 /* Timeslot 0 is never enabled */
742 cpc_writeb(falcbase + F_REG(TTR1, ch), 0x7f);
743 cpc_writeb(falcbase + F_REG(RTR1, ch), 0x7f);
744 }
745 cpc_writeb(falcbase + F_REG(ICB2, ch), 0);
746 cpc_writeb(falcbase + F_REG(TTR2, ch), 0xff);
747 cpc_writeb(falcbase + F_REG(RTR2, ch), 0xff);
748 cpc_writeb(falcbase + F_REG(ICB3, ch), 0);
749 cpc_writeb(falcbase + F_REG(TTR3, ch), 0xff);
750 cpc_writeb(falcbase + F_REG(RTR3, ch), 0xff);
751 if (conf->media == IF_IFACE_E1) {
752 cpc_writeb(falcbase + F_REG(ICB4, ch), 0);
753 cpc_writeb(falcbase + F_REG(TTR4, ch), 0xff);
754 cpc_writeb(falcbase + F_REG(RTR4, ch), 0xff);
755 } else {
756 cpc_writeb(falcbase + F_REG(ICB4, ch), 0xff);
757 cpc_writeb(falcbase + F_REG(TTR4, ch), 0x80);
758 cpc_writeb(falcbase + F_REG(RTR4, ch), 0x80);
759 }
760}
761
762static void falc_init_timeslot(pc300_t * card, int ch)
763{
764 pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
765 pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
766 falc_t *pfalc = (falc_t *) & chan->falc;
767 int tslot;
768
769 for (tslot = 0; tslot < pfalc->num_channels; tslot++) {
770 if (conf->tslot_bitmap & (1 << tslot)) {
771 // Channel enabled
772 falc_open_timeslot(card, ch, tslot + 1);
773 } else {
774 // Channel disabled
775 falc_close_timeslot(card, ch, tslot + 1);
776 }
777 }
778}
779
780static void falc_enable_comm(pc300_t * card, int ch)
781{
782 pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
783 falc_t *pfalc = (falc_t *) & chan->falc;
784
785 if (pfalc->full_bandwidth) {
786 falc_open_all_timeslots(card, ch);
787 } else {
788 falc_init_timeslot(card, ch);
789 }
790 // CTS/DCD ON
791 cpc_writeb(card->hw.falcbase + card->hw.cpld_reg1,
792 cpc_readb(card->hw.falcbase + card->hw.cpld_reg1) &
793 ~((CPLD_REG1_FALC_DCD | CPLD_REG1_FALC_CTS) << (2 * ch)));
794}
795
796static void falc_disable_comm(pc300_t * card, int ch)
797{
798 pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
799 falc_t *pfalc = (falc_t *) & chan->falc;
800
801 if (pfalc->loop_active != 2) {
802 falc_close_all_timeslots(card, ch);
803 }
804 // CTS/DCD OFF
805 cpc_writeb(card->hw.falcbase + card->hw.cpld_reg1,
806 cpc_readb(card->hw.falcbase + card->hw.cpld_reg1) |
807 ((CPLD_REG1_FALC_DCD | CPLD_REG1_FALC_CTS) << (2 * ch)));
808}
809
810static void falc_init_t1(pc300_t * card, int ch)
811{
812 pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
813 pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
814 falc_t *pfalc = (falc_t *) & chan->falc;
815 void __iomem *falcbase = card->hw.falcbase;
816 u8 dja = (ch ? (LIM2_DJA2 | LIM2_DJA1) : 0);
817
818 /* Switch to T1 mode (PCM 24) */
819 cpc_writeb(falcbase + F_REG(FMR1, ch), FMR1_PMOD);
820
821 /* Wait 20 us for setup */
822 udelay(20);
823
824 /* Transmit Buffer Size (1 frame) */
825 cpc_writeb(falcbase + F_REG(SIC1, ch), SIC1_XBS0);
826
827 /* Clock mode */
828 if (conf->phys_settings.clock_type == CLOCK_INT) { /* Master mode */
829 cpc_writeb(falcbase + F_REG(LIM0, ch),
830 cpc_readb(falcbase + F_REG(LIM0, ch)) | LIM0_MAS);
831 } else { /* Slave mode */
832 cpc_writeb(falcbase + F_REG(LIM0, ch),
833 cpc_readb(falcbase + F_REG(LIM0, ch)) & ~LIM0_MAS);
834 cpc_writeb(falcbase + F_REG(LOOP, ch),
835 cpc_readb(falcbase + F_REG(LOOP, ch)) & ~LOOP_RTM);
836 }
837
838 cpc_writeb(falcbase + F_REG(IPC, ch), IPC_SCI);
839 cpc_writeb(falcbase + F_REG(FMR0, ch),
840 cpc_readb(falcbase + F_REG(FMR0, ch)) &
841 ~(FMR0_XC0 | FMR0_XC1 | FMR0_RC0 | FMR0_RC1));
842
843 switch (conf->lcode) {
844 case PC300_LC_AMI:
845 cpc_writeb(falcbase + F_REG(FMR0, ch),
846 cpc_readb(falcbase + F_REG(FMR0, ch)) |
847 FMR0_XC1 | FMR0_RC1);
848 /* Clear Channel register to ON for all channels */
849 cpc_writeb(falcbase + F_REG(CCB1, ch), 0xff);
850 cpc_writeb(falcbase + F_REG(CCB2, ch), 0xff);
851 cpc_writeb(falcbase + F_REG(CCB3, ch), 0xff);
852 break;
853
854 case PC300_LC_B8ZS:
855 cpc_writeb(falcbase + F_REG(FMR0, ch),
856 cpc_readb(falcbase + F_REG(FMR0, ch)) |
857 FMR0_XC0 | FMR0_XC1 | FMR0_RC0 | FMR0_RC1);
858 break;
859
860 case PC300_LC_NRZ:
861 cpc_writeb(falcbase + F_REG(FMR0, ch),
862 cpc_readb(falcbase + F_REG(FMR0, ch)) | 0x00);
863 break;
864 }
865
866 cpc_writeb(falcbase + F_REG(LIM0, ch),
867 cpc_readb(falcbase + F_REG(LIM0, ch)) | LIM0_ELOS);
868 cpc_writeb(falcbase + F_REG(LIM0, ch),
869 cpc_readb(falcbase + F_REG(LIM0, ch)) & ~(LIM0_SCL1 | LIM0_SCL0));
870 /* Set interface mode to 2 MBPS */
871 cpc_writeb(falcbase + F_REG(FMR1, ch),
872 cpc_readb(falcbase + F_REG(FMR1, ch)) | FMR1_IMOD);
873
874 switch (conf->fr_mode) {
875 case PC300_FR_ESF:
876 pfalc->multiframe_mode = 0;
877 cpc_writeb(falcbase + F_REG(FMR4, ch),
878 cpc_readb(falcbase + F_REG(FMR4, ch)) | FMR4_FM1);
879 cpc_writeb(falcbase + F_REG(FMR1, ch),
880 cpc_readb(falcbase + F_REG(FMR1, ch)) |
881 FMR1_CRC | FMR1_EDL);
882 cpc_writeb(falcbase + F_REG(XDL1, ch), 0);
883 cpc_writeb(falcbase + F_REG(XDL2, ch), 0);
884 cpc_writeb(falcbase + F_REG(XDL3, ch), 0);
885 cpc_writeb(falcbase + F_REG(FMR0, ch),
886 cpc_readb(falcbase + F_REG(FMR0, ch)) & ~FMR0_SRAF);
887 cpc_writeb(falcbase + F_REG(FMR2, ch),
888 cpc_readb(falcbase + F_REG(FMR2,ch)) | FMR2_MCSP | FMR2_SSP);
889 break;
890
891 case PC300_FR_D4:
892 pfalc->multiframe_mode = 1;
893 cpc_writeb(falcbase + F_REG(FMR4, ch),
894 cpc_readb(falcbase + F_REG(FMR4, ch)) &
895 ~(FMR4_FM1 | FMR4_FM0));
896 cpc_writeb(falcbase + F_REG(FMR0, ch),
897 cpc_readb(falcbase + F_REG(FMR0, ch)) | FMR0_SRAF);
898 cpc_writeb(falcbase + F_REG(FMR2, ch),
899 cpc_readb(falcbase + F_REG(FMR2, ch)) & ~FMR2_SSP);
900 break;
901 }
902
903 /* Enable Automatic Resynchronization */
904 cpc_writeb(falcbase + F_REG(FMR4, ch),
905 cpc_readb(falcbase + F_REG(FMR4, ch)) | FMR4_AUTO);
906
907 /* Transmit Automatic Remote Alarm */
908 cpc_writeb(falcbase + F_REG(FMR2, ch),
909 cpc_readb(falcbase + F_REG(FMR2, ch)) | FMR2_AXRA);
910
911 /* Channel translation mode 1 : one to one */
912 cpc_writeb(falcbase + F_REG(FMR1, ch),
913 cpc_readb(falcbase + F_REG(FMR1, ch)) | FMR1_CTM);
914
915 /* No signaling */
916 cpc_writeb(falcbase + F_REG(FMR1, ch),
917 cpc_readb(falcbase + F_REG(FMR1, ch)) & ~FMR1_SIGM);
918 cpc_writeb(falcbase + F_REG(FMR5, ch),
919 cpc_readb(falcbase + F_REG(FMR5, ch)) &
920 ~(FMR5_EIBR | FMR5_SRS));
921 cpc_writeb(falcbase + F_REG(CCR1, ch), 0);
922
923 cpc_writeb(falcbase + F_REG(LIM1, ch),
924 cpc_readb(falcbase + F_REG(LIM1, ch)) | LIM1_RIL0 | LIM1_RIL1);
925
926 switch (conf->lbo) {
927 /* Provides proper Line Build Out */
928 case PC300_LBO_0_DB:
929 cpc_writeb(falcbase + F_REG(LIM2, ch), (LIM2_LOS1 | dja));
930 cpc_writeb(falcbase + F_REG(XPM0, ch), 0x5a);
931 cpc_writeb(falcbase + F_REG(XPM1, ch), 0x8f);
932 cpc_writeb(falcbase + F_REG(XPM2, ch), 0x20);
933 break;
934 case PC300_LBO_7_5_DB:
935 cpc_writeb(falcbase + F_REG(LIM2, ch), (0x40 | LIM2_LOS1 | dja));
936 cpc_writeb(falcbase + F_REG(XPM0, ch), 0x11);
937 cpc_writeb(falcbase + F_REG(XPM1, ch), 0x02);
938 cpc_writeb(falcbase + F_REG(XPM2, ch), 0x20);
939 break;
940 case PC300_LBO_15_DB:
941 cpc_writeb(falcbase + F_REG(LIM2, ch), (0x80 | LIM2_LOS1 | dja));
942 cpc_writeb(falcbase + F_REG(XPM0, ch), 0x8e);
943 cpc_writeb(falcbase + F_REG(XPM1, ch), 0x01);
944 cpc_writeb(falcbase + F_REG(XPM2, ch), 0x20);
945 break;
946 case PC300_LBO_22_5_DB:
947 cpc_writeb(falcbase + F_REG(LIM2, ch), (0xc0 | LIM2_LOS1 | dja));
948 cpc_writeb(falcbase + F_REG(XPM0, ch), 0x09);
949 cpc_writeb(falcbase + F_REG(XPM1, ch), 0x01);
950 cpc_writeb(falcbase + F_REG(XPM2, ch), 0x20);
951 break;
952 }
953
954 /* Transmit Clock-Slot Offset */
955 cpc_writeb(falcbase + F_REG(XC0, ch),
956 cpc_readb(falcbase + F_REG(XC0, ch)) | 0x01);
957 /* Transmit Time-slot Offset */
958 cpc_writeb(falcbase + F_REG(XC1, ch), 0x3e);
959 /* Receive Clock-Slot offset */
960 cpc_writeb(falcbase + F_REG(RC0, ch), 0x05);
961 /* Receive Time-slot offset */
962 cpc_writeb(falcbase + F_REG(RC1, ch), 0x00);
963
964 /* LOS Detection after 176 consecutive 0s */
965 cpc_writeb(falcbase + F_REG(PCDR, ch), 0x0a);
966 /* LOS Recovery after 22 ones in the time window of PCD */
967 cpc_writeb(falcbase + F_REG(PCRR, ch), 0x15);
968
969 cpc_writeb(falcbase + F_REG(IDLE, ch), 0x7f);
970
971 if (conf->fr_mode == PC300_FR_ESF_JAPAN) {
972 cpc_writeb(falcbase + F_REG(RC1, ch),
973 cpc_readb(falcbase + F_REG(RC1, ch)) | 0x80);
974 }
975
976 falc_close_all_timeslots(card, ch);
977}
978
979static void falc_init_e1(pc300_t * card, int ch)
980{
981 pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
982 pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
983 falc_t *pfalc = (falc_t *) & chan->falc;
984 void __iomem *falcbase = card->hw.falcbase;
985 u8 dja = (ch ? (LIM2_DJA2 | LIM2_DJA1) : 0);
986
987 /* Switch to E1 mode (PCM 30) */
988 cpc_writeb(falcbase + F_REG(FMR1, ch),
989 cpc_readb(falcbase + F_REG(FMR1, ch)) & ~FMR1_PMOD);
990
991 /* Clock mode */
992 if (conf->phys_settings.clock_type == CLOCK_INT) { /* Master mode */
993 cpc_writeb(falcbase + F_REG(LIM0, ch),
994 cpc_readb(falcbase + F_REG(LIM0, ch)) | LIM0_MAS);
995 } else { /* Slave mode */
996 cpc_writeb(falcbase + F_REG(LIM0, ch),
997 cpc_readb(falcbase + F_REG(LIM0, ch)) & ~LIM0_MAS);
998 }
999 cpc_writeb(falcbase + F_REG(LOOP, ch),
1000 cpc_readb(falcbase + F_REG(LOOP, ch)) & ~LOOP_SFM);
1001
1002 cpc_writeb(falcbase + F_REG(IPC, ch), IPC_SCI);
1003 cpc_writeb(falcbase + F_REG(FMR0, ch),
1004 cpc_readb(falcbase + F_REG(FMR0, ch)) &
1005 ~(FMR0_XC0 | FMR0_XC1 | FMR0_RC0 | FMR0_RC1));
1006
1007 switch (conf->lcode) {
1008 case PC300_LC_AMI:
1009 cpc_writeb(falcbase + F_REG(FMR0, ch),
1010 cpc_readb(falcbase + F_REG(FMR0, ch)) |
1011 FMR0_XC1 | FMR0_RC1);
1012 break;
1013
1014 case PC300_LC_HDB3:
1015 cpc_writeb(falcbase + F_REG(FMR0, ch),
1016 cpc_readb(falcbase + F_REG(FMR0, ch)) |
1017 FMR0_XC0 | FMR0_XC1 | FMR0_RC0 | FMR0_RC1);
1018 break;
1019
1020 case PC300_LC_NRZ:
1021 break;
1022 }
1023
1024 cpc_writeb(falcbase + F_REG(LIM0, ch),
1025 cpc_readb(falcbase + F_REG(LIM0, ch)) & ~(LIM0_SCL1 | LIM0_SCL0));
1026 /* Set interface mode to 2 MBPS */
1027 cpc_writeb(falcbase + F_REG(FMR1, ch),
1028 cpc_readb(falcbase + F_REG(FMR1, ch)) | FMR1_IMOD);
1029
1030 cpc_writeb(falcbase + F_REG(XPM0, ch), 0x18);
1031 cpc_writeb(falcbase + F_REG(XPM1, ch), 0x03);
1032 cpc_writeb(falcbase + F_REG(XPM2, ch), 0x00);
1033
1034 switch (conf->fr_mode) {
1035 case PC300_FR_MF_CRC4:
1036 pfalc->multiframe_mode = 1;
1037 cpc_writeb(falcbase + F_REG(FMR1, ch),
1038 cpc_readb(falcbase + F_REG(FMR1, ch)) | FMR1_XFS);
1039 cpc_writeb(falcbase + F_REG(FMR2, ch),
1040 cpc_readb(falcbase + F_REG(FMR2, ch)) | FMR2_RFS1);
1041 cpc_writeb(falcbase + F_REG(FMR2, ch),
1042 cpc_readb(falcbase + F_REG(FMR2, ch)) & ~FMR2_RFS0);
1043 cpc_writeb(falcbase + F_REG(FMR3, ch),
1044 cpc_readb(falcbase + F_REG(FMR3, ch)) & ~FMR3_EXTIW);
1045
1046 /* MultiFrame Resynchronization */
1047 cpc_writeb(falcbase + F_REG(FMR1, ch),
1048 cpc_readb(falcbase + F_REG(FMR1, ch)) | FMR1_MFCS);
1049
1050 /* Automatic Loss of Multiframe > 914 CRC errors */
1051 cpc_writeb(falcbase + F_REG(FMR2, ch),
1052 cpc_readb(falcbase + F_REG(FMR2, ch)) | FMR2_ALMF);
1053
1054 /* S1 and SI1/SI2 spare Bits set to 1 */
1055 cpc_writeb(falcbase + F_REG(XSP, ch),
1056 cpc_readb(falcbase + F_REG(XSP, ch)) & ~XSP_AXS);
1057 cpc_writeb(falcbase + F_REG(XSP, ch),
1058 cpc_readb(falcbase + F_REG(XSP, ch)) | XSP_EBP);
1059 cpc_writeb(falcbase + F_REG(XSP, ch),
1060 cpc_readb(falcbase + F_REG(XSP, ch)) | XSP_XS13 | XSP_XS15);
1061
1062 /* Automatic Force Resynchronization */
1063 cpc_writeb(falcbase + F_REG(FMR1, ch),
1064 cpc_readb(falcbase + F_REG(FMR1, ch)) | FMR1_AFR);
1065
1066 /* Transmit Automatic Remote Alarm */
1067 cpc_writeb(falcbase + F_REG(FMR2, ch),
1068 cpc_readb(falcbase + F_REG(FMR2, ch)) | FMR2_AXRA);
1069
1070 /* Transmit Spare Bits for National Use (Y, Sn, Sa) */
1071 cpc_writeb(falcbase + F_REG(XSW, ch),
1072 cpc_readb(falcbase + F_REG(XSW, ch)) |
1073 XSW_XY0 | XSW_XY1 | XSW_XY2 | XSW_XY3 | XSW_XY4);
1074 break;
1075
1076 case PC300_FR_MF_NON_CRC4:
1077 case PC300_FR_D4:
1078 pfalc->multiframe_mode = 0;
1079 cpc_writeb(falcbase + F_REG(FMR1, ch),
1080 cpc_readb(falcbase + F_REG(FMR1, ch)) & ~FMR1_XFS);
1081 cpc_writeb(falcbase + F_REG(FMR2, ch),
1082 cpc_readb(falcbase + F_REG(FMR2, ch)) &
1083 ~(FMR2_RFS1 | FMR2_RFS0));
1084 cpc_writeb(falcbase + F_REG(XSW, ch),
1085 cpc_readb(falcbase + F_REG(XSW, ch)) | XSW_XSIS);
1086 cpc_writeb(falcbase + F_REG(XSP, ch),
1087 cpc_readb(falcbase + F_REG(XSP, ch)) | XSP_XSIF);
1088
1089 /* Automatic Force Resynchronization */
1090 cpc_writeb(falcbase + F_REG(FMR1, ch),
1091 cpc_readb(falcbase + F_REG(FMR1, ch)) | FMR1_AFR);
1092
1093 /* Transmit Automatic Remote Alarm */
1094 cpc_writeb(falcbase + F_REG(FMR2, ch),
1095 cpc_readb(falcbase + F_REG(FMR2, ch)) | FMR2_AXRA);
1096
1097 /* Transmit Spare Bits for National Use (Y, Sn, Sa) */
1098 cpc_writeb(falcbase + F_REG(XSW, ch),
1099 cpc_readb(falcbase + F_REG(XSW, ch)) |
1100 XSW_XY0 | XSW_XY1 | XSW_XY2 | XSW_XY3 | XSW_XY4);
1101 break;
1102
1103 case PC300_FR_UNFRAMED:
1104 pfalc->multiframe_mode = 0;
1105 cpc_writeb(falcbase + F_REG(FMR1, ch),
1106 cpc_readb(falcbase + F_REG(FMR1, ch)) & ~FMR1_XFS);
1107 cpc_writeb(falcbase + F_REG(FMR2, ch),
1108 cpc_readb(falcbase + F_REG(FMR2, ch)) &
1109 ~(FMR2_RFS1 | FMR2_RFS0));
1110 cpc_writeb(falcbase + F_REG(XSP, ch),
1111 cpc_readb(falcbase + F_REG(XSP, ch)) | XSP_TT0);
1112 cpc_writeb(falcbase + F_REG(XSW, ch),
1113 cpc_readb(falcbase + F_REG(XSW, ch)) &
1114 ~(XSW_XTM|XSW_XY0|XSW_XY1|XSW_XY2|XSW_XY3|XSW_XY4));
1115 cpc_writeb(falcbase + F_REG(TSWM, ch), 0xff);
1116 cpc_writeb(falcbase + F_REG(FMR2, ch),
1117 cpc_readb(falcbase + F_REG(FMR2, ch)) |
1118 (FMR2_RTM | FMR2_DAIS));
1119 cpc_writeb(falcbase + F_REG(FMR2, ch),
1120 cpc_readb(falcbase + F_REG(FMR2, ch)) & ~FMR2_AXRA);
1121 cpc_writeb(falcbase + F_REG(FMR1, ch),
1122 cpc_readb(falcbase + F_REG(FMR1, ch)) & ~FMR1_AFR);
1123 pfalc->sync = 1;
1124 cpc_writeb(falcbase + card->hw.cpld_reg2,
1125 cpc_readb(falcbase + card->hw.cpld_reg2) |
1126 (CPLD_REG2_FALC_LED2 << (2 * ch)));
1127 break;
1128 }
1129
1130 /* No signaling */
1131 cpc_writeb(falcbase + F_REG(XSP, ch),
1132 cpc_readb(falcbase + F_REG(XSP, ch)) & ~XSP_CASEN);
1133 cpc_writeb(falcbase + F_REG(CCR1, ch), 0);
1134
1135 cpc_writeb(falcbase + F_REG(LIM1, ch),
1136 cpc_readb(falcbase + F_REG(LIM1, ch)) | LIM1_RIL0 | LIM1_RIL1);
1137 cpc_writeb(falcbase + F_REG(LIM2, ch), (LIM2_LOS1 | dja));
1138
1139 /* Transmit Clock-Slot Offset */
1140 cpc_writeb(falcbase + F_REG(XC0, ch),
1141 cpc_readb(falcbase + F_REG(XC0, ch)) | 0x01);
1142 /* Transmit Time-slot Offset */
1143 cpc_writeb(falcbase + F_REG(XC1, ch), 0x3e);
1144 /* Receive Clock-Slot offset */
1145 cpc_writeb(falcbase + F_REG(RC0, ch), 0x05);
1146 /* Receive Time-slot offset */
1147 cpc_writeb(falcbase + F_REG(RC1, ch), 0x00);
1148
1149 /* LOS Detection after 176 consecutive 0s */
1150 cpc_writeb(falcbase + F_REG(PCDR, ch), 0x0a);
1151 /* LOS Recovery after 22 ones in the time window of PCD */
1152 cpc_writeb(falcbase + F_REG(PCRR, ch), 0x15);
1153
1154 cpc_writeb(falcbase + F_REG(IDLE, ch), 0x7f);
1155
1156 falc_close_all_timeslots(card, ch);
1157}
1158
1159static void falc_init_hdlc(pc300_t * card, int ch)
1160{
1161 void __iomem *falcbase = card->hw.falcbase;
1162 pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
1163 pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
1164
1165 /* Enable transparent data transfer */
1166 if (conf->fr_mode == PC300_FR_UNFRAMED) {
1167 cpc_writeb(falcbase + F_REG(MODE, ch), 0);
1168 } else {
1169 cpc_writeb(falcbase + F_REG(MODE, ch),
1170 cpc_readb(falcbase + F_REG(MODE, ch)) |
1171 (MODE_HRAC | MODE_MDS2));
1172 cpc_writeb(falcbase + F_REG(RAH2, ch), 0xff);
1173 cpc_writeb(falcbase + F_REG(RAH1, ch), 0xff);
1174 cpc_writeb(falcbase + F_REG(RAL2, ch), 0xff);
1175 cpc_writeb(falcbase + F_REG(RAL1, ch), 0xff);
1176 }
1177
1178 /* Tx/Rx reset */
1179 falc_issue_cmd(card, ch, CMDR_RRES | CMDR_XRES | CMDR_SRES);
1180
1181 /* Enable interrupt sources */
1182 falc_intr_enable(card, ch);
1183}
1184
1185static void te_config(pc300_t * card, int ch)
1186{
1187 pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
1188 pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
1189 falc_t *pfalc = (falc_t *) & chan->falc;
1190 void __iomem *falcbase = card->hw.falcbase;
1191 u8 dummy;
1192 unsigned long flags;
1193
1194 memset(pfalc, 0, sizeof(falc_t));
1195 switch (conf->media) {
1196 case IF_IFACE_T1:
1197 pfalc->num_channels = NUM_OF_T1_CHANNELS;
1198 pfalc->offset = 1;
1199 break;
1200 case IF_IFACE_E1:
1201 pfalc->num_channels = NUM_OF_E1_CHANNELS;
1202 pfalc->offset = 0;
1203 break;
1204 }
1205 if (conf->tslot_bitmap == 0xffffffffUL)
1206 pfalc->full_bandwidth = 1;
1207 else
1208 pfalc->full_bandwidth = 0;
1209
1210 CPC_LOCK(card, flags);
1211 /* Reset the FALC chip */
1212 cpc_writeb(card->hw.falcbase + card->hw.cpld_reg1,
1213 cpc_readb(card->hw.falcbase + card->hw.cpld_reg1) |
1214 (CPLD_REG1_FALC_RESET << (2 * ch)));
1215 udelay(10000);
1216 cpc_writeb(card->hw.falcbase + card->hw.cpld_reg1,
1217 cpc_readb(card->hw.falcbase + card->hw.cpld_reg1) &
1218 ~(CPLD_REG1_FALC_RESET << (2 * ch)));
1219
1220 if (conf->media == IF_IFACE_T1) {
1221 falc_init_t1(card, ch);
1222 } else {
1223 falc_init_e1(card, ch);
1224 }
1225 falc_init_hdlc(card, ch);
1226 if (conf->rx_sens == PC300_RX_SENS_SH) {
1227 cpc_writeb(falcbase + F_REG(LIM0, ch),
1228 cpc_readb(falcbase + F_REG(LIM0, ch)) & ~LIM0_EQON);
1229 } else {
1230 cpc_writeb(falcbase + F_REG(LIM0, ch),
1231 cpc_readb(falcbase + F_REG(LIM0, ch)) | LIM0_EQON);
1232 }
1233 cpc_writeb(card->hw.falcbase + card->hw.cpld_reg2,
1234 cpc_readb(card->hw.falcbase + card->hw.cpld_reg2) |
1235 ((CPLD_REG2_FALC_TX_CLK | CPLD_REG2_FALC_RX_CLK) << (2 * ch)));
1236
1237 /* Clear all interrupt registers */
1238 dummy = cpc_readb(falcbase + F_REG(FISR0, ch)) +
1239 cpc_readb(falcbase + F_REG(FISR1, ch)) +
1240 cpc_readb(falcbase + F_REG(FISR2, ch)) +
1241 cpc_readb(falcbase + F_REG(FISR3, ch));
1242 CPC_UNLOCK(card, flags);
1243}
1244
1245static void falc_check_status(pc300_t * card, int ch, unsigned char frs0)
1246{
1247 pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
1248 pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
1249 falc_t *pfalc = (falc_t *) & chan->falc;
1250 void __iomem *falcbase = card->hw.falcbase;
1251
1252 /* Verify LOS */
1253 if (frs0 & FRS0_LOS) {
1254 if (!pfalc->red_alarm) {
1255 pfalc->red_alarm = 1;
1256 pfalc->los++;
1257 if (!pfalc->blue_alarm) {
1258 // EVENT_FALC_ABNORMAL
1259 if (conf->media == IF_IFACE_T1) {
1260 /* Disable this interrupt as it may otherwise interfere
1261 * with other working boards. */
1262 cpc_writeb(falcbase + F_REG(IMR0, ch),
1263 cpc_readb(falcbase + F_REG(IMR0, ch))
1264 | IMR0_PDEN);
1265 }
1266 falc_disable_comm(card, ch);
1267 // EVENT_FALC_ABNORMAL
1268 }
1269 }
1270 } else {
1271 if (pfalc->red_alarm) {
1272 pfalc->red_alarm = 0;
1273 pfalc->losr++;
1274 }
1275 }
1276
1277 if (conf->fr_mode != PC300_FR_UNFRAMED) {
1278 /* Verify AIS alarm */
1279 if (frs0 & FRS0_AIS) {
1280 if (!pfalc->blue_alarm) {
1281 pfalc->blue_alarm = 1;
1282 pfalc->ais++;
1283 // EVENT_AIS
1284 if (conf->media == IF_IFACE_T1) {
1285 /* Disable this interrupt as it may otherwise interfere with other working boards. */
1286 cpc_writeb(falcbase + F_REG(IMR0, ch),
1287 cpc_readb(falcbase + F_REG(IMR0, ch)) | IMR0_PDEN);
1288 }
1289 falc_disable_comm(card, ch);
1290 // EVENT_AIS
1291 }
1292 } else {
1293 pfalc->blue_alarm = 0;
1294 }
1295
1296 /* Verify LFA */
1297 if (frs0 & FRS0_LFA) {
1298 if (!pfalc->loss_fa) {
1299 pfalc->loss_fa = 1;
1300 pfalc->lfa++;
1301 if (!pfalc->blue_alarm && !pfalc->red_alarm) {
1302 // EVENT_FALC_ABNORMAL
1303 if (conf->media == IF_IFACE_T1) {
1304 /* Disable this interrupt as it may otherwise
1305 * interfere with other working boards. */
1306 cpc_writeb(falcbase + F_REG(IMR0, ch),
1307 cpc_readb(falcbase + F_REG(IMR0, ch))
1308 | IMR0_PDEN);
1309 }
1310 falc_disable_comm(card, ch);
1311 // EVENT_FALC_ABNORMAL
1312 }
1313 }
1314 } else {
1315 if (pfalc->loss_fa) {
1316 pfalc->loss_fa = 0;
1317 pfalc->farec++;
1318 }
1319 }
1320
1321 /* Verify LMFA */
1322 if (pfalc->multiframe_mode && (frs0 & FRS0_LMFA)) {
1323 /* D4 or CRC4 frame mode */
1324 if (!pfalc->loss_mfa) {
1325 pfalc->loss_mfa = 1;
1326 pfalc->lmfa++;
1327 if (!pfalc->blue_alarm && !pfalc->red_alarm &&
1328 !pfalc->loss_fa) {
1329 // EVENT_FALC_ABNORMAL
1330 if (conf->media == IF_IFACE_T1) {
1331 /* Disable this interrupt as it may otherwise
1332 * interfere with other working boards. */
1333 cpc_writeb(falcbase + F_REG(IMR0, ch),
1334 cpc_readb(falcbase + F_REG(IMR0, ch))
1335 | IMR0_PDEN);
1336 }
1337 falc_disable_comm(card, ch);
1338 // EVENT_FALC_ABNORMAL
1339 }
1340 }
1341 } else {
1342 pfalc->loss_mfa = 0;
1343 }
1344
1345 /* Verify Remote Alarm */
1346 if (frs0 & FRS0_RRA) {
1347 if (!pfalc->yellow_alarm) {
1348 pfalc->yellow_alarm = 1;
1349 pfalc->rai++;
1350 if (pfalc->sync) {
1351 // EVENT_RAI
1352 falc_disable_comm(card, ch);
1353 // EVENT_RAI
1354 }
1355 }
1356 } else {
1357 pfalc->yellow_alarm = 0;
1358 }
1359 } /* if !PC300_UNFRAMED */
1360
1361 if (pfalc->red_alarm || pfalc->loss_fa ||
1362 pfalc->loss_mfa || pfalc->blue_alarm) {
1363 if (pfalc->sync) {
1364 pfalc->sync = 0;
1365 chan->d.line_off++;
1366 cpc_writeb(falcbase + card->hw.cpld_reg2,
1367 cpc_readb(falcbase + card->hw.cpld_reg2) &
1368 ~(CPLD_REG2_FALC_LED2 << (2 * ch)));
1369 }
1370 } else {
1371 if (!pfalc->sync) {
1372 pfalc->sync = 1;
1373 chan->d.line_on++;
1374 cpc_writeb(falcbase + card->hw.cpld_reg2,
1375 cpc_readb(falcbase + card->hw.cpld_reg2) |
1376 (CPLD_REG2_FALC_LED2 << (2 * ch)));
1377 }
1378 }
1379
1380 if (pfalc->sync && !pfalc->yellow_alarm) {
1381 if (!pfalc->active) {
1382 // EVENT_FALC_NORMAL
1383 if (pfalc->loop_active) {
1384 return;
1385 }
1386 if (conf->media == IF_IFACE_T1) {
1387 cpc_writeb(falcbase + F_REG(IMR0, ch),
1388 cpc_readb(falcbase + F_REG(IMR0, ch)) & ~IMR0_PDEN);
1389 }
1390 falc_enable_comm(card, ch);
1391 // EVENT_FALC_NORMAL
1392 pfalc->active = 1;
1393 }
1394 } else {
1395 if (pfalc->active) {
1396 pfalc->active = 0;
1397 }
1398 }
1399}
1400
1401static void falc_update_stats(pc300_t * card, int ch)
1402{
1403 pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
1404 pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
1405 falc_t *pfalc = (falc_t *) & chan->falc;
1406 void __iomem *falcbase = card->hw.falcbase;
1407 u16 counter;
1408
1409 counter = cpc_readb(falcbase + F_REG(FECL, ch));
1410 counter |= cpc_readb(falcbase + F_REG(FECH, ch)) << 8;
1411 pfalc->fec += counter;
1412
1413 counter = cpc_readb(falcbase + F_REG(CVCL, ch));
1414 counter |= cpc_readb(falcbase + F_REG(CVCH, ch)) << 8;
1415 pfalc->cvc += counter;
1416
1417 counter = cpc_readb(falcbase + F_REG(CECL, ch));
1418 counter |= cpc_readb(falcbase + F_REG(CECH, ch)) << 8;
1419 pfalc->cec += counter;
1420
1421 counter = cpc_readb(falcbase + F_REG(EBCL, ch));
1422 counter |= cpc_readb(falcbase + F_REG(EBCH, ch)) << 8;
1423 pfalc->ebc += counter;
1424
1425 if (cpc_readb(falcbase + F_REG(LCR1, ch)) & LCR1_EPRM) {
1426 mdelay(10);
1427 counter = cpc_readb(falcbase + F_REG(BECL, ch));
1428 counter |= cpc_readb(falcbase + F_REG(BECH, ch)) << 8;
1429 pfalc->bec += counter;
1430
1431 if (((conf->media == IF_IFACE_T1) &&
1432 (cpc_readb(falcbase + F_REG(FRS1, ch)) & FRS1_LLBAD) &&
1433 (!(cpc_readb(falcbase + F_REG(FRS1, ch)) & FRS1_PDEN))) ||
1434 ((conf->media == IF_IFACE_E1) &&
1435 (cpc_readb(falcbase + F_REG(RSP, ch)) & RSP_LLBAD))) {
1436 pfalc->prbs = 2;
1437 } else {
1438 pfalc->prbs = 1;
1439 }
1440 }
1441}
1442
1443/*----------------------------------------------------------------------------
1444 * falc_remote_loop
1445 *----------------------------------------------------------------------------
1446 * Description: In the remote loopback mode the clock and data recovered
1447 * from the line inputs RL1/2 or RDIP/RDIN are routed back
1448 * to the line outputs XL1/2 or XDOP/XDON via the analog
1449 * transmitter. As in normal mode they are processed by
1450 * the synchronizer and then sent to the system interface.
1451 *----------------------------------------------------------------------------
1452 */
1453static void falc_remote_loop(pc300_t * card, int ch, int loop_on)
1454{
1455 pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
1456 pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
1457 falc_t *pfalc = (falc_t *) & chan->falc;
1458 void __iomem *falcbase = card->hw.falcbase;
1459
1460 if (loop_on) {
1461 // EVENT_FALC_ABNORMAL
1462 if (conf->media == IF_IFACE_T1) {
1463 /* Disable this interrupt as it may otherwise interfere with
1464 * other working boards. */
1465 cpc_writeb(falcbase + F_REG(IMR0, ch),
1466 cpc_readb(falcbase + F_REG(IMR0, ch)) | IMR0_PDEN);
1467 }
1468 falc_disable_comm(card, ch);
1469 // EVENT_FALC_ABNORMAL
1470 cpc_writeb(falcbase + F_REG(LIM1, ch),
1471 cpc_readb(falcbase + F_REG(LIM1, ch)) | LIM1_RL);
1472 pfalc->loop_active = 1;
1473 } else {
1474 cpc_writeb(falcbase + F_REG(LIM1, ch),
1475 cpc_readb(falcbase + F_REG(LIM1, ch)) & ~LIM1_RL);
1476 pfalc->sync = 0;
1477 cpc_writeb(falcbase + card->hw.cpld_reg2,
1478 cpc_readb(falcbase + card->hw.cpld_reg2) &
1479 ~(CPLD_REG2_FALC_LED2 << (2 * ch)));
1480 pfalc->active = 0;
1481 falc_issue_cmd(card, ch, CMDR_XRES);
1482 pfalc->loop_active = 0;
1483 }
1484}
1485
1486/*----------------------------------------------------------------------------
1487 * falc_local_loop
1488 *----------------------------------------------------------------------------
1489 * Description: The local loopback mode disconnects the receive lines
1490 * RL1/RL2 resp. RDIP/RDIN from the receiver. Instead of the
1491 * signals coming from the line the data provided by system
1492 * interface are routed through the analog receiver back to
1493 * the system interface. The unipolar bit stream will be
1494 * undisturbed transmitted on the line. Receiver and transmitter
1495 * coding must be identical.
1496 *----------------------------------------------------------------------------
1497 */
1498static void falc_local_loop(pc300_t * card, int ch, int loop_on)
1499{
1500 pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
1501 falc_t *pfalc = (falc_t *) & chan->falc;
1502 void __iomem *falcbase = card->hw.falcbase;
1503
1504 if (loop_on) {
1505 cpc_writeb(falcbase + F_REG(LIM0, ch),
1506 cpc_readb(falcbase + F_REG(LIM0, ch)) | LIM0_LL);
1507 pfalc->loop_active = 1;
1508 } else {
1509 cpc_writeb(falcbase + F_REG(LIM0, ch),
1510 cpc_readb(falcbase + F_REG(LIM0, ch)) & ~LIM0_LL);
1511 pfalc->loop_active = 0;
1512 }
1513}
1514
1515/*----------------------------------------------------------------------------
1516 * falc_payload_loop
1517 *----------------------------------------------------------------------------
1518 * Description: This routine allows to enable/disable payload loopback.
1519 * When the payload loop is activated, the received 192 bits
1520 * of payload data will be looped back to the transmit
1521 * direction. The framing bits, CRC6 and DL bits are not
1522 * looped. They are originated by the FALC-LH transmitter.
1523 *----------------------------------------------------------------------------
1524 */
1525static void falc_payload_loop(pc300_t * card, int ch, int loop_on)
1526{
1527 pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
1528 pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
1529 falc_t *pfalc = (falc_t *) & chan->falc;
1530 void __iomem *falcbase = card->hw.falcbase;
1531
1532 if (loop_on) {
1533 // EVENT_FALC_ABNORMAL
1534 if (conf->media == IF_IFACE_T1) {
1535 /* Disable this interrupt as it may otherwise interfere with
1536 * other working boards. */
1537 cpc_writeb(falcbase + F_REG(IMR0, ch),
1538 cpc_readb(falcbase + F_REG(IMR0, ch)) | IMR0_PDEN);
1539 }
1540 falc_disable_comm(card, ch);
1541 // EVENT_FALC_ABNORMAL
1542 cpc_writeb(falcbase + F_REG(FMR2, ch),
1543 cpc_readb(falcbase + F_REG(FMR2, ch)) | FMR2_PLB);
1544 if (conf->media == IF_IFACE_T1) {
1545 cpc_writeb(falcbase + F_REG(FMR4, ch),
1546 cpc_readb(falcbase + F_REG(FMR4, ch)) | FMR4_TM);
1547 } else {
1548 cpc_writeb(falcbase + F_REG(FMR5, ch),
1549 cpc_readb(falcbase + F_REG(FMR5, ch)) | XSP_TT0);
1550 }
1551 falc_open_all_timeslots(card, ch);
1552 pfalc->loop_active = 2;
1553 } else {
1554 cpc_writeb(falcbase + F_REG(FMR2, ch),
1555 cpc_readb(falcbase + F_REG(FMR2, ch)) & ~FMR2_PLB);
1556 if (conf->media == IF_IFACE_T1) {
1557 cpc_writeb(falcbase + F_REG(FMR4, ch),
1558 cpc_readb(falcbase + F_REG(FMR4, ch)) & ~FMR4_TM);
1559 } else {
1560 cpc_writeb(falcbase + F_REG(FMR5, ch),
1561 cpc_readb(falcbase + F_REG(FMR5, ch)) & ~XSP_TT0);
1562 }
1563 pfalc->sync = 0;
1564 cpc_writeb(falcbase + card->hw.cpld_reg2,
1565 cpc_readb(falcbase + card->hw.cpld_reg2) &
1566 ~(CPLD_REG2_FALC_LED2 << (2 * ch)));
1567 pfalc->active = 0;
1568 falc_issue_cmd(card, ch, CMDR_XRES);
1569 pfalc->loop_active = 0;
1570 }
1571}
1572
1573/*----------------------------------------------------------------------------
1574 * turn_off_xlu
1575 *----------------------------------------------------------------------------
1576 * Description: Turns XLU bit off in the proper register
1577 *----------------------------------------------------------------------------
1578 */
1579static void turn_off_xlu(pc300_t * card, int ch)
1580{
1581 pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
1582 pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
1583 void __iomem *falcbase = card->hw.falcbase;
1584
1585 if (conf->media == IF_IFACE_T1) {
1586 cpc_writeb(falcbase + F_REG(FMR5, ch),
1587 cpc_readb(falcbase + F_REG(FMR5, ch)) & ~FMR5_XLU);
1588 } else {
1589 cpc_writeb(falcbase + F_REG(FMR3, ch),
1590 cpc_readb(falcbase + F_REG(FMR3, ch)) & ~FMR3_XLU);
1591 }
1592}
1593
1594/*----------------------------------------------------------------------------
1595 * turn_off_xld
1596 *----------------------------------------------------------------------------
1597 * Description: Turns XLD bit off in the proper register
1598 *----------------------------------------------------------------------------
1599 */
1600static void turn_off_xld(pc300_t * card, int ch)
1601{
1602 pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
1603 pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
1604 void __iomem *falcbase = card->hw.falcbase;
1605
1606 if (conf->media == IF_IFACE_T1) {
1607 cpc_writeb(falcbase + F_REG(FMR5, ch),
1608 cpc_readb(falcbase + F_REG(FMR5, ch)) & ~FMR5_XLD);
1609 } else {
1610 cpc_writeb(falcbase + F_REG(FMR3, ch),
1611 cpc_readb(falcbase + F_REG(FMR3, ch)) & ~FMR3_XLD);
1612 }
1613}
1614
1615/*----------------------------------------------------------------------------
1616 * falc_generate_loop_up_code
1617 *----------------------------------------------------------------------------
1618 * Description: This routine writes the proper FALC chip register in order
1619 * to generate a LOOP activation code over a T1/E1 line.
1620 *----------------------------------------------------------------------------
1621 */
1622static void falc_generate_loop_up_code(pc300_t * card, int ch)
1623{
1624 pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
1625 pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
1626 falc_t *pfalc = (falc_t *) & chan->falc;
1627 void __iomem *falcbase = card->hw.falcbase;
1628
1629 if (conf->media == IF_IFACE_T1) {
1630 cpc_writeb(falcbase + F_REG(FMR5, ch),
1631 cpc_readb(falcbase + F_REG(FMR5, ch)) | FMR5_XLU);
1632 } else {
1633 cpc_writeb(falcbase + F_REG(FMR3, ch),
1634 cpc_readb(falcbase + F_REG(FMR3, ch)) | FMR3_XLU);
1635 }
1636 // EVENT_FALC_ABNORMAL
1637 if (conf->media == IF_IFACE_T1) {
1638 /* Disable this interrupt as it may otherwise interfere with
1639 * other working boards. */
1640 cpc_writeb(falcbase + F_REG(IMR0, ch),
1641 cpc_readb(falcbase + F_REG(IMR0, ch)) | IMR0_PDEN);
1642 }
1643 falc_disable_comm(card, ch);
1644 // EVENT_FALC_ABNORMAL
1645 pfalc->loop_gen = 1;
1646}
1647
1648/*----------------------------------------------------------------------------
1649 * falc_generate_loop_down_code
1650 *----------------------------------------------------------------------------
1651 * Description: This routine writes the proper FALC chip register in order
1652 * to generate a LOOP deactivation code over a T1/E1 line.
1653 *----------------------------------------------------------------------------
1654 */
1655static void falc_generate_loop_down_code(pc300_t * card, int ch)
1656{
1657 pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
1658 pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
1659 falc_t *pfalc = (falc_t *) & chan->falc;
1660 void __iomem *falcbase = card->hw.falcbase;
1661
1662 if (conf->media == IF_IFACE_T1) {
1663 cpc_writeb(falcbase + F_REG(FMR5, ch),
1664 cpc_readb(falcbase + F_REG(FMR5, ch)) | FMR5_XLD);
1665 } else {
1666 cpc_writeb(falcbase + F_REG(FMR3, ch),
1667 cpc_readb(falcbase + F_REG(FMR3, ch)) | FMR3_XLD);
1668 }
1669 pfalc->sync = 0;
1670 cpc_writeb(falcbase + card->hw.cpld_reg2,
1671 cpc_readb(falcbase + card->hw.cpld_reg2) &
1672 ~(CPLD_REG2_FALC_LED2 << (2 * ch)));
1673 pfalc->active = 0;
1674//? falc_issue_cmd(card, ch, CMDR_XRES);
1675 pfalc->loop_gen = 0;
1676}
1677
1678/*----------------------------------------------------------------------------
1679 * falc_pattern_test
1680 *----------------------------------------------------------------------------
1681 * Description: This routine generates a pattern code and checks
1682 * it on the reception side.
1683 *----------------------------------------------------------------------------
1684 */
1685static void falc_pattern_test(pc300_t * card, int ch, unsigned int activate)
1686{
1687 pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
1688 pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
1689 falc_t *pfalc = (falc_t *) & chan->falc;
1690 void __iomem *falcbase = card->hw.falcbase;
1691
1692 if (activate) {
1693 pfalc->prbs = 1;
1694 pfalc->bec = 0;
1695 if (conf->media == IF_IFACE_T1) {
1696 /* Disable local loop activation/deactivation detect */
1697 cpc_writeb(falcbase + F_REG(IMR3, ch),
1698 cpc_readb(falcbase + F_REG(IMR3, ch)) | IMR3_LLBSC);
1699 } else {
1700 /* Disable local loop activation/deactivation detect */
1701 cpc_writeb(falcbase + F_REG(IMR1, ch),
1702 cpc_readb(falcbase + F_REG(IMR1, ch)) | IMR1_LLBSC);
1703 }
1704 /* Activates generation and monitoring of PRBS
1705 * (Pseudo Random Bit Sequence) */
1706 cpc_writeb(falcbase + F_REG(LCR1, ch),
1707 cpc_readb(falcbase + F_REG(LCR1, ch)) | LCR1_EPRM | LCR1_XPRBS);
1708 } else {
1709 pfalc->prbs = 0;
1710 /* Deactivates generation and monitoring of PRBS
1711 * (Pseudo Random Bit Sequence) */
1712 cpc_writeb(falcbase + F_REG(LCR1, ch),
1713 cpc_readb(falcbase+F_REG(LCR1,ch)) & ~(LCR1_EPRM | LCR1_XPRBS));
1714 if (conf->media == IF_IFACE_T1) {
1715 /* Enable local loop activation/deactivation detect */
1716 cpc_writeb(falcbase + F_REG(IMR3, ch),
1717 cpc_readb(falcbase + F_REG(IMR3, ch)) & ~IMR3_LLBSC);
1718 } else {
1719 /* Enable local loop activation/deactivation detect */
1720 cpc_writeb(falcbase + F_REG(IMR1, ch),
1721 cpc_readb(falcbase + F_REG(IMR1, ch)) & ~IMR1_LLBSC);
1722 }
1723 }
1724}
1725
1726/*----------------------------------------------------------------------------
1727 * falc_pattern_test_error
1728 *----------------------------------------------------------------------------
1729 * Description: This routine returns the bit error counter value
1730 *----------------------------------------------------------------------------
1731 */
1732static u16 falc_pattern_test_error(pc300_t * card, int ch)
1733{
1734 pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
1735 falc_t *pfalc = (falc_t *) & chan->falc;
1736
1737 return pfalc->bec;
1738}
1739
1740/**********************************/
1741/*** Net Interface Routines ***/
1742/**********************************/
1743
1744static void
1745cpc_trace(struct net_device *dev, struct sk_buff *skb_main, char rx_tx)
1746{
1747 struct sk_buff *skb;
1748
1749 if ((skb = dev_alloc_skb(10 + skb_main->len)) == NULL) {
1750 printk("%s: out of memory\n", dev->name);
1751 return;
1752 }
1753 skb_put(skb, 10 + skb_main->len);
1754
1755 skb->dev = dev;
1756 skb->protocol = htons(ETH_P_CUST);
1757 skb_reset_mac_header(skb);
1758 skb->pkt_type = PACKET_HOST;
1759 skb->len = 10 + skb_main->len;
1760
1761 skb_copy_to_linear_data(skb, dev->name, 5);
1762 skb->data[5] = '[';
1763 skb->data[6] = rx_tx;
1764 skb->data[7] = ']';
1765 skb->data[8] = ':';
1766 skb->data[9] = ' ';
1767 skb_copy_from_linear_data(skb_main, &skb->data[10], skb_main->len);
1768
1769 netif_rx(skb);
1770}
1771
1772static void cpc_tx_timeout(struct net_device *dev)
1773{
1774 pc300dev_t *d = (pc300dev_t *) dev_to_hdlc(dev)->priv;
1775 pc300ch_t *chan = (pc300ch_t *) d->chan;
1776 pc300_t *card = (pc300_t *) chan->card;
1777 int ch = chan->channel;
1778 unsigned long flags;
1779 u8 ilar;
1780
1781 dev->stats.tx_errors++;
1782 dev->stats.tx_aborted_errors++;
1783 CPC_LOCK(card, flags);
1784 if ((ilar = cpc_readb(card->hw.scabase + ILAR)) != 0) {
1785 printk("%s: ILAR=0x%x\n", dev->name, ilar);
1786 cpc_writeb(card->hw.scabase + ILAR, ilar);
1787 cpc_writeb(card->hw.scabase + DMER, 0x80);
1788 }
1789 if (card->hw.type == PC300_TE) {
1790 cpc_writeb(card->hw.falcbase + card->hw.cpld_reg2,
1791 cpc_readb(card->hw.falcbase + card->hw.cpld_reg2) &
1792 ~(CPLD_REG2_FALC_LED1 << (2 * ch)));
1793 }
1794 dev->trans_start = jiffies; /* prevent tx timeout */
1795 CPC_UNLOCK(card, flags);
1796 netif_wake_queue(dev);
1797}
1798
1799static int cpc_queue_xmit(struct sk_buff *skb, struct net_device *dev)
1800{
1801 pc300dev_t *d = (pc300dev_t *) dev_to_hdlc(dev)->priv;
1802 pc300ch_t *chan = (pc300ch_t *) d->chan;
1803 pc300_t *card = (pc300_t *) chan->card;
1804 int ch = chan->channel;
1805 unsigned long flags;
1806#ifdef PC300_DEBUG_TX
1807 int i;
1808#endif
1809
1810 if (!netif_carrier_ok(dev)) {
1811 /* DCD must be OFF: drop packet */
1812 dev_kfree_skb(skb);
1813 dev->stats.tx_errors++;
1814 dev->stats.tx_carrier_errors++;
1815 return 0;
1816 } else if (cpc_readb(card->hw.scabase + M_REG(ST3, ch)) & ST3_DCD) {
1817 printk("%s: DCD is OFF. Going administrative down.\n", dev->name);
1818 dev->stats.tx_errors++;
1819 dev->stats.tx_carrier_errors++;
1820 dev_kfree_skb(skb);
1821 netif_carrier_off(dev);
1822 CPC_LOCK(card, flags);
1823 cpc_writeb(card->hw.scabase + M_REG(CMD, ch), CMD_TX_BUF_CLR);
1824 if (card->hw.type == PC300_TE) {
1825 cpc_writeb(card->hw.falcbase + card->hw.cpld_reg2,
1826 cpc_readb(card->hw.falcbase + card->hw.cpld_reg2) &
1827 ~(CPLD_REG2_FALC_LED1 << (2 * ch)));
1828 }
1829 CPC_UNLOCK(card, flags);
1830 netif_wake_queue(dev);
1831 return 0;
1832 }
1833
1834 /* Write buffer to DMA buffers */
1835 if (dma_buf_write(card, ch, (u8 *)skb->data, skb->len) != 0) {
1836// printk("%s: write error. Dropping TX packet.\n", dev->name);
1837 netif_stop_queue(dev);
1838 dev_kfree_skb(skb);
1839 dev->stats.tx_errors++;
1840 dev->stats.tx_dropped++;
1841 return 0;
1842 }
1843#ifdef PC300_DEBUG_TX
1844 printk("%s T:", dev->name);
1845 for (i = 0; i < skb->len; i++)
1846 printk(" %02x", *(skb->data + i));
1847 printk("\n");
1848#endif
1849
1850 if (d->trace_on) {
1851 cpc_trace(dev, skb, 'T');
1852 }
1853
1854 /* Start transmission */
1855 CPC_LOCK(card, flags);
1856 /* verify if it has more than one free descriptor */
1857 if (card->chan[ch].nfree_tx_bd <= 1) {
1858 /* don't have so stop the queue */
1859 netif_stop_queue(dev);
1860 }
1861 cpc_writel(card->hw.scabase + DTX_REG(EDAL, ch),
1862 TX_BD_ADDR(ch, chan->tx_next_bd));
1863 cpc_writeb(card->hw.scabase + M_REG(CMD, ch), CMD_TX_ENA);
1864 cpc_writeb(card->hw.scabase + DSR_TX(ch), DSR_DE);
1865 if (card->hw.type == PC300_TE) {
1866 cpc_writeb(card->hw.falcbase + card->hw.cpld_reg2,
1867 cpc_readb(card->hw.falcbase + card->hw.cpld_reg2) |
1868 (CPLD_REG2_FALC_LED1 << (2 * ch)));
1869 }
1870 CPC_UNLOCK(card, flags);
1871 dev_kfree_skb(skb);
1872
1873 return 0;
1874}
1875
1876static void cpc_net_rx(struct net_device *dev)
1877{
1878 pc300dev_t *d = (pc300dev_t *) dev_to_hdlc(dev)->priv;
1879 pc300ch_t *chan = (pc300ch_t *) d->chan;
1880 pc300_t *card = (pc300_t *) chan->card;
1881 int ch = chan->channel;
1882#ifdef PC300_DEBUG_RX
1883 int i;
1884#endif
1885 int rxb;
1886 struct sk_buff *skb;
1887
1888 while (1) {
1889 if ((rxb = dma_get_rx_frame_size(card, ch)) == -1)
1890 return;
1891
1892 if (!netif_carrier_ok(dev)) {
1893 /* DCD must be OFF: drop packet */
1894 printk("%s : DCD is OFF - drop %d rx bytes\n", dev->name, rxb);
1895 skb = NULL;
1896 } else {
1897 if (rxb > (dev->mtu + 40)) { /* add headers */
1898 printk("%s : MTU exceeded %d\n", dev->name, rxb);
1899 skb = NULL;
1900 } else {
1901 skb = dev_alloc_skb(rxb);
1902 if (skb == NULL) {
1903 printk("%s: Memory squeeze!!\n", dev->name);
1904 return;
1905 }
1906 skb->dev = dev;
1907 }
1908 }
1909
1910 if (((rxb = dma_buf_read(card, ch, skb)) <= 0) || (skb == NULL)) {
1911#ifdef PC300_DEBUG_RX
1912 printk("%s: rxb = %x\n", dev->name, rxb);
1913#endif
1914 if ((skb == NULL) && (rxb > 0)) {
1915 /* rxb > dev->mtu */
1916 dev->stats.rx_errors++;
1917 dev->stats.rx_length_errors++;
1918 continue;
1919 }
1920
1921 if (rxb < 0) { /* Invalid frame */
1922 rxb = -rxb;
1923 if (rxb & DST_OVR) {
1924 dev->stats.rx_errors++;
1925 dev->stats.rx_fifo_errors++;
1926 }
1927 if (rxb & DST_CRC) {
1928 dev->stats.rx_errors++;
1929 dev->stats.rx_crc_errors++;
1930 }
1931 if (rxb & (DST_RBIT | DST_SHRT | DST_ABT)) {
1932 dev->stats.rx_errors++;
1933 dev->stats.rx_frame_errors++;
1934 }
1935 }
1936 if (skb) {
1937 dev_kfree_skb_irq(skb);
1938 }
1939 continue;
1940 }
1941
1942 dev->stats.rx_bytes += rxb;
1943
1944#ifdef PC300_DEBUG_RX
1945 printk("%s R:", dev->name);
1946 for (i = 0; i < skb->len; i++)
1947 printk(" %02x", *(skb->data + i));
1948 printk("\n");
1949#endif
1950 if (d->trace_on) {
1951 cpc_trace(dev, skb, 'R');
1952 }
1953 dev->stats.rx_packets++;
1954 skb->protocol = hdlc_type_trans(skb, dev);
1955 netif_rx(skb);
1956 }
1957}
1958
1959/************************************/
1960/*** PC300 Interrupt Routines ***/
1961/************************************/
1962static void sca_tx_intr(pc300dev_t *dev)
1963{
1964 pc300ch_t *chan = (pc300ch_t *)dev->chan;
1965 pc300_t *card = (pc300_t *)chan->card;
1966 int ch = chan->channel;
1967 volatile pcsca_bd_t __iomem * ptdescr;
1968
1969 /* Clean up descriptors from previous transmission */
1970 ptdescr = (card->hw.rambase +
1971 TX_BD_ADDR(ch,chan->tx_first_bd));
1972 while ((cpc_readl(card->hw.scabase + DTX_REG(CDAL,ch)) !=
1973 TX_BD_ADDR(ch,chan->tx_first_bd)) &&
1974 (cpc_readb(&ptdescr->status) & DST_OSB)) {
1975 dev->dev->stats.tx_packets++;
1976 dev->dev->stats.tx_bytes += cpc_readw(&ptdescr->len);
1977 cpc_writeb(&ptdescr->status, DST_OSB);
1978 cpc_writew(&ptdescr->len, 0);
1979 chan->nfree_tx_bd++;
1980 chan->tx_first_bd = (chan->tx_first_bd + 1) & (N_DMA_TX_BUF - 1);
1981 ptdescr = (card->hw.rambase + TX_BD_ADDR(ch,chan->tx_first_bd));
1982 }
1983
1984#ifdef CONFIG_PC300_MLPPP
1985 if (chan->conf.proto == PC300_PROTO_MLPPP) {
1986 cpc_tty_trigger_poll(dev);
1987 } else {
1988#endif
1989 /* Tell the upper layer we are ready to transmit more packets */
1990 netif_wake_queue(dev->dev);
1991#ifdef CONFIG_PC300_MLPPP
1992 }
1993#endif
1994}
1995
1996static void sca_intr(pc300_t * card)
1997{
1998 void __iomem *scabase = card->hw.scabase;
1999 volatile u32 status;
2000 int ch;
2001 int intr_count = 0;
2002 unsigned char dsr_rx;
2003
2004 while ((status = cpc_readl(scabase + ISR0)) != 0) {
2005 for (ch = 0; ch < card->hw.nchan; ch++) {
2006 pc300ch_t *chan = &card->chan[ch];
2007 pc300dev_t *d = &chan->d;
2008 struct net_device *dev = d->dev;
2009
2010 spin_lock(&card->card_lock);
2011
2012 /**** Reception ****/
2013 if (status & IR0_DRX((IR0_DMIA | IR0_DMIB), ch)) {
2014 u8 drx_stat = cpc_readb(scabase + DSR_RX(ch));
2015
2016 /* Clear RX interrupts */
2017 cpc_writeb(scabase + DSR_RX(ch), drx_stat | DSR_DWE);
2018
2019#ifdef PC300_DEBUG_INTR
2020 printk ("sca_intr: RX intr chan[%d] (st=0x%08lx, dsr=0x%02x)\n",
2021 ch, status, drx_stat);
2022#endif
2023 if (status & IR0_DRX(IR0_DMIA, ch)) {
2024 if (drx_stat & DSR_BOF) {
2025#ifdef CONFIG_PC300_MLPPP
2026 if (chan->conf.proto == PC300_PROTO_MLPPP) {
2027 /* verify if driver is TTY */
2028 if ((cpc_readb(scabase + DSR_RX(ch)) & DSR_DE)) {
2029 rx_dma_stop(card, ch);
2030 }
2031 cpc_tty_receive(d);
2032 rx_dma_start(card, ch);
2033 } else
2034#endif
2035 {
2036 if ((cpc_readb(scabase + DSR_RX(ch)) & DSR_DE)) {
2037 rx_dma_stop(card, ch);
2038 }
2039 cpc_net_rx(dev);
2040 /* Discard invalid frames */
2041 dev->stats.rx_errors++;
2042 dev->stats.rx_over_errors++;
2043 chan->rx_first_bd = 0;
2044 chan->rx_last_bd = N_DMA_RX_BUF - 1;
2045 rx_dma_start(card, ch);
2046 }
2047 }
2048 }
2049 if (status & IR0_DRX(IR0_DMIB, ch)) {
2050 if (drx_stat & DSR_EOM) {
2051 if (card->hw.type == PC300_TE) {
2052 cpc_writeb(card->hw.falcbase +
2053 card->hw.cpld_reg2,
2054 cpc_readb (card->hw.falcbase +
2055 card->hw.cpld_reg2) |
2056 (CPLD_REG2_FALC_LED1 << (2 * ch)));
2057 }
2058#ifdef CONFIG_PC300_MLPPP
2059 if (chan->conf.proto == PC300_PROTO_MLPPP) {
2060 /* verify if driver is TTY */
2061 cpc_tty_receive(d);
2062 } else {
2063 cpc_net_rx(dev);
2064 }
2065#else
2066 cpc_net_rx(dev);
2067#endif
2068 if (card->hw.type == PC300_TE) {
2069 cpc_writeb(card->hw.falcbase +
2070 card->hw.cpld_reg2,
2071 cpc_readb (card->hw.falcbase +
2072 card->hw.cpld_reg2) &
2073 ~ (CPLD_REG2_FALC_LED1 << (2 * ch)));
2074 }
2075 }
2076 }
2077 if (!(dsr_rx = cpc_readb(scabase + DSR_RX(ch)) & DSR_DE)) {
2078#ifdef PC300_DEBUG_INTR
2079 printk("%s: RX intr chan[%d] (st=0x%08lx, dsr=0x%02x, dsr2=0x%02x)\n",
2080 dev->name, ch, status, drx_stat, dsr_rx);
2081#endif
2082 cpc_writeb(scabase + DSR_RX(ch), (dsr_rx | DSR_DE) & 0xfe);
2083 }
2084 }
2085
2086 /**** Transmission ****/
2087 if (status & IR0_DTX((IR0_EFT | IR0_DMIA | IR0_DMIB), ch)) {
2088 u8 dtx_stat = cpc_readb(scabase + DSR_TX(ch));
2089
2090 /* Clear TX interrupts */
2091 cpc_writeb(scabase + DSR_TX(ch), dtx_stat | DSR_DWE);
2092
2093#ifdef PC300_DEBUG_INTR
2094 printk ("sca_intr: TX intr chan[%d] (st=0x%08lx, dsr=0x%02x)\n",
2095 ch, status, dtx_stat);
2096#endif
2097 if (status & IR0_DTX(IR0_EFT, ch)) {
2098 if (dtx_stat & DSR_UDRF) {
2099 if (cpc_readb (scabase + M_REG(TBN, ch)) != 0) {
2100 cpc_writeb(scabase + M_REG(CMD,ch), CMD_TX_BUF_CLR);
2101 }
2102 if (card->hw.type == PC300_TE) {
2103 cpc_writeb(card->hw.falcbase + card->hw.cpld_reg2,
2104 cpc_readb (card->hw.falcbase +
2105 card->hw.cpld_reg2) &
2106 ~ (CPLD_REG2_FALC_LED1 << (2 * ch)));
2107 }
2108 dev->stats.tx_errors++;
2109 dev->stats.tx_fifo_errors++;
2110 sca_tx_intr(d);
2111 }
2112 }
2113 if (status & IR0_DTX(IR0_DMIA, ch)) {
2114 if (dtx_stat & DSR_BOF) {
2115 }
2116 }
2117 if (status & IR0_DTX(IR0_DMIB, ch)) {
2118 if (dtx_stat & DSR_EOM) {
2119 if (card->hw.type == PC300_TE) {
2120 cpc_writeb(card->hw.falcbase + card->hw.cpld_reg2,
2121 cpc_readb (card->hw.falcbase +
2122 card->hw.cpld_reg2) &
2123 ~ (CPLD_REG2_FALC_LED1 << (2 * ch)));
2124 }
2125 sca_tx_intr(d);
2126 }
2127 }
2128 }
2129
2130 /**** MSCI ****/
2131 if (status & IR0_M(IR0_RXINTA, ch)) {
2132 u8 st1 = cpc_readb(scabase + M_REG(ST1, ch));
2133
2134 /* Clear MSCI interrupts */
2135 cpc_writeb(scabase + M_REG(ST1, ch), st1);
2136
2137#ifdef PC300_DEBUG_INTR
2138 printk("sca_intr: MSCI intr chan[%d] (st=0x%08lx, st1=0x%02x)\n",
2139 ch, status, st1);
2140#endif
2141 if (st1 & ST1_CDCD) { /* DCD changed */
2142 if (cpc_readb(scabase + M_REG(ST3, ch)) & ST3_DCD) {
2143 printk ("%s: DCD is OFF. Going administrative down.\n",
2144 dev->name);
2145#ifdef CONFIG_PC300_MLPPP
2146 if (chan->conf.proto != PC300_PROTO_MLPPP) {
2147 netif_carrier_off(dev);
2148 }
2149#else
2150 netif_carrier_off(dev);
2151
2152#endif
2153 card->chan[ch].d.line_off++;
2154 } else { /* DCD = 1 */
2155 printk ("%s: DCD is ON. Going administrative up.\n",
2156 dev->name);
2157#ifdef CONFIG_PC300_MLPPP
2158 if (chan->conf.proto != PC300_PROTO_MLPPP)
2159 /* verify if driver is not TTY */
2160#endif
2161 netif_carrier_on(dev);
2162 card->chan[ch].d.line_on++;
2163 }
2164 }
2165 }
2166 spin_unlock(&card->card_lock);
2167 }
2168 if (++intr_count == 10)
2169 /* Too much work at this board. Force exit */
2170 break;
2171 }
2172}
2173
2174static void falc_t1_loop_detection(pc300_t *card, int ch, u8 frs1)
2175{
2176 pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
2177 falc_t *pfalc = (falc_t *) & chan->falc;
2178 void __iomem *falcbase = card->hw.falcbase;
2179
2180 if (((cpc_readb(falcbase + F_REG(LCR1, ch)) & LCR1_XPRBS) == 0) &&
2181 !pfalc->loop_gen) {
2182 if (frs1 & FRS1_LLBDD) {
2183 // A Line Loop Back Deactivation signal detected
2184 if (pfalc->loop_active) {
2185 falc_remote_loop(card, ch, 0);
2186 }
2187 } else {
2188 if ((frs1 & FRS1_LLBAD) &&
2189 ((cpc_readb(falcbase + F_REG(LCR1, ch)) & LCR1_EPRM) == 0)) {
2190 // A Line Loop Back Activation signal detected
2191 if (!pfalc->loop_active) {
2192 falc_remote_loop(card, ch, 1);
2193 }
2194 }
2195 }
2196 }
2197}
2198
2199static void falc_e1_loop_detection(pc300_t *card, int ch, u8 rsp)
2200{
2201 pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
2202 falc_t *pfalc = (falc_t *) & chan->falc;
2203 void __iomem *falcbase = card->hw.falcbase;
2204
2205 if (((cpc_readb(falcbase + F_REG(LCR1, ch)) & LCR1_XPRBS) == 0) &&
2206 !pfalc->loop_gen) {
2207 if (rsp & RSP_LLBDD) {
2208 // A Line Loop Back Deactivation signal detected
2209 if (pfalc->loop_active) {
2210 falc_remote_loop(card, ch, 0);
2211 }
2212 } else {
2213 if ((rsp & RSP_LLBAD) &&
2214 ((cpc_readb(falcbase + F_REG(LCR1, ch)) & LCR1_EPRM) == 0)) {
2215 // A Line Loop Back Activation signal detected
2216 if (!pfalc->loop_active) {
2217 falc_remote_loop(card, ch, 1);
2218 }
2219 }
2220 }
2221 }
2222}
2223
2224static void falc_t1_intr(pc300_t * card, int ch)
2225{
2226 pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
2227 falc_t *pfalc = (falc_t *) & chan->falc;
2228 void __iomem *falcbase = card->hw.falcbase;
2229 u8 isr0, isr3, gis;
2230 u8 dummy;
2231
2232 while ((gis = cpc_readb(falcbase + F_REG(GIS, ch))) != 0) {
2233 if (gis & GIS_ISR0) {
2234 isr0 = cpc_readb(falcbase + F_REG(FISR0, ch));
2235 if (isr0 & FISR0_PDEN) {
2236 /* Read the bit to clear the situation */
2237 if (cpc_readb(falcbase + F_REG(FRS1, ch)) &
2238 FRS1_PDEN) {
2239 pfalc->pden++;
2240 }
2241 }
2242 }
2243
2244 if (gis & GIS_ISR1) {
2245 dummy = cpc_readb(falcbase + F_REG(FISR1, ch));
2246 }
2247
2248 if (gis & GIS_ISR2) {
2249 dummy = cpc_readb(falcbase + F_REG(FISR2, ch));
2250 }
2251
2252 if (gis & GIS_ISR3) {
2253 isr3 = cpc_readb(falcbase + F_REG(FISR3, ch));
2254 if (isr3 & FISR3_SEC) {
2255 pfalc->sec++;
2256 falc_update_stats(card, ch);
2257 falc_check_status(card, ch,
2258 cpc_readb(falcbase + F_REG(FRS0, ch)));
2259 }
2260 if (isr3 & FISR3_ES) {
2261 pfalc->es++;
2262 }
2263 if (isr3 & FISR3_LLBSC) {
2264 falc_t1_loop_detection(card, ch,
2265 cpc_readb(falcbase + F_REG(FRS1, ch)));
2266 }
2267 }
2268 }
2269}
2270
2271static void falc_e1_intr(pc300_t * card, int ch)
2272{
2273 pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
2274 falc_t *pfalc = (falc_t *) & chan->falc;
2275 void __iomem *falcbase = card->hw.falcbase;
2276 u8 isr1, isr2, isr3, gis, rsp;
2277 u8 dummy;
2278
2279 while ((gis = cpc_readb(falcbase + F_REG(GIS, ch))) != 0) {
2280 rsp = cpc_readb(falcbase + F_REG(RSP, ch));
2281
2282 if (gis & GIS_ISR0) {
2283 dummy = cpc_readb(falcbase + F_REG(FISR0, ch));
2284 }
2285 if (gis & GIS_ISR1) {
2286 isr1 = cpc_readb(falcbase + F_REG(FISR1, ch));
2287 if (isr1 & FISR1_XMB) {
2288 if ((pfalc->xmb_cause & 2) &&
2289 pfalc->multiframe_mode) {
2290 if (cpc_readb (falcbase + F_REG(FRS0, ch)) &
2291 (FRS0_LOS | FRS0_AIS | FRS0_LFA)) {
2292 cpc_writeb(falcbase + F_REG(XSP, ch),
2293 cpc_readb(falcbase + F_REG(XSP, ch))
2294 & ~XSP_AXS);
2295 } else {
2296 cpc_writeb(falcbase + F_REG(XSP, ch),
2297 cpc_readb(falcbase + F_REG(XSP, ch))
2298 | XSP_AXS);
2299 }
2300 }
2301 pfalc->xmb_cause = 0;
2302 cpc_writeb(falcbase + F_REG(IMR1, ch),
2303 cpc_readb(falcbase + F_REG(IMR1, ch)) | IMR1_XMB);
2304 }
2305 if (isr1 & FISR1_LLBSC) {
2306 falc_e1_loop_detection(card, ch, rsp);
2307 }
2308 }
2309 if (gis & GIS_ISR2) {
2310 isr2 = cpc_readb(falcbase + F_REG(FISR2, ch));
2311 if (isr2 & FISR2_T400MS) {
2312 cpc_writeb(falcbase + F_REG(XSW, ch),
2313 cpc_readb(falcbase + F_REG(XSW, ch)) | XSW_XRA);
2314 }
2315 if (isr2 & FISR2_MFAR) {
2316 cpc_writeb(falcbase + F_REG(XSW, ch),
2317 cpc_readb(falcbase + F_REG(XSW, ch)) & ~XSW_XRA);
2318 }
2319 if (isr2 & (FISR2_FAR | FISR2_LFA | FISR2_AIS | FISR2_LOS)) {
2320 pfalc->xmb_cause |= 2;
2321 cpc_writeb(falcbase + F_REG(IMR1, ch),
2322 cpc_readb(falcbase + F_REG(IMR1, ch)) & ~IMR1_XMB);
2323 }
2324 }
2325 if (gis & GIS_ISR3) {
2326 isr3 = cpc_readb(falcbase + F_REG(FISR3, ch));
2327 if (isr3 & FISR3_SEC) {
2328 pfalc->sec++;
2329 falc_update_stats(card, ch);
2330 falc_check_status(card, ch,
2331 cpc_readb(falcbase + F_REG(FRS0, ch)));
2332 }
2333 if (isr3 & FISR3_ES) {
2334 pfalc->es++;
2335 }
2336 }
2337 }
2338}
2339
2340static void falc_intr(pc300_t * card)
2341{
2342 int ch;
2343
2344 for (ch = 0; ch < card->hw.nchan; ch++) {
2345 pc300ch_t *chan = &card->chan[ch];
2346 pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
2347
2348 if (conf->media == IF_IFACE_T1) {
2349 falc_t1_intr(card, ch);
2350 } else {
2351 falc_e1_intr(card, ch);
2352 }
2353 }
2354}
2355
2356static irqreturn_t cpc_intr(int irq, void *dev_id)
2357{
2358 pc300_t *card = dev_id;
2359 volatile u8 plx_status;
2360
2361 if (!card) {
2362#ifdef PC300_DEBUG_INTR
2363 printk("cpc_intr: spurious intr %d\n", irq);
2364#endif
2365 return IRQ_NONE; /* spurious intr */
2366 }
2367
2368 if (!card->hw.rambase) {
2369#ifdef PC300_DEBUG_INTR
2370 printk("cpc_intr: spurious intr2 %d\n", irq);
2371#endif
2372 return IRQ_NONE; /* spurious intr */
2373 }
2374
2375 switch (card->hw.type) {
2376 case PC300_RSV:
2377 case PC300_X21:
2378 sca_intr(card);
2379 break;
2380
2381 case PC300_TE:
2382 while ( (plx_status = (cpc_readb(card->hw.plxbase + card->hw.intctl_reg) &
2383 (PLX_9050_LINT1_STATUS | PLX_9050_LINT2_STATUS))) != 0) {
2384 if (plx_status & PLX_9050_LINT1_STATUS) { /* SCA Interrupt */
2385 sca_intr(card);
2386 }
2387 if (plx_status & PLX_9050_LINT2_STATUS) { /* FALC Interrupt */
2388 falc_intr(card);
2389 }
2390 }
2391 break;
2392 }
2393 return IRQ_HANDLED;
2394}
2395
2396static void cpc_sca_status(pc300_t * card, int ch)
2397{
2398 u8 ilar;
2399 void __iomem *scabase = card->hw.scabase;
2400 unsigned long flags;
2401
2402 tx_dma_buf_check(card, ch);
2403 rx_dma_buf_check(card, ch);
2404 ilar = cpc_readb(scabase + ILAR);
2405 printk ("ILAR=0x%02x, WCRL=0x%02x, PCR=0x%02x, BTCR=0x%02x, BOLR=0x%02x\n",
2406 ilar, cpc_readb(scabase + WCRL), cpc_readb(scabase + PCR),
2407 cpc_readb(scabase + BTCR), cpc_readb(scabase + BOLR));
2408 printk("TX_CDA=0x%08x, TX_EDA=0x%08x\n",
2409 cpc_readl(scabase + DTX_REG(CDAL, ch)),
2410 cpc_readl(scabase + DTX_REG(EDAL, ch)));
2411 printk("RX_CDA=0x%08x, RX_EDA=0x%08x, BFL=0x%04x\n",
2412 cpc_readl(scabase + DRX_REG(CDAL, ch)),
2413 cpc_readl(scabase + DRX_REG(EDAL, ch)),
2414 cpc_readw(scabase + DRX_REG(BFLL, ch)));
2415 printk("DMER=0x%02x, DSR_TX=0x%02x, DSR_RX=0x%02x\n",
2416 cpc_readb(scabase + DMER), cpc_readb(scabase + DSR_TX(ch)),
2417 cpc_readb(scabase + DSR_RX(ch)));
2418 printk("DMR_TX=0x%02x, DMR_RX=0x%02x, DIR_TX=0x%02x, DIR_RX=0x%02x\n",
2419 cpc_readb(scabase + DMR_TX(ch)), cpc_readb(scabase + DMR_RX(ch)),
2420 cpc_readb(scabase + DIR_TX(ch)),
2421 cpc_readb(scabase + DIR_RX(ch)));
2422 printk("DCR_TX=0x%02x, DCR_RX=0x%02x, FCT_TX=0x%02x, FCT_RX=0x%02x\n",
2423 cpc_readb(scabase + DCR_TX(ch)), cpc_readb(scabase + DCR_RX(ch)),
2424 cpc_readb(scabase + FCT_TX(ch)),
2425 cpc_readb(scabase + FCT_RX(ch)));
2426 printk("MD0=0x%02x, MD1=0x%02x, MD2=0x%02x, MD3=0x%02x, IDL=0x%02x\n",
2427 cpc_readb(scabase + M_REG(MD0, ch)),
2428 cpc_readb(scabase + M_REG(MD1, ch)),
2429 cpc_readb(scabase + M_REG(MD2, ch)),
2430 cpc_readb(scabase + M_REG(MD3, ch)),
2431 cpc_readb(scabase + M_REG(IDL, ch)));
2432 printk("CMD=0x%02x, SA0=0x%02x, SA1=0x%02x, TFN=0x%02x, CTL=0x%02x\n",
2433 cpc_readb(scabase + M_REG(CMD, ch)),
2434 cpc_readb(scabase + M_REG(SA0, ch)),
2435 cpc_readb(scabase + M_REG(SA1, ch)),
2436 cpc_readb(scabase + M_REG(TFN, ch)),
2437 cpc_readb(scabase + M_REG(CTL, ch)));
2438 printk("ST0=0x%02x, ST1=0x%02x, ST2=0x%02x, ST3=0x%02x, ST4=0x%02x\n",
2439 cpc_readb(scabase + M_REG(ST0, ch)),
2440 cpc_readb(scabase + M_REG(ST1, ch)),
2441 cpc_readb(scabase + M_REG(ST2, ch)),
2442 cpc_readb(scabase + M_REG(ST3, ch)),
2443 cpc_readb(scabase + M_REG(ST4, ch)));
2444 printk ("CST0=0x%02x, CST1=0x%02x, CST2=0x%02x, CST3=0x%02x, FST=0x%02x\n",
2445 cpc_readb(scabase + M_REG(CST0, ch)),
2446 cpc_readb(scabase + M_REG(CST1, ch)),
2447 cpc_readb(scabase + M_REG(CST2, ch)),
2448 cpc_readb(scabase + M_REG(CST3, ch)),
2449 cpc_readb(scabase + M_REG(FST, ch)));
2450 printk("TRC0=0x%02x, TRC1=0x%02x, RRC=0x%02x, TBN=0x%02x, RBN=0x%02x\n",
2451 cpc_readb(scabase + M_REG(TRC0, ch)),
2452 cpc_readb(scabase + M_REG(TRC1, ch)),
2453 cpc_readb(scabase + M_REG(RRC, ch)),
2454 cpc_readb(scabase + M_REG(TBN, ch)),
2455 cpc_readb(scabase + M_REG(RBN, ch)));
2456 printk("TFS=0x%02x, TNR0=0x%02x, TNR1=0x%02x, RNR=0x%02x\n",
2457 cpc_readb(scabase + M_REG(TFS, ch)),
2458 cpc_readb(scabase + M_REG(TNR0, ch)),
2459 cpc_readb(scabase + M_REG(TNR1, ch)),
2460 cpc_readb(scabase + M_REG(RNR, ch)));
2461 printk("TCR=0x%02x, RCR=0x%02x, TNR1=0x%02x, RNR=0x%02x\n",
2462 cpc_readb(scabase + M_REG(TCR, ch)),
2463 cpc_readb(scabase + M_REG(RCR, ch)),
2464 cpc_readb(scabase + M_REG(TNR1, ch)),
2465 cpc_readb(scabase + M_REG(RNR, ch)));
2466 printk("TXS=0x%02x, RXS=0x%02x, EXS=0x%02x, TMCT=0x%02x, TMCR=0x%02x\n",
2467 cpc_readb(scabase + M_REG(TXS, ch)),
2468 cpc_readb(scabase + M_REG(RXS, ch)),
2469 cpc_readb(scabase + M_REG(EXS, ch)),
2470 cpc_readb(scabase + M_REG(TMCT, ch)),
2471 cpc_readb(scabase + M_REG(TMCR, ch)));
2472 printk("IE0=0x%02x, IE1=0x%02x, IE2=0x%02x, IE4=0x%02x, FIE=0x%02x\n",
2473 cpc_readb(scabase + M_REG(IE0, ch)),
2474 cpc_readb(scabase + M_REG(IE1, ch)),
2475 cpc_readb(scabase + M_REG(IE2, ch)),
2476 cpc_readb(scabase + M_REG(IE4, ch)),
2477 cpc_readb(scabase + M_REG(FIE, ch)));
2478 printk("IER0=0x%08x\n", cpc_readl(scabase + IER0));
2479
2480 if (ilar != 0) {
2481 CPC_LOCK(card, flags);
2482 cpc_writeb(scabase + ILAR, ilar);
2483 cpc_writeb(scabase + DMER, 0x80);
2484 CPC_UNLOCK(card, flags);
2485 }
2486}
2487
2488static void cpc_falc_status(pc300_t * card, int ch)
2489{
2490 pc300ch_t *chan = &card->chan[ch];
2491 falc_t *pfalc = (falc_t *) & chan->falc;
2492 unsigned long flags;
2493
2494 CPC_LOCK(card, flags);
2495 printk("CH%d: %s %s %d channels\n",
2496 ch, (pfalc->sync ? "SYNC" : ""), (pfalc->active ? "ACTIVE" : ""),
2497 pfalc->num_channels);
2498
2499 printk(" pden=%d, los=%d, losr=%d, lfa=%d, farec=%d\n",
2500 pfalc->pden, pfalc->los, pfalc->losr, pfalc->lfa, pfalc->farec);
2501 printk(" lmfa=%d, ais=%d, sec=%d, es=%d, rai=%d\n",
2502 pfalc->lmfa, pfalc->ais, pfalc->sec, pfalc->es, pfalc->rai);
2503 printk(" bec=%d, fec=%d, cvc=%d, cec=%d, ebc=%d\n",
2504 pfalc->bec, pfalc->fec, pfalc->cvc, pfalc->cec, pfalc->ebc);
2505
2506 printk("\n");
2507 printk(" STATUS: %s %s %s %s %s %s\n",
2508 (pfalc->red_alarm ? "RED" : ""),
2509 (pfalc->blue_alarm ? "BLU" : ""),
2510 (pfalc->yellow_alarm ? "YEL" : ""),
2511 (pfalc->loss_fa ? "LFA" : ""),
2512 (pfalc->loss_mfa ? "LMF" : ""), (pfalc->prbs ? "PRB" : ""));
2513 CPC_UNLOCK(card, flags);
2514}
2515
2516static int cpc_change_mtu(struct net_device *dev, int new_mtu)
2517{
2518 if ((new_mtu < 128) || (new_mtu > PC300_DEF_MTU))
2519 return -EINVAL;
2520 dev->mtu = new_mtu;
2521 return 0;
2522}
2523
2524static int cpc_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2525{
2526 pc300dev_t *d = (pc300dev_t *) dev_to_hdlc(dev)->priv;
2527 pc300ch_t *chan = (pc300ch_t *) d->chan;
2528 pc300_t *card = (pc300_t *) chan->card;
2529 pc300conf_t conf_aux;
2530 pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
2531 int ch = chan->channel;
2532 void __user *arg = ifr->ifr_data;
2533 struct if_settings *settings = &ifr->ifr_settings;
2534 void __iomem *scabase = card->hw.scabase;
2535
2536 if (!capable(CAP_NET_ADMIN))
2537 return -EPERM;
2538
2539 switch (cmd) {
2540 case SIOCGPC300CONF:
2541#ifdef CONFIG_PC300_MLPPP
2542 if (conf->proto != PC300_PROTO_MLPPP) {
2543 conf->proto = /* FIXME hdlc->proto.id */ 0;
2544 }
2545#else
2546 conf->proto = /* FIXME hdlc->proto.id */ 0;
2547#endif
2548 memcpy(&conf_aux.conf, conf, sizeof(pc300chconf_t));
2549 memcpy(&conf_aux.hw, &card->hw, sizeof(pc300hw_t));
2550 if (!arg ||
2551 copy_to_user(arg, &conf_aux, sizeof(pc300conf_t)))
2552 return -EINVAL;
2553 return 0;
2554 case SIOCSPC300CONF:
2555 if (!capable(CAP_NET_ADMIN))
2556 return -EPERM;
2557 if (!arg ||
2558 copy_from_user(&conf_aux.conf, arg, sizeof(pc300chconf_t)))
2559 return -EINVAL;
2560 if (card->hw.cpld_id < 0x02 &&
2561 conf_aux.conf.fr_mode == PC300_FR_UNFRAMED) {
2562 /* CPLD_ID < 0x02 doesn't support Unframed E1 */
2563 return -EINVAL;
2564 }
2565#ifdef CONFIG_PC300_MLPPP
2566 if (conf_aux.conf.proto == PC300_PROTO_MLPPP) {
2567 if (conf->proto != PC300_PROTO_MLPPP) {
2568 memcpy(conf, &conf_aux.conf, sizeof(pc300chconf_t));
2569 cpc_tty_init(d); /* init TTY driver */
2570 }
2571 } else {
2572 if (conf_aux.conf.proto == 0xffff) {
2573 if (conf->proto == PC300_PROTO_MLPPP){
2574 /* ifdown interface */
2575 cpc_close(dev);
2576 }
2577 } else {
2578 memcpy(conf, &conf_aux.conf, sizeof(pc300chconf_t));
2579 /* FIXME hdlc->proto.id = conf->proto; */
2580 }
2581 }
2582#else
2583 memcpy(conf, &conf_aux.conf, sizeof(pc300chconf_t));
2584 /* FIXME hdlc->proto.id = conf->proto; */
2585#endif
2586 return 0;
2587 case SIOCGPC300STATUS:
2588 cpc_sca_status(card, ch);
2589 return 0;
2590 case SIOCGPC300FALCSTATUS:
2591 cpc_falc_status(card, ch);
2592 return 0;
2593
2594 case SIOCGPC300UTILSTATS:
2595 {
2596 if (!arg) { /* clear statistics */
2597 memset(&dev->stats, 0, sizeof(dev->stats));
2598 if (card->hw.type == PC300_TE) {
2599 memset(&chan->falc, 0, sizeof(falc_t));
2600 }
2601 } else {
2602 pc300stats_t pc300stats;
2603
2604 memset(&pc300stats, 0, sizeof(pc300stats_t));
2605 pc300stats.hw_type = card->hw.type;
2606 pc300stats.line_on = card->chan[ch].d.line_on;
2607 pc300stats.line_off = card->chan[ch].d.line_off;
2608 memcpy(&pc300stats.gen_stats, &dev->stats,
2609 sizeof(dev->stats));
2610 if (card->hw.type == PC300_TE)
2611 memcpy(&pc300stats.te_stats,&chan->falc,sizeof(falc_t));
2612 if (copy_to_user(arg, &pc300stats, sizeof(pc300stats_t)))
2613 return -EFAULT;
2614 }
2615 return 0;
2616 }
2617
2618 case SIOCGPC300UTILSTATUS:
2619 {
2620 struct pc300status pc300status;
2621
2622 pc300status.hw_type = card->hw.type;
2623 if (card->hw.type == PC300_TE) {
2624 pc300status.te_status.sync = chan->falc.sync;
2625 pc300status.te_status.red_alarm = chan->falc.red_alarm;
2626 pc300status.te_status.blue_alarm = chan->falc.blue_alarm;
2627 pc300status.te_status.loss_fa = chan->falc.loss_fa;
2628 pc300status.te_status.yellow_alarm =chan->falc.yellow_alarm;
2629 pc300status.te_status.loss_mfa = chan->falc.loss_mfa;
2630 pc300status.te_status.prbs = chan->falc.prbs;
2631 } else {
2632 pc300status.gen_status.dcd =
2633 !(cpc_readb (scabase + M_REG(ST3, ch)) & ST3_DCD);
2634 pc300status.gen_status.cts =
2635 !(cpc_readb (scabase + M_REG(ST3, ch)) & ST3_CTS);
2636 pc300status.gen_status.rts =
2637 !(cpc_readb (scabase + M_REG(CTL, ch)) & CTL_RTS);
2638 pc300status.gen_status.dtr =
2639 !(cpc_readb (scabase + M_REG(CTL, ch)) & CTL_DTR);
2640 /* There is no DSR in HD64572 */
2641 }
2642 if (!arg ||
2643 copy_to_user(arg, &pc300status, sizeof(pc300status_t)))
2644 return -EINVAL;
2645 return 0;
2646 }
2647
2648 case SIOCSPC300TRACE:
2649 /* Sets/resets a trace_flag for the respective device */
2650 if (!arg || copy_from_user(&d->trace_on, arg,sizeof(unsigned char)))
2651 return -EINVAL;
2652 return 0;
2653
2654 case SIOCSPC300LOOPBACK:
2655 {
2656 struct pc300loopback pc300loop;
2657
2658 /* TE boards only */
2659 if (card->hw.type != PC300_TE)
2660 return -EINVAL;
2661
2662 if (!arg ||
2663 copy_from_user(&pc300loop, arg, sizeof(pc300loopback_t)))
2664 return -EINVAL;
2665 switch (pc300loop.loop_type) {
2666 case PC300LOCLOOP: /* Turn the local loop on/off */
2667 falc_local_loop(card, ch, pc300loop.loop_on);
2668 return 0;
2669
2670 case PC300REMLOOP: /* Turn the remote loop on/off */
2671 falc_remote_loop(card, ch, pc300loop.loop_on);
2672 return 0;
2673
2674 case PC300PAYLOADLOOP: /* Turn the payload loop on/off */
2675 falc_payload_loop(card, ch, pc300loop.loop_on);
2676 return 0;
2677
2678 case PC300GENLOOPUP: /* Generate loop UP */
2679 if (pc300loop.loop_on) {
2680 falc_generate_loop_up_code (card, ch);
2681 } else {
2682 turn_off_xlu(card, ch);
2683 }
2684 return 0;
2685
2686 case PC300GENLOOPDOWN: /* Generate loop DOWN */
2687 if (pc300loop.loop_on) {
2688 falc_generate_loop_down_code (card, ch);
2689 } else {
2690 turn_off_xld(card, ch);
2691 }
2692 return 0;
2693
2694 default:
2695 return -EINVAL;
2696 }
2697 }
2698
2699 case SIOCSPC300PATTERNTEST:
2700 /* Turn the pattern test on/off and show the errors counter */
2701 {
2702 struct pc300patterntst pc300patrntst;
2703
2704 /* TE boards only */
2705 if (card->hw.type != PC300_TE)
2706 return -EINVAL;
2707
2708 if (card->hw.cpld_id < 0x02) {
2709 /* CPLD_ID < 0x02 doesn't support pattern test */
2710 return -EINVAL;
2711 }
2712
2713 if (!arg ||
2714 copy_from_user(&pc300patrntst,arg,sizeof(pc300patterntst_t)))
2715 return -EINVAL;
2716 if (pc300patrntst.patrntst_on == 2) {
2717 if (chan->falc.prbs == 0) {
2718 falc_pattern_test(card, ch, 1);
2719 }
2720 pc300patrntst.num_errors =
2721 falc_pattern_test_error(card, ch);
2722 if (copy_to_user(arg, &pc300patrntst,
2723 sizeof(pc300patterntst_t)))
2724 return -EINVAL;
2725 } else {
2726 falc_pattern_test(card, ch, pc300patrntst.patrntst_on);
2727 }
2728 return 0;
2729 }
2730
2731 case SIOCWANDEV:
2732 switch (ifr->ifr_settings.type) {
2733 case IF_GET_IFACE:
2734 {
2735 const size_t size = sizeof(sync_serial_settings);
2736 ifr->ifr_settings.type = conf->media;
2737 if (ifr->ifr_settings.size < size) {
2738 /* data size wanted */
2739 ifr->ifr_settings.size = size;
2740 return -ENOBUFS;
2741 }
2742
2743 if (copy_to_user(settings->ifs_ifsu.sync,
2744 &conf->phys_settings, size)) {
2745 return -EFAULT;
2746 }
2747 return 0;
2748 }
2749
2750 case IF_IFACE_V35:
2751 case IF_IFACE_V24:
2752 case IF_IFACE_X21:
2753 {
2754 const size_t size = sizeof(sync_serial_settings);
2755
2756 if (!capable(CAP_NET_ADMIN)) {
2757 return -EPERM;
2758 }
2759 /* incorrect data len? */
2760 if (ifr->ifr_settings.size != size) {
2761 return -ENOBUFS;
2762 }
2763
2764 if (copy_from_user(&conf->phys_settings,
2765 settings->ifs_ifsu.sync, size)) {
2766 return -EFAULT;
2767 }
2768
2769 if (conf->phys_settings.loopback) {
2770 cpc_writeb(card->hw.scabase + M_REG(MD2, ch),
2771 cpc_readb(card->hw.scabase + M_REG(MD2, ch)) |
2772 MD2_LOOP_MIR);
2773 }
2774 conf->media = ifr->ifr_settings.type;
2775 return 0;
2776 }
2777
2778 case IF_IFACE_T1:
2779 case IF_IFACE_E1:
2780 {
2781 const size_t te_size = sizeof(te1_settings);
2782 const size_t size = sizeof(sync_serial_settings);
2783
2784 if (!capable(CAP_NET_ADMIN)) {
2785 return -EPERM;
2786 }
2787
2788 /* incorrect data len? */
2789 if (ifr->ifr_settings.size != te_size) {
2790 return -ENOBUFS;
2791 }
2792
2793 if (copy_from_user(&conf->phys_settings,
2794 settings->ifs_ifsu.te1, size)) {
2795 return -EFAULT;
2796 }/* Ignoring HDLC slot_map for a while */
2797
2798 if (conf->phys_settings.loopback) {
2799 cpc_writeb(card->hw.scabase + M_REG(MD2, ch),
2800 cpc_readb(card->hw.scabase + M_REG(MD2, ch)) |
2801 MD2_LOOP_MIR);
2802 }
2803 conf->media = ifr->ifr_settings.type;
2804 return 0;
2805 }
2806 default:
2807 return hdlc_ioctl(dev, ifr, cmd);
2808 }
2809
2810 default:
2811 return hdlc_ioctl(dev, ifr, cmd);
2812 }
2813}
2814
2815static int clock_rate_calc(u32 rate, u32 clock, int *br_io)
2816{
2817 int br, tc;
2818 int br_pwr, error;
2819
2820 *br_io = 0;
2821
2822 if (rate == 0)
2823 return 0;
2824
2825 for (br = 0, br_pwr = 1; br <= 9; br++, br_pwr <<= 1) {
2826 if ((tc = clock / br_pwr / rate) <= 0xff) {
2827 *br_io = br;
2828 break;
2829 }
2830 }
2831
2832 if (tc <= 0xff) {
2833 error = ((rate - (clock / br_pwr / rate)) / rate) * 1000;
2834 /* Errors bigger than +/- 1% won't be tolerated */
2835 if (error < -10 || error > 10)
2836 return -1;
2837 else
2838 return tc;
2839 } else {
2840 return -1;
2841 }
2842}
2843
2844static int ch_config(pc300dev_t * d)
2845{
2846 pc300ch_t *chan = (pc300ch_t *) d->chan;
2847 pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
2848 pc300_t *card = (pc300_t *) chan->card;
2849 void __iomem *scabase = card->hw.scabase;
2850 void __iomem *plxbase = card->hw.plxbase;
2851 int ch = chan->channel;
2852 u32 clkrate = chan->conf.phys_settings.clock_rate;
2853 u32 clktype = chan->conf.phys_settings.clock_type;
2854 u16 encoding = chan->conf.proto_settings.encoding;
2855 u16 parity = chan->conf.proto_settings.parity;
2856 u8 md0, md2;
2857
2858 /* Reset the channel */
2859 cpc_writeb(scabase + M_REG(CMD, ch), CMD_CH_RST);
2860
2861 /* Configure the SCA registers */
2862 switch (parity) {
2863 case PARITY_NONE:
2864 md0 = MD0_BIT_SYNC;
2865 break;
2866 case PARITY_CRC16_PR0:
2867 md0 = MD0_CRC16_0|MD0_CRCC0|MD0_BIT_SYNC;
2868 break;
2869 case PARITY_CRC16_PR1:
2870 md0 = MD0_CRC16_1|MD0_CRCC0|MD0_BIT_SYNC;
2871 break;
2872 case PARITY_CRC32_PR1_CCITT:
2873 md0 = MD0_CRC32|MD0_CRCC0|MD0_BIT_SYNC;
2874 break;
2875 case PARITY_CRC16_PR1_CCITT:
2876 default:
2877 md0 = MD0_CRC_CCITT|MD0_CRCC0|MD0_BIT_SYNC;
2878 break;
2879 }
2880 switch (encoding) {
2881 case ENCODING_NRZI:
2882 md2 = MD2_F_DUPLEX|MD2_ADPLL_X8|MD2_NRZI;
2883 break;
2884 case ENCODING_FM_MARK: /* FM1 */
2885 md2 = MD2_F_DUPLEX|MD2_ADPLL_X8|MD2_FM|MD2_FM1;
2886 break;
2887 case ENCODING_FM_SPACE: /* FM0 */
2888 md2 = MD2_F_DUPLEX|MD2_ADPLL_X8|MD2_FM|MD2_FM0;
2889 break;
2890 case ENCODING_MANCHESTER: /* It's not working... */
2891 md2 = MD2_F_DUPLEX|MD2_ADPLL_X8|MD2_FM|MD2_MANCH;
2892 break;
2893 case ENCODING_NRZ:
2894 default:
2895 md2 = MD2_F_DUPLEX|MD2_ADPLL_X8|MD2_NRZ;
2896 break;
2897 }
2898 cpc_writeb(scabase + M_REG(MD0, ch), md0);
2899 cpc_writeb(scabase + M_REG(MD1, ch), 0);
2900 cpc_writeb(scabase + M_REG(MD2, ch), md2);
2901 cpc_writeb(scabase + M_REG(IDL, ch), 0x7e);
2902 cpc_writeb(scabase + M_REG(CTL, ch), CTL_URSKP | CTL_IDLC);
2903
2904 /* Configure HW media */
2905 switch (card->hw.type) {
2906 case PC300_RSV:
2907 if (conf->media == IF_IFACE_V35) {
2908 cpc_writel((plxbase + card->hw.gpioc_reg),
2909 cpc_readl(plxbase + card->hw.gpioc_reg) | PC300_CHMEDIA_MASK(ch));
2910 } else {
2911 cpc_writel((plxbase + card->hw.gpioc_reg),
2912 cpc_readl(plxbase + card->hw.gpioc_reg) & ~PC300_CHMEDIA_MASK(ch));
2913 }
2914 break;
2915
2916 case PC300_X21:
2917 break;
2918
2919 case PC300_TE:
2920 te_config(card, ch);
2921 break;
2922 }
2923
2924 switch (card->hw.type) {
2925 case PC300_RSV:
2926 case PC300_X21:
2927 if (clktype == CLOCK_INT || clktype == CLOCK_TXINT) {
2928 int tmc, br;
2929
2930 /* Calculate the clkrate parameters */
2931 tmc = clock_rate_calc(clkrate, card->hw.clock, &br);
2932 if (tmc < 0)
2933 return -EIO;
2934 cpc_writeb(scabase + M_REG(TMCT, ch), tmc);
2935 cpc_writeb(scabase + M_REG(TXS, ch),
2936 (TXS_DTRXC | TXS_IBRG | br));
2937 if (clktype == CLOCK_INT) {
2938 cpc_writeb(scabase + M_REG(TMCR, ch), tmc);
2939 cpc_writeb(scabase + M_REG(RXS, ch),
2940 (RXS_IBRG | br));
2941 } else {
2942 cpc_writeb(scabase + M_REG(TMCR, ch), 1);
2943 cpc_writeb(scabase + M_REG(RXS, ch), 0);
2944 }
2945 if (card->hw.type == PC300_X21) {
2946 cpc_writeb(scabase + M_REG(GPO, ch), 1);
2947 cpc_writeb(scabase + M_REG(EXS, ch), EXS_TES1 | EXS_RES1);
2948 } else {
2949 cpc_writeb(scabase + M_REG(EXS, ch), EXS_TES1);
2950 }
2951 } else {
2952 cpc_writeb(scabase + M_REG(TMCT, ch), 1);
2953 if (clktype == CLOCK_EXT) {
2954 cpc_writeb(scabase + M_REG(TXS, ch),
2955 TXS_DTRXC);
2956 } else {
2957 cpc_writeb(scabase + M_REG(TXS, ch),
2958 TXS_DTRXC|TXS_RCLK);
2959 }
2960 cpc_writeb(scabase + M_REG(TMCR, ch), 1);
2961 cpc_writeb(scabase + M_REG(RXS, ch), 0);
2962 if (card->hw.type == PC300_X21) {
2963 cpc_writeb(scabase + M_REG(GPO, ch), 0);
2964 cpc_writeb(scabase + M_REG(EXS, ch), EXS_TES1 | EXS_RES1);
2965 } else {
2966 cpc_writeb(scabase + M_REG(EXS, ch), EXS_TES1);
2967 }
2968 }
2969 break;
2970
2971 case PC300_TE:
2972 /* SCA always receives clock from the FALC chip */
2973 cpc_writeb(scabase + M_REG(TMCT, ch), 1);
2974 cpc_writeb(scabase + M_REG(TXS, ch), 0);
2975 cpc_writeb(scabase + M_REG(TMCR, ch), 1);
2976 cpc_writeb(scabase + M_REG(RXS, ch), 0);
2977 cpc_writeb(scabase + M_REG(EXS, ch), 0);
2978 break;
2979 }
2980
2981 /* Enable Interrupts */
2982 cpc_writel(scabase + IER0,
2983 cpc_readl(scabase + IER0) |
2984 IR0_M(IR0_RXINTA, ch) |
2985 IR0_DRX(IR0_EFT | IR0_DMIA | IR0_DMIB, ch) |
2986 IR0_DTX(IR0_EFT | IR0_DMIA | IR0_DMIB, ch));
2987 cpc_writeb(scabase + M_REG(IE0, ch),
2988 cpc_readl(scabase + M_REG(IE0, ch)) | IE0_RXINTA);
2989 cpc_writeb(scabase + M_REG(IE1, ch),
2990 cpc_readl(scabase + M_REG(IE1, ch)) | IE1_CDCD);
2991
2992 return 0;
2993}
2994
2995static int rx_config(pc300dev_t * d)
2996{
2997 pc300ch_t *chan = (pc300ch_t *) d->chan;
2998 pc300_t *card = (pc300_t *) chan->card;
2999 void __iomem *scabase = card->hw.scabase;
3000 int ch = chan->channel;
3001
3002 cpc_writeb(scabase + DSR_RX(ch), 0);
3003
3004 /* General RX settings */
3005 cpc_writeb(scabase + M_REG(RRC, ch), 0);
3006 cpc_writeb(scabase + M_REG(RNR, ch), 16);
3007
3008 /* Enable reception */
3009 cpc_writeb(scabase + M_REG(CMD, ch), CMD_RX_CRC_INIT);
3010 cpc_writeb(scabase + M_REG(CMD, ch), CMD_RX_ENA);
3011
3012 /* Initialize DMA stuff */
3013 chan->rx_first_bd = 0;
3014 chan->rx_last_bd = N_DMA_RX_BUF - 1;
3015 rx_dma_buf_init(card, ch);
3016 cpc_writeb(scabase + DCR_RX(ch), DCR_FCT_CLR);
3017 cpc_writeb(scabase + DMR_RX(ch), (DMR_TMOD | DMR_NF));
3018 cpc_writeb(scabase + DIR_RX(ch), (DIR_EOM | DIR_BOF));
3019
3020 /* Start DMA */
3021 rx_dma_start(card, ch);
3022
3023 return 0;
3024}
3025
3026static int tx_config(pc300dev_t * d)
3027{
3028 pc300ch_t *chan = (pc300ch_t *) d->chan;
3029 pc300_t *card = (pc300_t *) chan->card;
3030 void __iomem *scabase = card->hw.scabase;
3031 int ch = chan->channel;
3032
3033 cpc_writeb(scabase + DSR_TX(ch), 0);
3034
3035 /* General TX settings */
3036 cpc_writeb(scabase + M_REG(TRC0, ch), 0);
3037 cpc_writeb(scabase + M_REG(TFS, ch), 32);
3038 cpc_writeb(scabase + M_REG(TNR0, ch), 20);
3039 cpc_writeb(scabase + M_REG(TNR1, ch), 48);
3040 cpc_writeb(scabase + M_REG(TCR, ch), 8);
3041
3042 /* Enable transmission */
3043 cpc_writeb(scabase + M_REG(CMD, ch), CMD_TX_CRC_INIT);
3044
3045 /* Initialize DMA stuff */
3046 chan->tx_first_bd = 0;
3047 chan->tx_next_bd = 0;
3048 tx_dma_buf_init(card, ch);
3049 cpc_writeb(scabase + DCR_TX(ch), DCR_FCT_CLR);
3050 cpc_writeb(scabase + DMR_TX(ch), (DMR_TMOD | DMR_NF));
3051 cpc_writeb(scabase + DIR_TX(ch), (DIR_EOM | DIR_BOF | DIR_UDRF));
3052 cpc_writel(scabase + DTX_REG(CDAL, ch), TX_BD_ADDR(ch, chan->tx_first_bd));
3053 cpc_writel(scabase + DTX_REG(EDAL, ch), TX_BD_ADDR(ch, chan->tx_next_bd));
3054
3055 return 0;
3056}
3057
3058static int cpc_attach(struct net_device *dev, unsigned short encoding,
3059 unsigned short parity)
3060{
3061 pc300dev_t *d = (pc300dev_t *)dev_to_hdlc(dev)->priv;
3062 pc300ch_t *chan = (pc300ch_t *)d->chan;
3063 pc300_t *card = (pc300_t *)chan->card;
3064 pc300chconf_t *conf = (pc300chconf_t *)&chan->conf;
3065
3066 if (card->hw.type == PC300_TE) {
3067 if (encoding != ENCODING_NRZ && encoding != ENCODING_NRZI) {
3068 return -EINVAL;
3069 }
3070 } else {
3071 if (encoding != ENCODING_NRZ && encoding != ENCODING_NRZI &&
3072 encoding != ENCODING_FM_MARK && encoding != ENCODING_FM_SPACE) {
3073 /* Driver doesn't support ENCODING_MANCHESTER yet */
3074 return -EINVAL;
3075 }
3076 }
3077
3078 if (parity != PARITY_NONE && parity != PARITY_CRC16_PR0 &&
3079 parity != PARITY_CRC16_PR1 && parity != PARITY_CRC32_PR1_CCITT &&
3080 parity != PARITY_CRC16_PR1_CCITT) {
3081 return -EINVAL;
3082 }
3083
3084 conf->proto_settings.encoding = encoding;
3085 conf->proto_settings.parity = parity;
3086 return 0;
3087}
3088
3089static int cpc_opench(pc300dev_t * d)
3090{
3091 pc300ch_t *chan = (pc300ch_t *) d->chan;
3092 pc300_t *card = (pc300_t *) chan->card;
3093 int ch = chan->channel, rc;
3094 void __iomem *scabase = card->hw.scabase;
3095
3096 rc = ch_config(d);
3097 if (rc)
3098 return rc;
3099
3100 rx_config(d);
3101
3102 tx_config(d);
3103
3104 /* Assert RTS and DTR */
3105 cpc_writeb(scabase + M_REG(CTL, ch),
3106 cpc_readb(scabase + M_REG(CTL, ch)) & ~(CTL_RTS | CTL_DTR));
3107
3108 return 0;
3109}
3110
3111static void cpc_closech(pc300dev_t * d)
3112{
3113 pc300ch_t *chan = (pc300ch_t *) d->chan;
3114 pc300_t *card = (pc300_t *) chan->card;
3115 falc_t *pfalc = (falc_t *) & chan->falc;
3116 int ch = chan->channel;
3117
3118 cpc_writeb(card->hw.scabase + M_REG(CMD, ch), CMD_CH_RST);
3119 rx_dma_stop(card, ch);
3120 tx_dma_stop(card, ch);
3121
3122 if (card->hw.type == PC300_TE) {
3123 memset(pfalc, 0, sizeof(falc_t));
3124 cpc_writeb(card->hw.falcbase + card->hw.cpld_reg2,
3125 cpc_readb(card->hw.falcbase + card->hw.cpld_reg2) &
3126 ~((CPLD_REG2_FALC_TX_CLK | CPLD_REG2_FALC_RX_CLK |
3127 CPLD_REG2_FALC_LED2) << (2 * ch)));
3128 /* Reset the FALC chip */
3129 cpc_writeb(card->hw.falcbase + card->hw.cpld_reg1,
3130 cpc_readb(card->hw.falcbase + card->hw.cpld_reg1) |
3131 (CPLD_REG1_FALC_RESET << (2 * ch)));
3132 udelay(10000);
3133 cpc_writeb(card->hw.falcbase + card->hw.cpld_reg1,
3134 cpc_readb(card->hw.falcbase + card->hw.cpld_reg1) &
3135 ~(CPLD_REG1_FALC_RESET << (2 * ch)));
3136 }
3137}
3138
3139int cpc_open(struct net_device *dev)
3140{
3141 pc300dev_t *d = (pc300dev_t *) dev_to_hdlc(dev)->priv;
3142 struct ifreq ifr;
3143 int result;
3144
3145#ifdef PC300_DEBUG_OTHER
3146 printk("pc300: cpc_open");
3147#endif
3148
3149 result = hdlc_open(dev);
3150
3151 if (result)
3152 return result;
3153
3154 sprintf(ifr.ifr_name, "%s", dev->name);
3155 result = cpc_opench(d);
3156 if (result)
3157 goto err_out;
3158
3159 netif_start_queue(dev);
3160 return 0;
3161
3162err_out:
3163 hdlc_close(dev);
3164 return result;
3165}
3166
3167static int cpc_close(struct net_device *dev)
3168{
3169 pc300dev_t *d = (pc300dev_t *) dev_to_hdlc(dev)->priv;
3170 pc300ch_t *chan = (pc300ch_t *) d->chan;
3171 pc300_t *card = (pc300_t *) chan->card;
3172 unsigned long flags;
3173
3174#ifdef PC300_DEBUG_OTHER
3175 printk("pc300: cpc_close");
3176#endif
3177
3178 netif_stop_queue(dev);
3179
3180 CPC_LOCK(card, flags);
3181 cpc_closech(d);
3182 CPC_UNLOCK(card, flags);
3183
3184 hdlc_close(dev);
3185
3186#ifdef CONFIG_PC300_MLPPP
3187 if (chan->conf.proto == PC300_PROTO_MLPPP) {
3188 cpc_tty_unregister_service(d);
3189 chan->conf.proto = 0xffff;
3190 }
3191#endif
3192
3193 return 0;
3194}
3195
3196static u32 detect_ram(pc300_t * card)
3197{
3198 u32 i;
3199 u8 data;
3200 void __iomem *rambase = card->hw.rambase;
3201
3202 card->hw.ramsize = PC300_RAMSIZE;
3203 /* Let's find out how much RAM is present on this board */
3204 for (i = 0; i < card->hw.ramsize; i++) {
3205 data = (u8)(i & 0xff);
3206 cpc_writeb(rambase + i, data);
3207 if (cpc_readb(rambase + i) != data) {
3208 break;
3209 }
3210 }
3211 return i;
3212}
3213
3214static void plx_init(pc300_t * card)
3215{
3216 struct RUNTIME_9050 __iomem *plx_ctl = card->hw.plxbase;
3217
3218 /* Reset PLX */
3219 cpc_writel(&plx_ctl->init_ctrl,
3220 cpc_readl(&plx_ctl->init_ctrl) | 0x40000000);
3221 udelay(10000L);
3222 cpc_writel(&plx_ctl->init_ctrl,
3223 cpc_readl(&plx_ctl->init_ctrl) & ~0x40000000);
3224
3225 /* Reload Config. Registers from EEPROM */
3226 cpc_writel(&plx_ctl->init_ctrl,
3227 cpc_readl(&plx_ctl->init_ctrl) | 0x20000000);
3228 udelay(10000L);
3229 cpc_writel(&plx_ctl->init_ctrl,
3230 cpc_readl(&plx_ctl->init_ctrl) & ~0x20000000);
3231
3232}
3233
3234static void show_version(void)
3235{
3236 char *rcsvers, *rcsdate, *tmp;
3237
3238 rcsvers = strchr(rcsid, ' ');
3239 rcsvers++;
3240 tmp = strchr(rcsvers, ' ');
3241 *tmp++ = '\0';
3242 rcsdate = strchr(tmp, ' ');
3243 rcsdate++;
3244 tmp = strrchr(rcsdate, ' ');
3245 *tmp = '\0';
3246 pr_info("Cyclades-PC300 driver %s %s\n", rcsvers, rcsdate);
3247} /* show_version */
3248
3249static const struct net_device_ops cpc_netdev_ops = {
3250 .ndo_open = cpc_open,
3251 .ndo_stop = cpc_close,
3252 .ndo_tx_timeout = cpc_tx_timeout,
3253 .ndo_set_mac_address = NULL,
3254 .ndo_change_mtu = cpc_change_mtu,
3255 .ndo_do_ioctl = cpc_ioctl,
3256 .ndo_validate_addr = eth_validate_addr,
3257};
3258
3259static void cpc_init_card(pc300_t * card)
3260{
3261 int i, devcount = 0;
3262 static int board_nbr = 1;
3263
3264 /* Enable interrupts on the PCI bridge */
3265 plx_init(card);
3266 cpc_writew(card->hw.plxbase + card->hw.intctl_reg,
3267 cpc_readw(card->hw.plxbase + card->hw.intctl_reg) | 0x0040);
3268
3269#ifdef USE_PCI_CLOCK
3270 /* Set board clock to PCI clock */
3271 cpc_writel(card->hw.plxbase + card->hw.gpioc_reg,
3272 cpc_readl(card->hw.plxbase + card->hw.gpioc_reg) | 0x00000004UL);
3273 card->hw.clock = PC300_PCI_CLOCK;
3274#else
3275 /* Set board clock to internal oscillator clock */
3276 cpc_writel(card->hw.plxbase + card->hw.gpioc_reg,
3277 cpc_readl(card->hw.plxbase + card->hw.gpioc_reg) & ~0x00000004UL);
3278 card->hw.clock = PC300_OSC_CLOCK;
3279#endif
3280
3281 /* Detect actual on-board RAM size */
3282 card->hw.ramsize = detect_ram(card);
3283
3284 /* Set Global SCA-II registers */
3285 cpc_writeb(card->hw.scabase + PCR, PCR_PR2);
3286 cpc_writeb(card->hw.scabase + BTCR, 0x10);
3287 cpc_writeb(card->hw.scabase + WCRL, 0);
3288 cpc_writeb(card->hw.scabase + DMER, 0x80);
3289
3290 if (card->hw.type == PC300_TE) {
3291 u8 reg1;
3292
3293 /* Check CPLD version */
3294 reg1 = cpc_readb(card->hw.falcbase + CPLD_REG1);
3295 cpc_writeb(card->hw.falcbase + CPLD_REG1, (reg1 + 0x5a));
3296 if (cpc_readb(card->hw.falcbase + CPLD_REG1) == reg1) {
3297 /* New CPLD */
3298 card->hw.cpld_id = cpc_readb(card->hw.falcbase + CPLD_ID_REG);
3299 card->hw.cpld_reg1 = CPLD_V2_REG1;
3300 card->hw.cpld_reg2 = CPLD_V2_REG2;
3301 } else {
3302 /* old CPLD */
3303 card->hw.cpld_id = 0;
3304 card->hw.cpld_reg1 = CPLD_REG1;
3305 card->hw.cpld_reg2 = CPLD_REG2;
3306 cpc_writeb(card->hw.falcbase + CPLD_REG1, reg1);
3307 }
3308
3309 /* Enable the board's global clock */
3310 cpc_writeb(card->hw.falcbase + card->hw.cpld_reg1,
3311 cpc_readb(card->hw.falcbase + card->hw.cpld_reg1) |
3312 CPLD_REG1_GLOBAL_CLK);
3313
3314 }
3315
3316 for (i = 0; i < card->hw.nchan; i++) {
3317 pc300ch_t *chan = &card->chan[i];
3318 pc300dev_t *d = &chan->d;
3319 hdlc_device *hdlc;
3320 struct net_device *dev;
3321
3322 chan->card = card;
3323 chan->channel = i;
3324 chan->conf.phys_settings.clock_rate = 0;
3325 chan->conf.phys_settings.clock_type = CLOCK_EXT;
3326 chan->conf.proto_settings.encoding = ENCODING_NRZ;
3327 chan->conf.proto_settings.parity = PARITY_CRC16_PR1_CCITT;
3328 switch (card->hw.type) {
3329 case PC300_TE:
3330 chan->conf.media = IF_IFACE_T1;
3331 chan->conf.lcode = PC300_LC_B8ZS;
3332 chan->conf.fr_mode = PC300_FR_ESF;
3333 chan->conf.lbo = PC300_LBO_0_DB;
3334 chan->conf.rx_sens = PC300_RX_SENS_SH;
3335 chan->conf.tslot_bitmap = 0xffffffffUL;
3336 break;
3337
3338 case PC300_X21:
3339 chan->conf.media = IF_IFACE_X21;
3340 break;
3341
3342 case PC300_RSV:
3343 default:
3344 chan->conf.media = IF_IFACE_V35;
3345 break;
3346 }
3347 chan->conf.proto = IF_PROTO_PPP;
3348 chan->tx_first_bd = 0;
3349 chan->tx_next_bd = 0;
3350 chan->rx_first_bd = 0;
3351 chan->rx_last_bd = N_DMA_RX_BUF - 1;
3352 chan->nfree_tx_bd = N_DMA_TX_BUF;
3353
3354 d->chan = chan;
3355 d->trace_on = 0;
3356 d->line_on = 0;
3357 d->line_off = 0;
3358
3359 dev = alloc_hdlcdev(d);
3360 if (dev == NULL)
3361 continue;
3362
3363 hdlc = dev_to_hdlc(dev);
3364 hdlc->xmit = cpc_queue_xmit;
3365 hdlc->attach = cpc_attach;
3366 d->dev = dev;
3367 dev->mem_start = card->hw.ramphys;
3368 dev->mem_end = card->hw.ramphys + card->hw.ramsize - 1;
3369 dev->irq = card->hw.irq;
3370 dev->tx_queue_len = PC300_TX_QUEUE_LEN;
3371 dev->mtu = PC300_DEF_MTU;
3372
3373 dev->netdev_ops = &cpc_netdev_ops;
3374 dev->watchdog_timeo = PC300_TX_TIMEOUT;
3375
3376 if (register_hdlc_device(dev) == 0) {
3377 printk("%s: Cyclades-PC300/", dev->name);
3378 switch (card->hw.type) {
3379 case PC300_TE:
3380 if (card->hw.bus == PC300_PMC) {
3381 printk("TE-M");
3382 } else {
3383 printk("TE ");
3384 }
3385 break;
3386
3387 case PC300_X21:
3388 printk("X21 ");
3389 break;
3390
3391 case PC300_RSV:
3392 default:
3393 printk("RSV ");
3394 break;
3395 }
3396 printk (" #%d, %dKB of RAM at 0x%08x, IRQ%d, channel %d.\n",
3397 board_nbr, card->hw.ramsize / 1024,
3398 card->hw.ramphys, card->hw.irq, i + 1);
3399 devcount++;
3400 } else {
3401 printk ("Dev%d on card(0x%08x): unable to allocate i/f name.\n",
3402 i + 1, card->hw.ramphys);
3403 free_netdev(dev);
3404 continue;
3405 }
3406 }
3407 spin_lock_init(&card->card_lock);
3408
3409 board_nbr++;
3410}
3411
3412static int __devinit
3413cpc_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
3414{
3415 int err, eeprom_outdated = 0;
3416 u16 device_id;
3417 pc300_t *card;
3418
3419 if ((err = pci_enable_device(pdev)) < 0)
3420 return err;
3421
3422 card = kzalloc(sizeof(pc300_t), GFP_KERNEL);
3423 if (card == NULL) {
3424 printk("PC300 found at RAM 0x%016llx, "
3425 "but could not allocate card structure.\n",
3426 (unsigned long long)pci_resource_start(pdev, 3));
3427 err = -ENOMEM;
3428 goto err_disable_dev;
3429 }
3430
3431 err = -ENODEV;
3432
3433 /* read PCI configuration area */
3434 device_id = ent->device;
3435 card->hw.irq = pdev->irq;
3436 card->hw.iophys = pci_resource_start(pdev, 1);
3437 card->hw.iosize = pci_resource_len(pdev, 1);
3438 card->hw.scaphys = pci_resource_start(pdev, 2);
3439 card->hw.scasize = pci_resource_len(pdev, 2);
3440 card->hw.ramphys = pci_resource_start(pdev, 3);
3441 card->hw.alloc_ramsize = pci_resource_len(pdev, 3);
3442 card->hw.falcphys = pci_resource_start(pdev, 4);
3443 card->hw.falcsize = pci_resource_len(pdev, 4);
3444 card->hw.plxphys = pci_resource_start(pdev, 5);
3445 card->hw.plxsize = pci_resource_len(pdev, 5);
3446
3447 switch (device_id) {
3448 case PCI_DEVICE_ID_PC300_RX_1:
3449 case PCI_DEVICE_ID_PC300_TE_1:
3450 case PCI_DEVICE_ID_PC300_TE_M_1:
3451 card->hw.nchan = 1;
3452 break;
3453
3454 case PCI_DEVICE_ID_PC300_RX_2:
3455 case PCI_DEVICE_ID_PC300_TE_2:
3456 case PCI_DEVICE_ID_PC300_TE_M_2:
3457 default:
3458 card->hw.nchan = PC300_MAXCHAN;
3459 break;
3460 }
3461#ifdef PC300_DEBUG_PCI
3462 printk("cpc (bus=0x0%x,pci_id=0x%x,", pdev->bus->number, pdev->devfn);
3463 printk("rev_id=%d) IRQ%d\n", pdev->revision, card->hw.irq);
3464 printk("cpc:found ramaddr=0x%08lx plxaddr=0x%08lx "
3465 "ctladdr=0x%08lx falcaddr=0x%08lx\n",
3466 card->hw.ramphys, card->hw.plxphys, card->hw.scaphys,
3467 card->hw.falcphys);
3468#endif
3469 /* Although we don't use this I/O region, we should
3470 * request it from the kernel anyway, to avoid problems
3471 * with other drivers accessing it. */
3472 if (!request_region(card->hw.iophys, card->hw.iosize, "PLX Registers")) {
3473 /* In case we can't allocate it, warn user */
3474 printk("WARNING: couldn't allocate I/O region for PC300 board "
3475 "at 0x%08x!\n", card->hw.ramphys);
3476 }
3477
3478 if (card->hw.plxphys) {
3479 pci_write_config_dword(pdev, PCI_BASE_ADDRESS_0, card->hw.plxphys);
3480 } else {
3481 eeprom_outdated = 1;
3482 card->hw.plxphys = pci_resource_start(pdev, 0);
3483 card->hw.plxsize = pci_resource_len(pdev, 0);
3484 }
3485
3486 if (!request_mem_region(card->hw.plxphys, card->hw.plxsize,
3487 "PLX Registers")) {
3488 printk("PC300 found at RAM 0x%08x, "
3489 "but could not allocate PLX mem region.\n",
3490 card->hw.ramphys);
3491 goto err_release_io;
3492 }
3493 if (!request_mem_region(card->hw.ramphys, card->hw.alloc_ramsize,
3494 "On-board RAM")) {
3495 printk("PC300 found at RAM 0x%08x, "
3496 "but could not allocate RAM mem region.\n",
3497 card->hw.ramphys);
3498 goto err_release_plx;
3499 }
3500 if (!request_mem_region(card->hw.scaphys, card->hw.scasize,
3501 "SCA-II Registers")) {
3502 printk("PC300 found at RAM 0x%08x, "
3503 "but could not allocate SCA mem region.\n",
3504 card->hw.ramphys);
3505 goto err_release_ram;
3506 }
3507
3508 card->hw.plxbase = ioremap(card->hw.plxphys, card->hw.plxsize);
3509 card->hw.rambase = ioremap(card->hw.ramphys, card->hw.alloc_ramsize);
3510 card->hw.scabase = ioremap(card->hw.scaphys, card->hw.scasize);
3511 switch (device_id) {
3512 case PCI_DEVICE_ID_PC300_TE_1:
3513 case PCI_DEVICE_ID_PC300_TE_2:
3514 case PCI_DEVICE_ID_PC300_TE_M_1:
3515 case PCI_DEVICE_ID_PC300_TE_M_2:
3516 request_mem_region(card->hw.falcphys, card->hw.falcsize,
3517 "FALC Registers");
3518 card->hw.falcbase = ioremap(card->hw.falcphys, card->hw.falcsize);
3519 break;
3520
3521 case PCI_DEVICE_ID_PC300_RX_1:
3522 case PCI_DEVICE_ID_PC300_RX_2:
3523 default:
3524 card->hw.falcbase = NULL;
3525 break;
3526 }
3527
3528#ifdef PC300_DEBUG_PCI
3529 printk("cpc: relocate ramaddr=0x%08lx plxaddr=0x%08lx "
3530 "ctladdr=0x%08lx falcaddr=0x%08lx\n",
3531 card->hw.rambase, card->hw.plxbase, card->hw.scabase,
3532 card->hw.falcbase);
3533#endif
3534
3535 /* Set PCI drv pointer to the card structure */
3536 pci_set_drvdata(pdev, card);
3537
3538 /* Set board type */
3539 switch (device_id) {
3540 case PCI_DEVICE_ID_PC300_TE_1:
3541 case PCI_DEVICE_ID_PC300_TE_2:
3542 case PCI_DEVICE_ID_PC300_TE_M_1:
3543 case PCI_DEVICE_ID_PC300_TE_M_2:
3544 card->hw.type = PC300_TE;
3545
3546 if ((device_id == PCI_DEVICE_ID_PC300_TE_M_1) ||
3547 (device_id == PCI_DEVICE_ID_PC300_TE_M_2)) {
3548 card->hw.bus = PC300_PMC;
3549 /* Set PLX register offsets */
3550 card->hw.gpioc_reg = 0x54;
3551 card->hw.intctl_reg = 0x4c;
3552 } else {
3553 card->hw.bus = PC300_PCI;
3554 /* Set PLX register offsets */
3555 card->hw.gpioc_reg = 0x50;
3556 card->hw.intctl_reg = 0x4c;
3557 }
3558 break;
3559
3560 case PCI_DEVICE_ID_PC300_RX_1:
3561 case PCI_DEVICE_ID_PC300_RX_2:
3562 default:
3563 card->hw.bus = PC300_PCI;
3564 /* Set PLX register offsets */
3565 card->hw.gpioc_reg = 0x50;
3566 card->hw.intctl_reg = 0x4c;
3567
3568 if ((cpc_readl(card->hw.plxbase + card->hw.gpioc_reg) & PC300_CTYPE_MASK)) {
3569 card->hw.type = PC300_X21;
3570 } else {
3571 card->hw.type = PC300_RSV;
3572 }
3573 break;
3574 }
3575
3576 /* Allocate IRQ */
3577 if (request_irq(card->hw.irq, cpc_intr, IRQF_SHARED, "Cyclades-PC300", card)) {
3578 printk ("PC300 found at RAM 0x%08x, but could not allocate IRQ%d.\n",
3579 card->hw.ramphys, card->hw.irq);
3580 goto err_io_unmap;
3581 }
3582
3583 cpc_init_card(card);
3584
3585 if (eeprom_outdated)
3586 printk("WARNING: PC300 with outdated EEPROM.\n");
3587 return 0;
3588
3589err_io_unmap:
3590 iounmap(card->hw.plxbase);
3591 iounmap(card->hw.scabase);
3592 iounmap(card->hw.rambase);
3593 if (card->hw.type == PC300_TE) {
3594 iounmap(card->hw.falcbase);
3595 release_mem_region(card->hw.falcphys, card->hw.falcsize);
3596 }
3597 release_mem_region(card->hw.scaphys, card->hw.scasize);
3598err_release_ram:
3599 release_mem_region(card->hw.ramphys, card->hw.alloc_ramsize);
3600err_release_plx:
3601 release_mem_region(card->hw.plxphys, card->hw.plxsize);
3602err_release_io:
3603 release_region(card->hw.iophys, card->hw.iosize);
3604 kfree(card);
3605err_disable_dev:
3606 pci_disable_device(pdev);
3607 return err;
3608}
3609
3610static void __devexit cpc_remove_one(struct pci_dev *pdev)
3611{
3612 pc300_t *card = pci_get_drvdata(pdev);
3613
3614 if (card->hw.rambase) {
3615 int i;
3616
3617 /* Disable interrupts on the PCI bridge */
3618 cpc_writew(card->hw.plxbase + card->hw.intctl_reg,
3619 cpc_readw(card->hw.plxbase + card->hw.intctl_reg) & ~(0x0040));
3620
3621 for (i = 0; i < card->hw.nchan; i++) {
3622 unregister_hdlc_device(card->chan[i].d.dev);
3623 }
3624 iounmap(card->hw.plxbase);
3625 iounmap(card->hw.scabase);
3626 iounmap(card->hw.rambase);
3627 release_mem_region(card->hw.plxphys, card->hw.plxsize);
3628 release_mem_region(card->hw.ramphys, card->hw.alloc_ramsize);
3629 release_mem_region(card->hw.scaphys, card->hw.scasize);
3630 release_region(card->hw.iophys, card->hw.iosize);
3631 if (card->hw.type == PC300_TE) {
3632 iounmap(card->hw.falcbase);
3633 release_mem_region(card->hw.falcphys, card->hw.falcsize);
3634 }
3635 for (i = 0; i < card->hw.nchan; i++)
3636 if (card->chan[i].d.dev)
3637 free_netdev(card->chan[i].d.dev);
3638 if (card->hw.irq)
3639 free_irq(card->hw.irq, card);
3640 kfree(card);
3641 pci_disable_device(pdev);
3642 }
3643}
3644
3645static struct pci_driver cpc_driver = {
3646 .name = "pc300",
3647 .id_table = cpc_pci_dev_id,
3648 .probe = cpc_init_one,
3649 .remove = __devexit_p(cpc_remove_one),
3650};
3651
3652static int __init cpc_init(void)
3653{
3654 show_version();
3655 return pci_register_driver(&cpc_driver);
3656}
3657
3658static void __exit cpc_cleanup_module(void)
3659{
3660 pci_unregister_driver(&cpc_driver);
3661}
3662
3663module_init(cpc_init);
3664module_exit(cpc_cleanup_module);
3665
3666MODULE_DESCRIPTION("Cyclades-PC300 cards driver");
3667MODULE_AUTHOR( "Author: Ivan Passos <ivan@cyclades.com>\r\n"
3668 "Maintainer: PC300 Maintainer <pc300@cyclades.com");
3669MODULE_LICENSE("GPL");
3670
diff --git a/drivers/net/wan/pc300_tty.c b/drivers/net/wan/pc300_tty.c
deleted file mode 100644
index 4709f422856..00000000000
--- a/drivers/net/wan/pc300_tty.c
+++ /dev/null
@@ -1,1079 +0,0 @@
1/*
2 * pc300_tty.c Cyclades-PC300(tm) TTY Driver.
3 *
4 * Author: Regina Kodato <reginak@cyclades.com>
5 *
6 * Copyright: (c) 1999-2002 Cyclades Corp.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * as published by the Free Software Foundation; either version
11 * 2 of the License, or (at your option) any later version.
12 *
13 * $Log: pc300_tty.c,v $
14 * Revision 3.7 2002/03/07 14:17:09 henrique
15 * License data fixed
16 *
17 * Revision 3.6 2001/12/10 12:29:42 regina
18 * Fix the MLPPP bug
19 *
20 * Revision 3.5 2001/10/31 11:20:05 regina
21 * automatic pppd starts
22 *
23 * Revision 3.4 2001/08/06 12:01:51 regina
24 * problem in DSR_DE bit
25 *
26 * Revision 3.3 2001/07/26 22:58:41 regina
27 * update EDA value
28 *
29 * Revision 3.2 2001/07/12 13:11:20 regina
30 * bug fix - DCD-OFF in pc300 tty driver
31 *
32 * DMA transmission bug fix
33 *
34 * Revision 3.1 2001/06/22 13:13:02 regina
35 * MLPPP implementation
36 *
37 */
38
39#include <linux/module.h>
40#include <linux/kernel.h>
41#include <linux/errno.h>
42#include <linux/string.h>
43#include <linux/init.h>
44#include <linux/netdevice.h>
45#include <linux/spinlock.h>
46#include <linux/slab.h>
47#include <linux/if.h>
48#include <linux/skbuff.h>
49/* TTY includes */
50#include <linux/tty.h>
51#include <linux/tty_flip.h>
52#include <linux/serial.h>
53
54#include <asm/io.h>
55#include <asm/uaccess.h>
56
57#include "pc300.h"
58
59/* defines and macros */
60/* TTY Global definitions */
61#define CPC_TTY_NPORTS 8 /* maximum number of the sync tty connections */
62#define CPC_TTY_MAJOR CYCLADES_MAJOR
63#define CPC_TTY_MINOR_START 240 /* minor of the first PC300 interface */
64
65#define CPC_TTY_MAX_MTU 2000
66
67/* tty interface state */
68#define CPC_TTY_ST_IDLE 0
69#define CPC_TTY_ST_INIT 1 /* configured with MLPPP and up */
70#define CPC_TTY_ST_OPEN 2 /* opened by application */
71
72#define CPC_TTY_LOCK(card,flags)\
73 do {\
74 spin_lock_irqsave(&card->card_lock, flags); \
75 } while (0)
76
77#define CPC_TTY_UNLOCK(card,flags) \
78 do {\
79 spin_unlock_irqrestore(&card->card_lock, flags); \
80 } while (0)
81
82//#define CPC_TTY_DBG(format,a...) printk(format,##a)
83#define CPC_TTY_DBG(format,a...)
84
85/* data structures */
86typedef struct _st_cpc_rx_buf {
87 struct _st_cpc_rx_buf *next;
88 int size;
89 unsigned char data[1];
90} st_cpc_rx_buf;
91
92struct st_cpc_rx_list {
93 st_cpc_rx_buf *first;
94 st_cpc_rx_buf *last;
95};
96
97typedef struct _st_cpc_tty_area {
98 int state; /* state of the TTY interface */
99 int num_open;
100 unsigned int tty_minor; /* minor this interface */
101 volatile struct st_cpc_rx_list buf_rx; /* ptr. to reception buffer */
102 unsigned char* buf_tx; /* ptr. to transmission buffer */
103 pc300dev_t* pc300dev; /* ptr. to info struct in PC300 driver */
104 unsigned char name[20]; /* interf. name + "-tty" */
105 struct tty_struct *tty;
106 struct work_struct tty_tx_work; /* tx work - tx interrupt */
107 struct work_struct tty_rx_work; /* rx work - rx interrupt */
108 } st_cpc_tty_area;
109
110/* TTY data structures */
111static struct tty_driver serial_drv;
112
113/* local variables */
114static st_cpc_tty_area cpc_tty_area[CPC_TTY_NPORTS];
115
116static int cpc_tty_cnt = 0; /* number of intrfaces configured with MLPPP */
117static int cpc_tty_unreg_flag = 0;
118
119/* TTY functions prototype */
120static int cpc_tty_open(struct tty_struct *tty, struct file *flip);
121static void cpc_tty_close(struct tty_struct *tty, struct file *flip);
122static int cpc_tty_write(struct tty_struct *tty, const unsigned char *buf, int count);
123static int cpc_tty_write_room(struct tty_struct *tty);
124static int cpc_tty_chars_in_buffer(struct tty_struct *tty);
125static void cpc_tty_flush_buffer(struct tty_struct *tty);
126static void cpc_tty_hangup(struct tty_struct *tty);
127static void cpc_tty_rx_work(struct work_struct *work);
128static void cpc_tty_tx_work(struct work_struct *work);
129static int cpc_tty_send_to_card(pc300dev_t *dev,void *buf, int len);
130static void cpc_tty_trace(pc300dev_t *dev, char* buf, int len, char rxtx);
131static void cpc_tty_signal_off(pc300dev_t *pc300dev, unsigned char);
132static void cpc_tty_signal_on(pc300dev_t *pc300dev, unsigned char);
133
134static int pc300_tiocmset(struct tty_struct *, unsigned int, unsigned int);
135static int pc300_tiocmget(struct tty_struct *);
136
137/* functions called by PC300 driver */
138void cpc_tty_init(pc300dev_t *dev);
139void cpc_tty_unregister_service(pc300dev_t *pc300dev);
140void cpc_tty_receive(pc300dev_t *pc300dev);
141void cpc_tty_trigger_poll(pc300dev_t *pc300dev);
142
143/*
144 * PC300 TTY clear "signal"
145 */
146static void cpc_tty_signal_off(pc300dev_t *pc300dev, unsigned char signal)
147{
148 pc300ch_t *pc300chan = (pc300ch_t *)pc300dev->chan;
149 pc300_t *card = (pc300_t *) pc300chan->card;
150 int ch = pc300chan->channel;
151 unsigned long flags;
152
153 CPC_TTY_DBG("%s-tty: Clear signal %x\n",
154 pc300dev->dev->name, signal);
155 CPC_TTY_LOCK(card, flags);
156 cpc_writeb(card->hw.scabase + M_REG(CTL,ch),
157 cpc_readb(card->hw.scabase+M_REG(CTL,ch))& signal);
158 CPC_TTY_UNLOCK(card,flags);
159}
160
161/*
162 * PC300 TTY set "signal" to ON
163 */
164static void cpc_tty_signal_on(pc300dev_t *pc300dev, unsigned char signal)
165{
166 pc300ch_t *pc300chan = (pc300ch_t *)pc300dev->chan;
167 pc300_t *card = (pc300_t *) pc300chan->card;
168 int ch = pc300chan->channel;
169 unsigned long flags;
170
171 CPC_TTY_DBG("%s-tty: Set signal %x\n",
172 pc300dev->dev->name, signal);
173 CPC_TTY_LOCK(card, flags);
174 cpc_writeb(card->hw.scabase + M_REG(CTL,ch),
175 cpc_readb(card->hw.scabase+M_REG(CTL,ch))& ~signal);
176 CPC_TTY_UNLOCK(card,flags);
177}
178
179
180static const struct tty_operations pc300_ops = {
181 .open = cpc_tty_open,
182 .close = cpc_tty_close,
183 .write = cpc_tty_write,
184 .write_room = cpc_tty_write_room,
185 .chars_in_buffer = cpc_tty_chars_in_buffer,
186 .tiocmset = pc300_tiocmset,
187 .tiocmget = pc300_tiocmget,
188 .flush_buffer = cpc_tty_flush_buffer,
189 .hangup = cpc_tty_hangup,
190};
191
192
193/*
194 * PC300 TTY initialization routine
195 *
196 * This routine is called by the PC300 driver during board configuration
197 * (ioctl=SIOCSP300CONF). At this point the adapter is completely
198 * initialized.
199 * o verify kernel version (only 2.4.x)
200 * o register TTY driver
201 * o init cpc_tty_area struct
202 */
203void cpc_tty_init(pc300dev_t *pc300dev)
204{
205 unsigned long port;
206 int aux;
207 st_cpc_tty_area * cpc_tty;
208
209 /* hdlcX - X=interface number */
210 port = pc300dev->dev->name[4] - '0';
211 if (port >= CPC_TTY_NPORTS) {
212 printk("%s-tty: invalid interface selected (0-%i): %li",
213 pc300dev->dev->name,
214 CPC_TTY_NPORTS-1,port);
215 return;
216 }
217
218 if (cpc_tty_cnt == 0) { /* first TTY connection -> register driver */
219 CPC_TTY_DBG("%s-tty: driver init, major:%i, minor range:%i=%i\n",
220 pc300dev->dev->name,
221 CPC_TTY_MAJOR, CPC_TTY_MINOR_START,
222 CPC_TTY_MINOR_START+CPC_TTY_NPORTS);
223 /* initialize tty driver struct */
224 memset(&serial_drv,0,sizeof(struct tty_driver));
225 serial_drv.magic = TTY_DRIVER_MAGIC;
226 serial_drv.owner = THIS_MODULE;
227 serial_drv.driver_name = "pc300_tty";
228 serial_drv.name = "ttyCP";
229 serial_drv.major = CPC_TTY_MAJOR;
230 serial_drv.minor_start = CPC_TTY_MINOR_START;
231 serial_drv.num = CPC_TTY_NPORTS;
232 serial_drv.type = TTY_DRIVER_TYPE_SERIAL;
233 serial_drv.subtype = SERIAL_TYPE_NORMAL;
234
235 serial_drv.init_termios = tty_std_termios;
236 serial_drv.init_termios.c_cflag = B9600|CS8|CREAD|HUPCL|CLOCAL;
237 serial_drv.flags = TTY_DRIVER_REAL_RAW;
238
239 /* interface routines from the upper tty layer to the tty driver */
240 tty_set_operations(&serial_drv, &pc300_ops);
241
242 /* register the TTY driver */
243 if (tty_register_driver(&serial_drv)) {
244 printk("%s-tty: Failed to register serial driver! ",
245 pc300dev->dev->name);
246 return;
247 }
248
249 memset((void *)cpc_tty_area, 0,
250 sizeof(st_cpc_tty_area) * CPC_TTY_NPORTS);
251 }
252
253 cpc_tty = &cpc_tty_area[port];
254
255 if (cpc_tty->state != CPC_TTY_ST_IDLE) {
256 CPC_TTY_DBG("%s-tty: TTY port %i, already in use.\n",
257 pc300dev->dev->name, port);
258 return;
259 }
260
261 cpc_tty_cnt++;
262 cpc_tty->state = CPC_TTY_ST_INIT;
263 cpc_tty->num_open= 0;
264 cpc_tty->tty_minor = port + CPC_TTY_MINOR_START;
265 cpc_tty->pc300dev = pc300dev;
266
267 INIT_WORK(&cpc_tty->tty_tx_work, cpc_tty_tx_work);
268 INIT_WORK(&cpc_tty->tty_rx_work, cpc_tty_rx_work);
269
270 cpc_tty->buf_rx.first = cpc_tty->buf_rx.last = NULL;
271
272 pc300dev->cpc_tty = (void *)cpc_tty;
273
274 aux = strlen(pc300dev->dev->name);
275 memcpy(cpc_tty->name, pc300dev->dev->name, aux);
276 memcpy(&cpc_tty->name[aux], "-tty", 5);
277
278 cpc_open(pc300dev->dev);
279 cpc_tty_signal_off(pc300dev, CTL_DTR);
280
281 CPC_TTY_DBG("%s: Initializing TTY Sync Driver, tty major#%d minor#%i\n",
282 cpc_tty->name,CPC_TTY_MAJOR,cpc_tty->tty_minor);
283 return;
284}
285
286/*
287 * PC300 TTY OPEN routine
288 *
289 * This routine is called by the tty driver to open the interface
290 * o verify minor
291 * o allocate buffer to Rx and Tx
292 */
293static int cpc_tty_open(struct tty_struct *tty, struct file *flip)
294{
295 int port ;
296 st_cpc_tty_area *cpc_tty;
297
298 if (!tty) {
299 return -ENODEV;
300 }
301
302 port = tty->index;
303
304 if ((port < 0) || (port >= CPC_TTY_NPORTS)){
305 CPC_TTY_DBG("pc300_tty: open invalid port %d\n", port);
306 return -ENODEV;
307 }
308
309 cpc_tty = &cpc_tty_area[port];
310
311 if (cpc_tty->state == CPC_TTY_ST_IDLE){
312 CPC_TTY_DBG("%s: open - invalid interface, port=%d\n",
313 cpc_tty->name, tty->index);
314 return -ENODEV;
315 }
316
317 if (cpc_tty->num_open == 0) { /* first open of this tty */
318 if (!cpc_tty_area[port].buf_tx){
319 cpc_tty_area[port].buf_tx = kmalloc(CPC_TTY_MAX_MTU,GFP_KERNEL);
320 if (!cpc_tty_area[port].buf_tx) {
321 CPC_TTY_DBG("%s: error in memory allocation\n",cpc_tty->name);
322 return -ENOMEM;
323 }
324 }
325
326 if (cpc_tty_area[port].buf_rx.first) {
327 unsigned char * aux;
328 while (cpc_tty_area[port].buf_rx.first) {
329 aux = (unsigned char *)cpc_tty_area[port].buf_rx.first;
330 cpc_tty_area[port].buf_rx.first = cpc_tty_area[port].buf_rx.first->next;
331 kfree(aux);
332 }
333 cpc_tty_area[port].buf_rx.first = NULL;
334 cpc_tty_area[port].buf_rx.last = NULL;
335 }
336
337 cpc_tty_area[port].state = CPC_TTY_ST_OPEN;
338 cpc_tty_area[port].tty = tty;
339 tty->driver_data = &cpc_tty_area[port];
340
341 cpc_tty_signal_on(cpc_tty->pc300dev, CTL_DTR);
342 }
343
344 cpc_tty->num_open++;
345
346 CPC_TTY_DBG("%s: opening TTY driver\n", cpc_tty->name);
347
348 /* avisar driver PC300 */
349 return 0;
350}
351
352/*
353 * PC300 TTY CLOSE routine
354 *
355 * This routine is called by the tty driver to close the interface
356 * o call close channel in PC300 driver (cpc_closech)
357 * o free Rx and Tx buffers
358 */
359
360static void cpc_tty_close(struct tty_struct *tty, struct file *flip)
361{
362 st_cpc_tty_area *cpc_tty;
363 unsigned long flags;
364 int res;
365
366 if (!tty || !tty->driver_data ) {
367 CPC_TTY_DBG("hdlx-tty: no TTY in close\n");
368 return;
369 }
370
371 cpc_tty = (st_cpc_tty_area *) tty->driver_data;
372
373 if ((cpc_tty->tty != tty)|| (cpc_tty->state != CPC_TTY_ST_OPEN)) {
374 CPC_TTY_DBG("%s: TTY is not opened\n",cpc_tty->name);
375 return;
376 }
377
378 if (!cpc_tty->num_open) {
379 CPC_TTY_DBG("%s: TTY is closed\n",cpc_tty->name);
380 return;
381 }
382
383 if (--cpc_tty->num_open > 0) {
384 CPC_TTY_DBG("%s: TTY closed\n",cpc_tty->name);
385 return;
386 }
387
388 cpc_tty_signal_off(cpc_tty->pc300dev, CTL_DTR);
389
390 CPC_TTY_LOCK(cpc_tty->pc300dev->chan->card, flags); /* lock irq */
391 cpc_tty->tty = NULL;
392 cpc_tty->state = CPC_TTY_ST_INIT;
393 CPC_TTY_UNLOCK(cpc_tty->pc300dev->chan->card, flags); /* unlock irq */
394
395 if (cpc_tty->buf_rx.first) {
396 unsigned char * aux;
397 while (cpc_tty->buf_rx.first) {
398 aux = (unsigned char *)cpc_tty->buf_rx.first;
399 cpc_tty->buf_rx.first = cpc_tty->buf_rx.first->next;
400 kfree(aux);
401 }
402 cpc_tty->buf_rx.first = NULL;
403 cpc_tty->buf_rx.last = NULL;
404 }
405
406 kfree(cpc_tty->buf_tx);
407 cpc_tty->buf_tx = NULL;
408
409 CPC_TTY_DBG("%s: TTY closed\n",cpc_tty->name);
410
411 if (!serial_drv.refcount && cpc_tty_unreg_flag) {
412 cpc_tty_unreg_flag = 0;
413 CPC_TTY_DBG("%s: unregister the tty driver\n", cpc_tty->name);
414 if ((res=tty_unregister_driver(&serial_drv))) {
415 CPC_TTY_DBG("%s: ERROR ->unregister the tty driver error=%d\n",
416 cpc_tty->name,res);
417 }
418 }
419 return;
420}
421
422/*
423 * PC300 TTY WRITE routine
424 *
425 * This routine is called by the tty driver to write a series of characters
426 * to the tty device. The characters may come from user or kernel space.
427 * o verify the DCD signal
428 * o send characters to board and start the transmission
429 */
430static int cpc_tty_write(struct tty_struct *tty, const unsigned char *buf, int count)
431{
432 st_cpc_tty_area *cpc_tty;
433 pc300ch_t *pc300chan;
434 pc300_t *card;
435 int ch;
436 unsigned long flags;
437 struct net_device_stats *stats;
438
439 if (!tty || !tty->driver_data ) {
440 CPC_TTY_DBG("hdlcX-tty: no TTY in write\n");
441 return -ENODEV;
442 }
443
444 cpc_tty = (st_cpc_tty_area *) tty->driver_data;
445
446 if ((cpc_tty->tty != tty) || (cpc_tty->state != CPC_TTY_ST_OPEN)) {
447 CPC_TTY_DBG("%s: TTY is not opened\n", cpc_tty->name);
448 return -ENODEV;
449 }
450
451 if (count > CPC_TTY_MAX_MTU) {
452 CPC_TTY_DBG("%s: count is invalid\n",cpc_tty->name);
453 return -EINVAL; /* frame too big */
454 }
455
456 CPC_TTY_DBG("%s: cpc_tty_write data len=%i\n",cpc_tty->name,count);
457
458 pc300chan = (pc300ch_t *)((pc300dev_t*)cpc_tty->pc300dev)->chan;
459 stats = &cpc_tty->pc300dev->dev->stats;
460 card = (pc300_t *) pc300chan->card;
461 ch = pc300chan->channel;
462
463 /* verify DCD signal*/
464 if (cpc_readb(card->hw.scabase + M_REG(ST3,ch)) & ST3_DCD) {
465 /* DCD is OFF */
466 CPC_TTY_DBG("%s : DCD is OFF\n", cpc_tty->name);
467 stats->tx_errors++;
468 stats->tx_carrier_errors++;
469 CPC_TTY_LOCK(card, flags);
470 cpc_writeb(card->hw.scabase + M_REG(CMD, ch), CMD_TX_BUF_CLR);
471
472 if (card->hw.type == PC300_TE) {
473 cpc_writeb(card->hw.falcbase + card->hw.cpld_reg2,
474 cpc_readb(card->hw.falcbase + card->hw.cpld_reg2) &
475 ~(CPLD_REG2_FALC_LED1 << (2 *ch)));
476 }
477
478 CPC_TTY_UNLOCK(card, flags);
479
480 return -EINVAL;
481 }
482
483 if (cpc_tty_send_to_card(cpc_tty->pc300dev, (void*)buf, count)) {
484 /* failed to send */
485 CPC_TTY_DBG("%s: trasmition error\n", cpc_tty->name);
486 return 0;
487 }
488 return count;
489}
490
491/*
492 * PC300 TTY Write Room routine
493 *
494 * This routine returns the numbers of characteres the tty driver will accept
495 * for queuing to be written.
496 * o return MTU
497 */
498static int cpc_tty_write_room(struct tty_struct *tty)
499{
500 st_cpc_tty_area *cpc_tty;
501
502 if (!tty || !tty->driver_data ) {
503 CPC_TTY_DBG("hdlcX-tty: no TTY to write room\n");
504 return -ENODEV;
505 }
506
507 cpc_tty = (st_cpc_tty_area *) tty->driver_data;
508
509 if ((cpc_tty->tty != tty) || (cpc_tty->state != CPC_TTY_ST_OPEN)) {
510 CPC_TTY_DBG("%s: TTY is not opened\n",cpc_tty->name);
511 return -ENODEV;
512 }
513
514 CPC_TTY_DBG("%s: write room\n",cpc_tty->name);
515
516 return CPC_TTY_MAX_MTU;
517}
518
519/*
520 * PC300 TTY chars in buffer routine
521 *
522 * This routine returns the chars number in the transmission buffer
523 * o returns 0
524 */
525static int cpc_tty_chars_in_buffer(struct tty_struct *tty)
526{
527 st_cpc_tty_area *cpc_tty;
528
529 if (!tty || !tty->driver_data ) {
530 CPC_TTY_DBG("hdlcX-tty: no TTY to chars in buffer\n");
531 return -ENODEV;
532 }
533
534 cpc_tty = (st_cpc_tty_area *) tty->driver_data;
535
536 if ((cpc_tty->tty != tty) || (cpc_tty->state != CPC_TTY_ST_OPEN)) {
537 CPC_TTY_DBG("%s: TTY is not opened\n",cpc_tty->name);
538 return -ENODEV;
539 }
540
541 return 0;
542}
543
544static int pc300_tiocmset(struct tty_struct *tty,
545 unsigned int set, unsigned int clear)
546{
547 st_cpc_tty_area *cpc_tty;
548
549 CPC_TTY_DBG("%s: set:%x clear:%x\n", __func__, set, clear);
550
551 if (!tty || !tty->driver_data ) {
552 CPC_TTY_DBG("hdlcX-tty: no TTY to chars in buffer\n");
553 return -ENODEV;
554 }
555
556 cpc_tty = (st_cpc_tty_area *) tty->driver_data;
557
558 if (set & TIOCM_RTS)
559 cpc_tty_signal_on(cpc_tty->pc300dev, CTL_RTS);
560 if (set & TIOCM_DTR)
561 cpc_tty_signal_on(cpc_tty->pc300dev, CTL_DTR);
562
563 if (clear & TIOCM_RTS)
564 cpc_tty_signal_off(cpc_tty->pc300dev, CTL_RTS);
565 if (clear & TIOCM_DTR)
566 cpc_tty_signal_off(cpc_tty->pc300dev, CTL_DTR);
567
568 return 0;
569}
570
571static int pc300_tiocmget(struct tty_struct *tty)
572{
573 unsigned int result;
574 unsigned char status;
575 unsigned long flags;
576 st_cpc_tty_area *cpc_tty = (st_cpc_tty_area *) tty->driver_data;
577 pc300dev_t *pc300dev = cpc_tty->pc300dev;
578 pc300ch_t *pc300chan = (pc300ch_t *)pc300dev->chan;
579 pc300_t *card = (pc300_t *) pc300chan->card;
580 int ch = pc300chan->channel;
581
582 cpc_tty = (st_cpc_tty_area *) tty->driver_data;
583
584 CPC_TTY_DBG("%s-tty: tiocmget\n",
585 ((struct net_device*)(pc300dev->hdlc))->name);
586
587 CPC_TTY_LOCK(card, flags);
588 status = cpc_readb(card->hw.scabase+M_REG(CTL,ch));
589 CPC_TTY_UNLOCK(card,flags);
590
591 result = ((status & CTL_DTR) ? TIOCM_DTR : 0) |
592 ((status & CTL_RTS) ? TIOCM_RTS : 0);
593
594 return result;
595}
596
597/*
598 * PC300 TTY Flush Buffer routine
599 *
600 * This routine resets the transmission buffer
601 */
602static void cpc_tty_flush_buffer(struct tty_struct *tty)
603{
604 st_cpc_tty_area *cpc_tty;
605
606 if (!tty || !tty->driver_data ) {
607 CPC_TTY_DBG("hdlcX-tty: no TTY to flush buffer\n");
608 return;
609 }
610
611 cpc_tty = (st_cpc_tty_area *) tty->driver_data;
612
613 if ((cpc_tty->tty != tty) || (cpc_tty->state != CPC_TTY_ST_OPEN)) {
614 CPC_TTY_DBG("%s: TTY is not opened\n",cpc_tty->name);
615 return;
616 }
617
618 CPC_TTY_DBG("%s: call wake_up_interruptible\n",cpc_tty->name);
619
620 tty_wakeup(tty);
621 return;
622}
623
624/*
625 * PC300 TTY Hangup routine
626 *
627 * This routine is called by the tty driver to hangup the interface
628 * o clear DTR signal
629 */
630
631static void cpc_tty_hangup(struct tty_struct *tty)
632{
633 st_cpc_tty_area *cpc_tty;
634 int res;
635
636 if (!tty || !tty->driver_data ) {
637 CPC_TTY_DBG("hdlcX-tty: no TTY to hangup\n");
638 return ;
639 }
640
641 cpc_tty = (st_cpc_tty_area *) tty->driver_data;
642
643 if ((cpc_tty->tty != tty) || (cpc_tty->state != CPC_TTY_ST_OPEN)) {
644 CPC_TTY_DBG("%s: TTY is not opened\n",cpc_tty->name);
645 return ;
646 }
647 if (!serial_drv.refcount && cpc_tty_unreg_flag) {
648 cpc_tty_unreg_flag = 0;
649 CPC_TTY_DBG("%s: unregister the tty driver\n", cpc_tty->name);
650 if ((res=tty_unregister_driver(&serial_drv))) {
651 CPC_TTY_DBG("%s: ERROR ->unregister the tty driver error=%d\n",
652 cpc_tty->name,res);
653 }
654 }
655 cpc_tty_signal_off(cpc_tty->pc300dev, CTL_DTR);
656}
657
658/*
659 * PC300 TTY RX work routine
660 * This routine treats RX work
661 * o verify read buffer
662 * o call the line disc. read
663 * o free memory
664 */
665static void cpc_tty_rx_work(struct work_struct *work)
666{
667 st_cpc_tty_area *cpc_tty;
668 unsigned long port;
669 int i, j;
670 volatile st_cpc_rx_buf *buf;
671 char flags=0,flg_rx=1;
672 struct tty_ldisc *ld;
673
674 if (cpc_tty_cnt == 0) return;
675
676 for (i=0; (i < 4) && flg_rx ; i++) {
677 flg_rx = 0;
678
679 cpc_tty = container_of(work, st_cpc_tty_area, tty_rx_work);
680 port = cpc_tty - cpc_tty_area;
681
682 for (j=0; j < CPC_TTY_NPORTS; j++) {
683 cpc_tty = &cpc_tty_area[port];
684
685 if ((buf=cpc_tty->buf_rx.first) != NULL) {
686 if (cpc_tty->tty) {
687 ld = tty_ldisc_ref(cpc_tty->tty);
688 if (ld) {
689 if (ld->ops->receive_buf) {
690 CPC_TTY_DBG("%s: call line disc. receive_buf\n",cpc_tty->name);
691 ld->ops->receive_buf(cpc_tty->tty, (char *)(buf->data), &flags, buf->size);
692 }
693 tty_ldisc_deref(ld);
694 }
695 }
696 cpc_tty->buf_rx.first = cpc_tty->buf_rx.first->next;
697 kfree((void *)buf);
698 buf = cpc_tty->buf_rx.first;
699 flg_rx = 1;
700 }
701 if (++port == CPC_TTY_NPORTS) port = 0;
702 }
703 }
704}
705
706/*
707 * PC300 TTY RX work routine
708 *
709 * This routine treats RX interrupt.
710 * o read all frames in card
711 * o verify the frame size
712 * o read the frame in rx buffer
713 */
714static void cpc_tty_rx_disc_frame(pc300ch_t *pc300chan)
715{
716 volatile pcsca_bd_t __iomem * ptdescr;
717 volatile unsigned char status;
718 pc300_t *card = (pc300_t *)pc300chan->card;
719 int ch = pc300chan->channel;
720
721 /* dma buf read */
722 ptdescr = (pcsca_bd_t __iomem *)(card->hw.rambase +
723 RX_BD_ADDR(ch, pc300chan->rx_first_bd));
724 while (pc300chan->rx_first_bd != pc300chan->rx_last_bd) {
725 status = cpc_readb(&ptdescr->status);
726 cpc_writeb(&ptdescr->status, 0);
727 cpc_writeb(&ptdescr->len, 0);
728 pc300chan->rx_first_bd = (pc300chan->rx_first_bd + 1) &
729 (N_DMA_RX_BUF - 1);
730 if (status & DST_EOM) {
731 break; /* end of message */
732 }
733 ptdescr = (pcsca_bd_t __iomem *)(card->hw.rambase + cpc_readl(&ptdescr->next));
734 }
735}
736
737void cpc_tty_receive(pc300dev_t *pc300dev)
738{
739 st_cpc_tty_area *cpc_tty;
740 pc300ch_t *pc300chan = (pc300ch_t *)pc300dev->chan;
741 pc300_t *card = (pc300_t *)pc300chan->card;
742 int ch = pc300chan->channel;
743 volatile pcsca_bd_t __iomem * ptdescr;
744 struct net_device_stats *stats = &pc300dev->dev->stats;
745 int rx_len, rx_aux;
746 volatile unsigned char status;
747 unsigned short first_bd = pc300chan->rx_first_bd;
748 st_cpc_rx_buf *new = NULL;
749 unsigned char dsr_rx;
750
751 if (pc300dev->cpc_tty == NULL) {
752 return;
753 }
754
755 dsr_rx = cpc_readb(card->hw.scabase + DSR_RX(ch));
756
757 cpc_tty = pc300dev->cpc_tty;
758
759 while (1) {
760 rx_len = 0;
761 ptdescr = (pcsca_bd_t __iomem *)(card->hw.rambase + RX_BD_ADDR(ch, first_bd));
762 while ((status = cpc_readb(&ptdescr->status)) & DST_OSB) {
763 rx_len += cpc_readw(&ptdescr->len);
764 first_bd = (first_bd + 1) & (N_DMA_RX_BUF - 1);
765 if (status & DST_EOM) {
766 break;
767 }
768 ptdescr = (pcsca_bd_t __iomem *)(card->hw.rambase+cpc_readl(&ptdescr->next));
769 }
770
771 if (!rx_len) {
772 if (dsr_rx & DSR_BOF) {
773 /* update EDA */
774 cpc_writel(card->hw.scabase + DRX_REG(EDAL, ch),
775 RX_BD_ADDR(ch, pc300chan->rx_last_bd));
776 }
777 kfree(new);
778 return;
779 }
780
781 if (rx_len > CPC_TTY_MAX_MTU) {
782 /* Free RX descriptors */
783 CPC_TTY_DBG("%s: frame size is invalid.\n",cpc_tty->name);
784 stats->rx_errors++;
785 stats->rx_frame_errors++;
786 cpc_tty_rx_disc_frame(pc300chan);
787 continue;
788 }
789
790 new = kmalloc(rx_len + sizeof(st_cpc_rx_buf), GFP_ATOMIC);
791 if (!new) {
792 cpc_tty_rx_disc_frame(pc300chan);
793 continue;
794 }
795
796 /* dma buf read */
797 ptdescr = (pcsca_bd_t __iomem *)(card->hw.rambase +
798 RX_BD_ADDR(ch, pc300chan->rx_first_bd));
799
800 rx_len = 0; /* counter frame size */
801
802 while ((status = cpc_readb(&ptdescr->status)) & DST_OSB) {
803 rx_aux = cpc_readw(&ptdescr->len);
804 if ((status & (DST_OVR | DST_CRC | DST_RBIT | DST_SHRT | DST_ABT))
805 || (rx_aux > BD_DEF_LEN)) {
806 CPC_TTY_DBG("%s: reception error\n", cpc_tty->name);
807 stats->rx_errors++;
808 if (status & DST_OVR) {
809 stats->rx_fifo_errors++;
810 }
811 if (status & DST_CRC) {
812 stats->rx_crc_errors++;
813 }
814 if ((status & (DST_RBIT | DST_SHRT | DST_ABT)) ||
815 (rx_aux > BD_DEF_LEN)) {
816 stats->rx_frame_errors++;
817 }
818 /* discard remainig descriptors used by the bad frame */
819 CPC_TTY_DBG("%s: reception error - discard descriptors",
820 cpc_tty->name);
821 cpc_tty_rx_disc_frame(pc300chan);
822 rx_len = 0;
823 kfree(new);
824 new = NULL;
825 break; /* read next frame - while(1) */
826 }
827
828 if (cpc_tty->state != CPC_TTY_ST_OPEN) {
829 /* Free RX descriptors */
830 cpc_tty_rx_disc_frame(pc300chan);
831 stats->rx_dropped++;
832 rx_len = 0;
833 kfree(new);
834 new = NULL;
835 break; /* read next frame - while(1) */
836 }
837
838 /* read the segment of the frame */
839 if (rx_aux != 0) {
840 memcpy_fromio((new->data + rx_len),
841 (void __iomem *)(card->hw.rambase +
842 cpc_readl(&ptdescr->ptbuf)), rx_aux);
843 rx_len += rx_aux;
844 }
845 cpc_writeb(&ptdescr->status,0);
846 cpc_writeb(&ptdescr->len, 0);
847 pc300chan->rx_first_bd = (pc300chan->rx_first_bd + 1) &
848 (N_DMA_RX_BUF -1);
849 if (status & DST_EOM)break;
850
851 ptdescr = (pcsca_bd_t __iomem *) (card->hw.rambase +
852 cpc_readl(&ptdescr->next));
853 }
854 /* update pointer */
855 pc300chan->rx_last_bd = (pc300chan->rx_first_bd - 1) &
856 (N_DMA_RX_BUF - 1) ;
857 if (!(dsr_rx & DSR_BOF)) {
858 /* update EDA */
859 cpc_writel(card->hw.scabase + DRX_REG(EDAL, ch),
860 RX_BD_ADDR(ch, pc300chan->rx_last_bd));
861 }
862 if (rx_len != 0) {
863 stats->rx_bytes += rx_len;
864
865 if (pc300dev->trace_on) {
866 cpc_tty_trace(pc300dev, new->data,rx_len, 'R');
867 }
868 new->size = rx_len;
869 new->next = NULL;
870 if (cpc_tty->buf_rx.first == NULL) {
871 cpc_tty->buf_rx.first = new;
872 cpc_tty->buf_rx.last = new;
873 } else {
874 cpc_tty->buf_rx.last->next = new;
875 cpc_tty->buf_rx.last = new;
876 }
877 schedule_work(&(cpc_tty->tty_rx_work));
878 stats->rx_packets++;
879 }
880 }
881}
882
883/*
884 * PC300 TTY TX work routine
885 *
886 * This routine treats TX interrupt.
887 * o if need call line discipline wakeup
888 * o call wake_up_interruptible
889 */
890static void cpc_tty_tx_work(struct work_struct *work)
891{
892 st_cpc_tty_area *cpc_tty =
893 container_of(work, st_cpc_tty_area, tty_tx_work);
894 struct tty_struct *tty;
895
896 CPC_TTY_DBG("%s: cpc_tty_tx_work init\n",cpc_tty->name);
897
898 if ((tty = cpc_tty->tty) == NULL) {
899 CPC_TTY_DBG("%s: the interface is not opened\n",cpc_tty->name);
900 return;
901 }
902 tty_wakeup(tty);
903}
904
905/*
906 * PC300 TTY send to card routine
907 *
908 * This routine send data to card.
909 * o clear descriptors
910 * o write data to DMA buffers
911 * o start the transmission
912 */
913static int cpc_tty_send_to_card(pc300dev_t *dev,void* buf, int len)
914{
915 pc300ch_t *chan = (pc300ch_t *)dev->chan;
916 pc300_t *card = (pc300_t *)chan->card;
917 int ch = chan->channel;
918 struct net_device_stats *stats = &dev->dev->stats;
919 unsigned long flags;
920 volatile pcsca_bd_t __iomem *ptdescr;
921 int i, nchar;
922 int tosend = len;
923 int nbuf = ((len - 1)/BD_DEF_LEN) + 1;
924 unsigned char *pdata=buf;
925
926 CPC_TTY_DBG("%s:cpc_tty_send_to_cars len=%i",
927 (st_cpc_tty_area *)dev->cpc_tty->name,len);
928
929 if (nbuf >= card->chan[ch].nfree_tx_bd) {
930 return 1;
931 }
932
933 /* write buffer to DMA buffers */
934 CPC_TTY_DBG("%s: call dma_buf_write\n",
935 (st_cpc_tty_area *)dev->cpc_tty->name);
936 for (i = 0 ; i < nbuf ; i++) {
937 ptdescr = (pcsca_bd_t __iomem *)(card->hw.rambase +
938 TX_BD_ADDR(ch, card->chan[ch].tx_next_bd));
939 nchar = (BD_DEF_LEN > tosend) ? tosend : BD_DEF_LEN;
940 if (cpc_readb(&ptdescr->status) & DST_OSB) {
941 memcpy_toio((void __iomem *)(card->hw.rambase +
942 cpc_readl(&ptdescr->ptbuf)),
943 &pdata[len - tosend],
944 nchar);
945 card->chan[ch].nfree_tx_bd--;
946 if ((i + 1) == nbuf) {
947 /* This must be the last BD to be used */
948 cpc_writeb(&ptdescr->status, DST_EOM);
949 } else {
950 cpc_writeb(&ptdescr->status, 0);
951 }
952 cpc_writew(&ptdescr->len, nchar);
953 } else {
954 CPC_TTY_DBG("%s: error in dma_buf_write\n",
955 (st_cpc_tty_area *)dev->cpc_tty->name);
956 stats->tx_dropped++;
957 return 1;
958 }
959 tosend -= nchar;
960 card->chan[ch].tx_next_bd =
961 (card->chan[ch].tx_next_bd + 1) & (N_DMA_TX_BUF - 1);
962 }
963
964 if (dev->trace_on) {
965 cpc_tty_trace(dev, buf, len,'T');
966 }
967
968 /* start transmission */
969 CPC_TTY_DBG("%s: start transmission\n",
970 (st_cpc_tty_area *)dev->cpc_tty->name);
971
972 CPC_TTY_LOCK(card, flags);
973 cpc_writeb(card->hw.scabase + DTX_REG(EDAL, ch),
974 TX_BD_ADDR(ch, chan->tx_next_bd));
975 cpc_writeb(card->hw.scabase + M_REG(CMD, ch), CMD_TX_ENA);
976 cpc_writeb(card->hw.scabase + DSR_TX(ch), DSR_DE);
977
978 if (card->hw.type == PC300_TE) {
979 cpc_writeb(card->hw.falcbase + card->hw.cpld_reg2,
980 cpc_readb(card->hw.falcbase + card->hw.cpld_reg2) |
981 (CPLD_REG2_FALC_LED1 << (2 * ch)));
982 }
983 CPC_TTY_UNLOCK(card, flags);
984 return 0;
985}
986
987/*
988 * PC300 TTY trace routine
989 *
990 * This routine send trace of connection to application.
991 * o clear descriptors
992 * o write data to DMA buffers
993 * o start the transmission
994 */
995
996static void cpc_tty_trace(pc300dev_t *dev, char* buf, int len, char rxtx)
997{
998 struct sk_buff *skb;
999
1000 if ((skb = dev_alloc_skb(10 + len)) == NULL) {
1001 /* out of memory */
1002 CPC_TTY_DBG("%s: tty_trace - out of memory\n", dev->dev->name);
1003 return;
1004 }
1005
1006 skb_put (skb, 10 + len);
1007 skb->dev = dev->dev;
1008 skb->protocol = htons(ETH_P_CUST);
1009 skb_reset_mac_header(skb);
1010 skb->pkt_type = PACKET_HOST;
1011 skb->len = 10 + len;
1012
1013 skb_copy_to_linear_data(skb, dev->dev->name, 5);
1014 skb->data[5] = '[';
1015 skb->data[6] = rxtx;
1016 skb->data[7] = ']';
1017 skb->data[8] = ':';
1018 skb->data[9] = ' ';
1019 skb_copy_to_linear_data_offset(skb, 10, buf, len);
1020 netif_rx(skb);
1021}
1022
1023/*
1024 * PC300 TTY unregister service routine
1025 *
1026 * This routine unregister one interface.
1027 */
1028void cpc_tty_unregister_service(pc300dev_t *pc300dev)
1029{
1030 st_cpc_tty_area *cpc_tty;
1031 ulong flags;
1032 int res;
1033
1034 if ((cpc_tty= (st_cpc_tty_area *) pc300dev->cpc_tty) == NULL) {
1035 CPC_TTY_DBG("%s: interface is not TTY\n", pc300dev->dev->name);
1036 return;
1037 }
1038 CPC_TTY_DBG("%s: cpc_tty_unregister_service", cpc_tty->name);
1039
1040 if (cpc_tty->pc300dev != pc300dev) {
1041 CPC_TTY_DBG("%s: invalid tty ptr=%s\n",
1042 pc300dev->dev->name, cpc_tty->name);
1043 return;
1044 }
1045
1046 if (--cpc_tty_cnt == 0) {
1047 if (serial_drv.refcount) {
1048 CPC_TTY_DBG("%s: unregister is not possible, refcount=%d",
1049 cpc_tty->name, serial_drv.refcount);
1050 cpc_tty_cnt++;
1051 cpc_tty_unreg_flag = 1;
1052 return;
1053 } else {
1054 CPC_TTY_DBG("%s: unregister the tty driver\n", cpc_tty->name);
1055 if ((res=tty_unregister_driver(&serial_drv))) {
1056 CPC_TTY_DBG("%s: ERROR ->unregister the tty driver error=%d\n",
1057 cpc_tty->name,res);
1058 }
1059 }
1060 }
1061 CPC_TTY_LOCK(pc300dev->chan->card,flags);
1062 cpc_tty->tty = NULL;
1063 CPC_TTY_UNLOCK(pc300dev->chan->card, flags);
1064 cpc_tty->tty_minor = 0;
1065 cpc_tty->state = CPC_TTY_ST_IDLE;
1066}
1067
1068/*
1069 * PC300 TTY trigger poll routine
1070 * This routine is called by pc300driver to treats Tx interrupt.
1071 */
1072void cpc_tty_trigger_poll(pc300dev_t *pc300dev)
1073{
1074 st_cpc_tty_area *cpc_tty = (st_cpc_tty_area *)pc300dev->cpc_tty;
1075 if (!cpc_tty) {
1076 return;
1077 }
1078 schedule_work(&(cpc_tty->tty_tx_work));
1079}
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-17 04:22:39 -0400