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-rw-r--r--drivers/net/r8169.c944
1 files changed, 528 insertions, 416 deletions
diff --git a/drivers/net/r8169.c b/drivers/net/r8169.c
index 5ec7752caa4..982a9010c7a 100644
--- a/drivers/net/r8169.c
+++ b/drivers/net/r8169.c
@@ -1,53 +1,11 @@
1/* 1/*
2========================================================================= 2 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
3 r8169.c: A RealTek RTL-8169 Gigabit Ethernet driver for Linux kernel 2.4.x. 3 *
4 -------------------------------------------------------------------- 4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5 5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6 History: 6 * Copyright (c) a lot of people too. Please respect their work.
7 Feb 4 2002 - created initially by ShuChen <shuchen@realtek.com.tw>. 7 *
8 May 20 2002 - Add link status force-mode and TBI mode support. 8 * See MAINTAINERS file for support contact information.
9 2004 - Massive updates. See kernel SCM system for details.
10=========================================================================
11 1. [DEPRECATED: use ethtool instead] The media can be forced in 5 modes.
12 Command: 'insmod r8169 media = SET_MEDIA'
13 Ex: 'insmod r8169 media = 0x04' will force PHY to operate in 100Mpbs Half-duplex.
14
15 SET_MEDIA can be:
16 _10_Half = 0x01
17 _10_Full = 0x02
18 _100_Half = 0x04
19 _100_Full = 0x08
20 _1000_Full = 0x10
21
22 2. Support TBI mode.
23=========================================================================
24VERSION 1.1 <2002/10/4>
25
26 The bit4:0 of MII register 4 is called "selector field", and have to be
27 00001b to indicate support of IEEE std 802.3 during NWay process of
28 exchanging Link Code Word (FLP).
29
30VERSION 1.2 <2002/11/30>
31
32 - Large style cleanup
33 - Use ether_crc in stock kernel (linux/crc32.h)
34 - Copy mc_filter setup code from 8139cp
35 (includes an optimization, and avoids set_bit use)
36
37VERSION 1.6LK <2004/04/14>
38
39 - Merge of Realtek's version 1.6
40 - Conversion to DMA API
41 - Suspend/resume
42 - Endianness
43 - Misc Rx/Tx bugs
44
45VERSION 2.2LK <2005/01/25>
46
47 - RX csum, TX csum/SG, TSO
48 - VLAN
49 - baby (< 7200) Jumbo frames support
50 - Merge of Realtek's version 2.2 (new phy)
51 */ 9 */
52 10
53#include <linux/module.h> 11#include <linux/module.h>
@@ -108,11 +66,6 @@ VERSION 2.2LK <2005/01/25>
108#define rtl8169_rx_quota(count, quota) count 66#define rtl8169_rx_quota(count, quota) count
109#endif 67#endif
110 68
111/* media options */
112#define MAX_UNITS 8
113static int media[MAX_UNITS] = { -1, -1, -1, -1, -1, -1, -1, -1 };
114static int num_media = 0;
115
116/* Maximum events (Rx packets, etc.) to handle at each interrupt. */ 69/* Maximum events (Rx packets, etc.) to handle at each interrupt. */
117static const int max_interrupt_work = 20; 70static const int max_interrupt_work = 20;
118 71
@@ -126,7 +79,7 @@ static const int multicast_filter_limit = 32;
126#define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */ 79#define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
127#define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */ 80#define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
128#define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */ 81#define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
129#define EarlyTxThld 0x3F /* 0x3F means NO early transmit */ 82#define EarlyTxThld 0x3F /* 0x3F means NO early transmit */
130#define RxPacketMaxSize 0x3FE8 /* 16K - 1 - ETH_HLEN - VLAN - CRC... */ 83#define RxPacketMaxSize 0x3FE8 /* 16K - 1 - ETH_HLEN - VLAN - CRC... */
131#define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */ 84#define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */
132#define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */ 85#define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
@@ -151,16 +104,17 @@ static const int multicast_filter_limit = 32;
151#define RTL_R32(reg) ((unsigned long) readl (ioaddr + (reg))) 104#define RTL_R32(reg) ((unsigned long) readl (ioaddr + (reg)))
152 105
153enum mac_version { 106enum mac_version {
154 RTL_GIGA_MAC_VER_01 = 0x00, 107 RTL_GIGA_MAC_VER_01 = 0x01, // 8169
155 RTL_GIGA_MAC_VER_02 = 0x01, 108 RTL_GIGA_MAC_VER_02 = 0x02, // 8169S
156 RTL_GIGA_MAC_VER_03 = 0x02, 109 RTL_GIGA_MAC_VER_03 = 0x03, // 8110S
157 RTL_GIGA_MAC_VER_04 = 0x03, 110 RTL_GIGA_MAC_VER_04 = 0x04, // 8169SB
158 RTL_GIGA_MAC_VER_05 = 0x04, 111 RTL_GIGA_MAC_VER_05 = 0x05, // 8110SCd
159 RTL_GIGA_MAC_VER_11 = 0x0b, 112 RTL_GIGA_MAC_VER_06 = 0x06, // 8110SCe
160 RTL_GIGA_MAC_VER_12 = 0x0c, 113 RTL_GIGA_MAC_VER_11 = 0x0b, // 8168Bb
161 RTL_GIGA_MAC_VER_13 = 0x0d, 114 RTL_GIGA_MAC_VER_12 = 0x0c, // 8168Be 8168Bf
162 RTL_GIGA_MAC_VER_14 = 0x0e, 115 RTL_GIGA_MAC_VER_13 = 0x0d, // 8101Eb 8101Ec
163 RTL_GIGA_MAC_VER_15 = 0x0f 116 RTL_GIGA_MAC_VER_14 = 0x0e, // 8101
117 RTL_GIGA_MAC_VER_15 = 0x0f // 8101
164}; 118};
165 119
166enum phy_version { 120enum phy_version {
@@ -180,11 +134,12 @@ static const struct {
180 u8 mac_version; 134 u8 mac_version;
181 u32 RxConfigMask; /* Clears the bits supported by this chip */ 135 u32 RxConfigMask; /* Clears the bits supported by this chip */
182} rtl_chip_info[] = { 136} rtl_chip_info[] = {
183 _R("RTL8169", RTL_GIGA_MAC_VER_01, 0xff7e1880), 137 _R("RTL8169", RTL_GIGA_MAC_VER_01, 0xff7e1880), // 8169
184 _R("RTL8169s/8110s", RTL_GIGA_MAC_VER_02, 0xff7e1880), 138 _R("RTL8169s", RTL_GIGA_MAC_VER_02, 0xff7e1880), // 8169S
185 _R("RTL8169s/8110s", RTL_GIGA_MAC_VER_03, 0xff7e1880), 139 _R("RTL8110s", RTL_GIGA_MAC_VER_03, 0xff7e1880), // 8110S
186 _R("RTL8169sb/8110sb", RTL_GIGA_MAC_VER_04, 0xff7e1880), 140 _R("RTL8169sb/8110sb", RTL_GIGA_MAC_VER_04, 0xff7e1880), // 8169SB
187 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_05, 0xff7e1880), 141 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_05, 0xff7e1880), // 8110SCd
142 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_06, 0xff7e1880), // 8110SCe
188 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_11, 0xff7e1880), // PCI-E 143 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_11, 0xff7e1880), // PCI-E
189 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_12, 0xff7e1880), // PCI-E 144 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_12, 0xff7e1880), // PCI-E
190 _R("RTL8101e", RTL_GIGA_MAC_VER_13, 0xff7e1880), // PCI-E 8139 145 _R("RTL8101e", RTL_GIGA_MAC_VER_13, 0xff7e1880), // PCI-E 8139
@@ -199,20 +154,15 @@ enum cfg_version {
199 RTL_CFG_2 154 RTL_CFG_2
200}; 155};
201 156
202static const struct { 157static void rtl_hw_start_8169(struct net_device *);
203 unsigned int region; 158static void rtl_hw_start_8168(struct net_device *);
204 unsigned int align; 159static void rtl_hw_start_8101(struct net_device *);
205} rtl_cfg_info[] = {
206 [RTL_CFG_0] = { 1, NET_IP_ALIGN },
207 [RTL_CFG_1] = { 2, NET_IP_ALIGN },
208 [RTL_CFG_2] = { 2, 8 }
209};
210 160
211static struct pci_device_id rtl8169_pci_tbl[] = { 161static struct pci_device_id rtl8169_pci_tbl[] = {
212 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 }, 162 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 },
213 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 }, 163 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 },
214 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 }, 164 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 },
215 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_2 }, 165 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 },
216 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 }, 166 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 },
217 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 }, 167 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 },
218 { PCI_DEVICE(0x1259, 0xc107), 0, 0, RTL_CFG_0 }, 168 { PCI_DEVICE(0x1259, 0xc107), 0, 0, RTL_CFG_0 },
@@ -230,62 +180,63 @@ static struct {
230 u32 msg_enable; 180 u32 msg_enable;
231} debug = { -1 }; 181} debug = { -1 };
232 182
233enum RTL8169_registers { 183enum rtl_registers {
234 MAC0 = 0, /* Ethernet hardware address. */ 184 MAC0 = 0, /* Ethernet hardware address. */
235 MAR0 = 8, /* Multicast filter. */ 185 MAC4 = 4,
236 CounterAddrLow = 0x10, 186 MAR0 = 8, /* Multicast filter. */
237 CounterAddrHigh = 0x14, 187 CounterAddrLow = 0x10,
238 TxDescStartAddrLow = 0x20, 188 CounterAddrHigh = 0x14,
239 TxDescStartAddrHigh = 0x24, 189 TxDescStartAddrLow = 0x20,
240 TxHDescStartAddrLow = 0x28, 190 TxDescStartAddrHigh = 0x24,
241 TxHDescStartAddrHigh = 0x2c, 191 TxHDescStartAddrLow = 0x28,
242 FLASH = 0x30, 192 TxHDescStartAddrHigh = 0x2c,
243 ERSR = 0x36, 193 FLASH = 0x30,
244 ChipCmd = 0x37, 194 ERSR = 0x36,
245 TxPoll = 0x38, 195 ChipCmd = 0x37,
246 IntrMask = 0x3C, 196 TxPoll = 0x38,
247 IntrStatus = 0x3E, 197 IntrMask = 0x3c,
248 TxConfig = 0x40, 198 IntrStatus = 0x3e,
249 RxConfig = 0x44, 199 TxConfig = 0x40,
250 RxMissed = 0x4C, 200 RxConfig = 0x44,
251 Cfg9346 = 0x50, 201 RxMissed = 0x4c,
252 Config0 = 0x51, 202 Cfg9346 = 0x50,
253 Config1 = 0x52, 203 Config0 = 0x51,
254 Config2 = 0x53, 204 Config1 = 0x52,
255 Config3 = 0x54, 205 Config2 = 0x53,
256 Config4 = 0x55, 206 Config3 = 0x54,
257 Config5 = 0x56, 207 Config4 = 0x55,
258 MultiIntr = 0x5C, 208 Config5 = 0x56,
259 PHYAR = 0x60, 209 MultiIntr = 0x5c,
260 TBICSR = 0x64, 210 PHYAR = 0x60,
261 TBI_ANAR = 0x68, 211 TBICSR = 0x64,
262 TBI_LPAR = 0x6A, 212 TBI_ANAR = 0x68,
263 PHYstatus = 0x6C, 213 TBI_LPAR = 0x6a,
264 RxMaxSize = 0xDA, 214 PHYstatus = 0x6c,
265 CPlusCmd = 0xE0, 215 RxMaxSize = 0xda,
266 IntrMitigate = 0xE2, 216 CPlusCmd = 0xe0,
267 RxDescAddrLow = 0xE4, 217 IntrMitigate = 0xe2,
268 RxDescAddrHigh = 0xE8, 218 RxDescAddrLow = 0xe4,
269 EarlyTxThres = 0xEC, 219 RxDescAddrHigh = 0xe8,
270 FuncEvent = 0xF0, 220 EarlyTxThres = 0xec,
271 FuncEventMask = 0xF4, 221 FuncEvent = 0xf0,
272 FuncPresetState = 0xF8, 222 FuncEventMask = 0xf4,
273 FuncForceEvent = 0xFC, 223 FuncPresetState = 0xf8,
224 FuncForceEvent = 0xfc,
274}; 225};
275 226
276enum RTL8169_register_content { 227enum rtl_register_content {
277 /* InterruptStatusBits */ 228 /* InterruptStatusBits */
278 SYSErr = 0x8000, 229 SYSErr = 0x8000,
279 PCSTimeout = 0x4000, 230 PCSTimeout = 0x4000,
280 SWInt = 0x0100, 231 SWInt = 0x0100,
281 TxDescUnavail = 0x80, 232 TxDescUnavail = 0x0080,
282 RxFIFOOver = 0x40, 233 RxFIFOOver = 0x0040,
283 LinkChg = 0x20, 234 LinkChg = 0x0020,
284 RxOverflow = 0x10, 235 RxOverflow = 0x0010,
285 TxErr = 0x08, 236 TxErr = 0x0008,
286 TxOK = 0x04, 237 TxOK = 0x0004,
287 RxErr = 0x02, 238 RxErr = 0x0002,
288 RxOK = 0x01, 239 RxOK = 0x0001,
289 240
290 /* RxStatusDesc */ 241 /* RxStatusDesc */
291 RxFOVF = (1 << 23), 242 RxFOVF = (1 << 23),
@@ -295,26 +246,31 @@ enum RTL8169_register_content {
295 RxCRC = (1 << 19), 246 RxCRC = (1 << 19),
296 247
297 /* ChipCmdBits */ 248 /* ChipCmdBits */
298 CmdReset = 0x10, 249 CmdReset = 0x10,
299 CmdRxEnb = 0x08, 250 CmdRxEnb = 0x08,
300 CmdTxEnb = 0x04, 251 CmdTxEnb = 0x04,
301 RxBufEmpty = 0x01, 252 RxBufEmpty = 0x01,
253
254 /* TXPoll register p.5 */
255 HPQ = 0x80, /* Poll cmd on the high prio queue */
256 NPQ = 0x40, /* Poll cmd on the low prio queue */
257 FSWInt = 0x01, /* Forced software interrupt */
302 258
303 /* Cfg9346Bits */ 259 /* Cfg9346Bits */
304 Cfg9346_Lock = 0x00, 260 Cfg9346_Lock = 0x00,
305 Cfg9346_Unlock = 0xC0, 261 Cfg9346_Unlock = 0xc0,
306 262
307 /* rx_mode_bits */ 263 /* rx_mode_bits */
308 AcceptErr = 0x20, 264 AcceptErr = 0x20,
309 AcceptRunt = 0x10, 265 AcceptRunt = 0x10,
310 AcceptBroadcast = 0x08, 266 AcceptBroadcast = 0x08,
311 AcceptMulticast = 0x04, 267 AcceptMulticast = 0x04,
312 AcceptMyPhys = 0x02, 268 AcceptMyPhys = 0x02,
313 AcceptAllPhys = 0x01, 269 AcceptAllPhys = 0x01,
314 270
315 /* RxConfigBits */ 271 /* RxConfigBits */
316 RxCfgFIFOShift = 13, 272 RxCfgFIFOShift = 13,
317 RxCfgDMAShift = 8, 273 RxCfgDMAShift = 8,
318 274
319 /* TxConfigBits */ 275 /* TxConfigBits */
320 TxInterFrameGapShift = 24, 276 TxInterFrameGapShift = 24,
@@ -323,6 +279,10 @@ enum RTL8169_register_content {
323 /* Config1 register p.24 */ 279 /* Config1 register p.24 */
324 PMEnable = (1 << 0), /* Power Management Enable */ 280 PMEnable = (1 << 0), /* Power Management Enable */
325 281
282 /* Config2 register p. 25 */
283 PCI_Clock_66MHz = 0x01,
284 PCI_Clock_33MHz = 0x00,
285
326 /* Config3 register p.25 */ 286 /* Config3 register p.25 */
327 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */ 287 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
328 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */ 288 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
@@ -343,36 +303,34 @@ enum RTL8169_register_content {
343 TBINwComplete = 0x01000000, 303 TBINwComplete = 0x01000000,
344 304
345 /* CPlusCmd p.31 */ 305 /* CPlusCmd p.31 */
306 PktCntrDisable = (1 << 7), // 8168
346 RxVlan = (1 << 6), 307 RxVlan = (1 << 6),
347 RxChkSum = (1 << 5), 308 RxChkSum = (1 << 5),
348 PCIDAC = (1 << 4), 309 PCIDAC = (1 << 4),
349 PCIMulRW = (1 << 3), 310 PCIMulRW = (1 << 3),
311 INTT_0 = 0x0000, // 8168
312 INTT_1 = 0x0001, // 8168
313 INTT_2 = 0x0002, // 8168
314 INTT_3 = 0x0003, // 8168
350 315
351 /* rtl8169_PHYstatus */ 316 /* rtl8169_PHYstatus */
352 TBI_Enable = 0x80, 317 TBI_Enable = 0x80,
353 TxFlowCtrl = 0x40, 318 TxFlowCtrl = 0x40,
354 RxFlowCtrl = 0x20, 319 RxFlowCtrl = 0x20,
355 _1000bpsF = 0x10, 320 _1000bpsF = 0x10,
356 _100bps = 0x08, 321 _100bps = 0x08,
357 _10bps = 0x04, 322 _10bps = 0x04,
358 LinkStatus = 0x02, 323 LinkStatus = 0x02,
359 FullDup = 0x01, 324 FullDup = 0x01,
360
361 /* _MediaType */
362 _10_Half = 0x01,
363 _10_Full = 0x02,
364 _100_Half = 0x04,
365 _100_Full = 0x08,
366 _1000_Full = 0x10,
367 325
368 /* _TBICSRBit */ 326 /* _TBICSRBit */
369 TBILinkOK = 0x02000000, 327 TBILinkOK = 0x02000000,
370 328
371 /* DumpCounterCommand */ 329 /* DumpCounterCommand */
372 CounterDump = 0x8, 330 CounterDump = 0x8,
373}; 331};
374 332
375enum _DescStatusBit { 333enum desc_status_bit {
376 DescOwn = (1 << 31), /* Descriptor is owned by NIC */ 334 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
377 RingEnd = (1 << 30), /* End of descriptor ring */ 335 RingEnd = (1 << 30), /* End of descriptor ring */
378 FirstFrag = (1 << 29), /* First segment of a packet */ 336 FirstFrag = (1 << 29), /* First segment of a packet */
@@ -405,15 +363,15 @@ enum _DescStatusBit {
405#define RsvdMask 0x3fffc000 363#define RsvdMask 0x3fffc000
406 364
407struct TxDesc { 365struct TxDesc {
408 u32 opts1; 366 __le32 opts1;
409 u32 opts2; 367 __le32 opts2;
410 u64 addr; 368 __le64 addr;
411}; 369};
412 370
413struct RxDesc { 371struct RxDesc {
414 u32 opts1; 372 __le32 opts1;
415 u32 opts2; 373 __le32 opts2;
416 u64 addr; 374 __le64 addr;
417}; 375};
418 376
419struct ring_info { 377struct ring_info {
@@ -446,6 +404,8 @@ struct rtl8169_private {
446 unsigned rx_buf_sz; 404 unsigned rx_buf_sz;
447 struct timer_list timer; 405 struct timer_list timer;
448 u16 cp_cmd; 406 u16 cp_cmd;
407 u16 intr_event;
408 u16 napi_event;
449 u16 intr_mask; 409 u16 intr_mask;
450 int phy_auto_nego_reg; 410 int phy_auto_nego_reg;
451 int phy_1000_ctrl_reg; 411 int phy_1000_ctrl_reg;
@@ -455,6 +415,7 @@ struct rtl8169_private {
455 int (*set_speed)(struct net_device *, u8 autoneg, u16 speed, u8 duplex); 415 int (*set_speed)(struct net_device *, u8 autoneg, u16 speed, u8 duplex);
456 void (*get_settings)(struct net_device *, struct ethtool_cmd *); 416 void (*get_settings)(struct net_device *, struct ethtool_cmd *);
457 void (*phy_reset_enable)(void __iomem *); 417 void (*phy_reset_enable)(void __iomem *);
418 void (*hw_start)(struct net_device *);
458 unsigned int (*phy_reset_pending)(void __iomem *); 419 unsigned int (*phy_reset_pending)(void __iomem *);
459 unsigned int (*link_ok)(void __iomem *); 420 unsigned int (*link_ok)(void __iomem *);
460 struct delayed_work task; 421 struct delayed_work task;
@@ -463,8 +424,6 @@ struct rtl8169_private {
463 424
464MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>"); 425MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
465MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver"); 426MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
466module_param_array(media, int, &num_media, 0);
467MODULE_PARM_DESC(media, "force phy operation. Deprecated by ethtool (8).");
468module_param(rx_copybreak, int, 0); 427module_param(rx_copybreak, int, 0);
469MODULE_PARM_DESC(rx_copybreak, "Copy breakpoint for copy-only-tiny-frames"); 428MODULE_PARM_DESC(rx_copybreak, "Copy breakpoint for copy-only-tiny-frames");
470module_param(use_dac, int, 0); 429module_param(use_dac, int, 0);
@@ -478,9 +437,9 @@ static int rtl8169_open(struct net_device *dev);
478static int rtl8169_start_xmit(struct sk_buff *skb, struct net_device *dev); 437static int rtl8169_start_xmit(struct sk_buff *skb, struct net_device *dev);
479static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance); 438static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance);
480static int rtl8169_init_ring(struct net_device *dev); 439static int rtl8169_init_ring(struct net_device *dev);
481static void rtl8169_hw_start(struct net_device *dev); 440static void rtl_hw_start(struct net_device *dev);
482static int rtl8169_close(struct net_device *dev); 441static int rtl8169_close(struct net_device *dev);
483static void rtl8169_set_rx_mode(struct net_device *dev); 442static void rtl_set_rx_mode(struct net_device *dev);
484static void rtl8169_tx_timeout(struct net_device *dev); 443static void rtl8169_tx_timeout(struct net_device *dev);
485static struct net_device_stats *rtl8169_get_stats(struct net_device *dev); 444static struct net_device_stats *rtl8169_get_stats(struct net_device *dev);
486static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *, 445static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *,
@@ -493,35 +452,37 @@ static void rtl8169_rx_clear(struct rtl8169_private *tp);
493static int rtl8169_poll(struct net_device *dev, int *budget); 452static int rtl8169_poll(struct net_device *dev, int *budget);
494#endif 453#endif
495 454
496static const u16 rtl8169_intr_mask =
497 SYSErr | LinkChg | RxOverflow | RxFIFOOver | TxErr | TxOK | RxErr | RxOK;
498static const u16 rtl8169_napi_event =
499 RxOK | RxOverflow | RxFIFOOver | TxOK | TxErr;
500static const unsigned int rtl8169_rx_config = 455static const unsigned int rtl8169_rx_config =
501 (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift); 456 (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);
502 457
503static void mdio_write(void __iomem *ioaddr, int RegAddr, int value) 458static void mdio_write(void __iomem *ioaddr, int reg_addr, int value)
504{ 459{
505 int i; 460 int i;
506 461
507 RTL_W32(PHYAR, 0x80000000 | (RegAddr & 0xFF) << 16 | value); 462 RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0xFF) << 16 | value);
508 463
509 for (i = 20; i > 0; i--) { 464 for (i = 20; i > 0; i--) {
510 /* Check if the RTL8169 has completed writing to the specified MII register */ 465 /*
466 * Check if the RTL8169 has completed writing to the specified
467 * MII register.
468 */
511 if (!(RTL_R32(PHYAR) & 0x80000000)) 469 if (!(RTL_R32(PHYAR) & 0x80000000))
512 break; 470 break;
513 udelay(25); 471 udelay(25);
514 } 472 }
515} 473}
516 474
517static int mdio_read(void __iomem *ioaddr, int RegAddr) 475static int mdio_read(void __iomem *ioaddr, int reg_addr)
518{ 476{
519 int i, value = -1; 477 int i, value = -1;
520 478
521 RTL_W32(PHYAR, 0x0 | (RegAddr & 0xFF) << 16); 479 RTL_W32(PHYAR, 0x0 | (reg_addr & 0xFF) << 16);
522 480
523 for (i = 20; i > 0; i--) { 481 for (i = 20; i > 0; i--) {
524 /* Check if the RTL8169 has completed retrieving data from the specified MII register */ 482 /*
483 * Check if the RTL8169 has completed retrieving data from
484 * the specified MII register.
485 */
525 if (RTL_R32(PHYAR) & 0x80000000) { 486 if (RTL_R32(PHYAR) & 0x80000000) {
526 value = (int) (RTL_R32(PHYAR) & 0xFFFF); 487 value = (int) (RTL_R32(PHYAR) & 0xFFFF);
527 break; 488 break;
@@ -579,7 +540,8 @@ static void rtl8169_xmii_reset_enable(void __iomem *ioaddr)
579} 540}
580 541
581static void rtl8169_check_link_status(struct net_device *dev, 542static void rtl8169_check_link_status(struct net_device *dev,
582 struct rtl8169_private *tp, void __iomem *ioaddr) 543 struct rtl8169_private *tp,
544 void __iomem *ioaddr)
583{ 545{
584 unsigned long flags; 546 unsigned long flags;
585 547
@@ -596,38 +558,6 @@ static void rtl8169_check_link_status(struct net_device *dev,
596 spin_unlock_irqrestore(&tp->lock, flags); 558 spin_unlock_irqrestore(&tp->lock, flags);
597} 559}
598 560
599static void rtl8169_link_option(int idx, u8 *autoneg, u16 *speed, u8 *duplex)
600{
601 struct {
602 u16 speed;
603 u8 duplex;
604 u8 autoneg;
605 u8 media;
606 } link_settings[] = {
607 { SPEED_10, DUPLEX_HALF, AUTONEG_DISABLE, _10_Half },
608 { SPEED_10, DUPLEX_FULL, AUTONEG_DISABLE, _10_Full },
609 { SPEED_100, DUPLEX_HALF, AUTONEG_DISABLE, _100_Half },
610 { SPEED_100, DUPLEX_FULL, AUTONEG_DISABLE, _100_Full },
611 { SPEED_1000, DUPLEX_FULL, AUTONEG_DISABLE, _1000_Full },
612 /* Make TBI happy */
613 { SPEED_1000, DUPLEX_FULL, AUTONEG_ENABLE, 0xff }
614 }, *p;
615 unsigned char option;
616
617 option = ((idx < MAX_UNITS) && (idx >= 0)) ? media[idx] : 0xff;
618
619 if ((option != 0xff) && !idx && netif_msg_drv(&debug))
620 printk(KERN_WARNING PFX "media option is deprecated.\n");
621
622 for (p = link_settings; p->media != 0xff; p++) {
623 if (p->media == option)
624 break;
625 }
626 *autoneg = p->autoneg;
627 *speed = p->speed;
628 *duplex = p->duplex;
629}
630
631static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 561static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
632{ 562{
633 struct rtl8169_private *tp = netdev_priv(dev); 563 struct rtl8169_private *tp = netdev_priv(dev);
@@ -667,7 +597,7 @@ static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
667{ 597{
668 struct rtl8169_private *tp = netdev_priv(dev); 598 struct rtl8169_private *tp = netdev_priv(dev);
669 void __iomem *ioaddr = tp->mmio_addr; 599 void __iomem *ioaddr = tp->mmio_addr;
670 int i; 600 unsigned int i;
671 static struct { 601 static struct {
672 u32 opt; 602 u32 opt;
673 u16 reg; 603 u16 reg;
@@ -893,8 +823,7 @@ static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
893 int ret; 823 int ret;
894 824
895 if (tp->vlgrp && (opts2 & RxVlanTag)) { 825 if (tp->vlgrp && (opts2 & RxVlanTag)) {
896 rtl8169_rx_hwaccel_skb(skb, tp->vlgrp, 826 rtl8169_rx_hwaccel_skb(skb, tp->vlgrp, swab16(opts2 & 0xffff));
897 swab16(opts2 & 0xffff));
898 ret = 0; 827 ret = 0;
899 } else 828 } else
900 ret = -1; 829 ret = -1;
@@ -1115,7 +1044,6 @@ static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1115 } 1044 }
1116} 1045}
1117 1046
1118
1119static const struct ethtool_ops rtl8169_ethtool_ops = { 1047static const struct ethtool_ops rtl8169_ethtool_ops = {
1120 .get_drvinfo = rtl8169_get_drvinfo, 1048 .get_drvinfo = rtl8169_get_drvinfo,
1121 .get_regs_len = rtl8169_get_regs_len, 1049 .get_regs_len = rtl8169_get_regs_len,
@@ -1141,8 +1069,8 @@ static const struct ethtool_ops rtl8169_ethtool_ops = {
1141 .get_perm_addr = ethtool_op_get_perm_addr, 1069 .get_perm_addr = ethtool_op_get_perm_addr,
1142}; 1070};
1143 1071
1144static void rtl8169_write_gmii_reg_bit(void __iomem *ioaddr, int reg, int bitnum, 1072static void rtl8169_write_gmii_reg_bit(void __iomem *ioaddr, int reg,
1145 int bitval) 1073 int bitnum, int bitval)
1146{ 1074{
1147 int val; 1075 int val;
1148 1076
@@ -1152,8 +1080,20 @@ static void rtl8169_write_gmii_reg_bit(void __iomem *ioaddr, int reg, int bitnum
1152 mdio_write(ioaddr, reg, val & 0xffff); 1080 mdio_write(ioaddr, reg, val & 0xffff);
1153} 1081}
1154 1082
1155static void rtl8169_get_mac_version(struct rtl8169_private *tp, void __iomem *ioaddr) 1083static void rtl8169_get_mac_version(struct rtl8169_private *tp,
1084 void __iomem *ioaddr)
1156{ 1085{
1086 /*
1087 * The driver currently handles the 8168Bf and the 8168Be identically
1088 * but they can be identified more specifically through the test below
1089 * if needed:
1090 *
1091 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
1092 *
1093 * Same thing for the 8101Eb and the 8101Ec:
1094 *
1095 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
1096 */
1157 const struct { 1097 const struct {
1158 u32 mask; 1098 u32 mask;
1159 int mac_version; 1099 int mac_version;
@@ -1163,6 +1103,7 @@ static void rtl8169_get_mac_version(struct rtl8169_private *tp, void __iomem *io
1163 { 0x34000000, RTL_GIGA_MAC_VER_13 }, 1103 { 0x34000000, RTL_GIGA_MAC_VER_13 },
1164 { 0x30800000, RTL_GIGA_MAC_VER_14 }, 1104 { 0x30800000, RTL_GIGA_MAC_VER_14 },
1165 { 0x30000000, RTL_GIGA_MAC_VER_11 }, 1105 { 0x30000000, RTL_GIGA_MAC_VER_11 },
1106 { 0x98000000, RTL_GIGA_MAC_VER_06 },
1166 { 0x18000000, RTL_GIGA_MAC_VER_05 }, 1107 { 0x18000000, RTL_GIGA_MAC_VER_05 },
1167 { 0x10000000, RTL_GIGA_MAC_VER_04 }, 1108 { 0x10000000, RTL_GIGA_MAC_VER_04 },
1168 { 0x04000000, RTL_GIGA_MAC_VER_03 }, 1109 { 0x04000000, RTL_GIGA_MAC_VER_03 },
@@ -1171,7 +1112,7 @@ static void rtl8169_get_mac_version(struct rtl8169_private *tp, void __iomem *io
1171 }, *p = mac_info; 1112 }, *p = mac_info;
1172 u32 reg; 1113 u32 reg;
1173 1114
1174 reg = RTL_R32(TxConfig) & 0x7c800000; 1115 reg = RTL_R32(TxConfig) & 0xfc800000;
1175 while ((reg & p->mask) != p->mask) 1116 while ((reg & p->mask) != p->mask)
1176 p++; 1117 p++;
1177 tp->mac_version = p->mac_version; 1118 tp->mac_version = p->mac_version;
@@ -1182,7 +1123,8 @@ static void rtl8169_print_mac_version(struct rtl8169_private *tp)
1182 dprintk("mac_version = 0x%02x\n", tp->mac_version); 1123 dprintk("mac_version = 0x%02x\n", tp->mac_version);
1183} 1124}
1184 1125
1185static void rtl8169_get_phy_version(struct rtl8169_private *tp, void __iomem *ioaddr) 1126static void rtl8169_get_phy_version(struct rtl8169_private *tp,
1127 void __iomem *ioaddr)
1186{ 1128{
1187 const struct { 1129 const struct {
1188 u16 mask; 1130 u16 mask;
@@ -1259,7 +1201,7 @@ static void rtl8169_hw_phy_config(struct net_device *dev)
1259 0xbf00 } //w 0 15 0 bf00 1201 0xbf00 } //w 0 15 0 bf00
1260 } 1202 }
1261 }, *p = phy_magic; 1203 }, *p = phy_magic;
1262 int i; 1204 unsigned int i;
1263 1205
1264 rtl8169_print_mac_version(tp); 1206 rtl8169_print_mac_version(tp);
1265 rtl8169_print_phy_version(tp); 1207 rtl8169_print_phy_version(tp);
@@ -1393,7 +1335,7 @@ static void rtl8169_phy_reset(struct net_device *dev,
1393 struct rtl8169_private *tp) 1335 struct rtl8169_private *tp)
1394{ 1336{
1395 void __iomem *ioaddr = tp->mmio_addr; 1337 void __iomem *ioaddr = tp->mmio_addr;
1396 int i; 1338 unsigned int i;
1397 1339
1398 tp->phy_reset_enable(ioaddr); 1340 tp->phy_reset_enable(ioaddr);
1399 for (i = 0; i < 100; i++) { 1341 for (i = 0; i < 100; i++) {
@@ -1408,21 +1350,16 @@ static void rtl8169_phy_reset(struct net_device *dev,
1408static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp) 1350static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
1409{ 1351{
1410 void __iomem *ioaddr = tp->mmio_addr; 1352 void __iomem *ioaddr = tp->mmio_addr;
1411 static int board_idx = -1;
1412 u8 autoneg, duplex;
1413 u16 speed;
1414
1415 board_idx++;
1416 1353
1417 rtl8169_hw_phy_config(dev); 1354 rtl8169_hw_phy_config(dev);
1418 1355
1419 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n"); 1356 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1420 RTL_W8(0x82, 0x01); 1357 RTL_W8(0x82, 0x01);
1421 1358
1422 if (tp->mac_version < RTL_GIGA_MAC_VER_03) { 1359 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
1423 dprintk("Set PCI Latency=0x40\n"); 1360
1424 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40); 1361 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
1425 } 1362 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
1426 1363
1427 if (tp->mac_version == RTL_GIGA_MAC_VER_02) { 1364 if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
1428 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n"); 1365 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
@@ -1431,16 +1368,52 @@ static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
1431 mdio_write(ioaddr, 0x0b, 0x0000); //w 0x0b 15 0 0 1368 mdio_write(ioaddr, 0x0b, 0x0000); //w 0x0b 15 0 0
1432 } 1369 }
1433 1370
1434 rtl8169_link_option(board_idx, &autoneg, &speed, &duplex);
1435
1436 rtl8169_phy_reset(dev, tp); 1371 rtl8169_phy_reset(dev, tp);
1437 1372
1438 rtl8169_set_speed(dev, autoneg, speed, duplex); 1373 /*
1374 * rtl8169_set_speed_xmii takes good care of the Fast Ethernet
1375 * only 8101. Don't panic.
1376 */
1377 rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL);
1439 1378
1440 if ((RTL_R8(PHYstatus) & TBI_Enable) && netif_msg_link(tp)) 1379 if ((RTL_R8(PHYstatus) & TBI_Enable) && netif_msg_link(tp))
1441 printk(KERN_INFO PFX "%s: TBI auto-negotiating\n", dev->name); 1380 printk(KERN_INFO PFX "%s: TBI auto-negotiating\n", dev->name);
1442} 1381}
1443 1382
1383static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
1384{
1385 void __iomem *ioaddr = tp->mmio_addr;
1386 u32 high;
1387 u32 low;
1388
1389 low = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24);
1390 high = addr[4] | (addr[5] << 8);
1391
1392 spin_lock_irq(&tp->lock);
1393
1394 RTL_W8(Cfg9346, Cfg9346_Unlock);
1395 RTL_W32(MAC0, low);
1396 RTL_W32(MAC4, high);
1397 RTL_W8(Cfg9346, Cfg9346_Lock);
1398
1399 spin_unlock_irq(&tp->lock);
1400}
1401
1402static int rtl_set_mac_address(struct net_device *dev, void *p)
1403{
1404 struct rtl8169_private *tp = netdev_priv(dev);
1405 struct sockaddr *addr = p;
1406
1407 if (!is_valid_ether_addr(addr->sa_data))
1408 return -EADDRNOTAVAIL;
1409
1410 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
1411
1412 rtl_rar_set(tp, dev->dev_addr);
1413
1414 return 0;
1415}
1416
1444static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) 1417static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1445{ 1418{
1446 struct rtl8169_private *tp = netdev_priv(dev); 1419 struct rtl8169_private *tp = netdev_priv(dev);
@@ -1467,15 +1440,49 @@ static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1467 return -EOPNOTSUPP; 1440 return -EOPNOTSUPP;
1468} 1441}
1469 1442
1443static const struct rtl_cfg_info {
1444 void (*hw_start)(struct net_device *);
1445 unsigned int region;
1446 unsigned int align;
1447 u16 intr_event;
1448 u16 napi_event;
1449} rtl_cfg_infos [] = {
1450 [RTL_CFG_0] = {
1451 .hw_start = rtl_hw_start_8169,
1452 .region = 1,
1453 .align = 0,
1454 .intr_event = SYSErr | LinkChg | RxOverflow |
1455 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
1456 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow
1457 },
1458 [RTL_CFG_1] = {
1459 .hw_start = rtl_hw_start_8168,
1460 .region = 2,
1461 .align = 8,
1462 .intr_event = SYSErr | LinkChg | RxOverflow |
1463 TxErr | TxOK | RxOK | RxErr,
1464 .napi_event = TxErr | TxOK | RxOK | RxOverflow
1465 },
1466 [RTL_CFG_2] = {
1467 .hw_start = rtl_hw_start_8101,
1468 .region = 2,
1469 .align = 8,
1470 .intr_event = SYSErr | LinkChg | RxOverflow | PCSTimeout |
1471 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
1472 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow
1473 }
1474};
1475
1470static int __devinit 1476static int __devinit
1471rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) 1477rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1472{ 1478{
1473 const unsigned int region = rtl_cfg_info[ent->driver_data].region; 1479 const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
1480 const unsigned int region = cfg->region;
1474 struct rtl8169_private *tp; 1481 struct rtl8169_private *tp;
1475 struct net_device *dev; 1482 struct net_device *dev;
1476 void __iomem *ioaddr; 1483 void __iomem *ioaddr;
1477 unsigned int pm_cap; 1484 unsigned int i;
1478 int i, rc; 1485 int rc;
1479 1486
1480 if (netif_msg_drv(&debug)) { 1487 if (netif_msg_drv(&debug)) {
1481 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n", 1488 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
@@ -1508,20 +1515,6 @@ rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1508 if (rc < 0) 1515 if (rc < 0)
1509 goto err_out_disable_2; 1516 goto err_out_disable_2;
1510 1517
1511 /* save power state before pci_enable_device overwrites it */
1512 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
1513 if (pm_cap) {
1514 u16 pwr_command, acpi_idle_state;
1515
1516 pci_read_config_word(pdev, pm_cap + PCI_PM_CTRL, &pwr_command);
1517 acpi_idle_state = pwr_command & PCI_PM_CTRL_STATE_MASK;
1518 } else {
1519 if (netif_msg_probe(tp)) {
1520 dev_err(&pdev->dev,
1521 "PowerManagement capability not found.\n");
1522 }
1523 }
1524
1525 /* make sure PCI base addr 1 is MMIO */ 1518 /* make sure PCI base addr 1 is MMIO */
1526 if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) { 1519 if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
1527 if (netif_msg_probe(tp)) { 1520 if (netif_msg_probe(tp)) {
@@ -1585,7 +1578,7 @@ rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1585 RTL_W8(ChipCmd, CmdReset); 1578 RTL_W8(ChipCmd, CmdReset);
1586 1579
1587 /* Check that the chip has finished the reset. */ 1580 /* Check that the chip has finished the reset. */
1588 for (i = 100; i > 0; i--) { 1581 for (i = 0; i < 100; i++) {
1589 if ((RTL_R8(ChipCmd) & CmdReset) == 0) 1582 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
1590 break; 1583 break;
1591 msleep_interruptible(1); 1584 msleep_interruptible(1);
@@ -1647,11 +1640,12 @@ rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1647 SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops); 1640 SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
1648 dev->stop = rtl8169_close; 1641 dev->stop = rtl8169_close;
1649 dev->tx_timeout = rtl8169_tx_timeout; 1642 dev->tx_timeout = rtl8169_tx_timeout;
1650 dev->set_multicast_list = rtl8169_set_rx_mode; 1643 dev->set_multicast_list = rtl_set_rx_mode;
1651 dev->watchdog_timeo = RTL8169_TX_TIMEOUT; 1644 dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
1652 dev->irq = pdev->irq; 1645 dev->irq = pdev->irq;
1653 dev->base_addr = (unsigned long) ioaddr; 1646 dev->base_addr = (unsigned long) ioaddr;
1654 dev->change_mtu = rtl8169_change_mtu; 1647 dev->change_mtu = rtl8169_change_mtu;
1648 dev->set_mac_address = rtl_set_mac_address;
1655 1649
1656#ifdef CONFIG_R8169_NAPI 1650#ifdef CONFIG_R8169_NAPI
1657 dev->poll = rtl8169_poll; 1651 dev->poll = rtl8169_poll;
@@ -1670,7 +1664,10 @@ rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1670 tp->intr_mask = 0xffff; 1664 tp->intr_mask = 0xffff;
1671 tp->pci_dev = pdev; 1665 tp->pci_dev = pdev;
1672 tp->mmio_addr = ioaddr; 1666 tp->mmio_addr = ioaddr;
1673 tp->align = rtl_cfg_info[ent->driver_data].align; 1667 tp->align = cfg->align;
1668 tp->hw_start = cfg->hw_start;
1669 tp->intr_event = cfg->intr_event;
1670 tp->napi_event = cfg->napi_event;
1674 1671
1675 init_timer(&tp->timer); 1672 init_timer(&tp->timer);
1676 tp->timer.data = (unsigned long) dev; 1673 tp->timer.data = (unsigned long) dev;
@@ -1685,15 +1682,17 @@ rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1685 pci_set_drvdata(pdev, dev); 1682 pci_set_drvdata(pdev, dev);
1686 1683
1687 if (netif_msg_probe(tp)) { 1684 if (netif_msg_probe(tp)) {
1685 u32 xid = RTL_R32(TxConfig) & 0x7cf0f8ff;
1686
1688 printk(KERN_INFO "%s: %s at 0x%lx, " 1687 printk(KERN_INFO "%s: %s at 0x%lx, "
1689 "%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x, " 1688 "%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x, "
1690 "IRQ %d\n", 1689 "XID %08x IRQ %d\n",
1691 dev->name, 1690 dev->name,
1692 rtl_chip_info[tp->chipset].name, 1691 rtl_chip_info[tp->chipset].name,
1693 dev->base_addr, 1692 dev->base_addr,
1694 dev->dev_addr[0], dev->dev_addr[1], 1693 dev->dev_addr[0], dev->dev_addr[1],
1695 dev->dev_addr[2], dev->dev_addr[3], 1694 dev->dev_addr[2], dev->dev_addr[3],
1696 dev->dev_addr[4], dev->dev_addr[5], dev->irq); 1695 dev->dev_addr[4], dev->dev_addr[5], xid, dev->irq);
1697 } 1696 }
1698 1697
1699 rtl8169_init_phy(dev, tp); 1698 rtl8169_init_phy(dev, tp);
@@ -1714,15 +1713,11 @@ err_out_free_dev_1:
1714 goto out; 1713 goto out;
1715} 1714}
1716 1715
1717static void __devexit 1716static void __devexit rtl8169_remove_one(struct pci_dev *pdev)
1718rtl8169_remove_one(struct pci_dev *pdev)
1719{ 1717{
1720 struct net_device *dev = pci_get_drvdata(pdev); 1718 struct net_device *dev = pci_get_drvdata(pdev);
1721 struct rtl8169_private *tp = netdev_priv(dev); 1719 struct rtl8169_private *tp = netdev_priv(dev);
1722 1720
1723 assert(dev != NULL);
1724 assert(tp != NULL);
1725
1726 flush_scheduled_work(); 1721 flush_scheduled_work();
1727 1722
1728 unregister_netdev(dev); 1723 unregister_netdev(dev);
@@ -1774,7 +1769,7 @@ static int rtl8169_open(struct net_device *dev)
1774 if (retval < 0) 1769 if (retval < 0)
1775 goto err_release_ring_2; 1770 goto err_release_ring_2;
1776 1771
1777 rtl8169_hw_start(dev); 1772 rtl_hw_start(dev);
1778 1773
1779 rtl8169_request_timer(dev); 1774 rtl8169_request_timer(dev);
1780 1775
@@ -1805,7 +1800,7 @@ static void rtl8169_hw_reset(void __iomem *ioaddr)
1805 RTL_R8(ChipCmd); 1800 RTL_R8(ChipCmd);
1806} 1801}
1807 1802
1808static void rtl8169_set_rx_tx_config_registers(struct rtl8169_private *tp) 1803static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
1809{ 1804{
1810 void __iomem *ioaddr = tp->mmio_addr; 1805 void __iomem *ioaddr = tp->mmio_addr;
1811 u32 cfg = rtl8169_rx_config; 1806 u32 cfg = rtl8169_rx_config;
@@ -1818,45 +1813,90 @@ static void rtl8169_set_rx_tx_config_registers(struct rtl8169_private *tp)
1818 (InterFrameGap << TxInterFrameGapShift)); 1813 (InterFrameGap << TxInterFrameGapShift));
1819} 1814}
1820 1815
1821static void rtl8169_hw_start(struct net_device *dev) 1816static void rtl_hw_start(struct net_device *dev)
1822{ 1817{
1823 struct rtl8169_private *tp = netdev_priv(dev); 1818 struct rtl8169_private *tp = netdev_priv(dev);
1824 void __iomem *ioaddr = tp->mmio_addr; 1819 void __iomem *ioaddr = tp->mmio_addr;
1825 struct pci_dev *pdev = tp->pci_dev; 1820 unsigned int i;
1826 u16 cmd;
1827 u32 i;
1828 1821
1829 /* Soft reset the chip. */ 1822 /* Soft reset the chip. */
1830 RTL_W8(ChipCmd, CmdReset); 1823 RTL_W8(ChipCmd, CmdReset);
1831 1824
1832 /* Check that the chip has finished the reset. */ 1825 /* Check that the chip has finished the reset. */
1833 for (i = 100; i > 0; i--) { 1826 for (i = 0; i < 100; i++) {
1834 if ((RTL_R8(ChipCmd) & CmdReset) == 0) 1827 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
1835 break; 1828 break;
1836 msleep_interruptible(1); 1829 msleep_interruptible(1);
1837 } 1830 }
1838 1831
1839 if (tp->mac_version == RTL_GIGA_MAC_VER_05) { 1832 tp->hw_start(dev);
1840 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
1841 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
1842 }
1843 1833
1844 if (tp->mac_version == RTL_GIGA_MAC_VER_13) { 1834 netif_start_queue(dev);
1845 pci_write_config_word(pdev, 0x68, 0x00); 1835}
1846 pci_write_config_word(pdev, 0x69, 0x08);
1847 }
1848 1836
1849 /* Undocumented stuff. */
1850 if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
1851 /* Realtek's r1000_n.c driver uses '&& 0x01' here. Well... */
1852 if ((RTL_R8(Config2) & 0x07) & 0x01)
1853 RTL_W32(0x7c, 0x0007ffff);
1854 1837
1855 RTL_W32(0x7c, 0x0007ff00); 1838static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
1839 void __iomem *ioaddr)
1840{
1841 /*
1842 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
1843 * register to be written before TxDescAddrLow to work.
1844 * Switching from MMIO to I/O access fixes the issue as well.
1845 */
1846 RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
1847 RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_32BIT_MASK);
1848 RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
1849 RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_32BIT_MASK);
1850}
1851
1852static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
1853{
1854 u16 cmd;
1855
1856 cmd = RTL_R16(CPlusCmd);
1857 RTL_W16(CPlusCmd, cmd);
1858 return cmd;
1859}
1860
1861static void rtl_set_rx_max_size(void __iomem *ioaddr)
1862{
1863 /* Low hurts. Let's disable the filtering. */
1864 RTL_W16(RxMaxSize, 16383);
1865}
1866
1867static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
1868{
1869 struct {
1870 u32 mac_version;
1871 u32 clk;
1872 u32 val;
1873 } cfg2_info [] = {
1874 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
1875 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
1876 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
1877 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
1878 }, *p = cfg2_info;
1879 unsigned int i;
1880 u32 clk;
1856 1881
1857 pci_read_config_word(pdev, PCI_COMMAND, &cmd); 1882 clk = RTL_R8(Config2) & PCI_Clock_66MHz;
1858 cmd = cmd & 0xef; 1883 for (i = 0; i < ARRAY_SIZE(cfg2_info); i++) {
1859 pci_write_config_word(pdev, PCI_COMMAND, cmd); 1884 if ((p->mac_version == mac_version) && (p->clk == clk)) {
1885 RTL_W32(0x7c, p->val);
1886 break;
1887 }
1888 }
1889}
1890
1891static void rtl_hw_start_8169(struct net_device *dev)
1892{
1893 struct rtl8169_private *tp = netdev_priv(dev);
1894 void __iomem *ioaddr = tp->mmio_addr;
1895 struct pci_dev *pdev = tp->pci_dev;
1896
1897 if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
1898 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
1899 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
1860 } 1900 }
1861 1901
1862 RTL_W8(Cfg9346, Cfg9346_Unlock); 1902 RTL_W8(Cfg9346, Cfg9346_Unlock);
@@ -1868,19 +1908,11 @@ static void rtl8169_hw_start(struct net_device *dev)
1868 1908
1869 RTL_W8(EarlyTxThres, EarlyTxThld); 1909 RTL_W8(EarlyTxThres, EarlyTxThld);
1870 1910
1871 /* Low hurts. Let's disable the filtering. */ 1911 rtl_set_rx_max_size(ioaddr);
1872 RTL_W16(RxMaxSize, 16383);
1873
1874 if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
1875 (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
1876 (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
1877 (tp->mac_version == RTL_GIGA_MAC_VER_04))
1878 rtl8169_set_rx_tx_config_registers(tp);
1879 1912
1880 cmd = RTL_R16(CPlusCmd); 1913 rtl_set_rx_tx_config_registers(tp);
1881 RTL_W16(CPlusCmd, cmd);
1882 1914
1883 tp->cp_cmd |= cmd | PCIMulRW; 1915 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
1884 1916
1885 if ((tp->mac_version == RTL_GIGA_MAC_VER_02) || 1917 if ((tp->mac_version == RTL_GIGA_MAC_VER_02) ||
1886 (tp->mac_version == RTL_GIGA_MAC_VER_03)) { 1918 (tp->mac_version == RTL_GIGA_MAC_VER_03)) {
@@ -1891,29 +1923,15 @@ static void rtl8169_hw_start(struct net_device *dev)
1891 1923
1892 RTL_W16(CPlusCmd, tp->cp_cmd); 1924 RTL_W16(CPlusCmd, tp->cp_cmd);
1893 1925
1926 rtl8169_set_magic_reg(ioaddr, tp->mac_version);
1927
1894 /* 1928 /*
1895 * Undocumented corner. Supposedly: 1929 * Undocumented corner. Supposedly:
1896 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets 1930 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
1897 */ 1931 */
1898 RTL_W16(IntrMitigate, 0x0000); 1932 RTL_W16(IntrMitigate, 0x0000);
1899 1933
1900 /* 1934 rtl_set_rx_tx_desc_registers(tp, ioaddr);
1901 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
1902 * register to be written before TxDescAddrLow to work.
1903 * Switching from MMIO to I/O access fixes the issue as well.
1904 */
1905 RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr >> 32));
1906 RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr & DMA_32BIT_MASK));
1907 RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr >> 32));
1908 RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr & DMA_32BIT_MASK));
1909
1910 if ((tp->mac_version != RTL_GIGA_MAC_VER_01) &&
1911 (tp->mac_version != RTL_GIGA_MAC_VER_02) &&
1912 (tp->mac_version != RTL_GIGA_MAC_VER_03) &&
1913 (tp->mac_version != RTL_GIGA_MAC_VER_04)) {
1914 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
1915 rtl8169_set_rx_tx_config_registers(tp);
1916 }
1917 1935
1918 RTL_W8(Cfg9346, Cfg9346_Lock); 1936 RTL_W8(Cfg9346, Cfg9346_Lock);
1919 1937
@@ -1922,15 +1940,107 @@ static void rtl8169_hw_start(struct net_device *dev)
1922 1940
1923 RTL_W32(RxMissed, 0); 1941 RTL_W32(RxMissed, 0);
1924 1942
1925 rtl8169_set_rx_mode(dev); 1943 rtl_set_rx_mode(dev);
1926 1944
1927 /* no early-rx interrupts */ 1945 /* no early-rx interrupts */
1928 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000); 1946 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
1929 1947
1930 /* Enable all known interrupts by setting the interrupt mask. */ 1948 /* Enable all known interrupts by setting the interrupt mask. */
1931 RTL_W16(IntrMask, rtl8169_intr_mask); 1949 RTL_W16(IntrMask, tp->intr_event);
1932 1950
1933 netif_start_queue(dev); 1951 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
1952}
1953
1954static void rtl_hw_start_8168(struct net_device *dev)
1955{
1956 struct rtl8169_private *tp = netdev_priv(dev);
1957 void __iomem *ioaddr = tp->mmio_addr;
1958 struct pci_dev *pdev = tp->pci_dev;
1959 u8 ctl;
1960
1961 RTL_W8(Cfg9346, Cfg9346_Unlock);
1962
1963 RTL_W8(EarlyTxThres, EarlyTxThld);
1964
1965 rtl_set_rx_max_size(ioaddr);
1966
1967 rtl_set_rx_tx_config_registers(tp);
1968
1969 tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
1970
1971 RTL_W16(CPlusCmd, tp->cp_cmd);
1972
1973 /* Tx performance tweak. */
1974 pci_read_config_byte(pdev, 0x69, &ctl);
1975 ctl = (ctl & ~0x70) | 0x50;
1976 pci_write_config_byte(pdev, 0x69, ctl);
1977
1978 RTL_W16(IntrMitigate, 0x5151);
1979
1980 /* Work around for RxFIFO overflow. */
1981 if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
1982 tp->intr_event |= RxFIFOOver | PCSTimeout;
1983 tp->intr_event &= ~RxOverflow;
1984 }
1985
1986 rtl_set_rx_tx_desc_registers(tp, ioaddr);
1987
1988 RTL_W8(Cfg9346, Cfg9346_Lock);
1989
1990 RTL_R8(IntrMask);
1991
1992 RTL_W32(RxMissed, 0);
1993
1994 rtl_set_rx_mode(dev);
1995
1996 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
1997
1998 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
1999
2000 RTL_W16(IntrMask, tp->intr_event);
2001}
2002
2003static void rtl_hw_start_8101(struct net_device *dev)
2004{
2005 struct rtl8169_private *tp = netdev_priv(dev);
2006 void __iomem *ioaddr = tp->mmio_addr;
2007 struct pci_dev *pdev = tp->pci_dev;
2008
2009 if (tp->mac_version == RTL_GIGA_MAC_VER_13) {
2010 pci_write_config_word(pdev, 0x68, 0x00);
2011 pci_write_config_word(pdev, 0x69, 0x08);
2012 }
2013
2014 RTL_W8(Cfg9346, Cfg9346_Unlock);
2015
2016 RTL_W8(EarlyTxThres, EarlyTxThld);
2017
2018 rtl_set_rx_max_size(ioaddr);
2019
2020 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
2021
2022 RTL_W16(CPlusCmd, tp->cp_cmd);
2023
2024 RTL_W16(IntrMitigate, 0x0000);
2025
2026 rtl_set_rx_tx_desc_registers(tp, ioaddr);
2027
2028 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2029 rtl_set_rx_tx_config_registers(tp);
2030
2031 RTL_W8(Cfg9346, Cfg9346_Lock);
2032
2033 RTL_R8(IntrMask);
2034
2035 RTL_W32(RxMissed, 0);
2036
2037 rtl_set_rx_mode(dev);
2038
2039 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2040
2041 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
2042
2043 RTL_W16(IntrMask, tp->intr_event);
1934} 2044}
1935 2045
1936static int rtl8169_change_mtu(struct net_device *dev, int new_mtu) 2046static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
@@ -1956,7 +2066,7 @@ static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
1956 2066
1957 netif_poll_enable(dev); 2067 netif_poll_enable(dev);
1958 2068
1959 rtl8169_hw_start(dev); 2069 rtl_hw_start(dev);
1960 2070
1961 rtl8169_request_timer(dev); 2071 rtl8169_request_timer(dev);
1962 2072
@@ -1997,38 +2107,38 @@ static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
1997 rtl8169_mark_to_asic(desc, rx_buf_sz); 2107 rtl8169_mark_to_asic(desc, rx_buf_sz);
1998} 2108}
1999 2109
2000static int rtl8169_alloc_rx_skb(struct pci_dev *pdev, struct sk_buff **sk_buff, 2110static struct sk_buff *rtl8169_alloc_rx_skb(struct pci_dev *pdev,
2001 struct RxDesc *desc, int rx_buf_sz, 2111 struct net_device *dev,
2002 unsigned int align) 2112 struct RxDesc *desc, int rx_buf_sz,
2113 unsigned int align)
2003{ 2114{
2004 struct sk_buff *skb; 2115 struct sk_buff *skb;
2005 dma_addr_t mapping; 2116 dma_addr_t mapping;
2006 int ret = 0; 2117 unsigned int pad;
2007 2118
2008 skb = dev_alloc_skb(rx_buf_sz + align); 2119 pad = align ? align : NET_IP_ALIGN;
2120
2121 skb = netdev_alloc_skb(dev, rx_buf_sz + pad);
2009 if (!skb) 2122 if (!skb)
2010 goto err_out; 2123 goto err_out;
2011 2124
2012 skb_reserve(skb, (align - 1) & (unsigned long)skb->data); 2125 skb_reserve(skb, align ? ((pad - 1) & (unsigned long)skb->data) : pad);
2013 *sk_buff = skb;
2014 2126
2015 mapping = pci_map_single(pdev, skb->data, rx_buf_sz, 2127 mapping = pci_map_single(pdev, skb->data, rx_buf_sz,
2016 PCI_DMA_FROMDEVICE); 2128 PCI_DMA_FROMDEVICE);
2017 2129
2018 rtl8169_map_to_asic(desc, mapping, rx_buf_sz); 2130 rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
2019
2020out: 2131out:
2021 return ret; 2132 return skb;
2022 2133
2023err_out: 2134err_out:
2024 ret = -ENOMEM;
2025 rtl8169_make_unusable_by_asic(desc); 2135 rtl8169_make_unusable_by_asic(desc);
2026 goto out; 2136 goto out;
2027} 2137}
2028 2138
2029static void rtl8169_rx_clear(struct rtl8169_private *tp) 2139static void rtl8169_rx_clear(struct rtl8169_private *tp)
2030{ 2140{
2031 int i; 2141 unsigned int i;
2032 2142
2033 for (i = 0; i < NUM_RX_DESC; i++) { 2143 for (i = 0; i < NUM_RX_DESC; i++) {
2034 if (tp->Rx_skbuff[i]) { 2144 if (tp->Rx_skbuff[i]) {
@@ -2043,16 +2153,22 @@ static u32 rtl8169_rx_fill(struct rtl8169_private *tp, struct net_device *dev,
2043{ 2153{
2044 u32 cur; 2154 u32 cur;
2045 2155
2046 for (cur = start; end - cur > 0; cur++) { 2156 for (cur = start; end - cur != 0; cur++) {
2047 int ret, i = cur % NUM_RX_DESC; 2157 struct sk_buff *skb;
2158 unsigned int i = cur % NUM_RX_DESC;
2159
2160 WARN_ON((s32)(end - cur) < 0);
2048 2161
2049 if (tp->Rx_skbuff[i]) 2162 if (tp->Rx_skbuff[i])
2050 continue; 2163 continue;
2051 2164
2052 ret = rtl8169_alloc_rx_skb(tp->pci_dev, tp->Rx_skbuff + i, 2165 skb = rtl8169_alloc_rx_skb(tp->pci_dev, dev,
2053 tp->RxDescArray + i, tp->rx_buf_sz, tp->align); 2166 tp->RxDescArray + i,
2054 if (ret < 0) 2167 tp->rx_buf_sz, tp->align);
2168 if (!skb)
2055 break; 2169 break;
2170
2171 tp->Rx_skbuff[i] = skb;
2056 } 2172 }
2057 return cur - start; 2173 return cur - start;
2058} 2174}
@@ -2164,14 +2280,9 @@ static void rtl8169_reinit_task(struct work_struct *work)
2164 2280
2165 ret = rtl8169_open(dev); 2281 ret = rtl8169_open(dev);
2166 if (unlikely(ret < 0)) { 2282 if (unlikely(ret < 0)) {
2167 if (net_ratelimit()) { 2283 if (net_ratelimit() && netif_msg_drv(tp)) {
2168 struct rtl8169_private *tp = netdev_priv(dev); 2284 printk(PFX KERN_ERR "%s: reinit failure (status = %d)."
2169 2285 " Rescheduling.\n", dev->name, ret);
2170 if (netif_msg_drv(tp)) {
2171 printk(PFX KERN_ERR
2172 "%s: reinit failure (status = %d)."
2173 " Rescheduling.\n", dev->name, ret);
2174 }
2175 } 2286 }
2176 rtl8169_schedule_work(dev, rtl8169_reinit_task); 2287 rtl8169_schedule_work(dev, rtl8169_reinit_task);
2177 } 2288 }
@@ -2198,16 +2309,12 @@ static void rtl8169_reset_task(struct work_struct *work)
2198 2309
2199 if (tp->dirty_rx == tp->cur_rx) { 2310 if (tp->dirty_rx == tp->cur_rx) {
2200 rtl8169_init_ring_indexes(tp); 2311 rtl8169_init_ring_indexes(tp);
2201 rtl8169_hw_start(dev); 2312 rtl_hw_start(dev);
2202 netif_wake_queue(dev); 2313 netif_wake_queue(dev);
2203 } else { 2314 } else {
2204 if (net_ratelimit()) { 2315 if (net_ratelimit() && netif_msg_intr(tp)) {
2205 struct rtl8169_private *tp = netdev_priv(dev); 2316 printk(PFX KERN_EMERG "%s: Rx buffers shortage\n",
2206 2317 dev->name);
2207 if (netif_msg_intr(tp)) {
2208 printk(PFX KERN_EMERG
2209 "%s: Rx buffers shortage\n", dev->name);
2210 }
2211 } 2318 }
2212 rtl8169_schedule_work(dev, rtl8169_reset_task); 2319 rtl8169_schedule_work(dev, rtl8169_reset_task);
2213 } 2320 }
@@ -2344,7 +2451,7 @@ static int rtl8169_start_xmit(struct sk_buff *skb, struct net_device *dev)
2344 2451
2345 smp_wmb(); 2452 smp_wmb();
2346 2453
2347 RTL_W8(TxPoll, 0x40); /* set polling bit */ 2454 RTL_W8(TxPoll, NPQ); /* set polling bit */
2348 2455
2349 if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) { 2456 if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) {
2350 netif_stop_queue(dev); 2457 netif_stop_queue(dev);
@@ -2414,16 +2521,12 @@ static void rtl8169_pcierr_interrupt(struct net_device *dev)
2414 rtl8169_schedule_work(dev, rtl8169_reinit_task); 2521 rtl8169_schedule_work(dev, rtl8169_reinit_task);
2415} 2522}
2416 2523
2417static void 2524static void rtl8169_tx_interrupt(struct net_device *dev,
2418rtl8169_tx_interrupt(struct net_device *dev, struct rtl8169_private *tp, 2525 struct rtl8169_private *tp,
2419 void __iomem *ioaddr) 2526 void __iomem *ioaddr)
2420{ 2527{
2421 unsigned int dirty_tx, tx_left; 2528 unsigned int dirty_tx, tx_left;
2422 2529
2423 assert(dev != NULL);
2424 assert(tp != NULL);
2425 assert(ioaddr != NULL);
2426
2427 dirty_tx = tp->dirty_tx; 2530 dirty_tx = tp->dirty_tx;
2428 smp_rmb(); 2531 smp_rmb();
2429 tx_left = tp->cur_tx - dirty_tx; 2532 tx_left = tp->cur_tx - dirty_tx;
@@ -2480,38 +2583,37 @@ static inline void rtl8169_rx_csum(struct sk_buff *skb, struct RxDesc *desc)
2480 skb->ip_summed = CHECKSUM_NONE; 2583 skb->ip_summed = CHECKSUM_NONE;
2481} 2584}
2482 2585
2483static inline int rtl8169_try_rx_copy(struct sk_buff **sk_buff, int pkt_size, 2586static inline bool rtl8169_try_rx_copy(struct sk_buff **sk_buff,
2484 struct RxDesc *desc, int rx_buf_sz, 2587 struct rtl8169_private *tp, int pkt_size,
2485 unsigned int align) 2588 dma_addr_t addr)
2486{ 2589{
2487 int ret = -1; 2590 struct sk_buff *skb;
2591 bool done = false;
2488 2592
2489 if (pkt_size < rx_copybreak) { 2593 if (pkt_size >= rx_copybreak)
2490 struct sk_buff *skb; 2594 goto out;
2491 2595
2492 skb = dev_alloc_skb(pkt_size + align); 2596 skb = netdev_alloc_skb(tp->dev, pkt_size + NET_IP_ALIGN);
2493 if (skb) { 2597 if (!skb)
2494 skb_reserve(skb, (align - 1) & (unsigned long)skb->data); 2598 goto out;
2495 eth_copy_and_sum(skb, sk_buff[0]->data, pkt_size, 0); 2599
2496 *sk_buff = skb; 2600 pci_dma_sync_single_for_cpu(tp->pci_dev, addr, pkt_size,
2497 rtl8169_mark_to_asic(desc, rx_buf_sz); 2601 PCI_DMA_FROMDEVICE);
2498 ret = 0; 2602 skb_reserve(skb, NET_IP_ALIGN);
2499 } 2603 skb_copy_from_linear_data(*sk_buff, skb->data, pkt_size);
2500 } 2604 *sk_buff = skb;
2501 return ret; 2605 done = true;
2606out:
2607 return done;
2502} 2608}
2503 2609
2504static int 2610static int rtl8169_rx_interrupt(struct net_device *dev,
2505rtl8169_rx_interrupt(struct net_device *dev, struct rtl8169_private *tp, 2611 struct rtl8169_private *tp,
2506 void __iomem *ioaddr) 2612 void __iomem *ioaddr)
2507{ 2613{
2508 unsigned int cur_rx, rx_left; 2614 unsigned int cur_rx, rx_left;
2509 unsigned int delta, count; 2615 unsigned int delta, count;
2510 2616
2511 assert(dev != NULL);
2512 assert(tp != NULL);
2513 assert(ioaddr != NULL);
2514
2515 cur_rx = tp->cur_rx; 2617 cur_rx = tp->cur_rx;
2516 rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx; 2618 rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
2517 rx_left = rtl8169_rx_quota(rx_left, (u32) dev->quota); 2619 rx_left = rtl8169_rx_quota(rx_left, (u32) dev->quota);
@@ -2544,9 +2646,9 @@ rtl8169_rx_interrupt(struct net_device *dev, struct rtl8169_private *tp,
2544 rtl8169_mark_to_asic(desc, tp->rx_buf_sz); 2646 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
2545 } else { 2647 } else {
2546 struct sk_buff *skb = tp->Rx_skbuff[entry]; 2648 struct sk_buff *skb = tp->Rx_skbuff[entry];
2649 dma_addr_t addr = le64_to_cpu(desc->addr);
2547 int pkt_size = (status & 0x00001FFF) - 4; 2650 int pkt_size = (status & 0x00001FFF) - 4;
2548 void (*pci_action)(struct pci_dev *, dma_addr_t, 2651 struct pci_dev *pdev = tp->pci_dev;
2549 size_t, int) = pci_dma_sync_single_for_device;
2550 2652
2551 /* 2653 /*
2552 * The driver does not support incoming fragmented 2654 * The driver does not support incoming fragmented
@@ -2562,19 +2664,16 @@ rtl8169_rx_interrupt(struct net_device *dev, struct rtl8169_private *tp,
2562 2664
2563 rtl8169_rx_csum(skb, desc); 2665 rtl8169_rx_csum(skb, desc);
2564 2666
2565 pci_dma_sync_single_for_cpu(tp->pci_dev, 2667 if (rtl8169_try_rx_copy(&skb, tp, pkt_size, addr)) {
2566 le64_to_cpu(desc->addr), tp->rx_buf_sz, 2668 pci_dma_sync_single_for_device(pdev, addr,
2567 PCI_DMA_FROMDEVICE); 2669 pkt_size, PCI_DMA_FROMDEVICE);
2568 2670 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
2569 if (rtl8169_try_rx_copy(&skb, pkt_size, desc, 2671 } else {
2570 tp->rx_buf_sz, tp->align)) { 2672 pci_unmap_single(pdev, addr, pkt_size,
2571 pci_action = pci_unmap_single; 2673 PCI_DMA_FROMDEVICE);
2572 tp->Rx_skbuff[entry] = NULL; 2674 tp->Rx_skbuff[entry] = NULL;
2573 } 2675 }
2574 2676
2575 pci_action(tp->pci_dev, le64_to_cpu(desc->addr),
2576 tp->rx_buf_sz, PCI_DMA_FROMDEVICE);
2577
2578 skb_put(skb, pkt_size); 2677 skb_put(skb, pkt_size);
2579 skb->protocol = eth_type_trans(skb, dev); 2678 skb->protocol = eth_type_trans(skb, dev);
2580 2679
@@ -2585,6 +2684,13 @@ rtl8169_rx_interrupt(struct net_device *dev, struct rtl8169_private *tp,
2585 tp->stats.rx_bytes += pkt_size; 2684 tp->stats.rx_bytes += pkt_size;
2586 tp->stats.rx_packets++; 2685 tp->stats.rx_packets++;
2587 } 2686 }
2687
2688 /* Work around for AMD plateform. */
2689 if ((desc->opts2 & 0xfffe000) &&
2690 (tp->mac_version == RTL_GIGA_MAC_VER_05)) {
2691 desc->opts2 = 0;
2692 cur_rx++;
2693 }
2588 } 2694 }
2589 2695
2590 count = cur_rx - tp->cur_rx; 2696 count = cur_rx - tp->cur_rx;
@@ -2608,11 +2714,9 @@ rtl8169_rx_interrupt(struct net_device *dev, struct rtl8169_private *tp,
2608 return count; 2714 return count;
2609} 2715}
2610 2716
2611/* The interrupt handler does all of the Rx thread work and cleans up after the Tx thread. */ 2717static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
2612static irqreturn_t
2613rtl8169_interrupt(int irq, void *dev_instance)
2614{ 2718{
2615 struct net_device *dev = (struct net_device *) dev_instance; 2719 struct net_device *dev = dev_instance;
2616 struct rtl8169_private *tp = netdev_priv(dev); 2720 struct rtl8169_private *tp = netdev_priv(dev);
2617 int boguscnt = max_interrupt_work; 2721 int boguscnt = max_interrupt_work;
2618 void __iomem *ioaddr = tp->mmio_addr; 2722 void __iomem *ioaddr = tp->mmio_addr;
@@ -2637,9 +2741,17 @@ rtl8169_interrupt(int irq, void *dev_instance)
2637 RTL_W16(IntrStatus, 2741 RTL_W16(IntrStatus,
2638 (status & RxFIFOOver) ? (status | RxOverflow) : status); 2742 (status & RxFIFOOver) ? (status | RxOverflow) : status);
2639 2743
2640 if (!(status & rtl8169_intr_mask)) 2744 if (!(status & tp->intr_event))
2641 break; 2745 break;
2642 2746
2747 /* Work around for rx fifo overflow */
2748 if (unlikely(status & RxFIFOOver) &&
2749 (tp->mac_version == RTL_GIGA_MAC_VER_11)) {
2750 netif_stop_queue(dev);
2751 rtl8169_tx_timeout(dev);
2752 break;
2753 }
2754
2643 if (unlikely(status & SYSErr)) { 2755 if (unlikely(status & SYSErr)) {
2644 rtl8169_pcierr_interrupt(dev); 2756 rtl8169_pcierr_interrupt(dev);
2645 break; 2757 break;
@@ -2649,8 +2761,8 @@ rtl8169_interrupt(int irq, void *dev_instance)
2649 rtl8169_check_link_status(dev, tp, ioaddr); 2761 rtl8169_check_link_status(dev, tp, ioaddr);
2650 2762
2651#ifdef CONFIG_R8169_NAPI 2763#ifdef CONFIG_R8169_NAPI
2652 RTL_W16(IntrMask, rtl8169_intr_mask & ~rtl8169_napi_event); 2764 RTL_W16(IntrMask, tp->intr_event & ~tp->napi_event);
2653 tp->intr_mask = ~rtl8169_napi_event; 2765 tp->intr_mask = ~tp->napi_event;
2654 2766
2655 if (likely(netif_rx_schedule_prep(dev))) 2767 if (likely(netif_rx_schedule_prep(dev)))
2656 __netif_rx_schedule(dev); 2768 __netif_rx_schedule(dev);
@@ -2661,9 +2773,9 @@ rtl8169_interrupt(int irq, void *dev_instance)
2661 break; 2773 break;
2662#else 2774#else
2663 /* Rx interrupt */ 2775 /* Rx interrupt */
2664 if (status & (RxOK | RxOverflow | RxFIFOOver)) { 2776 if (status & (RxOK | RxOverflow | RxFIFOOver))
2665 rtl8169_rx_interrupt(dev, tp, ioaddr); 2777 rtl8169_rx_interrupt(dev, tp, ioaddr);
2666 } 2778
2667 /* Tx interrupt */ 2779 /* Tx interrupt */
2668 if (status & (TxOK | TxErr)) 2780 if (status & (TxOK | TxErr))
2669 rtl8169_tx_interrupt(dev, tp, ioaddr); 2781 rtl8169_tx_interrupt(dev, tp, ioaddr);
@@ -2707,7 +2819,7 @@ static int rtl8169_poll(struct net_device *dev, int *budget)
2707 * write is safe - FR 2819 * write is safe - FR
2708 */ 2820 */
2709 smp_wmb(); 2821 smp_wmb();
2710 RTL_W16(IntrMask, rtl8169_intr_mask); 2822 RTL_W16(IntrMask, tp->intr_event);
2711 } 2823 }
2712 2824
2713 return (work_done >= work_to_do); 2825 return (work_done >= work_to_do);
@@ -2789,14 +2901,13 @@ static int rtl8169_close(struct net_device *dev)
2789 return 0; 2901 return 0;
2790} 2902}
2791 2903
2792static void 2904static void rtl_set_rx_mode(struct net_device *dev)
2793rtl8169_set_rx_mode(struct net_device *dev)
2794{ 2905{
2795 struct rtl8169_private *tp = netdev_priv(dev); 2906 struct rtl8169_private *tp = netdev_priv(dev);
2796 void __iomem *ioaddr = tp->mmio_addr; 2907 void __iomem *ioaddr = tp->mmio_addr;
2797 unsigned long flags; 2908 unsigned long flags;
2798 u32 mc_filter[2]; /* Multicast hash filter */ 2909 u32 mc_filter[2]; /* Multicast hash filter */
2799 int i, rx_mode; 2910 int rx_mode;
2800 u32 tmp = 0; 2911 u32 tmp = 0;
2801 2912
2802 if (dev->flags & IFF_PROMISC) { 2913 if (dev->flags & IFF_PROMISC) {
@@ -2816,6 +2927,8 @@ rtl8169_set_rx_mode(struct net_device *dev)
2816 mc_filter[1] = mc_filter[0] = 0xffffffff; 2927 mc_filter[1] = mc_filter[0] = 0xffffffff;
2817 } else { 2928 } else {
2818 struct dev_mc_list *mclist; 2929 struct dev_mc_list *mclist;
2930 unsigned int i;
2931
2819 rx_mode = AcceptBroadcast | AcceptMyPhys; 2932 rx_mode = AcceptBroadcast | AcceptMyPhys;
2820 mc_filter[1] = mc_filter[0] = 0; 2933 mc_filter[1] = mc_filter[0] = 0;
2821 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count; 2934 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
@@ -2840,10 +2953,11 @@ rtl8169_set_rx_mode(struct net_device *dev)
2840 mc_filter[1] = 0xffffffff; 2953 mc_filter[1] = 0xffffffff;
2841 } 2954 }
2842 2955
2843 RTL_W32(RxConfig, tmp);
2844 RTL_W32(MAR0 + 0, mc_filter[0]); 2956 RTL_W32(MAR0 + 0, mc_filter[0]);
2845 RTL_W32(MAR0 + 4, mc_filter[1]); 2957 RTL_W32(MAR0 + 4, mc_filter[1]);
2846 2958
2959 RTL_W32(RxConfig, tmp);
2960
2847 spin_unlock_irqrestore(&tp->lock, flags); 2961 spin_unlock_irqrestore(&tp->lock, flags);
2848} 2962}
2849 2963
@@ -2931,14 +3045,12 @@ static struct pci_driver rtl8169_pci_driver = {
2931#endif 3045#endif
2932}; 3046};
2933 3047
2934static int __init 3048static int __init rtl8169_init_module(void)
2935rtl8169_init_module(void)
2936{ 3049{
2937 return pci_register_driver(&rtl8169_pci_driver); 3050 return pci_register_driver(&rtl8169_pci_driver);
2938} 3051}
2939 3052
2940static void __exit 3053static void __exit rtl8169_cleanup_module(void)
2941rtl8169_cleanup_module(void)
2942{ 3054{
2943 pci_unregister_driver(&rtl8169_pci_driver); 3055 pci_unregister_driver(&rtl8169_pci_driver);
2944} 3056}
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-14 23:00:02 -0500