1 files changed, 25 insertions, 17 deletions

diff --git a/drivers/net/ixgbe/ixgbe_type.h b/drivers/net/ixgbe/ixgbe_type.h
index fd3358f5413..013751db5fc 100644
--- a/drivers/net/ixgbe/ixgbe_type.h
+++ b/drivers/net/ixgbe/ixgbe_type.h
@@ -1,7 +1,7 @@
 /*******************************************************************************
 
   Intel 10 Gigabit PCI Express Linux driver
-  Copyright(c) 1999 - 2010 Intel Corporation.
+  Copyright(c) 1999 - 2011 Intel Corporation.
 
   This program is free software; you can redistribute it and/or modify it
   under the terms and conditions of the GNU General Public License,
@@ -91,7 +91,7 @@
 
 /* General Receive Control */
 #define IXGBE_GRC_MNG  0x00000001 /* Manageability Enable */
-#define IXGBE_GRC_APME 0x00000002 /* Advanced Power Management Enable */
+#define IXGBE_GRC_APME 0x00000002 /* APM enabled in EEPROM */
 
 #define IXGBE_VPDDIAG0  0x10204
 #define IXGBE_VPDDIAG1  0x10208
@@ -342,7 +342,7 @@
 /* Wake Up Control */
 #define IXGBE_WUC_PME_EN     0x00000002 /* PME Enable */
 #define IXGBE_WUC_PME_STATUS 0x00000004 /* PME Status */
-#define IXGBE_WUC_ADVD3WUC   0x00000010 /* D3Cold wake up cap. enable*/
+#define IXGBE_WUC_WKEN       0x00000010 /* Enable PE_WAKE_N pin assertion  */
 
 /* Wake Up Filter Control */
 #define IXGBE_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */
@@ -1614,6 +1614,8 @@
 #define IXGBE_ALT_SAN_MAC_ADDR_CAPS_ALTWWN  0x1 /* Alt. WWN base exists */
 
 /* PCI Bus Info */
+#define IXGBE_PCI_DEVICE_STATUS   0xAA
+#define IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING   0x0020
 #define IXGBE_PCI_LINK_STATUS     0xB2
 #define IXGBE_PCI_DEVICE_CONTROL2 0xC8
 #define IXGBE_PCI_LINK_WIDTH      0x3F0
@@ -1680,6 +1682,8 @@
 #define IXGBE_RXCTRL_DMBYPS     0x00000002  /* Descriptor Monitor Bypass */
 #define IXGBE_RXDCTL_ENABLE     0x02000000  /* Enable specific Rx Queue */
 #define IXGBE_RXDCTL_VME        0x40000000  /* VLAN mode enable */
+#define IXGBE_RXDCTL_RLPMLMASK  0x00003FFF  /* Only supported on the X540 */
+#define IXGBE_RXDCTL_RLPML_EN   0x00008000
 
 #define IXGBE_FCTRL_SBP 0x00000002 /* Store Bad Packet */
 #define IXGBE_FCTRL_MPE 0x00000100 /* Multicast Promiscuous Ena*/
@@ -2240,6 +2244,7 @@ enum ixgbe_mac_type {
 
 enum ixgbe_phy_type {
         ixgbe_phy_unknown = 0,
+        ixgbe_phy_none,
         ixgbe_phy_tn,
         ixgbe_phy_aq,
         ixgbe_phy_cu_unknown,
@@ -2328,32 +2333,31 @@ enum ixgbe_bus_type {
 /* PCI bus speeds */
 enum ixgbe_bus_speed {
         ixgbe_bus_speed_unknown = 0,
-        ixgbe_bus_speed_33,
-        ixgbe_bus_speed_66,
-        ixgbe_bus_speed_100,
-        ixgbe_bus_speed_120,
-        ixgbe_bus_speed_133,
-        ixgbe_bus_speed_2500,
-        ixgbe_bus_speed_5000,
+        ixgbe_bus_speed_33      = 33,
+        ixgbe_bus_speed_66      = 66,
+        ixgbe_bus_speed_100     = 100,
+        ixgbe_bus_speed_120     = 120,
+        ixgbe_bus_speed_133     = 133,
+        ixgbe_bus_speed_2500    = 2500,
+        ixgbe_bus_speed_5000    = 5000,
         ixgbe_bus_speed_reserved
 };
 
 /* PCI bus widths */
 enum ixgbe_bus_width {
         ixgbe_bus_width_unknown = 0,
-        ixgbe_bus_width_pcie_x1,
-        ixgbe_bus_width_pcie_x2,
+        ixgbe_bus_width_pcie_x1 = 1,
+        ixgbe_bus_width_pcie_x2 = 2,
         ixgbe_bus_width_pcie_x4 = 4,
         ixgbe_bus_width_pcie_x8 = 8,
-        ixgbe_bus_width_32,
-        ixgbe_bus_width_64,
+        ixgbe_bus_width_32      = 32,
+        ixgbe_bus_width_64      = 64,
         ixgbe_bus_width_reserved
 };
 
 struct ixgbe_addr_filter_info {
         u32 num_mc_addrs;
         u32 rar_used_count;
-        u32 mc_addr_in_rar_count;
         u32 mta_in_use;
         u32 overflow_promisc;
         bool uc_set_promisc;
@@ -2491,6 +2495,8 @@ struct ixgbe_mac_operations {
         s32 (*write_analog_reg8)(struct ixgbe_hw*, u32, u8);
         s32 (*setup_sfp)(struct ixgbe_hw *);
         s32 (*enable_rx_dma)(struct ixgbe_hw *, u32);
+        s32 (*acquire_swfw_sync)(struct ixgbe_hw *, u16);
+        void (*release_swfw_sync)(struct ixgbe_hw *, u16);
 
         /* Link */
         void (*disable_tx_laser)(struct ixgbe_hw *);
@@ -2513,7 +2519,6 @@ struct ixgbe_mac_operations {
         s32 (*set_vmdq)(struct ixgbe_hw *, u32, u32);
         s32 (*clear_vmdq)(struct ixgbe_hw *, u32, u32);
         s32 (*init_rx_addrs)(struct ixgbe_hw *);
-        s32 (*update_uc_addr_list)(struct ixgbe_hw *, struct net_device *);
         s32 (*update_mc_addr_list)(struct ixgbe_hw *, struct net_device *);
         s32 (*enable_mc)(struct ixgbe_hw *);
         s32 (*disable_mc)(struct ixgbe_hw *);
@@ -2554,6 +2559,7 @@ struct ixgbe_eeprom_info {
         u16                             address_bits;
 };
 
+#define IXGBE_FLAGS_DOUBLE_RESET_REQUIRED       0x01
 struct ixgbe_mac_info {
         struct ixgbe_mac_operations     ops;
         enum ixgbe_mac_type             type;
@@ -2564,6 +2570,8 @@ struct ixgbe_mac_info {
         u16                             wwnn_prefix;
         /* prefix for World Wide Port Name (WWPN) */
         u16                             wwpn_prefix;
+#define IXGBE_MAX_MTA                   128
+        u32                             mta_shadow[IXGBE_MAX_MTA];
         s32                             mc_filter_type;
         u32                             mcft_size;
         u32                             vft_size;
@@ -2576,6 +2584,7 @@ struct ixgbe_mac_info {
         u32                             orig_autoc2;
         bool                            orig_link_settings_stored;
         bool                            autotry_restart;
+        u8                              flags;
 };
 
 struct ixgbe_phy_info {
@@ -2682,7 +2691,6 @@ struct ixgbe_info {
 #define IXGBE_ERR_EEPROM_VERSION                -24
 #define IXGBE_ERR_NO_SPACE                      -25
 #define IXGBE_ERR_OVERTEMP                      -26
-#define IXGBE_ERR_RAR_INDEX                     -27
 #define IXGBE_ERR_SFP_SETUP_NOT_COMPLETE        -30
 #define IXGBE_ERR_PBA_SECTION                   -31
 #define IXGBE_ERR_INVALID_ARGUMENT              -32