aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/net/ixgbe/ixgbe_phy.c
diff options
context:
space:
mode:
Diffstat (limited to 'drivers/net/ixgbe/ixgbe_phy.c')
-rw-r--r--drivers/net/ixgbe/ixgbe_phy.c594
1 files changed, 429 insertions, 165 deletions
diff --git a/drivers/net/ixgbe/ixgbe_phy.c b/drivers/net/ixgbe/ixgbe_phy.c
index 8f7123e8fc0..f72f705f618 100644
--- a/drivers/net/ixgbe/ixgbe_phy.c
+++ b/drivers/net/ixgbe/ixgbe_phy.c
@@ -1,7 +1,7 @@
1/******************************************************************************* 1/*******************************************************************************
2 2
3 Intel 10 Gigabit PCI Express Linux driver 3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2010 Intel Corporation. 4 Copyright(c) 1999 - 2011 Intel Corporation.
5 5
6 This program is free software; you can redistribute it and/or modify it 6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License, 7 under the terms and conditions of the GNU General Public License,
@@ -57,6 +57,7 @@ s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw)
57{ 57{
58 s32 status = IXGBE_ERR_PHY_ADDR_INVALID; 58 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
59 u32 phy_addr; 59 u32 phy_addr;
60 u16 ext_ability = 0;
60 61
61 if (hw->phy.type == ixgbe_phy_unknown) { 62 if (hw->phy.type == ixgbe_phy_unknown) {
62 for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) { 63 for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) {
@@ -65,12 +66,29 @@ s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw)
65 ixgbe_get_phy_id(hw); 66 ixgbe_get_phy_id(hw);
66 hw->phy.type = 67 hw->phy.type =
67 ixgbe_get_phy_type_from_id(hw->phy.id); 68 ixgbe_get_phy_type_from_id(hw->phy.id);
69
70 if (hw->phy.type == ixgbe_phy_unknown) {
71 hw->phy.ops.read_reg(hw,
72 MDIO_PMA_EXTABLE,
73 MDIO_MMD_PMAPMD,
74 &ext_ability);
75 if (ext_ability &
76 (MDIO_PMA_EXTABLE_10GBT |
77 MDIO_PMA_EXTABLE_1000BT))
78 hw->phy.type =
79 ixgbe_phy_cu_unknown;
80 else
81 hw->phy.type =
82 ixgbe_phy_generic;
83 }
84
68 status = 0; 85 status = 0;
69 break; 86 break;
70 } 87 }
71 } 88 }
72 /* clear value if nothing found */ 89 /* clear value if nothing found */
73 hw->phy.mdio.prtad = 0; 90 if (status != 0)
91 hw->phy.mdio.prtad = 0;
74 } else { 92 } else {
75 status = 0; 93 status = 0;
76 } 94 }
@@ -138,17 +156,51 @@ static enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id)
138 **/ 156 **/
139s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw) 157s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw)
140{ 158{
159 u32 i;
160 u16 ctrl = 0;
161 s32 status = 0;
162
163 if (hw->phy.type == ixgbe_phy_unknown)
164 status = ixgbe_identify_phy_generic(hw);
165
166 if (status != 0 || hw->phy.type == ixgbe_phy_none)
167 goto out;
168
141 /* Don't reset PHY if it's shut down due to overtemp. */ 169 /* Don't reset PHY if it's shut down due to overtemp. */
142 if (!hw->phy.reset_if_overtemp && 170 if (!hw->phy.reset_if_overtemp &&
143 (IXGBE_ERR_OVERTEMP == hw->phy.ops.check_overtemp(hw))) 171 (IXGBE_ERR_OVERTEMP == hw->phy.ops.check_overtemp(hw)))
144 return 0; 172 goto out;
145 173
146 /* 174 /*
147 * Perform soft PHY reset to the PHY_XS. 175 * Perform soft PHY reset to the PHY_XS.
148 * This will cause a soft reset to the PHY 176 * This will cause a soft reset to the PHY
149 */ 177 */
150 return hw->phy.ops.write_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS, 178 hw->phy.ops.write_reg(hw, MDIO_CTRL1,
151 MDIO_CTRL1_RESET); 179 MDIO_MMD_PHYXS,
180 MDIO_CTRL1_RESET);
181
182 /*
183 * Poll for reset bit to self-clear indicating reset is complete.
184 * Some PHYs could take up to 3 seconds to complete and need about
185 * 1.7 usec delay after the reset is complete.
186 */
187 for (i = 0; i < 30; i++) {
188 msleep(100);
189 hw->phy.ops.read_reg(hw, MDIO_CTRL1,
190 MDIO_MMD_PHYXS, &ctrl);
191 if (!(ctrl & MDIO_CTRL1_RESET)) {
192 udelay(2);
193 break;
194 }
195 }
196
197 if (ctrl & MDIO_CTRL1_RESET) {
198 status = IXGBE_ERR_RESET_FAILED;
199 hw_dbg(hw, "PHY reset polling failed to complete.\n");
200 }
201
202out:
203 return status;
152} 204}
153 205
154/** 206/**
@@ -171,7 +223,7 @@ s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
171 else 223 else
172 gssr = IXGBE_GSSR_PHY0_SM; 224 gssr = IXGBE_GSSR_PHY0_SM;
173 225
174 if (ixgbe_acquire_swfw_sync(hw, gssr) != 0) 226 if (hw->mac.ops.acquire_swfw_sync(hw, gssr) != 0)
175 status = IXGBE_ERR_SWFW_SYNC; 227 status = IXGBE_ERR_SWFW_SYNC;
176 228
177 if (status == 0) { 229 if (status == 0) {
@@ -243,7 +295,7 @@ s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
243 } 295 }
244 } 296 }
245 297
246 ixgbe_release_swfw_sync(hw, gssr); 298 hw->mac.ops.release_swfw_sync(hw, gssr);
247 } 299 }
248 300
249 return status; 301 return status;
@@ -269,7 +321,7 @@ s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
269 else 321 else
270 gssr = IXGBE_GSSR_PHY0_SM; 322 gssr = IXGBE_GSSR_PHY0_SM;
271 323
272 if (ixgbe_acquire_swfw_sync(hw, gssr) != 0) 324 if (hw->mac.ops.acquire_swfw_sync(hw, gssr) != 0)
273 status = IXGBE_ERR_SWFW_SYNC; 325 status = IXGBE_ERR_SWFW_SYNC;
274 326
275 if (status == 0) { 327 if (status == 0) {
@@ -336,7 +388,7 @@ s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
336 } 388 }
337 } 389 }
338 390
339 ixgbe_release_swfw_sync(hw, gssr); 391 hw->mac.ops.release_swfw_sync(hw, gssr);
340 } 392 }
341 393
342 return status; 394 return status;
@@ -350,49 +402,89 @@ s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
350 **/ 402 **/
351s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw) 403s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw)
352{ 404{
353 s32 status = IXGBE_NOT_IMPLEMENTED; 405 s32 status = 0;
354 u32 time_out; 406 u32 time_out;
355 u32 max_time_out = 10; 407 u32 max_time_out = 10;
356 u16 autoneg_reg; 408 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
409 bool autoneg = false;
410 ixgbe_link_speed speed;
357 411
358 /* 412 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
359 * Set advertisement settings in PHY based on autoneg_advertised 413
360 * settings. If autoneg_advertised = 0, then advertise default values 414 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
361 * tnx devices cannot be "forced" to a autoneg 10G and fail. But can 415 /* Set or unset auto-negotiation 10G advertisement */
362 * for a 1G. 416 hw->phy.ops.read_reg(hw, MDIO_AN_10GBT_CTRL,
363 */ 417 MDIO_MMD_AN,
364 hw->phy.ops.read_reg(hw, MDIO_AN_ADVERTISE, MDIO_MMD_AN, &autoneg_reg); 418 &autoneg_reg);
365 419
366 if (hw->phy.autoneg_advertised == IXGBE_LINK_SPEED_1GB_FULL)
367 autoneg_reg &= ~MDIO_AN_10GBT_CTRL_ADV10G; 420 autoneg_reg &= ~MDIO_AN_10GBT_CTRL_ADV10G;
368 else 421 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
369 autoneg_reg |= MDIO_AN_10GBT_CTRL_ADV10G; 422 autoneg_reg |= MDIO_AN_10GBT_CTRL_ADV10G;
423
424 hw->phy.ops.write_reg(hw, MDIO_AN_10GBT_CTRL,
425 MDIO_MMD_AN,
426 autoneg_reg);
427 }
428
429 if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
430 /* Set or unset auto-negotiation 1G advertisement */
431 hw->phy.ops.read_reg(hw,
432 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
433 MDIO_MMD_AN,
434 &autoneg_reg);
435
436 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE;
437 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
438 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE;
439
440 hw->phy.ops.write_reg(hw,
441 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
442 MDIO_MMD_AN,
443 autoneg_reg);
444 }
445
446 if (speed & IXGBE_LINK_SPEED_100_FULL) {
447 /* Set or unset auto-negotiation 100M advertisement */
448 hw->phy.ops.read_reg(hw, MDIO_AN_ADVERTISE,
449 MDIO_MMD_AN,
450 &autoneg_reg);
370 451
371 hw->phy.ops.write_reg(hw, MDIO_AN_ADVERTISE, MDIO_MMD_AN, autoneg_reg); 452 autoneg_reg &= ~ADVERTISE_100FULL;
453 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
454 autoneg_reg |= ADVERTISE_100FULL;
455
456 hw->phy.ops.write_reg(hw, MDIO_AN_ADVERTISE,
457 MDIO_MMD_AN,
458 autoneg_reg);
459 }
372 460
373 /* Restart PHY autonegotiation and wait for completion */ 461 /* Restart PHY autonegotiation and wait for completion */
374 hw->phy.ops.read_reg(hw, MDIO_CTRL1, MDIO_MMD_AN, &autoneg_reg); 462 hw->phy.ops.read_reg(hw, MDIO_CTRL1,
463 MDIO_MMD_AN, &autoneg_reg);
375 464
376 autoneg_reg |= MDIO_AN_CTRL1_RESTART; 465 autoneg_reg |= MDIO_AN_CTRL1_RESTART;
377 466
378 hw->phy.ops.write_reg(hw, MDIO_CTRL1, MDIO_MMD_AN, autoneg_reg); 467 hw->phy.ops.write_reg(hw, MDIO_CTRL1,
468 MDIO_MMD_AN, autoneg_reg);
379 469
380 /* Wait for autonegotiation to finish */ 470 /* Wait for autonegotiation to finish */
381 for (time_out = 0; time_out < max_time_out; time_out++) { 471 for (time_out = 0; time_out < max_time_out; time_out++) {
382 udelay(10); 472 udelay(10);
383 /* Restart PHY autonegotiation and wait for completion */ 473 /* Restart PHY autonegotiation and wait for completion */
384 status = hw->phy.ops.read_reg(hw, MDIO_STAT1, MDIO_MMD_AN, 474 status = hw->phy.ops.read_reg(hw, MDIO_STAT1,
385 &autoneg_reg); 475 MDIO_MMD_AN,
476 &autoneg_reg);
386 477
387 autoneg_reg &= MDIO_AN_STAT1_COMPLETE; 478 autoneg_reg &= MDIO_AN_STAT1_COMPLETE;
388 if (autoneg_reg == MDIO_AN_STAT1_COMPLETE) { 479 if (autoneg_reg == MDIO_AN_STAT1_COMPLETE) {
389 status = 0;
390 break; 480 break;
391 } 481 }
392 } 482 }
393 483
394 if (time_out == max_time_out) 484 if (time_out == max_time_out) {
395 status = IXGBE_ERR_LINK_SETUP; 485 status = IXGBE_ERR_LINK_SETUP;
486 hw_dbg(hw, "ixgbe_setup_phy_link_generic: time out");
487 }
396 488
397 return status; 489 return status;
398} 490}
@@ -421,6 +513,9 @@ s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,
421 if (speed & IXGBE_LINK_SPEED_1GB_FULL) 513 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
422 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL; 514 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
423 515
516 if (speed & IXGBE_LINK_SPEED_100_FULL)
517 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL;
518
424 /* Setup link based on the new speed settings */ 519 /* Setup link based on the new speed settings */
425 hw->phy.ops.setup_link(hw); 520 hw->phy.ops.setup_link(hw);
426 521
@@ -461,6 +556,180 @@ s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw,
461} 556}
462 557
463/** 558/**
559 * ixgbe_check_phy_link_tnx - Determine link and speed status
560 * @hw: pointer to hardware structure
561 *
562 * Reads the VS1 register to determine if link is up and the current speed for
563 * the PHY.
564 **/
565s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
566 bool *link_up)
567{
568 s32 status = 0;
569 u32 time_out;
570 u32 max_time_out = 10;
571 u16 phy_link = 0;
572 u16 phy_speed = 0;
573 u16 phy_data = 0;
574
575 /* Initialize speed and link to default case */
576 *link_up = false;
577 *speed = IXGBE_LINK_SPEED_10GB_FULL;
578
579 /*
580 * Check current speed and link status of the PHY register.
581 * This is a vendor specific register and may have to
582 * be changed for other copper PHYs.
583 */
584 for (time_out = 0; time_out < max_time_out; time_out++) {
585 udelay(10);
586 status = hw->phy.ops.read_reg(hw,
587 MDIO_STAT1,
588 MDIO_MMD_VEND1,
589 &phy_data);
590 phy_link = phy_data &
591 IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS;
592 phy_speed = phy_data &
593 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS;
594 if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) {
595 *link_up = true;
596 if (phy_speed ==
597 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS)
598 *speed = IXGBE_LINK_SPEED_1GB_FULL;
599 break;
600 }
601 }
602
603 return status;
604}
605
606/**
607 * ixgbe_setup_phy_link_tnx - Set and restart autoneg
608 * @hw: pointer to hardware structure
609 *
610 * Restart autonegotiation and PHY and waits for completion.
611 **/
612s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw)
613{
614 s32 status = 0;
615 u32 time_out;
616 u32 max_time_out = 10;
617 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
618 bool autoneg = false;
619 ixgbe_link_speed speed;
620
621 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
622
623 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
624 /* Set or unset auto-negotiation 10G advertisement */
625 hw->phy.ops.read_reg(hw, MDIO_AN_10GBT_CTRL,
626 MDIO_MMD_AN,
627 &autoneg_reg);
628
629 autoneg_reg &= ~MDIO_AN_10GBT_CTRL_ADV10G;
630 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
631 autoneg_reg |= MDIO_AN_10GBT_CTRL_ADV10G;
632
633 hw->phy.ops.write_reg(hw, MDIO_AN_10GBT_CTRL,
634 MDIO_MMD_AN,
635 autoneg_reg);
636 }
637
638 if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
639 /* Set or unset auto-negotiation 1G advertisement */
640 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
641 MDIO_MMD_AN,
642 &autoneg_reg);
643
644 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
645 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
646 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
647
648 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
649 MDIO_MMD_AN,
650 autoneg_reg);
651 }
652
653 if (speed & IXGBE_LINK_SPEED_100_FULL) {
654 /* Set or unset auto-negotiation 100M advertisement */
655 hw->phy.ops.read_reg(hw, MDIO_AN_ADVERTISE,
656 MDIO_MMD_AN,
657 &autoneg_reg);
658
659 autoneg_reg &= ~ADVERTISE_100FULL;
660 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
661 autoneg_reg |= ADVERTISE_100FULL;
662
663 hw->phy.ops.write_reg(hw, MDIO_AN_ADVERTISE,
664 MDIO_MMD_AN,
665 autoneg_reg);
666 }
667
668 /* Restart PHY autonegotiation and wait for completion */
669 hw->phy.ops.read_reg(hw, MDIO_CTRL1,
670 MDIO_MMD_AN, &autoneg_reg);
671
672 autoneg_reg |= MDIO_AN_CTRL1_RESTART;
673
674 hw->phy.ops.write_reg(hw, MDIO_CTRL1,
675 MDIO_MMD_AN, autoneg_reg);
676
677 /* Wait for autonegotiation to finish */
678 for (time_out = 0; time_out < max_time_out; time_out++) {
679 udelay(10);
680 /* Restart PHY autonegotiation and wait for completion */
681 status = hw->phy.ops.read_reg(hw, MDIO_STAT1,
682 MDIO_MMD_AN,
683 &autoneg_reg);
684
685 autoneg_reg &= MDIO_AN_STAT1_COMPLETE;
686 if (autoneg_reg == MDIO_AN_STAT1_COMPLETE)
687 break;
688 }
689
690 if (time_out == max_time_out) {
691 status = IXGBE_ERR_LINK_SETUP;
692 hw_dbg(hw, "ixgbe_setup_phy_link_tnx: time out");
693 }
694
695 return status;
696}
697
698/**
699 * ixgbe_get_phy_firmware_version_tnx - Gets the PHY Firmware Version
700 * @hw: pointer to hardware structure
701 * @firmware_version: pointer to the PHY Firmware Version
702 **/
703s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw,
704 u16 *firmware_version)
705{
706 s32 status = 0;
707
708 status = hw->phy.ops.read_reg(hw, TNX_FW_REV,
709 MDIO_MMD_VEND1,
710 firmware_version);
711
712 return status;
713}
714
715/**
716 * ixgbe_get_phy_firmware_version_generic - Gets the PHY Firmware Version
717 * @hw: pointer to hardware structure
718 * @firmware_version: pointer to the PHY Firmware Version
719 **/
720s32 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw,
721 u16 *firmware_version)
722{
723 s32 status = 0;
724
725 status = hw->phy.ops.read_reg(hw, AQ_FW_REV,
726 MDIO_MMD_VEND1,
727 firmware_version);
728
729 return status;
730}
731
732/**
464 * ixgbe_reset_phy_nl - Performs a PHY reset 733 * ixgbe_reset_phy_nl - Performs a PHY reset
465 * @hw: pointer to hardware structure 734 * @hw: pointer to hardware structure
466 **/ 735 **/
@@ -556,11 +825,10 @@ out:
556} 825}
557 826
558/** 827/**
559 * ixgbe_identify_sfp_module_generic - Identifies SFP module and assigns 828 * ixgbe_identify_sfp_module_generic - Identifies SFP modules
560 * the PHY type.
561 * @hw: pointer to hardware structure 829 * @hw: pointer to hardware structure
562 * 830 *
563 * Searches for and indentifies the SFP module. Assings appropriate PHY type. 831 * Searches for and identifies the SFP module and assigns appropriate PHY type.
564 **/ 832 **/
565s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw) 833s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)
566{ 834{
@@ -581,41 +849,62 @@ s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)
581 goto out; 849 goto out;
582 } 850 }
583 851
584 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_IDENTIFIER, 852 status = hw->phy.ops.read_i2c_eeprom(hw,
853 IXGBE_SFF_IDENTIFIER,
585 &identifier); 854 &identifier);
586 855
587 if (status == IXGBE_ERR_SFP_NOT_PRESENT || status == IXGBE_ERR_I2C) { 856 if (status == IXGBE_ERR_SWFW_SYNC ||
588 status = IXGBE_ERR_SFP_NOT_PRESENT; 857 status == IXGBE_ERR_I2C ||
589 hw->phy.sfp_type = ixgbe_sfp_type_not_present; 858 status == IXGBE_ERR_SFP_NOT_PRESENT)
590 if (hw->phy.type != ixgbe_phy_nl) { 859 goto err_read_i2c_eeprom;
591 hw->phy.id = 0;
592 hw->phy.type = ixgbe_phy_unknown;
593 }
594 goto out;
595 }
596 860
597 if (identifier == IXGBE_SFF_IDENTIFIER_SFP) { 861 /* LAN ID is needed for sfp_type determination */
598 hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_1GBE_COMP_CODES, 862 hw->mac.ops.set_lan_id(hw);
599 &comp_codes_1g); 863
600 hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_10GBE_COMP_CODES, 864 if (identifier != IXGBE_SFF_IDENTIFIER_SFP) {
601 &comp_codes_10g); 865 hw->phy.type = ixgbe_phy_sfp_unsupported;
602 hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_CABLE_TECHNOLOGY, 866 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
603 &cable_tech); 867 } else {
604 868 status = hw->phy.ops.read_i2c_eeprom(hw,
605 /* ID Module 869 IXGBE_SFF_1GBE_COMP_CODES,
606 * ========= 870 &comp_codes_1g);
607 * 0 SFP_DA_CU 871
608 * 1 SFP_SR 872 if (status == IXGBE_ERR_SWFW_SYNC ||
609 * 2 SFP_LR 873 status == IXGBE_ERR_I2C ||
610 * 3 SFP_DA_CORE0 - 82599-specific 874 status == IXGBE_ERR_SFP_NOT_PRESENT)
611 * 4 SFP_DA_CORE1 - 82599-specific 875 goto err_read_i2c_eeprom;
612 * 5 SFP_SR/LR_CORE0 - 82599-specific 876
613 * 6 SFP_SR/LR_CORE1 - 82599-specific 877 status = hw->phy.ops.read_i2c_eeprom(hw,
614 * 7 SFP_act_lmt_DA_CORE0 - 82599-specific 878 IXGBE_SFF_10GBE_COMP_CODES,
615 * 8 SFP_act_lmt_DA_CORE1 - 82599-specific 879 &comp_codes_10g);
616 * 9 SFP_1g_cu_CORE0 - 82599-specific 880
617 * 10 SFP_1g_cu_CORE1 - 82599-specific 881 if (status == IXGBE_ERR_SWFW_SYNC ||
618 */ 882 status == IXGBE_ERR_I2C ||
883 status == IXGBE_ERR_SFP_NOT_PRESENT)
884 goto err_read_i2c_eeprom;
885 status = hw->phy.ops.read_i2c_eeprom(hw,
886 IXGBE_SFF_CABLE_TECHNOLOGY,
887 &cable_tech);
888
889 if (status == IXGBE_ERR_SWFW_SYNC ||
890 status == IXGBE_ERR_I2C ||
891 status == IXGBE_ERR_SFP_NOT_PRESENT)
892 goto err_read_i2c_eeprom;
893
894 /* ID Module
895 * =========
896 * 0 SFP_DA_CU
897 * 1 SFP_SR
898 * 2 SFP_LR
899 * 3 SFP_DA_CORE0 - 82599-specific
900 * 4 SFP_DA_CORE1 - 82599-specific
901 * 5 SFP_SR/LR_CORE0 - 82599-specific
902 * 6 SFP_SR/LR_CORE1 - 82599-specific
903 * 7 SFP_act_lmt_DA_CORE0 - 82599-specific
904 * 8 SFP_act_lmt_DA_CORE1 - 82599-specific
905 * 9 SFP_1g_cu_CORE0 - 82599-specific
906 * 10 SFP_1g_cu_CORE1 - 82599-specific
907 */
619 if (hw->mac.type == ixgbe_mac_82598EB) { 908 if (hw->mac.type == ixgbe_mac_82598EB) {
620 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) 909 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
621 hw->phy.sfp_type = ixgbe_sfp_type_da_cu; 910 hw->phy.sfp_type = ixgbe_sfp_type_da_cu;
@@ -647,31 +936,27 @@ s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)
647 ixgbe_sfp_type_da_act_lmt_core1; 936 ixgbe_sfp_type_da_act_lmt_core1;
648 } else { 937 } else {
649 hw->phy.sfp_type = 938 hw->phy.sfp_type =
650 ixgbe_sfp_type_unknown; 939 ixgbe_sfp_type_unknown;
651 } 940 }
652 } else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE) 941 } else if (comp_codes_10g &
942 (IXGBE_SFF_10GBASESR_CAPABLE |
943 IXGBE_SFF_10GBASELR_CAPABLE)) {
653 if (hw->bus.lan_id == 0) 944 if (hw->bus.lan_id == 0)
654 hw->phy.sfp_type = 945 hw->phy.sfp_type =
655 ixgbe_sfp_type_srlr_core0; 946 ixgbe_sfp_type_srlr_core0;
656 else 947 else
657 hw->phy.sfp_type = 948 hw->phy.sfp_type =
658 ixgbe_sfp_type_srlr_core1; 949 ixgbe_sfp_type_srlr_core1;
659 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE) 950 } else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) {
660 if (hw->bus.lan_id == 0)
661 hw->phy.sfp_type =
662 ixgbe_sfp_type_srlr_core0;
663 else
664 hw->phy.sfp_type =
665 ixgbe_sfp_type_srlr_core1;
666 else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE)
667 if (hw->bus.lan_id == 0) 951 if (hw->bus.lan_id == 0)
668 hw->phy.sfp_type = 952 hw->phy.sfp_type =
669 ixgbe_sfp_type_1g_cu_core0; 953 ixgbe_sfp_type_1g_cu_core0;
670 else 954 else
671 hw->phy.sfp_type = 955 hw->phy.sfp_type =
672 ixgbe_sfp_type_1g_cu_core1; 956 ixgbe_sfp_type_1g_cu_core1;
673 else 957 } else {
674 hw->phy.sfp_type = ixgbe_sfp_type_unknown; 958 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
959 }
675 } 960 }
676 961
677 if (hw->phy.sfp_type != stored_sfp_type) 962 if (hw->phy.sfp_type != stored_sfp_type)
@@ -688,16 +973,33 @@ s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)
688 /* Determine PHY vendor */ 973 /* Determine PHY vendor */
689 if (hw->phy.type != ixgbe_phy_nl) { 974 if (hw->phy.type != ixgbe_phy_nl) {
690 hw->phy.id = identifier; 975 hw->phy.id = identifier;
691 hw->phy.ops.read_i2c_eeprom(hw, 976 status = hw->phy.ops.read_i2c_eeprom(hw,
692 IXGBE_SFF_VENDOR_OUI_BYTE0, 977 IXGBE_SFF_VENDOR_OUI_BYTE0,
693 &oui_bytes[0]); 978 &oui_bytes[0]);
694 hw->phy.ops.read_i2c_eeprom(hw, 979
980 if (status == IXGBE_ERR_SWFW_SYNC ||
981 status == IXGBE_ERR_I2C ||
982 status == IXGBE_ERR_SFP_NOT_PRESENT)
983 goto err_read_i2c_eeprom;
984
985 status = hw->phy.ops.read_i2c_eeprom(hw,
695 IXGBE_SFF_VENDOR_OUI_BYTE1, 986 IXGBE_SFF_VENDOR_OUI_BYTE1,
696 &oui_bytes[1]); 987 &oui_bytes[1]);
697 hw->phy.ops.read_i2c_eeprom(hw, 988
989 if (status == IXGBE_ERR_SWFW_SYNC ||
990 status == IXGBE_ERR_I2C ||
991 status == IXGBE_ERR_SFP_NOT_PRESENT)
992 goto err_read_i2c_eeprom;
993
994 status = hw->phy.ops.read_i2c_eeprom(hw,
698 IXGBE_SFF_VENDOR_OUI_BYTE2, 995 IXGBE_SFF_VENDOR_OUI_BYTE2,
699 &oui_bytes[2]); 996 &oui_bytes[2]);
700 997
998 if (status == IXGBE_ERR_SWFW_SYNC ||
999 status == IXGBE_ERR_I2C ||
1000 status == IXGBE_ERR_SFP_NOT_PRESENT)
1001 goto err_read_i2c_eeprom;
1002
701 vendor_oui = 1003 vendor_oui =
702 ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) | 1004 ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
703 (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) | 1005 (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
@@ -707,7 +1009,7 @@ s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)
707 case IXGBE_SFF_VENDOR_OUI_TYCO: 1009 case IXGBE_SFF_VENDOR_OUI_TYCO:
708 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) 1010 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
709 hw->phy.type = 1011 hw->phy.type =
710 ixgbe_phy_sfp_passive_tyco; 1012 ixgbe_phy_sfp_passive_tyco;
711 break; 1013 break;
712 case IXGBE_SFF_VENDOR_OUI_FTL: 1014 case IXGBE_SFF_VENDOR_OUI_FTL:
713 if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) 1015 if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
@@ -724,7 +1026,7 @@ s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)
724 default: 1026 default:
725 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) 1027 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
726 hw->phy.type = 1028 hw->phy.type =
727 ixgbe_phy_sfp_passive_unknown; 1029 ixgbe_phy_sfp_passive_unknown;
728 else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) 1030 else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
729 hw->phy.type = 1031 hw->phy.type =
730 ixgbe_phy_sfp_active_unknown; 1032 ixgbe_phy_sfp_active_unknown;
@@ -734,7 +1036,7 @@ s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)
734 } 1036 }
735 } 1037 }
736 1038
737 /* All passive DA cables are supported */ 1039 /* Allow any DA cable vendor */
738 if (cable_tech & (IXGBE_SFF_DA_PASSIVE_CABLE | 1040 if (cable_tech & (IXGBE_SFF_DA_PASSIVE_CABLE |
739 IXGBE_SFF_DA_ACTIVE_CABLE)) { 1041 IXGBE_SFF_DA_ACTIVE_CABLE)) {
740 status = 0; 1042 status = 0;
@@ -756,7 +1058,6 @@ s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)
756 goto out; 1058 goto out;
757 } 1059 }
758 1060
759 /* This is guaranteed to be 82599, no need to check for NULL */
760 hw->mac.ops.get_device_caps(hw, &enforce_sfp); 1061 hw->mac.ops.get_device_caps(hw, &enforce_sfp);
761 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP) && 1062 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP) &&
762 !((hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0) || 1063 !((hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0) ||
@@ -776,15 +1077,24 @@ s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)
776 1077
777out: 1078out:
778 return status; 1079 return status;
1080
1081err_read_i2c_eeprom:
1082 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1083 if (hw->phy.type != ixgbe_phy_nl) {
1084 hw->phy.id = 0;
1085 hw->phy.type = ixgbe_phy_unknown;
1086 }
1087 return IXGBE_ERR_SFP_NOT_PRESENT;
779} 1088}
780 1089
781/** 1090/**
782 * ixgbe_get_sfp_init_sequence_offsets - Checks the MAC's EEPROM to see 1091 * ixgbe_get_sfp_init_sequence_offsets - Provides offset of PHY init sequence
783 * if it supports a given SFP+ module type, if so it returns the offsets to the
784 * phy init sequence block.
785 * @hw: pointer to hardware structure 1092 * @hw: pointer to hardware structure
786 * @list_offset: offset to the SFP ID list 1093 * @list_offset: offset to the SFP ID list
787 * @data_offset: offset to the SFP data block 1094 * @data_offset: offset to the SFP data block
1095 *
1096 * Checks the MAC's EEPROM to see if it supports a given SFP+ module type, if
1097 * so it returns the offsets to the phy init sequence block.
788 **/ 1098 **/
789s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw, 1099s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,
790 u16 *list_offset, 1100 u16 *list_offset,
@@ -899,11 +1209,22 @@ s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
899 u8 dev_addr, u8 *data) 1209 u8 dev_addr, u8 *data)
900{ 1210{
901 s32 status = 0; 1211 s32 status = 0;
902 u32 max_retry = 1; 1212 u32 max_retry = 10;
903 u32 retry = 0; 1213 u32 retry = 0;
1214 u16 swfw_mask = 0;
904 bool nack = 1; 1215 bool nack = 1;
905 1216
1217 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
1218 swfw_mask = IXGBE_GSSR_PHY1_SM;
1219 else
1220 swfw_mask = IXGBE_GSSR_PHY0_SM;
1221
906 do { 1222 do {
1223 if (ixgbe_acquire_swfw_sync(hw, swfw_mask) != 0) {
1224 status = IXGBE_ERR_SWFW_SYNC;
1225 goto read_byte_out;
1226 }
1227
907 ixgbe_i2c_start(hw); 1228 ixgbe_i2c_start(hw);
908 1229
909 /* Device Address and write indication */ 1230 /* Device Address and write indication */
@@ -946,6 +1267,8 @@ s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
946 break; 1267 break;
947 1268
948fail: 1269fail:
1270 ixgbe_release_swfw_sync(hw, swfw_mask);
1271 msleep(100);
949 ixgbe_i2c_bus_clear(hw); 1272 ixgbe_i2c_bus_clear(hw);
950 retry++; 1273 retry++;
951 if (retry < max_retry) 1274 if (retry < max_retry)
@@ -955,6 +1278,9 @@ fail:
955 1278
956 } while (retry < max_retry); 1279 } while (retry < max_retry);
957 1280
1281 ixgbe_release_swfw_sync(hw, swfw_mask);
1282
1283read_byte_out:
958 return status; 1284 return status;
959} 1285}
960 1286
@@ -973,6 +1299,17 @@ s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
973 s32 status = 0; 1299 s32 status = 0;
974 u32 max_retry = 1; 1300 u32 max_retry = 1;
975 u32 retry = 0; 1301 u32 retry = 0;
1302 u16 swfw_mask = 0;
1303
1304 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
1305 swfw_mask = IXGBE_GSSR_PHY1_SM;
1306 else
1307 swfw_mask = IXGBE_GSSR_PHY0_SM;
1308
1309 if (ixgbe_acquire_swfw_sync(hw, swfw_mask) != 0) {
1310 status = IXGBE_ERR_SWFW_SYNC;
1311 goto write_byte_out;
1312 }
976 1313
977 do { 1314 do {
978 ixgbe_i2c_start(hw); 1315 ixgbe_i2c_start(hw);
@@ -1013,6 +1350,9 @@ fail:
1013 hw_dbg(hw, "I2C byte write error.\n"); 1350 hw_dbg(hw, "I2C byte write error.\n");
1014 } while (retry < max_retry); 1351 } while (retry < max_retry);
1015 1352
1353 ixgbe_release_swfw_sync(hw, swfw_mask);
1354
1355write_byte_out:
1016 return status; 1356 return status;
1017} 1357}
1018 1358
@@ -1331,6 +1671,8 @@ static void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw)
1331 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); 1671 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1332 u32 i; 1672 u32 i;
1333 1673
1674 ixgbe_i2c_start(hw);
1675
1334 ixgbe_set_i2c_data(hw, &i2cctl, 1); 1676 ixgbe_set_i2c_data(hw, &i2cctl, 1);
1335 1677
1336 for (i = 0; i < 9; i++) { 1678 for (i = 0; i < 9; i++) {
@@ -1345,91 +1687,13 @@ static void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw)
1345 udelay(IXGBE_I2C_T_LOW); 1687 udelay(IXGBE_I2C_T_LOW);
1346 } 1688 }
1347 1689
1690 ixgbe_i2c_start(hw);
1691
1348 /* Put the i2c bus back to default state */ 1692 /* Put the i2c bus back to default state */
1349 ixgbe_i2c_stop(hw); 1693 ixgbe_i2c_stop(hw);
1350} 1694}
1351 1695
1352/** 1696/**
1353 * ixgbe_check_phy_link_tnx - Determine link and speed status
1354 * @hw: pointer to hardware structure
1355 *
1356 * Reads the VS1 register to determine if link is up and the current speed for
1357 * the PHY.
1358 **/
1359s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
1360 bool *link_up)
1361{
1362 s32 status = 0;
1363 u32 time_out;
1364 u32 max_time_out = 10;
1365 u16 phy_link = 0;
1366 u16 phy_speed = 0;
1367 u16 phy_data = 0;
1368
1369 /* Initialize speed and link to default case */
1370 *link_up = false;
1371 *speed = IXGBE_LINK_SPEED_10GB_FULL;
1372
1373 /*
1374 * Check current speed and link status of the PHY register.
1375 * This is a vendor specific register and may have to
1376 * be changed for other copper PHYs.
1377 */
1378 for (time_out = 0; time_out < max_time_out; time_out++) {
1379 udelay(10);
1380 status = hw->phy.ops.read_reg(hw,
1381 IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS,
1382 MDIO_MMD_VEND1,
1383 &phy_data);
1384 phy_link = phy_data &
1385 IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS;
1386 phy_speed = phy_data &
1387 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS;
1388 if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) {
1389 *link_up = true;
1390 if (phy_speed ==
1391 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS)
1392 *speed = IXGBE_LINK_SPEED_1GB_FULL;
1393 break;
1394 }
1395 }
1396
1397 return status;
1398}
1399
1400/**
1401 * ixgbe_get_phy_firmware_version_tnx - Gets the PHY Firmware Version
1402 * @hw: pointer to hardware structure
1403 * @firmware_version: pointer to the PHY Firmware Version
1404 **/
1405s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw,
1406 u16 *firmware_version)
1407{
1408 s32 status = 0;
1409
1410 status = hw->phy.ops.read_reg(hw, TNX_FW_REV, MDIO_MMD_VEND1,
1411 firmware_version);
1412
1413 return status;
1414}
1415
1416/**
1417 * ixgbe_get_phy_firmware_version_generic - Gets the PHY Firmware Version
1418 * @hw: pointer to hardware structure
1419 * @firmware_version: pointer to the PHY Firmware Version
1420**/
1421s32 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw,
1422 u16 *firmware_version)
1423{
1424 s32 status = 0;
1425
1426 status = hw->phy.ops.read_reg(hw, AQ_FW_REV, MDIO_MMD_VEND1,
1427 firmware_version);
1428
1429 return status;
1430}
1431
1432/**
1433 * ixgbe_tn_check_overtemp - Checks if an overtemp occured. 1697 * ixgbe_tn_check_overtemp - Checks if an overtemp occured.
1434 * @hw: pointer to hardware structure 1698 * @hw: pointer to hardware structure
1435 * 1699 *
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-23 16:34:42 -0400