diff options
Diffstat (limited to 'drivers/net/ethernet/sfc/falcon.c')
-rw-r--r-- | drivers/net/ethernet/sfc/falcon.c | 1875 |
1 files changed, 0 insertions, 1875 deletions
diff --git a/drivers/net/ethernet/sfc/falcon.c b/drivers/net/ethernet/sfc/falcon.c deleted file mode 100644 index 49bcd196e10..00000000000 --- a/drivers/net/ethernet/sfc/falcon.c +++ /dev/null | |||
@@ -1,1875 +0,0 @@ | |||
1 | /**************************************************************************** | ||
2 | * Driver for Solarflare Solarstorm network controllers and boards | ||
3 | * Copyright 2005-2006 Fen Systems Ltd. | ||
4 | * Copyright 2006-2010 Solarflare Communications Inc. | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify it | ||
7 | * under the terms of the GNU General Public License version 2 as published | ||
8 | * by the Free Software Foundation, incorporated herein by reference. | ||
9 | */ | ||
10 | |||
11 | #include <linux/bitops.h> | ||
12 | #include <linux/delay.h> | ||
13 | #include <linux/pci.h> | ||
14 | #include <linux/module.h> | ||
15 | #include <linux/seq_file.h> | ||
16 | #include <linux/i2c.h> | ||
17 | #include <linux/mii.h> | ||
18 | #include <linux/slab.h> | ||
19 | #include "net_driver.h" | ||
20 | #include "bitfield.h" | ||
21 | #include "efx.h" | ||
22 | #include "spi.h" | ||
23 | #include "nic.h" | ||
24 | #include "regs.h" | ||
25 | #include "io.h" | ||
26 | #include "phy.h" | ||
27 | #include "workarounds.h" | ||
28 | #include "selftest.h" | ||
29 | |||
30 | /* Hardware control for SFC4000 (aka Falcon). */ | ||
31 | |||
32 | static int falcon_reset_hw(struct efx_nic *efx, enum reset_type method); | ||
33 | |||
34 | static const unsigned int | ||
35 | /* "Large" EEPROM device: Atmel AT25640 or similar | ||
36 | * 8 KB, 16-bit address, 32 B write block */ | ||
37 | large_eeprom_type = ((13 << SPI_DEV_TYPE_SIZE_LBN) | ||
38 | | (2 << SPI_DEV_TYPE_ADDR_LEN_LBN) | ||
39 | | (5 << SPI_DEV_TYPE_BLOCK_SIZE_LBN)), | ||
40 | /* Default flash device: Atmel AT25F1024 | ||
41 | * 128 KB, 24-bit address, 32 KB erase block, 256 B write block */ | ||
42 | default_flash_type = ((17 << SPI_DEV_TYPE_SIZE_LBN) | ||
43 | | (3 << SPI_DEV_TYPE_ADDR_LEN_LBN) | ||
44 | | (0x52 << SPI_DEV_TYPE_ERASE_CMD_LBN) | ||
45 | | (15 << SPI_DEV_TYPE_ERASE_SIZE_LBN) | ||
46 | | (8 << SPI_DEV_TYPE_BLOCK_SIZE_LBN)); | ||
47 | |||
48 | /************************************************************************** | ||
49 | * | ||
50 | * I2C bus - this is a bit-bashing interface using GPIO pins | ||
51 | * Note that it uses the output enables to tristate the outputs | ||
52 | * SDA is the data pin and SCL is the clock | ||
53 | * | ||
54 | ************************************************************************** | ||
55 | */ | ||
56 | static void falcon_setsda(void *data, int state) | ||
57 | { | ||
58 | struct efx_nic *efx = (struct efx_nic *)data; | ||
59 | efx_oword_t reg; | ||
60 | |||
61 | efx_reado(efx, ®, FR_AB_GPIO_CTL); | ||
62 | EFX_SET_OWORD_FIELD(reg, FRF_AB_GPIO3_OEN, !state); | ||
63 | efx_writeo(efx, ®, FR_AB_GPIO_CTL); | ||
64 | } | ||
65 | |||
66 | static void falcon_setscl(void *data, int state) | ||
67 | { | ||
68 | struct efx_nic *efx = (struct efx_nic *)data; | ||
69 | efx_oword_t reg; | ||
70 | |||
71 | efx_reado(efx, ®, FR_AB_GPIO_CTL); | ||
72 | EFX_SET_OWORD_FIELD(reg, FRF_AB_GPIO0_OEN, !state); | ||
73 | efx_writeo(efx, ®, FR_AB_GPIO_CTL); | ||
74 | } | ||
75 | |||
76 | static int falcon_getsda(void *data) | ||
77 | { | ||
78 | struct efx_nic *efx = (struct efx_nic *)data; | ||
79 | efx_oword_t reg; | ||
80 | |||
81 | efx_reado(efx, ®, FR_AB_GPIO_CTL); | ||
82 | return EFX_OWORD_FIELD(reg, FRF_AB_GPIO3_IN); | ||
83 | } | ||
84 | |||
85 | static int falcon_getscl(void *data) | ||
86 | { | ||
87 | struct efx_nic *efx = (struct efx_nic *)data; | ||
88 | efx_oword_t reg; | ||
89 | |||
90 | efx_reado(efx, ®, FR_AB_GPIO_CTL); | ||
91 | return EFX_OWORD_FIELD(reg, FRF_AB_GPIO0_IN); | ||
92 | } | ||
93 | |||
94 | static const struct i2c_algo_bit_data falcon_i2c_bit_operations = { | ||
95 | .setsda = falcon_setsda, | ||
96 | .setscl = falcon_setscl, | ||
97 | .getsda = falcon_getsda, | ||
98 | .getscl = falcon_getscl, | ||
99 | .udelay = 5, | ||
100 | /* Wait up to 50 ms for slave to let us pull SCL high */ | ||
101 | .timeout = DIV_ROUND_UP(HZ, 20), | ||
102 | }; | ||
103 | |||
104 | static void falcon_push_irq_moderation(struct efx_channel *channel) | ||
105 | { | ||
106 | efx_dword_t timer_cmd; | ||
107 | struct efx_nic *efx = channel->efx; | ||
108 | |||
109 | /* Set timer register */ | ||
110 | if (channel->irq_moderation) { | ||
111 | EFX_POPULATE_DWORD_2(timer_cmd, | ||
112 | FRF_AB_TC_TIMER_MODE, | ||
113 | FFE_BB_TIMER_MODE_INT_HLDOFF, | ||
114 | FRF_AB_TC_TIMER_VAL, | ||
115 | channel->irq_moderation - 1); | ||
116 | } else { | ||
117 | EFX_POPULATE_DWORD_2(timer_cmd, | ||
118 | FRF_AB_TC_TIMER_MODE, | ||
119 | FFE_BB_TIMER_MODE_DIS, | ||
120 | FRF_AB_TC_TIMER_VAL, 0); | ||
121 | } | ||
122 | BUILD_BUG_ON(FR_AA_TIMER_COMMAND_KER != FR_BZ_TIMER_COMMAND_P0); | ||
123 | efx_writed_page_locked(efx, &timer_cmd, FR_BZ_TIMER_COMMAND_P0, | ||
124 | channel->channel); | ||
125 | } | ||
126 | |||
127 | static void falcon_deconfigure_mac_wrapper(struct efx_nic *efx); | ||
128 | |||
129 | static void falcon_prepare_flush(struct efx_nic *efx) | ||
130 | { | ||
131 | falcon_deconfigure_mac_wrapper(efx); | ||
132 | |||
133 | /* Wait for the tx and rx fifo's to get to the next packet boundary | ||
134 | * (~1ms without back-pressure), then to drain the remainder of the | ||
135 | * fifo's at data path speeds (negligible), with a healthy margin. */ | ||
136 | msleep(10); | ||
137 | } | ||
138 | |||
139 | /* Acknowledge a legacy interrupt from Falcon | ||
140 | * | ||
141 | * This acknowledges a legacy (not MSI) interrupt via INT_ACK_KER_REG. | ||
142 | * | ||
143 | * Due to SFC bug 3706 (silicon revision <=A1) reads can be duplicated in the | ||
144 | * BIU. Interrupt acknowledge is read sensitive so must write instead | ||
145 | * (then read to ensure the BIU collector is flushed) | ||
146 | * | ||
147 | * NB most hardware supports MSI interrupts | ||
148 | */ | ||
149 | inline void falcon_irq_ack_a1(struct efx_nic *efx) | ||
150 | { | ||
151 | efx_dword_t reg; | ||
152 | |||
153 | EFX_POPULATE_DWORD_1(reg, FRF_AA_INT_ACK_KER_FIELD, 0xb7eb7e); | ||
154 | efx_writed(efx, ®, FR_AA_INT_ACK_KER); | ||
155 | efx_readd(efx, ®, FR_AA_WORK_AROUND_BROKEN_PCI_READS); | ||
156 | } | ||
157 | |||
158 | |||
159 | irqreturn_t falcon_legacy_interrupt_a1(int irq, void *dev_id) | ||
160 | { | ||
161 | struct efx_nic *efx = dev_id; | ||
162 | efx_oword_t *int_ker = efx->irq_status.addr; | ||
163 | int syserr; | ||
164 | int queues; | ||
165 | |||
166 | /* Check to see if this is our interrupt. If it isn't, we | ||
167 | * exit without having touched the hardware. | ||
168 | */ | ||
169 | if (unlikely(EFX_OWORD_IS_ZERO(*int_ker))) { | ||
170 | netif_vdbg(efx, intr, efx->net_dev, | ||
171 | "IRQ %d on CPU %d not for me\n", irq, | ||
172 | raw_smp_processor_id()); | ||
173 | return IRQ_NONE; | ||
174 | } | ||
175 | efx->last_irq_cpu = raw_smp_processor_id(); | ||
176 | netif_vdbg(efx, intr, efx->net_dev, | ||
177 | "IRQ %d on CPU %d status " EFX_OWORD_FMT "\n", | ||
178 | irq, raw_smp_processor_id(), EFX_OWORD_VAL(*int_ker)); | ||
179 | |||
180 | /* Check to see if we have a serious error condition */ | ||
181 | syserr = EFX_OWORD_FIELD(*int_ker, FSF_AZ_NET_IVEC_FATAL_INT); | ||
182 | if (unlikely(syserr)) | ||
183 | return efx_nic_fatal_interrupt(efx); | ||
184 | |||
185 | /* Determine interrupting queues, clear interrupt status | ||
186 | * register and acknowledge the device interrupt. | ||
187 | */ | ||
188 | BUILD_BUG_ON(FSF_AZ_NET_IVEC_INT_Q_WIDTH > EFX_MAX_CHANNELS); | ||
189 | queues = EFX_OWORD_FIELD(*int_ker, FSF_AZ_NET_IVEC_INT_Q); | ||
190 | EFX_ZERO_OWORD(*int_ker); | ||
191 | wmb(); /* Ensure the vector is cleared before interrupt ack */ | ||
192 | falcon_irq_ack_a1(efx); | ||
193 | |||
194 | if (queues & 1) | ||
195 | efx_schedule_channel_irq(efx_get_channel(efx, 0)); | ||
196 | if (queues & 2) | ||
197 | efx_schedule_channel_irq(efx_get_channel(efx, 1)); | ||
198 | return IRQ_HANDLED; | ||
199 | } | ||
200 | /************************************************************************** | ||
201 | * | ||
202 | * EEPROM/flash | ||
203 | * | ||
204 | ************************************************************************** | ||
205 | */ | ||
206 | |||
207 | #define FALCON_SPI_MAX_LEN sizeof(efx_oword_t) | ||
208 | |||
209 | static int falcon_spi_poll(struct efx_nic *efx) | ||
210 | { | ||
211 | efx_oword_t reg; | ||
212 | efx_reado(efx, ®, FR_AB_EE_SPI_HCMD); | ||
213 | return EFX_OWORD_FIELD(reg, FRF_AB_EE_SPI_HCMD_CMD_EN) ? -EBUSY : 0; | ||
214 | } | ||
215 | |||
216 | /* Wait for SPI command completion */ | ||
217 | static int falcon_spi_wait(struct efx_nic *efx) | ||
218 | { | ||
219 | /* Most commands will finish quickly, so we start polling at | ||
220 | * very short intervals. Sometimes the command may have to | ||
221 | * wait for VPD or expansion ROM access outside of our | ||
222 | * control, so we allow up to 100 ms. */ | ||
223 | unsigned long timeout = jiffies + 1 + DIV_ROUND_UP(HZ, 10); | ||
224 | int i; | ||
225 | |||
226 | for (i = 0; i < 10; i++) { | ||
227 | if (!falcon_spi_poll(efx)) | ||
228 | return 0; | ||
229 | udelay(10); | ||
230 | } | ||
231 | |||
232 | for (;;) { | ||
233 | if (!falcon_spi_poll(efx)) | ||
234 | return 0; | ||
235 | if (time_after_eq(jiffies, timeout)) { | ||
236 | netif_err(efx, hw, efx->net_dev, | ||
237 | "timed out waiting for SPI\n"); | ||
238 | return -ETIMEDOUT; | ||
239 | } | ||
240 | schedule_timeout_uninterruptible(1); | ||
241 | } | ||
242 | } | ||
243 | |||
244 | int falcon_spi_cmd(struct efx_nic *efx, const struct efx_spi_device *spi, | ||
245 | unsigned int command, int address, | ||
246 | const void *in, void *out, size_t len) | ||
247 | { | ||
248 | bool addressed = (address >= 0); | ||
249 | bool reading = (out != NULL); | ||
250 | efx_oword_t reg; | ||
251 | int rc; | ||
252 | |||
253 | /* Input validation */ | ||
254 | if (len > FALCON_SPI_MAX_LEN) | ||
255 | return -EINVAL; | ||
256 | |||
257 | /* Check that previous command is not still running */ | ||
258 | rc = falcon_spi_poll(efx); | ||
259 | if (rc) | ||
260 | return rc; | ||
261 | |||
262 | /* Program address register, if we have an address */ | ||
263 | if (addressed) { | ||
264 | EFX_POPULATE_OWORD_1(reg, FRF_AB_EE_SPI_HADR_ADR, address); | ||
265 | efx_writeo(efx, ®, FR_AB_EE_SPI_HADR); | ||
266 | } | ||
267 | |||
268 | /* Program data register, if we have data */ | ||
269 | if (in != NULL) { | ||
270 | memcpy(®, in, len); | ||
271 | efx_writeo(efx, ®, FR_AB_EE_SPI_HDATA); | ||
272 | } | ||
273 | |||
274 | /* Issue read/write command */ | ||
275 | EFX_POPULATE_OWORD_7(reg, | ||
276 | FRF_AB_EE_SPI_HCMD_CMD_EN, 1, | ||
277 | FRF_AB_EE_SPI_HCMD_SF_SEL, spi->device_id, | ||
278 | FRF_AB_EE_SPI_HCMD_DABCNT, len, | ||
279 | FRF_AB_EE_SPI_HCMD_READ, reading, | ||
280 | FRF_AB_EE_SPI_HCMD_DUBCNT, 0, | ||
281 | FRF_AB_EE_SPI_HCMD_ADBCNT, | ||
282 | (addressed ? spi->addr_len : 0), | ||
283 | FRF_AB_EE_SPI_HCMD_ENC, command); | ||
284 | efx_writeo(efx, ®, FR_AB_EE_SPI_HCMD); | ||
285 | |||
286 | /* Wait for read/write to complete */ | ||
287 | rc = falcon_spi_wait(efx); | ||
288 | if (rc) | ||
289 | return rc; | ||
290 | |||
291 | /* Read data */ | ||
292 | if (out != NULL) { | ||
293 | efx_reado(efx, ®, FR_AB_EE_SPI_HDATA); | ||
294 | memcpy(out, ®, len); | ||
295 | } | ||
296 | |||
297 | return 0; | ||
298 | } | ||
299 | |||
300 | static size_t | ||
301 | falcon_spi_write_limit(const struct efx_spi_device *spi, size_t start) | ||
302 | { | ||
303 | return min(FALCON_SPI_MAX_LEN, | ||
304 | (spi->block_size - (start & (spi->block_size - 1)))); | ||
305 | } | ||
306 | |||
307 | static inline u8 | ||
308 | efx_spi_munge_command(const struct efx_spi_device *spi, | ||
309 | const u8 command, const unsigned int address) | ||
310 | { | ||
311 | return command | (((address >> 8) & spi->munge_address) << 3); | ||
312 | } | ||
313 | |||
314 | /* Wait up to 10 ms for buffered write completion */ | ||
315 | int | ||
316 | falcon_spi_wait_write(struct efx_nic *efx, const struct efx_spi_device *spi) | ||
317 | { | ||
318 | unsigned long timeout = jiffies + 1 + DIV_ROUND_UP(HZ, 100); | ||
319 | u8 status; | ||
320 | int rc; | ||
321 | |||
322 | for (;;) { | ||
323 | rc = falcon_spi_cmd(efx, spi, SPI_RDSR, -1, NULL, | ||
324 | &status, sizeof(status)); | ||
325 | if (rc) | ||
326 | return rc; | ||
327 | if (!(status & SPI_STATUS_NRDY)) | ||
328 | return 0; | ||
329 | if (time_after_eq(jiffies, timeout)) { | ||
330 | netif_err(efx, hw, efx->net_dev, | ||
331 | "SPI write timeout on device %d" | ||
332 | " last status=0x%02x\n", | ||
333 | spi->device_id, status); | ||
334 | return -ETIMEDOUT; | ||
335 | } | ||
336 | schedule_timeout_uninterruptible(1); | ||
337 | } | ||
338 | } | ||
339 | |||
340 | int falcon_spi_read(struct efx_nic *efx, const struct efx_spi_device *spi, | ||
341 | loff_t start, size_t len, size_t *retlen, u8 *buffer) | ||
342 | { | ||
343 | size_t block_len, pos = 0; | ||
344 | unsigned int command; | ||
345 | int rc = 0; | ||
346 | |||
347 | while (pos < len) { | ||
348 | block_len = min(len - pos, FALCON_SPI_MAX_LEN); | ||
349 | |||
350 | command = efx_spi_munge_command(spi, SPI_READ, start + pos); | ||
351 | rc = falcon_spi_cmd(efx, spi, command, start + pos, NULL, | ||
352 | buffer + pos, block_len); | ||
353 | if (rc) | ||
354 | break; | ||
355 | pos += block_len; | ||
356 | |||
357 | /* Avoid locking up the system */ | ||
358 | cond_resched(); | ||
359 | if (signal_pending(current)) { | ||
360 | rc = -EINTR; | ||
361 | break; | ||
362 | } | ||
363 | } | ||
364 | |||
365 | if (retlen) | ||
366 | *retlen = pos; | ||
367 | return rc; | ||
368 | } | ||
369 | |||
370 | int | ||
371 | falcon_spi_write(struct efx_nic *efx, const struct efx_spi_device *spi, | ||
372 | loff_t start, size_t len, size_t *retlen, const u8 *buffer) | ||
373 | { | ||
374 | u8 verify_buffer[FALCON_SPI_MAX_LEN]; | ||
375 | size_t block_len, pos = 0; | ||
376 | unsigned int command; | ||
377 | int rc = 0; | ||
378 | |||
379 | while (pos < len) { | ||
380 | rc = falcon_spi_cmd(efx, spi, SPI_WREN, -1, NULL, NULL, 0); | ||
381 | if (rc) | ||
382 | break; | ||
383 | |||
384 | block_len = min(len - pos, | ||
385 | falcon_spi_write_limit(spi, start + pos)); | ||
386 | command = efx_spi_munge_command(spi, SPI_WRITE, start + pos); | ||
387 | rc = falcon_spi_cmd(efx, spi, command, start + pos, | ||
388 | buffer + pos, NULL, block_len); | ||
389 | if (rc) | ||
390 | break; | ||
391 | |||
392 | rc = falcon_spi_wait_write(efx, spi); | ||
393 | if (rc) | ||
394 | break; | ||
395 | |||
396 | command = efx_spi_munge_command(spi, SPI_READ, start + pos); | ||
397 | rc = falcon_spi_cmd(efx, spi, command, start + pos, | ||
398 | NULL, verify_buffer, block_len); | ||
399 | if (memcmp(verify_buffer, buffer + pos, block_len)) { | ||
400 | rc = -EIO; | ||
401 | break; | ||
402 | } | ||
403 | |||
404 | pos += block_len; | ||
405 | |||
406 | /* Avoid locking up the system */ | ||
407 | cond_resched(); | ||
408 | if (signal_pending(current)) { | ||
409 | rc = -EINTR; | ||
410 | break; | ||
411 | } | ||
412 | } | ||
413 | |||
414 | if (retlen) | ||
415 | *retlen = pos; | ||
416 | return rc; | ||
417 | } | ||
418 | |||
419 | /************************************************************************** | ||
420 | * | ||
421 | * MAC wrapper | ||
422 | * | ||
423 | ************************************************************************** | ||
424 | */ | ||
425 | |||
426 | static void falcon_push_multicast_hash(struct efx_nic *efx) | ||
427 | { | ||
428 | union efx_multicast_hash *mc_hash = &efx->multicast_hash; | ||
429 | |||
430 | WARN_ON(!mutex_is_locked(&efx->mac_lock)); | ||
431 | |||
432 | efx_writeo(efx, &mc_hash->oword[0], FR_AB_MAC_MC_HASH_REG0); | ||
433 | efx_writeo(efx, &mc_hash->oword[1], FR_AB_MAC_MC_HASH_REG1); | ||
434 | } | ||
435 | |||
436 | static void falcon_reset_macs(struct efx_nic *efx) | ||
437 | { | ||
438 | struct falcon_nic_data *nic_data = efx->nic_data; | ||
439 | efx_oword_t reg, mac_ctrl; | ||
440 | int count; | ||
441 | |||
442 | if (efx_nic_rev(efx) < EFX_REV_FALCON_B0) { | ||
443 | /* It's not safe to use GLB_CTL_REG to reset the | ||
444 | * macs, so instead use the internal MAC resets | ||
445 | */ | ||
446 | EFX_POPULATE_OWORD_1(reg, FRF_AB_XM_CORE_RST, 1); | ||
447 | efx_writeo(efx, ®, FR_AB_XM_GLB_CFG); | ||
448 | |||
449 | for (count = 0; count < 10000; count++) { | ||
450 | efx_reado(efx, ®, FR_AB_XM_GLB_CFG); | ||
451 | if (EFX_OWORD_FIELD(reg, FRF_AB_XM_CORE_RST) == | ||
452 | 0) | ||
453 | return; | ||
454 | udelay(10); | ||
455 | } | ||
456 | |||
457 | netif_err(efx, hw, efx->net_dev, | ||
458 | "timed out waiting for XMAC core reset\n"); | ||
459 | } | ||
460 | |||
461 | /* Mac stats will fail whist the TX fifo is draining */ | ||
462 | WARN_ON(nic_data->stats_disable_count == 0); | ||
463 | |||
464 | efx_reado(efx, &mac_ctrl, FR_AB_MAC_CTRL); | ||
465 | EFX_SET_OWORD_FIELD(mac_ctrl, FRF_BB_TXFIFO_DRAIN_EN, 1); | ||
466 | efx_writeo(efx, &mac_ctrl, FR_AB_MAC_CTRL); | ||
467 | |||
468 | efx_reado(efx, ®, FR_AB_GLB_CTL); | ||
469 | EFX_SET_OWORD_FIELD(reg, FRF_AB_RST_XGTX, 1); | ||
470 | EFX_SET_OWORD_FIELD(reg, FRF_AB_RST_XGRX, 1); | ||
471 | EFX_SET_OWORD_FIELD(reg, FRF_AB_RST_EM, 1); | ||
472 | efx_writeo(efx, ®, FR_AB_GLB_CTL); | ||
473 | |||
474 | count = 0; | ||
475 | while (1) { | ||
476 | efx_reado(efx, ®, FR_AB_GLB_CTL); | ||
477 | if (!EFX_OWORD_FIELD(reg, FRF_AB_RST_XGTX) && | ||
478 | !EFX_OWORD_FIELD(reg, FRF_AB_RST_XGRX) && | ||
479 | !EFX_OWORD_FIELD(reg, FRF_AB_RST_EM)) { | ||
480 | netif_dbg(efx, hw, efx->net_dev, | ||
481 | "Completed MAC reset after %d loops\n", | ||
482 | count); | ||
483 | break; | ||
484 | } | ||
485 | if (count > 20) { | ||
486 | netif_err(efx, hw, efx->net_dev, "MAC reset failed\n"); | ||
487 | break; | ||
488 | } | ||
489 | count++; | ||
490 | udelay(10); | ||
491 | } | ||
492 | |||
493 | /* Ensure the correct MAC is selected before statistics | ||
494 | * are re-enabled by the caller */ | ||
495 | efx_writeo(efx, &mac_ctrl, FR_AB_MAC_CTRL); | ||
496 | |||
497 | falcon_setup_xaui(efx); | ||
498 | } | ||
499 | |||
500 | void falcon_drain_tx_fifo(struct efx_nic *efx) | ||
501 | { | ||
502 | efx_oword_t reg; | ||
503 | |||
504 | if ((efx_nic_rev(efx) < EFX_REV_FALCON_B0) || | ||
505 | (efx->loopback_mode != LOOPBACK_NONE)) | ||
506 | return; | ||
507 | |||
508 | efx_reado(efx, ®, FR_AB_MAC_CTRL); | ||
509 | /* There is no point in draining more than once */ | ||
510 | if (EFX_OWORD_FIELD(reg, FRF_BB_TXFIFO_DRAIN_EN)) | ||
511 | return; | ||
512 | |||
513 | falcon_reset_macs(efx); | ||
514 | } | ||
515 | |||
516 | static void falcon_deconfigure_mac_wrapper(struct efx_nic *efx) | ||
517 | { | ||
518 | efx_oword_t reg; | ||
519 | |||
520 | if (efx_nic_rev(efx) < EFX_REV_FALCON_B0) | ||
521 | return; | ||
522 | |||
523 | /* Isolate the MAC -> RX */ | ||
524 | efx_reado(efx, ®, FR_AZ_RX_CFG); | ||
525 | EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_INGR_EN, 0); | ||
526 | efx_writeo(efx, ®, FR_AZ_RX_CFG); | ||
527 | |||
528 | /* Isolate TX -> MAC */ | ||
529 | falcon_drain_tx_fifo(efx); | ||
530 | } | ||
531 | |||
532 | void falcon_reconfigure_mac_wrapper(struct efx_nic *efx) | ||
533 | { | ||
534 | struct efx_link_state *link_state = &efx->link_state; | ||
535 | efx_oword_t reg; | ||
536 | int link_speed, isolate; | ||
537 | |||
538 | isolate = !!ACCESS_ONCE(efx->reset_pending); | ||
539 | |||
540 | switch (link_state->speed) { | ||
541 | case 10000: link_speed = 3; break; | ||
542 | case 1000: link_speed = 2; break; | ||
543 | case 100: link_speed = 1; break; | ||
544 | default: link_speed = 0; break; | ||
545 | } | ||
546 | /* MAC_LINK_STATUS controls MAC backpressure but doesn't work | ||
547 | * as advertised. Disable to ensure packets are not | ||
548 | * indefinitely held and TX queue can be flushed at any point | ||
549 | * while the link is down. */ | ||
550 | EFX_POPULATE_OWORD_5(reg, | ||
551 | FRF_AB_MAC_XOFF_VAL, 0xffff /* max pause time */, | ||
552 | FRF_AB_MAC_BCAD_ACPT, 1, | ||
553 | FRF_AB_MAC_UC_PROM, efx->promiscuous, | ||
554 | FRF_AB_MAC_LINK_STATUS, 1, /* always set */ | ||
555 | FRF_AB_MAC_SPEED, link_speed); | ||
556 | /* On B0, MAC backpressure can be disabled and packets get | ||
557 | * discarded. */ | ||
558 | if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0) { | ||
559 | EFX_SET_OWORD_FIELD(reg, FRF_BB_TXFIFO_DRAIN_EN, | ||
560 | !link_state->up || isolate); | ||
561 | } | ||
562 | |||
563 | efx_writeo(efx, ®, FR_AB_MAC_CTRL); | ||
564 | |||
565 | /* Restore the multicast hash registers. */ | ||
566 | falcon_push_multicast_hash(efx); | ||
567 | |||
568 | efx_reado(efx, ®, FR_AZ_RX_CFG); | ||
569 | /* Enable XOFF signal from RX FIFO (we enabled it during NIC | ||
570 | * initialisation but it may read back as 0) */ | ||
571 | EFX_SET_OWORD_FIELD(reg, FRF_AZ_RX_XOFF_MAC_EN, 1); | ||
572 | /* Unisolate the MAC -> RX */ | ||
573 | if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0) | ||
574 | EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_INGR_EN, !isolate); | ||
575 | efx_writeo(efx, ®, FR_AZ_RX_CFG); | ||
576 | } | ||
577 | |||
578 | static void falcon_stats_request(struct efx_nic *efx) | ||
579 | { | ||
580 | struct falcon_nic_data *nic_data = efx->nic_data; | ||
581 | efx_oword_t reg; | ||
582 | |||
583 | WARN_ON(nic_data->stats_pending); | ||
584 | WARN_ON(nic_data->stats_disable_count); | ||
585 | |||
586 | if (nic_data->stats_dma_done == NULL) | ||
587 | return; /* no mac selected */ | ||
588 | |||
589 | *nic_data->stats_dma_done = FALCON_STATS_NOT_DONE; | ||
590 | nic_data->stats_pending = true; | ||
591 | wmb(); /* ensure done flag is clear */ | ||
592 | |||
593 | /* Initiate DMA transfer of stats */ | ||
594 | EFX_POPULATE_OWORD_2(reg, | ||
595 | FRF_AB_MAC_STAT_DMA_CMD, 1, | ||
596 | FRF_AB_MAC_STAT_DMA_ADR, | ||
597 | efx->stats_buffer.dma_addr); | ||
598 | efx_writeo(efx, ®, FR_AB_MAC_STAT_DMA); | ||
599 | |||
600 | mod_timer(&nic_data->stats_timer, round_jiffies_up(jiffies + HZ / 2)); | ||
601 | } | ||
602 | |||
603 | static void falcon_stats_complete(struct efx_nic *efx) | ||
604 | { | ||
605 | struct falcon_nic_data *nic_data = efx->nic_data; | ||
606 | |||
607 | if (!nic_data->stats_pending) | ||
608 | return; | ||
609 | |||
610 | nic_data->stats_pending = false; | ||
611 | if (*nic_data->stats_dma_done == FALCON_STATS_DONE) { | ||
612 | rmb(); /* read the done flag before the stats */ | ||
613 | falcon_update_stats_xmac(efx); | ||
614 | } else { | ||
615 | netif_err(efx, hw, efx->net_dev, | ||
616 | "timed out waiting for statistics\n"); | ||
617 | } | ||
618 | } | ||
619 | |||
620 | static void falcon_stats_timer_func(unsigned long context) | ||
621 | { | ||
622 | struct efx_nic *efx = (struct efx_nic *)context; | ||
623 | struct falcon_nic_data *nic_data = efx->nic_data; | ||
624 | |||
625 | spin_lock(&efx->stats_lock); | ||
626 | |||
627 | falcon_stats_complete(efx); | ||
628 | if (nic_data->stats_disable_count == 0) | ||
629 | falcon_stats_request(efx); | ||
630 | |||
631 | spin_unlock(&efx->stats_lock); | ||
632 | } | ||
633 | |||
634 | static bool falcon_loopback_link_poll(struct efx_nic *efx) | ||
635 | { | ||
636 | struct efx_link_state old_state = efx->link_state; | ||
637 | |||
638 | WARN_ON(!mutex_is_locked(&efx->mac_lock)); | ||
639 | WARN_ON(!LOOPBACK_INTERNAL(efx)); | ||
640 | |||
641 | efx->link_state.fd = true; | ||
642 | efx->link_state.fc = efx->wanted_fc; | ||
643 | efx->link_state.up = true; | ||
644 | efx->link_state.speed = 10000; | ||
645 | |||
646 | return !efx_link_state_equal(&efx->link_state, &old_state); | ||
647 | } | ||
648 | |||
649 | static int falcon_reconfigure_port(struct efx_nic *efx) | ||
650 | { | ||
651 | int rc; | ||
652 | |||
653 | WARN_ON(efx_nic_rev(efx) > EFX_REV_FALCON_B0); | ||
654 | |||
655 | /* Poll the PHY link state *before* reconfiguring it. This means we | ||
656 | * will pick up the correct speed (in loopback) to select the correct | ||
657 | * MAC. | ||
658 | */ | ||
659 | if (LOOPBACK_INTERNAL(efx)) | ||
660 | falcon_loopback_link_poll(efx); | ||
661 | else | ||
662 | efx->phy_op->poll(efx); | ||
663 | |||
664 | falcon_stop_nic_stats(efx); | ||
665 | falcon_deconfigure_mac_wrapper(efx); | ||
666 | |||
667 | falcon_reset_macs(efx); | ||
668 | |||
669 | efx->phy_op->reconfigure(efx); | ||
670 | rc = falcon_reconfigure_xmac(efx); | ||
671 | BUG_ON(rc); | ||
672 | |||
673 | falcon_start_nic_stats(efx); | ||
674 | |||
675 | /* Synchronise efx->link_state with the kernel */ | ||
676 | efx_link_status_changed(efx); | ||
677 | |||
678 | return 0; | ||
679 | } | ||
680 | |||
681 | /************************************************************************** | ||
682 | * | ||
683 | * PHY access via GMII | ||
684 | * | ||
685 | ************************************************************************** | ||
686 | */ | ||
687 | |||
688 | /* Wait for GMII access to complete */ | ||
689 | static int falcon_gmii_wait(struct efx_nic *efx) | ||
690 | { | ||
691 | efx_oword_t md_stat; | ||
692 | int count; | ||
693 | |||
694 | /* wait up to 50ms - taken max from datasheet */ | ||
695 | for (count = 0; count < 5000; count++) { | ||
696 | efx_reado(efx, &md_stat, FR_AB_MD_STAT); | ||
697 | if (EFX_OWORD_FIELD(md_stat, FRF_AB_MD_BSY) == 0) { | ||
698 | if (EFX_OWORD_FIELD(md_stat, FRF_AB_MD_LNFL) != 0 || | ||
699 | EFX_OWORD_FIELD(md_stat, FRF_AB_MD_BSERR) != 0) { | ||
700 | netif_err(efx, hw, efx->net_dev, | ||
701 | "error from GMII access " | ||
702 | EFX_OWORD_FMT"\n", | ||
703 | EFX_OWORD_VAL(md_stat)); | ||
704 | return -EIO; | ||
705 | } | ||
706 | return 0; | ||
707 | } | ||
708 | udelay(10); | ||
709 | } | ||
710 | netif_err(efx, hw, efx->net_dev, "timed out waiting for GMII\n"); | ||
711 | return -ETIMEDOUT; | ||
712 | } | ||
713 | |||
714 | /* Write an MDIO register of a PHY connected to Falcon. */ | ||
715 | static int falcon_mdio_write(struct net_device *net_dev, | ||
716 | int prtad, int devad, u16 addr, u16 value) | ||
717 | { | ||
718 | struct efx_nic *efx = netdev_priv(net_dev); | ||
719 | struct falcon_nic_data *nic_data = efx->nic_data; | ||
720 | efx_oword_t reg; | ||
721 | int rc; | ||
722 | |||
723 | netif_vdbg(efx, hw, efx->net_dev, | ||
724 | "writing MDIO %d register %d.%d with 0x%04x\n", | ||
725 | prtad, devad, addr, value); | ||
726 | |||
727 | mutex_lock(&nic_data->mdio_lock); | ||
728 | |||
729 | /* Check MDIO not currently being accessed */ | ||
730 | rc = falcon_gmii_wait(efx); | ||
731 | if (rc) | ||
732 | goto out; | ||
733 | |||
734 | /* Write the address/ID register */ | ||
735 | EFX_POPULATE_OWORD_1(reg, FRF_AB_MD_PHY_ADR, addr); | ||
736 | efx_writeo(efx, ®, FR_AB_MD_PHY_ADR); | ||
737 | |||
738 | EFX_POPULATE_OWORD_2(reg, FRF_AB_MD_PRT_ADR, prtad, | ||
739 | FRF_AB_MD_DEV_ADR, devad); | ||
740 | efx_writeo(efx, ®, FR_AB_MD_ID); | ||
741 | |||
742 | /* Write data */ | ||
743 | EFX_POPULATE_OWORD_1(reg, FRF_AB_MD_TXD, value); | ||
744 | efx_writeo(efx, ®, FR_AB_MD_TXD); | ||
745 | |||
746 | EFX_POPULATE_OWORD_2(reg, | ||
747 | FRF_AB_MD_WRC, 1, | ||
748 | FRF_AB_MD_GC, 0); | ||
749 | efx_writeo(efx, ®, FR_AB_MD_CS); | ||
750 | |||
751 | /* Wait for data to be written */ | ||
752 | rc = falcon_gmii_wait(efx); | ||
753 | if (rc) { | ||
754 | /* Abort the write operation */ | ||
755 | EFX_POPULATE_OWORD_2(reg, | ||
756 | FRF_AB_MD_WRC, 0, | ||
757 | FRF_AB_MD_GC, 1); | ||
758 | efx_writeo(efx, ®, FR_AB_MD_CS); | ||
759 | udelay(10); | ||
760 | } | ||
761 | |||
762 | out: | ||
763 | mutex_unlock(&nic_data->mdio_lock); | ||
764 | return rc; | ||
765 | } | ||
766 | |||
767 | /* Read an MDIO register of a PHY connected to Falcon. */ | ||
768 | static int falcon_mdio_read(struct net_device *net_dev, | ||
769 | int prtad, int devad, u16 addr) | ||
770 | { | ||
771 | struct efx_nic *efx = netdev_priv(net_dev); | ||
772 | struct falcon_nic_data *nic_data = efx->nic_data; | ||
773 | efx_oword_t reg; | ||
774 | int rc; | ||
775 | |||
776 | mutex_lock(&nic_data->mdio_lock); | ||
777 | |||
778 | /* Check MDIO not currently being accessed */ | ||
779 | rc = falcon_gmii_wait(efx); | ||
780 | if (rc) | ||
781 | goto out; | ||
782 | |||
783 | EFX_POPULATE_OWORD_1(reg, FRF_AB_MD_PHY_ADR, addr); | ||
784 | efx_writeo(efx, ®, FR_AB_MD_PHY_ADR); | ||
785 | |||
786 | EFX_POPULATE_OWORD_2(reg, FRF_AB_MD_PRT_ADR, prtad, | ||
787 | FRF_AB_MD_DEV_ADR, devad); | ||
788 | efx_writeo(efx, ®, FR_AB_MD_ID); | ||
789 | |||
790 | /* Request data to be read */ | ||
791 | EFX_POPULATE_OWORD_2(reg, FRF_AB_MD_RDC, 1, FRF_AB_MD_GC, 0); | ||
792 | efx_writeo(efx, ®, FR_AB_MD_CS); | ||
793 | |||
794 | /* Wait for data to become available */ | ||
795 | rc = falcon_gmii_wait(efx); | ||
796 | if (rc == 0) { | ||
797 | efx_reado(efx, ®, FR_AB_MD_RXD); | ||
798 | rc = EFX_OWORD_FIELD(reg, FRF_AB_MD_RXD); | ||
799 | netif_vdbg(efx, hw, efx->net_dev, | ||
800 | "read from MDIO %d register %d.%d, got %04x\n", | ||
801 | prtad, devad, addr, rc); | ||
802 | } else { | ||
803 | /* Abort the read operation */ | ||
804 | EFX_POPULATE_OWORD_2(reg, | ||
805 | FRF_AB_MD_RIC, 0, | ||
806 | FRF_AB_MD_GC, 1); | ||
807 | efx_writeo(efx, ®, FR_AB_MD_CS); | ||
808 | |||
809 | netif_dbg(efx, hw, efx->net_dev, | ||
810 | "read from MDIO %d register %d.%d, got error %d\n", | ||
811 | prtad, devad, addr, rc); | ||
812 | } | ||
813 | |||
814 | out: | ||
815 | mutex_unlock(&nic_data->mdio_lock); | ||
816 | return rc; | ||
817 | } | ||
818 | |||
819 | /* This call is responsible for hooking in the MAC and PHY operations */ | ||
820 | static int falcon_probe_port(struct efx_nic *efx) | ||
821 | { | ||
822 | struct falcon_nic_data *nic_data = efx->nic_data; | ||
823 | int rc; | ||
824 | |||
825 | switch (efx->phy_type) { | ||
826 | case PHY_TYPE_SFX7101: | ||
827 | efx->phy_op = &falcon_sfx7101_phy_ops; | ||
828 | break; | ||
829 | case PHY_TYPE_QT2022C2: | ||
830 | case PHY_TYPE_QT2025C: | ||
831 | efx->phy_op = &falcon_qt202x_phy_ops; | ||
832 | break; | ||
833 | case PHY_TYPE_TXC43128: | ||
834 | efx->phy_op = &falcon_txc_phy_ops; | ||
835 | break; | ||
836 | default: | ||
837 | netif_err(efx, probe, efx->net_dev, "Unknown PHY type %d\n", | ||
838 | efx->phy_type); | ||
839 | return -ENODEV; | ||
840 | } | ||
841 | |||
842 | /* Fill out MDIO structure and loopback modes */ | ||
843 | mutex_init(&nic_data->mdio_lock); | ||
844 | efx->mdio.mdio_read = falcon_mdio_read; | ||
845 | efx->mdio.mdio_write = falcon_mdio_write; | ||
846 | rc = efx->phy_op->probe(efx); | ||
847 | if (rc != 0) | ||
848 | return rc; | ||
849 | |||
850 | /* Initial assumption */ | ||
851 | efx->link_state.speed = 10000; | ||
852 | efx->link_state.fd = true; | ||
853 | |||
854 | /* Hardware flow ctrl. FalconA RX FIFO too small for pause generation */ | ||
855 | if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0) | ||
856 | efx->wanted_fc = EFX_FC_RX | EFX_FC_TX; | ||
857 | else | ||
858 | efx->wanted_fc = EFX_FC_RX; | ||
859 | if (efx->mdio.mmds & MDIO_DEVS_AN) | ||
860 | efx->wanted_fc |= EFX_FC_AUTO; | ||
861 | |||
862 | /* Allocate buffer for stats */ | ||
863 | rc = efx_nic_alloc_buffer(efx, &efx->stats_buffer, | ||
864 | FALCON_MAC_STATS_SIZE); | ||
865 | if (rc) | ||
866 | return rc; | ||
867 | netif_dbg(efx, probe, efx->net_dev, | ||
868 | "stats buffer at %llx (virt %p phys %llx)\n", | ||
869 | (u64)efx->stats_buffer.dma_addr, | ||
870 | efx->stats_buffer.addr, | ||
871 | (u64)virt_to_phys(efx->stats_buffer.addr)); | ||
872 | nic_data->stats_dma_done = efx->stats_buffer.addr + XgDmaDone_offset; | ||
873 | |||
874 | return 0; | ||
875 | } | ||
876 | |||
877 | static void falcon_remove_port(struct efx_nic *efx) | ||
878 | { | ||
879 | efx->phy_op->remove(efx); | ||
880 | efx_nic_free_buffer(efx, &efx->stats_buffer); | ||
881 | } | ||
882 | |||
883 | /* Global events are basically PHY events */ | ||
884 | static bool | ||
885 | falcon_handle_global_event(struct efx_channel *channel, efx_qword_t *event) | ||
886 | { | ||
887 | struct efx_nic *efx = channel->efx; | ||
888 | struct falcon_nic_data *nic_data = efx->nic_data; | ||
889 | |||
890 | if (EFX_QWORD_FIELD(*event, FSF_AB_GLB_EV_G_PHY0_INTR) || | ||
891 | EFX_QWORD_FIELD(*event, FSF_AB_GLB_EV_XG_PHY0_INTR) || | ||
892 | EFX_QWORD_FIELD(*event, FSF_AB_GLB_EV_XFP_PHY0_INTR)) | ||
893 | /* Ignored */ | ||
894 | return true; | ||
895 | |||
896 | if ((efx_nic_rev(efx) == EFX_REV_FALCON_B0) && | ||
897 | EFX_QWORD_FIELD(*event, FSF_BB_GLB_EV_XG_MGT_INTR)) { | ||
898 | nic_data->xmac_poll_required = true; | ||
899 | return true; | ||
900 | } | ||
901 | |||
902 | if (efx_nic_rev(efx) <= EFX_REV_FALCON_A1 ? | ||
903 | EFX_QWORD_FIELD(*event, FSF_AA_GLB_EV_RX_RECOVERY) : | ||
904 | EFX_QWORD_FIELD(*event, FSF_BB_GLB_EV_RX_RECOVERY)) { | ||
905 | netif_err(efx, rx_err, efx->net_dev, | ||
906 | "channel %d seen global RX_RESET event. Resetting.\n", | ||
907 | channel->channel); | ||
908 | |||
909 | atomic_inc(&efx->rx_reset); | ||
910 | efx_schedule_reset(efx, EFX_WORKAROUND_6555(efx) ? | ||
911 | RESET_TYPE_RX_RECOVERY : RESET_TYPE_DISABLE); | ||
912 | return true; | ||
913 | } | ||
914 | |||
915 | return false; | ||
916 | } | ||
917 | |||
918 | /************************************************************************** | ||
919 | * | ||
920 | * Falcon test code | ||
921 | * | ||
922 | **************************************************************************/ | ||
923 | |||
924 | static int | ||
925 | falcon_read_nvram(struct efx_nic *efx, struct falcon_nvconfig *nvconfig_out) | ||
926 | { | ||
927 | struct falcon_nic_data *nic_data = efx->nic_data; | ||
928 | struct falcon_nvconfig *nvconfig; | ||
929 | struct efx_spi_device *spi; | ||
930 | void *region; | ||
931 | int rc, magic_num, struct_ver; | ||
932 | __le16 *word, *limit; | ||
933 | u32 csum; | ||
934 | |||
935 | if (efx_spi_present(&nic_data->spi_flash)) | ||
936 | spi = &nic_data->spi_flash; | ||
937 | else if (efx_spi_present(&nic_data->spi_eeprom)) | ||
938 | spi = &nic_data->spi_eeprom; | ||
939 | else | ||
940 | return -EINVAL; | ||
941 | |||
942 | region = kmalloc(FALCON_NVCONFIG_END, GFP_KERNEL); | ||
943 | if (!region) | ||
944 | return -ENOMEM; | ||
945 | nvconfig = region + FALCON_NVCONFIG_OFFSET; | ||
946 | |||
947 | mutex_lock(&nic_data->spi_lock); | ||
948 | rc = falcon_spi_read(efx, spi, 0, FALCON_NVCONFIG_END, NULL, region); | ||
949 | mutex_unlock(&nic_data->spi_lock); | ||
950 | if (rc) { | ||
951 | netif_err(efx, hw, efx->net_dev, "Failed to read %s\n", | ||
952 | efx_spi_present(&nic_data->spi_flash) ? | ||
953 | "flash" : "EEPROM"); | ||
954 | rc = -EIO; | ||
955 | goto out; | ||
956 | } | ||
957 | |||
958 | magic_num = le16_to_cpu(nvconfig->board_magic_num); | ||
959 | struct_ver = le16_to_cpu(nvconfig->board_struct_ver); | ||
960 | |||
961 | rc = -EINVAL; | ||
962 | if (magic_num != FALCON_NVCONFIG_BOARD_MAGIC_NUM) { | ||
963 | netif_err(efx, hw, efx->net_dev, | ||
964 | "NVRAM bad magic 0x%x\n", magic_num); | ||
965 | goto out; | ||
966 | } | ||
967 | if (struct_ver < 2) { | ||
968 | netif_err(efx, hw, efx->net_dev, | ||
969 | "NVRAM has ancient version 0x%x\n", struct_ver); | ||
970 | goto out; | ||
971 | } else if (struct_ver < 4) { | ||
972 | word = &nvconfig->board_magic_num; | ||
973 | limit = (__le16 *) (nvconfig + 1); | ||
974 | } else { | ||
975 | word = region; | ||
976 | limit = region + FALCON_NVCONFIG_END; | ||
977 | } | ||
978 | for (csum = 0; word < limit; ++word) | ||
979 | csum += le16_to_cpu(*word); | ||
980 | |||
981 | if (~csum & 0xffff) { | ||
982 | netif_err(efx, hw, efx->net_dev, | ||
983 | "NVRAM has incorrect checksum\n"); | ||
984 | goto out; | ||
985 | } | ||
986 | |||
987 | rc = 0; | ||
988 | if (nvconfig_out) | ||
989 | memcpy(nvconfig_out, nvconfig, sizeof(*nvconfig)); | ||
990 | |||
991 | out: | ||
992 | kfree(region); | ||
993 | return rc; | ||
994 | } | ||
995 | |||
996 | static int falcon_test_nvram(struct efx_nic *efx) | ||
997 | { | ||
998 | return falcon_read_nvram(efx, NULL); | ||
999 | } | ||
1000 | |||
1001 | static const struct efx_nic_register_test falcon_b0_register_tests[] = { | ||
1002 | { FR_AZ_ADR_REGION, | ||
1003 | EFX_OWORD32(0x0003FFFF, 0x0003FFFF, 0x0003FFFF, 0x0003FFFF) }, | ||
1004 | { FR_AZ_RX_CFG, | ||
1005 | EFX_OWORD32(0xFFFFFFFE, 0x00017FFF, 0x00000000, 0x00000000) }, | ||
1006 | { FR_AZ_TX_CFG, | ||
1007 | EFX_OWORD32(0x7FFF0037, 0x00000000, 0x00000000, 0x00000000) }, | ||
1008 | { FR_AZ_TX_RESERVED, | ||
1009 | EFX_OWORD32(0xFFFEFE80, 0x1FFFFFFF, 0x020000FE, 0x007FFFFF) }, | ||
1010 | { FR_AB_MAC_CTRL, | ||
1011 | EFX_OWORD32(0xFFFF0000, 0x00000000, 0x00000000, 0x00000000) }, | ||
1012 | { FR_AZ_SRM_TX_DC_CFG, | ||
1013 | EFX_OWORD32(0x001FFFFF, 0x00000000, 0x00000000, 0x00000000) }, | ||
1014 | { FR_AZ_RX_DC_CFG, | ||
1015 | EFX_OWORD32(0x0000000F, 0x00000000, 0x00000000, 0x00000000) }, | ||
1016 | { FR_AZ_RX_DC_PF_WM, | ||
1017 | EFX_OWORD32(0x000003FF, 0x00000000, 0x00000000, 0x00000000) }, | ||
1018 | { FR_BZ_DP_CTRL, | ||
1019 | EFX_OWORD32(0x00000FFF, 0x00000000, 0x00000000, 0x00000000) }, | ||
1020 | { FR_AB_GM_CFG2, | ||
1021 | EFX_OWORD32(0x00007337, 0x00000000, 0x00000000, 0x00000000) }, | ||
1022 | { FR_AB_GMF_CFG0, | ||
1023 | EFX_OWORD32(0x00001F1F, 0x00000000, 0x00000000, 0x00000000) }, | ||
1024 | { FR_AB_XM_GLB_CFG, | ||
1025 | EFX_OWORD32(0x00000C68, 0x00000000, 0x00000000, 0x00000000) }, | ||
1026 | { FR_AB_XM_TX_CFG, | ||
1027 | EFX_OWORD32(0x00080164, 0x00000000, 0x00000000, 0x00000000) }, | ||
1028 | { FR_AB_XM_RX_CFG, | ||
1029 | EFX_OWORD32(0x07100A0C, 0x00000000, 0x00000000, 0x00000000) }, | ||
1030 | { FR_AB_XM_RX_PARAM, | ||
1031 | EFX_OWORD32(0x00001FF8, 0x00000000, 0x00000000, 0x00000000) }, | ||
1032 | { FR_AB_XM_FC, | ||
1033 | EFX_OWORD32(0xFFFF0001, 0x00000000, 0x00000000, 0x00000000) }, | ||
1034 | { FR_AB_XM_ADR_LO, | ||
1035 | EFX_OWORD32(0xFFFFFFFF, 0x00000000, 0x00000000, 0x00000000) }, | ||
1036 | { FR_AB_XX_SD_CTL, | ||
1037 | EFX_OWORD32(0x0003FF0F, 0x00000000, 0x00000000, 0x00000000) }, | ||
1038 | }; | ||
1039 | |||
1040 | static int | ||
1041 | falcon_b0_test_chip(struct efx_nic *efx, struct efx_self_tests *tests) | ||
1042 | { | ||
1043 | enum reset_type reset_method = RESET_TYPE_INVISIBLE; | ||
1044 | int rc, rc2; | ||
1045 | |||
1046 | mutex_lock(&efx->mac_lock); | ||
1047 | if (efx->loopback_modes) { | ||
1048 | /* We need the 312 clock from the PHY to test the XMAC | ||
1049 | * registers, so move into XGMII loopback if available */ | ||
1050 | if (efx->loopback_modes & (1 << LOOPBACK_XGMII)) | ||
1051 | efx->loopback_mode = LOOPBACK_XGMII; | ||
1052 | else | ||
1053 | efx->loopback_mode = __ffs(efx->loopback_modes); | ||
1054 | } | ||
1055 | __efx_reconfigure_port(efx); | ||
1056 | mutex_unlock(&efx->mac_lock); | ||
1057 | |||
1058 | efx_reset_down(efx, reset_method); | ||
1059 | |||
1060 | tests->registers = | ||
1061 | efx_nic_test_registers(efx, falcon_b0_register_tests, | ||
1062 | ARRAY_SIZE(falcon_b0_register_tests)) | ||
1063 | ? -1 : 1; | ||
1064 | |||
1065 | rc = falcon_reset_hw(efx, reset_method); | ||
1066 | rc2 = efx_reset_up(efx, reset_method, rc == 0); | ||
1067 | return rc ? rc : rc2; | ||
1068 | } | ||
1069 | |||
1070 | /************************************************************************** | ||
1071 | * | ||
1072 | * Device reset | ||
1073 | * | ||
1074 | ************************************************************************** | ||
1075 | */ | ||
1076 | |||
1077 | static enum reset_type falcon_map_reset_reason(enum reset_type reason) | ||
1078 | { | ||
1079 | switch (reason) { | ||
1080 | case RESET_TYPE_RX_RECOVERY: | ||
1081 | case RESET_TYPE_RX_DESC_FETCH: | ||
1082 | case RESET_TYPE_TX_DESC_FETCH: | ||
1083 | case RESET_TYPE_TX_SKIP: | ||
1084 | /* These can occasionally occur due to hardware bugs. | ||
1085 | * We try to reset without disrupting the link. | ||
1086 | */ | ||
1087 | return RESET_TYPE_INVISIBLE; | ||
1088 | default: | ||
1089 | return RESET_TYPE_ALL; | ||
1090 | } | ||
1091 | } | ||
1092 | |||
1093 | static int falcon_map_reset_flags(u32 *flags) | ||
1094 | { | ||
1095 | enum { | ||
1096 | FALCON_RESET_INVISIBLE = (ETH_RESET_DMA | ETH_RESET_FILTER | | ||
1097 | ETH_RESET_OFFLOAD | ETH_RESET_MAC), | ||
1098 | FALCON_RESET_ALL = FALCON_RESET_INVISIBLE | ETH_RESET_PHY, | ||
1099 | FALCON_RESET_WORLD = FALCON_RESET_ALL | ETH_RESET_IRQ, | ||
1100 | }; | ||
1101 | |||
1102 | if ((*flags & FALCON_RESET_WORLD) == FALCON_RESET_WORLD) { | ||
1103 | *flags &= ~FALCON_RESET_WORLD; | ||
1104 | return RESET_TYPE_WORLD; | ||
1105 | } | ||
1106 | |||
1107 | if ((*flags & FALCON_RESET_ALL) == FALCON_RESET_ALL) { | ||
1108 | *flags &= ~FALCON_RESET_ALL; | ||
1109 | return RESET_TYPE_ALL; | ||
1110 | } | ||
1111 | |||
1112 | if ((*flags & FALCON_RESET_INVISIBLE) == FALCON_RESET_INVISIBLE) { | ||
1113 | *flags &= ~FALCON_RESET_INVISIBLE; | ||
1114 | return RESET_TYPE_INVISIBLE; | ||
1115 | } | ||
1116 | |||
1117 | return -EINVAL; | ||
1118 | } | ||
1119 | |||
1120 | /* Resets NIC to known state. This routine must be called in process | ||
1121 | * context and is allowed to sleep. */ | ||
1122 | static int __falcon_reset_hw(struct efx_nic *efx, enum reset_type method) | ||
1123 | { | ||
1124 | struct falcon_nic_data *nic_data = efx->nic_data; | ||
1125 | efx_oword_t glb_ctl_reg_ker; | ||
1126 | int rc; | ||
1127 | |||
1128 | netif_dbg(efx, hw, efx->net_dev, "performing %s hardware reset\n", | ||
1129 | RESET_TYPE(method)); | ||
1130 | |||
1131 | /* Initiate device reset */ | ||
1132 | if (method == RESET_TYPE_WORLD) { | ||
1133 | rc = pci_save_state(efx->pci_dev); | ||
1134 | if (rc) { | ||
1135 | netif_err(efx, drv, efx->net_dev, | ||
1136 | "failed to backup PCI state of primary " | ||
1137 | "function prior to hardware reset\n"); | ||
1138 | goto fail1; | ||
1139 | } | ||
1140 | if (efx_nic_is_dual_func(efx)) { | ||
1141 | rc = pci_save_state(nic_data->pci_dev2); | ||
1142 | if (rc) { | ||
1143 | netif_err(efx, drv, efx->net_dev, | ||
1144 | "failed to backup PCI state of " | ||
1145 | "secondary function prior to " | ||
1146 | "hardware reset\n"); | ||
1147 | goto fail2; | ||
1148 | } | ||
1149 | } | ||
1150 | |||
1151 | EFX_POPULATE_OWORD_2(glb_ctl_reg_ker, | ||
1152 | FRF_AB_EXT_PHY_RST_DUR, | ||
1153 | FFE_AB_EXT_PHY_RST_DUR_10240US, | ||
1154 | FRF_AB_SWRST, 1); | ||
1155 | } else { | ||
1156 | EFX_POPULATE_OWORD_7(glb_ctl_reg_ker, | ||
1157 | /* exclude PHY from "invisible" reset */ | ||
1158 | FRF_AB_EXT_PHY_RST_CTL, | ||
1159 | method == RESET_TYPE_INVISIBLE, | ||
1160 | /* exclude EEPROM/flash and PCIe */ | ||
1161 | FRF_AB_PCIE_CORE_RST_CTL, 1, | ||
1162 | FRF_AB_PCIE_NSTKY_RST_CTL, 1, | ||
1163 | FRF_AB_PCIE_SD_RST_CTL, 1, | ||
1164 | FRF_AB_EE_RST_CTL, 1, | ||
1165 | FRF_AB_EXT_PHY_RST_DUR, | ||
1166 | FFE_AB_EXT_PHY_RST_DUR_10240US, | ||
1167 | FRF_AB_SWRST, 1); | ||
1168 | } | ||
1169 | efx_writeo(efx, &glb_ctl_reg_ker, FR_AB_GLB_CTL); | ||
1170 | |||
1171 | netif_dbg(efx, hw, efx->net_dev, "waiting for hardware reset\n"); | ||
1172 | schedule_timeout_uninterruptible(HZ / 20); | ||
1173 | |||
1174 | /* Restore PCI configuration if needed */ | ||
1175 | if (method == RESET_TYPE_WORLD) { | ||
1176 | if (efx_nic_is_dual_func(efx)) | ||
1177 | pci_restore_state(nic_data->pci_dev2); | ||
1178 | pci_restore_state(efx->pci_dev); | ||
1179 | netif_dbg(efx, drv, efx->net_dev, | ||
1180 | "successfully restored PCI config\n"); | ||
1181 | } | ||
1182 | |||
1183 | /* Assert that reset complete */ | ||
1184 | efx_reado(efx, &glb_ctl_reg_ker, FR_AB_GLB_CTL); | ||
1185 | if (EFX_OWORD_FIELD(glb_ctl_reg_ker, FRF_AB_SWRST) != 0) { | ||
1186 | rc = -ETIMEDOUT; | ||
1187 | netif_err(efx, hw, efx->net_dev, | ||
1188 | "timed out waiting for hardware reset\n"); | ||
1189 | goto fail3; | ||
1190 | } | ||
1191 | netif_dbg(efx, hw, efx->net_dev, "hardware reset complete\n"); | ||
1192 | |||
1193 | return 0; | ||
1194 | |||
1195 | /* pci_save_state() and pci_restore_state() MUST be called in pairs */ | ||
1196 | fail2: | ||
1197 | pci_restore_state(efx->pci_dev); | ||
1198 | fail1: | ||
1199 | fail3: | ||
1200 | return rc; | ||
1201 | } | ||
1202 | |||
1203 | static int falcon_reset_hw(struct efx_nic *efx, enum reset_type method) | ||
1204 | { | ||
1205 | struct falcon_nic_data *nic_data = efx->nic_data; | ||
1206 | int rc; | ||
1207 | |||
1208 | mutex_lock(&nic_data->spi_lock); | ||
1209 | rc = __falcon_reset_hw(efx, method); | ||
1210 | mutex_unlock(&nic_data->spi_lock); | ||
1211 | |||
1212 | return rc; | ||
1213 | } | ||
1214 | |||
1215 | static void falcon_monitor(struct efx_nic *efx) | ||
1216 | { | ||
1217 | bool link_changed; | ||
1218 | int rc; | ||
1219 | |||
1220 | BUG_ON(!mutex_is_locked(&efx->mac_lock)); | ||
1221 | |||
1222 | rc = falcon_board(efx)->type->monitor(efx); | ||
1223 | if (rc) { | ||
1224 | netif_err(efx, hw, efx->net_dev, | ||
1225 | "Board sensor %s; shutting down PHY\n", | ||
1226 | (rc == -ERANGE) ? "reported fault" : "failed"); | ||
1227 | efx->phy_mode |= PHY_MODE_LOW_POWER; | ||
1228 | rc = __efx_reconfigure_port(efx); | ||
1229 | WARN_ON(rc); | ||
1230 | } | ||
1231 | |||
1232 | if (LOOPBACK_INTERNAL(efx)) | ||
1233 | link_changed = falcon_loopback_link_poll(efx); | ||
1234 | else | ||
1235 | link_changed = efx->phy_op->poll(efx); | ||
1236 | |||
1237 | if (link_changed) { | ||
1238 | falcon_stop_nic_stats(efx); | ||
1239 | falcon_deconfigure_mac_wrapper(efx); | ||
1240 | |||
1241 | falcon_reset_macs(efx); | ||
1242 | rc = falcon_reconfigure_xmac(efx); | ||
1243 | BUG_ON(rc); | ||
1244 | |||
1245 | falcon_start_nic_stats(efx); | ||
1246 | |||
1247 | efx_link_status_changed(efx); | ||
1248 | } | ||
1249 | |||
1250 | falcon_poll_xmac(efx); | ||
1251 | } | ||
1252 | |||
1253 | /* Zeroes out the SRAM contents. This routine must be called in | ||
1254 | * process context and is allowed to sleep. | ||
1255 | */ | ||
1256 | static int falcon_reset_sram(struct efx_nic *efx) | ||
1257 | { | ||
1258 | efx_oword_t srm_cfg_reg_ker, gpio_cfg_reg_ker; | ||
1259 | int count; | ||
1260 | |||
1261 | /* Set the SRAM wake/sleep GPIO appropriately. */ | ||
1262 | efx_reado(efx, &gpio_cfg_reg_ker, FR_AB_GPIO_CTL); | ||
1263 | EFX_SET_OWORD_FIELD(gpio_cfg_reg_ker, FRF_AB_GPIO1_OEN, 1); | ||
1264 | EFX_SET_OWORD_FIELD(gpio_cfg_reg_ker, FRF_AB_GPIO1_OUT, 1); | ||
1265 | efx_writeo(efx, &gpio_cfg_reg_ker, FR_AB_GPIO_CTL); | ||
1266 | |||
1267 | /* Initiate SRAM reset */ | ||
1268 | EFX_POPULATE_OWORD_2(srm_cfg_reg_ker, | ||
1269 | FRF_AZ_SRM_INIT_EN, 1, | ||
1270 | FRF_AZ_SRM_NB_SZ, 0); | ||
1271 | efx_writeo(efx, &srm_cfg_reg_ker, FR_AZ_SRM_CFG); | ||
1272 | |||
1273 | /* Wait for SRAM reset to complete */ | ||
1274 | count = 0; | ||
1275 | do { | ||
1276 | netif_dbg(efx, hw, efx->net_dev, | ||
1277 | "waiting for SRAM reset (attempt %d)...\n", count); | ||
1278 | |||
1279 | /* SRAM reset is slow; expect around 16ms */ | ||
1280 | schedule_timeout_uninterruptible(HZ / 50); | ||
1281 | |||
1282 | /* Check for reset complete */ | ||
1283 | efx_reado(efx, &srm_cfg_reg_ker, FR_AZ_SRM_CFG); | ||
1284 | if (!EFX_OWORD_FIELD(srm_cfg_reg_ker, FRF_AZ_SRM_INIT_EN)) { | ||
1285 | netif_dbg(efx, hw, efx->net_dev, | ||
1286 | "SRAM reset complete\n"); | ||
1287 | |||
1288 | return 0; | ||
1289 | } | ||
1290 | } while (++count < 20); /* wait up to 0.4 sec */ | ||
1291 | |||
1292 | netif_err(efx, hw, efx->net_dev, "timed out waiting for SRAM reset\n"); | ||
1293 | return -ETIMEDOUT; | ||
1294 | } | ||
1295 | |||
1296 | static void falcon_spi_device_init(struct efx_nic *efx, | ||
1297 | struct efx_spi_device *spi_device, | ||
1298 | unsigned int device_id, u32 device_type) | ||
1299 | { | ||
1300 | if (device_type != 0) { | ||
1301 | spi_device->device_id = device_id; | ||
1302 | spi_device->size = | ||
1303 | 1 << SPI_DEV_TYPE_FIELD(device_type, SPI_DEV_TYPE_SIZE); | ||
1304 | spi_device->addr_len = | ||
1305 | SPI_DEV_TYPE_FIELD(device_type, SPI_DEV_TYPE_ADDR_LEN); | ||
1306 | spi_device->munge_address = (spi_device->size == 1 << 9 && | ||
1307 | spi_device->addr_len == 1); | ||
1308 | spi_device->erase_command = | ||
1309 | SPI_DEV_TYPE_FIELD(device_type, SPI_DEV_TYPE_ERASE_CMD); | ||
1310 | spi_device->erase_size = | ||
1311 | 1 << SPI_DEV_TYPE_FIELD(device_type, | ||
1312 | SPI_DEV_TYPE_ERASE_SIZE); | ||
1313 | spi_device->block_size = | ||
1314 | 1 << SPI_DEV_TYPE_FIELD(device_type, | ||
1315 | SPI_DEV_TYPE_BLOCK_SIZE); | ||
1316 | } else { | ||
1317 | spi_device->size = 0; | ||
1318 | } | ||
1319 | } | ||
1320 | |||
1321 | /* Extract non-volatile configuration */ | ||
1322 | static int falcon_probe_nvconfig(struct efx_nic *efx) | ||
1323 | { | ||
1324 | struct falcon_nic_data *nic_data = efx->nic_data; | ||
1325 | struct falcon_nvconfig *nvconfig; | ||
1326 | int rc; | ||
1327 | |||
1328 | nvconfig = kmalloc(sizeof(*nvconfig), GFP_KERNEL); | ||
1329 | if (!nvconfig) | ||
1330 | return -ENOMEM; | ||
1331 | |||
1332 | rc = falcon_read_nvram(efx, nvconfig); | ||
1333 | if (rc) | ||
1334 | goto out; | ||
1335 | |||
1336 | efx->phy_type = nvconfig->board_v2.port0_phy_type; | ||
1337 | efx->mdio.prtad = nvconfig->board_v2.port0_phy_addr; | ||
1338 | |||
1339 | if (le16_to_cpu(nvconfig->board_struct_ver) >= 3) { | ||
1340 | falcon_spi_device_init( | ||
1341 | efx, &nic_data->spi_flash, FFE_AB_SPI_DEVICE_FLASH, | ||
1342 | le32_to_cpu(nvconfig->board_v3 | ||
1343 | .spi_device_type[FFE_AB_SPI_DEVICE_FLASH])); | ||
1344 | falcon_spi_device_init( | ||
1345 | efx, &nic_data->spi_eeprom, FFE_AB_SPI_DEVICE_EEPROM, | ||
1346 | le32_to_cpu(nvconfig->board_v3 | ||
1347 | .spi_device_type[FFE_AB_SPI_DEVICE_EEPROM])); | ||
1348 | } | ||
1349 | |||
1350 | /* Read the MAC addresses */ | ||
1351 | memcpy(efx->net_dev->perm_addr, nvconfig->mac_address[0], ETH_ALEN); | ||
1352 | |||
1353 | netif_dbg(efx, probe, efx->net_dev, "PHY is %d phy_id %d\n", | ||
1354 | efx->phy_type, efx->mdio.prtad); | ||
1355 | |||
1356 | rc = falcon_probe_board(efx, | ||
1357 | le16_to_cpu(nvconfig->board_v2.board_revision)); | ||
1358 | out: | ||
1359 | kfree(nvconfig); | ||
1360 | return rc; | ||
1361 | } | ||
1362 | |||
1363 | static void falcon_dimension_resources(struct efx_nic *efx) | ||
1364 | { | ||
1365 | efx->rx_dc_base = 0x20000; | ||
1366 | efx->tx_dc_base = 0x26000; | ||
1367 | } | ||
1368 | |||
1369 | /* Probe all SPI devices on the NIC */ | ||
1370 | static void falcon_probe_spi_devices(struct efx_nic *efx) | ||
1371 | { | ||
1372 | struct falcon_nic_data *nic_data = efx->nic_data; | ||
1373 | efx_oword_t nic_stat, gpio_ctl, ee_vpd_cfg; | ||
1374 | int boot_dev; | ||
1375 | |||
1376 | efx_reado(efx, &gpio_ctl, FR_AB_GPIO_CTL); | ||
1377 | efx_reado(efx, &nic_stat, FR_AB_NIC_STAT); | ||
1378 | efx_reado(efx, &ee_vpd_cfg, FR_AB_EE_VPD_CFG0); | ||
1379 | |||
1380 | if (EFX_OWORD_FIELD(gpio_ctl, FRF_AB_GPIO3_PWRUP_VALUE)) { | ||
1381 | boot_dev = (EFX_OWORD_FIELD(nic_stat, FRF_AB_SF_PRST) ? | ||
1382 | FFE_AB_SPI_DEVICE_FLASH : FFE_AB_SPI_DEVICE_EEPROM); | ||
1383 | netif_dbg(efx, probe, efx->net_dev, "Booted from %s\n", | ||
1384 | boot_dev == FFE_AB_SPI_DEVICE_FLASH ? | ||
1385 | "flash" : "EEPROM"); | ||
1386 | } else { | ||
1387 | /* Disable VPD and set clock dividers to safe | ||
1388 | * values for initial programming. */ | ||
1389 | boot_dev = -1; | ||
1390 | netif_dbg(efx, probe, efx->net_dev, | ||
1391 | "Booted from internal ASIC settings;" | ||
1392 | " setting SPI config\n"); | ||
1393 | EFX_POPULATE_OWORD_3(ee_vpd_cfg, FRF_AB_EE_VPD_EN, 0, | ||
1394 | /* 125 MHz / 7 ~= 20 MHz */ | ||
1395 | FRF_AB_EE_SF_CLOCK_DIV, 7, | ||
1396 | /* 125 MHz / 63 ~= 2 MHz */ | ||
1397 | FRF_AB_EE_EE_CLOCK_DIV, 63); | ||
1398 | efx_writeo(efx, &ee_vpd_cfg, FR_AB_EE_VPD_CFG0); | ||
1399 | } | ||
1400 | |||
1401 | mutex_init(&nic_data->spi_lock); | ||
1402 | |||
1403 | if (boot_dev == FFE_AB_SPI_DEVICE_FLASH) | ||
1404 | falcon_spi_device_init(efx, &nic_data->spi_flash, | ||
1405 | FFE_AB_SPI_DEVICE_FLASH, | ||
1406 | default_flash_type); | ||
1407 | if (boot_dev == FFE_AB_SPI_DEVICE_EEPROM) | ||
1408 | falcon_spi_device_init(efx, &nic_data->spi_eeprom, | ||
1409 | FFE_AB_SPI_DEVICE_EEPROM, | ||
1410 | large_eeprom_type); | ||
1411 | } | ||
1412 | |||
1413 | static int falcon_probe_nic(struct efx_nic *efx) | ||
1414 | { | ||
1415 | struct falcon_nic_data *nic_data; | ||
1416 | struct falcon_board *board; | ||
1417 | int rc; | ||
1418 | |||
1419 | /* Allocate storage for hardware specific data */ | ||
1420 | nic_data = kzalloc(sizeof(*nic_data), GFP_KERNEL); | ||
1421 | if (!nic_data) | ||
1422 | return -ENOMEM; | ||
1423 | efx->nic_data = nic_data; | ||
1424 | |||
1425 | rc = -ENODEV; | ||
1426 | |||
1427 | if (efx_nic_fpga_ver(efx) != 0) { | ||
1428 | netif_err(efx, probe, efx->net_dev, | ||
1429 | "Falcon FPGA not supported\n"); | ||
1430 | goto fail1; | ||
1431 | } | ||
1432 | |||
1433 | if (efx_nic_rev(efx) <= EFX_REV_FALCON_A1) { | ||
1434 | efx_oword_t nic_stat; | ||
1435 | struct pci_dev *dev; | ||
1436 | u8 pci_rev = efx->pci_dev->revision; | ||
1437 | |||
1438 | if ((pci_rev == 0xff) || (pci_rev == 0)) { | ||
1439 | netif_err(efx, probe, efx->net_dev, | ||
1440 | "Falcon rev A0 not supported\n"); | ||
1441 | goto fail1; | ||
1442 | } | ||
1443 | efx_reado(efx, &nic_stat, FR_AB_NIC_STAT); | ||
1444 | if (EFX_OWORD_FIELD(nic_stat, FRF_AB_STRAP_10G) == 0) { | ||
1445 | netif_err(efx, probe, efx->net_dev, | ||
1446 | "Falcon rev A1 1G not supported\n"); | ||
1447 | goto fail1; | ||
1448 | } | ||
1449 | if (EFX_OWORD_FIELD(nic_stat, FRF_AA_STRAP_PCIE) == 0) { | ||
1450 | netif_err(efx, probe, efx->net_dev, | ||
1451 | "Falcon rev A1 PCI-X not supported\n"); | ||
1452 | goto fail1; | ||
1453 | } | ||
1454 | |||
1455 | dev = pci_dev_get(efx->pci_dev); | ||
1456 | while ((dev = pci_get_device(PCI_VENDOR_ID_SOLARFLARE, | ||
1457 | PCI_DEVICE_ID_SOLARFLARE_SFC4000A_1, | ||
1458 | dev))) { | ||
1459 | if (dev->bus == efx->pci_dev->bus && | ||
1460 | dev->devfn == efx->pci_dev->devfn + 1) { | ||
1461 | nic_data->pci_dev2 = dev; | ||
1462 | break; | ||
1463 | } | ||
1464 | } | ||
1465 | if (!nic_data->pci_dev2) { | ||
1466 | netif_err(efx, probe, efx->net_dev, | ||
1467 | "failed to find secondary function\n"); | ||
1468 | rc = -ENODEV; | ||
1469 | goto fail2; | ||
1470 | } | ||
1471 | } | ||
1472 | |||
1473 | /* Now we can reset the NIC */ | ||
1474 | rc = __falcon_reset_hw(efx, RESET_TYPE_ALL); | ||
1475 | if (rc) { | ||
1476 | netif_err(efx, probe, efx->net_dev, "failed to reset NIC\n"); | ||
1477 | goto fail3; | ||
1478 | } | ||
1479 | |||
1480 | /* Allocate memory for INT_KER */ | ||
1481 | rc = efx_nic_alloc_buffer(efx, &efx->irq_status, sizeof(efx_oword_t)); | ||
1482 | if (rc) | ||
1483 | goto fail4; | ||
1484 | BUG_ON(efx->irq_status.dma_addr & 0x0f); | ||
1485 | |||
1486 | netif_dbg(efx, probe, efx->net_dev, | ||
1487 | "INT_KER at %llx (virt %p phys %llx)\n", | ||
1488 | (u64)efx->irq_status.dma_addr, | ||
1489 | efx->irq_status.addr, | ||
1490 | (u64)virt_to_phys(efx->irq_status.addr)); | ||
1491 | |||
1492 | falcon_probe_spi_devices(efx); | ||
1493 | |||
1494 | /* Read in the non-volatile configuration */ | ||
1495 | rc = falcon_probe_nvconfig(efx); | ||
1496 | if (rc) { | ||
1497 | if (rc == -EINVAL) | ||
1498 | netif_err(efx, probe, efx->net_dev, "NVRAM is invalid\n"); | ||
1499 | goto fail5; | ||
1500 | } | ||
1501 | |||
1502 | efx->timer_quantum_ns = 4968; /* 621 cycles */ | ||
1503 | |||
1504 | /* Initialise I2C adapter */ | ||
1505 | board = falcon_board(efx); | ||
1506 | board->i2c_adap.owner = THIS_MODULE; | ||
1507 | board->i2c_data = falcon_i2c_bit_operations; | ||
1508 | board->i2c_data.data = efx; | ||
1509 | board->i2c_adap.algo_data = &board->i2c_data; | ||
1510 | board->i2c_adap.dev.parent = &efx->pci_dev->dev; | ||
1511 | strlcpy(board->i2c_adap.name, "SFC4000 GPIO", | ||
1512 | sizeof(board->i2c_adap.name)); | ||
1513 | rc = i2c_bit_add_bus(&board->i2c_adap); | ||
1514 | if (rc) | ||
1515 | goto fail5; | ||
1516 | |||
1517 | rc = falcon_board(efx)->type->init(efx); | ||
1518 | if (rc) { | ||
1519 | netif_err(efx, probe, efx->net_dev, | ||
1520 | "failed to initialise board\n"); | ||
1521 | goto fail6; | ||
1522 | } | ||
1523 | |||
1524 | nic_data->stats_disable_count = 1; | ||
1525 | setup_timer(&nic_data->stats_timer, &falcon_stats_timer_func, | ||
1526 | (unsigned long)efx); | ||
1527 | |||
1528 | return 0; | ||
1529 | |||
1530 | fail6: | ||
1531 | BUG_ON(i2c_del_adapter(&board->i2c_adap)); | ||
1532 | memset(&board->i2c_adap, 0, sizeof(board->i2c_adap)); | ||
1533 | fail5: | ||
1534 | efx_nic_free_buffer(efx, &efx->irq_status); | ||
1535 | fail4: | ||
1536 | fail3: | ||
1537 | if (nic_data->pci_dev2) { | ||
1538 | pci_dev_put(nic_data->pci_dev2); | ||
1539 | nic_data->pci_dev2 = NULL; | ||
1540 | } | ||
1541 | fail2: | ||
1542 | fail1: | ||
1543 | kfree(efx->nic_data); | ||
1544 | return rc; | ||
1545 | } | ||
1546 | |||
1547 | static void falcon_init_rx_cfg(struct efx_nic *efx) | ||
1548 | { | ||
1549 | /* Prior to Siena the RX DMA engine will split each frame at | ||
1550 | * intervals of RX_USR_BUF_SIZE (32-byte units). We set it to | ||
1551 | * be so large that that never happens. */ | ||
1552 | const unsigned huge_buf_size = (3 * 4096) >> 5; | ||
1553 | /* RX control FIFO thresholds (32 entries) */ | ||
1554 | const unsigned ctrl_xon_thr = 20; | ||
1555 | const unsigned ctrl_xoff_thr = 25; | ||
1556 | efx_oword_t reg; | ||
1557 | |||
1558 | efx_reado(efx, ®, FR_AZ_RX_CFG); | ||
1559 | if (efx_nic_rev(efx) <= EFX_REV_FALCON_A1) { | ||
1560 | /* Data FIFO size is 5.5K */ | ||
1561 | EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_DESC_PUSH_EN, 0); | ||
1562 | EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_USR_BUF_SIZE, | ||
1563 | huge_buf_size); | ||
1564 | EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_XON_MAC_TH, 512 >> 8); | ||
1565 | EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_XOFF_MAC_TH, 2048 >> 8); | ||
1566 | EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_XON_TX_TH, ctrl_xon_thr); | ||
1567 | EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_XOFF_TX_TH, ctrl_xoff_thr); | ||
1568 | } else { | ||
1569 | /* Data FIFO size is 80K; register fields moved */ | ||
1570 | EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_DESC_PUSH_EN, 0); | ||
1571 | EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_USR_BUF_SIZE, | ||
1572 | huge_buf_size); | ||
1573 | /* Send XON and XOFF at ~3 * max MTU away from empty/full */ | ||
1574 | EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_XON_MAC_TH, 27648 >> 8); | ||
1575 | EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_XOFF_MAC_TH, 54272 >> 8); | ||
1576 | EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_XON_TX_TH, ctrl_xon_thr); | ||
1577 | EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_XOFF_TX_TH, ctrl_xoff_thr); | ||
1578 | EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_INGR_EN, 1); | ||
1579 | |||
1580 | /* Enable hash insertion. This is broken for the | ||
1581 | * 'Falcon' hash so also select Toeplitz TCP/IPv4 and | ||
1582 | * IPv4 hashes. */ | ||
1583 | EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_HASH_INSRT_HDR, 1); | ||
1584 | EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_HASH_ALG, 1); | ||
1585 | EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_IP_HASH, 1); | ||
1586 | } | ||
1587 | /* Always enable XOFF signal from RX FIFO. We enable | ||
1588 | * or disable transmission of pause frames at the MAC. */ | ||
1589 | EFX_SET_OWORD_FIELD(reg, FRF_AZ_RX_XOFF_MAC_EN, 1); | ||
1590 | efx_writeo(efx, ®, FR_AZ_RX_CFG); | ||
1591 | } | ||
1592 | |||
1593 | /* This call performs hardware-specific global initialisation, such as | ||
1594 | * defining the descriptor cache sizes and number of RSS channels. | ||
1595 | * It does not set up any buffers, descriptor rings or event queues. | ||
1596 | */ | ||
1597 | static int falcon_init_nic(struct efx_nic *efx) | ||
1598 | { | ||
1599 | efx_oword_t temp; | ||
1600 | int rc; | ||
1601 | |||
1602 | /* Use on-chip SRAM */ | ||
1603 | efx_reado(efx, &temp, FR_AB_NIC_STAT); | ||
1604 | EFX_SET_OWORD_FIELD(temp, FRF_AB_ONCHIP_SRAM, 1); | ||
1605 | efx_writeo(efx, &temp, FR_AB_NIC_STAT); | ||
1606 | |||
1607 | rc = falcon_reset_sram(efx); | ||
1608 | if (rc) | ||
1609 | return rc; | ||
1610 | |||
1611 | /* Clear the parity enables on the TX data fifos as | ||
1612 | * they produce false parity errors because of timing issues | ||
1613 | */ | ||
1614 | if (EFX_WORKAROUND_5129(efx)) { | ||
1615 | efx_reado(efx, &temp, FR_AZ_CSR_SPARE); | ||
1616 | EFX_SET_OWORD_FIELD(temp, FRF_AB_MEM_PERR_EN_TX_DATA, 0); | ||
1617 | efx_writeo(efx, &temp, FR_AZ_CSR_SPARE); | ||
1618 | } | ||
1619 | |||
1620 | if (EFX_WORKAROUND_7244(efx)) { | ||
1621 | efx_reado(efx, &temp, FR_BZ_RX_FILTER_CTL); | ||
1622 | EFX_SET_OWORD_FIELD(temp, FRF_BZ_UDP_FULL_SRCH_LIMIT, 8); | ||
1623 | EFX_SET_OWORD_FIELD(temp, FRF_BZ_UDP_WILD_SRCH_LIMIT, 8); | ||
1624 | EFX_SET_OWORD_FIELD(temp, FRF_BZ_TCP_FULL_SRCH_LIMIT, 8); | ||
1625 | EFX_SET_OWORD_FIELD(temp, FRF_BZ_TCP_WILD_SRCH_LIMIT, 8); | ||
1626 | efx_writeo(efx, &temp, FR_BZ_RX_FILTER_CTL); | ||
1627 | } | ||
1628 | |||
1629 | /* XXX This is documented only for Falcon A0/A1 */ | ||
1630 | /* Setup RX. Wait for descriptor is broken and must | ||
1631 | * be disabled. RXDP recovery shouldn't be needed, but is. | ||
1632 | */ | ||
1633 | efx_reado(efx, &temp, FR_AA_RX_SELF_RST); | ||
1634 | EFX_SET_OWORD_FIELD(temp, FRF_AA_RX_NODESC_WAIT_DIS, 1); | ||
1635 | EFX_SET_OWORD_FIELD(temp, FRF_AA_RX_SELF_RST_EN, 1); | ||
1636 | if (EFX_WORKAROUND_5583(efx)) | ||
1637 | EFX_SET_OWORD_FIELD(temp, FRF_AA_RX_ISCSI_DIS, 1); | ||
1638 | efx_writeo(efx, &temp, FR_AA_RX_SELF_RST); | ||
1639 | |||
1640 | /* Do not enable TX_NO_EOP_DISC_EN, since it limits packets to 16 | ||
1641 | * descriptors (which is bad). | ||
1642 | */ | ||
1643 | efx_reado(efx, &temp, FR_AZ_TX_CFG); | ||
1644 | EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_NO_EOP_DISC_EN, 0); | ||
1645 | efx_writeo(efx, &temp, FR_AZ_TX_CFG); | ||
1646 | |||
1647 | falcon_init_rx_cfg(efx); | ||
1648 | |||
1649 | if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0) { | ||
1650 | /* Set hash key for IPv4 */ | ||
1651 | memcpy(&temp, efx->rx_hash_key, sizeof(temp)); | ||
1652 | efx_writeo(efx, &temp, FR_BZ_RX_RSS_TKEY); | ||
1653 | |||
1654 | /* Set destination of both TX and RX Flush events */ | ||
1655 | EFX_POPULATE_OWORD_1(temp, FRF_BZ_FLS_EVQ_ID, 0); | ||
1656 | efx_writeo(efx, &temp, FR_BZ_DP_CTRL); | ||
1657 | } | ||
1658 | |||
1659 | efx_nic_init_common(efx); | ||
1660 | |||
1661 | return 0; | ||
1662 | } | ||
1663 | |||
1664 | static void falcon_remove_nic(struct efx_nic *efx) | ||
1665 | { | ||
1666 | struct falcon_nic_data *nic_data = efx->nic_data; | ||
1667 | struct falcon_board *board = falcon_board(efx); | ||
1668 | int rc; | ||
1669 | |||
1670 | board->type->fini(efx); | ||
1671 | |||
1672 | /* Remove I2C adapter and clear it in preparation for a retry */ | ||
1673 | rc = i2c_del_adapter(&board->i2c_adap); | ||
1674 | BUG_ON(rc); | ||
1675 | memset(&board->i2c_adap, 0, sizeof(board->i2c_adap)); | ||
1676 | |||
1677 | efx_nic_free_buffer(efx, &efx->irq_status); | ||
1678 | |||
1679 | __falcon_reset_hw(efx, RESET_TYPE_ALL); | ||
1680 | |||
1681 | /* Release the second function after the reset */ | ||
1682 | if (nic_data->pci_dev2) { | ||
1683 | pci_dev_put(nic_data->pci_dev2); | ||
1684 | nic_data->pci_dev2 = NULL; | ||
1685 | } | ||
1686 | |||
1687 | /* Tear down the private nic state */ | ||
1688 | kfree(efx->nic_data); | ||
1689 | efx->nic_data = NULL; | ||
1690 | } | ||
1691 | |||
1692 | static void falcon_update_nic_stats(struct efx_nic *efx) | ||
1693 | { | ||
1694 | struct falcon_nic_data *nic_data = efx->nic_data; | ||
1695 | efx_oword_t cnt; | ||
1696 | |||
1697 | if (nic_data->stats_disable_count) | ||
1698 | return; | ||
1699 | |||
1700 | efx_reado(efx, &cnt, FR_AZ_RX_NODESC_DROP); | ||
1701 | efx->n_rx_nodesc_drop_cnt += | ||
1702 | EFX_OWORD_FIELD(cnt, FRF_AB_RX_NODESC_DROP_CNT); | ||
1703 | |||
1704 | if (nic_data->stats_pending && | ||
1705 | *nic_data->stats_dma_done == FALCON_STATS_DONE) { | ||
1706 | nic_data->stats_pending = false; | ||
1707 | rmb(); /* read the done flag before the stats */ | ||
1708 | falcon_update_stats_xmac(efx); | ||
1709 | } | ||
1710 | } | ||
1711 | |||
1712 | void falcon_start_nic_stats(struct efx_nic *efx) | ||
1713 | { | ||
1714 | struct falcon_nic_data *nic_data = efx->nic_data; | ||
1715 | |||
1716 | spin_lock_bh(&efx->stats_lock); | ||
1717 | if (--nic_data->stats_disable_count == 0) | ||
1718 | falcon_stats_request(efx); | ||
1719 | spin_unlock_bh(&efx->stats_lock); | ||
1720 | } | ||
1721 | |||
1722 | void falcon_stop_nic_stats(struct efx_nic *efx) | ||
1723 | { | ||
1724 | struct falcon_nic_data *nic_data = efx->nic_data; | ||
1725 | int i; | ||
1726 | |||
1727 | might_sleep(); | ||
1728 | |||
1729 | spin_lock_bh(&efx->stats_lock); | ||
1730 | ++nic_data->stats_disable_count; | ||
1731 | spin_unlock_bh(&efx->stats_lock); | ||
1732 | |||
1733 | del_timer_sync(&nic_data->stats_timer); | ||
1734 | |||
1735 | /* Wait enough time for the most recent transfer to | ||
1736 | * complete. */ | ||
1737 | for (i = 0; i < 4 && nic_data->stats_pending; i++) { | ||
1738 | if (*nic_data->stats_dma_done == FALCON_STATS_DONE) | ||
1739 | break; | ||
1740 | msleep(1); | ||
1741 | } | ||
1742 | |||
1743 | spin_lock_bh(&efx->stats_lock); | ||
1744 | falcon_stats_complete(efx); | ||
1745 | spin_unlock_bh(&efx->stats_lock); | ||
1746 | } | ||
1747 | |||
1748 | static void falcon_set_id_led(struct efx_nic *efx, enum efx_led_mode mode) | ||
1749 | { | ||
1750 | falcon_board(efx)->type->set_id_led(efx, mode); | ||
1751 | } | ||
1752 | |||
1753 | /************************************************************************** | ||
1754 | * | ||
1755 | * Wake on LAN | ||
1756 | * | ||
1757 | ************************************************************************** | ||
1758 | */ | ||
1759 | |||
1760 | static void falcon_get_wol(struct efx_nic *efx, struct ethtool_wolinfo *wol) | ||
1761 | { | ||
1762 | wol->supported = 0; | ||
1763 | wol->wolopts = 0; | ||
1764 | memset(&wol->sopass, 0, sizeof(wol->sopass)); | ||
1765 | } | ||
1766 | |||
1767 | static int falcon_set_wol(struct efx_nic *efx, u32 type) | ||
1768 | { | ||
1769 | if (type != 0) | ||
1770 | return -EINVAL; | ||
1771 | return 0; | ||
1772 | } | ||
1773 | |||
1774 | /************************************************************************** | ||
1775 | * | ||
1776 | * Revision-dependent attributes used by efx.c and nic.c | ||
1777 | * | ||
1778 | ************************************************************************** | ||
1779 | */ | ||
1780 | |||
1781 | const struct efx_nic_type falcon_a1_nic_type = { | ||
1782 | .probe = falcon_probe_nic, | ||
1783 | .remove = falcon_remove_nic, | ||
1784 | .init = falcon_init_nic, | ||
1785 | .dimension_resources = falcon_dimension_resources, | ||
1786 | .fini = efx_port_dummy_op_void, | ||
1787 | .monitor = falcon_monitor, | ||
1788 | .map_reset_reason = falcon_map_reset_reason, | ||
1789 | .map_reset_flags = falcon_map_reset_flags, | ||
1790 | .reset = falcon_reset_hw, | ||
1791 | .probe_port = falcon_probe_port, | ||
1792 | .remove_port = falcon_remove_port, | ||
1793 | .handle_global_event = falcon_handle_global_event, | ||
1794 | .prepare_flush = falcon_prepare_flush, | ||
1795 | .finish_flush = efx_port_dummy_op_void, | ||
1796 | .update_stats = falcon_update_nic_stats, | ||
1797 | .start_stats = falcon_start_nic_stats, | ||
1798 | .stop_stats = falcon_stop_nic_stats, | ||
1799 | .set_id_led = falcon_set_id_led, | ||
1800 | .push_irq_moderation = falcon_push_irq_moderation, | ||
1801 | .reconfigure_port = falcon_reconfigure_port, | ||
1802 | .reconfigure_mac = falcon_reconfigure_xmac, | ||
1803 | .check_mac_fault = falcon_xmac_check_fault, | ||
1804 | .get_wol = falcon_get_wol, | ||
1805 | .set_wol = falcon_set_wol, | ||
1806 | .resume_wol = efx_port_dummy_op_void, | ||
1807 | .test_nvram = falcon_test_nvram, | ||
1808 | |||
1809 | .revision = EFX_REV_FALCON_A1, | ||
1810 | .mem_map_size = 0x20000, | ||
1811 | .txd_ptr_tbl_base = FR_AA_TX_DESC_PTR_TBL_KER, | ||
1812 | .rxd_ptr_tbl_base = FR_AA_RX_DESC_PTR_TBL_KER, | ||
1813 | .buf_tbl_base = FR_AA_BUF_FULL_TBL_KER, | ||
1814 | .evq_ptr_tbl_base = FR_AA_EVQ_PTR_TBL_KER, | ||
1815 | .evq_rptr_tbl_base = FR_AA_EVQ_RPTR_KER, | ||
1816 | .max_dma_mask = DMA_BIT_MASK(FSF_AZ_TX_KER_BUF_ADDR_WIDTH), | ||
1817 | .rx_buffer_padding = 0x24, | ||
1818 | .max_interrupt_mode = EFX_INT_MODE_MSI, | ||
1819 | .phys_addr_channels = 4, | ||
1820 | .timer_period_max = 1 << FRF_AB_TC_TIMER_VAL_WIDTH, | ||
1821 | .offload_features = NETIF_F_IP_CSUM, | ||
1822 | }; | ||
1823 | |||
1824 | const struct efx_nic_type falcon_b0_nic_type = { | ||
1825 | .probe = falcon_probe_nic, | ||
1826 | .remove = falcon_remove_nic, | ||
1827 | .init = falcon_init_nic, | ||
1828 | .dimension_resources = falcon_dimension_resources, | ||
1829 | .fini = efx_port_dummy_op_void, | ||
1830 | .monitor = falcon_monitor, | ||
1831 | .map_reset_reason = falcon_map_reset_reason, | ||
1832 | .map_reset_flags = falcon_map_reset_flags, | ||
1833 | .reset = falcon_reset_hw, | ||
1834 | .probe_port = falcon_probe_port, | ||
1835 | .remove_port = falcon_remove_port, | ||
1836 | .handle_global_event = falcon_handle_global_event, | ||
1837 | .prepare_flush = falcon_prepare_flush, | ||
1838 | .finish_flush = efx_port_dummy_op_void, | ||
1839 | .update_stats = falcon_update_nic_stats, | ||
1840 | .start_stats = falcon_start_nic_stats, | ||
1841 | .stop_stats = falcon_stop_nic_stats, | ||
1842 | .set_id_led = falcon_set_id_led, | ||
1843 | .push_irq_moderation = falcon_push_irq_moderation, | ||
1844 | .reconfigure_port = falcon_reconfigure_port, | ||
1845 | .reconfigure_mac = falcon_reconfigure_xmac, | ||
1846 | .check_mac_fault = falcon_xmac_check_fault, | ||
1847 | .get_wol = falcon_get_wol, | ||
1848 | .set_wol = falcon_set_wol, | ||
1849 | .resume_wol = efx_port_dummy_op_void, | ||
1850 | .test_chip = falcon_b0_test_chip, | ||
1851 | .test_nvram = falcon_test_nvram, | ||
1852 | |||
1853 | .revision = EFX_REV_FALCON_B0, | ||
1854 | /* Map everything up to and including the RSS indirection | ||
1855 | * table. Don't map MSI-X table, MSI-X PBA since Linux | ||
1856 | * requires that they not be mapped. */ | ||
1857 | .mem_map_size = (FR_BZ_RX_INDIRECTION_TBL + | ||
1858 | FR_BZ_RX_INDIRECTION_TBL_STEP * | ||
1859 | FR_BZ_RX_INDIRECTION_TBL_ROWS), | ||
1860 | .txd_ptr_tbl_base = FR_BZ_TX_DESC_PTR_TBL, | ||
1861 | .rxd_ptr_tbl_base = FR_BZ_RX_DESC_PTR_TBL, | ||
1862 | .buf_tbl_base = FR_BZ_BUF_FULL_TBL, | ||
1863 | .evq_ptr_tbl_base = FR_BZ_EVQ_PTR_TBL, | ||
1864 | .evq_rptr_tbl_base = FR_BZ_EVQ_RPTR, | ||
1865 | .max_dma_mask = DMA_BIT_MASK(FSF_AZ_TX_KER_BUF_ADDR_WIDTH), | ||
1866 | .rx_buffer_hash_size = 0x10, | ||
1867 | .rx_buffer_padding = 0, | ||
1868 | .max_interrupt_mode = EFX_INT_MODE_MSIX, | ||
1869 | .phys_addr_channels = 32, /* Hardware limit is 64, but the legacy | ||
1870 | * interrupt handler only supports 32 | ||
1871 | * channels */ | ||
1872 | .timer_period_max = 1 << FRF_AB_TC_TIMER_VAL_WIDTH, | ||
1873 | .offload_features = NETIF_F_IP_CSUM | NETIF_F_RXHASH | NETIF_F_NTUPLE, | ||
1874 | }; | ||
1875 | |||