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path: root/drivers/net/ethernet/marvell/sky2.c
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Diffstat (limited to 'drivers/net/ethernet/marvell/sky2.c')
-rw-r--r--drivers/net/ethernet/marvell/sky2.c18
1 files changed, 16 insertions, 2 deletions
diff --git a/drivers/net/ethernet/marvell/sky2.c b/drivers/net/ethernet/marvell/sky2.c
index 28a54451a3e..2b0748dba8b 100644
--- a/drivers/net/ethernet/marvell/sky2.c
+++ b/drivers/net/ethernet/marvell/sky2.c
@@ -141,6 +141,7 @@ static DEFINE_PCI_DEVICE_TABLE(sky2_id_table) = {
141 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4370) }, /* 88E8075 */ 141 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4370) }, /* 88E8075 */
142 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4380) }, /* 88E8057 */ 142 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4380) }, /* 88E8057 */
143 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4381) }, /* 88E8059 */ 143 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4381) }, /* 88E8059 */
144 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4382) }, /* 88E8079 */
144 { 0 } 145 { 0 }
145}; 146};
146 147
@@ -3079,8 +3080,10 @@ static irqreturn_t sky2_intr(int irq, void *dev_id)
3079 3080
3080 /* Reading this mask interrupts as side effect */ 3081 /* Reading this mask interrupts as side effect */
3081 status = sky2_read32(hw, B0_Y2_SP_ISRC2); 3082 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
3082 if (status == 0 || status == ~0) 3083 if (status == 0 || status == ~0) {
3084 sky2_write32(hw, B0_Y2_SP_ICR, 2);
3083 return IRQ_NONE; 3085 return IRQ_NONE;
3086 }
3084 3087
3085 prefetch(&hw->st_le[hw->st_idx]); 3088 prefetch(&hw->st_le[hw->st_idx]);
3086 3089
@@ -3349,6 +3352,17 @@ static void sky2_reset(struct sky2_hw *hw)
3349 sky2_pci_write16(hw, pdev->pcie_cap + PCI_EXP_LNKCTL, 3352 sky2_pci_write16(hw, pdev->pcie_cap + PCI_EXP_LNKCTL,
3350 reg); 3353 reg);
3351 3354
3355 if (hw->chip_id == CHIP_ID_YUKON_PRM &&
3356 hw->chip_rev == CHIP_REV_YU_PRM_A0) {
3357 /* change PHY Interrupt polarity to low active */
3358 reg = sky2_read16(hw, GPHY_CTRL);
3359 sky2_write16(hw, GPHY_CTRL, reg | GPC_INTPOL);
3360
3361 /* adapt HW for low active PHY Interrupt */
3362 reg = sky2_read16(hw, Y2_CFG_SPC + PCI_LDO_CTRL);
3363 sky2_write16(hw, Y2_CFG_SPC + PCI_LDO_CTRL, reg | PHY_M_UNDOC1);
3364 }
3365
3352 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 3366 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
3353 3367
3354 /* re-enable PEX PM in PEX PHY debug reg. 8 (clear bit 12) */ 3368 /* re-enable PEX PM in PEX PHY debug reg. 8 (clear bit 12) */
@@ -4871,7 +4885,7 @@ static const char *sky2_name(u8 chipid, char *buf, int sz)
4871 "UL 2", /* 0xba */ 4885 "UL 2", /* 0xba */
4872 "Unknown", /* 0xbb */ 4886 "Unknown", /* 0xbb */
4873 "Optima", /* 0xbc */ 4887 "Optima", /* 0xbc */
4874 "Optima Prime", /* 0xbd */ 4888 "OptimaEEE", /* 0xbd */
4875 "Optima 2", /* 0xbe */ 4889 "Optima 2", /* 0xbe */
4876 }; 4890 };
4877 4891