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path: root/drivers/net/ethernet/broadcom/bnx2.c
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Diffstat (limited to 'drivers/net/ethernet/broadcom/bnx2.c')
-rw-r--r--drivers/net/ethernet/broadcom/bnx2.c93
1 files changed, 86 insertions, 7 deletions
diff --git a/drivers/net/ethernet/broadcom/bnx2.c b/drivers/net/ethernet/broadcom/bnx2.c
index 1fa4927a45b..0ced154129a 100644
--- a/drivers/net/ethernet/broadcom/bnx2.c
+++ b/drivers/net/ethernet/broadcom/bnx2.c
@@ -14,6 +14,7 @@
14#include <linux/module.h> 14#include <linux/module.h>
15#include <linux/moduleparam.h> 15#include <linux/moduleparam.h>
16 16
17#include <linux/stringify.h>
17#include <linux/kernel.h> 18#include <linux/kernel.h>
18#include <linux/timer.h> 19#include <linux/timer.h>
19#include <linux/errno.h> 20#include <linux/errno.h>
@@ -57,8 +58,8 @@
57#include "bnx2_fw.h" 58#include "bnx2_fw.h"
58 59
59#define DRV_MODULE_NAME "bnx2" 60#define DRV_MODULE_NAME "bnx2"
60#define DRV_MODULE_VERSION "2.2.1" 61#define DRV_MODULE_VERSION "2.2.3"
61#define DRV_MODULE_RELDATE "Dec 18, 2011" 62#define DRV_MODULE_RELDATE "June 27, 2012"
62#define FW_MIPS_FILE_06 "bnx2/bnx2-mips-06-6.2.3.fw" 63#define FW_MIPS_FILE_06 "bnx2/bnx2-mips-06-6.2.3.fw"
63#define FW_RV2P_FILE_06 "bnx2/bnx2-rv2p-06-6.0.15.fw" 64#define FW_RV2P_FILE_06 "bnx2/bnx2-rv2p-06-6.0.15.fw"
64#define FW_MIPS_FILE_09 "bnx2/bnx2-mips-09-6.2.1b.fw" 65#define FW_MIPS_FILE_09 "bnx2/bnx2-mips-09-6.2.1b.fw"
@@ -872,8 +873,7 @@ bnx2_alloc_mem(struct bnx2 *bp)
872 873
873 bnapi = &bp->bnx2_napi[i]; 874 bnapi = &bp->bnx2_napi[i];
874 875
875 sblk = (void *) (status_blk + 876 sblk = (status_blk + BNX2_SBLK_MSIX_ALIGN_SIZE * i);
876 BNX2_SBLK_MSIX_ALIGN_SIZE * i);
877 bnapi->status_blk.msix = sblk; 877 bnapi->status_blk.msix = sblk;
878 bnapi->hw_tx_cons_ptr = 878 bnapi->hw_tx_cons_ptr =
879 &sblk->status_tx_quick_consumer_index; 879 &sblk->status_tx_quick_consumer_index;
@@ -1972,22 +1972,26 @@ bnx2_remote_phy_event(struct bnx2 *bp)
1972 switch (speed) { 1972 switch (speed) {
1973 case BNX2_LINK_STATUS_10HALF: 1973 case BNX2_LINK_STATUS_10HALF:
1974 bp->duplex = DUPLEX_HALF; 1974 bp->duplex = DUPLEX_HALF;
1975 /* fall through */
1975 case BNX2_LINK_STATUS_10FULL: 1976 case BNX2_LINK_STATUS_10FULL:
1976 bp->line_speed = SPEED_10; 1977 bp->line_speed = SPEED_10;
1977 break; 1978 break;
1978 case BNX2_LINK_STATUS_100HALF: 1979 case BNX2_LINK_STATUS_100HALF:
1979 bp->duplex = DUPLEX_HALF; 1980 bp->duplex = DUPLEX_HALF;
1981 /* fall through */
1980 case BNX2_LINK_STATUS_100BASE_T4: 1982 case BNX2_LINK_STATUS_100BASE_T4:
1981 case BNX2_LINK_STATUS_100FULL: 1983 case BNX2_LINK_STATUS_100FULL:
1982 bp->line_speed = SPEED_100; 1984 bp->line_speed = SPEED_100;
1983 break; 1985 break;
1984 case BNX2_LINK_STATUS_1000HALF: 1986 case BNX2_LINK_STATUS_1000HALF:
1985 bp->duplex = DUPLEX_HALF; 1987 bp->duplex = DUPLEX_HALF;
1988 /* fall through */
1986 case BNX2_LINK_STATUS_1000FULL: 1989 case BNX2_LINK_STATUS_1000FULL:
1987 bp->line_speed = SPEED_1000; 1990 bp->line_speed = SPEED_1000;
1988 break; 1991 break;
1989 case BNX2_LINK_STATUS_2500HALF: 1992 case BNX2_LINK_STATUS_2500HALF:
1990 bp->duplex = DUPLEX_HALF; 1993 bp->duplex = DUPLEX_HALF;
1994 /* fall through */
1991 case BNX2_LINK_STATUS_2500FULL: 1995 case BNX2_LINK_STATUS_2500FULL:
1992 bp->line_speed = SPEED_2500; 1996 bp->line_speed = SPEED_2500;
1993 break; 1997 break;
@@ -2473,6 +2477,7 @@ bnx2_dump_mcp_state(struct bnx2 *bp)
2473 bnx2_shmem_rd(bp, BNX2_BC_STATE_RESET_TYPE)); 2477 bnx2_shmem_rd(bp, BNX2_BC_STATE_RESET_TYPE));
2474 pr_cont(" condition[%08x]\n", 2478 pr_cont(" condition[%08x]\n",
2475 bnx2_shmem_rd(bp, BNX2_BC_STATE_CONDITION)); 2479 bnx2_shmem_rd(bp, BNX2_BC_STATE_CONDITION));
2480 DP_SHMEM_LINE(bp, BNX2_BC_RESET_TYPE);
2476 DP_SHMEM_LINE(bp, 0x3cc); 2481 DP_SHMEM_LINE(bp, 0x3cc);
2477 DP_SHMEM_LINE(bp, 0x3dc); 2482 DP_SHMEM_LINE(bp, 0x3dc);
2478 DP_SHMEM_LINE(bp, 0x3ec); 2483 DP_SHMEM_LINE(bp, 0x3ec);
@@ -6245,7 +6250,7 @@ bnx2_enable_msix(struct bnx2 *bp, int msix_vecs)
6245static int 6250static int
6246bnx2_setup_int_mode(struct bnx2 *bp, int dis_msi) 6251bnx2_setup_int_mode(struct bnx2 *bp, int dis_msi)
6247{ 6252{
6248 int cpus = num_online_cpus(); 6253 int cpus = netif_get_num_default_rss_queues();
6249 int msix_vecs; 6254 int msix_vecs;
6250 6255
6251 if (!bp->num_req_rx_rings) 6256 if (!bp->num_req_rx_rings)
@@ -6406,6 +6411,75 @@ bnx2_reset_task(struct work_struct *work)
6406 rtnl_unlock(); 6411 rtnl_unlock();
6407} 6412}
6408 6413
6414#define BNX2_FTQ_ENTRY(ftq) { __stringify(ftq##FTQ_CTL), BNX2_##ftq##FTQ_CTL }
6415
6416static void
6417bnx2_dump_ftq(struct bnx2 *bp)
6418{
6419 int i;
6420 u32 reg, bdidx, cid, valid;
6421 struct net_device *dev = bp->dev;
6422 static const struct ftq_reg {
6423 char *name;
6424 u32 off;
6425 } ftq_arr[] = {
6426 BNX2_FTQ_ENTRY(RV2P_P),
6427 BNX2_FTQ_ENTRY(RV2P_T),
6428 BNX2_FTQ_ENTRY(RV2P_M),
6429 BNX2_FTQ_ENTRY(TBDR_),
6430 BNX2_FTQ_ENTRY(TDMA_),
6431 BNX2_FTQ_ENTRY(TXP_),
6432 BNX2_FTQ_ENTRY(TXP_),
6433 BNX2_FTQ_ENTRY(TPAT_),
6434 BNX2_FTQ_ENTRY(RXP_C),
6435 BNX2_FTQ_ENTRY(RXP_),
6436 BNX2_FTQ_ENTRY(COM_COMXQ_),
6437 BNX2_FTQ_ENTRY(COM_COMTQ_),
6438 BNX2_FTQ_ENTRY(COM_COMQ_),
6439 BNX2_FTQ_ENTRY(CP_CPQ_),
6440 };
6441
6442 netdev_err(dev, "<--- start FTQ dump --->\n");
6443 for (i = 0; i < ARRAY_SIZE(ftq_arr); i++)
6444 netdev_err(dev, "%s %08x\n", ftq_arr[i].name,
6445 bnx2_reg_rd_ind(bp, ftq_arr[i].off));
6446
6447 netdev_err(dev, "CPU states:\n");
6448 for (reg = BNX2_TXP_CPU_MODE; reg <= BNX2_CP_CPU_MODE; reg += 0x40000)
6449 netdev_err(dev, "%06x mode %x state %x evt_mask %x pc %x pc %x instr %x\n",
6450 reg, bnx2_reg_rd_ind(bp, reg),
6451 bnx2_reg_rd_ind(bp, reg + 4),
6452 bnx2_reg_rd_ind(bp, reg + 8),
6453 bnx2_reg_rd_ind(bp, reg + 0x1c),
6454 bnx2_reg_rd_ind(bp, reg + 0x1c),
6455 bnx2_reg_rd_ind(bp, reg + 0x20));
6456
6457 netdev_err(dev, "<--- end FTQ dump --->\n");
6458 netdev_err(dev, "<--- start TBDC dump --->\n");
6459 netdev_err(dev, "TBDC free cnt: %ld\n",
6460 REG_RD(bp, BNX2_TBDC_STATUS) & BNX2_TBDC_STATUS_FREE_CNT);
6461 netdev_err(dev, "LINE CID BIDX CMD VALIDS\n");
6462 for (i = 0; i < 0x20; i++) {
6463 int j = 0;
6464
6465 REG_WR(bp, BNX2_TBDC_BD_ADDR, i);
6466 REG_WR(bp, BNX2_TBDC_CAM_OPCODE,
6467 BNX2_TBDC_CAM_OPCODE_OPCODE_CAM_READ);
6468 REG_WR(bp, BNX2_TBDC_COMMAND, BNX2_TBDC_COMMAND_CMD_REG_ARB);
6469 while ((REG_RD(bp, BNX2_TBDC_COMMAND) &
6470 BNX2_TBDC_COMMAND_CMD_REG_ARB) && j < 100)
6471 j++;
6472
6473 cid = REG_RD(bp, BNX2_TBDC_CID);
6474 bdidx = REG_RD(bp, BNX2_TBDC_BIDX);
6475 valid = REG_RD(bp, BNX2_TBDC_CAM_OPCODE);
6476 netdev_err(dev, "%02x %06x %04lx %02x [%x]\n",
6477 i, cid, bdidx & BNX2_TBDC_BDIDX_BDIDX,
6478 bdidx >> 24, (valid >> 8) & 0x0ff);
6479 }
6480 netdev_err(dev, "<--- end TBDC dump --->\n");
6481}
6482
6409static void 6483static void
6410bnx2_dump_state(struct bnx2 *bp) 6484bnx2_dump_state(struct bnx2 *bp)
6411{ 6485{
@@ -6435,6 +6509,7 @@ bnx2_tx_timeout(struct net_device *dev)
6435{ 6509{
6436 struct bnx2 *bp = netdev_priv(dev); 6510 struct bnx2 *bp = netdev_priv(dev);
6437 6511
6512 bnx2_dump_ftq(bp);
6438 bnx2_dump_state(bp); 6513 bnx2_dump_state(bp);
6439 bnx2_dump_mcp_state(bp); 6514 bnx2_dump_mcp_state(bp);
6440 6515
@@ -6628,6 +6703,7 @@ bnx2_close(struct net_device *dev)
6628 6703
6629 bnx2_disable_int_sync(bp); 6704 bnx2_disable_int_sync(bp);
6630 bnx2_napi_disable(bp); 6705 bnx2_napi_disable(bp);
6706 netif_tx_disable(dev);
6631 del_timer_sync(&bp->timer); 6707 del_timer_sync(&bp->timer);
6632 bnx2_shutdown_chip(bp); 6708 bnx2_shutdown_chip(bp);
6633 bnx2_free_irq(bp); 6709 bnx2_free_irq(bp);
@@ -7832,7 +7908,7 @@ bnx2_get_5709_media(struct bnx2 *bp)
7832 else 7908 else
7833 strap = (val & BNX2_MISC_DUAL_MEDIA_CTRL_PHY_CTRL_STRAP) >> 8; 7909 strap = (val & BNX2_MISC_DUAL_MEDIA_CTRL_PHY_CTRL_STRAP) >> 8;
7834 7910
7835 if (PCI_FUNC(bp->pdev->devfn) == 0) { 7911 if (bp->func == 0) {
7836 switch (strap) { 7912 switch (strap) {
7837 case 0x4: 7913 case 0x4:
7838 case 0x5: 7914 case 0x5:
@@ -8131,9 +8207,12 @@ bnx2_init_board(struct pci_dev *pdev, struct net_device *dev)
8131 8207
8132 reg = bnx2_reg_rd_ind(bp, BNX2_SHM_HDR_SIGNATURE); 8208 reg = bnx2_reg_rd_ind(bp, BNX2_SHM_HDR_SIGNATURE);
8133 8209
8210 if (bnx2_reg_rd_ind(bp, BNX2_MCP_TOE_ID) & BNX2_MCP_TOE_ID_FUNCTION_ID)
8211 bp->func = 1;
8212
8134 if ((reg & BNX2_SHM_HDR_SIGNATURE_SIG_MASK) == 8213 if ((reg & BNX2_SHM_HDR_SIGNATURE_SIG_MASK) ==
8135 BNX2_SHM_HDR_SIGNATURE_SIG) { 8214 BNX2_SHM_HDR_SIGNATURE_SIG) {
8136 u32 off = PCI_FUNC(pdev->devfn) << 2; 8215 u32 off = bp->func << 2;
8137 8216
8138 bp->shmem_base = bnx2_reg_rd_ind(bp, BNX2_SHM_HDR_ADDR_0 + off); 8217 bp->shmem_base = bnx2_reg_rd_ind(bp, BNX2_SHM_HDR_ADDR_0 + off);
8139 } else 8218 } else