diff options
Diffstat (limited to 'drivers/net/can')
-rw-r--r-- | drivers/net/can/Kconfig | 7 | ||||
-rw-r--r-- | drivers/net/can/Makefile | 1 | ||||
-rw-r--r-- | drivers/net/can/at91_can.c | 34 | ||||
-rw-r--r-- | drivers/net/can/dev.c | 74 | ||||
-rw-r--r-- | drivers/net/can/sja1000/sja1000.c | 17 | ||||
-rw-r--r-- | drivers/net/can/sja1000/sja1000.h | 2 | ||||
-rw-r--r-- | drivers/net/can/ti_hecc.c | 993 | ||||
-rw-r--r-- | drivers/net/can/usb/ems_usb.c | 20 |
8 files changed, 1073 insertions, 75 deletions
diff --git a/drivers/net/can/Kconfig b/drivers/net/can/Kconfig index df32c109b7a..26d77cc0ded 100644 --- a/drivers/net/can/Kconfig +++ b/drivers/net/can/Kconfig | |||
@@ -95,6 +95,13 @@ config CAN_AT91 | |||
95 | ---help--- | 95 | ---help--- |
96 | This is a driver for the SoC CAN controller in Atmel's AT91SAM9263. | 96 | This is a driver for the SoC CAN controller in Atmel's AT91SAM9263. |
97 | 97 | ||
98 | config CAN_TI_HECC | ||
99 | depends on CAN_DEV && ARCH_OMAP3 | ||
100 | tristate "TI High End CAN Controller" | ||
101 | ---help--- | ||
102 | Driver for TI HECC (High End CAN Controller) module found on many | ||
103 | TI devices. The device specifications are available from www.ti.com | ||
104 | |||
98 | config CAN_DEBUG_DEVICES | 105 | config CAN_DEBUG_DEVICES |
99 | bool "CAN devices debugging messages" | 106 | bool "CAN devices debugging messages" |
100 | depends on CAN | 107 | depends on CAN |
diff --git a/drivers/net/can/Makefile b/drivers/net/can/Makefile index 0dea62721f2..31f4ab5df28 100644 --- a/drivers/net/can/Makefile +++ b/drivers/net/can/Makefile | |||
@@ -11,5 +11,6 @@ obj-y += usb/ | |||
11 | 11 | ||
12 | obj-$(CONFIG_CAN_SJA1000) += sja1000/ | 12 | obj-$(CONFIG_CAN_SJA1000) += sja1000/ |
13 | obj-$(CONFIG_CAN_AT91) += at91_can.o | 13 | obj-$(CONFIG_CAN_AT91) += at91_can.o |
14 | obj-$(CONFIG_CAN_TI_HECC) += ti_hecc.o | ||
14 | 15 | ||
15 | ccflags-$(CONFIG_CAN_DEBUG_DEVICES) := -DDEBUG | 16 | ccflags-$(CONFIG_CAN_DEBUG_DEVICES) := -DDEBUG |
diff --git a/drivers/net/can/at91_can.c b/drivers/net/can/at91_can.c index f67ae285a35..cbe3fce53e3 100644 --- a/drivers/net/can/at91_can.c +++ b/drivers/net/can/at91_can.c | |||
@@ -221,38 +221,6 @@ static inline void set_mb_mode(const struct at91_priv *priv, unsigned int mb, | |||
221 | set_mb_mode_prio(priv, mb, mode, 0); | 221 | set_mb_mode_prio(priv, mb, mode, 0); |
222 | } | 222 | } |
223 | 223 | ||
224 | static struct sk_buff *alloc_can_skb(struct net_device *dev, | ||
225 | struct can_frame **cf) | ||
226 | { | ||
227 | struct sk_buff *skb; | ||
228 | |||
229 | skb = netdev_alloc_skb(dev, sizeof(struct can_frame)); | ||
230 | if (unlikely(!skb)) | ||
231 | return NULL; | ||
232 | |||
233 | skb->protocol = htons(ETH_P_CAN); | ||
234 | skb->ip_summed = CHECKSUM_UNNECESSARY; | ||
235 | *cf = (struct can_frame *)skb_put(skb, sizeof(struct can_frame)); | ||
236 | |||
237 | return skb; | ||
238 | } | ||
239 | |||
240 | static struct sk_buff *alloc_can_err_skb(struct net_device *dev, | ||
241 | struct can_frame **cf) | ||
242 | { | ||
243 | struct sk_buff *skb; | ||
244 | |||
245 | skb = alloc_can_skb(dev, cf); | ||
246 | if (unlikely(!skb)) | ||
247 | return NULL; | ||
248 | |||
249 | memset(*cf, 0, sizeof(struct can_frame)); | ||
250 | (*cf)->can_id = CAN_ERR_FLAG; | ||
251 | (*cf)->can_dlc = CAN_ERR_DLC; | ||
252 | |||
253 | return skb; | ||
254 | } | ||
255 | |||
256 | /* | 224 | /* |
257 | * Swtich transceiver on or off | 225 | * Swtich transceiver on or off |
258 | */ | 226 | */ |
@@ -1087,7 +1055,7 @@ static int __init at91_can_probe(struct platform_device *pdev) | |||
1087 | goto exit_release; | 1055 | goto exit_release; |
1088 | } | 1056 | } |
1089 | 1057 | ||
1090 | dev = alloc_candev(sizeof(struct at91_priv)); | 1058 | dev = alloc_candev(sizeof(struct at91_priv), AT91_MB_TX_NUM); |
1091 | if (!dev) { | 1059 | if (!dev) { |
1092 | err = -ENOMEM; | 1060 | err = -ENOMEM; |
1093 | goto exit_iounmap; | 1061 | goto exit_iounmap; |
diff --git a/drivers/net/can/dev.c b/drivers/net/can/dev.c index f0b9a1e1db4..c3db111d2ff 100644 --- a/drivers/net/can/dev.c +++ b/drivers/net/can/dev.c | |||
@@ -245,7 +245,7 @@ static void can_flush_echo_skb(struct net_device *dev) | |||
245 | struct net_device_stats *stats = &dev->stats; | 245 | struct net_device_stats *stats = &dev->stats; |
246 | int i; | 246 | int i; |
247 | 247 | ||
248 | for (i = 0; i < CAN_ECHO_SKB_MAX; i++) { | 248 | for (i = 0; i < priv->echo_skb_max; i++) { |
249 | if (priv->echo_skb[i]) { | 249 | if (priv->echo_skb[i]) { |
250 | kfree_skb(priv->echo_skb[i]); | 250 | kfree_skb(priv->echo_skb[i]); |
251 | priv->echo_skb[i] = NULL; | 251 | priv->echo_skb[i] = NULL; |
@@ -262,10 +262,13 @@ static void can_flush_echo_skb(struct net_device *dev) | |||
262 | * of the device driver. The driver must protect access to | 262 | * of the device driver. The driver must protect access to |
263 | * priv->echo_skb, if necessary. | 263 | * priv->echo_skb, if necessary. |
264 | */ | 264 | */ |
265 | void can_put_echo_skb(struct sk_buff *skb, struct net_device *dev, int idx) | 265 | void can_put_echo_skb(struct sk_buff *skb, struct net_device *dev, |
266 | unsigned int idx) | ||
266 | { | 267 | { |
267 | struct can_priv *priv = netdev_priv(dev); | 268 | struct can_priv *priv = netdev_priv(dev); |
268 | 269 | ||
270 | BUG_ON(idx >= priv->echo_skb_max); | ||
271 | |||
269 | /* check flag whether this packet has to be looped back */ | 272 | /* check flag whether this packet has to be looped back */ |
270 | if (!(dev->flags & IFF_ECHO) || skb->pkt_type != PACKET_LOOPBACK) { | 273 | if (!(dev->flags & IFF_ECHO) || skb->pkt_type != PACKET_LOOPBACK) { |
271 | kfree_skb(skb); | 274 | kfree_skb(skb); |
@@ -311,10 +314,12 @@ EXPORT_SYMBOL_GPL(can_put_echo_skb); | |||
311 | * is handled in the device driver. The driver must protect | 314 | * is handled in the device driver. The driver must protect |
312 | * access to priv->echo_skb, if necessary. | 315 | * access to priv->echo_skb, if necessary. |
313 | */ | 316 | */ |
314 | void can_get_echo_skb(struct net_device *dev, int idx) | 317 | void can_get_echo_skb(struct net_device *dev, unsigned int idx) |
315 | { | 318 | { |
316 | struct can_priv *priv = netdev_priv(dev); | 319 | struct can_priv *priv = netdev_priv(dev); |
317 | 320 | ||
321 | BUG_ON(idx >= priv->echo_skb_max); | ||
322 | |||
318 | if (priv->echo_skb[idx]) { | 323 | if (priv->echo_skb[idx]) { |
319 | netif_rx(priv->echo_skb[idx]); | 324 | netif_rx(priv->echo_skb[idx]); |
320 | priv->echo_skb[idx] = NULL; | 325 | priv->echo_skb[idx] = NULL; |
@@ -327,10 +332,12 @@ EXPORT_SYMBOL_GPL(can_get_echo_skb); | |||
327 | * | 332 | * |
328 | * The function is typically called when TX failed. | 333 | * The function is typically called when TX failed. |
329 | */ | 334 | */ |
330 | void can_free_echo_skb(struct net_device *dev, int idx) | 335 | void can_free_echo_skb(struct net_device *dev, unsigned int idx) |
331 | { | 336 | { |
332 | struct can_priv *priv = netdev_priv(dev); | 337 | struct can_priv *priv = netdev_priv(dev); |
333 | 338 | ||
339 | BUG_ON(idx >= priv->echo_skb_max); | ||
340 | |||
334 | if (priv->echo_skb[idx]) { | 341 | if (priv->echo_skb[idx]) { |
335 | kfree_skb(priv->echo_skb[idx]); | 342 | kfree_skb(priv->echo_skb[idx]); |
336 | priv->echo_skb[idx] = NULL; | 343 | priv->echo_skb[idx] = NULL; |
@@ -359,17 +366,12 @@ void can_restart(unsigned long data) | |||
359 | can_flush_echo_skb(dev); | 366 | can_flush_echo_skb(dev); |
360 | 367 | ||
361 | /* send restart message upstream */ | 368 | /* send restart message upstream */ |
362 | skb = dev_alloc_skb(sizeof(struct can_frame)); | 369 | skb = alloc_can_err_skb(dev, &cf); |
363 | if (skb == NULL) { | 370 | if (skb == NULL) { |
364 | err = -ENOMEM; | 371 | err = -ENOMEM; |
365 | goto restart; | 372 | goto restart; |
366 | } | 373 | } |
367 | skb->dev = dev; | 374 | cf->can_id |= CAN_ERR_RESTARTED; |
368 | skb->protocol = htons(ETH_P_CAN); | ||
369 | cf = (struct can_frame *)skb_put(skb, sizeof(struct can_frame)); | ||
370 | memset(cf, 0, sizeof(struct can_frame)); | ||
371 | cf->can_id = CAN_ERR_FLAG | CAN_ERR_RESTARTED; | ||
372 | cf->can_dlc = CAN_ERR_DLC; | ||
373 | 375 | ||
374 | netif_rx(skb); | 376 | netif_rx(skb); |
375 | 377 | ||
@@ -442,20 +444,66 @@ static void can_setup(struct net_device *dev) | |||
442 | dev->features = NETIF_F_NO_CSUM; | 444 | dev->features = NETIF_F_NO_CSUM; |
443 | } | 445 | } |
444 | 446 | ||
447 | struct sk_buff *alloc_can_skb(struct net_device *dev, struct can_frame **cf) | ||
448 | { | ||
449 | struct sk_buff *skb; | ||
450 | |||
451 | skb = netdev_alloc_skb(dev, sizeof(struct can_frame)); | ||
452 | if (unlikely(!skb)) | ||
453 | return NULL; | ||
454 | |||
455 | skb->protocol = htons(ETH_P_CAN); | ||
456 | skb->pkt_type = PACKET_BROADCAST; | ||
457 | skb->ip_summed = CHECKSUM_UNNECESSARY; | ||
458 | *cf = (struct can_frame *)skb_put(skb, sizeof(struct can_frame)); | ||
459 | memset(*cf, 0, sizeof(struct can_frame)); | ||
460 | |||
461 | return skb; | ||
462 | } | ||
463 | EXPORT_SYMBOL_GPL(alloc_can_skb); | ||
464 | |||
465 | struct sk_buff *alloc_can_err_skb(struct net_device *dev, struct can_frame **cf) | ||
466 | { | ||
467 | struct sk_buff *skb; | ||
468 | |||
469 | skb = alloc_can_skb(dev, cf); | ||
470 | if (unlikely(!skb)) | ||
471 | return NULL; | ||
472 | |||
473 | (*cf)->can_id = CAN_ERR_FLAG; | ||
474 | (*cf)->can_dlc = CAN_ERR_DLC; | ||
475 | |||
476 | return skb; | ||
477 | } | ||
478 | EXPORT_SYMBOL_GPL(alloc_can_err_skb); | ||
479 | |||
445 | /* | 480 | /* |
446 | * Allocate and setup space for the CAN network device | 481 | * Allocate and setup space for the CAN network device |
447 | */ | 482 | */ |
448 | struct net_device *alloc_candev(int sizeof_priv) | 483 | struct net_device *alloc_candev(int sizeof_priv, unsigned int echo_skb_max) |
449 | { | 484 | { |
450 | struct net_device *dev; | 485 | struct net_device *dev; |
451 | struct can_priv *priv; | 486 | struct can_priv *priv; |
487 | int size; | ||
452 | 488 | ||
453 | dev = alloc_netdev(sizeof_priv, "can%d", can_setup); | 489 | if (echo_skb_max) |
490 | size = ALIGN(sizeof_priv, sizeof(struct sk_buff *)) + | ||
491 | echo_skb_max * sizeof(struct sk_buff *); | ||
492 | else | ||
493 | size = sizeof_priv; | ||
494 | |||
495 | dev = alloc_netdev(size, "can%d", can_setup); | ||
454 | if (!dev) | 496 | if (!dev) |
455 | return NULL; | 497 | return NULL; |
456 | 498 | ||
457 | priv = netdev_priv(dev); | 499 | priv = netdev_priv(dev); |
458 | 500 | ||
501 | if (echo_skb_max) { | ||
502 | priv->echo_skb_max = echo_skb_max; | ||
503 | priv->echo_skb = (void *)priv + | ||
504 | ALIGN(sizeof_priv, sizeof(struct sk_buff *)); | ||
505 | } | ||
506 | |||
459 | priv->state = CAN_STATE_STOPPED; | 507 | priv->state = CAN_STATE_STOPPED; |
460 | 508 | ||
461 | init_timer(&priv->restart_timer); | 509 | init_timer(&priv->restart_timer); |
diff --git a/drivers/net/can/sja1000/sja1000.c b/drivers/net/can/sja1000/sja1000.c index 16d2ecd2a3b..782a47fabf2 100644 --- a/drivers/net/can/sja1000/sja1000.c +++ b/drivers/net/can/sja1000/sja1000.c | |||
@@ -296,11 +296,9 @@ static void sja1000_rx(struct net_device *dev) | |||
296 | uint8_t dlc; | 296 | uint8_t dlc; |
297 | int i; | 297 | int i; |
298 | 298 | ||
299 | skb = dev_alloc_skb(sizeof(struct can_frame)); | 299 | skb = alloc_can_skb(dev, &cf); |
300 | if (skb == NULL) | 300 | if (skb == NULL) |
301 | return; | 301 | return; |
302 | skb->dev = dev; | ||
303 | skb->protocol = htons(ETH_P_CAN); | ||
304 | 302 | ||
305 | fi = priv->read_reg(priv, REG_FI); | 303 | fi = priv->read_reg(priv, REG_FI); |
306 | dlc = fi & 0x0F; | 304 | dlc = fi & 0x0F; |
@@ -323,8 +321,6 @@ static void sja1000_rx(struct net_device *dev) | |||
323 | if (fi & FI_RTR) | 321 | if (fi & FI_RTR) |
324 | id |= CAN_RTR_FLAG; | 322 | id |= CAN_RTR_FLAG; |
325 | 323 | ||
326 | cf = (struct can_frame *)skb_put(skb, sizeof(struct can_frame)); | ||
327 | memset(cf, 0, sizeof(struct can_frame)); | ||
328 | cf->can_id = id; | 324 | cf->can_id = id; |
329 | cf->can_dlc = dlc; | 325 | cf->can_dlc = dlc; |
330 | for (i = 0; i < dlc; i++) | 326 | for (i = 0; i < dlc; i++) |
@@ -351,15 +347,9 @@ static int sja1000_err(struct net_device *dev, uint8_t isrc, uint8_t status) | |||
351 | enum can_state state = priv->can.state; | 347 | enum can_state state = priv->can.state; |
352 | uint8_t ecc, alc; | 348 | uint8_t ecc, alc; |
353 | 349 | ||
354 | skb = dev_alloc_skb(sizeof(struct can_frame)); | 350 | skb = alloc_can_err_skb(dev, &cf); |
355 | if (skb == NULL) | 351 | if (skb == NULL) |
356 | return -ENOMEM; | 352 | return -ENOMEM; |
357 | skb->dev = dev; | ||
358 | skb->protocol = htons(ETH_P_CAN); | ||
359 | cf = (struct can_frame *)skb_put(skb, sizeof(struct can_frame)); | ||
360 | memset(cf, 0, sizeof(struct can_frame)); | ||
361 | cf->can_id = CAN_ERR_FLAG; | ||
362 | cf->can_dlc = CAN_ERR_DLC; | ||
363 | 353 | ||
364 | if (isrc & IRQ_DOI) { | 354 | if (isrc & IRQ_DOI) { |
365 | /* data overrun interrupt */ | 355 | /* data overrun interrupt */ |
@@ -565,7 +555,8 @@ struct net_device *alloc_sja1000dev(int sizeof_priv) | |||
565 | struct net_device *dev; | 555 | struct net_device *dev; |
566 | struct sja1000_priv *priv; | 556 | struct sja1000_priv *priv; |
567 | 557 | ||
568 | dev = alloc_candev(sizeof(struct sja1000_priv) + sizeof_priv); | 558 | dev = alloc_candev(sizeof(struct sja1000_priv) + sizeof_priv, |
559 | SJA1000_ECHO_SKB_MAX); | ||
569 | if (!dev) | 560 | if (!dev) |
570 | return NULL; | 561 | return NULL; |
571 | 562 | ||
diff --git a/drivers/net/can/sja1000/sja1000.h b/drivers/net/can/sja1000/sja1000.h index 302d2c763ad..97a622b9302 100644 --- a/drivers/net/can/sja1000/sja1000.h +++ b/drivers/net/can/sja1000/sja1000.h | |||
@@ -50,6 +50,8 @@ | |||
50 | #include <linux/can/dev.h> | 50 | #include <linux/can/dev.h> |
51 | #include <linux/can/platform/sja1000.h> | 51 | #include <linux/can/platform/sja1000.h> |
52 | 52 | ||
53 | #define SJA1000_ECHO_SKB_MAX 1 /* the SJA1000 has one TX buffer object */ | ||
54 | |||
53 | #define SJA1000_MAX_IRQ 20 /* max. number of interrupts handled in ISR */ | 55 | #define SJA1000_MAX_IRQ 20 /* max. number of interrupts handled in ISR */ |
54 | 56 | ||
55 | /* SJA1000 registers - manual section 6.4 (Pelican Mode) */ | 57 | /* SJA1000 registers - manual section 6.4 (Pelican Mode) */ |
diff --git a/drivers/net/can/ti_hecc.c b/drivers/net/can/ti_hecc.c new file mode 100644 index 00000000000..07e8016b17e --- /dev/null +++ b/drivers/net/can/ti_hecc.c | |||
@@ -0,0 +1,993 @@ | |||
1 | /* | ||
2 | * TI HECC (CAN) device driver | ||
3 | * | ||
4 | * This driver supports TI's HECC (High End CAN Controller module) and the | ||
5 | * specs for the same is available at <http://www.ti.com> | ||
6 | * | ||
7 | * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/ | ||
8 | * | ||
9 | * This program is free software; you can redistribute it and/or | ||
10 | * modify it under the terms of the GNU General Public License as | ||
11 | * published by the Free Software Foundation version 2. | ||
12 | * | ||
13 | * This program is distributed as is WITHOUT ANY WARRANTY of any | ||
14 | * kind, whether express or implied; without even the implied warranty | ||
15 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
16 | * GNU General Public License for more details. | ||
17 | * | ||
18 | */ | ||
19 | |||
20 | /* | ||
21 | * Your platform definitions should specify module ram offsets and interrupt | ||
22 | * number to use as follows: | ||
23 | * | ||
24 | * static struct ti_hecc_platform_data am3517_evm_hecc_pdata = { | ||
25 | * .scc_hecc_offset = 0, | ||
26 | * .scc_ram_offset = 0x3000, | ||
27 | * .hecc_ram_offset = 0x3000, | ||
28 | * .mbx_offset = 0x2000, | ||
29 | * .int_line = 0, | ||
30 | * .revision = 1, | ||
31 | * }; | ||
32 | * | ||
33 | * Please see include/can/platform/ti_hecc.h for description of above fields | ||
34 | * | ||
35 | */ | ||
36 | |||
37 | #include <linux/module.h> | ||
38 | #include <linux/init.h> | ||
39 | #include <linux/kernel.h> | ||
40 | #include <linux/types.h> | ||
41 | #include <linux/interrupt.h> | ||
42 | #include <linux/errno.h> | ||
43 | #include <linux/netdevice.h> | ||
44 | #include <linux/skbuff.h> | ||
45 | #include <linux/platform_device.h> | ||
46 | #include <linux/clk.h> | ||
47 | |||
48 | #include <linux/can.h> | ||
49 | #include <linux/can/dev.h> | ||
50 | #include <linux/can/error.h> | ||
51 | #include <linux/can/platform/ti_hecc.h> | ||
52 | |||
53 | #define DRV_NAME "ti_hecc" | ||
54 | #define HECC_MODULE_VERSION "0.7" | ||
55 | MODULE_VERSION(HECC_MODULE_VERSION); | ||
56 | #define DRV_DESC "TI High End CAN Controller Driver " HECC_MODULE_VERSION | ||
57 | |||
58 | /* TX / RX Mailbox Configuration */ | ||
59 | #define HECC_MAX_MAILBOXES 32 /* hardware mailboxes - do not change */ | ||
60 | #define MAX_TX_PRIO 0x3F /* hardware value - do not change */ | ||
61 | |||
62 | /* | ||
63 | * Important Note: TX mailbox configuration | ||
64 | * TX mailboxes should be restricted to the number of SKB buffers to avoid | ||
65 | * maintaining SKB buffers separately. TX mailboxes should be a power of 2 | ||
66 | * for the mailbox logic to work. Top mailbox numbers are reserved for RX | ||
67 | * and lower mailboxes for TX. | ||
68 | * | ||
69 | * HECC_MAX_TX_MBOX HECC_MB_TX_SHIFT | ||
70 | * 4 (default) 2 | ||
71 | * 8 3 | ||
72 | * 16 4 | ||
73 | */ | ||
74 | #define HECC_MB_TX_SHIFT 2 /* as per table above */ | ||
75 | #define HECC_MAX_TX_MBOX BIT(HECC_MB_TX_SHIFT) | ||
76 | |||
77 | #define HECC_TX_PRIO_SHIFT (HECC_MB_TX_SHIFT) | ||
78 | #define HECC_TX_PRIO_MASK (MAX_TX_PRIO << HECC_MB_TX_SHIFT) | ||
79 | #define HECC_TX_MB_MASK (HECC_MAX_TX_MBOX - 1) | ||
80 | #define HECC_TX_MASK ((HECC_MAX_TX_MBOX - 1) | HECC_TX_PRIO_MASK) | ||
81 | #define HECC_TX_MBOX_MASK (~(BIT(HECC_MAX_TX_MBOX) - 1)) | ||
82 | #define HECC_DEF_NAPI_WEIGHT HECC_MAX_RX_MBOX | ||
83 | |||
84 | /* | ||
85 | * Important Note: RX mailbox configuration | ||
86 | * RX mailboxes are further logically split into two - main and buffer | ||
87 | * mailboxes. The goal is to get all packets into main mailboxes as | ||
88 | * driven by mailbox number and receive priority (higher to lower) and | ||
89 | * buffer mailboxes are used to receive pkts while main mailboxes are being | ||
90 | * processed. This ensures in-order packet reception. | ||
91 | * | ||
92 | * Here are the recommended values for buffer mailbox. Note that RX mailboxes | ||
93 | * start after TX mailboxes: | ||
94 | * | ||
95 | * HECC_MAX_RX_MBOX HECC_RX_BUFFER_MBOX No of buffer mailboxes | ||
96 | * 28 12 8 | ||
97 | * 16 20 4 | ||
98 | */ | ||
99 | |||
100 | #define HECC_MAX_RX_MBOX (HECC_MAX_MAILBOXES - HECC_MAX_TX_MBOX) | ||
101 | #define HECC_RX_BUFFER_MBOX 12 /* as per table above */ | ||
102 | #define HECC_RX_FIRST_MBOX (HECC_MAX_MAILBOXES - 1) | ||
103 | #define HECC_RX_HIGH_MBOX_MASK (~(BIT(HECC_RX_BUFFER_MBOX) - 1)) | ||
104 | |||
105 | /* TI HECC module registers */ | ||
106 | #define HECC_CANME 0x0 /* Mailbox enable */ | ||
107 | #define HECC_CANMD 0x4 /* Mailbox direction */ | ||
108 | #define HECC_CANTRS 0x8 /* Transmit request set */ | ||
109 | #define HECC_CANTRR 0xC /* Transmit request */ | ||
110 | #define HECC_CANTA 0x10 /* Transmission acknowledge */ | ||
111 | #define HECC_CANAA 0x14 /* Abort acknowledge */ | ||
112 | #define HECC_CANRMP 0x18 /* Receive message pending */ | ||
113 | #define HECC_CANRML 0x1C /* Remote message lost */ | ||
114 | #define HECC_CANRFP 0x20 /* Remote frame pending */ | ||
115 | #define HECC_CANGAM 0x24 /* SECC only:Global acceptance mask */ | ||
116 | #define HECC_CANMC 0x28 /* Master control */ | ||
117 | #define HECC_CANBTC 0x2C /* Bit timing configuration */ | ||
118 | #define HECC_CANES 0x30 /* Error and status */ | ||
119 | #define HECC_CANTEC 0x34 /* Transmit error counter */ | ||
120 | #define HECC_CANREC 0x38 /* Receive error counter */ | ||
121 | #define HECC_CANGIF0 0x3C /* Global interrupt flag 0 */ | ||
122 | #define HECC_CANGIM 0x40 /* Global interrupt mask */ | ||
123 | #define HECC_CANGIF1 0x44 /* Global interrupt flag 1 */ | ||
124 | #define HECC_CANMIM 0x48 /* Mailbox interrupt mask */ | ||
125 | #define HECC_CANMIL 0x4C /* Mailbox interrupt level */ | ||
126 | #define HECC_CANOPC 0x50 /* Overwrite protection control */ | ||
127 | #define HECC_CANTIOC 0x54 /* Transmit I/O control */ | ||
128 | #define HECC_CANRIOC 0x58 /* Receive I/O control */ | ||
129 | #define HECC_CANLNT 0x5C /* HECC only: Local network time */ | ||
130 | #define HECC_CANTOC 0x60 /* HECC only: Time-out control */ | ||
131 | #define HECC_CANTOS 0x64 /* HECC only: Time-out status */ | ||
132 | #define HECC_CANTIOCE 0x68 /* SCC only:Enhanced TX I/O control */ | ||
133 | #define HECC_CANRIOCE 0x6C /* SCC only:Enhanced RX I/O control */ | ||
134 | |||
135 | /* Mailbox registers */ | ||
136 | #define HECC_CANMID 0x0 | ||
137 | #define HECC_CANMCF 0x4 | ||
138 | #define HECC_CANMDL 0x8 | ||
139 | #define HECC_CANMDH 0xC | ||
140 | |||
141 | #define HECC_SET_REG 0xFFFFFFFF | ||
142 | #define HECC_CANID_MASK 0x3FF /* 18 bits mask for extended id's */ | ||
143 | #define HECC_CCE_WAIT_COUNT 100 /* Wait for ~1 sec for CCE bit */ | ||
144 | |||
145 | #define HECC_CANMC_SCM BIT(13) /* SCC compat mode */ | ||
146 | #define HECC_CANMC_CCR BIT(12) /* Change config request */ | ||
147 | #define HECC_CANMC_PDR BIT(11) /* Local Power down - for sleep mode */ | ||
148 | #define HECC_CANMC_ABO BIT(7) /* Auto Bus On */ | ||
149 | #define HECC_CANMC_STM BIT(6) /* Self test mode - loopback */ | ||
150 | #define HECC_CANMC_SRES BIT(5) /* Software reset */ | ||
151 | |||
152 | #define HECC_CANTIOC_EN BIT(3) /* Enable CAN TX I/O pin */ | ||
153 | #define HECC_CANRIOC_EN BIT(3) /* Enable CAN RX I/O pin */ | ||
154 | |||
155 | #define HECC_CANMID_IDE BIT(31) /* Extended frame format */ | ||
156 | #define HECC_CANMID_AME BIT(30) /* Acceptance mask enable */ | ||
157 | #define HECC_CANMID_AAM BIT(29) /* Auto answer mode */ | ||
158 | |||
159 | #define HECC_CANES_FE BIT(24) /* form error */ | ||
160 | #define HECC_CANES_BE BIT(23) /* bit error */ | ||
161 | #define HECC_CANES_SA1 BIT(22) /* stuck at dominant error */ | ||
162 | #define HECC_CANES_CRCE BIT(21) /* CRC error */ | ||
163 | #define HECC_CANES_SE BIT(20) /* stuff bit error */ | ||
164 | #define HECC_CANES_ACKE BIT(19) /* ack error */ | ||
165 | #define HECC_CANES_BO BIT(18) /* Bus off status */ | ||
166 | #define HECC_CANES_EP BIT(17) /* Error passive status */ | ||
167 | #define HECC_CANES_EW BIT(16) /* Error warning status */ | ||
168 | #define HECC_CANES_SMA BIT(5) /* suspend mode ack */ | ||
169 | #define HECC_CANES_CCE BIT(4) /* Change config enabled */ | ||
170 | #define HECC_CANES_PDA BIT(3) /* Power down mode ack */ | ||
171 | |||
172 | #define HECC_CANBTC_SAM BIT(7) /* sample points */ | ||
173 | |||
174 | #define HECC_BUS_ERROR (HECC_CANES_FE | HECC_CANES_BE |\ | ||
175 | HECC_CANES_CRCE | HECC_CANES_SE |\ | ||
176 | HECC_CANES_ACKE) | ||
177 | |||
178 | #define HECC_CANMCF_RTR BIT(4) /* Remote transmit request */ | ||
179 | |||
180 | #define HECC_CANGIF_MAIF BIT(17) /* Message alarm interrupt */ | ||
181 | #define HECC_CANGIF_TCOIF BIT(16) /* Timer counter overflow int */ | ||
182 | #define HECC_CANGIF_GMIF BIT(15) /* Global mailbox interrupt */ | ||
183 | #define HECC_CANGIF_AAIF BIT(14) /* Abort ack interrupt */ | ||
184 | #define HECC_CANGIF_WDIF BIT(13) /* Write denied interrupt */ | ||
185 | #define HECC_CANGIF_WUIF BIT(12) /* Wake up interrupt */ | ||
186 | #define HECC_CANGIF_RMLIF BIT(11) /* Receive message lost interrupt */ | ||
187 | #define HECC_CANGIF_BOIF BIT(10) /* Bus off interrupt */ | ||
188 | #define HECC_CANGIF_EPIF BIT(9) /* Error passive interrupt */ | ||
189 | #define HECC_CANGIF_WLIF BIT(8) /* Warning level interrupt */ | ||
190 | #define HECC_CANGIF_MBOX_MASK 0x1F /* Mailbox number mask */ | ||
191 | #define HECC_CANGIM_I1EN BIT(1) /* Int line 1 enable */ | ||
192 | #define HECC_CANGIM_I0EN BIT(0) /* Int line 0 enable */ | ||
193 | #define HECC_CANGIM_DEF_MASK 0x700 /* only busoff/warning/passive */ | ||
194 | #define HECC_CANGIM_SIL BIT(2) /* system interrupts to int line 1 */ | ||
195 | |||
196 | /* CAN Bittiming constants as per HECC specs */ | ||
197 | static struct can_bittiming_const ti_hecc_bittiming_const = { | ||
198 | .name = DRV_NAME, | ||
199 | .tseg1_min = 1, | ||
200 | .tseg1_max = 16, | ||
201 | .tseg2_min = 1, | ||
202 | .tseg2_max = 8, | ||
203 | .sjw_max = 4, | ||
204 | .brp_min = 1, | ||
205 | .brp_max = 256, | ||
206 | .brp_inc = 1, | ||
207 | }; | ||
208 | |||
209 | struct ti_hecc_priv { | ||
210 | struct can_priv can; /* MUST be first member/field */ | ||
211 | struct napi_struct napi; | ||
212 | struct net_device *ndev; | ||
213 | struct clk *clk; | ||
214 | void __iomem *base; | ||
215 | u32 scc_ram_offset; | ||
216 | u32 hecc_ram_offset; | ||
217 | u32 mbx_offset; | ||
218 | u32 int_line; | ||
219 | spinlock_t mbx_lock; /* CANME register needs protection */ | ||
220 | u32 tx_head; | ||
221 | u32 tx_tail; | ||
222 | u32 rx_next; | ||
223 | }; | ||
224 | |||
225 | static inline int get_tx_head_mb(struct ti_hecc_priv *priv) | ||
226 | { | ||
227 | return priv->tx_head & HECC_TX_MB_MASK; | ||
228 | } | ||
229 | |||
230 | static inline int get_tx_tail_mb(struct ti_hecc_priv *priv) | ||
231 | { | ||
232 | return priv->tx_tail & HECC_TX_MB_MASK; | ||
233 | } | ||
234 | |||
235 | static inline int get_tx_head_prio(struct ti_hecc_priv *priv) | ||
236 | { | ||
237 | return (priv->tx_head >> HECC_TX_PRIO_SHIFT) & MAX_TX_PRIO; | ||
238 | } | ||
239 | |||
240 | static inline void hecc_write_lam(struct ti_hecc_priv *priv, u32 mbxno, u32 val) | ||
241 | { | ||
242 | __raw_writel(val, priv->base + priv->hecc_ram_offset + mbxno * 4); | ||
243 | } | ||
244 | |||
245 | static inline void hecc_write_mbx(struct ti_hecc_priv *priv, u32 mbxno, | ||
246 | u32 reg, u32 val) | ||
247 | { | ||
248 | __raw_writel(val, priv->base + priv->mbx_offset + mbxno * 0x10 + | ||
249 | reg); | ||
250 | } | ||
251 | |||
252 | static inline u32 hecc_read_mbx(struct ti_hecc_priv *priv, u32 mbxno, u32 reg) | ||
253 | { | ||
254 | return __raw_readl(priv->base + priv->mbx_offset + mbxno * 0x10 + | ||
255 | reg); | ||
256 | } | ||
257 | |||
258 | static inline void hecc_write(struct ti_hecc_priv *priv, u32 reg, u32 val) | ||
259 | { | ||
260 | __raw_writel(val, priv->base + reg); | ||
261 | } | ||
262 | |||
263 | static inline u32 hecc_read(struct ti_hecc_priv *priv, int reg) | ||
264 | { | ||
265 | return __raw_readl(priv->base + reg); | ||
266 | } | ||
267 | |||
268 | static inline void hecc_set_bit(struct ti_hecc_priv *priv, int reg, | ||
269 | u32 bit_mask) | ||
270 | { | ||
271 | hecc_write(priv, reg, hecc_read(priv, reg) | bit_mask); | ||
272 | } | ||
273 | |||
274 | static inline void hecc_clear_bit(struct ti_hecc_priv *priv, int reg, | ||
275 | u32 bit_mask) | ||
276 | { | ||
277 | hecc_write(priv, reg, hecc_read(priv, reg) & ~bit_mask); | ||
278 | } | ||
279 | |||
280 | static inline u32 hecc_get_bit(struct ti_hecc_priv *priv, int reg, u32 bit_mask) | ||
281 | { | ||
282 | return (hecc_read(priv, reg) & bit_mask) ? 1 : 0; | ||
283 | } | ||
284 | |||
285 | static int ti_hecc_get_state(const struct net_device *ndev, | ||
286 | enum can_state *state) | ||
287 | { | ||
288 | struct ti_hecc_priv *priv = netdev_priv(ndev); | ||
289 | |||
290 | *state = priv->can.state; | ||
291 | return 0; | ||
292 | } | ||
293 | |||
294 | static int ti_hecc_set_btc(struct ti_hecc_priv *priv) | ||
295 | { | ||
296 | struct can_bittiming *bit_timing = &priv->can.bittiming; | ||
297 | u32 can_btc; | ||
298 | |||
299 | can_btc = (bit_timing->phase_seg2 - 1) & 0x7; | ||
300 | can_btc |= ((bit_timing->phase_seg1 + bit_timing->prop_seg - 1) | ||
301 | & 0xF) << 3; | ||
302 | if (priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES) { | ||
303 | if (bit_timing->brp > 4) | ||
304 | can_btc |= HECC_CANBTC_SAM; | ||
305 | else | ||
306 | dev_warn(priv->ndev->dev.parent, "WARN: Triple" \ | ||
307 | "sampling not set due to h/w limitations"); | ||
308 | } | ||
309 | can_btc |= ((bit_timing->sjw - 1) & 0x3) << 8; | ||
310 | can_btc |= ((bit_timing->brp - 1) & 0xFF) << 16; | ||
311 | |||
312 | /* ERM being set to 0 by default meaning resync at falling edge */ | ||
313 | |||
314 | hecc_write(priv, HECC_CANBTC, can_btc); | ||
315 | dev_info(priv->ndev->dev.parent, "setting CANBTC=%#x\n", can_btc); | ||
316 | |||
317 | return 0; | ||
318 | } | ||
319 | |||
320 | static void ti_hecc_reset(struct net_device *ndev) | ||
321 | { | ||
322 | u32 cnt; | ||
323 | struct ti_hecc_priv *priv = netdev_priv(ndev); | ||
324 | |||
325 | dev_dbg(ndev->dev.parent, "resetting hecc ...\n"); | ||
326 | hecc_set_bit(priv, HECC_CANMC, HECC_CANMC_SRES); | ||
327 | |||
328 | /* Set change control request and wait till enabled */ | ||
329 | hecc_set_bit(priv, HECC_CANMC, HECC_CANMC_CCR); | ||
330 | |||
331 | /* | ||
332 | * INFO: It has been observed that at times CCE bit may not be | ||
333 | * set and hw seems to be ok even if this bit is not set so | ||
334 | * timing out with a timing of 1ms to respect the specs | ||
335 | */ | ||
336 | cnt = HECC_CCE_WAIT_COUNT; | ||
337 | while (!hecc_get_bit(priv, HECC_CANES, HECC_CANES_CCE) && cnt != 0) { | ||
338 | --cnt; | ||
339 | udelay(10); | ||
340 | } | ||
341 | |||
342 | /* | ||
343 | * Note: On HECC, BTC can be programmed only in initialization mode, so | ||
344 | * it is expected that the can bittiming parameters are set via ip | ||
345 | * utility before the device is opened | ||
346 | */ | ||
347 | ti_hecc_set_btc(priv); | ||
348 | |||
349 | /* Clear CCR (and CANMC register) and wait for CCE = 0 enable */ | ||
350 | hecc_write(priv, HECC_CANMC, 0); | ||
351 | |||
352 | /* | ||
353 | * INFO: CAN net stack handles bus off and hence disabling auto-bus-on | ||
354 | * hecc_set_bit(priv, HECC_CANMC, HECC_CANMC_ABO); | ||
355 | */ | ||
356 | |||
357 | /* | ||
358 | * INFO: It has been observed that at times CCE bit may not be | ||
359 | * set and hw seems to be ok even if this bit is not set so | ||
360 | */ | ||
361 | cnt = HECC_CCE_WAIT_COUNT; | ||
362 | while (hecc_get_bit(priv, HECC_CANES, HECC_CANES_CCE) && cnt != 0) { | ||
363 | --cnt; | ||
364 | udelay(10); | ||
365 | } | ||
366 | |||
367 | /* Enable TX and RX I/O Control pins */ | ||
368 | hecc_write(priv, HECC_CANTIOC, HECC_CANTIOC_EN); | ||
369 | hecc_write(priv, HECC_CANRIOC, HECC_CANRIOC_EN); | ||
370 | |||
371 | /* Clear registers for clean operation */ | ||
372 | hecc_write(priv, HECC_CANTA, HECC_SET_REG); | ||
373 | hecc_write(priv, HECC_CANRMP, HECC_SET_REG); | ||
374 | hecc_write(priv, HECC_CANGIF0, HECC_SET_REG); | ||
375 | hecc_write(priv, HECC_CANGIF1, HECC_SET_REG); | ||
376 | hecc_write(priv, HECC_CANME, 0); | ||
377 | hecc_write(priv, HECC_CANMD, 0); | ||
378 | |||
379 | /* SCC compat mode NOT supported (and not needed too) */ | ||
380 | hecc_set_bit(priv, HECC_CANMC, HECC_CANMC_SCM); | ||
381 | } | ||
382 | |||
383 | static void ti_hecc_start(struct net_device *ndev) | ||
384 | { | ||
385 | struct ti_hecc_priv *priv = netdev_priv(ndev); | ||
386 | u32 cnt, mbxno, mbx_mask; | ||
387 | |||
388 | /* put HECC in initialization mode and set btc */ | ||
389 | ti_hecc_reset(ndev); | ||
390 | |||
391 | priv->tx_head = priv->tx_tail = HECC_TX_MASK; | ||
392 | priv->rx_next = HECC_RX_FIRST_MBOX; | ||
393 | |||
394 | /* Enable local and global acceptance mask registers */ | ||
395 | hecc_write(priv, HECC_CANGAM, HECC_SET_REG); | ||
396 | |||
397 | /* Prepare configured mailboxes to receive messages */ | ||
398 | for (cnt = 0; cnt < HECC_MAX_RX_MBOX; cnt++) { | ||
399 | mbxno = HECC_MAX_MAILBOXES - 1 - cnt; | ||
400 | mbx_mask = BIT(mbxno); | ||
401 | hecc_clear_bit(priv, HECC_CANME, mbx_mask); | ||
402 | hecc_write_mbx(priv, mbxno, HECC_CANMID, HECC_CANMID_AME); | ||
403 | hecc_write_lam(priv, mbxno, HECC_SET_REG); | ||
404 | hecc_set_bit(priv, HECC_CANMD, mbx_mask); | ||
405 | hecc_set_bit(priv, HECC_CANME, mbx_mask); | ||
406 | hecc_set_bit(priv, HECC_CANMIM, mbx_mask); | ||
407 | } | ||
408 | |||
409 | /* Prevent message over-write & Enable interrupts */ | ||
410 | hecc_write(priv, HECC_CANOPC, HECC_SET_REG); | ||
411 | if (priv->int_line) { | ||
412 | hecc_write(priv, HECC_CANMIL, HECC_SET_REG); | ||
413 | hecc_write(priv, HECC_CANGIM, HECC_CANGIM_DEF_MASK | | ||
414 | HECC_CANGIM_I1EN | HECC_CANGIM_SIL); | ||
415 | } else { | ||
416 | hecc_write(priv, HECC_CANMIL, 0); | ||
417 | hecc_write(priv, HECC_CANGIM, | ||
418 | HECC_CANGIM_DEF_MASK | HECC_CANGIM_I0EN); | ||
419 | } | ||
420 | priv->can.state = CAN_STATE_ERROR_ACTIVE; | ||
421 | } | ||
422 | |||
423 | static void ti_hecc_stop(struct net_device *ndev) | ||
424 | { | ||
425 | struct ti_hecc_priv *priv = netdev_priv(ndev); | ||
426 | |||
427 | /* Disable interrupts and disable mailboxes */ | ||
428 | hecc_write(priv, HECC_CANGIM, 0); | ||
429 | hecc_write(priv, HECC_CANMIM, 0); | ||
430 | hecc_write(priv, HECC_CANME, 0); | ||
431 | priv->can.state = CAN_STATE_STOPPED; | ||
432 | } | ||
433 | |||
434 | static int ti_hecc_do_set_mode(struct net_device *ndev, enum can_mode mode) | ||
435 | { | ||
436 | int ret = 0; | ||
437 | |||
438 | switch (mode) { | ||
439 | case CAN_MODE_START: | ||
440 | ti_hecc_start(ndev); | ||
441 | netif_wake_queue(ndev); | ||
442 | break; | ||
443 | default: | ||
444 | ret = -EOPNOTSUPP; | ||
445 | break; | ||
446 | } | ||
447 | |||
448 | return ret; | ||
449 | } | ||
450 | |||
451 | /* | ||
452 | * ti_hecc_xmit: HECC Transmit | ||
453 | * | ||
454 | * The transmit mailboxes start from 0 to HECC_MAX_TX_MBOX. In HECC the | ||
455 | * priority of the mailbox for tranmission is dependent upon priority setting | ||
456 | * field in mailbox registers. The mailbox with highest value in priority field | ||
457 | * is transmitted first. Only when two mailboxes have the same value in | ||
458 | * priority field the highest numbered mailbox is transmitted first. | ||
459 | * | ||
460 | * To utilize the HECC priority feature as described above we start with the | ||
461 | * highest numbered mailbox with highest priority level and move on to the next | ||
462 | * mailbox with the same priority level and so on. Once we loop through all the | ||
463 | * transmit mailboxes we choose the next priority level (lower) and so on | ||
464 | * until we reach the lowest priority level on the lowest numbered mailbox | ||
465 | * when we stop transmission until all mailboxes are transmitted and then | ||
466 | * restart at highest numbered mailbox with highest priority. | ||
467 | * | ||
468 | * Two counters (head and tail) are used to track the next mailbox to transmit | ||
469 | * and to track the echo buffer for already transmitted mailbox. The queue | ||
470 | * is stopped when all the mailboxes are busy or when there is a priority | ||
471 | * value roll-over happens. | ||
472 | */ | ||
473 | static netdev_tx_t ti_hecc_xmit(struct sk_buff *skb, struct net_device *ndev) | ||
474 | { | ||
475 | struct ti_hecc_priv *priv = netdev_priv(ndev); | ||
476 | struct can_frame *cf = (struct can_frame *)skb->data; | ||
477 | u32 mbxno, mbx_mask, data; | ||
478 | unsigned long flags; | ||
479 | |||
480 | mbxno = get_tx_head_mb(priv); | ||
481 | mbx_mask = BIT(mbxno); | ||
482 | spin_lock_irqsave(&priv->mbx_lock, flags); | ||
483 | if (unlikely(hecc_read(priv, HECC_CANME) & mbx_mask)) { | ||
484 | spin_unlock_irqrestore(&priv->mbx_lock, flags); | ||
485 | netif_stop_queue(ndev); | ||
486 | dev_err(priv->ndev->dev.parent, | ||
487 | "BUG: TX mbx not ready tx_head=%08X, tx_tail=%08X\n", | ||
488 | priv->tx_head, priv->tx_tail); | ||
489 | return NETDEV_TX_BUSY; | ||
490 | } | ||
491 | spin_unlock_irqrestore(&priv->mbx_lock, flags); | ||
492 | |||
493 | /* Prepare mailbox for transmission */ | ||
494 | data = min_t(u8, cf->can_dlc, 8); | ||
495 | if (cf->can_id & CAN_RTR_FLAG) /* Remote transmission request */ | ||
496 | data |= HECC_CANMCF_RTR; | ||
497 | data |= get_tx_head_prio(priv) << 8; | ||
498 | hecc_write_mbx(priv, mbxno, HECC_CANMCF, data); | ||
499 | |||
500 | if (cf->can_id & CAN_EFF_FLAG) /* Extended frame format */ | ||
501 | data = (cf->can_id & CAN_EFF_MASK) | HECC_CANMID_IDE; | ||
502 | else /* Standard frame format */ | ||
503 | data = (cf->can_id & CAN_SFF_MASK) << 18; | ||
504 | hecc_write_mbx(priv, mbxno, HECC_CANMID, data); | ||
505 | hecc_write_mbx(priv, mbxno, HECC_CANMDL, | ||
506 | be32_to_cpu(*(u32 *)(cf->data))); | ||
507 | if (cf->can_dlc > 4) | ||
508 | hecc_write_mbx(priv, mbxno, HECC_CANMDH, | ||
509 | be32_to_cpu(*(u32 *)(cf->data + 4))); | ||
510 | else | ||
511 | *(u32 *)(cf->data + 4) = 0; | ||
512 | can_put_echo_skb(skb, ndev, mbxno); | ||
513 | |||
514 | spin_lock_irqsave(&priv->mbx_lock, flags); | ||
515 | --priv->tx_head; | ||
516 | if ((hecc_read(priv, HECC_CANME) & BIT(get_tx_head_mb(priv))) || | ||
517 | (priv->tx_head & HECC_TX_MASK) == HECC_TX_MASK) { | ||
518 | netif_stop_queue(ndev); | ||
519 | } | ||
520 | hecc_set_bit(priv, HECC_CANME, mbx_mask); | ||
521 | spin_unlock_irqrestore(&priv->mbx_lock, flags); | ||
522 | |||
523 | hecc_clear_bit(priv, HECC_CANMD, mbx_mask); | ||
524 | hecc_set_bit(priv, HECC_CANMIM, mbx_mask); | ||
525 | hecc_write(priv, HECC_CANTRS, mbx_mask); | ||
526 | |||
527 | return NETDEV_TX_OK; | ||
528 | } | ||
529 | |||
530 | static int ti_hecc_rx_pkt(struct ti_hecc_priv *priv, int mbxno) | ||
531 | { | ||
532 | struct net_device_stats *stats = &priv->ndev->stats; | ||
533 | struct can_frame *cf; | ||
534 | struct sk_buff *skb; | ||
535 | u32 data, mbx_mask; | ||
536 | unsigned long flags; | ||
537 | |||
538 | skb = alloc_can_skb(priv->ndev, &cf); | ||
539 | if (!skb) { | ||
540 | if (printk_ratelimit()) | ||
541 | dev_err(priv->ndev->dev.parent, | ||
542 | "ti_hecc_rx_pkt: alloc_can_skb() failed\n"); | ||
543 | return -ENOMEM; | ||
544 | } | ||
545 | |||
546 | mbx_mask = BIT(mbxno); | ||
547 | data = hecc_read_mbx(priv, mbxno, HECC_CANMID); | ||
548 | if (data & HECC_CANMID_IDE) | ||
549 | cf->can_id = (data & CAN_EFF_MASK) | CAN_EFF_FLAG; | ||
550 | else | ||
551 | cf->can_id = (data >> 18) & CAN_SFF_MASK; | ||
552 | data = hecc_read_mbx(priv, mbxno, HECC_CANMCF); | ||
553 | if (data & HECC_CANMCF_RTR) | ||
554 | cf->can_id |= CAN_RTR_FLAG; | ||
555 | cf->can_dlc = data & 0xF; | ||
556 | data = hecc_read_mbx(priv, mbxno, HECC_CANMDL); | ||
557 | *(u32 *)(cf->data) = cpu_to_be32(data); | ||
558 | if (cf->can_dlc > 4) { | ||
559 | data = hecc_read_mbx(priv, mbxno, HECC_CANMDH); | ||
560 | *(u32 *)(cf->data + 4) = cpu_to_be32(data); | ||
561 | } else { | ||
562 | *(u32 *)(cf->data + 4) = 0; | ||
563 | } | ||
564 | spin_lock_irqsave(&priv->mbx_lock, flags); | ||
565 | hecc_clear_bit(priv, HECC_CANME, mbx_mask); | ||
566 | hecc_write(priv, HECC_CANRMP, mbx_mask); | ||
567 | /* enable mailbox only if it is part of rx buffer mailboxes */ | ||
568 | if (priv->rx_next < HECC_RX_BUFFER_MBOX) | ||
569 | hecc_set_bit(priv, HECC_CANME, mbx_mask); | ||
570 | spin_unlock_irqrestore(&priv->mbx_lock, flags); | ||
571 | |||
572 | stats->rx_bytes += cf->can_dlc; | ||
573 | netif_receive_skb(skb); | ||
574 | stats->rx_packets++; | ||
575 | |||
576 | return 0; | ||
577 | } | ||
578 | |||
579 | /* | ||
580 | * ti_hecc_rx_poll - HECC receive pkts | ||
581 | * | ||
582 | * The receive mailboxes start from highest numbered mailbox till last xmit | ||
583 | * mailbox. On CAN frame reception the hardware places the data into highest | ||
584 | * numbered mailbox that matches the CAN ID filter. Since all receive mailboxes | ||
585 | * have same filtering (ALL CAN frames) packets will arrive in the highest | ||
586 | * available RX mailbox and we need to ensure in-order packet reception. | ||
587 | * | ||
588 | * To ensure the packets are received in the right order we logically divide | ||
589 | * the RX mailboxes into main and buffer mailboxes. Packets are received as per | ||
590 | * mailbox priotity (higher to lower) in the main bank and once it is full we | ||
591 | * disable further reception into main mailboxes. While the main mailboxes are | ||
592 | * processed in NAPI, further packets are received in buffer mailboxes. | ||
593 | * | ||
594 | * We maintain a RX next mailbox counter to process packets and once all main | ||
595 | * mailboxe packets are passed to the upper stack we enable all of them but | ||
596 | * continue to process packets received in buffer mailboxes. With each packet | ||
597 | * received from buffer mailbox we enable it immediately so as to handle the | ||
598 | * overflow from higher mailboxes. | ||
599 | */ | ||
600 | static int ti_hecc_rx_poll(struct napi_struct *napi, int quota) | ||
601 | { | ||
602 | struct net_device *ndev = napi->dev; | ||
603 | struct ti_hecc_priv *priv = netdev_priv(ndev); | ||
604 | u32 num_pkts = 0; | ||
605 | u32 mbx_mask; | ||
606 | unsigned long pending_pkts, flags; | ||
607 | |||
608 | if (!netif_running(ndev)) | ||
609 | return 0; | ||
610 | |||
611 | while ((pending_pkts = hecc_read(priv, HECC_CANRMP)) && | ||
612 | num_pkts < quota) { | ||
613 | mbx_mask = BIT(priv->rx_next); /* next rx mailbox to process */ | ||
614 | if (mbx_mask & pending_pkts) { | ||
615 | if (ti_hecc_rx_pkt(priv, priv->rx_next) < 0) | ||
616 | return num_pkts; | ||
617 | ++num_pkts; | ||
618 | } else if (priv->rx_next > HECC_RX_BUFFER_MBOX) { | ||
619 | break; /* pkt not received yet */ | ||
620 | } | ||
621 | --priv->rx_next; | ||
622 | if (priv->rx_next == HECC_RX_BUFFER_MBOX) { | ||
623 | /* enable high bank mailboxes */ | ||
624 | spin_lock_irqsave(&priv->mbx_lock, flags); | ||
625 | mbx_mask = hecc_read(priv, HECC_CANME); | ||
626 | mbx_mask |= HECC_RX_HIGH_MBOX_MASK; | ||
627 | hecc_write(priv, HECC_CANME, mbx_mask); | ||
628 | spin_unlock_irqrestore(&priv->mbx_lock, flags); | ||
629 | } else if (priv->rx_next == HECC_MAX_TX_MBOX - 1) { | ||
630 | priv->rx_next = HECC_RX_FIRST_MBOX; | ||
631 | break; | ||
632 | } | ||
633 | } | ||
634 | |||
635 | /* Enable packet interrupt if all pkts are handled */ | ||
636 | if (hecc_read(priv, HECC_CANRMP) == 0) { | ||
637 | napi_complete(napi); | ||
638 | /* Re-enable RX mailbox interrupts */ | ||
639 | mbx_mask = hecc_read(priv, HECC_CANMIM); | ||
640 | mbx_mask |= HECC_TX_MBOX_MASK; | ||
641 | hecc_write(priv, HECC_CANMIM, mbx_mask); | ||
642 | } | ||
643 | |||
644 | return num_pkts; | ||
645 | } | ||
646 | |||
647 | static int ti_hecc_error(struct net_device *ndev, int int_status, | ||
648 | int err_status) | ||
649 | { | ||
650 | struct ti_hecc_priv *priv = netdev_priv(ndev); | ||
651 | struct net_device_stats *stats = &ndev->stats; | ||
652 | struct can_frame *cf; | ||
653 | struct sk_buff *skb; | ||
654 | |||
655 | /* propogate the error condition to the can stack */ | ||
656 | skb = alloc_can_err_skb(ndev, &cf); | ||
657 | if (!skb) { | ||
658 | if (printk_ratelimit()) | ||
659 | dev_err(priv->ndev->dev.parent, | ||
660 | "ti_hecc_error: alloc_can_err_skb() failed\n"); | ||
661 | return -ENOMEM; | ||
662 | } | ||
663 | |||
664 | if (int_status & HECC_CANGIF_WLIF) { /* warning level int */ | ||
665 | if ((int_status & HECC_CANGIF_BOIF) == 0) { | ||
666 | priv->can.state = CAN_STATE_ERROR_WARNING; | ||
667 | ++priv->can.can_stats.error_warning; | ||
668 | cf->can_id |= CAN_ERR_CRTL; | ||
669 | if (hecc_read(priv, HECC_CANTEC) > 96) | ||
670 | cf->data[1] |= CAN_ERR_CRTL_TX_WARNING; | ||
671 | if (hecc_read(priv, HECC_CANREC) > 96) | ||
672 | cf->data[1] |= CAN_ERR_CRTL_RX_WARNING; | ||
673 | } | ||
674 | hecc_set_bit(priv, HECC_CANES, HECC_CANES_EW); | ||
675 | dev_dbg(priv->ndev->dev.parent, "Error Warning interrupt\n"); | ||
676 | hecc_clear_bit(priv, HECC_CANMC, HECC_CANMC_CCR); | ||
677 | } | ||
678 | |||
679 | if (int_status & HECC_CANGIF_EPIF) { /* error passive int */ | ||
680 | if ((int_status & HECC_CANGIF_BOIF) == 0) { | ||
681 | priv->can.state = CAN_STATE_ERROR_PASSIVE; | ||
682 | ++priv->can.can_stats.error_passive; | ||
683 | cf->can_id |= CAN_ERR_CRTL; | ||
684 | if (hecc_read(priv, HECC_CANTEC) > 127) | ||
685 | cf->data[1] |= CAN_ERR_CRTL_TX_PASSIVE; | ||
686 | if (hecc_read(priv, HECC_CANREC) > 127) | ||
687 | cf->data[1] |= CAN_ERR_CRTL_RX_PASSIVE; | ||
688 | } | ||
689 | hecc_set_bit(priv, HECC_CANES, HECC_CANES_EP); | ||
690 | dev_dbg(priv->ndev->dev.parent, "Error passive interrupt\n"); | ||
691 | hecc_clear_bit(priv, HECC_CANMC, HECC_CANMC_CCR); | ||
692 | } | ||
693 | |||
694 | /* | ||
695 | * Need to check busoff condition in error status register too to | ||
696 | * ensure warning interrupts don't hog the system | ||
697 | */ | ||
698 | if ((int_status & HECC_CANGIF_BOIF) || (err_status & HECC_CANES_BO)) { | ||
699 | priv->can.state = CAN_STATE_BUS_OFF; | ||
700 | cf->can_id |= CAN_ERR_BUSOFF; | ||
701 | hecc_set_bit(priv, HECC_CANES, HECC_CANES_BO); | ||
702 | hecc_clear_bit(priv, HECC_CANMC, HECC_CANMC_CCR); | ||
703 | /* Disable all interrupts in bus-off to avoid int hog */ | ||
704 | hecc_write(priv, HECC_CANGIM, 0); | ||
705 | can_bus_off(ndev); | ||
706 | } | ||
707 | |||
708 | if (err_status & HECC_BUS_ERROR) { | ||
709 | ++priv->can.can_stats.bus_error; | ||
710 | cf->can_id |= CAN_ERR_BUSERROR | CAN_ERR_PROT; | ||
711 | cf->data[2] |= CAN_ERR_PROT_UNSPEC; | ||
712 | if (err_status & HECC_CANES_FE) { | ||
713 | hecc_set_bit(priv, HECC_CANES, HECC_CANES_FE); | ||
714 | cf->data[2] |= CAN_ERR_PROT_FORM; | ||
715 | } | ||
716 | if (err_status & HECC_CANES_BE) { | ||
717 | hecc_set_bit(priv, HECC_CANES, HECC_CANES_BE); | ||
718 | cf->data[2] |= CAN_ERR_PROT_BIT; | ||
719 | } | ||
720 | if (err_status & HECC_CANES_SE) { | ||
721 | hecc_set_bit(priv, HECC_CANES, HECC_CANES_SE); | ||
722 | cf->data[2] |= CAN_ERR_PROT_STUFF; | ||
723 | } | ||
724 | if (err_status & HECC_CANES_CRCE) { | ||
725 | hecc_set_bit(priv, HECC_CANES, HECC_CANES_CRCE); | ||
726 | cf->data[2] |= CAN_ERR_PROT_LOC_CRC_SEQ | | ||
727 | CAN_ERR_PROT_LOC_CRC_DEL; | ||
728 | } | ||
729 | if (err_status & HECC_CANES_ACKE) { | ||
730 | hecc_set_bit(priv, HECC_CANES, HECC_CANES_ACKE); | ||
731 | cf->data[2] |= CAN_ERR_PROT_LOC_ACK | | ||
732 | CAN_ERR_PROT_LOC_ACK_DEL; | ||
733 | } | ||
734 | } | ||
735 | |||
736 | netif_receive_skb(skb); | ||
737 | stats->rx_packets++; | ||
738 | stats->rx_bytes += cf->can_dlc; | ||
739 | return 0; | ||
740 | } | ||
741 | |||
742 | static irqreturn_t ti_hecc_interrupt(int irq, void *dev_id) | ||
743 | { | ||
744 | struct net_device *ndev = (struct net_device *)dev_id; | ||
745 | struct ti_hecc_priv *priv = netdev_priv(ndev); | ||
746 | struct net_device_stats *stats = &ndev->stats; | ||
747 | u32 mbxno, mbx_mask, int_status, err_status; | ||
748 | unsigned long ack, flags; | ||
749 | |||
750 | int_status = hecc_read(priv, | ||
751 | (priv->int_line) ? HECC_CANGIF1 : HECC_CANGIF0); | ||
752 | |||
753 | if (!int_status) | ||
754 | return IRQ_NONE; | ||
755 | |||
756 | err_status = hecc_read(priv, HECC_CANES); | ||
757 | if (err_status & (HECC_BUS_ERROR | HECC_CANES_BO | | ||
758 | HECC_CANES_EP | HECC_CANES_EW)) | ||
759 | ti_hecc_error(ndev, int_status, err_status); | ||
760 | |||
761 | if (int_status & HECC_CANGIF_GMIF) { | ||
762 | while (priv->tx_tail - priv->tx_head > 0) { | ||
763 | mbxno = get_tx_tail_mb(priv); | ||
764 | mbx_mask = BIT(mbxno); | ||
765 | if (!(mbx_mask & hecc_read(priv, HECC_CANTA))) | ||
766 | break; | ||
767 | hecc_clear_bit(priv, HECC_CANMIM, mbx_mask); | ||
768 | hecc_write(priv, HECC_CANTA, mbx_mask); | ||
769 | spin_lock_irqsave(&priv->mbx_lock, flags); | ||
770 | hecc_clear_bit(priv, HECC_CANME, mbx_mask); | ||
771 | spin_unlock_irqrestore(&priv->mbx_lock, flags); | ||
772 | stats->tx_bytes += hecc_read_mbx(priv, mbxno, | ||
773 | HECC_CANMCF) & 0xF; | ||
774 | stats->tx_packets++; | ||
775 | can_get_echo_skb(ndev, mbxno); | ||
776 | --priv->tx_tail; | ||
777 | } | ||
778 | |||
779 | /* restart queue if wrap-up or if queue stalled on last pkt */ | ||
780 | if (((priv->tx_head == priv->tx_tail) && | ||
781 | ((priv->tx_head & HECC_TX_MASK) != HECC_TX_MASK)) || | ||
782 | (((priv->tx_tail & HECC_TX_MASK) == HECC_TX_MASK) && | ||
783 | ((priv->tx_head & HECC_TX_MASK) == HECC_TX_MASK))) | ||
784 | netif_wake_queue(ndev); | ||
785 | |||
786 | /* Disable RX mailbox interrupts and let NAPI reenable them */ | ||
787 | if (hecc_read(priv, HECC_CANRMP)) { | ||
788 | ack = hecc_read(priv, HECC_CANMIM); | ||
789 | ack &= BIT(HECC_MAX_TX_MBOX) - 1; | ||
790 | hecc_write(priv, HECC_CANMIM, ack); | ||
791 | napi_schedule(&priv->napi); | ||
792 | } | ||
793 | } | ||
794 | |||
795 | /* clear all interrupt conditions - read back to avoid spurious ints */ | ||
796 | if (priv->int_line) { | ||
797 | hecc_write(priv, HECC_CANGIF1, HECC_SET_REG); | ||
798 | int_status = hecc_read(priv, HECC_CANGIF1); | ||
799 | } else { | ||
800 | hecc_write(priv, HECC_CANGIF0, HECC_SET_REG); | ||
801 | int_status = hecc_read(priv, HECC_CANGIF0); | ||
802 | } | ||
803 | |||
804 | return IRQ_HANDLED; | ||
805 | } | ||
806 | |||
807 | static int ti_hecc_open(struct net_device *ndev) | ||
808 | { | ||
809 | struct ti_hecc_priv *priv = netdev_priv(ndev); | ||
810 | int err; | ||
811 | |||
812 | err = request_irq(ndev->irq, ti_hecc_interrupt, IRQF_SHARED, | ||
813 | ndev->name, ndev); | ||
814 | if (err) { | ||
815 | dev_err(ndev->dev.parent, "error requesting interrupt\n"); | ||
816 | return err; | ||
817 | } | ||
818 | |||
819 | /* Open common can device */ | ||
820 | err = open_candev(ndev); | ||
821 | if (err) { | ||
822 | dev_err(ndev->dev.parent, "open_candev() failed %d\n", err); | ||
823 | free_irq(ndev->irq, ndev); | ||
824 | return err; | ||
825 | } | ||
826 | |||
827 | clk_enable(priv->clk); | ||
828 | ti_hecc_start(ndev); | ||
829 | napi_enable(&priv->napi); | ||
830 | netif_start_queue(ndev); | ||
831 | |||
832 | return 0; | ||
833 | } | ||
834 | |||
835 | static int ti_hecc_close(struct net_device *ndev) | ||
836 | { | ||
837 | struct ti_hecc_priv *priv = netdev_priv(ndev); | ||
838 | |||
839 | netif_stop_queue(ndev); | ||
840 | napi_disable(&priv->napi); | ||
841 | ti_hecc_stop(ndev); | ||
842 | free_irq(ndev->irq, ndev); | ||
843 | clk_disable(priv->clk); | ||
844 | close_candev(ndev); | ||
845 | |||
846 | return 0; | ||
847 | } | ||
848 | |||
849 | static const struct net_device_ops ti_hecc_netdev_ops = { | ||
850 | .ndo_open = ti_hecc_open, | ||
851 | .ndo_stop = ti_hecc_close, | ||
852 | .ndo_start_xmit = ti_hecc_xmit, | ||
853 | }; | ||
854 | |||
855 | static int ti_hecc_probe(struct platform_device *pdev) | ||
856 | { | ||
857 | struct net_device *ndev = (struct net_device *)0; | ||
858 | struct ti_hecc_priv *priv; | ||
859 | struct ti_hecc_platform_data *pdata; | ||
860 | struct resource *mem, *irq; | ||
861 | void __iomem *addr; | ||
862 | int err = -ENODEV; | ||
863 | |||
864 | pdata = pdev->dev.platform_data; | ||
865 | if (!pdata) { | ||
866 | dev_err(&pdev->dev, "No platform data\n"); | ||
867 | goto probe_exit; | ||
868 | } | ||
869 | |||
870 | mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); | ||
871 | if (!mem) { | ||
872 | dev_err(&pdev->dev, "No mem resources\n"); | ||
873 | goto probe_exit; | ||
874 | } | ||
875 | irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0); | ||
876 | if (!irq) { | ||
877 | dev_err(&pdev->dev, "No irq resource\n"); | ||
878 | goto probe_exit; | ||
879 | } | ||
880 | if (!request_mem_region(mem->start, resource_size(mem), pdev->name)) { | ||
881 | dev_err(&pdev->dev, "HECC region already claimed\n"); | ||
882 | err = -EBUSY; | ||
883 | goto probe_exit; | ||
884 | } | ||
885 | addr = ioremap(mem->start, resource_size(mem)); | ||
886 | if (!addr) { | ||
887 | dev_err(&pdev->dev, "ioremap failed\n"); | ||
888 | err = -ENOMEM; | ||
889 | goto probe_exit_free_region; | ||
890 | } | ||
891 | |||
892 | ndev = alloc_candev(sizeof(struct ti_hecc_priv), HECC_MAX_TX_MBOX); | ||
893 | if (!ndev) { | ||
894 | dev_err(&pdev->dev, "alloc_candev failed\n"); | ||
895 | err = -ENOMEM; | ||
896 | goto probe_exit_iounmap; | ||
897 | } | ||
898 | |||
899 | priv = netdev_priv(ndev); | ||
900 | priv->ndev = ndev; | ||
901 | priv->base = addr; | ||
902 | priv->scc_ram_offset = pdata->scc_ram_offset; | ||
903 | priv->hecc_ram_offset = pdata->hecc_ram_offset; | ||
904 | priv->mbx_offset = pdata->mbx_offset; | ||
905 | priv->int_line = pdata->int_line; | ||
906 | |||
907 | priv->can.bittiming_const = &ti_hecc_bittiming_const; | ||
908 | priv->can.do_set_mode = ti_hecc_do_set_mode; | ||
909 | priv->can.do_get_state = ti_hecc_get_state; | ||
910 | |||
911 | ndev->irq = irq->start; | ||
912 | ndev->flags |= IFF_ECHO; | ||
913 | platform_set_drvdata(pdev, ndev); | ||
914 | SET_NETDEV_DEV(ndev, &pdev->dev); | ||
915 | ndev->netdev_ops = &ti_hecc_netdev_ops; | ||
916 | |||
917 | priv->clk = clk_get(&pdev->dev, "hecc_ck"); | ||
918 | if (IS_ERR(priv->clk)) { | ||
919 | dev_err(&pdev->dev, "No clock available\n"); | ||
920 | err = PTR_ERR(priv->clk); | ||
921 | priv->clk = NULL; | ||
922 | goto probe_exit_candev; | ||
923 | } | ||
924 | priv->can.clock.freq = clk_get_rate(priv->clk); | ||
925 | netif_napi_add(ndev, &priv->napi, ti_hecc_rx_poll, | ||
926 | HECC_DEF_NAPI_WEIGHT); | ||
927 | |||
928 | err = register_candev(ndev); | ||
929 | if (err) { | ||
930 | dev_err(&pdev->dev, "register_candev() failed\n"); | ||
931 | goto probe_exit_clk; | ||
932 | } | ||
933 | dev_info(&pdev->dev, "device registered (reg_base=%p, irq=%u)\n", | ||
934 | priv->base, (u32) ndev->irq); | ||
935 | |||
936 | return 0; | ||
937 | |||
938 | probe_exit_clk: | ||
939 | clk_put(priv->clk); | ||
940 | probe_exit_candev: | ||
941 | free_candev(ndev); | ||
942 | probe_exit_iounmap: | ||
943 | iounmap(addr); | ||
944 | probe_exit_free_region: | ||
945 | release_mem_region(mem->start, resource_size(mem)); | ||
946 | probe_exit: | ||
947 | return err; | ||
948 | } | ||
949 | |||
950 | static int __devexit ti_hecc_remove(struct platform_device *pdev) | ||
951 | { | ||
952 | struct resource *res; | ||
953 | struct net_device *ndev = platform_get_drvdata(pdev); | ||
954 | struct ti_hecc_priv *priv = netdev_priv(ndev); | ||
955 | |||
956 | clk_put(priv->clk); | ||
957 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | ||
958 | iounmap(priv->base); | ||
959 | release_mem_region(res->start, resource_size(res)); | ||
960 | unregister_candev(ndev); | ||
961 | free_candev(ndev); | ||
962 | platform_set_drvdata(pdev, NULL); | ||
963 | |||
964 | return 0; | ||
965 | } | ||
966 | |||
967 | /* TI HECC netdevice driver: platform driver structure */ | ||
968 | static struct platform_driver ti_hecc_driver = { | ||
969 | .driver = { | ||
970 | .name = DRV_NAME, | ||
971 | .owner = THIS_MODULE, | ||
972 | }, | ||
973 | .probe = ti_hecc_probe, | ||
974 | .remove = __devexit_p(ti_hecc_remove), | ||
975 | }; | ||
976 | |||
977 | static int __init ti_hecc_init_driver(void) | ||
978 | { | ||
979 | printk(KERN_INFO DRV_DESC "\n"); | ||
980 | return platform_driver_register(&ti_hecc_driver); | ||
981 | } | ||
982 | module_init(ti_hecc_init_driver); | ||
983 | |||
984 | static void __exit ti_hecc_exit_driver(void) | ||
985 | { | ||
986 | printk(KERN_INFO DRV_DESC " unloaded\n"); | ||
987 | platform_driver_unregister(&ti_hecc_driver); | ||
988 | } | ||
989 | module_exit(ti_hecc_exit_driver); | ||
990 | |||
991 | MODULE_AUTHOR("Anant Gole <anantgole@ti.com>"); | ||
992 | MODULE_LICENSE("GPL v2"); | ||
993 | MODULE_DESCRIPTION(DRV_DESC); | ||
diff --git a/drivers/net/can/usb/ems_usb.c b/drivers/net/can/usb/ems_usb.c index 9012e0abc62..3685f3e42d1 100644 --- a/drivers/net/can/usb/ems_usb.c +++ b/drivers/net/can/usb/ems_usb.c | |||
@@ -232,7 +232,7 @@ MODULE_DEVICE_TABLE(usb, ems_usb_table); | |||
232 | #define INTR_IN_BUFFER_SIZE 4 | 232 | #define INTR_IN_BUFFER_SIZE 4 |
233 | 233 | ||
234 | #define MAX_RX_URBS 10 | 234 | #define MAX_RX_URBS 10 |
235 | #define MAX_TX_URBS CAN_ECHO_SKB_MAX | 235 | #define MAX_TX_URBS 10 |
236 | 236 | ||
237 | struct ems_usb; | 237 | struct ems_usb; |
238 | 238 | ||
@@ -311,14 +311,10 @@ static void ems_usb_rx_can_msg(struct ems_usb *dev, struct ems_cpc_msg *msg) | |||
311 | int i; | 311 | int i; |
312 | struct net_device_stats *stats = &dev->netdev->stats; | 312 | struct net_device_stats *stats = &dev->netdev->stats; |
313 | 313 | ||
314 | skb = netdev_alloc_skb(dev->netdev, sizeof(struct can_frame)); | 314 | skb = alloc_can_skb(dev->netdev, &cf); |
315 | if (skb == NULL) | 315 | if (skb == NULL) |
316 | return; | 316 | return; |
317 | 317 | ||
318 | skb->protocol = htons(ETH_P_CAN); | ||
319 | |||
320 | cf = (struct can_frame *)skb_put(skb, sizeof(struct can_frame)); | ||
321 | |||
322 | cf->can_id = msg->msg.can_msg.id; | 318 | cf->can_id = msg->msg.can_msg.id; |
323 | cf->can_dlc = min_t(u8, msg->msg.can_msg.length, 8); | 319 | cf->can_dlc = min_t(u8, msg->msg.can_msg.length, 8); |
324 | 320 | ||
@@ -346,18 +342,10 @@ static void ems_usb_rx_err(struct ems_usb *dev, struct ems_cpc_msg *msg) | |||
346 | struct sk_buff *skb; | 342 | struct sk_buff *skb; |
347 | struct net_device_stats *stats = &dev->netdev->stats; | 343 | struct net_device_stats *stats = &dev->netdev->stats; |
348 | 344 | ||
349 | skb = netdev_alloc_skb(dev->netdev, sizeof(struct can_frame)); | 345 | skb = alloc_can_err_skb(dev->netdev, &cf); |
350 | if (skb == NULL) | 346 | if (skb == NULL) |
351 | return; | 347 | return; |
352 | 348 | ||
353 | skb->protocol = htons(ETH_P_CAN); | ||
354 | |||
355 | cf = (struct can_frame *)skb_put(skb, sizeof(struct can_frame)); | ||
356 | memset(cf, 0, sizeof(struct can_frame)); | ||
357 | |||
358 | cf->can_id = CAN_ERR_FLAG; | ||
359 | cf->can_dlc = CAN_ERR_DLC; | ||
360 | |||
361 | if (msg->type == CPC_MSG_TYPE_CAN_STATE) { | 349 | if (msg->type == CPC_MSG_TYPE_CAN_STATE) { |
362 | u8 state = msg->msg.can_state; | 350 | u8 state = msg->msg.can_state; |
363 | 351 | ||
@@ -1012,7 +1000,7 @@ static int ems_usb_probe(struct usb_interface *intf, | |||
1012 | struct ems_usb *dev; | 1000 | struct ems_usb *dev; |
1013 | int i, err = -ENOMEM; | 1001 | int i, err = -ENOMEM; |
1014 | 1002 | ||
1015 | netdev = alloc_candev(sizeof(struct ems_usb)); | 1003 | netdev = alloc_candev(sizeof(struct ems_usb), MAX_TX_URBS); |
1016 | if (!netdev) { | 1004 | if (!netdev) { |
1017 | dev_err(netdev->dev.parent, "Couldn't alloc candev\n"); | 1005 | dev_err(netdev->dev.parent, "Couldn't alloc candev\n"); |
1018 | return -ENOMEM; | 1006 | return -ENOMEM; |