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path: root/drivers/net/atl1c/atl1c_hw.h
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Diffstat (limited to 'drivers/net/atl1c/atl1c_hw.h')
-rw-r--r--drivers/net/atl1c/atl1c_hw.h43
1 files changed, 2 insertions, 41 deletions
diff --git a/drivers/net/atl1c/atl1c_hw.h b/drivers/net/atl1c/atl1c_hw.h
index 3dd675979aa..655fc6c4a8a 100644
--- a/drivers/net/atl1c/atl1c_hw.h
+++ b/drivers/net/atl1c/atl1c_hw.h
@@ -736,55 +736,16 @@ int atl1c_phy_power_saving(struct atl1c_hw *hw);
736#define REG_DEBUG_DATA0 0x1900 736#define REG_DEBUG_DATA0 0x1900
737#define REG_DEBUG_DATA1 0x1904 737#define REG_DEBUG_DATA1 0x1904
738 738
739/* PHY Control Register */
740#define MII_BMCR 0x00
741#define BMCR_SPEED_SELECT_MSB 0x0040 /* bits 6,13: 10=1000, 01=100, 00=10 */
742#define BMCR_COLL_TEST_ENABLE 0x0080 /* Collision test enable */
743#define BMCR_FULL_DUPLEX 0x0100 /* FDX =1, half duplex =0 */
744#define BMCR_RESTART_AUTO_NEG 0x0200 /* Restart auto negotiation */
745#define BMCR_ISOLATE 0x0400 /* Isolate PHY from MII */
746#define BMCR_POWER_DOWN 0x0800 /* Power down */
747#define BMCR_AUTO_NEG_EN 0x1000 /* Auto Neg Enable */
748#define BMCR_SPEED_SELECT_LSB 0x2000 /* bits 6,13: 10=1000, 01=100, 00=10 */
749#define BMCR_LOOPBACK 0x4000 /* 0 = normal, 1 = loopback */
750#define BMCR_RESET 0x8000 /* 0 = normal, 1 = PHY reset */
751#define BMCR_SPEED_MASK 0x2040
752#define BMCR_SPEED_1000 0x0040
753#define BMCR_SPEED_100 0x2000
754#define BMCR_SPEED_10 0x0000
755
756/* PHY Status Register */
757#define MII_BMSR 0x01
758#define BMMSR_EXTENDED_CAPS 0x0001 /* Extended register capabilities */
759#define BMSR_JABBER_DETECT 0x0002 /* Jabber Detected */
760#define BMSR_LINK_STATUS 0x0004 /* Link Status 1 = link */
761#define BMSR_AUTONEG_CAPS 0x0008 /* Auto Neg Capable */
762#define BMSR_REMOTE_FAULT 0x0010 /* Remote Fault Detect */
763#define BMSR_AUTONEG_COMPLETE 0x0020 /* Auto Neg Complete */
764#define BMSR_PREAMBLE_SUPPRESS 0x0040 /* Preamble may be suppressed */
765#define BMSR_EXTENDED_STATUS 0x0100 /* Ext. status info in Reg 0x0F */
766#define BMSR_100T2_HD_CAPS 0x0200 /* 100T2 Half Duplex Capable */
767#define BMSR_100T2_FD_CAPS 0x0400 /* 100T2 Full Duplex Capable */
768#define BMSR_10T_HD_CAPS 0x0800 /* 10T Half Duplex Capable */
769#define BMSR_10T_FD_CAPS 0x1000 /* 10T Full Duplex Capable */
770#define BMSR_100X_HD_CAPS 0x2000 /* 100X Half Duplex Capable */
771#define BMMII_SR_100X_FD_CAPS 0x4000 /* 100X Full Duplex Capable */
772#define BMMII_SR_100T4_CAPS 0x8000 /* 100T4 Capable */
773
774#define MII_PHYSID1 0x02
775#define MII_PHYSID2 0x03
776#define L1D_MPW_PHYID1 0xD01C /* V7 */ 739#define L1D_MPW_PHYID1 0xD01C /* V7 */
777#define L1D_MPW_PHYID2 0xD01D /* V1-V6 */ 740#define L1D_MPW_PHYID2 0xD01D /* V1-V6 */
778#define L1D_MPW_PHYID3 0xD01E /* V8 */ 741#define L1D_MPW_PHYID3 0xD01E /* V8 */
779 742
780 743
781/* Autoneg Advertisement Register */ 744/* Autoneg Advertisement Register */
782#define MII_ADVERTISE 0x04 745#define ADVERTISE_DEFAULT_CAP \
783#define ADVERTISE_SPEED_MASK 0x01E0 746 (ADVERTISE_ALL | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)
784#define ADVERTISE_DEFAULT_CAP 0x0DE0
785 747
786/* 1000BASE-T Control Register */ 748/* 1000BASE-T Control Register */
787#define MII_GIGA_CR 0x09
788#define GIGA_CR_1000T_REPEATER_DTE 0x0400 /* 1=Repeater/switch device port 0=DTE device */ 749#define GIGA_CR_1000T_REPEATER_DTE 0x0400 /* 1=Repeater/switch device port 0=DTE device */
789 750
790#define GIGA_CR_1000T_MS_VALUE 0x0800 /* 1=Configure PHY as Master 0=Configure PHY as Slave */ 751#define GIGA_CR_1000T_MS_VALUE 0x0800 /* 1=Configure PHY as Master 0=Configure PHY as Slave */