1 files changed, 21 insertions, 16 deletions

diff --git a/drivers/mtd/nand/fsl_elbc_nand.c b/drivers/mtd/nand/fsl_elbc_nand.c
index 80b5264f0a3..78429380611 100644
--- a/drivers/mtd/nand/fsl_elbc_nand.c
+++ b/drivers/mtd/nand/fsl_elbc_nand.c
@@ -75,6 +75,7 @@ struct fsl_elbc_fcm_ctrl {
         unsigned int use_mdr;    /* Non zero if the MDR is to be set      */
         unsigned int oob;        /* Non zero if operating on OOB data     */
         unsigned int counter;    /* counter for the initializations       */
+        unsigned int max_bitflips;  /* Saved during READ0 cmd             */
 };
 
 /* These map to the positions used by the FCM hardware ECC generator */
@@ -253,6 +254,8 @@ static int fsl_elbc_run_command(struct mtd_info *mtd)
         if (chip->ecc.mode != NAND_ECC_HW)
                 return 0;
 
+        elbc_fcm_ctrl->max_bitflips = 0;
+
         if (elbc_fcm_ctrl->read_bytes == mtd->writesize + mtd->oobsize) {
                 uint32_t lteccr = in_be32(&lbc->lteccr);
                 /*
@@ -262,11 +265,16 @@ static int fsl_elbc_run_command(struct mtd_info *mtd)
                  * bits 28-31 are uncorrectable errors, marked elsewhere.
                  * for small page nand only 1 bit is used.
                  * if the ELBC doesn't have the lteccr register it reads 0
+                 * FIXME: 4 bits can be corrected on NANDs with 2k pages, so
+                 * count the number of sub-pages with bitflips and update
+                 * ecc_stats.corrected accordingly.
                  */
                 if (lteccr & 0x000F000F)
                         out_be32(&lbc->lteccr, 0x000F000F); /* clear lteccr */
-                if (lteccr & 0x000F0000)
+                if (lteccr & 0x000F0000) {
                         mtd->ecc_stats.corrected++;
+                        elbc_fcm_ctrl->max_bitflips = 1;
+                }
         }
 
         return 0;
@@ -738,26 +746,28 @@ static int fsl_elbc_chip_init_tail(struct mtd_info *mtd)
         return 0;
 }
 
-static int fsl_elbc_read_page(struct mtd_info *mtd,
-                              struct nand_chip *chip,
-                              uint8_t *buf,
-                              int page)
+static int fsl_elbc_read_page(struct mtd_info *mtd, struct nand_chip *chip,
+                              uint8_t *buf, int oob_required, int page)
 {
+        struct fsl_elbc_mtd *priv = chip->priv;
+        struct fsl_lbc_ctrl *ctrl = priv->ctrl;
+        struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = ctrl->nand;
+
         fsl_elbc_read_buf(mtd, buf, mtd->writesize);
-        fsl_elbc_read_buf(mtd, chip->oob_poi, mtd->oobsize);
+        if (oob_required)
+                fsl_elbc_read_buf(mtd, chip->oob_poi, mtd->oobsize);
 
         if (fsl_elbc_wait(mtd, chip) & NAND_STATUS_FAIL)
                 mtd->ecc_stats.failed++;
 
-        return 0;
+        return elbc_fcm_ctrl->max_bitflips;
 }
 
 /* ECC will be calculated automatically, and errors will be detected in
  * waitfunc.
  */
-static void fsl_elbc_write_page(struct mtd_info *mtd,
-                                struct nand_chip *chip,
-                                const uint8_t *buf)
+static void fsl_elbc_write_page(struct mtd_info *mtd, struct nand_chip *chip,
+                                const uint8_t *buf, int oob_required)
 {
         fsl_elbc_write_buf(mtd, buf, mtd->writesize);
         fsl_elbc_write_buf(mtd, chip->oob_poi, mtd->oobsize);
@@ -795,7 +805,7 @@ static int fsl_elbc_chip_init(struct fsl_elbc_mtd *priv)
         chip->bbt_md = &bbt_mirror_descr;
 
         /* set up nand options */
-        chip->options = NAND_NO_READRDY | NAND_NO_AUTOINCR;
+        chip->options = NAND_NO_READRDY;
         chip->bbt_options = NAND_BBT_USE_FLASH;
 
         chip->controller = &elbc_fcm_ctrl->controller;
@@ -814,11 +824,6 @@ static int fsl_elbc_chip_init(struct fsl_elbc_mtd *priv)
                 chip->ecc.size = 512;
                 chip->ecc.bytes = 3;
                 chip->ecc.strength = 1;
-                /*
-                 * FIXME: can hardware ecc correct 4 bitflips if page size is
-                 * 2k?  Then does hardware report number of corrections for this
-                 * case?  If so, ecc_stats reporting needs to be fixed as well.
-                 */
         } else {
                 /* otherwise fall back to default software ECC */
                 chip->ecc.mode = NAND_ECC_SOFT;