diff options
Diffstat (limited to 'drivers/media/dvb/ddbridge')
-rw-r--r-- | drivers/media/dvb/ddbridge/ddbridge-core.c | 1690 | ||||
-rw-r--r-- | drivers/media/dvb/ddbridge/ddbridge-regs.h | 151 | ||||
-rw-r--r-- | drivers/media/dvb/ddbridge/ddbridge.h | 187 |
3 files changed, 2028 insertions, 0 deletions
diff --git a/drivers/media/dvb/ddbridge/ddbridge-core.c b/drivers/media/dvb/ddbridge/ddbridge-core.c new file mode 100644 index 00000000000..ba9974bc154 --- /dev/null +++ b/drivers/media/dvb/ddbridge/ddbridge-core.c | |||
@@ -0,0 +1,1690 @@ | |||
1 | /* | ||
2 | * ddbridge.c: Digital Devices PCIe bridge driver | ||
3 | * | ||
4 | * Copyright (C) 2010-2011 Digital Devices GmbH | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or | ||
7 | * modify it under the terms of the GNU General Public License | ||
8 | * version 2 only, as published by the Free Software Foundation. | ||
9 | * | ||
10 | * | ||
11 | * This program is distributed in the hope that it will be useful, | ||
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
14 | * GNU General Public License for more details. | ||
15 | * | ||
16 | * | ||
17 | * You should have received a copy of the GNU General Public License | ||
18 | * along with this program; if not, write to the Free Software | ||
19 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA | ||
20 | * 02110-1301, USA | ||
21 | * Or, point your browser to http://www.gnu.org/copyleft/gpl.html | ||
22 | */ | ||
23 | |||
24 | #include <linux/module.h> | ||
25 | #include <linux/init.h> | ||
26 | #include <linux/interrupt.h> | ||
27 | #include <linux/delay.h> | ||
28 | #include <linux/slab.h> | ||
29 | #include <linux/poll.h> | ||
30 | #include <asm/io.h> | ||
31 | #include <linux/pci.h> | ||
32 | #include <linux/pci_ids.h> | ||
33 | #include <linux/timer.h> | ||
34 | #include <linux/version.h> | ||
35 | #include <linux/i2c.h> | ||
36 | #include <linux/swab.h> | ||
37 | #include <linux/vmalloc.h> | ||
38 | #include "ddbridge.h" | ||
39 | |||
40 | #include "ddbridge-regs.h" | ||
41 | |||
42 | #include "tda18271c2dd.h" | ||
43 | #include "stv6110x.h" | ||
44 | #include "stv090x.h" | ||
45 | #include "lnbh24.h" | ||
46 | #include "drxk.h" | ||
47 | |||
48 | DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr); | ||
49 | |||
50 | /* MSI had problems with lost interrupts, fixed but needs testing */ | ||
51 | #undef CONFIG_PCI_MSI | ||
52 | |||
53 | /******************************************************************************/ | ||
54 | |||
55 | static int i2c_read(struct i2c_adapter *adapter, u8 adr, u8 *val) | ||
56 | { | ||
57 | struct i2c_msg msgs[1] = {{.addr = adr, .flags = I2C_M_RD, | ||
58 | .buf = val, .len = 1 }}; | ||
59 | return (i2c_transfer(adapter, msgs, 1) == 1) ? 0 : -1; | ||
60 | } | ||
61 | |||
62 | static int i2c_read_reg(struct i2c_adapter *adapter, u8 adr, u8 reg, u8 *val) | ||
63 | { | ||
64 | struct i2c_msg msgs[2] = {{.addr = adr, .flags = 0, | ||
65 | .buf = ®, .len = 1 }, | ||
66 | {.addr = adr, .flags = I2C_M_RD, | ||
67 | .buf = val, .len = 1 }}; | ||
68 | return (i2c_transfer(adapter, msgs, 2) == 2) ? 0 : -1; | ||
69 | } | ||
70 | |||
71 | static int i2c_read_reg16(struct i2c_adapter *adapter, u8 adr, | ||
72 | u16 reg, u8 *val) | ||
73 | { | ||
74 | u8 msg[2] = {reg>>8, reg&0xff}; | ||
75 | struct i2c_msg msgs[2] = {{.addr = adr, .flags = 0, | ||
76 | .buf = msg, .len = 2}, | ||
77 | {.addr = adr, .flags = I2C_M_RD, | ||
78 | .buf = val, .len = 1}}; | ||
79 | return (i2c_transfer(adapter, msgs, 2) == 2) ? 0 : -1; | ||
80 | } | ||
81 | |||
82 | static int ddb_i2c_cmd(struct ddb_i2c *i2c, u32 adr, u32 cmd) | ||
83 | { | ||
84 | struct ddb *dev = i2c->dev; | ||
85 | int stat; | ||
86 | u32 val; | ||
87 | |||
88 | i2c->done = 0; | ||
89 | ddbwritel((adr << 9) | cmd, i2c->regs + I2C_COMMAND); | ||
90 | stat = wait_event_timeout(i2c->wq, i2c->done == 1, HZ); | ||
91 | if (stat <= 0) { | ||
92 | printk("I2C timeout\n"); | ||
93 | { /* MSI debugging*/ | ||
94 | u32 istat = ddbreadl(INTERRUPT_STATUS); | ||
95 | printk("IRS %08x\n", istat); | ||
96 | ddbwritel(istat, INTERRUPT_ACK); | ||
97 | } | ||
98 | return -EIO; | ||
99 | } | ||
100 | val=ddbreadl(i2c->regs+I2C_COMMAND); | ||
101 | if (val & 0x70000) | ||
102 | return -EIO; | ||
103 | return 0; | ||
104 | } | ||
105 | |||
106 | static int ddb_i2c_master_xfer(struct i2c_adapter *adapter, | ||
107 | struct i2c_msg msg[], int num) | ||
108 | { | ||
109 | struct ddb_i2c *i2c = (struct ddb_i2c *)i2c_get_adapdata(adapter); | ||
110 | struct ddb *dev = i2c->dev; | ||
111 | u8 addr=0; | ||
112 | |||
113 | if (num) | ||
114 | addr = msg[0].addr; | ||
115 | |||
116 | if (num == 2 && msg[1].flags & I2C_M_RD && | ||
117 | !(msg[0].flags & I2C_M_RD)) { | ||
118 | memcpy_toio(dev->regs + I2C_TASKMEM_BASE + i2c->wbuf, | ||
119 | msg[0].buf,msg[0].len); | ||
120 | ddbwritel(msg[0].len|(msg[1].len << 16), | ||
121 | i2c->regs+I2C_TASKLENGTH); | ||
122 | if (!ddb_i2c_cmd(i2c, addr, 1)) { | ||
123 | memcpy_fromio(msg[1].buf, | ||
124 | dev->regs + I2C_TASKMEM_BASE + i2c->rbuf, | ||
125 | msg[1].len); | ||
126 | return num; | ||
127 | } | ||
128 | } | ||
129 | |||
130 | if (num == 1 && !(msg[0].flags & I2C_M_RD)) { | ||
131 | ddbcpyto(I2C_TASKMEM_BASE + i2c->wbuf,msg[0].buf, msg[0].len); | ||
132 | ddbwritel(msg[0].len, i2c->regs + I2C_TASKLENGTH); | ||
133 | if (!ddb_i2c_cmd(i2c, addr, 2)) | ||
134 | return num; | ||
135 | } | ||
136 | if (num == 1 && (msg[0].flags & I2C_M_RD)) { | ||
137 | ddbwritel(msg[0].len << 16, i2c->regs + I2C_TASKLENGTH); | ||
138 | if (!ddb_i2c_cmd(i2c, addr, 3)) { | ||
139 | ddbcpyfrom(msg[0].buf, | ||
140 | I2C_TASKMEM_BASE + i2c->rbuf, msg[0].len); | ||
141 | return num; | ||
142 | } | ||
143 | } | ||
144 | return -EIO; | ||
145 | } | ||
146 | |||
147 | |||
148 | static u32 ddb_i2c_functionality(struct i2c_adapter *adap) | ||
149 | { | ||
150 | return I2C_FUNC_SMBUS_EMUL; | ||
151 | } | ||
152 | |||
153 | struct i2c_algorithm ddb_i2c_algo = { | ||
154 | .master_xfer = ddb_i2c_master_xfer, | ||
155 | .functionality = ddb_i2c_functionality, | ||
156 | }; | ||
157 | |||
158 | static void ddb_i2c_release(struct ddb *dev) | ||
159 | { | ||
160 | int i; | ||
161 | struct ddb_i2c *i2c; | ||
162 | struct i2c_adapter *adap; | ||
163 | |||
164 | for (i = 0; i < dev->info->port_num; i++) { | ||
165 | i2c = &dev->i2c[i]; | ||
166 | adap = &i2c->adap; | ||
167 | i2c_del_adapter(adap); | ||
168 | } | ||
169 | } | ||
170 | |||
171 | static int ddb_i2c_init(struct ddb *dev) | ||
172 | { | ||
173 | int i, j, stat = 0; | ||
174 | struct ddb_i2c *i2c; | ||
175 | struct i2c_adapter *adap; | ||
176 | |||
177 | for (i = 0; i < dev->info->port_num; i++) { | ||
178 | i2c = &dev->i2c[i]; | ||
179 | i2c->dev = dev; | ||
180 | i2c->nr = i; | ||
181 | i2c->wbuf = i * (I2C_TASKMEM_SIZE / 4); | ||
182 | i2c->rbuf = i2c->wbuf + (I2C_TASKMEM_SIZE / 8); | ||
183 | i2c->regs = 0x80 + i * 0x20; | ||
184 | ddbwritel(I2C_SPEED_100, i2c->regs + I2C_TIMING); | ||
185 | ddbwritel((i2c->rbuf << 16) | i2c->wbuf, | ||
186 | i2c->regs + I2C_TASKADDRESS); | ||
187 | init_waitqueue_head(&i2c->wq); | ||
188 | |||
189 | adap = &i2c->adap; | ||
190 | i2c_set_adapdata(adap, i2c); | ||
191 | #ifdef I2C_ADAP_CLASS_TV_DIGITAL | ||
192 | adap->class = I2C_ADAP_CLASS_TV_DIGITAL|I2C_CLASS_TV_ANALOG; | ||
193 | #else | ||
194 | #ifdef I2C_CLASS_TV_ANALOG | ||
195 | adap->class = I2C_CLASS_TV_ANALOG; | ||
196 | #endif | ||
197 | #endif | ||
198 | strcpy(adap->name, "ddbridge"); | ||
199 | adap->algo = &ddb_i2c_algo; | ||
200 | adap->algo_data = (void *)i2c; | ||
201 | adap->dev.parent = &dev->pdev->dev; | ||
202 | stat = i2c_add_adapter(adap); | ||
203 | if (stat) | ||
204 | break; | ||
205 | } | ||
206 | if (stat) | ||
207 | for (j = 0; j < i; j++) { | ||
208 | i2c = &dev->i2c[j]; | ||
209 | adap = &i2c->adap; | ||
210 | i2c_del_adapter(adap); | ||
211 | } | ||
212 | return stat; | ||
213 | } | ||
214 | |||
215 | |||
216 | /******************************************************************************/ | ||
217 | /******************************************************************************/ | ||
218 | /******************************************************************************/ | ||
219 | |||
220 | static void set_table(struct ddb *dev, u32 off, | ||
221 | dma_addr_t *pbuf, u32 num) | ||
222 | { | ||
223 | u32 i, base; | ||
224 | u64 mem; | ||
225 | |||
226 | base = DMA_BASE_ADDRESS_TABLE + off; | ||
227 | for (i = 0; i < num; i++) { | ||
228 | mem = pbuf[i]; | ||
229 | ddbwritel(mem & 0xffffffff, base + i * 8); | ||
230 | ddbwritel(mem >> 32, base + i * 8 + 4); | ||
231 | } | ||
232 | } | ||
233 | |||
234 | static void ddb_address_table(struct ddb *dev) | ||
235 | { | ||
236 | u32 i, j, base; | ||
237 | u64 mem; | ||
238 | dma_addr_t *pbuf; | ||
239 | |||
240 | for (i = 0; i < dev->info->port_num * 2; i++) { | ||
241 | base = DMA_BASE_ADDRESS_TABLE + i * 0x100; | ||
242 | pbuf = dev->input[i].pbuf; | ||
243 | for (j = 0; j < dev->input[i].dma_buf_num; j++) { | ||
244 | mem = pbuf[j]; | ||
245 | ddbwritel(mem & 0xffffffff, base + j * 8); | ||
246 | ddbwritel(mem >> 32, base + j * 8 + 4); | ||
247 | } | ||
248 | } | ||
249 | for (i = 0; i < dev->info->port_num; i++) { | ||
250 | base = DMA_BASE_ADDRESS_TABLE + 0x800 + i * 0x100; | ||
251 | pbuf = dev->output[i].pbuf; | ||
252 | for (j = 0; j < dev->output[i].dma_buf_num; j++) { | ||
253 | mem = pbuf[j]; | ||
254 | ddbwritel(mem & 0xffffffff, base + j * 8); | ||
255 | ddbwritel(mem >> 32, base + j * 8 + 4); | ||
256 | } | ||
257 | } | ||
258 | } | ||
259 | |||
260 | static void io_free(struct pci_dev *pdev, u8 **vbuf, | ||
261 | dma_addr_t *pbuf, u32 size, int num) | ||
262 | { | ||
263 | int i; | ||
264 | |||
265 | for (i = 0; i < num; i++) { | ||
266 | if (vbuf[i]) { | ||
267 | pci_free_consistent(pdev, size, vbuf[i], pbuf[i]); | ||
268 | vbuf[i] = 0; | ||
269 | } | ||
270 | } | ||
271 | } | ||
272 | |||
273 | static int io_alloc(struct pci_dev *pdev, u8 **vbuf, | ||
274 | dma_addr_t *pbuf, u32 size, int num) | ||
275 | { | ||
276 | int i; | ||
277 | |||
278 | for (i = 0; i < num; i++) { | ||
279 | vbuf[i] = pci_alloc_consistent(pdev, size, &pbuf[i]); | ||
280 | if (!vbuf[i]) | ||
281 | return -ENOMEM; | ||
282 | } | ||
283 | return 0; | ||
284 | } | ||
285 | |||
286 | static int ddb_buffers_alloc(struct ddb *dev) | ||
287 | { | ||
288 | int i; | ||
289 | struct ddb_port *port; | ||
290 | |||
291 | for (i = 0; i < dev->info->port_num; i++) { | ||
292 | port = &dev->port[i]; | ||
293 | switch (port->class) { | ||
294 | case DDB_PORT_TUNER: | ||
295 | if (io_alloc(dev->pdev, port->input[0]->vbuf, | ||
296 | port->input[0]->pbuf, | ||
297 | port->input[0]->dma_buf_size, | ||
298 | port->input[0]->dma_buf_num) < 0) | ||
299 | return -1; | ||
300 | if (io_alloc(dev->pdev, port->input[1]->vbuf, | ||
301 | port->input[1]->pbuf, | ||
302 | port->input[1]->dma_buf_size, | ||
303 | port->input[1]->dma_buf_num) < 0) | ||
304 | return -1; | ||
305 | break; | ||
306 | case DDB_PORT_CI: | ||
307 | if (io_alloc(dev->pdev, port->input[0]->vbuf, | ||
308 | port->input[0]->pbuf, | ||
309 | port->input[0]->dma_buf_size, | ||
310 | port->input[0]->dma_buf_num) < 0) | ||
311 | return -1; | ||
312 | if (io_alloc(dev->pdev, port->output->vbuf, | ||
313 | port->output->pbuf, | ||
314 | port->output->dma_buf_size, | ||
315 | port->output->dma_buf_num) < 0) | ||
316 | return -1; | ||
317 | break; | ||
318 | default: | ||
319 | break; | ||
320 | } | ||
321 | } | ||
322 | ddb_address_table(dev); | ||
323 | return 0; | ||
324 | } | ||
325 | |||
326 | static void ddb_buffers_free(struct ddb *dev) | ||
327 | { | ||
328 | int i; | ||
329 | struct ddb_port *port; | ||
330 | |||
331 | for (i = 0; i < dev->info->port_num; i++) { | ||
332 | port = &dev->port[i]; | ||
333 | io_free(dev->pdev, port->input[0]->vbuf, | ||
334 | port->input[0]->pbuf, | ||
335 | port->input[0]->dma_buf_size, | ||
336 | port->input[0]->dma_buf_num); | ||
337 | io_free(dev->pdev, port->input[1]->vbuf, | ||
338 | port->input[1]->pbuf, | ||
339 | port->input[1]->dma_buf_size, | ||
340 | port->input[1]->dma_buf_num); | ||
341 | io_free(dev->pdev, port->output->vbuf, | ||
342 | port->output->pbuf, | ||
343 | port->output->dma_buf_size, | ||
344 | port->output->dma_buf_num); | ||
345 | } | ||
346 | } | ||
347 | |||
348 | static void ddb_input_start(struct ddb_input *input) | ||
349 | { | ||
350 | struct ddb *dev = input->port->dev; | ||
351 | |||
352 | spin_lock_irq(&input->lock); | ||
353 | input->cbuf = 0; | ||
354 | input->coff = 0; | ||
355 | |||
356 | /* reset */ | ||
357 | ddbwritel(0, TS_INPUT_CONTROL(input->nr)); | ||
358 | ddbwritel(2, TS_INPUT_CONTROL(input->nr)); | ||
359 | ddbwritel(0, TS_INPUT_CONTROL(input->nr)); | ||
360 | |||
361 | ddbwritel((1 << 16) | | ||
362 | (input->dma_buf_num << 11) | | ||
363 | (input->dma_buf_size >> 7), | ||
364 | DMA_BUFFER_SIZE(input->nr)); | ||
365 | ddbwritel(0, DMA_BUFFER_ACK(input->nr)); | ||
366 | |||
367 | ddbwritel(1, DMA_BASE_WRITE); | ||
368 | ddbwritel(3, DMA_BUFFER_CONTROL(input->nr)); | ||
369 | ddbwritel(9, TS_INPUT_CONTROL(input->nr)); | ||
370 | input->running = 1; | ||
371 | spin_unlock_irq(&input->lock); | ||
372 | } | ||
373 | |||
374 | static void ddb_input_stop(struct ddb_input *input) | ||
375 | { | ||
376 | struct ddb *dev = input->port->dev; | ||
377 | |||
378 | spin_lock_irq(&input->lock); | ||
379 | ddbwritel(0, TS_INPUT_CONTROL(input->nr)); | ||
380 | ddbwritel(0, DMA_BUFFER_CONTROL(input->nr)); | ||
381 | input->running = 0; | ||
382 | spin_unlock_irq(&input->lock); | ||
383 | } | ||
384 | |||
385 | static void ddb_output_start(struct ddb_output *output) | ||
386 | { | ||
387 | struct ddb *dev = output->port->dev; | ||
388 | |||
389 | spin_lock_irq(&output->lock); | ||
390 | output->cbuf = 0; | ||
391 | output->coff = 0; | ||
392 | ddbwritel(0, TS_OUTPUT_CONTROL(output->nr)); | ||
393 | ddbwritel(2, TS_OUTPUT_CONTROL(output->nr)); | ||
394 | ddbwritel(0, TS_OUTPUT_CONTROL(output->nr)); | ||
395 | ddbwritel(0x3c, TS_OUTPUT_CONTROL(output->nr)); | ||
396 | ddbwritel((1 << 16) | | ||
397 | (output->dma_buf_num << 11) | | ||
398 | (output->dma_buf_size >> 7), | ||
399 | DMA_BUFFER_SIZE(output->nr + 8)); | ||
400 | ddbwritel(0, DMA_BUFFER_ACK(output->nr + 8)); | ||
401 | |||
402 | ddbwritel(1, DMA_BASE_READ); | ||
403 | ddbwritel(3, DMA_BUFFER_CONTROL(output->nr + 8)); | ||
404 | //ddbwritel(0xbd, TS_OUTPUT_CONTROL(output->nr)); | ||
405 | ddbwritel(0x1d, TS_OUTPUT_CONTROL(output->nr)); | ||
406 | output->running = 1; | ||
407 | spin_unlock_irq(&output->lock); | ||
408 | } | ||
409 | |||
410 | static void ddb_output_stop(struct ddb_output *output) | ||
411 | { | ||
412 | struct ddb *dev = output->port->dev; | ||
413 | |||
414 | spin_lock_irq(&output->lock); | ||
415 | ddbwritel(0, TS_OUTPUT_CONTROL(output->nr)); | ||
416 | ddbwritel(0, DMA_BUFFER_CONTROL(output->nr + 8)); | ||
417 | output->running = 0; | ||
418 | spin_unlock_irq(&output->lock); | ||
419 | } | ||
420 | |||
421 | static u32 ddb_output_free(struct ddb_output *output) | ||
422 | { | ||
423 | u32 idx, off, stat = output->stat; | ||
424 | s32 diff; | ||
425 | |||
426 | idx = (stat >> 11) & 0x1f; | ||
427 | off = (stat & 0x7ff) << 7; | ||
428 | |||
429 | if (output->cbuf != idx) { | ||
430 | if ((((output->cbuf + 1) % output->dma_buf_num) == idx) && | ||
431 | (output->dma_buf_size - output->coff <= 188)) | ||
432 | return 0; | ||
433 | return 188; | ||
434 | } | ||
435 | diff = off - output->coff; | ||
436 | if (diff <= 0 || diff > 188) | ||
437 | return 188; | ||
438 | return 0; | ||
439 | } | ||
440 | |||
441 | static ssize_t ddb_output_write(struct ddb_output* output, | ||
442 | const u8 *buf, size_t count) | ||
443 | { | ||
444 | struct ddb *dev = output->port->dev; | ||
445 | u32 idx, off, stat = output->stat; | ||
446 | u32 left = count, len; | ||
447 | |||
448 | idx = (stat >> 11) & 0x1f; | ||
449 | off = (stat & 0x7ff) << 7; | ||
450 | |||
451 | while (left) { | ||
452 | len = output->dma_buf_size - output->coff; | ||
453 | if ((((output->cbuf + 1) % output->dma_buf_num) == idx) && | ||
454 | (off == 0)) { | ||
455 | if (len<=188) | ||
456 | break; | ||
457 | len-=188; | ||
458 | } | ||
459 | if (output->cbuf == idx) { | ||
460 | if (off > output->coff) { | ||
461 | #if 1 | ||
462 | len = off - output->coff; | ||
463 | len -= (len % 188); | ||
464 | if (len <= 188) | ||
465 | |||
466 | #endif | ||
467 | break; | ||
468 | len -= 188; | ||
469 | } | ||
470 | } | ||
471 | if (len > left) | ||
472 | len = left; | ||
473 | if (copy_from_user(output->vbuf[output->cbuf] + output->coff, | ||
474 | buf, len)) | ||
475 | return -EIO; | ||
476 | left -= len; | ||
477 | buf += len; | ||
478 | output->coff += len; | ||
479 | if (output->coff == output->dma_buf_size) { | ||
480 | output->coff = 0; | ||
481 | output->cbuf = ((output->cbuf + 1) % output->dma_buf_num); | ||
482 | } | ||
483 | ddbwritel((output->cbuf << 11) | (output->coff >> 7), | ||
484 | DMA_BUFFER_ACK(output->nr + 8)); | ||
485 | } | ||
486 | return count - left; | ||
487 | } | ||
488 | |||
489 | static u32 ddb_input_avail(struct ddb_input *input) | ||
490 | { | ||
491 | struct ddb *dev = input->port->dev; | ||
492 | u32 idx, off, stat = input->stat; | ||
493 | u32 ctrl = ddbreadl(DMA_BUFFER_CONTROL(input->nr)); | ||
494 | |||
495 | idx = (stat >> 11) & 0x1f; | ||
496 | off = (stat & 0x7ff) << 7; | ||
497 | |||
498 | if (ctrl & 4) { | ||
499 | printk("IA %d %d %08x\n", idx, off, ctrl); | ||
500 | ddbwritel(input->stat, DMA_BUFFER_ACK(input->nr)); | ||
501 | return 0; | ||
502 | } | ||
503 | if (input->cbuf != idx) | ||
504 | return 188; | ||
505 | return 0; | ||
506 | } | ||
507 | |||
508 | static size_t ddb_input_read(struct ddb_input *input, u8 *buf, size_t count) | ||
509 | { | ||
510 | struct ddb *dev = input->port->dev; | ||
511 | u32 left = count; | ||
512 | u32 idx, off, free, stat = input->stat; | ||
513 | int ret; | ||
514 | |||
515 | idx = (stat >> 11) & 0x1f; | ||
516 | off = (stat & 0x7ff) << 7; | ||
517 | |||
518 | while (left) { | ||
519 | if (input->cbuf == idx) | ||
520 | return count - left; | ||
521 | free = input->dma_buf_size - input->coff; | ||
522 | if (free > left) | ||
523 | free = left; | ||
524 | ret = copy_to_user(buf, input->vbuf[input->cbuf] + | ||
525 | input->coff, free); | ||
526 | input->coff += free; | ||
527 | if (input->coff == input->dma_buf_size) { | ||
528 | input->coff = 0; | ||
529 | input->cbuf = (input->cbuf+1) % input->dma_buf_num; | ||
530 | } | ||
531 | left -= free; | ||
532 | ddbwritel((input->cbuf << 11) | (input->coff >> 7), | ||
533 | DMA_BUFFER_ACK(input->nr)); | ||
534 | } | ||
535 | return count; | ||
536 | } | ||
537 | |||
538 | /******************************************************************************/ | ||
539 | /******************************************************************************/ | ||
540 | /******************************************************************************/ | ||
541 | |||
542 | #if 0 | ||
543 | static struct ddb_input *fe2input(struct ddb *dev, struct dvb_frontend *fe) | ||
544 | { | ||
545 | int i; | ||
546 | |||
547 | for (i = 0; i < dev->info->port_num * 2; i++) { | ||
548 | if (dev->input[i].fe==fe) | ||
549 | return &dev->input[i]; | ||
550 | } | ||
551 | return NULL; | ||
552 | } | ||
553 | #endif | ||
554 | |||
555 | static int drxk_gate_ctrl(struct dvb_frontend *fe, int enable) | ||
556 | { | ||
557 | struct ddb_input *input = fe->sec_priv; | ||
558 | struct ddb_port *port = input->port; | ||
559 | int status; | ||
560 | |||
561 | if (enable) { | ||
562 | mutex_lock(&port->i2c_gate_lock); | ||
563 | status = input->gate_ctrl(fe, 1); | ||
564 | } else { | ||
565 | status = input->gate_ctrl(fe, 0); | ||
566 | mutex_unlock(&port->i2c_gate_lock); | ||
567 | } | ||
568 | return status; | ||
569 | } | ||
570 | |||
571 | static int demod_attach_drxk(struct ddb_input *input) | ||
572 | { | ||
573 | struct i2c_adapter *i2c = &input->port->i2c->adap; | ||
574 | struct dvb_frontend *fe; | ||
575 | |||
576 | fe=input->fe = dvb_attach(drxk_attach, | ||
577 | i2c, 0x29 + (input->nr&1), | ||
578 | &input->fe2); | ||
579 | if (!input->fe) { | ||
580 | printk("No DRXK found!\n"); | ||
581 | return -ENODEV; | ||
582 | } | ||
583 | fe->sec_priv = input; | ||
584 | input->gate_ctrl = fe->ops.i2c_gate_ctrl; | ||
585 | fe->ops.i2c_gate_ctrl = drxk_gate_ctrl; | ||
586 | return 0; | ||
587 | } | ||
588 | |||
589 | static int tuner_attach_tda18271(struct ddb_input *input) | ||
590 | { | ||
591 | struct i2c_adapter *i2c = &input->port->i2c->adap; | ||
592 | struct dvb_frontend *fe; | ||
593 | |||
594 | if (input->fe->ops.i2c_gate_ctrl) | ||
595 | input->fe->ops.i2c_gate_ctrl(input->fe, 1); | ||
596 | fe = dvb_attach(tda18271c2dd_attach, input->fe, i2c, 0x60); | ||
597 | if (!fe) { | ||
598 | printk("No TDA18271 found!\n"); | ||
599 | return -ENODEV; | ||
600 | } | ||
601 | if (input->fe->ops.i2c_gate_ctrl) | ||
602 | input->fe->ops.i2c_gate_ctrl(input->fe, 0); | ||
603 | return 0; | ||
604 | } | ||
605 | |||
606 | /******************************************************************************/ | ||
607 | /******************************************************************************/ | ||
608 | /******************************************************************************/ | ||
609 | |||
610 | static struct stv090x_config stv0900 = { | ||
611 | .device = STV0900, | ||
612 | .demod_mode = STV090x_DUAL, | ||
613 | .clk_mode = STV090x_CLK_EXT, | ||
614 | |||
615 | .xtal = 27000000, | ||
616 | .address = 0x69, | ||
617 | |||
618 | .ts1_mode = STV090x_TSMODE_SERIAL_PUNCTURED, | ||
619 | .ts2_mode = STV090x_TSMODE_SERIAL_PUNCTURED, | ||
620 | |||
621 | .repeater_level = STV090x_RPTLEVEL_16, | ||
622 | |||
623 | .adc1_range = STV090x_ADC_1Vpp, | ||
624 | .adc2_range = STV090x_ADC_1Vpp, | ||
625 | |||
626 | .diseqc_envelope_mode = true, | ||
627 | }; | ||
628 | |||
629 | static struct stv090x_config stv0900_aa = { | ||
630 | .device = STV0900, | ||
631 | .demod_mode = STV090x_DUAL, | ||
632 | .clk_mode = STV090x_CLK_EXT, | ||
633 | |||
634 | .xtal = 27000000, | ||
635 | .address = 0x68, | ||
636 | |||
637 | .ts1_mode = STV090x_TSMODE_SERIAL_PUNCTURED, | ||
638 | .ts2_mode = STV090x_TSMODE_SERIAL_PUNCTURED, | ||
639 | |||
640 | .repeater_level = STV090x_RPTLEVEL_16, | ||
641 | |||
642 | .adc1_range = STV090x_ADC_1Vpp, | ||
643 | .adc2_range = STV090x_ADC_1Vpp, | ||
644 | |||
645 | .diseqc_envelope_mode = true, | ||
646 | }; | ||
647 | |||
648 | static struct stv6110x_config stv6110a = { | ||
649 | .addr = 0x60, | ||
650 | .refclk = 27000000, | ||
651 | .clk_div = 1, | ||
652 | }; | ||
653 | |||
654 | static struct stv6110x_config stv6110b = { | ||
655 | .addr = 0x63, | ||
656 | .refclk = 27000000, | ||
657 | .clk_div = 1, | ||
658 | }; | ||
659 | |||
660 | static int demod_attach_stv0900(struct ddb_input *input, int type) | ||
661 | { | ||
662 | struct i2c_adapter *i2c = &input->port->i2c->adap; | ||
663 | struct stv090x_config *feconf = type ? &stv0900_aa : &stv0900; | ||
664 | |||
665 | input->fe=dvb_attach(stv090x_attach, feconf, i2c, | ||
666 | (input->nr & 1) ? STV090x_DEMODULATOR_1 | ||
667 | : STV090x_DEMODULATOR_0); | ||
668 | if (!input->fe) { | ||
669 | printk("No STV0900 found!\n"); | ||
670 | return -ENODEV; | ||
671 | } | ||
672 | if (!dvb_attach(lnbh24_attach, input->fe, i2c, 0, | ||
673 | 0, (input->nr & 1) ? | ||
674 | (0x09 - type) : (0x0b - type))) { | ||
675 | printk("No LNBH24 found!\n"); | ||
676 | return -ENODEV; | ||
677 | } | ||
678 | return 0; | ||
679 | } | ||
680 | |||
681 | static int tuner_attach_stv6110(struct ddb_input *input, int type) | ||
682 | { | ||
683 | struct i2c_adapter *i2c = &input->port->i2c->adap; | ||
684 | struct stv090x_config *feconf = type ? &stv0900_aa : &stv0900; | ||
685 | struct stv6110x_config *tunerconf = (input->nr & 1) ? | ||
686 | &stv6110b : &stv6110a; | ||
687 | struct stv6110x_devctl *ctl; | ||
688 | |||
689 | ctl = dvb_attach(stv6110x_attach, input->fe, tunerconf, i2c); | ||
690 | if (!ctl) { | ||
691 | printk("No STV6110X found!\n"); | ||
692 | return -ENODEV; | ||
693 | } | ||
694 | printk("attach tuner input %d adr %02x\n", input->nr, tunerconf->addr); | ||
695 | |||
696 | feconf->tuner_init = ctl->tuner_init; | ||
697 | feconf->tuner_sleep = ctl->tuner_sleep; | ||
698 | feconf->tuner_set_mode = ctl->tuner_set_mode; | ||
699 | feconf->tuner_set_frequency = ctl->tuner_set_frequency; | ||
700 | feconf->tuner_get_frequency = ctl->tuner_get_frequency; | ||
701 | feconf->tuner_set_bandwidth = ctl->tuner_set_bandwidth; | ||
702 | feconf->tuner_get_bandwidth = ctl->tuner_get_bandwidth; | ||
703 | feconf->tuner_set_bbgain = ctl->tuner_set_bbgain; | ||
704 | feconf->tuner_get_bbgain = ctl->tuner_get_bbgain; | ||
705 | feconf->tuner_set_refclk = ctl->tuner_set_refclk; | ||
706 | feconf->tuner_get_status = ctl->tuner_get_status; | ||
707 | |||
708 | return 0; | ||
709 | } | ||
710 | |||
711 | int my_dvb_dmx_ts_card_init(struct dvb_demux *dvbdemux, char *id, | ||
712 | int (*start_feed)(struct dvb_demux_feed *), | ||
713 | int (*stop_feed)(struct dvb_demux_feed *), | ||
714 | void *priv) | ||
715 | { | ||
716 | dvbdemux->priv = priv; | ||
717 | |||
718 | dvbdemux->filternum = 256; | ||
719 | dvbdemux->feednum = 256; | ||
720 | dvbdemux->start_feed = start_feed; | ||
721 | dvbdemux->stop_feed = stop_feed; | ||
722 | dvbdemux->write_to_decoder = NULL; | ||
723 | dvbdemux->dmx.capabilities = (DMX_TS_FILTERING | | ||
724 | DMX_SECTION_FILTERING | | ||
725 | DMX_MEMORY_BASED_FILTERING); | ||
726 | return dvb_dmx_init(dvbdemux); | ||
727 | } | ||
728 | |||
729 | int my_dvb_dmxdev_ts_card_init(struct dmxdev *dmxdev, | ||
730 | struct dvb_demux *dvbdemux, | ||
731 | struct dmx_frontend *hw_frontend, | ||
732 | struct dmx_frontend *mem_frontend, | ||
733 | struct dvb_adapter *dvb_adapter) | ||
734 | { | ||
735 | int ret; | ||
736 | |||
737 | dmxdev->filternum = 256; | ||
738 | dmxdev->demux = &dvbdemux->dmx; | ||
739 | dmxdev->capabilities = 0; | ||
740 | ret = dvb_dmxdev_init(dmxdev, dvb_adapter); | ||
741 | if (ret < 0) | ||
742 | return ret; | ||
743 | |||
744 | hw_frontend->source = DMX_FRONTEND_0; | ||
745 | dvbdemux->dmx.add_frontend(&dvbdemux->dmx, hw_frontend); | ||
746 | mem_frontend->source = DMX_MEMORY_FE; | ||
747 | dvbdemux->dmx.add_frontend(&dvbdemux->dmx, mem_frontend); | ||
748 | return dvbdemux->dmx.connect_frontend(&dvbdemux->dmx, hw_frontend); | ||
749 | } | ||
750 | |||
751 | static int start_feed(struct dvb_demux_feed *dvbdmxfeed) | ||
752 | { | ||
753 | struct dvb_demux *dvbdmx = dvbdmxfeed->demux; | ||
754 | struct ddb_input *input = dvbdmx->priv; | ||
755 | |||
756 | if (!input->users) | ||
757 | ddb_input_start(input); | ||
758 | |||
759 | return ++input->users; | ||
760 | } | ||
761 | |||
762 | static int stop_feed(struct dvb_demux_feed *dvbdmxfeed) | ||
763 | { | ||
764 | struct dvb_demux *dvbdmx = dvbdmxfeed->demux; | ||
765 | struct ddb_input *input = dvbdmx->priv; | ||
766 | |||
767 | if (--input->users) | ||
768 | return input->users; | ||
769 | |||
770 | ddb_input_stop(input); | ||
771 | return 0; | ||
772 | } | ||
773 | |||
774 | |||
775 | static void dvb_input_detach(struct ddb_input *input) | ||
776 | { | ||
777 | struct dvb_adapter *adap = &input->adap; | ||
778 | struct dvb_demux *dvbdemux = &input->demux; | ||
779 | |||
780 | switch (input->attached) { | ||
781 | case 5: | ||
782 | if (input->fe2) | ||
783 | dvb_unregister_frontend(input->fe2); | ||
784 | if (input->fe) { | ||
785 | dvb_unregister_frontend(input->fe); | ||
786 | dvb_frontend_detach(input->fe); | ||
787 | input->fe = NULL; | ||
788 | } | ||
789 | case 4: | ||
790 | dvb_net_release(&input->dvbnet); | ||
791 | |||
792 | case 3: | ||
793 | dvbdemux->dmx.close(&dvbdemux->dmx); | ||
794 | dvbdemux->dmx.remove_frontend(&dvbdemux->dmx, | ||
795 | &input->hw_frontend); | ||
796 | dvbdemux->dmx.remove_frontend(&dvbdemux->dmx, | ||
797 | &input->mem_frontend); | ||
798 | dvb_dmxdev_release(&input->dmxdev); | ||
799 | |||
800 | case 2: | ||
801 | dvb_dmx_release(&input->demux); | ||
802 | |||
803 | case 1: | ||
804 | dvb_unregister_adapter(adap); | ||
805 | } | ||
806 | input->attached = 0; | ||
807 | } | ||
808 | |||
809 | static int dvb_input_attach(struct ddb_input *input) | ||
810 | { | ||
811 | int ret; | ||
812 | struct ddb_port *port = input->port; | ||
813 | struct dvb_adapter *adap = &input->adap; | ||
814 | struct dvb_demux *dvbdemux = &input->demux; | ||
815 | |||
816 | ret=dvb_register_adapter(adap, "DDBridge",THIS_MODULE, | ||
817 | &input->port->dev->pdev->dev, | ||
818 | adapter_nr); | ||
819 | if (ret < 0) { | ||
820 | printk("ddbridge: Could not register adapter." | ||
821 | "Check if you enabled enough adapters in dvb-core!\n"); | ||
822 | return ret; | ||
823 | } | ||
824 | input->attached = 1; | ||
825 | |||
826 | ret = my_dvb_dmx_ts_card_init(dvbdemux, "SW demux", | ||
827 | start_feed, | ||
828 | stop_feed, input); | ||
829 | if (ret < 0) | ||
830 | return ret; | ||
831 | input->attached = 2; | ||
832 | |||
833 | ret = my_dvb_dmxdev_ts_card_init(&input->dmxdev, &input->demux, | ||
834 | &input->hw_frontend, | ||
835 | &input->mem_frontend, adap); | ||
836 | if (ret < 0) | ||
837 | return ret; | ||
838 | input->attached = 3; | ||
839 | |||
840 | ret = dvb_net_init(adap, &input->dvbnet, input->dmxdev.demux); | ||
841 | if (ret < 0) | ||
842 | return ret; | ||
843 | input->attached = 4; | ||
844 | |||
845 | input->fe = 0; | ||
846 | switch (port->type) { | ||
847 | case DDB_TUNER_DVBS_ST: | ||
848 | if (demod_attach_stv0900(input, 0) < 0) | ||
849 | return -ENODEV; | ||
850 | if (tuner_attach_stv6110(input, 0) < 0) | ||
851 | return -ENODEV; | ||
852 | if (input->fe) { | ||
853 | if (dvb_register_frontend(adap, input->fe) < 0) | ||
854 | return -ENODEV; | ||
855 | } | ||
856 | break; | ||
857 | case DDB_TUNER_DVBS_ST_AA: | ||
858 | if (demod_attach_stv0900(input, 1) < 0) | ||
859 | return -ENODEV; | ||
860 | if (tuner_attach_stv6110(input, 1) < 0) | ||
861 | return -ENODEV; | ||
862 | if (input->fe) { | ||
863 | if (dvb_register_frontend(adap, input->fe) < 0) | ||
864 | return -ENODEV; | ||
865 | } | ||
866 | break; | ||
867 | case DDB_TUNER_DVBCT_TR: | ||
868 | if (demod_attach_drxk(input) < 0) | ||
869 | return -ENODEV; | ||
870 | if (tuner_attach_tda18271(input) < 0) | ||
871 | return -ENODEV; | ||
872 | if (input->fe) { | ||
873 | if (dvb_register_frontend(adap, input->fe) < 0) | ||
874 | return -ENODEV; | ||
875 | } | ||
876 | if (input->fe2) { | ||
877 | if (dvb_register_frontend(adap, input->fe2) < 0) | ||
878 | return -ENODEV; | ||
879 | input->fe2->tuner_priv=input->fe->tuner_priv; | ||
880 | memcpy(&input->fe2->ops.tuner_ops, | ||
881 | &input->fe->ops.tuner_ops, | ||
882 | sizeof(struct dvb_tuner_ops)); | ||
883 | } | ||
884 | break; | ||
885 | } | ||
886 | input->attached = 5; | ||
887 | return 0; | ||
888 | } | ||
889 | |||
890 | /****************************************************************************/ | ||
891 | /****************************************************************************/ | ||
892 | |||
893 | static ssize_t ts_write(struct file *file, const char *buf, | ||
894 | size_t count, loff_t *ppos) | ||
895 | { | ||
896 | struct dvb_device *dvbdev = file->private_data; | ||
897 | struct ddb_output *output = dvbdev->priv; | ||
898 | size_t left = count; | ||
899 | int stat; | ||
900 | |||
901 | while (left) { | ||
902 | if (ddb_output_free(output) < 188) { | ||
903 | if (file->f_flags & O_NONBLOCK) | ||
904 | break; | ||
905 | if (wait_event_interruptible( | ||
906 | output->wq, ddb_output_free(output) >= 188) < 0) | ||
907 | break; | ||
908 | } | ||
909 | stat = ddb_output_write(output, buf, left); | ||
910 | if (stat < 0) | ||
911 | break; | ||
912 | buf += stat; | ||
913 | left -= stat; | ||
914 | } | ||
915 | return (left == count) ? -EAGAIN : (count - left); | ||
916 | } | ||
917 | |||
918 | static ssize_t ts_read(struct file *file, char *buf, | ||
919 | size_t count, loff_t *ppos) | ||
920 | { | ||
921 | struct dvb_device *dvbdev = file->private_data; | ||
922 | struct ddb_output *output = dvbdev->priv; | ||
923 | struct ddb_input *input = output->port->input[0]; | ||
924 | int left, read; | ||
925 | |||
926 | count -= count % 188; | ||
927 | left = count; | ||
928 | while (left) { | ||
929 | if (ddb_input_avail(input) < 188) { | ||
930 | if (file->f_flags & O_NONBLOCK) | ||
931 | break; | ||
932 | if (wait_event_interruptible( | ||
933 | input->wq, ddb_input_avail(input) >= 188) < 0) | ||
934 | break; | ||
935 | } | ||
936 | read = ddb_input_read(input, buf, left); | ||
937 | left -= read; | ||
938 | buf += read; | ||
939 | } | ||
940 | return (left == count) ? -EAGAIN : (count - left); | ||
941 | } | ||
942 | |||
943 | static unsigned int ts_poll(struct file *file, poll_table *wait) | ||
944 | { | ||
945 | struct dvb_device *dvbdev = file->private_data; | ||
946 | struct ddb_output *output = dvbdev->priv; | ||
947 | struct ddb_input *input = output->port->input[0]; | ||
948 | unsigned int mask = 0; | ||
949 | |||
950 | #if 0 | ||
951 | if (data_avail_to_read) | ||
952 | mask |= POLLIN | POLLRDNORM; | ||
953 | if (data_avail_to_write) | ||
954 | mask |= POLLOUT | POLLWRNORM; | ||
955 | |||
956 | poll_wait(file, &read_queue, wait); | ||
957 | poll_wait(file, &write_queue, wait); | ||
958 | #endif | ||
959 | return mask; | ||
960 | } | ||
961 | |||
962 | static struct file_operations ci_fops = { | ||
963 | .owner = THIS_MODULE, | ||
964 | .read = ts_read, | ||
965 | .write = ts_write, | ||
966 | .open = dvb_generic_open, | ||
967 | .release = dvb_generic_release, | ||
968 | .poll = ts_poll, | ||
969 | .mmap = 0, | ||
970 | }; | ||
971 | |||
972 | static struct dvb_device dvbdev_ci = { | ||
973 | .priv = 0, | ||
974 | .readers = -1, | ||
975 | .writers = -1, | ||
976 | .users = -1, | ||
977 | .fops = &ci_fops, | ||
978 | }; | ||
979 | |||
980 | /****************************************************************************/ | ||
981 | /****************************************************************************/ | ||
982 | /****************************************************************************/ | ||
983 | |||
984 | static void input_tasklet(unsigned long data) | ||
985 | { | ||
986 | struct ddb_input *input = (struct ddb_input *) data; | ||
987 | struct ddb *dev = input->port->dev; | ||
988 | |||
989 | spin_lock(&input->lock); | ||
990 | if (!input->running) { | ||
991 | spin_unlock(&input->lock); | ||
992 | return; | ||
993 | } | ||
994 | input->stat = ddbreadl(DMA_BUFFER_CURRENT(input->nr)); | ||
995 | |||
996 | if (input->port->class == DDB_PORT_TUNER) { | ||
997 | if (4&ddbreadl(DMA_BUFFER_CONTROL(input->nr))) | ||
998 | printk("Overflow input %d\n", input->nr); | ||
999 | while (input->cbuf != ((input->stat >> 11) & 0x1f) | ||
1000 | || (4&ddbreadl(DMA_BUFFER_CONTROL(input->nr)))) { | ||
1001 | dvb_dmx_swfilter_packets(&input->demux, | ||
1002 | input->vbuf[input->cbuf], | ||
1003 | input->dma_buf_size / 188); | ||
1004 | |||
1005 | input->cbuf = (input->cbuf + 1) % input->dma_buf_num; | ||
1006 | ddbwritel((input->cbuf << 11), | ||
1007 | DMA_BUFFER_ACK(input->nr)); | ||
1008 | input->stat = ddbreadl(DMA_BUFFER_CURRENT(input->nr)); | ||
1009 | } | ||
1010 | } | ||
1011 | if (input->port->class == DDB_PORT_CI) | ||
1012 | wake_up(&input->wq); | ||
1013 | spin_unlock(&input->lock); | ||
1014 | } | ||
1015 | |||
1016 | static void output_tasklet(unsigned long data) | ||
1017 | { | ||
1018 | struct ddb_output *output = (struct ddb_output *) data; | ||
1019 | struct ddb *dev = output->port->dev; | ||
1020 | |||
1021 | spin_lock(&output->lock); | ||
1022 | if (!output->running) { | ||
1023 | spin_unlock(&output->lock); | ||
1024 | return; | ||
1025 | } | ||
1026 | output->stat = ddbreadl(DMA_BUFFER_CURRENT(output->nr + 8)); | ||
1027 | wake_up(&output->wq); | ||
1028 | spin_unlock(&output->lock); | ||
1029 | } | ||
1030 | |||
1031 | |||
1032 | struct cxd2099_cfg cxd_cfg = { | ||
1033 | .bitrate = 62000, | ||
1034 | .adr = 0x40, | ||
1035 | .polarity = 1, | ||
1036 | .clock_mode = 1, | ||
1037 | }; | ||
1038 | |||
1039 | static int ddb_ci_attach(struct ddb_port *port) | ||
1040 | { | ||
1041 | int ret; | ||
1042 | |||
1043 | ret = dvb_register_adapter(&port->output->adap, | ||
1044 | "DDBridge", | ||
1045 | THIS_MODULE, | ||
1046 | &port->dev->pdev->dev, | ||
1047 | adapter_nr); | ||
1048 | if (ret < 0) | ||
1049 | return ret; | ||
1050 | port->en = cxd2099_attach(&cxd_cfg, port, &port->i2c->adap); | ||
1051 | if (!port->en) { | ||
1052 | dvb_unregister_adapter(&port->output->adap); | ||
1053 | return -ENODEV; | ||
1054 | } | ||
1055 | ddb_input_start(port->input[0]); | ||
1056 | ddb_output_start(port->output); | ||
1057 | dvb_ca_en50221_init(&port->output->adap, | ||
1058 | port->en, 0, 1); | ||
1059 | ret=dvb_register_device(&port->output->adap, &port->output->dev, | ||
1060 | &dvbdev_ci, (void *) port->output, | ||
1061 | DVB_DEVICE_SEC); | ||
1062 | return ret; | ||
1063 | } | ||
1064 | |||
1065 | static int ddb_port_attach(struct ddb_port *port) | ||
1066 | { | ||
1067 | int ret = 0; | ||
1068 | |||
1069 | switch (port->class) { | ||
1070 | case DDB_PORT_TUNER: | ||
1071 | ret = dvb_input_attach(port->input[0]); | ||
1072 | if (ret<0) | ||
1073 | break; | ||
1074 | ret = dvb_input_attach(port->input[1]); | ||
1075 | break; | ||
1076 | case DDB_PORT_CI: | ||
1077 | ret = ddb_ci_attach(port); | ||
1078 | break; | ||
1079 | default: | ||
1080 | break; | ||
1081 | } | ||
1082 | if (ret < 0) | ||
1083 | printk("port_attach on port %d failed\n", port->nr); | ||
1084 | return ret; | ||
1085 | } | ||
1086 | |||
1087 | static int ddb_ports_attach(struct ddb *dev) | ||
1088 | { | ||
1089 | int i, ret = 0; | ||
1090 | struct ddb_port *port; | ||
1091 | |||
1092 | for (i = 0; i < dev->info->port_num; i++) { | ||
1093 | port = &dev->port[i]; | ||
1094 | ret = ddb_port_attach(port); | ||
1095 | if (ret < 0) | ||
1096 | break; | ||
1097 | } | ||
1098 | return ret; | ||
1099 | } | ||
1100 | |||
1101 | static void ddb_ports_detach(struct ddb *dev) | ||
1102 | { | ||
1103 | int i; | ||
1104 | struct ddb_port *port; | ||
1105 | |||
1106 | for (i = 0; i < dev->info->port_num; i++) { | ||
1107 | port = &dev->port[i]; | ||
1108 | switch (port->class) { | ||
1109 | case DDB_PORT_TUNER: | ||
1110 | dvb_input_detach(port->input[0]); | ||
1111 | dvb_input_detach(port->input[1]); | ||
1112 | break; | ||
1113 | case DDB_PORT_CI: | ||
1114 | if (port->output->dev) | ||
1115 | dvb_unregister_device(port->output->dev); | ||
1116 | if (port->en) { | ||
1117 | ddb_input_stop(port->input[0]); | ||
1118 | ddb_output_stop(port->output); | ||
1119 | dvb_ca_en50221_release(port->en); | ||
1120 | kfree(port->en); | ||
1121 | port->en = 0; | ||
1122 | dvb_unregister_adapter(&port->output->adap); | ||
1123 | } | ||
1124 | break; | ||
1125 | } | ||
1126 | } | ||
1127 | } | ||
1128 | |||
1129 | /****************************************************************************/ | ||
1130 | /****************************************************************************/ | ||
1131 | |||
1132 | static int port_has_ci(struct ddb_port *port) | ||
1133 | { | ||
1134 | u8 val; | ||
1135 | return (i2c_read_reg(&port->i2c->adap, 0x40, 0, &val) ? 0 : 1); | ||
1136 | } | ||
1137 | |||
1138 | static int port_has_stv0900(struct ddb_port *port) | ||
1139 | { | ||
1140 | u8 val; | ||
1141 | if (i2c_read_reg16(&port->i2c->adap, 0x69, 0xf100, &val) < 0) | ||
1142 | return 0; | ||
1143 | return 1; | ||
1144 | } | ||
1145 | |||
1146 | static int port_has_stv0900_aa(struct ddb_port *port) | ||
1147 | { | ||
1148 | u8 val; | ||
1149 | if (i2c_read_reg16(&port->i2c->adap, 0x68, 0xf100, &val) < 0) | ||
1150 | return 0; | ||
1151 | return 1; | ||
1152 | } | ||
1153 | |||
1154 | static int port_has_drxks(struct ddb_port *port) | ||
1155 | { | ||
1156 | u8 val; | ||
1157 | if (i2c_read(&port->i2c->adap, 0x29, &val) < 0) | ||
1158 | return 0; | ||
1159 | if (i2c_read(&port->i2c->adap, 0x2a, &val) < 0) | ||
1160 | return 0; | ||
1161 | return 1; | ||
1162 | } | ||
1163 | |||
1164 | static void ddb_port_probe(struct ddb_port *port) | ||
1165 | { | ||
1166 | struct ddb *dev = port->dev; | ||
1167 | char *modname = "NO MODULE"; | ||
1168 | |||
1169 | port->class = DDB_PORT_NONE; | ||
1170 | |||
1171 | if (port_has_ci(port)) { | ||
1172 | modname = "CI"; | ||
1173 | port->class = DDB_PORT_CI; | ||
1174 | ddbwritel(I2C_SPEED_400, port->i2c->regs + I2C_TIMING); | ||
1175 | } else if (port_has_stv0900(port)) { | ||
1176 | modname = "DUAL DVB-S2"; | ||
1177 | port->class = DDB_PORT_TUNER; | ||
1178 | port->type = DDB_TUNER_DVBS_ST; | ||
1179 | ddbwritel(I2C_SPEED_100, port->i2c->regs + I2C_TIMING); | ||
1180 | } else if (port_has_stv0900_aa(port)) { | ||
1181 | modname = "DUAL DVB-S2"; | ||
1182 | port->class = DDB_PORT_TUNER; | ||
1183 | port->type = DDB_TUNER_DVBS_ST_AA; | ||
1184 | ddbwritel(I2C_SPEED_100, port->i2c->regs + I2C_TIMING); | ||
1185 | } else if (port_has_drxks(port)) { | ||
1186 | modname = "DUAL DVB-C/T"; | ||
1187 | port->class = DDB_PORT_TUNER; | ||
1188 | port->type = DDB_TUNER_DVBCT_TR; | ||
1189 | ddbwritel(I2C_SPEED_400, port->i2c->regs + I2C_TIMING); | ||
1190 | } | ||
1191 | printk("Port %d (TAB %d): %s\n", port->nr, port->nr+1, modname); | ||
1192 | } | ||
1193 | |||
1194 | static void ddb_input_init(struct ddb_port *port, int nr) | ||
1195 | { | ||
1196 | struct ddb *dev = port->dev; | ||
1197 | struct ddb_input *input = &dev->input[nr]; | ||
1198 | |||
1199 | input->nr = nr; | ||
1200 | input->port = port; | ||
1201 | input->dma_buf_num = INPUT_DMA_BUFS; | ||
1202 | input->dma_buf_size = INPUT_DMA_SIZE; | ||
1203 | ddbwritel(0, TS_INPUT_CONTROL(nr)); | ||
1204 | ddbwritel(2, TS_INPUT_CONTROL(nr)); | ||
1205 | ddbwritel(0, TS_INPUT_CONTROL(nr)); | ||
1206 | ddbwritel(0, DMA_BUFFER_ACK(nr)); | ||
1207 | tasklet_init(&input->tasklet, input_tasklet, (unsigned long) input); | ||
1208 | spin_lock_init(&input->lock); | ||
1209 | init_waitqueue_head(&input->wq); | ||
1210 | } | ||
1211 | |||
1212 | static void ddb_output_init(struct ddb_port *port, int nr) | ||
1213 | { | ||
1214 | struct ddb *dev = port->dev; | ||
1215 | struct ddb_output *output = &dev->output[nr]; | ||
1216 | output->nr = nr; | ||
1217 | output->port = port; | ||
1218 | output->dma_buf_num = OUTPUT_DMA_BUFS; | ||
1219 | output->dma_buf_size = OUTPUT_DMA_SIZE; | ||
1220 | |||
1221 | ddbwritel(0, TS_OUTPUT_CONTROL(nr)); | ||
1222 | ddbwritel(2, TS_OUTPUT_CONTROL(nr)); | ||
1223 | ddbwritel(0, TS_OUTPUT_CONTROL(nr)); | ||
1224 | tasklet_init(&output->tasklet, output_tasklet, (unsigned long) output); | ||
1225 | init_waitqueue_head(&output->wq); | ||
1226 | } | ||
1227 | |||
1228 | static void ddb_ports_init(struct ddb *dev) | ||
1229 | { | ||
1230 | int i; | ||
1231 | struct ddb_port *port; | ||
1232 | |||
1233 | for (i = 0; i < dev->info->port_num; i++) { | ||
1234 | port = &dev->port[i]; | ||
1235 | port->dev = dev; | ||
1236 | port->nr = i; | ||
1237 | port->i2c = &dev->i2c[i]; | ||
1238 | port->input[0] = &dev->input[2 * i]; | ||
1239 | port->input[1] = &dev->input[2 * i + 1]; | ||
1240 | port->output = &dev->output[i]; | ||
1241 | |||
1242 | mutex_init(&port->i2c_gate_lock); | ||
1243 | ddb_port_probe(port); | ||
1244 | ddb_input_init(port, 2 * i); | ||
1245 | ddb_input_init(port, 2 * i + 1); | ||
1246 | ddb_output_init(port, i); | ||
1247 | } | ||
1248 | } | ||
1249 | |||
1250 | static void ddb_ports_release(struct ddb *dev) | ||
1251 | { | ||
1252 | int i; | ||
1253 | struct ddb_port *port; | ||
1254 | |||
1255 | for (i = 0; i < dev->info->port_num; i++) { | ||
1256 | port = &dev->port[i]; | ||
1257 | port->dev = dev; | ||
1258 | tasklet_kill(&port->input[0]->tasklet); | ||
1259 | tasklet_kill(&port->input[1]->tasklet); | ||
1260 | tasklet_kill(&port->output->tasklet); | ||
1261 | } | ||
1262 | } | ||
1263 | |||
1264 | /****************************************************************************/ | ||
1265 | /****************************************************************************/ | ||
1266 | /****************************************************************************/ | ||
1267 | |||
1268 | static void irq_handle_i2c(struct ddb *dev, int n) | ||
1269 | { | ||
1270 | struct ddb_i2c *i2c = &dev->i2c[n]; | ||
1271 | |||
1272 | i2c->done = 1; | ||
1273 | wake_up(&i2c->wq); | ||
1274 | } | ||
1275 | |||
1276 | static irqreturn_t irq_handler(int irq, void *dev_id) | ||
1277 | { | ||
1278 | struct ddb *dev = (struct ddb *) dev_id; | ||
1279 | u32 s = ddbreadl(INTERRUPT_STATUS); | ||
1280 | |||
1281 | if (!s) | ||
1282 | return IRQ_NONE; | ||
1283 | |||
1284 | do { | ||
1285 | ddbwritel(s, INTERRUPT_ACK); | ||
1286 | |||
1287 | if (s & 0x00000001) irq_handle_i2c(dev, 0); | ||
1288 | if (s & 0x00000002) irq_handle_i2c(dev, 1); | ||
1289 | if (s & 0x00000004) irq_handle_i2c(dev, 2); | ||
1290 | if (s & 0x00000008) irq_handle_i2c(dev, 3); | ||
1291 | |||
1292 | if (s & 0x00000100) tasklet_schedule(&dev->input[0].tasklet); | ||
1293 | if (s & 0x00000200) tasklet_schedule(&dev->input[1].tasklet); | ||
1294 | if (s & 0x00000400) tasklet_schedule(&dev->input[2].tasklet); | ||
1295 | if (s & 0x00000800) tasklet_schedule(&dev->input[3].tasklet); | ||
1296 | if (s & 0x00001000) tasklet_schedule(&dev->input[4].tasklet); | ||
1297 | if (s & 0x00002000) tasklet_schedule(&dev->input[5].tasklet); | ||
1298 | if (s & 0x00004000) tasklet_schedule(&dev->input[6].tasklet); | ||
1299 | if (s & 0x00008000) tasklet_schedule(&dev->input[7].tasklet); | ||
1300 | |||
1301 | if (s & 0x00010000) tasklet_schedule(&dev->output[0].tasklet); | ||
1302 | if (s & 0x00020000) tasklet_schedule(&dev->output[1].tasklet); | ||
1303 | if (s & 0x00040000) tasklet_schedule(&dev->output[2].tasklet); | ||
1304 | if (s & 0x00080000) tasklet_schedule(&dev->output[3].tasklet); | ||
1305 | |||
1306 | /* if (s & 0x000f0000) printk("%08x\n", istat); */ | ||
1307 | } while ((s = ddbreadl(INTERRUPT_STATUS))); | ||
1308 | |||
1309 | return IRQ_HANDLED; | ||
1310 | } | ||
1311 | |||
1312 | /******************************************************************************/ | ||
1313 | /******************************************************************************/ | ||
1314 | /******************************************************************************/ | ||
1315 | |||
1316 | static int flashio(struct ddb *dev, u8 *wbuf, u32 wlen, u8 *rbuf, u32 rlen) | ||
1317 | { | ||
1318 | u32 data, shift; | ||
1319 | |||
1320 | if (wlen > 4) | ||
1321 | ddbwritel(1, SPI_CONTROL); | ||
1322 | while (wlen > 4) { | ||
1323 | /* FIXME: check for big-endian */ | ||
1324 | data = swab32(*(u32 *)wbuf); | ||
1325 | wbuf += 4; | ||
1326 | wlen -= 4; | ||
1327 | ddbwritel(data, SPI_DATA); | ||
1328 | while (ddbreadl(SPI_CONTROL) & 0x0004); | ||
1329 | } | ||
1330 | |||
1331 | if (rlen) | ||
1332 | ddbwritel(0x0001 | ((wlen << (8 + 3)) & 0x1f00), SPI_CONTROL); | ||
1333 | else | ||
1334 | ddbwritel(0x0003 | ((wlen << (8 + 3)) & 0x1f00), SPI_CONTROL); | ||
1335 | |||
1336 | data=0; | ||
1337 | shift = ((4 - wlen) * 8); | ||
1338 | while (wlen) { | ||
1339 | data <<= 8; | ||
1340 | data |= *wbuf; | ||
1341 | wlen--; | ||
1342 | wbuf++; | ||
1343 | } | ||
1344 | if (shift) | ||
1345 | data <<= shift; | ||
1346 | ddbwritel(data, SPI_DATA); | ||
1347 | while (ddbreadl(SPI_CONTROL) & 0x0004); | ||
1348 | |||
1349 | if (!rlen) { | ||
1350 | ddbwritel(0, SPI_CONTROL); | ||
1351 | return 0; | ||
1352 | } | ||
1353 | if (rlen > 4) | ||
1354 | ddbwritel(1, SPI_CONTROL); | ||
1355 | |||
1356 | while (rlen > 4) { | ||
1357 | ddbwritel(0xffffffff, SPI_DATA); | ||
1358 | while (ddbreadl(SPI_CONTROL) & 0x0004); | ||
1359 | data = ddbreadl(SPI_DATA); | ||
1360 | *(u32 *) rbuf = swab32(data); | ||
1361 | rbuf += 4; | ||
1362 | rlen -= 4; | ||
1363 | } | ||
1364 | ddbwritel(0x0003 | ((rlen << (8 + 3)) & 0x1F00), SPI_CONTROL); | ||
1365 | ddbwritel(0xffffffff, SPI_DATA); | ||
1366 | while (ddbreadl(SPI_CONTROL) & 0x0004); | ||
1367 | |||
1368 | data = ddbreadl(SPI_DATA); | ||
1369 | ddbwritel(0, SPI_CONTROL); | ||
1370 | |||
1371 | if (rlen < 4) | ||
1372 | data <<= ((4 - rlen) * 8); | ||
1373 | |||
1374 | while (rlen > 0) { | ||
1375 | *rbuf = ((data >> 24) & 0xff); | ||
1376 | data <<= 8; | ||
1377 | rbuf++; | ||
1378 | rlen--; | ||
1379 | } | ||
1380 | return 0; | ||
1381 | } | ||
1382 | |||
1383 | #define DDB_MAGIC 'd' | ||
1384 | |||
1385 | struct ddb_flashio { | ||
1386 | __u8 *write_buf; | ||
1387 | __u32 write_len; | ||
1388 | __u8 *read_buf; | ||
1389 | __u32 read_len; | ||
1390 | }; | ||
1391 | |||
1392 | #define IOCTL_DDB_FLASHIO _IOWR(DDB_MAGIC, 0x00, struct ddb_flashio) | ||
1393 | |||
1394 | #define DDB_NAME "ddbridge" | ||
1395 | |||
1396 | static u32 ddb_num; | ||
1397 | static struct ddb *ddbs[32]; | ||
1398 | static struct class *ddb_class; | ||
1399 | static int ddb_major; | ||
1400 | |||
1401 | static int ddb_open(struct inode *inode, struct file *file) | ||
1402 | { | ||
1403 | struct ddb *dev = ddbs[iminor(inode)]; | ||
1404 | |||
1405 | file->private_data = dev; | ||
1406 | return 0; | ||
1407 | } | ||
1408 | |||
1409 | static long ddb_ioctl(struct file *file, unsigned int cmd, unsigned long arg) | ||
1410 | { | ||
1411 | struct ddb *dev = file->private_data; | ||
1412 | void *parg = (void *)arg; | ||
1413 | int res = -EFAULT; | ||
1414 | |||
1415 | switch (cmd) { | ||
1416 | case IOCTL_DDB_FLASHIO: | ||
1417 | { | ||
1418 | struct ddb_flashio fio; | ||
1419 | u8 *rbuf, *wbuf; | ||
1420 | |||
1421 | if (copy_from_user(&fio, parg, sizeof(fio))) | ||
1422 | break; | ||
1423 | if (fio.write_len + fio.read_len > 1028) { | ||
1424 | printk("IOBUF too small\n"); | ||
1425 | return -ENOMEM; | ||
1426 | } | ||
1427 | wbuf = &dev->iobuf[0]; | ||
1428 | if (!wbuf) | ||
1429 | return -ENOMEM; | ||
1430 | rbuf = wbuf + fio.write_len; | ||
1431 | if (copy_from_user(wbuf, fio.write_buf, fio.write_len)) { | ||
1432 | vfree(wbuf); | ||
1433 | break; | ||
1434 | } | ||
1435 | res = flashio(dev, wbuf, fio.write_len, | ||
1436 | rbuf, fio.read_len); | ||
1437 | if (copy_to_user(fio.read_buf, rbuf, fio.read_len)) | ||
1438 | res = -EFAULT; | ||
1439 | break; | ||
1440 | } | ||
1441 | default: | ||
1442 | break; | ||
1443 | } | ||
1444 | return res; | ||
1445 | } | ||
1446 | |||
1447 | static struct file_operations ddb_fops={ | ||
1448 | .unlocked_ioctl = ddb_ioctl, | ||
1449 | .open = ddb_open, | ||
1450 | }; | ||
1451 | |||
1452 | static char *ddb_devnode(struct device *device, mode_t *mode) | ||
1453 | { | ||
1454 | struct ddb *dev = dev_get_drvdata(device); | ||
1455 | |||
1456 | return kasprintf(GFP_KERNEL, "ddbridge/card%d", dev->nr); | ||
1457 | } | ||
1458 | |||
1459 | static int ddb_class_create(void) | ||
1460 | { | ||
1461 | if ((ddb_major = register_chrdev(0, DDB_NAME, &ddb_fops))<0) | ||
1462 | return ddb_major; | ||
1463 | |||
1464 | ddb_class = class_create(THIS_MODULE, DDB_NAME); | ||
1465 | if (IS_ERR(ddb_class)) { | ||
1466 | unregister_chrdev(ddb_major, DDB_NAME); | ||
1467 | return -1; | ||
1468 | } | ||
1469 | ddb_class->devnode = ddb_devnode; | ||
1470 | return 0; | ||
1471 | } | ||
1472 | |||
1473 | static void ddb_class_destroy(void) | ||
1474 | { | ||
1475 | class_destroy(ddb_class); | ||
1476 | unregister_chrdev(ddb_major, DDB_NAME); | ||
1477 | } | ||
1478 | |||
1479 | static int ddb_device_create(struct ddb *dev) | ||
1480 | { | ||
1481 | dev->nr = ddb_num++; | ||
1482 | dev->ddb_dev = device_create(ddb_class, NULL, | ||
1483 | MKDEV(ddb_major, dev->nr), | ||
1484 | dev, "ddbridge%d", dev->nr); | ||
1485 | ddbs[dev->nr] = dev; | ||
1486 | if (IS_ERR(dev->ddb_dev)) | ||
1487 | return -1; | ||
1488 | return 0; | ||
1489 | } | ||
1490 | |||
1491 | static void ddb_device_destroy(struct ddb *dev) | ||
1492 | { | ||
1493 | ddb_num--; | ||
1494 | if (IS_ERR(dev->ddb_dev)) | ||
1495 | return; | ||
1496 | device_destroy(ddb_class, MKDEV(ddb_major, 0)); | ||
1497 | } | ||
1498 | |||
1499 | |||
1500 | /****************************************************************************/ | ||
1501 | /****************************************************************************/ | ||
1502 | /****************************************************************************/ | ||
1503 | |||
1504 | static void ddb_unmap(struct ddb *dev) | ||
1505 | { | ||
1506 | if (dev->regs) | ||
1507 | iounmap(dev->regs); | ||
1508 | vfree(dev); | ||
1509 | } | ||
1510 | |||
1511 | |||
1512 | static void __devexit ddb_remove(struct pci_dev *pdev) | ||
1513 | { | ||
1514 | struct ddb *dev = (struct ddb *) pci_get_drvdata(pdev); | ||
1515 | |||
1516 | ddb_ports_detach(dev); | ||
1517 | ddb_i2c_release(dev); | ||
1518 | |||
1519 | ddbwritel(0, INTERRUPT_ENABLE); | ||
1520 | free_irq(dev->pdev->irq, dev); | ||
1521 | #ifdef CONFIG_PCI_MSI | ||
1522 | if (dev->msi) | ||
1523 | pci_disable_msi(dev->pdev); | ||
1524 | #endif | ||
1525 | ddb_ports_release(dev); | ||
1526 | ddb_buffers_free(dev); | ||
1527 | ddb_device_destroy(dev); | ||
1528 | |||
1529 | ddb_unmap(dev); | ||
1530 | pci_set_drvdata(pdev, 0); | ||
1531 | pci_disable_device(pdev); | ||
1532 | } | ||
1533 | |||
1534 | |||
1535 | static int __devinit ddb_probe(struct pci_dev *pdev, | ||
1536 | const struct pci_device_id *id) | ||
1537 | { | ||
1538 | struct ddb *dev; | ||
1539 | int stat=0; | ||
1540 | int irq_flag = IRQF_SHARED; | ||
1541 | |||
1542 | if (pci_enable_device(pdev)<0) | ||
1543 | return -ENODEV; | ||
1544 | |||
1545 | dev = vmalloc(sizeof(struct ddb)); | ||
1546 | if (dev == NULL) | ||
1547 | return -ENOMEM; | ||
1548 | memset(dev, 0, sizeof(struct ddb)); | ||
1549 | |||
1550 | dev->pdev = pdev; | ||
1551 | pci_set_drvdata(pdev, dev); | ||
1552 | dev->info = (struct ddb_info *) id->driver_data; | ||
1553 | printk("DDBridge driver detected: %s\n", dev->info->name); | ||
1554 | |||
1555 | dev->regs = ioremap(pci_resource_start(dev->pdev,0), | ||
1556 | pci_resource_len(dev->pdev,0)); | ||
1557 | if (!dev->regs) { | ||
1558 | stat = -ENOMEM; | ||
1559 | goto fail; | ||
1560 | } | ||
1561 | printk("HW %08x FW %08x\n", ddbreadl(0), ddbreadl(4)); | ||
1562 | |||
1563 | #ifdef CONFIG_PCI_MSI | ||
1564 | if (pci_msi_enabled()) | ||
1565 | stat = pci_enable_msi(dev->pdev); | ||
1566 | if (stat) { | ||
1567 | printk(KERN_INFO ": MSI not available.\n"); | ||
1568 | } else { | ||
1569 | irq_flag = 0; | ||
1570 | dev->msi = 1; | ||
1571 | } | ||
1572 | #endif | ||
1573 | if ((stat = request_irq(dev->pdev->irq, irq_handler, | ||
1574 | irq_flag, "DDBridge", | ||
1575 | (void *) dev))<0) | ||
1576 | goto fail1; | ||
1577 | ddbwritel(0, DMA_BASE_WRITE); | ||
1578 | ddbwritel(0, DMA_BASE_READ); | ||
1579 | ddbwritel(0xffffffff, INTERRUPT_ACK); | ||
1580 | ddbwritel(0xfff0f, INTERRUPT_ENABLE); | ||
1581 | ddbwritel(0, MSI1_ENABLE); | ||
1582 | |||
1583 | if (ddb_i2c_init(dev) < 0) | ||
1584 | goto fail1; | ||
1585 | ddb_ports_init(dev); | ||
1586 | if (ddb_buffers_alloc(dev) < 0) { | ||
1587 | printk(KERN_INFO ": Could not allocate buffer memory\n"); | ||
1588 | goto fail2; | ||
1589 | } | ||
1590 | if (ddb_ports_attach(dev) < 0) | ||
1591 | goto fail3; | ||
1592 | ddb_device_create(dev); | ||
1593 | return 0; | ||
1594 | |||
1595 | fail3: | ||
1596 | ddb_ports_detach(dev); | ||
1597 | printk("fail3\n"); | ||
1598 | ddb_ports_release(dev); | ||
1599 | fail2: | ||
1600 | printk("fail2\n"); | ||
1601 | ddb_buffers_free(dev); | ||
1602 | fail1: | ||
1603 | printk("fail1\n"); | ||
1604 | if (dev->msi) | ||
1605 | pci_disable_msi(dev->pdev); | ||
1606 | free_irq(dev->pdev->irq, dev); | ||
1607 | fail: | ||
1608 | printk("fail\n"); | ||
1609 | ddb_unmap(dev); | ||
1610 | pci_set_drvdata(pdev, 0); | ||
1611 | pci_disable_device(pdev); | ||
1612 | return -1; | ||
1613 | } | ||
1614 | |||
1615 | /******************************************************************************/ | ||
1616 | /******************************************************************************/ | ||
1617 | /******************************************************************************/ | ||
1618 | |||
1619 | static struct ddb_info ddb_none = { | ||
1620 | .type = DDB_NONE, | ||
1621 | .name = "Digital Devices PCIe bridge", | ||
1622 | }; | ||
1623 | |||
1624 | static struct ddb_info ddb_octopus = { | ||
1625 | .type = DDB_OCTOPUS, | ||
1626 | .name = "Digital Devices Octopus DVB adapter", | ||
1627 | .port_num = 4, | ||
1628 | }; | ||
1629 | |||
1630 | static struct ddb_info ddb_octopus_le = { | ||
1631 | .type = DDB_OCTOPUS, | ||
1632 | .name = "Digital Devices Octopus LE DVB adapter", | ||
1633 | .port_num = 2, | ||
1634 | }; | ||
1635 | |||
1636 | static struct ddb_info ddb_v6 = { | ||
1637 | .type = DDB_OCTOPUS, | ||
1638 | .name = "Digital Devices Cine S2 V6 DVB adapter", | ||
1639 | .port_num = 3, | ||
1640 | }; | ||
1641 | |||
1642 | #define DDVID 0xdd01 /* Digital Devices Vendor ID */ | ||
1643 | |||
1644 | #define DDB_ID(_vend, _dev, _subvend,_subdev,_driverdata) { \ | ||
1645 | .vendor = _vend, .device = _dev, \ | ||
1646 | .subvendor = _subvend, .subdevice = _subdev, \ | ||
1647 | .driver_data = (unsigned long)&_driverdata } | ||
1648 | |||
1649 | static const struct pci_device_id ddb_id_tbl[] __devinitdata = { | ||
1650 | DDB_ID(DDVID, 0x0002, DDVID, 0x0001, ddb_octopus), | ||
1651 | DDB_ID(DDVID, 0x0003, DDVID, 0x0001, ddb_octopus), | ||
1652 | DDB_ID(DDVID, 0x0003, DDVID, 0x0002, ddb_octopus_le), | ||
1653 | DDB_ID(DDVID, 0x0003, DDVID, 0x0010, ddb_octopus), | ||
1654 | DDB_ID(DDVID, 0x0003, DDVID, 0x0020, ddb_v6), | ||
1655 | /* in case sub-ids got deleted in flash */ | ||
1656 | DDB_ID(DDVID, 0x0003, PCI_ANY_ID, PCI_ANY_ID, ddb_none), | ||
1657 | {0} | ||
1658 | }; | ||
1659 | MODULE_DEVICE_TABLE(pci, ddb_id_tbl); | ||
1660 | |||
1661 | |||
1662 | static struct pci_driver ddb_pci_driver = { | ||
1663 | .name = "DDBridge", | ||
1664 | .id_table = ddb_id_tbl, | ||
1665 | .probe = ddb_probe, | ||
1666 | .remove = ddb_remove, | ||
1667 | }; | ||
1668 | |||
1669 | static __init int module_init_ddbridge(void) | ||
1670 | { | ||
1671 | printk("Digital Devices PCIE bridge driver, " | ||
1672 | "Copyright (C) 2010-11 Digital Devices GmbH\n"); | ||
1673 | if (ddb_class_create()) | ||
1674 | return -1; | ||
1675 | return pci_register_driver(&ddb_pci_driver); | ||
1676 | } | ||
1677 | |||
1678 | static __exit void module_exit_ddbridge(void) | ||
1679 | { | ||
1680 | pci_unregister_driver(&ddb_pci_driver); | ||
1681 | ddb_class_destroy(); | ||
1682 | } | ||
1683 | |||
1684 | module_init(module_init_ddbridge); | ||
1685 | module_exit(module_exit_ddbridge); | ||
1686 | |||
1687 | MODULE_DESCRIPTION("Digital Devices PCIe Bridge"); | ||
1688 | MODULE_AUTHOR("Ralph Metzler"); | ||
1689 | MODULE_LICENSE("GPL"); | ||
1690 | MODULE_VERSION("0.5"); | ||
diff --git a/drivers/media/dvb/ddbridge/ddbridge-regs.h b/drivers/media/dvb/ddbridge/ddbridge-regs.h new file mode 100644 index 00000000000..0130073af62 --- /dev/null +++ b/drivers/media/dvb/ddbridge/ddbridge-regs.h | |||
@@ -0,0 +1,151 @@ | |||
1 | /* | ||
2 | * ddbridge-regs.h: Digital Devices PCIe bridge driver | ||
3 | * | ||
4 | * Copyright (C) 2010-2011 Digital Devices GmbH | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or | ||
7 | * modify it under the terms of the GNU General Public License | ||
8 | * version 2 only, as published by the Free Software Foundation. | ||
9 | * | ||
10 | * | ||
11 | * This program is distributed in the hope that it will be useful, | ||
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
14 | * GNU General Public License for more details. | ||
15 | * | ||
16 | * | ||
17 | * You should have received a copy of the GNU General Public License | ||
18 | * along with this program; if not, write to the Free Software | ||
19 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA | ||
20 | * 02110-1301, USA | ||
21 | * Or, point your browser to http://www.gnu.org/copyleft/gpl.html | ||
22 | */ | ||
23 | |||
24 | // $Id: DD-DVBBridgeV1.h 273 2010-09-17 05:03:16Z manfred $ | ||
25 | |||
26 | // Register Definitions | ||
27 | |||
28 | #define CUR_REGISTERMAP_VERSION 0x10000 | ||
29 | |||
30 | #define HARDWARE_VERSION 0x00 | ||
31 | #define REGISTERMAP_VERSION 0x04 | ||
32 | |||
33 | // -------------------------------------------------------------------------- | ||
34 | // SPI Controller | ||
35 | |||
36 | #define SPI_CONTROL 0x10 | ||
37 | #define SPI_DATA 0x14 | ||
38 | |||
39 | // -------------------------------------------------------------------------- | ||
40 | |||
41 | // Interrupt controller | ||
42 | // How many MSI's are available depends on HW (Min 2 max 8) | ||
43 | // How many are usable also depends on Host platform | ||
44 | |||
45 | #define INTERRUPT_BASE (0x40) | ||
46 | |||
47 | #define INTERRUPT_ENABLE (INTERRUPT_BASE + 0x00) | ||
48 | #define MSI0_ENABLE (INTERRUPT_BASE + 0x00) | ||
49 | #define MSI1_ENABLE (INTERRUPT_BASE + 0x04) | ||
50 | #define MSI2_ENABLE (INTERRUPT_BASE + 0x08) | ||
51 | #define MSI3_ENABLE (INTERRUPT_BASE + 0x0C) | ||
52 | #define MSI4_ENABLE (INTERRUPT_BASE + 0x10) | ||
53 | #define MSI5_ENABLE (INTERRUPT_BASE + 0x14) | ||
54 | #define MSI6_ENABLE (INTERRUPT_BASE + 0x18) | ||
55 | #define MSI7_ENABLE (INTERRUPT_BASE + 0x1C) | ||
56 | |||
57 | #define INTERRUPT_STATUS (INTERRUPT_BASE + 0x20) | ||
58 | #define INTERRUPT_ACK (INTERRUPT_BASE + 0x20) | ||
59 | |||
60 | #define INTMASK_I2C1 (0x00000001) | ||
61 | #define INTMASK_I2C2 (0x00000002) | ||
62 | #define INTMASK_I2C3 (0x00000004) | ||
63 | #define INTMASK_I2C4 (0x00000008) | ||
64 | |||
65 | #define INTMASK_CIRQ1 (0x00000010) | ||
66 | #define INTMASK_CIRQ2 (0x00000020) | ||
67 | #define INTMASK_CIRQ3 (0x00000040) | ||
68 | #define INTMASK_CIRQ4 (0x00000080) | ||
69 | |||
70 | #define INTMASK_TSINPUT1 (0x00000100) | ||
71 | #define INTMASK_TSINPUT2 (0x00000200) | ||
72 | #define INTMASK_TSINPUT3 (0x00000400) | ||
73 | #define INTMASK_TSINPUT4 (0x00000800) | ||
74 | #define INTMASK_TSINPUT5 (0x00001000) | ||
75 | #define INTMASK_TSINPUT6 (0x00002000) | ||
76 | #define INTMASK_TSINPUT7 (0x00004000) | ||
77 | #define INTMASK_TSINPUT8 (0x00008000) | ||
78 | |||
79 | #define INTMASK_TSOUTPUT1 (0x00010000) | ||
80 | #define INTMASK_TSOUTPUT2 (0x00020000) | ||
81 | #define INTMASK_TSOUTPUT3 (0x00040000) | ||
82 | #define INTMASK_TSOUTPUT4 (0x00080000) | ||
83 | |||
84 | // -------------------------------------------------------------------------- | ||
85 | // I2C Master Controller | ||
86 | |||
87 | #define I2C_BASE (0x80) // Byte offset | ||
88 | |||
89 | #define I2C_COMMAND (0x00) | ||
90 | #define I2C_TIMING (0x04) | ||
91 | #define I2C_TASKLENGTH (0x08) // High read, low write | ||
92 | #define I2C_TASKADDRESS (0x0C) // High read, low write | ||
93 | |||
94 | #define I2C_MONITOR (0x1C) | ||
95 | |||
96 | #define I2C_BASE_1 (I2C_BASE + 0x00) | ||
97 | #define I2C_BASE_2 (I2C_BASE + 0x20) | ||
98 | #define I2C_BASE_3 (I2C_BASE + 0x40) | ||
99 | #define I2C_BASE_4 (I2C_BASE + 0x60) | ||
100 | |||
101 | #define I2C_BASE_N(i) (I2C_BASE + (i) * 0x20) | ||
102 | |||
103 | #define I2C_TASKMEM_BASE (0x1000) // Byte offset | ||
104 | #define I2C_TASKMEM_SIZE (0x1000) | ||
105 | |||
106 | #define I2C_SPEED_400 (0x04030404) | ||
107 | #define I2C_SPEED_200 (0x09080909) | ||
108 | #define I2C_SPEED_154 (0x0C0B0C0C) | ||
109 | #define I2C_SPEED_100 (0x13121313) | ||
110 | #define I2C_SPEED_77 (0x19181919) | ||
111 | #define I2C_SPEED_50 (0x27262727) | ||
112 | |||
113 | |||
114 | // -------------------------------------------------------------------------- | ||
115 | // DMA Controller | ||
116 | |||
117 | #define DMA_BASE_WRITE (0x100) | ||
118 | #define DMA_BASE_READ (0x140) | ||
119 | |||
120 | #define DMA_CONTROL (0x00) // 64 | ||
121 | #define DMA_ERROR (0x04) // 65 ( only read instance ) | ||
122 | |||
123 | #define DMA_DIAG_CONTROL (0x1C) // 71 | ||
124 | #define DMA_DIAG_PACKETCOUNTER_LOW (0x20) // 72 | ||
125 | #define DMA_DIAG_PACKETCOUNTER_HIGH (0x24) // 73 | ||
126 | #define DMA_DIAG_TIMECOUNTER_LOW (0x28) // 74 | ||
127 | #define DMA_DIAG_TIMECOUNTER_HIGH (0x2C) // 75 | ||
128 | #define DMA_DIAG_RECHECKCOUNTER (0x30) // 76 ( Split completions on read ) | ||
129 | #define DMA_DIAG_WAITTIMEOUTINIT (0x34) // 77 | ||
130 | #define DMA_DIAG_WAITOVERFLOWCOUNTER (0x38) // 78 | ||
131 | #define DMA_DIAG_WAITCOUNTER (0x3C) // 79 | ||
132 | |||
133 | // -------------------------------------------------------------------------- | ||
134 | // DMA Buffer | ||
135 | |||
136 | #define TS_INPUT_BASE (0x200) | ||
137 | #define TS_INPUT_CONTROL(i) (TS_INPUT_BASE + (i) * 16 + 0x00) | ||
138 | |||
139 | #define TS_OUTPUT_BASE (0x280) | ||
140 | #define TS_OUTPUT_CONTROL(i) (TS_OUTPUT_BASE + (i) * 16 + 0x00) | ||
141 | |||
142 | #define DMA_BUFFER_BASE (0x300) | ||
143 | |||
144 | #define DMA_BUFFER_CONTROL(i) (DMA_BUFFER_BASE + (i) * 16 + 0x00) | ||
145 | #define DMA_BUFFER_ACK(i) (DMA_BUFFER_BASE + (i) * 16 + 0x04) | ||
146 | #define DMA_BUFFER_CURRENT(i) (DMA_BUFFER_BASE + (i) * 16 + 0x08) | ||
147 | #define DMA_BUFFER_SIZE(i) (DMA_BUFFER_BASE + (i) * 16 + 0x0c) | ||
148 | |||
149 | #define DMA_BASE_ADDRESS_TABLE (0x2000) | ||
150 | #define DMA_BASE_ADDRESS_TABLE_ENTRIES (512) | ||
151 | |||
diff --git a/drivers/media/dvb/ddbridge/ddbridge.h b/drivers/media/dvb/ddbridge/ddbridge.h new file mode 100644 index 00000000000..c8363010356 --- /dev/null +++ b/drivers/media/dvb/ddbridge/ddbridge.h | |||
@@ -0,0 +1,187 @@ | |||
1 | /* | ||
2 | * ddbridge.h: Digital Devices PCIe bridge driver | ||
3 | * | ||
4 | * Copyright (C) 2010-2011 Digital Devices GmbH | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or | ||
7 | * modify it under the terms of the GNU General Public License | ||
8 | * version 2 only, as published by the Free Software Foundation. | ||
9 | * | ||
10 | * | ||
11 | * This program is distributed in the hope that it will be useful, | ||
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
14 | * GNU General Public License for more details. | ||
15 | * | ||
16 | * | ||
17 | * You should have received a copy of the GNU General Public License | ||
18 | * along with this program; if not, write to the Free Software | ||
19 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA | ||
20 | * 02110-1301, USA | ||
21 | * Or, point your browser to http://www.gnu.org/copyleft/gpl.html | ||
22 | */ | ||
23 | |||
24 | #ifndef _DDBRIDGE_H_ | ||
25 | #define _DDBRIDGE_H_ | ||
26 | |||
27 | #include <linux/types.h> | ||
28 | #include <linux/sched.h> | ||
29 | #include <linux/interrupt.h> | ||
30 | #include <linux/i2c.h> | ||
31 | #include <linux/mutex.h> | ||
32 | #include <asm/dma.h> | ||
33 | #include <linux/dvb/frontend.h> | ||
34 | #include <linux/dvb/ca.h> | ||
35 | #include <linux/dvb/video.h> | ||
36 | #include <linux/dvb/audio.h> | ||
37 | #include <linux/socket.h> | ||
38 | |||
39 | #include "dmxdev.h" | ||
40 | #include "dvbdev.h" | ||
41 | #include "dvb_demux.h" | ||
42 | #include "dvb_frontend.h" | ||
43 | #include "dvb_ringbuffer.h" | ||
44 | #include "dvb_ca_en50221.h" | ||
45 | #include "dvb_net.h" | ||
46 | #include "cxd2099.h" | ||
47 | |||
48 | #define DDB_MAX_I2C 4 | ||
49 | #define DDB_MAX_PORT 4 | ||
50 | #define DDB_MAX_INPUT 8 | ||
51 | #define DDB_MAX_OUTPUT 4 | ||
52 | |||
53 | struct ddb_info { | ||
54 | int type; | ||
55 | #define DDB_NONE 0 | ||
56 | #define DDB_OCTOPUS 1 | ||
57 | char *name; | ||
58 | int port_num; | ||
59 | u32 port_type[DDB_MAX_PORT]; | ||
60 | }; | ||
61 | |||
62 | /* DMA_SIZE MUST be divisible by 188 and 128 !!! */ | ||
63 | |||
64 | #define INPUT_DMA_MAX_BUFS 32 /* hardware table limit */ | ||
65 | #define INPUT_DMA_BUFS 8 | ||
66 | #define INPUT_DMA_SIZE (128*47*21) | ||
67 | |||
68 | #define OUTPUT_DMA_MAX_BUFS 32 | ||
69 | #define OUTPUT_DMA_BUFS 8 | ||
70 | #define OUTPUT_DMA_SIZE (128*47*21) | ||
71 | |||
72 | struct ddb; | ||
73 | struct ddb_port; | ||
74 | |||
75 | struct ddb_input { | ||
76 | struct ddb_port *port; | ||
77 | u32 nr; | ||
78 | int attached; | ||
79 | |||
80 | dma_addr_t pbuf[INPUT_DMA_MAX_BUFS]; | ||
81 | u8 *vbuf[INPUT_DMA_MAX_BUFS]; | ||
82 | u32 dma_buf_num; | ||
83 | u32 dma_buf_size; | ||
84 | |||
85 | struct tasklet_struct tasklet; | ||
86 | spinlock_t lock; | ||
87 | wait_queue_head_t wq; | ||
88 | int running; | ||
89 | u32 stat; | ||
90 | u32 cbuf; | ||
91 | u32 coff; | ||
92 | |||
93 | struct dvb_adapter adap; | ||
94 | struct dvb_device *dev; | ||
95 | struct dvb_frontend *fe; | ||
96 | struct dvb_frontend *fe2; | ||
97 | struct dmxdev dmxdev; | ||
98 | struct dvb_demux demux; | ||
99 | struct dvb_net dvbnet; | ||
100 | struct dmx_frontend hw_frontend; | ||
101 | struct dmx_frontend mem_frontend; | ||
102 | int users; | ||
103 | int (*gate_ctrl)(struct dvb_frontend *, int); | ||
104 | }; | ||
105 | |||
106 | struct ddb_output { | ||
107 | struct ddb_port *port; | ||
108 | u32 nr; | ||
109 | dma_addr_t pbuf[OUTPUT_DMA_MAX_BUFS]; | ||
110 | u8 *vbuf[OUTPUT_DMA_MAX_BUFS]; | ||
111 | u32 dma_buf_num; | ||
112 | u32 dma_buf_size; | ||
113 | struct tasklet_struct tasklet; | ||
114 | spinlock_t lock; | ||
115 | wait_queue_head_t wq; | ||
116 | int running; | ||
117 | u32 stat; | ||
118 | u32 cbuf; | ||
119 | u32 coff; | ||
120 | |||
121 | struct dvb_adapter adap; | ||
122 | struct dvb_device *dev; | ||
123 | }; | ||
124 | |||
125 | struct ddb_i2c { | ||
126 | struct ddb *dev; | ||
127 | u32 nr; | ||
128 | struct i2c_adapter adap; | ||
129 | struct i2c_adapter adap2; | ||
130 | u32 regs; | ||
131 | u32 rbuf; | ||
132 | u32 wbuf; | ||
133 | int done; | ||
134 | wait_queue_head_t wq; | ||
135 | }; | ||
136 | |||
137 | struct ddb_port { | ||
138 | struct ddb *dev; | ||
139 | u32 nr; | ||
140 | struct ddb_i2c *i2c; | ||
141 | struct mutex i2c_gate_lock; | ||
142 | u32 class; | ||
143 | #define DDB_PORT_NONE 0 | ||
144 | #define DDB_PORT_CI 1 | ||
145 | #define DDB_PORT_TUNER 2 | ||
146 | u32 type; | ||
147 | #define DDB_TUNER_NONE 0 | ||
148 | #define DDB_TUNER_DVBS_ST 1 | ||
149 | #define DDB_TUNER_DVBS_ST_AA 2 | ||
150 | #define DDB_TUNER_DVBCT_TR 16 | ||
151 | #define DDB_TUNER_DVBCT_ST 17 | ||
152 | u32 adr; | ||
153 | |||
154 | struct ddb_input *input[2]; | ||
155 | struct ddb_output *output; | ||
156 | struct dvb_ca_en50221 *en; | ||
157 | }; | ||
158 | |||
159 | struct ddb { | ||
160 | struct pci_dev *pdev; | ||
161 | unsigned char *regs; | ||
162 | struct ddb_port port[DDB_MAX_PORT]; | ||
163 | struct ddb_i2c i2c[DDB_MAX_I2C]; | ||
164 | struct ddb_input input[DDB_MAX_INPUT]; | ||
165 | struct ddb_output output[DDB_MAX_OUTPUT]; | ||
166 | |||
167 | struct device *ddb_dev; | ||
168 | int nr; | ||
169 | u8 iobuf[1028]; | ||
170 | |||
171 | struct ddb_info *info; | ||
172 | int msi; | ||
173 | }; | ||
174 | |||
175 | /****************************************************************************/ | ||
176 | |||
177 | #define ddbwritel(_val, _adr) writel((_val), \ | ||
178 | (char *) (dev->regs+(_adr))) | ||
179 | #define ddbreadl(_adr) readl((char *) (dev->regs+(_adr))) | ||
180 | #define ddbcpyto(_adr,_src,_count) memcpy_toio((char *) \ | ||
181 | (dev->regs+(_adr)),(_src),(_count)) | ||
182 | #define ddbcpyfrom(_dst,_adr,_count) memcpy_fromio((_dst),(char *) \ | ||
183 | (dev->regs+(_adr)),(_count)) | ||
184 | |||
185 | /****************************************************************************/ | ||
186 | |||
187 | #endif | ||