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-rw-r--r--drivers/isdn/hardware/mISDN/Kconfig13
-rw-r--r--drivers/isdn/hardware/mISDN/Makefile2
-rw-r--r--drivers/isdn/hardware/mISDN/isar.h269
-rw-r--r--drivers/isdn/hardware/mISDN/mISDNisar.c1726
-rw-r--r--drivers/isdn/hardware/mISDN/speedfax.c526
5 files changed, 2536 insertions, 0 deletions
diff --git a/drivers/isdn/hardware/mISDN/Kconfig b/drivers/isdn/hardware/mISDN/Kconfig
index 212dee6adec..2600534be07 100644
--- a/drivers/isdn/hardware/mISDN/Kconfig
+++ b/drivers/isdn/hardware/mISDN/Kconfig
@@ -47,6 +47,15 @@ config MISDN_AVMFRITZ
47 help 47 help
48 Enable support for AVMs FRITZ!CARD PCI cards 48 Enable support for AVMs FRITZ!CARD PCI cards
49 49
50config MISDN_SPEEDFAX
51 tristate "Support for Sedlbauer Speedfax+"
52 depends on MISDN
53 depends on PCI
54 select MISDN_IPAC
55 select MISDN_ISAR
56 help
57 Enable support for Sedlbauer Speedfax+.
58
50config MISDN_INFINEON 59config MISDN_INFINEON
51 tristate "Support for cards with Infineon chipset" 60 tristate "Support for cards with Infineon chipset"
52 depends on MISDN 61 depends on MISDN
@@ -61,3 +70,7 @@ config MISDN_IPAC
61 tristate 70 tristate
62 depends on MISDN 71 depends on MISDN
63 72
73config MISDN_ISAR
74 tristate
75 depends on MISDN
76
diff --git a/drivers/isdn/hardware/mISDN/Makefile b/drivers/isdn/hardware/mISDN/Makefile
index 8204d84af70..e18f964e185 100644
--- a/drivers/isdn/hardware/mISDN/Makefile
+++ b/drivers/isdn/hardware/mISDN/Makefile
@@ -7,6 +7,8 @@ obj-$(CONFIG_MISDN_HFCPCI) += hfcpci.o
7obj-$(CONFIG_MISDN_HFCMULTI) += hfcmulti.o 7obj-$(CONFIG_MISDN_HFCMULTI) += hfcmulti.o
8obj-$(CONFIG_MISDN_HFCUSB) += hfcsusb.o 8obj-$(CONFIG_MISDN_HFCUSB) += hfcsusb.o
9obj-$(CONFIG_MISDN_AVMFRITZ) += avmfritz.o 9obj-$(CONFIG_MISDN_AVMFRITZ) += avmfritz.o
10obj-$(CONFIG_MISDN_SPEEDFAX) += speedfax.o
10obj-$(CONFIG_MISDN_INFINEON) += mISDNinfineon.o 11obj-$(CONFIG_MISDN_INFINEON) += mISDNinfineon.o
11# chip modules 12# chip modules
12obj-$(CONFIG_MISDN_IPAC) += mISDNipac.o 13obj-$(CONFIG_MISDN_IPAC) += mISDNipac.o
14obj-$(CONFIG_MISDN_ISAR) += mISDNisar.o
diff --git a/drivers/isdn/hardware/mISDN/isar.h b/drivers/isdn/hardware/mISDN/isar.h
new file mode 100644
index 00000000000..092351acd2a
--- /dev/null
+++ b/drivers/isdn/hardware/mISDN/isar.h
@@ -0,0 +1,269 @@
1/*
2 *
3 * isar.h ISAR (Siemens PSB 7110) specific defines
4 *
5 * Author Karsten Keil (keil@isdn4linux.de)
6 *
7 * Copyright 2009 by Karsten Keil <keil@isdn4linux.de>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 *
22 */
23
24#include "iohelper.h"
25
26struct isar_hw;
27
28struct isar_ch {
29 struct bchannel bch;
30 struct isar_hw *is;
31 struct timer_list ftimer;
32 u8 nr;
33 u8 dpath;
34 u8 mml;
35 u8 state;
36 u8 cmd;
37 u8 mod;
38 u8 newcmd;
39 u8 newmod;
40 u8 try_mod;
41 u8 conmsg[16];
42};
43
44struct isar_hw {
45 struct isar_ch ch[2];
46 void *hw;
47 spinlock_t *hwlock; /* lock HW acccess */
48 char *name;
49 struct module *owner;
50 read_reg_t *read_reg;
51 write_reg_t *write_reg;
52 fifo_func_t *read_fifo;
53 fifo_func_t *write_fifo;
54 int (*ctrl)(void *, u32, u_long);
55 void (*release)(struct isar_hw *);
56 int (*init)(struct isar_hw *);
57 int (*open)(struct isar_hw *, struct channel_req *);
58 int (*firmware)(struct isar_hw *, const u8 *, int);
59 unsigned long Flags;
60 int version;
61 u8 bstat;
62 u8 iis;
63 u8 cmsb;
64 u8 clsb;
65 u8 buf[256];
66 u8 log[256];
67};
68
69#define ISAR_IRQMSK 0x04
70#define ISAR_IRQSTA 0x04
71#define ISAR_IRQBIT 0x75
72#define ISAR_CTRL_H 0x61
73#define ISAR_CTRL_L 0x60
74#define ISAR_IIS 0x58
75#define ISAR_IIA 0x58
76#define ISAR_HIS 0x50
77#define ISAR_HIA 0x50
78#define ISAR_MBOX 0x4c
79#define ISAR_WADR 0x4a
80#define ISAR_RADR 0x48
81
82#define ISAR_HIS_VNR 0x14
83#define ISAR_HIS_DKEY 0x02
84#define ISAR_HIS_FIRM 0x1e
85#define ISAR_HIS_STDSP 0x08
86#define ISAR_HIS_DIAG 0x05
87#define ISAR_HIS_P0CFG 0x3c
88#define ISAR_HIS_P12CFG 0x24
89#define ISAR_HIS_SARTCFG 0x25
90#define ISAR_HIS_PUMPCFG 0x26
91#define ISAR_HIS_PUMPCTRL 0x2a
92#define ISAR_HIS_IOM2CFG 0x27
93#define ISAR_HIS_IOM2REQ 0x07
94#define ISAR_HIS_IOM2CTRL 0x2b
95#define ISAR_HIS_BSTREQ 0x0c
96#define ISAR_HIS_PSTREQ 0x0e
97#define ISAR_HIS_SDATA 0x20
98#define ISAR_HIS_DPS1 0x40
99#define ISAR_HIS_DPS2 0x80
100#define SET_DPS(x) ((x<<6) & 0xc0)
101
102#define ISAR_IIS_MSCMSD 0x3f
103#define ISAR_IIS_VNR 0x15
104#define ISAR_IIS_DKEY 0x03
105#define ISAR_IIS_FIRM 0x1f
106#define ISAR_IIS_STDSP 0x09
107#define ISAR_IIS_DIAG 0x25
108#define ISAR_IIS_GSTEV 0x00
109#define ISAR_IIS_BSTEV 0x28
110#define ISAR_IIS_BSTRSP 0x2c
111#define ISAR_IIS_PSTRSP 0x2e
112#define ISAR_IIS_PSTEV 0x2a
113#define ISAR_IIS_IOM2RSP 0x27
114#define ISAR_IIS_RDATA 0x20
115#define ISAR_IIS_INVMSG 0x3f
116
117#define ISAR_CTRL_SWVER 0x10
118#define ISAR_CTRL_STST 0x40
119
120#define ISAR_MSG_HWVER 0x20
121
122#define ISAR_DP1_USE 1
123#define ISAR_DP2_USE 2
124#define ISAR_RATE_REQ 3
125
126#define PMOD_DISABLE 0
127#define PMOD_FAX 1
128#define PMOD_DATAMODEM 2
129#define PMOD_HALFDUPLEX 3
130#define PMOD_V110 4
131#define PMOD_DTMF 5
132#define PMOD_DTMF_TRANS 6
133#define PMOD_BYPASS 7
134
135#define PCTRL_ORIG 0x80
136#define PV32P2_V23R 0x40
137#define PV32P2_V22A 0x20
138#define PV32P2_V22B 0x10
139#define PV32P2_V22C 0x08
140#define PV32P2_V21 0x02
141#define PV32P2_BEL 0x01
142
143/* LSB MSB in ISAR doc wrong !!! Arghhh */
144#define PV32P3_AMOD 0x80
145#define PV32P3_V32B 0x02
146#define PV32P3_V23B 0x01
147#define PV32P4_48 0x11
148#define PV32P5_48 0x05
149#define PV32P4_UT48 0x11
150#define PV32P5_UT48 0x0d
151#define PV32P4_96 0x11
152#define PV32P5_96 0x03
153#define PV32P4_UT96 0x11
154#define PV32P5_UT96 0x0f
155#define PV32P4_B96 0x91
156#define PV32P5_B96 0x0b
157#define PV32P4_UTB96 0xd1
158#define PV32P5_UTB96 0x0f
159#define PV32P4_120 0xb1
160#define PV32P5_120 0x09
161#define PV32P4_UT120 0xf1
162#define PV32P5_UT120 0x0f
163#define PV32P4_144 0x99
164#define PV32P5_144 0x09
165#define PV32P4_UT144 0xf9
166#define PV32P5_UT144 0x0f
167#define PV32P6_CTN 0x01
168#define PV32P6_ATN 0x02
169
170#define PFAXP2_CTN 0x01
171#define PFAXP2_ATN 0x04
172
173#define PSEV_10MS_TIMER 0x02
174#define PSEV_CON_ON 0x18
175#define PSEV_CON_OFF 0x19
176#define PSEV_V24_OFF 0x20
177#define PSEV_CTS_ON 0x21
178#define PSEV_CTS_OFF 0x22
179#define PSEV_DCD_ON 0x23
180#define PSEV_DCD_OFF 0x24
181#define PSEV_DSR_ON 0x25
182#define PSEV_DSR_OFF 0x26
183#define PSEV_REM_RET 0xcc
184#define PSEV_REM_REN 0xcd
185#define PSEV_GSTN_CLR 0xd4
186
187#define PSEV_RSP_READY 0xbc
188#define PSEV_LINE_TX_H 0xb3
189#define PSEV_LINE_TX_B 0xb2
190#define PSEV_LINE_RX_H 0xb1
191#define PSEV_LINE_RX_B 0xb0
192#define PSEV_RSP_CONN 0xb5
193#define PSEV_RSP_DISC 0xb7
194#define PSEV_RSP_FCERR 0xb9
195#define PSEV_RSP_SILDET 0xbe
196#define PSEV_RSP_SILOFF 0xab
197#define PSEV_FLAGS_DET 0xba
198
199#define PCTRL_CMD_TDTMF 0x5a
200
201#define PCTRL_CMD_FTH 0xa7
202#define PCTRL_CMD_FRH 0xa5
203#define PCTRL_CMD_FTM 0xa8
204#define PCTRL_CMD_FRM 0xa6
205#define PCTRL_CMD_SILON 0xac
206#define PCTRL_CMD_CONT 0xa2
207#define PCTRL_CMD_ESC 0xa4
208#define PCTRL_CMD_SILOFF 0xab
209#define PCTRL_CMD_HALT 0xa9
210
211#define PCTRL_LOC_RET 0xcf
212#define PCTRL_LOC_REN 0xce
213
214#define SMODE_DISABLE 0
215#define SMODE_V14 2
216#define SMODE_HDLC 3
217#define SMODE_BINARY 4
218#define SMODE_FSK_V14 5
219
220#define SCTRL_HDMC_BOTH 0x00
221#define SCTRL_HDMC_DTX 0x80
222#define SCTRL_HDMC_DRX 0x40
223#define S_P1_OVSP 0x40
224#define S_P1_SNP 0x20
225#define S_P1_EOP 0x10
226#define S_P1_EDP 0x08
227#define S_P1_NSB 0x04
228#define S_P1_CHS_8 0x03
229#define S_P1_CHS_7 0x02
230#define S_P1_CHS_6 0x01
231#define S_P1_CHS_5 0x00
232
233#define S_P2_BFT_DEF 0x10
234
235#define IOM_CTRL_ENA 0x80
236#define IOM_CTRL_NOPCM 0x00
237#define IOM_CTRL_ALAW 0x02
238#define IOM_CTRL_ULAW 0x04
239#define IOM_CTRL_RCV 0x01
240
241#define IOM_P1_TXD 0x10
242
243#define HDLC_FED 0x40
244#define HDLC_FSD 0x20
245#define HDLC_FST 0x20
246#define HDLC_ERROR 0x1c
247#define HDLC_ERR_FAD 0x10
248#define HDLC_ERR_RER 0x08
249#define HDLC_ERR_CER 0x04
250#define SART_NMD 0x01
251
252#define BSTAT_RDM0 0x1
253#define BSTAT_RDM1 0x2
254#define BSTAT_RDM2 0x4
255#define BSTAT_RDM3 0x8
256#define BSTEV_TBO 0x1f
257#define BSTEV_RBO 0x2f
258
259/* FAX State Machine */
260#define STFAX_NULL 0
261#define STFAX_READY 1
262#define STFAX_LINE 2
263#define STFAX_CONT 3
264#define STFAX_ACTIV 4
265#define STFAX_ESCAPE 5
266#define STFAX_SILDET 6
267
268extern u32 mISDNisar_init(struct isar_hw *, void *);
269extern void mISDNisar_irq(struct isar_hw *);
diff --git a/drivers/isdn/hardware/mISDN/mISDNisar.c b/drivers/isdn/hardware/mISDN/mISDNisar.c
new file mode 100644
index 00000000000..de352a17673
--- /dev/null
+++ b/drivers/isdn/hardware/mISDN/mISDNisar.c
@@ -0,0 +1,1726 @@
1/*
2 * mISDNisar.c ISAR (Siemens PSB 7110) specific functions
3 *
4 * Author Karsten Keil (keil@isdn4linux.de)
5 *
6 * Copyright 2009 by Karsten Keil <keil@isdn4linux.de>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20 *
21 */
22
23/* define this to enable static debug messages, if you kernel supports
24 * dynamic debugging, you should use debugfs for this
25 */
26/* #define DEBUG */
27
28#include <linux/delay.h>
29#include <linux/vmalloc.h>
30#include <linux/mISDNhw.h>
31#include "isar.h"
32
33#define ISAR_REV "2.1"
34
35MODULE_AUTHOR("Karsten Keil");
36MODULE_LICENSE("GPL v2");
37MODULE_VERSION(ISAR_REV);
38
39#define DEBUG_HW_FIRMWARE_FIFO 0x10000
40
41static const u8 faxmodulation_s[] = "3,24,48,72,73,74,96,97,98,121,122,145,146";
42static const u8 faxmodulation[] = {3, 24, 48, 72, 73, 74, 96, 97, 98, 121,
43 122, 145, 146};
44#define FAXMODCNT 13
45
46static void isar_setup(struct isar_hw *);
47
48static inline int
49waitforHIA(struct isar_hw *isar, int timeout)
50{
51 int t = timeout;
52 u8 val = isar->read_reg(isar->hw, ISAR_HIA);
53
54 while ((val & 1) && t) {
55 udelay(1);
56 t--;
57 val = isar->read_reg(isar->hw, ISAR_HIA);
58 }
59 pr_debug("%s: HIA after %dus\n", isar->name, timeout - t);
60 return timeout;
61}
62
63/*
64 * send msg to ISAR mailbox
65 * if msg is NULL use isar->buf
66 */
67static int
68send_mbox(struct isar_hw *isar, u8 his, u8 creg, u8 len, u8 *msg)
69{
70 if (!waitforHIA(isar, 1000))
71 return 0;
72 pr_debug("send_mbox(%02x,%02x,%d)\n", his, creg, len);
73 isar->write_reg(isar->hw, ISAR_CTRL_H, creg);
74 isar->write_reg(isar->hw, ISAR_CTRL_L, len);
75 isar->write_reg(isar->hw, ISAR_WADR, 0);
76 if (!msg)
77 msg = isar->buf;
78 if (msg && len) {
79 isar->write_fifo(isar->hw, ISAR_MBOX, msg, len);
80 if (isar->ch[0].bch.debug & DEBUG_HW_BFIFO) {
81 int l = 0;
82
83 while (l < (int)len) {
84 hex_dump_to_buffer(msg + l, len - l, 32, 1,
85 isar->log, 256, 1);
86 pr_debug("%s: %s %02x: %s\n", isar->name,
87 __func__, l, isar->log);
88 l += 32;
89 }
90 }
91 }
92 isar->write_reg(isar->hw, ISAR_HIS, his);
93 waitforHIA(isar, 1000);
94 return 1;
95}
96
97/*
98 * receive message from ISAR mailbox
99 * if msg is NULL use isar->buf
100 */
101static void
102rcv_mbox(struct isar_hw *isar, u8 *msg)
103{
104 if (!msg)
105 msg = isar->buf;
106 isar->write_reg(isar->hw, ISAR_RADR, 0);
107 if (msg && isar->clsb) {
108 isar->read_fifo(isar->hw, ISAR_MBOX, msg, isar->clsb);
109 if (isar->ch[0].bch.debug & DEBUG_HW_BFIFO) {
110 int l = 0;
111
112 while (l < (int)isar->clsb) {
113 hex_dump_to_buffer(msg + l, isar->clsb - l, 32,
114 1, isar->log, 256, 1);
115 pr_debug("%s: %s %02x: %s\n", isar->name,
116 __func__, l, isar->log);
117 l += 32;
118 }
119 }
120 }
121 isar->write_reg(isar->hw, ISAR_IIA, 0);
122}
123
124static inline void
125get_irq_infos(struct isar_hw *isar)
126{
127 isar->iis = isar->read_reg(isar->hw, ISAR_IIS);
128 isar->cmsb = isar->read_reg(isar->hw, ISAR_CTRL_H);
129 isar->clsb = isar->read_reg(isar->hw, ISAR_CTRL_L);
130 pr_debug("%s: rcv_mbox(%02x,%02x,%d)\n", isar->name,
131 isar->iis, isar->cmsb, isar->clsb);
132}
133
134/*
135 * poll answer message from ISAR mailbox
136 * should be used only with ISAR IRQs disabled before DSP was started
137 *
138 */
139static int
140poll_mbox(struct isar_hw *isar, int maxdelay)
141{
142 int t = maxdelay;
143 u8 irq;
144
145 irq = isar->read_reg(isar->hw, ISAR_IRQBIT);
146 while (t && !(irq & ISAR_IRQSTA)) {
147 udelay(1);
148 t--;
149 }
150 if (t) {
151 get_irq_infos(isar);
152 rcv_mbox(isar, NULL);
153 }
154 pr_debug("%s: pulled %d bytes after %d us\n",
155 isar->name, isar->clsb, maxdelay - t);
156 return t;
157}
158
159static int
160ISARVersion(struct isar_hw *isar)
161{
162 int ver;
163
164 /* disable ISAR IRQ */
165 isar->write_reg(isar->hw, ISAR_IRQBIT, 0);
166 isar->buf[0] = ISAR_MSG_HWVER;
167 isar->buf[1] = 0;
168 isar->buf[2] = 1;
169 if (!send_mbox(isar, ISAR_HIS_VNR, 0, 3, NULL))
170 return -1;
171 if (!poll_mbox(isar, 1000))
172 return -2;
173 if (isar->iis == ISAR_IIS_VNR) {
174 if (isar->clsb == 1) {
175 ver = isar->buf[0] & 0xf;
176 return ver;
177 }
178 return -3;
179 }
180 return -4;
181}
182
183static int
184load_firmware(struct isar_hw *isar, const u8 *buf, int size)
185{
186 u32 saved_debug = isar->ch[0].bch.debug;
187 int ret, cnt;
188 u8 nom, noc;
189 u16 left, val, *sp = (u16 *)buf;
190 u8 *mp;
191 u_long flags;
192
193 struct {
194 u16 sadr;
195 u16 len;
196 u16 d_key;
197 } blk_head;
198
199 if (1 != isar->version) {
200 pr_err("%s: ISAR wrong version %d firmware download aborted\n",
201 isar->name, isar->version);
202 return -EINVAL;
203 }
204 if (!(saved_debug & DEBUG_HW_FIRMWARE_FIFO))
205 isar->ch[0].bch.debug &= ~DEBUG_HW_BFIFO;
206 pr_debug("%s: load firmware %d words (%d bytes)\n",
207 isar->name, size/2, size);
208 cnt = 0;
209 size /= 2;
210 /* disable ISAR IRQ */
211 spin_lock_irqsave(isar->hwlock, flags);
212 isar->write_reg(isar->hw, ISAR_IRQBIT, 0);
213 spin_unlock_irqrestore(isar->hwlock, flags);
214 while (cnt < size) {
215 blk_head.sadr = le16_to_cpu(*sp++);
216 blk_head.len = le16_to_cpu(*sp++);
217 blk_head.d_key = le16_to_cpu(*sp++);
218 cnt += 3;
219 pr_debug("ISAR firmware block (%#x,%d,%#x)\n",
220 blk_head.sadr, blk_head.len, blk_head.d_key & 0xff);
221 left = blk_head.len;
222 if (cnt + left > size) {
223 pr_info("%s: firmware error have %d need %d words\n",
224 isar->name, size, cnt + left);
225 ret = -EINVAL;
226 goto reterrflg;
227 }
228 spin_lock_irqsave(isar->hwlock, flags);
229 if (!send_mbox(isar, ISAR_HIS_DKEY, blk_head.d_key & 0xff,
230 0, NULL)) {
231 pr_info("ISAR send_mbox dkey failed\n");
232 ret = -ETIME;
233 goto reterror;
234 }
235 if (!poll_mbox(isar, 1000)) {
236 pr_warning("ISAR poll_mbox dkey failed\n");
237 ret = -ETIME;
238 goto reterror;
239 }
240 spin_unlock_irqrestore(isar->hwlock, flags);
241 if ((isar->iis != ISAR_IIS_DKEY) || isar->cmsb || isar->clsb) {
242 pr_info("ISAR wrong dkey response (%x,%x,%x)\n",
243 isar->iis, isar->cmsb, isar->clsb);
244 ret = 1;
245 goto reterrflg;
246 }
247 while (left > 0) {
248 if (left > 126)
249 noc = 126;
250 else
251 noc = left;
252 nom = (2 * noc) + 3;
253 mp = isar->buf;
254 /* the ISAR is big endian */
255 *mp++ = blk_head.sadr >> 8;
256 *mp++ = blk_head.sadr & 0xFF;
257 left -= noc;
258 cnt += noc;
259 *mp++ = noc;
260 pr_debug("%s: load %3d words at %04x\n", isar->name,
261 noc, blk_head.sadr);
262 blk_head.sadr += noc;
263 while (noc) {
264 val = le16_to_cpu(*sp++);
265 *mp++ = val >> 8;
266 *mp++ = val & 0xFF;;
267 noc--;
268 }
269 spin_lock_irqsave(isar->hwlock, flags);
270 if (!send_mbox(isar, ISAR_HIS_FIRM, 0, nom, NULL)) {
271 pr_info("ISAR send_mbox prog failed\n");
272 ret = -ETIME;
273 goto reterror;
274 }
275 if (!poll_mbox(isar, 1000)) {
276 pr_info("ISAR poll_mbox prog failed\n");
277 ret = -ETIME;
278 goto reterror;
279 }
280 spin_unlock_irqrestore(isar->hwlock, flags);
281 if ((isar->iis != ISAR_IIS_FIRM) ||
282 isar->cmsb || isar->clsb) {
283 pr_info("ISAR wrong prog response (%x,%x,%x)\n",
284 isar->iis, isar->cmsb, isar->clsb);
285 ret = -EIO;
286 goto reterrflg;
287 }
288 }
289 pr_debug("%s: ISAR firmware block %d words loaded\n",
290 isar->name, blk_head.len);
291 }
292 isar->ch[0].bch.debug = saved_debug;
293 /* 10ms delay */
294 cnt = 10;
295 while (cnt--)
296 mdelay(1);
297 isar->buf[0] = 0xff;
298 isar->buf[1] = 0xfe;
299 isar->bstat = 0;
300 spin_lock_irqsave(isar->hwlock, flags);
301 if (!send_mbox(isar, ISAR_HIS_STDSP, 0, 2, NULL)) {
302 pr_info("ISAR send_mbox start dsp failed\n");
303 ret = -ETIME;
304 goto reterror;
305 }
306 if (!poll_mbox(isar, 1000)) {
307 pr_info("ISAR poll_mbox start dsp failed\n");
308 ret = -ETIME;
309 goto reterror;
310 }
311 if ((isar->iis != ISAR_IIS_STDSP) || isar->cmsb || isar->clsb) {
312 pr_info("ISAR wrong start dsp response (%x,%x,%x)\n",
313 isar->iis, isar->cmsb, isar->clsb);
314 ret = -EIO;
315 goto reterror;
316 } else
317 pr_debug("%s: ISAR start dsp success\n", isar->name);
318
319 /* NORMAL mode entered */
320 /* Enable IRQs of ISAR */
321 isar->write_reg(isar->hw, ISAR_IRQBIT, ISAR_IRQSTA);
322 spin_unlock_irqrestore(isar->hwlock, flags);
323 cnt = 1000; /* max 1s */
324 while ((!isar->bstat) && cnt) {
325 mdelay(1);
326 cnt--;
327 }
328 if (!cnt) {
329 pr_info("ISAR no general status event received\n");
330 ret = -ETIME;
331 goto reterrflg;
332 } else
333 pr_debug("%s: ISAR general status event %x\n",
334 isar->name, isar->bstat);
335 /* 10ms delay */
336 cnt = 10;
337 while (cnt--)
338 mdelay(1);
339 isar->iis = 0;
340 spin_lock_irqsave(isar->hwlock, flags);
341 if (!send_mbox(isar, ISAR_HIS_DIAG, ISAR_CTRL_STST, 0, NULL)) {
342 pr_info("ISAR send_mbox self tst failed\n");
343 ret = -ETIME;
344 goto reterror;
345 }
346 spin_unlock_irqrestore(isar->hwlock, flags);
347 cnt = 10000; /* max 100 ms */
348 while ((isar->iis != ISAR_IIS_DIAG) && cnt) {
349 udelay(10);
350 cnt--;
351 }
352 mdelay(1);
353 if (!cnt) {
354 pr_info("ISAR no self tst response\n");
355 ret = -ETIME;
356 goto reterrflg;
357 }
358 if ((isar->cmsb == ISAR_CTRL_STST) && (isar->clsb == 1)
359 && (isar->buf[0] == 0))
360 pr_debug("%s: ISAR selftest OK\n", isar->name);
361 else {
362 pr_info("ISAR selftest not OK %x/%x/%x\n",
363 isar->cmsb, isar->clsb, isar->buf[0]);
364 ret = -EIO;
365 goto reterrflg;
366 }
367 spin_lock_irqsave(isar->hwlock, flags);
368 isar->iis = 0;
369 if (!send_mbox(isar, ISAR_HIS_DIAG, ISAR_CTRL_SWVER, 0, NULL)) {
370 pr_info("ISAR RQST SVN failed\n");
371 ret = -ETIME;
372 goto reterror;
373 }
374 spin_unlock_irqrestore(isar->hwlock, flags);
375 cnt = 30000; /* max 300 ms */
376 while ((isar->iis != ISAR_IIS_DIAG) && cnt) {
377 udelay(10);
378 cnt--;
379 }
380 mdelay(1);
381 if (!cnt) {
382 pr_info("ISAR no SVN response\n");
383 ret = -ETIME;
384 goto reterrflg;
385 } else {
386 if ((isar->cmsb == ISAR_CTRL_SWVER) && (isar->clsb == 1)) {
387 pr_notice("%s: ISAR software version %#x\n",
388 isar->name, isar->buf[0]);
389 } else {
390 pr_info("%s: ISAR wrong swver response (%x,%x)"
391 " cnt(%d)\n", isar->name, isar->cmsb,
392 isar->clsb, cnt);
393 ret = -EIO;
394 goto reterrflg;
395 }
396 }
397 spin_lock_irqsave(isar->hwlock, flags);
398 isar_setup(isar);
399 spin_unlock_irqrestore(isar->hwlock, flags);
400 ret = 0;
401reterrflg:
402 spin_lock_irqsave(isar->hwlock, flags);
403reterror:
404 isar->ch[0].bch.debug = saved_debug;
405 if (ret)
406 /* disable ISAR IRQ */
407 isar->write_reg(isar->hw, ISAR_IRQBIT, 0);
408 spin_unlock_irqrestore(isar->hwlock, flags);
409 return ret;
410}
411
412static inline void
413deliver_status(struct isar_ch *ch, int status)
414{
415 pr_debug("%s: HL->LL FAXIND %x\n", ch->is->name, status);
416 _queue_data(&ch->bch.ch, PH_CONTROL_IND, status, 0, NULL, GFP_ATOMIC);
417}
418
419static inline void
420isar_rcv_frame(struct isar_ch *ch)
421{
422 u8 *ptr;
423
424 if (!ch->is->clsb) {
425 pr_debug("%s; ISAR zero len frame\n", ch->is->name);
426 ch->is->write_reg(ch->is->hw, ISAR_IIA, 0);
427 return;
428 }
429 switch (ch->bch.state) {
430 case ISDN_P_NONE:
431 pr_debug("%s: ISAR protocol 0 spurious IIS_RDATA %x/%x/%x\n",
432 ch->is->name, ch->is->iis, ch->is->cmsb, ch->is->clsb);
433 ch->is->write_reg(ch->is->hw, ISAR_IIA, 0);
434 break;
435 case ISDN_P_B_RAW:
436 case ISDN_P_B_L2DTMF:
437 case ISDN_P_B_MODEM_ASYNC:
438 if (!ch->bch.rx_skb) {
439 ch->bch.rx_skb = mI_alloc_skb(ch->bch.maxlen,
440 GFP_ATOMIC);
441 if (unlikely(!ch->bch.rx_skb)) {
442 pr_info("%s: B receive out of memory\n",
443 ch->is->name);
444 ch->is->write_reg(ch->is->hw, ISAR_IIA, 0);
445 break;
446 }
447 }
448 rcv_mbox(ch->is, skb_put(ch->bch.rx_skb, ch->is->clsb));
449 recv_Bchannel(&ch->bch, 0);
450 break;
451 case ISDN_P_B_HDLC:
452 if (!ch->bch.rx_skb) {
453 ch->bch.rx_skb = mI_alloc_skb(ch->bch.maxlen,
454 GFP_ATOMIC);
455 if (unlikely(!ch->bch.rx_skb)) {
456 pr_info("%s: B receive out of memory\n",
457 ch->is->name);
458 ch->is->write_reg(ch->is->hw, ISAR_IIA, 0);
459 break;
460 }
461 }
462 if ((ch->bch.rx_skb->len + ch->is->clsb) >
463 (ch->bch.maxlen + 2)) {
464 pr_debug("%s: incoming packet too large\n",
465 ch->is->name);
466 ch->is->write_reg(ch->is->hw, ISAR_IIA, 0);
467 skb_trim(ch->bch.rx_skb, 0);
468 break;
469 }
470 if (ch->is->cmsb & HDLC_ERROR) {
471 pr_debug("%s: ISAR frame error %x len %d\n",
472 ch->is->name, ch->is->cmsb, ch->is->clsb);
473#ifdef ERROR_STATISTIC
474 if (ch->is->cmsb & HDLC_ERR_RER)
475 ch->bch.err_inv++;
476 if (ch->is->cmsb & HDLC_ERR_CER)
477 ch->bch.err_crc++;
478#endif
479 skb_trim(ch->bch.rx_skb, 0);
480 ch->is->write_reg(ch->is->hw, ISAR_IIA, 0);
481 break;
482 }
483 if (ch->is->cmsb & HDLC_FSD)
484 skb_trim(ch->bch.rx_skb, 0);
485 ptr = skb_put(ch->bch.rx_skb, ch->is->clsb);
486 rcv_mbox(ch->is, ptr);
487 if (ch->is->cmsb & HDLC_FED) {
488 if (ch->bch.rx_skb->len < 3) { /* last 2 are the FCS */
489 pr_debug("%s: ISAR frame to short %d\n",
490 ch->is->name, ch->bch.rx_skb->len);
491 skb_trim(ch->bch.rx_skb, 0);
492 break;
493 }
494 skb_trim(ch->bch.rx_skb, ch->bch.rx_skb->len - 2);
495 recv_Bchannel(&ch->bch, 0);
496 }
497 break;
498 case ISDN_P_B_T30_FAX:
499 if (ch->state != STFAX_ACTIV) {
500 pr_debug("%s: isar_rcv_frame: not ACTIV\n",
501 ch->is->name);
502 ch->is->write_reg(ch->is->hw, ISAR_IIA, 0);
503 if (ch->bch.rx_skb)
504 skb_trim(ch->bch.rx_skb, 0);
505 break;
506 }
507 if (!ch->bch.rx_skb) {
508 ch->bch.rx_skb = mI_alloc_skb(ch->bch.maxlen,
509 GFP_ATOMIC);
510 if (unlikely(!ch->bch.rx_skb)) {
511 pr_info("%s: B receive out of memory\n",
512 __func__);
513 ch->is->write_reg(ch->is->hw, ISAR_IIA, 0);
514 break;
515 }
516 }
517 if (ch->cmd == PCTRL_CMD_FRM) {
518 rcv_mbox(ch->is, skb_put(ch->bch.rx_skb, ch->is->clsb));
519 pr_debug("%s: isar_rcv_frame: %d\n",
520 ch->is->name, ch->bch.rx_skb->len);
521 if (ch->is->cmsb & SART_NMD) { /* ABORT */
522 pr_debug("%s: isar_rcv_frame: no more data\n",
523 ch->is->name);
524 ch->is->write_reg(ch->is->hw, ISAR_IIA, 0);
525 send_mbox(ch->is, SET_DPS(ch->dpath) |
526 ISAR_HIS_PUMPCTRL, PCTRL_CMD_ESC,
527 0, NULL);
528 ch->state = STFAX_ESCAPE;
529 /* set_skb_flag(skb, DF_NOMOREDATA); */
530 }
531 recv_Bchannel(&ch->bch, 0);
532 if (ch->is->cmsb & SART_NMD)
533 deliver_status(ch, HW_MOD_NOCARR);
534 break;
535 }
536 if (ch->cmd != PCTRL_CMD_FRH) {
537 pr_debug("%s: isar_rcv_frame: unknown fax mode %x\n",
538 ch->is->name, ch->cmd);
539 ch->is->write_reg(ch->is->hw, ISAR_IIA, 0);
540 if (ch->bch.rx_skb)
541 skb_trim(ch->bch.rx_skb, 0);
542 break;
543 }
544 /* PCTRL_CMD_FRH */
545 if ((ch->bch.rx_skb->len + ch->is->clsb) >
546 (ch->bch.maxlen + 2)) {
547 pr_info("%s: %s incoming packet too large\n",
548 ch->is->name, __func__);
549 ch->is->write_reg(ch->is->hw, ISAR_IIA, 0);
550 skb_trim(ch->bch.rx_skb, 0);
551 break;
552 } else if (ch->is->cmsb & HDLC_ERROR) {
553 pr_info("%s: ISAR frame error %x len %d\n",
554 ch->is->name, ch->is->cmsb, ch->is->clsb);
555 skb_trim(ch->bch.rx_skb, 0);
556 ch->is->write_reg(ch->is->hw, ISAR_IIA, 0);
557 break;
558 }
559 if (ch->is->cmsb & HDLC_FSD)
560 skb_trim(ch->bch.rx_skb, 0);
561 ptr = skb_put(ch->bch.rx_skb, ch->is->clsb);
562 rcv_mbox(ch->is, ptr);
563 if (ch->is->cmsb & HDLC_FED) {
564 if (ch->bch.rx_skb->len < 3) { /* last 2 are the FCS */
565 pr_info("%s: ISAR frame to short %d\n",
566 ch->is->name, ch->bch.rx_skb->len);
567 skb_trim(ch->bch.rx_skb, 0);
568 break;
569 }
570 skb_trim(ch->bch.rx_skb, ch->bch.rx_skb->len - 2);
571 recv_Bchannel(&ch->bch, 0);
572 }
573 if (ch->is->cmsb & SART_NMD) { /* ABORT */
574 pr_debug("%s: isar_rcv_frame: no more data\n",
575 ch->is->name);
576 ch->is->write_reg(ch->is->hw, ISAR_IIA, 0);
577 if (ch->bch.rx_skb)
578 skb_trim(ch->bch.rx_skb, 0);
579 send_mbox(ch->is, SET_DPS(ch->dpath) |
580 ISAR_HIS_PUMPCTRL, PCTRL_CMD_ESC, 0, NULL);
581 ch->state = STFAX_ESCAPE;
582 deliver_status(ch, HW_MOD_NOCARR);
583 }
584 break;
585 default:
586 pr_info("isar_rcv_frame protocol (%x)error\n", ch->bch.state);
587 ch->is->write_reg(ch->is->hw, ISAR_IIA, 0);
588 break;
589 }
590}
591
592static void
593isar_fill_fifo(struct isar_ch *ch)
594{
595 int count;
596 u8 msb;
597 u8 *ptr;
598
599 pr_debug("%s: ch%d tx_skb %p tx_idx %d\n",
600 ch->is->name, ch->bch.nr, ch->bch.tx_skb, ch->bch.tx_idx);
601 if (!ch->bch.tx_skb)
602 return;
603 count = ch->bch.tx_skb->len - ch->bch.tx_idx;
604 if (count <= 0)
605 return;
606 if (!(ch->is->bstat &
607 (ch->dpath == 1 ? BSTAT_RDM1 : BSTAT_RDM2)))
608 return;
609 if (count > ch->mml) {
610 msb = 0;
611 count = ch->mml;
612 } else {
613 msb = HDLC_FED;
614 }
615 ptr = ch->bch.tx_skb->data + ch->bch.tx_idx;
616 if (!ch->bch.tx_idx) {
617 pr_debug("%s: frame start\n", ch->is->name);
618 if ((ch->bch.state == ISDN_P_B_T30_FAX) &&
619 (ch->cmd == PCTRL_CMD_FTH)) {
620 if (count > 1) {
621 if ((ptr[0] == 0xff) && (ptr[1] == 0x13)) {
622 /* last frame */
623 test_and_set_bit(FLG_LASTDATA,
624 &ch->bch.Flags);
625 pr_debug("%s: set LASTDATA\n",
626 ch->is->name);
627 if (msb == HDLC_FED)
628 test_and_set_bit(FLG_DLEETX,
629 &ch->bch.Flags);
630 }
631 }
632 }
633 msb |= HDLC_FST;
634 }
635 ch->bch.tx_idx += count;
636 switch (ch->bch.state) {
637 case ISDN_P_NONE:
638 pr_info("%s: wrong protocol 0\n", __func__);
639 break;
640 case ISDN_P_B_RAW:
641 case ISDN_P_B_L2DTMF:
642 case ISDN_P_B_MODEM_ASYNC:
643 send_mbox(ch->is, SET_DPS(ch->dpath) | ISAR_HIS_SDATA,
644 0, count, ptr);
645 break;
646 case ISDN_P_B_HDLC:
647 send_mbox(ch->is, SET_DPS(ch->dpath) | ISAR_HIS_SDATA,
648 msb, count, ptr);
649 break;
650 case ISDN_P_B_T30_FAX:
651 if (ch->state != STFAX_ACTIV)
652 pr_debug("%s: not ACTIV\n", ch->is->name);
653 else if (ch->cmd == PCTRL_CMD_FTH)
654 send_mbox(ch->is, SET_DPS(ch->dpath) | ISAR_HIS_SDATA,
655 msb, count, ptr);
656 else if (ch->cmd == PCTRL_CMD_FTM)
657 send_mbox(ch->is, SET_DPS(ch->dpath) | ISAR_HIS_SDATA,
658 0, count, ptr);
659 else
660 pr_debug("%s: not FTH/FTM\n", ch->is->name);
661 break;
662 default:
663 pr_info("%s: protocol(%x) error\n",
664 __func__, ch->bch.state);
665 break;
666 }
667}
668
669static inline struct isar_ch *
670sel_bch_isar(struct isar_hw *isar, u8 dpath)
671{
672 struct isar_ch *base = &isar->ch[0];
673
674 if ((!dpath) || (dpath > 2))
675 return NULL;
676 if (base->dpath == dpath)
677 return base;
678 base++;
679 if (base->dpath == dpath)
680 return base;
681 return NULL;
682}
683
684static void
685send_next(struct isar_ch *ch)
686{
687 pr_debug("%s: %s ch%d tx_skb %p tx_idx %d\n",
688 ch->is->name, __func__, ch->bch.nr,
689 ch->bch.tx_skb, ch->bch.tx_idx);
690 if (ch->bch.state == ISDN_P_B_T30_FAX) {
691 if (ch->cmd == PCTRL_CMD_FTH) {
692 if (test_bit(FLG_LASTDATA, &ch->bch.Flags)) {
693 pr_debug("set NMD_DATA\n");
694 test_and_set_bit(FLG_NMD_DATA, &ch->bch.Flags);
695 }
696 } else if (ch->cmd == PCTRL_CMD_FTM) {
697 if (test_bit(FLG_DLEETX, &ch->bch.Flags)) {
698 test_and_set_bit(FLG_LASTDATA, &ch->bch.Flags);
699 test_and_set_bit(FLG_NMD_DATA, &ch->bch.Flags);
700 }
701 }
702 }
703 if (ch->bch.tx_skb) {
704 /* send confirm, on trans, free on hdlc. */
705 if (test_bit(FLG_TRANSPARENT, &ch->bch.Flags))
706 confirm_Bsend(&ch->bch);
707 dev_kfree_skb(ch->bch.tx_skb);
708 }
709 if (get_next_bframe(&ch->bch))
710 isar_fill_fifo(ch);
711 else {
712 if (test_and_clear_bit(FLG_DLEETX, &ch->bch.Flags)) {
713 if (test_and_clear_bit(FLG_LASTDATA,
714 &ch->bch.Flags)) {
715 if (test_and_clear_bit(FLG_NMD_DATA,
716 &ch->bch.Flags)) {
717 u8 zd = 0;
718 send_mbox(ch->is, SET_DPS(ch->dpath) |
719 ISAR_HIS_SDATA, 0x01, 1, &zd);
720 }
721 test_and_set_bit(FLG_LL_OK, &ch->bch.Flags);
722 } else {
723 deliver_status(ch, HW_MOD_CONNECT);
724 }
725 }
726 }
727}
728
729static void
730check_send(struct isar_hw *isar, u8 rdm)
731{
732 struct isar_ch *ch;
733
734 pr_debug("%s: rdm %x\n", isar->name, rdm);
735 if (rdm & BSTAT_RDM1) {
736 ch = sel_bch_isar(isar, 1);
737 if (ch && test_bit(FLG_ACTIVE, &ch->bch.Flags)) {
738 if (ch->bch.tx_skb && (ch->bch.tx_skb->len >
739 ch->bch.tx_idx))
740 isar_fill_fifo(ch);
741 else
742 send_next(ch);
743 }
744 }
745 if (rdm & BSTAT_RDM2) {
746 ch = sel_bch_isar(isar, 2);
747 if (ch && test_bit(FLG_ACTIVE, &ch->bch.Flags)) {
748 if (ch->bch.tx_skb && (ch->bch.tx_skb->len >
749 ch->bch.tx_idx))
750 isar_fill_fifo(ch);
751 else
752 send_next(ch);
753 }
754 }
755}
756
757const char *dmril[] = {"NO SPEED", "1200/75", "NODEF2", "75/1200", "NODEF4",
758 "300", "600", "1200", "2400", "4800", "7200",
759 "9600nt", "9600t", "12000", "14400", "WRONG"};
760const char *dmrim[] = {"NO MOD", "NO DEF", "V32/V32b", "V22", "V21",
761 "Bell103", "V23", "Bell202", "V17", "V29", "V27ter"};
762
763static void
764isar_pump_status_rsp(struct isar_ch *ch) {
765 u8 ril = ch->is->buf[0];
766 u8 rim;
767
768 if (!test_and_clear_bit(ISAR_RATE_REQ, &ch->is->Flags))
769 return;
770 if (ril > 14) {
771 pr_info("%s: wrong pstrsp ril=%d\n", ch->is->name, ril);
772 ril = 15;
773 }
774 switch (ch->is->buf[1]) {
775 case 0:
776 rim = 0;
777 break;
778 case 0x20:
779 rim = 2;
780 break;
781 case 0x40:
782 rim = 3;
783 break;
784 case 0x41:
785 rim = 4;
786 break;
787 case 0x51:
788 rim = 5;
789 break;
790 case 0x61:
791 rim = 6;
792 break;
793 case 0x71:
794 rim = 7;
795 break;
796 case 0x82:
797 rim = 8;
798 break;
799 case 0x92:
800 rim = 9;
801 break;
802 case 0xa2:
803 rim = 10;
804 break;
805 default:
806 rim = 1;
807 break;
808 }
809 sprintf(ch->conmsg, "%s %s", dmril[ril], dmrim[rim]);
810 pr_debug("%s: pump strsp %s\n", ch->is->name, ch->conmsg);
811}
812
813static void
814isar_pump_statev_modem(struct isar_ch *ch, u8 devt) {
815 u8 dps = SET_DPS(ch->dpath);
816
817 switch (devt) {
818 case PSEV_10MS_TIMER:
819 pr_debug("%s: pump stev TIMER\n", ch->is->name);
820 break;
821 case PSEV_CON_ON:
822 pr_debug("%s: pump stev CONNECT\n", ch->is->name);
823 deliver_status(ch, HW_MOD_CONNECT);
824 break;
825 case PSEV_CON_OFF:
826 pr_debug("%s: pump stev NO CONNECT\n", ch->is->name);
827 send_mbox(ch->is, dps | ISAR_HIS_PSTREQ, 0, 0, NULL);
828 deliver_status(ch, HW_MOD_NOCARR);
829 break;
830 case PSEV_V24_OFF:
831 pr_debug("%s: pump stev V24 OFF\n", ch->is->name);
832 break;
833 case PSEV_CTS_ON:
834 pr_debug("%s: pump stev CTS ON\n", ch->is->name);
835 break;
836 case PSEV_CTS_OFF:
837 pr_debug("%s pump stev CTS OFF\n", ch->is->name);
838 break;
839 case PSEV_DCD_ON:
840 pr_debug("%s: pump stev CARRIER ON\n", ch->is->name);
841 test_and_set_bit(ISAR_RATE_REQ, &ch->is->Flags);
842 send_mbox(ch->is, dps | ISAR_HIS_PSTREQ, 0, 0, NULL);
843 break;
844 case PSEV_DCD_OFF:
845 pr_debug("%s: pump stev CARRIER OFF\n", ch->is->name);
846 break;
847 case PSEV_DSR_ON:
848 pr_debug("%s: pump stev DSR ON\n", ch->is->name);
849 break;
850 case PSEV_DSR_OFF:
851 pr_debug("%s: pump stev DSR_OFF\n", ch->is->name);
852 break;
853 case PSEV_REM_RET:
854 pr_debug("%s: pump stev REMOTE RETRAIN\n", ch->is->name);
855 break;
856 case PSEV_REM_REN:
857 pr_debug("%s: pump stev REMOTE RENEGOTIATE\n", ch->is->name);
858 break;
859 case PSEV_GSTN_CLR:
860 pr_debug("%s: pump stev GSTN CLEAR\n", ch->is->name);
861 break;
862 default:
863 pr_info("u%s: nknown pump stev %x\n", ch->is->name, devt);
864 break;
865 }
866}
867
868static void
869isar_pump_statev_fax(struct isar_ch *ch, u8 devt) {
870 u8 dps = SET_DPS(ch->dpath);
871 u8 p1;
872
873 switch (devt) {
874 case PSEV_10MS_TIMER:
875 pr_debug("%s: pump stev TIMER\n", ch->is->name);
876 break;
877 case PSEV_RSP_READY:
878 pr_debug("%s: pump stev RSP_READY\n", ch->is->name);
879 ch->state = STFAX_READY;
880 deliver_status(ch, HW_MOD_READY);
881#ifdef AUTOCON
882 if (test_bit(BC_FLG_ORIG, &ch->bch.Flags))
883 isar_pump_cmd(bch, HW_MOD_FRH, 3);
884 else
885 isar_pump_cmd(bch, HW_MOD_FTH, 3);
886#endif
887 break;
888 case PSEV_LINE_TX_H:
889 if (ch->state == STFAX_LINE) {
890 pr_debug("%s: pump stev LINE_TX_H\n", ch->is->name);
891 ch->state = STFAX_CONT;
892 send_mbox(ch->is, dps | ISAR_HIS_PUMPCTRL,
893 PCTRL_CMD_CONT, 0, NULL);
894 } else {
895 pr_debug("%s: pump stev LINE_TX_H wrong st %x\n",
896 ch->is->name, ch->state);
897 }
898 break;
899 case PSEV_LINE_RX_H:
900 if (ch->state == STFAX_LINE) {
901 pr_debug("%s: pump stev LINE_RX_H\n", ch->is->name);
902 ch->state = STFAX_CONT;
903 send_mbox(ch->is, dps | ISAR_HIS_PUMPCTRL,
904 PCTRL_CMD_CONT, 0, NULL);
905 } else {
906 pr_debug("%s: pump stev LINE_RX_H wrong st %x\n",
907 ch->is->name, ch->state);
908 }
909 break;
910 case PSEV_LINE_TX_B:
911 if (ch->state == STFAX_LINE) {
912 pr_debug("%s: pump stev LINE_TX_B\n", ch->is->name);
913 ch->state = STFAX_CONT;
914 send_mbox(ch->is, dps | ISAR_HIS_PUMPCTRL,
915 PCTRL_CMD_CONT, 0, NULL);
916 } else {
917 pr_debug("%s: pump stev LINE_TX_B wrong st %x\n",
918 ch->is->name, ch->state);
919 }
920 break;
921 case PSEV_LINE_RX_B:
922 if (ch->state == STFAX_LINE) {
923 pr_debug("%s: pump stev LINE_RX_B\n", ch->is->name);
924 ch->state = STFAX_CONT;
925 send_mbox(ch->is, dps | ISAR_HIS_PUMPCTRL,
926 PCTRL_CMD_CONT, 0, NULL);
927 } else {
928 pr_debug("%s: pump stev LINE_RX_B wrong st %x\n",
929 ch->is->name, ch->state);
930 }
931 break;
932 case PSEV_RSP_CONN:
933 if (ch->state == STFAX_CONT) {
934 pr_debug("%s: pump stev RSP_CONN\n", ch->is->name);
935 ch->state = STFAX_ACTIV;
936 test_and_set_bit(ISAR_RATE_REQ, &ch->is->Flags);
937 send_mbox(ch->is, dps | ISAR_HIS_PSTREQ, 0, 0, NULL);
938 if (ch->cmd == PCTRL_CMD_FTH) {
939 int delay = (ch->mod == 3) ? 1000 : 200;
940 /* 1s (200 ms) Flags before data */
941 if (test_and_set_bit(FLG_FTI_RUN,
942 &ch->bch.Flags))
943 del_timer(&ch->ftimer);
944 ch->ftimer.expires =
945 jiffies + ((delay * HZ)/1000);
946 test_and_set_bit(FLG_LL_CONN,
947 &ch->bch.Flags);
948 add_timer(&ch->ftimer);
949 } else {
950 deliver_status(ch, HW_MOD_CONNECT);
951 }
952 } else {
953 pr_debug("%s: pump stev RSP_CONN wrong st %x\n",
954 ch->is->name, ch->state);
955 }
956 break;
957 case PSEV_FLAGS_DET:
958 pr_debug("%s: pump stev FLAGS_DET\n", ch->is->name);
959 break;
960 case PSEV_RSP_DISC:
961 pr_debug("%s: pump stev RSP_DISC state(%d)\n",
962 ch->is->name, ch->state);
963 if (ch->state == STFAX_ESCAPE) {
964 p1 = 5;
965 switch (ch->newcmd) {
966 case 0:
967 ch->state = STFAX_READY;
968 break;
969 case PCTRL_CMD_FTM:
970 p1 = 2;
971 case PCTRL_CMD_FTH:
972 send_mbox(ch->is, dps | ISAR_HIS_PUMPCTRL,
973 PCTRL_CMD_SILON, 1, &p1);
974 ch->state = STFAX_SILDET;
975 break;
976 case PCTRL_CMD_FRH:
977 case PCTRL_CMD_FRM:
978 ch->mod = ch->newmod;
979 p1 = ch->newmod;
980 ch->newmod = 0;
981 ch->cmd = ch->newcmd;
982 ch->newcmd = 0;
983 send_mbox(ch->is, dps | ISAR_HIS_PUMPCTRL,
984 ch->cmd, 1, &p1);
985 ch->state = STFAX_LINE;
986 ch->try_mod = 3;
987 break;
988 default:
989 pr_debug("%s: RSP_DISC unknown newcmd %x\n",
990 ch->is->name, ch->newcmd);
991 break;
992 }
993 } else if (ch->state == STFAX_ACTIV) {
994 if (test_and_clear_bit(FLG_LL_OK, &ch->bch.Flags))
995 deliver_status(ch, HW_MOD_OK);
996 else if (ch->cmd == PCTRL_CMD_FRM)
997 deliver_status(ch, HW_MOD_NOCARR);
998 else
999 deliver_status(ch, HW_MOD_FCERROR);
1000 ch->state = STFAX_READY;
1001 } else if (ch->state != STFAX_SILDET) {
1002 /* ignore in STFAX_SILDET */
1003 ch->state = STFAX_READY;
1004 deliver_status(ch, HW_MOD_FCERROR);
1005 }
1006 break;
1007 case PSEV_RSP_SILDET:
1008 pr_debug("%s: pump stev RSP_SILDET\n", ch->is->name);
1009 if (ch->state == STFAX_SILDET) {
1010 ch->mod = ch->newmod;
1011 p1 = ch->newmod;
1012 ch->newmod = 0;
1013 ch->cmd = ch->newcmd;
1014 ch->newcmd = 0;
1015 send_mbox(ch->is, dps | ISAR_HIS_PUMPCTRL,
1016 ch->cmd, 1, &p1);
1017 ch->state = STFAX_LINE;
1018 ch->try_mod = 3;
1019 }
1020 break;
1021 case PSEV_RSP_SILOFF:
1022 pr_debug("%s: pump stev RSP_SILOFF\n", ch->is->name);
1023 break;
1024 case PSEV_RSP_FCERR:
1025 if (ch->state == STFAX_LINE) {
1026 pr_debug("%s: pump stev RSP_FCERR try %d\n",
1027 ch->is->name, ch->try_mod);
1028 if (ch->try_mod--) {
1029 send_mbox(ch->is, dps | ISAR_HIS_PUMPCTRL,
1030 ch->cmd, 1, &ch->mod);
1031 break;
1032 }
1033 }
1034 pr_debug("%s: pump stev RSP_FCERR\n", ch->is->name);
1035 ch->state = STFAX_ESCAPE;
1036 send_mbox(ch->is, dps | ISAR_HIS_PUMPCTRL, PCTRL_CMD_ESC,
1037 0, NULL);
1038 deliver_status(ch, HW_MOD_FCERROR);
1039 break;
1040 default:
1041 break;
1042 }
1043}
1044
1045void
1046mISDNisar_irq(struct isar_hw *isar)
1047{
1048 struct isar_ch *ch;
1049
1050 get_irq_infos(isar);
1051 switch (isar->iis & ISAR_IIS_MSCMSD) {
1052 case ISAR_IIS_RDATA:
1053 ch = sel_bch_isar(isar, isar->iis >> 6);
1054 if (ch)
1055 isar_rcv_frame(ch);
1056 else {
1057 pr_debug("%s: ISAR spurious IIS_RDATA %x/%x/%x\n",
1058 isar->name, isar->iis, isar->cmsb,
1059 isar->clsb);
1060 isar->write_reg(isar->hw, ISAR_IIA, 0);
1061 }
1062 break;
1063 case ISAR_IIS_GSTEV:
1064 isar->write_reg(isar->hw, ISAR_IIA, 0);
1065 isar->bstat |= isar->cmsb;
1066 check_send(isar, isar->cmsb);
1067 break;
1068 case ISAR_IIS_BSTEV:
1069#ifdef ERROR_STATISTIC
1070 ch = sel_bch_isar(isar, isar->iis >> 6);
1071 if (ch) {
1072 if (isar->cmsb == BSTEV_TBO)
1073 ch->bch.err_tx++;
1074 if (isar->cmsb == BSTEV_RBO)
1075 ch->bch.err_rdo++;
1076 }
1077#endif
1078 pr_debug("%s: Buffer STEV dpath%d msb(%x)\n",
1079 isar->name, isar->iis>>6, isar->cmsb);
1080 isar->write_reg(isar->hw, ISAR_IIA, 0);
1081 break;
1082 case ISAR_IIS_PSTEV:
1083 ch = sel_bch_isar(isar, isar->iis >> 6);
1084 if (ch) {
1085 rcv_mbox(isar, NULL);
1086 if (ch->bch.state == ISDN_P_B_MODEM_ASYNC)
1087 isar_pump_statev_modem(ch, isar->cmsb);
1088 else if (ch->bch.state == ISDN_P_B_T30_FAX)
1089 isar_pump_statev_fax(ch, isar->cmsb);
1090 else if (ch->bch.state == ISDN_P_B_RAW) {
1091 int tt;
1092 tt = isar->cmsb | 0x30;
1093 if (tt == 0x3e)
1094 tt = '*';
1095 else if (tt == 0x3f)
1096 tt = '#';
1097 else if (tt > '9')
1098 tt += 7;
1099 tt |= DTMF_TONE_VAL;
1100 _queue_data(&ch->bch.ch, PH_CONTROL_IND,
1101 MISDN_ID_ANY, sizeof(tt), &tt,
1102 GFP_ATOMIC);
1103 } else
1104 pr_debug("%s: ISAR IIS_PSTEV pm %d sta %x\n",
1105 isar->name, ch->bch.state,
1106 isar->cmsb);
1107 } else {
1108 pr_debug("%s: ISAR spurious IIS_PSTEV %x/%x/%x\n",
1109 isar->name, isar->iis, isar->cmsb,
1110 isar->clsb);
1111 isar->write_reg(isar->hw, ISAR_IIA, 0);
1112 }
1113 break;
1114 case ISAR_IIS_PSTRSP:
1115 ch = sel_bch_isar(isar, isar->iis >> 6);
1116 if (ch) {
1117 rcv_mbox(isar, NULL);
1118 isar_pump_status_rsp(ch);
1119 } else {
1120 pr_debug("%s: ISAR spurious IIS_PSTRSP %x/%x/%x\n",
1121 isar->name, isar->iis, isar->cmsb,
1122 isar->clsb);
1123 isar->write_reg(isar->hw, ISAR_IIA, 0);
1124 }
1125 break;
1126 case ISAR_IIS_DIAG:
1127 case ISAR_IIS_BSTRSP:
1128 case ISAR_IIS_IOM2RSP:
1129 rcv_mbox(isar, NULL);
1130 break;
1131 case ISAR_IIS_INVMSG:
1132 rcv_mbox(isar, NULL);
1133 pr_debug("%s: invalid msg his:%x\n", isar->name, isar->cmsb);
1134 break;
1135 default:
1136 rcv_mbox(isar, NULL);
1137 pr_debug("%s: unhandled msg iis(%x) ctrl(%x/%x)\n",
1138 isar->name, isar->iis, isar->cmsb, isar->clsb);
1139 break;
1140 }
1141}
1142EXPORT_SYMBOL(mISDNisar_irq);
1143
1144static void
1145ftimer_handler(unsigned long data)
1146{
1147 struct isar_ch *ch = (struct isar_ch *)data;
1148
1149 pr_debug("%s: ftimer flags %lx\n", ch->is->name, ch->bch.Flags);
1150 test_and_clear_bit(FLG_FTI_RUN, &ch->bch.Flags);
1151 if (test_and_clear_bit(FLG_LL_CONN, &ch->bch.Flags))
1152 deliver_status(ch, HW_MOD_CONNECT);
1153}
1154
1155static void
1156setup_pump(struct isar_ch *ch) {
1157 u8 dps = SET_DPS(ch->dpath);
1158 u8 ctrl, param[6];
1159
1160 switch (ch->bch.state) {
1161 case ISDN_P_NONE:
1162 case ISDN_P_B_RAW:
1163 case ISDN_P_B_HDLC:
1164 send_mbox(ch->is, dps | ISAR_HIS_PUMPCFG, PMOD_BYPASS, 0, NULL);
1165 break;
1166 case ISDN_P_B_L2DTMF:
1167 if (test_bit(FLG_DTMFSEND, &ch->bch.Flags)) {
1168 param[0] = 5; /* TOA 5 db */
1169 send_mbox(ch->is, dps | ISAR_HIS_PUMPCFG,
1170 PMOD_DTMF_TRANS, 1, param);
1171 } else {
1172 param[0] = 40; /* REL -46 dbm */
1173 send_mbox(ch->is, dps | ISAR_HIS_PUMPCFG,
1174 PMOD_DTMF, 1, param);
1175 }
1176 case ISDN_P_B_MODEM_ASYNC:
1177 ctrl = PMOD_DATAMODEM;
1178 if (test_bit(FLG_ORIGIN, &ch->bch.Flags)) {
1179 ctrl |= PCTRL_ORIG;
1180 param[5] = PV32P6_CTN;
1181 } else {
1182 param[5] = PV32P6_ATN;
1183 }
1184 param[0] = 6; /* 6 db */
1185 param[1] = PV32P2_V23R | PV32P2_V22A | PV32P2_V22B |
1186 PV32P2_V22C | PV32P2_V21 | PV32P2_BEL;
1187 param[2] = PV32P3_AMOD | PV32P3_V32B | PV32P3_V23B;
1188 param[3] = PV32P4_UT144;
1189 param[4] = PV32P5_UT144;
1190 send_mbox(ch->is, dps | ISAR_HIS_PUMPCFG, ctrl, 6, param);
1191 break;
1192 case ISDN_P_B_T30_FAX:
1193 ctrl = PMOD_FAX;
1194 if (test_bit(FLG_ORIGIN, &ch->bch.Flags)) {
1195 ctrl |= PCTRL_ORIG;
1196 param[1] = PFAXP2_CTN;
1197 } else {
1198 param[1] = PFAXP2_ATN;
1199 }
1200 param[0] = 6; /* 6 db */
1201 send_mbox(ch->is, dps | ISAR_HIS_PUMPCFG, ctrl, 2, param);
1202 ch->state = STFAX_NULL;
1203 ch->newcmd = 0;
1204 ch->newmod = 0;
1205 test_and_set_bit(FLG_FTI_RUN, &ch->bch.Flags);
1206 break;
1207 }
1208 udelay(1000);
1209 send_mbox(ch->is, dps | ISAR_HIS_PSTREQ, 0, 0, NULL);
1210 udelay(1000);
1211}
1212
1213static void
1214setup_sart(struct isar_ch *ch) {
1215 u8 dps = SET_DPS(ch->dpath);
1216 u8 ctrl, param[2] = {0, 0};
1217
1218 switch (ch->bch.state) {
1219 case ISDN_P_NONE:
1220 send_mbox(ch->is, dps | ISAR_HIS_SARTCFG, SMODE_DISABLE,
1221 0, NULL);
1222 break;
1223 case ISDN_P_B_RAW:
1224 case ISDN_P_B_L2DTMF:
1225 send_mbox(ch->is, dps | ISAR_HIS_SARTCFG, SMODE_BINARY,
1226 2, param);
1227 break;
1228 case ISDN_P_B_HDLC:
1229 case ISDN_P_B_T30_FAX:
1230 send_mbox(ch->is, dps | ISAR_HIS_SARTCFG, SMODE_HDLC,
1231 1, param);
1232 break;
1233 case ISDN_P_B_MODEM_ASYNC:
1234 ctrl = SMODE_V14 | SCTRL_HDMC_BOTH;
1235 param[0] = S_P1_CHS_8;
1236 param[1] = S_P2_BFT_DEF;
1237 send_mbox(ch->is, dps | ISAR_HIS_SARTCFG, ctrl, 2, param);
1238 break;
1239 }
1240 udelay(1000);
1241 send_mbox(ch->is, dps | ISAR_HIS_BSTREQ, 0, 0, NULL);
1242 udelay(1000);
1243}
1244
1245static void
1246setup_iom2(struct isar_ch *ch) {
1247 u8 dps = SET_DPS(ch->dpath);
1248 u8 cmsb = IOM_CTRL_ENA, msg[5] = {IOM_P1_TXD, 0, 0, 0, 0};
1249
1250 if (ch->bch.nr == 2) {
1251 msg[1] = 1;
1252 msg[3] = 1;
1253 }
1254 switch (ch->bch.state) {
1255 case ISDN_P_NONE:
1256 cmsb = 0;
1257 /* dummy slot */
1258 msg[1] = ch->dpath + 2;
1259 msg[3] = ch->dpath + 2;
1260 break;
1261 case ISDN_P_B_RAW:
1262 case ISDN_P_B_HDLC:
1263 break;
1264 case ISDN_P_B_MODEM_ASYNC:
1265 case ISDN_P_B_T30_FAX:
1266 cmsb |= IOM_CTRL_RCV;
1267 case ISDN_P_B_L2DTMF:
1268 if (test_bit(FLG_DTMFSEND, &ch->bch.Flags))
1269 cmsb |= IOM_CTRL_RCV;
1270 cmsb |= IOM_CTRL_ALAW;
1271 break;
1272 }
1273 send_mbox(ch->is, dps | ISAR_HIS_IOM2CFG, cmsb, 5, msg);
1274 udelay(1000);
1275 send_mbox(ch->is, dps | ISAR_HIS_IOM2REQ, 0, 0, NULL);
1276 udelay(1000);
1277}
1278
1279static int
1280modeisar(struct isar_ch *ch, u32 bprotocol)
1281{
1282 /* Here we are selecting the best datapath for requested protocol */
1283 if (ch->bch.state == ISDN_P_NONE) { /* New Setup */
1284 switch (bprotocol) {
1285 case ISDN_P_NONE: /* init */
1286 if (!ch->dpath)
1287 /* no init for dpath 0 */
1288 return 0;
1289 test_and_clear_bit(FLG_HDLC, &ch->bch.Flags);
1290 test_and_clear_bit(FLG_TRANSPARENT, &ch->bch.Flags);
1291 break;
1292 case ISDN_P_B_RAW:
1293 case ISDN_P_B_HDLC:
1294 /* best is datapath 2 */
1295 if (!test_and_set_bit(ISAR_DP2_USE, &ch->is->Flags))
1296 ch->dpath = 2;
1297 else if (!test_and_set_bit(ISAR_DP1_USE,
1298 &ch->is->Flags))
1299 ch->dpath = 1;
1300 else {
1301 pr_info("modeisar both pathes in use\n");
1302 return -EBUSY;
1303 }
1304 if (bprotocol == ISDN_P_B_HDLC)
1305 test_and_set_bit(FLG_HDLC, &ch->bch.Flags);
1306 else
1307 test_and_set_bit(FLG_TRANSPARENT,
1308 &ch->bch.Flags);
1309 break;
1310 case ISDN_P_B_MODEM_ASYNC:
1311 case ISDN_P_B_T30_FAX:
1312 case ISDN_P_B_L2DTMF:
1313 /* only datapath 1 */
1314 if (!test_and_set_bit(ISAR_DP1_USE, &ch->is->Flags))
1315 ch->dpath = 1;
1316 else {
1317 pr_info("%s: ISAR modeisar analog functions"
1318 "only with DP1\n", ch->is->name);
1319 return -EBUSY;
1320 }
1321 break;
1322 default:
1323 pr_info("%s: protocol not known %x\n", ch->is->name,
1324 bprotocol);
1325 return -ENOPROTOOPT;
1326 }
1327 }
1328 pr_debug("%s: ISAR ch%d dp%d protocol %x->%x\n", ch->is->name,
1329 ch->bch.nr, ch->dpath, ch->bch.state, bprotocol);
1330 ch->bch.state = bprotocol;
1331 setup_pump(ch);
1332 setup_iom2(ch);
1333 setup_sart(ch);
1334 if (ch->bch.state == ISDN_P_NONE) {
1335 /* Clear resources */
1336 if (ch->dpath == 1)
1337 test_and_clear_bit(ISAR_DP1_USE, &ch->is->Flags);
1338 else if (ch->dpath == 2)
1339 test_and_clear_bit(ISAR_DP2_USE, &ch->is->Flags);
1340 ch->dpath = 0;
1341 ch->is->ctrl(ch->is->hw, HW_DEACT_IND, ch->bch.nr);
1342 } else
1343 ch->is->ctrl(ch->is->hw, HW_ACTIVATE_IND, ch->bch.nr);
1344 return 0;
1345}
1346
1347static void
1348isar_pump_cmd(struct isar_ch *ch, u32 cmd, u8 para)
1349{
1350 u8 dps = SET_DPS(ch->dpath);
1351 u8 ctrl = 0, nom = 0, p1 = 0;
1352
1353 pr_debug("%s: isar_pump_cmd %x/%x state(%x)\n",
1354 ch->is->name, cmd, para, ch->bch.state);
1355 switch (cmd) {
1356 case HW_MOD_FTM:
1357 if (ch->state == STFAX_READY) {
1358 p1 = para;
1359 ctrl = PCTRL_CMD_FTM;
1360 nom = 1;
1361 ch->state = STFAX_LINE;
1362 ch->cmd = ctrl;
1363 ch->mod = para;
1364 ch->newmod = 0;
1365 ch->newcmd = 0;
1366 ch->try_mod = 3;
1367 } else if ((ch->state == STFAX_ACTIV) &&
1368 (ch->cmd == PCTRL_CMD_FTM) && (ch->mod == para))
1369 deliver_status(ch, HW_MOD_CONNECT);
1370 else {
1371 ch->newmod = para;
1372 ch->newcmd = PCTRL_CMD_FTM;
1373 nom = 0;
1374 ctrl = PCTRL_CMD_ESC;
1375 ch->state = STFAX_ESCAPE;
1376 }
1377 break;
1378 case HW_MOD_FTH:
1379 if (ch->state == STFAX_READY) {
1380 p1 = para;
1381 ctrl = PCTRL_CMD_FTH;
1382 nom = 1;
1383 ch->state = STFAX_LINE;
1384 ch->cmd = ctrl;
1385 ch->mod = para;
1386 ch->newmod = 0;
1387 ch->newcmd = 0;
1388 ch->try_mod = 3;
1389 } else if ((ch->state == STFAX_ACTIV) &&
1390 (ch->cmd == PCTRL_CMD_FTH) && (ch->mod == para))
1391 deliver_status(ch, HW_MOD_CONNECT);
1392 else {
1393 ch->newmod = para;
1394 ch->newcmd = PCTRL_CMD_FTH;
1395 nom = 0;
1396 ctrl = PCTRL_CMD_ESC;
1397 ch->state = STFAX_ESCAPE;
1398 }
1399 break;
1400 case HW_MOD_FRM:
1401 if (ch->state == STFAX_READY) {
1402 p1 = para;
1403 ctrl = PCTRL_CMD_FRM;
1404 nom = 1;
1405 ch->state = STFAX_LINE;
1406 ch->cmd = ctrl;
1407 ch->mod = para;
1408 ch->newmod = 0;
1409 ch->newcmd = 0;
1410 ch->try_mod = 3;
1411 } else if ((ch->state == STFAX_ACTIV) &&
1412 (ch->cmd == PCTRL_CMD_FRM) && (ch->mod == para))
1413 deliver_status(ch, HW_MOD_CONNECT);
1414 else {
1415 ch->newmod = para;
1416 ch->newcmd = PCTRL_CMD_FRM;
1417 nom = 0;
1418 ctrl = PCTRL_CMD_ESC;
1419 ch->state = STFAX_ESCAPE;
1420 }
1421 break;
1422 case HW_MOD_FRH:
1423 if (ch->state == STFAX_READY) {
1424 p1 = para;
1425 ctrl = PCTRL_CMD_FRH;
1426 nom = 1;
1427 ch->state = STFAX_LINE;
1428 ch->cmd = ctrl;
1429 ch->mod = para;
1430 ch->newmod = 0;
1431 ch->newcmd = 0;
1432 ch->try_mod = 3;
1433 } else if ((ch->state == STFAX_ACTIV) &&
1434 (ch->cmd == PCTRL_CMD_FRH) && (ch->mod == para))
1435 deliver_status(ch, HW_MOD_CONNECT);
1436 else {
1437 ch->newmod = para;
1438 ch->newcmd = PCTRL_CMD_FRH;
1439 nom = 0;
1440 ctrl = PCTRL_CMD_ESC;
1441 ch->state = STFAX_ESCAPE;
1442 }
1443 break;
1444 case PCTRL_CMD_TDTMF:
1445 p1 = para;
1446 nom = 1;
1447 ctrl = PCTRL_CMD_TDTMF;
1448 break;
1449 }
1450 if (ctrl)
1451 send_mbox(ch->is, dps | ISAR_HIS_PUMPCTRL, ctrl, nom, &p1);
1452}
1453
1454static void
1455isar_setup(struct isar_hw *isar)
1456{
1457 u8 msg;
1458 int i;
1459
1460 /* Dpath 1, 2 */
1461 msg = 61;
1462 for (i = 0; i < 2; i++) {
1463 /* Buffer Config */
1464 send_mbox(isar, (i ? ISAR_HIS_DPS2 : ISAR_HIS_DPS1) |
1465 ISAR_HIS_P12CFG, 4, 1, &msg);
1466 isar->ch[i].mml = msg;
1467 isar->ch[i].bch.state = 0;
1468 isar->ch[i].dpath = i + 1;
1469 modeisar(&isar->ch[i], ISDN_P_NONE);
1470 }
1471}
1472
1473static int
1474isar_l2l1(struct mISDNchannel *ch, struct sk_buff *skb)
1475{
1476 struct bchannel *bch = container_of(ch, struct bchannel, ch);
1477 struct isar_ch *ich = container_of(bch, struct isar_ch, bch);
1478 int ret = -EINVAL;
1479 struct mISDNhead *hh = mISDN_HEAD_P(skb);
1480 u32 id, *val;
1481 u_long flags;
1482
1483 switch (hh->prim) {
1484 case PH_DATA_REQ:
1485 spin_lock_irqsave(ich->is->hwlock, flags);
1486 ret = bchannel_senddata(bch, skb);
1487 if (ret > 0) { /* direct TX */
1488 id = hh->id; /* skb can be freed */
1489 ret = 0;
1490 isar_fill_fifo(ich);
1491 spin_unlock_irqrestore(ich->is->hwlock, flags);
1492 if (!test_bit(FLG_TRANSPARENT, &bch->Flags))
1493 queue_ch_frame(ch, PH_DATA_CNF, id, NULL);
1494 } else
1495 spin_unlock_irqrestore(ich->is->hwlock, flags);
1496 return ret;
1497 case PH_ACTIVATE_REQ:
1498 spin_lock_irqsave(ich->is->hwlock, flags);
1499 if (!test_and_set_bit(FLG_ACTIVE, &bch->Flags))
1500 ret = modeisar(ich, ch->protocol);
1501 else
1502 ret = 0;
1503 spin_unlock_irqrestore(ich->is->hwlock, flags);
1504 if (!ret)
1505 _queue_data(ch, PH_ACTIVATE_IND, MISDN_ID_ANY, 0,
1506 NULL, GFP_KERNEL);
1507 break;
1508 case PH_DEACTIVATE_REQ:
1509 spin_lock_irqsave(ich->is->hwlock, flags);
1510 mISDN_clear_bchannel(bch);
1511 modeisar(ich, ISDN_P_NONE);
1512 spin_unlock_irqrestore(ich->is->hwlock, flags);
1513 _queue_data(ch, PH_DEACTIVATE_IND, MISDN_ID_ANY, 0,
1514 NULL, GFP_KERNEL);
1515 ret = 0;
1516 break;
1517 case PH_CONTROL_REQ:
1518 val = (u32 *)skb->data;
1519 pr_debug("%s: PH_CONTROL | REQUEST %x/%x\n", ich->is->name,
1520 hh->id, *val);
1521 if ((hh->id == 0) && ((*val & ~DTMF_TONE_MASK) ==
1522 DTMF_TONE_VAL)) {
1523 if (bch->state == ISDN_P_B_L2DTMF) {
1524 char tt = *val & DTMF_TONE_MASK;
1525
1526 if (tt == '*')
1527 tt = 0x1e;
1528 else if (tt == '#')
1529 tt = 0x1f;
1530 else if (tt > '9')
1531 tt -= 7;
1532 tt &= 0x1f;
1533 spin_lock_irqsave(ich->is->hwlock, flags);
1534 isar_pump_cmd(ich, PCTRL_CMD_TDTMF, tt);
1535 spin_unlock_irqrestore(ich->is->hwlock, flags);
1536 } else {
1537 pr_info("%s: DTMF send wrong protocol %x\n",
1538 __func__, bch->state);
1539 return -EINVAL;
1540 }
1541 } else if ((hh->id == HW_MOD_FRM) || (hh->id == HW_MOD_FRH) ||
1542 (hh->id == HW_MOD_FTM) || (hh->id == HW_MOD_FTH)) {
1543 for (id = 0; id < FAXMODCNT; id++)
1544 if (faxmodulation[id] == *val)
1545 break;
1546 if ((FAXMODCNT > id) &&
1547 test_bit(FLG_INITIALIZED, &bch->Flags)) {
1548 pr_debug("%s: isar: new mod\n", ich->is->name);
1549 isar_pump_cmd(ich, hh->id, *val);
1550 ret = 0;
1551 } else {
1552 pr_info("%s: wrong modulation\n",
1553 ich->is->name);
1554 ret = -EINVAL;
1555 }
1556 } else if (hh->id == HW_MOD_LASTDATA)
1557 test_and_set_bit(FLG_DLEETX, &bch->Flags);
1558 else {
1559 pr_info("%s: unknown PH_CONTROL_REQ %x\n",
1560 ich->is->name, hh->id);
1561 ret = -EINVAL;
1562 }
1563 default:
1564 pr_info("%s: %s unknown prim(%x,%x)\n",
1565 ich->is->name, __func__, hh->prim, hh->id);
1566 ret = -EINVAL;
1567 }
1568 if (!ret)
1569 dev_kfree_skb(skb);
1570 return ret;
1571}
1572
1573static int
1574channel_bctrl(struct bchannel *bch, struct mISDN_ctrl_req *cq)
1575{
1576 int ret = 0;
1577
1578 switch (cq->op) {
1579 case MISDN_CTRL_GETOP:
1580 cq->op = 0;
1581 break;
1582 /* Nothing implemented yet */
1583 case MISDN_CTRL_FILL_EMPTY:
1584 default:
1585 pr_info("%s: unknown Op %x\n", __func__, cq->op);
1586 ret = -EINVAL;
1587 break;
1588 }
1589 return ret;
1590}
1591
1592static int
1593isar_bctrl(struct mISDNchannel *ch, u32 cmd, void *arg)
1594{
1595 struct bchannel *bch = container_of(ch, struct bchannel, ch);
1596 struct isar_ch *ich = container_of(bch, struct isar_ch, bch);
1597 int ret = -EINVAL;
1598 u_long flags;
1599
1600 pr_debug("%s: %s cmd:%x %p\n", ich->is->name, __func__, cmd, arg);
1601 switch (cmd) {
1602 case CLOSE_CHANNEL:
1603 test_and_clear_bit(FLG_OPEN, &bch->Flags);
1604 if (test_bit(FLG_ACTIVE, &bch->Flags)) {
1605 spin_lock_irqsave(ich->is->hwlock, flags);
1606 mISDN_freebchannel(bch);
1607 modeisar(ich, ISDN_P_NONE);
1608 spin_unlock_irqrestore(ich->is->hwlock, flags);
1609 } else {
1610 skb_queue_purge(&bch->rqueue);
1611 bch->rcount = 0;
1612 }
1613 ch->protocol = ISDN_P_NONE;
1614 ch->peer = NULL;
1615 module_put(ich->is->owner);
1616 ret = 0;
1617 break;
1618 case CONTROL_CHANNEL:
1619 ret = channel_bctrl(bch, arg);
1620 break;
1621 default:
1622 pr_info("%s: %s unknown prim(%x)\n",
1623 ich->is->name, __func__, cmd);
1624 }
1625 return ret;
1626}
1627
1628static void
1629free_isar(struct isar_hw *isar)
1630{
1631 modeisar(&isar->ch[0], ISDN_P_NONE);
1632 modeisar(&isar->ch[1], ISDN_P_NONE);
1633 del_timer(&isar->ch[0].ftimer);
1634 del_timer(&isar->ch[1].ftimer);
1635 test_and_clear_bit(FLG_INITIALIZED, &isar->ch[0].bch.Flags);
1636 test_and_clear_bit(FLG_INITIALIZED, &isar->ch[1].bch.Flags);
1637}
1638
1639static int
1640init_isar(struct isar_hw *isar)
1641{
1642 int cnt = 3;
1643
1644 while (cnt--) {
1645 isar->version = ISARVersion(isar);
1646 if (isar->ch[0].bch.debug & DEBUG_HW)
1647 pr_notice("%s: Testing version %d (%d time)\n",
1648 isar->name, isar->version, 3 - cnt);
1649 if (isar->version == 1)
1650 break;
1651 isar->ctrl(isar->hw, HW_RESET_REQ, 0);
1652 }
1653 if (isar->version != 1)
1654 return -EINVAL;
1655 isar->ch[0].ftimer.function = &ftimer_handler;
1656 isar->ch[0].ftimer.data = (long)&isar->ch[0];
1657 init_timer(&isar->ch[0].ftimer);
1658 test_and_set_bit(FLG_INITIALIZED, &isar->ch[0].bch.Flags);
1659 isar->ch[1].ftimer.function = &ftimer_handler;
1660 isar->ch[1].ftimer.data = (long)&isar->ch[1];
1661 init_timer(&isar->ch[1].ftimer);
1662 test_and_set_bit(FLG_INITIALIZED, &isar->ch[1].bch.Flags);
1663 return 0;
1664}
1665
1666static int
1667isar_open(struct isar_hw *isar, struct channel_req *rq)
1668{
1669 struct bchannel *bch;
1670
1671 if (rq->adr.channel > 2)
1672 return -EINVAL;
1673 if (rq->protocol == ISDN_P_NONE)
1674 return -EINVAL;
1675 bch = &isar->ch[rq->adr.channel - 1].bch;
1676 if (test_and_set_bit(FLG_OPEN, &bch->Flags))
1677 return -EBUSY; /* b-channel can be only open once */
1678 test_and_clear_bit(FLG_FILLEMPTY, &bch->Flags);
1679 bch->ch.protocol = rq->protocol;
1680 rq->ch = &bch->ch;
1681 return 0;
1682}
1683
1684u32
1685mISDNisar_init(struct isar_hw *isar, void *hw)
1686{
1687 u32 ret, i;
1688
1689 isar->hw = hw;
1690 for (i = 0; i < 2; i++) {
1691 isar->ch[i].bch.nr = i + 1;
1692 mISDN_initbchannel(&isar->ch[i].bch, MAX_DATA_MEM);
1693 isar->ch[i].bch.ch.nr = i + 1;
1694 isar->ch[i].bch.ch.send = &isar_l2l1;
1695 isar->ch[i].bch.ch.ctrl = isar_bctrl;
1696 isar->ch[i].bch.hw = hw;
1697 isar->ch[i].is = isar;
1698 }
1699
1700 isar->init = &init_isar;
1701 isar->release = &free_isar;
1702 isar->firmware = &load_firmware;
1703 isar->open = &isar_open;
1704
1705 ret = (1 << (ISDN_P_B_RAW & ISDN_P_B_MASK)) |
1706 (1 << (ISDN_P_B_HDLC & ISDN_P_B_MASK)) |
1707 (1 << (ISDN_P_B_L2DTMF & ISDN_P_B_MASK)) |
1708 (1 << (ISDN_P_B_MODEM_ASYNC & ISDN_P_B_MASK)) |
1709 (1 << (ISDN_P_B_T30_FAX & ISDN_P_B_MASK));
1710
1711 return ret;
1712}
1713EXPORT_SYMBOL(mISDNisar_init);
1714
1715static int isar_mod_init(void)
1716{
1717 pr_notice("mISDN: ISAR driver Rev. %s\n", ISAR_REV);
1718 return 0;
1719}
1720
1721static void isar_mod_cleanup(void)
1722{
1723 pr_notice("mISDN: ISAR module unloaded\n");
1724}
1725module_init(isar_mod_init);
1726module_exit(isar_mod_cleanup);
diff --git a/drivers/isdn/hardware/mISDN/speedfax.c b/drivers/isdn/hardware/mISDN/speedfax.c
new file mode 100644
index 00000000000..ff3a4e290da
--- /dev/null
+++ b/drivers/isdn/hardware/mISDN/speedfax.c
@@ -0,0 +1,526 @@
1/*
2 * speedfax.c low level stuff for Sedlbauer Speedfax+ cards
3 * based on the ISAR DSP
4 * Thanks to Sedlbauer AG for informations and HW
5 *
6 * Author Karsten Keil <keil@isdn4linux.de>
7 *
8 * Copyright 2009 by Karsten Keil <keil@isdn4linux.de>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22 *
23 */
24
25#include <linux/module.h>
26#include <linux/pci.h>
27#include <linux/delay.h>
28#include <linux/mISDNhw.h>
29#include <linux/firmware.h>
30#include "ipac.h"
31#include "isar.h"
32
33#define SPEEDFAX_REV "2.0"
34
35#define PCI_SUBVENDOR_SPEEDFAX_PYRAMID 0x51
36#define PCI_SUBVENDOR_SPEEDFAX_PCI 0x54
37#define PCI_SUB_ID_SEDLBAUER 0x01
38
39#define SFAX_PCI_ADDR 0xc8
40#define SFAX_PCI_ISAC 0xd0
41#define SFAX_PCI_ISAR 0xe0
42
43/* TIGER 100 Registers */
44
45#define TIGER_RESET_ADDR 0x00
46#define TIGER_EXTERN_RESET_ON 0x01
47#define TIGER_EXTERN_RESET_OFF 0x00
48#define TIGER_AUX_CTRL 0x02
49#define TIGER_AUX_DATA 0x03
50#define TIGER_AUX_IRQMASK 0x05
51#define TIGER_AUX_STATUS 0x07
52
53/* Tiger AUX BITs */
54#define SFAX_AUX_IOMASK 0xdd /* 1 and 5 are inputs */
55#define SFAX_ISAR_RESET_BIT_OFF 0x00
56#define SFAX_ISAR_RESET_BIT_ON 0x01
57#define SFAX_TIGER_IRQ_BIT 0x02
58#define SFAX_LED1_BIT 0x08
59#define SFAX_LED2_BIT 0x10
60
61#define SFAX_PCI_RESET_ON (SFAX_ISAR_RESET_BIT_ON)
62#define SFAX_PCI_RESET_OFF (SFAX_LED1_BIT | SFAX_LED2_BIT)
63
64static int sfax_cnt;
65static u32 debug;
66static u32 irqloops = 4;
67
68struct sfax_hw {
69 struct list_head list;
70 struct pci_dev *pdev;
71 char name[MISDN_MAX_IDLEN];
72 u32 irq;
73 u32 irqcnt;
74 u32 cfg;
75 struct _ioport p_isac;
76 struct _ioport p_isar;
77 u8 aux_data;
78 spinlock_t lock; /* HW access lock */
79 struct isac_hw isac;
80 struct isar_hw isar;
81};
82
83static LIST_HEAD(Cards);
84static DEFINE_RWLOCK(card_lock); /* protect Cards */
85
86static void
87_set_debug(struct sfax_hw *card)
88{
89 card->isac.dch.debug = debug;
90 card->isar.ch[0].bch.debug = debug;
91 card->isar.ch[1].bch.debug = debug;
92}
93
94static int
95set_debug(const char *val, struct kernel_param *kp)
96{
97 int ret;
98 struct sfax_hw *card;
99
100 ret = param_set_uint(val, kp);
101 if (!ret) {
102 read_lock(&card_lock);
103 list_for_each_entry(card, &Cards, list)
104 _set_debug(card);
105 read_unlock(&card_lock);
106 }
107 return ret;
108}
109
110MODULE_AUTHOR("Karsten Keil");
111MODULE_LICENSE("GPL v2");
112MODULE_VERSION(SPEEDFAX_REV);
113module_param_call(debug, set_debug, param_get_uint, &debug, S_IRUGO | S_IWUSR);
114MODULE_PARM_DESC(debug, "Speedfax debug mask");
115module_param(irqloops, uint, S_IRUGO | S_IWUSR);
116MODULE_PARM_DESC(irqloops, "Speedfax maximal irqloops (default 4)");
117
118IOFUNC_IND(ISAC, sfax_hw, p_isac)
119IOFUNC_IND(ISAR, sfax_hw, p_isar)
120
121static irqreturn_t
122speedfax_irq(int intno, void *dev_id)
123{
124 struct sfax_hw *sf = dev_id;
125 u8 val;
126 int cnt = irqloops;
127
128 spin_lock(&sf->lock);
129 val = inb(sf->cfg + TIGER_AUX_STATUS);
130 if (val & SFAX_TIGER_IRQ_BIT) { /* for us or shared ? */
131 spin_unlock(&sf->lock);
132 return IRQ_NONE; /* shared */
133 }
134 sf->irqcnt++;
135 val = ReadISAR_IND(sf, ISAR_IRQBIT);
136Start_ISAR:
137 if (val & ISAR_IRQSTA)
138 mISDNisar_irq(&sf->isar);
139 val = ReadISAC_IND(sf, ISAC_ISTA);
140 if (val)
141 mISDNisac_irq(&sf->isac, val);
142 val = ReadISAR_IND(sf, ISAR_IRQBIT);
143 if ((val & ISAR_IRQSTA) && cnt--)
144 goto Start_ISAR;
145 if (cnt < irqloops)
146 pr_debug("%s: %d irqloops cpu%d\n", sf->name,
147 irqloops - cnt, smp_processor_id());
148 if (irqloops && !cnt)
149 pr_notice("%s: %d IRQ LOOP cpu%d\n", sf->name,
150 irqloops, smp_processor_id());
151 spin_unlock(&sf->lock);
152 return IRQ_HANDLED;
153}
154
155static void
156enable_hwirq(struct sfax_hw *sf)
157{
158 WriteISAC_IND(sf, ISAC_MASK, 0);
159 WriteISAR_IND(sf, ISAR_IRQBIT, ISAR_IRQMSK);
160 outb(SFAX_TIGER_IRQ_BIT, sf->cfg + TIGER_AUX_IRQMASK);
161}
162
163static void
164disable_hwirq(struct sfax_hw *sf)
165{
166 WriteISAC_IND(sf, ISAC_MASK, 0xFF);
167 WriteISAR_IND(sf, ISAR_IRQBIT, 0);
168 outb(0, sf->cfg + TIGER_AUX_IRQMASK);
169}
170
171static void
172reset_speedfax(struct sfax_hw *sf)
173{
174
175 pr_debug("%s: resetting card\n", sf->name);
176 outb(TIGER_EXTERN_RESET_ON, sf->cfg + TIGER_RESET_ADDR);
177 outb(SFAX_PCI_RESET_ON, sf->cfg + TIGER_AUX_DATA);
178 mdelay(1);
179 outb(TIGER_EXTERN_RESET_OFF, sf->cfg + TIGER_RESET_ADDR);
180 sf->aux_data = SFAX_PCI_RESET_OFF;
181 outb(sf->aux_data, sf->cfg + TIGER_AUX_DATA);
182 mdelay(1);
183}
184
185static int
186sfax_ctrl(struct sfax_hw *sf, u32 cmd, u_long arg)
187{
188 int ret = 0;
189
190 switch (cmd) {
191 case HW_RESET_REQ:
192 reset_speedfax(sf);
193 break;
194 case HW_ACTIVATE_IND:
195 if (arg & 1)
196 sf->aux_data &= ~SFAX_LED1_BIT;
197 if (arg & 2)
198 sf->aux_data &= ~SFAX_LED2_BIT;
199 outb(sf->aux_data, sf->cfg + TIGER_AUX_DATA);
200 break;
201 case HW_DEACT_IND:
202 if (arg & 1)
203 sf->aux_data |= SFAX_LED1_BIT;
204 if (arg & 2)
205 sf->aux_data |= SFAX_LED2_BIT;
206 outb(sf->aux_data, sf->cfg + TIGER_AUX_DATA);
207 break;
208 default:
209 pr_info("%s: %s unknown command %x %lx\n",
210 sf->name, __func__, cmd, arg);
211 ret = -EINVAL;
212 break;
213 }
214 return ret;
215}
216
217static int
218channel_ctrl(struct sfax_hw *sf, struct mISDN_ctrl_req *cq)
219{
220 int ret = 0;
221
222 switch (cq->op) {
223 case MISDN_CTRL_GETOP:
224 cq->op = MISDN_CTRL_LOOP;
225 break;
226 case MISDN_CTRL_LOOP:
227 /* cq->channel: 0 disable, 1 B1 loop 2 B2 loop, 3 both */
228 if (cq->channel < 0 || cq->channel > 3) {
229 ret = -EINVAL;
230 break;
231 }
232 ret = sf->isac.ctrl(&sf->isac, HW_TESTLOOP, cq->channel);
233 break;
234 default:
235 pr_info("%s: unknown Op %x\n", sf->name, cq->op);
236 ret = -EINVAL;
237 break;
238 }
239 return ret;
240}
241
242static int
243sfax_dctrl(struct mISDNchannel *ch, u32 cmd, void *arg)
244{
245 struct mISDNdevice *dev = container_of(ch, struct mISDNdevice, D);
246 struct dchannel *dch = container_of(dev, struct dchannel, dev);
247 struct sfax_hw *sf = dch->hw;
248 struct channel_req *rq;
249 int err = 0;
250
251 pr_debug("%s: cmd:%x %p\n", sf->name, cmd, arg);
252 switch (cmd) {
253 case OPEN_CHANNEL:
254 rq = arg;
255 if (rq->protocol == ISDN_P_TE_S0)
256 err = sf->isac.open(&sf->isac, rq);
257 else
258 err = sf->isar.open(&sf->isar, rq);
259 if (err)
260 break;
261 if (!try_module_get(THIS_MODULE))
262 pr_info("%s: cannot get module\n", sf->name);
263 break;
264 case CLOSE_CHANNEL:
265 pr_debug("%s: dev(%d) close from %p\n", sf->name,
266 dch->dev.id, __builtin_return_address(0));
267 module_put(THIS_MODULE);
268 break;
269 case CONTROL_CHANNEL:
270 err = channel_ctrl(sf, arg);
271 break;
272 default:
273 pr_debug("%s: unknown command %x\n", sf->name, cmd);
274 return -EINVAL;
275 }
276 return err;
277}
278
279static int __devinit
280init_card(struct sfax_hw *sf)
281{
282 int ret, cnt = 3;
283 u_long flags;
284
285 ret = request_irq(sf->irq, speedfax_irq, IRQF_SHARED, sf->name, sf);
286 if (ret) {
287 pr_info("%s: couldn't get interrupt %d\n", sf->name, sf->irq);
288 return ret;
289 }
290 while (cnt--) {
291 spin_lock_irqsave(&sf->lock, flags);
292 ret = sf->isac.init(&sf->isac);
293 if (ret) {
294 spin_unlock_irqrestore(&sf->lock, flags);
295 pr_info("%s: ISAC init failed with %d\n",
296 sf->name, ret);
297 break;
298 }
299 enable_hwirq(sf);
300 /* RESET Receiver and Transmitter */
301 WriteISAC_IND(sf, ISAC_CMDR, 0x41);
302 spin_unlock_irqrestore(&sf->lock, flags);
303 msleep_interruptible(10);
304 if (debug & DEBUG_HW)
305 pr_notice("%s: IRQ %d count %d\n", sf->name,
306 sf->irq, sf->irqcnt);
307 if (!sf->irqcnt) {
308 pr_info("%s: IRQ(%d) got no requests during init %d\n",
309 sf->name, sf->irq, 3 - cnt);
310 } else
311 return 0;
312 }
313 free_irq(sf->irq, sf);
314 return -EIO;
315}
316
317
318static int __devinit
319setup_speedfax(struct sfax_hw *sf)
320{
321 u_long flags;
322
323 if (!request_region(sf->cfg, 256, sf->name)) {
324 pr_info("mISDN: %s config port %x-%x already in use\n",
325 sf->name, sf->cfg, sf->cfg + 255);
326 return -EIO;
327 }
328 outb(0xff, sf->cfg);
329 outb(0, sf->cfg);
330 outb(0xdd, sf->cfg + TIGER_AUX_CTRL);
331 outb(0, sf->cfg + TIGER_AUX_IRQMASK);
332
333 sf->isac.type = IPAC_TYPE_ISAC;
334 sf->p_isac.ale = sf->cfg + SFAX_PCI_ADDR;
335 sf->p_isac.port = sf->cfg + SFAX_PCI_ISAC;
336 sf->p_isar.ale = sf->cfg + SFAX_PCI_ADDR;
337 sf->p_isar.port = sf->cfg + SFAX_PCI_ISAR;
338 ASSIGN_FUNC(IND, ISAC, sf->isac);
339 ASSIGN_FUNC(IND, ISAR, sf->isar);
340 spin_lock_irqsave(&sf->lock, flags);
341 reset_speedfax(sf);
342 disable_hwirq(sf);
343 spin_unlock_irqrestore(&sf->lock, flags);
344 return 0;
345}
346
347static void
348release_card(struct sfax_hw *card) {
349 u_long flags;
350
351 spin_lock_irqsave(&card->lock, flags);
352 disable_hwirq(card);
353 spin_unlock_irqrestore(&card->lock, flags);
354 card->isac.release(&card->isac);
355 free_irq(card->irq, card);
356 card->isar.release(&card->isar);
357 mISDN_unregister_device(&card->isac.dch.dev);
358 release_region(card->cfg, 256);
359 pci_disable_device(card->pdev);
360 pci_set_drvdata(card->pdev, NULL);
361 write_lock_irqsave(&card_lock, flags);
362 list_del(&card->list);
363 write_unlock_irqrestore(&card_lock, flags);
364 kfree(card);
365 sfax_cnt--;
366}
367
368static int __devinit
369setup_instance(struct sfax_hw *card)
370{
371 const struct firmware *firmware;
372 int i, err;
373 u_long flags;
374
375 snprintf(card->name, MISDN_MAX_IDLEN - 1, "Speedfax.%d", sfax_cnt + 1);
376 write_lock_irqsave(&card_lock, flags);
377 list_add_tail(&card->list, &Cards);
378 write_unlock_irqrestore(&card_lock, flags);
379 _set_debug(card);
380 spin_lock_init(&card->lock);
381 card->isac.hwlock = &card->lock;
382 card->isar.hwlock = &card->lock;
383 card->isar.ctrl = (void *)&sfax_ctrl;
384 card->isac.name = card->name;
385 card->isar.name = card->name;
386 card->isar.owner = THIS_MODULE;
387
388 err = request_firmware(&firmware, "isdn/ISAR.BIN", &card->pdev->dev);
389 if (err < 0) {
390 pr_info("%s: firmware request failed %d\n",
391 card->name, err);
392 goto error_fw;
393 }
394 if (debug & DEBUG_HW)
395 pr_notice("%s: got firmware %zu bytes\n",
396 card->name, firmware->size);
397
398 mISDNisac_init(&card->isac, card);
399
400 card->isac.dch.dev.D.ctrl = sfax_dctrl;
401 card->isac.dch.dev.Bprotocols =
402 mISDNisar_init(&card->isar, card);
403 for (i = 0; i < 2; i++) {
404 set_channelmap(i + 1, card->isac.dch.dev.channelmap);
405 list_add(&card->isar.ch[i].bch.ch.list,
406 &card->isac.dch.dev.bchannels);
407 }
408
409 err = setup_speedfax(card);
410 if (err)
411 goto error_setup;
412 err = card->isar.init(&card->isar);
413 if (err)
414 goto error;
415 err = mISDN_register_device(&card->isac.dch.dev,
416 &card->pdev->dev, card->name);
417 if (err)
418 goto error;
419 err = init_card(card);
420 if (err)
421 goto error_init;
422 err = card->isar.firmware(&card->isar, firmware->data, firmware->size);
423 if (!err) {
424 release_firmware(firmware);
425 sfax_cnt++;
426 pr_notice("SpeedFax %d cards installed\n", sfax_cnt);
427 return 0;
428 }
429 disable_hwirq(card);
430 free_irq(card->irq, card);
431error_init:
432 mISDN_unregister_device(&card->isac.dch.dev);
433error:
434 release_region(card->cfg, 256);
435error_setup:
436 card->isac.release(&card->isac);
437 card->isar.release(&card->isar);
438 release_firmware(firmware);
439error_fw:
440 pci_disable_device(card->pdev);
441 write_lock_irqsave(&card_lock, flags);
442 list_del(&card->list);
443 write_unlock_irqrestore(&card_lock, flags);
444 kfree(card);
445 return err;
446}
447
448static int __devinit
449sfaxpci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
450{
451 int err = -ENOMEM;
452 struct sfax_hw *card = kzalloc(sizeof(struct sfax_hw), GFP_KERNEL);
453
454 if (!card) {
455 pr_info("No memory for Speedfax+ PCI\n");
456 return err;
457 }
458 card->pdev = pdev;
459 err = pci_enable_device(pdev);
460 if (err) {
461 kfree(card);
462 return err;
463 }
464
465 pr_notice("mISDN: Speedfax found adapter %s at %s\n",
466 (char *)ent->driver_data, pci_name(pdev));
467
468 card->cfg = pci_resource_start(pdev, 0);
469 card->irq = pdev->irq;
470 pci_set_drvdata(pdev, card);
471 err = setup_instance(card);
472 if (err)
473 pci_set_drvdata(pdev, NULL);
474 return err;
475}
476
477static void __devexit
478sfax_remove_pci(struct pci_dev *pdev)
479{
480 struct sfax_hw *card = pci_get_drvdata(pdev);
481
482 if (card)
483 release_card(card);
484 else
485 pr_debug("%s: drvdata allready removed\n", __func__);
486}
487
488static struct pci_device_id sfaxpci_ids[] __devinitdata = {
489 { PCI_VENDOR_ID_TIGERJET, PCI_DEVICE_ID_TIGERJET_100,
490 PCI_SUBVENDOR_SPEEDFAX_PYRAMID, PCI_SUB_ID_SEDLBAUER,
491 0, 0, (unsigned long) "Pyramid Speedfax + PCI"
492 },
493 { PCI_VENDOR_ID_TIGERJET, PCI_DEVICE_ID_TIGERJET_100,
494 PCI_SUBVENDOR_SPEEDFAX_PCI, PCI_SUB_ID_SEDLBAUER,
495 0, 0, (unsigned long) "Sedlbauer Speedfax + PCI"
496 },
497 { }
498};
499MODULE_DEVICE_TABLE(pci, sfaxpci_ids);
500
501static struct pci_driver sfaxpci_driver = {
502 .name = "speedfax+ pci",
503 .probe = sfaxpci_probe,
504 .remove = __devexit_p(sfax_remove_pci),
505 .id_table = sfaxpci_ids,
506};
507
508static int __init
509Speedfax_init(void)
510{
511 int err;
512
513 pr_notice("Sedlbauer Speedfax+ Driver Rev. %s\n",
514 SPEEDFAX_REV);
515 err = pci_register_driver(&sfaxpci_driver);
516 return err;
517}
518
519static void __exit
520Speedfax_cleanup(void)
521{
522 pci_unregister_driver(&sfaxpci_driver);
523}
524
525module_init(Speedfax_init);
526module_exit(Speedfax_cleanup);
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-27 02:51:01 -0500