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-rw-r--r--drivers/gpu/drm/ati_pcigart.c2
-rw-r--r--drivers/gpu/drm/drm_bufs.c33
-rw-r--r--drivers/gpu/drm/drm_crtc.c6
-rw-r--r--drivers/gpu/drm/drm_crtc_helper.c10
-rw-r--r--drivers/gpu/drm/drm_edid.c840
-rw-r--r--drivers/gpu/drm/drm_edid_modes.h380
-rw-r--r--drivers/gpu/drm/drm_fops.c16
-rw-r--r--drivers/gpu/drm/drm_gem.c2
-rw-r--r--drivers/gpu/drm/drm_ioctl.c1
-rw-r--r--drivers/gpu/drm/i2c/ch7006_drv.c1
-rw-r--r--drivers/gpu/drm/i2c/ch7006_mode.c5
-rw-r--r--drivers/gpu/drm/i2c/ch7006_priv.h1
-rw-r--r--drivers/gpu/drm/i915/i915_gem.c26
-rw-r--r--drivers/gpu/drm/i915/i915_gem_tiling.c4
-rw-r--r--drivers/gpu/drm/i915/intel_display.c15
-rw-r--r--drivers/gpu/drm/i915/intel_fb.c4
-rw-r--r--drivers/gpu/drm/nouveau/Makefile8
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_bios.c194
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_bios.h1
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_bo.c6
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_connector.c19
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_display.c6
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_dp.c87
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_drv.h45
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_encoder.h6
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_fbcon.c2
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_gem.c8
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_hw.c11
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_i2c.c41
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_i2c.h8
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_irq.c6
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_mem.c15
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_reg.h18
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_state.c91
-rw-r--r--drivers/gpu/drm/nouveau/nv04_crtc.c15
-rw-r--r--drivers/gpu/drm/nouveau/nv04_dfp.c73
-rw-r--r--drivers/gpu/drm/nouveau/nv04_tv.c10
-rw-r--r--drivers/gpu/drm/nouveau/nv10_graph.c175
-rw-r--r--drivers/gpu/drm/nouveau/nv30_fb.c24
-rw-r--r--drivers/gpu/drm/nouveau/nv50_crtc.c34
-rw-r--r--drivers/gpu/drm/nouveau/nv50_display.c5
-rw-r--r--drivers/gpu/drm/nouveau/nvc0_fb.c38
-rw-r--r--drivers/gpu/drm/nouveau/nvc0_fifo.c96
-rw-r--r--drivers/gpu/drm/nouveau/nvc0_graph.c75
-rw-r--r--drivers/gpu/drm/nouveau/nvc0_instmem.c232
-rw-r--r--drivers/gpu/drm/radeon/r600_cp.c2
-rw-r--r--drivers/gpu/drm/radeon/r600_cs.c33
-rw-r--r--drivers/gpu/drm/radeon/radeon.h2
-rw-r--r--drivers/gpu/drm/radeon/radeon_atombios.c180
-rw-r--r--drivers/gpu/drm/radeon/radeon_clocks.c81
-rw-r--r--drivers/gpu/drm/radeon/radeon_combios.c388
-rw-r--r--drivers/gpu/drm/radeon/radeon_connectors.c45
-rw-r--r--drivers/gpu/drm/radeon/radeon_cs.c2
-rw-r--r--drivers/gpu/drm/radeon/radeon_cursor.c2
-rw-r--r--drivers/gpu/drm/radeon/radeon_device.c3
-rw-r--r--drivers/gpu/drm/radeon/radeon_display.c34
-rw-r--r--drivers/gpu/drm/radeon/radeon_gem.c12
-rw-r--r--drivers/gpu/drm/radeon/radeon_i2c.c82
-rw-r--r--drivers/gpu/drm/radeon/radeon_kms.c28
-rw-r--r--drivers/gpu/drm/radeon/radeon_mode.h24
-rw-r--r--drivers/gpu/drm/radeon/radeon_pm.c24
-rw-r--r--drivers/gpu/drm/radeon/reg_srcs/rv5151
-rw-r--r--drivers/gpu/drm/vmwgfx/vmwgfx_kms.c8
-rw-r--r--drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c2
64 files changed, 2491 insertions, 1157 deletions
diff --git a/drivers/gpu/drm/ati_pcigart.c b/drivers/gpu/drm/ati_pcigart.c
index 17be051b7aa..1c364924220 100644
--- a/drivers/gpu/drm/ati_pcigart.c
+++ b/drivers/gpu/drm/ati_pcigart.c
@@ -152,7 +152,7 @@ int drm_ati_pcigart_init(struct drm_device *dev, struct drm_ati_pcigart_info *ga
152 /* we need to support large memory configurations */ 152 /* we need to support large memory configurations */
153 entry->busaddr[i] = pci_map_page(dev->pdev, entry->pagelist[i], 153 entry->busaddr[i] = pci_map_page(dev->pdev, entry->pagelist[i],
154 0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); 154 0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
155 if (entry->busaddr[i] == 0) { 155 if (pci_dma_mapping_error(dev->pdev, entry->busaddr[i])) {
156 DRM_ERROR("unable to map PCIGART pages!\n"); 156 DRM_ERROR("unable to map PCIGART pages!\n");
157 drm_ati_pcigart_cleanup(dev, gart_info); 157 drm_ati_pcigart_cleanup(dev, gart_info);
158 address = NULL; 158 address = NULL;
diff --git a/drivers/gpu/drm/drm_bufs.c b/drivers/gpu/drm/drm_bufs.c
index a5c9ce93bbc..3e257a50bf5 100644
--- a/drivers/gpu/drm/drm_bufs.c
+++ b/drivers/gpu/drm/drm_bufs.c
@@ -328,14 +328,13 @@ static int drm_addmap_core(struct drm_device * dev, resource_size_t offset,
328 return -EINVAL; 328 return -EINVAL;
329 } 329 }
330 330
331 list = kmalloc(sizeof(*list), GFP_KERNEL); 331 list = kzalloc(sizeof(*list), GFP_KERNEL);
332 if (!list) { 332 if (!list) {
333 if (map->type == _DRM_REGISTERS) 333 if (map->type == _DRM_REGISTERS)
334 iounmap(map->handle); 334 iounmap(map->handle);
335 kfree(map); 335 kfree(map);
336 return -EINVAL; 336 return -EINVAL;
337 } 337 }
338 memset(list, 0, sizeof(*list));
339 list->map = map; 338 list->map = map;
340 339
341 mutex_lock(&dev->struct_mutex); 340 mutex_lock(&dev->struct_mutex);
@@ -678,13 +677,12 @@ int drm_addbufs_agp(struct drm_device * dev, struct drm_buf_desc * request)
678 return -EINVAL; 677 return -EINVAL;
679 } 678 }
680 679
681 entry->buflist = kmalloc(count * sizeof(*entry->buflist), GFP_KERNEL); 680 entry->buflist = kzalloc(count * sizeof(*entry->buflist), GFP_KERNEL);
682 if (!entry->buflist) { 681 if (!entry->buflist) {
683 mutex_unlock(&dev->struct_mutex); 682 mutex_unlock(&dev->struct_mutex);
684 atomic_dec(&dev->buf_alloc); 683 atomic_dec(&dev->buf_alloc);
685 return -ENOMEM; 684 return -ENOMEM;
686 } 685 }
687 memset(entry->buflist, 0, count * sizeof(*entry->buflist));
688 686
689 entry->buf_size = size; 687 entry->buf_size = size;
690 entry->page_order = page_order; 688 entry->page_order = page_order;
@@ -708,7 +706,7 @@ int drm_addbufs_agp(struct drm_device * dev, struct drm_buf_desc * request)
708 buf->file_priv = NULL; 706 buf->file_priv = NULL;
709 707
710 buf->dev_priv_size = dev->driver->dev_priv_size; 708 buf->dev_priv_size = dev->driver->dev_priv_size;
711 buf->dev_private = kmalloc(buf->dev_priv_size, GFP_KERNEL); 709 buf->dev_private = kzalloc(buf->dev_priv_size, GFP_KERNEL);
712 if (!buf->dev_private) { 710 if (!buf->dev_private) {
713 /* Set count correctly so we free the proper amount. */ 711 /* Set count correctly so we free the proper amount. */
714 entry->buf_count = count; 712 entry->buf_count = count;
@@ -717,7 +715,6 @@ int drm_addbufs_agp(struct drm_device * dev, struct drm_buf_desc * request)
717 atomic_dec(&dev->buf_alloc); 715 atomic_dec(&dev->buf_alloc);
718 return -ENOMEM; 716 return -ENOMEM;
719 } 717 }
720 memset(buf->dev_private, 0, buf->dev_priv_size);
721 718
722 DRM_DEBUG("buffer %d @ %p\n", entry->buf_count, buf->address); 719 DRM_DEBUG("buffer %d @ %p\n", entry->buf_count, buf->address);
723 720
@@ -832,22 +829,20 @@ int drm_addbufs_pci(struct drm_device * dev, struct drm_buf_desc * request)
832 return -EINVAL; 829 return -EINVAL;
833 } 830 }
834 831
835 entry->buflist = kmalloc(count * sizeof(*entry->buflist), GFP_KERNEL); 832 entry->buflist = kzalloc(count * sizeof(*entry->buflist), GFP_KERNEL);
836 if (!entry->buflist) { 833 if (!entry->buflist) {
837 mutex_unlock(&dev->struct_mutex); 834 mutex_unlock(&dev->struct_mutex);
838 atomic_dec(&dev->buf_alloc); 835 atomic_dec(&dev->buf_alloc);
839 return -ENOMEM; 836 return -ENOMEM;
840 } 837 }
841 memset(entry->buflist, 0, count * sizeof(*entry->buflist));
842 838
843 entry->seglist = kmalloc(count * sizeof(*entry->seglist), GFP_KERNEL); 839 entry->seglist = kzalloc(count * sizeof(*entry->seglist), GFP_KERNEL);
844 if (!entry->seglist) { 840 if (!entry->seglist) {
845 kfree(entry->buflist); 841 kfree(entry->buflist);
846 mutex_unlock(&dev->struct_mutex); 842 mutex_unlock(&dev->struct_mutex);
847 atomic_dec(&dev->buf_alloc); 843 atomic_dec(&dev->buf_alloc);
848 return -ENOMEM; 844 return -ENOMEM;
849 } 845 }
850 memset(entry->seglist, 0, count * sizeof(*entry->seglist));
851 846
852 /* Keep the original pagelist until we know all the allocations 847 /* Keep the original pagelist until we know all the allocations
853 * have succeeded 848 * have succeeded
@@ -911,8 +906,8 @@ int drm_addbufs_pci(struct drm_device * dev, struct drm_buf_desc * request)
911 buf->file_priv = NULL; 906 buf->file_priv = NULL;
912 907
913 buf->dev_priv_size = dev->driver->dev_priv_size; 908 buf->dev_priv_size = dev->driver->dev_priv_size;
914 buf->dev_private = kmalloc(buf->dev_priv_size, 909 buf->dev_private = kzalloc(buf->dev_priv_size,
915 GFP_KERNEL); 910 GFP_KERNEL);
916 if (!buf->dev_private) { 911 if (!buf->dev_private) {
917 /* Set count correctly so we free the proper amount. */ 912 /* Set count correctly so we free the proper amount. */
918 entry->buf_count = count; 913 entry->buf_count = count;
@@ -923,7 +918,6 @@ int drm_addbufs_pci(struct drm_device * dev, struct drm_buf_desc * request)
923 atomic_dec(&dev->buf_alloc); 918 atomic_dec(&dev->buf_alloc);
924 return -ENOMEM; 919 return -ENOMEM;
925 } 920 }
926 memset(buf->dev_private, 0, buf->dev_priv_size);
927 921
928 DRM_DEBUG("buffer %d @ %p\n", 922 DRM_DEBUG("buffer %d @ %p\n",
929 entry->buf_count, buf->address); 923 entry->buf_count, buf->address);
@@ -1048,14 +1042,13 @@ static int drm_addbufs_sg(struct drm_device * dev, struct drm_buf_desc * request
1048 return -EINVAL; 1042 return -EINVAL;
1049 } 1043 }
1050 1044
1051 entry->buflist = kmalloc(count * sizeof(*entry->buflist), 1045 entry->buflist = kzalloc(count * sizeof(*entry->buflist),
1052 GFP_KERNEL); 1046 GFP_KERNEL);
1053 if (!entry->buflist) { 1047 if (!entry->buflist) {
1054 mutex_unlock(&dev->struct_mutex); 1048 mutex_unlock(&dev->struct_mutex);
1055 atomic_dec(&dev->buf_alloc); 1049 atomic_dec(&dev->buf_alloc);
1056 return -ENOMEM; 1050 return -ENOMEM;
1057 } 1051 }
1058 memset(entry->buflist, 0, count * sizeof(*entry->buflist));
1059 1052
1060 entry->buf_size = size; 1053 entry->buf_size = size;
1061 entry->page_order = page_order; 1054 entry->page_order = page_order;
@@ -1080,7 +1073,7 @@ static int drm_addbufs_sg(struct drm_device * dev, struct drm_buf_desc * request
1080 buf->file_priv = NULL; 1073 buf->file_priv = NULL;
1081 1074
1082 buf->dev_priv_size = dev->driver->dev_priv_size; 1075 buf->dev_priv_size = dev->driver->dev_priv_size;
1083 buf->dev_private = kmalloc(buf->dev_priv_size, GFP_KERNEL); 1076 buf->dev_private = kzalloc(buf->dev_priv_size, GFP_KERNEL);
1084 if (!buf->dev_private) { 1077 if (!buf->dev_private) {
1085 /* Set count correctly so we free the proper amount. */ 1078 /* Set count correctly so we free the proper amount. */
1086 entry->buf_count = count; 1079 entry->buf_count = count;
@@ -1090,8 +1083,6 @@ static int drm_addbufs_sg(struct drm_device * dev, struct drm_buf_desc * request
1090 return -ENOMEM; 1083 return -ENOMEM;
1091 } 1084 }
1092 1085
1093 memset(buf->dev_private, 0, buf->dev_priv_size);
1094
1095 DRM_DEBUG("buffer %d @ %p\n", entry->buf_count, buf->address); 1086 DRM_DEBUG("buffer %d @ %p\n", entry->buf_count, buf->address);
1096 1087
1097 offset += alignment; 1088 offset += alignment;
@@ -1209,14 +1200,13 @@ static int drm_addbufs_fb(struct drm_device * dev, struct drm_buf_desc * request
1209 return -EINVAL; 1200 return -EINVAL;
1210 } 1201 }
1211 1202
1212 entry->buflist = kmalloc(count * sizeof(*entry->buflist), 1203 entry->buflist = kzalloc(count * sizeof(*entry->buflist),
1213 GFP_KERNEL); 1204 GFP_KERNEL);
1214 if (!entry->buflist) { 1205 if (!entry->buflist) {
1215 mutex_unlock(&dev->struct_mutex); 1206 mutex_unlock(&dev->struct_mutex);
1216 atomic_dec(&dev->buf_alloc); 1207 atomic_dec(&dev->buf_alloc);
1217 return -ENOMEM; 1208 return -ENOMEM;
1218 } 1209 }
1219 memset(entry->buflist, 0, count * sizeof(*entry->buflist));
1220 1210
1221 entry->buf_size = size; 1211 entry->buf_size = size;
1222 entry->page_order = page_order; 1212 entry->page_order = page_order;
@@ -1240,7 +1230,7 @@ static int drm_addbufs_fb(struct drm_device * dev, struct drm_buf_desc * request
1240 buf->file_priv = NULL; 1230 buf->file_priv = NULL;
1241 1231
1242 buf->dev_priv_size = dev->driver->dev_priv_size; 1232 buf->dev_priv_size = dev->driver->dev_priv_size;
1243 buf->dev_private = kmalloc(buf->dev_priv_size, GFP_KERNEL); 1233 buf->dev_private = kzalloc(buf->dev_priv_size, GFP_KERNEL);
1244 if (!buf->dev_private) { 1234 if (!buf->dev_private) {
1245 /* Set count correctly so we free the proper amount. */ 1235 /* Set count correctly so we free the proper amount. */
1246 entry->buf_count = count; 1236 entry->buf_count = count;
@@ -1249,7 +1239,6 @@ static int drm_addbufs_fb(struct drm_device * dev, struct drm_buf_desc * request
1249 atomic_dec(&dev->buf_alloc); 1239 atomic_dec(&dev->buf_alloc);
1250 return -ENOMEM; 1240 return -ENOMEM;
1251 } 1241 }
1252 memset(buf->dev_private, 0, buf->dev_priv_size);
1253 1242
1254 DRM_DEBUG("buffer %d @ %p\n", entry->buf_count, buf->address); 1243 DRM_DEBUG("buffer %d @ %p\n", entry->buf_count, buf->address);
1255 1244
diff --git a/drivers/gpu/drm/drm_crtc.c b/drivers/gpu/drm/drm_crtc.c
index 4c68f76993d..37e0b4fa482 100644
--- a/drivers/gpu/drm/drm_crtc.c
+++ b/drivers/gpu/drm/drm_crtc.c
@@ -1682,9 +1682,9 @@ int drm_mode_addfb(struct drm_device *dev,
1682 /* TODO setup destructor callback */ 1682 /* TODO setup destructor callback */
1683 1683
1684 fb = dev->mode_config.funcs->fb_create(dev, file_priv, r); 1684 fb = dev->mode_config.funcs->fb_create(dev, file_priv, r);
1685 if (!fb) { 1685 if (IS_ERR(fb)) {
1686 DRM_ERROR("could not create framebuffer\n"); 1686 DRM_ERROR("could not create framebuffer\n");
1687 ret = -EINVAL; 1687 ret = PTR_ERR(fb);
1688 goto out; 1688 goto out;
1689 } 1689 }
1690 1690
@@ -2541,7 +2541,7 @@ int drm_mode_gamma_set_ioctl(struct drm_device *dev,
2541 goto out; 2541 goto out;
2542 } 2542 }
2543 2543
2544 crtc->funcs->gamma_set(crtc, r_base, g_base, b_base, crtc->gamma_size); 2544 crtc->funcs->gamma_set(crtc, r_base, g_base, b_base, 0, crtc->gamma_size);
2545 2545
2546out: 2546out:
2547 mutex_unlock(&dev->mode_config.mutex); 2547 mutex_unlock(&dev->mode_config.mutex);
diff --git a/drivers/gpu/drm/drm_crtc_helper.c b/drivers/gpu/drm/drm_crtc_helper.c
index b9e4dbfa053..7e31d434834 100644
--- a/drivers/gpu/drm/drm_crtc_helper.c
+++ b/drivers/gpu/drm/drm_crtc_helper.c
@@ -817,12 +817,12 @@ int drm_helper_resume_force_mode(struct drm_device *dev)
817 if (encoder_funcs->dpms) 817 if (encoder_funcs->dpms)
818 (*encoder_funcs->dpms) (encoder, 818 (*encoder_funcs->dpms) (encoder,
819 drm_helper_choose_encoder_dpms(encoder)); 819 drm_helper_choose_encoder_dpms(encoder));
820
821 crtc_funcs = crtc->helper_private;
822 if (crtc_funcs->dpms)
823 (*crtc_funcs->dpms) (crtc,
824 drm_helper_choose_crtc_dpms(crtc));
825 } 820 }
821
822 crtc_funcs = crtc->helper_private;
823 if (crtc_funcs->dpms)
824 (*crtc_funcs->dpms) (crtc,
825 drm_helper_choose_crtc_dpms(crtc));
826 } 826 }
827 } 827 }
828 /* disable the unused connectors while restoring the modesetting */ 828 /* disable the unused connectors while restoring the modesetting */
diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index dce5c4a97f8..96e96310822 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -33,6 +33,11 @@
33#include <linux/i2c-algo-bit.h> 33#include <linux/i2c-algo-bit.h>
34#include "drmP.h" 34#include "drmP.h"
35#include "drm_edid.h" 35#include "drm_edid.h"
36#include "drm_edid_modes.h"
37
38#define version_greater(edid, maj, min) \
39 (((edid)->version > (maj)) || \
40 ((edid)->version == (maj) && (edid)->revision > (min)))
36 41
37#define EDID_EST_TIMINGS 16 42#define EDID_EST_TIMINGS 16
38#define EDID_STD_TIMINGS 8 43#define EDID_STD_TIMINGS 8
@@ -62,6 +67,13 @@
62/* use +hsync +vsync for detailed mode */ 67/* use +hsync +vsync for detailed mode */
63#define EDID_QUIRK_DETAILED_SYNC_PP (1 << 6) 68#define EDID_QUIRK_DETAILED_SYNC_PP (1 << 6)
64 69
70struct detailed_mode_closure {
71 struct drm_connector *connector;
72 struct edid *edid;
73 bool preferred;
74 u32 quirks;
75 int modes;
76};
65 77
66#define LEVEL_DMT 0 78#define LEVEL_DMT 0
67#define LEVEL_GTF 1 79#define LEVEL_GTF 1
@@ -375,7 +387,6 @@ static u32 edid_get_quirks(struct edid *edid)
375#define MODE_SIZE(m) ((m)->hdisplay * (m)->vdisplay) 387#define MODE_SIZE(m) ((m)->hdisplay * (m)->vdisplay)
376#define MODE_REFRESH_DIFF(m,r) (abs((m)->vrefresh - target_refresh)) 388#define MODE_REFRESH_DIFF(m,r) (abs((m)->vrefresh - target_refresh))
377 389
378
379/** 390/**
380 * edid_fixup_preferred - set preferred modes based on quirk list 391 * edid_fixup_preferred - set preferred modes based on quirk list
381 * @connector: has mode list to fix up 392 * @connector: has mode list to fix up
@@ -422,245 +433,6 @@ static void edid_fixup_preferred(struct drm_connector *connector,
422 preferred_mode->type |= DRM_MODE_TYPE_PREFERRED; 433 preferred_mode->type |= DRM_MODE_TYPE_PREFERRED;
423} 434}
424 435
425/*
426 * Add the Autogenerated from the DMT spec.
427 * This table is copied from xfree86/modes/xf86EdidModes.c.
428 * But the mode with Reduced blank feature is deleted.
429 */
430static struct drm_display_mode drm_dmt_modes[] = {
431 /* 640x350@85Hz */
432 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
433 736, 832, 0, 350, 382, 385, 445, 0,
434 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
435 /* 640x400@85Hz */
436 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
437 736, 832, 0, 400, 401, 404, 445, 0,
438 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
439 /* 720x400@85Hz */
440 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 756,
441 828, 936, 0, 400, 401, 404, 446, 0,
442 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
443 /* 640x480@60Hz */
444 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
445 752, 800, 0, 480, 489, 492, 525, 0,
446 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
447 /* 640x480@72Hz */
448 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
449 704, 832, 0, 480, 489, 492, 520, 0,
450 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
451 /* 640x480@75Hz */
452 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
453 720, 840, 0, 480, 481, 484, 500, 0,
454 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
455 /* 640x480@85Hz */
456 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 36000, 640, 696,
457 752, 832, 0, 480, 481, 484, 509, 0,
458 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
459 /* 800x600@56Hz */
460 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
461 896, 1024, 0, 600, 601, 603, 625, 0,
462 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
463 /* 800x600@60Hz */
464 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
465 968, 1056, 0, 600, 601, 605, 628, 0,
466 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
467 /* 800x600@72Hz */
468 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
469 976, 1040, 0, 600, 637, 643, 666, 0,
470 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
471 /* 800x600@75Hz */
472 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
473 896, 1056, 0, 600, 601, 604, 625, 0,
474 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
475 /* 800x600@85Hz */
476 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 56250, 800, 832,
477 896, 1048, 0, 600, 601, 604, 631, 0,
478 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
479 /* 848x480@60Hz */
480 { DRM_MODE("848x480", DRM_MODE_TYPE_DRIVER, 33750, 848, 864,
481 976, 1088, 0, 480, 486, 494, 517, 0,
482 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
483 /* 1024x768@43Hz, interlace */
484 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032,
485 1208, 1264, 0, 768, 768, 772, 817, 0,
486 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
487 DRM_MODE_FLAG_INTERLACE) },
488 /* 1024x768@60Hz */
489 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
490 1184, 1344, 0, 768, 771, 777, 806, 0,
491 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
492 /* 1024x768@70Hz */
493 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
494 1184, 1328, 0, 768, 771, 777, 806, 0,
495 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
496 /* 1024x768@75Hz */
497 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040,
498 1136, 1312, 0, 768, 769, 772, 800, 0,
499 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
500 /* 1024x768@85Hz */
501 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 94500, 1024, 1072,
502 1168, 1376, 0, 768, 769, 772, 808, 0,
503 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
504 /* 1152x864@75Hz */
505 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
506 1344, 1600, 0, 864, 865, 868, 900, 0,
507 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
508 /* 1280x768@60Hz */
509 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344,
510 1472, 1664, 0, 768, 771, 778, 798, 0,
511 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
512 /* 1280x768@75Hz */
513 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 102250, 1280, 1360,
514 1488, 1696, 0, 768, 771, 778, 805, 0,
515 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
516 /* 1280x768@85Hz */
517 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 117500, 1280, 1360,
518 1496, 1712, 0, 768, 771, 778, 809, 0,
519 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
520 /* 1280x800@60Hz */
521 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352,
522 1480, 1680, 0, 800, 803, 809, 831, 0,
523 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
524 /* 1280x800@75Hz */
525 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 106500, 1280, 1360,
526 1488, 1696, 0, 800, 803, 809, 838, 0,
527 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
528 /* 1280x800@85Hz */
529 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 122500, 1280, 1360,
530 1496, 1712, 0, 800, 803, 809, 843, 0,
531 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
532 /* 1280x960@60Hz */
533 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1376,
534 1488, 1800, 0, 960, 961, 964, 1000, 0,
535 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
536 /* 1280x960@85Hz */
537 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1344,
538 1504, 1728, 0, 960, 961, 964, 1011, 0,
539 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
540 /* 1280x1024@60Hz */
541 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1328,
542 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
543 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
544 /* 1280x1024@75Hz */
545 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
546 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
547 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
548 /* 1280x1024@85Hz */
549 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 157500, 1280, 1344,
550 1504, 1728, 0, 1024, 1025, 1028, 1072, 0,
551 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
552 /* 1360x768@60Hz */
553 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 85500, 1360, 1424,
554 1536, 1792, 0, 768, 771, 777, 795, 0,
555 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
556 /* 1440x1050@60Hz */
557 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488,
558 1632, 1864, 0, 1050, 1053, 1057, 1089, 0,
559 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
560 /* 1440x1050@75Hz */
561 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 156000, 1400, 1504,
562 1648, 1896, 0, 1050, 1053, 1057, 1099, 0,
563 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
564 /* 1440x1050@85Hz */
565 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 179500, 1400, 1504,
566 1656, 1912, 0, 1050, 1053, 1057, 1105, 0,
567 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
568 /* 1440x900@60Hz */
569 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 106500, 1440, 1520,
570 1672, 1904, 0, 900, 903, 909, 934, 0,
571 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
572 /* 1440x900@75Hz */
573 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 136750, 1440, 1536,
574 1688, 1936, 0, 900, 903, 909, 942, 0,
575 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
576 /* 1440x900@85Hz */
577 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 157000, 1440, 1544,
578 1696, 1952, 0, 900, 903, 909, 948, 0,
579 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
580 /* 1600x1200@60Hz */
581 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664,
582 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
583 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
584 /* 1600x1200@65Hz */
585 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 175500, 1600, 1664,
586 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
587 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
588 /* 1600x1200@70Hz */
589 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 189000, 1600, 1664,
590 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
591 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
592 /* 1600x1200@75Hz */
593 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 202500, 1600, 1664,
594 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
595 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
596 /* 1600x1200@85Hz */
597 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 229500, 1600, 1664,
598 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
599 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
600 /* 1680x1050@60Hz */
601 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784,
602 1960, 2240, 0, 1050, 1053, 1059, 1089, 0,
603 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
604 /* 1680x1050@75Hz */
605 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 187000, 1680, 1800,
606 1976, 2272, 0, 1050, 1053, 1059, 1099, 0,
607 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
608 /* 1680x1050@85Hz */
609 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 214750, 1680, 1808,
610 1984, 2288, 0, 1050, 1053, 1059, 1105, 0,
611 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
612 /* 1792x1344@60Hz */
613 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 204750, 1792, 1920,
614 2120, 2448, 0, 1344, 1345, 1348, 1394, 0,
615 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
616 /* 1729x1344@75Hz */
617 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 261000, 1792, 1888,
618 2104, 2456, 0, 1344, 1345, 1348, 1417, 0,
619 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
620 /* 1853x1392@60Hz */
621 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 218250, 1856, 1952,
622 2176, 2528, 0, 1392, 1393, 1396, 1439, 0,
623 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
624 /* 1856x1392@75Hz */
625 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 288000, 1856, 1984,
626 2208, 2560, 0, 1392, 1395, 1399, 1500, 0,
627 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
628 /* 1920x1200@60Hz */
629 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056,
630 2256, 2592, 0, 1200, 1203, 1209, 1245, 0,
631 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
632 /* 1920x1200@75Hz */
633 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 245250, 1920, 2056,
634 2264, 2608, 0, 1200, 1203, 1209, 1255, 0,
635 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
636 /* 1920x1200@85Hz */
637 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 281250, 1920, 2064,
638 2272, 2624, 0, 1200, 1203, 1209, 1262, 0,
639 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
640 /* 1920x1440@60Hz */
641 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 234000, 1920, 2048,
642 2256, 2600, 0, 1440, 1441, 1444, 1500, 0,
643 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
644 /* 1920x1440@75Hz */
645 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2064,
646 2288, 2640, 0, 1440, 1441, 1444, 1500, 0,
647 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
648 /* 2560x1600@60Hz */
649 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 348500, 2560, 2752,
650 3032, 3504, 0, 1600, 1603, 1609, 1658, 0,
651 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
652 /* 2560x1600@75HZ */
653 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 443250, 2560, 2768,
654 3048, 3536, 0, 1600, 1603, 1609, 1672, 0,
655 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
656 /* 2560x1600@85HZ */
657 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 505250, 2560, 2768,
658 3048, 3536, 0, 1600, 1603, 1609, 1682, 0,
659 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
660};
661static const int drm_num_dmt_modes =
662 sizeof(drm_dmt_modes) / sizeof(struct drm_display_mode);
663
664struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev, 436struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev,
665 int hsize, int vsize, int fresh) 437 int hsize, int vsize, int fresh)
666{ 438{
@@ -685,6 +457,46 @@ EXPORT_SYMBOL(drm_mode_find_dmt);
685typedef void detailed_cb(struct detailed_timing *timing, void *closure); 457typedef void detailed_cb(struct detailed_timing *timing, void *closure);
686 458
687static void 459static void
460cea_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure)
461{
462 int i, n = 0;
463 u8 rev = ext[0x01], d = ext[0x02];
464 u8 *det_base = ext + d;
465
466 switch (rev) {
467 case 0:
468 /* can't happen */
469 return;
470 case 1:
471 /* have to infer how many blocks we have, check pixel clock */
472 for (i = 0; i < 6; i++)
473 if (det_base[18*i] || det_base[18*i+1])
474 n++;
475 break;
476 default:
477 /* explicit count */
478 n = min(ext[0x03] & 0x0f, 6);
479 break;
480 }
481
482 for (i = 0; i < n; i++)
483 cb((struct detailed_timing *)(det_base + 18 * i), closure);
484}
485
486static void
487vtb_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure)
488{
489 unsigned int i, n = min((int)ext[0x02], 6);
490 u8 *det_base = ext + 5;
491
492 if (ext[0x01] != 1)
493 return; /* unknown version */
494
495 for (i = 0; i < n; i++)
496 cb((struct detailed_timing *)(det_base + 18 * i), closure);
497}
498
499static void
688drm_for_each_detailed_block(u8 *raw_edid, detailed_cb *cb, void *closure) 500drm_for_each_detailed_block(u8 *raw_edid, detailed_cb *cb, void *closure)
689{ 501{
690 int i; 502 int i;
@@ -696,7 +508,19 @@ drm_for_each_detailed_block(u8 *raw_edid, detailed_cb *cb, void *closure)
696 for (i = 0; i < EDID_DETAILED_TIMINGS; i++) 508 for (i = 0; i < EDID_DETAILED_TIMINGS; i++)
697 cb(&(edid->detailed_timings[i]), closure); 509 cb(&(edid->detailed_timings[i]), closure);
698 510
699 /* XXX extension block walk */ 511 for (i = 1; i <= raw_edid[0x7e]; i++) {
512 u8 *ext = raw_edid + (i * EDID_LENGTH);
513 switch (*ext) {
514 case CEA_EXT:
515 cea_for_each_detailed_block(ext, cb, closure);
516 break;
517 case VTB_EXT:
518 vtb_for_each_detailed_block(ext, cb, closure);
519 break;
520 default:
521 break;
522 }
523 }
700} 524}
701 525
702static void 526static void
@@ -1047,117 +871,6 @@ static struct drm_display_mode *drm_mode_detailed(struct drm_device *dev,
1047 return mode; 871 return mode;
1048} 872}
1049 873
1050/*
1051 * Detailed mode info for the EDID "established modes" data to use.
1052 */
1053static struct drm_display_mode edid_est_modes[] = {
1054 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
1055 968, 1056, 0, 600, 601, 605, 628, 0,
1056 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@60Hz */
1057 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
1058 896, 1024, 0, 600, 601, 603, 625, 0,
1059 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@56Hz */
1060 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
1061 720, 840, 0, 480, 481, 484, 500, 0,
1062 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@75Hz */
1063 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
1064 704, 832, 0, 480, 489, 491, 520, 0,
1065 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@72Hz */
1066 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 30240, 640, 704,
1067 768, 864, 0, 480, 483, 486, 525, 0,
1068 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@67Hz */
1069 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25200, 640, 656,
1070 752, 800, 0, 480, 490, 492, 525, 0,
1071 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@60Hz */
1072 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 738,
1073 846, 900, 0, 400, 421, 423, 449, 0,
1074 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 720x400@88Hz */
1075 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 28320, 720, 738,
1076 846, 900, 0, 400, 412, 414, 449, 0,
1077 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 720x400@70Hz */
1078 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
1079 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
1080 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1280x1024@75Hz */
1081 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78800, 1024, 1040,
1082 1136, 1312, 0, 768, 769, 772, 800, 0,
1083 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1024x768@75Hz */
1084 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
1085 1184, 1328, 0, 768, 771, 777, 806, 0,
1086 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@70Hz */
1087 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
1088 1184, 1344, 0, 768, 771, 777, 806, 0,
1089 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@60Hz */
1090 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER,44900, 1024, 1032,
1091 1208, 1264, 0, 768, 768, 776, 817, 0,
1092 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_INTERLACE) }, /* 1024x768@43Hz */
1093 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 57284, 832, 864,
1094 928, 1152, 0, 624, 625, 628, 667, 0,
1095 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 832x624@75Hz */
1096 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
1097 896, 1056, 0, 600, 601, 604, 625, 0,
1098 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@75Hz */
1099 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
1100 976, 1040, 0, 600, 637, 643, 666, 0,
1101 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@72Hz */
1102 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
1103 1344, 1600, 0, 864, 865, 868, 900, 0,
1104 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1152x864@75Hz */
1105};
1106
1107/**
1108 * add_established_modes - get est. modes from EDID and add them
1109 * @edid: EDID block to scan
1110 *
1111 * Each EDID block contains a bitmap of the supported "established modes" list
1112 * (defined above). Tease them out and add them to the global modes list.
1113 */
1114static int add_established_modes(struct drm_connector *connector, struct edid *edid)
1115{
1116 struct drm_device *dev = connector->dev;
1117 unsigned long est_bits = edid->established_timings.t1 |
1118 (edid->established_timings.t2 << 8) |
1119 ((edid->established_timings.mfg_rsvd & 0x80) << 9);
1120 int i, modes = 0;
1121
1122 for (i = 0; i <= EDID_EST_TIMINGS; i++)
1123 if (est_bits & (1<<i)) {
1124 struct drm_display_mode *newmode;
1125 newmode = drm_mode_duplicate(dev, &edid_est_modes[i]);
1126 if (newmode) {
1127 drm_mode_probed_add(connector, newmode);
1128 modes++;
1129 }
1130 }
1131
1132 return modes;
1133}
1134
1135/**
1136 * add_standard_modes - get std. modes from EDID and add them
1137 * @edid: EDID block to scan
1138 *
1139 * Standard modes can be calculated using the CVT standard. Grab them from
1140 * @edid, calculate them, and add them to the list.
1141 */
1142static int add_standard_modes(struct drm_connector *connector, struct edid *edid)
1143{
1144 int i, modes = 0;
1145
1146 for (i = 0; i < EDID_STD_TIMINGS; i++) {
1147 struct drm_display_mode *newmode;
1148
1149 newmode = drm_mode_std(connector, edid,
1150 &edid->standard_timings[i],
1151 edid->revision);
1152 if (newmode) {
1153 drm_mode_probed_add(connector, newmode);
1154 modes++;
1155 }
1156 }
1157
1158 return modes;
1159}
1160
1161static bool 874static bool
1162mode_is_rb(struct drm_display_mode *mode) 875mode_is_rb(struct drm_display_mode *mode)
1163{ 876{
@@ -1267,113 +980,33 @@ drm_gtf_modes_for_range(struct drm_connector *connector, struct edid *edid,
1267 return modes; 980 return modes;
1268} 981}
1269 982
1270static int drm_cvt_modes(struct drm_connector *connector, 983static void
1271 struct detailed_timing *timing) 984do_inferred_modes(struct detailed_timing *timing, void *c)
1272{ 985{
1273 int i, j, modes = 0; 986 struct detailed_mode_closure *closure = c;
1274 struct drm_display_mode *newmode; 987 struct detailed_non_pixel *data = &timing->data.other_data;
1275 struct drm_device *dev = connector->dev; 988 int gtf = (closure->edid->features & DRM_EDID_FEATURE_DEFAULT_GTF);
1276 struct cvt_timing *cvt;
1277 const int rates[] = { 60, 85, 75, 60, 50 };
1278 const u8 empty[3] = { 0, 0, 0 };
1279
1280 for (i = 0; i < 4; i++) {
1281 int uninitialized_var(width), height;
1282 cvt = &(timing->data.other_data.data.cvt[i]);
1283 989
1284 if (!memcmp(cvt->code, empty, 3)) 990 if (gtf && data->type == EDID_DETAIL_MONITOR_RANGE)
1285 continue; 991 closure->modes += drm_gtf_modes_for_range(closure->connector,
992 closure->edid,
993 timing);
994}
1286 995
1287 height = (cvt->code[0] + ((cvt->code[1] & 0xf0) << 4) + 1) * 2; 996static int
1288 switch (cvt->code[1] & 0x0c) { 997add_inferred_modes(struct drm_connector *connector, struct edid *edid)
1289 case 0x00: 998{
1290 width = height * 4 / 3; 999 struct detailed_mode_closure closure = {
1291 break; 1000 connector, edid, 0, 0, 0
1292 case 0x04: 1001 };
1293 width = height * 16 / 9;
1294 break;
1295 case 0x08:
1296 width = height * 16 / 10;
1297 break;
1298 case 0x0c:
1299 width = height * 15 / 9;
1300 break;
1301 }
1302 1002
1303 for (j = 1; j < 5; j++) { 1003 if (version_greater(edid, 1, 0))
1304 if (cvt->code[2] & (1 << j)) { 1004 drm_for_each_detailed_block((u8 *)edid, do_inferred_modes,
1305 newmode = drm_cvt_mode(dev, width, height, 1005 &closure);
1306 rates[j], j == 0,
1307 false, false);
1308 if (newmode) {
1309 drm_mode_probed_add(connector, newmode);
1310 modes++;
1311 }
1312 }
1313 }
1314 }
1315 1006
1316 return modes; 1007 return closure.modes;
1317} 1008}
1318 1009
1319static const struct {
1320 short w;
1321 short h;
1322 short r;
1323 short rb;
1324} est3_modes[] = {
1325 /* byte 6 */
1326 { 640, 350, 85, 0 },
1327 { 640, 400, 85, 0 },
1328 { 720, 400, 85, 0 },
1329 { 640, 480, 85, 0 },
1330 { 848, 480, 60, 0 },
1331 { 800, 600, 85, 0 },
1332 { 1024, 768, 85, 0 },
1333 { 1152, 864, 75, 0 },
1334 /* byte 7 */
1335 { 1280, 768, 60, 1 },
1336 { 1280, 768, 60, 0 },
1337 { 1280, 768, 75, 0 },
1338 { 1280, 768, 85, 0 },
1339 { 1280, 960, 60, 0 },
1340 { 1280, 960, 85, 0 },
1341 { 1280, 1024, 60, 0 },
1342 { 1280, 1024, 85, 0 },
1343 /* byte 8 */
1344 { 1360, 768, 60, 0 },
1345 { 1440, 900, 60, 1 },
1346 { 1440, 900, 60, 0 },
1347 { 1440, 900, 75, 0 },
1348 { 1440, 900, 85, 0 },
1349 { 1400, 1050, 60, 1 },
1350 { 1400, 1050, 60, 0 },
1351 { 1400, 1050, 75, 0 },
1352 /* byte 9 */
1353 { 1400, 1050, 85, 0 },
1354 { 1680, 1050, 60, 1 },
1355 { 1680, 1050, 60, 0 },
1356 { 1680, 1050, 75, 0 },
1357 { 1680, 1050, 85, 0 },
1358 { 1600, 1200, 60, 0 },
1359 { 1600, 1200, 65, 0 },
1360 { 1600, 1200, 70, 0 },
1361 /* byte 10 */
1362 { 1600, 1200, 75, 0 },
1363 { 1600, 1200, 85, 0 },
1364 { 1792, 1344, 60, 0 },
1365 { 1792, 1344, 85, 0 },
1366 { 1856, 1392, 60, 0 },
1367 { 1856, 1392, 75, 0 },
1368 { 1920, 1200, 60, 1 },
1369 { 1920, 1200, 60, 0 },
1370 /* byte 11 */
1371 { 1920, 1200, 75, 0 },
1372 { 1920, 1200, 85, 0 },
1373 { 1920, 1440, 60, 0 },
1374 { 1920, 1440, 75, 0 },
1375};
1376
1377static int 1010static int
1378drm_est3_modes(struct drm_connector *connector, struct detailed_timing *timing) 1011drm_est3_modes(struct drm_connector *connector, struct detailed_timing *timing)
1379{ 1012{
@@ -1403,37 +1036,63 @@ drm_est3_modes(struct drm_connector *connector, struct detailed_timing *timing)
1403 return modes; 1036 return modes;
1404} 1037}
1405 1038
1406static int add_detailed_modes(struct drm_connector *connector, 1039static void
1407 struct detailed_timing *timing, 1040do_established_modes(struct detailed_timing *timing, void *c)
1408 struct edid *edid, u32 quirks, int preferred)
1409{ 1041{
1410 int i, modes = 0; 1042 struct detailed_mode_closure *closure = c;
1411 struct detailed_non_pixel *data = &timing->data.other_data; 1043 struct detailed_non_pixel *data = &timing->data.other_data;
1412 int gtf = (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF);
1413 struct drm_display_mode *newmode;
1414 struct drm_device *dev = connector->dev;
1415 1044
1416 if (timing->pixel_clock) { 1045 if (data->type == EDID_DETAIL_EST_TIMINGS)
1417 newmode = drm_mode_detailed(dev, edid, timing, quirks); 1046 closure->modes += drm_est3_modes(closure->connector, timing);
1418 if (!newmode) 1047}
1419 return 0;
1420 1048
1421 if (preferred) 1049/**
1422 newmode->type |= DRM_MODE_TYPE_PREFERRED; 1050 * add_established_modes - get est. modes from EDID and add them
1051 * @edid: EDID block to scan
1052 *
1053 * Each EDID block contains a bitmap of the supported "established modes" list
1054 * (defined above). Tease them out and add them to the global modes list.
1055 */
1056static int
1057add_established_modes(struct drm_connector *connector, struct edid *edid)
1058{
1059 struct drm_device *dev = connector->dev;
1060 unsigned long est_bits = edid->established_timings.t1 |
1061 (edid->established_timings.t2 << 8) |
1062 ((edid->established_timings.mfg_rsvd & 0x80) << 9);
1063 int i, modes = 0;
1064 struct detailed_mode_closure closure = {
1065 connector, edid, 0, 0, 0
1066 };
1423 1067
1424 drm_mode_probed_add(connector, newmode); 1068 for (i = 0; i <= EDID_EST_TIMINGS; i++) {
1425 return 1; 1069 if (est_bits & (1<<i)) {
1070 struct drm_display_mode *newmode;
1071 newmode = drm_mode_duplicate(dev, &edid_est_modes[i]);
1072 if (newmode) {
1073 drm_mode_probed_add(connector, newmode);
1074 modes++;
1075 }
1076 }
1426 } 1077 }
1427 1078
1428 /* other timing types */ 1079 if (version_greater(edid, 1, 0))
1429 switch (data->type) { 1080 drm_for_each_detailed_block((u8 *)edid,
1430 case EDID_DETAIL_MONITOR_RANGE: 1081 do_established_modes, &closure);
1431 if (gtf) 1082
1432 modes += drm_gtf_modes_for_range(connector, edid, 1083 return modes + closure.modes;
1433 timing); 1084}
1434 break; 1085
1435 case EDID_DETAIL_STD_MODES: 1086static void
1436 /* Six modes per detailed section */ 1087do_standard_modes(struct detailed_timing *timing, void *c)
1088{
1089 struct detailed_mode_closure *closure = c;
1090 struct detailed_non_pixel *data = &timing->data.other_data;
1091 struct drm_connector *connector = closure->connector;
1092 struct edid *edid = closure->edid;
1093
1094 if (data->type == EDID_DETAIL_STD_MODES) {
1095 int i;
1437 for (i = 0; i < 6; i++) { 1096 for (i = 0; i < 6; i++) {
1438 struct std_timing *std; 1097 struct std_timing *std;
1439 struct drm_display_mode *newmode; 1098 struct drm_display_mode *newmode;
@@ -1443,108 +1102,169 @@ static int add_detailed_modes(struct drm_connector *connector,
1443 edid->revision); 1102 edid->revision);
1444 if (newmode) { 1103 if (newmode) {
1445 drm_mode_probed_add(connector, newmode); 1104 drm_mode_probed_add(connector, newmode);
1446 modes++; 1105 closure->modes++;
1447 } 1106 }
1448 } 1107 }
1449 break;
1450 case EDID_DETAIL_CVT_3BYTE:
1451 modes += drm_cvt_modes(connector, timing);
1452 break;
1453 case EDID_DETAIL_EST_TIMINGS:
1454 modes += drm_est3_modes(connector, timing);
1455 break;
1456 default:
1457 break;
1458 } 1108 }
1459
1460 return modes;
1461} 1109}
1462 1110
1463/** 1111/**
1464 * add_detailed_info - get detailed mode info from EDID data 1112 * add_standard_modes - get std. modes from EDID and add them
1465 * @connector: attached connector
1466 * @edid: EDID block to scan 1113 * @edid: EDID block to scan
1467 * @quirks: quirks to apply
1468 * 1114 *
1469 * Some of the detailed timing sections may contain mode information. Grab 1115 * Standard modes can be calculated using the appropriate standard (DMT,
1470 * it and add it to the list. 1116 * GTF or CVT. Grab them from @edid and add them to the list.
1471 */ 1117 */
1472static int add_detailed_info(struct drm_connector *connector, 1118static int
1473 struct edid *edid, u32 quirks) 1119add_standard_modes(struct drm_connector *connector, struct edid *edid)
1474{ 1120{
1475 int i, modes = 0; 1121 int i, modes = 0;
1122 struct detailed_mode_closure closure = {
1123 connector, edid, 0, 0, 0
1124 };
1125
1126 for (i = 0; i < EDID_STD_TIMINGS; i++) {
1127 struct drm_display_mode *newmode;
1128
1129 newmode = drm_mode_std(connector, edid,
1130 &edid->standard_timings[i],
1131 edid->revision);
1132 if (newmode) {
1133 drm_mode_probed_add(connector, newmode);
1134 modes++;
1135 }
1136 }
1137
1138 if (version_greater(edid, 1, 0))
1139 drm_for_each_detailed_block((u8 *)edid, do_standard_modes,
1140 &closure);
1141
1142 /* XXX should also look for standard codes in VTB blocks */
1143
1144 return modes + closure.modes;
1145}
1476 1146
1477 for (i = 0; i < EDID_DETAILED_TIMINGS; i++) { 1147static int drm_cvt_modes(struct drm_connector *connector,
1478 struct detailed_timing *timing = &edid->detailed_timings[i]; 1148 struct detailed_timing *timing)
1479 int preferred = (i == 0); 1149{
1150 int i, j, modes = 0;
1151 struct drm_display_mode *newmode;
1152 struct drm_device *dev = connector->dev;
1153 struct cvt_timing *cvt;
1154 const int rates[] = { 60, 85, 75, 60, 50 };
1155 const u8 empty[3] = { 0, 0, 0 };
1480 1156
1481 if (preferred && edid->version == 1 && edid->revision < 4) 1157 for (i = 0; i < 4; i++) {
1482 preferred = (edid->features & DRM_EDID_FEATURE_PREFERRED_TIMING); 1158 int uninitialized_var(width), height;
1159 cvt = &(timing->data.other_data.data.cvt[i]);
1483 1160
1484 /* In 1.0, only timings are allowed */ 1161 if (!memcmp(cvt->code, empty, 3))
1485 if (!timing->pixel_clock && edid->version == 1 &&
1486 edid->revision == 0)
1487 continue; 1162 continue;
1488 1163
1489 modes += add_detailed_modes(connector, timing, edid, quirks, 1164 height = (cvt->code[0] + ((cvt->code[1] & 0xf0) << 4) + 1) * 2;
1490 preferred); 1165 switch (cvt->code[1] & 0x0c) {
1166 case 0x00:
1167 width = height * 4 / 3;
1168 break;
1169 case 0x04:
1170 width = height * 16 / 9;
1171 break;
1172 case 0x08:
1173 width = height * 16 / 10;
1174 break;
1175 case 0x0c:
1176 width = height * 15 / 9;
1177 break;
1178 }
1179
1180 for (j = 1; j < 5; j++) {
1181 if (cvt->code[2] & (1 << j)) {
1182 newmode = drm_cvt_mode(dev, width, height,
1183 rates[j], j == 0,
1184 false, false);
1185 if (newmode) {
1186 drm_mode_probed_add(connector, newmode);
1187 modes++;
1188 }
1189 }
1190 }
1491 } 1191 }
1492 1192
1493 return modes; 1193 return modes;
1494} 1194}
1495 1195
1496/** 1196static void
1497 * add_detailed_mode_eedid - get detailed mode info from addtional timing 1197do_cvt_mode(struct detailed_timing *timing, void *c)
1498 * EDID block
1499 * @connector: attached connector
1500 * @edid: EDID block to scan(It is only to get addtional timing EDID block)
1501 * @quirks: quirks to apply
1502 *
1503 * Some of the detailed timing sections may contain mode information. Grab
1504 * it and add it to the list.
1505 */
1506static int add_detailed_info_eedid(struct drm_connector *connector,
1507 struct edid *edid, u32 quirks)
1508{ 1198{
1509 int i, modes = 0; 1199 struct detailed_mode_closure *closure = c;
1510 char *edid_ext = NULL; 1200 struct detailed_non_pixel *data = &timing->data.other_data;
1511 struct detailed_timing *timing;
1512 int start_offset, end_offset;
1513 1201
1514 if (edid->version == 1 && edid->revision < 3) 1202 if (data->type == EDID_DETAIL_CVT_3BYTE)
1515 return 0; 1203 closure->modes += drm_cvt_modes(closure->connector, timing);
1516 if (!edid->extensions) 1204}
1517 return 0;
1518 1205
1519 /* Find CEA extension */ 1206static int
1520 for (i = 0; i < edid->extensions; i++) { 1207add_cvt_modes(struct drm_connector *connector, struct edid *edid)
1521 edid_ext = (char *)edid + EDID_LENGTH * (i + 1); 1208{
1522 if (edid_ext[0] == 0x02) 1209 struct detailed_mode_closure closure = {
1523 break; 1210 connector, edid, 0, 0, 0
1524 } 1211 };
1525 1212
1526 if (i == edid->extensions) 1213 if (version_greater(edid, 1, 2))
1527 return 0; 1214 drm_for_each_detailed_block((u8 *)edid, do_cvt_mode, &closure);
1528 1215
1529 /* Get the start offset of detailed timing block */ 1216 /* XXX should also look for CVT codes in VTB blocks */
1530 start_offset = edid_ext[2];
1531 if (start_offset == 0) {
1532 /* If the start_offset is zero, it means that neither detailed
1533 * info nor data block exist. In such case it is also
1534 * unnecessary to parse the detailed timing info.
1535 */
1536 return 0;
1537 }
1538 1217
1539 end_offset = EDID_LENGTH; 1218 return closure.modes;
1540 end_offset -= sizeof(struct detailed_timing); 1219}
1541 for (i = start_offset; i < end_offset; 1220
1542 i += sizeof(struct detailed_timing)) { 1221static void
1543 timing = (struct detailed_timing *)(edid_ext + i); 1222do_detailed_mode(struct detailed_timing *timing, void *c)
1544 modes += add_detailed_modes(connector, timing, edid, quirks, 0); 1223{
1224 struct detailed_mode_closure *closure = c;
1225 struct drm_display_mode *newmode;
1226
1227 if (timing->pixel_clock) {
1228 newmode = drm_mode_detailed(closure->connector->dev,
1229 closure->edid, timing,
1230 closure->quirks);
1231 if (!newmode)
1232 return;
1233
1234 if (closure->preferred)
1235 newmode->type |= DRM_MODE_TYPE_PREFERRED;
1236
1237 drm_mode_probed_add(closure->connector, newmode);
1238 closure->modes++;
1239 closure->preferred = 0;
1545 } 1240 }
1241}
1546 1242
1547 return modes; 1243/*
1244 * add_detailed_modes - Add modes from detailed timings
1245 * @connector: attached connector
1246 * @edid: EDID block to scan
1247 * @quirks: quirks to apply
1248 */
1249static int
1250add_detailed_modes(struct drm_connector *connector, struct edid *edid,
1251 u32 quirks)
1252{
1253 struct detailed_mode_closure closure = {
1254 connector,
1255 edid,
1256 1,
1257 quirks,
1258 0
1259 };
1260
1261 if (closure.preferred && !version_greater(edid, 1, 3))
1262 closure.preferred =
1263 (edid->features & DRM_EDID_FEATURE_PREFERRED_TIMING);
1264
1265 drm_for_each_detailed_block((u8 *)edid, do_detailed_mode, &closure);
1266
1267 return closure.modes;
1548} 1268}
1549 1269
1550#define HDMI_IDENTIFIER 0x000C03 1270#define HDMI_IDENTIFIER 0x000C03
@@ -1640,35 +1360,21 @@ int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid)
1640 * - established timing codes 1360 * - established timing codes
1641 * - modes inferred from GTF or CVT range information 1361 * - modes inferred from GTF or CVT range information
1642 * 1362 *
1643 * We don't quite implement this yet, but we're close. 1363 * We get this pretty much right.
1644 * 1364 *
1645 * XXX order for additional mode types in extension blocks? 1365 * XXX order for additional mode types in extension blocks?
1646 */ 1366 */
1647 num_modes += add_detailed_info(connector, edid, quirks); 1367 num_modes += add_detailed_modes(connector, edid, quirks);
1648 num_modes += add_detailed_info_eedid(connector, edid, quirks); 1368 num_modes += add_cvt_modes(connector, edid);
1649 num_modes += add_standard_modes(connector, edid); 1369 num_modes += add_standard_modes(connector, edid);
1650 num_modes += add_established_modes(connector, edid); 1370 num_modes += add_established_modes(connector, edid);
1371 num_modes += add_inferred_modes(connector, edid);
1651 1372
1652 if (quirks & (EDID_QUIRK_PREFER_LARGE_60 | EDID_QUIRK_PREFER_LARGE_75)) 1373 if (quirks & (EDID_QUIRK_PREFER_LARGE_60 | EDID_QUIRK_PREFER_LARGE_75))
1653 edid_fixup_preferred(connector, quirks); 1374 edid_fixup_preferred(connector, quirks);
1654 1375
1655 connector->display_info.serration_vsync = (edid->input & DRM_EDID_INPUT_SERRATION_VSYNC) ? 1 : 0;
1656 connector->display_info.sync_on_green = (edid->input & DRM_EDID_INPUT_SYNC_ON_GREEN) ? 1 : 0;
1657 connector->display_info.composite_sync = (edid->input & DRM_EDID_INPUT_COMPOSITE_SYNC) ? 1 : 0;
1658 connector->display_info.separate_syncs = (edid->input & DRM_EDID_INPUT_SEPARATE_SYNCS) ? 1 : 0;
1659 connector->display_info.blank_to_black = (edid->input & DRM_EDID_INPUT_BLANK_TO_BLACK) ? 1 : 0;
1660 connector->display_info.video_level = (edid->input & DRM_EDID_INPUT_VIDEO_LEVEL) >> 5;
1661 connector->display_info.digital = (edid->input & DRM_EDID_INPUT_DIGITAL) ? 1 : 0;
1662 connector->display_info.width_mm = edid->width_cm * 10; 1376 connector->display_info.width_mm = edid->width_cm * 10;
1663 connector->display_info.height_mm = edid->height_cm * 10; 1377 connector->display_info.height_mm = edid->height_cm * 10;
1664 connector->display_info.gamma = edid->gamma;
1665 connector->display_info.gtf_supported = (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF) ? 1 : 0;
1666 connector->display_info.standard_color = (edid->features & DRM_EDID_FEATURE_STANDARD_COLOR) ? 1 : 0;
1667 connector->display_info.display_type = (edid->features & DRM_EDID_FEATURE_DISPLAY_TYPE) >> 3;
1668 connector->display_info.active_off_supported = (edid->features & DRM_EDID_FEATURE_PM_ACTIVE_OFF) ? 1 : 0;
1669 connector->display_info.suspend_supported = (edid->features & DRM_EDID_FEATURE_PM_SUSPEND) ? 1 : 0;
1670 connector->display_info.standby_supported = (edid->features & DRM_EDID_FEATURE_PM_STANDBY) ? 1 : 0;
1671 connector->display_info.gamma = edid->gamma;
1672 1378
1673 return num_modes; 1379 return num_modes;
1674} 1380}
diff --git a/drivers/gpu/drm/drm_edid_modes.h b/drivers/gpu/drm/drm_edid_modes.h
new file mode 100644
index 00000000000..6eb7592e152
--- /dev/null
+++ b/drivers/gpu/drm/drm_edid_modes.h
@@ -0,0 +1,380 @@
1/*
2 * Copyright (c) 2007-2008 Intel Corporation
3 * Jesse Barnes <jesse.barnes@intel.com>
4 * Copyright 2010 Red Hat, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sub license,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial portions
15 * of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
23 * DEALINGS IN THE SOFTWARE.
24 */
25
26#include <linux/kernel.h>
27#include "drmP.h"
28#include "drm_edid.h"
29
30/*
31 * Autogenerated from the DMT spec.
32 * This table is copied from xfree86/modes/xf86EdidModes.c.
33 * But the mode with Reduced blank feature is deleted.
34 */
35static struct drm_display_mode drm_dmt_modes[] = {
36 /* 640x350@85Hz */
37 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
38 736, 832, 0, 350, 382, 385, 445, 0,
39 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
40 /* 640x400@85Hz */
41 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
42 736, 832, 0, 400, 401, 404, 445, 0,
43 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
44 /* 720x400@85Hz */
45 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 756,
46 828, 936, 0, 400, 401, 404, 446, 0,
47 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
48 /* 640x480@60Hz */
49 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
50 752, 800, 0, 480, 489, 492, 525, 0,
51 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
52 /* 640x480@72Hz */
53 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
54 704, 832, 0, 480, 489, 492, 520, 0,
55 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
56 /* 640x480@75Hz */
57 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
58 720, 840, 0, 480, 481, 484, 500, 0,
59 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
60 /* 640x480@85Hz */
61 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 36000, 640, 696,
62 752, 832, 0, 480, 481, 484, 509, 0,
63 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
64 /* 800x600@56Hz */
65 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
66 896, 1024, 0, 600, 601, 603, 625, 0,
67 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
68 /* 800x600@60Hz */
69 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
70 968, 1056, 0, 600, 601, 605, 628, 0,
71 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
72 /* 800x600@72Hz */
73 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
74 976, 1040, 0, 600, 637, 643, 666, 0,
75 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
76 /* 800x600@75Hz */
77 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
78 896, 1056, 0, 600, 601, 604, 625, 0,
79 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
80 /* 800x600@85Hz */
81 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 56250, 800, 832,
82 896, 1048, 0, 600, 601, 604, 631, 0,
83 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
84 /* 848x480@60Hz */
85 { DRM_MODE("848x480", DRM_MODE_TYPE_DRIVER, 33750, 848, 864,
86 976, 1088, 0, 480, 486, 494, 517, 0,
87 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
88 /* 1024x768@43Hz, interlace */
89 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032,
90 1208, 1264, 0, 768, 768, 772, 817, 0,
91 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
92 DRM_MODE_FLAG_INTERLACE) },
93 /* 1024x768@60Hz */
94 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
95 1184, 1344, 0, 768, 771, 777, 806, 0,
96 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
97 /* 1024x768@70Hz */
98 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
99 1184, 1328, 0, 768, 771, 777, 806, 0,
100 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
101 /* 1024x768@75Hz */
102 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040,
103 1136, 1312, 0, 768, 769, 772, 800, 0,
104 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
105 /* 1024x768@85Hz */
106 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 94500, 1024, 1072,
107 1168, 1376, 0, 768, 769, 772, 808, 0,
108 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
109 /* 1152x864@75Hz */
110 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
111 1344, 1600, 0, 864, 865, 868, 900, 0,
112 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
113 /* 1280x768@60Hz */
114 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344,
115 1472, 1664, 0, 768, 771, 778, 798, 0,
116 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
117 /* 1280x768@75Hz */
118 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 102250, 1280, 1360,
119 1488, 1696, 0, 768, 771, 778, 805, 0,
120 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
121 /* 1280x768@85Hz */
122 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 117500, 1280, 1360,
123 1496, 1712, 0, 768, 771, 778, 809, 0,
124 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
125 /* 1280x800@60Hz */
126 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352,
127 1480, 1680, 0, 800, 803, 809, 831, 0,
128 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
129 /* 1280x800@75Hz */
130 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 106500, 1280, 1360,
131 1488, 1696, 0, 800, 803, 809, 838, 0,
132 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
133 /* 1280x800@85Hz */
134 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 122500, 1280, 1360,
135 1496, 1712, 0, 800, 803, 809, 843, 0,
136 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
137 /* 1280x960@60Hz */
138 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1376,
139 1488, 1800, 0, 960, 961, 964, 1000, 0,
140 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
141 /* 1280x960@85Hz */
142 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1344,
143 1504, 1728, 0, 960, 961, 964, 1011, 0,
144 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
145 /* 1280x1024@60Hz */
146 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1328,
147 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
148 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
149 /* 1280x1024@75Hz */
150 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
151 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
152 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
153 /* 1280x1024@85Hz */
154 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 157500, 1280, 1344,
155 1504, 1728, 0, 1024, 1025, 1028, 1072, 0,
156 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
157 /* 1360x768@60Hz */
158 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 85500, 1360, 1424,
159 1536, 1792, 0, 768, 771, 777, 795, 0,
160 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
161 /* 1440x1050@60Hz */
162 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488,
163 1632, 1864, 0, 1050, 1053, 1057, 1089, 0,
164 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
165 /* 1440x1050@75Hz */
166 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 156000, 1400, 1504,
167 1648, 1896, 0, 1050, 1053, 1057, 1099, 0,
168 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
169 /* 1440x1050@85Hz */
170 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 179500, 1400, 1504,
171 1656, 1912, 0, 1050, 1053, 1057, 1105, 0,
172 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
173 /* 1440x900@60Hz */
174 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 106500, 1440, 1520,
175 1672, 1904, 0, 900, 903, 909, 934, 0,
176 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
177 /* 1440x900@75Hz */
178 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 136750, 1440, 1536,
179 1688, 1936, 0, 900, 903, 909, 942, 0,
180 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
181 /* 1440x900@85Hz */
182 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 157000, 1440, 1544,
183 1696, 1952, 0, 900, 903, 909, 948, 0,
184 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
185 /* 1600x1200@60Hz */
186 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664,
187 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
188 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
189 /* 1600x1200@65Hz */
190 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 175500, 1600, 1664,
191 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
192 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
193 /* 1600x1200@70Hz */
194 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 189000, 1600, 1664,
195 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
196 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
197 /* 1600x1200@75Hz */
198 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 202500, 1600, 1664,
199 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
200 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
201 /* 1600x1200@85Hz */
202 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 229500, 1600, 1664,
203 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
204 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
205 /* 1680x1050@60Hz */
206 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784,
207 1960, 2240, 0, 1050, 1053, 1059, 1089, 0,
208 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
209 /* 1680x1050@75Hz */
210 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 187000, 1680, 1800,
211 1976, 2272, 0, 1050, 1053, 1059, 1099, 0,
212 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
213 /* 1680x1050@85Hz */
214 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 214750, 1680, 1808,
215 1984, 2288, 0, 1050, 1053, 1059, 1105, 0,
216 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
217 /* 1792x1344@60Hz */
218 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 204750, 1792, 1920,
219 2120, 2448, 0, 1344, 1345, 1348, 1394, 0,
220 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
221 /* 1729x1344@75Hz */
222 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 261000, 1792, 1888,
223 2104, 2456, 0, 1344, 1345, 1348, 1417, 0,
224 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
225 /* 1853x1392@60Hz */
226 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 218250, 1856, 1952,
227 2176, 2528, 0, 1392, 1393, 1396, 1439, 0,
228 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
229 /* 1856x1392@75Hz */
230 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 288000, 1856, 1984,
231 2208, 2560, 0, 1392, 1395, 1399, 1500, 0,
232 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
233 /* 1920x1200@60Hz */
234 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056,
235 2256, 2592, 0, 1200, 1203, 1209, 1245, 0,
236 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
237 /* 1920x1200@75Hz */
238 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 245250, 1920, 2056,
239 2264, 2608, 0, 1200, 1203, 1209, 1255, 0,
240 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
241 /* 1920x1200@85Hz */
242 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 281250, 1920, 2064,
243 2272, 2624, 0, 1200, 1203, 1209, 1262, 0,
244 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
245 /* 1920x1440@60Hz */
246 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 234000, 1920, 2048,
247 2256, 2600, 0, 1440, 1441, 1444, 1500, 0,
248 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
249 /* 1920x1440@75Hz */
250 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2064,
251 2288, 2640, 0, 1440, 1441, 1444, 1500, 0,
252 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
253 /* 2560x1600@60Hz */
254 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 348500, 2560, 2752,
255 3032, 3504, 0, 1600, 1603, 1609, 1658, 0,
256 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
257 /* 2560x1600@75HZ */
258 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 443250, 2560, 2768,
259 3048, 3536, 0, 1600, 1603, 1609, 1672, 0,
260 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
261 /* 2560x1600@85HZ */
262 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 505250, 2560, 2768,
263 3048, 3536, 0, 1600, 1603, 1609, 1682, 0,
264 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
265};
266static const int drm_num_dmt_modes =
267 sizeof(drm_dmt_modes) / sizeof(struct drm_display_mode);
268
269static struct drm_display_mode edid_est_modes[] = {
270 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
271 968, 1056, 0, 600, 601, 605, 628, 0,
272 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@60Hz */
273 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
274 896, 1024, 0, 600, 601, 603, 625, 0,
275 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@56Hz */
276 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
277 720, 840, 0, 480, 481, 484, 500, 0,
278 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@75Hz */
279 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
280 704, 832, 0, 480, 489, 491, 520, 0,
281 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@72Hz */
282 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 30240, 640, 704,
283 768, 864, 0, 480, 483, 486, 525, 0,
284 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@67Hz */
285 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25200, 640, 656,
286 752, 800, 0, 480, 490, 492, 525, 0,
287 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@60Hz */
288 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 738,
289 846, 900, 0, 400, 421, 423, 449, 0,
290 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 720x400@88Hz */
291 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 28320, 720, 738,
292 846, 900, 0, 400, 412, 414, 449, 0,
293 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 720x400@70Hz */
294 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
295 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
296 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1280x1024@75Hz */
297 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78800, 1024, 1040,
298 1136, 1312, 0, 768, 769, 772, 800, 0,
299 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1024x768@75Hz */
300 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
301 1184, 1328, 0, 768, 771, 777, 806, 0,
302 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@70Hz */
303 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
304 1184, 1344, 0, 768, 771, 777, 806, 0,
305 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@60Hz */
306 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER,44900, 1024, 1032,
307 1208, 1264, 0, 768, 768, 776, 817, 0,
308 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_INTERLACE) }, /* 1024x768@43Hz */
309 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 57284, 832, 864,
310 928, 1152, 0, 624, 625, 628, 667, 0,
311 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 832x624@75Hz */
312 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
313 896, 1056, 0, 600, 601, 604, 625, 0,
314 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@75Hz */
315 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
316 976, 1040, 0, 600, 637, 643, 666, 0,
317 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@72Hz */
318 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
319 1344, 1600, 0, 864, 865, 868, 900, 0,
320 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1152x864@75Hz */
321};
322
323static const struct {
324 short w;
325 short h;
326 short r;
327 short rb;
328} est3_modes[] = {
329 /* byte 6 */
330 { 640, 350, 85, 0 },
331 { 640, 400, 85, 0 },
332 { 720, 400, 85, 0 },
333 { 640, 480, 85, 0 },
334 { 848, 480, 60, 0 },
335 { 800, 600, 85, 0 },
336 { 1024, 768, 85, 0 },
337 { 1152, 864, 75, 0 },
338 /* byte 7 */
339 { 1280, 768, 60, 1 },
340 { 1280, 768, 60, 0 },
341 { 1280, 768, 75, 0 },
342 { 1280, 768, 85, 0 },
343 { 1280, 960, 60, 0 },
344 { 1280, 960, 85, 0 },
345 { 1280, 1024, 60, 0 },
346 { 1280, 1024, 85, 0 },
347 /* byte 8 */
348 { 1360, 768, 60, 0 },
349 { 1440, 900, 60, 1 },
350 { 1440, 900, 60, 0 },
351 { 1440, 900, 75, 0 },
352 { 1440, 900, 85, 0 },
353 { 1400, 1050, 60, 1 },
354 { 1400, 1050, 60, 0 },
355 { 1400, 1050, 75, 0 },
356 /* byte 9 */
357 { 1400, 1050, 85, 0 },
358 { 1680, 1050, 60, 1 },
359 { 1680, 1050, 60, 0 },
360 { 1680, 1050, 75, 0 },
361 { 1680, 1050, 85, 0 },
362 { 1600, 1200, 60, 0 },
363 { 1600, 1200, 65, 0 },
364 { 1600, 1200, 70, 0 },
365 /* byte 10 */
366 { 1600, 1200, 75, 0 },
367 { 1600, 1200, 85, 0 },
368 { 1792, 1344, 60, 0 },
369 { 1792, 1344, 85, 0 },
370 { 1856, 1392, 60, 0 },
371 { 1856, 1392, 75, 0 },
372 { 1920, 1200, 60, 1 },
373 { 1920, 1200, 60, 0 },
374 /* byte 11 */
375 { 1920, 1200, 75, 0 },
376 { 1920, 1200, 85, 0 },
377 { 1920, 1440, 60, 0 },
378 { 1920, 1440, 75, 0 },
379};
380static const int num_est3_modes = sizeof(est3_modes) / sizeof(est3_modes[0]);
diff --git a/drivers/gpu/drm/drm_fops.c b/drivers/gpu/drm/drm_fops.c
index 2ca8df8b610..3a652a65546 100644
--- a/drivers/gpu/drm/drm_fops.c
+++ b/drivers/gpu/drm/drm_fops.c
@@ -135,15 +135,9 @@ int drm_open(struct inode *inode, struct file *filp)
135 retcode = drm_open_helper(inode, filp, dev); 135 retcode = drm_open_helper(inode, filp, dev);
136 if (!retcode) { 136 if (!retcode) {
137 atomic_inc(&dev->counts[_DRM_STAT_OPENS]); 137 atomic_inc(&dev->counts[_DRM_STAT_OPENS]);
138 spin_lock(&dev->count_lock); 138 if (!dev->open_count++)
139 if (!dev->open_count++) {
140 spin_unlock(&dev->count_lock);
141 retcode = drm_setup(dev); 139 retcode = drm_setup(dev);
142 goto out;
143 }
144 spin_unlock(&dev->count_lock);
145 } 140 }
146out:
147 if (!retcode) { 141 if (!retcode) {
148 mutex_lock(&dev->struct_mutex); 142 mutex_lock(&dev->struct_mutex);
149 if (minor->type == DRM_MINOR_LEGACY) { 143 if (minor->type == DRM_MINOR_LEGACY) {
@@ -570,18 +564,14 @@ int drm_release(struct inode *inode, struct file *filp)
570 */ 564 */
571 565
572 atomic_inc(&dev->counts[_DRM_STAT_CLOSES]); 566 atomic_inc(&dev->counts[_DRM_STAT_CLOSES]);
573 spin_lock(&dev->count_lock);
574 if (!--dev->open_count) { 567 if (!--dev->open_count) {
575 if (atomic_read(&dev->ioctl_count)) { 568 if (atomic_read(&dev->ioctl_count)) {
576 DRM_ERROR("Device busy: %d\n", 569 DRM_ERROR("Device busy: %d\n",
577 atomic_read(&dev->ioctl_count)); 570 atomic_read(&dev->ioctl_count));
578 retcode = -EBUSY; 571 retcode = -EBUSY;
579 goto out; 572 } else
580 } 573 retcode = drm_lastclose(dev);
581 retcode = drm_lastclose(dev);
582 } 574 }
583out:
584 spin_unlock(&dev->count_lock);
585 mutex_unlock(&drm_global_mutex); 575 mutex_unlock(&drm_global_mutex);
586 576
587 return retcode; 577 return retcode;
diff --git a/drivers/gpu/drm/drm_gem.c b/drivers/gpu/drm/drm_gem.c
index 4f1b8671448..bf92d07510d 100644
--- a/drivers/gpu/drm/drm_gem.c
+++ b/drivers/gpu/drm/drm_gem.c
@@ -322,7 +322,7 @@ drm_gem_flink_ioctl(struct drm_device *dev, void *data,
322 322
323 obj = drm_gem_object_lookup(dev, file_priv, args->handle); 323 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
324 if (obj == NULL) 324 if (obj == NULL)
325 return -EBADF; 325 return -ENOENT;
326 326
327again: 327again:
328 if (idr_pre_get(&dev->object_name_idr, GFP_KERNEL) == 0) { 328 if (idr_pre_get(&dev->object_name_idr, GFP_KERNEL) == 0) {
diff --git a/drivers/gpu/drm/drm_ioctl.c b/drivers/gpu/drm/drm_ioctl.c
index 7b03b197fc0..47db4df37a6 100644
--- a/drivers/gpu/drm/drm_ioctl.c
+++ b/drivers/gpu/drm/drm_ioctl.c
@@ -392,6 +392,7 @@ int drm_setversion(struct drm_device *dev, void *data, struct drm_file *file_pri
392 if (sv->drm_di_minor >= 1) { 392 if (sv->drm_di_minor >= 1) {
393 /* 393 /*
394 * Version 1.1 includes tying of DRM to specific device 394 * Version 1.1 includes tying of DRM to specific device
395 * Version 1.4 has proper PCI domain support
395 */ 396 */
396 retcode = drm_set_busid(dev, file_priv); 397 retcode = drm_set_busid(dev, file_priv);
397 if (retcode) 398 if (retcode)
diff --git a/drivers/gpu/drm/i2c/ch7006_drv.c b/drivers/gpu/drm/i2c/ch7006_drv.c
index 833b35f44a7..08792a740f1 100644
--- a/drivers/gpu/drm/i2c/ch7006_drv.c
+++ b/drivers/gpu/drm/i2c/ch7006_drv.c
@@ -470,6 +470,7 @@ static int ch7006_encoder_init(struct i2c_client *client,
470 priv->hmargin = 50; 470 priv->hmargin = 50;
471 priv->vmargin = 50; 471 priv->vmargin = 50;
472 priv->last_dpms = -1; 472 priv->last_dpms = -1;
473 priv->chip_version = ch7006_read(client, CH7006_VERSION_ID);
473 474
474 if (ch7006_tv_norm) { 475 if (ch7006_tv_norm) {
475 for (i = 0; i < NUM_TV_NORMS; i++) { 476 for (i = 0; i < NUM_TV_NORMS; i++) {
diff --git a/drivers/gpu/drm/i2c/ch7006_mode.c b/drivers/gpu/drm/i2c/ch7006_mode.c
index e447dfb6389..c860f24a5af 100644
--- a/drivers/gpu/drm/i2c/ch7006_mode.c
+++ b/drivers/gpu/drm/i2c/ch7006_mode.c
@@ -316,7 +316,10 @@ void ch7006_setup_power_state(struct drm_encoder *encoder)
316 } 316 }
317 317
318 } else { 318 } else {
319 *power |= bitfs(CH7006_POWER_LEVEL, FULL_POWER_OFF); 319 if (priv->chip_version >= 0x20)
320 *power |= bitfs(CH7006_POWER_LEVEL, FULL_POWER_OFF);
321 else
322 *power |= bitfs(CH7006_POWER_LEVEL, POWER_OFF);
320 } 323 }
321} 324}
322 325
diff --git a/drivers/gpu/drm/i2c/ch7006_priv.h b/drivers/gpu/drm/i2c/ch7006_priv.h
index 1c6d2e3bd96..17667b7d57e 100644
--- a/drivers/gpu/drm/i2c/ch7006_priv.h
+++ b/drivers/gpu/drm/i2c/ch7006_priv.h
@@ -95,6 +95,7 @@ struct ch7006_priv {
95 int flicker; 95 int flicker;
96 int scale; 96 int scale;
97 97
98 int chip_version;
98 int last_dpms; 99 int last_dpms;
99}; 100};
100 101
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 2a4ed7ca8b4..0758c7802e6 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -456,7 +456,7 @@ i915_gem_pread_ioctl(struct drm_device *dev, void *data,
456 456
457 obj = drm_gem_object_lookup(dev, file_priv, args->handle); 457 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
458 if (obj == NULL) 458 if (obj == NULL)
459 return -EBADF; 459 return -ENOENT;
460 obj_priv = to_intel_bo(obj); 460 obj_priv = to_intel_bo(obj);
461 461
462 /* Bounds check source. 462 /* Bounds check source.
@@ -919,7 +919,7 @@ i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
919 919
920 obj = drm_gem_object_lookup(dev, file_priv, args->handle); 920 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
921 if (obj == NULL) 921 if (obj == NULL)
922 return -EBADF; 922 return -ENOENT;
923 obj_priv = to_intel_bo(obj); 923 obj_priv = to_intel_bo(obj);
924 924
925 /* Bounds check destination. 925 /* Bounds check destination.
@@ -1002,7 +1002,7 @@ i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1002 1002
1003 obj = drm_gem_object_lookup(dev, file_priv, args->handle); 1003 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1004 if (obj == NULL) 1004 if (obj == NULL)
1005 return -EBADF; 1005 return -ENOENT;
1006 obj_priv = to_intel_bo(obj); 1006 obj_priv = to_intel_bo(obj);
1007 1007
1008 mutex_lock(&dev->struct_mutex); 1008 mutex_lock(&dev->struct_mutex);
@@ -1060,7 +1060,7 @@ i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1060 obj = drm_gem_object_lookup(dev, file_priv, args->handle); 1060 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1061 if (obj == NULL) { 1061 if (obj == NULL) {
1062 mutex_unlock(&dev->struct_mutex); 1062 mutex_unlock(&dev->struct_mutex);
1063 return -EBADF; 1063 return -ENOENT;
1064 } 1064 }
1065 1065
1066#if WATCH_BUF 1066#if WATCH_BUF
@@ -1099,7 +1099,7 @@ i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1099 1099
1100 obj = drm_gem_object_lookup(dev, file_priv, args->handle); 1100 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1101 if (obj == NULL) 1101 if (obj == NULL)
1102 return -EBADF; 1102 return -ENOENT;
1103 1103
1104 offset = args->offset; 1104 offset = args->offset;
1105 1105
@@ -1373,7 +1373,7 @@ i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1373 1373
1374 obj = drm_gem_object_lookup(dev, file_priv, args->handle); 1374 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1375 if (obj == NULL) 1375 if (obj == NULL)
1376 return -EBADF; 1376 return -ENOENT;
1377 1377
1378 mutex_lock(&dev->struct_mutex); 1378 mutex_lock(&dev->struct_mutex);
1379 1379
@@ -3364,7 +3364,7 @@ i915_gem_object_pin_and_relocate(struct drm_gem_object *obj,
3364 reloc->target_handle); 3364 reloc->target_handle);
3365 if (target_obj == NULL) { 3365 if (target_obj == NULL) {
3366 i915_gem_object_unpin(obj); 3366 i915_gem_object_unpin(obj);
3367 return -EBADF; 3367 return -ENOENT;
3368 } 3368 }
3369 target_obj_priv = to_intel_bo(target_obj); 3369 target_obj_priv = to_intel_bo(target_obj);
3370 3370
@@ -3781,7 +3781,7 @@ i915_gem_do_execbuffer(struct drm_device *dev, void *data,
3781 exec_list[i].handle, i); 3781 exec_list[i].handle, i);
3782 /* prevent error path from reading uninitialized data */ 3782 /* prevent error path from reading uninitialized data */
3783 args->buffer_count = i + 1; 3783 args->buffer_count = i + 1;
3784 ret = -EBADF; 3784 ret = -ENOENT;
3785 goto err; 3785 goto err;
3786 } 3786 }
3787 3787
@@ -3791,7 +3791,7 @@ i915_gem_do_execbuffer(struct drm_device *dev, void *data,
3791 object_list[i]); 3791 object_list[i]);
3792 /* prevent error path from reading uninitialized data */ 3792 /* prevent error path from reading uninitialized data */
3793 args->buffer_count = i + 1; 3793 args->buffer_count = i + 1;
3794 ret = -EBADF; 3794 ret = -EINVAL;
3795 goto err; 3795 goto err;
3796 } 3796 }
3797 obj_priv->in_execbuffer = true; 3797 obj_priv->in_execbuffer = true;
@@ -4265,7 +4265,7 @@ i915_gem_pin_ioctl(struct drm_device *dev, void *data,
4265 DRM_ERROR("Bad handle in i915_gem_pin_ioctl(): %d\n", 4265 DRM_ERROR("Bad handle in i915_gem_pin_ioctl(): %d\n",
4266 args->handle); 4266 args->handle);
4267 mutex_unlock(&dev->struct_mutex); 4267 mutex_unlock(&dev->struct_mutex);
4268 return -EBADF; 4268 return -ENOENT;
4269 } 4269 }
4270 obj_priv = to_intel_bo(obj); 4270 obj_priv = to_intel_bo(obj);
4271 4271
@@ -4321,7 +4321,7 @@ i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
4321 DRM_ERROR("Bad handle in i915_gem_unpin_ioctl(): %d\n", 4321 DRM_ERROR("Bad handle in i915_gem_unpin_ioctl(): %d\n",
4322 args->handle); 4322 args->handle);
4323 mutex_unlock(&dev->struct_mutex); 4323 mutex_unlock(&dev->struct_mutex);
4324 return -EBADF; 4324 return -ENOENT;
4325 } 4325 }
4326 4326
4327 obj_priv = to_intel_bo(obj); 4327 obj_priv = to_intel_bo(obj);
@@ -4355,7 +4355,7 @@ i915_gem_busy_ioctl(struct drm_device *dev, void *data,
4355 if (obj == NULL) { 4355 if (obj == NULL) {
4356 DRM_ERROR("Bad handle in i915_gem_busy_ioctl(): %d\n", 4356 DRM_ERROR("Bad handle in i915_gem_busy_ioctl(): %d\n",
4357 args->handle); 4357 args->handle);
4358 return -EBADF; 4358 return -ENOENT;
4359 } 4359 }
4360 4360
4361 mutex_lock(&dev->struct_mutex); 4361 mutex_lock(&dev->struct_mutex);
@@ -4408,7 +4408,7 @@ i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
4408 if (obj == NULL) { 4408 if (obj == NULL) {
4409 DRM_ERROR("Bad handle in i915_gem_madvise_ioctl(): %d\n", 4409 DRM_ERROR("Bad handle in i915_gem_madvise_ioctl(): %d\n",
4410 args->handle); 4410 args->handle);
4411 return -EBADF; 4411 return -ENOENT;
4412 } 4412 }
4413 4413
4414 mutex_lock(&dev->struct_mutex); 4414 mutex_lock(&dev->struct_mutex);
diff --git a/drivers/gpu/drm/i915/i915_gem_tiling.c b/drivers/gpu/drm/i915/i915_gem_tiling.c
index 155719e4d16..710eca70b32 100644
--- a/drivers/gpu/drm/i915/i915_gem_tiling.c
+++ b/drivers/gpu/drm/i915/i915_gem_tiling.c
@@ -275,7 +275,7 @@ i915_gem_set_tiling(struct drm_device *dev, void *data,
275 275
276 obj = drm_gem_object_lookup(dev, file_priv, args->handle); 276 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
277 if (obj == NULL) 277 if (obj == NULL)
278 return -EINVAL; 278 return -ENOENT;
279 obj_priv = to_intel_bo(obj); 279 obj_priv = to_intel_bo(obj);
280 280
281 if (!i915_tiling_ok(dev, args->stride, obj->size, args->tiling_mode)) { 281 if (!i915_tiling_ok(dev, args->stride, obj->size, args->tiling_mode)) {
@@ -362,7 +362,7 @@ i915_gem_get_tiling(struct drm_device *dev, void *data,
362 362
363 obj = drm_gem_object_lookup(dev, file_priv, args->handle); 363 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
364 if (obj == NULL) 364 if (obj == NULL)
365 return -EINVAL; 365 return -ENOENT;
366 obj_priv = to_intel_bo(obj); 366 obj_priv = to_intel_bo(obj);
367 367
368 mutex_lock(&dev->struct_mutex); 368 mutex_lock(&dev->struct_mutex);
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 1e5e0d379fa..5ec10e02341 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4429,15 +4429,12 @@ void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
4429} 4429}
4430 4430
4431static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, 4431static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
4432 u16 *blue, uint32_t size) 4432 u16 *blue, uint32_t start, uint32_t size)
4433{ 4433{
4434 int end = (start + size > 256) ? 256 : start + size, i;
4434 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 4435 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4435 int i;
4436
4437 if (size != 256)
4438 return;
4439 4436
4440 for (i = 0; i < 256; i++) { 4437 for (i = start; i < end; i++) {
4441 intel_crtc->lut_r[i] = red[i] >> 8; 4438 intel_crtc->lut_r[i] = red[i] >> 8;
4442 intel_crtc->lut_g[i] = green[i] >> 8; 4439 intel_crtc->lut_g[i] = green[i] >> 8;
4443 intel_crtc->lut_b[i] = blue[i] >> 8; 4440 intel_crtc->lut_b[i] = blue[i] >> 8;
@@ -5412,18 +5409,18 @@ intel_user_framebuffer_create(struct drm_device *dev,
5412 5409
5413 obj = drm_gem_object_lookup(dev, filp, mode_cmd->handle); 5410 obj = drm_gem_object_lookup(dev, filp, mode_cmd->handle);
5414 if (!obj) 5411 if (!obj)
5415 return NULL; 5412 return ERR_PTR(-ENOENT);
5416 5413
5417 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); 5414 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
5418 if (!intel_fb) 5415 if (!intel_fb)
5419 return NULL; 5416 return ERR_PTR(-ENOMEM);
5420 5417
5421 ret = intel_framebuffer_init(dev, intel_fb, 5418 ret = intel_framebuffer_init(dev, intel_fb,
5422 mode_cmd, obj); 5419 mode_cmd, obj);
5423 if (ret) { 5420 if (ret) {
5424 drm_gem_object_unreference_unlocked(obj); 5421 drm_gem_object_unreference_unlocked(obj);
5425 kfree(intel_fb); 5422 kfree(intel_fb);
5426 return NULL; 5423 return ERR_PTR(ret);
5427 } 5424 }
5428 5425
5429 return &intel_fb->base; 5426 return &intel_fb->base;
diff --git a/drivers/gpu/drm/i915/intel_fb.c b/drivers/gpu/drm/i915/intel_fb.c
index a79525f434a..7bdc96256bf 100644
--- a/drivers/gpu/drm/i915/intel_fb.c
+++ b/drivers/gpu/drm/i915/intel_fb.c
@@ -121,7 +121,9 @@ static int intelfb_create(struct intel_fbdev *ifbdev,
121 121
122 info->par = ifbdev; 122 info->par = ifbdev;
123 123
124 intel_framebuffer_init(dev, &ifbdev->ifb, &mode_cmd, fbo); 124 ret = intel_framebuffer_init(dev, &ifbdev->ifb, &mode_cmd, fbo);
125 if (ret)
126 goto out_unpin;
125 127
126 fb = &ifbdev->ifb.base; 128 fb = &ifbdev->ifb.base;
127 129
diff --git a/drivers/gpu/drm/nouveau/Makefile b/drivers/gpu/drm/nouveau/Makefile
index 2405d5ef0ca..e9b06e4ef2a 100644
--- a/drivers/gpu/drm/nouveau/Makefile
+++ b/drivers/gpu/drm/nouveau/Makefile
@@ -12,12 +12,12 @@ nouveau-y := nouveau_drv.o nouveau_state.o nouveau_channel.o nouveau_mem.o \
12 nouveau_dp.o \ 12 nouveau_dp.o \
13 nv04_timer.o \ 13 nv04_timer.o \
14 nv04_mc.o nv40_mc.o nv50_mc.o \ 14 nv04_mc.o nv40_mc.o nv50_mc.o \
15 nv04_fb.o nv10_fb.o nv30_fb.o nv40_fb.o nv50_fb.o \ 15 nv04_fb.o nv10_fb.o nv30_fb.o nv40_fb.o nv50_fb.o nvc0_fb.o \
16 nv04_fifo.o nv10_fifo.o nv40_fifo.o nv50_fifo.o \ 16 nv04_fifo.o nv10_fifo.o nv40_fifo.o nv50_fifo.o nvc0_fifo.o \
17 nv04_graph.o nv10_graph.o nv20_graph.o \ 17 nv04_graph.o nv10_graph.o nv20_graph.o \
18 nv40_graph.o nv50_graph.o \ 18 nv40_graph.o nv50_graph.o nvc0_graph.o \
19 nv40_grctx.o nv50_grctx.o \ 19 nv40_grctx.o nv50_grctx.o \
20 nv04_instmem.o nv50_instmem.o \ 20 nv04_instmem.o nv50_instmem.o nvc0_instmem.o \
21 nv50_crtc.o nv50_dac.o nv50_sor.o \ 21 nv50_crtc.o nv50_dac.o nv50_sor.o \
22 nv50_cursor.o nv50_display.o nv50_fbcon.o \ 22 nv50_cursor.o nv50_display.o nv50_fbcon.o \
23 nv04_dac.o nv04_dfp.o nv04_tv.o nv17_tv.o nv17_tv_modes.o \ 23 nv04_dac.o nv04_dfp.o nv04_tv.o nv17_tv.o nv17_tv_modes.o \
diff --git a/drivers/gpu/drm/nouveau/nouveau_bios.c b/drivers/gpu/drm/nouveau/nouveau_bios.c
index 7369b5e7364..0b69a9628c9 100644
--- a/drivers/gpu/drm/nouveau/nouveau_bios.c
+++ b/drivers/gpu/drm/nouveau/nouveau_bios.c
@@ -1928,6 +1928,31 @@ init_condition_time(struct nvbios *bios, uint16_t offset,
1928} 1928}
1929 1929
1930static int 1930static int
1931init_ltime(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1932{
1933 /*
1934 * INIT_LTIME opcode: 0x57 ('V')
1935 *
1936 * offset (8 bit): opcode
1937 * offset + 1 (16 bit): time
1938 *
1939 * Sleep for "time" miliseconds.
1940 */
1941
1942 unsigned time = ROM16(bios->data[offset + 1]);
1943
1944 if (!iexec->execute)
1945 return 3;
1946
1947 BIOSLOG(bios, "0x%04X: Sleeping for 0x%04X miliseconds\n",
1948 offset, time);
1949
1950 msleep(time);
1951
1952 return 3;
1953}
1954
1955static int
1931init_zm_reg_sequence(struct nvbios *bios, uint16_t offset, 1956init_zm_reg_sequence(struct nvbios *bios, uint16_t offset,
1932 struct init_exec *iexec) 1957 struct init_exec *iexec)
1933{ 1958{
@@ -1995,6 +2020,64 @@ init_sub_direct(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1995} 2020}
1996 2021
1997static int 2022static int
2023init_i2c_if(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2024{
2025 /*
2026 * INIT_I2C_IF opcode: 0x5E ('^')
2027 *
2028 * offset (8 bit): opcode
2029 * offset + 1 (8 bit): DCB I2C table entry index
2030 * offset + 2 (8 bit): I2C slave address
2031 * offset + 3 (8 bit): I2C register
2032 * offset + 4 (8 bit): mask
2033 * offset + 5 (8 bit): data
2034 *
2035 * Read the register given by "I2C register" on the device addressed
2036 * by "I2C slave address" on the I2C bus given by "DCB I2C table
2037 * entry index". Compare the result AND "mask" to "data".
2038 * If they're not equal, skip subsequent opcodes until condition is
2039 * inverted (INIT_NOT), or we hit INIT_RESUME
2040 */
2041
2042 uint8_t i2c_index = bios->data[offset + 1];
2043 uint8_t i2c_address = bios->data[offset + 2] >> 1;
2044 uint8_t reg = bios->data[offset + 3];
2045 uint8_t mask = bios->data[offset + 4];
2046 uint8_t data = bios->data[offset + 5];
2047 struct nouveau_i2c_chan *chan;
2048 union i2c_smbus_data val;
2049 int ret;
2050
2051 /* no execute check by design */
2052
2053 BIOSLOG(bios, "0x%04X: DCBI2CIndex: 0x%02X, I2CAddress: 0x%02X\n",
2054 offset, i2c_index, i2c_address);
2055
2056 chan = init_i2c_device_find(bios->dev, i2c_index);
2057 if (!chan)
2058 return -ENODEV;
2059
2060 ret = i2c_smbus_xfer(&chan->adapter, i2c_address, 0,
2061 I2C_SMBUS_READ, reg,
2062 I2C_SMBUS_BYTE_DATA, &val);
2063 if (ret < 0) {
2064 BIOSLOG(bios, "0x%04X: I2CReg: 0x%02X, Value: [no device], "
2065 "Mask: 0x%02X, Data: 0x%02X\n",
2066 offset, reg, mask, data);
2067 iexec->execute = 0;
2068 return 6;
2069 }
2070
2071 BIOSLOG(bios, "0x%04X: I2CReg: 0x%02X, Value: 0x%02X, "
2072 "Mask: 0x%02X, Data: 0x%02X\n",
2073 offset, reg, val.byte, mask, data);
2074
2075 iexec->execute = ((val.byte & mask) == data);
2076
2077 return 6;
2078}
2079
2080static int
1998init_copy_nv_reg(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2081init_copy_nv_reg(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1999{ 2082{
2000 /* 2083 /*
@@ -2083,9 +2166,10 @@ peek_fb(struct drm_device *dev, struct io_mapping *fb,
2083 uint32_t val = 0; 2166 uint32_t val = 0;
2084 2167
2085 if (off < pci_resource_len(dev->pdev, 1)) { 2168 if (off < pci_resource_len(dev->pdev, 1)) {
2086 uint32_t __iomem *p = io_mapping_map_atomic_wc(fb, off, KM_USER0); 2169 uint32_t __iomem *p =
2170 io_mapping_map_atomic_wc(fb, off & PAGE_MASK, KM_USER0);
2087 2171
2088 val = ioread32(p); 2172 val = ioread32(p + (off & ~PAGE_MASK));
2089 2173
2090 io_mapping_unmap_atomic(p, KM_USER0); 2174 io_mapping_unmap_atomic(p, KM_USER0);
2091 } 2175 }
@@ -2098,9 +2182,10 @@ poke_fb(struct drm_device *dev, struct io_mapping *fb,
2098 uint32_t off, uint32_t val) 2182 uint32_t off, uint32_t val)
2099{ 2183{
2100 if (off < pci_resource_len(dev->pdev, 1)) { 2184 if (off < pci_resource_len(dev->pdev, 1)) {
2101 uint32_t __iomem *p = io_mapping_map_atomic_wc(fb, off, KM_USER0); 2185 uint32_t __iomem *p =
2186 io_mapping_map_atomic_wc(fb, off & PAGE_MASK, KM_USER0);
2102 2187
2103 iowrite32(val, p); 2188 iowrite32(val, p + (off & ~PAGE_MASK));
2104 wmb(); 2189 wmb();
2105 2190
2106 io_mapping_unmap_atomic(p, KM_USER0); 2191 io_mapping_unmap_atomic(p, KM_USER0);
@@ -2165,7 +2250,7 @@ nv04_init_compute_mem(struct nvbios *bios)
2165 NV04_PFB_BOOT_0_RAM_AMOUNT, 2250 NV04_PFB_BOOT_0_RAM_AMOUNT,
2166 NV04_PFB_BOOT_0_RAM_AMOUNT_4MB); 2251 NV04_PFB_BOOT_0_RAM_AMOUNT_4MB);
2167 2252
2168 } else if (peek_fb(dev, fb, 0) == patt) { 2253 } else if (peek_fb(dev, fb, 0) != patt) {
2169 if (read_back_fb(dev, fb, 0x800000, patt)) 2254 if (read_back_fb(dev, fb, 0x800000, patt))
2170 bios_md32(bios, NV04_PFB_BOOT_0, 2255 bios_md32(bios, NV04_PFB_BOOT_0,
2171 NV04_PFB_BOOT_0_RAM_AMOUNT, 2256 NV04_PFB_BOOT_0_RAM_AMOUNT,
@@ -2593,7 +2678,7 @@ init_configure_preinit(struct nvbios *bios, uint16_t offset,
2593 /* no iexec->execute check by design */ 2678 /* no iexec->execute check by design */
2594 2679
2595 uint32_t straps = bios_rd32(bios, NV_PEXTDEV_BOOT_0); 2680 uint32_t straps = bios_rd32(bios, NV_PEXTDEV_BOOT_0);
2596 uint8_t cr3c = ((straps << 2) & 0xf0) | (straps & (1 << 6)); 2681 uint8_t cr3c = ((straps << 2) & 0xf0) | (straps & 0x40) >> 6;
2597 2682
2598 if (bios->major_version > 2) 2683 if (bios->major_version > 2)
2599 return 0; 2684 return 0;
@@ -3140,7 +3225,7 @@ init_gpio(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
3140 const uint32_t nv50_gpio_ctl[2] = { 0xe100, 0xe28c }; 3225 const uint32_t nv50_gpio_ctl[2] = { 0xe100, 0xe28c };
3141 int i; 3226 int i;
3142 3227
3143 if (dev_priv->card_type != NV_50) { 3228 if (dev_priv->card_type < NV_50) {
3144 NV_ERROR(bios->dev, "INIT_GPIO on unsupported chipset\n"); 3229 NV_ERROR(bios->dev, "INIT_GPIO on unsupported chipset\n");
3145 return 1; 3230 return 1;
3146 } 3231 }
@@ -3490,6 +3575,69 @@ init_zm_auxch(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
3490 return len; 3575 return len;
3491} 3576}
3492 3577
3578static int
3579init_i2c_long_if(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
3580{
3581 /*
3582 * INIT_I2C_LONG_IF opcode: 0x9A ('')
3583 *
3584 * offset (8 bit): opcode
3585 * offset + 1 (8 bit): DCB I2C table entry index
3586 * offset + 2 (8 bit): I2C slave address
3587 * offset + 3 (16 bit): I2C register
3588 * offset + 5 (8 bit): mask
3589 * offset + 6 (8 bit): data
3590 *
3591 * Read the register given by "I2C register" on the device addressed
3592 * by "I2C slave address" on the I2C bus given by "DCB I2C table
3593 * entry index". Compare the result AND "mask" to "data".
3594 * If they're not equal, skip subsequent opcodes until condition is
3595 * inverted (INIT_NOT), or we hit INIT_RESUME
3596 */
3597
3598 uint8_t i2c_index = bios->data[offset + 1];
3599 uint8_t i2c_address = bios->data[offset + 2] >> 1;
3600 uint8_t reglo = bios->data[offset + 3];
3601 uint8_t reghi = bios->data[offset + 4];
3602 uint8_t mask = bios->data[offset + 5];
3603 uint8_t data = bios->data[offset + 6];
3604 struct nouveau_i2c_chan *chan;
3605 uint8_t buf0[2] = { reghi, reglo };
3606 uint8_t buf1[1];
3607 struct i2c_msg msg[2] = {
3608 { i2c_address, 0, 1, buf0 },
3609 { i2c_address, I2C_M_RD, 1, buf1 },
3610 };
3611 int ret;
3612
3613 /* no execute check by design */
3614
3615 BIOSLOG(bios, "0x%04X: DCBI2CIndex: 0x%02X, I2CAddress: 0x%02X\n",
3616 offset, i2c_index, i2c_address);
3617
3618 chan = init_i2c_device_find(bios->dev, i2c_index);
3619 if (!chan)
3620 return -ENODEV;
3621
3622
3623 ret = i2c_transfer(&chan->adapter, msg, 2);
3624 if (ret < 0) {
3625 BIOSLOG(bios, "0x%04X: I2CReg: 0x%02X:0x%02X, Value: [no device], "
3626 "Mask: 0x%02X, Data: 0x%02X\n",
3627 offset, reghi, reglo, mask, data);
3628 iexec->execute = 0;
3629 return 7;
3630 }
3631
3632 BIOSLOG(bios, "0x%04X: I2CReg: 0x%02X:0x%02X, Value: 0x%02X, "
3633 "Mask: 0x%02X, Data: 0x%02X\n",
3634 offset, reghi, reglo, buf1[0], mask, data);
3635
3636 iexec->execute = ((buf1[0] & mask) == data);
3637
3638 return 7;
3639}
3640
3493static struct init_tbl_entry itbl_entry[] = { 3641static struct init_tbl_entry itbl_entry[] = {
3494 /* command name , id , length , offset , mult , command handler */ 3642 /* command name , id , length , offset , mult , command handler */
3495 /* INIT_PROG (0x31, 15, 10, 4) removed due to no example of use */ 3643 /* INIT_PROG (0x31, 15, 10, 4) removed due to no example of use */
@@ -3516,9 +3664,11 @@ static struct init_tbl_entry itbl_entry[] = {
3516 { "INIT_ZM_CR" , 0x53, init_zm_cr }, 3664 { "INIT_ZM_CR" , 0x53, init_zm_cr },
3517 { "INIT_ZM_CR_GROUP" , 0x54, init_zm_cr_group }, 3665 { "INIT_ZM_CR_GROUP" , 0x54, init_zm_cr_group },
3518 { "INIT_CONDITION_TIME" , 0x56, init_condition_time }, 3666 { "INIT_CONDITION_TIME" , 0x56, init_condition_time },
3667 { "INIT_LTIME" , 0x57, init_ltime },
3519 { "INIT_ZM_REG_SEQUENCE" , 0x58, init_zm_reg_sequence }, 3668 { "INIT_ZM_REG_SEQUENCE" , 0x58, init_zm_reg_sequence },
3520 /* INIT_INDIRECT_REG (0x5A, 7, 0, 0) removed due to no example of use */ 3669 /* INIT_INDIRECT_REG (0x5A, 7, 0, 0) removed due to no example of use */
3521 { "INIT_SUB_DIRECT" , 0x5B, init_sub_direct }, 3670 { "INIT_SUB_DIRECT" , 0x5B, init_sub_direct },
3671 { "INIT_I2C_IF" , 0x5E, init_i2c_if },
3522 { "INIT_COPY_NV_REG" , 0x5F, init_copy_nv_reg }, 3672 { "INIT_COPY_NV_REG" , 0x5F, init_copy_nv_reg },
3523 { "INIT_ZM_INDEX_IO" , 0x62, init_zm_index_io }, 3673 { "INIT_ZM_INDEX_IO" , 0x62, init_zm_index_io },
3524 { "INIT_COMPUTE_MEM" , 0x63, init_compute_mem }, 3674 { "INIT_COMPUTE_MEM" , 0x63, init_compute_mem },
@@ -3552,6 +3702,7 @@ static struct init_tbl_entry itbl_entry[] = {
3552 { "INIT_97" , 0x97, init_97 }, 3702 { "INIT_97" , 0x97, init_97 },
3553 { "INIT_AUXCH" , 0x98, init_auxch }, 3703 { "INIT_AUXCH" , 0x98, init_auxch },
3554 { "INIT_ZM_AUXCH" , 0x99, init_zm_auxch }, 3704 { "INIT_ZM_AUXCH" , 0x99, init_zm_auxch },
3705 { "INIT_I2C_LONG_IF" , 0x9A, init_i2c_long_if },
3555 { NULL , 0 , NULL } 3706 { NULL , 0 , NULL }
3556}; 3707};
3557 3708
@@ -4410,7 +4561,7 @@ nouveau_bios_run_display_table(struct drm_device *dev, struct dcb_entry *dcbent,
4410 bios->display.script_table_ptr, 4561 bios->display.script_table_ptr,
4411 table[2], table[3], table[0] >= 0x21); 4562 table[2], table[3], table[0] >= 0x21);
4412 if (!otable) { 4563 if (!otable) {
4413 NV_ERROR(dev, "Couldn't find matching output script table\n"); 4564 NV_DEBUG_KMS(dev, "failed to match any output table\n");
4414 return 1; 4565 return 1;
4415 } 4566 }
4416 4567
@@ -4467,7 +4618,7 @@ nouveau_bios_run_display_table(struct drm_device *dev, struct dcb_entry *dcbent,
4467 if (script) 4618 if (script)
4468 script = clkcmptable(bios, script, pxclk); 4619 script = clkcmptable(bios, script, pxclk);
4469 if (!script) { 4620 if (!script) {
4470 NV_ERROR(dev, "clock script 0 not found\n"); 4621 NV_DEBUG_KMS(dev, "clock script 0 not found\n");
4471 return 1; 4622 return 1;
4472 } 4623 }
4473 4624
@@ -4826,7 +4977,7 @@ int get_pll_limits(struct drm_device *dev, uint32_t limit_match, struct pll_lims
4826 pll_lim->min_p = record[12]; 4977 pll_lim->min_p = record[12];
4827 pll_lim->max_p = record[13]; 4978 pll_lim->max_p = record[13];
4828 /* where did this go to?? */ 4979 /* where did this go to?? */
4829 if (limit_match == 0x00614100 || limit_match == 0x00614900) 4980 if ((entry[0] & 0xf0) == 0x80)
4830 pll_lim->refclk = 27000; 4981 pll_lim->refclk = 27000;
4831 else 4982 else
4832 pll_lim->refclk = 100000; 4983 pll_lim->refclk = 100000;
@@ -5852,7 +6003,7 @@ static void fabricate_vga_output(struct dcb_table *dcb, int i2c, int heads)
5852 entry->i2c_index = i2c; 6003 entry->i2c_index = i2c;
5853 entry->heads = heads; 6004 entry->heads = heads;
5854 entry->location = DCB_LOC_ON_CHIP; 6005 entry->location = DCB_LOC_ON_CHIP;
5855 /* "or" mostly unused in early gen crt modesetting, 0 is fine */ 6006 entry->or = 1;
5856} 6007}
5857 6008
5858static void fabricate_dvi_i_output(struct dcb_table *dcb, bool twoHeads) 6009static void fabricate_dvi_i_output(struct dcb_table *dcb, bool twoHeads)
@@ -5980,7 +6131,13 @@ parse_dcb20_entry(struct drm_device *dev, struct dcb_table *dcb,
5980 } 6131 }
5981 break; 6132 break;
5982 case OUTPUT_TMDS: 6133 case OUTPUT_TMDS:
5983 entry->tmdsconf.sor.link = (conf & 0x00000030) >> 4; 6134 if (dcb->version >= 0x40)
6135 entry->tmdsconf.sor.link = (conf & 0x00000030) >> 4;
6136 else if (dcb->version >= 0x30)
6137 entry->tmdsconf.slave_addr = (conf & 0x00000700) >> 8;
6138 else if (dcb->version >= 0x22)
6139 entry->tmdsconf.slave_addr = (conf & 0x00000070) >> 4;
6140
5984 break; 6141 break;
5985 case 0xe: 6142 case 0xe:
5986 /* weird g80 mobile type that "nv" treats as a terminator */ 6143 /* weird g80 mobile type that "nv" treats as a terminator */
@@ -6270,6 +6427,19 @@ parse_dcb_table(struct drm_device *dev, struct nvbios *bios, bool twoHeads)
6270 dcb->i2c_table = &bios->data[i2ctabptr]; 6427 dcb->i2c_table = &bios->data[i2ctabptr];
6271 if (dcb->version >= 0x30) 6428 if (dcb->version >= 0x30)
6272 dcb->i2c_default_indices = dcb->i2c_table[4]; 6429 dcb->i2c_default_indices = dcb->i2c_table[4];
6430
6431 /*
6432 * Parse the "management" I2C bus, used for hardware
6433 * monitoring and some external TMDS transmitters.
6434 */
6435 if (dcb->version >= 0x22) {
6436 int idx = (dcb->version >= 0x40 ?
6437 dcb->i2c_default_indices & 0xf :
6438 2);
6439
6440 read_dcb_i2c_entry(dev, dcb->version, dcb->i2c_table,
6441 idx, &dcb->i2c[idx]);
6442 }
6273 } 6443 }
6274 6444
6275 if (entries > DCB_MAX_NUM_ENTRIES) 6445 if (entries > DCB_MAX_NUM_ENTRIES)
diff --git a/drivers/gpu/drm/nouveau/nouveau_bios.h b/drivers/gpu/drm/nouveau/nouveau_bios.h
index 024458a8d06..fd14dfd3d78 100644
--- a/drivers/gpu/drm/nouveau/nouveau_bios.h
+++ b/drivers/gpu/drm/nouveau/nouveau_bios.h
@@ -131,6 +131,7 @@ struct dcb_entry {
131 } dpconf; 131 } dpconf;
132 struct { 132 struct {
133 struct sor_conf sor; 133 struct sor_conf sor;
134 int slave_addr;
134 } tmdsconf; 135 } tmdsconf;
135 }; 136 };
136 bool i2c_upper_default; 137 bool i2c_upper_default;
diff --git a/drivers/gpu/drm/nouveau/nouveau_bo.c b/drivers/gpu/drm/nouveau/nouveau_bo.c
index 3ca8343c15d..84f85183d04 100644
--- a/drivers/gpu/drm/nouveau/nouveau_bo.c
+++ b/drivers/gpu/drm/nouveau/nouveau_bo.c
@@ -51,9 +51,6 @@ nouveau_bo_del_ttm(struct ttm_buffer_object *bo)
51 if (nvbo->tile) 51 if (nvbo->tile)
52 nv10_mem_expire_tiling(dev, nvbo->tile, NULL); 52 nv10_mem_expire_tiling(dev, nvbo->tile, NULL);
53 53
54 spin_lock(&dev_priv->ttm.bo_list_lock);
55 list_del(&nvbo->head);
56 spin_unlock(&dev_priv->ttm.bo_list_lock);
57 kfree(nvbo); 54 kfree(nvbo);
58} 55}
59 56
@@ -166,9 +163,6 @@ nouveau_bo_new(struct drm_device *dev, struct nouveau_channel *chan,
166 } 163 }
167 nvbo->channel = NULL; 164 nvbo->channel = NULL;
168 165
169 spin_lock(&dev_priv->ttm.bo_list_lock);
170 list_add_tail(&nvbo->head, &dev_priv->ttm.bo_list);
171 spin_unlock(&dev_priv->ttm.bo_list_lock);
172 *pnvbo = nvbo; 166 *pnvbo = nvbo;
173 return 0; 167 return 0;
174} 168}
diff --git a/drivers/gpu/drm/nouveau/nouveau_connector.c b/drivers/gpu/drm/nouveau/nouveau_connector.c
index 734e92635e8..b1b22baf142 100644
--- a/drivers/gpu/drm/nouveau/nouveau_connector.c
+++ b/drivers/gpu/drm/nouveau/nouveau_connector.c
@@ -37,12 +37,6 @@
37#include "nouveau_connector.h" 37#include "nouveau_connector.h"
38#include "nouveau_hw.h" 38#include "nouveau_hw.h"
39 39
40static inline struct drm_encoder_slave_funcs *
41get_slave_funcs(struct nouveau_encoder *enc)
42{
43 return to_encoder_slave(to_drm_encoder(enc))->slave_funcs;
44}
45
46static struct nouveau_encoder * 40static struct nouveau_encoder *
47find_encoder_by_type(struct drm_connector *connector, int type) 41find_encoder_by_type(struct drm_connector *connector, int type)
48{ 42{
@@ -360,6 +354,7 @@ nouveau_connector_set_property(struct drm_connector *connector,
360{ 354{
361 struct nouveau_connector *nv_connector = nouveau_connector(connector); 355 struct nouveau_connector *nv_connector = nouveau_connector(connector);
362 struct nouveau_encoder *nv_encoder = nv_connector->detected_encoder; 356 struct nouveau_encoder *nv_encoder = nv_connector->detected_encoder;
357 struct drm_encoder *encoder = to_drm_encoder(nv_encoder);
363 struct drm_device *dev = connector->dev; 358 struct drm_device *dev = connector->dev;
364 int ret; 359 int ret;
365 360
@@ -432,8 +427,8 @@ nouveau_connector_set_property(struct drm_connector *connector,
432 } 427 }
433 428
434 if (nv_encoder && nv_encoder->dcb->type == OUTPUT_TV) 429 if (nv_encoder && nv_encoder->dcb->type == OUTPUT_TV)
435 return get_slave_funcs(nv_encoder)-> 430 return get_slave_funcs(encoder)->set_property(
436 set_property(to_drm_encoder(nv_encoder), connector, property, value); 431 encoder, connector, property, value);
437 432
438 return -EINVAL; 433 return -EINVAL;
439} 434}
@@ -545,6 +540,7 @@ nouveau_connector_get_modes(struct drm_connector *connector)
545 struct drm_nouveau_private *dev_priv = dev->dev_private; 540 struct drm_nouveau_private *dev_priv = dev->dev_private;
546 struct nouveau_connector *nv_connector = nouveau_connector(connector); 541 struct nouveau_connector *nv_connector = nouveau_connector(connector);
547 struct nouveau_encoder *nv_encoder = nv_connector->detected_encoder; 542 struct nouveau_encoder *nv_encoder = nv_connector->detected_encoder;
543 struct drm_encoder *encoder = to_drm_encoder(nv_encoder);
548 int ret = 0; 544 int ret = 0;
549 545
550 /* destroy the native mode, the attached monitor could have changed. 546 /* destroy the native mode, the attached monitor could have changed.
@@ -580,8 +576,7 @@ nouveau_connector_get_modes(struct drm_connector *connector)
580 } 576 }
581 577
582 if (nv_encoder->dcb->type == OUTPUT_TV) 578 if (nv_encoder->dcb->type == OUTPUT_TV)
583 ret = get_slave_funcs(nv_encoder)-> 579 ret = get_slave_funcs(encoder)->get_modes(encoder, connector);
584 get_modes(to_drm_encoder(nv_encoder), connector);
585 580
586 if (nv_connector->dcb->type == DCB_CONNECTOR_LVDS || 581 if (nv_connector->dcb->type == DCB_CONNECTOR_LVDS ||
587 nv_connector->dcb->type == DCB_CONNECTOR_eDP) 582 nv_connector->dcb->type == DCB_CONNECTOR_eDP)
@@ -597,6 +592,7 @@ nouveau_connector_mode_valid(struct drm_connector *connector,
597 struct drm_nouveau_private *dev_priv = connector->dev->dev_private; 592 struct drm_nouveau_private *dev_priv = connector->dev->dev_private;
598 struct nouveau_connector *nv_connector = nouveau_connector(connector); 593 struct nouveau_connector *nv_connector = nouveau_connector(connector);
599 struct nouveau_encoder *nv_encoder = nv_connector->detected_encoder; 594 struct nouveau_encoder *nv_encoder = nv_connector->detected_encoder;
595 struct drm_encoder *encoder = to_drm_encoder(nv_encoder);
600 unsigned min_clock = 25000, max_clock = min_clock; 596 unsigned min_clock = 25000, max_clock = min_clock;
601 unsigned clock = mode->clock; 597 unsigned clock = mode->clock;
602 598
@@ -623,8 +619,7 @@ nouveau_connector_mode_valid(struct drm_connector *connector,
623 max_clock = 350000; 619 max_clock = 350000;
624 break; 620 break;
625 case OUTPUT_TV: 621 case OUTPUT_TV:
626 return get_slave_funcs(nv_encoder)-> 622 return get_slave_funcs(encoder)->mode_valid(encoder, mode);
627 mode_valid(to_drm_encoder(nv_encoder), mode);
628 case OUTPUT_DP: 623 case OUTPUT_DP:
629 if (nv_encoder->dp.link_bw == DP_LINK_BW_2_7) 624 if (nv_encoder->dp.link_bw == DP_LINK_BW_2_7)
630 max_clock = nv_encoder->dp.link_nr * 270000; 625 max_clock = nv_encoder->dp.link_nr * 270000;
diff --git a/drivers/gpu/drm/nouveau/nouveau_display.c b/drivers/gpu/drm/nouveau/nouveau_display.c
index 74e6b4ed12c..2e11fd65b4d 100644
--- a/drivers/gpu/drm/nouveau/nouveau_display.c
+++ b/drivers/gpu/drm/nouveau/nouveau_display.c
@@ -84,16 +84,16 @@ nouveau_user_framebuffer_create(struct drm_device *dev,
84 84
85 gem = drm_gem_object_lookup(dev, file_priv, mode_cmd->handle); 85 gem = drm_gem_object_lookup(dev, file_priv, mode_cmd->handle);
86 if (!gem) 86 if (!gem)
87 return NULL; 87 return ERR_PTR(-ENOENT);
88 88
89 nouveau_fb = kzalloc(sizeof(struct nouveau_framebuffer), GFP_KERNEL); 89 nouveau_fb = kzalloc(sizeof(struct nouveau_framebuffer), GFP_KERNEL);
90 if (!nouveau_fb) 90 if (!nouveau_fb)
91 return NULL; 91 return ERR_PTR(-ENOMEM);
92 92
93 ret = nouveau_framebuffer_init(dev, nouveau_fb, mode_cmd, nouveau_gem_object(gem)); 93 ret = nouveau_framebuffer_init(dev, nouveau_fb, mode_cmd, nouveau_gem_object(gem));
94 if (ret) { 94 if (ret) {
95 drm_gem_object_unreference(gem); 95 drm_gem_object_unreference(gem);
96 return NULL; 96 return ERR_PTR(ret);
97 } 97 }
98 98
99 return &nouveau_fb->base; 99 return &nouveau_fb->base;
diff --git a/drivers/gpu/drm/nouveau/nouveau_dp.c b/drivers/gpu/drm/nouveau/nouveau_dp.c
index 33742b11188..8a1b188b4cd 100644
--- a/drivers/gpu/drm/nouveau/nouveau_dp.c
+++ b/drivers/gpu/drm/nouveau/nouveau_dp.c
@@ -572,47 +572,64 @@ out:
572 return ret ? ret : (stat & NV50_AUXCH_STAT_REPLY); 572 return ret ? ret : (stat & NV50_AUXCH_STAT_REPLY);
573} 573}
574 574
575int 575static int
576nouveau_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode, 576nouveau_dp_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
577 uint8_t write_byte, uint8_t *read_byte)
578{ 577{
579 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data; 578 struct nouveau_i2c_chan *auxch = (struct nouveau_i2c_chan *)adap;
580 struct nouveau_i2c_chan *auxch = (struct nouveau_i2c_chan *)adapter;
581 struct drm_device *dev = auxch->dev; 579 struct drm_device *dev = auxch->dev;
582 int ret = 0, cmd, addr = algo_data->address; 580 struct i2c_msg *msg = msgs;
583 uint8_t *buf; 581 int ret, mcnt = num;
584
585 if (mode == MODE_I2C_READ) {
586 cmd = AUX_I2C_READ;
587 buf = read_byte;
588 } else {
589 cmd = (mode & MODE_I2C_READ) ? AUX_I2C_READ : AUX_I2C_WRITE;
590 buf = &write_byte;
591 }
592 582
593 if (!(mode & MODE_I2C_STOP)) 583 while (mcnt--) {
594 cmd |= AUX_I2C_MOT; 584 u8 remaining = msg->len;
585 u8 *ptr = msg->buf;
595 586
596 if (mode & MODE_I2C_START) 587 while (remaining) {
597 return 1; 588 u8 cnt = (remaining > 16) ? 16 : remaining;
589 u8 cmd;
598 590
599 for (;;) { 591 if (msg->flags & I2C_M_RD)
600 ret = nouveau_dp_auxch(auxch, cmd, addr, buf, 1); 592 cmd = AUX_I2C_READ;
601 if (ret < 0) 593 else
602 return ret; 594 cmd = AUX_I2C_WRITE;
603 595
604 switch (ret & NV50_AUXCH_STAT_REPLY_I2C) { 596 if (mcnt || remaining > 16)
605 case NV50_AUXCH_STAT_REPLY_I2C_ACK: 597 cmd |= AUX_I2C_MOT;
606 return 1; 598
607 case NV50_AUXCH_STAT_REPLY_I2C_NACK: 599 ret = nouveau_dp_auxch(auxch, cmd, msg->addr, ptr, cnt);
608 return -EREMOTEIO; 600 if (ret < 0)
609 case NV50_AUXCH_STAT_REPLY_I2C_DEFER: 601 return ret;
610 udelay(100); 602
611 break; 603 switch (ret & NV50_AUXCH_STAT_REPLY_I2C) {
612 default: 604 case NV50_AUXCH_STAT_REPLY_I2C_ACK:
613 NV_ERROR(dev, "invalid auxch status: 0x%08x\n", ret); 605 break;
614 return -EREMOTEIO; 606 case NV50_AUXCH_STAT_REPLY_I2C_NACK:
607 return -EREMOTEIO;
608 case NV50_AUXCH_STAT_REPLY_I2C_DEFER:
609 udelay(100);
610 continue;
611 default:
612 NV_ERROR(dev, "bad auxch reply: 0x%08x\n", ret);
613 return -EREMOTEIO;
614 }
615
616 ptr += cnt;
617 remaining -= cnt;
615 } 618 }
619
620 msg++;
616 } 621 }
622
623 return num;
624}
625
626static u32
627nouveau_dp_i2c_func(struct i2c_adapter *adap)
628{
629 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
617} 630}
618 631
632const struct i2c_algorithm nouveau_dp_i2c_algo = {
633 .master_xfer = nouveau_dp_i2c_xfer,
634 .functionality = nouveau_dp_i2c_func
635};
diff --git a/drivers/gpu/drm/nouveau/nouveau_drv.h b/drivers/gpu/drm/nouveau/nouveau_drv.h
index e15db15dca7..e424bf74d70 100644
--- a/drivers/gpu/drm/nouveau/nouveau_drv.h
+++ b/drivers/gpu/drm/nouveau/nouveau_drv.h
@@ -410,7 +410,7 @@ enum nv04_fp_display_regs {
410 410
411struct nv04_crtc_reg { 411struct nv04_crtc_reg {
412 unsigned char MiscOutReg; /* */ 412 unsigned char MiscOutReg; /* */
413 uint8_t CRTC[0x9f]; 413 uint8_t CRTC[0xa0];
414 uint8_t CR58[0x10]; 414 uint8_t CR58[0x10];
415 uint8_t Sequencer[5]; 415 uint8_t Sequencer[5];
416 uint8_t Graphics[9]; 416 uint8_t Graphics[9];
@@ -509,6 +509,7 @@ enum nouveau_card_type {
509 NV_30 = 0x30, 509 NV_30 = 0x30,
510 NV_40 = 0x40, 510 NV_40 = 0x40,
511 NV_50 = 0x50, 511 NV_50 = 0x50,
512 NV_C0 = 0xc0,
512}; 513};
513 514
514struct drm_nouveau_private { 515struct drm_nouveau_private {
@@ -536,8 +537,6 @@ struct drm_nouveau_private {
536 struct drm_global_reference mem_global_ref; 537 struct drm_global_reference mem_global_ref;
537 struct ttm_bo_global_ref bo_global_ref; 538 struct ttm_bo_global_ref bo_global_ref;
538 struct ttm_bo_device bdev; 539 struct ttm_bo_device bdev;
539 spinlock_t bo_list_lock;
540 struct list_head bo_list;
541 atomic_t validate_sequence; 540 atomic_t validate_sequence;
542 } ttm; 541 } ttm;
543 542
@@ -931,6 +930,10 @@ extern void nv40_fb_set_region_tiling(struct drm_device *, int, uint32_t,
931extern int nv50_fb_init(struct drm_device *); 930extern int nv50_fb_init(struct drm_device *);
932extern void nv50_fb_takedown(struct drm_device *); 931extern void nv50_fb_takedown(struct drm_device *);
933 932
933/* nvc0_fb.c */
934extern int nvc0_fb_init(struct drm_device *);
935extern void nvc0_fb_takedown(struct drm_device *);
936
934/* nv04_fifo.c */ 937/* nv04_fifo.c */
935extern int nv04_fifo_init(struct drm_device *); 938extern int nv04_fifo_init(struct drm_device *);
936extern void nv04_fifo_disable(struct drm_device *); 939extern void nv04_fifo_disable(struct drm_device *);
@@ -968,6 +971,20 @@ extern void nv50_fifo_destroy_context(struct nouveau_channel *);
968extern int nv50_fifo_load_context(struct nouveau_channel *); 971extern int nv50_fifo_load_context(struct nouveau_channel *);
969extern int nv50_fifo_unload_context(struct drm_device *); 972extern int nv50_fifo_unload_context(struct drm_device *);
970 973
974/* nvc0_fifo.c */
975extern int nvc0_fifo_init(struct drm_device *);
976extern void nvc0_fifo_takedown(struct drm_device *);
977extern void nvc0_fifo_disable(struct drm_device *);
978extern void nvc0_fifo_enable(struct drm_device *);
979extern bool nvc0_fifo_reassign(struct drm_device *, bool);
980extern bool nvc0_fifo_cache_flush(struct drm_device *);
981extern bool nvc0_fifo_cache_pull(struct drm_device *, bool);
982extern int nvc0_fifo_channel_id(struct drm_device *);
983extern int nvc0_fifo_create_context(struct nouveau_channel *);
984extern void nvc0_fifo_destroy_context(struct nouveau_channel *);
985extern int nvc0_fifo_load_context(struct nouveau_channel *);
986extern int nvc0_fifo_unload_context(struct drm_device *);
987
971/* nv04_graph.c */ 988/* nv04_graph.c */
972extern struct nouveau_pgraph_object_class nv04_graph_grclass[]; 989extern struct nouveau_pgraph_object_class nv04_graph_grclass[];
973extern int nv04_graph_init(struct drm_device *); 990extern int nv04_graph_init(struct drm_device *);
@@ -1032,6 +1049,16 @@ extern int nv50_graph_unload_context(struct drm_device *);
1032extern void nv50_graph_context_switch(struct drm_device *); 1049extern void nv50_graph_context_switch(struct drm_device *);
1033extern int nv50_grctx_init(struct nouveau_grctx *); 1050extern int nv50_grctx_init(struct nouveau_grctx *);
1034 1051
1052/* nvc0_graph.c */
1053extern int nvc0_graph_init(struct drm_device *);
1054extern void nvc0_graph_takedown(struct drm_device *);
1055extern void nvc0_graph_fifo_access(struct drm_device *, bool);
1056extern struct nouveau_channel *nvc0_graph_channel(struct drm_device *);
1057extern int nvc0_graph_create_context(struct nouveau_channel *);
1058extern void nvc0_graph_destroy_context(struct nouveau_channel *);
1059extern int nvc0_graph_load_context(struct nouveau_channel *);
1060extern int nvc0_graph_unload_context(struct drm_device *);
1061
1035/* nv04_instmem.c */ 1062/* nv04_instmem.c */
1036extern int nv04_instmem_init(struct drm_device *); 1063extern int nv04_instmem_init(struct drm_device *);
1037extern void nv04_instmem_takedown(struct drm_device *); 1064extern void nv04_instmem_takedown(struct drm_device *);
@@ -1058,6 +1085,18 @@ extern void nv50_instmem_flush(struct drm_device *);
1058extern void nv84_instmem_flush(struct drm_device *); 1085extern void nv84_instmem_flush(struct drm_device *);
1059extern void nv50_vm_flush(struct drm_device *, int engine); 1086extern void nv50_vm_flush(struct drm_device *, int engine);
1060 1087
1088/* nvc0_instmem.c */
1089extern int nvc0_instmem_init(struct drm_device *);
1090extern void nvc0_instmem_takedown(struct drm_device *);
1091extern int nvc0_instmem_suspend(struct drm_device *);
1092extern void nvc0_instmem_resume(struct drm_device *);
1093extern int nvc0_instmem_populate(struct drm_device *, struct nouveau_gpuobj *,
1094 uint32_t *size);
1095extern void nvc0_instmem_clear(struct drm_device *, struct nouveau_gpuobj *);
1096extern int nvc0_instmem_bind(struct drm_device *, struct nouveau_gpuobj *);
1097extern int nvc0_instmem_unbind(struct drm_device *, struct nouveau_gpuobj *);
1098extern void nvc0_instmem_flush(struct drm_device *);
1099
1061/* nv04_mc.c */ 1100/* nv04_mc.c */
1062extern int nv04_mc_init(struct drm_device *); 1101extern int nv04_mc_init(struct drm_device *);
1063extern void nv04_mc_takedown(struct drm_device *); 1102extern void nv04_mc_takedown(struct drm_device *);
diff --git a/drivers/gpu/drm/nouveau/nouveau_encoder.h b/drivers/gpu/drm/nouveau/nouveau_encoder.h
index a1a0d48ae70..7c82d68bc15 100644
--- a/drivers/gpu/drm/nouveau/nouveau_encoder.h
+++ b/drivers/gpu/drm/nouveau/nouveau_encoder.h
@@ -71,6 +71,12 @@ static inline struct drm_encoder *to_drm_encoder(struct nouveau_encoder *enc)
71 return &enc->base.base; 71 return &enc->base.base;
72} 72}
73 73
74static inline struct drm_encoder_slave_funcs *
75get_slave_funcs(struct drm_encoder *enc)
76{
77 return to_encoder_slave(enc)->slave_funcs;
78}
79
74struct nouveau_connector * 80struct nouveau_connector *
75nouveau_encoder_connector_get(struct nouveau_encoder *encoder); 81nouveau_encoder_connector_get(struct nouveau_encoder *encoder);
76int nv50_sor_create(struct drm_connector *, struct dcb_entry *); 82int nv50_sor_create(struct drm_connector *, struct dcb_entry *);
diff --git a/drivers/gpu/drm/nouveau/nouveau_fbcon.c b/drivers/gpu/drm/nouveau/nouveau_fbcon.c
index 099f637264a..dbd30b2e43f 100644
--- a/drivers/gpu/drm/nouveau/nouveau_fbcon.c
+++ b/drivers/gpu/drm/nouveau/nouveau_fbcon.c
@@ -281,6 +281,8 @@ nouveau_fbcon_create(struct nouveau_fbdev *nfbdev,
281 281
282 if (dev_priv->channel && !nouveau_nofbaccel) { 282 if (dev_priv->channel && !nouveau_nofbaccel) {
283 switch (dev_priv->card_type) { 283 switch (dev_priv->card_type) {
284 case NV_C0:
285 break;
284 case NV_50: 286 case NV_50:
285 nv50_fbcon_accel_init(info); 287 nv50_fbcon_accel_init(info);
286 info->fbops = &nv50_fbcon_ops; 288 info->fbops = &nv50_fbcon_ops;
diff --git a/drivers/gpu/drm/nouveau/nouveau_gem.c b/drivers/gpu/drm/nouveau/nouveau_gem.c
index 547f2c24c1e..0f417ac1b69 100644
--- a/drivers/gpu/drm/nouveau/nouveau_gem.c
+++ b/drivers/gpu/drm/nouveau/nouveau_gem.c
@@ -284,7 +284,7 @@ retry:
284 if (!gem) { 284 if (!gem) {
285 NV_ERROR(dev, "Unknown handle 0x%08x\n", b->handle); 285 NV_ERROR(dev, "Unknown handle 0x%08x\n", b->handle);
286 validate_fini(op, NULL); 286 validate_fini(op, NULL);
287 return -EINVAL; 287 return -ENOENT;
288 } 288 }
289 nvbo = gem->driver_private; 289 nvbo = gem->driver_private;
290 290
@@ -759,7 +759,7 @@ nouveau_gem_ioctl_cpu_prep(struct drm_device *dev, void *data,
759 759
760 gem = drm_gem_object_lookup(dev, file_priv, req->handle); 760 gem = drm_gem_object_lookup(dev, file_priv, req->handle);
761 if (!gem) 761 if (!gem)
762 return ret; 762 return -ENOENT;
763 nvbo = nouveau_gem_object(gem); 763 nvbo = nouveau_gem_object(gem);
764 764
765 if (nvbo->cpu_filp) { 765 if (nvbo->cpu_filp) {
@@ -797,7 +797,7 @@ nouveau_gem_ioctl_cpu_fini(struct drm_device *dev, void *data,
797 797
798 gem = drm_gem_object_lookup(dev, file_priv, req->handle); 798 gem = drm_gem_object_lookup(dev, file_priv, req->handle);
799 if (!gem) 799 if (!gem)
800 return ret; 800 return -ENOENT;
801 nvbo = nouveau_gem_object(gem); 801 nvbo = nouveau_gem_object(gem);
802 802
803 if (nvbo->cpu_filp != file_priv) 803 if (nvbo->cpu_filp != file_priv)
@@ -822,7 +822,7 @@ nouveau_gem_ioctl_info(struct drm_device *dev, void *data,
822 822
823 gem = drm_gem_object_lookup(dev, file_priv, req->handle); 823 gem = drm_gem_object_lookup(dev, file_priv, req->handle);
824 if (!gem) 824 if (!gem)
825 return -EINVAL; 825 return -ENOENT;
826 826
827 ret = nouveau_gem_info(gem, req); 827 ret = nouveau_gem_info(gem, req);
828 drm_gem_object_unreference_unlocked(gem); 828 drm_gem_object_unreference_unlocked(gem);
diff --git a/drivers/gpu/drm/nouveau/nouveau_hw.c b/drivers/gpu/drm/nouveau/nouveau_hw.c
index 7855b35effc..7b613682e40 100644
--- a/drivers/gpu/drm/nouveau/nouveau_hw.c
+++ b/drivers/gpu/drm/nouveau/nouveau_hw.c
@@ -865,8 +865,12 @@ nv_save_state_ext(struct drm_device *dev, int head,
865 rd_cio_state(dev, head, regp, NV_CIO_CRE_FF_INDEX); 865 rd_cio_state(dev, head, regp, NV_CIO_CRE_FF_INDEX);
866 rd_cio_state(dev, head, regp, NV_CIO_CRE_FFLWM__INDEX); 866 rd_cio_state(dev, head, regp, NV_CIO_CRE_FFLWM__INDEX);
867 rd_cio_state(dev, head, regp, NV_CIO_CRE_21); 867 rd_cio_state(dev, head, regp, NV_CIO_CRE_21);
868 if (dev_priv->card_type >= NV_30) 868
869 if (dev_priv->card_type >= NV_30) {
869 rd_cio_state(dev, head, regp, NV_CIO_CRE_47); 870 rd_cio_state(dev, head, regp, NV_CIO_CRE_47);
871 rd_cio_state(dev, head, regp, 0x9f);
872 }
873
870 rd_cio_state(dev, head, regp, NV_CIO_CRE_49); 874 rd_cio_state(dev, head, regp, NV_CIO_CRE_49);
871 rd_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR0_INDEX); 875 rd_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR0_INDEX);
872 rd_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR1_INDEX); 876 rd_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR1_INDEX);
@@ -971,8 +975,11 @@ nv_load_state_ext(struct drm_device *dev, int head,
971 wr_cio_state(dev, head, regp, NV_CIO_CRE_ENH_INDEX); 975 wr_cio_state(dev, head, regp, NV_CIO_CRE_ENH_INDEX);
972 wr_cio_state(dev, head, regp, NV_CIO_CRE_FF_INDEX); 976 wr_cio_state(dev, head, regp, NV_CIO_CRE_FF_INDEX);
973 wr_cio_state(dev, head, regp, NV_CIO_CRE_FFLWM__INDEX); 977 wr_cio_state(dev, head, regp, NV_CIO_CRE_FFLWM__INDEX);
974 if (dev_priv->card_type >= NV_30) 978
979 if (dev_priv->card_type >= NV_30) {
975 wr_cio_state(dev, head, regp, NV_CIO_CRE_47); 980 wr_cio_state(dev, head, regp, NV_CIO_CRE_47);
981 wr_cio_state(dev, head, regp, 0x9f);
982 }
976 983
977 wr_cio_state(dev, head, regp, NV_CIO_CRE_49); 984 wr_cio_state(dev, head, regp, NV_CIO_CRE_49);
978 wr_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR0_INDEX); 985 wr_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR0_INDEX);
diff --git a/drivers/gpu/drm/nouveau/nouveau_i2c.c b/drivers/gpu/drm/nouveau/nouveau_i2c.c
index cb0cb34440c..0bd407ca3d4 100644
--- a/drivers/gpu/drm/nouveau/nouveau_i2c.c
+++ b/drivers/gpu/drm/nouveau/nouveau_i2c.c
@@ -163,7 +163,7 @@ nouveau_i2c_init(struct drm_device *dev, struct dcb_i2c_entry *entry, int index)
163 if (entry->chan) 163 if (entry->chan)
164 return -EEXIST; 164 return -EEXIST;
165 165
166 if (dev_priv->card_type == NV_50 && entry->read >= NV50_I2C_PORTS) { 166 if (dev_priv->card_type == NV_C0 && entry->read >= NV50_I2C_PORTS) {
167 NV_ERROR(dev, "unknown i2c port %d\n", entry->read); 167 NV_ERROR(dev, "unknown i2c port %d\n", entry->read);
168 return -EINVAL; 168 return -EINVAL;
169 } 169 }
@@ -174,26 +174,26 @@ nouveau_i2c_init(struct drm_device *dev, struct dcb_i2c_entry *entry, int index)
174 174
175 switch (entry->port_type) { 175 switch (entry->port_type) {
176 case 0: 176 case 0:
177 i2c->algo.bit.setsda = nv04_i2c_setsda; 177 i2c->bit.setsda = nv04_i2c_setsda;
178 i2c->algo.bit.setscl = nv04_i2c_setscl; 178 i2c->bit.setscl = nv04_i2c_setscl;
179 i2c->algo.bit.getsda = nv04_i2c_getsda; 179 i2c->bit.getsda = nv04_i2c_getsda;
180 i2c->algo.bit.getscl = nv04_i2c_getscl; 180 i2c->bit.getscl = nv04_i2c_getscl;
181 i2c->rd = entry->read; 181 i2c->rd = entry->read;
182 i2c->wr = entry->write; 182 i2c->wr = entry->write;
183 break; 183 break;
184 case 4: 184 case 4:
185 i2c->algo.bit.setsda = nv4e_i2c_setsda; 185 i2c->bit.setsda = nv4e_i2c_setsda;
186 i2c->algo.bit.setscl = nv4e_i2c_setscl; 186 i2c->bit.setscl = nv4e_i2c_setscl;
187 i2c->algo.bit.getsda = nv4e_i2c_getsda; 187 i2c->bit.getsda = nv4e_i2c_getsda;
188 i2c->algo.bit.getscl = nv4e_i2c_getscl; 188 i2c->bit.getscl = nv4e_i2c_getscl;
189 i2c->rd = 0x600800 + entry->read; 189 i2c->rd = 0x600800 + entry->read;
190 i2c->wr = 0x600800 + entry->write; 190 i2c->wr = 0x600800 + entry->write;
191 break; 191 break;
192 case 5: 192 case 5:
193 i2c->algo.bit.setsda = nv50_i2c_setsda; 193 i2c->bit.setsda = nv50_i2c_setsda;
194 i2c->algo.bit.setscl = nv50_i2c_setscl; 194 i2c->bit.setscl = nv50_i2c_setscl;
195 i2c->algo.bit.getsda = nv50_i2c_getsda; 195 i2c->bit.getsda = nv50_i2c_getsda;
196 i2c->algo.bit.getscl = nv50_i2c_getscl; 196 i2c->bit.getscl = nv50_i2c_getscl;
197 i2c->rd = nv50_i2c_port[entry->read]; 197 i2c->rd = nv50_i2c_port[entry->read];
198 i2c->wr = i2c->rd; 198 i2c->wr = i2c->rd;
199 break; 199 break;
@@ -216,17 +216,14 @@ nouveau_i2c_init(struct drm_device *dev, struct dcb_i2c_entry *entry, int index)
216 i2c_set_adapdata(&i2c->adapter, i2c); 216 i2c_set_adapdata(&i2c->adapter, i2c);
217 217
218 if (entry->port_type < 6) { 218 if (entry->port_type < 6) {
219 i2c->adapter.algo_data = &i2c->algo.bit; 219 i2c->adapter.algo_data = &i2c->bit;
220 i2c->algo.bit.udelay = 40; 220 i2c->bit.udelay = 40;
221 i2c->algo.bit.timeout = usecs_to_jiffies(5000); 221 i2c->bit.timeout = usecs_to_jiffies(5000);
222 i2c->algo.bit.data = i2c; 222 i2c->bit.data = i2c;
223 ret = i2c_bit_add_bus(&i2c->adapter); 223 ret = i2c_bit_add_bus(&i2c->adapter);
224 } else { 224 } else {
225 i2c->adapter.algo_data = &i2c->algo.dp; 225 i2c->adapter.algo = &nouveau_dp_i2c_algo;
226 i2c->algo.dp.running = false; 226 ret = i2c_add_adapter(&i2c->adapter);
227 i2c->algo.dp.address = 0;
228 i2c->algo.dp.aux_ch = nouveau_dp_i2c_aux_ch;
229 ret = i2c_dp_aux_add_bus(&i2c->adapter);
230 } 227 }
231 228
232 if (ret) { 229 if (ret) {
diff --git a/drivers/gpu/drm/nouveau/nouveau_i2c.h b/drivers/gpu/drm/nouveau/nouveau_i2c.h
index 6dd2f8713cd..f71cb32f757 100644
--- a/drivers/gpu/drm/nouveau/nouveau_i2c.h
+++ b/drivers/gpu/drm/nouveau/nouveau_i2c.h
@@ -33,10 +33,7 @@ struct dcb_i2c_entry;
33struct nouveau_i2c_chan { 33struct nouveau_i2c_chan {
34 struct i2c_adapter adapter; 34 struct i2c_adapter adapter;
35 struct drm_device *dev; 35 struct drm_device *dev;
36 union { 36 struct i2c_algo_bit_data bit;
37 struct i2c_algo_bit_data bit;
38 struct i2c_algo_dp_aux_data dp;
39 } algo;
40 unsigned rd; 37 unsigned rd;
41 unsigned wr; 38 unsigned wr;
42 unsigned data; 39 unsigned data;
@@ -49,7 +46,6 @@ bool nouveau_probe_i2c_addr(struct nouveau_i2c_chan *i2c, int addr);
49int nouveau_i2c_identify(struct drm_device *dev, const char *what, 46int nouveau_i2c_identify(struct drm_device *dev, const char *what,
50 struct i2c_board_info *info, int index); 47 struct i2c_board_info *info, int index);
51 48
52int nouveau_dp_i2c_aux_ch(struct i2c_adapter *, int mode, uint8_t write_byte, 49extern const struct i2c_algorithm nouveau_dp_i2c_algo;
53 uint8_t *read_byte);
54 50
55#endif /* __NOUVEAU_I2C_H__ */ 51#endif /* __NOUVEAU_I2C_H__ */
diff --git a/drivers/gpu/drm/nouveau/nouveau_irq.c b/drivers/gpu/drm/nouveau/nouveau_irq.c
index 53360f15606..794b0ee30cf 100644
--- a/drivers/gpu/drm/nouveau/nouveau_irq.c
+++ b/drivers/gpu/drm/nouveau/nouveau_irq.c
@@ -49,7 +49,7 @@ nouveau_irq_preinstall(struct drm_device *dev)
49 /* Master disable */ 49 /* Master disable */
50 nv_wr32(dev, NV03_PMC_INTR_EN_0, 0); 50 nv_wr32(dev, NV03_PMC_INTR_EN_0, 0);
51 51
52 if (dev_priv->card_type == NV_50) { 52 if (dev_priv->card_type >= NV_50) {
53 INIT_WORK(&dev_priv->irq_work, nv50_display_irq_handler_bh); 53 INIT_WORK(&dev_priv->irq_work, nv50_display_irq_handler_bh);
54 INIT_WORK(&dev_priv->hpd_work, nv50_display_irq_hotplug_bh); 54 INIT_WORK(&dev_priv->hpd_work, nv50_display_irq_hotplug_bh);
55 INIT_LIST_HEAD(&dev_priv->vbl_waiting); 55 INIT_LIST_HEAD(&dev_priv->vbl_waiting);
@@ -586,11 +586,11 @@ nouveau_pgraph_irq_handler(struct drm_device *dev)
586 } 586 }
587 587
588 if (status & NV_PGRAPH_INTR_CONTEXT_SWITCH) { 588 if (status & NV_PGRAPH_INTR_CONTEXT_SWITCH) {
589 nouveau_pgraph_intr_context_switch(dev);
590
591 status &= ~NV_PGRAPH_INTR_CONTEXT_SWITCH; 589 status &= ~NV_PGRAPH_INTR_CONTEXT_SWITCH;
592 nv_wr32(dev, NV03_PGRAPH_INTR, 590 nv_wr32(dev, NV03_PGRAPH_INTR,
593 NV_PGRAPH_INTR_CONTEXT_SWITCH); 591 NV_PGRAPH_INTR_CONTEXT_SWITCH);
592
593 nouveau_pgraph_intr_context_switch(dev);
594 } 594 }
595 595
596 if (status) { 596 if (status) {
diff --git a/drivers/gpu/drm/nouveau/nouveau_mem.c b/drivers/gpu/drm/nouveau/nouveau_mem.c
index a9f36ab256b..9689d414768 100644
--- a/drivers/gpu/drm/nouveau/nouveau_mem.c
+++ b/drivers/gpu/drm/nouveau/nouveau_mem.c
@@ -320,7 +320,8 @@ nouveau_mem_detect(struct drm_device *dev)
320 if (dev_priv->card_type < NV_50) { 320 if (dev_priv->card_type < NV_50) {
321 dev_priv->vram_size = nv_rd32(dev, NV04_PFB_FIFO_DATA); 321 dev_priv->vram_size = nv_rd32(dev, NV04_PFB_FIFO_DATA);
322 dev_priv->vram_size &= NV10_PFB_FIFO_DATA_RAM_AMOUNT_MB_MASK; 322 dev_priv->vram_size &= NV10_PFB_FIFO_DATA_RAM_AMOUNT_MB_MASK;
323 } else { 323 } else
324 if (dev_priv->card_type < NV_C0) {
324 dev_priv->vram_size = nv_rd32(dev, NV04_PFB_FIFO_DATA); 325 dev_priv->vram_size = nv_rd32(dev, NV04_PFB_FIFO_DATA);
325 dev_priv->vram_size |= (dev_priv->vram_size & 0xff) << 32; 326 dev_priv->vram_size |= (dev_priv->vram_size & 0xff) << 32;
326 dev_priv->vram_size &= 0xffffffff00ll; 327 dev_priv->vram_size &= 0xffffffff00ll;
@@ -328,6 +329,9 @@ nouveau_mem_detect(struct drm_device *dev)
328 dev_priv->vram_sys_base = nv_rd32(dev, 0x100e10); 329 dev_priv->vram_sys_base = nv_rd32(dev, 0x100e10);
329 dev_priv->vram_sys_base <<= 12; 330 dev_priv->vram_sys_base <<= 12;
330 } 331 }
332 } else {
333 dev_priv->vram_size = nv_rd32(dev, 0x10f20c) << 20;
334 dev_priv->vram_size *= nv_rd32(dev, 0x121c74);
331 } 335 }
332 336
333 NV_INFO(dev, "Detected %dMiB VRAM\n", (int)(dev_priv->vram_size >> 20)); 337 NV_INFO(dev, "Detected %dMiB VRAM\n", (int)(dev_priv->vram_size >> 20));
@@ -351,7 +355,7 @@ nouveau_mem_reset_agp(struct drm_device *dev)
351 /* First of all, disable fast writes, otherwise if it's 355 /* First of all, disable fast writes, otherwise if it's
352 * already enabled in the AGP bridge and we disable the card's 356 * already enabled in the AGP bridge and we disable the card's
353 * AGP controller we might be locking ourselves out of it. */ 357 * AGP controller we might be locking ourselves out of it. */
354 if (dev->agp->acquired) { 358 if (nv_rd32(dev, NV04_PBUS_PCI_NV_19) & PCI_AGP_COMMAND_FW) {
355 struct drm_agp_info info; 359 struct drm_agp_info info;
356 struct drm_agp_mode mode; 360 struct drm_agp_mode mode;
357 361
@@ -359,7 +363,7 @@ nouveau_mem_reset_agp(struct drm_device *dev)
359 if (ret) 363 if (ret)
360 return ret; 364 return ret;
361 365
362 mode.mode = info.mode & ~0x10; 366 mode.mode = info.mode & ~PCI_AGP_COMMAND_FW;
363 ret = drm_agp_enable(dev, mode); 367 ret = drm_agp_enable(dev, mode);
364 if (ret) 368 if (ret)
365 return ret; 369 return ret;
@@ -405,6 +409,8 @@ nouveau_mem_init_agp(struct drm_device *dev)
405 } 409 }
406 } 410 }
407 411
412 nouveau_mem_reset_agp(dev);
413
408 ret = drm_agp_info(dev, &info); 414 ret = drm_agp_info(dev, &info);
409 if (ret) { 415 if (ret) {
410 NV_ERROR(dev, "Unable to get AGP info: %d\n", ret); 416 NV_ERROR(dev, "Unable to get AGP info: %d\n", ret);
@@ -459,8 +465,6 @@ nouveau_mem_init(struct drm_device *dev)
459 return ret; 465 return ret;
460 } 466 }
461 467
462 INIT_LIST_HEAD(&dev_priv->ttm.bo_list);
463 spin_lock_init(&dev_priv->ttm.bo_list_lock);
464 spin_lock_init(&dev_priv->tile.lock); 468 spin_lock_init(&dev_priv->tile.lock);
465 469
466 dev_priv->fb_available_size = dev_priv->vram_size; 470 dev_priv->fb_available_size = dev_priv->vram_size;
@@ -494,7 +498,6 @@ nouveau_mem_init(struct drm_device *dev)
494 /* GART */ 498 /* GART */
495#if !defined(__powerpc__) && !defined(__ia64__) 499#if !defined(__powerpc__) && !defined(__ia64__)
496 if (drm_device_is_agp(dev) && dev->agp && !nouveau_noagp) { 500 if (drm_device_is_agp(dev) && dev->agp && !nouveau_noagp) {
497 nouveau_mem_reset_agp(dev);
498 ret = nouveau_mem_init_agp(dev); 501 ret = nouveau_mem_init_agp(dev);
499 if (ret) 502 if (ret)
500 NV_ERROR(dev, "Error initialising AGP: %d\n", ret); 503 NV_ERROR(dev, "Error initialising AGP: %d\n", ret);
diff --git a/drivers/gpu/drm/nouveau/nouveau_reg.h b/drivers/gpu/drm/nouveau/nouveau_reg.h
index 9c1056cb8a9..21a6e453b97 100644
--- a/drivers/gpu/drm/nouveau/nouveau_reg.h
+++ b/drivers/gpu/drm/nouveau/nouveau_reg.h
@@ -220,28 +220,21 @@
220# define NV_PGRAPH_INTR_ERROR (1<<20) 220# define NV_PGRAPH_INTR_ERROR (1<<20)
221#define NV10_PGRAPH_CTX_CONTROL 0x00400144 221#define NV10_PGRAPH_CTX_CONTROL 0x00400144
222#define NV10_PGRAPH_CTX_USER 0x00400148 222#define NV10_PGRAPH_CTX_USER 0x00400148
223#define NV10_PGRAPH_CTX_SWITCH1 0x0040014C 223#define NV10_PGRAPH_CTX_SWITCH(i) (0x0040014C + 0x4*(i))
224#define NV10_PGRAPH_CTX_SWITCH2 0x00400150
225#define NV10_PGRAPH_CTX_SWITCH3 0x00400154
226#define NV10_PGRAPH_CTX_SWITCH4 0x00400158
227#define NV10_PGRAPH_CTX_SWITCH5 0x0040015C
228#define NV04_PGRAPH_CTX_SWITCH1 0x00400160 224#define NV04_PGRAPH_CTX_SWITCH1 0x00400160
229#define NV10_PGRAPH_CTX_CACHE1 0x00400160 225#define NV10_PGRAPH_CTX_CACHE(i, j) (0x00400160 \
226 + 0x4*(i) + 0x20*(j))
230#define NV04_PGRAPH_CTX_SWITCH2 0x00400164 227#define NV04_PGRAPH_CTX_SWITCH2 0x00400164
231#define NV04_PGRAPH_CTX_SWITCH3 0x00400168 228#define NV04_PGRAPH_CTX_SWITCH3 0x00400168
232#define NV04_PGRAPH_CTX_SWITCH4 0x0040016C 229#define NV04_PGRAPH_CTX_SWITCH4 0x0040016C
233#define NV04_PGRAPH_CTX_CONTROL 0x00400170 230#define NV04_PGRAPH_CTX_CONTROL 0x00400170
234#define NV04_PGRAPH_CTX_USER 0x00400174 231#define NV04_PGRAPH_CTX_USER 0x00400174
235#define NV04_PGRAPH_CTX_CACHE1 0x00400180 232#define NV04_PGRAPH_CTX_CACHE1 0x00400180
236#define NV10_PGRAPH_CTX_CACHE2 0x00400180
237#define NV03_PGRAPH_CTX_CONTROL 0x00400190 233#define NV03_PGRAPH_CTX_CONTROL 0x00400190
238#define NV03_PGRAPH_CTX_USER 0x00400194 234#define NV03_PGRAPH_CTX_USER 0x00400194
239#define NV04_PGRAPH_CTX_CACHE2 0x004001A0 235#define NV04_PGRAPH_CTX_CACHE2 0x004001A0
240#define NV10_PGRAPH_CTX_CACHE3 0x004001A0
241#define NV04_PGRAPH_CTX_CACHE3 0x004001C0 236#define NV04_PGRAPH_CTX_CACHE3 0x004001C0
242#define NV10_PGRAPH_CTX_CACHE4 0x004001C0
243#define NV04_PGRAPH_CTX_CACHE4 0x004001E0 237#define NV04_PGRAPH_CTX_CACHE4 0x004001E0
244#define NV10_PGRAPH_CTX_CACHE5 0x004001E0
245#define NV40_PGRAPH_CTXCTL_0304 0x00400304 238#define NV40_PGRAPH_CTXCTL_0304 0x00400304
246#define NV40_PGRAPH_CTXCTL_0304_XFER_CTX 0x00000001 239#define NV40_PGRAPH_CTXCTL_0304_XFER_CTX 0x00000001
247#define NV40_PGRAPH_CTXCTL_UCODE_STAT 0x00400308 240#define NV40_PGRAPH_CTXCTL_UCODE_STAT 0x00400308
@@ -356,9 +349,12 @@
356#define NV04_PGRAPH_FFINTFC_ST2 0x00400754 349#define NV04_PGRAPH_FFINTFC_ST2 0x00400754
357#define NV10_PGRAPH_RDI_DATA 0x00400754 350#define NV10_PGRAPH_RDI_DATA 0x00400754
358#define NV04_PGRAPH_DMA_PITCH 0x00400760 351#define NV04_PGRAPH_DMA_PITCH 0x00400760
359#define NV10_PGRAPH_FFINTFC_ST2 0x00400764 352#define NV10_PGRAPH_FFINTFC_FIFO_PTR 0x00400760
360#define NV04_PGRAPH_DVD_COLORFMT 0x00400764 353#define NV04_PGRAPH_DVD_COLORFMT 0x00400764
354#define NV10_PGRAPH_FFINTFC_ST2 0x00400764
361#define NV04_PGRAPH_SCALED_FORMAT 0x00400768 355#define NV04_PGRAPH_SCALED_FORMAT 0x00400768
356#define NV10_PGRAPH_FFINTFC_ST2_DL 0x00400768
357#define NV10_PGRAPH_FFINTFC_ST2_DH 0x0040076c
362#define NV10_PGRAPH_DMA_PITCH 0x00400770 358#define NV10_PGRAPH_DMA_PITCH 0x00400770
363#define NV10_PGRAPH_DVD_COLORFMT 0x00400774 359#define NV10_PGRAPH_DVD_COLORFMT 0x00400774
364#define NV10_PGRAPH_SCALED_FORMAT 0x00400778 360#define NV10_PGRAPH_SCALED_FORMAT 0x00400778
diff --git a/drivers/gpu/drm/nouveau/nouveau_state.c b/drivers/gpu/drm/nouveau/nouveau_state.c
index ee3729e7823..989322be372 100644
--- a/drivers/gpu/drm/nouveau/nouveau_state.c
+++ b/drivers/gpu/drm/nouveau/nouveau_state.c
@@ -359,6 +359,54 @@ static int nouveau_init_engine_ptrs(struct drm_device *dev)
359 engine->gpio.set = nv50_gpio_set; 359 engine->gpio.set = nv50_gpio_set;
360 engine->gpio.irq_enable = nv50_gpio_irq_enable; 360 engine->gpio.irq_enable = nv50_gpio_irq_enable;
361 break; 361 break;
362 case 0xC0:
363 engine->instmem.init = nvc0_instmem_init;
364 engine->instmem.takedown = nvc0_instmem_takedown;
365 engine->instmem.suspend = nvc0_instmem_suspend;
366 engine->instmem.resume = nvc0_instmem_resume;
367 engine->instmem.populate = nvc0_instmem_populate;
368 engine->instmem.clear = nvc0_instmem_clear;
369 engine->instmem.bind = nvc0_instmem_bind;
370 engine->instmem.unbind = nvc0_instmem_unbind;
371 engine->instmem.flush = nvc0_instmem_flush;
372 engine->mc.init = nv50_mc_init;
373 engine->mc.takedown = nv50_mc_takedown;
374 engine->timer.init = nv04_timer_init;
375 engine->timer.read = nv04_timer_read;
376 engine->timer.takedown = nv04_timer_takedown;
377 engine->fb.init = nvc0_fb_init;
378 engine->fb.takedown = nvc0_fb_takedown;
379 engine->graph.grclass = NULL; //nvc0_graph_grclass;
380 engine->graph.init = nvc0_graph_init;
381 engine->graph.takedown = nvc0_graph_takedown;
382 engine->graph.fifo_access = nvc0_graph_fifo_access;
383 engine->graph.channel = nvc0_graph_channel;
384 engine->graph.create_context = nvc0_graph_create_context;
385 engine->graph.destroy_context = nvc0_graph_destroy_context;
386 engine->graph.load_context = nvc0_graph_load_context;
387 engine->graph.unload_context = nvc0_graph_unload_context;
388 engine->fifo.channels = 128;
389 engine->fifo.init = nvc0_fifo_init;
390 engine->fifo.takedown = nvc0_fifo_takedown;
391 engine->fifo.disable = nvc0_fifo_disable;
392 engine->fifo.enable = nvc0_fifo_enable;
393 engine->fifo.reassign = nvc0_fifo_reassign;
394 engine->fifo.channel_id = nvc0_fifo_channel_id;
395 engine->fifo.create_context = nvc0_fifo_create_context;
396 engine->fifo.destroy_context = nvc0_fifo_destroy_context;
397 engine->fifo.load_context = nvc0_fifo_load_context;
398 engine->fifo.unload_context = nvc0_fifo_unload_context;
399 engine->display.early_init = nv50_display_early_init;
400 engine->display.late_takedown = nv50_display_late_takedown;
401 engine->display.create = nv50_display_create;
402 engine->display.init = nv50_display_init;
403 engine->display.destroy = nv50_display_destroy;
404 engine->gpio.init = nv50_gpio_init;
405 engine->gpio.takedown = nouveau_stub_takedown;
406 engine->gpio.get = nv50_gpio_get;
407 engine->gpio.set = nv50_gpio_set;
408 engine->gpio.irq_enable = nv50_gpio_irq_enable;
409 break;
362 default: 410 default:
363 NV_ERROR(dev, "NV%02x unsupported\n", dev_priv->chipset); 411 NV_ERROR(dev, "NV%02x unsupported\n", dev_priv->chipset);
364 return 1; 412 return 1;
@@ -739,8 +787,10 @@ int nouveau_load(struct drm_device *dev, unsigned long flags)
739 int ret; 787 int ret;
740 788
741 dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL); 789 dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
742 if (!dev_priv) 790 if (!dev_priv) {
743 return -ENOMEM; 791 ret = -ENOMEM;
792 goto err_out;
793 }
744 dev->dev_private = dev_priv; 794 dev->dev_private = dev_priv;
745 dev_priv->dev = dev; 795 dev_priv->dev = dev;
746 796
@@ -750,8 +800,10 @@ int nouveau_load(struct drm_device *dev, unsigned long flags)
750 dev->pci_vendor, dev->pci_device, dev->pdev->class); 800 dev->pci_vendor, dev->pci_device, dev->pdev->class);
751 801
752 dev_priv->wq = create_workqueue("nouveau"); 802 dev_priv->wq = create_workqueue("nouveau");
753 if (!dev_priv->wq) 803 if (!dev_priv->wq) {
754 return -EINVAL; 804 ret = -EINVAL;
805 goto err_priv;
806 }
755 807
756 /* resource 0 is mmio regs */ 808 /* resource 0 is mmio regs */
757 /* resource 1 is linear FB */ 809 /* resource 1 is linear FB */
@@ -764,7 +816,8 @@ int nouveau_load(struct drm_device *dev, unsigned long flags)
764 if (!dev_priv->mmio) { 816 if (!dev_priv->mmio) {
765 NV_ERROR(dev, "Unable to initialize the mmio mapping. " 817 NV_ERROR(dev, "Unable to initialize the mmio mapping. "
766 "Please report your setup to " DRIVER_EMAIL "\n"); 818 "Please report your setup to " DRIVER_EMAIL "\n");
767 return -EINVAL; 819 ret = -EINVAL;
820 goto err_wq;
768 } 821 }
769 NV_DEBUG(dev, "regs mapped ok at 0x%llx\n", 822 NV_DEBUG(dev, "regs mapped ok at 0x%llx\n",
770 (unsigned long long)mmio_start_offs); 823 (unsigned long long)mmio_start_offs);
@@ -810,9 +863,13 @@ int nouveau_load(struct drm_device *dev, unsigned long flags)
810 case 0xa0: 863 case 0xa0:
811 dev_priv->card_type = NV_50; 864 dev_priv->card_type = NV_50;
812 break; 865 break;
866 case 0xc0:
867 dev_priv->card_type = NV_C0;
868 break;
813 default: 869 default:
814 NV_INFO(dev, "Unsupported chipset 0x%08x\n", reg0); 870 NV_INFO(dev, "Unsupported chipset 0x%08x\n", reg0);
815 return -EINVAL; 871 ret = -EINVAL;
872 goto err_mmio;
816 } 873 }
817 874
818 NV_INFO(dev, "Detected an NV%2x generation card (0x%08x)\n", 875 NV_INFO(dev, "Detected an NV%2x generation card (0x%08x)\n",
@@ -820,7 +877,7 @@ int nouveau_load(struct drm_device *dev, unsigned long flags)
820 877
821 ret = nouveau_remove_conflicting_drivers(dev); 878 ret = nouveau_remove_conflicting_drivers(dev);
822 if (ret) 879 if (ret)
823 return ret; 880 goto err_mmio;
824 881
825 /* Map PRAMIN BAR, or on older cards, the aperture withing BAR0 */ 882 /* Map PRAMIN BAR, or on older cards, the aperture withing BAR0 */
826 if (dev_priv->card_type >= NV_40) { 883 if (dev_priv->card_type >= NV_40) {
@@ -834,7 +891,8 @@ int nouveau_load(struct drm_device *dev, unsigned long flags)
834 dev_priv->ramin_size); 891 dev_priv->ramin_size);
835 if (!dev_priv->ramin) { 892 if (!dev_priv->ramin) {
836 NV_ERROR(dev, "Failed to PRAMIN BAR"); 893 NV_ERROR(dev, "Failed to PRAMIN BAR");
837 return -ENOMEM; 894 ret = -ENOMEM;
895 goto err_mmio;
838 } 896 }
839 } else { 897 } else {
840 dev_priv->ramin_size = 1 * 1024 * 1024; 898 dev_priv->ramin_size = 1 * 1024 * 1024;
@@ -842,7 +900,8 @@ int nouveau_load(struct drm_device *dev, unsigned long flags)
842 dev_priv->ramin_size); 900 dev_priv->ramin_size);
843 if (!dev_priv->ramin) { 901 if (!dev_priv->ramin) {
844 NV_ERROR(dev, "Failed to map BAR0 PRAMIN.\n"); 902 NV_ERROR(dev, "Failed to map BAR0 PRAMIN.\n");
845 return -ENOMEM; 903 ret = -ENOMEM;
904 goto err_mmio;
846 } 905 }
847 } 906 }
848 907
@@ -857,9 +916,21 @@ int nouveau_load(struct drm_device *dev, unsigned long flags)
857 /* For kernel modesetting, init card now and bring up fbcon */ 916 /* For kernel modesetting, init card now and bring up fbcon */
858 ret = nouveau_card_init(dev); 917 ret = nouveau_card_init(dev);
859 if (ret) 918 if (ret)
860 return ret; 919 goto err_ramin;
861 920
862 return 0; 921 return 0;
922
923err_ramin:
924 iounmap(dev_priv->ramin);
925err_mmio:
926 iounmap(dev_priv->mmio);
927err_wq:
928 destroy_workqueue(dev_priv->wq);
929err_priv:
930 kfree(dev_priv);
931 dev->dev_private = NULL;
932err_out:
933 return ret;
863} 934}
864 935
865void nouveau_lastclose(struct drm_device *dev) 936void nouveau_lastclose(struct drm_device *dev)
diff --git a/drivers/gpu/drm/nouveau/nv04_crtc.c b/drivers/gpu/drm/nouveau/nv04_crtc.c
index 1c20c08ce67..497df8765f2 100644
--- a/drivers/gpu/drm/nouveau/nv04_crtc.c
+++ b/drivers/gpu/drm/nouveau/nv04_crtc.c
@@ -542,6 +542,9 @@ nv_crtc_mode_set_regs(struct drm_crtc *crtc, struct drm_display_mode * mode)
542 * 1 << 30 on 0x60.830), for no apparent reason */ 542 * 1 << 30 on 0x60.830), for no apparent reason */
543 regp->CRTC[NV_CIO_CRE_59] = off_chip_digital; 543 regp->CRTC[NV_CIO_CRE_59] = off_chip_digital;
544 544
545 if (dev_priv->card_type >= NV_30)
546 regp->CRTC[0x9f] = off_chip_digital ? 0x11 : 0x1;
547
545 regp->crtc_830 = mode->crtc_vdisplay - 3; 548 regp->crtc_830 = mode->crtc_vdisplay - 3;
546 regp->crtc_834 = mode->crtc_vdisplay - 1; 549 regp->crtc_834 = mode->crtc_vdisplay - 1;
547 550
@@ -739,15 +742,13 @@ nv_crtc_gamma_load(struct drm_crtc *crtc)
739} 742}
740 743
741static void 744static void
742nv_crtc_gamma_set(struct drm_crtc *crtc, u16 *r, u16 *g, u16 *b, uint32_t size) 745nv_crtc_gamma_set(struct drm_crtc *crtc, u16 *r, u16 *g, u16 *b, uint32_t start,
746 uint32_t size)
743{ 747{
748 int end = (start + size > 256) ? 256 : start + size, i;
744 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 749 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
745 int i;
746 750
747 if (size != 256) 751 for (i = start; i < end; i++) {
748 return;
749
750 for (i = 0; i < 256; i++) {
751 nv_crtc->lut.r[i] = r[i]; 752 nv_crtc->lut.r[i] = r[i];
752 nv_crtc->lut.g[i] = g[i]; 753 nv_crtc->lut.g[i] = g[i];
753 nv_crtc->lut.b[i] = b[i]; 754 nv_crtc->lut.b[i] = b[i];
@@ -914,7 +915,7 @@ nv04_crtc_cursor_set(struct drm_crtc *crtc, struct drm_file *file_priv,
914 915
915 gem = drm_gem_object_lookup(dev, file_priv, buffer_handle); 916 gem = drm_gem_object_lookup(dev, file_priv, buffer_handle);
916 if (!gem) 917 if (!gem)
917 return -EINVAL; 918 return -ENOENT;
918 cursor = nouveau_gem_object(gem); 919 cursor = nouveau_gem_object(gem);
919 920
920 ret = nouveau_bo_map(cursor); 921 ret = nouveau_bo_map(cursor);
diff --git a/drivers/gpu/drm/nouveau/nv04_dfp.c b/drivers/gpu/drm/nouveau/nv04_dfp.c
index 3311f3a8c81..a5dcf768580 100644
--- a/drivers/gpu/drm/nouveau/nv04_dfp.c
+++ b/drivers/gpu/drm/nouveau/nv04_dfp.c
@@ -34,6 +34,8 @@
34#include "nouveau_hw.h" 34#include "nouveau_hw.h"
35#include "nvreg.h" 35#include "nvreg.h"
36 36
37#include "i2c/sil164.h"
38
37#define FP_TG_CONTROL_ON (NV_PRAMDAC_FP_TG_CONTROL_DISPEN_POS | \ 39#define FP_TG_CONTROL_ON (NV_PRAMDAC_FP_TG_CONTROL_DISPEN_POS | \
38 NV_PRAMDAC_FP_TG_CONTROL_HSYNC_POS | \ 40 NV_PRAMDAC_FP_TG_CONTROL_HSYNC_POS | \
39 NV_PRAMDAC_FP_TG_CONTROL_VSYNC_POS) 41 NV_PRAMDAC_FP_TG_CONTROL_VSYNC_POS)
@@ -144,6 +146,36 @@ void nv04_dfp_update_fp_control(struct drm_encoder *encoder, int mode)
144 } 146 }
145} 147}
146 148
149static struct drm_encoder *get_tmds_slave(struct drm_encoder *encoder)
150{
151 struct drm_device *dev = encoder->dev;
152 struct dcb_entry *dcb = nouveau_encoder(encoder)->dcb;
153 struct drm_encoder *slave;
154
155 if (dcb->type != OUTPUT_TMDS || dcb->location == DCB_LOC_ON_CHIP)
156 return NULL;
157
158 /* Some BIOSes (e.g. the one in a Quadro FX1000) report several
159 * TMDS transmitters at the same I2C address, in the same I2C
160 * bus. This can still work because in that case one of them is
161 * always hard-wired to a reasonable configuration using straps,
162 * and the other one needs to be programmed.
163 *
164 * I don't think there's a way to know which is which, even the
165 * blob programs the one exposed via I2C for *both* heads, so
166 * let's do the same.
167 */
168 list_for_each_entry(slave, &dev->mode_config.encoder_list, head) {
169 struct dcb_entry *slave_dcb = nouveau_encoder(slave)->dcb;
170
171 if (slave_dcb->type == OUTPUT_TMDS && get_slave_funcs(slave) &&
172 slave_dcb->tmdsconf.slave_addr == dcb->tmdsconf.slave_addr)
173 return slave;
174 }
175
176 return NULL;
177}
178
147static bool nv04_dfp_mode_fixup(struct drm_encoder *encoder, 179static bool nv04_dfp_mode_fixup(struct drm_encoder *encoder,
148 struct drm_display_mode *mode, 180 struct drm_display_mode *mode,
149 struct drm_display_mode *adjusted_mode) 181 struct drm_display_mode *adjusted_mode)
@@ -429,6 +461,11 @@ static void nv04_dfp_commit(struct drm_encoder *encoder)
429 else 461 else
430 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + nv04_dac_output_offset(encoder), 0x00100000); 462 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + nv04_dac_output_offset(encoder), 0x00100000);
431 463
464 /* Init external transmitters */
465 if (get_tmds_slave(encoder))
466 get_slave_funcs(get_tmds_slave(encoder))->mode_set(
467 encoder, &nv_encoder->mode, &nv_encoder->mode);
468
432 helper->dpms(encoder, DRM_MODE_DPMS_ON); 469 helper->dpms(encoder, DRM_MODE_DPMS_ON);
433 470
434 NV_INFO(dev, "Output %s is running on CRTC %d using output %c\n", 471 NV_INFO(dev, "Output %s is running on CRTC %d using output %c\n",
@@ -550,10 +587,42 @@ static void nv04_dfp_destroy(struct drm_encoder *encoder)
550 587
551 NV_DEBUG_KMS(encoder->dev, "\n"); 588 NV_DEBUG_KMS(encoder->dev, "\n");
552 589
590 if (get_slave_funcs(encoder))
591 get_slave_funcs(encoder)->destroy(encoder);
592
553 drm_encoder_cleanup(encoder); 593 drm_encoder_cleanup(encoder);
554 kfree(nv_encoder); 594 kfree(nv_encoder);
555} 595}
556 596
597static void nv04_tmds_slave_init(struct drm_encoder *encoder)
598{
599 struct drm_device *dev = encoder->dev;
600 struct dcb_entry *dcb = nouveau_encoder(encoder)->dcb;
601 struct nouveau_i2c_chan *i2c = nouveau_i2c_find(dev, 2);
602 struct i2c_board_info info[] = {
603 {
604 .type = "sil164",
605 .addr = (dcb->tmdsconf.slave_addr == 0x7 ? 0x3a : 0x38),
606 .platform_data = &(struct sil164_encoder_params) {
607 SIL164_INPUT_EDGE_RISING
608 }
609 },
610 { }
611 };
612 int type;
613
614 if (!nv_gf4_disp_arch(dev) || !i2c ||
615 get_tmds_slave(encoder))
616 return;
617
618 type = nouveau_i2c_identify(dev, "TMDS transmitter", info, 2);
619 if (type < 0)
620 return;
621
622 drm_i2c_encoder_init(dev, to_encoder_slave(encoder),
623 &i2c->adapter, &info[type]);
624}
625
557static const struct drm_encoder_helper_funcs nv04_lvds_helper_funcs = { 626static const struct drm_encoder_helper_funcs nv04_lvds_helper_funcs = {
558 .dpms = nv04_lvds_dpms, 627 .dpms = nv04_lvds_dpms,
559 .save = nv04_dfp_save, 628 .save = nv04_dfp_save,
@@ -616,6 +685,10 @@ nv04_dfp_create(struct drm_connector *connector, struct dcb_entry *entry)
616 encoder->possible_crtcs = entry->heads; 685 encoder->possible_crtcs = entry->heads;
617 encoder->possible_clones = 0; 686 encoder->possible_clones = 0;
618 687
688 if (entry->type == OUTPUT_TMDS &&
689 entry->location != DCB_LOC_ON_CHIP)
690 nv04_tmds_slave_init(encoder);
691
619 drm_mode_connector_attach_encoder(connector, encoder); 692 drm_mode_connector_attach_encoder(connector, encoder);
620 return 0; 693 return 0;
621} 694}
diff --git a/drivers/gpu/drm/nouveau/nv04_tv.c b/drivers/gpu/drm/nouveau/nv04_tv.c
index 94e299cef0b..0b5d012d7c2 100644
--- a/drivers/gpu/drm/nouveau/nv04_tv.c
+++ b/drivers/gpu/drm/nouveau/nv04_tv.c
@@ -89,7 +89,7 @@ static void nv04_tv_dpms(struct drm_encoder *encoder, int mode)
89 89
90 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_PLL_COEFF_SELECT, state->pllsel); 90 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_PLL_COEFF_SELECT, state->pllsel);
91 91
92 to_encoder_slave(encoder)->slave_funcs->dpms(encoder, mode); 92 get_slave_funcs(encoder)->dpms(encoder, mode);
93} 93}
94 94
95static void nv04_tv_bind(struct drm_device *dev, int head, bool bind) 95static void nv04_tv_bind(struct drm_device *dev, int head, bool bind)
@@ -152,7 +152,7 @@ static void nv04_tv_mode_set(struct drm_encoder *encoder,
152 regp->tv_vskew = 1; 152 regp->tv_vskew = 1;
153 regp->tv_vsync_delay = 1; 153 regp->tv_vsync_delay = 1;
154 154
155 to_encoder_slave(encoder)->slave_funcs->mode_set(encoder, mode, adjusted_mode); 155 get_slave_funcs(encoder)->mode_set(encoder, mode, adjusted_mode);
156} 156}
157 157
158static void nv04_tv_commit(struct drm_encoder *encoder) 158static void nv04_tv_commit(struct drm_encoder *encoder)
@@ -171,8 +171,7 @@ static void nv04_tv_commit(struct drm_encoder *encoder)
171 171
172static void nv04_tv_destroy(struct drm_encoder *encoder) 172static void nv04_tv_destroy(struct drm_encoder *encoder)
173{ 173{
174 to_encoder_slave(encoder)->slave_funcs->destroy(encoder); 174 get_slave_funcs(encoder)->destroy(encoder);
175
176 drm_encoder_cleanup(encoder); 175 drm_encoder_cleanup(encoder);
177 176
178 kfree(encoder->helper_private); 177 kfree(encoder->helper_private);
@@ -229,7 +228,7 @@ nv04_tv_create(struct drm_connector *connector, struct dcb_entry *entry)
229 goto fail_cleanup; 228 goto fail_cleanup;
230 229
231 /* Fill the function pointers */ 230 /* Fill the function pointers */
232 sfuncs = to_encoder_slave(encoder)->slave_funcs; 231 sfuncs = get_slave_funcs(encoder);
233 232
234 *hfuncs = (struct drm_encoder_helper_funcs) { 233 *hfuncs = (struct drm_encoder_helper_funcs) {
235 .dpms = nv04_tv_dpms, 234 .dpms = nv04_tv_dpms,
@@ -243,7 +242,6 @@ nv04_tv_create(struct drm_connector *connector, struct dcb_entry *entry)
243 }; 242 };
244 243
245 /* Attach it to the specified connector. */ 244 /* Attach it to the specified connector. */
246 sfuncs->set_config(encoder, nv04_tv_encoder_info[type].platform_data);
247 sfuncs->create_resources(encoder, connector); 245 sfuncs->create_resources(encoder, connector);
248 drm_mode_connector_attach_encoder(connector, encoder); 246 drm_mode_connector_attach_encoder(connector, encoder);
249 247
diff --git a/drivers/gpu/drm/nouveau/nv10_graph.c b/drivers/gpu/drm/nouveau/nv10_graph.c
index fcf2cdd1949..b2f6a57c0cc 100644
--- a/drivers/gpu/drm/nouveau/nv10_graph.c
+++ b/drivers/gpu/drm/nouveau/nv10_graph.c
@@ -43,51 +43,51 @@ struct pipe_state {
43}; 43};
44 44
45static int nv10_graph_ctx_regs[] = { 45static int nv10_graph_ctx_regs[] = {
46 NV10_PGRAPH_CTX_SWITCH1, 46 NV10_PGRAPH_CTX_SWITCH(0),
47 NV10_PGRAPH_CTX_SWITCH2, 47 NV10_PGRAPH_CTX_SWITCH(1),
48 NV10_PGRAPH_CTX_SWITCH3, 48 NV10_PGRAPH_CTX_SWITCH(2),
49 NV10_PGRAPH_CTX_SWITCH4, 49 NV10_PGRAPH_CTX_SWITCH(3),
50 NV10_PGRAPH_CTX_SWITCH5, 50 NV10_PGRAPH_CTX_SWITCH(4),
51 NV10_PGRAPH_CTX_CACHE1, /* 8 values from 0x400160 to 0x40017c */ 51 NV10_PGRAPH_CTX_CACHE(0, 0),
52 NV10_PGRAPH_CTX_CACHE2, /* 8 values from 0x400180 to 0x40019c */ 52 NV10_PGRAPH_CTX_CACHE(0, 1),
53 NV10_PGRAPH_CTX_CACHE3, /* 8 values from 0x4001a0 to 0x4001bc */ 53 NV10_PGRAPH_CTX_CACHE(0, 2),
54 NV10_PGRAPH_CTX_CACHE4, /* 8 values from 0x4001c0 to 0x4001dc */ 54 NV10_PGRAPH_CTX_CACHE(0, 3),
55 NV10_PGRAPH_CTX_CACHE5, /* 8 values from 0x4001e0 to 0x4001fc */ 55 NV10_PGRAPH_CTX_CACHE(0, 4),
56 0x00400164, 56 NV10_PGRAPH_CTX_CACHE(1, 0),
57 0x00400184, 57 NV10_PGRAPH_CTX_CACHE(1, 1),
58 0x004001a4, 58 NV10_PGRAPH_CTX_CACHE(1, 2),
59 0x004001c4, 59 NV10_PGRAPH_CTX_CACHE(1, 3),
60 0x004001e4, 60 NV10_PGRAPH_CTX_CACHE(1, 4),
61 0x00400168, 61 NV10_PGRAPH_CTX_CACHE(2, 0),
62 0x00400188, 62 NV10_PGRAPH_CTX_CACHE(2, 1),
63 0x004001a8, 63 NV10_PGRAPH_CTX_CACHE(2, 2),
64 0x004001c8, 64 NV10_PGRAPH_CTX_CACHE(2, 3),
65 0x004001e8, 65 NV10_PGRAPH_CTX_CACHE(2, 4),
66 0x0040016c, 66 NV10_PGRAPH_CTX_CACHE(3, 0),
67 0x0040018c, 67 NV10_PGRAPH_CTX_CACHE(3, 1),
68 0x004001ac, 68 NV10_PGRAPH_CTX_CACHE(3, 2),
69 0x004001cc, 69 NV10_PGRAPH_CTX_CACHE(3, 3),
70 0x004001ec, 70 NV10_PGRAPH_CTX_CACHE(3, 4),
71 0x00400170, 71 NV10_PGRAPH_CTX_CACHE(4, 0),
72 0x00400190, 72 NV10_PGRAPH_CTX_CACHE(4, 1),
73 0x004001b0, 73 NV10_PGRAPH_CTX_CACHE(4, 2),
74 0x004001d0, 74 NV10_PGRAPH_CTX_CACHE(4, 3),
75 0x004001f0, 75 NV10_PGRAPH_CTX_CACHE(4, 4),
76 0x00400174, 76 NV10_PGRAPH_CTX_CACHE(5, 0),
77 0x00400194, 77 NV10_PGRAPH_CTX_CACHE(5, 1),
78 0x004001b4, 78 NV10_PGRAPH_CTX_CACHE(5, 2),
79 0x004001d4, 79 NV10_PGRAPH_CTX_CACHE(5, 3),
80 0x004001f4, 80 NV10_PGRAPH_CTX_CACHE(5, 4),
81 0x00400178, 81 NV10_PGRAPH_CTX_CACHE(6, 0),
82 0x00400198, 82 NV10_PGRAPH_CTX_CACHE(6, 1),
83 0x004001b8, 83 NV10_PGRAPH_CTX_CACHE(6, 2),
84 0x004001d8, 84 NV10_PGRAPH_CTX_CACHE(6, 3),
85 0x004001f8, 85 NV10_PGRAPH_CTX_CACHE(6, 4),
86 0x0040017c, 86 NV10_PGRAPH_CTX_CACHE(7, 0),
87 0x0040019c, 87 NV10_PGRAPH_CTX_CACHE(7, 1),
88 0x004001bc, 88 NV10_PGRAPH_CTX_CACHE(7, 2),
89 0x004001dc, 89 NV10_PGRAPH_CTX_CACHE(7, 3),
90 0x004001fc, 90 NV10_PGRAPH_CTX_CACHE(7, 4),
91 NV10_PGRAPH_CTX_USER, 91 NV10_PGRAPH_CTX_USER,
92 NV04_PGRAPH_DMA_START_0, 92 NV04_PGRAPH_DMA_START_0,
93 NV04_PGRAPH_DMA_START_1, 93 NV04_PGRAPH_DMA_START_1,
@@ -653,6 +653,78 @@ static int nv17_graph_ctx_regs_find_offset(struct drm_device *dev, int reg)
653 return -1; 653 return -1;
654} 654}
655 655
656static void nv10_graph_load_dma_vtxbuf(struct nouveau_channel *chan,
657 uint32_t inst)
658{
659 struct drm_device *dev = chan->dev;
660 struct drm_nouveau_private *dev_priv = dev->dev_private;
661 struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
662 uint32_t st2, st2_dl, st2_dh, fifo_ptr, fifo[0x60/4];
663 uint32_t ctx_user, ctx_switch[5];
664 int i, subchan = -1;
665
666 /* NV10TCL_DMA_VTXBUF (method 0x18c) modifies hidden state
667 * that cannot be restored via MMIO. Do it through the FIFO
668 * instead.
669 */
670
671 /* Look for a celsius object */
672 for (i = 0; i < 8; i++) {
673 int class = nv_rd32(dev, NV10_PGRAPH_CTX_CACHE(i, 0)) & 0xfff;
674
675 if (class == 0x56 || class == 0x96 || class == 0x99) {
676 subchan = i;
677 break;
678 }
679 }
680
681 if (subchan < 0 || !inst)
682 return;
683
684 /* Save the current ctx object */
685 ctx_user = nv_rd32(dev, NV10_PGRAPH_CTX_USER);
686 for (i = 0; i < 5; i++)
687 ctx_switch[i] = nv_rd32(dev, NV10_PGRAPH_CTX_SWITCH(i));
688
689 /* Save the FIFO state */
690 st2 = nv_rd32(dev, NV10_PGRAPH_FFINTFC_ST2);
691 st2_dl = nv_rd32(dev, NV10_PGRAPH_FFINTFC_ST2_DL);
692 st2_dh = nv_rd32(dev, NV10_PGRAPH_FFINTFC_ST2_DH);
693 fifo_ptr = nv_rd32(dev, NV10_PGRAPH_FFINTFC_FIFO_PTR);
694
695 for (i = 0; i < ARRAY_SIZE(fifo); i++)
696 fifo[i] = nv_rd32(dev, 0x4007a0 + 4 * i);
697
698 /* Switch to the celsius subchannel */
699 for (i = 0; i < 5; i++)
700 nv_wr32(dev, NV10_PGRAPH_CTX_SWITCH(i),
701 nv_rd32(dev, NV10_PGRAPH_CTX_CACHE(subchan, i)));
702 nv_mask(dev, NV10_PGRAPH_CTX_USER, 0xe000, subchan << 13);
703
704 /* Inject NV10TCL_DMA_VTXBUF */
705 nv_wr32(dev, NV10_PGRAPH_FFINTFC_FIFO_PTR, 0);
706 nv_wr32(dev, NV10_PGRAPH_FFINTFC_ST2,
707 0x2c000000 | chan->id << 20 | subchan << 16 | 0x18c);
708 nv_wr32(dev, NV10_PGRAPH_FFINTFC_ST2_DL, inst);
709 nv_mask(dev, NV10_PGRAPH_CTX_CONTROL, 0, 0x10000);
710 pgraph->fifo_access(dev, true);
711 pgraph->fifo_access(dev, false);
712
713 /* Restore the FIFO state */
714 for (i = 0; i < ARRAY_SIZE(fifo); i++)
715 nv_wr32(dev, 0x4007a0 + 4 * i, fifo[i]);
716
717 nv_wr32(dev, NV10_PGRAPH_FFINTFC_FIFO_PTR, fifo_ptr);
718 nv_wr32(dev, NV10_PGRAPH_FFINTFC_ST2, st2);
719 nv_wr32(dev, NV10_PGRAPH_FFINTFC_ST2_DL, st2_dl);
720 nv_wr32(dev, NV10_PGRAPH_FFINTFC_ST2_DH, st2_dh);
721
722 /* Restore the current ctx object */
723 for (i = 0; i < 5; i++)
724 nv_wr32(dev, NV10_PGRAPH_CTX_SWITCH(i), ctx_switch[i]);
725 nv_wr32(dev, NV10_PGRAPH_CTX_USER, ctx_user);
726}
727
656int nv10_graph_load_context(struct nouveau_channel *chan) 728int nv10_graph_load_context(struct nouveau_channel *chan)
657{ 729{
658 struct drm_device *dev = chan->dev; 730 struct drm_device *dev = chan->dev;
@@ -670,6 +742,8 @@ int nv10_graph_load_context(struct nouveau_channel *chan)
670 } 742 }
671 743
672 nv10_graph_load_pipe(chan); 744 nv10_graph_load_pipe(chan);
745 nv10_graph_load_dma_vtxbuf(chan, (nv_rd32(dev, NV10_PGRAPH_GLOBALSTATE1)
746 & 0xffff));
673 747
674 nv_wr32(dev, NV10_PGRAPH_CTX_CONTROL, 0x10010100); 748 nv_wr32(dev, NV10_PGRAPH_CTX_CONTROL, 0x10010100);
675 tmp = nv_rd32(dev, NV10_PGRAPH_CTX_USER); 749 tmp = nv_rd32(dev, NV10_PGRAPH_CTX_USER);
@@ -856,11 +930,12 @@ int nv10_graph_init(struct drm_device *dev)
856 for (i = 0; i < NV10_PFB_TILE__SIZE; i++) 930 for (i = 0; i < NV10_PFB_TILE__SIZE; i++)
857 nv10_graph_set_region_tiling(dev, i, 0, 0, 0); 931 nv10_graph_set_region_tiling(dev, i, 0, 0, 0);
858 932
859 nv_wr32(dev, NV10_PGRAPH_CTX_SWITCH1, 0x00000000); 933 nv_wr32(dev, NV10_PGRAPH_CTX_SWITCH(0), 0x00000000);
860 nv_wr32(dev, NV10_PGRAPH_CTX_SWITCH2, 0x00000000); 934 nv_wr32(dev, NV10_PGRAPH_CTX_SWITCH(1), 0x00000000);
861 nv_wr32(dev, NV10_PGRAPH_CTX_SWITCH3, 0x00000000); 935 nv_wr32(dev, NV10_PGRAPH_CTX_SWITCH(2), 0x00000000);
862 nv_wr32(dev, NV10_PGRAPH_CTX_SWITCH4, 0x00000000); 936 nv_wr32(dev, NV10_PGRAPH_CTX_SWITCH(3), 0x00000000);
863 nv_wr32(dev, NV10_PGRAPH_STATE , 0xFFFFFFFF); 937 nv_wr32(dev, NV10_PGRAPH_CTX_SWITCH(4), 0x00000000);
938 nv_wr32(dev, NV10_PGRAPH_STATE, 0xFFFFFFFF);
864 939
865 tmp = nv_rd32(dev, NV10_PGRAPH_CTX_USER) & 0x00ffffff; 940 tmp = nv_rd32(dev, NV10_PGRAPH_CTX_USER) & 0x00ffffff;
866 tmp |= (dev_priv->engine.fifo.channels - 1) << 24; 941 tmp |= (dev_priv->engine.fifo.channels - 1) << 24;
diff --git a/drivers/gpu/drm/nouveau/nv30_fb.c b/drivers/gpu/drm/nouveau/nv30_fb.c
index 9d35c8b3b83..4a3f2f09512 100644
--- a/drivers/gpu/drm/nouveau/nv30_fb.c
+++ b/drivers/gpu/drm/nouveau/nv30_fb.c
@@ -30,15 +30,25 @@
30#include "nouveau_drm.h" 30#include "nouveau_drm.h"
31 31
32static int 32static int
33calc_ref(int b, int l, int i) 33calc_bias(struct drm_device *dev, int k, int i, int j)
34{
35 struct drm_nouveau_private *dev_priv = dev->dev_private;
36 int b = (dev_priv->chipset > 0x30 ?
37 nv_rd32(dev, 0x122c + 0x10 * k + 0x4 * j) >> (4 * (i ^ 1)) :
38 0) & 0xf;
39
40 return 2 * (b & 0x8 ? b - 0x10 : b);
41}
42
43static int
44calc_ref(struct drm_device *dev, int l, int k, int i)
34{ 45{
35 int j, x = 0; 46 int j, x = 0;
36 47
37 for (j = 0; j < 4; j++) { 48 for (j = 0; j < 4; j++) {
38 int n = (b >> (8 * j) & 0xf); 49 int m = (l >> (8 * i) & 0xff) + calc_bias(dev, k, i, j);
39 int m = (l >> (8 * i) & 0xff) + 2 * (n & 0x8 ? n - 0x10 : n);
40 50
41 x |= (0x80 | (m & 0x1f)) << (8 * j); 51 x |= (0x80 | clamp(m, 0, 0x1f)) << (8 * j);
42 } 52 }
43 53
44 return x; 54 return x;
@@ -63,18 +73,16 @@ nv30_fb_init(struct drm_device *dev)
63 dev_priv->chipset == 0x35) { 73 dev_priv->chipset == 0x35) {
64 /* Related to ROP count */ 74 /* Related to ROP count */
65 int n = (dev_priv->chipset == 0x31 ? 2 : 4); 75 int n = (dev_priv->chipset == 0x31 ? 2 : 4);
66 int b = (dev_priv->chipset > 0x30 ?
67 nv_rd32(dev, 0x122c) & 0xf : 0);
68 int l = nv_rd32(dev, 0x1003d0); 76 int l = nv_rd32(dev, 0x1003d0);
69 77
70 for (i = 0; i < n; i++) { 78 for (i = 0; i < n; i++) {
71 for (j = 0; j < 3; j++) 79 for (j = 0; j < 3; j++)
72 nv_wr32(dev, 0x10037c + 0xc * i + 0x4 * j, 80 nv_wr32(dev, 0x10037c + 0xc * i + 0x4 * j,
73 calc_ref(b, l, j)); 81 calc_ref(dev, l, 0, j));
74 82
75 for (j = 0; j < 2; j++) 83 for (j = 0; j < 2; j++)
76 nv_wr32(dev, 0x1003ac + 0x8 * i + 0x4 * j, 84 nv_wr32(dev, 0x1003ac + 0x8 * i + 0x4 * j,
77 calc_ref(b, l, j)); 85 calc_ref(dev, l, 1, j));
78 } 86 }
79 } 87 }
80 88
diff --git a/drivers/gpu/drm/nouveau/nv50_crtc.c b/drivers/gpu/drm/nouveau/nv50_crtc.c
index 5d11ea10166..bfd4ca2fe7e 100644
--- a/drivers/gpu/drm/nouveau/nv50_crtc.c
+++ b/drivers/gpu/drm/nouveau/nv50_crtc.c
@@ -264,11 +264,16 @@ nv50_crtc_set_scale(struct nouveau_crtc *nv_crtc, int scaling_mode, bool update)
264int 264int
265nv50_crtc_set_clock(struct drm_device *dev, int head, int pclk) 265nv50_crtc_set_clock(struct drm_device *dev, int head, int pclk)
266{ 266{
267 uint32_t reg = NV50_PDISPLAY_CRTC_CLK_CTRL1(head); 267 struct drm_nouveau_private *dev_priv = dev->dev_private;
268 struct pll_lims pll; 268 struct pll_lims pll;
269 uint32_t reg1, reg2; 269 uint32_t reg, reg1, reg2;
270 int ret, N1, M1, N2, M2, P; 270 int ret, N1, M1, N2, M2, P;
271 271
272 if (dev_priv->chipset < NV_C0)
273 reg = NV50_PDISPLAY_CRTC_CLK_CTRL1(head);
274 else
275 reg = 0x614140 + (head * 0x800);
276
272 ret = get_pll_limits(dev, reg, &pll); 277 ret = get_pll_limits(dev, reg, &pll);
273 if (ret) 278 if (ret)
274 return ret; 279 return ret;
@@ -286,7 +291,8 @@ nv50_crtc_set_clock(struct drm_device *dev, int head, int pclk)
286 nv_wr32(dev, reg, 0x10000611); 291 nv_wr32(dev, reg, 0x10000611);
287 nv_wr32(dev, reg + 4, reg1 | (M1 << 16) | N1); 292 nv_wr32(dev, reg + 4, reg1 | (M1 << 16) | N1);
288 nv_wr32(dev, reg + 8, reg2 | (P << 28) | (M2 << 16) | N2); 293 nv_wr32(dev, reg + 8, reg2 | (P << 28) | (M2 << 16) | N2);
289 } else { 294 } else
295 if (dev_priv->chipset < NV_C0) {
290 ret = nv50_calc_pll2(dev, &pll, pclk, &N1, &N2, &M1, &P); 296 ret = nv50_calc_pll2(dev, &pll, pclk, &N1, &N2, &M1, &P);
291 if (ret <= 0) 297 if (ret <= 0)
292 return 0; 298 return 0;
@@ -298,6 +304,17 @@ nv50_crtc_set_clock(struct drm_device *dev, int head, int pclk)
298 nv_wr32(dev, reg, 0x50000610); 304 nv_wr32(dev, reg, 0x50000610);
299 nv_wr32(dev, reg + 4, reg1 | (P << 16) | (M1 << 8) | N1); 305 nv_wr32(dev, reg + 4, reg1 | (P << 16) | (M1 << 8) | N1);
300 nv_wr32(dev, reg + 8, N2); 306 nv_wr32(dev, reg + 8, N2);
307 } else {
308 ret = nv50_calc_pll2(dev, &pll, pclk, &N1, &N2, &M1, &P);
309 if (ret <= 0)
310 return 0;
311
312 NV_DEBUG(dev, "pclk %d out %d N %d fN 0x%04x M %d P %d\n",
313 pclk, ret, N1, N2, M1, P);
314
315 nv_mask(dev, reg + 0x0c, 0x00000000, 0x00000100);
316 nv_wr32(dev, reg + 0x04, (P << 16) | (N1 << 8) | M1);
317 nv_wr32(dev, reg + 0x10, N2 << 16);
301 } 318 }
302 319
303 return 0; 320 return 0;
@@ -348,7 +365,7 @@ nv50_crtc_cursor_set(struct drm_crtc *crtc, struct drm_file *file_priv,
348 365
349 gem = drm_gem_object_lookup(dev, file_priv, buffer_handle); 366 gem = drm_gem_object_lookup(dev, file_priv, buffer_handle);
350 if (!gem) 367 if (!gem)
351 return -EINVAL; 368 return -ENOENT;
352 cursor = nouveau_gem_object(gem); 369 cursor = nouveau_gem_object(gem);
353 370
354 ret = nouveau_bo_map(cursor); 371 ret = nouveau_bo_map(cursor);
@@ -381,15 +398,12 @@ nv50_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
381 398
382static void 399static void
383nv50_crtc_gamma_set(struct drm_crtc *crtc, u16 *r, u16 *g, u16 *b, 400nv50_crtc_gamma_set(struct drm_crtc *crtc, u16 *r, u16 *g, u16 *b,
384 uint32_t size) 401 uint32_t start, uint32_t size)
385{ 402{
403 int end = (start + size > 256) ? 256 : start + size, i;
386 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 404 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
387 int i;
388
389 if (size != 256)
390 return;
391 405
392 for (i = 0; i < 256; i++) { 406 for (i = start; i < end; i++) {
393 nv_crtc->lut.r[i] = r[i]; 407 nv_crtc->lut.r[i] = r[i];
394 nv_crtc->lut.g[i] = g[i]; 408 nv_crtc->lut.g[i] = g[i];
395 nv_crtc->lut.b[i] = b[i]; 409 nv_crtc->lut.b[i] = b[i];
diff --git a/drivers/gpu/drm/nouveau/nv50_display.c b/drivers/gpu/drm/nouveau/nv50_display.c
index f13ad0de9c8..612fa6d6a0c 100644
--- a/drivers/gpu/drm/nouveau/nv50_display.c
+++ b/drivers/gpu/drm/nouveau/nv50_display.c
@@ -76,7 +76,10 @@ nv50_evo_dmaobj_new(struct nouveau_channel *evo, uint32_t class, uint32_t name,
76 nv_wo32(dev, obj, 2, offset); 76 nv_wo32(dev, obj, 2, offset);
77 nv_wo32(dev, obj, 3, 0x00000000); 77 nv_wo32(dev, obj, 3, 0x00000000);
78 nv_wo32(dev, obj, 4, 0x00000000); 78 nv_wo32(dev, obj, 4, 0x00000000);
79 nv_wo32(dev, obj, 5, 0x00010000); 79 if (dev_priv->card_type < NV_C0)
80 nv_wo32(dev, obj, 5, 0x00010000);
81 else
82 nv_wo32(dev, obj, 5, 0x00020000);
80 dev_priv->engine.instmem.flush(dev); 83 dev_priv->engine.instmem.flush(dev);
81 84
82 return 0; 85 return 0;
diff --git a/drivers/gpu/drm/nouveau/nvc0_fb.c b/drivers/gpu/drm/nouveau/nvc0_fb.c
new file mode 100644
index 00000000000..26a996025dd
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nvc0_fb.c
@@ -0,0 +1,38 @@
1/*
2 * Copyright 2010 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24
25#include "drmP.h"
26
27#include "nouveau_drv.h"
28
29int
30nvc0_fb_init(struct drm_device *dev)
31{
32 return 0;
33}
34
35void
36nvc0_fb_takedown(struct drm_device *dev)
37{
38}
diff --git a/drivers/gpu/drm/nouveau/nvc0_fifo.c b/drivers/gpu/drm/nouveau/nvc0_fifo.c
new file mode 100644
index 00000000000..d6437587197
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nvc0_fifo.c
@@ -0,0 +1,96 @@
1/*
2 * Copyright 2010 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24
25#include "drmP.h"
26
27#include "nouveau_drv.h"
28
29void
30nvc0_fifo_disable(struct drm_device *dev)
31{
32}
33
34void
35nvc0_fifo_enable(struct drm_device *dev)
36{
37}
38
39bool
40nvc0_fifo_reassign(struct drm_device *dev, bool enable)
41{
42 return false;
43}
44
45bool
46nvc0_fifo_cache_flush(struct drm_device *dev)
47{
48 return true;
49}
50
51bool
52nvc0_fifo_cache_pull(struct drm_device *dev, bool enable)
53{
54 return false;
55}
56
57int
58nvc0_fifo_channel_id(struct drm_device *dev)
59{
60 return 127;
61}
62
63int
64nvc0_fifo_create_context(struct nouveau_channel *chan)
65{
66 return 0;
67}
68
69void
70nvc0_fifo_destroy_context(struct nouveau_channel *chan)
71{
72}
73
74int
75nvc0_fifo_load_context(struct nouveau_channel *chan)
76{
77 return 0;
78}
79
80int
81nvc0_fifo_unload_context(struct drm_device *dev)
82{
83 return 0;
84}
85
86void
87nvc0_fifo_takedown(struct drm_device *dev)
88{
89}
90
91int
92nvc0_fifo_init(struct drm_device *dev)
93{
94 return 0;
95}
96
diff --git a/drivers/gpu/drm/nouveau/nvc0_graph.c b/drivers/gpu/drm/nouveau/nvc0_graph.c
new file mode 100644
index 00000000000..717a5177a8d
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nvc0_graph.c
@@ -0,0 +1,75 @@
1/*
2 * Copyright 2010 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24
25#include "drmP.h"
26
27#include "nouveau_drv.h"
28
29void
30nvc0_graph_fifo_access(struct drm_device *dev, bool enabled)
31{
32}
33
34struct nouveau_channel *
35nvc0_graph_channel(struct drm_device *dev)
36{
37 return NULL;
38}
39
40int
41nvc0_graph_create_context(struct nouveau_channel *chan)
42{
43 return 0;
44}
45
46void
47nvc0_graph_destroy_context(struct nouveau_channel *chan)
48{
49}
50
51int
52nvc0_graph_load_context(struct nouveau_channel *chan)
53{
54 return 0;
55}
56
57int
58nvc0_graph_unload_context(struct drm_device *dev)
59{
60 return 0;
61}
62
63void
64nvc0_graph_takedown(struct drm_device *dev)
65{
66}
67
68int
69nvc0_graph_init(struct drm_device *dev)
70{
71 struct drm_nouveau_private *dev_priv = dev->dev_private;
72 dev_priv->engine.graph.accel_blocked = true;
73 return 0;
74}
75
diff --git a/drivers/gpu/drm/nouveau/nvc0_instmem.c b/drivers/gpu/drm/nouveau/nvc0_instmem.c
new file mode 100644
index 00000000000..3ab3cdc4217
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nvc0_instmem.c
@@ -0,0 +1,232 @@
1/*
2 * Copyright 2010 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24
25#include "drmP.h"
26
27#include "nouveau_drv.h"
28
29int
30nvc0_instmem_populate(struct drm_device *dev, struct nouveau_gpuobj *gpuobj,
31 uint32_t *size)
32{
33 int ret;
34
35 *size = ALIGN(*size, 4096);
36 if (*size == 0)
37 return -EINVAL;
38
39 ret = nouveau_bo_new(dev, NULL, *size, 0, TTM_PL_FLAG_VRAM, 0, 0x0000,
40 true, false, &gpuobj->im_backing);
41 if (ret) {
42 NV_ERROR(dev, "error getting PRAMIN backing pages: %d\n", ret);
43 return ret;
44 }
45
46 ret = nouveau_bo_pin(gpuobj->im_backing, TTM_PL_FLAG_VRAM);
47 if (ret) {
48 NV_ERROR(dev, "error pinning PRAMIN backing VRAM: %d\n", ret);
49 nouveau_bo_ref(NULL, &gpuobj->im_backing);
50 return ret;
51 }
52
53 gpuobj->im_backing_start = gpuobj->im_backing->bo.mem.mm_node->start;
54 gpuobj->im_backing_start <<= PAGE_SHIFT;
55 return 0;
56}
57
58void
59nvc0_instmem_clear(struct drm_device *dev, struct nouveau_gpuobj *gpuobj)
60{
61 struct drm_nouveau_private *dev_priv = dev->dev_private;
62
63 if (gpuobj && gpuobj->im_backing) {
64 if (gpuobj->im_bound)
65 dev_priv->engine.instmem.unbind(dev, gpuobj);
66 nouveau_bo_unpin(gpuobj->im_backing);
67 nouveau_bo_ref(NULL, &gpuobj->im_backing);
68 gpuobj->im_backing = NULL;
69 }
70}
71
72int
73nvc0_instmem_bind(struct drm_device *dev, struct nouveau_gpuobj *gpuobj)
74{
75 struct drm_nouveau_private *dev_priv = dev->dev_private;
76 uint32_t pte, pte_end;
77 uint64_t vram;
78
79 if (!gpuobj->im_backing || !gpuobj->im_pramin || gpuobj->im_bound)
80 return -EINVAL;
81
82 NV_DEBUG(dev, "st=0x%lx sz=0x%lx\n",
83 gpuobj->im_pramin->start, gpuobj->im_pramin->size);
84
85 pte = gpuobj->im_pramin->start >> 12;
86 pte_end = (gpuobj->im_pramin->size >> 12) + pte;
87 vram = gpuobj->im_backing_start;
88
89 NV_DEBUG(dev, "pramin=0x%lx, pte=%d, pte_end=%d\n",
90 gpuobj->im_pramin->start, pte, pte_end);
91 NV_DEBUG(dev, "first vram page: 0x%08x\n", gpuobj->im_backing_start);
92
93 while (pte < pte_end) {
94 nv_wr32(dev, 0x702000 + (pte * 8), (vram >> 8) | 1);
95 nv_wr32(dev, 0x702004 + (pte * 8), 0);
96 vram += 4096;
97 pte++;
98 }
99 dev_priv->engine.instmem.flush(dev);
100
101 if (1) {
102 u32 chan = nv_rd32(dev, 0x1700) << 16;
103 nv_wr32(dev, 0x100cb8, (chan + 0x1000) >> 8);
104 nv_wr32(dev, 0x100cbc, 0x80000005);
105 }
106
107 gpuobj->im_bound = 1;
108 return 0;
109}
110
111int
112nvc0_instmem_unbind(struct drm_device *dev, struct nouveau_gpuobj *gpuobj)
113{
114 struct drm_nouveau_private *dev_priv = dev->dev_private;
115 uint32_t pte, pte_end;
116
117 if (gpuobj->im_bound == 0)
118 return -EINVAL;
119
120 pte = gpuobj->im_pramin->start >> 12;
121 pte_end = (gpuobj->im_pramin->size >> 12) + pte;
122 while (pte < pte_end) {
123 nv_wr32(dev, 0x702000 + (pte * 8), 0);
124 nv_wr32(dev, 0x702004 + (pte * 8), 0);
125 pte++;
126 }
127 dev_priv->engine.instmem.flush(dev);
128
129 gpuobj->im_bound = 0;
130 return 0;
131}
132
133void
134nvc0_instmem_flush(struct drm_device *dev)
135{
136 nv_wr32(dev, 0x070000, 1);
137 if (!nv_wait(0x070000, 0x00000002, 0x00000000))
138 NV_ERROR(dev, "PRAMIN flush timeout\n");
139}
140
141int
142nvc0_instmem_suspend(struct drm_device *dev)
143{
144 struct drm_nouveau_private *dev_priv = dev->dev_private;
145 int i;
146
147 dev_priv->susres.ramin_copy = vmalloc(65536);
148 if (!dev_priv->susres.ramin_copy)
149 return -ENOMEM;
150
151 for (i = 0x700000; i < 0x710000; i += 4)
152 dev_priv->susres.ramin_copy[i/4] = nv_rd32(dev, i);
153 return 0;
154}
155
156void
157nvc0_instmem_resume(struct drm_device *dev)
158{
159 struct drm_nouveau_private *dev_priv = dev->dev_private;
160 u64 chan;
161 int i;
162
163 chan = dev_priv->vram_size - dev_priv->ramin_rsvd_vram;
164 nv_wr32(dev, 0x001700, chan >> 16);
165
166 for (i = 0x700000; i < 0x710000; i += 4)
167 nv_wr32(dev, i, dev_priv->susres.ramin_copy[i/4]);
168 vfree(dev_priv->susres.ramin_copy);
169 dev_priv->susres.ramin_copy = NULL;
170
171 nv_wr32(dev, 0x001714, 0xc0000000 | (chan >> 12));
172}
173
174int
175nvc0_instmem_init(struct drm_device *dev)
176{
177 struct drm_nouveau_private *dev_priv = dev->dev_private;
178 u64 chan, pgt3, imem, lim3 = dev_priv->ramin_size - 1;
179 int ret, i;
180
181 dev_priv->ramin_rsvd_vram = 1 * 1024 * 1024;
182 chan = dev_priv->vram_size - dev_priv->ramin_rsvd_vram;
183 imem = 4096 + 4096 + 32768;
184
185 nv_wr32(dev, 0x001700, chan >> 16);
186
187 /* channel setup */
188 nv_wr32(dev, 0x700200, lower_32_bits(chan + 0x1000));
189 nv_wr32(dev, 0x700204, upper_32_bits(chan + 0x1000));
190 nv_wr32(dev, 0x700208, lower_32_bits(lim3));
191 nv_wr32(dev, 0x70020c, upper_32_bits(lim3));
192
193 /* point pgd -> pgt */
194 nv_wr32(dev, 0x701000, 0);
195 nv_wr32(dev, 0x701004, ((chan + 0x2000) >> 8) | 1);
196
197 /* point pgt -> physical vram for channel */
198 pgt3 = 0x2000;
199 for (i = 0; i < dev_priv->ramin_rsvd_vram; i += 4096, pgt3 += 8) {
200 nv_wr32(dev, 0x700000 + pgt3, ((chan + i) >> 8) | 1);
201 nv_wr32(dev, 0x700004 + pgt3, 0);
202 }
203
204 /* clear rest of pgt */
205 for (; i < dev_priv->ramin_size; i += 4096, pgt3 += 8) {
206 nv_wr32(dev, 0x700000 + pgt3, 0);
207 nv_wr32(dev, 0x700004 + pgt3, 0);
208 }
209
210 /* point bar3 at the channel */
211 nv_wr32(dev, 0x001714, 0xc0000000 | (chan >> 12));
212
213 /* Global PRAMIN heap */
214 ret = drm_mm_init(&dev_priv->ramin_heap, imem,
215 dev_priv->ramin_size - imem);
216 if (ret) {
217 NV_ERROR(dev, "Failed to init RAMIN heap\n");
218 return -ENOMEM;
219 }
220
221 /*XXX: incorrect, but needed to make hash func "work" */
222 dev_priv->ramht_offset = 0x10000;
223 dev_priv->ramht_bits = 9;
224 dev_priv->ramht_size = (1 << dev_priv->ramht_bits);
225 return 0;
226}
227
228void
229nvc0_instmem_takedown(struct drm_device *dev)
230{
231}
232
diff --git a/drivers/gpu/drm/radeon/r600_cp.c b/drivers/gpu/drm/radeon/r600_cp.c
index 68e6f434930..4f4cd8b286d 100644
--- a/drivers/gpu/drm/radeon/r600_cp.c
+++ b/drivers/gpu/drm/radeon/r600_cp.c
@@ -200,7 +200,7 @@ int r600_page_table_init(struct drm_device *dev)
200 entry->pagelist[i], 0, 200 entry->pagelist[i], 0,
201 PAGE_SIZE, 201 PAGE_SIZE,
202 PCI_DMA_BIDIRECTIONAL); 202 PCI_DMA_BIDIRECTIONAL);
203 if (entry->busaddr[i] == 0) { 203 if (pci_dma_mapping_error(dev->pdev, entry->busaddr[i])) {
204 DRM_ERROR("unable to map PCIGART pages!\n"); 204 DRM_ERROR("unable to map PCIGART pages!\n");
205 r600_page_table_cleanup(dev, gart_info); 205 r600_page_table_cleanup(dev, gart_info);
206 goto done; 206 goto done;
diff --git a/drivers/gpu/drm/radeon/r600_cs.c b/drivers/gpu/drm/radeon/r600_cs.c
index c3ea212e0c3..d8864949e38 100644
--- a/drivers/gpu/drm/radeon/r600_cs.c
+++ b/drivers/gpu/drm/radeon/r600_cs.c
@@ -133,6 +133,7 @@ static inline int r600_bpe_from_format(u32 *bpe, u32 format)
133 case V_038004_FMT_GB_GR: 133 case V_038004_FMT_GB_GR:
134 case V_038004_FMT_BG_RG: 134 case V_038004_FMT_BG_RG:
135 case V_038004_COLOR_INVALID: 135 case V_038004_COLOR_INVALID:
136 default:
136 *bpe = 16; 137 *bpe = 16;
137 return -EINVAL; 138 return -EINVAL;
138 } 139 }
@@ -174,7 +175,7 @@ static inline int r600_cs_track_validate_cb(struct radeon_cs_parser *p, int i)
174 dev_warn(p->dev, "FMASK or CMASK buffer are not supported by this kernel\n"); 175 dev_warn(p->dev, "FMASK or CMASK buffer are not supported by this kernel\n");
175 return -EINVAL; 176 return -EINVAL;
176 } 177 }
177 size = radeon_bo_size(track->cb_color_bo[i]); 178 size = radeon_bo_size(track->cb_color_bo[i]) - track->cb_color_bo_offset[i];
178 if (r600_bpe_from_format(&bpe, G_0280A0_FORMAT(track->cb_color_info[i]))) { 179 if (r600_bpe_from_format(&bpe, G_0280A0_FORMAT(track->cb_color_info[i]))) {
179 dev_warn(p->dev, "%s:%d cb invalid format %d for %d (0x%08X)\n", 180 dev_warn(p->dev, "%s:%d cb invalid format %d for %d (0x%08X)\n",
180 __func__, __LINE__, G_0280A0_FORMAT(track->cb_color_info[i]), 181 __func__, __LINE__, G_0280A0_FORMAT(track->cb_color_info[i]),
@@ -327,7 +328,6 @@ static int r600_cs_track_check(struct radeon_cs_parser *p)
327 dev_warn(p->dev, "z/stencil buffer size not set\n"); 328 dev_warn(p->dev, "z/stencil buffer size not set\n");
328 return -EINVAL; 329 return -EINVAL;
329 } 330 }
330 printk_once(KERN_WARNING "You have old & broken userspace please consider updating mesa\n");
331 tmp = radeon_bo_size(track->db_bo) - track->db_offset; 331 tmp = radeon_bo_size(track->db_bo) - track->db_offset;
332 tmp = (tmp / bpe) >> 6; 332 tmp = (tmp / bpe) >> 6;
333 if (!tmp) { 333 if (!tmp) {
@@ -882,8 +882,6 @@ static inline int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx
882 return -EINVAL; 882 return -EINVAL;
883 } 883 }
884 ib[idx] = track->cb_color_base_last[tmp]; 884 ib[idx] = track->cb_color_base_last[tmp];
885 printk_once(KERN_WARNING "You have old & broken userspace "
886 "please consider updating mesa & xf86-video-ati\n");
887 track->cb_color_frag_bo[tmp] = track->cb_color_bo[tmp]; 885 track->cb_color_frag_bo[tmp] = track->cb_color_bo[tmp];
888 } else { 886 } else {
889 r = r600_cs_packet_next_reloc(p, &reloc); 887 r = r600_cs_packet_next_reloc(p, &reloc);
@@ -910,8 +908,6 @@ static inline int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx
910 return -EINVAL; 908 return -EINVAL;
911 } 909 }
912 ib[idx] = track->cb_color_base_last[tmp]; 910 ib[idx] = track->cb_color_base_last[tmp];
913 printk_once(KERN_WARNING "You have old & broken userspace "
914 "please consider updating mesa & xf86-video-ati\n");
915 track->cb_color_tile_bo[tmp] = track->cb_color_bo[tmp]; 911 track->cb_color_tile_bo[tmp] = track->cb_color_bo[tmp];
916 } else { 912 } else {
917 r = r600_cs_packet_next_reloc(p, &reloc); 913 r = r600_cs_packet_next_reloc(p, &reloc);
@@ -938,7 +934,7 @@ static inline int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx
938 return -EINVAL; 934 return -EINVAL;
939 } 935 }
940 tmp = (reg - CB_COLOR0_BASE) / 4; 936 tmp = (reg - CB_COLOR0_BASE) / 4;
941 track->cb_color_bo_offset[tmp] = radeon_get_ib_value(p, idx); 937 track->cb_color_bo_offset[tmp] = radeon_get_ib_value(p, idx) << 8;
942 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); 938 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
943 track->cb_color_base_last[tmp] = ib[idx]; 939 track->cb_color_base_last[tmp] = ib[idx];
944 track->cb_color_bo[tmp] = reloc->robj; 940 track->cb_color_bo[tmp] = reloc->robj;
@@ -950,7 +946,7 @@ static inline int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx
950 "0x%04X\n", reg); 946 "0x%04X\n", reg);
951 return -EINVAL; 947 return -EINVAL;
952 } 948 }
953 track->db_offset = radeon_get_ib_value(p, idx); 949 track->db_offset = radeon_get_ib_value(p, idx) << 8;
954 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); 950 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
955 track->db_bo = reloc->robj; 951 track->db_bo = reloc->robj;
956 break; 952 break;
@@ -1055,10 +1051,10 @@ static void r600_texture_size(unsigned nfaces, unsigned blevel, unsigned nlevels
1055 } 1051 }
1056 *l0_size = ALIGN((w0 * bpe), pitch_align) * h0 * d0; 1052 *l0_size = ALIGN((w0 * bpe), pitch_align) * h0 * d0;
1057 *mipmap_size = offset; 1053 *mipmap_size = offset;
1058 if (!blevel)
1059 *mipmap_size -= *l0_size;
1060 if (!nlevels) 1054 if (!nlevels)
1061 *mipmap_size = *l0_size; 1055 *mipmap_size = *l0_size;
1056 if (!blevel)
1057 *mipmap_size -= *l0_size;
1062} 1058}
1063 1059
1064/** 1060/**
@@ -1165,14 +1161,14 @@ static inline int r600_check_texture_resource(struct radeon_cs_parser *p, u32 i
1165 (pitch_align * bpe), 1161 (pitch_align * bpe),
1166 &l0_size, &mipmap_size); 1162 &l0_size, &mipmap_size);
1167 /* using get ib will give us the offset into the texture bo */ 1163 /* using get ib will give us the offset into the texture bo */
1168 word0 = radeon_get_ib_value(p, idx + 2); 1164 word0 = radeon_get_ib_value(p, idx + 2) << 8;
1169 if ((l0_size + word0) > radeon_bo_size(texture)) { 1165 if ((l0_size + word0) > radeon_bo_size(texture)) {
1170 dev_warn(p->dev, "texture bo too small (%d %d %d %d -> %d have %ld)\n", 1166 dev_warn(p->dev, "texture bo too small (%d %d %d %d -> %d have %ld)\n",
1171 w0, h0, bpe, word0, l0_size, radeon_bo_size(texture)); 1167 w0, h0, bpe, word0, l0_size, radeon_bo_size(texture));
1172 return -EINVAL; 1168 return -EINVAL;
1173 } 1169 }
1174 /* using get ib will give us the offset into the mipmap bo */ 1170 /* using get ib will give us the offset into the mipmap bo */
1175 word0 = radeon_get_ib_value(p, idx + 3); 1171 word0 = radeon_get_ib_value(p, idx + 3) << 8;
1176 if ((mipmap_size + word0) > radeon_bo_size(mipmap)) { 1172 if ((mipmap_size + word0) > radeon_bo_size(mipmap)) {
1177 dev_warn(p->dev, "mipmap bo too small (%d %d %d %d %d %d -> %d have %ld)\n", 1173 dev_warn(p->dev, "mipmap bo too small (%d %d %d %d %d %d -> %d have %ld)\n",
1178 w0, h0, bpe, blevel, nlevels, word0, mipmap_size, radeon_bo_size(texture)); 1174 w0, h0, bpe, blevel, nlevels, word0, mipmap_size, radeon_bo_size(texture));
@@ -1366,7 +1362,7 @@ static int r600_packet3_check(struct radeon_cs_parser *p,
1366 } 1362 }
1367 for (i = 0; i < (pkt->count / 7); i++) { 1363 for (i = 0; i < (pkt->count / 7); i++) {
1368 struct radeon_bo *texture, *mipmap; 1364 struct radeon_bo *texture, *mipmap;
1369 u32 size, offset; 1365 u32 size, offset, base_offset, mip_offset;
1370 1366
1371 switch (G__SQ_VTX_CONSTANT_TYPE(radeon_get_ib_value(p, idx+(i*7)+6+1))) { 1367 switch (G__SQ_VTX_CONSTANT_TYPE(radeon_get_ib_value(p, idx+(i*7)+6+1))) {
1372 case SQ_TEX_VTX_VALID_TEXTURE: 1368 case SQ_TEX_VTX_VALID_TEXTURE:
@@ -1376,7 +1372,7 @@ static int r600_packet3_check(struct radeon_cs_parser *p,
1376 DRM_ERROR("bad SET_RESOURCE\n"); 1372 DRM_ERROR("bad SET_RESOURCE\n");
1377 return -EINVAL; 1373 return -EINVAL;
1378 } 1374 }
1379 ib[idx+1+(i*7)+2] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); 1375 base_offset = (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1380 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) 1376 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
1381 ib[idx+1+(i*7)+0] |= S_038000_TILE_MODE(V_038000_ARRAY_2D_TILED_THIN1); 1377 ib[idx+1+(i*7)+0] |= S_038000_TILE_MODE(V_038000_ARRAY_2D_TILED_THIN1);
1382 else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) 1378 else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
@@ -1388,12 +1384,14 @@ static int r600_packet3_check(struct radeon_cs_parser *p,
1388 DRM_ERROR("bad SET_RESOURCE\n"); 1384 DRM_ERROR("bad SET_RESOURCE\n");
1389 return -EINVAL; 1385 return -EINVAL;
1390 } 1386 }
1391 ib[idx+1+(i*7)+3] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); 1387 mip_offset = (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1392 mipmap = reloc->robj; 1388 mipmap = reloc->robj;
1393 r = r600_check_texture_resource(p, idx+(i*7)+1, 1389 r = r600_check_texture_resource(p, idx+(i*7)+1,
1394 texture, mipmap, reloc->lobj.tiling_flags); 1390 texture, mipmap, reloc->lobj.tiling_flags);
1395 if (r) 1391 if (r)
1396 return r; 1392 return r;
1393 ib[idx+1+(i*7)+2] += base_offset;
1394 ib[idx+1+(i*7)+3] += mip_offset;
1397 break; 1395 break;
1398 case SQ_TEX_VTX_VALID_BUFFER: 1396 case SQ_TEX_VTX_VALID_BUFFER:
1399 /* vtx base */ 1397 /* vtx base */
@@ -1403,10 +1401,11 @@ static int r600_packet3_check(struct radeon_cs_parser *p,
1403 return -EINVAL; 1401 return -EINVAL;
1404 } 1402 }
1405 offset = radeon_get_ib_value(p, idx+1+(i*7)+0); 1403 offset = radeon_get_ib_value(p, idx+1+(i*7)+0);
1406 size = radeon_get_ib_value(p, idx+1+(i*7)+1); 1404 size = radeon_get_ib_value(p, idx+1+(i*7)+1) + 1;
1407 if (p->rdev && (size + offset) > radeon_bo_size(reloc->robj)) { 1405 if (p->rdev && (size + offset) > radeon_bo_size(reloc->robj)) {
1408 /* force size to size of the buffer */ 1406 /* force size to size of the buffer */
1409 dev_warn(p->dev, "vbo resource seems too big for the bo\n"); 1407 dev_warn(p->dev, "vbo resource seems too big (%d) for the bo (%ld)\n",
1408 size + offset, radeon_bo_size(reloc->robj));
1410 ib[idx+1+(i*7)+1] = radeon_bo_size(reloc->robj); 1409 ib[idx+1+(i*7)+1] = radeon_bo_size(reloc->robj);
1411 } 1410 }
1412 ib[idx+1+(i*7)+0] += (u32)((reloc->lobj.gpu_offset) & 0xffffffff); 1411 ib[idx+1+(i*7)+0] += (u32)((reloc->lobj.gpu_offset) & 0xffffffff);
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index 3cd1c470b77..3dfcfa3ca42 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -1100,6 +1100,8 @@ struct radeon_device {
1100 struct notifier_block acpi_nb; 1100 struct notifier_block acpi_nb;
1101 /* only one userspace can use Hyperz features at a time */ 1101 /* only one userspace can use Hyperz features at a time */
1102 struct drm_file *hyperz_filp; 1102 struct drm_file *hyperz_filp;
1103 /* i2c buses */
1104 struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS];
1103}; 1105};
1104 1106
1105int radeon_device_init(struct radeon_device *rdev, 1107int radeon_device_init(struct radeon_device *rdev,
diff --git a/drivers/gpu/drm/radeon/radeon_atombios.c b/drivers/gpu/drm/radeon/radeon_atombios.c
index 3bc2bcdf530..6d30868744e 100644
--- a/drivers/gpu/drm/radeon/radeon_atombios.c
+++ b/drivers/gpu/drm/radeon/radeon_atombios.c
@@ -48,7 +48,8 @@ radeon_add_atom_connector(struct drm_device *dev,
48 struct radeon_i2c_bus_rec *i2c_bus, 48 struct radeon_i2c_bus_rec *i2c_bus,
49 bool linkb, uint32_t igp_lane_info, 49 bool linkb, uint32_t igp_lane_info,
50 uint16_t connector_object_id, 50 uint16_t connector_object_id,
51 struct radeon_hpd *hpd); 51 struct radeon_hpd *hpd,
52 struct radeon_router *router);
52 53
53/* from radeon_legacy_encoder.c */ 54/* from radeon_legacy_encoder.c */
54extern void 55extern void
@@ -114,7 +115,8 @@ static inline struct radeon_i2c_bus_rec radeon_lookup_i2c_gpio(struct radeon_dev
114 115
115 i2c.i2c_id = gpio->sucI2cId.ucAccess; 116 i2c.i2c_id = gpio->sucI2cId.ucAccess;
116 117
117 i2c.valid = true; 118 if (i2c.mask_clk_reg)
119 i2c.valid = true;
118 break; 120 break;
119 } 121 }
120 } 122 }
@@ -123,6 +125,66 @@ static inline struct radeon_i2c_bus_rec radeon_lookup_i2c_gpio(struct radeon_dev
123 return i2c; 125 return i2c;
124} 126}
125 127
128void radeon_atombios_i2c_init(struct radeon_device *rdev)
129{
130 struct atom_context *ctx = rdev->mode_info.atom_context;
131 ATOM_GPIO_I2C_ASSIGMENT *gpio;
132 struct radeon_i2c_bus_rec i2c;
133 int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
134 struct _ATOM_GPIO_I2C_INFO *i2c_info;
135 uint16_t data_offset, size;
136 int i, num_indices;
137 char stmp[32];
138
139 memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec));
140
141 if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
142 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
143
144 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
145 sizeof(ATOM_GPIO_I2C_ASSIGMENT);
146
147 for (i = 0; i < num_indices; i++) {
148 gpio = &i2c_info->asGPIO_Info[i];
149 i2c.valid = false;
150 i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex) * 4;
151 i2c.mask_data_reg = le16_to_cpu(gpio->usDataMaskRegisterIndex) * 4;
152 i2c.en_clk_reg = le16_to_cpu(gpio->usClkEnRegisterIndex) * 4;
153 i2c.en_data_reg = le16_to_cpu(gpio->usDataEnRegisterIndex) * 4;
154 i2c.y_clk_reg = le16_to_cpu(gpio->usClkY_RegisterIndex) * 4;
155 i2c.y_data_reg = le16_to_cpu(gpio->usDataY_RegisterIndex) * 4;
156 i2c.a_clk_reg = le16_to_cpu(gpio->usClkA_RegisterIndex) * 4;
157 i2c.a_data_reg = le16_to_cpu(gpio->usDataA_RegisterIndex) * 4;
158 i2c.mask_clk_mask = (1 << gpio->ucClkMaskShift);
159 i2c.mask_data_mask = (1 << gpio->ucDataMaskShift);
160 i2c.en_clk_mask = (1 << gpio->ucClkEnShift);
161 i2c.en_data_mask = (1 << gpio->ucDataEnShift);
162 i2c.y_clk_mask = (1 << gpio->ucClkY_Shift);
163 i2c.y_data_mask = (1 << gpio->ucDataY_Shift);
164 i2c.a_clk_mask = (1 << gpio->ucClkA_Shift);
165 i2c.a_data_mask = (1 << gpio->ucDataA_Shift);
166
167 if (gpio->sucI2cId.sbfAccess.bfHW_Capable)
168 i2c.hw_capable = true;
169 else
170 i2c.hw_capable = false;
171
172 if (gpio->sucI2cId.ucAccess == 0xa0)
173 i2c.mm_i2c = true;
174 else
175 i2c.mm_i2c = false;
176
177 i2c.i2c_id = gpio->sucI2cId.ucAccess;
178
179 if (i2c.mask_clk_reg) {
180 i2c.valid = true;
181 sprintf(stmp, "0x%x", i2c.i2c_id);
182 rdev->i2c_bus[i] = radeon_i2c_create(rdev->ddev, &i2c, stmp);
183 }
184 }
185 }
186}
187
126static inline struct radeon_gpio_rec radeon_lookup_gpio(struct radeon_device *rdev, 188static inline struct radeon_gpio_rec radeon_lookup_gpio(struct radeon_device *rdev,
127 u8 id) 189 u8 id)
128{ 190{
@@ -206,6 +268,7 @@ static bool radeon_atom_apply_quirks(struct drm_device *dev,
206 uint16_t *line_mux, 268 uint16_t *line_mux,
207 struct radeon_hpd *hpd) 269 struct radeon_hpd *hpd)
208{ 270{
271 struct radeon_device *rdev = dev->dev_private;
209 272
210 /* Asus M2A-VM HDMI board lists the DVI port as HDMI */ 273 /* Asus M2A-VM HDMI board lists the DVI port as HDMI */
211 if ((dev->pdev->device == 0x791e) && 274 if ((dev->pdev->device == 0x791e) &&
@@ -308,13 +371,22 @@ static bool radeon_atom_apply_quirks(struct drm_device *dev,
308 } 371 }
309 } 372 }
310 373
311 /* Acer laptop reports DVI-D as DVI-I */ 374 /* Acer laptop reports DVI-D as DVI-I and hpd pins reversed */
312 if ((dev->pdev->device == 0x95c4) && 375 if ((dev->pdev->device == 0x95c4) &&
313 (dev->pdev->subsystem_vendor == 0x1025) && 376 (dev->pdev->subsystem_vendor == 0x1025) &&
314 (dev->pdev->subsystem_device == 0x013c)) { 377 (dev->pdev->subsystem_device == 0x013c)) {
378 struct radeon_gpio_rec gpio;
379
315 if ((*connector_type == DRM_MODE_CONNECTOR_DVII) && 380 if ((*connector_type == DRM_MODE_CONNECTOR_DVII) &&
316 (supported_device == ATOM_DEVICE_DFP1_SUPPORT)) 381 (supported_device == ATOM_DEVICE_DFP1_SUPPORT)) {
382 gpio = radeon_lookup_gpio(rdev, 6);
383 *hpd = radeon_atom_get_hpd_info_from_gpio(rdev, &gpio);
317 *connector_type = DRM_MODE_CONNECTOR_DVID; 384 *connector_type = DRM_MODE_CONNECTOR_DVID;
385 } else if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
386 (supported_device == ATOM_DEVICE_DFP1_SUPPORT)) {
387 gpio = radeon_lookup_gpio(rdev, 7);
388 *hpd = radeon_atom_get_hpd_info_from_gpio(rdev, &gpio);
389 }
318 } 390 }
319 391
320 /* XFX Pine Group device rv730 reports no VGA DDC lines 392 /* XFX Pine Group device rv730 reports no VGA DDC lines
@@ -399,13 +471,15 @@ bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev)
399 u16 size, data_offset; 471 u16 size, data_offset;
400 u8 frev, crev; 472 u8 frev, crev;
401 ATOM_CONNECTOR_OBJECT_TABLE *con_obj; 473 ATOM_CONNECTOR_OBJECT_TABLE *con_obj;
474 ATOM_OBJECT_TABLE *router_obj;
402 ATOM_DISPLAY_OBJECT_PATH_TABLE *path_obj; 475 ATOM_DISPLAY_OBJECT_PATH_TABLE *path_obj;
403 ATOM_OBJECT_HEADER *obj_header; 476 ATOM_OBJECT_HEADER *obj_header;
404 int i, j, path_size, device_support; 477 int i, j, k, path_size, device_support;
405 int connector_type; 478 int connector_type;
406 u16 igp_lane_info, conn_id, connector_object_id; 479 u16 igp_lane_info, conn_id, connector_object_id;
407 bool linkb; 480 bool linkb;
408 struct radeon_i2c_bus_rec ddc_bus; 481 struct radeon_i2c_bus_rec ddc_bus;
482 struct radeon_router router;
409 struct radeon_gpio_rec gpio; 483 struct radeon_gpio_rec gpio;
410 struct radeon_hpd hpd; 484 struct radeon_hpd hpd;
411 485
@@ -415,6 +489,8 @@ bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev)
415 if (crev < 2) 489 if (crev < 2)
416 return false; 490 return false;
417 491
492 router.valid = false;
493
418 obj_header = (ATOM_OBJECT_HEADER *) (ctx->bios + data_offset); 494 obj_header = (ATOM_OBJECT_HEADER *) (ctx->bios + data_offset);
419 path_obj = (ATOM_DISPLAY_OBJECT_PATH_TABLE *) 495 path_obj = (ATOM_DISPLAY_OBJECT_PATH_TABLE *)
420 (ctx->bios + data_offset + 496 (ctx->bios + data_offset +
@@ -422,6 +498,9 @@ bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev)
422 con_obj = (ATOM_CONNECTOR_OBJECT_TABLE *) 498 con_obj = (ATOM_CONNECTOR_OBJECT_TABLE *)
423 (ctx->bios + data_offset + 499 (ctx->bios + data_offset +
424 le16_to_cpu(obj_header->usConnectorObjectTableOffset)); 500 le16_to_cpu(obj_header->usConnectorObjectTableOffset));
501 router_obj = (ATOM_OBJECT_TABLE *)
502 (ctx->bios + data_offset +
503 le16_to_cpu(obj_header->usRouterObjectTableOffset));
425 device_support = le16_to_cpu(obj_header->usDeviceSupport); 504 device_support = le16_to_cpu(obj_header->usDeviceSupport);
426 505
427 path_size = 0; 506 path_size = 0;
@@ -508,33 +587,86 @@ bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev)
508 if (connector_type == DRM_MODE_CONNECTOR_Unknown) 587 if (connector_type == DRM_MODE_CONNECTOR_Unknown)
509 continue; 588 continue;
510 589
511 for (j = 0; j < ((le16_to_cpu(path->usSize) - 8) / 2); 590 for (j = 0; j < ((le16_to_cpu(path->usSize) - 8) / 2); j++) {
512 j++) { 591 uint8_t grph_obj_id, grph_obj_num, grph_obj_type;
513 uint8_t enc_obj_id, enc_obj_num, enc_obj_type;
514 592
515 enc_obj_id = 593 grph_obj_id =
516 (le16_to_cpu(path->usGraphicObjIds[j]) & 594 (le16_to_cpu(path->usGraphicObjIds[j]) &
517 OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; 595 OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
518 enc_obj_num = 596 grph_obj_num =
519 (le16_to_cpu(path->usGraphicObjIds[j]) & 597 (le16_to_cpu(path->usGraphicObjIds[j]) &
520 ENUM_ID_MASK) >> ENUM_ID_SHIFT; 598 ENUM_ID_MASK) >> ENUM_ID_SHIFT;
521 enc_obj_type = 599 grph_obj_type =
522 (le16_to_cpu(path->usGraphicObjIds[j]) & 600 (le16_to_cpu(path->usGraphicObjIds[j]) &
523 OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT; 601 OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
524 602
525 /* FIXME: add support for router objects */ 603 if (grph_obj_type == GRAPH_OBJECT_TYPE_ENCODER) {
526 if (enc_obj_type == GRAPH_OBJECT_TYPE_ENCODER) { 604 if (grph_obj_num == 2)
527 if (enc_obj_num == 2)
528 linkb = true; 605 linkb = true;
529 else 606 else
530 linkb = false; 607 linkb = false;
531 608
532 radeon_add_atom_encoder(dev, 609 radeon_add_atom_encoder(dev,
533 enc_obj_id, 610 grph_obj_id,
534 le16_to_cpu 611 le16_to_cpu
535 (path-> 612 (path->
536 usDeviceTag)); 613 usDeviceTag));
537 614
615 } else if (grph_obj_type == GRAPH_OBJECT_TYPE_ROUTER) {
616 router.valid = false;
617 for (k = 0; k < router_obj->ucNumberOfObjects; k++) {
618 u16 router_obj_id = le16_to_cpu(router_obj->asObjects[j].usObjectID);
619 if (le16_to_cpu(path->usGraphicObjIds[j]) == router_obj_id) {
620 ATOM_COMMON_RECORD_HEADER *record = (ATOM_COMMON_RECORD_HEADER *)
621 (ctx->bios + data_offset +
622 le16_to_cpu(router_obj->asObjects[k].usRecordOffset));
623 ATOM_I2C_RECORD *i2c_record;
624 ATOM_I2C_ID_CONFIG_ACCESS *i2c_config;
625 ATOM_ROUTER_DDC_PATH_SELECT_RECORD *ddc_path;
626 ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *router_src_dst_table =
627 (ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *)
628 (ctx->bios + data_offset +
629 le16_to_cpu(router_obj->asObjects[k].usSrcDstTableOffset));
630 int enum_id;
631
632 router.router_id = router_obj_id;
633 for (enum_id = 0; enum_id < router_src_dst_table->ucNumberOfDst;
634 enum_id++) {
635 if (le16_to_cpu(path->usConnObjectId) ==
636 le16_to_cpu(router_src_dst_table->usDstObjectID[enum_id]))
637 break;
638 }
639
640 while (record->ucRecordType > 0 &&
641 record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
642 switch (record->ucRecordType) {
643 case ATOM_I2C_RECORD_TYPE:
644 i2c_record =
645 (ATOM_I2C_RECORD *)
646 record;
647 i2c_config =
648 (ATOM_I2C_ID_CONFIG_ACCESS *)
649 &i2c_record->sucI2cId;
650 router.i2c_info =
651 radeon_lookup_i2c_gpio(rdev,
652 i2c_config->
653 ucAccess);
654 router.i2c_addr = i2c_record->ucI2CAddr >> 1;
655 break;
656 case ATOM_ROUTER_DDC_PATH_SELECT_RECORD_TYPE:
657 ddc_path = (ATOM_ROUTER_DDC_PATH_SELECT_RECORD *)
658 record;
659 router.valid = true;
660 router.mux_type = ddc_path->ucMuxType;
661 router.mux_control_pin = ddc_path->ucMuxControlPin;
662 router.mux_state = ddc_path->ucMuxState[enum_id];
663 break;
664 }
665 record = (ATOM_COMMON_RECORD_HEADER *)
666 ((char *)record + record->ucRecordSize);
667 }
668 }
669 }
538 } 670 }
539 } 671 }
540 672
@@ -614,7 +746,8 @@ bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev)
614 connector_type, &ddc_bus, 746 connector_type, &ddc_bus,
615 linkb, igp_lane_info, 747 linkb, igp_lane_info,
616 connector_object_id, 748 connector_object_id,
617 &hpd); 749 &hpd,
750 &router);
618 751
619 } 752 }
620 } 753 }
@@ -691,6 +824,9 @@ bool radeon_get_atom_connector_info_from_supported_devices_table(struct
691 int i, j, max_device; 824 int i, j, max_device;
692 struct bios_connector *bios_connectors; 825 struct bios_connector *bios_connectors;
693 size_t bc_size = sizeof(*bios_connectors) * ATOM_MAX_SUPPORTED_DEVICE; 826 size_t bc_size = sizeof(*bios_connectors) * ATOM_MAX_SUPPORTED_DEVICE;
827 struct radeon_router router;
828
829 router.valid = false;
694 830
695 bios_connectors = kzalloc(bc_size, GFP_KERNEL); 831 bios_connectors = kzalloc(bc_size, GFP_KERNEL);
696 if (!bios_connectors) 832 if (!bios_connectors)
@@ -862,7 +998,8 @@ bool radeon_get_atom_connector_info_from_supported_devices_table(struct
862 &bios_connectors[i].ddc_bus, 998 &bios_connectors[i].ddc_bus,
863 false, 0, 999 false, 0,
864 connector_object_id, 1000 connector_object_id,
865 &bios_connectors[i].hpd); 1001 &bios_connectors[i].hpd,
1002 &router);
866 } 1003 }
867 } 1004 }
868 1005
@@ -1521,7 +1658,7 @@ void radeon_atombios_get_power_modes(struct radeon_device *rdev)
1521 thermal_controller_names[power_info->info.ucOverdriveThermalController], 1658 thermal_controller_names[power_info->info.ucOverdriveThermalController],
1522 power_info->info.ucOverdriveControllerAddress >> 1); 1659 power_info->info.ucOverdriveControllerAddress >> 1);
1523 i2c_bus = radeon_lookup_i2c_gpio(rdev, power_info->info.ucOverdriveI2cLine); 1660 i2c_bus = radeon_lookup_i2c_gpio(rdev, power_info->info.ucOverdriveI2cLine);
1524 rdev->pm.i2c_bus = radeon_i2c_create(rdev->ddev, &i2c_bus, "Thermal"); 1661 rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
1525 if (rdev->pm.i2c_bus) { 1662 if (rdev->pm.i2c_bus) {
1526 struct i2c_board_info info = { }; 1663 struct i2c_board_info info = { };
1527 const char *name = thermal_controller_names[power_info->info. 1664 const char *name = thermal_controller_names[power_info->info.
@@ -1814,7 +1951,7 @@ void radeon_atombios_get_power_modes(struct radeon_device *rdev)
1814 (controller->ucFanParameters & 1951 (controller->ucFanParameters &
1815 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with"); 1952 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
1816 i2c_bus = radeon_lookup_i2c_gpio(rdev, controller->ucI2cLine); 1953 i2c_bus = radeon_lookup_i2c_gpio(rdev, controller->ucI2cLine);
1817 rdev->pm.i2c_bus = radeon_i2c_create(rdev->ddev, &i2c_bus, "Thermal"); 1954 rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
1818 if (rdev->pm.i2c_bus) { 1955 if (rdev->pm.i2c_bus) {
1819 struct i2c_board_info info = { }; 1956 struct i2c_board_info info = { };
1820 const char *name = pp_lib_thermal_controller_names[controller->ucType]; 1957 const char *name = pp_lib_thermal_controller_names[controller->ucType];
@@ -1927,6 +2064,11 @@ void radeon_atombios_get_power_modes(struct radeon_device *rdev)
1927 rdev->pm.power_state[state_index].type = 2064 rdev->pm.power_state[state_index].type =
1928 POWER_STATE_TYPE_PERFORMANCE; 2065 POWER_STATE_TYPE_PERFORMANCE;
1929 break; 2066 break;
2067 case ATOM_PPLIB_CLASSIFICATION_UI_NONE:
2068 if (misc2 & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE)
2069 rdev->pm.power_state[state_index].type =
2070 POWER_STATE_TYPE_PERFORMANCE;
2071 break;
1930 } 2072 }
1931 rdev->pm.power_state[state_index].flags = 0; 2073 rdev->pm.power_state[state_index].flags = 0;
1932 if (misc & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) 2074 if (misc & ATOM_PPLIB_SINGLE_DISPLAY_ONLY)
diff --git a/drivers/gpu/drm/radeon/radeon_clocks.c b/drivers/gpu/drm/radeon/radeon_clocks.c
index f64936cc4dd..14448a740ba 100644
--- a/drivers/gpu/drm/radeon/radeon_clocks.c
+++ b/drivers/gpu/drm/radeon/radeon_clocks.c
@@ -91,6 +91,85 @@ uint32_t radeon_legacy_get_memory_clock(struct radeon_device *rdev)
91 return mclk; 91 return mclk;
92} 92}
93 93
94#ifdef CONFIG_OF
95/*
96 * Read XTAL (ref clock), SCLK and MCLK from Open Firmware device
97 * tree. Hopefully, ATI OF driver is kind enough to fill these
98 */
99static bool __devinit radeon_read_clocks_OF(struct drm_device *dev)
100{
101 struct radeon_device *rdev = dev->dev_private;
102 struct device_node *dp = rdev->pdev->dev.of_node;
103 const u32 *val;
104 struct radeon_pll *p1pll = &rdev->clock.p1pll;
105 struct radeon_pll *p2pll = &rdev->clock.p2pll;
106 struct radeon_pll *spll = &rdev->clock.spll;
107 struct radeon_pll *mpll = &rdev->clock.mpll;
108
109 if (dp == NULL)
110 return false;
111 val = of_get_property(dp, "ATY,RefCLK", NULL);
112 if (!val || !*val) {
113 printk(KERN_WARNING "radeonfb: No ATY,RefCLK property !\n");
114 return false;
115 }
116 p1pll->reference_freq = p2pll->reference_freq = (*val) / 10;
117 p1pll->reference_div = RREG32_PLL(RADEON_PPLL_REF_DIV) & 0x3ff;
118 if (p1pll->reference_div < 2)
119 p1pll->reference_div = 12;
120 p2pll->reference_div = p1pll->reference_div;
121
122 /* These aren't in the device-tree */
123 if (rdev->family >= CHIP_R420) {
124 p1pll->pll_in_min = 100;
125 p1pll->pll_in_max = 1350;
126 p1pll->pll_out_min = 20000;
127 p1pll->pll_out_max = 50000;
128 p2pll->pll_in_min = 100;
129 p2pll->pll_in_max = 1350;
130 p2pll->pll_out_min = 20000;
131 p2pll->pll_out_max = 50000;
132 } else {
133 p1pll->pll_in_min = 40;
134 p1pll->pll_in_max = 500;
135 p1pll->pll_out_min = 12500;
136 p1pll->pll_out_max = 35000;
137 p2pll->pll_in_min = 40;
138 p2pll->pll_in_max = 500;
139 p2pll->pll_out_min = 12500;
140 p2pll->pll_out_max = 35000;
141 }
142
143 spll->reference_freq = mpll->reference_freq = p1pll->reference_freq;
144 spll->reference_div = mpll->reference_div =
145 RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV) &
146 RADEON_M_SPLL_REF_DIV_MASK;
147
148 val = of_get_property(dp, "ATY,SCLK", NULL);
149 if (val && *val)
150 rdev->clock.default_sclk = (*val) / 10;
151 else
152 rdev->clock.default_sclk =
153 radeon_legacy_get_engine_clock(rdev);
154
155 val = of_get_property(dp, "ATY,MCLK", NULL);
156 if (val && *val)
157 rdev->clock.default_mclk = (*val) / 10;
158 else
159 rdev->clock.default_mclk =
160 radeon_legacy_get_memory_clock(rdev);
161
162 DRM_INFO("Using device-tree clock info\n");
163
164 return true;
165}
166#else
167static bool __devinit radeon_read_clocks_OF(struct drm_device *dev)
168{
169 return false;
170}
171#endif /* CONFIG_OF */
172
94void radeon_get_clock_info(struct drm_device *dev) 173void radeon_get_clock_info(struct drm_device *dev)
95{ 174{
96 struct radeon_device *rdev = dev->dev_private; 175 struct radeon_device *rdev = dev->dev_private;
@@ -105,6 +184,8 @@ void radeon_get_clock_info(struct drm_device *dev)
105 ret = radeon_atom_get_clock_info(dev); 184 ret = radeon_atom_get_clock_info(dev);
106 else 185 else
107 ret = radeon_combios_get_clock_info(dev); 186 ret = radeon_combios_get_clock_info(dev);
187 if (!ret)
188 ret = radeon_read_clocks_OF(dev);
108 189
109 if (ret) { 190 if (ret) {
110 if (p1pll->reference_div < 2) { 191 if (p1pll->reference_div < 2) {
diff --git a/drivers/gpu/drm/radeon/radeon_combios.c b/drivers/gpu/drm/radeon/radeon_combios.c
index 5e1474cde4b..885dcfac183 100644
--- a/drivers/gpu/drm/radeon/radeon_combios.c
+++ b/drivers/gpu/drm/radeon/radeon_combios.c
@@ -480,9 +480,66 @@ radeon_combios_get_hardcoded_edid(struct radeon_device *rdev)
480} 480}
481 481
482static struct radeon_i2c_bus_rec combios_setup_i2c_bus(struct radeon_device *rdev, 482static struct radeon_i2c_bus_rec combios_setup_i2c_bus(struct radeon_device *rdev,
483 int ddc_line) 483 enum radeon_combios_ddc ddc,
484 u32 clk_mask,
485 u32 data_mask)
484{ 486{
485 struct radeon_i2c_bus_rec i2c; 487 struct radeon_i2c_bus_rec i2c;
488 int ddc_line = 0;
489
490 /* ddc id = mask reg
491 * DDC_NONE_DETECTED = none
492 * DDC_DVI = RADEON_GPIO_DVI_DDC
493 * DDC_VGA = RADEON_GPIO_VGA_DDC
494 * DDC_LCD = RADEON_GPIOPAD_MASK
495 * DDC_GPIO = RADEON_MDGPIO_MASK
496 * r1xx/r2xx
497 * DDC_MONID = RADEON_GPIO_MONID
498 * DDC_CRT2 = RADEON_GPIO_CRT2_DDC
499 * r3xx
500 * DDC_MONID = RADEON_GPIO_MONID
501 * DDC_CRT2 = RADEON_GPIO_DVI_DDC
502 * rs3xx/rs4xx
503 * DDC_MONID = RADEON_GPIOPAD_MASK
504 * DDC_CRT2 = RADEON_GPIO_MONID
505 */
506 switch (ddc) {
507 case DDC_NONE_DETECTED:
508 default:
509 ddc_line = 0;
510 break;
511 case DDC_DVI:
512 ddc_line = RADEON_GPIO_DVI_DDC;
513 break;
514 case DDC_VGA:
515 ddc_line = RADEON_GPIO_VGA_DDC;
516 break;
517 case DDC_LCD:
518 ddc_line = RADEON_GPIOPAD_MASK;
519 break;
520 case DDC_GPIO:
521 ddc_line = RADEON_MDGPIO_MASK;
522 break;
523 case DDC_MONID:
524 if (rdev->family == CHIP_RS300 ||
525 rdev->family == CHIP_RS400 ||
526 rdev->family == CHIP_RS480)
527 ddc_line = RADEON_GPIOPAD_MASK;
528 else
529 ddc_line = RADEON_GPIO_MONID;
530 break;
531 case DDC_CRT2:
532 if (rdev->family == CHIP_RS300 ||
533 rdev->family == CHIP_RS400 ||
534 rdev->family == CHIP_RS480)
535 ddc_line = RADEON_GPIO_MONID;
536 else if (rdev->family >= CHIP_R300) {
537 ddc_line = RADEON_GPIO_DVI_DDC;
538 ddc = DDC_DVI;
539 } else
540 ddc_line = RADEON_GPIO_CRT2_DDC;
541 break;
542 }
486 543
487 if (ddc_line == RADEON_GPIOPAD_MASK) { 544 if (ddc_line == RADEON_GPIOPAD_MASK) {
488 i2c.mask_clk_reg = RADEON_GPIOPAD_MASK; 545 i2c.mask_clk_reg = RADEON_GPIOPAD_MASK;
@@ -503,15 +560,6 @@ static struct radeon_i2c_bus_rec combios_setup_i2c_bus(struct radeon_device *rde
503 i2c.y_clk_reg = RADEON_MDGPIO_Y; 560 i2c.y_clk_reg = RADEON_MDGPIO_Y;
504 i2c.y_data_reg = RADEON_MDGPIO_Y; 561 i2c.y_data_reg = RADEON_MDGPIO_Y;
505 } else { 562 } else {
506 i2c.mask_clk_mask = RADEON_GPIO_EN_1;
507 i2c.mask_data_mask = RADEON_GPIO_EN_0;
508 i2c.a_clk_mask = RADEON_GPIO_A_1;
509 i2c.a_data_mask = RADEON_GPIO_A_0;
510 i2c.en_clk_mask = RADEON_GPIO_EN_1;
511 i2c.en_data_mask = RADEON_GPIO_EN_0;
512 i2c.y_clk_mask = RADEON_GPIO_Y_1;
513 i2c.y_data_mask = RADEON_GPIO_Y_0;
514
515 i2c.mask_clk_reg = ddc_line; 563 i2c.mask_clk_reg = ddc_line;
516 i2c.mask_data_reg = ddc_line; 564 i2c.mask_data_reg = ddc_line;
517 i2c.a_clk_reg = ddc_line; 565 i2c.a_clk_reg = ddc_line;
@@ -522,6 +570,26 @@ static struct radeon_i2c_bus_rec combios_setup_i2c_bus(struct radeon_device *rde
522 i2c.y_data_reg = ddc_line; 570 i2c.y_data_reg = ddc_line;
523 } 571 }
524 572
573 if (clk_mask && data_mask) {
574 i2c.mask_clk_mask = clk_mask;
575 i2c.mask_data_mask = data_mask;
576 i2c.a_clk_mask = clk_mask;
577 i2c.a_data_mask = data_mask;
578 i2c.en_clk_mask = clk_mask;
579 i2c.en_data_mask = data_mask;
580 i2c.y_clk_mask = clk_mask;
581 i2c.y_data_mask = data_mask;
582 } else {
583 i2c.mask_clk_mask = RADEON_GPIO_EN_1;
584 i2c.mask_data_mask = RADEON_GPIO_EN_0;
585 i2c.a_clk_mask = RADEON_GPIO_A_1;
586 i2c.a_data_mask = RADEON_GPIO_A_0;
587 i2c.en_clk_mask = RADEON_GPIO_EN_1;
588 i2c.en_data_mask = RADEON_GPIO_EN_0;
589 i2c.y_clk_mask = RADEON_GPIO_Y_1;
590 i2c.y_data_mask = RADEON_GPIO_Y_0;
591 }
592
525 switch (rdev->family) { 593 switch (rdev->family) {
526 case CHIP_R100: 594 case CHIP_R100:
527 case CHIP_RV100: 595 case CHIP_RV100:
@@ -599,7 +667,8 @@ static struct radeon_i2c_bus_rec combios_setup_i2c_bus(struct radeon_device *rde
599 break; 667 break;
600 } 668 }
601 i2c.mm_i2c = false; 669 i2c.mm_i2c = false;
602 i2c.i2c_id = 0; 670
671 i2c.i2c_id = ddc;
603 i2c.hpd = RADEON_HPD_NONE; 672 i2c.hpd = RADEON_HPD_NONE;
604 673
605 if (ddc_line) 674 if (ddc_line)
@@ -610,6 +679,62 @@ static struct radeon_i2c_bus_rec combios_setup_i2c_bus(struct radeon_device *rde
610 return i2c; 679 return i2c;
611} 680}
612 681
682void radeon_combios_i2c_init(struct radeon_device *rdev)
683{
684 struct drm_device *dev = rdev->ddev;
685 struct radeon_i2c_bus_rec i2c;
686
687
688 i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
689 rdev->i2c_bus[0] = radeon_i2c_create(dev, &i2c, "DVI_DDC");
690
691 i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
692 rdev->i2c_bus[1] = radeon_i2c_create(dev, &i2c, "VGA_DDC");
693
694 i2c.valid = true;
695 i2c.hw_capable = true;
696 i2c.mm_i2c = true;
697 i2c.i2c_id = 0xa0;
698 rdev->i2c_bus[2] = radeon_i2c_create(dev, &i2c, "MM_I2C");
699
700 if (rdev->family == CHIP_RS300 ||
701 rdev->family == CHIP_RS400 ||
702 rdev->family == CHIP_RS480) {
703 u16 offset;
704 u8 id, blocks, clk, data;
705 int i;
706
707 i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
708 rdev->i2c_bus[3] = radeon_i2c_create(dev, &i2c, "MONID");
709
710 offset = combios_get_table_offset(dev, COMBIOS_I2C_INFO_TABLE);
711 if (offset) {
712 blocks = RBIOS8(offset + 2);
713 for (i = 0; i < blocks; i++) {
714 id = RBIOS8(offset + 3 + (i * 5) + 0);
715 if (id == 136) {
716 clk = RBIOS8(offset + 3 + (i * 5) + 3);
717 data = RBIOS8(offset + 3 + (i * 5) + 4);
718 i2c = combios_setup_i2c_bus(rdev, DDC_MONID,
719 clk, data);
720 rdev->i2c_bus[4] = radeon_i2c_create(dev, &i2c, "GPIOPAD_MASK");
721 break;
722 }
723 }
724 }
725
726 } else if (rdev->family >= CHIP_R300) {
727 i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
728 rdev->i2c_bus[3] = radeon_i2c_create(dev, &i2c, "MONID");
729 } else {
730 i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
731 rdev->i2c_bus[3] = radeon_i2c_create(dev, &i2c, "MONID");
732
733 i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
734 rdev->i2c_bus[4] = radeon_i2c_create(dev, &i2c, "CRT2_DDC");
735 }
736}
737
613bool radeon_combios_get_clock_info(struct drm_device *dev) 738bool radeon_combios_get_clock_info(struct drm_device *dev)
614{ 739{
615 struct radeon_device *rdev = dev->dev_private; 740 struct radeon_device *rdev = dev->dev_private;
@@ -1247,8 +1372,8 @@ bool radeon_legacy_get_ext_tmds_info_from_table(struct radeon_encoder *encoder,
1247 struct radeon_i2c_bus_rec i2c_bus; 1372 struct radeon_i2c_bus_rec i2c_bus;
1248 1373
1249 /* default for macs */ 1374 /* default for macs */
1250 i2c_bus = combios_setup_i2c_bus(rdev, RADEON_GPIO_MONID); 1375 i2c_bus = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
1251 tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO"); 1376 tmds->i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
1252 1377
1253 /* XXX some macs have duallink chips */ 1378 /* XXX some macs have duallink chips */
1254 switch (rdev->mode_info.connector_table) { 1379 switch (rdev->mode_info.connector_table) {
@@ -1269,47 +1394,16 @@ bool radeon_legacy_get_ext_tmds_info_from_combios(struct radeon_encoder *encoder
1269 struct drm_device *dev = encoder->base.dev; 1394 struct drm_device *dev = encoder->base.dev;
1270 struct radeon_device *rdev = dev->dev_private; 1395 struct radeon_device *rdev = dev->dev_private;
1271 uint16_t offset; 1396 uint16_t offset;
1272 uint8_t ver, id, blocks, clk, data; 1397 uint8_t ver;
1273 int i;
1274 enum radeon_combios_ddc gpio; 1398 enum radeon_combios_ddc gpio;
1275 struct radeon_i2c_bus_rec i2c_bus; 1399 struct radeon_i2c_bus_rec i2c_bus;
1276 1400
1277 tmds->i2c_bus = NULL; 1401 tmds->i2c_bus = NULL;
1278 if (rdev->flags & RADEON_IS_IGP) { 1402 if (rdev->flags & RADEON_IS_IGP) {
1279 offset = combios_get_table_offset(dev, COMBIOS_I2C_INFO_TABLE); 1403 i2c_bus = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
1280 if (offset) { 1404 tmds->i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
1281 ver = RBIOS8(offset); 1405 tmds->dvo_chip = DVO_SIL164;
1282 DRM_INFO("GPIO Table revision: %d\n", ver); 1406 tmds->slave_addr = 0x70 >> 1; /* 7 bit addressing */
1283 blocks = RBIOS8(offset + 2);
1284 for (i = 0; i < blocks; i++) {
1285 id = RBIOS8(offset + 3 + (i * 5) + 0);
1286 if (id == 136) {
1287 clk = RBIOS8(offset + 3 + (i * 5) + 3);
1288 data = RBIOS8(offset + 3 + (i * 5) + 4);
1289 i2c_bus.valid = true;
1290 i2c_bus.mask_clk_mask = (1 << clk);
1291 i2c_bus.mask_data_mask = (1 << data);
1292 i2c_bus.a_clk_mask = (1 << clk);
1293 i2c_bus.a_data_mask = (1 << data);
1294 i2c_bus.en_clk_mask = (1 << clk);
1295 i2c_bus.en_data_mask = (1 << data);
1296 i2c_bus.y_clk_mask = (1 << clk);
1297 i2c_bus.y_data_mask = (1 << data);
1298 i2c_bus.mask_clk_reg = RADEON_GPIOPAD_MASK;
1299 i2c_bus.mask_data_reg = RADEON_GPIOPAD_MASK;
1300 i2c_bus.a_clk_reg = RADEON_GPIOPAD_A;
1301 i2c_bus.a_data_reg = RADEON_GPIOPAD_A;
1302 i2c_bus.en_clk_reg = RADEON_GPIOPAD_EN;
1303 i2c_bus.en_data_reg = RADEON_GPIOPAD_EN;
1304 i2c_bus.y_clk_reg = RADEON_GPIOPAD_Y;
1305 i2c_bus.y_data_reg = RADEON_GPIOPAD_Y;
1306 tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO");
1307 tmds->dvo_chip = DVO_SIL164;
1308 tmds->slave_addr = 0x70 >> 1; /* 7 bit addressing */
1309 break;
1310 }
1311 }
1312 }
1313 } else { 1407 } else {
1314 offset = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE); 1408 offset = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE);
1315 if (offset) { 1409 if (offset) {
@@ -1318,37 +1412,15 @@ bool radeon_legacy_get_ext_tmds_info_from_combios(struct radeon_encoder *encoder
1318 tmds->slave_addr = RBIOS8(offset + 4 + 2); 1412 tmds->slave_addr = RBIOS8(offset + 4 + 2);
1319 tmds->slave_addr >>= 1; /* 7 bit addressing */ 1413 tmds->slave_addr >>= 1; /* 7 bit addressing */
1320 gpio = RBIOS8(offset + 4 + 3); 1414 gpio = RBIOS8(offset + 4 + 3);
1321 switch (gpio) { 1415 if (gpio == DDC_LCD) {
1322 case DDC_MONID: 1416 /* MM i2c */
1323 i2c_bus = combios_setup_i2c_bus(rdev, RADEON_GPIO_MONID);
1324 tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO");
1325 break;
1326 case DDC_DVI:
1327 i2c_bus = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
1328 tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO");
1329 break;
1330 case DDC_VGA:
1331 i2c_bus = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
1332 tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO");
1333 break;
1334 case DDC_CRT2:
1335 /* R3xx+ chips don't have GPIO_CRT2_DDC gpio pad */
1336 if (rdev->family >= CHIP_R300)
1337 i2c_bus = combios_setup_i2c_bus(rdev, RADEON_GPIO_MONID);
1338 else
1339 i2c_bus = combios_setup_i2c_bus(rdev, RADEON_GPIO_CRT2_DDC);
1340 tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO");
1341 break;
1342 case DDC_LCD: /* MM i2c */
1343 i2c_bus.valid = true; 1417 i2c_bus.valid = true;
1344 i2c_bus.hw_capable = true; 1418 i2c_bus.hw_capable = true;
1345 i2c_bus.mm_i2c = true; 1419 i2c_bus.mm_i2c = true;
1346 tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO"); 1420 i2c_bus.i2c_id = 0xa0;
1347 break; 1421 } else
1348 default: 1422 i2c_bus = combios_setup_i2c_bus(rdev, gpio, 0, 0);
1349 DRM_ERROR("Unsupported gpio %d\n", gpio); 1423 tmds->i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
1350 break;
1351 }
1352 } 1424 }
1353 } 1425 }
1354 1426
@@ -1430,7 +1502,7 @@ bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
1430 /* these are the most common settings */ 1502 /* these are the most common settings */
1431 if (rdev->flags & RADEON_SINGLE_CRTC) { 1503 if (rdev->flags & RADEON_SINGLE_CRTC) {
1432 /* VGA - primary dac */ 1504 /* VGA - primary dac */
1433 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC); 1505 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1434 hpd.hpd = RADEON_HPD_NONE; 1506 hpd.hpd = RADEON_HPD_NONE;
1435 radeon_add_legacy_encoder(dev, 1507 radeon_add_legacy_encoder(dev,
1436 radeon_get_encoder_id(dev, 1508 radeon_get_encoder_id(dev,
@@ -1445,7 +1517,7 @@ bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
1445 &hpd); 1517 &hpd);
1446 } else if (rdev->flags & RADEON_IS_MOBILITY) { 1518 } else if (rdev->flags & RADEON_IS_MOBILITY) {
1447 /* LVDS */ 1519 /* LVDS */
1448 ddc_i2c = combios_setup_i2c_bus(rdev, 0); 1520 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_NONE_DETECTED, 0, 0);
1449 hpd.hpd = RADEON_HPD_NONE; 1521 hpd.hpd = RADEON_HPD_NONE;
1450 radeon_add_legacy_encoder(dev, 1522 radeon_add_legacy_encoder(dev,
1451 radeon_get_encoder_id(dev, 1523 radeon_get_encoder_id(dev,
@@ -1460,7 +1532,7 @@ bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
1460 &hpd); 1532 &hpd);
1461 1533
1462 /* VGA - primary dac */ 1534 /* VGA - primary dac */
1463 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC); 1535 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1464 hpd.hpd = RADEON_HPD_NONE; 1536 hpd.hpd = RADEON_HPD_NONE;
1465 radeon_add_legacy_encoder(dev, 1537 radeon_add_legacy_encoder(dev,
1466 radeon_get_encoder_id(dev, 1538 radeon_get_encoder_id(dev,
@@ -1475,7 +1547,7 @@ bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
1475 &hpd); 1547 &hpd);
1476 } else { 1548 } else {
1477 /* DVI-I - tv dac, int tmds */ 1549 /* DVI-I - tv dac, int tmds */
1478 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC); 1550 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1479 hpd.hpd = RADEON_HPD_1; 1551 hpd.hpd = RADEON_HPD_1;
1480 radeon_add_legacy_encoder(dev, 1552 radeon_add_legacy_encoder(dev,
1481 radeon_get_encoder_id(dev, 1553 radeon_get_encoder_id(dev,
@@ -1496,7 +1568,7 @@ bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
1496 &hpd); 1568 &hpd);
1497 1569
1498 /* VGA - primary dac */ 1570 /* VGA - primary dac */
1499 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC); 1571 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1500 hpd.hpd = RADEON_HPD_NONE; 1572 hpd.hpd = RADEON_HPD_NONE;
1501 radeon_add_legacy_encoder(dev, 1573 radeon_add_legacy_encoder(dev,
1502 radeon_get_encoder_id(dev, 1574 radeon_get_encoder_id(dev,
@@ -1532,7 +1604,7 @@ bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
1532 DRM_INFO("Connector Table: %d (ibook)\n", 1604 DRM_INFO("Connector Table: %d (ibook)\n",
1533 rdev->mode_info.connector_table); 1605 rdev->mode_info.connector_table);
1534 /* LVDS */ 1606 /* LVDS */
1535 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC); 1607 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1536 hpd.hpd = RADEON_HPD_NONE; 1608 hpd.hpd = RADEON_HPD_NONE;
1537 radeon_add_legacy_encoder(dev, 1609 radeon_add_legacy_encoder(dev,
1538 radeon_get_encoder_id(dev, 1610 radeon_get_encoder_id(dev,
@@ -1544,7 +1616,7 @@ bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
1544 CONNECTOR_OBJECT_ID_LVDS, 1616 CONNECTOR_OBJECT_ID_LVDS,
1545 &hpd); 1617 &hpd);
1546 /* VGA - TV DAC */ 1618 /* VGA - TV DAC */
1547 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC); 1619 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1548 hpd.hpd = RADEON_HPD_NONE; 1620 hpd.hpd = RADEON_HPD_NONE;
1549 radeon_add_legacy_encoder(dev, 1621 radeon_add_legacy_encoder(dev,
1550 radeon_get_encoder_id(dev, 1622 radeon_get_encoder_id(dev,
@@ -1573,7 +1645,7 @@ bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
1573 DRM_INFO("Connector Table: %d (powerbook external tmds)\n", 1645 DRM_INFO("Connector Table: %d (powerbook external tmds)\n",
1574 rdev->mode_info.connector_table); 1646 rdev->mode_info.connector_table);
1575 /* LVDS */ 1647 /* LVDS */
1576 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC); 1648 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1577 hpd.hpd = RADEON_HPD_NONE; 1649 hpd.hpd = RADEON_HPD_NONE;
1578 radeon_add_legacy_encoder(dev, 1650 radeon_add_legacy_encoder(dev,
1579 radeon_get_encoder_id(dev, 1651 radeon_get_encoder_id(dev,
@@ -1585,7 +1657,7 @@ bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
1585 CONNECTOR_OBJECT_ID_LVDS, 1657 CONNECTOR_OBJECT_ID_LVDS,
1586 &hpd); 1658 &hpd);
1587 /* DVI-I - primary dac, ext tmds */ 1659 /* DVI-I - primary dac, ext tmds */
1588 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC); 1660 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1589 hpd.hpd = RADEON_HPD_2; /* ??? */ 1661 hpd.hpd = RADEON_HPD_2; /* ??? */
1590 radeon_add_legacy_encoder(dev, 1662 radeon_add_legacy_encoder(dev,
1591 radeon_get_encoder_id(dev, 1663 radeon_get_encoder_id(dev,
@@ -1622,7 +1694,7 @@ bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
1622 DRM_INFO("Connector Table: %d (powerbook internal tmds)\n", 1694 DRM_INFO("Connector Table: %d (powerbook internal tmds)\n",
1623 rdev->mode_info.connector_table); 1695 rdev->mode_info.connector_table);
1624 /* LVDS */ 1696 /* LVDS */
1625 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC); 1697 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1626 hpd.hpd = RADEON_HPD_NONE; 1698 hpd.hpd = RADEON_HPD_NONE;
1627 radeon_add_legacy_encoder(dev, 1699 radeon_add_legacy_encoder(dev,
1628 radeon_get_encoder_id(dev, 1700 radeon_get_encoder_id(dev,
@@ -1634,7 +1706,7 @@ bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
1634 CONNECTOR_OBJECT_ID_LVDS, 1706 CONNECTOR_OBJECT_ID_LVDS,
1635 &hpd); 1707 &hpd);
1636 /* DVI-I - primary dac, int tmds */ 1708 /* DVI-I - primary dac, int tmds */
1637 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC); 1709 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1638 hpd.hpd = RADEON_HPD_1; /* ??? */ 1710 hpd.hpd = RADEON_HPD_1; /* ??? */
1639 radeon_add_legacy_encoder(dev, 1711 radeon_add_legacy_encoder(dev,
1640 radeon_get_encoder_id(dev, 1712 radeon_get_encoder_id(dev,
@@ -1670,7 +1742,7 @@ bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
1670 DRM_INFO("Connector Table: %d (powerbook vga)\n", 1742 DRM_INFO("Connector Table: %d (powerbook vga)\n",
1671 rdev->mode_info.connector_table); 1743 rdev->mode_info.connector_table);
1672 /* LVDS */ 1744 /* LVDS */
1673 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC); 1745 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1674 hpd.hpd = RADEON_HPD_NONE; 1746 hpd.hpd = RADEON_HPD_NONE;
1675 radeon_add_legacy_encoder(dev, 1747 radeon_add_legacy_encoder(dev,
1676 radeon_get_encoder_id(dev, 1748 radeon_get_encoder_id(dev,
@@ -1682,7 +1754,7 @@ bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
1682 CONNECTOR_OBJECT_ID_LVDS, 1754 CONNECTOR_OBJECT_ID_LVDS,
1683 &hpd); 1755 &hpd);
1684 /* VGA - primary dac */ 1756 /* VGA - primary dac */
1685 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC); 1757 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1686 hpd.hpd = RADEON_HPD_NONE; 1758 hpd.hpd = RADEON_HPD_NONE;
1687 radeon_add_legacy_encoder(dev, 1759 radeon_add_legacy_encoder(dev,
1688 radeon_get_encoder_id(dev, 1760 radeon_get_encoder_id(dev,
@@ -1711,7 +1783,7 @@ bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
1711 DRM_INFO("Connector Table: %d (mini external tmds)\n", 1783 DRM_INFO("Connector Table: %d (mini external tmds)\n",
1712 rdev->mode_info.connector_table); 1784 rdev->mode_info.connector_table);
1713 /* DVI-I - tv dac, ext tmds */ 1785 /* DVI-I - tv dac, ext tmds */
1714 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_CRT2_DDC); 1786 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
1715 hpd.hpd = RADEON_HPD_2; /* ??? */ 1787 hpd.hpd = RADEON_HPD_2; /* ??? */
1716 radeon_add_legacy_encoder(dev, 1788 radeon_add_legacy_encoder(dev,
1717 radeon_get_encoder_id(dev, 1789 radeon_get_encoder_id(dev,
@@ -1748,7 +1820,7 @@ bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
1748 DRM_INFO("Connector Table: %d (mini internal tmds)\n", 1820 DRM_INFO("Connector Table: %d (mini internal tmds)\n",
1749 rdev->mode_info.connector_table); 1821 rdev->mode_info.connector_table);
1750 /* DVI-I - tv dac, int tmds */ 1822 /* DVI-I - tv dac, int tmds */
1751 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_CRT2_DDC); 1823 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
1752 hpd.hpd = RADEON_HPD_1; /* ??? */ 1824 hpd.hpd = RADEON_HPD_1; /* ??? */
1753 radeon_add_legacy_encoder(dev, 1825 radeon_add_legacy_encoder(dev,
1754 radeon_get_encoder_id(dev, 1826 radeon_get_encoder_id(dev,
@@ -1784,7 +1856,7 @@ bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
1784 DRM_INFO("Connector Table: %d (imac g5 isight)\n", 1856 DRM_INFO("Connector Table: %d (imac g5 isight)\n",
1785 rdev->mode_info.connector_table); 1857 rdev->mode_info.connector_table);
1786 /* DVI-D - int tmds */ 1858 /* DVI-D - int tmds */
1787 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_MONID); 1859 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
1788 hpd.hpd = RADEON_HPD_1; /* ??? */ 1860 hpd.hpd = RADEON_HPD_1; /* ??? */
1789 radeon_add_legacy_encoder(dev, 1861 radeon_add_legacy_encoder(dev,
1790 radeon_get_encoder_id(dev, 1862 radeon_get_encoder_id(dev,
@@ -1796,7 +1868,7 @@ bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
1796 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D, 1868 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D,
1797 &hpd); 1869 &hpd);
1798 /* VGA - tv dac */ 1870 /* VGA - tv dac */
1799 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC); 1871 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1800 hpd.hpd = RADEON_HPD_NONE; 1872 hpd.hpd = RADEON_HPD_NONE;
1801 radeon_add_legacy_encoder(dev, 1873 radeon_add_legacy_encoder(dev,
1802 radeon_get_encoder_id(dev, 1874 radeon_get_encoder_id(dev,
@@ -1825,7 +1897,7 @@ bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
1825 DRM_INFO("Connector Table: %d (emac)\n", 1897 DRM_INFO("Connector Table: %d (emac)\n",
1826 rdev->mode_info.connector_table); 1898 rdev->mode_info.connector_table);
1827 /* VGA - primary dac */ 1899 /* VGA - primary dac */
1828 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC); 1900 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1829 hpd.hpd = RADEON_HPD_NONE; 1901 hpd.hpd = RADEON_HPD_NONE;
1830 radeon_add_legacy_encoder(dev, 1902 radeon_add_legacy_encoder(dev,
1831 radeon_get_encoder_id(dev, 1903 radeon_get_encoder_id(dev,
@@ -1837,7 +1909,7 @@ bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
1837 CONNECTOR_OBJECT_ID_VGA, 1909 CONNECTOR_OBJECT_ID_VGA,
1838 &hpd); 1910 &hpd);
1839 /* VGA - tv dac */ 1911 /* VGA - tv dac */
1840 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_CRT2_DDC); 1912 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
1841 hpd.hpd = RADEON_HPD_NONE; 1913 hpd.hpd = RADEON_HPD_NONE;
1842 radeon_add_legacy_encoder(dev, 1914 radeon_add_legacy_encoder(dev,
1843 radeon_get_encoder_id(dev, 1915 radeon_get_encoder_id(dev,
@@ -1866,7 +1938,7 @@ bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
1866 DRM_INFO("Connector Table: %d (rn50-power)\n", 1938 DRM_INFO("Connector Table: %d (rn50-power)\n",
1867 rdev->mode_info.connector_table); 1939 rdev->mode_info.connector_table);
1868 /* VGA - primary dac */ 1940 /* VGA - primary dac */
1869 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC); 1941 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1870 hpd.hpd = RADEON_HPD_NONE; 1942 hpd.hpd = RADEON_HPD_NONE;
1871 radeon_add_legacy_encoder(dev, 1943 radeon_add_legacy_encoder(dev,
1872 radeon_get_encoder_id(dev, 1944 radeon_get_encoder_id(dev,
@@ -1877,7 +1949,7 @@ bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
1877 DRM_MODE_CONNECTOR_VGA, &ddc_i2c, 1949 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1878 CONNECTOR_OBJECT_ID_VGA, 1950 CONNECTOR_OBJECT_ID_VGA,
1879 &hpd); 1951 &hpd);
1880 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_CRT2_DDC); 1952 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
1881 hpd.hpd = RADEON_HPD_NONE; 1953 hpd.hpd = RADEON_HPD_NONE;
1882 radeon_add_legacy_encoder(dev, 1954 radeon_add_legacy_encoder(dev,
1883 radeon_get_encoder_id(dev, 1955 radeon_get_encoder_id(dev,
@@ -1907,31 +1979,6 @@ static bool radeon_apply_legacy_quirks(struct drm_device *dev,
1907 struct radeon_i2c_bus_rec *ddc_i2c, 1979 struct radeon_i2c_bus_rec *ddc_i2c,
1908 struct radeon_hpd *hpd) 1980 struct radeon_hpd *hpd)
1909{ 1981{
1910 struct radeon_device *rdev = dev->dev_private;
1911
1912 /* XPRESS DDC quirks */
1913 if ((rdev->family == CHIP_RS400 ||
1914 rdev->family == CHIP_RS480) &&
1915 ddc_i2c->mask_clk_reg == RADEON_GPIO_CRT2_DDC)
1916 *ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_MONID);
1917 else if ((rdev->family == CHIP_RS400 ||
1918 rdev->family == CHIP_RS480) &&
1919 ddc_i2c->mask_clk_reg == RADEON_GPIO_MONID) {
1920 *ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIOPAD_MASK);
1921 ddc_i2c->mask_clk_mask = (0x20 << 8);
1922 ddc_i2c->mask_data_mask = 0x80;
1923 ddc_i2c->a_clk_mask = (0x20 << 8);
1924 ddc_i2c->a_data_mask = 0x80;
1925 ddc_i2c->en_clk_mask = (0x20 << 8);
1926 ddc_i2c->en_data_mask = 0x80;
1927 ddc_i2c->y_clk_mask = (0x20 << 8);
1928 ddc_i2c->y_data_mask = 0x80;
1929 }
1930
1931 /* R3xx+ chips don't have GPIO_CRT2_DDC gpio pad */
1932 if ((rdev->family >= CHIP_R300) &&
1933 ddc_i2c->mask_clk_reg == RADEON_GPIO_CRT2_DDC)
1934 *ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
1935 1982
1936 /* Certain IBM chipset RN50s have a BIOS reporting two VGAs, 1983 /* Certain IBM chipset RN50s have a BIOS reporting two VGAs,
1937 one with VGA DDC and one with CRT2 DDC. - kill the CRT2 DDC one */ 1984 one with VGA DDC and one with CRT2 DDC. - kill the CRT2 DDC one */
@@ -2035,27 +2082,7 @@ bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev)
2035 connector = (tmp >> 12) & 0xf; 2082 connector = (tmp >> 12) & 0xf;
2036 2083
2037 ddc_type = (tmp >> 8) & 0xf; 2084 ddc_type = (tmp >> 8) & 0xf;
2038 switch (ddc_type) { 2085 ddc_i2c = combios_setup_i2c_bus(rdev, ddc_type, 0, 0);
2039 case DDC_MONID:
2040 ddc_i2c =
2041 combios_setup_i2c_bus(rdev, RADEON_GPIO_MONID);
2042 break;
2043 case DDC_DVI:
2044 ddc_i2c =
2045 combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
2046 break;
2047 case DDC_VGA:
2048 ddc_i2c =
2049 combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
2050 break;
2051 case DDC_CRT2:
2052 ddc_i2c =
2053 combios_setup_i2c_bus(rdev, RADEON_GPIO_CRT2_DDC);
2054 break;
2055 default:
2056 ddc_i2c.valid = false;
2057 break;
2058 }
2059 2086
2060 switch (connector) { 2087 switch (connector) {
2061 case CONNECTOR_PROPRIETARY_LEGACY: 2088 case CONNECTOR_PROPRIETARY_LEGACY:
@@ -2225,7 +2252,7 @@ bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev)
2225 0), 2252 0),
2226 ATOM_DEVICE_DFP1_SUPPORT); 2253 ATOM_DEVICE_DFP1_SUPPORT);
2227 2254
2228 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC); 2255 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
2229 hpd.hpd = RADEON_HPD_1; 2256 hpd.hpd = RADEON_HPD_1;
2230 radeon_add_legacy_connector(dev, 2257 radeon_add_legacy_connector(dev,
2231 0, 2258 0,
@@ -2245,7 +2272,7 @@ bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev)
2245 ATOM_DEVICE_CRT1_SUPPORT, 2272 ATOM_DEVICE_CRT1_SUPPORT,
2246 1), 2273 1),
2247 ATOM_DEVICE_CRT1_SUPPORT); 2274 ATOM_DEVICE_CRT1_SUPPORT);
2248 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC); 2275 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
2249 hpd.hpd = RADEON_HPD_NONE; 2276 hpd.hpd = RADEON_HPD_NONE;
2250 radeon_add_legacy_connector(dev, 2277 radeon_add_legacy_connector(dev,
2251 0, 2278 0,
@@ -2278,70 +2305,25 @@ bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev)
2278 if (lcd_ddc_info) { 2305 if (lcd_ddc_info) {
2279 ddc_type = RBIOS8(lcd_ddc_info + 2); 2306 ddc_type = RBIOS8(lcd_ddc_info + 2);
2280 switch (ddc_type) { 2307 switch (ddc_type) {
2281 case DDC_MONID:
2282 ddc_i2c =
2283 combios_setup_i2c_bus
2284 (rdev, RADEON_GPIO_MONID);
2285 break;
2286 case DDC_DVI:
2287 ddc_i2c =
2288 combios_setup_i2c_bus
2289 (rdev, RADEON_GPIO_DVI_DDC);
2290 break;
2291 case DDC_VGA:
2292 ddc_i2c =
2293 combios_setup_i2c_bus
2294 (rdev, RADEON_GPIO_VGA_DDC);
2295 break;
2296 case DDC_CRT2:
2297 ddc_i2c =
2298 combios_setup_i2c_bus
2299 (rdev, RADEON_GPIO_CRT2_DDC);
2300 break;
2301 case DDC_LCD: 2308 case DDC_LCD:
2302 ddc_i2c = 2309 ddc_i2c =
2303 combios_setup_i2c_bus 2310 combios_setup_i2c_bus(rdev,
2304 (rdev, RADEON_GPIOPAD_MASK); 2311 DDC_LCD,
2305 ddc_i2c.mask_clk_mask = 2312 RBIOS32(lcd_ddc_info + 3),
2306 RBIOS32(lcd_ddc_info + 3); 2313 RBIOS32(lcd_ddc_info + 7));
2307 ddc_i2c.mask_data_mask = 2314 radeon_i2c_add(rdev, &ddc_i2c, "LCD");
2308 RBIOS32(lcd_ddc_info + 7);
2309 ddc_i2c.a_clk_mask =
2310 RBIOS32(lcd_ddc_info + 3);
2311 ddc_i2c.a_data_mask =
2312 RBIOS32(lcd_ddc_info + 7);
2313 ddc_i2c.en_clk_mask =
2314 RBIOS32(lcd_ddc_info + 3);
2315 ddc_i2c.en_data_mask =
2316 RBIOS32(lcd_ddc_info + 7);
2317 ddc_i2c.y_clk_mask =
2318 RBIOS32(lcd_ddc_info + 3);
2319 ddc_i2c.y_data_mask =
2320 RBIOS32(lcd_ddc_info + 7);
2321 break; 2315 break;
2322 case DDC_GPIO: 2316 case DDC_GPIO:
2323 ddc_i2c = 2317 ddc_i2c =
2324 combios_setup_i2c_bus 2318 combios_setup_i2c_bus(rdev,
2325 (rdev, RADEON_MDGPIO_MASK); 2319 DDC_GPIO,
2326 ddc_i2c.mask_clk_mask = 2320 RBIOS32(lcd_ddc_info + 3),
2327 RBIOS32(lcd_ddc_info + 3); 2321 RBIOS32(lcd_ddc_info + 7));
2328 ddc_i2c.mask_data_mask = 2322 radeon_i2c_add(rdev, &ddc_i2c, "LCD");
2329 RBIOS32(lcd_ddc_info + 7);
2330 ddc_i2c.a_clk_mask =
2331 RBIOS32(lcd_ddc_info + 3);
2332 ddc_i2c.a_data_mask =
2333 RBIOS32(lcd_ddc_info + 7);
2334 ddc_i2c.en_clk_mask =
2335 RBIOS32(lcd_ddc_info + 3);
2336 ddc_i2c.en_data_mask =
2337 RBIOS32(lcd_ddc_info + 7);
2338 ddc_i2c.y_clk_mask =
2339 RBIOS32(lcd_ddc_info + 3);
2340 ddc_i2c.y_data_mask =
2341 RBIOS32(lcd_ddc_info + 7);
2342 break; 2323 break;
2343 default: 2324 default:
2344 ddc_i2c.valid = false; 2325 ddc_i2c =
2326 combios_setup_i2c_bus(rdev, ddc_type, 0, 0);
2345 break; 2327 break;
2346 } 2328 }
2347 DRM_DEBUG_KMS("LCD DDC Info Table found!\n"); 2329 DRM_DEBUG_KMS("LCD DDC Info Table found!\n");
diff --git a/drivers/gpu/drm/radeon/radeon_connectors.c b/drivers/gpu/drm/radeon/radeon_connectors.c
index 2395c8600cf..47c4b276d30 100644
--- a/drivers/gpu/drm/radeon/radeon_connectors.c
+++ b/drivers/gpu/drm/radeon/radeon_connectors.c
@@ -518,8 +518,6 @@ static void radeon_connector_destroy(struct drm_connector *connector)
518{ 518{
519 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 519 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
520 520
521 if (radeon_connector->ddc_bus)
522 radeon_i2c_destroy(radeon_connector->ddc_bus);
523 if (radeon_connector->edid) 521 if (radeon_connector->edid)
524 kfree(radeon_connector->edid); 522 kfree(radeon_connector->edid);
525 kfree(radeon_connector->con_priv); 523 kfree(radeon_connector->con_priv);
@@ -955,8 +953,6 @@ static void radeon_dp_connector_destroy(struct drm_connector *connector)
955 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 953 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
956 struct radeon_connector_atom_dig *radeon_dig_connector = radeon_connector->con_priv; 954 struct radeon_connector_atom_dig *radeon_dig_connector = radeon_connector->con_priv;
957 955
958 if (radeon_connector->ddc_bus)
959 radeon_i2c_destroy(radeon_connector->ddc_bus);
960 if (radeon_connector->edid) 956 if (radeon_connector->edid)
961 kfree(radeon_connector->edid); 957 kfree(radeon_connector->edid);
962 if (radeon_dig_connector->dp_i2c_bus) 958 if (radeon_dig_connector->dp_i2c_bus)
@@ -1044,7 +1040,8 @@ radeon_add_atom_connector(struct drm_device *dev,
1044 bool linkb, 1040 bool linkb,
1045 uint32_t igp_lane_info, 1041 uint32_t igp_lane_info,
1046 uint16_t connector_object_id, 1042 uint16_t connector_object_id,
1047 struct radeon_hpd *hpd) 1043 struct radeon_hpd *hpd,
1044 struct radeon_router *router)
1048{ 1045{
1049 struct radeon_device *rdev = dev->dev_private; 1046 struct radeon_device *rdev = dev->dev_private;
1050 struct drm_connector *connector; 1047 struct drm_connector *connector;
@@ -1069,6 +1066,11 @@ radeon_add_atom_connector(struct drm_device *dev,
1069 radeon_connector->shared_ddc = true; 1066 radeon_connector->shared_ddc = true;
1070 shared_ddc = true; 1067 shared_ddc = true;
1071 } 1068 }
1069 if (radeon_connector->router_bus && router->valid &&
1070 (radeon_connector->router.router_id == router->router_id)) {
1071 radeon_connector->shared_ddc = false;
1072 shared_ddc = false;
1073 }
1072 } 1074 }
1073 } 1075 }
1074 1076
@@ -1083,12 +1085,18 @@ radeon_add_atom_connector(struct drm_device *dev,
1083 radeon_connector->shared_ddc = shared_ddc; 1085 radeon_connector->shared_ddc = shared_ddc;
1084 radeon_connector->connector_object_id = connector_object_id; 1086 radeon_connector->connector_object_id = connector_object_id;
1085 radeon_connector->hpd = *hpd; 1087 radeon_connector->hpd = *hpd;
1088 radeon_connector->router = *router;
1089 if (router->valid) {
1090 radeon_connector->router_bus = radeon_i2c_lookup(rdev, &router->i2c_info);
1091 if (!radeon_connector->router_bus)
1092 goto failed;
1093 }
1086 switch (connector_type) { 1094 switch (connector_type) {
1087 case DRM_MODE_CONNECTOR_VGA: 1095 case DRM_MODE_CONNECTOR_VGA:
1088 drm_connector_init(dev, &radeon_connector->base, &radeon_vga_connector_funcs, connector_type); 1096 drm_connector_init(dev, &radeon_connector->base, &radeon_vga_connector_funcs, connector_type);
1089 drm_connector_helper_add(&radeon_connector->base, &radeon_vga_connector_helper_funcs); 1097 drm_connector_helper_add(&radeon_connector->base, &radeon_vga_connector_helper_funcs);
1090 if (i2c_bus->valid) { 1098 if (i2c_bus->valid) {
1091 radeon_connector->ddc_bus = radeon_i2c_create(dev, i2c_bus, "VGA"); 1099 radeon_connector->ddc_bus = radeon_i2c_lookup(rdev, i2c_bus);
1092 if (!radeon_connector->ddc_bus) 1100 if (!radeon_connector->ddc_bus)
1093 goto failed; 1101 goto failed;
1094 } 1102 }
@@ -1104,7 +1112,7 @@ radeon_add_atom_connector(struct drm_device *dev,
1104 drm_connector_init(dev, &radeon_connector->base, &radeon_vga_connector_funcs, connector_type); 1112 drm_connector_init(dev, &radeon_connector->base, &radeon_vga_connector_funcs, connector_type);
1105 drm_connector_helper_add(&radeon_connector->base, &radeon_vga_connector_helper_funcs); 1113 drm_connector_helper_add(&radeon_connector->base, &radeon_vga_connector_helper_funcs);
1106 if (i2c_bus->valid) { 1114 if (i2c_bus->valid) {
1107 radeon_connector->ddc_bus = radeon_i2c_create(dev, i2c_bus, "DVI"); 1115 radeon_connector->ddc_bus = radeon_i2c_lookup(rdev, i2c_bus);
1108 if (!radeon_connector->ddc_bus) 1116 if (!radeon_connector->ddc_bus)
1109 goto failed; 1117 goto failed;
1110 } 1118 }
@@ -1126,7 +1134,7 @@ radeon_add_atom_connector(struct drm_device *dev,
1126 drm_connector_init(dev, &radeon_connector->base, &radeon_dvi_connector_funcs, connector_type); 1134 drm_connector_init(dev, &radeon_connector->base, &radeon_dvi_connector_funcs, connector_type);
1127 drm_connector_helper_add(&radeon_connector->base, &radeon_dvi_connector_helper_funcs); 1135 drm_connector_helper_add(&radeon_connector->base, &radeon_dvi_connector_helper_funcs);
1128 if (i2c_bus->valid) { 1136 if (i2c_bus->valid) {
1129 radeon_connector->ddc_bus = radeon_i2c_create(dev, i2c_bus, "DVI"); 1137 radeon_connector->ddc_bus = radeon_i2c_lookup(rdev, i2c_bus);
1130 if (!radeon_connector->ddc_bus) 1138 if (!radeon_connector->ddc_bus)
1131 goto failed; 1139 goto failed;
1132 } 1140 }
@@ -1156,7 +1164,7 @@ radeon_add_atom_connector(struct drm_device *dev,
1156 drm_connector_init(dev, &radeon_connector->base, &radeon_dvi_connector_funcs, connector_type); 1164 drm_connector_init(dev, &radeon_connector->base, &radeon_dvi_connector_funcs, connector_type);
1157 drm_connector_helper_add(&radeon_connector->base, &radeon_dvi_connector_helper_funcs); 1165 drm_connector_helper_add(&radeon_connector->base, &radeon_dvi_connector_helper_funcs);
1158 if (i2c_bus->valid) { 1166 if (i2c_bus->valid) {
1159 radeon_connector->ddc_bus = radeon_i2c_create(dev, i2c_bus, "HDMI"); 1167 radeon_connector->ddc_bus = radeon_i2c_lookup(rdev, i2c_bus);
1160 if (!radeon_connector->ddc_bus) 1168 if (!radeon_connector->ddc_bus)
1161 goto failed; 1169 goto failed;
1162 } 1170 }
@@ -1187,10 +1195,7 @@ radeon_add_atom_connector(struct drm_device *dev,
1187 radeon_dig_connector->dp_i2c_bus = radeon_i2c_create_dp(dev, i2c_bus, "DP-auxch"); 1195 radeon_dig_connector->dp_i2c_bus = radeon_i2c_create_dp(dev, i2c_bus, "DP-auxch");
1188 if (!radeon_dig_connector->dp_i2c_bus) 1196 if (!radeon_dig_connector->dp_i2c_bus)
1189 goto failed; 1197 goto failed;
1190 if (connector_type == DRM_MODE_CONNECTOR_eDP) 1198 radeon_connector->ddc_bus = radeon_i2c_lookup(rdev, i2c_bus);
1191 radeon_connector->ddc_bus = radeon_i2c_create(dev, i2c_bus, "eDP");
1192 else
1193 radeon_connector->ddc_bus = radeon_i2c_create(dev, i2c_bus, "DP");
1194 if (!radeon_connector->ddc_bus) 1199 if (!radeon_connector->ddc_bus)
1195 goto failed; 1200 goto failed;
1196 } 1201 }
@@ -1230,7 +1235,7 @@ radeon_add_atom_connector(struct drm_device *dev,
1230 drm_connector_init(dev, &radeon_connector->base, &radeon_lvds_connector_funcs, connector_type); 1235 drm_connector_init(dev, &radeon_connector->base, &radeon_lvds_connector_funcs, connector_type);
1231 drm_connector_helper_add(&radeon_connector->base, &radeon_lvds_connector_helper_funcs); 1236 drm_connector_helper_add(&radeon_connector->base, &radeon_lvds_connector_helper_funcs);
1232 if (i2c_bus->valid) { 1237 if (i2c_bus->valid) {
1233 radeon_connector->ddc_bus = radeon_i2c_create(dev, i2c_bus, "LVDS"); 1238 radeon_connector->ddc_bus = radeon_i2c_lookup(rdev, i2c_bus);
1234 if (!radeon_connector->ddc_bus) 1239 if (!radeon_connector->ddc_bus)
1235 goto failed; 1240 goto failed;
1236 } 1241 }
@@ -1252,8 +1257,6 @@ radeon_add_atom_connector(struct drm_device *dev,
1252 return; 1257 return;
1253 1258
1254failed: 1259failed:
1255 if (radeon_connector->ddc_bus)
1256 radeon_i2c_destroy(radeon_connector->ddc_bus);
1257 drm_connector_cleanup(connector); 1260 drm_connector_cleanup(connector);
1258 kfree(connector); 1261 kfree(connector);
1259} 1262}
@@ -1300,7 +1303,7 @@ radeon_add_legacy_connector(struct drm_device *dev,
1300 drm_connector_init(dev, &radeon_connector->base, &radeon_vga_connector_funcs, connector_type); 1303 drm_connector_init(dev, &radeon_connector->base, &radeon_vga_connector_funcs, connector_type);
1301 drm_connector_helper_add(&radeon_connector->base, &radeon_vga_connector_helper_funcs); 1304 drm_connector_helper_add(&radeon_connector->base, &radeon_vga_connector_helper_funcs);
1302 if (i2c_bus->valid) { 1305 if (i2c_bus->valid) {
1303 radeon_connector->ddc_bus = radeon_i2c_create(dev, i2c_bus, "VGA"); 1306 radeon_connector->ddc_bus = radeon_i2c_lookup(rdev, i2c_bus);
1304 if (!radeon_connector->ddc_bus) 1307 if (!radeon_connector->ddc_bus)
1305 goto failed; 1308 goto failed;
1306 } 1309 }
@@ -1316,7 +1319,7 @@ radeon_add_legacy_connector(struct drm_device *dev,
1316 drm_connector_init(dev, &radeon_connector->base, &radeon_vga_connector_funcs, connector_type); 1319 drm_connector_init(dev, &radeon_connector->base, &radeon_vga_connector_funcs, connector_type);
1317 drm_connector_helper_add(&radeon_connector->base, &radeon_vga_connector_helper_funcs); 1320 drm_connector_helper_add(&radeon_connector->base, &radeon_vga_connector_helper_funcs);
1318 if (i2c_bus->valid) { 1321 if (i2c_bus->valid) {
1319 radeon_connector->ddc_bus = radeon_i2c_create(dev, i2c_bus, "DVI"); 1322 radeon_connector->ddc_bus = radeon_i2c_lookup(rdev, i2c_bus);
1320 if (!radeon_connector->ddc_bus) 1323 if (!radeon_connector->ddc_bus)
1321 goto failed; 1324 goto failed;
1322 } 1325 }
@@ -1332,7 +1335,7 @@ radeon_add_legacy_connector(struct drm_device *dev,
1332 drm_connector_init(dev, &radeon_connector->base, &radeon_dvi_connector_funcs, connector_type); 1335 drm_connector_init(dev, &radeon_connector->base, &radeon_dvi_connector_funcs, connector_type);
1333 drm_connector_helper_add(&radeon_connector->base, &radeon_dvi_connector_helper_funcs); 1336 drm_connector_helper_add(&radeon_connector->base, &radeon_dvi_connector_helper_funcs);
1334 if (i2c_bus->valid) { 1337 if (i2c_bus->valid) {
1335 radeon_connector->ddc_bus = radeon_i2c_create(dev, i2c_bus, "DVI"); 1338 radeon_connector->ddc_bus = radeon_i2c_lookup(rdev, i2c_bus);
1336 if (!radeon_connector->ddc_bus) 1339 if (!radeon_connector->ddc_bus)
1337 goto failed; 1340 goto failed;
1338 } 1341 }
@@ -1372,7 +1375,7 @@ radeon_add_legacy_connector(struct drm_device *dev,
1372 drm_connector_init(dev, &radeon_connector->base, &radeon_lvds_connector_funcs, connector_type); 1375 drm_connector_init(dev, &radeon_connector->base, &radeon_lvds_connector_funcs, connector_type);
1373 drm_connector_helper_add(&radeon_connector->base, &radeon_lvds_connector_helper_funcs); 1376 drm_connector_helper_add(&radeon_connector->base, &radeon_lvds_connector_helper_funcs);
1374 if (i2c_bus->valid) { 1377 if (i2c_bus->valid) {
1375 radeon_connector->ddc_bus = radeon_i2c_create(dev, i2c_bus, "LVDS"); 1378 radeon_connector->ddc_bus = radeon_i2c_lookup(rdev, i2c_bus);
1376 if (!radeon_connector->ddc_bus) 1379 if (!radeon_connector->ddc_bus)
1377 goto failed; 1380 goto failed;
1378 } 1381 }
@@ -1393,8 +1396,6 @@ radeon_add_legacy_connector(struct drm_device *dev,
1393 return; 1396 return;
1394 1397
1395failed: 1398failed:
1396 if (radeon_connector->ddc_bus)
1397 radeon_i2c_destroy(radeon_connector->ddc_bus);
1398 drm_connector_cleanup(connector); 1399 drm_connector_cleanup(connector);
1399 kfree(connector); 1400 kfree(connector);
1400} 1401}
diff --git a/drivers/gpu/drm/radeon/radeon_cs.c b/drivers/gpu/drm/radeon/radeon_cs.c
index ae0fb7356e6..fcc79b5d22d 100644
--- a/drivers/gpu/drm/radeon/radeon_cs.c
+++ b/drivers/gpu/drm/radeon/radeon_cs.c
@@ -72,7 +72,7 @@ int radeon_cs_parser_relocs(struct radeon_cs_parser *p)
72 if (p->relocs[i].gobj == NULL) { 72 if (p->relocs[i].gobj == NULL) {
73 DRM_ERROR("gem object lookup failed 0x%x\n", 73 DRM_ERROR("gem object lookup failed 0x%x\n",
74 r->handle); 74 r->handle);
75 return -EINVAL; 75 return -ENOENT;
76 } 76 }
77 p->relocs_ptr[i] = &p->relocs[i]; 77 p->relocs_ptr[i] = &p->relocs[i];
78 p->relocs[i].robj = p->relocs[i].gobj->driver_private; 78 p->relocs[i].robj = p->relocs[i].gobj->driver_private;
diff --git a/drivers/gpu/drm/radeon/radeon_cursor.c b/drivers/gpu/drm/radeon/radeon_cursor.c
index 4eb67c0e099..5731fc9b1ae 100644
--- a/drivers/gpu/drm/radeon/radeon_cursor.c
+++ b/drivers/gpu/drm/radeon/radeon_cursor.c
@@ -170,7 +170,7 @@ int radeon_crtc_cursor_set(struct drm_crtc *crtc,
170 obj = drm_gem_object_lookup(crtc->dev, file_priv, handle); 170 obj = drm_gem_object_lookup(crtc->dev, file_priv, handle);
171 if (!obj) { 171 if (!obj) {
172 DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle, radeon_crtc->crtc_id); 172 DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle, radeon_crtc->crtc_id);
173 return -EINVAL; 173 return -ENOENT;
174 } 174 }
175 175
176 ret = radeon_gem_object_pin(obj, RADEON_GEM_DOMAIN_VRAM, &gpu_addr); 176 ret = radeon_gem_object_pin(obj, RADEON_GEM_DOMAIN_VRAM, &gpu_addr);
diff --git a/drivers/gpu/drm/radeon/radeon_device.c b/drivers/gpu/drm/radeon/radeon_device.c
index a64811a9451..4f7a170d156 100644
--- a/drivers/gpu/drm/radeon/radeon_device.c
+++ b/drivers/gpu/drm/radeon/radeon_device.c
@@ -347,7 +347,8 @@ int radeon_dummy_page_init(struct radeon_device *rdev)
347 return -ENOMEM; 347 return -ENOMEM;
348 rdev->dummy_page.addr = pci_map_page(rdev->pdev, rdev->dummy_page.page, 348 rdev->dummy_page.addr = pci_map_page(rdev->pdev, rdev->dummy_page.page,
349 0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); 349 0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
350 if (!rdev->dummy_page.addr) { 350 if (pci_dma_mapping_error(rdev->pdev, rdev->dummy_page.addr)) {
351 dev_err(&rdev->pdev->dev, "Failed to DMA MAP the dummy page\n");
351 __free_page(rdev->dummy_page.page); 352 __free_page(rdev->dummy_page.page);
352 rdev->dummy_page.page = NULL; 353 rdev->dummy_page.page = NULL;
353 return -ENOMEM; 354 return -ENOMEM;
diff --git a/drivers/gpu/drm/radeon/radeon_display.c b/drivers/gpu/drm/radeon/radeon_display.c
index 74dac9635d7..5764f4d3b4f 100644
--- a/drivers/gpu/drm/radeon/radeon_display.c
+++ b/drivers/gpu/drm/radeon/radeon_display.c
@@ -161,17 +161,13 @@ void radeon_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
161} 161}
162 162
163static void radeon_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, 163static void radeon_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
164 u16 *blue, uint32_t size) 164 u16 *blue, uint32_t start, uint32_t size)
165{ 165{
166 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 166 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
167 int i; 167 int end = (start + size > 256) ? 256 : start + size, i;
168
169 if (size != 256) {
170 return;
171 }
172 168
173 /* userspace palettes are always correct as is */ 169 /* userspace palettes are always correct as is */
174 for (i = 0; i < 256; i++) { 170 for (i = start; i < end; i++) {
175 radeon_crtc->lut_r[i] = red[i] >> 6; 171 radeon_crtc->lut_r[i] = red[i] >> 6;
176 radeon_crtc->lut_g[i] = green[i] >> 6; 172 radeon_crtc->lut_g[i] = green[i] >> 6;
177 radeon_crtc->lut_b[i] = blue[i] >> 6; 173 radeon_crtc->lut_b[i] = blue[i] >> 6;
@@ -319,6 +315,10 @@ static void radeon_print_display_setup(struct drm_device *dev)
319 radeon_connector->ddc_bus->rec.en_data_reg, 315 radeon_connector->ddc_bus->rec.en_data_reg,
320 radeon_connector->ddc_bus->rec.y_clk_reg, 316 radeon_connector->ddc_bus->rec.y_clk_reg,
321 radeon_connector->ddc_bus->rec.y_data_reg); 317 radeon_connector->ddc_bus->rec.y_data_reg);
318 if (radeon_connector->router_bus)
319 DRM_INFO(" DDC Router 0x%x/0x%x\n",
320 radeon_connector->router.mux_control_pin,
321 radeon_connector->router.mux_state);
322 } else { 322 } else {
323 if (connector->connector_type == DRM_MODE_CONNECTOR_VGA || 323 if (connector->connector_type == DRM_MODE_CONNECTOR_VGA ||
324 connector->connector_type == DRM_MODE_CONNECTOR_DVII || 324 connector->connector_type == DRM_MODE_CONNECTOR_DVII ||
@@ -395,6 +395,10 @@ int radeon_ddc_get_modes(struct radeon_connector *radeon_connector)
395 struct radeon_device *rdev = dev->dev_private; 395 struct radeon_device *rdev = dev->dev_private;
396 int ret = 0; 396 int ret = 0;
397 397
398 /* on hw with routers, select right port */
399 if (radeon_connector->router.valid)
400 radeon_router_select_port(radeon_connector);
401
398 if ((radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_DisplayPort) || 402 if ((radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_DisplayPort) ||
399 (radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP)) { 403 (radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP)) {
400 struct radeon_connector_atom_dig *dig = radeon_connector->con_priv; 404 struct radeon_connector_atom_dig *dig = radeon_connector->con_priv;
@@ -425,6 +429,10 @@ static int radeon_ddc_dump(struct drm_connector *connector)
425 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 429 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
426 int ret = 0; 430 int ret = 0;
427 431
432 /* on hw with routers, select right port */
433 if (radeon_connector->router.valid)
434 radeon_router_select_port(radeon_connector);
435
428 if (!radeon_connector->ddc_bus) 436 if (!radeon_connector->ddc_bus)
429 return -1; 437 return -1;
430 edid = drm_get_edid(connector, &radeon_connector->ddc_bus->adapter); 438 edid = drm_get_edid(connector, &radeon_connector->ddc_bus->adapter);
@@ -876,13 +884,12 @@ radeon_user_framebuffer_create(struct drm_device *dev,
876 if (obj == NULL) { 884 if (obj == NULL) {
877 dev_err(&dev->pdev->dev, "No GEM object associated to handle 0x%08X, " 885 dev_err(&dev->pdev->dev, "No GEM object associated to handle 0x%08X, "
878 "can't create framebuffer\n", mode_cmd->handle); 886 "can't create framebuffer\n", mode_cmd->handle);
879 return NULL; 887 return ERR_PTR(-ENOENT);
880 } 888 }
881 889
882 radeon_fb = kzalloc(sizeof(*radeon_fb), GFP_KERNEL); 890 radeon_fb = kzalloc(sizeof(*radeon_fb), GFP_KERNEL);
883 if (radeon_fb == NULL) { 891 if (radeon_fb == NULL)
884 return NULL; 892 return ERR_PTR(-ENOMEM);
885 }
886 893
887 radeon_framebuffer_init(dev, radeon_fb, mode_cmd, obj); 894 radeon_framebuffer_init(dev, radeon_fb, mode_cmd, obj);
888 895
@@ -1040,6 +1047,9 @@ int radeon_modeset_init(struct radeon_device *rdev)
1040 return ret; 1047 return ret;
1041 } 1048 }
1042 1049
1050 /* init i2c buses */
1051 radeon_i2c_init(rdev);
1052
1043 /* check combios for a valid hardcoded EDID - Sun servers */ 1053 /* check combios for a valid hardcoded EDID - Sun servers */
1044 if (!rdev->is_atom_bios) { 1054 if (!rdev->is_atom_bios) {
1045 /* check for hardcoded EDID in BIOS */ 1055 /* check for hardcoded EDID in BIOS */
@@ -1080,6 +1090,8 @@ void radeon_modeset_fini(struct radeon_device *rdev)
1080 drm_mode_config_cleanup(rdev->ddev); 1090 drm_mode_config_cleanup(rdev->ddev);
1081 rdev->mode_info.mode_config_initialized = false; 1091 rdev->mode_info.mode_config_initialized = false;
1082 } 1092 }
1093 /* free i2c buses */
1094 radeon_i2c_fini(rdev);
1083} 1095}
1084 1096
1085bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc, 1097bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
diff --git a/drivers/gpu/drm/radeon/radeon_gem.c b/drivers/gpu/drm/radeon/radeon_gem.c
index a72a3ee5d69..c578f265b24 100644
--- a/drivers/gpu/drm/radeon/radeon_gem.c
+++ b/drivers/gpu/drm/radeon/radeon_gem.c
@@ -226,7 +226,7 @@ int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
226 /* just do a BO wait for now */ 226 /* just do a BO wait for now */
227 gobj = drm_gem_object_lookup(dev, filp, args->handle); 227 gobj = drm_gem_object_lookup(dev, filp, args->handle);
228 if (gobj == NULL) { 228 if (gobj == NULL) {
229 return -EINVAL; 229 return -ENOENT;
230 } 230 }
231 robj = gobj->driver_private; 231 robj = gobj->driver_private;
232 232
@@ -245,7 +245,7 @@ int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
245 245
246 gobj = drm_gem_object_lookup(dev, filp, args->handle); 246 gobj = drm_gem_object_lookup(dev, filp, args->handle);
247 if (gobj == NULL) { 247 if (gobj == NULL) {
248 return -EINVAL; 248 return -ENOENT;
249 } 249 }
250 robj = gobj->driver_private; 250 robj = gobj->driver_private;
251 args->addr_ptr = radeon_bo_mmap_offset(robj); 251 args->addr_ptr = radeon_bo_mmap_offset(robj);
@@ -264,7 +264,7 @@ int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
264 264
265 gobj = drm_gem_object_lookup(dev, filp, args->handle); 265 gobj = drm_gem_object_lookup(dev, filp, args->handle);
266 if (gobj == NULL) { 266 if (gobj == NULL) {
267 return -EINVAL; 267 return -ENOENT;
268 } 268 }
269 robj = gobj->driver_private; 269 robj = gobj->driver_private;
270 r = radeon_bo_wait(robj, &cur_placement, true); 270 r = radeon_bo_wait(robj, &cur_placement, true);
@@ -294,7 +294,7 @@ int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
294 294
295 gobj = drm_gem_object_lookup(dev, filp, args->handle); 295 gobj = drm_gem_object_lookup(dev, filp, args->handle);
296 if (gobj == NULL) { 296 if (gobj == NULL) {
297 return -EINVAL; 297 return -ENOENT;
298 } 298 }
299 robj = gobj->driver_private; 299 robj = gobj->driver_private;
300 r = radeon_bo_wait(robj, NULL, false); 300 r = radeon_bo_wait(robj, NULL, false);
@@ -316,7 +316,7 @@ int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
316 DRM_DEBUG("%d \n", args->handle); 316 DRM_DEBUG("%d \n", args->handle);
317 gobj = drm_gem_object_lookup(dev, filp, args->handle); 317 gobj = drm_gem_object_lookup(dev, filp, args->handle);
318 if (gobj == NULL) 318 if (gobj == NULL)
319 return -EINVAL; 319 return -ENOENT;
320 robj = gobj->driver_private; 320 robj = gobj->driver_private;
321 r = radeon_bo_set_tiling_flags(robj, args->tiling_flags, args->pitch); 321 r = radeon_bo_set_tiling_flags(robj, args->tiling_flags, args->pitch);
322 drm_gem_object_unreference_unlocked(gobj); 322 drm_gem_object_unreference_unlocked(gobj);
@@ -334,7 +334,7 @@ int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
334 DRM_DEBUG("\n"); 334 DRM_DEBUG("\n");
335 gobj = drm_gem_object_lookup(dev, filp, args->handle); 335 gobj = drm_gem_object_lookup(dev, filp, args->handle);
336 if (gobj == NULL) 336 if (gobj == NULL)
337 return -EINVAL; 337 return -ENOENT;
338 rbo = gobj->driver_private; 338 rbo = gobj->driver_private;
339 r = radeon_bo_reserve(rbo, false); 339 r = radeon_bo_reserve(rbo, false);
340 if (unlikely(r != 0)) 340 if (unlikely(r != 0))
diff --git a/drivers/gpu/drm/radeon/radeon_i2c.c b/drivers/gpu/drm/radeon/radeon_i2c.c
index 5def6f5dff3..bfd2ce5f537 100644
--- a/drivers/gpu/drm/radeon/radeon_i2c.c
+++ b/drivers/gpu/drm/radeon/radeon_i2c.c
@@ -52,6 +52,10 @@ bool radeon_ddc_probe(struct radeon_connector *radeon_connector)
52 } 52 }
53 }; 53 };
54 54
55 /* on hw with routers, select right port */
56 if (radeon_connector->router.valid)
57 radeon_router_select_port(radeon_connector);
58
55 ret = i2c_transfer(&radeon_connector->ddc_bus->adapter, msgs, 2); 59 ret = i2c_transfer(&radeon_connector->ddc_bus->adapter, msgs, 2);
56 if (ret == 2) 60 if (ret == 2)
57 return true; 61 return true;
@@ -960,6 +964,59 @@ void radeon_i2c_destroy(struct radeon_i2c_chan *i2c)
960 kfree(i2c); 964 kfree(i2c);
961} 965}
962 966
967/* Add the default buses */
968void radeon_i2c_init(struct radeon_device *rdev)
969{
970 if (rdev->is_atom_bios)
971 radeon_atombios_i2c_init(rdev);
972 else
973 radeon_combios_i2c_init(rdev);
974}
975
976/* remove all the buses */
977void radeon_i2c_fini(struct radeon_device *rdev)
978{
979 int i;
980
981 for (i = 0; i < RADEON_MAX_I2C_BUS; i++) {
982 if (rdev->i2c_bus[i]) {
983 radeon_i2c_destroy(rdev->i2c_bus[i]);
984 rdev->i2c_bus[i] = NULL;
985 }
986 }
987}
988
989/* Add additional buses */
990void radeon_i2c_add(struct radeon_device *rdev,
991 struct radeon_i2c_bus_rec *rec,
992 const char *name)
993{
994 struct drm_device *dev = rdev->ddev;
995 int i;
996
997 for (i = 0; i < RADEON_MAX_I2C_BUS; i++) {
998 if (!rdev->i2c_bus[i]) {
999 rdev->i2c_bus[i] = radeon_i2c_create(dev, rec, name);
1000 return;
1001 }
1002 }
1003}
1004
1005/* looks up bus based on id */
1006struct radeon_i2c_chan *radeon_i2c_lookup(struct radeon_device *rdev,
1007 struct radeon_i2c_bus_rec *i2c_bus)
1008{
1009 int i;
1010
1011 for (i = 0; i < RADEON_MAX_I2C_BUS; i++) {
1012 if (rdev->i2c_bus[i] &&
1013 (rdev->i2c_bus[i]->rec.i2c_id == i2c_bus->i2c_id)) {
1014 return rdev->i2c_bus[i];
1015 }
1016 }
1017 return NULL;
1018}
1019
963struct drm_encoder *radeon_best_encoder(struct drm_connector *connector) 1020struct drm_encoder *radeon_best_encoder(struct drm_connector *connector)
964{ 1021{
965 return NULL; 1022 return NULL;
@@ -1020,3 +1077,28 @@ void radeon_i2c_put_byte(struct radeon_i2c_chan *i2c_bus,
1020 addr, val); 1077 addr, val);
1021} 1078}
1022 1079
1080/* router switching */
1081void radeon_router_select_port(struct radeon_connector *radeon_connector)
1082{
1083 u8 val;
1084
1085 if (!radeon_connector->router.valid)
1086 return;
1087
1088 radeon_i2c_get_byte(radeon_connector->router_bus,
1089 radeon_connector->router.i2c_addr,
1090 0x3, &val);
1091 val &= radeon_connector->router.mux_control_pin;
1092 radeon_i2c_put_byte(radeon_connector->router_bus,
1093 radeon_connector->router.i2c_addr,
1094 0x3, val);
1095 radeon_i2c_get_byte(radeon_connector->router_bus,
1096 radeon_connector->router.i2c_addr,
1097 0x1, &val);
1098 val &= radeon_connector->router.mux_control_pin;
1099 val |= radeon_connector->router.mux_state;
1100 radeon_i2c_put_byte(radeon_connector->router_bus,
1101 radeon_connector->router.i2c_addr,
1102 0x1, val);
1103}
1104
diff --git a/drivers/gpu/drm/radeon/radeon_kms.c b/drivers/gpu/drm/radeon/radeon_kms.c
index ddcd3b13f15..b1c8ace5f08 100644
--- a/drivers/gpu/drm/radeon/radeon_kms.c
+++ b/drivers/gpu/drm/radeon/radeon_kms.c
@@ -112,7 +112,9 @@ int radeon_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
112 112
113 info = data; 113 info = data;
114 value_ptr = (uint32_t *)((unsigned long)info->value); 114 value_ptr = (uint32_t *)((unsigned long)info->value);
115 value = *value_ptr; 115 if (DRM_COPY_FROM_USER(&value, value_ptr, sizeof(value)))
116 return -EFAULT;
117
116 switch (info->request) { 118 switch (info->request) {
117 case RADEON_INFO_DEVICE_ID: 119 case RADEON_INFO_DEVICE_ID:
118 value = dev->pci_device; 120 value = dev->pci_device;
@@ -160,13 +162,27 @@ int radeon_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
160 return -EINVAL; 162 return -EINVAL;
161 } 163 }
162 case RADEON_INFO_WANT_HYPERZ: 164 case RADEON_INFO_WANT_HYPERZ:
165 /* The "value" here is both an input and output parameter.
166 * If the input value is 1, filp requests hyper-z access.
167 * If the input value is 0, filp revokes its hyper-z access.
168 *
169 * When returning, the value is 1 if filp owns hyper-z access,
170 * 0 otherwise. */
171 if (value >= 2) {
172 DRM_DEBUG_KMS("WANT_HYPERZ: invalid value %d\n", value);
173 return -EINVAL;
174 }
163 mutex_lock(&dev->struct_mutex); 175 mutex_lock(&dev->struct_mutex);
164 if (rdev->hyperz_filp) 176 if (value == 1) {
165 value = 0; 177 /* wants hyper-z */
166 else { 178 if (!rdev->hyperz_filp)
167 rdev->hyperz_filp = filp; 179 rdev->hyperz_filp = filp;
168 value = 1; 180 } else if (value == 0) {
181 /* revokes hyper-z */
182 if (rdev->hyperz_filp == filp)
183 rdev->hyperz_filp = NULL;
169 } 184 }
185 value = rdev->hyperz_filp == filp ? 1 : 0;
170 mutex_unlock(&dev->struct_mutex); 186 mutex_unlock(&dev->struct_mutex);
171 break; 187 break;
172 default: 188 default:
diff --git a/drivers/gpu/drm/radeon/radeon_mode.h b/drivers/gpu/drm/radeon/radeon_mode.h
index 71aea4037e9..5bbc086b926 100644
--- a/drivers/gpu/drm/radeon/radeon_mode.h
+++ b/drivers/gpu/drm/radeon/radeon_mode.h
@@ -82,6 +82,8 @@ enum radeon_hpd_id {
82 RADEON_HPD_NONE = 0xff, 82 RADEON_HPD_NONE = 0xff,
83}; 83};
84 84
85#define RADEON_MAX_I2C_BUS 16
86
85/* radeon gpio-based i2c 87/* radeon gpio-based i2c
86 * 1. "mask" reg and bits 88 * 1. "mask" reg and bits
87 * grabs the gpio pins for software use 89 * grabs the gpio pins for software use
@@ -398,6 +400,16 @@ struct radeon_hpd {
398 struct radeon_gpio_rec gpio; 400 struct radeon_gpio_rec gpio;
399}; 401};
400 402
403struct radeon_router {
404 bool valid;
405 u32 router_id;
406 struct radeon_i2c_bus_rec i2c_info;
407 u8 i2c_addr;
408 u8 mux_type;
409 u8 mux_control_pin;
410 u8 mux_state;
411};
412
401struct radeon_connector { 413struct radeon_connector {
402 struct drm_connector base; 414 struct drm_connector base;
403 uint32_t connector_id; 415 uint32_t connector_id;
@@ -413,6 +425,8 @@ struct radeon_connector {
413 bool dac_load_detect; 425 bool dac_load_detect;
414 uint16_t connector_object_id; 426 uint16_t connector_object_id;
415 struct radeon_hpd hpd; 427 struct radeon_hpd hpd;
428 struct radeon_router router;
429 struct radeon_i2c_chan *router_bus;
416}; 430};
417 431
418struct radeon_framebuffer { 432struct radeon_framebuffer {
@@ -445,6 +459,15 @@ extern void atombios_dig_transmitter_setup(struct drm_encoder *encoder,
445extern int radeon_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode, 459extern int radeon_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
446 uint8_t write_byte, uint8_t *read_byte); 460 uint8_t write_byte, uint8_t *read_byte);
447 461
462extern void radeon_i2c_init(struct radeon_device *rdev);
463extern void radeon_i2c_fini(struct radeon_device *rdev);
464extern void radeon_combios_i2c_init(struct radeon_device *rdev);
465extern void radeon_atombios_i2c_init(struct radeon_device *rdev);
466extern void radeon_i2c_add(struct radeon_device *rdev,
467 struct radeon_i2c_bus_rec *rec,
468 const char *name);
469extern struct radeon_i2c_chan *radeon_i2c_lookup(struct radeon_device *rdev,
470 struct radeon_i2c_bus_rec *i2c_bus);
448extern struct radeon_i2c_chan *radeon_i2c_create_dp(struct drm_device *dev, 471extern struct radeon_i2c_chan *radeon_i2c_create_dp(struct drm_device *dev,
449 struct radeon_i2c_bus_rec *rec, 472 struct radeon_i2c_bus_rec *rec,
450 const char *name); 473 const char *name);
@@ -460,6 +483,7 @@ extern void radeon_i2c_put_byte(struct radeon_i2c_chan *i2c,
460 u8 slave_addr, 483 u8 slave_addr,
461 u8 addr, 484 u8 addr,
462 u8 val); 485 u8 val);
486extern void radeon_router_select_port(struct radeon_connector *radeon_connector);
463extern bool radeon_ddc_probe(struct radeon_connector *radeon_connector); 487extern bool radeon_ddc_probe(struct radeon_connector *radeon_connector);
464extern int radeon_ddc_get_modes(struct radeon_connector *radeon_connector); 488extern int radeon_ddc_get_modes(struct radeon_connector *radeon_connector);
465 489
diff --git a/drivers/gpu/drm/radeon/radeon_pm.c b/drivers/gpu/drm/radeon/radeon_pm.c
index 95f8b3a3c43..58038f5cab3 100644
--- a/drivers/gpu/drm/radeon/radeon_pm.c
+++ b/drivers/gpu/drm/radeon/radeon_pm.c
@@ -472,9 +472,9 @@ static const struct attribute_group hwmon_attrgroup = {
472 .attrs = hwmon_attributes, 472 .attrs = hwmon_attributes,
473}; 473};
474 474
475static void radeon_hwmon_init(struct radeon_device *rdev) 475static int radeon_hwmon_init(struct radeon_device *rdev)
476{ 476{
477 int err; 477 int err = 0;
478 478
479 rdev->pm.int_hwmon_dev = NULL; 479 rdev->pm.int_hwmon_dev = NULL;
480 480
@@ -483,15 +483,26 @@ static void radeon_hwmon_init(struct radeon_device *rdev)
483 case THERMAL_TYPE_RV770: 483 case THERMAL_TYPE_RV770:
484 case THERMAL_TYPE_EVERGREEN: 484 case THERMAL_TYPE_EVERGREEN:
485 rdev->pm.int_hwmon_dev = hwmon_device_register(rdev->dev); 485 rdev->pm.int_hwmon_dev = hwmon_device_register(rdev->dev);
486 if (IS_ERR(rdev->pm.int_hwmon_dev)) {
487 err = PTR_ERR(rdev->pm.int_hwmon_dev);
488 dev_err(rdev->dev,
489 "Unable to register hwmon device: %d\n", err);
490 break;
491 }
486 dev_set_drvdata(rdev->pm.int_hwmon_dev, rdev->ddev); 492 dev_set_drvdata(rdev->pm.int_hwmon_dev, rdev->ddev);
487 err = sysfs_create_group(&rdev->pm.int_hwmon_dev->kobj, 493 err = sysfs_create_group(&rdev->pm.int_hwmon_dev->kobj,
488 &hwmon_attrgroup); 494 &hwmon_attrgroup);
489 if (err) 495 if (err) {
490 DRM_ERROR("Unable to create hwmon sysfs file: %d\n", err); 496 dev_err(rdev->dev,
497 "Unable to create hwmon sysfs file: %d\n", err);
498 hwmon_device_unregister(rdev->dev);
499 }
491 break; 500 break;
492 default: 501 default:
493 break; 502 break;
494 } 503 }
504
505 return err;
495} 506}
496 507
497static void radeon_hwmon_fini(struct radeon_device *rdev) 508static void radeon_hwmon_fini(struct radeon_device *rdev)
@@ -540,6 +551,7 @@ void radeon_pm_resume(struct radeon_device *rdev)
540int radeon_pm_init(struct radeon_device *rdev) 551int radeon_pm_init(struct radeon_device *rdev)
541{ 552{
542 int ret; 553 int ret;
554
543 /* default to profile method */ 555 /* default to profile method */
544 rdev->pm.pm_method = PM_METHOD_PROFILE; 556 rdev->pm.pm_method = PM_METHOD_PROFILE;
545 rdev->pm.profile = PM_PROFILE_DEFAULT; 557 rdev->pm.profile = PM_PROFILE_DEFAULT;
@@ -561,7 +573,9 @@ int radeon_pm_init(struct radeon_device *rdev)
561 } 573 }
562 574
563 /* set up the internal thermal sensor if applicable */ 575 /* set up the internal thermal sensor if applicable */
564 radeon_hwmon_init(rdev); 576 ret = radeon_hwmon_init(rdev);
577 if (ret)
578 return ret;
565 if (rdev->pm.num_power_states > 1) { 579 if (rdev->pm.num_power_states > 1) {
566 /* where's the best place to put these? */ 580 /* where's the best place to put these? */
567 ret = device_create_file(rdev->dev, &dev_attr_power_profile); 581 ret = device_create_file(rdev->dev, &dev_attr_power_profile);
diff --git a/drivers/gpu/drm/radeon/reg_srcs/rv515 b/drivers/gpu/drm/radeon/reg_srcs/rv515
index 8293855f5f0..b3f9f1d9200 100644
--- a/drivers/gpu/drm/radeon/reg_srcs/rv515
+++ b/drivers/gpu/drm/radeon/reg_srcs/rv515
@@ -316,6 +316,7 @@ rv515 0x6d40
3160x4BD0 FG_FOG_COLOR_B 3160x4BD0 FG_FOG_COLOR_B
3170x4BD4 FG_ALPHA_FUNC 3170x4BD4 FG_ALPHA_FUNC
3180x4BD8 FG_DEPTH_SRC 3180x4BD8 FG_DEPTH_SRC
3190x4BE0 FG_ALPHA_VALUE
3190x4C00 US_ALU_CONST_R_0 3200x4C00 US_ALU_CONST_R_0
3200x4C04 US_ALU_CONST_G_0 3210x4C04 US_ALU_CONST_G_0
3210x4C08 US_ALU_CONST_B_0 3220x4C08 US_ALU_CONST_B_0
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c b/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c
index 437ac786277..64d7f47df86 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c
@@ -737,7 +737,7 @@ static struct drm_framebuffer *vmw_kms_fb_create(struct drm_device *dev,
737 737
738 if (ret) { 738 if (ret) {
739 DRM_ERROR("failed to create vmw_framebuffer: %i\n", ret); 739 DRM_ERROR("failed to create vmw_framebuffer: %i\n", ret);
740 return NULL; 740 return ERR_PTR(ret);
741 } 741 }
742 return &vfb->base; 742 return &vfb->base;
743 743
@@ -747,7 +747,7 @@ try_dmabuf:
747 ret = vmw_user_dmabuf_lookup(tfile, mode_cmd->handle, &bo); 747 ret = vmw_user_dmabuf_lookup(tfile, mode_cmd->handle, &bo);
748 if (ret) { 748 if (ret) {
749 DRM_ERROR("failed to find buffer: %i\n", ret); 749 DRM_ERROR("failed to find buffer: %i\n", ret);
750 return NULL; 750 return ERR_PTR(-ENOENT);
751 } 751 }
752 752
753 ret = vmw_kms_new_framebuffer_dmabuf(dev_priv, bo, &vfb, 753 ret = vmw_kms_new_framebuffer_dmabuf(dev_priv, bo, &vfb,
@@ -758,7 +758,7 @@ try_dmabuf:
758 758
759 if (ret) { 759 if (ret) {
760 DRM_ERROR("failed to create vmw_framebuffer: %i\n", ret); 760 DRM_ERROR("failed to create vmw_framebuffer: %i\n", ret);
761 return NULL; 761 return ERR_PTR(ret);
762 } 762 }
763 763
764 return &vfb->base; 764 return &vfb->base;
@@ -768,7 +768,7 @@ err_not_scanout:
768 /* vmw_user_surface_lookup takes one ref */ 768 /* vmw_user_surface_lookup takes one ref */
769 vmw_surface_unreference(&surface); 769 vmw_surface_unreference(&surface);
770 770
771 return NULL; 771 return ERR_PTR(-EINVAL);
772} 772}
773 773
774static struct drm_mode_config_funcs vmw_kms_funcs = { 774static struct drm_mode_config_funcs vmw_kms_funcs = {
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c b/drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c
index cfaf690a5b2..2ff5cf78235 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c
@@ -79,7 +79,7 @@ static void vmw_ldu_crtc_restore(struct drm_crtc *crtc)
79 79
80static void vmw_ldu_crtc_gamma_set(struct drm_crtc *crtc, 80static void vmw_ldu_crtc_gamma_set(struct drm_crtc *crtc,
81 u16 *r, u16 *g, u16 *b, 81 u16 *r, u16 *g, u16 *b,
82 uint32_t size) 82 uint32_t start, uint32_t size)
83{ 83{
84} 84}
85 85
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-24 04:23:42 -0400