diff options
Diffstat (limited to 'drivers/gpu')
-rw-r--r-- | drivers/gpu/drm/radeon/evergreen.c | 4 | ||||
-rw-r--r-- | drivers/gpu/drm/radeon/ni.c | 12 | ||||
-rw-r--r-- | drivers/gpu/drm/radeon/r100.c | 6 | ||||
-rw-r--r-- | drivers/gpu/drm/radeon/r600.c | 4 |
4 files changed, 12 insertions, 14 deletions
diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c index dc0a5b56c81..f10d1c1c255 100644 --- a/drivers/gpu/drm/radeon/evergreen.c +++ b/drivers/gpu/drm/radeon/evergreen.c | |||
@@ -1404,7 +1404,8 @@ int evergreen_cp_resume(struct radeon_device *rdev) | |||
1404 | /* Initialize the ring buffer's read and write pointers */ | 1404 | /* Initialize the ring buffer's read and write pointers */ |
1405 | WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA); | 1405 | WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA); |
1406 | WREG32(CP_RB_RPTR_WR, 0); | 1406 | WREG32(CP_RB_RPTR_WR, 0); |
1407 | WREG32(CP_RB_WPTR, 0); | 1407 | rdev->cp.wptr = 0; |
1408 | WREG32(CP_RB_WPTR, rdev->cp.wptr); | ||
1408 | 1409 | ||
1409 | /* set the wb address wether it's enabled or not */ | 1410 | /* set the wb address wether it's enabled or not */ |
1410 | WREG32(CP_RB_RPTR_ADDR, | 1411 | WREG32(CP_RB_RPTR_ADDR, |
@@ -1426,7 +1427,6 @@ int evergreen_cp_resume(struct radeon_device *rdev) | |||
1426 | WREG32(CP_DEBUG, (1 << 27) | (1 << 28)); | 1427 | WREG32(CP_DEBUG, (1 << 27) | (1 << 28)); |
1427 | 1428 | ||
1428 | rdev->cp.rptr = RREG32(CP_RB_RPTR); | 1429 | rdev->cp.rptr = RREG32(CP_RB_RPTR); |
1429 | rdev->cp.wptr = RREG32(CP_RB_WPTR); | ||
1430 | 1430 | ||
1431 | evergreen_cp_start(rdev); | 1431 | evergreen_cp_start(rdev); |
1432 | rdev->cp.ready = true; | 1432 | rdev->cp.ready = true; |
diff --git a/drivers/gpu/drm/radeon/ni.c b/drivers/gpu/drm/radeon/ni.c index cbf57d75d92..99fbd793c08 100644 --- a/drivers/gpu/drm/radeon/ni.c +++ b/drivers/gpu/drm/radeon/ni.c | |||
@@ -1187,7 +1187,8 @@ int cayman_cp_resume(struct radeon_device *rdev) | |||
1187 | 1187 | ||
1188 | /* Initialize the ring buffer's read and write pointers */ | 1188 | /* Initialize the ring buffer's read and write pointers */ |
1189 | WREG32(CP_RB0_CNTL, tmp | RB_RPTR_WR_ENA); | 1189 | WREG32(CP_RB0_CNTL, tmp | RB_RPTR_WR_ENA); |
1190 | WREG32(CP_RB0_WPTR, 0); | 1190 | rdev->cp.wptr = 0; |
1191 | WREG32(CP_RB0_WPTR, rdev->cp.wptr); | ||
1191 | 1192 | ||
1192 | /* set the wb address wether it's enabled or not */ | 1193 | /* set the wb address wether it's enabled or not */ |
1193 | WREG32(CP_RB0_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC); | 1194 | WREG32(CP_RB0_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC); |
@@ -1207,7 +1208,6 @@ int cayman_cp_resume(struct radeon_device *rdev) | |||
1207 | WREG32(CP_RB0_BASE, rdev->cp.gpu_addr >> 8); | 1208 | WREG32(CP_RB0_BASE, rdev->cp.gpu_addr >> 8); |
1208 | 1209 | ||
1209 | rdev->cp.rptr = RREG32(CP_RB0_RPTR); | 1210 | rdev->cp.rptr = RREG32(CP_RB0_RPTR); |
1210 | rdev->cp.wptr = RREG32(CP_RB0_WPTR); | ||
1211 | 1211 | ||
1212 | /* ring1 - compute only */ | 1212 | /* ring1 - compute only */ |
1213 | /* Set ring buffer size */ | 1213 | /* Set ring buffer size */ |
@@ -1220,7 +1220,8 @@ int cayman_cp_resume(struct radeon_device *rdev) | |||
1220 | 1220 | ||
1221 | /* Initialize the ring buffer's read and write pointers */ | 1221 | /* Initialize the ring buffer's read and write pointers */ |
1222 | WREG32(CP_RB1_CNTL, tmp | RB_RPTR_WR_ENA); | 1222 | WREG32(CP_RB1_CNTL, tmp | RB_RPTR_WR_ENA); |
1223 | WREG32(CP_RB1_WPTR, 0); | 1223 | rdev->cp1.wptr = 0; |
1224 | WREG32(CP_RB1_WPTR, rdev->cp1.wptr); | ||
1224 | 1225 | ||
1225 | /* set the wb address wether it's enabled or not */ | 1226 | /* set the wb address wether it's enabled or not */ |
1226 | WREG32(CP_RB1_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP1_RPTR_OFFSET) & 0xFFFFFFFC); | 1227 | WREG32(CP_RB1_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP1_RPTR_OFFSET) & 0xFFFFFFFC); |
@@ -1232,7 +1233,6 @@ int cayman_cp_resume(struct radeon_device *rdev) | |||
1232 | WREG32(CP_RB1_BASE, rdev->cp1.gpu_addr >> 8); | 1233 | WREG32(CP_RB1_BASE, rdev->cp1.gpu_addr >> 8); |
1233 | 1234 | ||
1234 | rdev->cp1.rptr = RREG32(CP_RB1_RPTR); | 1235 | rdev->cp1.rptr = RREG32(CP_RB1_RPTR); |
1235 | rdev->cp1.wptr = RREG32(CP_RB1_WPTR); | ||
1236 | 1236 | ||
1237 | /* ring2 - compute only */ | 1237 | /* ring2 - compute only */ |
1238 | /* Set ring buffer size */ | 1238 | /* Set ring buffer size */ |
@@ -1245,7 +1245,8 @@ int cayman_cp_resume(struct radeon_device *rdev) | |||
1245 | 1245 | ||
1246 | /* Initialize the ring buffer's read and write pointers */ | 1246 | /* Initialize the ring buffer's read and write pointers */ |
1247 | WREG32(CP_RB2_CNTL, tmp | RB_RPTR_WR_ENA); | 1247 | WREG32(CP_RB2_CNTL, tmp | RB_RPTR_WR_ENA); |
1248 | WREG32(CP_RB2_WPTR, 0); | 1248 | rdev->cp2.wptr = 0; |
1249 | WREG32(CP_RB2_WPTR, rdev->cp2.wptr); | ||
1249 | 1250 | ||
1250 | /* set the wb address wether it's enabled or not */ | 1251 | /* set the wb address wether it's enabled or not */ |
1251 | WREG32(CP_RB2_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP2_RPTR_OFFSET) & 0xFFFFFFFC); | 1252 | WREG32(CP_RB2_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP2_RPTR_OFFSET) & 0xFFFFFFFC); |
@@ -1257,7 +1258,6 @@ int cayman_cp_resume(struct radeon_device *rdev) | |||
1257 | WREG32(CP_RB2_BASE, rdev->cp2.gpu_addr >> 8); | 1258 | WREG32(CP_RB2_BASE, rdev->cp2.gpu_addr >> 8); |
1258 | 1259 | ||
1259 | rdev->cp2.rptr = RREG32(CP_RB2_RPTR); | 1260 | rdev->cp2.rptr = RREG32(CP_RB2_RPTR); |
1260 | rdev->cp2.wptr = RREG32(CP_RB2_WPTR); | ||
1261 | 1261 | ||
1262 | /* start the rings */ | 1262 | /* start the rings */ |
1263 | cayman_cp_start(rdev); | 1263 | cayman_cp_start(rdev); |
diff --git a/drivers/gpu/drm/radeon/r100.c b/drivers/gpu/drm/radeon/r100.c index f2204cb1ccd..11e44a3479e 100644 --- a/drivers/gpu/drm/radeon/r100.c +++ b/drivers/gpu/drm/radeon/r100.c | |||
@@ -990,7 +990,8 @@ int r100_cp_init(struct radeon_device *rdev, unsigned ring_size) | |||
990 | /* Force read & write ptr to 0 */ | 990 | /* Force read & write ptr to 0 */ |
991 | WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA | RADEON_RB_NO_UPDATE); | 991 | WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA | RADEON_RB_NO_UPDATE); |
992 | WREG32(RADEON_CP_RB_RPTR_WR, 0); | 992 | WREG32(RADEON_CP_RB_RPTR_WR, 0); |
993 | WREG32(RADEON_CP_RB_WPTR, 0); | 993 | rdev->cp.wptr = 0; |
994 | WREG32(RADEON_CP_RB_WPTR, rdev->cp.wptr); | ||
994 | 995 | ||
995 | /* set the wb address whether it's enabled or not */ | 996 | /* set the wb address whether it's enabled or not */ |
996 | WREG32(R_00070C_CP_RB_RPTR_ADDR, | 997 | WREG32(R_00070C_CP_RB_RPTR_ADDR, |
@@ -1007,9 +1008,6 @@ int r100_cp_init(struct radeon_device *rdev, unsigned ring_size) | |||
1007 | WREG32(RADEON_CP_RB_CNTL, tmp); | 1008 | WREG32(RADEON_CP_RB_CNTL, tmp); |
1008 | udelay(10); | 1009 | udelay(10); |
1009 | rdev->cp.rptr = RREG32(RADEON_CP_RB_RPTR); | 1010 | rdev->cp.rptr = RREG32(RADEON_CP_RB_RPTR); |
1010 | rdev->cp.wptr = RREG32(RADEON_CP_RB_WPTR); | ||
1011 | /* protect against crazy HW on resume */ | ||
1012 | rdev->cp.wptr &= rdev->cp.ptr_mask; | ||
1013 | /* Set cp mode to bus mastering & enable cp*/ | 1011 | /* Set cp mode to bus mastering & enable cp*/ |
1014 | WREG32(RADEON_CP_CSQ_MODE, | 1012 | WREG32(RADEON_CP_CSQ_MODE, |
1015 | REG_SET(RADEON_INDIRECT2_START, indirect2_start) | | 1013 | REG_SET(RADEON_INDIRECT2_START, indirect2_start) | |
diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c index aa5571b73aa..c68427612e3 100644 --- a/drivers/gpu/drm/radeon/r600.c +++ b/drivers/gpu/drm/radeon/r600.c | |||
@@ -2209,7 +2209,8 @@ int r600_cp_resume(struct radeon_device *rdev) | |||
2209 | /* Initialize the ring buffer's read and write pointers */ | 2209 | /* Initialize the ring buffer's read and write pointers */ |
2210 | WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA); | 2210 | WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA); |
2211 | WREG32(CP_RB_RPTR_WR, 0); | 2211 | WREG32(CP_RB_RPTR_WR, 0); |
2212 | WREG32(CP_RB_WPTR, 0); | 2212 | rdev->cp.wptr = 0; |
2213 | WREG32(CP_RB_WPTR, rdev->cp.wptr); | ||
2213 | 2214 | ||
2214 | /* set the wb address whether it's enabled or not */ | 2215 | /* set the wb address whether it's enabled or not */ |
2215 | WREG32(CP_RB_RPTR_ADDR, | 2216 | WREG32(CP_RB_RPTR_ADDR, |
@@ -2231,7 +2232,6 @@ int r600_cp_resume(struct radeon_device *rdev) | |||
2231 | WREG32(CP_DEBUG, (1 << 27) | (1 << 28)); | 2232 | WREG32(CP_DEBUG, (1 << 27) | (1 << 28)); |
2232 | 2233 | ||
2233 | rdev->cp.rptr = RREG32(CP_RB_RPTR); | 2234 | rdev->cp.rptr = RREG32(CP_RB_RPTR); |
2234 | rdev->cp.wptr = RREG32(CP_RB_WPTR); | ||
2235 | 2235 | ||
2236 | r600_cp_start(rdev); | 2236 | r600_cp_start(rdev); |
2237 | rdev->cp.ready = true; | 2237 | rdev->cp.ready = true; |