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-rw-r--r--drivers/gpu/drm/exynos/exynos_drm_drv.c4
-rw-r--r--drivers/gpu/drm/exynos/exynos_drm_encoder.c7
-rw-r--r--drivers/gpu/drm/exynos/exynos_drm_fb.c19
-rw-r--r--drivers/gpu/drm/exynos/exynos_drm_fb.h4
-rw-r--r--drivers/gpu/drm/exynos/exynos_drm_gem.c9
-rw-r--r--drivers/gpu/drm/exynos/exynos_mixer.c12
-rw-r--r--drivers/gpu/drm/i915/i915_drv.c13
-rw-r--r--drivers/gpu/drm/i915/i915_drv.h3
-rw-r--r--drivers/gpu/drm/i915/i915_irq.c38
-rw-r--r--drivers/gpu/drm/i915/i915_reg.h43
-rw-r--r--drivers/gpu/drm/i915/intel_display.c19
-rw-r--r--drivers/gpu/drm/i915/intel_ringbuffer.c21
-rw-r--r--drivers/gpu/drm/radeon/evergreen_cs.c49
-rw-r--r--drivers/gpu/drm/radeon/ni.c21
-rw-r--r--drivers/gpu/drm/radeon/r600.c15
-rw-r--r--drivers/gpu/drm/radeon/r600_audio.c5
-rw-r--r--drivers/gpu/drm/radeon/r600_hdmi.c1
-rw-r--r--drivers/gpu/drm/radeon/radeon.h5
-rw-r--r--drivers/gpu/drm/radeon/radeon_drv.c3
-rw-r--r--drivers/gpu/drm/radeon/radeon_gart.c19
-rw-r--r--drivers/gpu/drm/radeon/radeon_kms.c2
-rw-r--r--drivers/gpu/drm/radeon/rs600.c12
-rw-r--r--drivers/gpu/drm/radeon/rs690.c12
-rw-r--r--drivers/gpu/drm/radeon/rv770.c18
-rw-r--r--drivers/gpu/drm/radeon/si.c477
-rw-r--r--drivers/gpu/drm/radeon/sid.h19
-rw-r--r--drivers/gpu/drm/ttm/ttm_bo.c13
-rw-r--r--drivers/gpu/vga/vga_switcheroo.c27
28 files changed, 462 insertions, 428 deletions
diff --git a/drivers/gpu/drm/exynos/exynos_drm_drv.c b/drivers/gpu/drm/exynos/exynos_drm_drv.c
index 420953197d0..d6de2e07fa0 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_drv.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_drv.c
@@ -244,8 +244,8 @@ static const struct file_operations exynos_drm_driver_fops = {
244}; 244};
245 245
246static struct drm_driver exynos_drm_driver = { 246static struct drm_driver exynos_drm_driver = {
247 .driver_features = DRIVER_HAVE_IRQ | DRIVER_BUS_PLATFORM | 247 .driver_features = DRIVER_HAVE_IRQ | DRIVER_MODESET |
248 DRIVER_MODESET | DRIVER_GEM | DRIVER_PRIME, 248 DRIVER_GEM | DRIVER_PRIME,
249 .load = exynos_drm_load, 249 .load = exynos_drm_load,
250 .unload = exynos_drm_unload, 250 .unload = exynos_drm_unload,
251 .open = exynos_drm_open, 251 .open = exynos_drm_open,
diff --git a/drivers/gpu/drm/exynos/exynos_drm_encoder.c b/drivers/gpu/drm/exynos/exynos_drm_encoder.c
index 6e9ac7bd1dc..23d5ad379f8 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_encoder.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_encoder.c
@@ -172,19 +172,12 @@ static void exynos_drm_encoder_commit(struct drm_encoder *encoder)
172 manager_ops->commit(manager->dev); 172 manager_ops->commit(manager->dev);
173} 173}
174 174
175static struct drm_crtc *
176exynos_drm_encoder_get_crtc(struct drm_encoder *encoder)
177{
178 return encoder->crtc;
179}
180
181static struct drm_encoder_helper_funcs exynos_encoder_helper_funcs = { 175static struct drm_encoder_helper_funcs exynos_encoder_helper_funcs = {
182 .dpms = exynos_drm_encoder_dpms, 176 .dpms = exynos_drm_encoder_dpms,
183 .mode_fixup = exynos_drm_encoder_mode_fixup, 177 .mode_fixup = exynos_drm_encoder_mode_fixup,
184 .mode_set = exynos_drm_encoder_mode_set, 178 .mode_set = exynos_drm_encoder_mode_set,
185 .prepare = exynos_drm_encoder_prepare, 179 .prepare = exynos_drm_encoder_prepare,
186 .commit = exynos_drm_encoder_commit, 180 .commit = exynos_drm_encoder_commit,
187 .get_crtc = exynos_drm_encoder_get_crtc,
188}; 181};
189 182
190static void exynos_drm_encoder_destroy(struct drm_encoder *encoder) 183static void exynos_drm_encoder_destroy(struct drm_encoder *encoder)
diff --git a/drivers/gpu/drm/exynos/exynos_drm_fb.c b/drivers/gpu/drm/exynos/exynos_drm_fb.c
index f82a299553f..4ccfe4328fa 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_fb.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_fb.c
@@ -51,11 +51,22 @@ struct exynos_drm_fb {
51static void exynos_drm_fb_destroy(struct drm_framebuffer *fb) 51static void exynos_drm_fb_destroy(struct drm_framebuffer *fb)
52{ 52{
53 struct exynos_drm_fb *exynos_fb = to_exynos_fb(fb); 53 struct exynos_drm_fb *exynos_fb = to_exynos_fb(fb);
54 unsigned int i;
54 55
55 DRM_DEBUG_KMS("%s\n", __FILE__); 56 DRM_DEBUG_KMS("%s\n", __FILE__);
56 57
57 drm_framebuffer_cleanup(fb); 58 drm_framebuffer_cleanup(fb);
58 59
60 for (i = 0; i < ARRAY_SIZE(exynos_fb->exynos_gem_obj); i++) {
61 struct drm_gem_object *obj;
62
63 if (exynos_fb->exynos_gem_obj[i] == NULL)
64 continue;
65
66 obj = &exynos_fb->exynos_gem_obj[i]->base;
67 drm_gem_object_unreference_unlocked(obj);
68 }
69
59 kfree(exynos_fb); 70 kfree(exynos_fb);
60 exynos_fb = NULL; 71 exynos_fb = NULL;
61} 72}
@@ -134,11 +145,11 @@ exynos_user_fb_create(struct drm_device *dev, struct drm_file *file_priv,
134 return ERR_PTR(-ENOENT); 145 return ERR_PTR(-ENOENT);
135 } 146 }
136 147
137 drm_gem_object_unreference_unlocked(obj);
138
139 fb = exynos_drm_framebuffer_init(dev, mode_cmd, obj); 148 fb = exynos_drm_framebuffer_init(dev, mode_cmd, obj);
140 if (IS_ERR(fb)) 149 if (IS_ERR(fb)) {
150 drm_gem_object_unreference_unlocked(obj);
141 return fb; 151 return fb;
152 }
142 153
143 exynos_fb = to_exynos_fb(fb); 154 exynos_fb = to_exynos_fb(fb);
144 nr = exynos_drm_format_num_buffers(fb->pixel_format); 155 nr = exynos_drm_format_num_buffers(fb->pixel_format);
@@ -152,8 +163,6 @@ exynos_user_fb_create(struct drm_device *dev, struct drm_file *file_priv,
152 return ERR_PTR(-ENOENT); 163 return ERR_PTR(-ENOENT);
153 } 164 }
154 165
155 drm_gem_object_unreference_unlocked(obj);
156
157 exynos_fb->exynos_gem_obj[i] = to_exynos_gem_obj(obj); 166 exynos_fb->exynos_gem_obj[i] = to_exynos_gem_obj(obj);
158 } 167 }
159 168
diff --git a/drivers/gpu/drm/exynos/exynos_drm_fb.h b/drivers/gpu/drm/exynos/exynos_drm_fb.h
index 3ecb30d9355..50823756cde 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_fb.h
+++ b/drivers/gpu/drm/exynos/exynos_drm_fb.h
@@ -31,10 +31,10 @@
31static inline int exynos_drm_format_num_buffers(uint32_t format) 31static inline int exynos_drm_format_num_buffers(uint32_t format)
32{ 32{
33 switch (format) { 33 switch (format) {
34 case DRM_FORMAT_NV12M: 34 case DRM_FORMAT_NV12:
35 case DRM_FORMAT_NV12MT: 35 case DRM_FORMAT_NV12MT:
36 return 2; 36 return 2;
37 case DRM_FORMAT_YUV420M: 37 case DRM_FORMAT_YUV420:
38 return 3; 38 return 3;
39 default: 39 default:
40 return 1; 40 return 1;
diff --git a/drivers/gpu/drm/exynos/exynos_drm_gem.c b/drivers/gpu/drm/exynos/exynos_drm_gem.c
index fc91293c456..5c8b683029e 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_gem.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_gem.c
@@ -689,7 +689,6 @@ int exynos_drm_gem_dumb_map_offset(struct drm_file *file_priv,
689 struct drm_device *dev, uint32_t handle, 689 struct drm_device *dev, uint32_t handle,
690 uint64_t *offset) 690 uint64_t *offset)
691{ 691{
692 struct exynos_drm_gem_obj *exynos_gem_obj;
693 struct drm_gem_object *obj; 692 struct drm_gem_object *obj;
694 int ret = 0; 693 int ret = 0;
695 694
@@ -710,15 +709,13 @@ int exynos_drm_gem_dumb_map_offset(struct drm_file *file_priv,
710 goto unlock; 709 goto unlock;
711 } 710 }
712 711
713 exynos_gem_obj = to_exynos_gem_obj(obj); 712 if (!obj->map_list.map) {
714 713 ret = drm_gem_create_mmap_offset(obj);
715 if (!exynos_gem_obj->base.map_list.map) {
716 ret = drm_gem_create_mmap_offset(&exynos_gem_obj->base);
717 if (ret) 714 if (ret)
718 goto out; 715 goto out;
719 } 716 }
720 717
721 *offset = (u64)exynos_gem_obj->base.map_list.hash.key << PAGE_SHIFT; 718 *offset = (u64)obj->map_list.hash.key << PAGE_SHIFT;
722 DRM_DEBUG_KMS("offset = 0x%lx\n", (unsigned long)*offset); 719 DRM_DEBUG_KMS("offset = 0x%lx\n", (unsigned long)*offset);
723 720
724out: 721out:
diff --git a/drivers/gpu/drm/exynos/exynos_mixer.c b/drivers/gpu/drm/exynos/exynos_mixer.c
index 68ef0102837..e2147a2ddce 100644
--- a/drivers/gpu/drm/exynos/exynos_mixer.c
+++ b/drivers/gpu/drm/exynos/exynos_mixer.c
@@ -365,7 +365,7 @@ static void vp_video_buffer(struct mixer_context *ctx, int win)
365 switch (win_data->pixel_format) { 365 switch (win_data->pixel_format) {
366 case DRM_FORMAT_NV12MT: 366 case DRM_FORMAT_NV12MT:
367 tiled_mode = true; 367 tiled_mode = true;
368 case DRM_FORMAT_NV12M: 368 case DRM_FORMAT_NV12:
369 crcb_mode = false; 369 crcb_mode = false;
370 buf_num = 2; 370 buf_num = 2;
371 break; 371 break;
@@ -601,18 +601,20 @@ static void mixer_win_reset(struct mixer_context *ctx)
601 mixer_reg_write(res, MXR_BG_COLOR2, 0x008080); 601 mixer_reg_write(res, MXR_BG_COLOR2, 0x008080);
602 602
603 /* setting graphical layers */ 603 /* setting graphical layers */
604
605 val = MXR_GRP_CFG_COLOR_KEY_DISABLE; /* no blank key */ 604 val = MXR_GRP_CFG_COLOR_KEY_DISABLE; /* no blank key */
606 val |= MXR_GRP_CFG_WIN_BLEND_EN; 605 val |= MXR_GRP_CFG_WIN_BLEND_EN;
606 val |= MXR_GRP_CFG_BLEND_PRE_MUL;
607 val |= MXR_GRP_CFG_PIXEL_BLEND_EN;
607 val |= MXR_GRP_CFG_ALPHA_VAL(0xff); /* non-transparent alpha */ 608 val |= MXR_GRP_CFG_ALPHA_VAL(0xff); /* non-transparent alpha */
608 609
609 /* the same configuration for both layers */ 610 /* the same configuration for both layers */
610 mixer_reg_write(res, MXR_GRAPHIC_CFG(0), val); 611 mixer_reg_write(res, MXR_GRAPHIC_CFG(0), val);
611
612 val |= MXR_GRP_CFG_BLEND_PRE_MUL;
613 val |= MXR_GRP_CFG_PIXEL_BLEND_EN;
614 mixer_reg_write(res, MXR_GRAPHIC_CFG(1), val); 612 mixer_reg_write(res, MXR_GRAPHIC_CFG(1), val);
615 613
614 /* setting video layers */
615 val = MXR_GRP_CFG_ALPHA_VAL(0);
616 mixer_reg_write(res, MXR_VIDEO_CFG, val);
617
616 /* configuration of Video Processor Registers */ 618 /* configuration of Video Processor Registers */
617 vp_win_reset(ctx); 619 vp_win_reset(ctx);
618 vp_default_filter(res); 620 vp_default_filter(res);
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 238a5216583..9fe9ebe52a7 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -233,6 +233,7 @@ static const struct intel_device_info intel_sandybridge_d_info = {
233 .has_blt_ring = 1, 233 .has_blt_ring = 1,
234 .has_llc = 1, 234 .has_llc = 1,
235 .has_pch_split = 1, 235 .has_pch_split = 1,
236 .has_force_wake = 1,
236}; 237};
237 238
238static const struct intel_device_info intel_sandybridge_m_info = { 239static const struct intel_device_info intel_sandybridge_m_info = {
@@ -243,6 +244,7 @@ static const struct intel_device_info intel_sandybridge_m_info = {
243 .has_blt_ring = 1, 244 .has_blt_ring = 1,
244 .has_llc = 1, 245 .has_llc = 1,
245 .has_pch_split = 1, 246 .has_pch_split = 1,
247 .has_force_wake = 1,
246}; 248};
247 249
248static const struct intel_device_info intel_ivybridge_d_info = { 250static const struct intel_device_info intel_ivybridge_d_info = {
@@ -252,6 +254,7 @@ static const struct intel_device_info intel_ivybridge_d_info = {
252 .has_blt_ring = 1, 254 .has_blt_ring = 1,
253 .has_llc = 1, 255 .has_llc = 1,
254 .has_pch_split = 1, 256 .has_pch_split = 1,
257 .has_force_wake = 1,
255}; 258};
256 259
257static const struct intel_device_info intel_ivybridge_m_info = { 260static const struct intel_device_info intel_ivybridge_m_info = {
@@ -262,6 +265,7 @@ static const struct intel_device_info intel_ivybridge_m_info = {
262 .has_blt_ring = 1, 265 .has_blt_ring = 1,
263 .has_llc = 1, 266 .has_llc = 1,
264 .has_pch_split = 1, 267 .has_pch_split = 1,
268 .has_force_wake = 1,
265}; 269};
266 270
267static const struct intel_device_info intel_valleyview_m_info = { 271static const struct intel_device_info intel_valleyview_m_info = {
@@ -289,6 +293,7 @@ static const struct intel_device_info intel_haswell_d_info = {
289 .has_blt_ring = 1, 293 .has_blt_ring = 1,
290 .has_llc = 1, 294 .has_llc = 1,
291 .has_pch_split = 1, 295 .has_pch_split = 1,
296 .has_force_wake = 1,
292}; 297};
293 298
294static const struct intel_device_info intel_haswell_m_info = { 299static const struct intel_device_info intel_haswell_m_info = {
@@ -298,6 +303,7 @@ static const struct intel_device_info intel_haswell_m_info = {
298 .has_blt_ring = 1, 303 .has_blt_ring = 1,
299 .has_llc = 1, 304 .has_llc = 1,
300 .has_pch_split = 1, 305 .has_pch_split = 1,
306 .has_force_wake = 1,
301}; 307};
302 308
303static const struct pci_device_id pciidlist[] = { /* aka */ 309static const struct pci_device_id pciidlist[] = { /* aka */
@@ -1139,10 +1145,9 @@ MODULE_LICENSE("GPL and additional rights");
1139 1145
1140/* We give fast paths for the really cool registers */ 1146/* We give fast paths for the really cool registers */
1141#define NEEDS_FORCE_WAKE(dev_priv, reg) \ 1147#define NEEDS_FORCE_WAKE(dev_priv, reg) \
1142 (((dev_priv)->info->gen >= 6) && \ 1148 ((HAS_FORCE_WAKE((dev_priv)->dev)) && \
1143 ((reg) < 0x40000) && \ 1149 ((reg) < 0x40000) && \
1144 ((reg) != FORCEWAKE)) && \ 1150 ((reg) != FORCEWAKE))
1145 (!IS_VALLEYVIEW((dev_priv)->dev))
1146 1151
1147#define __i915_read(x, y) \ 1152#define __i915_read(x, y) \
1148u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \ 1153u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index c9cfc67c2cf..b0b676abde0 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -285,6 +285,7 @@ struct intel_device_info {
285 u8 is_ivybridge:1; 285 u8 is_ivybridge:1;
286 u8 is_valleyview:1; 286 u8 is_valleyview:1;
287 u8 has_pch_split:1; 287 u8 has_pch_split:1;
288 u8 has_force_wake:1;
288 u8 is_haswell:1; 289 u8 is_haswell:1;
289 u8 has_fbc:1; 290 u8 has_fbc:1;
290 u8 has_pipe_cxsr:1; 291 u8 has_pipe_cxsr:1;
@@ -1101,6 +1102,8 @@ struct drm_i915_file_private {
1101#define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT) 1102#define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
1102#define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX) 1103#define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
1103 1104
1105#define HAS_FORCE_WAKE(dev) (INTEL_INFO(dev)->has_force_wake)
1106
1104#include "i915_trace.h" 1107#include "i915_trace.h"
1105 1108
1106/** 1109/**
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 1417660a93e..b1fe0edda95 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -510,7 +510,7 @@ out:
510 return ret; 510 return ret;
511} 511}
512 512
513static void pch_irq_handler(struct drm_device *dev, u32 pch_iir) 513static void ibx_irq_handler(struct drm_device *dev, u32 pch_iir)
514{ 514{
515 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 515 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
516 int pipe; 516 int pipe;
@@ -550,6 +550,35 @@ static void pch_irq_handler(struct drm_device *dev, u32 pch_iir)
550 DRM_DEBUG_DRIVER("PCH transcoder A underrun interrupt\n"); 550 DRM_DEBUG_DRIVER("PCH transcoder A underrun interrupt\n");
551} 551}
552 552
553static void cpt_irq_handler(struct drm_device *dev, u32 pch_iir)
554{
555 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
556 int pipe;
557
558 if (pch_iir & SDE_AUDIO_POWER_MASK_CPT)
559 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
560 (pch_iir & SDE_AUDIO_POWER_MASK_CPT) >>
561 SDE_AUDIO_POWER_SHIFT_CPT);
562
563 if (pch_iir & SDE_AUX_MASK_CPT)
564 DRM_DEBUG_DRIVER("AUX channel interrupt\n");
565
566 if (pch_iir & SDE_GMBUS_CPT)
567 DRM_DEBUG_DRIVER("PCH GMBUS interrupt\n");
568
569 if (pch_iir & SDE_AUDIO_CP_REQ_CPT)
570 DRM_DEBUG_DRIVER("Audio CP request interrupt\n");
571
572 if (pch_iir & SDE_AUDIO_CP_CHG_CPT)
573 DRM_DEBUG_DRIVER("Audio CP change interrupt\n");
574
575 if (pch_iir & SDE_FDI_MASK_CPT)
576 for_each_pipe(pipe)
577 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
578 pipe_name(pipe),
579 I915_READ(FDI_RX_IIR(pipe)));
580}
581
553static irqreturn_t ivybridge_irq_handler(DRM_IRQ_ARGS) 582static irqreturn_t ivybridge_irq_handler(DRM_IRQ_ARGS)
554{ 583{
555 struct drm_device *dev = (struct drm_device *) arg; 584 struct drm_device *dev = (struct drm_device *) arg;
@@ -591,7 +620,7 @@ static irqreturn_t ivybridge_irq_handler(DRM_IRQ_ARGS)
591 620
592 if (pch_iir & SDE_HOTPLUG_MASK_CPT) 621 if (pch_iir & SDE_HOTPLUG_MASK_CPT)
593 queue_work(dev_priv->wq, &dev_priv->hotplug_work); 622 queue_work(dev_priv->wq, &dev_priv->hotplug_work);
594 pch_irq_handler(dev, pch_iir); 623 cpt_irq_handler(dev, pch_iir);
595 624
596 /* clear PCH hotplug event before clear CPU irq */ 625 /* clear PCH hotplug event before clear CPU irq */
597 I915_WRITE(SDEIIR, pch_iir); 626 I915_WRITE(SDEIIR, pch_iir);
@@ -684,7 +713,10 @@ static irqreturn_t ironlake_irq_handler(DRM_IRQ_ARGS)
684 if (de_iir & DE_PCH_EVENT) { 713 if (de_iir & DE_PCH_EVENT) {
685 if (pch_iir & hotplug_mask) 714 if (pch_iir & hotplug_mask)
686 queue_work(dev_priv->wq, &dev_priv->hotplug_work); 715 queue_work(dev_priv->wq, &dev_priv->hotplug_work);
687 pch_irq_handler(dev, pch_iir); 716 if (HAS_PCH_CPT(dev))
717 cpt_irq_handler(dev, pch_iir);
718 else
719 ibx_irq_handler(dev, pch_iir);
688 } 720 }
689 721
690 if (de_iir & DE_PCU_EVENT) { 722 if (de_iir & DE_PCU_EVENT) {
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 2d49b9507ed..48d5e8e051c 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -210,6 +210,14 @@
210#define MI_DISPLAY_FLIP MI_INSTR(0x14, 2) 210#define MI_DISPLAY_FLIP MI_INSTR(0x14, 2)
211#define MI_DISPLAY_FLIP_I915 MI_INSTR(0x14, 1) 211#define MI_DISPLAY_FLIP_I915 MI_INSTR(0x14, 1)
212#define MI_DISPLAY_FLIP_PLANE(n) ((n) << 20) 212#define MI_DISPLAY_FLIP_PLANE(n) ((n) << 20)
213/* IVB has funny definitions for which plane to flip. */
214#define MI_DISPLAY_FLIP_IVB_PLANE_A (0 << 19)
215#define MI_DISPLAY_FLIP_IVB_PLANE_B (1 << 19)
216#define MI_DISPLAY_FLIP_IVB_SPRITE_A (2 << 19)
217#define MI_DISPLAY_FLIP_IVB_SPRITE_B (3 << 19)
218#define MI_DISPLAY_FLIP_IVB_PLANE_C (4 << 19)
219#define MI_DISPLAY_FLIP_IVB_SPRITE_C (5 << 19)
220
213#define MI_SET_CONTEXT MI_INSTR(0x18, 0) 221#define MI_SET_CONTEXT MI_INSTR(0x18, 0)
214#define MI_MM_SPACE_GTT (1<<8) 222#define MI_MM_SPACE_GTT (1<<8)
215#define MI_MM_SPACE_PHYSICAL (0<<8) 223#define MI_MM_SPACE_PHYSICAL (0<<8)
@@ -3313,7 +3321,7 @@
3313 3321
3314/* PCH */ 3322/* PCH */
3315 3323
3316/* south display engine interrupt */ 3324/* south display engine interrupt: IBX */
3317#define SDE_AUDIO_POWER_D (1 << 27) 3325#define SDE_AUDIO_POWER_D (1 << 27)
3318#define SDE_AUDIO_POWER_C (1 << 26) 3326#define SDE_AUDIO_POWER_C (1 << 26)
3319#define SDE_AUDIO_POWER_B (1 << 25) 3327#define SDE_AUDIO_POWER_B (1 << 25)
@@ -3349,15 +3357,44 @@
3349#define SDE_TRANSA_CRC_ERR (1 << 1) 3357#define SDE_TRANSA_CRC_ERR (1 << 1)
3350#define SDE_TRANSA_FIFO_UNDER (1 << 0) 3358#define SDE_TRANSA_FIFO_UNDER (1 << 0)
3351#define SDE_TRANS_MASK (0x3f) 3359#define SDE_TRANS_MASK (0x3f)
3352/* CPT */ 3360
3353#define SDE_CRT_HOTPLUG_CPT (1 << 19) 3361/* south display engine interrupt: CPT/PPT */
3362#define SDE_AUDIO_POWER_D_CPT (1 << 31)
3363#define SDE_AUDIO_POWER_C_CPT (1 << 30)
3364#define SDE_AUDIO_POWER_B_CPT (1 << 29)
3365#define SDE_AUDIO_POWER_SHIFT_CPT 29
3366#define SDE_AUDIO_POWER_MASK_CPT (7 << 29)
3367#define SDE_AUXD_CPT (1 << 27)
3368#define SDE_AUXC_CPT (1 << 26)
3369#define SDE_AUXB_CPT (1 << 25)
3370#define SDE_AUX_MASK_CPT (7 << 25)
3354#define SDE_PORTD_HOTPLUG_CPT (1 << 23) 3371#define SDE_PORTD_HOTPLUG_CPT (1 << 23)
3355#define SDE_PORTC_HOTPLUG_CPT (1 << 22) 3372#define SDE_PORTC_HOTPLUG_CPT (1 << 22)
3356#define SDE_PORTB_HOTPLUG_CPT (1 << 21) 3373#define SDE_PORTB_HOTPLUG_CPT (1 << 21)
3374#define SDE_CRT_HOTPLUG_CPT (1 << 19)
3357#define SDE_HOTPLUG_MASK_CPT (SDE_CRT_HOTPLUG_CPT | \ 3375#define SDE_HOTPLUG_MASK_CPT (SDE_CRT_HOTPLUG_CPT | \
3358 SDE_PORTD_HOTPLUG_CPT | \ 3376 SDE_PORTD_HOTPLUG_CPT | \
3359 SDE_PORTC_HOTPLUG_CPT | \ 3377 SDE_PORTC_HOTPLUG_CPT | \
3360 SDE_PORTB_HOTPLUG_CPT) 3378 SDE_PORTB_HOTPLUG_CPT)
3379#define SDE_GMBUS_CPT (1 << 17)
3380#define SDE_AUDIO_CP_REQ_C_CPT (1 << 10)
3381#define SDE_AUDIO_CP_CHG_C_CPT (1 << 9)
3382#define SDE_FDI_RXC_CPT (1 << 8)
3383#define SDE_AUDIO_CP_REQ_B_CPT (1 << 6)
3384#define SDE_AUDIO_CP_CHG_B_CPT (1 << 5)
3385#define SDE_FDI_RXB_CPT (1 << 4)
3386#define SDE_AUDIO_CP_REQ_A_CPT (1 << 2)
3387#define SDE_AUDIO_CP_CHG_A_CPT (1 << 1)
3388#define SDE_FDI_RXA_CPT (1 << 0)
3389#define SDE_AUDIO_CP_REQ_CPT (SDE_AUDIO_CP_REQ_C_CPT | \
3390 SDE_AUDIO_CP_REQ_B_CPT | \
3391 SDE_AUDIO_CP_REQ_A_CPT)
3392#define SDE_AUDIO_CP_CHG_CPT (SDE_AUDIO_CP_CHG_C_CPT | \
3393 SDE_AUDIO_CP_CHG_B_CPT | \
3394 SDE_AUDIO_CP_CHG_A_CPT)
3395#define SDE_FDI_MASK_CPT (SDE_FDI_RXC_CPT | \
3396 SDE_FDI_RXB_CPT | \
3397 SDE_FDI_RXA_CPT)
3361 3398
3362#define SDEISR 0xc4000 3399#define SDEISR 0xc4000
3363#define SDEIMR 0xc4004 3400#define SDEIMR 0xc4004
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 91478942090..e0aa064def3 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -6158,17 +6158,34 @@ static int intel_gen7_queue_flip(struct drm_device *dev,
6158 struct drm_i915_private *dev_priv = dev->dev_private; 6158 struct drm_i915_private *dev_priv = dev->dev_private;
6159 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 6159 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6160 struct intel_ring_buffer *ring = &dev_priv->ring[BCS]; 6160 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
6161 uint32_t plane_bit = 0;
6161 int ret; 6162 int ret;
6162 6163
6163 ret = intel_pin_and_fence_fb_obj(dev, obj, ring); 6164 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6164 if (ret) 6165 if (ret)
6165 goto err; 6166 goto err;
6166 6167
6168 switch(intel_crtc->plane) {
6169 case PLANE_A:
6170 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
6171 break;
6172 case PLANE_B:
6173 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
6174 break;
6175 case PLANE_C:
6176 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
6177 break;
6178 default:
6179 WARN_ONCE(1, "unknown plane in flip command\n");
6180 ret = -ENODEV;
6181 goto err;
6182 }
6183
6167 ret = intel_ring_begin(ring, 4); 6184 ret = intel_ring_begin(ring, 4);
6168 if (ret) 6185 if (ret)
6169 goto err_unpin; 6186 goto err_unpin;
6170 6187
6171 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | (intel_crtc->plane << 19)); 6188 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
6172 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode)); 6189 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
6173 intel_ring_emit(ring, (obj->gtt_offset)); 6190 intel_ring_emit(ring, (obj->gtt_offset));
6174 intel_ring_emit(ring, (MI_NOOP)); 6191 intel_ring_emit(ring, (MI_NOOP));
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index b59b6d5b758..e5b84ff89ca 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -266,10 +266,15 @@ u32 intel_ring_get_active_head(struct intel_ring_buffer *ring)
266 266
267static int init_ring_common(struct intel_ring_buffer *ring) 267static int init_ring_common(struct intel_ring_buffer *ring)
268{ 268{
269 drm_i915_private_t *dev_priv = ring->dev->dev_private; 269 struct drm_device *dev = ring->dev;
270 drm_i915_private_t *dev_priv = dev->dev_private;
270 struct drm_i915_gem_object *obj = ring->obj; 271 struct drm_i915_gem_object *obj = ring->obj;
272 int ret = 0;
271 u32 head; 273 u32 head;
272 274
275 if (HAS_FORCE_WAKE(dev))
276 gen6_gt_force_wake_get(dev_priv);
277
273 /* Stop the ring if it's running. */ 278 /* Stop the ring if it's running. */
274 I915_WRITE_CTL(ring, 0); 279 I915_WRITE_CTL(ring, 0);
275 I915_WRITE_HEAD(ring, 0); 280 I915_WRITE_HEAD(ring, 0);
@@ -317,7 +322,8 @@ static int init_ring_common(struct intel_ring_buffer *ring)
317 I915_READ_HEAD(ring), 322 I915_READ_HEAD(ring),
318 I915_READ_TAIL(ring), 323 I915_READ_TAIL(ring),
319 I915_READ_START(ring)); 324 I915_READ_START(ring));
320 return -EIO; 325 ret = -EIO;
326 goto out;
321 } 327 }
322 328
323 if (!drm_core_check_feature(ring->dev, DRIVER_MODESET)) 329 if (!drm_core_check_feature(ring->dev, DRIVER_MODESET))
@@ -326,9 +332,14 @@ static int init_ring_common(struct intel_ring_buffer *ring)
326 ring->head = I915_READ_HEAD(ring); 332 ring->head = I915_READ_HEAD(ring);
327 ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR; 333 ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
328 ring->space = ring_space(ring); 334 ring->space = ring_space(ring);
335 ring->last_retired_head = -1;
329 } 336 }
330 337
331 return 0; 338out:
339 if (HAS_FORCE_WAKE(dev))
340 gen6_gt_force_wake_put(dev_priv);
341
342 return ret;
332} 343}
333 344
334static int 345static int
@@ -987,6 +998,10 @@ static int intel_init_ring_buffer(struct drm_device *dev,
987 if (ret) 998 if (ret)
988 goto err_unref; 999 goto err_unref;
989 1000
1001 ret = i915_gem_object_set_to_gtt_domain(obj, true);
1002 if (ret)
1003 goto err_unpin;
1004
990 ring->virtual_start = ioremap_wc(dev->agp->base + obj->gtt_offset, 1005 ring->virtual_start = ioremap_wc(dev->agp->base + obj->gtt_offset,
991 ring->size); 1006 ring->size);
992 if (ring->virtual_start == NULL) { 1007 if (ring->virtual_start == NULL) {
diff --git a/drivers/gpu/drm/radeon/evergreen_cs.c b/drivers/gpu/drm/radeon/evergreen_cs.c
index 4e7dd2b4843..c16554122cc 100644
--- a/drivers/gpu/drm/radeon/evergreen_cs.c
+++ b/drivers/gpu/drm/radeon/evergreen_cs.c
@@ -52,6 +52,7 @@ struct evergreen_cs_track {
52 u32 cb_color_view[12]; 52 u32 cb_color_view[12];
53 u32 cb_color_pitch[12]; 53 u32 cb_color_pitch[12];
54 u32 cb_color_slice[12]; 54 u32 cb_color_slice[12];
55 u32 cb_color_slice_idx[12];
55 u32 cb_color_attrib[12]; 56 u32 cb_color_attrib[12];
56 u32 cb_color_cmask_slice[8];/* unused */ 57 u32 cb_color_cmask_slice[8];/* unused */
57 u32 cb_color_fmask_slice[8];/* unused */ 58 u32 cb_color_fmask_slice[8];/* unused */
@@ -127,12 +128,14 @@ static void evergreen_cs_track_init(struct evergreen_cs_track *track)
127 track->cb_color_info[i] = 0; 128 track->cb_color_info[i] = 0;
128 track->cb_color_view[i] = 0xFFFFFFFF; 129 track->cb_color_view[i] = 0xFFFFFFFF;
129 track->cb_color_pitch[i] = 0; 130 track->cb_color_pitch[i] = 0;
130 track->cb_color_slice[i] = 0; 131 track->cb_color_slice[i] = 0xfffffff;
132 track->cb_color_slice_idx[i] = 0;
131 } 133 }
132 track->cb_target_mask = 0xFFFFFFFF; 134 track->cb_target_mask = 0xFFFFFFFF;
133 track->cb_shader_mask = 0xFFFFFFFF; 135 track->cb_shader_mask = 0xFFFFFFFF;
134 track->cb_dirty = true; 136 track->cb_dirty = true;
135 137
138 track->db_depth_slice = 0xffffffff;
136 track->db_depth_view = 0xFFFFC000; 139 track->db_depth_view = 0xFFFFC000;
137 track->db_depth_size = 0xFFFFFFFF; 140 track->db_depth_size = 0xFFFFFFFF;
138 track->db_depth_control = 0xFFFFFFFF; 141 track->db_depth_control = 0xFFFFFFFF;
@@ -250,10 +253,9 @@ static int evergreen_surface_check_2d(struct radeon_cs_parser *p,
250{ 253{
251 struct evergreen_cs_track *track = p->track; 254 struct evergreen_cs_track *track = p->track;
252 unsigned palign, halign, tileb, slice_pt; 255 unsigned palign, halign, tileb, slice_pt;
256 unsigned mtile_pr, mtile_ps, mtileb;
253 257
254 tileb = 64 * surf->bpe * surf->nsamples; 258 tileb = 64 * surf->bpe * surf->nsamples;
255 palign = track->group_size / (8 * surf->bpe * surf->nsamples);
256 palign = MAX(8, palign);
257 slice_pt = 1; 259 slice_pt = 1;
258 if (tileb > surf->tsplit) { 260 if (tileb > surf->tsplit) {
259 slice_pt = tileb / surf->tsplit; 261 slice_pt = tileb / surf->tsplit;
@@ -262,7 +264,10 @@ static int evergreen_surface_check_2d(struct radeon_cs_parser *p,
262 /* macro tile width & height */ 264 /* macro tile width & height */
263 palign = (8 * surf->bankw * track->npipes) * surf->mtilea; 265 palign = (8 * surf->bankw * track->npipes) * surf->mtilea;
264 halign = (8 * surf->bankh * surf->nbanks) / surf->mtilea; 266 halign = (8 * surf->bankh * surf->nbanks) / surf->mtilea;
265 surf->layer_size = surf->nbx * surf->nby * surf->bpe * slice_pt; 267 mtileb = (palign / 8) * (halign / 8) * tileb;;
268 mtile_pr = surf->nbx / palign;
269 mtile_ps = (mtile_pr * surf->nby) / halign;
270 surf->layer_size = mtile_ps * mtileb * slice_pt;
266 surf->base_align = (palign / 8) * (halign / 8) * tileb; 271 surf->base_align = (palign / 8) * (halign / 8) * tileb;
267 surf->palign = palign; 272 surf->palign = palign;
268 surf->halign = halign; 273 surf->halign = halign;
@@ -434,6 +439,39 @@ static int evergreen_cs_track_validate_cb(struct radeon_cs_parser *p, unsigned i
434 439
435 offset += surf.layer_size * mslice; 440 offset += surf.layer_size * mslice;
436 if (offset > radeon_bo_size(track->cb_color_bo[id])) { 441 if (offset > radeon_bo_size(track->cb_color_bo[id])) {
442 /* old ddx are broken they allocate bo with w*h*bpp but
443 * program slice with ALIGN(h, 8), catch this and patch
444 * command stream.
445 */
446 if (!surf.mode) {
447 volatile u32 *ib = p->ib.ptr;
448 unsigned long tmp, nby, bsize, size, min = 0;
449
450 /* find the height the ddx wants */
451 if (surf.nby > 8) {
452 min = surf.nby - 8;
453 }
454 bsize = radeon_bo_size(track->cb_color_bo[id]);
455 tmp = track->cb_color_bo_offset[id] << 8;
456 for (nby = surf.nby; nby > min; nby--) {
457 size = nby * surf.nbx * surf.bpe * surf.nsamples;
458 if ((tmp + size * mslice) <= bsize) {
459 break;
460 }
461 }
462 if (nby > min) {
463 surf.nby = nby;
464 slice = ((nby * surf.nbx) / 64) - 1;
465 if (!evergreen_surface_check(p, &surf, "cb")) {
466 /* check if this one works */
467 tmp += surf.layer_size * mslice;
468 if (tmp <= bsize) {
469 ib[track->cb_color_slice_idx[id]] = slice;
470 goto old_ddx_ok;
471 }
472 }
473 }
474 }
437 dev_warn(p->dev, "%s:%d cb[%d] bo too small (layer size %d, " 475 dev_warn(p->dev, "%s:%d cb[%d] bo too small (layer size %d, "
438 "offset %d, max layer %d, bo size %ld, slice %d)\n", 476 "offset %d, max layer %d, bo size %ld, slice %d)\n",
439 __func__, __LINE__, id, surf.layer_size, 477 __func__, __LINE__, id, surf.layer_size,
@@ -446,6 +484,7 @@ static int evergreen_cs_track_validate_cb(struct radeon_cs_parser *p, unsigned i
446 surf.tsplit, surf.mtilea); 484 surf.tsplit, surf.mtilea);
447 return -EINVAL; 485 return -EINVAL;
448 } 486 }
487old_ddx_ok:
449 488
450 return 0; 489 return 0;
451} 490}
@@ -1532,6 +1571,7 @@ static int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
1532 case CB_COLOR7_SLICE: 1571 case CB_COLOR7_SLICE:
1533 tmp = (reg - CB_COLOR0_SLICE) / 0x3c; 1572 tmp = (reg - CB_COLOR0_SLICE) / 0x3c;
1534 track->cb_color_slice[tmp] = radeon_get_ib_value(p, idx); 1573 track->cb_color_slice[tmp] = radeon_get_ib_value(p, idx);
1574 track->cb_color_slice_idx[tmp] = idx;
1535 track->cb_dirty = true; 1575 track->cb_dirty = true;
1536 break; 1576 break;
1537 case CB_COLOR8_SLICE: 1577 case CB_COLOR8_SLICE:
@@ -1540,6 +1580,7 @@ static int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
1540 case CB_COLOR11_SLICE: 1580 case CB_COLOR11_SLICE:
1541 tmp = ((reg - CB_COLOR8_SLICE) / 0x1c) + 8; 1581 tmp = ((reg - CB_COLOR8_SLICE) / 0x1c) + 8;
1542 track->cb_color_slice[tmp] = radeon_get_ib_value(p, idx); 1582 track->cb_color_slice[tmp] = radeon_get_ib_value(p, idx);
1583 track->cb_color_slice_idx[tmp] = idx;
1543 track->cb_dirty = true; 1584 track->cb_dirty = true;
1544 break; 1585 break;
1545 case CB_COLOR0_ATTRIB: 1586 case CB_COLOR0_ATTRIB:
diff --git a/drivers/gpu/drm/radeon/ni.c b/drivers/gpu/drm/radeon/ni.c
index 3df4efa1194..3186522a445 100644
--- a/drivers/gpu/drm/radeon/ni.c
+++ b/drivers/gpu/drm/radeon/ni.c
@@ -460,15 +460,28 @@ static void cayman_gpu_init(struct radeon_device *rdev)
460 rdev->config.cayman.max_pipes_per_simd = 4; 460 rdev->config.cayman.max_pipes_per_simd = 4;
461 rdev->config.cayman.max_tile_pipes = 2; 461 rdev->config.cayman.max_tile_pipes = 2;
462 if ((rdev->pdev->device == 0x9900) || 462 if ((rdev->pdev->device == 0x9900) ||
463 (rdev->pdev->device == 0x9901)) { 463 (rdev->pdev->device == 0x9901) ||
464 (rdev->pdev->device == 0x9905) ||
465 (rdev->pdev->device == 0x9906) ||
466 (rdev->pdev->device == 0x9907) ||
467 (rdev->pdev->device == 0x9908) ||
468 (rdev->pdev->device == 0x9909) ||
469 (rdev->pdev->device == 0x9910) ||
470 (rdev->pdev->device == 0x9917)) {
464 rdev->config.cayman.max_simds_per_se = 6; 471 rdev->config.cayman.max_simds_per_se = 6;
465 rdev->config.cayman.max_backends_per_se = 2; 472 rdev->config.cayman.max_backends_per_se = 2;
466 } else if ((rdev->pdev->device == 0x9903) || 473 } else if ((rdev->pdev->device == 0x9903) ||
467 (rdev->pdev->device == 0x9904)) { 474 (rdev->pdev->device == 0x9904) ||
475 (rdev->pdev->device == 0x990A) ||
476 (rdev->pdev->device == 0x9913) ||
477 (rdev->pdev->device == 0x9918)) {
468 rdev->config.cayman.max_simds_per_se = 4; 478 rdev->config.cayman.max_simds_per_se = 4;
469 rdev->config.cayman.max_backends_per_se = 2; 479 rdev->config.cayman.max_backends_per_se = 2;
470 } else if ((rdev->pdev->device == 0x9990) || 480 } else if ((rdev->pdev->device == 0x9919) ||
471 (rdev->pdev->device == 0x9991)) { 481 (rdev->pdev->device == 0x9990) ||
482 (rdev->pdev->device == 0x9991) ||
483 (rdev->pdev->device == 0x9994) ||
484 (rdev->pdev->device == 0x99A0)) {
472 rdev->config.cayman.max_simds_per_se = 3; 485 rdev->config.cayman.max_simds_per_se = 3;
473 rdev->config.cayman.max_backends_per_se = 1; 486 rdev->config.cayman.max_backends_per_se = 1;
474 } else { 487 } else {
diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c
index 45cfcea6350..f30dc95f83b 100644
--- a/drivers/gpu/drm/radeon/r600.c
+++ b/drivers/gpu/drm/radeon/r600.c
@@ -2426,6 +2426,12 @@ int r600_startup(struct radeon_device *rdev)
2426 if (r) 2426 if (r)
2427 return r; 2427 return r;
2428 2428
2429 r = r600_audio_init(rdev);
2430 if (r) {
2431 DRM_ERROR("radeon: audio init failed\n");
2432 return r;
2433 }
2434
2429 return 0; 2435 return 0;
2430} 2436}
2431 2437
@@ -2462,12 +2468,6 @@ int r600_resume(struct radeon_device *rdev)
2462 return r; 2468 return r;
2463 } 2469 }
2464 2470
2465 r = r600_audio_init(rdev);
2466 if (r) {
2467 DRM_ERROR("radeon: audio resume failed\n");
2468 return r;
2469 }
2470
2471 return r; 2471 return r;
2472} 2472}
2473 2473
@@ -2577,9 +2577,6 @@ int r600_init(struct radeon_device *rdev)
2577 rdev->accel_working = false; 2577 rdev->accel_working = false;
2578 } 2578 }
2579 2579
2580 r = r600_audio_init(rdev);
2581 if (r)
2582 return r; /* TODO error handling */
2583 return 0; 2580 return 0;
2584} 2581}
2585 2582
diff --git a/drivers/gpu/drm/radeon/r600_audio.c b/drivers/gpu/drm/radeon/r600_audio.c
index 7c4fa77f018..7479a5c503e 100644
--- a/drivers/gpu/drm/radeon/r600_audio.c
+++ b/drivers/gpu/drm/radeon/r600_audio.c
@@ -192,6 +192,7 @@ void r600_audio_set_clock(struct drm_encoder *encoder, int clock)
192 struct radeon_device *rdev = dev->dev_private; 192 struct radeon_device *rdev = dev->dev_private;
193 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 193 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
194 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 194 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
195 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
195 int base_rate = 48000; 196 int base_rate = 48000;
196 197
197 switch (radeon_encoder->encoder_id) { 198 switch (radeon_encoder->encoder_id) {
@@ -217,8 +218,8 @@ void r600_audio_set_clock(struct drm_encoder *encoder, int clock)
217 WREG32(EVERGREEN_AUDIO_PLL1_DIV, clock * 10); 218 WREG32(EVERGREEN_AUDIO_PLL1_DIV, clock * 10);
218 WREG32(EVERGREEN_AUDIO_PLL1_UNK, 0x00000071); 219 WREG32(EVERGREEN_AUDIO_PLL1_UNK, 0x00000071);
219 220
220 /* Some magic trigger or src sel? */ 221 /* Select DTO source */
221 WREG32_P(0x5ac, 0x01, ~0x77); 222 WREG32(0x5ac, radeon_crtc->crtc_id);
222 } else { 223 } else {
223 switch (dig->dig_encoder) { 224 switch (dig->dig_encoder) {
224 case 0: 225 case 0:
diff --git a/drivers/gpu/drm/radeon/r600_hdmi.c b/drivers/gpu/drm/radeon/r600_hdmi.c
index 226379e00ac..969c27529df 100644
--- a/drivers/gpu/drm/radeon/r600_hdmi.c
+++ b/drivers/gpu/drm/radeon/r600_hdmi.c
@@ -348,7 +348,6 @@ void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mod
348 WREG32(HDMI0_AUDIO_PACKET_CONTROL + offset, 348 WREG32(HDMI0_AUDIO_PACKET_CONTROL + offset,
349 HDMI0_AUDIO_SAMPLE_SEND | /* send audio packets */ 349 HDMI0_AUDIO_SAMPLE_SEND | /* send audio packets */
350 HDMI0_AUDIO_DELAY_EN(1) | /* default audio delay */ 350 HDMI0_AUDIO_DELAY_EN(1) | /* default audio delay */
351 HDMI0_AUDIO_SEND_MAX_PACKETS | /* send NULL packets if no audio is available */
352 HDMI0_AUDIO_PACKETS_PER_LINE(3) | /* should be suffient for all audio modes and small enough for all hblanks */ 351 HDMI0_AUDIO_PACKETS_PER_LINE(3) | /* should be suffient for all audio modes and small enough for all hblanks */
353 HDMI0_60958_CS_UPDATE); /* allow 60958 channel status fields to be updated */ 352 HDMI0_60958_CS_UPDATE); /* allow 60958 channel status fields to be updated */
354 } 353 }
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index 85dac33e3cc..fefcca55c1e 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -1374,9 +1374,9 @@ struct cayman_asic {
1374 1374
1375struct si_asic { 1375struct si_asic {
1376 unsigned max_shader_engines; 1376 unsigned max_shader_engines;
1377 unsigned max_pipes_per_simd;
1378 unsigned max_tile_pipes; 1377 unsigned max_tile_pipes;
1379 unsigned max_simds_per_se; 1378 unsigned max_cu_per_sh;
1379 unsigned max_sh_per_se;
1380 unsigned max_backends_per_se; 1380 unsigned max_backends_per_se;
1381 unsigned max_texture_channel_caches; 1381 unsigned max_texture_channel_caches;
1382 unsigned max_gprs; 1382 unsigned max_gprs;
@@ -1387,7 +1387,6 @@ struct si_asic {
1387 unsigned sc_hiz_tile_fifo_size; 1387 unsigned sc_hiz_tile_fifo_size;
1388 unsigned sc_earlyz_tile_fifo_size; 1388 unsigned sc_earlyz_tile_fifo_size;
1389 1389
1390 unsigned num_shader_engines;
1391 unsigned num_tile_pipes; 1390 unsigned num_tile_pipes;
1392 unsigned num_backends_per_se; 1391 unsigned num_backends_per_se;
1393 unsigned backend_disable_mask_per_asic; 1392 unsigned backend_disable_mask_per_asic;
diff --git a/drivers/gpu/drm/radeon/radeon_drv.c b/drivers/gpu/drm/radeon/radeon_drv.c
index f0bb2b543b1..03e5f5df40f 100644
--- a/drivers/gpu/drm/radeon/radeon_drv.c
+++ b/drivers/gpu/drm/radeon/radeon_drv.c
@@ -57,9 +57,10 @@
57 * 2.13.0 - virtual memory support, streamout 57 * 2.13.0 - virtual memory support, streamout
58 * 2.14.0 - add evergreen tiling informations 58 * 2.14.0 - add evergreen tiling informations
59 * 2.15.0 - add max_pipes query 59 * 2.15.0 - add max_pipes query
60 * 2.16.0 - fix evergreen 2D tiled surface calculation
60 */ 61 */
61#define KMS_DRIVER_MAJOR 2 62#define KMS_DRIVER_MAJOR 2
62#define KMS_DRIVER_MINOR 15 63#define KMS_DRIVER_MINOR 16
63#define KMS_DRIVER_PATCHLEVEL 0 64#define KMS_DRIVER_PATCHLEVEL 0
64int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags); 65int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags);
65int radeon_driver_unload_kms(struct drm_device *dev); 66int radeon_driver_unload_kms(struct drm_device *dev);
diff --git a/drivers/gpu/drm/radeon/radeon_gart.c b/drivers/gpu/drm/radeon/radeon_gart.c
index 79db56e6c2a..59d44937dd9 100644
--- a/drivers/gpu/drm/radeon/radeon_gart.c
+++ b/drivers/gpu/drm/radeon/radeon_gart.c
@@ -476,12 +476,18 @@ int radeon_vm_bo_add(struct radeon_device *rdev,
476 476
477 mutex_lock(&vm->mutex); 477 mutex_lock(&vm->mutex);
478 if (last_pfn > vm->last_pfn) { 478 if (last_pfn > vm->last_pfn) {
479 /* grow va space 32M by 32M */ 479 /* release mutex and lock in right order */
480 unsigned align = ((32 << 20) >> 12) - 1; 480 mutex_unlock(&vm->mutex);
481 radeon_mutex_lock(&rdev->cs_mutex); 481 radeon_mutex_lock(&rdev->cs_mutex);
482 radeon_vm_unbind_locked(rdev, vm); 482 mutex_lock(&vm->mutex);
483 /* and check again */
484 if (last_pfn > vm->last_pfn) {
485 /* grow va space 32M by 32M */
486 unsigned align = ((32 << 20) >> 12) - 1;
487 radeon_vm_unbind_locked(rdev, vm);
488 vm->last_pfn = (last_pfn + align) & ~align;
489 }
483 radeon_mutex_unlock(&rdev->cs_mutex); 490 radeon_mutex_unlock(&rdev->cs_mutex);
484 vm->last_pfn = (last_pfn + align) & ~align;
485 } 491 }
486 head = &vm->va; 492 head = &vm->va;
487 last_offset = 0; 493 last_offset = 0;
@@ -595,8 +601,8 @@ int radeon_vm_bo_rmv(struct radeon_device *rdev,
595 if (bo_va == NULL) 601 if (bo_va == NULL)
596 return 0; 602 return 0;
597 603
598 mutex_lock(&vm->mutex);
599 radeon_mutex_lock(&rdev->cs_mutex); 604 radeon_mutex_lock(&rdev->cs_mutex);
605 mutex_lock(&vm->mutex);
600 radeon_vm_bo_update_pte(rdev, vm, bo, NULL); 606 radeon_vm_bo_update_pte(rdev, vm, bo, NULL);
601 radeon_mutex_unlock(&rdev->cs_mutex); 607 radeon_mutex_unlock(&rdev->cs_mutex);
602 list_del(&bo_va->vm_list); 608 list_del(&bo_va->vm_list);
@@ -641,9 +647,8 @@ void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm)
641 struct radeon_bo_va *bo_va, *tmp; 647 struct radeon_bo_va *bo_va, *tmp;
642 int r; 648 int r;
643 649
644 mutex_lock(&vm->mutex);
645
646 radeon_mutex_lock(&rdev->cs_mutex); 650 radeon_mutex_lock(&rdev->cs_mutex);
651 mutex_lock(&vm->mutex);
647 radeon_vm_unbind_locked(rdev, vm); 652 radeon_vm_unbind_locked(rdev, vm);
648 radeon_mutex_unlock(&rdev->cs_mutex); 653 radeon_mutex_unlock(&rdev->cs_mutex);
649 654
diff --git a/drivers/gpu/drm/radeon/radeon_kms.c b/drivers/gpu/drm/radeon/radeon_kms.c
index f1016a5820d..5c58d7d90cb 100644
--- a/drivers/gpu/drm/radeon/radeon_kms.c
+++ b/drivers/gpu/drm/radeon/radeon_kms.c
@@ -273,7 +273,7 @@ int radeon_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
273 break; 273 break;
274 case RADEON_INFO_MAX_PIPES: 274 case RADEON_INFO_MAX_PIPES:
275 if (rdev->family >= CHIP_TAHITI) 275 if (rdev->family >= CHIP_TAHITI)
276 value = rdev->config.si.max_pipes_per_simd; 276 value = rdev->config.si.max_cu_per_sh;
277 else if (rdev->family >= CHIP_CAYMAN) 277 else if (rdev->family >= CHIP_CAYMAN)
278 value = rdev->config.cayman.max_pipes_per_simd; 278 value = rdev->config.cayman.max_pipes_per_simd;
279 else if (rdev->family >= CHIP_CEDAR) 279 else if (rdev->family >= CHIP_CEDAR)
diff --git a/drivers/gpu/drm/radeon/rs600.c b/drivers/gpu/drm/radeon/rs600.c
index 25f9eef12c4..e95c5e61d4e 100644
--- a/drivers/gpu/drm/radeon/rs600.c
+++ b/drivers/gpu/drm/radeon/rs600.c
@@ -908,12 +908,6 @@ static int rs600_startup(struct radeon_device *rdev)
908 return r; 908 return r;
909 } 909 }
910 910
911 r = r600_audio_init(rdev);
912 if (r) {
913 dev_err(rdev->dev, "failed initializing audio\n");
914 return r;
915 }
916
917 r = radeon_ib_pool_start(rdev); 911 r = radeon_ib_pool_start(rdev);
918 if (r) 912 if (r)
919 return r; 913 return r;
@@ -922,6 +916,12 @@ static int rs600_startup(struct radeon_device *rdev)
922 if (r) 916 if (r)
923 return r; 917 return r;
924 918
919 r = r600_audio_init(rdev);
920 if (r) {
921 dev_err(rdev->dev, "failed initializing audio\n");
922 return r;
923 }
924
925 return 0; 925 return 0;
926} 926}
927 927
diff --git a/drivers/gpu/drm/radeon/rs690.c b/drivers/gpu/drm/radeon/rs690.c
index 3277ddecfe9..159b6a43fda 100644
--- a/drivers/gpu/drm/radeon/rs690.c
+++ b/drivers/gpu/drm/radeon/rs690.c
@@ -637,12 +637,6 @@ static int rs690_startup(struct radeon_device *rdev)
637 return r; 637 return r;
638 } 638 }
639 639
640 r = r600_audio_init(rdev);
641 if (r) {
642 dev_err(rdev->dev, "failed initializing audio\n");
643 return r;
644 }
645
646 r = radeon_ib_pool_start(rdev); 640 r = radeon_ib_pool_start(rdev);
647 if (r) 641 if (r)
648 return r; 642 return r;
@@ -651,6 +645,12 @@ static int rs690_startup(struct radeon_device *rdev)
651 if (r) 645 if (r)
652 return r; 646 return r;
653 647
648 r = r600_audio_init(rdev);
649 if (r) {
650 dev_err(rdev->dev, "failed initializing audio\n");
651 return r;
652 }
653
654 return 0; 654 return 0;
655} 655}
656 656
diff --git a/drivers/gpu/drm/radeon/rv770.c b/drivers/gpu/drm/radeon/rv770.c
index 04ddc365a90..4ad0281fdc3 100644
--- a/drivers/gpu/drm/radeon/rv770.c
+++ b/drivers/gpu/drm/radeon/rv770.c
@@ -956,6 +956,12 @@ static int rv770_startup(struct radeon_device *rdev)
956 if (r) 956 if (r)
957 return r; 957 return r;
958 958
959 r = r600_audio_init(rdev);
960 if (r) {
961 DRM_ERROR("radeon: audio init failed\n");
962 return r;
963 }
964
959 return 0; 965 return 0;
960} 966}
961 967
@@ -978,12 +984,6 @@ int rv770_resume(struct radeon_device *rdev)
978 return r; 984 return r;
979 } 985 }
980 986
981 r = r600_audio_init(rdev);
982 if (r) {
983 dev_err(rdev->dev, "radeon: audio init failed\n");
984 return r;
985 }
986
987 return r; 987 return r;
988 988
989} 989}
@@ -1092,12 +1092,6 @@ int rv770_init(struct radeon_device *rdev)
1092 rdev->accel_working = false; 1092 rdev->accel_working = false;
1093 } 1093 }
1094 1094
1095 r = r600_audio_init(rdev);
1096 if (r) {
1097 dev_err(rdev->dev, "radeon: audio init failed\n");
1098 return r;
1099 }
1100
1101 return 0; 1095 return 0;
1102} 1096}
1103 1097
diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c
index 549732e56ca..c7b61f16ecf 100644
--- a/drivers/gpu/drm/radeon/si.c
+++ b/drivers/gpu/drm/radeon/si.c
@@ -867,200 +867,6 @@ void dce6_bandwidth_update(struct radeon_device *rdev)
867/* 867/*
868 * Core functions 868 * Core functions
869 */ 869 */
870static u32 si_get_tile_pipe_to_backend_map(struct radeon_device *rdev,
871 u32 num_tile_pipes,
872 u32 num_backends_per_asic,
873 u32 *backend_disable_mask_per_asic,
874 u32 num_shader_engines)
875{
876 u32 backend_map = 0;
877 u32 enabled_backends_mask = 0;
878 u32 enabled_backends_count = 0;
879 u32 num_backends_per_se;
880 u32 cur_pipe;
881 u32 swizzle_pipe[SI_MAX_PIPES];
882 u32 cur_backend = 0;
883 u32 i;
884 bool force_no_swizzle;
885
886 /* force legal values */
887 if (num_tile_pipes < 1)
888 num_tile_pipes = 1;
889 if (num_tile_pipes > rdev->config.si.max_tile_pipes)
890 num_tile_pipes = rdev->config.si.max_tile_pipes;
891 if (num_shader_engines < 1)
892 num_shader_engines = 1;
893 if (num_shader_engines > rdev->config.si.max_shader_engines)
894 num_shader_engines = rdev->config.si.max_shader_engines;
895 if (num_backends_per_asic < num_shader_engines)
896 num_backends_per_asic = num_shader_engines;
897 if (num_backends_per_asic > (rdev->config.si.max_backends_per_se * num_shader_engines))
898 num_backends_per_asic = rdev->config.si.max_backends_per_se * num_shader_engines;
899
900 /* make sure we have the same number of backends per se */
901 num_backends_per_asic = ALIGN(num_backends_per_asic, num_shader_engines);
902 /* set up the number of backends per se */
903 num_backends_per_se = num_backends_per_asic / num_shader_engines;
904 if (num_backends_per_se > rdev->config.si.max_backends_per_se) {
905 num_backends_per_se = rdev->config.si.max_backends_per_se;
906 num_backends_per_asic = num_backends_per_se * num_shader_engines;
907 }
908
909 /* create enable mask and count for enabled backends */
910 for (i = 0; i < SI_MAX_BACKENDS; ++i) {
911 if (((*backend_disable_mask_per_asic >> i) & 1) == 0) {
912 enabled_backends_mask |= (1 << i);
913 ++enabled_backends_count;
914 }
915 if (enabled_backends_count == num_backends_per_asic)
916 break;
917 }
918
919 /* force the backends mask to match the current number of backends */
920 if (enabled_backends_count != num_backends_per_asic) {
921 u32 this_backend_enabled;
922 u32 shader_engine;
923 u32 backend_per_se;
924
925 enabled_backends_mask = 0;
926 enabled_backends_count = 0;
927 *backend_disable_mask_per_asic = SI_MAX_BACKENDS_MASK;
928 for (i = 0; i < SI_MAX_BACKENDS; ++i) {
929 /* calc the current se */
930 shader_engine = i / rdev->config.si.max_backends_per_se;
931 /* calc the backend per se */
932 backend_per_se = i % rdev->config.si.max_backends_per_se;
933 /* default to not enabled */
934 this_backend_enabled = 0;
935 if ((shader_engine < num_shader_engines) &&
936 (backend_per_se < num_backends_per_se))
937 this_backend_enabled = 1;
938 if (this_backend_enabled) {
939 enabled_backends_mask |= (1 << i);
940 *backend_disable_mask_per_asic &= ~(1 << i);
941 ++enabled_backends_count;
942 }
943 }
944 }
945
946
947 memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * SI_MAX_PIPES);
948 switch (rdev->family) {
949 case CHIP_TAHITI:
950 case CHIP_PITCAIRN:
951 case CHIP_VERDE:
952 force_no_swizzle = true;
953 break;
954 default:
955 force_no_swizzle = false;
956 break;
957 }
958 if (force_no_swizzle) {
959 bool last_backend_enabled = false;
960
961 force_no_swizzle = false;
962 for (i = 0; i < SI_MAX_BACKENDS; ++i) {
963 if (((enabled_backends_mask >> i) & 1) == 1) {
964 if (last_backend_enabled)
965 force_no_swizzle = true;
966 last_backend_enabled = true;
967 } else
968 last_backend_enabled = false;
969 }
970 }
971
972 switch (num_tile_pipes) {
973 case 1:
974 case 3:
975 case 5:
976 case 7:
977 DRM_ERROR("odd number of pipes!\n");
978 break;
979 case 2:
980 swizzle_pipe[0] = 0;
981 swizzle_pipe[1] = 1;
982 break;
983 case 4:
984 if (force_no_swizzle) {
985 swizzle_pipe[0] = 0;
986 swizzle_pipe[1] = 1;
987 swizzle_pipe[2] = 2;
988 swizzle_pipe[3] = 3;
989 } else {
990 swizzle_pipe[0] = 0;
991 swizzle_pipe[1] = 2;
992 swizzle_pipe[2] = 1;
993 swizzle_pipe[3] = 3;
994 }
995 break;
996 case 6:
997 if (force_no_swizzle) {
998 swizzle_pipe[0] = 0;
999 swizzle_pipe[1] = 1;
1000 swizzle_pipe[2] = 2;
1001 swizzle_pipe[3] = 3;
1002 swizzle_pipe[4] = 4;
1003 swizzle_pipe[5] = 5;
1004 } else {
1005 swizzle_pipe[0] = 0;
1006 swizzle_pipe[1] = 2;
1007 swizzle_pipe[2] = 4;
1008 swizzle_pipe[3] = 1;
1009 swizzle_pipe[4] = 3;
1010 swizzle_pipe[5] = 5;
1011 }
1012 break;
1013 case 8:
1014 if (force_no_swizzle) {
1015 swizzle_pipe[0] = 0;
1016 swizzle_pipe[1] = 1;
1017 swizzle_pipe[2] = 2;
1018 swizzle_pipe[3] = 3;
1019 swizzle_pipe[4] = 4;
1020 swizzle_pipe[5] = 5;
1021 swizzle_pipe[6] = 6;
1022 swizzle_pipe[7] = 7;
1023 } else {
1024 swizzle_pipe[0] = 0;
1025 swizzle_pipe[1] = 2;
1026 swizzle_pipe[2] = 4;
1027 swizzle_pipe[3] = 6;
1028 swizzle_pipe[4] = 1;
1029 swizzle_pipe[5] = 3;
1030 swizzle_pipe[6] = 5;
1031 swizzle_pipe[7] = 7;
1032 }
1033 break;
1034 }
1035
1036 for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) {
1037 while (((1 << cur_backend) & enabled_backends_mask) == 0)
1038 cur_backend = (cur_backend + 1) % SI_MAX_BACKENDS;
1039
1040 backend_map |= (((cur_backend & 0xf) << (swizzle_pipe[cur_pipe] * 4)));
1041
1042 cur_backend = (cur_backend + 1) % SI_MAX_BACKENDS;
1043 }
1044
1045 return backend_map;
1046}
1047
1048static u32 si_get_disable_mask_per_asic(struct radeon_device *rdev,
1049 u32 disable_mask_per_se,
1050 u32 max_disable_mask_per_se,
1051 u32 num_shader_engines)
1052{
1053 u32 disable_field_width_per_se = r600_count_pipe_bits(disable_mask_per_se);
1054 u32 disable_mask_per_asic = disable_mask_per_se & max_disable_mask_per_se;
1055
1056 if (num_shader_engines == 1)
1057 return disable_mask_per_asic;
1058 else if (num_shader_engines == 2)
1059 return disable_mask_per_asic | (disable_mask_per_asic << disable_field_width_per_se);
1060 else
1061 return 0xffffffff;
1062}
1063
1064static void si_tiling_mode_table_init(struct radeon_device *rdev) 870static void si_tiling_mode_table_init(struct radeon_device *rdev)
1065{ 871{
1066 const u32 num_tile_mode_states = 32; 872 const u32 num_tile_mode_states = 32;
@@ -1562,18 +1368,151 @@ static void si_tiling_mode_table_init(struct radeon_device *rdev)
1562 DRM_ERROR("unknown asic: 0x%x\n", rdev->family); 1368 DRM_ERROR("unknown asic: 0x%x\n", rdev->family);
1563} 1369}
1564 1370
1371static void si_select_se_sh(struct radeon_device *rdev,
1372 u32 se_num, u32 sh_num)
1373{
1374 u32 data = INSTANCE_BROADCAST_WRITES;
1375
1376 if ((se_num == 0xffffffff) && (sh_num == 0xffffffff))
1377 data = SH_BROADCAST_WRITES | SE_BROADCAST_WRITES;
1378 else if (se_num == 0xffffffff)
1379 data |= SE_BROADCAST_WRITES | SH_INDEX(sh_num);
1380 else if (sh_num == 0xffffffff)
1381 data |= SH_BROADCAST_WRITES | SE_INDEX(se_num);
1382 else
1383 data |= SH_INDEX(sh_num) | SE_INDEX(se_num);
1384 WREG32(GRBM_GFX_INDEX, data);
1385}
1386
1387static u32 si_create_bitmask(u32 bit_width)
1388{
1389 u32 i, mask = 0;
1390
1391 for (i = 0; i < bit_width; i++) {
1392 mask <<= 1;
1393 mask |= 1;
1394 }
1395 return mask;
1396}
1397
1398static u32 si_get_cu_enabled(struct radeon_device *rdev, u32 cu_per_sh)
1399{
1400 u32 data, mask;
1401
1402 data = RREG32(CC_GC_SHADER_ARRAY_CONFIG);
1403 if (data & 1)
1404 data &= INACTIVE_CUS_MASK;
1405 else
1406 data = 0;
1407 data |= RREG32(GC_USER_SHADER_ARRAY_CONFIG);
1408
1409 data >>= INACTIVE_CUS_SHIFT;
1410
1411 mask = si_create_bitmask(cu_per_sh);
1412
1413 return ~data & mask;
1414}
1415
1416static void si_setup_spi(struct radeon_device *rdev,
1417 u32 se_num, u32 sh_per_se,
1418 u32 cu_per_sh)
1419{
1420 int i, j, k;
1421 u32 data, mask, active_cu;
1422
1423 for (i = 0; i < se_num; i++) {
1424 for (j = 0; j < sh_per_se; j++) {
1425 si_select_se_sh(rdev, i, j);
1426 data = RREG32(SPI_STATIC_THREAD_MGMT_3);
1427 active_cu = si_get_cu_enabled(rdev, cu_per_sh);
1428
1429 mask = 1;
1430 for (k = 0; k < 16; k++) {
1431 mask <<= k;
1432 if (active_cu & mask) {
1433 data &= ~mask;
1434 WREG32(SPI_STATIC_THREAD_MGMT_3, data);
1435 break;
1436 }
1437 }
1438 }
1439 }
1440 si_select_se_sh(rdev, 0xffffffff, 0xffffffff);
1441}
1442
1443static u32 si_get_rb_disabled(struct radeon_device *rdev,
1444 u32 max_rb_num, u32 se_num,
1445 u32 sh_per_se)
1446{
1447 u32 data, mask;
1448
1449 data = RREG32(CC_RB_BACKEND_DISABLE);
1450 if (data & 1)
1451 data &= BACKEND_DISABLE_MASK;
1452 else
1453 data = 0;
1454 data |= RREG32(GC_USER_RB_BACKEND_DISABLE);
1455
1456 data >>= BACKEND_DISABLE_SHIFT;
1457
1458 mask = si_create_bitmask(max_rb_num / se_num / sh_per_se);
1459
1460 return data & mask;
1461}
1462
1463static void si_setup_rb(struct radeon_device *rdev,
1464 u32 se_num, u32 sh_per_se,
1465 u32 max_rb_num)
1466{
1467 int i, j;
1468 u32 data, mask;
1469 u32 disabled_rbs = 0;
1470 u32 enabled_rbs = 0;
1471
1472 for (i = 0; i < se_num; i++) {
1473 for (j = 0; j < sh_per_se; j++) {
1474 si_select_se_sh(rdev, i, j);
1475 data = si_get_rb_disabled(rdev, max_rb_num, se_num, sh_per_se);
1476 disabled_rbs |= data << ((i * sh_per_se + j) * TAHITI_RB_BITMAP_WIDTH_PER_SH);
1477 }
1478 }
1479 si_select_se_sh(rdev, 0xffffffff, 0xffffffff);
1480
1481 mask = 1;
1482 for (i = 0; i < max_rb_num; i++) {
1483 if (!(disabled_rbs & mask))
1484 enabled_rbs |= mask;
1485 mask <<= 1;
1486 }
1487
1488 for (i = 0; i < se_num; i++) {
1489 si_select_se_sh(rdev, i, 0xffffffff);
1490 data = 0;
1491 for (j = 0; j < sh_per_se; j++) {
1492 switch (enabled_rbs & 3) {
1493 case 1:
1494 data |= (RASTER_CONFIG_RB_MAP_0 << (i * sh_per_se + j) * 2);
1495 break;
1496 case 2:
1497 data |= (RASTER_CONFIG_RB_MAP_3 << (i * sh_per_se + j) * 2);
1498 break;
1499 case 3:
1500 default:
1501 data |= (RASTER_CONFIG_RB_MAP_2 << (i * sh_per_se + j) * 2);
1502 break;
1503 }
1504 enabled_rbs >>= 2;
1505 }
1506 WREG32(PA_SC_RASTER_CONFIG, data);
1507 }
1508 si_select_se_sh(rdev, 0xffffffff, 0xffffffff);
1509}
1510
1565static void si_gpu_init(struct radeon_device *rdev) 1511static void si_gpu_init(struct radeon_device *rdev)
1566{ 1512{
1567 u32 cc_rb_backend_disable = 0;
1568 u32 cc_gc_shader_array_config;
1569 u32 gb_addr_config = 0; 1513 u32 gb_addr_config = 0;
1570 u32 mc_shared_chmap, mc_arb_ramcfg; 1514 u32 mc_shared_chmap, mc_arb_ramcfg;
1571 u32 gb_backend_map;
1572 u32 cgts_tcc_disable;
1573 u32 sx_debug_1; 1515 u32 sx_debug_1;
1574 u32 gc_user_shader_array_config;
1575 u32 gc_user_rb_backend_disable;
1576 u32 cgts_user_tcc_disable;
1577 u32 hdp_host_path_cntl; 1516 u32 hdp_host_path_cntl;
1578 u32 tmp; 1517 u32 tmp;
1579 int i, j; 1518 int i, j;
@@ -1581,9 +1520,9 @@ static void si_gpu_init(struct radeon_device *rdev)
1581 switch (rdev->family) { 1520 switch (rdev->family) {
1582 case CHIP_TAHITI: 1521 case CHIP_TAHITI:
1583 rdev->config.si.max_shader_engines = 2; 1522 rdev->config.si.max_shader_engines = 2;
1584 rdev->config.si.max_pipes_per_simd = 4;
1585 rdev->config.si.max_tile_pipes = 12; 1523 rdev->config.si.max_tile_pipes = 12;
1586 rdev->config.si.max_simds_per_se = 8; 1524 rdev->config.si.max_cu_per_sh = 8;
1525 rdev->config.si.max_sh_per_se = 2;
1587 rdev->config.si.max_backends_per_se = 4; 1526 rdev->config.si.max_backends_per_se = 4;
1588 rdev->config.si.max_texture_channel_caches = 12; 1527 rdev->config.si.max_texture_channel_caches = 12;
1589 rdev->config.si.max_gprs = 256; 1528 rdev->config.si.max_gprs = 256;
@@ -1594,12 +1533,13 @@ static void si_gpu_init(struct radeon_device *rdev)
1594 rdev->config.si.sc_prim_fifo_size_backend = 0x100; 1533 rdev->config.si.sc_prim_fifo_size_backend = 0x100;
1595 rdev->config.si.sc_hiz_tile_fifo_size = 0x30; 1534 rdev->config.si.sc_hiz_tile_fifo_size = 0x30;
1596 rdev->config.si.sc_earlyz_tile_fifo_size = 0x130; 1535 rdev->config.si.sc_earlyz_tile_fifo_size = 0x130;
1536 gb_addr_config = TAHITI_GB_ADDR_CONFIG_GOLDEN;
1597 break; 1537 break;
1598 case CHIP_PITCAIRN: 1538 case CHIP_PITCAIRN:
1599 rdev->config.si.max_shader_engines = 2; 1539 rdev->config.si.max_shader_engines = 2;
1600 rdev->config.si.max_pipes_per_simd = 4;
1601 rdev->config.si.max_tile_pipes = 8; 1540 rdev->config.si.max_tile_pipes = 8;
1602 rdev->config.si.max_simds_per_se = 5; 1541 rdev->config.si.max_cu_per_sh = 5;
1542 rdev->config.si.max_sh_per_se = 2;
1603 rdev->config.si.max_backends_per_se = 4; 1543 rdev->config.si.max_backends_per_se = 4;
1604 rdev->config.si.max_texture_channel_caches = 8; 1544 rdev->config.si.max_texture_channel_caches = 8;
1605 rdev->config.si.max_gprs = 256; 1545 rdev->config.si.max_gprs = 256;
@@ -1610,13 +1550,14 @@ static void si_gpu_init(struct radeon_device *rdev)
1610 rdev->config.si.sc_prim_fifo_size_backend = 0x100; 1550 rdev->config.si.sc_prim_fifo_size_backend = 0x100;
1611 rdev->config.si.sc_hiz_tile_fifo_size = 0x30; 1551 rdev->config.si.sc_hiz_tile_fifo_size = 0x30;
1612 rdev->config.si.sc_earlyz_tile_fifo_size = 0x130; 1552 rdev->config.si.sc_earlyz_tile_fifo_size = 0x130;
1553 gb_addr_config = TAHITI_GB_ADDR_CONFIG_GOLDEN;
1613 break; 1554 break;
1614 case CHIP_VERDE: 1555 case CHIP_VERDE:
1615 default: 1556 default:
1616 rdev->config.si.max_shader_engines = 1; 1557 rdev->config.si.max_shader_engines = 1;
1617 rdev->config.si.max_pipes_per_simd = 4;
1618 rdev->config.si.max_tile_pipes = 4; 1558 rdev->config.si.max_tile_pipes = 4;
1619 rdev->config.si.max_simds_per_se = 2; 1559 rdev->config.si.max_cu_per_sh = 2;
1560 rdev->config.si.max_sh_per_se = 2;
1620 rdev->config.si.max_backends_per_se = 4; 1561 rdev->config.si.max_backends_per_se = 4;
1621 rdev->config.si.max_texture_channel_caches = 4; 1562 rdev->config.si.max_texture_channel_caches = 4;
1622 rdev->config.si.max_gprs = 256; 1563 rdev->config.si.max_gprs = 256;
@@ -1627,6 +1568,7 @@ static void si_gpu_init(struct radeon_device *rdev)
1627 rdev->config.si.sc_prim_fifo_size_backend = 0x40; 1568 rdev->config.si.sc_prim_fifo_size_backend = 0x40;
1628 rdev->config.si.sc_hiz_tile_fifo_size = 0x30; 1569 rdev->config.si.sc_hiz_tile_fifo_size = 0x30;
1629 rdev->config.si.sc_earlyz_tile_fifo_size = 0x130; 1570 rdev->config.si.sc_earlyz_tile_fifo_size = 0x130;
1571 gb_addr_config = VERDE_GB_ADDR_CONFIG_GOLDEN;
1630 break; 1572 break;
1631 } 1573 }
1632 1574
@@ -1648,31 +1590,7 @@ static void si_gpu_init(struct radeon_device *rdev)
1648 mc_shared_chmap = RREG32(MC_SHARED_CHMAP); 1590 mc_shared_chmap = RREG32(MC_SHARED_CHMAP);
1649 mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG); 1591 mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
1650 1592
1651 cc_rb_backend_disable = RREG32(CC_RB_BACKEND_DISABLE);
1652 cc_gc_shader_array_config = RREG32(CC_GC_SHADER_ARRAY_CONFIG);
1653 cgts_tcc_disable = 0xffff0000;
1654 for (i = 0; i < rdev->config.si.max_texture_channel_caches; i++)
1655 cgts_tcc_disable &= ~(1 << (16 + i));
1656 gc_user_rb_backend_disable = RREG32(GC_USER_RB_BACKEND_DISABLE);
1657 gc_user_shader_array_config = RREG32(GC_USER_SHADER_ARRAY_CONFIG);
1658 cgts_user_tcc_disable = RREG32(CGTS_USER_TCC_DISABLE);
1659
1660 rdev->config.si.num_shader_engines = rdev->config.si.max_shader_engines;
1661 rdev->config.si.num_tile_pipes = rdev->config.si.max_tile_pipes; 1593 rdev->config.si.num_tile_pipes = rdev->config.si.max_tile_pipes;
1662 tmp = ((~gc_user_rb_backend_disable) & BACKEND_DISABLE_MASK) >> BACKEND_DISABLE_SHIFT;
1663 rdev->config.si.num_backends_per_se = r600_count_pipe_bits(tmp);
1664 tmp = (gc_user_rb_backend_disable & BACKEND_DISABLE_MASK) >> BACKEND_DISABLE_SHIFT;
1665 rdev->config.si.backend_disable_mask_per_asic =
1666 si_get_disable_mask_per_asic(rdev, tmp, SI_MAX_BACKENDS_PER_SE_MASK,
1667 rdev->config.si.num_shader_engines);
1668 rdev->config.si.backend_map =
1669 si_get_tile_pipe_to_backend_map(rdev, rdev->config.si.num_tile_pipes,
1670 rdev->config.si.num_backends_per_se *
1671 rdev->config.si.num_shader_engines,
1672 &rdev->config.si.backend_disable_mask_per_asic,
1673 rdev->config.si.num_shader_engines);
1674 tmp = ((~cgts_user_tcc_disable) & TCC_DISABLE_MASK) >> TCC_DISABLE_SHIFT;
1675 rdev->config.si.num_texture_channel_caches = r600_count_pipe_bits(tmp);
1676 rdev->config.si.mem_max_burst_length_bytes = 256; 1594 rdev->config.si.mem_max_burst_length_bytes = 256;
1677 tmp = (mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT; 1595 tmp = (mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT;
1678 rdev->config.si.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024; 1596 rdev->config.si.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024;
@@ -1683,55 +1601,8 @@ static void si_gpu_init(struct radeon_device *rdev)
1683 rdev->config.si.num_gpus = 1; 1601 rdev->config.si.num_gpus = 1;
1684 rdev->config.si.multi_gpu_tile_size = 64; 1602 rdev->config.si.multi_gpu_tile_size = 64;
1685 1603
1686 gb_addr_config = 0; 1604 /* fix up row size */
1687 switch (rdev->config.si.num_tile_pipes) { 1605 gb_addr_config &= ~ROW_SIZE_MASK;
1688 case 1:
1689 gb_addr_config |= NUM_PIPES(0);
1690 break;
1691 case 2:
1692 gb_addr_config |= NUM_PIPES(1);
1693 break;
1694 case 4:
1695 gb_addr_config |= NUM_PIPES(2);
1696 break;
1697 case 8:
1698 default:
1699 gb_addr_config |= NUM_PIPES(3);
1700 break;
1701 }
1702
1703 tmp = (rdev->config.si.mem_max_burst_length_bytes / 256) - 1;
1704 gb_addr_config |= PIPE_INTERLEAVE_SIZE(tmp);
1705 gb_addr_config |= NUM_SHADER_ENGINES(rdev->config.si.num_shader_engines - 1);
1706 tmp = (rdev->config.si.shader_engine_tile_size / 16) - 1;
1707 gb_addr_config |= SHADER_ENGINE_TILE_SIZE(tmp);
1708 switch (rdev->config.si.num_gpus) {
1709 case 1:
1710 default:
1711 gb_addr_config |= NUM_GPUS(0);
1712 break;
1713 case 2:
1714 gb_addr_config |= NUM_GPUS(1);
1715 break;
1716 case 4:
1717 gb_addr_config |= NUM_GPUS(2);
1718 break;
1719 }
1720 switch (rdev->config.si.multi_gpu_tile_size) {
1721 case 16:
1722 gb_addr_config |= MULTI_GPU_TILE_SIZE(0);
1723 break;
1724 case 32:
1725 default:
1726 gb_addr_config |= MULTI_GPU_TILE_SIZE(1);
1727 break;
1728 case 64:
1729 gb_addr_config |= MULTI_GPU_TILE_SIZE(2);
1730 break;
1731 case 128:
1732 gb_addr_config |= MULTI_GPU_TILE_SIZE(3);
1733 break;
1734 }
1735 switch (rdev->config.si.mem_row_size_in_kb) { 1606 switch (rdev->config.si.mem_row_size_in_kb) {
1736 case 1: 1607 case 1:
1737 default: 1608 default:
@@ -1745,26 +1616,6 @@ static void si_gpu_init(struct radeon_device *rdev)
1745 break; 1616 break;
1746 } 1617 }
1747 1618
1748 tmp = (gb_addr_config & NUM_PIPES_MASK) >> NUM_PIPES_SHIFT;
1749 rdev->config.si.num_tile_pipes = (1 << tmp);
1750 tmp = (gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT;
1751 rdev->config.si.mem_max_burst_length_bytes = (tmp + 1) * 256;
1752 tmp = (gb_addr_config & NUM_SHADER_ENGINES_MASK) >> NUM_SHADER_ENGINES_SHIFT;
1753 rdev->config.si.num_shader_engines = tmp + 1;
1754 tmp = (gb_addr_config & NUM_GPUS_MASK) >> NUM_GPUS_SHIFT;
1755 rdev->config.si.num_gpus = tmp + 1;
1756 tmp = (gb_addr_config & MULTI_GPU_TILE_SIZE_MASK) >> MULTI_GPU_TILE_SIZE_SHIFT;
1757 rdev->config.si.multi_gpu_tile_size = 1 << tmp;
1758 tmp = (gb_addr_config & ROW_SIZE_MASK) >> ROW_SIZE_SHIFT;
1759 rdev->config.si.mem_row_size_in_kb = 1 << tmp;
1760
1761 gb_backend_map =
1762 si_get_tile_pipe_to_backend_map(rdev, rdev->config.si.num_tile_pipes,
1763 rdev->config.si.num_backends_per_se *
1764 rdev->config.si.num_shader_engines,
1765 &rdev->config.si.backend_disable_mask_per_asic,
1766 rdev->config.si.num_shader_engines);
1767
1768 /* setup tiling info dword. gb_addr_config is not adequate since it does 1619 /* setup tiling info dword. gb_addr_config is not adequate since it does
1769 * not have bank info, so create a custom tiling dword. 1620 * not have bank info, so create a custom tiling dword.
1770 * bits 3:0 num_pipes 1621 * bits 3:0 num_pipes
@@ -1789,33 +1640,29 @@ static void si_gpu_init(struct radeon_device *rdev)
1789 rdev->config.si.tile_config |= (3 << 0); 1640 rdev->config.si.tile_config |= (3 << 0);
1790 break; 1641 break;
1791 } 1642 }
1792 rdev->config.si.tile_config |= 1643 if ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT)
1793 ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) << 4; 1644 rdev->config.si.tile_config |= 1 << 4;
1645 else
1646 rdev->config.si.tile_config |= 0 << 4;
1794 rdev->config.si.tile_config |= 1647 rdev->config.si.tile_config |=
1795 ((gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT) << 8; 1648 ((gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT) << 8;
1796 rdev->config.si.tile_config |= 1649 rdev->config.si.tile_config |=
1797 ((gb_addr_config & ROW_SIZE_MASK) >> ROW_SIZE_SHIFT) << 12; 1650 ((gb_addr_config & ROW_SIZE_MASK) >> ROW_SIZE_SHIFT) << 12;
1798 1651
1799 rdev->config.si.backend_map = gb_backend_map;
1800 WREG32(GB_ADDR_CONFIG, gb_addr_config); 1652 WREG32(GB_ADDR_CONFIG, gb_addr_config);
1801 WREG32(DMIF_ADDR_CONFIG, gb_addr_config); 1653 WREG32(DMIF_ADDR_CONFIG, gb_addr_config);
1802 WREG32(HDP_ADDR_CONFIG, gb_addr_config); 1654 WREG32(HDP_ADDR_CONFIG, gb_addr_config);
1803 1655
1804 /* primary versions */ 1656 si_tiling_mode_table_init(rdev);
1805 WREG32(CC_RB_BACKEND_DISABLE, cc_rb_backend_disable);
1806 WREG32(CC_SYS_RB_BACKEND_DISABLE, cc_rb_backend_disable);
1807 WREG32(CC_GC_SHADER_ARRAY_CONFIG, cc_gc_shader_array_config);
1808
1809 WREG32(CGTS_TCC_DISABLE, cgts_tcc_disable);
1810 1657
1811 /* user versions */ 1658 si_setup_rb(rdev, rdev->config.si.max_shader_engines,
1812 WREG32(GC_USER_RB_BACKEND_DISABLE, cc_rb_backend_disable); 1659 rdev->config.si.max_sh_per_se,
1813 WREG32(GC_USER_SYS_RB_BACKEND_DISABLE, cc_rb_backend_disable); 1660 rdev->config.si.max_backends_per_se);
1814 WREG32(GC_USER_SHADER_ARRAY_CONFIG, cc_gc_shader_array_config);
1815 1661
1816 WREG32(CGTS_USER_TCC_DISABLE, cgts_tcc_disable); 1662 si_setup_spi(rdev, rdev->config.si.max_shader_engines,
1663 rdev->config.si.max_sh_per_se,
1664 rdev->config.si.max_cu_per_sh);
1817 1665
1818 si_tiling_mode_table_init(rdev);
1819 1666
1820 /* set HW defaults for 3D engine */ 1667 /* set HW defaults for 3D engine */
1821 WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) | 1668 WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) |
diff --git a/drivers/gpu/drm/radeon/sid.h b/drivers/gpu/drm/radeon/sid.h
index 53ea2c42dbd..db406796286 100644
--- a/drivers/gpu/drm/radeon/sid.h
+++ b/drivers/gpu/drm/radeon/sid.h
@@ -24,6 +24,11 @@
24#ifndef SI_H 24#ifndef SI_H
25#define SI_H 25#define SI_H
26 26
27#define TAHITI_RB_BITMAP_WIDTH_PER_SH 2
28
29#define TAHITI_GB_ADDR_CONFIG_GOLDEN 0x12011003
30#define VERDE_GB_ADDR_CONFIG_GOLDEN 0x12010002
31
27#define CG_MULT_THERMAL_STATUS 0x714 32#define CG_MULT_THERMAL_STATUS 0x714
28#define ASIC_MAX_TEMP(x) ((x) << 0) 33#define ASIC_MAX_TEMP(x) ((x) << 0)
29#define ASIC_MAX_TEMP_MASK 0x000001ff 34#define ASIC_MAX_TEMP_MASK 0x000001ff
@@ -408,6 +413,12 @@
408#define SOFT_RESET_IA (1 << 15) 413#define SOFT_RESET_IA (1 << 15)
409 414
410#define GRBM_GFX_INDEX 0x802C 415#define GRBM_GFX_INDEX 0x802C
416#define INSTANCE_INDEX(x) ((x) << 0)
417#define SH_INDEX(x) ((x) << 8)
418#define SE_INDEX(x) ((x) << 16)
419#define SH_BROADCAST_WRITES (1 << 29)
420#define INSTANCE_BROADCAST_WRITES (1 << 30)
421#define SE_BROADCAST_WRITES (1 << 31)
411 422
412#define GRBM_INT_CNTL 0x8060 423#define GRBM_INT_CNTL 0x8060
413# define RDERR_INT_ENABLE (1 << 0) 424# define RDERR_INT_ENABLE (1 << 0)
@@ -480,6 +491,8 @@
480#define VGT_TF_MEMORY_BASE 0x89B8 491#define VGT_TF_MEMORY_BASE 0x89B8
481 492
482#define CC_GC_SHADER_ARRAY_CONFIG 0x89bc 493#define CC_GC_SHADER_ARRAY_CONFIG 0x89bc
494#define INACTIVE_CUS_MASK 0xFFFF0000
495#define INACTIVE_CUS_SHIFT 16
483#define GC_USER_SHADER_ARRAY_CONFIG 0x89c0 496#define GC_USER_SHADER_ARRAY_CONFIG 0x89c0
484 497
485#define PA_CL_ENHANCE 0x8A14 498#define PA_CL_ENHANCE 0x8A14
@@ -688,6 +701,12 @@
688#define RLC_MC_CNTL 0xC344 701#define RLC_MC_CNTL 0xC344
689#define RLC_UCODE_CNTL 0xC348 702#define RLC_UCODE_CNTL 0xC348
690 703
704#define PA_SC_RASTER_CONFIG 0x28350
705# define RASTER_CONFIG_RB_MAP_0 0
706# define RASTER_CONFIG_RB_MAP_1 1
707# define RASTER_CONFIG_RB_MAP_2 2
708# define RASTER_CONFIG_RB_MAP_3 3
709
691#define VGT_EVENT_INITIATOR 0x28a90 710#define VGT_EVENT_INITIATOR 0x28a90
692# define SAMPLE_STREAMOUTSTATS1 (1 << 0) 711# define SAMPLE_STREAMOUTSTATS1 (1 << 0)
693# define SAMPLE_STREAMOUTSTATS2 (2 << 0) 712# define SAMPLE_STREAMOUTSTATS2 (2 << 0)
diff --git a/drivers/gpu/drm/ttm/ttm_bo.c b/drivers/gpu/drm/ttm/ttm_bo.c
index b67cfcaa661..36f4b28c1b9 100644
--- a/drivers/gpu/drm/ttm/ttm_bo.c
+++ b/drivers/gpu/drm/ttm/ttm_bo.c
@@ -1204,6 +1204,7 @@ int ttm_bo_init(struct ttm_bo_device *bdev,
1204 (*destroy)(bo); 1204 (*destroy)(bo);
1205 else 1205 else
1206 kfree(bo); 1206 kfree(bo);
1207 ttm_mem_global_free(mem_glob, acc_size);
1207 return -EINVAL; 1208 return -EINVAL;
1208 } 1209 }
1209 bo->destroy = destroy; 1210 bo->destroy = destroy;
@@ -1307,22 +1308,14 @@ int ttm_bo_create(struct ttm_bo_device *bdev,
1307 struct ttm_buffer_object **p_bo) 1308 struct ttm_buffer_object **p_bo)
1308{ 1309{
1309 struct ttm_buffer_object *bo; 1310 struct ttm_buffer_object *bo;
1310 struct ttm_mem_global *mem_glob = bdev->glob->mem_glob;
1311 size_t acc_size; 1311 size_t acc_size;
1312 int ret; 1312 int ret;
1313 1313
1314 acc_size = ttm_bo_acc_size(bdev, size, sizeof(struct ttm_buffer_object));
1315 ret = ttm_mem_global_alloc(mem_glob, acc_size, false, false);
1316 if (unlikely(ret != 0))
1317 return ret;
1318
1319 bo = kzalloc(sizeof(*bo), GFP_KERNEL); 1314 bo = kzalloc(sizeof(*bo), GFP_KERNEL);
1320 1315 if (unlikely(bo == NULL))
1321 if (unlikely(bo == NULL)) {
1322 ttm_mem_global_free(mem_glob, acc_size);
1323 return -ENOMEM; 1316 return -ENOMEM;
1324 }
1325 1317
1318 acc_size = ttm_bo_acc_size(bdev, size, sizeof(struct ttm_buffer_object));
1326 ret = ttm_bo_init(bdev, bo, size, type, placement, page_alignment, 1319 ret = ttm_bo_init(bdev, bo, size, type, placement, page_alignment,
1327 buffer_start, interruptible, 1320 buffer_start, interruptible,
1328 persistent_swap_storage, acc_size, NULL, NULL); 1321 persistent_swap_storage, acc_size, NULL, NULL);
diff --git a/drivers/gpu/vga/vga_switcheroo.c b/drivers/gpu/vga/vga_switcheroo.c
index 38f9534ac51..5b3c7d135dc 100644
--- a/drivers/gpu/vga/vga_switcheroo.c
+++ b/drivers/gpu/vga/vga_switcheroo.c
@@ -190,6 +190,19 @@ find_active_client(struct list_head *head)
190 return NULL; 190 return NULL;
191} 191}
192 192
193int vga_switcheroo_get_client_state(struct pci_dev *pdev)
194{
195 struct vga_switcheroo_client *client;
196
197 client = find_client_from_pci(&vgasr_priv.clients, pdev);
198 if (!client)
199 return VGA_SWITCHEROO_NOT_FOUND;
200 if (!vgasr_priv.active)
201 return VGA_SWITCHEROO_INIT;
202 return client->pwr_state;
203}
204EXPORT_SYMBOL(vga_switcheroo_get_client_state);
205
193void vga_switcheroo_unregister_client(struct pci_dev *pdev) 206void vga_switcheroo_unregister_client(struct pci_dev *pdev)
194{ 207{
195 struct vga_switcheroo_client *client; 208 struct vga_switcheroo_client *client;
@@ -291,8 +304,6 @@ static int vga_switchto_stage1(struct vga_switcheroo_client *new_client)
291 vga_switchon(new_client); 304 vga_switchon(new_client);
292 305
293 vga_set_default_device(new_client->pdev); 306 vga_set_default_device(new_client->pdev);
294 set_audio_state(new_client->id, VGA_SWITCHEROO_ON);
295
296 return 0; 307 return 0;
297} 308}
298 309
@@ -308,6 +319,8 @@ static int vga_switchto_stage2(struct vga_switcheroo_client *new_client)
308 319
309 active->active = false; 320 active->active = false;
310 321
322 set_audio_state(active->id, VGA_SWITCHEROO_OFF);
323
311 if (new_client->fb_info) { 324 if (new_client->fb_info) {
312 struct fb_event event; 325 struct fb_event event;
313 event.info = new_client->fb_info; 326 event.info = new_client->fb_info;
@@ -321,11 +334,11 @@ static int vga_switchto_stage2(struct vga_switcheroo_client *new_client)
321 if (new_client->ops->reprobe) 334 if (new_client->ops->reprobe)
322 new_client->ops->reprobe(new_client->pdev); 335 new_client->ops->reprobe(new_client->pdev);
323 336
324 set_audio_state(active->id, VGA_SWITCHEROO_OFF);
325
326 if (active->pwr_state == VGA_SWITCHEROO_ON) 337 if (active->pwr_state == VGA_SWITCHEROO_ON)
327 vga_switchoff(active); 338 vga_switchoff(active);
328 339
340 set_audio_state(new_client->id, VGA_SWITCHEROO_ON);
341
329 new_client->active = true; 342 new_client->active = true;
330 return 0; 343 return 0;
331} 344}
@@ -371,8 +384,9 @@ vga_switcheroo_debugfs_write(struct file *filp, const char __user *ubuf,
371 /* pwr off the device not in use */ 384 /* pwr off the device not in use */
372 if (strncmp(usercmd, "OFF", 3) == 0) { 385 if (strncmp(usercmd, "OFF", 3) == 0) {
373 list_for_each_entry(client, &vgasr_priv.clients, list) { 386 list_for_each_entry(client, &vgasr_priv.clients, list) {
374 if (client->active) 387 if (client->active || client_is_audio(client))
375 continue; 388 continue;
389 set_audio_state(client->id, VGA_SWITCHEROO_OFF);
376 if (client->pwr_state == VGA_SWITCHEROO_ON) 390 if (client->pwr_state == VGA_SWITCHEROO_ON)
377 vga_switchoff(client); 391 vga_switchoff(client);
378 } 392 }
@@ -381,10 +395,11 @@ vga_switcheroo_debugfs_write(struct file *filp, const char __user *ubuf,
381 /* pwr on the device not in use */ 395 /* pwr on the device not in use */
382 if (strncmp(usercmd, "ON", 2) == 0) { 396 if (strncmp(usercmd, "ON", 2) == 0) {
383 list_for_each_entry(client, &vgasr_priv.clients, list) { 397 list_for_each_entry(client, &vgasr_priv.clients, list) {
384 if (client->active) 398 if (client->active || client_is_audio(client))
385 continue; 399 continue;
386 if (client->pwr_state == VGA_SWITCHEROO_OFF) 400 if (client->pwr_state == VGA_SWITCHEROO_OFF)
387 vga_switchon(client); 401 vga_switchon(client);
402 set_audio_state(client->id, VGA_SWITCHEROO_ON);
388 } 403 }
389 goto out; 404 goto out;
390 } 405 }
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-22 17:39:13 -0400