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-rw-r--r--drivers/gpu/drm/radeon/atombios_encoders.c4
-rw-r--r--drivers/gpu/drm/radeon/r100.c2
-rw-r--r--drivers/gpu/drm/radeon/r600.c2
-rw-r--r--drivers/gpu/drm/radeon/r600_cp.c6
-rw-r--r--drivers/gpu/drm/radeon/radeon_clocks.c24
-rw-r--r--drivers/gpu/drm/radeon/radeon_combios.c8
-rw-r--r--drivers/gpu/drm/radeon/radeon_i2c.c4
-rw-r--r--drivers/gpu/drm/radeon/radeon_legacy_encoders.c12
8 files changed, 35 insertions, 27 deletions
diff --git a/drivers/gpu/drm/radeon/atombios_encoders.c b/drivers/gpu/drm/radeon/atombios_encoders.c
index e607c4d7dd9..2d39f9977e0 100644
--- a/drivers/gpu/drm/radeon/atombios_encoders.c
+++ b/drivers/gpu/drm/radeon/atombios_encoders.c
@@ -230,6 +230,10 @@ atombios_dvo_setup(struct drm_encoder *encoder, int action)
230 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 230 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
231 return; 231 return;
232 232
233 /* some R4xx chips have the wrong frev */
234 if (rdev->family <= CHIP_RV410)
235 frev = 1;
236
233 switch (frev) { 237 switch (frev) {
234 case 1: 238 case 1:
235 switch (crev) { 239 switch (crev) {
diff --git a/drivers/gpu/drm/radeon/r100.c b/drivers/gpu/drm/radeon/r100.c
index 81801c176aa..fe33d35dae8 100644
--- a/drivers/gpu/drm/radeon/r100.c
+++ b/drivers/gpu/drm/radeon/r100.c
@@ -2553,7 +2553,7 @@ static void r100_pll_errata_after_data(struct radeon_device *rdev)
2553 * or the chip could hang on a subsequent access 2553 * or the chip could hang on a subsequent access
2554 */ 2554 */
2555 if (rdev->pll_errata & CHIP_ERRATA_PLL_DELAY) { 2555 if (rdev->pll_errata & CHIP_ERRATA_PLL_DELAY) {
2556 udelay(5000); 2556 mdelay(5);
2557 } 2557 }
2558 2558
2559 /* This function is required to workaround a hardware bug in some (all?) 2559 /* This function is required to workaround a hardware bug in some (all?)
diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c
index 391bd2636a8..de71243b591 100644
--- a/drivers/gpu/drm/radeon/r600.c
+++ b/drivers/gpu/drm/radeon/r600.c
@@ -2839,7 +2839,7 @@ void r600_rlc_stop(struct radeon_device *rdev)
2839 /* r7xx asics need to soft reset RLC before halting */ 2839 /* r7xx asics need to soft reset RLC before halting */
2840 WREG32(SRBM_SOFT_RESET, SOFT_RESET_RLC); 2840 WREG32(SRBM_SOFT_RESET, SOFT_RESET_RLC);
2841 RREG32(SRBM_SOFT_RESET); 2841 RREG32(SRBM_SOFT_RESET);
2842 udelay(15000); 2842 mdelay(15);
2843 WREG32(SRBM_SOFT_RESET, 0); 2843 WREG32(SRBM_SOFT_RESET, 0);
2844 RREG32(SRBM_SOFT_RESET); 2844 RREG32(SRBM_SOFT_RESET);
2845 } 2845 }
diff --git a/drivers/gpu/drm/radeon/r600_cp.c b/drivers/gpu/drm/radeon/r600_cp.c
index 84c54625095..75ed17c9611 100644
--- a/drivers/gpu/drm/radeon/r600_cp.c
+++ b/drivers/gpu/drm/radeon/r600_cp.c
@@ -407,7 +407,7 @@ static void r600_cp_load_microcode(drm_radeon_private_t *dev_priv)
407 407
408 RADEON_WRITE(R600_GRBM_SOFT_RESET, R600_SOFT_RESET_CP); 408 RADEON_WRITE(R600_GRBM_SOFT_RESET, R600_SOFT_RESET_CP);
409 RADEON_READ(R600_GRBM_SOFT_RESET); 409 RADEON_READ(R600_GRBM_SOFT_RESET);
410 DRM_UDELAY(15000); 410 mdelay(15);
411 RADEON_WRITE(R600_GRBM_SOFT_RESET, 0); 411 RADEON_WRITE(R600_GRBM_SOFT_RESET, 0);
412 412
413 fw_data = (const __be32 *)dev_priv->me_fw->data; 413 fw_data = (const __be32 *)dev_priv->me_fw->data;
@@ -500,7 +500,7 @@ static void r700_cp_load_microcode(drm_radeon_private_t *dev_priv)
500 500
501 RADEON_WRITE(R600_GRBM_SOFT_RESET, R600_SOFT_RESET_CP); 501 RADEON_WRITE(R600_GRBM_SOFT_RESET, R600_SOFT_RESET_CP);
502 RADEON_READ(R600_GRBM_SOFT_RESET); 502 RADEON_READ(R600_GRBM_SOFT_RESET);
503 DRM_UDELAY(15000); 503 mdelay(15);
504 RADEON_WRITE(R600_GRBM_SOFT_RESET, 0); 504 RADEON_WRITE(R600_GRBM_SOFT_RESET, 0);
505 505
506 fw_data = (const __be32 *)dev_priv->pfp_fw->data; 506 fw_data = (const __be32 *)dev_priv->pfp_fw->data;
@@ -1797,7 +1797,7 @@ static void r600_cp_init_ring_buffer(struct drm_device *dev,
1797 1797
1798 RADEON_WRITE(R600_GRBM_SOFT_RESET, R600_SOFT_RESET_CP); 1798 RADEON_WRITE(R600_GRBM_SOFT_RESET, R600_SOFT_RESET_CP);
1799 RADEON_READ(R600_GRBM_SOFT_RESET); 1799 RADEON_READ(R600_GRBM_SOFT_RESET);
1800 DRM_UDELAY(15000); 1800 mdelay(15);
1801 RADEON_WRITE(R600_GRBM_SOFT_RESET, 0); 1801 RADEON_WRITE(R600_GRBM_SOFT_RESET, 0);
1802 1802
1803 1803
diff --git a/drivers/gpu/drm/radeon/radeon_clocks.c b/drivers/gpu/drm/radeon/radeon_clocks.c
index 6ae0c75f016..9c6b29a4192 100644
--- a/drivers/gpu/drm/radeon/radeon_clocks.c
+++ b/drivers/gpu/drm/radeon/radeon_clocks.c
@@ -633,7 +633,7 @@ void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable)
633 tmp &= ~(R300_SCLK_FORCE_VAP); 633 tmp &= ~(R300_SCLK_FORCE_VAP);
634 tmp |= RADEON_SCLK_FORCE_CP; 634 tmp |= RADEON_SCLK_FORCE_CP;
635 WREG32_PLL(RADEON_SCLK_CNTL, tmp); 635 WREG32_PLL(RADEON_SCLK_CNTL, tmp);
636 udelay(15000); 636 mdelay(15);
637 637
638 tmp = RREG32_PLL(R300_SCLK_CNTL2); 638 tmp = RREG32_PLL(R300_SCLK_CNTL2);
639 tmp &= ~(R300_SCLK_FORCE_TCL | 639 tmp &= ~(R300_SCLK_FORCE_TCL |
@@ -651,12 +651,12 @@ void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable)
651 tmp |= (RADEON_ENGIN_DYNCLK_MODE | 651 tmp |= (RADEON_ENGIN_DYNCLK_MODE |
652 (0x01 << RADEON_ACTIVE_HILO_LAT_SHIFT)); 652 (0x01 << RADEON_ACTIVE_HILO_LAT_SHIFT));
653 WREG32_PLL(RADEON_CLK_PWRMGT_CNTL, tmp); 653 WREG32_PLL(RADEON_CLK_PWRMGT_CNTL, tmp);
654 udelay(15000); 654 mdelay(15);
655 655
656 tmp = RREG32_PLL(RADEON_CLK_PIN_CNTL); 656 tmp = RREG32_PLL(RADEON_CLK_PIN_CNTL);
657 tmp |= RADEON_SCLK_DYN_START_CNTL; 657 tmp |= RADEON_SCLK_DYN_START_CNTL;
658 WREG32_PLL(RADEON_CLK_PIN_CNTL, tmp); 658 WREG32_PLL(RADEON_CLK_PIN_CNTL, tmp);
659 udelay(15000); 659 mdelay(15);
660 660
661 /* When DRI is enabled, setting DYN_STOP_LAT to zero can cause some R200 661 /* When DRI is enabled, setting DYN_STOP_LAT to zero can cause some R200
662 to lockup randomly, leave them as set by BIOS. 662 to lockup randomly, leave them as set by BIOS.
@@ -696,7 +696,7 @@ void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable)
696 tmp |= RADEON_SCLK_MORE_FORCEON; 696 tmp |= RADEON_SCLK_MORE_FORCEON;
697 } 697 }
698 WREG32_PLL(RADEON_SCLK_MORE_CNTL, tmp); 698 WREG32_PLL(RADEON_SCLK_MORE_CNTL, tmp);
699 udelay(15000); 699 mdelay(15);
700 } 700 }
701 701
702 /* RV200::A11 A12, RV250::A11 A12 */ 702 /* RV200::A11 A12, RV250::A11 A12 */
@@ -709,7 +709,7 @@ void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable)
709 tmp |= RADEON_TCL_BYPASS_DISABLE; 709 tmp |= RADEON_TCL_BYPASS_DISABLE;
710 WREG32_PLL(RADEON_PLL_PWRMGT_CNTL, tmp); 710 WREG32_PLL(RADEON_PLL_PWRMGT_CNTL, tmp);
711 } 711 }
712 udelay(15000); 712 mdelay(15);
713 713
714 /*enable dynamic mode for display clocks (PIXCLK and PIX2CLK) */ 714 /*enable dynamic mode for display clocks (PIXCLK and PIX2CLK) */
715 tmp = RREG32_PLL(RADEON_PIXCLKS_CNTL); 715 tmp = RREG32_PLL(RADEON_PIXCLKS_CNTL);
@@ -722,14 +722,14 @@ void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable)
722 RADEON_PIXCLK_TMDS_ALWAYS_ONb); 722 RADEON_PIXCLK_TMDS_ALWAYS_ONb);
723 723
724 WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp); 724 WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp);
725 udelay(15000); 725 mdelay(15);
726 726
727 tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL); 727 tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL);
728 tmp |= (RADEON_PIXCLK_ALWAYS_ONb | 728 tmp |= (RADEON_PIXCLK_ALWAYS_ONb |
729 RADEON_PIXCLK_DAC_ALWAYS_ONb); 729 RADEON_PIXCLK_DAC_ALWAYS_ONb);
730 730
731 WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp); 731 WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp);
732 udelay(15000); 732 mdelay(15);
733 } 733 }
734 } else { 734 } else {
735 /* Turn everything OFF (ForceON to everything) */ 735 /* Turn everything OFF (ForceON to everything) */
@@ -861,7 +861,7 @@ void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable)
861 } 861 }
862 WREG32_PLL(RADEON_SCLK_CNTL, tmp); 862 WREG32_PLL(RADEON_SCLK_CNTL, tmp);
863 863
864 udelay(16000); 864 mdelay(16);
865 865
866 if ((rdev->family == CHIP_R300) || 866 if ((rdev->family == CHIP_R300) ||
867 (rdev->family == CHIP_R350)) { 867 (rdev->family == CHIP_R350)) {
@@ -870,7 +870,7 @@ void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable)
870 R300_SCLK_FORCE_GA | 870 R300_SCLK_FORCE_GA |
871 R300_SCLK_FORCE_CBA); 871 R300_SCLK_FORCE_CBA);
872 WREG32_PLL(R300_SCLK_CNTL2, tmp); 872 WREG32_PLL(R300_SCLK_CNTL2, tmp);
873 udelay(16000); 873 mdelay(16);
874 } 874 }
875 875
876 if (rdev->flags & RADEON_IS_IGP) { 876 if (rdev->flags & RADEON_IS_IGP) {
@@ -878,7 +878,7 @@ void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable)
878 tmp &= ~(RADEON_FORCEON_MCLKA | 878 tmp &= ~(RADEON_FORCEON_MCLKA |
879 RADEON_FORCEON_YCLKA); 879 RADEON_FORCEON_YCLKA);
880 WREG32_PLL(RADEON_MCLK_CNTL, tmp); 880 WREG32_PLL(RADEON_MCLK_CNTL, tmp);
881 udelay(16000); 881 mdelay(16);
882 } 882 }
883 883
884 if ((rdev->family == CHIP_RV200) || 884 if ((rdev->family == CHIP_RV200) ||
@@ -887,7 +887,7 @@ void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable)
887 tmp = RREG32_PLL(RADEON_SCLK_MORE_CNTL); 887 tmp = RREG32_PLL(RADEON_SCLK_MORE_CNTL);
888 tmp |= RADEON_SCLK_MORE_FORCEON; 888 tmp |= RADEON_SCLK_MORE_FORCEON;
889 WREG32_PLL(RADEON_SCLK_MORE_CNTL, tmp); 889 WREG32_PLL(RADEON_SCLK_MORE_CNTL, tmp);
890 udelay(16000); 890 mdelay(16);
891 } 891 }
892 892
893 tmp = RREG32_PLL(RADEON_PIXCLKS_CNTL); 893 tmp = RREG32_PLL(RADEON_PIXCLKS_CNTL);
@@ -900,7 +900,7 @@ void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable)
900 RADEON_PIXCLK_TMDS_ALWAYS_ONb); 900 RADEON_PIXCLK_TMDS_ALWAYS_ONb);
901 901
902 WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp); 902 WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp);
903 udelay(16000); 903 mdelay(16);
904 904
905 tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL); 905 tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL);
906 tmp &= ~(RADEON_PIXCLK_ALWAYS_ONb | 906 tmp &= ~(RADEON_PIXCLK_ALWAYS_ONb |
diff --git a/drivers/gpu/drm/radeon/radeon_combios.c b/drivers/gpu/drm/radeon/radeon_combios.c
index 81fc100be7e..2cad9fde92f 100644
--- a/drivers/gpu/drm/radeon/radeon_combios.c
+++ b/drivers/gpu/drm/radeon/radeon_combios.c
@@ -2845,7 +2845,7 @@ bool radeon_combios_external_tmds_setup(struct drm_encoder *encoder)
2845 case 4: 2845 case 4:
2846 val = RBIOS16(index); 2846 val = RBIOS16(index);
2847 index += 2; 2847 index += 2;
2848 udelay(val * 1000); 2848 mdelay(val);
2849 break; 2849 break;
2850 case 6: 2850 case 6:
2851 slave_addr = id & 0xff; 2851 slave_addr = id & 0xff;
@@ -3044,7 +3044,7 @@ static void combios_parse_pll_table(struct drm_device *dev, uint16_t offset)
3044 udelay(150); 3044 udelay(150);
3045 break; 3045 break;
3046 case 2: 3046 case 2:
3047 udelay(1000); 3047 mdelay(1);
3048 break; 3048 break;
3049 case 3: 3049 case 3:
3050 while (tmp--) { 3050 while (tmp--) {
@@ -3075,13 +3075,13 @@ static void combios_parse_pll_table(struct drm_device *dev, uint16_t offset)
3075 /*mclk_cntl |= 0x00001111;*//* ??? */ 3075 /*mclk_cntl |= 0x00001111;*//* ??? */
3076 WREG32_PLL(RADEON_MCLK_CNTL, 3076 WREG32_PLL(RADEON_MCLK_CNTL,
3077 mclk_cntl); 3077 mclk_cntl);
3078 udelay(10000); 3078 mdelay(10);
3079#endif 3079#endif
3080 WREG32_PLL 3080 WREG32_PLL
3081 (RADEON_CLK_PWRMGT_CNTL, 3081 (RADEON_CLK_PWRMGT_CNTL,
3082 tmp & 3082 tmp &
3083 ~RADEON_CG_NO1_DEBUG_0); 3083 ~RADEON_CG_NO1_DEBUG_0);
3084 udelay(10000); 3084 mdelay(10);
3085 } 3085 }
3086 break; 3086 break;
3087 default: 3087 default:
diff --git a/drivers/gpu/drm/radeon/radeon_i2c.c b/drivers/gpu/drm/radeon/radeon_i2c.c
index 85bcfc8923a..3edec1c198e 100644
--- a/drivers/gpu/drm/radeon/radeon_i2c.c
+++ b/drivers/gpu/drm/radeon/radeon_i2c.c
@@ -900,6 +900,10 @@ struct radeon_i2c_chan *radeon_i2c_create(struct drm_device *dev,
900 struct radeon_i2c_chan *i2c; 900 struct radeon_i2c_chan *i2c;
901 int ret; 901 int ret;
902 902
903 /* don't add the mm_i2c bus unless hw_i2c is enabled */
904 if (rec->mm_i2c && (radeon_hw_i2c == 0))
905 return NULL;
906
903 i2c = kzalloc(sizeof(struct radeon_i2c_chan), GFP_KERNEL); 907 i2c = kzalloc(sizeof(struct radeon_i2c_chan), GFP_KERNEL);
904 if (i2c == NULL) 908 if (i2c == NULL)
905 return NULL; 909 return NULL;
diff --git a/drivers/gpu/drm/radeon/radeon_legacy_encoders.c b/drivers/gpu/drm/radeon/radeon_legacy_encoders.c
index 2f46e0c8df5..42db254f6bb 100644
--- a/drivers/gpu/drm/radeon/radeon_legacy_encoders.c
+++ b/drivers/gpu/drm/radeon/radeon_legacy_encoders.c
@@ -88,7 +88,7 @@ static void radeon_legacy_lvds_update(struct drm_encoder *encoder, int mode)
88 lvds_pll_cntl = RREG32(RADEON_LVDS_PLL_CNTL); 88 lvds_pll_cntl = RREG32(RADEON_LVDS_PLL_CNTL);
89 lvds_pll_cntl |= RADEON_LVDS_PLL_EN; 89 lvds_pll_cntl |= RADEON_LVDS_PLL_EN;
90 WREG32(RADEON_LVDS_PLL_CNTL, lvds_pll_cntl); 90 WREG32(RADEON_LVDS_PLL_CNTL, lvds_pll_cntl);
91 udelay(1000); 91 mdelay(1);
92 92
93 lvds_pll_cntl = RREG32(RADEON_LVDS_PLL_CNTL); 93 lvds_pll_cntl = RREG32(RADEON_LVDS_PLL_CNTL);
94 lvds_pll_cntl &= ~RADEON_LVDS_PLL_RESET; 94 lvds_pll_cntl &= ~RADEON_LVDS_PLL_RESET;
@@ -101,7 +101,7 @@ static void radeon_legacy_lvds_update(struct drm_encoder *encoder, int mode)
101 (backlight_level << RADEON_LVDS_BL_MOD_LEVEL_SHIFT)); 101 (backlight_level << RADEON_LVDS_BL_MOD_LEVEL_SHIFT));
102 if (is_mac) 102 if (is_mac)
103 lvds_gen_cntl |= RADEON_LVDS_BL_MOD_EN; 103 lvds_gen_cntl |= RADEON_LVDS_BL_MOD_EN;
104 udelay(panel_pwr_delay * 1000); 104 mdelay(panel_pwr_delay);
105 WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl); 105 WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
106 break; 106 break;
107 case DRM_MODE_DPMS_STANDBY: 107 case DRM_MODE_DPMS_STANDBY:
@@ -118,10 +118,10 @@ static void radeon_legacy_lvds_update(struct drm_encoder *encoder, int mode)
118 WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl); 118 WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
119 lvds_gen_cntl &= ~(RADEON_LVDS_ON | RADEON_LVDS_BLON | RADEON_LVDS_EN | RADEON_LVDS_DIGON); 119 lvds_gen_cntl &= ~(RADEON_LVDS_ON | RADEON_LVDS_BLON | RADEON_LVDS_EN | RADEON_LVDS_DIGON);
120 } 120 }
121 udelay(panel_pwr_delay * 1000); 121 mdelay(panel_pwr_delay);
122 WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl); 122 WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
123 WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl); 123 WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl);
124 udelay(panel_pwr_delay * 1000); 124 mdelay(panel_pwr_delay);
125 break; 125 break;
126 } 126 }
127 127
@@ -656,7 +656,7 @@ static enum drm_connector_status radeon_legacy_primary_dac_detect(struct drm_enc
656 656
657 WREG32(RADEON_DAC_MACRO_CNTL, tmp); 657 WREG32(RADEON_DAC_MACRO_CNTL, tmp);
658 658
659 udelay(2000); 659 mdelay(2);
660 660
661 if (RREG32(RADEON_DAC_CNTL) & RADEON_DAC_CMP_OUTPUT) 661 if (RREG32(RADEON_DAC_CNTL) & RADEON_DAC_CMP_OUTPUT)
662 found = connector_status_connected; 662 found = connector_status_connected;
@@ -1499,7 +1499,7 @@ static enum drm_connector_status radeon_legacy_tv_dac_detect(struct drm_encoder
1499 tmp = dac_cntl2 | RADEON_DAC2_DAC2_CLK_SEL | RADEON_DAC2_CMP_EN; 1499 tmp = dac_cntl2 | RADEON_DAC2_DAC2_CLK_SEL | RADEON_DAC2_CMP_EN;
1500 WREG32(RADEON_DAC_CNTL2, tmp); 1500 WREG32(RADEON_DAC_CNTL2, tmp);
1501 1501
1502 udelay(10000); 1502 mdelay(10);
1503 1503
1504 if (ASIC_IS_R300(rdev)) { 1504 if (ASIC_IS_R300(rdev)) {
1505 if (RREG32(RADEON_DAC_CNTL2) & RADEON_DAC2_CMP_OUT_B) 1505 if (RREG32(RADEON_DAC_CNTL2) & RADEON_DAC2_CMP_OUT_B)
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-21 15:05:31 -0400