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path: root/drivers/gpu/drm/radeon/si.c
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Diffstat (limited to 'drivers/gpu/drm/radeon/si.c')
-rw-r--r--drivers/gpu/drm/radeon/si.c10
1 files changed, 9 insertions, 1 deletions
diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c
index 2b12cae52b2..7c3e330c7b5 100644
--- a/drivers/gpu/drm/radeon/si.c
+++ b/drivers/gpu/drm/radeon/si.c
@@ -1772,12 +1772,20 @@ void si_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
1772 1772
1773 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2); 1773 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2);
1774 } else { 1774 } else {
1775 u32 next_rptr;
1775 if (ring->rptr_save_reg) { 1776 if (ring->rptr_save_reg) {
1776 uint32_t next_rptr = ring->wptr + 3 + 4 + 8; 1777 next_rptr = ring->wptr + 3 + 4 + 8;
1777 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 1778 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1778 radeon_ring_write(ring, ((ring->rptr_save_reg - 1779 radeon_ring_write(ring, ((ring->rptr_save_reg -
1779 PACKET3_SET_CONFIG_REG_START) >> 2)); 1780 PACKET3_SET_CONFIG_REG_START) >> 2));
1780 radeon_ring_write(ring, next_rptr); 1781 radeon_ring_write(ring, next_rptr);
1782 } else if (rdev->wb.enabled) {
1783 next_rptr = ring->wptr + 5 + 4 + 8;
1784 radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
1785 radeon_ring_write(ring, (1 << 8));
1786 radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
1787 radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xffffffff);
1788 radeon_ring_write(ring, next_rptr);
1781 } 1789 }
1782 1790
1783 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); 1791 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);