diff options
Diffstat (limited to 'drivers/gpu/drm/radeon/radeon_encoders.c')
-rw-r--r-- | drivers/gpu/drm/radeon/radeon_encoders.c | 19 |
1 files changed, 14 insertions, 5 deletions
diff --git a/drivers/gpu/drm/radeon/radeon_encoders.c b/drivers/gpu/drm/radeon/radeon_encoders.c index c83ad890e4d..76835b0397a 100644 --- a/drivers/gpu/drm/radeon/radeon_encoders.c +++ b/drivers/gpu/drm/radeon/radeon_encoders.c | |||
@@ -712,7 +712,7 @@ atombios_get_encoder_mode(struct drm_encoder *encoder) | |||
712 | * - 2 DIG encoder blocks. | 712 | * - 2 DIG encoder blocks. |
713 | * DIG1/2 can drive UNIPHY0/1/2 link A or link B | 713 | * DIG1/2 can drive UNIPHY0/1/2 link A or link B |
714 | * | 714 | * |
715 | * DCE 4.0 | 715 | * DCE 4.0/5.0 |
716 | * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B). | 716 | * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B). |
717 | * Supports up to 6 digital outputs | 717 | * Supports up to 6 digital outputs |
718 | * - 6 DIG encoder blocks. | 718 | * - 6 DIG encoder blocks. |
@@ -829,6 +829,7 @@ union dig_transmitter_control { | |||
829 | DIG_TRANSMITTER_CONTROL_PS_ALLOCATION v1; | 829 | DIG_TRANSMITTER_CONTROL_PS_ALLOCATION v1; |
830 | DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 v2; | 830 | DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 v2; |
831 | DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 v3; | 831 | DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 v3; |
832 | DIG_TRANSMITTER_CONTROL_PARAMETERS_V4 v4; | ||
832 | }; | 833 | }; |
833 | 834 | ||
834 | void | 835 | void |
@@ -923,10 +924,18 @@ atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t | |||
923 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); | 924 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); |
924 | pll_id = radeon_crtc->pll_id; | 925 | pll_id = radeon_crtc->pll_id; |
925 | } | 926 | } |
926 | if (is_dp && rdev->clock.dp_extclk) | 927 | |
927 | args.v3.acConfig.ucRefClkSource = 2; /* external src */ | 928 | if (ASIC_IS_DCE5(rdev)) { |
928 | else | 929 | if (is_dp && rdev->clock.dp_extclk) |
929 | args.v3.acConfig.ucRefClkSource = pll_id; | 930 | args.v4.acConfig.ucRefClkSource = 3; /* external src */ |
931 | else | ||
932 | args.v4.acConfig.ucRefClkSource = pll_id; | ||
933 | } else { | ||
934 | if (is_dp && rdev->clock.dp_extclk) | ||
935 | args.v3.acConfig.ucRefClkSource = 2; /* external src */ | ||
936 | else | ||
937 | args.v3.acConfig.ucRefClkSource = pll_id; | ||
938 | } | ||
930 | 939 | ||
931 | switch (radeon_encoder->encoder_id) { | 940 | switch (radeon_encoder->encoder_id) { |
932 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: | 941 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: |