diff options
Diffstat (limited to 'drivers/gpu/drm/radeon/r600.c')
-rw-r--r-- | drivers/gpu/drm/radeon/r600.c | 201 |
1 files changed, 105 insertions, 96 deletions
diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c index bd2b3d087b1..eaf57cc7582 100644 --- a/drivers/gpu/drm/radeon/r600.c +++ b/drivers/gpu/drm/radeon/r600.c | |||
@@ -1344,7 +1344,7 @@ int r600_gpu_soft_reset(struct radeon_device *rdev) | |||
1344 | return 0; | 1344 | return 0; |
1345 | } | 1345 | } |
1346 | 1346 | ||
1347 | bool r600_gpu_is_lockup(struct radeon_device *rdev) | 1347 | bool r600_gpu_is_lockup(struct radeon_device *rdev, struct radeon_cp *cp) |
1348 | { | 1348 | { |
1349 | u32 srbm_status; | 1349 | u32 srbm_status; |
1350 | u32 grbm_status; | 1350 | u32 grbm_status; |
@@ -1361,19 +1361,19 @@ bool r600_gpu_is_lockup(struct radeon_device *rdev) | |||
1361 | grbm_status = RREG32(R_008010_GRBM_STATUS); | 1361 | grbm_status = RREG32(R_008010_GRBM_STATUS); |
1362 | grbm_status2 = RREG32(R_008014_GRBM_STATUS2); | 1362 | grbm_status2 = RREG32(R_008014_GRBM_STATUS2); |
1363 | if (!G_008010_GUI_ACTIVE(grbm_status)) { | 1363 | if (!G_008010_GUI_ACTIVE(grbm_status)) { |
1364 | r100_gpu_lockup_update(lockup, &rdev->cp); | 1364 | r100_gpu_lockup_update(lockup, cp); |
1365 | return false; | 1365 | return false; |
1366 | } | 1366 | } |
1367 | /* force CP activities */ | 1367 | /* force CP activities */ |
1368 | r = radeon_ring_lock(rdev, 2); | 1368 | r = radeon_ring_lock(rdev, cp, 2); |
1369 | if (!r) { | 1369 | if (!r) { |
1370 | /* PACKET2 NOP */ | 1370 | /* PACKET2 NOP */ |
1371 | radeon_ring_write(rdev, 0x80000000); | 1371 | radeon_ring_write(cp, 0x80000000); |
1372 | radeon_ring_write(rdev, 0x80000000); | 1372 | radeon_ring_write(cp, 0x80000000); |
1373 | radeon_ring_unlock_commit(rdev); | 1373 | radeon_ring_unlock_commit(rdev, cp); |
1374 | } | 1374 | } |
1375 | rdev->cp.rptr = RREG32(R600_CP_RB_RPTR); | 1375 | cp->rptr = RREG32(R600_CP_RB_RPTR); |
1376 | return r100_gpu_cp_is_lockup(rdev, lockup, &rdev->cp); | 1376 | return r100_gpu_cp_is_lockup(rdev, lockup, cp); |
1377 | } | 1377 | } |
1378 | 1378 | ||
1379 | int r600_asic_reset(struct radeon_device *rdev) | 1379 | int r600_asic_reset(struct radeon_device *rdev) |
@@ -2144,27 +2144,28 @@ static int r600_cp_load_microcode(struct radeon_device *rdev) | |||
2144 | 2144 | ||
2145 | int r600_cp_start(struct radeon_device *rdev) | 2145 | int r600_cp_start(struct radeon_device *rdev) |
2146 | { | 2146 | { |
2147 | struct radeon_cp *cp = &rdev->cp; | ||
2147 | int r; | 2148 | int r; |
2148 | uint32_t cp_me; | 2149 | uint32_t cp_me; |
2149 | 2150 | ||
2150 | r = radeon_ring_lock(rdev, 7); | 2151 | r = radeon_ring_lock(rdev, cp, 7); |
2151 | if (r) { | 2152 | if (r) { |
2152 | DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r); | 2153 | DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r); |
2153 | return r; | 2154 | return r; |
2154 | } | 2155 | } |
2155 | radeon_ring_write(rdev, PACKET3(PACKET3_ME_INITIALIZE, 5)); | 2156 | radeon_ring_write(cp, PACKET3(PACKET3_ME_INITIALIZE, 5)); |
2156 | radeon_ring_write(rdev, 0x1); | 2157 | radeon_ring_write(cp, 0x1); |
2157 | if (rdev->family >= CHIP_RV770) { | 2158 | if (rdev->family >= CHIP_RV770) { |
2158 | radeon_ring_write(rdev, 0x0); | 2159 | radeon_ring_write(cp, 0x0); |
2159 | radeon_ring_write(rdev, rdev->config.rv770.max_hw_contexts - 1); | 2160 | radeon_ring_write(cp, rdev->config.rv770.max_hw_contexts - 1); |
2160 | } else { | 2161 | } else { |
2161 | radeon_ring_write(rdev, 0x3); | 2162 | radeon_ring_write(cp, 0x3); |
2162 | radeon_ring_write(rdev, rdev->config.r600.max_hw_contexts - 1); | 2163 | radeon_ring_write(cp, rdev->config.r600.max_hw_contexts - 1); |
2163 | } | 2164 | } |
2164 | radeon_ring_write(rdev, PACKET3_ME_INITIALIZE_DEVICE_ID(1)); | 2165 | radeon_ring_write(cp, PACKET3_ME_INITIALIZE_DEVICE_ID(1)); |
2165 | radeon_ring_write(rdev, 0); | 2166 | radeon_ring_write(cp, 0); |
2166 | radeon_ring_write(rdev, 0); | 2167 | radeon_ring_write(cp, 0); |
2167 | radeon_ring_unlock_commit(rdev); | 2168 | radeon_ring_unlock_commit(rdev, cp); |
2168 | 2169 | ||
2169 | cp_me = 0xff; | 2170 | cp_me = 0xff; |
2170 | WREG32(R_0086D8_CP_ME_CNTL, cp_me); | 2171 | WREG32(R_0086D8_CP_ME_CNTL, cp_me); |
@@ -2173,6 +2174,7 @@ int r600_cp_start(struct radeon_device *rdev) | |||
2173 | 2174 | ||
2174 | int r600_cp_resume(struct radeon_device *rdev) | 2175 | int r600_cp_resume(struct radeon_device *rdev) |
2175 | { | 2176 | { |
2177 | struct radeon_cp *cp = &rdev->cp; | ||
2176 | u32 tmp; | 2178 | u32 tmp; |
2177 | u32 rb_bufsz; | 2179 | u32 rb_bufsz; |
2178 | int r; | 2180 | int r; |
@@ -2184,7 +2186,7 @@ int r600_cp_resume(struct radeon_device *rdev) | |||
2184 | WREG32(GRBM_SOFT_RESET, 0); | 2186 | WREG32(GRBM_SOFT_RESET, 0); |
2185 | 2187 | ||
2186 | /* Set ring buffer size */ | 2188 | /* Set ring buffer size */ |
2187 | rb_bufsz = drm_order(rdev->cp.ring_size / 8); | 2189 | rb_bufsz = drm_order(cp->ring_size / 8); |
2188 | tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz; | 2190 | tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz; |
2189 | #ifdef __BIG_ENDIAN | 2191 | #ifdef __BIG_ENDIAN |
2190 | tmp |= BUF_SWAP_32BIT; | 2192 | tmp |= BUF_SWAP_32BIT; |
@@ -2198,8 +2200,8 @@ int r600_cp_resume(struct radeon_device *rdev) | |||
2198 | /* Initialize the ring buffer's read and write pointers */ | 2200 | /* Initialize the ring buffer's read and write pointers */ |
2199 | WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA); | 2201 | WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA); |
2200 | WREG32(CP_RB_RPTR_WR, 0); | 2202 | WREG32(CP_RB_RPTR_WR, 0); |
2201 | rdev->cp.wptr = 0; | 2203 | cp->wptr = 0; |
2202 | WREG32(CP_RB_WPTR, rdev->cp.wptr); | 2204 | WREG32(CP_RB_WPTR, cp->wptr); |
2203 | 2205 | ||
2204 | /* set the wb address whether it's enabled or not */ | 2206 | /* set the wb address whether it's enabled or not */ |
2205 | WREG32(CP_RB_RPTR_ADDR, | 2207 | WREG32(CP_RB_RPTR_ADDR, |
@@ -2217,42 +2219,42 @@ int r600_cp_resume(struct radeon_device *rdev) | |||
2217 | mdelay(1); | 2219 | mdelay(1); |
2218 | WREG32(CP_RB_CNTL, tmp); | 2220 | WREG32(CP_RB_CNTL, tmp); |
2219 | 2221 | ||
2220 | WREG32(CP_RB_BASE, rdev->cp.gpu_addr >> 8); | 2222 | WREG32(CP_RB_BASE, cp->gpu_addr >> 8); |
2221 | WREG32(CP_DEBUG, (1 << 27) | (1 << 28)); | 2223 | WREG32(CP_DEBUG, (1 << 27) | (1 << 28)); |
2222 | 2224 | ||
2223 | rdev->cp.rptr = RREG32(CP_RB_RPTR); | 2225 | cp->rptr = RREG32(CP_RB_RPTR); |
2224 | 2226 | ||
2225 | r600_cp_start(rdev); | 2227 | r600_cp_start(rdev); |
2226 | rdev->cp.ready = true; | 2228 | cp->ready = true; |
2227 | r = radeon_ring_test(rdev); | 2229 | r = radeon_ring_test(rdev, cp); |
2228 | if (r) { | 2230 | if (r) { |
2229 | rdev->cp.ready = false; | 2231 | cp->ready = false; |
2230 | return r; | 2232 | return r; |
2231 | } | 2233 | } |
2232 | return 0; | 2234 | return 0; |
2233 | } | 2235 | } |
2234 | 2236 | ||
2235 | void r600_cp_commit(struct radeon_device *rdev) | 2237 | void r600_cp_commit(struct radeon_device *rdev, struct radeon_cp *cp) |
2236 | { | 2238 | { |
2237 | WREG32(CP_RB_WPTR, rdev->cp.wptr); | 2239 | WREG32(CP_RB_WPTR, cp->wptr); |
2238 | (void)RREG32(CP_RB_WPTR); | 2240 | (void)RREG32(CP_RB_WPTR); |
2239 | } | 2241 | } |
2240 | 2242 | ||
2241 | void r600_ring_init(struct radeon_device *rdev, unsigned ring_size) | 2243 | void r600_ring_init(struct radeon_device *rdev, struct radeon_cp *cp, unsigned ring_size) |
2242 | { | 2244 | { |
2243 | u32 rb_bufsz; | 2245 | u32 rb_bufsz; |
2244 | 2246 | ||
2245 | /* Align ring size */ | 2247 | /* Align ring size */ |
2246 | rb_bufsz = drm_order(ring_size / 8); | 2248 | rb_bufsz = drm_order(ring_size / 8); |
2247 | ring_size = (1 << (rb_bufsz + 1)) * 4; | 2249 | ring_size = (1 << (rb_bufsz + 1)) * 4; |
2248 | rdev->cp.ring_size = ring_size; | 2250 | cp->ring_size = ring_size; |
2249 | rdev->cp.align_mask = 16 - 1; | 2251 | cp->align_mask = 16 - 1; |
2250 | } | 2252 | } |
2251 | 2253 | ||
2252 | void r600_cp_fini(struct radeon_device *rdev) | 2254 | void r600_cp_fini(struct radeon_device *rdev) |
2253 | { | 2255 | { |
2254 | r600_cp_stop(rdev); | 2256 | r600_cp_stop(rdev); |
2255 | radeon_ring_fini(rdev); | 2257 | radeon_ring_fini(rdev, &rdev->cp); |
2256 | } | 2258 | } |
2257 | 2259 | ||
2258 | 2260 | ||
@@ -2271,7 +2273,7 @@ void r600_scratch_init(struct radeon_device *rdev) | |||
2271 | } | 2273 | } |
2272 | } | 2274 | } |
2273 | 2275 | ||
2274 | int r600_ring_test(struct radeon_device *rdev) | 2276 | int r600_ring_test(struct radeon_device *rdev, struct radeon_cp *cp) |
2275 | { | 2277 | { |
2276 | uint32_t scratch; | 2278 | uint32_t scratch; |
2277 | uint32_t tmp = 0; | 2279 | uint32_t tmp = 0; |
@@ -2284,16 +2286,16 @@ int r600_ring_test(struct radeon_device *rdev) | |||
2284 | return r; | 2286 | return r; |
2285 | } | 2287 | } |
2286 | WREG32(scratch, 0xCAFEDEAD); | 2288 | WREG32(scratch, 0xCAFEDEAD); |
2287 | r = radeon_ring_lock(rdev, 3); | 2289 | r = radeon_ring_lock(rdev, cp, 3); |
2288 | if (r) { | 2290 | if (r) { |
2289 | DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r); | 2291 | DRM_ERROR("radeon: cp failed to lock ring %p (%d).\n", cp, r); |
2290 | radeon_scratch_free(rdev, scratch); | 2292 | radeon_scratch_free(rdev, scratch); |
2291 | return r; | 2293 | return r; |
2292 | } | 2294 | } |
2293 | radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1)); | 2295 | radeon_ring_write(cp, PACKET3(PACKET3_SET_CONFIG_REG, 1)); |
2294 | radeon_ring_write(rdev, ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2)); | 2296 | radeon_ring_write(cp, ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2)); |
2295 | radeon_ring_write(rdev, 0xDEADBEEF); | 2297 | radeon_ring_write(cp, 0xDEADBEEF); |
2296 | radeon_ring_unlock_commit(rdev); | 2298 | radeon_ring_unlock_commit(rdev, cp); |
2297 | for (i = 0; i < rdev->usec_timeout; i++) { | 2299 | for (i = 0; i < rdev->usec_timeout; i++) { |
2298 | tmp = RREG32(scratch); | 2300 | tmp = RREG32(scratch); |
2299 | if (tmp == 0xDEADBEEF) | 2301 | if (tmp == 0xDEADBEEF) |
@@ -2301,10 +2303,10 @@ int r600_ring_test(struct radeon_device *rdev) | |||
2301 | DRM_UDELAY(1); | 2303 | DRM_UDELAY(1); |
2302 | } | 2304 | } |
2303 | if (i < rdev->usec_timeout) { | 2305 | if (i < rdev->usec_timeout) { |
2304 | DRM_INFO("ring test succeeded in %d usecs\n", i); | 2306 | DRM_INFO("ring test on %p succeeded in %d usecs\n", cp, i); |
2305 | } else { | 2307 | } else { |
2306 | DRM_ERROR("radeon: ring test failed (scratch(0x%04X)=0x%08X)\n", | 2308 | DRM_ERROR("radeon: ring %p test failed (scratch(0x%04X)=0x%08X)\n", |
2307 | scratch, tmp); | 2309 | cp, scratch, tmp); |
2308 | r = -EINVAL; | 2310 | r = -EINVAL; |
2309 | } | 2311 | } |
2310 | radeon_scratch_free(rdev, scratch); | 2312 | radeon_scratch_free(rdev, scratch); |
@@ -2314,59 +2316,62 @@ int r600_ring_test(struct radeon_device *rdev) | |||
2314 | void r600_fence_ring_emit(struct radeon_device *rdev, | 2316 | void r600_fence_ring_emit(struct radeon_device *rdev, |
2315 | struct radeon_fence *fence) | 2317 | struct radeon_fence *fence) |
2316 | { | 2318 | { |
2319 | struct radeon_cp *cp = &rdev->cp; | ||
2320 | |||
2317 | if (rdev->wb.use_event) { | 2321 | if (rdev->wb.use_event) { |
2318 | u64 addr = rdev->wb.gpu_addr + R600_WB_EVENT_OFFSET + | 2322 | u64 addr = rdev->wb.gpu_addr + R600_WB_EVENT_OFFSET + |
2319 | (u64)(rdev->fence_drv[fence->ring].scratch_reg - rdev->scratch.reg_base); | 2323 | (u64)(rdev->fence_drv[fence->ring].scratch_reg - rdev->scratch.reg_base); |
2320 | /* flush read cache over gart */ | 2324 | /* flush read cache over gart */ |
2321 | radeon_ring_write(rdev, PACKET3(PACKET3_SURFACE_SYNC, 3)); | 2325 | radeon_ring_write(cp, PACKET3(PACKET3_SURFACE_SYNC, 3)); |
2322 | radeon_ring_write(rdev, PACKET3_TC_ACTION_ENA | | 2326 | radeon_ring_write(cp, PACKET3_TC_ACTION_ENA | |
2323 | PACKET3_VC_ACTION_ENA | | 2327 | PACKET3_VC_ACTION_ENA | |
2324 | PACKET3_SH_ACTION_ENA); | 2328 | PACKET3_SH_ACTION_ENA); |
2325 | radeon_ring_write(rdev, 0xFFFFFFFF); | 2329 | radeon_ring_write(cp, 0xFFFFFFFF); |
2326 | radeon_ring_write(rdev, 0); | 2330 | radeon_ring_write(cp, 0); |
2327 | radeon_ring_write(rdev, 10); /* poll interval */ | 2331 | radeon_ring_write(cp, 10); /* poll interval */ |
2328 | /* EVENT_WRITE_EOP - flush caches, send int */ | 2332 | /* EVENT_WRITE_EOP - flush caches, send int */ |
2329 | radeon_ring_write(rdev, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); | 2333 | radeon_ring_write(cp, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); |
2330 | radeon_ring_write(rdev, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT_TS) | EVENT_INDEX(5)); | 2334 | radeon_ring_write(cp, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT_TS) | EVENT_INDEX(5)); |
2331 | radeon_ring_write(rdev, addr & 0xffffffff); | 2335 | radeon_ring_write(cp, addr & 0xffffffff); |
2332 | radeon_ring_write(rdev, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2)); | 2336 | radeon_ring_write(cp, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2)); |
2333 | radeon_ring_write(rdev, fence->seq); | 2337 | radeon_ring_write(cp, fence->seq); |
2334 | radeon_ring_write(rdev, 0); | 2338 | radeon_ring_write(cp, 0); |
2335 | } else { | 2339 | } else { |
2336 | /* flush read cache over gart */ | 2340 | /* flush read cache over gart */ |
2337 | radeon_ring_write(rdev, PACKET3(PACKET3_SURFACE_SYNC, 3)); | 2341 | radeon_ring_write(cp, PACKET3(PACKET3_SURFACE_SYNC, 3)); |
2338 | radeon_ring_write(rdev, PACKET3_TC_ACTION_ENA | | 2342 | radeon_ring_write(cp, PACKET3_TC_ACTION_ENA | |
2339 | PACKET3_VC_ACTION_ENA | | 2343 | PACKET3_VC_ACTION_ENA | |
2340 | PACKET3_SH_ACTION_ENA); | 2344 | PACKET3_SH_ACTION_ENA); |
2341 | radeon_ring_write(rdev, 0xFFFFFFFF); | 2345 | radeon_ring_write(cp, 0xFFFFFFFF); |
2342 | radeon_ring_write(rdev, 0); | 2346 | radeon_ring_write(cp, 0); |
2343 | radeon_ring_write(rdev, 10); /* poll interval */ | 2347 | radeon_ring_write(cp, 10); /* poll interval */ |
2344 | radeon_ring_write(rdev, PACKET3(PACKET3_EVENT_WRITE, 0)); | 2348 | radeon_ring_write(cp, PACKET3(PACKET3_EVENT_WRITE, 0)); |
2345 | radeon_ring_write(rdev, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT) | EVENT_INDEX(0)); | 2349 | radeon_ring_write(cp, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT) | EVENT_INDEX(0)); |
2346 | /* wait for 3D idle clean */ | 2350 | /* wait for 3D idle clean */ |
2347 | radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1)); | 2351 | radeon_ring_write(cp, PACKET3(PACKET3_SET_CONFIG_REG, 1)); |
2348 | radeon_ring_write(rdev, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2); | 2352 | radeon_ring_write(cp, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2); |
2349 | radeon_ring_write(rdev, WAIT_3D_IDLE_bit | WAIT_3D_IDLECLEAN_bit); | 2353 | radeon_ring_write(cp, WAIT_3D_IDLE_bit | WAIT_3D_IDLECLEAN_bit); |
2350 | /* Emit fence sequence & fire IRQ */ | 2354 | /* Emit fence sequence & fire IRQ */ |
2351 | radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1)); | 2355 | radeon_ring_write(cp, PACKET3(PACKET3_SET_CONFIG_REG, 1)); |
2352 | radeon_ring_write(rdev, ((rdev->fence_drv[fence->ring].scratch_reg - PACKET3_SET_CONFIG_REG_OFFSET) >> 2)); | 2356 | radeon_ring_write(cp, ((rdev->fence_drv[fence->ring].scratch_reg - PACKET3_SET_CONFIG_REG_OFFSET) >> 2)); |
2353 | radeon_ring_write(rdev, fence->seq); | 2357 | radeon_ring_write(cp, fence->seq); |
2354 | /* CP_INTERRUPT packet 3 no longer exists, use packet 0 */ | 2358 | /* CP_INTERRUPT packet 3 no longer exists, use packet 0 */ |
2355 | radeon_ring_write(rdev, PACKET0(CP_INT_STATUS, 0)); | 2359 | radeon_ring_write(cp, PACKET0(CP_INT_STATUS, 0)); |
2356 | radeon_ring_write(rdev, RB_INT_STAT); | 2360 | radeon_ring_write(cp, RB_INT_STAT); |
2357 | } | 2361 | } |
2358 | } | 2362 | } |
2359 | 2363 | ||
2360 | void r600_semaphore_ring_emit(struct radeon_device *rdev, | 2364 | void r600_semaphore_ring_emit(struct radeon_device *rdev, |
2365 | struct radeon_cp *cp, | ||
2361 | struct radeon_semaphore *semaphore, | 2366 | struct radeon_semaphore *semaphore, |
2362 | unsigned ring, bool emit_wait) | 2367 | bool emit_wait) |
2363 | { | 2368 | { |
2364 | uint64_t addr = semaphore->gpu_addr; | 2369 | uint64_t addr = semaphore->gpu_addr; |
2365 | unsigned sel = emit_wait ? PACKET3_SEM_SEL_WAIT : PACKET3_SEM_SEL_SIGNAL; | 2370 | unsigned sel = emit_wait ? PACKET3_SEM_SEL_WAIT : PACKET3_SEM_SEL_SIGNAL; |
2366 | 2371 | ||
2367 | radeon_ring_write(rdev, PACKET3(PACKET3_MEM_SEMAPHORE, 1)); | 2372 | radeon_ring_write(cp, PACKET3(PACKET3_MEM_SEMAPHORE, 1)); |
2368 | radeon_ring_write(rdev, addr & 0xffffffff); | 2373 | radeon_ring_write(cp, addr & 0xffffffff); |
2369 | radeon_ring_write(rdev, (upper_32_bits(addr) & 0xff) | sel); | 2374 | radeon_ring_write(cp, (upper_32_bits(addr) & 0xff) | sel); |
2370 | } | 2375 | } |
2371 | 2376 | ||
2372 | int r600_copy_blit(struct radeon_device *rdev, | 2377 | int r600_copy_blit(struct radeon_device *rdev, |
@@ -2421,6 +2426,7 @@ void r600_clear_surface_reg(struct radeon_device *rdev, int reg) | |||
2421 | 2426 | ||
2422 | int r600_startup(struct radeon_device *rdev) | 2427 | int r600_startup(struct radeon_device *rdev) |
2423 | { | 2428 | { |
2429 | struct radeon_cp *cp = &rdev->cp; | ||
2424 | int r; | 2430 | int r; |
2425 | 2431 | ||
2426 | /* enable pcie gen2 link */ | 2432 | /* enable pcie gen2 link */ |
@@ -2468,7 +2474,7 @@ int r600_startup(struct radeon_device *rdev) | |||
2468 | } | 2474 | } |
2469 | r600_irq_set(rdev); | 2475 | r600_irq_set(rdev); |
2470 | 2476 | ||
2471 | r = radeon_ring_init(rdev, rdev->cp.ring_size); | 2477 | r = radeon_ring_init(rdev, cp, cp->ring_size); |
2472 | if (r) | 2478 | if (r) |
2473 | return r; | 2479 | return r; |
2474 | r = r600_cp_load_microcode(rdev); | 2480 | r = r600_cp_load_microcode(rdev); |
@@ -2512,7 +2518,7 @@ int r600_resume(struct radeon_device *rdev) | |||
2512 | return r; | 2518 | return r; |
2513 | } | 2519 | } |
2514 | 2520 | ||
2515 | r = r600_ib_test(rdev); | 2521 | r = r600_ib_test(rdev, RADEON_RING_TYPE_GFX_INDEX); |
2516 | if (r) { | 2522 | if (r) { |
2517 | DRM_ERROR("radeon: failed testing IB (%d).\n", r); | 2523 | DRM_ERROR("radeon: failed testing IB (%d).\n", r); |
2518 | return r; | 2524 | return r; |
@@ -2608,7 +2614,7 @@ int r600_init(struct radeon_device *rdev) | |||
2608 | return r; | 2614 | return r; |
2609 | 2615 | ||
2610 | rdev->cp.ring_obj = NULL; | 2616 | rdev->cp.ring_obj = NULL; |
2611 | r600_ring_init(rdev, 1024 * 1024); | 2617 | r600_ring_init(rdev, &rdev->cp, 1024 * 1024); |
2612 | 2618 | ||
2613 | rdev->ih.ring_obj = NULL; | 2619 | rdev->ih.ring_obj = NULL; |
2614 | r600_ih_ring_init(rdev, 64 * 1024); | 2620 | r600_ih_ring_init(rdev, 64 * 1024); |
@@ -2634,7 +2640,7 @@ int r600_init(struct radeon_device *rdev) | |||
2634 | dev_err(rdev->dev, "IB initialization failed (%d).\n", r); | 2640 | dev_err(rdev->dev, "IB initialization failed (%d).\n", r); |
2635 | rdev->accel_working = false; | 2641 | rdev->accel_working = false; |
2636 | } else { | 2642 | } else { |
2637 | r = r600_ib_test(rdev); | 2643 | r = r600_ib_test(rdev, RADEON_RING_TYPE_GFX_INDEX); |
2638 | if (r) { | 2644 | if (r) { |
2639 | dev_err(rdev->dev, "IB test failed (%d).\n", r); | 2645 | dev_err(rdev->dev, "IB test failed (%d).\n", r); |
2640 | rdev->accel_working = false; | 2646 | rdev->accel_working = false; |
@@ -2675,18 +2681,20 @@ void r600_fini(struct radeon_device *rdev) | |||
2675 | */ | 2681 | */ |
2676 | void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib) | 2682 | void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib) |
2677 | { | 2683 | { |
2684 | struct radeon_cp *cp = &rdev->cp; | ||
2685 | |||
2678 | /* FIXME: implement */ | 2686 | /* FIXME: implement */ |
2679 | radeon_ring_write(rdev, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); | 2687 | radeon_ring_write(cp, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); |
2680 | radeon_ring_write(rdev, | 2688 | radeon_ring_write(cp, |
2681 | #ifdef __BIG_ENDIAN | 2689 | #ifdef __BIG_ENDIAN |
2682 | (2 << 0) | | 2690 | (2 << 0) | |
2683 | #endif | 2691 | #endif |
2684 | (ib->gpu_addr & 0xFFFFFFFC)); | 2692 | (ib->gpu_addr & 0xFFFFFFFC)); |
2685 | radeon_ring_write(rdev, upper_32_bits(ib->gpu_addr) & 0xFF); | 2693 | radeon_ring_write(cp, upper_32_bits(ib->gpu_addr) & 0xFF); |
2686 | radeon_ring_write(rdev, ib->length_dw); | 2694 | radeon_ring_write(cp, ib->length_dw); |
2687 | } | 2695 | } |
2688 | 2696 | ||
2689 | int r600_ib_test(struct radeon_device *rdev) | 2697 | int r600_ib_test(struct radeon_device *rdev, int ring) |
2690 | { | 2698 | { |
2691 | struct radeon_ib *ib; | 2699 | struct radeon_ib *ib; |
2692 | uint32_t scratch; | 2700 | uint32_t scratch; |
@@ -2700,7 +2708,7 @@ int r600_ib_test(struct radeon_device *rdev) | |||
2700 | return r; | 2708 | return r; |
2701 | } | 2709 | } |
2702 | WREG32(scratch, 0xCAFEDEAD); | 2710 | WREG32(scratch, 0xCAFEDEAD); |
2703 | r = radeon_ib_get(rdev, &ib); | 2711 | r = radeon_ib_get(rdev, ring, &ib); |
2704 | if (r) { | 2712 | if (r) { |
2705 | DRM_ERROR("radeon: failed to get ib (%d).\n", r); | 2713 | DRM_ERROR("radeon: failed to get ib (%d).\n", r); |
2706 | return r; | 2714 | return r; |
@@ -2741,7 +2749,7 @@ int r600_ib_test(struct radeon_device *rdev) | |||
2741 | DRM_UDELAY(1); | 2749 | DRM_UDELAY(1); |
2742 | } | 2750 | } |
2743 | if (i < rdev->usec_timeout) { | 2751 | if (i < rdev->usec_timeout) { |
2744 | DRM_INFO("ib test succeeded in %u usecs\n", i); | 2752 | DRM_INFO("ib test on ring %d succeeded in %u usecs\n", ib->fence->ring, i); |
2745 | } else { | 2753 | } else { |
2746 | DRM_ERROR("radeon: ib test failed (scratch(0x%04X)=0x%08X)\n", | 2754 | DRM_ERROR("radeon: ib test failed (scratch(0x%04X)=0x%08X)\n", |
2747 | scratch, tmp); | 2755 | scratch, tmp); |
@@ -3514,21 +3522,22 @@ static int r600_debugfs_cp_ring_info(struct seq_file *m, void *data) | |||
3514 | struct drm_info_node *node = (struct drm_info_node *) m->private; | 3522 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
3515 | struct drm_device *dev = node->minor->dev; | 3523 | struct drm_device *dev = node->minor->dev; |
3516 | struct radeon_device *rdev = dev->dev_private; | 3524 | struct radeon_device *rdev = dev->dev_private; |
3525 | struct radeon_cp *cp = &rdev->cp; | ||
3517 | unsigned count, i, j; | 3526 | unsigned count, i, j; |
3518 | 3527 | ||
3519 | radeon_ring_free_size(rdev); | 3528 | radeon_ring_free_size(rdev, cp); |
3520 | count = (rdev->cp.ring_size / 4) - rdev->cp.ring_free_dw; | 3529 | count = (cp->ring_size / 4) - cp->ring_free_dw; |
3521 | seq_printf(m, "CP_STAT 0x%08x\n", RREG32(CP_STAT)); | 3530 | seq_printf(m, "CP_STAT 0x%08x\n", RREG32(CP_STAT)); |
3522 | seq_printf(m, "CP_RB_WPTR 0x%08x\n", RREG32(CP_RB_WPTR)); | 3531 | seq_printf(m, "CP_RB_WPTR 0x%08x\n", RREG32(CP_RB_WPTR)); |
3523 | seq_printf(m, "CP_RB_RPTR 0x%08x\n", RREG32(CP_RB_RPTR)); | 3532 | seq_printf(m, "CP_RB_RPTR 0x%08x\n", RREG32(CP_RB_RPTR)); |
3524 | seq_printf(m, "driver's copy of the CP_RB_WPTR 0x%08x\n", rdev->cp.wptr); | 3533 | seq_printf(m, "driver's copy of the CP_RB_WPTR 0x%08x\n", cp->wptr); |
3525 | seq_printf(m, "driver's copy of the CP_RB_RPTR 0x%08x\n", rdev->cp.rptr); | 3534 | seq_printf(m, "driver's copy of the CP_RB_RPTR 0x%08x\n", cp->rptr); |
3526 | seq_printf(m, "%u free dwords in ring\n", rdev->cp.ring_free_dw); | 3535 | seq_printf(m, "%u free dwords in ring\n", cp->ring_free_dw); |
3527 | seq_printf(m, "%u dwords in ring\n", count); | 3536 | seq_printf(m, "%u dwords in ring\n", count); |
3528 | i = rdev->cp.rptr; | 3537 | i = cp->rptr; |
3529 | for (j = 0; j <= count; j++) { | 3538 | for (j = 0; j <= count; j++) { |
3530 | seq_printf(m, "r[%04d]=0x%08x\n", i, rdev->cp.ring[i]); | 3539 | seq_printf(m, "r[%04d]=0x%08x\n", i, cp->ring[i]); |
3531 | i = (i + 1) & rdev->cp.ptr_mask; | 3540 | i = (i + 1) & cp->ptr_mask; |
3532 | } | 3541 | } |
3533 | return 0; | 3542 | return 0; |
3534 | } | 3543 | } |