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path: root/drivers/gpu/drm/radeon/r200.c
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Diffstat (limited to 'drivers/gpu/drm/radeon/r200.c')
-rw-r--r--drivers/gpu/drm/radeon/r200.c21
1 files changed, 11 insertions, 10 deletions
diff --git a/drivers/gpu/drm/radeon/r200.c b/drivers/gpu/drm/radeon/r200.c
index a1f3ba063c2..d84e633f72f 100644
--- a/drivers/gpu/drm/radeon/r200.c
+++ b/drivers/gpu/drm/radeon/r200.c
@@ -87,6 +87,7 @@ int r200_copy_dma(struct radeon_device *rdev,
87 unsigned num_gpu_pages, 87 unsigned num_gpu_pages,
88 struct radeon_fence *fence) 88 struct radeon_fence *fence)
89{ 89{
90 struct radeon_cp *cp = &rdev->cp;
90 uint32_t size; 91 uint32_t size;
91 uint32_t cur_size; 92 uint32_t cur_size;
92 int i, num_loops; 93 int i, num_loops;
@@ -95,33 +96,33 @@ int r200_copy_dma(struct radeon_device *rdev,
95 /* radeon pitch is /64 */ 96 /* radeon pitch is /64 */
96 size = num_gpu_pages << RADEON_GPU_PAGE_SHIFT; 97 size = num_gpu_pages << RADEON_GPU_PAGE_SHIFT;
97 num_loops = DIV_ROUND_UP(size, 0x1FFFFF); 98 num_loops = DIV_ROUND_UP(size, 0x1FFFFF);
98 r = radeon_ring_lock(rdev, num_loops * 4 + 64); 99 r = radeon_ring_lock(rdev, cp, num_loops * 4 + 64);
99 if (r) { 100 if (r) {
100 DRM_ERROR("radeon: moving bo (%d).\n", r); 101 DRM_ERROR("radeon: moving bo (%d).\n", r);
101 return r; 102 return r;
102 } 103 }
103 /* Must wait for 2D idle & clean before DMA or hangs might happen */ 104 /* Must wait for 2D idle & clean before DMA or hangs might happen */
104 radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0)); 105 radeon_ring_write(cp, PACKET0(RADEON_WAIT_UNTIL, 0));
105 radeon_ring_write(rdev, (1 << 16)); 106 radeon_ring_write(cp, (1 << 16));
106 for (i = 0; i < num_loops; i++) { 107 for (i = 0; i < num_loops; i++) {
107 cur_size = size; 108 cur_size = size;
108 if (cur_size > 0x1FFFFF) { 109 if (cur_size > 0x1FFFFF) {
109 cur_size = 0x1FFFFF; 110 cur_size = 0x1FFFFF;
110 } 111 }
111 size -= cur_size; 112 size -= cur_size;
112 radeon_ring_write(rdev, PACKET0(0x720, 2)); 113 radeon_ring_write(cp, PACKET0(0x720, 2));
113 radeon_ring_write(rdev, src_offset); 114 radeon_ring_write(cp, src_offset);
114 radeon_ring_write(rdev, dst_offset); 115 radeon_ring_write(cp, dst_offset);
115 radeon_ring_write(rdev, cur_size | (1 << 31) | (1 << 30)); 116 radeon_ring_write(cp, cur_size | (1 << 31) | (1 << 30));
116 src_offset += cur_size; 117 src_offset += cur_size;
117 dst_offset += cur_size; 118 dst_offset += cur_size;
118 } 119 }
119 radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0)); 120 radeon_ring_write(cp, PACKET0(RADEON_WAIT_UNTIL, 0));
120 radeon_ring_write(rdev, RADEON_WAIT_DMA_GUI_IDLE); 121 radeon_ring_write(cp, RADEON_WAIT_DMA_GUI_IDLE);
121 if (fence) { 122 if (fence) {
122 r = radeon_fence_emit(rdev, fence); 123 r = radeon_fence_emit(rdev, fence);
123 } 124 }
124 radeon_ring_unlock_commit(rdev); 125 radeon_ring_unlock_commit(rdev, cp);
125 return r; 126 return r;
126} 127}
127 128