diff options
Diffstat (limited to 'drivers/gpu/drm/radeon/evergreen_blit_kms.c')
-rw-r--r-- | drivers/gpu/drm/radeon/evergreen_blit_kms.c | 242 |
1 files changed, 125 insertions, 117 deletions
diff --git a/drivers/gpu/drm/radeon/evergreen_blit_kms.c b/drivers/gpu/drm/radeon/evergreen_blit_kms.c index 914e5af8416..75d0a6f0a39 100644 --- a/drivers/gpu/drm/radeon/evergreen_blit_kms.c +++ b/drivers/gpu/drm/radeon/evergreen_blit_kms.c | |||
@@ -49,6 +49,7 @@ static void | |||
49 | set_render_target(struct radeon_device *rdev, int format, | 49 | set_render_target(struct radeon_device *rdev, int format, |
50 | int w, int h, u64 gpu_addr) | 50 | int w, int h, u64 gpu_addr) |
51 | { | 51 | { |
52 | struct radeon_cp *cp = &rdev->cp; | ||
52 | u32 cb_color_info; | 53 | u32 cb_color_info; |
53 | int pitch, slice; | 54 | int pitch, slice; |
54 | 55 | ||
@@ -62,23 +63,23 @@ set_render_target(struct radeon_device *rdev, int format, | |||
62 | pitch = (w / 8) - 1; | 63 | pitch = (w / 8) - 1; |
63 | slice = ((w * h) / 64) - 1; | 64 | slice = ((w * h) / 64) - 1; |
64 | 65 | ||
65 | radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 15)); | 66 | radeon_ring_write(cp, PACKET3(PACKET3_SET_CONTEXT_REG, 15)); |
66 | radeon_ring_write(rdev, (CB_COLOR0_BASE - PACKET3_SET_CONTEXT_REG_START) >> 2); | 67 | radeon_ring_write(cp, (CB_COLOR0_BASE - PACKET3_SET_CONTEXT_REG_START) >> 2); |
67 | radeon_ring_write(rdev, gpu_addr >> 8); | 68 | radeon_ring_write(cp, gpu_addr >> 8); |
68 | radeon_ring_write(rdev, pitch); | 69 | radeon_ring_write(cp, pitch); |
69 | radeon_ring_write(rdev, slice); | 70 | radeon_ring_write(cp, slice); |
70 | radeon_ring_write(rdev, 0); | 71 | radeon_ring_write(cp, 0); |
71 | radeon_ring_write(rdev, cb_color_info); | 72 | radeon_ring_write(cp, cb_color_info); |
72 | radeon_ring_write(rdev, 0); | 73 | radeon_ring_write(cp, 0); |
73 | radeon_ring_write(rdev, (w - 1) | ((h - 1) << 16)); | 74 | radeon_ring_write(cp, (w - 1) | ((h - 1) << 16)); |
74 | radeon_ring_write(rdev, 0); | 75 | radeon_ring_write(cp, 0); |
75 | radeon_ring_write(rdev, 0); | 76 | radeon_ring_write(cp, 0); |
76 | radeon_ring_write(rdev, 0); | 77 | radeon_ring_write(cp, 0); |
77 | radeon_ring_write(rdev, 0); | 78 | radeon_ring_write(cp, 0); |
78 | radeon_ring_write(rdev, 0); | 79 | radeon_ring_write(cp, 0); |
79 | radeon_ring_write(rdev, 0); | 80 | radeon_ring_write(cp, 0); |
80 | radeon_ring_write(rdev, 0); | 81 | radeon_ring_write(cp, 0); |
81 | radeon_ring_write(rdev, 0); | 82 | radeon_ring_write(cp, 0); |
82 | } | 83 | } |
83 | 84 | ||
84 | /* emits 5dw */ | 85 | /* emits 5dw */ |
@@ -87,6 +88,7 @@ cp_set_surface_sync(struct radeon_device *rdev, | |||
87 | u32 sync_type, u32 size, | 88 | u32 sync_type, u32 size, |
88 | u64 mc_addr) | 89 | u64 mc_addr) |
89 | { | 90 | { |
91 | struct radeon_cp *cp = &rdev->cp; | ||
90 | u32 cp_coher_size; | 92 | u32 cp_coher_size; |
91 | 93 | ||
92 | if (size == 0xffffffff) | 94 | if (size == 0xffffffff) |
@@ -99,39 +101,40 @@ cp_set_surface_sync(struct radeon_device *rdev, | |||
99 | * to the RB directly. For IBs, the CP programs this as part of the | 101 | * to the RB directly. For IBs, the CP programs this as part of the |
100 | * surface_sync packet. | 102 | * surface_sync packet. |
101 | */ | 103 | */ |
102 | radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1)); | 104 | radeon_ring_write(cp, PACKET3(PACKET3_SET_CONFIG_REG, 1)); |
103 | radeon_ring_write(rdev, (0x85e8 - PACKET3_SET_CONFIG_REG_START) >> 2); | 105 | radeon_ring_write(cp, (0x85e8 - PACKET3_SET_CONFIG_REG_START) >> 2); |
104 | radeon_ring_write(rdev, 0); /* CP_COHER_CNTL2 */ | 106 | radeon_ring_write(cp, 0); /* CP_COHER_CNTL2 */ |
105 | } | 107 | } |
106 | radeon_ring_write(rdev, PACKET3(PACKET3_SURFACE_SYNC, 3)); | 108 | radeon_ring_write(cp, PACKET3(PACKET3_SURFACE_SYNC, 3)); |
107 | radeon_ring_write(rdev, sync_type); | 109 | radeon_ring_write(cp, sync_type); |
108 | radeon_ring_write(rdev, cp_coher_size); | 110 | radeon_ring_write(cp, cp_coher_size); |
109 | radeon_ring_write(rdev, mc_addr >> 8); | 111 | radeon_ring_write(cp, mc_addr >> 8); |
110 | radeon_ring_write(rdev, 10); /* poll interval */ | 112 | radeon_ring_write(cp, 10); /* poll interval */ |
111 | } | 113 | } |
112 | 114 | ||
113 | /* emits 11dw + 1 surface sync = 16dw */ | 115 | /* emits 11dw + 1 surface sync = 16dw */ |
114 | static void | 116 | static void |
115 | set_shaders(struct radeon_device *rdev) | 117 | set_shaders(struct radeon_device *rdev) |
116 | { | 118 | { |
119 | struct radeon_cp *cp = &rdev->cp; | ||
117 | u64 gpu_addr; | 120 | u64 gpu_addr; |
118 | 121 | ||
119 | /* VS */ | 122 | /* VS */ |
120 | gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.vs_offset; | 123 | gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.vs_offset; |
121 | radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 3)); | 124 | radeon_ring_write(cp, PACKET3(PACKET3_SET_CONTEXT_REG, 3)); |
122 | radeon_ring_write(rdev, (SQ_PGM_START_VS - PACKET3_SET_CONTEXT_REG_START) >> 2); | 125 | radeon_ring_write(cp, (SQ_PGM_START_VS - PACKET3_SET_CONTEXT_REG_START) >> 2); |
123 | radeon_ring_write(rdev, gpu_addr >> 8); | 126 | radeon_ring_write(cp, gpu_addr >> 8); |
124 | radeon_ring_write(rdev, 2); | 127 | radeon_ring_write(cp, 2); |
125 | radeon_ring_write(rdev, 0); | 128 | radeon_ring_write(cp, 0); |
126 | 129 | ||
127 | /* PS */ | 130 | /* PS */ |
128 | gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.ps_offset; | 131 | gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.ps_offset; |
129 | radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 4)); | 132 | radeon_ring_write(cp, PACKET3(PACKET3_SET_CONTEXT_REG, 4)); |
130 | radeon_ring_write(rdev, (SQ_PGM_START_PS - PACKET3_SET_CONTEXT_REG_START) >> 2); | 133 | radeon_ring_write(cp, (SQ_PGM_START_PS - PACKET3_SET_CONTEXT_REG_START) >> 2); |
131 | radeon_ring_write(rdev, gpu_addr >> 8); | 134 | radeon_ring_write(cp, gpu_addr >> 8); |
132 | radeon_ring_write(rdev, 1); | 135 | radeon_ring_write(cp, 1); |
133 | radeon_ring_write(rdev, 0); | 136 | radeon_ring_write(cp, 0); |
134 | radeon_ring_write(rdev, 2); | 137 | radeon_ring_write(cp, 2); |
135 | 138 | ||
136 | gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.vs_offset; | 139 | gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.vs_offset; |
137 | cp_set_surface_sync(rdev, PACKET3_SH_ACTION_ENA, 512, gpu_addr); | 140 | cp_set_surface_sync(rdev, PACKET3_SH_ACTION_ENA, 512, gpu_addr); |
@@ -141,6 +144,7 @@ set_shaders(struct radeon_device *rdev) | |||
141 | static void | 144 | static void |
142 | set_vtx_resource(struct radeon_device *rdev, u64 gpu_addr) | 145 | set_vtx_resource(struct radeon_device *rdev, u64 gpu_addr) |
143 | { | 146 | { |
147 | struct radeon_cp *cp = &rdev->cp; | ||
144 | u32 sq_vtx_constant_word2, sq_vtx_constant_word3; | 148 | u32 sq_vtx_constant_word2, sq_vtx_constant_word3; |
145 | 149 | ||
146 | /* high addr, stride */ | 150 | /* high addr, stride */ |
@@ -155,16 +159,16 @@ set_vtx_resource(struct radeon_device *rdev, u64 gpu_addr) | |||
155 | SQ_VTCX_SEL_Z(SQ_SEL_Z) | | 159 | SQ_VTCX_SEL_Z(SQ_SEL_Z) | |
156 | SQ_VTCX_SEL_W(SQ_SEL_W); | 160 | SQ_VTCX_SEL_W(SQ_SEL_W); |
157 | 161 | ||
158 | radeon_ring_write(rdev, PACKET3(PACKET3_SET_RESOURCE, 8)); | 162 | radeon_ring_write(cp, PACKET3(PACKET3_SET_RESOURCE, 8)); |
159 | radeon_ring_write(rdev, 0x580); | 163 | radeon_ring_write(cp, 0x580); |
160 | radeon_ring_write(rdev, gpu_addr & 0xffffffff); | 164 | radeon_ring_write(cp, gpu_addr & 0xffffffff); |
161 | radeon_ring_write(rdev, 48 - 1); /* size */ | 165 | radeon_ring_write(cp, 48 - 1); /* size */ |
162 | radeon_ring_write(rdev, sq_vtx_constant_word2); | 166 | radeon_ring_write(cp, sq_vtx_constant_word2); |
163 | radeon_ring_write(rdev, sq_vtx_constant_word3); | 167 | radeon_ring_write(cp, sq_vtx_constant_word3); |
164 | radeon_ring_write(rdev, 0); | 168 | radeon_ring_write(cp, 0); |
165 | radeon_ring_write(rdev, 0); | 169 | radeon_ring_write(cp, 0); |
166 | radeon_ring_write(rdev, 0); | 170 | radeon_ring_write(cp, 0); |
167 | radeon_ring_write(rdev, S__SQ_CONSTANT_TYPE(SQ_TEX_VTX_VALID_BUFFER)); | 171 | radeon_ring_write(cp, S__SQ_CONSTANT_TYPE(SQ_TEX_VTX_VALID_BUFFER)); |
168 | 172 | ||
169 | if ((rdev->family == CHIP_CEDAR) || | 173 | if ((rdev->family == CHIP_CEDAR) || |
170 | (rdev->family == CHIP_PALM) || | 174 | (rdev->family == CHIP_PALM) || |
@@ -185,6 +189,7 @@ set_tex_resource(struct radeon_device *rdev, | |||
185 | int format, int w, int h, int pitch, | 189 | int format, int w, int h, int pitch, |
186 | u64 gpu_addr, u32 size) | 190 | u64 gpu_addr, u32 size) |
187 | { | 191 | { |
192 | struct radeon_cp *cp = &rdev->cp; | ||
188 | u32 sq_tex_resource_word0, sq_tex_resource_word1; | 193 | u32 sq_tex_resource_word0, sq_tex_resource_word1; |
189 | u32 sq_tex_resource_word4, sq_tex_resource_word7; | 194 | u32 sq_tex_resource_word4, sq_tex_resource_word7; |
190 | 195 | ||
@@ -208,16 +213,16 @@ set_tex_resource(struct radeon_device *rdev, | |||
208 | cp_set_surface_sync(rdev, | 213 | cp_set_surface_sync(rdev, |
209 | PACKET3_TC_ACTION_ENA, size, gpu_addr); | 214 | PACKET3_TC_ACTION_ENA, size, gpu_addr); |
210 | 215 | ||
211 | radeon_ring_write(rdev, PACKET3(PACKET3_SET_RESOURCE, 8)); | 216 | radeon_ring_write(cp, PACKET3(PACKET3_SET_RESOURCE, 8)); |
212 | radeon_ring_write(rdev, 0); | 217 | radeon_ring_write(cp, 0); |
213 | radeon_ring_write(rdev, sq_tex_resource_word0); | 218 | radeon_ring_write(cp, sq_tex_resource_word0); |
214 | radeon_ring_write(rdev, sq_tex_resource_word1); | 219 | radeon_ring_write(cp, sq_tex_resource_word1); |
215 | radeon_ring_write(rdev, gpu_addr >> 8); | 220 | radeon_ring_write(cp, gpu_addr >> 8); |
216 | radeon_ring_write(rdev, gpu_addr >> 8); | 221 | radeon_ring_write(cp, gpu_addr >> 8); |
217 | radeon_ring_write(rdev, sq_tex_resource_word4); | 222 | radeon_ring_write(cp, sq_tex_resource_word4); |
218 | radeon_ring_write(rdev, 0); | 223 | radeon_ring_write(cp, 0); |
219 | radeon_ring_write(rdev, 0); | 224 | radeon_ring_write(cp, 0); |
220 | radeon_ring_write(rdev, sq_tex_resource_word7); | 225 | radeon_ring_write(cp, sq_tex_resource_word7); |
221 | } | 226 | } |
222 | 227 | ||
223 | /* emits 12 */ | 228 | /* emits 12 */ |
@@ -225,6 +230,7 @@ static void | |||
225 | set_scissors(struct radeon_device *rdev, int x1, int y1, | 230 | set_scissors(struct radeon_device *rdev, int x1, int y1, |
226 | int x2, int y2) | 231 | int x2, int y2) |
227 | { | 232 | { |
233 | struct radeon_cp *cp = &rdev->cp; | ||
228 | /* workaround some hw bugs */ | 234 | /* workaround some hw bugs */ |
229 | if (x2 == 0) | 235 | if (x2 == 0) |
230 | x1 = 1; | 236 | x1 = 1; |
@@ -235,43 +241,44 @@ set_scissors(struct radeon_device *rdev, int x1, int y1, | |||
235 | x2 = 2; | 241 | x2 = 2; |
236 | } | 242 | } |
237 | 243 | ||
238 | radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 2)); | 244 | radeon_ring_write(cp, PACKET3(PACKET3_SET_CONTEXT_REG, 2)); |
239 | radeon_ring_write(rdev, (PA_SC_SCREEN_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_START) >> 2); | 245 | radeon_ring_write(cp, (PA_SC_SCREEN_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_START) >> 2); |
240 | radeon_ring_write(rdev, (x1 << 0) | (y1 << 16)); | 246 | radeon_ring_write(cp, (x1 << 0) | (y1 << 16)); |
241 | radeon_ring_write(rdev, (x2 << 0) | (y2 << 16)); | 247 | radeon_ring_write(cp, (x2 << 0) | (y2 << 16)); |
242 | 248 | ||
243 | radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 2)); | 249 | radeon_ring_write(cp, PACKET3(PACKET3_SET_CONTEXT_REG, 2)); |
244 | radeon_ring_write(rdev, (PA_SC_GENERIC_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_START) >> 2); | 250 | radeon_ring_write(cp, (PA_SC_GENERIC_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_START) >> 2); |
245 | radeon_ring_write(rdev, (x1 << 0) | (y1 << 16) | (1 << 31)); | 251 | radeon_ring_write(cp, (x1 << 0) | (y1 << 16) | (1 << 31)); |
246 | radeon_ring_write(rdev, (x2 << 0) | (y2 << 16)); | 252 | radeon_ring_write(cp, (x2 << 0) | (y2 << 16)); |
247 | 253 | ||
248 | radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 2)); | 254 | radeon_ring_write(cp, PACKET3(PACKET3_SET_CONTEXT_REG, 2)); |
249 | radeon_ring_write(rdev, (PA_SC_WINDOW_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_START) >> 2); | 255 | radeon_ring_write(cp, (PA_SC_WINDOW_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_START) >> 2); |
250 | radeon_ring_write(rdev, (x1 << 0) | (y1 << 16) | (1 << 31)); | 256 | radeon_ring_write(cp, (x1 << 0) | (y1 << 16) | (1 << 31)); |
251 | radeon_ring_write(rdev, (x2 << 0) | (y2 << 16)); | 257 | radeon_ring_write(cp, (x2 << 0) | (y2 << 16)); |
252 | } | 258 | } |
253 | 259 | ||
254 | /* emits 10 */ | 260 | /* emits 10 */ |
255 | static void | 261 | static void |
256 | draw_auto(struct radeon_device *rdev) | 262 | draw_auto(struct radeon_device *rdev) |
257 | { | 263 | { |
258 | radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1)); | 264 | struct radeon_cp *cp = &rdev->cp; |
259 | radeon_ring_write(rdev, (VGT_PRIMITIVE_TYPE - PACKET3_SET_CONFIG_REG_START) >> 2); | 265 | radeon_ring_write(cp, PACKET3(PACKET3_SET_CONFIG_REG, 1)); |
260 | radeon_ring_write(rdev, DI_PT_RECTLIST); | 266 | radeon_ring_write(cp, (VGT_PRIMITIVE_TYPE - PACKET3_SET_CONFIG_REG_START) >> 2); |
267 | radeon_ring_write(cp, DI_PT_RECTLIST); | ||
261 | 268 | ||
262 | radeon_ring_write(rdev, PACKET3(PACKET3_INDEX_TYPE, 0)); | 269 | radeon_ring_write(cp, PACKET3(PACKET3_INDEX_TYPE, 0)); |
263 | radeon_ring_write(rdev, | 270 | radeon_ring_write(cp, |
264 | #ifdef __BIG_ENDIAN | 271 | #ifdef __BIG_ENDIAN |
265 | (2 << 2) | | 272 | (2 << 2) | |
266 | #endif | 273 | #endif |
267 | DI_INDEX_SIZE_16_BIT); | 274 | DI_INDEX_SIZE_16_BIT); |
268 | 275 | ||
269 | radeon_ring_write(rdev, PACKET3(PACKET3_NUM_INSTANCES, 0)); | 276 | radeon_ring_write(cp, PACKET3(PACKET3_NUM_INSTANCES, 0)); |
270 | radeon_ring_write(rdev, 1); | 277 | radeon_ring_write(cp, 1); |
271 | 278 | ||
272 | radeon_ring_write(rdev, PACKET3(PACKET3_DRAW_INDEX_AUTO, 1)); | 279 | radeon_ring_write(cp, PACKET3(PACKET3_DRAW_INDEX_AUTO, 1)); |
273 | radeon_ring_write(rdev, 3); | 280 | radeon_ring_write(cp, 3); |
274 | radeon_ring_write(rdev, DI_SRC_SEL_AUTO_INDEX); | 281 | radeon_ring_write(cp, DI_SRC_SEL_AUTO_INDEX); |
275 | 282 | ||
276 | } | 283 | } |
277 | 284 | ||
@@ -279,6 +286,7 @@ draw_auto(struct radeon_device *rdev) | |||
279 | static void | 286 | static void |
280 | set_default_state(struct radeon_device *rdev) | 287 | set_default_state(struct radeon_device *rdev) |
281 | { | 288 | { |
289 | struct radeon_cp *cp = &rdev->cp; | ||
282 | u32 sq_config, sq_gpr_resource_mgmt_1, sq_gpr_resource_mgmt_2, sq_gpr_resource_mgmt_3; | 290 | u32 sq_config, sq_gpr_resource_mgmt_1, sq_gpr_resource_mgmt_2, sq_gpr_resource_mgmt_3; |
283 | u32 sq_thread_resource_mgmt, sq_thread_resource_mgmt_2; | 291 | u32 sq_thread_resource_mgmt, sq_thread_resource_mgmt_2; |
284 | u32 sq_stack_resource_mgmt_1, sq_stack_resource_mgmt_2, sq_stack_resource_mgmt_3; | 292 | u32 sq_stack_resource_mgmt_1, sq_stack_resource_mgmt_2, sq_stack_resource_mgmt_3; |
@@ -292,8 +300,8 @@ set_default_state(struct radeon_device *rdev) | |||
292 | int dwords; | 300 | int dwords; |
293 | 301 | ||
294 | /* set clear context state */ | 302 | /* set clear context state */ |
295 | radeon_ring_write(rdev, PACKET3(PACKET3_CLEAR_STATE, 0)); | 303 | radeon_ring_write(cp, PACKET3(PACKET3_CLEAR_STATE, 0)); |
296 | radeon_ring_write(rdev, 0); | 304 | radeon_ring_write(cp, 0); |
297 | 305 | ||
298 | if (rdev->family < CHIP_CAYMAN) { | 306 | if (rdev->family < CHIP_CAYMAN) { |
299 | switch (rdev->family) { | 307 | switch (rdev->family) { |
@@ -550,60 +558,60 @@ set_default_state(struct radeon_device *rdev) | |||
550 | NUM_LS_STACK_ENTRIES(num_ls_stack_entries)); | 558 | NUM_LS_STACK_ENTRIES(num_ls_stack_entries)); |
551 | 559 | ||
552 | /* disable dyn gprs */ | 560 | /* disable dyn gprs */ |
553 | radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1)); | 561 | radeon_ring_write(cp, PACKET3(PACKET3_SET_CONFIG_REG, 1)); |
554 | radeon_ring_write(rdev, (SQ_DYN_GPR_CNTL_PS_FLUSH_REQ - PACKET3_SET_CONFIG_REG_START) >> 2); | 562 | radeon_ring_write(cp, (SQ_DYN_GPR_CNTL_PS_FLUSH_REQ - PACKET3_SET_CONFIG_REG_START) >> 2); |
555 | radeon_ring_write(rdev, 0); | 563 | radeon_ring_write(cp, 0); |
556 | 564 | ||
557 | /* setup LDS */ | 565 | /* setup LDS */ |
558 | radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1)); | 566 | radeon_ring_write(cp, PACKET3(PACKET3_SET_CONFIG_REG, 1)); |
559 | radeon_ring_write(rdev, (SQ_LDS_RESOURCE_MGMT - PACKET3_SET_CONFIG_REG_START) >> 2); | 567 | radeon_ring_write(cp, (SQ_LDS_RESOURCE_MGMT - PACKET3_SET_CONFIG_REG_START) >> 2); |
560 | radeon_ring_write(rdev, 0x10001000); | 568 | radeon_ring_write(cp, 0x10001000); |
561 | 569 | ||
562 | /* SQ config */ | 570 | /* SQ config */ |
563 | radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 11)); | 571 | radeon_ring_write(cp, PACKET3(PACKET3_SET_CONFIG_REG, 11)); |
564 | radeon_ring_write(rdev, (SQ_CONFIG - PACKET3_SET_CONFIG_REG_START) >> 2); | 572 | radeon_ring_write(cp, (SQ_CONFIG - PACKET3_SET_CONFIG_REG_START) >> 2); |
565 | radeon_ring_write(rdev, sq_config); | 573 | radeon_ring_write(cp, sq_config); |
566 | radeon_ring_write(rdev, sq_gpr_resource_mgmt_1); | 574 | radeon_ring_write(cp, sq_gpr_resource_mgmt_1); |
567 | radeon_ring_write(rdev, sq_gpr_resource_mgmt_2); | 575 | radeon_ring_write(cp, sq_gpr_resource_mgmt_2); |
568 | radeon_ring_write(rdev, sq_gpr_resource_mgmt_3); | 576 | radeon_ring_write(cp, sq_gpr_resource_mgmt_3); |
569 | radeon_ring_write(rdev, 0); | 577 | radeon_ring_write(cp, 0); |
570 | radeon_ring_write(rdev, 0); | 578 | radeon_ring_write(cp, 0); |
571 | radeon_ring_write(rdev, sq_thread_resource_mgmt); | 579 | radeon_ring_write(cp, sq_thread_resource_mgmt); |
572 | radeon_ring_write(rdev, sq_thread_resource_mgmt_2); | 580 | radeon_ring_write(cp, sq_thread_resource_mgmt_2); |
573 | radeon_ring_write(rdev, sq_stack_resource_mgmt_1); | 581 | radeon_ring_write(cp, sq_stack_resource_mgmt_1); |
574 | radeon_ring_write(rdev, sq_stack_resource_mgmt_2); | 582 | radeon_ring_write(cp, sq_stack_resource_mgmt_2); |
575 | radeon_ring_write(rdev, sq_stack_resource_mgmt_3); | 583 | radeon_ring_write(cp, sq_stack_resource_mgmt_3); |
576 | } | 584 | } |
577 | 585 | ||
578 | /* CONTEXT_CONTROL */ | 586 | /* CONTEXT_CONTROL */ |
579 | radeon_ring_write(rdev, 0xc0012800); | 587 | radeon_ring_write(cp, 0xc0012800); |
580 | radeon_ring_write(rdev, 0x80000000); | 588 | radeon_ring_write(cp, 0x80000000); |
581 | radeon_ring_write(rdev, 0x80000000); | 589 | radeon_ring_write(cp, 0x80000000); |
582 | 590 | ||
583 | /* SQ_VTX_BASE_VTX_LOC */ | 591 | /* SQ_VTX_BASE_VTX_LOC */ |
584 | radeon_ring_write(rdev, 0xc0026f00); | 592 | radeon_ring_write(cp, 0xc0026f00); |
585 | radeon_ring_write(rdev, 0x00000000); | 593 | radeon_ring_write(cp, 0x00000000); |
586 | radeon_ring_write(rdev, 0x00000000); | 594 | radeon_ring_write(cp, 0x00000000); |
587 | radeon_ring_write(rdev, 0x00000000); | 595 | radeon_ring_write(cp, 0x00000000); |
588 | 596 | ||
589 | /* SET_SAMPLER */ | 597 | /* SET_SAMPLER */ |
590 | radeon_ring_write(rdev, 0xc0036e00); | 598 | radeon_ring_write(cp, 0xc0036e00); |
591 | radeon_ring_write(rdev, 0x00000000); | 599 | radeon_ring_write(cp, 0x00000000); |
592 | radeon_ring_write(rdev, 0x00000012); | 600 | radeon_ring_write(cp, 0x00000012); |
593 | radeon_ring_write(rdev, 0x00000000); | 601 | radeon_ring_write(cp, 0x00000000); |
594 | radeon_ring_write(rdev, 0x00000000); | 602 | radeon_ring_write(cp, 0x00000000); |
595 | 603 | ||
596 | /* set to DX10/11 mode */ | 604 | /* set to DX10/11 mode */ |
597 | radeon_ring_write(rdev, PACKET3(PACKET3_MODE_CONTROL, 0)); | 605 | radeon_ring_write(cp, PACKET3(PACKET3_MODE_CONTROL, 0)); |
598 | radeon_ring_write(rdev, 1); | 606 | radeon_ring_write(cp, 1); |
599 | 607 | ||
600 | /* emit an IB pointing at default state */ | 608 | /* emit an IB pointing at default state */ |
601 | dwords = ALIGN(rdev->r600_blit.state_len, 0x10); | 609 | dwords = ALIGN(rdev->r600_blit.state_len, 0x10); |
602 | gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.state_offset; | 610 | gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.state_offset; |
603 | radeon_ring_write(rdev, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); | 611 | radeon_ring_write(cp, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); |
604 | radeon_ring_write(rdev, gpu_addr & 0xFFFFFFFC); | 612 | radeon_ring_write(cp, gpu_addr & 0xFFFFFFFC); |
605 | radeon_ring_write(rdev, upper_32_bits(gpu_addr) & 0xFF); | 613 | radeon_ring_write(cp, upper_32_bits(gpu_addr) & 0xFF); |
606 | radeon_ring_write(rdev, dwords); | 614 | radeon_ring_write(cp, dwords); |
607 | 615 | ||
608 | } | 616 | } |
609 | 617 | ||