1 files changed, 66 insertions, 20 deletions

diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c
index f95d7fc1f5e..061fa0a2890 100644
--- a/drivers/gpu/drm/radeon/evergreen.c
+++ b/drivers/gpu/drm/radeon/evergreen.c
@@ -2306,22 +2306,20 @@ bool evergreen_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *rin
         return radeon_ring_test_lockup(rdev, ring);
 }
 
-static int evergreen_gpu_soft_reset(struct radeon_device *rdev)
+static void evergreen_gpu_soft_reset_gfx(struct radeon_device *rdev)
 {
-        struct evergreen_mc_save save;
         u32 grbm_reset = 0;
 
         if (!(RREG32(GRBM_STATUS) & GUI_ACTIVE))
-                return 0;
+                return;
 
-        dev_info(rdev->dev, "GPU softreset \n");
-        dev_info(rdev->dev, "  GRBM_STATUS=0x%08X\n",
+        dev_info(rdev->dev, "  GRBM_STATUS               = 0x%08X\n",
                 RREG32(GRBM_STATUS));
-        dev_info(rdev->dev, "  GRBM_STATUS_SE0=0x%08X\n",
+        dev_info(rdev->dev, "  GRBM_STATUS_SE0           = 0x%08X\n",
                 RREG32(GRBM_STATUS_SE0));
-        dev_info(rdev->dev, "  GRBM_STATUS_SE1=0x%08X\n",
+        dev_info(rdev->dev, "  GRBM_STATUS_SE1           = 0x%08X\n",
                 RREG32(GRBM_STATUS_SE1));
-        dev_info(rdev->dev, "  SRBM_STATUS=0x%08X\n",
+        dev_info(rdev->dev, "  SRBM_STATUS               = 0x%08X\n",
                 RREG32(SRBM_STATUS));
         dev_info(rdev->dev, "  R_008674_CP_STALLED_STAT1 = 0x%08X\n",
                 RREG32(CP_STALLED_STAT1));
@@ -2331,10 +2329,7 @@ static int evergreen_gpu_soft_reset(struct radeon_device *rdev)
                 RREG32(CP_BUSY_STAT));
         dev_info(rdev->dev, "  R_008680_CP_STAT          = 0x%08X\n",
                 RREG32(CP_STAT));
-        evergreen_mc_stop(rdev, &save);
-        if (evergreen_mc_wait_for_idle(rdev)) {
-                dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
-        }
+
         /* Disable CP parsing/prefetching */
         WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT);
 
@@ -2358,15 +2353,14 @@ static int evergreen_gpu_soft_reset(struct radeon_device *rdev)
         udelay(50);
         WREG32(GRBM_SOFT_RESET, 0);
         (void)RREG32(GRBM_SOFT_RESET);
-        /* Wait a little for things to settle down */
-        udelay(50);
-        dev_info(rdev->dev, "  GRBM_STATUS=0x%08X\n",
+
+        dev_info(rdev->dev, "  GRBM_STATUS               = 0x%08X\n",
                 RREG32(GRBM_STATUS));
-        dev_info(rdev->dev, "  GRBM_STATUS_SE0=0x%08X\n",
+        dev_info(rdev->dev, "  GRBM_STATUS_SE0           = 0x%08X\n",
                 RREG32(GRBM_STATUS_SE0));
-        dev_info(rdev->dev, "  GRBM_STATUS_SE1=0x%08X\n",
+        dev_info(rdev->dev, "  GRBM_STATUS_SE1           = 0x%08X\n",
                 RREG32(GRBM_STATUS_SE1));
-        dev_info(rdev->dev, "  SRBM_STATUS=0x%08X\n",
+        dev_info(rdev->dev, "  SRBM_STATUS               = 0x%08X\n",
                 RREG32(SRBM_STATUS));
         dev_info(rdev->dev, "  R_008674_CP_STALLED_STAT1 = 0x%08X\n",
                 RREG32(CP_STALLED_STAT1));
@@ -2376,13 +2370,65 @@ static int evergreen_gpu_soft_reset(struct radeon_device *rdev)
                 RREG32(CP_BUSY_STAT));
         dev_info(rdev->dev, "  R_008680_CP_STAT          = 0x%08X\n",
                 RREG32(CP_STAT));
+}
+
+static void evergreen_gpu_soft_reset_dma(struct radeon_device *rdev)
+{
+        u32 tmp;
+
+        if (RREG32(DMA_STATUS_REG) & DMA_IDLE)
+                return;
+
+        dev_info(rdev->dev, "  R_00D034_DMA_STATUS_REG   = 0x%08X\n",
+                RREG32(DMA_STATUS_REG));
+
+        /* Disable DMA */
+        tmp = RREG32(DMA_RB_CNTL);
+        tmp &= ~DMA_RB_ENABLE;
+        WREG32(DMA_RB_CNTL, tmp);
+
+        /* Reset dma */
+        WREG32(SRBM_SOFT_RESET, SOFT_RESET_DMA);
+        RREG32(SRBM_SOFT_RESET);
+        udelay(50);
+        WREG32(SRBM_SOFT_RESET, 0);
+
+        dev_info(rdev->dev, "  R_00D034_DMA_STATUS_REG   = 0x%08X\n",
+                RREG32(DMA_STATUS_REG));
+}
+
+static int evergreen_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask)
+{
+        struct evergreen_mc_save save;
+
+        if (reset_mask == 0)
+                return 0;
+
+        dev_info(rdev->dev, "GPU softreset: 0x%08X\n", reset_mask);
+
+        evergreen_mc_stop(rdev, &save);
+        if (evergreen_mc_wait_for_idle(rdev)) {
+                dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
+        }
+
+        if (reset_mask & (RADEON_RESET_GFX | RADEON_RESET_COMPUTE))
+                evergreen_gpu_soft_reset_gfx(rdev);
+
+        if (reset_mask & RADEON_RESET_DMA)
+                evergreen_gpu_soft_reset_dma(rdev);
+
+        /* Wait a little for things to settle down */
+        udelay(50);
+
         evergreen_mc_resume(rdev, &save);
         return 0;
 }
 
 int evergreen_asic_reset(struct radeon_device *rdev)
 {
-        return evergreen_gpu_soft_reset(rdev);
+        return evergreen_gpu_soft_reset(rdev, (RADEON_RESET_GFX |
+                                               RADEON_RESET_COMPUTE |
+                                               RADEON_RESET_DMA));
 }
 
 /* Interrupts */
@@ -3215,7 +3261,7 @@ void evergreen_dma_fence_ring_emit(struct radeon_device *rdev,
         radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_TRAP, 0, 0, 0));
         /* flush HDP */
         radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0, 0));
-        radeon_ring_write(ring, (0xf << 16) | HDP_MEM_COHERENCY_FLUSH_CNTL);
+        radeon_ring_write(ring, (0xf << 16) | (HDP_MEM_COHERENCY_FLUSH_CNTL >> 2));
         radeon_ring_write(ring, 1);
 }