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path: root/drivers/gpu/drm/radeon/atombios_crtc.c
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Diffstat (limited to 'drivers/gpu/drm/radeon/atombios_crtc.c')
-rw-r--r--drivers/gpu/drm/radeon/atombios_crtc.c97
1 files changed, 54 insertions, 43 deletions
diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c b/drivers/gpu/drm/radeon/atombios_crtc.c
index a515b2a09d8..2b97262e3ab 100644
--- a/drivers/gpu/drm/radeon/atombios_crtc.c
+++ b/drivers/gpu/drm/radeon/atombios_crtc.c
@@ -558,7 +558,7 @@ static u32 atombios_adjust_pll(struct drm_crtc *crtc,
558 bpc = connector->display_info.bpc; 558 bpc = connector->display_info.bpc;
559 encoder_mode = atombios_get_encoder_mode(encoder); 559 encoder_mode = atombios_get_encoder_mode(encoder);
560 if ((radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT | ATOM_DEVICE_DFP_SUPPORT)) || 560 if ((radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT | ATOM_DEVICE_DFP_SUPPORT)) ||
561 radeon_encoder_is_dp_bridge(encoder)) { 561 (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE)) {
562 if (connector) { 562 if (connector) {
563 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 563 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
564 struct radeon_connector_atom_dig *dig_connector = 564 struct radeon_connector_atom_dig *dig_connector =
@@ -638,44 +638,29 @@ static u32 atombios_adjust_pll(struct drm_crtc *crtc,
638 if (ss_enabled && ss->percentage) 638 if (ss_enabled && ss->percentage)
639 args.v3.sInput.ucDispPllConfig |= 639 args.v3.sInput.ucDispPllConfig |=
640 DISPPLL_CONFIG_SS_ENABLE; 640 DISPPLL_CONFIG_SS_ENABLE;
641 if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT) || 641 if (ENCODER_MODE_IS_DP(encoder_mode)) {
642 radeon_encoder_is_dp_bridge(encoder)) { 642 args.v3.sInput.ucDispPllConfig |=
643 DISPPLL_CONFIG_COHERENT_MODE;
644 /* 16200 or 27000 */
645 args.v3.sInput.usPixelClock = cpu_to_le16(dp_clock / 10);
646 } else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
643 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 647 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
644 if (encoder_mode == ATOM_ENCODER_MODE_DP) { 648 if (encoder_mode == ATOM_ENCODER_MODE_HDMI)
649 /* deep color support */
650 args.v3.sInput.usPixelClock =
651 cpu_to_le16((mode->clock * bpc / 8) / 10);
652 if (dig->coherent_mode)
645 args.v3.sInput.ucDispPllConfig |= 653 args.v3.sInput.ucDispPllConfig |=
646 DISPPLL_CONFIG_COHERENT_MODE; 654 DISPPLL_CONFIG_COHERENT_MODE;
647 /* 16200 or 27000 */ 655 if (mode->clock > 165000)
648 args.v3.sInput.usPixelClock = cpu_to_le16(dp_clock / 10);
649 } else {
650 if (encoder_mode == ATOM_ENCODER_MODE_HDMI) {
651 /* deep color support */
652 args.v3.sInput.usPixelClock =
653 cpu_to_le16((mode->clock * bpc / 8) / 10);
654 }
655 if (dig->coherent_mode)
656 args.v3.sInput.ucDispPllConfig |=
657 DISPPLL_CONFIG_COHERENT_MODE;
658 if (mode->clock > 165000)
659 args.v3.sInput.ucDispPllConfig |=
660 DISPPLL_CONFIG_DUAL_LINK;
661 }
662 } else if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
663 if (encoder_mode == ATOM_ENCODER_MODE_DP) {
664 args.v3.sInput.ucDispPllConfig |= 656 args.v3.sInput.ucDispPllConfig |=
665 DISPPLL_CONFIG_COHERENT_MODE; 657 DISPPLL_CONFIG_DUAL_LINK;
666 /* 16200 or 27000 */
667 args.v3.sInput.usPixelClock = cpu_to_le16(dp_clock / 10);
668 } else if (encoder_mode != ATOM_ENCODER_MODE_LVDS) {
669 if (mode->clock > 165000)
670 args.v3.sInput.ucDispPllConfig |=
671 DISPPLL_CONFIG_DUAL_LINK;
672 }
673 } 658 }
674 if (radeon_encoder_is_dp_bridge(encoder)) { 659 if (radeon_encoder_get_dp_bridge_encoder_id(encoder) !=
675 struct drm_encoder *ext_encoder = radeon_atom_get_external_encoder(encoder); 660 ENCODER_OBJECT_ID_NONE)
676 struct radeon_encoder *ext_radeon_encoder = to_radeon_encoder(ext_encoder); 661 args.v3.sInput.ucExtTransmitterID =
677 args.v3.sInput.ucExtTransmitterID = ext_radeon_encoder->encoder_id; 662 radeon_encoder_get_dp_bridge_encoder_id(encoder);
678 } else 663 else
679 args.v3.sInput.ucExtTransmitterID = 0; 664 args.v3.sInput.ucExtTransmitterID = 0;
680 665
681 atom_execute_table(rdev->mode_info.atom_context, 666 atom_execute_table(rdev->mode_info.atom_context,
@@ -945,6 +930,7 @@ static void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode
945 bpc = connector->display_info.bpc; 930 bpc = connector->display_info.bpc;
946 931
947 switch (encoder_mode) { 932 switch (encoder_mode) {
933 case ATOM_ENCODER_MODE_DP_MST:
948 case ATOM_ENCODER_MODE_DP: 934 case ATOM_ENCODER_MODE_DP:
949 /* DP/eDP */ 935 /* DP/eDP */
950 dp_clock = dig_connector->dp_clock / 10; 936 dp_clock = dig_connector->dp_clock / 10;
@@ -1121,9 +1107,40 @@ static int dce4_crtc_do_set_base(struct drm_crtc *crtc,
1121 return -EINVAL; 1107 return -EINVAL;
1122 } 1108 }
1123 1109
1124 if (tiling_flags & RADEON_TILING_MACRO) 1110 if (tiling_flags & RADEON_TILING_MACRO) {
1111 if (rdev->family >= CHIP_CAYMAN)
1112 tmp = rdev->config.cayman.tile_config;
1113 else
1114 tmp = rdev->config.evergreen.tile_config;
1115
1116 switch ((tmp & 0xf0) >> 4) {
1117 case 0: /* 4 banks */
1118 fb_format |= EVERGREEN_GRPH_NUM_BANKS(EVERGREEN_ADDR_SURF_4_BANK);
1119 break;
1120 case 1: /* 8 banks */
1121 default:
1122 fb_format |= EVERGREEN_GRPH_NUM_BANKS(EVERGREEN_ADDR_SURF_8_BANK);
1123 break;
1124 case 2: /* 16 banks */
1125 fb_format |= EVERGREEN_GRPH_NUM_BANKS(EVERGREEN_ADDR_SURF_16_BANK);
1126 break;
1127 }
1128
1129 switch ((tmp & 0xf000) >> 12) {
1130 case 0: /* 1KB rows */
1131 default:
1132 fb_format |= EVERGREEN_GRPH_TILE_SPLIT(EVERGREEN_ADDR_SURF_TILE_SPLIT_1KB);
1133 break;
1134 case 1: /* 2KB rows */
1135 fb_format |= EVERGREEN_GRPH_TILE_SPLIT(EVERGREEN_ADDR_SURF_TILE_SPLIT_2KB);
1136 break;
1137 case 2: /* 4KB rows */
1138 fb_format |= EVERGREEN_GRPH_TILE_SPLIT(EVERGREEN_ADDR_SURF_TILE_SPLIT_4KB);
1139 break;
1140 }
1141
1125 fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_2D_TILED_THIN1); 1142 fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_2D_TILED_THIN1);
1126 else if (tiling_flags & RADEON_TILING_MICRO) 1143 } else if (tiling_flags & RADEON_TILING_MICRO)
1127 fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_1D_TILED_THIN1); 1144 fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_1D_TILED_THIN1);
1128 1145
1129 switch (radeon_crtc->crtc_id) { 1146 switch (radeon_crtc->crtc_id) {
@@ -1450,7 +1467,7 @@ static int radeon_atom_pick_pll(struct drm_crtc *crtc)
1450 * PPLL/DCPLL programming and only program the DP DTO for the 1467 * PPLL/DCPLL programming and only program the DP DTO for the
1451 * crtc virtual pixel clock. 1468 * crtc virtual pixel clock.
1452 */ 1469 */
1453 if (atombios_get_encoder_mode(test_encoder) == ATOM_ENCODER_MODE_DP) { 1470 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(test_encoder))) {
1454 if (ASIC_IS_DCE5(rdev) || rdev->clock.dp_extclk) 1471 if (ASIC_IS_DCE5(rdev) || rdev->clock.dp_extclk)
1455 return ATOM_PPLL_INVALID; 1472 return ATOM_PPLL_INVALID;
1456 } 1473 }
@@ -1536,12 +1553,6 @@ static bool atombios_crtc_mode_fixup(struct drm_crtc *crtc,
1536 struct drm_display_mode *mode, 1553 struct drm_display_mode *mode,
1537 struct drm_display_mode *adjusted_mode) 1554 struct drm_display_mode *adjusted_mode)
1538{ 1555{
1539 struct drm_device *dev = crtc->dev;
1540 struct radeon_device *rdev = dev->dev_private;
1541
1542 /* adjust pm to upcoming mode change */
1543 radeon_pm_compute_clocks(rdev);
1544
1545 if (!radeon_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode)) 1556 if (!radeon_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode))
1546 return false; 1557 return false;
1547 return true; 1558 return true;
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-12 20:54:47 -0500