3 files changed, 12 insertions, 12 deletions

diff --git a/drivers/gpu/drm/nouveau/nouveau_display.c b/drivers/gpu/drm/nouveau/nouveau_display.c
index 7687a77f01d..2531ef54c3e 100644
--- a/drivers/gpu/drm/nouveau/nouveau_display.c
+++ b/drivers/gpu/drm/nouveau/nouveau_display.c
@@ -107,14 +107,14 @@ nouveau_framebuffer_init(struct drm_device *dev,
 
                 if (!tile_flags) {
                         if (dev_priv->card_type < NV_D0)
-                                nv_fb->r_pitch = 0x00100000 | fb->pitch;
+                                nv_fb->r_pitch = 0x00100000 | fb->pitches[0];
                         else
-                                nv_fb->r_pitch = 0x01000000 | fb->pitch;
+                                nv_fb->r_pitch = 0x01000000 | fb->pitches[0];
                 } else {
                         u32 mode = nvbo->tile_mode;
                         if (dev_priv->card_type >= NV_C0)
                                 mode >>= 4;
-                        nv_fb->r_pitch = ((fb->pitch / 4) << 4) | mode;
+                        nv_fb->r_pitch = ((fb->pitches[0] / 4) << 4) | mode;
                 }
         }
 
@@ -294,7 +294,7 @@ nouveau_crtc_page_flip(struct drm_crtc *crtc, struct drm_framebuffer *fb,
         /* Initialize a page flip struct */
         *s = (struct nouveau_page_flip_state)
                 { { }, event, nouveau_crtc(crtc)->index,
-                  fb->bits_per_pixel, fb->pitch, crtc->x, crtc->y,
+                  fb->bits_per_pixel, fb->pitches[0], crtc->x, crtc->y,
                   new_bo->bo.offset };
 
         /* Choose the channel the flip will be handled in */
diff --git a/drivers/gpu/drm/nouveau/nouveau_fbcon.c b/drivers/gpu/drm/nouveau/nouveau_fbcon.c
index d663065181b..defffd14078 100644
--- a/drivers/gpu/drm/nouveau/nouveau_fbcon.c
+++ b/drivers/gpu/drm/nouveau/nouveau_fbcon.c
@@ -370,7 +370,7 @@ nouveau_fbcon_create(struct nouveau_fbdev *nfbdev,
         info->screen_base = nvbo_kmap_obj_iovirtual(nouveau_fb->nvbo);
         info->screen_size = size;
 
-        drm_fb_helper_fill_fix(info, fb->pitch, fb->depth);
+        drm_fb_helper_fill_fix(info, fb->pitches[0], fb->depth);
         drm_fb_helper_fill_var(info, &nfbdev->helper, sizes->fb_width, sizes->fb_height);
 
         /* Set aperture base/size for vesafb takeover */
diff --git a/drivers/gpu/drm/nouveau/nv04_crtc.c b/drivers/gpu/drm/nouveau/nv04_crtc.c
index 5e45398a9e2..728d07584d3 100644
--- a/drivers/gpu/drm/nouveau/nv04_crtc.c
+++ b/drivers/gpu/drm/nouveau/nv04_crtc.c
@@ -364,7 +364,7 @@ nv_crtc_mode_set_vga(struct drm_crtc *crtc, struct drm_display_mode *mode)
         regp->CRTC[NV_CIO_CR_VRE_INDEX] = 1 << 5 | XLATE(vertEnd, 0, NV_CIO_CR_VRE_3_0);
         regp->CRTC[NV_CIO_CR_VDE_INDEX] = vertDisplay;
         /* framebuffer can be larger than crtc scanout area. */
-        regp->CRTC[NV_CIO_CR_OFFSET_INDEX] = fb->pitch / 8;
+        regp->CRTC[NV_CIO_CR_OFFSET_INDEX] = fb->pitches[0] / 8;
         regp->CRTC[NV_CIO_CR_ULINE_INDEX] = 0x00;
         regp->CRTC[NV_CIO_CR_VBS_INDEX] = vertBlankStart;
         regp->CRTC[NV_CIO_CR_VBE_INDEX] = vertBlankEnd;
@@ -377,9 +377,9 @@ nv_crtc_mode_set_vga(struct drm_crtc *crtc, struct drm_display_mode *mode)
 
         /* framebuffer can be larger than crtc scanout area. */
         regp->CRTC[NV_CIO_CRE_RPC0_INDEX] =
-                XLATE(fb->pitch / 8, 8, NV_CIO_CRE_RPC0_OFFSET_10_8);
+                XLATE(fb->pitches[0] / 8, 8, NV_CIO_CRE_RPC0_OFFSET_10_8);
         regp->CRTC[NV_CIO_CRE_42] =
-                XLATE(fb->pitch / 8, 11, NV_CIO_CRE_42_OFFSET_11);
+                XLATE(fb->pitches[0] / 8, 11, NV_CIO_CRE_42_OFFSET_11);
         regp->CRTC[NV_CIO_CRE_RPC1_INDEX] = mode->crtc_hdisplay < 1280 ?
                                             MASK(NV_CIO_CRE_RPC1_LARGE) : 0x00;
         regp->CRTC[NV_CIO_CRE_LSR_INDEX] = XLATE(horizBlankEnd, 6, NV_CIO_CRE_LSR_HBE_6) |
@@ -835,18 +835,18 @@ nv04_crtc_do_mode_set_base(struct drm_crtc *crtc,
         NVWriteRAMDAC(dev, nv_crtc->index, NV_PRAMDAC_GENERAL_CONTROL,
                       regp->ramdac_gen_ctrl);
 
-        regp->CRTC[NV_CIO_CR_OFFSET_INDEX] = drm_fb->pitch >> 3;
+        regp->CRTC[NV_CIO_CR_OFFSET_INDEX] = drm_fb->pitches[0] >> 3;
         regp->CRTC[NV_CIO_CRE_RPC0_INDEX] =
-                XLATE(drm_fb->pitch >> 3, 8, NV_CIO_CRE_RPC0_OFFSET_10_8);
+                XLATE(drm_fb->pitches[0] >> 3, 8, NV_CIO_CRE_RPC0_OFFSET_10_8);
         regp->CRTC[NV_CIO_CRE_42] =
-                XLATE(drm_fb->pitch / 8, 11, NV_CIO_CRE_42_OFFSET_11);
+                XLATE(drm_fb->pitches[0] / 8, 11, NV_CIO_CRE_42_OFFSET_11);
         crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_RPC0_INDEX);
         crtc_wr_cio_state(crtc, regp, NV_CIO_CR_OFFSET_INDEX);
         crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_42);
 
         /* Update the framebuffer location. */
         regp->fb_start = nv_crtc->fb.offset & ~3;
-        regp->fb_start += (y * drm_fb->pitch) + (x * drm_fb->bits_per_pixel / 8);
+        regp->fb_start += (y * drm_fb->pitches[0]) + (x * drm_fb->bits_per_pixel / 8);
         nv_set_crtc_base(dev, nv_crtc->index, regp->fb_start);
 
         /* Update the arbitration parameters. */