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path: root/drivers/gpu/drm/i915/intel_overlay.c
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Diffstat (limited to 'drivers/gpu/drm/i915/intel_overlay.c')
-rw-r--r--drivers/gpu/drm/i915/intel_overlay.c101
1 files changed, 100 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/intel_overlay.c b/drivers/gpu/drm/i915/intel_overlay.c
index d39aea24eab..1d306a458be 100644
--- a/drivers/gpu/drm/i915/intel_overlay.c
+++ b/drivers/gpu/drm/i915/intel_overlay.c
@@ -25,6 +25,8 @@
25 * 25 *
26 * Derived from Xorg ddx, xf86-video-intel, src/i830_video.c 26 * Derived from Xorg ddx, xf86-video-intel, src/i830_video.c
27 */ 27 */
28
29#include <linux/seq_file.h>
28#include "drmP.h" 30#include "drmP.h"
29#include "drm.h" 31#include "drm.h"
30#include "i915_drm.h" 32#include "i915_drm.h"
@@ -1367,7 +1369,8 @@ void intel_setup_overlay(struct drm_device *dev)
1367 overlay->flip_addr = overlay->reg_bo->gtt_offset; 1369 overlay->flip_addr = overlay->reg_bo->gtt_offset;
1368 } else { 1370 } else {
1369 ret = i915_gem_attach_phys_object(dev, reg_bo, 1371 ret = i915_gem_attach_phys_object(dev, reg_bo,
1370 I915_GEM_PHYS_OVERLAY_REGS); 1372 I915_GEM_PHYS_OVERLAY_REGS,
1373 0);
1371 if (ret) { 1374 if (ret) {
1372 DRM_ERROR("failed to attach phys overlay regs\n"); 1375 DRM_ERROR("failed to attach phys overlay regs\n");
1373 goto out_free_bo; 1376 goto out_free_bo;
@@ -1416,3 +1419,99 @@ void intel_cleanup_overlay(struct drm_device *dev)
1416 kfree(dev_priv->overlay); 1419 kfree(dev_priv->overlay);
1417 } 1420 }
1418} 1421}
1422
1423struct intel_overlay_error_state {
1424 struct overlay_registers regs;
1425 unsigned long base;
1426 u32 dovsta;
1427 u32 isr;
1428};
1429
1430struct intel_overlay_error_state *
1431intel_overlay_capture_error_state(struct drm_device *dev)
1432{
1433 drm_i915_private_t *dev_priv = dev->dev_private;
1434 struct intel_overlay *overlay = dev_priv->overlay;
1435 struct intel_overlay_error_state *error;
1436 struct overlay_registers __iomem *regs;
1437
1438 if (!overlay || !overlay->active)
1439 return NULL;
1440
1441 error = kmalloc(sizeof(*error), GFP_ATOMIC);
1442 if (error == NULL)
1443 return NULL;
1444
1445 error->dovsta = I915_READ(DOVSTA);
1446 error->isr = I915_READ(ISR);
1447 if (OVERLAY_NONPHYSICAL(overlay->dev))
1448 error->base = (long) overlay->reg_bo->gtt_offset;
1449 else
1450 error->base = (long) overlay->reg_bo->phys_obj->handle->vaddr;
1451
1452 regs = intel_overlay_map_regs_atomic(overlay);
1453 if (!regs)
1454 goto err;
1455
1456 memcpy_fromio(&error->regs, regs, sizeof(struct overlay_registers));
1457 intel_overlay_unmap_regs_atomic(overlay);
1458
1459 return error;
1460
1461err:
1462 kfree(error);
1463 return NULL;
1464}
1465
1466void
1467intel_overlay_print_error_state(struct seq_file *m, struct intel_overlay_error_state *error)
1468{
1469 seq_printf(m, "Overlay, status: 0x%08x, interrupt: 0x%08x\n",
1470 error->dovsta, error->isr);
1471 seq_printf(m, " Register file at 0x%08lx:\n",
1472 error->base);
1473
1474#define P(x) seq_printf(m, " " #x ": 0x%08x\n", error->regs.x)
1475 P(OBUF_0Y);
1476 P(OBUF_1Y);
1477 P(OBUF_0U);
1478 P(OBUF_0V);
1479 P(OBUF_1U);
1480 P(OBUF_1V);
1481 P(OSTRIDE);
1482 P(YRGB_VPH);
1483 P(UV_VPH);
1484 P(HORZ_PH);
1485 P(INIT_PHS);
1486 P(DWINPOS);
1487 P(DWINSZ);
1488 P(SWIDTH);
1489 P(SWIDTHSW);
1490 P(SHEIGHT);
1491 P(YRGBSCALE);
1492 P(UVSCALE);
1493 P(OCLRC0);
1494 P(OCLRC1);
1495 P(DCLRKV);
1496 P(DCLRKM);
1497 P(SCLRKVH);
1498 P(SCLRKVL);
1499 P(SCLRKEN);
1500 P(OCONFIG);
1501 P(OCMD);
1502 P(OSTART_0Y);
1503 P(OSTART_1Y);
1504 P(OSTART_0U);
1505 P(OSTART_0V);
1506 P(OSTART_1U);
1507 P(OSTART_1V);
1508 P(OTILEOFF_0Y);
1509 P(OTILEOFF_1Y);
1510 P(OTILEOFF_0U);
1511 P(OTILEOFF_0V);
1512 P(OTILEOFF_1U);
1513 P(OTILEOFF_1V);
1514 P(FASTHSCALE);
1515 P(UVSCALEV);
1516#undef P
1517}