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-rw-r--r--drivers/gpio/Kconfig88
-rw-r--r--drivers/gpio/Makefile90
-rw-r--r--drivers/gpio/gpio-74x164.c (renamed from drivers/gpio/74x164.c)33
-rw-r--r--drivers/gpio/gpio-ab8500.c (renamed from drivers/gpio/ab8500-gpio.c)3
-rw-r--r--drivers/gpio/gpio-adp5520.c (renamed from drivers/gpio/adp5520-gpio.c)0
-rw-r--r--drivers/gpio/gpio-adp5588.c (renamed from drivers/gpio/adp5588-gpio.c)0
-rw-r--r--drivers/gpio/gpio-bt8xx.c (renamed from drivers/gpio/bt8xxgpio.c)2
-rw-r--r--drivers/gpio/gpio-cs5535.c (renamed from drivers/gpio/cs5535-gpio.c)0
-rw-r--r--drivers/gpio/gpio-da9052.c277
-rw-r--r--drivers/gpio/gpio-ep93xx.c405
-rw-r--r--drivers/gpio/gpio-exynos4.c5
-rw-r--r--drivers/gpio/gpio-generic.c (renamed from drivers/gpio/basic_mmio_gpio.c)21
-rw-r--r--drivers/gpio/gpio-it8761e.c (renamed from drivers/gpio/it8761e_gpio.c)2
-rw-r--r--drivers/gpio/gpio-janz-ttl.c (renamed from drivers/gpio/janz-ttl.c)0
-rw-r--r--drivers/gpio/gpio-langwell.c (renamed from drivers/gpio/langwell_gpio.c)4
-rw-r--r--drivers/gpio/gpio-max7300.c (renamed from drivers/gpio/max7300.c)2
-rw-r--r--drivers/gpio/gpio-max7301.c (renamed from drivers/gpio/max7301.c)2
-rw-r--r--drivers/gpio/gpio-max730x.c (renamed from drivers/gpio/max730x.c)2
-rw-r--r--drivers/gpio/gpio-max732x.c (renamed from drivers/gpio/max732x.c)2
-rw-r--r--drivers/gpio/gpio-mc33880.c (renamed from drivers/gpio/mc33880.c)2
-rw-r--r--drivers/gpio/gpio-mcp23s08.c (renamed from drivers/gpio/mcp23s08.c)291
-rw-r--r--drivers/gpio/gpio-ml-ioh.c (renamed from drivers/gpio/ml_ioh_gpio.c)2
-rw-r--r--drivers/gpio/gpio-mpc5200.c376
-rw-r--r--drivers/gpio/gpio-msm-v1.c636
-rw-r--r--drivers/gpio/gpio-msm-v2.c433
-rw-r--r--drivers/gpio/gpio-mxc.c460
-rw-r--r--drivers/gpio/gpio-mxs.c289
-rw-r--r--drivers/gpio/gpio-omap.c725
-rw-r--r--drivers/gpio/gpio-pca953x.c (renamed from drivers/gpio/pca953x.c)106
-rw-r--r--drivers/gpio/gpio-pcf857x.c (renamed from drivers/gpio/pcf857x.c)2
-rw-r--r--drivers/gpio/gpio-pch.c (renamed from drivers/gpio/pch_gpio.c)0
-rw-r--r--drivers/gpio/gpio-pl061.c (renamed from drivers/gpio/pl061.c)4
-rw-r--r--drivers/gpio/gpio-plat-samsung.c3
-rw-r--r--drivers/gpio/gpio-rdc321x.c (renamed from drivers/gpio/rdc321x-gpio.c)0
-rw-r--r--drivers/gpio/gpio-s5pc100.c5
-rw-r--r--drivers/gpio/gpio-s5pv210.c5
-rw-r--r--drivers/gpio/gpio-sch.c (renamed from drivers/gpio/sch_gpio.c)2
-rw-r--r--drivers/gpio/gpio-stmpe.c (renamed from drivers/gpio/stmpe-gpio.c)0
-rw-r--r--drivers/gpio/gpio-sx150x.c (renamed from drivers/gpio/sx150x.c)0
-rw-r--r--drivers/gpio/gpio-tc3589x.c (renamed from drivers/gpio/tc3589x-gpio.c)0
-rw-r--r--drivers/gpio/gpio-tegra.c552
-rw-r--r--drivers/gpio/gpio-timberdale.c (renamed from drivers/gpio/timbgpio.c)2
-rw-r--r--drivers/gpio/gpio-tps65910.c (renamed from drivers/gpio/tps65910-gpio.c)24
-rw-r--r--drivers/gpio/gpio-tps65912.c156
-rw-r--r--drivers/gpio/gpio-twl4030.c (renamed from drivers/gpio/twl4030-gpio.c)2
-rw-r--r--drivers/gpio/gpio-u300.c13
-rw-r--r--drivers/gpio/gpio-ucb1400.c (renamed from drivers/gpio/ucb1400_gpio.c)0
-rw-r--r--drivers/gpio/gpio-vr41xx.c (renamed from drivers/gpio/vr41xx_giu.c)2
-rw-r--r--drivers/gpio/gpio-vx855.c (renamed from drivers/gpio/vx855_gpio.c)0
-rw-r--r--drivers/gpio/gpio-wm831x.c (renamed from drivers/gpio/wm831x-gpio.c)2
-rw-r--r--drivers/gpio/gpio-wm8350.c (renamed from drivers/gpio/wm8350-gpiolib.c)2
-rw-r--r--drivers/gpio/gpio-wm8994.c (renamed from drivers/gpio/wm8994-gpio.c)2
-rw-r--r--drivers/gpio/gpio-xilinx.c (renamed from drivers/gpio/xilinx_gpio.c)0
-rw-r--r--drivers/gpio/gpiolib.c83
54 files changed, 4294 insertions, 825 deletions
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index 2967002a9f8..d539efd96d4 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -63,33 +63,74 @@ config GPIO_SYSFS
63 Kernel drivers may also request that a particular GPIO be 63 Kernel drivers may also request that a particular GPIO be
64 exported to userspace; this can be useful when debugging. 64 exported to userspace; this can be useful when debugging.
65 65
66config GPIO_GENERIC
67 tristate
68
66# put drivers in the right section, in alphabetical order 69# put drivers in the right section, in alphabetical order
67 70
71config GPIO_DA9052
72 tristate "Dialog DA9052 GPIO"
73 depends on PMIC_DA9052
74 help
75 Say yes here to enable the GPIO driver for the DA9052 chip.
76
68config GPIO_MAX730X 77config GPIO_MAX730X
69 tristate 78 tristate
70 79
71comment "Memory mapped GPIO drivers:" 80comment "Memory mapped GPIO drivers:"
72 81
73config GPIO_BASIC_MMIO_CORE 82config GPIO_GENERIC_PLATFORM
74 tristate 83 tristate "Generic memory-mapped GPIO controller support (MMIO platform device)"
75 help 84 select GPIO_GENERIC
76 Provides core functionality for basic memory-mapped GPIO controllers.
77
78config GPIO_BASIC_MMIO
79 tristate "Basic memory-mapped GPIO controllers support"
80 select GPIO_BASIC_MMIO_CORE
81 help 85 help
82 Say yes here to support basic memory-mapped GPIO controllers. 86 Say yes here to support basic platform_device memory-mapped GPIO controllers.
83 87
84config GPIO_IT8761E 88config GPIO_IT8761E
85 tristate "IT8761E GPIO support" 89 tristate "IT8761E GPIO support"
86 help 90 help
87 Say yes here to support GPIO functionality of IT8761E super I/O chip. 91 Say yes here to support GPIO functionality of IT8761E super I/O chip.
88 92
93config GPIO_EP93XX
94 def_bool y
95 depends on ARCH_EP93XX
96 select GPIO_GENERIC
97
89config GPIO_EXYNOS4 98config GPIO_EXYNOS4
90 def_bool y 99 def_bool y
91 depends on CPU_EXYNOS4210 100 depends on CPU_EXYNOS4210
92 101
102config GPIO_MPC5200
103 def_bool y
104 depends on PPC_MPC52xx
105
106config GPIO_MSM_V1
107 tristate "Qualcomm MSM GPIO v1"
108 depends on GPIOLIB && ARCH_MSM
109 help
110 Say yes here to support the GPIO interface on ARM v6 based
111 Qualcomm MSM chips. Most of the pins on the MSM can be
112 selected for GPIO, and are controlled by this driver.
113
114config GPIO_MSM_V2
115 tristate "Qualcomm MSM GPIO v2"
116 depends on GPIOLIB && ARCH_MSM
117 help
118 Say yes here to support the GPIO interface on ARM v7 based
119 Qualcomm MSM chips. Most of the pins on the MSM can be
120 selected for GPIO, and are controlled by this driver.
121
122config GPIO_MXC
123 def_bool y
124 depends on ARCH_MXC
125 select GPIO_GENERIC
126 select GENERIC_IRQ_CHIP
127
128config GPIO_MXS
129 def_bool y
130 depends on ARCH_MXS
131 select GPIO_GENERIC
132 select GENERIC_IRQ_CHIP
133
93config GPIO_PLAT_SAMSUNG 134config GPIO_PLAT_SAMSUNG
94 def_bool y 135 def_bool y
95 depends on SAMSUNG_GPIOLIB_4BIT 136 depends on SAMSUNG_GPIOLIB_4BIT
@@ -137,9 +178,6 @@ config GPIO_SCH
137 The Intel Tunnel Creek processor has 5 GPIOs powered by the 178 The Intel Tunnel Creek processor has 5 GPIOs powered by the
138 core power rail and 9 from suspend power supply. 179 core power rail and 9 from suspend power supply.
139 180
140 This driver can also be built as a module. If so, the module
141 will be called sch-gpio.
142
143config GPIO_VX855 181config GPIO_VX855
144 tristate "VIA VX855/VX875 GPIO" 182 tristate "VIA VX855/VX875 GPIO"
145 depends on MFD_SUPPORT && PCI 183 depends on MFD_SUPPORT && PCI
@@ -202,9 +240,6 @@ config GPIO_PCA953X
202 240
203 16 bits: pca9535, pca9539, pca9555, tca6416 241 16 bits: pca9535, pca9539, pca9555, tca6416
204 242
205 This driver can also be built as a module. If so, the module
206 will be called pca953x.
207
208config GPIO_PCA953X_IRQ 243config GPIO_PCA953X_IRQ
209 bool "Interrupt controller support for PCA953x" 244 bool "Interrupt controller support for PCA953x"
210 depends on GPIO_PCA953X=y 245 depends on GPIO_PCA953X=y
@@ -261,6 +296,12 @@ config GPIO_TC3589X
261 This enables support for the GPIOs found on the TC3589X 296 This enables support for the GPIOs found on the TC3589X
262 I/O Expander. 297 I/O Expander.
263 298
299config GPIO_TPS65912
300 tristate "TI TPS65912 GPIO"
301 depends on (MFD_TPS65912_I2C || MFD_TPS65912_SPI)
302 help
303 This driver supports TPS65912 gpio chip
304
264config GPIO_TWL4030 305config GPIO_TWL4030
265 tristate "TWL4030, TWL5030, and TPS659x0 GPIOs" 306 tristate "TWL4030, TWL5030, and TPS659x0 GPIOs"
266 depends on TWL4030_CORE 307 depends on TWL4030_CORE
@@ -296,17 +337,12 @@ config GPIO_ADP5520
296 This option enables support for on-chip GPIO found 337 This option enables support for on-chip GPIO found
297 on Analog Devices ADP5520 PMICs. 338 on Analog Devices ADP5520 PMICs.
298 339
299 To compile this driver as a module, choose M here: the module will
300 be called adp5520-gpio.
301
302config GPIO_ADP5588 340config GPIO_ADP5588
303 tristate "ADP5588 I2C GPIO expander" 341 tristate "ADP5588 I2C GPIO expander"
304 depends on I2C 342 depends on I2C
305 help 343 help
306 This option enables support for 18 GPIOs found 344 This option enables support for 18 GPIOs found
307 on Analog Devices ADP5588 GPIO Expanders. 345 on Analog Devices ADP5588 GPIO Expanders.
308 To compile this driver as a module, choose M here: the module will be
309 called adp5588-gpio.
310 346
311config GPIO_ADP5588_IRQ 347config GPIO_ADP5588_IRQ
312 bool "Interrupt controller support for ADP5588" 348 bool "Interrupt controller support for ADP5588"
@@ -398,10 +434,11 @@ config GPIO_MAX7301
398 GPIO driver for Maxim MAX7301 SPI-based GPIO expander. 434 GPIO driver for Maxim MAX7301 SPI-based GPIO expander.
399 435
400config GPIO_MCP23S08 436config GPIO_MCP23S08
401 tristate "Microchip MCP23Sxx I/O expander" 437 tristate "Microchip MCP23xxx I/O expander"
402 depends on SPI_MASTER 438 depends on SPI_MASTER || I2C
403 help 439 help
404 SPI driver for Microchip MCP23S08/MPC23S17 I/O expanders. 440 SPI/I2C driver for Microchip MCP23S08/MCP23S17/MCP23008/MCP23017
441 I/O expanders.
405 This provides a GPIO interface supporting inputs and outputs. 442 This provides a GPIO interface supporting inputs and outputs.
406 443
407config GPIO_MC33880 444config GPIO_MC33880
@@ -428,9 +465,6 @@ config GPIO_UCB1400
428 This enables support for the Philips UCB1400 GPIO pins. 465 This enables support for the Philips UCB1400 GPIO pins.
429 The UCB1400 is an AC97 audio codec. 466 The UCB1400 is an AC97 audio codec.
430 467
431 To compile this driver as a module, choose M here: the
432 module will be called ucb1400_gpio.
433
434comment "MODULbus GPIO expanders:" 468comment "MODULbus GPIO expanders:"
435 469
436config GPIO_JANZ_TTL 470config GPIO_JANZ_TTL
@@ -441,7 +475,7 @@ config GPIO_JANZ_TTL
441 This driver provides support for driving the pins in output 475 This driver provides support for driving the pins in output
442 mode only. Input mode is not supported. 476 mode only. Input mode is not supported.
443 477
444config AB8500_GPIO 478config GPIO_AB8500
445 bool "ST-Ericsson AB8500 Mixed Signal Circuit gpio functions" 479 bool "ST-Ericsson AB8500 Mixed Signal Circuit gpio functions"
446 depends on AB8500_CORE && BROKEN 480 depends on AB8500_CORE && BROKEN
447 help 481 help
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index b605f8ec6fb..9588948c96f 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -4,47 +4,59 @@ ccflags-$(CONFIG_DEBUG_GPIO) += -DDEBUG
4 4
5obj-$(CONFIG_GPIOLIB) += gpiolib.o 5obj-$(CONFIG_GPIOLIB) += gpiolib.o
6 6
7obj-$(CONFIG_GPIO_ADP5520) += adp5520-gpio.o 7# Device drivers. Generally keep list sorted alphabetically
8obj-$(CONFIG_GPIO_ADP5588) += adp5588-gpio.o 8obj-$(CONFIG_GPIO_GENERIC) += gpio-generic.o
9obj-$(CONFIG_GPIO_BASIC_MMIO_CORE) += basic_mmio_gpio.o 9
10obj-$(CONFIG_GPIO_BASIC_MMIO) += basic_mmio_gpio.o 10obj-$(CONFIG_GPIO_74X164) += gpio-74x164.o
11obj-$(CONFIG_GPIO_AB8500) += gpio-ab8500.o
12obj-$(CONFIG_GPIO_ADP5520) += gpio-adp5520.o
13obj-$(CONFIG_GPIO_ADP5588) += gpio-adp5588.o
14obj-$(CONFIG_GPIO_BT8XX) += gpio-bt8xx.o
15obj-$(CONFIG_GPIO_CS5535) += gpio-cs5535.o
16obj-$(CONFIG_GPIO_DA9052) += gpio-da9052.o
17obj-$(CONFIG_GPIO_EP93XX) += gpio-ep93xx.o
11obj-$(CONFIG_GPIO_EXYNOS4) += gpio-exynos4.o 18obj-$(CONFIG_GPIO_EXYNOS4) += gpio-exynos4.o
19obj-$(CONFIG_GPIO_IT8761E) += gpio-it8761e.o
20obj-$(CONFIG_GPIO_JANZ_TTL) += gpio-janz-ttl.o
21obj-$(CONFIG_GPIO_LANGWELL) += gpio-langwell.o
22obj-$(CONFIG_GPIO_MAX730X) += gpio-max730x.o
23obj-$(CONFIG_GPIO_MAX7300) += gpio-max7300.o
24obj-$(CONFIG_GPIO_MAX7301) += gpio-max7301.o
25obj-$(CONFIG_GPIO_MAX732X) += gpio-max732x.o
26obj-$(CONFIG_GPIO_MC33880) += gpio-mc33880.o
27obj-$(CONFIG_GPIO_MCP23S08) += gpio-mcp23s08.o
28obj-$(CONFIG_GPIO_ML_IOH) += gpio-ml-ioh.o
29obj-$(CONFIG_GPIO_MPC5200) += gpio-mpc5200.o
30obj-$(CONFIG_GPIO_MSM_V1) += gpio-msm-v1.o
31obj-$(CONFIG_GPIO_MSM_V2) += gpio-msm-v2.o
32obj-$(CONFIG_GPIO_MXC) += gpio-mxc.o
33obj-$(CONFIG_GPIO_MXS) += gpio-mxs.o
34obj-$(CONFIG_PLAT_NOMADIK) += gpio-nomadik.o
35obj-$(CONFIG_ARCH_OMAP) += gpio-omap.o
36obj-$(CONFIG_GPIO_PCA953X) += gpio-pca953x.o
37obj-$(CONFIG_GPIO_PCF857X) += gpio-pcf857x.o
38obj-$(CONFIG_GPIO_PCH) += gpio-pch.o
39obj-$(CONFIG_GPIO_PL061) += gpio-pl061.o
40obj-$(CONFIG_GPIO_RDC321X) += gpio-rdc321x.o
41
12obj-$(CONFIG_GPIO_PLAT_SAMSUNG) += gpio-plat-samsung.o 42obj-$(CONFIG_GPIO_PLAT_SAMSUNG) += gpio-plat-samsung.o
13obj-$(CONFIG_GPIO_S5PC100) += gpio-s5pc100.o 43obj-$(CONFIG_GPIO_S5PC100) += gpio-s5pc100.o
14obj-$(CONFIG_GPIO_S5PV210) += gpio-s5pv210.o 44obj-$(CONFIG_GPIO_S5PV210) += gpio-s5pv210.o
15obj-$(CONFIG_GPIO_LANGWELL) += langwell_gpio.o 45
16obj-$(CONFIG_GPIO_MAX730X) += max730x.o 46obj-$(CONFIG_GPIO_SCH) += gpio-sch.o
17obj-$(CONFIG_GPIO_MAX7300) += max7300.o 47obj-$(CONFIG_GPIO_STMPE) += gpio-stmpe.o
18obj-$(CONFIG_GPIO_MAX7301) += max7301.o 48obj-$(CONFIG_GPIO_SX150X) += gpio-sx150x.o
19obj-$(CONFIG_GPIO_MAX732X) += max732x.o 49obj-$(CONFIG_GPIO_TC3589X) += gpio-tc3589x.o
20obj-$(CONFIG_GPIO_MC33880) += mc33880.o 50obj-$(CONFIG_ARCH_TEGRA) += gpio-tegra.o
21obj-$(CONFIG_GPIO_MCP23S08) += mcp23s08.o 51obj-$(CONFIG_GPIO_TIMBERDALE) += gpio-timberdale.o
22obj-$(CONFIG_GPIO_74X164) += 74x164.o 52obj-$(CONFIG_GPIO_TPS65910) += gpio-tps65910.o
23obj-$(CONFIG_ARCH_OMAP) += gpio-omap.o 53obj-$(CONFIG_GPIO_TPS65912) += gpio-tps65912.o
24obj-$(CONFIG_GPIO_PCA953X) += pca953x.o 54obj-$(CONFIG_GPIO_TWL4030) += gpio-twl4030.o
25obj-$(CONFIG_GPIO_PCF857X) += pcf857x.o
26obj-$(CONFIG_GPIO_PCH) += pch_gpio.o
27obj-$(CONFIG_GPIO_PL061) += pl061.o
28obj-$(CONFIG_GPIO_STMPE) += stmpe-gpio.o
29obj-$(CONFIG_GPIO_TC3589X) += tc3589x-gpio.o
30obj-$(CONFIG_GPIO_TIMBERDALE) += timbgpio.o
31obj-$(CONFIG_GPIO_TWL4030) += twl4030-gpio.o
32obj-$(CONFIG_GPIO_UCB1400) += ucb1400_gpio.o
33obj-$(CONFIG_GPIO_XILINX) += xilinx_gpio.o
34obj-$(CONFIG_GPIO_CS5535) += cs5535-gpio.o
35obj-$(CONFIG_GPIO_BT8XX) += bt8xxgpio.o
36obj-$(CONFIG_GPIO_IT8761E) += it8761e_gpio.o
37obj-$(CONFIG_GPIO_VR41XX) += vr41xx_giu.o
38obj-$(CONFIG_GPIO_WM831X) += wm831x-gpio.o
39obj-$(CONFIG_GPIO_WM8350) += wm8350-gpiolib.o
40obj-$(CONFIG_GPIO_WM8994) += wm8994-gpio.o
41obj-$(CONFIG_GPIO_SCH) += sch_gpio.o
42obj-$(CONFIG_MACH_U300) += gpio-u300.o 55obj-$(CONFIG_MACH_U300) += gpio-u300.o
43obj-$(CONFIG_PLAT_NOMADIK) += gpio-nomadik.o 56obj-$(CONFIG_GPIO_UCB1400) += gpio-ucb1400.o
44obj-$(CONFIG_GPIO_RDC321X) += rdc321x-gpio.o 57obj-$(CONFIG_GPIO_VR41XX) += gpio-vr41xx.o
45obj-$(CONFIG_GPIO_JANZ_TTL) += janz-ttl.o 58obj-$(CONFIG_GPIO_VX855) += gpio-vx855.o
46obj-$(CONFIG_GPIO_SX150X) += sx150x.o 59obj-$(CONFIG_GPIO_WM831X) += gpio-wm831x.o
47obj-$(CONFIG_GPIO_VX855) += vx855_gpio.o 60obj-$(CONFIG_GPIO_WM8350) += gpio-wm8350.o
48obj-$(CONFIG_GPIO_ML_IOH) += ml_ioh_gpio.o 61obj-$(CONFIG_GPIO_WM8994) += gpio-wm8994.o
49obj-$(CONFIG_AB8500_GPIO) += ab8500-gpio.o 62obj-$(CONFIG_GPIO_XILINX) += gpio-xilinx.o
50obj-$(CONFIG_GPIO_TPS65910) += tps65910-gpio.o
diff --git a/drivers/gpio/74x164.c b/drivers/gpio/gpio-74x164.c
index 84e07021983..ff525c0958d 100644
--- a/drivers/gpio/74x164.c
+++ b/drivers/gpio/gpio-74x164.c
@@ -16,9 +16,6 @@
16#include <linux/gpio.h> 16#include <linux/gpio.h>
17#include <linux/slab.h> 17#include <linux/slab.h>
18 18
19#define GEN_74X164_GPIO_COUNT 8
20
21
22struct gen_74x164_chip { 19struct gen_74x164_chip {
23 struct spi_device *spi; 20 struct spi_device *spi;
24 struct gpio_chip gpio_chip; 21 struct gpio_chip gpio_chip;
@@ -26,9 +23,7 @@ struct gen_74x164_chip {
26 u8 port_config; 23 u8 port_config;
27}; 24};
28 25
29static void gen_74x164_set_value(struct gpio_chip *, unsigned, int); 26static struct gen_74x164_chip *gpio_to_74x164_chip(struct gpio_chip *gc)
30
31static struct gen_74x164_chip *gpio_to_chip(struct gpio_chip *gc)
32{ 27{
33 return container_of(gc, struct gen_74x164_chip, gpio_chip); 28 return container_of(gc, struct gen_74x164_chip, gpio_chip);
34} 29}
@@ -39,16 +34,9 @@ static int __gen_74x164_write_config(struct gen_74x164_chip *chip)
39 &chip->port_config, sizeof(chip->port_config)); 34 &chip->port_config, sizeof(chip->port_config));
40} 35}
41 36
42static int gen_74x164_direction_output(struct gpio_chip *gc,
43 unsigned offset, int val)
44{
45 gen_74x164_set_value(gc, offset, val);
46 return 0;
47}
48
49static int gen_74x164_get_value(struct gpio_chip *gc, unsigned offset) 37static int gen_74x164_get_value(struct gpio_chip *gc, unsigned offset)
50{ 38{
51 struct gen_74x164_chip *chip = gpio_to_chip(gc); 39 struct gen_74x164_chip *chip = gpio_to_74x164_chip(gc);
52 int ret; 40 int ret;
53 41
54 mutex_lock(&chip->lock); 42 mutex_lock(&chip->lock);
@@ -61,7 +49,7 @@ static int gen_74x164_get_value(struct gpio_chip *gc, unsigned offset)
61static void gen_74x164_set_value(struct gpio_chip *gc, 49static void gen_74x164_set_value(struct gpio_chip *gc,
62 unsigned offset, int val) 50 unsigned offset, int val)
63{ 51{
64 struct gen_74x164_chip *chip = gpio_to_chip(gc); 52 struct gen_74x164_chip *chip = gpio_to_74x164_chip(gc);
65 53
66 mutex_lock(&chip->lock); 54 mutex_lock(&chip->lock);
67 if (val) 55 if (val)
@@ -73,6 +61,13 @@ static void gen_74x164_set_value(struct gpio_chip *gc,
73 mutex_unlock(&chip->lock); 61 mutex_unlock(&chip->lock);
74} 62}
75 63
64static int gen_74x164_direction_output(struct gpio_chip *gc,
65 unsigned offset, int val)
66{
67 gen_74x164_set_value(gc, offset, val);
68 return 0;
69}
70
76static int __devinit gen_74x164_probe(struct spi_device *spi) 71static int __devinit gen_74x164_probe(struct spi_device *spi)
77{ 72{
78 struct gen_74x164_chip *chip; 73 struct gen_74x164_chip *chip;
@@ -104,12 +99,12 @@ static int __devinit gen_74x164_probe(struct spi_device *spi)
104 99
105 chip->spi = spi; 100 chip->spi = spi;
106 101
107 chip->gpio_chip.label = GEN_74X164_DRIVER_NAME, 102 chip->gpio_chip.label = spi->modalias;
108 chip->gpio_chip.direction_output = gen_74x164_direction_output; 103 chip->gpio_chip.direction_output = gen_74x164_direction_output;
109 chip->gpio_chip.get = gen_74x164_get_value; 104 chip->gpio_chip.get = gen_74x164_get_value;
110 chip->gpio_chip.set = gen_74x164_set_value; 105 chip->gpio_chip.set = gen_74x164_set_value;
111 chip->gpio_chip.base = pdata->base; 106 chip->gpio_chip.base = pdata->base;
112 chip->gpio_chip.ngpio = GEN_74X164_GPIO_COUNT; 107 chip->gpio_chip.ngpio = 8;
113 chip->gpio_chip.can_sleep = 1; 108 chip->gpio_chip.can_sleep = 1;
114 chip->gpio_chip.dev = &spi->dev; 109 chip->gpio_chip.dev = &spi->dev;
115 chip->gpio_chip.owner = THIS_MODULE; 110 chip->gpio_chip.owner = THIS_MODULE;
@@ -157,7 +152,7 @@ static int __devexit gen_74x164_remove(struct spi_device *spi)
157 152
158static struct spi_driver gen_74x164_driver = { 153static struct spi_driver gen_74x164_driver = {
159 .driver = { 154 .driver = {
160 .name = GEN_74X164_DRIVER_NAME, 155 .name = "74x164",
161 .owner = THIS_MODULE, 156 .owner = THIS_MODULE,
162 }, 157 },
163 .probe = gen_74x164_probe, 158 .probe = gen_74x164_probe,
diff --git a/drivers/gpio/ab8500-gpio.c b/drivers/gpio/gpio-ab8500.c
index 970053c89ff..050c05d9189 100644
--- a/drivers/gpio/ab8500-gpio.c
+++ b/drivers/gpio/gpio-ab8500.c
@@ -15,7 +15,6 @@
15#include <linux/module.h> 15#include <linux/module.h>
16#include <linux/err.h> 16#include <linux/err.h>
17#include <linux/platform_device.h> 17#include <linux/platform_device.h>
18#include <linux/slab.h>
19#include <linux/gpio.h> 18#include <linux/gpio.h>
20#include <linux/irq.h> 19#include <linux/irq.h>
21#include <linux/interrupt.h> 20#include <linux/interrupt.h>
@@ -517,5 +516,5 @@ module_exit(ab8500_gpio_exit);
517 516
518MODULE_AUTHOR("BIBEK BASU <bibek.basu@stericsson.com>"); 517MODULE_AUTHOR("BIBEK BASU <bibek.basu@stericsson.com>");
519MODULE_DESCRIPTION("Driver allows to use AB8500 unused pins to be used as GPIO"); 518MODULE_DESCRIPTION("Driver allows to use AB8500 unused pins to be used as GPIO");
520MODULE_ALIAS("AB8500 GPIO driver"); 519MODULE_ALIAS("platform:ab8500-gpio");
521MODULE_LICENSE("GPL v2"); 520MODULE_LICENSE("GPL v2");
diff --git a/drivers/gpio/adp5520-gpio.c b/drivers/gpio/gpio-adp5520.c
index 9f278153700..9f278153700 100644
--- a/drivers/gpio/adp5520-gpio.c
+++ b/drivers/gpio/gpio-adp5520.c
diff --git a/drivers/gpio/adp5588-gpio.c b/drivers/gpio/gpio-adp5588.c
index 3525ad91877..3525ad91877 100644
--- a/drivers/gpio/adp5588-gpio.c
+++ b/drivers/gpio/gpio-adp5588.c
diff --git a/drivers/gpio/bt8xxgpio.c b/drivers/gpio/gpio-bt8xx.c
index aa4f09ad3ce..ec57936aef6 100644
--- a/drivers/gpio/bt8xxgpio.c
+++ b/drivers/gpio/gpio-bt8xx.c
@@ -2,7 +2,7 @@
2 2
3 bt8xx GPIO abuser 3 bt8xx GPIO abuser
4 4
5 Copyright (C) 2008 Michael Buesch <mb@bu3sch.de> 5 Copyright (C) 2008 Michael Buesch <m@bues.ch>
6 6
7 Please do _only_ contact the people listed _above_ with issues related to this driver. 7 Please do _only_ contact the people listed _above_ with issues related to this driver.
8 All the other people listed below are not related to this driver. Their names 8 All the other people listed below are not related to this driver. Their names
diff --git a/drivers/gpio/cs5535-gpio.c b/drivers/gpio/gpio-cs5535.c
index 6e16cba56ad..6e16cba56ad 100644
--- a/drivers/gpio/cs5535-gpio.c
+++ b/drivers/gpio/gpio-cs5535.c
diff --git a/drivers/gpio/gpio-da9052.c b/drivers/gpio/gpio-da9052.c
new file mode 100644
index 00000000000..038f5eb8b13
--- /dev/null
+++ b/drivers/gpio/gpio-da9052.c
@@ -0,0 +1,277 @@
1/*
2 * GPIO Driver for Dialog DA9052 PMICs.
3 *
4 * Copyright(c) 2011 Dialog Semiconductor Ltd.
5 *
6 * Author: David Dajun Chen <dchen@diasemi.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 */
14#include <linux/module.h>
15#include <linux/fs.h>
16#include <linux/uaccess.h>
17#include <linux/platform_device.h>
18#include <linux/gpio.h>
19#include <linux/syscalls.h>
20#include <linux/seq_file.h>
21
22#include <linux/mfd/da9052/da9052.h>
23#include <linux/mfd/da9052/reg.h>
24#include <linux/mfd/da9052/pdata.h>
25#include <linux/mfd/da9052/gpio.h>
26
27#define DA9052_INPUT 1
28#define DA9052_OUTPUT_OPENDRAIN 2
29#define DA9052_OUTPUT_PUSHPULL 3
30
31#define DA9052_SUPPLY_VDD_IO1 0
32
33#define DA9052_DEBOUNCING_OFF 0
34#define DA9052_DEBOUNCING_ON 1
35
36#define DA9052_OUTPUT_LOWLEVEL 0
37
38#define DA9052_ACTIVE_LOW 0
39#define DA9052_ACTIVE_HIGH 1
40
41#define DA9052_GPIO_MAX_PORTS_PER_REGISTER 8
42#define DA9052_GPIO_SHIFT_COUNT(no) (no%8)
43#define DA9052_GPIO_MASK_UPPER_NIBBLE 0xF0
44#define DA9052_GPIO_MASK_LOWER_NIBBLE 0x0F
45#define DA9052_GPIO_NIBBLE_SHIFT 4
46
47struct da9052_gpio {
48 struct da9052 *da9052;
49 struct gpio_chip gp;
50};
51
52static inline struct da9052_gpio *to_da9052_gpio(struct gpio_chip *chip)
53{
54 return container_of(chip, struct da9052_gpio, gp);
55}
56
57static unsigned char da9052_gpio_port_odd(unsigned offset)
58{
59 return offset % 2;
60}
61
62static int da9052_gpio_get(struct gpio_chip *gc, unsigned offset)
63{
64 struct da9052_gpio *gpio = to_da9052_gpio(gc);
65 int da9052_port_direction = 0;
66 int ret;
67
68 ret = da9052_reg_read(gpio->da9052,
69 DA9052_GPIO_0_1_REG + (offset >> 1));
70 if (ret < 0)
71 return ret;
72
73 if (da9052_gpio_port_odd(offset)) {
74 da9052_port_direction = ret & DA9052_GPIO_ODD_PORT_PIN;
75 da9052_port_direction >>= 4;
76 } else {
77 da9052_port_direction = ret & DA9052_GPIO_EVEN_PORT_PIN;
78 }
79
80 switch (da9052_port_direction) {
81 case DA9052_INPUT:
82 if (offset < DA9052_GPIO_MAX_PORTS_PER_REGISTER)
83 ret = da9052_reg_read(gpio->da9052,
84 DA9052_STATUS_C_REG);
85 else
86 ret = da9052_reg_read(gpio->da9052,
87 DA9052_STATUS_D_REG);
88 if (ret < 0)
89 return ret;
90 if (ret & (1 << DA9052_GPIO_SHIFT_COUNT(offset)))
91 return 1;
92 else
93 return 0;
94 case DA9052_OUTPUT_PUSHPULL:
95 if (da9052_gpio_port_odd(offset))
96 return ret & DA9052_GPIO_ODD_PORT_MODE;
97 else
98 return ret & DA9052_GPIO_EVEN_PORT_MODE;
99 default:
100 return -EINVAL;
101 }
102}
103
104static void da9052_gpio_set(struct gpio_chip *gc, unsigned offset, int value)
105{
106 struct da9052_gpio *gpio = to_da9052_gpio(gc);
107 unsigned char register_value = 0;
108 int ret;
109
110 if (da9052_gpio_port_odd(offset)) {
111 if (value) {
112 register_value = DA9052_GPIO_ODD_PORT_MODE;
113 ret = da9052_reg_update(gpio->da9052, (offset >> 1) +
114 DA9052_GPIO_0_1_REG,
115 DA9052_GPIO_ODD_PORT_MODE,
116 register_value);
117 if (ret != 0)
118 dev_err(gpio->da9052->dev,
119 "Failed to updated gpio odd reg,%d",
120 ret);
121 }
122 } else {
123 if (value) {
124 register_value = DA9052_GPIO_EVEN_PORT_MODE;
125 ret = da9052_reg_update(gpio->da9052, (offset >> 1) +
126 DA9052_GPIO_0_1_REG,
127 DA9052_GPIO_EVEN_PORT_MODE,
128 register_value);
129 if (ret != 0)
130 dev_err(gpio->da9052->dev,
131 "Failed to updated gpio even reg,%d",
132 ret);
133 }
134 }
135}
136
137static int da9052_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
138{
139 struct da9052_gpio *gpio = to_da9052_gpio(gc);
140 unsigned char register_value;
141 int ret;
142
143 /* Format: function - 2 bits type - 1 bit mode - 1 bit */
144 register_value = DA9052_INPUT | DA9052_ACTIVE_LOW << 2 |
145 DA9052_DEBOUNCING_ON << 3;
146
147 if (da9052_gpio_port_odd(offset))
148 ret = da9052_reg_update(gpio->da9052, (offset >> 1) +
149 DA9052_GPIO_0_1_REG,
150 DA9052_GPIO_MASK_UPPER_NIBBLE,
151 (register_value <<
152 DA9052_GPIO_NIBBLE_SHIFT));
153 else
154 ret = da9052_reg_update(gpio->da9052, (offset >> 1) +
155 DA9052_GPIO_0_1_REG,
156 DA9052_GPIO_MASK_LOWER_NIBBLE,
157 register_value);
158
159 return ret;
160}
161
162static int da9052_gpio_direction_output(struct gpio_chip *gc,
163 unsigned offset, int value)
164{
165 struct da9052_gpio *gpio = to_da9052_gpio(gc);
166 unsigned char register_value;
167 int ret;
168
169 /* Format: Function - 2 bits Type - 1 bit Mode - 1 bit */
170 register_value = DA9052_OUTPUT_PUSHPULL | DA9052_SUPPLY_VDD_IO1 << 2 |
171 value << 3;
172
173 if (da9052_gpio_port_odd(offset))
174 ret = da9052_reg_update(gpio->da9052, (offset >> 1) +
175 DA9052_GPIO_0_1_REG,
176 DA9052_GPIO_MASK_UPPER_NIBBLE,
177 (register_value <<
178 DA9052_GPIO_NIBBLE_SHIFT));
179 else
180 ret = da9052_reg_update(gpio->da9052, (offset >> 1) +
181 DA9052_GPIO_0_1_REG,
182 DA9052_GPIO_MASK_LOWER_NIBBLE,
183 register_value);
184
185 return ret;
186}
187
188static int da9052_gpio_to_irq(struct gpio_chip *gc, u32 offset)
189{
190 struct da9052_gpio *gpio = to_da9052_gpio(gc);
191 struct da9052 *da9052 = gpio->da9052;
192
193 return da9052->irq_base + DA9052_IRQ_GPI0 + offset;
194}
195
196static struct gpio_chip reference_gp __devinitdata = {
197 .label = "da9052-gpio",
198 .owner = THIS_MODULE,
199 .get = da9052_gpio_get,
200 .set = da9052_gpio_set,
201 .direction_input = da9052_gpio_direction_input,
202 .direction_output = da9052_gpio_direction_output,
203 .to_irq = da9052_gpio_to_irq,
204 .can_sleep = 1;
205 .ngpio = 16;
206 .base = -1;
207};
208
209static int __devinit da9052_gpio_probe(struct platform_device *pdev)
210{
211 struct da9052_gpio *gpio;
212 struct da9052_pdata *pdata;
213 int ret;
214
215 gpio = kzalloc(sizeof(*gpio), GFP_KERNEL);
216 if (gpio == NULL)
217 return -ENOMEM;
218
219 gpio->da9052 = dev_get_drvdata(pdev->dev.parent);
220 pdata = gpio->da9052->dev->platform_data;
221
222 gpio->gp = reference_gp;
223 if (pdata && pdata->gpio_base)
224 gpio->gp.base = pdata->gpio_base;
225
226 ret = gpiochip_add(&gpio->gp);
227 if (ret < 0) {
228 dev_err(&pdev->dev, "Could not register gpiochip, %d\n", ret);
229 goto err_mem;
230 }
231
232 platform_set_drvdata(pdev, gpio);
233
234 return 0;
235
236err_mem:
237 kfree(gpio);
238 return ret;
239}
240
241static int __devexit da9052_gpio_remove(struct platform_device *pdev)
242{
243 struct da9052_gpio *gpio = platform_get_drvdata(pdev);
244 int ret;
245
246 ret = gpiochip_remove(&gpio->gp);
247 if (ret == 0)
248 kfree(gpio);
249
250 return ret;
251}
252
253static struct platform_driver da9052_gpio_driver = {
254 .probe = da9052_gpio_probe,
255 .remove = __devexit_p(da9052_gpio_remove),
256 .driver = {
257 .name = "da9052-gpio",
258 .owner = THIS_MODULE,
259 },
260};
261
262static int __init da9052_gpio_init(void)
263{
264 return platform_driver_register(&da9052_gpio_driver);
265}
266module_init(da9052_gpio_init);
267
268static void __exit da9052_gpio_exit(void)
269{
270 return platform_driver_unregister(&da9052_gpio_driver);
271}
272module_exit(da9052_gpio_exit);
273
274MODULE_AUTHOR("David Dajun Chen <dchen@diasemi.com>");
275MODULE_DESCRIPTION("DA9052 GPIO Device Driver");
276MODULE_LICENSE("GPL");
277MODULE_ALIAS("platform:da9052-gpio");
diff --git a/drivers/gpio/gpio-ep93xx.c b/drivers/gpio/gpio-ep93xx.c
new file mode 100644
index 00000000000..72fb9c66532
--- /dev/null
+++ b/drivers/gpio/gpio-ep93xx.c
@@ -0,0 +1,405 @@
1/*
2 * Generic EP93xx GPIO handling
3 *
4 * Copyright (c) 2008 Ryan Mallon
5 * Copyright (c) 2011 H Hartley Sweeten <hsweeten@visionengravers.com>
6 *
7 * Based on code originally from:
8 * linux/arch/arm/mach-ep93xx/core.c
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
16
17#include <linux/init.h>
18#include <linux/platform_device.h>
19#include <linux/io.h>
20#include <linux/gpio.h>
21#include <linux/irq.h>
22#include <linux/slab.h>
23#include <linux/basic_mmio_gpio.h>
24
25#include <mach/hardware.h>
26
27struct ep93xx_gpio {
28 void __iomem *mmio_base;
29 struct bgpio_chip bgc[8];
30};
31
32/*************************************************************************
33 * Interrupt handling for EP93xx on-chip GPIOs
34 *************************************************************************/
35static unsigned char gpio_int_unmasked[3];
36static unsigned char gpio_int_enabled[3];
37static unsigned char gpio_int_type1[3];
38static unsigned char gpio_int_type2[3];
39static unsigned char gpio_int_debounce[3];
40
41/* Port ordering is: A B F */
42static const u8 int_type1_register_offset[3] = { 0x90, 0xac, 0x4c };
43static const u8 int_type2_register_offset[3] = { 0x94, 0xb0, 0x50 };
44static const u8 eoi_register_offset[3] = { 0x98, 0xb4, 0x54 };
45static const u8 int_en_register_offset[3] = { 0x9c, 0xb8, 0x58 };
46static const u8 int_debounce_register_offset[3] = { 0xa8, 0xc4, 0x64 };
47
48static void ep93xx_gpio_update_int_params(unsigned port)
49{
50 BUG_ON(port > 2);
51
52 __raw_writeb(0, EP93XX_GPIO_REG(int_en_register_offset[port]));
53
54 __raw_writeb(gpio_int_type2[port],
55 EP93XX_GPIO_REG(int_type2_register_offset[port]));
56
57 __raw_writeb(gpio_int_type1[port],
58 EP93XX_GPIO_REG(int_type1_register_offset[port]));
59
60 __raw_writeb(gpio_int_unmasked[port] & gpio_int_enabled[port],
61 EP93XX_GPIO_REG(int_en_register_offset[port]));
62}
63
64static inline void ep93xx_gpio_int_mask(unsigned line)
65{
66 gpio_int_unmasked[line >> 3] &= ~(1 << (line & 7));
67}
68
69static void ep93xx_gpio_int_debounce(unsigned int irq, bool enable)
70{
71 int line = irq_to_gpio(irq);
72 int port = line >> 3;
73 int port_mask = 1 << (line & 7);
74
75 if (enable)
76 gpio_int_debounce[port] |= port_mask;
77 else
78 gpio_int_debounce[port] &= ~port_mask;
79
80 __raw_writeb(gpio_int_debounce[port],
81 EP93XX_GPIO_REG(int_debounce_register_offset[port]));
82}
83
84static void ep93xx_gpio_ab_irq_handler(unsigned int irq, struct irq_desc *desc)
85{
86 unsigned char status;
87 int i;
88
89 status = __raw_readb(EP93XX_GPIO_A_INT_STATUS);
90 for (i = 0; i < 8; i++) {
91 if (status & (1 << i)) {
92 int gpio_irq = gpio_to_irq(EP93XX_GPIO_LINE_A(0)) + i;
93 generic_handle_irq(gpio_irq);
94 }
95 }
96
97 status = __raw_readb(EP93XX_GPIO_B_INT_STATUS);
98 for (i = 0; i < 8; i++) {
99 if (status & (1 << i)) {
100 int gpio_irq = gpio_to_irq(EP93XX_GPIO_LINE_B(0)) + i;
101 generic_handle_irq(gpio_irq);
102 }
103 }
104}
105
106static void ep93xx_gpio_f_irq_handler(unsigned int irq, struct irq_desc *desc)
107{
108 /*
109 * map discontiguous hw irq range to continuous sw irq range:
110 *
111 * IRQ_EP93XX_GPIO{0..7}MUX -> gpio_to_irq(EP93XX_GPIO_LINE_F({0..7})
112 */
113 int port_f_idx = ((irq + 1) & 7) ^ 4; /* {19..22,47..50} -> {0..7} */
114 int gpio_irq = gpio_to_irq(EP93XX_GPIO_LINE_F(0)) + port_f_idx;
115
116 generic_handle_irq(gpio_irq);
117}
118
119static void ep93xx_gpio_irq_ack(struct irq_data *d)
120{
121 int line = irq_to_gpio(d->irq);
122 int port = line >> 3;
123 int port_mask = 1 << (line & 7);
124
125 if (irqd_get_trigger_type(d) == IRQ_TYPE_EDGE_BOTH) {
126 gpio_int_type2[port] ^= port_mask; /* switch edge direction */
127 ep93xx_gpio_update_int_params(port);
128 }
129
130 __raw_writeb(port_mask, EP93XX_GPIO_REG(eoi_register_offset[port]));
131}
132
133static void ep93xx_gpio_irq_mask_ack(struct irq_data *d)
134{
135 int line = irq_to_gpio(d->irq);
136 int port = line >> 3;
137 int port_mask = 1 << (line & 7);
138
139 if (irqd_get_trigger_type(d) == IRQ_TYPE_EDGE_BOTH)
140 gpio_int_type2[port] ^= port_mask; /* switch edge direction */
141
142 gpio_int_unmasked[port] &= ~port_mask;
143 ep93xx_gpio_update_int_params(port);
144
145 __raw_writeb(port_mask, EP93XX_GPIO_REG(eoi_register_offset[port]));
146}
147
148static void ep93xx_gpio_irq_mask(struct irq_data *d)
149{
150 int line = irq_to_gpio(d->irq);
151 int port = line >> 3;
152
153 gpio_int_unmasked[port] &= ~(1 << (line & 7));
154 ep93xx_gpio_update_int_params(port);
155}
156
157static void ep93xx_gpio_irq_unmask(struct irq_data *d)
158{
159 int line = irq_to_gpio(d->irq);
160 int port = line >> 3;
161
162 gpio_int_unmasked[port] |= 1 << (line & 7);
163 ep93xx_gpio_update_int_params(port);
164}
165
166/*
167 * gpio_int_type1 controls whether the interrupt is level (0) or
168 * edge (1) triggered, while gpio_int_type2 controls whether it
169 * triggers on low/falling (0) or high/rising (1).
170 */
171static int ep93xx_gpio_irq_type(struct irq_data *d, unsigned int type)
172{
173 const int gpio = irq_to_gpio(d->irq);
174 const int port = gpio >> 3;
175 const int port_mask = 1 << (gpio & 7);
176 irq_flow_handler_t handler;
177
178 gpio_direction_input(gpio);
179
180 switch (type) {
181 case IRQ_TYPE_EDGE_RISING:
182 gpio_int_type1[port] |= port_mask;
183 gpio_int_type2[port] |= port_mask;
184 handler = handle_edge_irq;
185 break;
186 case IRQ_TYPE_EDGE_FALLING:
187 gpio_int_type1[port] |= port_mask;
188 gpio_int_type2[port] &= ~port_mask;
189 handler = handle_edge_irq;
190 break;
191 case IRQ_TYPE_LEVEL_HIGH:
192 gpio_int_type1[port] &= ~port_mask;
193 gpio_int_type2[port] |= port_mask;
194 handler = handle_level_irq;
195 break;
196 case IRQ_TYPE_LEVEL_LOW:
197 gpio_int_type1[port] &= ~port_mask;
198 gpio_int_type2[port] &= ~port_mask;
199 handler = handle_level_irq;
200 break;
201 case IRQ_TYPE_EDGE_BOTH:
202 gpio_int_type1[port] |= port_mask;
203 /* set initial polarity based on current input level */
204 if (gpio_get_value(gpio))
205 gpio_int_type2[port] &= ~port_mask; /* falling */
206 else
207 gpio_int_type2[port] |= port_mask; /* rising */
208 handler = handle_edge_irq;
209 break;
210 default:
211 pr_err("failed to set irq type %d for gpio %d\n", type, gpio);
212 return -EINVAL;
213 }
214
215 __irq_set_handler_locked(d->irq, handler);
216
217 gpio_int_enabled[port] |= port_mask;
218
219 ep93xx_gpio_update_int_params(port);
220
221 return 0;
222}
223
224static struct irq_chip ep93xx_gpio_irq_chip = {
225 .name = "GPIO",
226 .irq_ack = ep93xx_gpio_irq_ack,
227 .irq_mask_ack = ep93xx_gpio_irq_mask_ack,
228 .irq_mask = ep93xx_gpio_irq_mask,
229 .irq_unmask = ep93xx_gpio_irq_unmask,
230 .irq_set_type = ep93xx_gpio_irq_type,
231};
232
233static void ep93xx_gpio_init_irq(void)
234{
235 int gpio_irq;
236
237 for (gpio_irq = gpio_to_irq(0);
238 gpio_irq <= gpio_to_irq(EP93XX_GPIO_LINE_MAX_IRQ); ++gpio_irq) {
239 irq_set_chip_and_handler(gpio_irq, &ep93xx_gpio_irq_chip,
240 handle_level_irq);
241 set_irq_flags(gpio_irq, IRQF_VALID);
242 }
243
244 irq_set_chained_handler(IRQ_EP93XX_GPIO_AB,
245 ep93xx_gpio_ab_irq_handler);
246 irq_set_chained_handler(IRQ_EP93XX_GPIO0MUX,
247 ep93xx_gpio_f_irq_handler);
248 irq_set_chained_handler(IRQ_EP93XX_GPIO1MUX,
249 ep93xx_gpio_f_irq_handler);
250 irq_set_chained_handler(IRQ_EP93XX_GPIO2MUX,
251 ep93xx_gpio_f_irq_handler);
252 irq_set_chained_handler(IRQ_EP93XX_GPIO3MUX,
253 ep93xx_gpio_f_irq_handler);
254 irq_set_chained_handler(IRQ_EP93XX_GPIO4MUX,
255 ep93xx_gpio_f_irq_handler);
256 irq_set_chained_handler(IRQ_EP93XX_GPIO5MUX,
257 ep93xx_gpio_f_irq_handler);
258 irq_set_chained_handler(IRQ_EP93XX_GPIO6MUX,
259 ep93xx_gpio_f_irq_handler);
260 irq_set_chained_handler(IRQ_EP93XX_GPIO7MUX,
261 ep93xx_gpio_f_irq_handler);
262}
263
264
265/*************************************************************************
266 * gpiolib interface for EP93xx on-chip GPIOs
267 *************************************************************************/
268struct ep93xx_gpio_bank {
269 const char *label;
270 int data;
271 int dir;
272 int base;
273 bool has_debounce;
274};
275
276#define EP93XX_GPIO_BANK(_label, _data, _dir, _base, _debounce) \
277 { \
278 .label = _label, \
279 .data = _data, \
280 .dir = _dir, \
281 .base = _base, \
282 .has_debounce = _debounce, \
283 }
284
285static struct ep93xx_gpio_bank ep93xx_gpio_banks[] = {
286 EP93XX_GPIO_BANK("A", 0x00, 0x10, 0, true),
287 EP93XX_GPIO_BANK("B", 0x04, 0x14, 8, true),
288 EP93XX_GPIO_BANK("C", 0x08, 0x18, 40, false),
289 EP93XX_GPIO_BANK("D", 0x0c, 0x1c, 24, false),
290 EP93XX_GPIO_BANK("E", 0x20, 0x24, 32, false),
291 EP93XX_GPIO_BANK("F", 0x30, 0x34, 16, true),
292 EP93XX_GPIO_BANK("G", 0x38, 0x3c, 48, false),
293 EP93XX_GPIO_BANK("H", 0x40, 0x44, 56, false),
294};
295
296static int ep93xx_gpio_set_debounce(struct gpio_chip *chip,
297 unsigned offset, unsigned debounce)
298{
299 int gpio = chip->base + offset;
300 int irq = gpio_to_irq(gpio);
301
302 if (irq < 0)
303 return -EINVAL;
304
305 ep93xx_gpio_int_debounce(irq, debounce ? true : false);
306
307 return 0;
308}
309
310static int ep93xx_gpio_add_bank(struct bgpio_chip *bgc, struct device *dev,
311 void __iomem *mmio_base, struct ep93xx_gpio_bank *bank)
312{
313 void __iomem *data = mmio_base + bank->data;
314 void __iomem *dir = mmio_base + bank->dir;
315 int err;
316
317 err = bgpio_init(bgc, dev, 1, data, NULL, NULL, dir, NULL, false);
318 if (err)
319 return err;
320
321 bgc->gc.label = bank->label;
322 bgc->gc.base = bank->base;
323
324 if (bank->has_debounce)
325 bgc->gc.set_debounce = ep93xx_gpio_set_debounce;
326
327 return gpiochip_add(&bgc->gc);
328}
329
330static int __devinit ep93xx_gpio_probe(struct platform_device *pdev)
331{
332 struct ep93xx_gpio *ep93xx_gpio;
333 struct resource *res;
334 void __iomem *mmio;
335 int i;
336 int ret;
337
338 ep93xx_gpio = kzalloc(sizeof(*ep93xx_gpio), GFP_KERNEL);
339 if (!ep93xx_gpio)
340 return -ENOMEM;
341
342 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
343 if (!res) {
344 ret = -ENXIO;
345 goto exit_free;
346 }
347
348 if (!request_mem_region(res->start, resource_size(res), pdev->name)) {
349 ret = -EBUSY;
350 goto exit_free;
351 }
352
353 mmio = ioremap(res->start, resource_size(res));
354 if (!mmio) {
355 ret = -ENXIO;
356 goto exit_release;
357 }
358 ep93xx_gpio->mmio_base = mmio;
359
360 /* Default all ports to GPIO */
361 ep93xx_devcfg_set_bits(EP93XX_SYSCON_DEVCFG_KEYS |
362 EP93XX_SYSCON_DEVCFG_GONK |
363 EP93XX_SYSCON_DEVCFG_EONIDE |
364 EP93XX_SYSCON_DEVCFG_GONIDE |
365 EP93XX_SYSCON_DEVCFG_HONIDE);
366
367 for (i = 0; i < ARRAY_SIZE(ep93xx_gpio_banks); i++) {
368 struct bgpio_chip *bgc = &ep93xx_gpio->bgc[i];
369 struct ep93xx_gpio_bank *bank = &ep93xx_gpio_banks[i];
370
371 if (ep93xx_gpio_add_bank(bgc, &pdev->dev, mmio, bank))
372 dev_warn(&pdev->dev, "Unable to add gpio bank %s\n",
373 bank->label);
374 }
375
376 ep93xx_gpio_init_irq();
377
378 return 0;
379
380exit_release:
381 release_mem_region(res->start, resource_size(res));
382exit_free:
383 kfree(ep93xx_gpio);
384 dev_info(&pdev->dev, "%s failed with errno %d\n", __func__, ret);
385 return ret;
386}
387
388static struct platform_driver ep93xx_gpio_driver = {
389 .driver = {
390 .name = "gpio-ep93xx",
391 .owner = THIS_MODULE,
392 },
393 .probe = ep93xx_gpio_probe,
394};
395
396static int __init ep93xx_gpio_init(void)
397{
398 return platform_driver_register(&ep93xx_gpio_driver);
399}
400postcore_initcall(ep93xx_gpio_init);
401
402MODULE_AUTHOR("Ryan Mallon <ryan@bluewatersys.com> "
403 "H Hartley Sweeten <hsweeten@visionengravers.com>");
404MODULE_DESCRIPTION("EP93XX GPIO driver");
405MODULE_LICENSE("GPL");
diff --git a/drivers/gpio/gpio-exynos4.c b/drivers/gpio/gpio-exynos4.c
index 9029835112e..d24b337cf1a 100644
--- a/drivers/gpio/gpio-exynos4.c
+++ b/drivers/gpio/gpio-exynos4.c
@@ -1,10 +1,9 @@
1/* linux/arch/arm/mach-exynos4/gpiolib.c 1/*
2 * EXYNOS4 - GPIOlib support
2 * 3 *
3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. 4 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com 5 * http://www.samsung.com
5 * 6 *
6 * EXYNOS4 - GPIOlib support
7 *
8 * This program is free software; you can redistribute it and/or modify 7 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as 8 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation. 9 * published by the Free Software Foundation.
diff --git a/drivers/gpio/basic_mmio_gpio.c b/drivers/gpio/gpio-generic.c
index 8152e9f516b..4e24436b0f8 100644
--- a/drivers/gpio/basic_mmio_gpio.c
+++ b/drivers/gpio/gpio-generic.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * Driver for basic memory-mapped GPIO controllers. 2 * Generic driver for memory-mapped GPIO controllers.
3 * 3 *
4 * Copyright 2008 MontaVista Software, Inc. 4 * Copyright 2008 MontaVista Software, Inc.
5 * Copyright 2008,2010 Anton Vorontsov <cbouatmailru@gmail.com> 5 * Copyright 2008,2010 Anton Vorontsov <cbouatmailru@gmail.com>
@@ -351,7 +351,7 @@ static int bgpio_setup_direction(struct bgpio_chip *bgc,
351 return 0; 351 return 0;
352} 352}
353 353
354int __devexit bgpio_remove(struct bgpio_chip *bgc) 354int bgpio_remove(struct bgpio_chip *bgc)
355{ 355{
356 int err = gpiochip_remove(&bgc->gc); 356 int err = gpiochip_remove(&bgc->gc);
357 357
@@ -361,15 +361,10 @@ int __devexit bgpio_remove(struct bgpio_chip *bgc)
361} 361}
362EXPORT_SYMBOL_GPL(bgpio_remove); 362EXPORT_SYMBOL_GPL(bgpio_remove);
363 363
364int __devinit bgpio_init(struct bgpio_chip *bgc, 364int bgpio_init(struct bgpio_chip *bgc, struct device *dev,
365 struct device *dev, 365 unsigned long sz, void __iomem *dat, void __iomem *set,
366 unsigned long sz, 366 void __iomem *clr, void __iomem *dirout, void __iomem *dirin,
367 void __iomem *dat, 367 bool big_endian)
368 void __iomem *set,
369 void __iomem *clr,
370 void __iomem *dirout,
371 void __iomem *dirin,
372 bool big_endian)
373{ 368{
374 int ret; 369 int ret;
375 370
@@ -404,7 +399,7 @@ int __devinit bgpio_init(struct bgpio_chip *bgc,
404} 399}
405EXPORT_SYMBOL_GPL(bgpio_init); 400EXPORT_SYMBOL_GPL(bgpio_init);
406 401
407#ifdef CONFIG_GPIO_BASIC_MMIO 402#ifdef CONFIG_GPIO_GENERIC_PLATFORM
408 403
409static void __iomem *bgpio_map(struct platform_device *pdev, 404static void __iomem *bgpio_map(struct platform_device *pdev,
410 const char *name, 405 const char *name,
@@ -541,7 +536,7 @@ static void __exit bgpio_platform_exit(void)
541} 536}
542module_exit(bgpio_platform_exit); 537module_exit(bgpio_platform_exit);
543 538
544#endif /* CONFIG_GPIO_BASIC_MMIO */ 539#endif /* CONFIG_GPIO_GENERIC_PLATFORM */
545 540
546MODULE_DESCRIPTION("Driver for basic memory-mapped GPIO controllers"); 541MODULE_DESCRIPTION("Driver for basic memory-mapped GPIO controllers");
547MODULE_AUTHOR("Anton Vorontsov <cbouatmailru@gmail.com>"); 542MODULE_AUTHOR("Anton Vorontsov <cbouatmailru@gmail.com>");
diff --git a/drivers/gpio/it8761e_gpio.c b/drivers/gpio/gpio-it8761e.c
index 48fc43c4bdd..278b8131701 100644
--- a/drivers/gpio/it8761e_gpio.c
+++ b/drivers/gpio/gpio-it8761e.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * it8761_gpio.c - GPIO interface for IT8761E Super I/O chip 2 * GPIO interface for IT8761E Super I/O chip
3 * 3 *
4 * Author: Denis Turischev <denis@compulab.co.il> 4 * Author: Denis Turischev <denis@compulab.co.il>
5 * 5 *
diff --git a/drivers/gpio/janz-ttl.c b/drivers/gpio/gpio-janz-ttl.c
index 813ac077e5d..813ac077e5d 100644
--- a/drivers/gpio/janz-ttl.c
+++ b/drivers/gpio/gpio-janz-ttl.c
diff --git a/drivers/gpio/langwell_gpio.c b/drivers/gpio/gpio-langwell.c
index 644ba1255d3..d2eb57c60e0 100644
--- a/drivers/gpio/langwell_gpio.c
+++ b/drivers/gpio/gpio-langwell.c
@@ -1,4 +1,6 @@
1/* langwell_gpio.c Moorestown platform Langwell chip GPIO driver 1/*
2 * Moorestown platform Langwell chip GPIO driver
3 *
2 * Copyright (c) 2008 - 2009, Intel Corporation. 4 * Copyright (c) 2008 - 2009, Intel Corporation.
3 * 5 *
4 * This program is free software; you can redistribute it and/or modify 6 * This program is free software; you can redistribute it and/or modify
diff --git a/drivers/gpio/max7300.c b/drivers/gpio/gpio-max7300.c
index 962f661c18c..a5ca0ab1b37 100644
--- a/drivers/gpio/max7300.c
+++ b/drivers/gpio/gpio-max7300.c
@@ -1,6 +1,4 @@
1/* 1/*
2 * drivers/gpio/max7300.c
3 *
4 * Copyright (C) 2009 Wolfram Sang, Pengutronix 2 * Copyright (C) 2009 Wolfram Sang, Pengutronix
5 * 3 *
6 * This program is free software; you can redistribute it and/or modify 4 * This program is free software; you can redistribute it and/or modify
diff --git a/drivers/gpio/max7301.c b/drivers/gpio/gpio-max7301.c
index 92a100ddef6..741acfcbe76 100644
--- a/drivers/gpio/max7301.c
+++ b/drivers/gpio/gpio-max7301.c
@@ -1,6 +1,4 @@
1/* 1/*
2 * drivers/gpio/max7301.c
3 *
4 * Copyright (C) 2006 Juergen Beisert, Pengutronix 2 * Copyright (C) 2006 Juergen Beisert, Pengutronix
5 * Copyright (C) 2008 Guennadi Liakhovetski, Pengutronix 3 * Copyright (C) 2008 Guennadi Liakhovetski, Pengutronix
6 * Copyright (C) 2009 Wolfram Sang, Pengutronix 4 * Copyright (C) 2009 Wolfram Sang, Pengutronix
diff --git a/drivers/gpio/max730x.c b/drivers/gpio/gpio-max730x.c
index 94ce773f95f..05e2dac60b3 100644
--- a/drivers/gpio/max730x.c
+++ b/drivers/gpio/gpio-max730x.c
@@ -1,6 +1,4 @@
1/** 1/**
2 * drivers/gpio/max7301.c
3 *
4 * Copyright (C) 2006 Juergen Beisert, Pengutronix 2 * Copyright (C) 2006 Juergen Beisert, Pengutronix
5 * Copyright (C) 2008 Guennadi Liakhovetski, Pengutronix 3 * Copyright (C) 2008 Guennadi Liakhovetski, Pengutronix
6 * Copyright (C) 2009 Wolfram Sang, Pengutronix 4 * Copyright (C) 2009 Wolfram Sang, Pengutronix
diff --git a/drivers/gpio/max732x.c b/drivers/gpio/gpio-max732x.c
index ad6951edc16..9504120812a 100644
--- a/drivers/gpio/max732x.c
+++ b/drivers/gpio/gpio-max732x.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * max732x.c - I2C Port Expander with 8/16 I/O 2 * MAX732x I2C Port Expander with 8/16 I/O
3 * 3 *
4 * Copyright (C) 2007 Marvell International Ltd. 4 * Copyright (C) 2007 Marvell International Ltd.
5 * Copyright (C) 2008 Jack Ren <jack.ren@marvell.com> 5 * Copyright (C) 2008 Jack Ren <jack.ren@marvell.com>
diff --git a/drivers/gpio/mc33880.c b/drivers/gpio/gpio-mc33880.c
index 4ec797593bd..b3b4652e89e 100644
--- a/drivers/gpio/mc33880.c
+++ b/drivers/gpio/gpio-mc33880.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * mc33880.c MC33880 high-side/low-side switch GPIO driver 2 * MC33880 high-side/low-side switch GPIO driver
3 * Copyright (c) 2009 Intel Corporation 3 * Copyright (c) 2009 Intel Corporation
4 * 4 *
5 * This program is free software; you can redistribute it and/or modify 5 * This program is free software; you can redistribute it and/or modify
diff --git a/drivers/gpio/mcp23s08.c b/drivers/gpio/gpio-mcp23s08.c
index 40e076083ec..1ef46e6c2a2 100644
--- a/drivers/gpio/mcp23s08.c
+++ b/drivers/gpio/gpio-mcp23s08.c
@@ -1,12 +1,12 @@
1/* 1/*
2 * mcp23s08.c - SPI gpio expander driver 2 * MCP23S08 SPI/GPIO gpio expander driver
3 */ 3 */
4 4
5#include <linux/kernel.h> 5#include <linux/kernel.h>
6#include <linux/device.h> 6#include <linux/device.h>
7#include <linux/workqueue.h>
8#include <linux/mutex.h> 7#include <linux/mutex.h>
9#include <linux/gpio.h> 8#include <linux/gpio.h>
9#include <linux/i2c.h>
10#include <linux/spi/spi.h> 10#include <linux/spi/spi.h>
11#include <linux/spi/mcp23s08.h> 11#include <linux/spi/mcp23s08.h>
12#include <linux/slab.h> 12#include <linux/slab.h>
@@ -17,13 +17,13 @@
17 */ 17 */
18#define MCP_TYPE_S08 0 18#define MCP_TYPE_S08 0
19#define MCP_TYPE_S17 1 19#define MCP_TYPE_S17 1
20#define MCP_TYPE_008 2
21#define MCP_TYPE_017 3
20 22
21/* Registers are all 8 bits wide. 23/* Registers are all 8 bits wide.
22 * 24 *
23 * The mcp23s17 has twice as many bits, and can be configured to work 25 * The mcp23s17 has twice as many bits, and can be configured to work
24 * with either 16 bit registers or with two adjacent 8 bit banks. 26 * with either 16 bit registers or with two adjacent 8 bit banks.
25 *
26 * Also, there are I2C versions of both chips.
27 */ 27 */
28#define MCP_IODIR 0x00 /* init/reset: all ones */ 28#define MCP_IODIR 0x00 /* init/reset: all ones */
29#define MCP_IPOL 0x01 29#define MCP_IPOL 0x01
@@ -51,7 +51,6 @@ struct mcp23s08_ops {
51}; 51};
52 52
53struct mcp23s08 { 53struct mcp23s08 {
54 struct spi_device *spi;
55 u8 addr; 54 u8 addr;
56 55
57 u16 cache[11]; 56 u16 cache[11];
@@ -60,9 +59,8 @@ struct mcp23s08 {
60 59
61 struct gpio_chip chip; 60 struct gpio_chip chip;
62 61
63 struct work_struct work;
64
65 const struct mcp23s08_ops *ops; 62 const struct mcp23s08_ops *ops;
63 void *data; /* ops specific data */
66}; 64};
67 65
68/* A given spi_device can represent up to eight mcp23sxx chips 66/* A given spi_device can represent up to eight mcp23sxx chips
@@ -76,6 +74,74 @@ struct mcp23s08_driver_data {
76 struct mcp23s08 chip[]; 74 struct mcp23s08 chip[];
77}; 75};
78 76
77/*----------------------------------------------------------------------*/
78
79#ifdef CONFIG_I2C
80
81static int mcp23008_read(struct mcp23s08 *mcp, unsigned reg)
82{
83 return i2c_smbus_read_byte_data(mcp->data, reg);
84}
85
86static int mcp23008_write(struct mcp23s08 *mcp, unsigned reg, unsigned val)
87{
88 return i2c_smbus_write_byte_data(mcp->data, reg, val);
89}
90
91static int
92mcp23008_read_regs(struct mcp23s08 *mcp, unsigned reg, u16 *vals, unsigned n)
93{
94 while (n--) {
95 int ret = mcp23008_read(mcp, reg++);
96 if (ret < 0)
97 return ret;
98 *vals++ = ret;
99 }
100
101 return 0;
102}
103
104static int mcp23017_read(struct mcp23s08 *mcp, unsigned reg)
105{
106 return i2c_smbus_read_word_data(mcp->data, reg << 1);
107}
108
109static int mcp23017_write(struct mcp23s08 *mcp, unsigned reg, unsigned val)
110{
111 return i2c_smbus_write_word_data(mcp->data, reg << 1, val);
112}
113
114static int
115mcp23017_read_regs(struct mcp23s08 *mcp, unsigned reg, u16 *vals, unsigned n)
116{
117 while (n--) {
118 int ret = mcp23017_read(mcp, reg++);
119 if (ret < 0)
120 return ret;
121 *vals++ = ret;
122 }
123
124 return 0;
125}
126
127static const struct mcp23s08_ops mcp23008_ops = {
128 .read = mcp23008_read,
129 .write = mcp23008_write,
130 .read_regs = mcp23008_read_regs,
131};
132
133static const struct mcp23s08_ops mcp23017_ops = {
134 .read = mcp23017_read,
135 .write = mcp23017_write,
136 .read_regs = mcp23017_read_regs,
137};
138
139#endif /* CONFIG_I2C */
140
141/*----------------------------------------------------------------------*/
142
143#ifdef CONFIG_SPI_MASTER
144
79static int mcp23s08_read(struct mcp23s08 *mcp, unsigned reg) 145static int mcp23s08_read(struct mcp23s08 *mcp, unsigned reg)
80{ 146{
81 u8 tx[2], rx[1]; 147 u8 tx[2], rx[1];
@@ -83,7 +149,7 @@ static int mcp23s08_read(struct mcp23s08 *mcp, unsigned reg)
83 149
84 tx[0] = mcp->addr | 0x01; 150 tx[0] = mcp->addr | 0x01;
85 tx[1] = reg; 151 tx[1] = reg;
86 status = spi_write_then_read(mcp->spi, tx, sizeof tx, rx, sizeof rx); 152 status = spi_write_then_read(mcp->data, tx, sizeof tx, rx, sizeof rx);
87 return (status < 0) ? status : rx[0]; 153 return (status < 0) ? status : rx[0];
88} 154}
89 155
@@ -94,7 +160,7 @@ static int mcp23s08_write(struct mcp23s08 *mcp, unsigned reg, unsigned val)
94 tx[0] = mcp->addr; 160 tx[0] = mcp->addr;
95 tx[1] = reg; 161 tx[1] = reg;
96 tx[2] = val; 162 tx[2] = val;
97 return spi_write_then_read(mcp->spi, tx, sizeof tx, NULL, 0); 163 return spi_write_then_read(mcp->data, tx, sizeof tx, NULL, 0);
98} 164}
99 165
100static int 166static int
@@ -109,7 +175,7 @@ mcp23s08_read_regs(struct mcp23s08 *mcp, unsigned reg, u16 *vals, unsigned n)
109 tx[1] = reg; 175 tx[1] = reg;
110 176
111 tmp = (u8 *)vals; 177 tmp = (u8 *)vals;
112 status = spi_write_then_read(mcp->spi, tx, sizeof tx, tmp, n); 178 status = spi_write_then_read(mcp->data, tx, sizeof tx, tmp, n);
113 if (status >= 0) { 179 if (status >= 0) {
114 while (n--) 180 while (n--)
115 vals[n] = tmp[n]; /* expand to 16bit */ 181 vals[n] = tmp[n]; /* expand to 16bit */
@@ -124,7 +190,7 @@ static int mcp23s17_read(struct mcp23s08 *mcp, unsigned reg)
124 190
125 tx[0] = mcp->addr | 0x01; 191 tx[0] = mcp->addr | 0x01;
126 tx[1] = reg << 1; 192 tx[1] = reg << 1;
127 status = spi_write_then_read(mcp->spi, tx, sizeof tx, rx, sizeof rx); 193 status = spi_write_then_read(mcp->data, tx, sizeof tx, rx, sizeof rx);
128 return (status < 0) ? status : (rx[0] | (rx[1] << 8)); 194 return (status < 0) ? status : (rx[0] | (rx[1] << 8));
129} 195}
130 196
@@ -136,7 +202,7 @@ static int mcp23s17_write(struct mcp23s08 *mcp, unsigned reg, unsigned val)
136 tx[1] = reg << 1; 202 tx[1] = reg << 1;
137 tx[2] = val; 203 tx[2] = val;
138 tx[3] = val >> 8; 204 tx[3] = val >> 8;
139 return spi_write_then_read(mcp->spi, tx, sizeof tx, NULL, 0); 205 return spi_write_then_read(mcp->data, tx, sizeof tx, NULL, 0);
140} 206}
141 207
142static int 208static int
@@ -150,7 +216,7 @@ mcp23s17_read_regs(struct mcp23s08 *mcp, unsigned reg, u16 *vals, unsigned n)
150 tx[0] = mcp->addr | 0x01; 216 tx[0] = mcp->addr | 0x01;
151 tx[1] = reg << 1; 217 tx[1] = reg << 1;
152 218
153 status = spi_write_then_read(mcp->spi, tx, sizeof tx, 219 status = spi_write_then_read(mcp->data, tx, sizeof tx,
154 (u8 *)vals, n * 2); 220 (u8 *)vals, n * 2);
155 if (status >= 0) { 221 if (status >= 0) {
156 while (n--) 222 while (n--)
@@ -172,6 +238,7 @@ static const struct mcp23s08_ops mcp23s17_ops = {
172 .read_regs = mcp23s17_read_regs, 238 .read_regs = mcp23s17_read_regs,
173}; 239};
174 240
241#endif /* CONFIG_SPI_MASTER */
175 242
176/*----------------------------------------------------------------------*/ 243/*----------------------------------------------------------------------*/
177 244
@@ -299,17 +366,16 @@ done:
299 366
300/*----------------------------------------------------------------------*/ 367/*----------------------------------------------------------------------*/
301 368
302static int mcp23s08_probe_one(struct spi_device *spi, unsigned addr, 369static int mcp23s08_probe_one(struct mcp23s08 *mcp, struct device *dev,
370 void *data, unsigned addr,
303 unsigned type, unsigned base, unsigned pullups) 371 unsigned type, unsigned base, unsigned pullups)
304{ 372{
305 struct mcp23s08_driver_data *data = spi_get_drvdata(spi); 373 int status;
306 struct mcp23s08 *mcp = data->mcp[addr];
307 int status;
308 374
309 mutex_init(&mcp->lock); 375 mutex_init(&mcp->lock);
310 376
311 mcp->spi = spi; 377 mcp->data = data;
312 mcp->addr = 0x40 | (addr << 1); 378 mcp->addr = addr;
313 379
314 mcp->chip.direction_input = mcp23s08_direction_input; 380 mcp->chip.direction_input = mcp23s08_direction_input;
315 mcp->chip.get = mcp23s08_get; 381 mcp->chip.get = mcp23s08_get;
@@ -317,18 +383,43 @@ static int mcp23s08_probe_one(struct spi_device *spi, unsigned addr,
317 mcp->chip.set = mcp23s08_set; 383 mcp->chip.set = mcp23s08_set;
318 mcp->chip.dbg_show = mcp23s08_dbg_show; 384 mcp->chip.dbg_show = mcp23s08_dbg_show;
319 385
320 if (type == MCP_TYPE_S17) { 386 switch (type) {
387#ifdef CONFIG_SPI_MASTER
388 case MCP_TYPE_S08:
389 mcp->ops = &mcp23s08_ops;
390 mcp->chip.ngpio = 8;
391 mcp->chip.label = "mcp23s08";
392 break;
393
394 case MCP_TYPE_S17:
321 mcp->ops = &mcp23s17_ops; 395 mcp->ops = &mcp23s17_ops;
322 mcp->chip.ngpio = 16; 396 mcp->chip.ngpio = 16;
323 mcp->chip.label = "mcp23s17"; 397 mcp->chip.label = "mcp23s17";
324 } else { 398 break;
325 mcp->ops = &mcp23s08_ops; 399#endif /* CONFIG_SPI_MASTER */
400
401#ifdef CONFIG_I2C
402 case MCP_TYPE_008:
403 mcp->ops = &mcp23008_ops;
326 mcp->chip.ngpio = 8; 404 mcp->chip.ngpio = 8;
327 mcp->chip.label = "mcp23s08"; 405 mcp->chip.label = "mcp23008";
406 break;
407
408 case MCP_TYPE_017:
409 mcp->ops = &mcp23017_ops;
410 mcp->chip.ngpio = 16;
411 mcp->chip.label = "mcp23017";
412 break;
413#endif /* CONFIG_I2C */
414
415 default:
416 dev_err(dev, "invalid device type (%d)\n", type);
417 return -EINVAL;
328 } 418 }
419
329 mcp->chip.base = base; 420 mcp->chip.base = base;
330 mcp->chip.can_sleep = 1; 421 mcp->chip.can_sleep = 1;
331 mcp->chip.dev = &spi->dev; 422 mcp->chip.dev = dev;
332 mcp->chip.owner = THIS_MODULE; 423 mcp->chip.owner = THIS_MODULE;
333 424
334 /* verify MCP_IOCON.SEQOP = 0, so sequential reads work, 425 /* verify MCP_IOCON.SEQOP = 0, so sequential reads work,
@@ -374,11 +465,98 @@ static int mcp23s08_probe_one(struct spi_device *spi, unsigned addr,
374 status = gpiochip_add(&mcp->chip); 465 status = gpiochip_add(&mcp->chip);
375fail: 466fail:
376 if (status < 0) 467 if (status < 0)
377 dev_dbg(&spi->dev, "can't setup chip %d, --> %d\n", 468 dev_dbg(dev, "can't setup chip %d, --> %d\n",
378 addr, status); 469 addr, status);
379 return status; 470 return status;
380} 471}
381 472
473/*----------------------------------------------------------------------*/
474
475#ifdef CONFIG_I2C
476
477static int __devinit mcp230xx_probe(struct i2c_client *client,
478 const struct i2c_device_id *id)
479{
480 struct mcp23s08_platform_data *pdata;
481 struct mcp23s08 *mcp;
482 int status;
483
484 pdata = client->dev.platform_data;
485 if (!pdata || !gpio_is_valid(pdata->base)) {
486 dev_dbg(&client->dev, "invalid or missing platform data\n");
487 return -EINVAL;
488 }
489
490 mcp = kzalloc(sizeof *mcp, GFP_KERNEL);
491 if (!mcp)
492 return -ENOMEM;
493
494 status = mcp23s08_probe_one(mcp, &client->dev, client, client->addr,
495 id->driver_data, pdata->base,
496 pdata->chip[0].pullups);
497 if (status)
498 goto fail;
499
500 i2c_set_clientdata(client, mcp);
501
502 return 0;
503
504fail:
505 kfree(mcp);
506
507 return status;
508}
509
510static int __devexit mcp230xx_remove(struct i2c_client *client)
511{
512 struct mcp23s08 *mcp = i2c_get_clientdata(client);
513 int status;
514
515 status = gpiochip_remove(&mcp->chip);
516 if (status == 0)
517 kfree(mcp);
518
519 return status;
520}
521
522static const struct i2c_device_id mcp230xx_id[] = {
523 { "mcp23008", MCP_TYPE_008 },
524 { "mcp23017", MCP_TYPE_017 },
525 { },
526};
527MODULE_DEVICE_TABLE(i2c, mcp230xx_id);
528
529static struct i2c_driver mcp230xx_driver = {
530 .driver = {
531 .name = "mcp230xx",
532 .owner = THIS_MODULE,
533 },
534 .probe = mcp230xx_probe,
535 .remove = __devexit_p(mcp230xx_remove),
536 .id_table = mcp230xx_id,
537};
538
539static int __init mcp23s08_i2c_init(void)
540{
541 return i2c_add_driver(&mcp230xx_driver);
542}
543
544static void mcp23s08_i2c_exit(void)
545{
546 i2c_del_driver(&mcp230xx_driver);
547}
548
549#else
550
551static int __init mcp23s08_i2c_init(void) { return 0; }
552static void mcp23s08_i2c_exit(void) { }
553
554#endif /* CONFIG_I2C */
555
556/*----------------------------------------------------------------------*/
557
558#ifdef CONFIG_SPI_MASTER
559
382static int mcp23s08_probe(struct spi_device *spi) 560static int mcp23s08_probe(struct spi_device *spi)
383{ 561{
384 struct mcp23s08_platform_data *pdata; 562 struct mcp23s08_platform_data *pdata;
@@ -421,7 +599,8 @@ static int mcp23s08_probe(struct spi_device *spi)
421 continue; 599 continue;
422 chips--; 600 chips--;
423 data->mcp[addr] = &data->chip[chips]; 601 data->mcp[addr] = &data->chip[chips];
424 status = mcp23s08_probe_one(spi, addr, type, base, 602 status = mcp23s08_probe_one(data->mcp[addr], &spi->dev, spi,
603 0x40 | (addr << 1), type, base,
425 pdata->chip[addr].pullups); 604 pdata->chip[addr].pullups);
426 if (status < 0) 605 if (status < 0)
427 goto fail; 606 goto fail;
@@ -435,14 +614,6 @@ static int mcp23s08_probe(struct spi_device *spi)
435 * handled here... 614 * handled here...
436 */ 615 */
437 616
438 if (pdata->setup) {
439 status = pdata->setup(spi,
440 pdata->base, data->ngpio,
441 pdata->context);
442 if (status < 0)
443 dev_dbg(&spi->dev, "setup --> %d\n", status);
444 }
445
446 return 0; 617 return 0;
447 618
448fail: 619fail:
@@ -462,20 +633,9 @@ fail:
462static int mcp23s08_remove(struct spi_device *spi) 633static int mcp23s08_remove(struct spi_device *spi)
463{ 634{
464 struct mcp23s08_driver_data *data = spi_get_drvdata(spi); 635 struct mcp23s08_driver_data *data = spi_get_drvdata(spi);
465 struct mcp23s08_platform_data *pdata = spi->dev.platform_data;
466 unsigned addr; 636 unsigned addr;
467 int status = 0; 637 int status = 0;
468 638
469 if (pdata->teardown) {
470 status = pdata->teardown(spi,
471 pdata->base, data->ngpio,
472 pdata->context);
473 if (status < 0) {
474 dev_err(&spi->dev, "%s --> %d\n", "teardown", status);
475 return status;
476 }
477 }
478
479 for (addr = 0; addr < ARRAY_SIZE(data->mcp); addr++) { 639 for (addr = 0; addr < ARRAY_SIZE(data->mcp); addr++) {
480 int tmp; 640 int tmp;
481 641
@@ -510,20 +670,53 @@ static struct spi_driver mcp23s08_driver = {
510 }, 670 },
511}; 671};
512 672
673static int __init mcp23s08_spi_init(void)
674{
675 return spi_register_driver(&mcp23s08_driver);
676}
677
678static void mcp23s08_spi_exit(void)
679{
680 spi_unregister_driver(&mcp23s08_driver);
681}
682
683#else
684
685static int __init mcp23s08_spi_init(void) { return 0; }
686static void mcp23s08_spi_exit(void) { }
687
688#endif /* CONFIG_SPI_MASTER */
689
513/*----------------------------------------------------------------------*/ 690/*----------------------------------------------------------------------*/
514 691
515static int __init mcp23s08_init(void) 692static int __init mcp23s08_init(void)
516{ 693{
517 return spi_register_driver(&mcp23s08_driver); 694 int ret;
695
696 ret = mcp23s08_spi_init();
697 if (ret)
698 goto spi_fail;
699
700 ret = mcp23s08_i2c_init();
701 if (ret)
702 goto i2c_fail;
703
704 return 0;
705
706 i2c_fail:
707 mcp23s08_spi_exit();
708 spi_fail:
709 return ret;
518} 710}
519/* register after spi postcore initcall and before 711/* register after spi/i2c postcore initcall and before
520 * subsys initcalls that may rely on these GPIOs 712 * subsys initcalls that may rely on these GPIOs
521 */ 713 */
522subsys_initcall(mcp23s08_init); 714subsys_initcall(mcp23s08_init);
523 715
524static void __exit mcp23s08_exit(void) 716static void __exit mcp23s08_exit(void)
525{ 717{
526 spi_unregister_driver(&mcp23s08_driver); 718 mcp23s08_spi_exit();
719 mcp23s08_i2c_exit();
527} 720}
528module_exit(mcp23s08_exit); 721module_exit(mcp23s08_exit);
529 722
diff --git a/drivers/gpio/ml_ioh_gpio.c b/drivers/gpio/gpio-ml-ioh.c
index 1bc621ac353..a9016f56ed7 100644
--- a/drivers/gpio/ml_ioh_gpio.c
+++ b/drivers/gpio/gpio-ml-ioh.c
@@ -233,7 +233,7 @@ static int __devinit ioh_gpio_probe(struct pci_dev *pdev,
233 return 0; 233 return 0;
234 234
235err_gpiochip_add: 235err_gpiochip_add:
236 for (; i != 0; i--) { 236 while (--i >= 0) {
237 chip--; 237 chip--;
238 ret = gpiochip_remove(&chip->gpio); 238 ret = gpiochip_remove(&chip->gpio);
239 if (ret) 239 if (ret)
diff --git a/drivers/gpio/gpio-mpc5200.c b/drivers/gpio/gpio-mpc5200.c
new file mode 100644
index 00000000000..52d3ed20810
--- /dev/null
+++ b/drivers/gpio/gpio-mpc5200.c
@@ -0,0 +1,376 @@
1/*
2 * MPC52xx gpio driver
3 *
4 * Copyright (c) 2008 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2
8 * as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20#include <linux/of.h>
21#include <linux/kernel.h>
22#include <linux/slab.h>
23#include <linux/of_gpio.h>
24#include <linux/io.h>
25#include <linux/of_platform.h>
26
27#include <asm/gpio.h>
28#include <asm/mpc52xx.h>
29#include <sysdev/fsl_soc.h>
30
31static DEFINE_SPINLOCK(gpio_lock);
32
33struct mpc52xx_gpiochip {
34 struct of_mm_gpio_chip mmchip;
35 unsigned int shadow_dvo;
36 unsigned int shadow_gpioe;
37 unsigned int shadow_ddr;
38};
39
40/*
41 * GPIO LIB API implementation for wakeup GPIOs.
42 *
43 * There's a maximum of 8 wakeup GPIOs. Which of these are available
44 * for use depends on your board setup.
45 *
46 * 0 -> GPIO_WKUP_7
47 * 1 -> GPIO_WKUP_6
48 * 2 -> PSC6_1
49 * 3 -> PSC6_0
50 * 4 -> ETH_17
51 * 5 -> PSC3_9
52 * 6 -> PSC2_4
53 * 7 -> PSC1_4
54 *
55 */
56static int mpc52xx_wkup_gpio_get(struct gpio_chip *gc, unsigned int gpio)
57{
58 struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
59 struct mpc52xx_gpio_wkup __iomem *regs = mm_gc->regs;
60 unsigned int ret;
61
62 ret = (in_8(&regs->wkup_ival) >> (7 - gpio)) & 1;
63
64 pr_debug("%s: gpio: %d ret: %d\n", __func__, gpio, ret);
65
66 return ret;
67}
68
69static inline void
70__mpc52xx_wkup_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
71{
72 struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
73 struct mpc52xx_gpiochip *chip = container_of(mm_gc,
74 struct mpc52xx_gpiochip, mmchip);
75 struct mpc52xx_gpio_wkup __iomem *regs = mm_gc->regs;
76
77 if (val)
78 chip->shadow_dvo |= 1 << (7 - gpio);
79 else
80 chip->shadow_dvo &= ~(1 << (7 - gpio));
81
82 out_8(&regs->wkup_dvo, chip->shadow_dvo);
83}
84
85static void
86mpc52xx_wkup_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
87{
88 unsigned long flags;
89
90 spin_lock_irqsave(&gpio_lock, flags);
91
92 __mpc52xx_wkup_gpio_set(gc, gpio, val);
93
94 spin_unlock_irqrestore(&gpio_lock, flags);
95
96 pr_debug("%s: gpio: %d val: %d\n", __func__, gpio, val);
97}
98
99static int mpc52xx_wkup_gpio_dir_in(struct gpio_chip *gc, unsigned int gpio)
100{
101 struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
102 struct mpc52xx_gpiochip *chip = container_of(mm_gc,
103 struct mpc52xx_gpiochip, mmchip);
104 struct mpc52xx_gpio_wkup __iomem *regs = mm_gc->regs;
105 unsigned long flags;
106
107 spin_lock_irqsave(&gpio_lock, flags);
108
109 /* set the direction */
110 chip->shadow_ddr &= ~(1 << (7 - gpio));
111 out_8(&regs->wkup_ddr, chip->shadow_ddr);
112
113 /* and enable the pin */
114 chip->shadow_gpioe |= 1 << (7 - gpio);
115 out_8(&regs->wkup_gpioe, chip->shadow_gpioe);
116
117 spin_unlock_irqrestore(&gpio_lock, flags);
118
119 return 0;
120}
121
122static int
123mpc52xx_wkup_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
124{
125 struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
126 struct mpc52xx_gpio_wkup __iomem *regs = mm_gc->regs;
127 struct mpc52xx_gpiochip *chip = container_of(mm_gc,
128 struct mpc52xx_gpiochip, mmchip);
129 unsigned long flags;
130
131 spin_lock_irqsave(&gpio_lock, flags);
132
133 __mpc52xx_wkup_gpio_set(gc, gpio, val);
134
135 /* Then set direction */
136 chip->shadow_ddr |= 1 << (7 - gpio);
137 out_8(&regs->wkup_ddr, chip->shadow_ddr);
138
139 /* Finally enable the pin */
140 chip->shadow_gpioe |= 1 << (7 - gpio);
141 out_8(&regs->wkup_gpioe, chip->shadow_gpioe);
142
143 spin_unlock_irqrestore(&gpio_lock, flags);
144
145 pr_debug("%s: gpio: %d val: %d\n", __func__, gpio, val);
146
147 return 0;
148}
149
150static int __devinit mpc52xx_wkup_gpiochip_probe(struct platform_device *ofdev)
151{
152 struct mpc52xx_gpiochip *chip;
153 struct mpc52xx_gpio_wkup __iomem *regs;
154 struct gpio_chip *gc;
155 int ret;
156
157 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
158 if (!chip)
159 return -ENOMEM;
160
161 gc = &chip->mmchip.gc;
162
163 gc->ngpio = 8;
164 gc->direction_input = mpc52xx_wkup_gpio_dir_in;
165 gc->direction_output = mpc52xx_wkup_gpio_dir_out;
166 gc->get = mpc52xx_wkup_gpio_get;
167 gc->set = mpc52xx_wkup_gpio_set;
168
169 ret = of_mm_gpiochip_add(ofdev->dev.of_node, &chip->mmchip);
170 if (ret)
171 return ret;
172
173 regs = chip->mmchip.regs;
174 chip->shadow_gpioe = in_8(&regs->wkup_gpioe);
175 chip->shadow_ddr = in_8(&regs->wkup_ddr);
176 chip->shadow_dvo = in_8(&regs->wkup_dvo);
177
178 return 0;
179}
180
181static int mpc52xx_gpiochip_remove(struct platform_device *ofdev)
182{
183 return -EBUSY;
184}
185
186static const struct of_device_id mpc52xx_wkup_gpiochip_match[] = {
187 { .compatible = "fsl,mpc5200-gpio-wkup", },
188 {}
189};
190
191static struct platform_driver mpc52xx_wkup_gpiochip_driver = {
192 .driver = {
193 .name = "mpc5200-gpio-wkup",
194 .owner = THIS_MODULE,
195 .of_match_table = mpc52xx_wkup_gpiochip_match,
196 },
197 .probe = mpc52xx_wkup_gpiochip_probe,
198 .remove = mpc52xx_gpiochip_remove,
199};
200
201/*
202 * GPIO LIB API implementation for simple GPIOs
203 *
204 * There's a maximum of 32 simple GPIOs. Which of these are available
205 * for use depends on your board setup.
206 * The numbering reflects the bit numbering in the port registers:
207 *
208 * 0..1 > reserved
209 * 2..3 > IRDA
210 * 4..7 > ETHR
211 * 8..11 > reserved
212 * 12..15 > USB
213 * 16..17 > reserved
214 * 18..23 > PSC3
215 * 24..27 > PSC2
216 * 28..31 > PSC1
217 */
218static int mpc52xx_simple_gpio_get(struct gpio_chip *gc, unsigned int gpio)
219{
220 struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
221 struct mpc52xx_gpio __iomem *regs = mm_gc->regs;
222 unsigned int ret;
223
224 ret = (in_be32(&regs->simple_ival) >> (31 - gpio)) & 1;
225
226 return ret;
227}
228
229static inline void
230__mpc52xx_simple_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
231{
232 struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
233 struct mpc52xx_gpiochip *chip = container_of(mm_gc,
234 struct mpc52xx_gpiochip, mmchip);
235 struct mpc52xx_gpio __iomem *regs = mm_gc->regs;
236
237 if (val)
238 chip->shadow_dvo |= 1 << (31 - gpio);
239 else
240 chip->shadow_dvo &= ~(1 << (31 - gpio));
241 out_be32(&regs->simple_dvo, chip->shadow_dvo);
242}
243
244static void
245mpc52xx_simple_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
246{
247 unsigned long flags;
248
249 spin_lock_irqsave(&gpio_lock, flags);
250
251 __mpc52xx_simple_gpio_set(gc, gpio, val);
252
253 spin_unlock_irqrestore(&gpio_lock, flags);
254
255 pr_debug("%s: gpio: %d val: %d\n", __func__, gpio, val);
256}
257
258static int mpc52xx_simple_gpio_dir_in(struct gpio_chip *gc, unsigned int gpio)
259{
260 struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
261 struct mpc52xx_gpiochip *chip = container_of(mm_gc,
262 struct mpc52xx_gpiochip, mmchip);
263 struct mpc52xx_gpio __iomem *regs = mm_gc->regs;
264 unsigned long flags;
265
266 spin_lock_irqsave(&gpio_lock, flags);
267
268 /* set the direction */
269 chip->shadow_ddr &= ~(1 << (31 - gpio));
270 out_be32(&regs->simple_ddr, chip->shadow_ddr);
271
272 /* and enable the pin */
273 chip->shadow_gpioe |= 1 << (31 - gpio);
274 out_be32(&regs->simple_gpioe, chip->shadow_gpioe);
275
276 spin_unlock_irqrestore(&gpio_lock, flags);
277
278 return 0;
279}
280
281static int
282mpc52xx_simple_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
283{
284 struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
285 struct mpc52xx_gpiochip *chip = container_of(mm_gc,
286 struct mpc52xx_gpiochip, mmchip);
287 struct mpc52xx_gpio __iomem *regs = mm_gc->regs;
288 unsigned long flags;
289
290 spin_lock_irqsave(&gpio_lock, flags);
291
292 /* First set initial value */
293 __mpc52xx_simple_gpio_set(gc, gpio, val);
294
295 /* Then set direction */
296 chip->shadow_ddr |= 1 << (31 - gpio);
297 out_be32(&regs->simple_ddr, chip->shadow_ddr);
298
299 /* Finally enable the pin */
300 chip->shadow_gpioe |= 1 << (31 - gpio);
301 out_be32(&regs->simple_gpioe, chip->shadow_gpioe);
302
303 spin_unlock_irqrestore(&gpio_lock, flags);
304
305 pr_debug("%s: gpio: %d val: %d\n", __func__, gpio, val);
306
307 return 0;
308}
309
310static int __devinit mpc52xx_simple_gpiochip_probe(struct platform_device *ofdev)
311{
312 struct mpc52xx_gpiochip *chip;
313 struct gpio_chip *gc;
314 struct mpc52xx_gpio __iomem *regs;
315 int ret;
316
317 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
318 if (!chip)
319 return -ENOMEM;
320
321 gc = &chip->mmchip.gc;
322
323 gc->ngpio = 32;
324 gc->direction_input = mpc52xx_simple_gpio_dir_in;
325 gc->direction_output = mpc52xx_simple_gpio_dir_out;
326 gc->get = mpc52xx_simple_gpio_get;
327 gc->set = mpc52xx_simple_gpio_set;
328
329 ret = of_mm_gpiochip_add(ofdev->dev.of_node, &chip->mmchip);
330 if (ret)
331 return ret;
332
333 regs = chip->mmchip.regs;
334 chip->shadow_gpioe = in_be32(&regs->simple_gpioe);
335 chip->shadow_ddr = in_be32(&regs->simple_ddr);
336 chip->shadow_dvo = in_be32(&regs->simple_dvo);
337
338 return 0;
339}
340
341static const struct of_device_id mpc52xx_simple_gpiochip_match[] = {
342 { .compatible = "fsl,mpc5200-gpio", },
343 {}
344};
345
346static struct platform_driver mpc52xx_simple_gpiochip_driver = {
347 .driver = {
348 .name = "mpc5200-gpio",
349 .owner = THIS_MODULE,
350 .of_match_table = mpc52xx_simple_gpiochip_match,
351 },
352 .probe = mpc52xx_simple_gpiochip_probe,
353 .remove = mpc52xx_gpiochip_remove,
354};
355
356static int __init mpc52xx_gpio_init(void)
357{
358 if (platform_driver_register(&mpc52xx_wkup_gpiochip_driver))
359 printk(KERN_ERR "Unable to register wakeup GPIO driver\n");
360
361 if (platform_driver_register(&mpc52xx_simple_gpiochip_driver))
362 printk(KERN_ERR "Unable to register simple GPIO driver\n");
363
364 return 0;
365}
366
367
368/* Make sure we get initialised before anyone else tries to use us */
369subsys_initcall(mpc52xx_gpio_init);
370
371/* No exit call at the moment as we cannot unregister of gpio chips */
372
373MODULE_DESCRIPTION("Freescale MPC52xx gpio driver");
374MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de");
375MODULE_LICENSE("GPL v2");
376
diff --git a/drivers/gpio/gpio-msm-v1.c b/drivers/gpio/gpio-msm-v1.c
new file mode 100644
index 00000000000..52a4d4286eb
--- /dev/null
+++ b/drivers/gpio/gpio-msm-v1.c
@@ -0,0 +1,636 @@
1/*
2 * Copyright (C) 2007 Google, Inc.
3 * Copyright (c) 2009-2011, Code Aurora Forum. All rights reserved.
4 *
5 * This software is licensed under the terms of the GNU General Public
6 * License version 2, as published by the Free Software Foundation, and
7 * may be copied, distributed, and modified under those terms.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 */
15
16#include <linux/bitops.h>
17#include <linux/gpio.h>
18#include <linux/interrupt.h>
19#include <linux/io.h>
20#include <linux/irq.h>
21#include <linux/module.h>
22#include <mach/cpu.h>
23#include <mach/msm_gpiomux.h>
24#include <mach/msm_iomap.h>
25
26/* see 80-VA736-2 Rev C pp 695-751
27**
28** These are actually the *shadow* gpio registers, since the
29** real ones (which allow full access) are only available to the
30** ARM9 side of the world.
31**
32** Since the _BASE need to be page-aligned when we're mapping them
33** to virtual addresses, adjust for the additional offset in these
34** macros.
35*/
36
37#define MSM_GPIO1_REG(off) (MSM_GPIO1_BASE + (off))
38#define MSM_GPIO2_REG(off) (MSM_GPIO2_BASE + 0x400 + (off))
39#define MSM_GPIO1_SHADOW_REG(off) (MSM_GPIO1_BASE + 0x800 + (off))
40#define MSM_GPIO2_SHADOW_REG(off) (MSM_GPIO2_BASE + 0xC00 + (off))
41
42/*
43 * MSM7X00 registers
44 */
45/* output value */
46#define MSM7X00_GPIO_OUT_0 MSM_GPIO1_SHADOW_REG(0x00) /* gpio 15-0 */
47#define MSM7X00_GPIO_OUT_1 MSM_GPIO2_SHADOW_REG(0x00) /* gpio 42-16 */
48#define MSM7X00_GPIO_OUT_2 MSM_GPIO1_SHADOW_REG(0x04) /* gpio 67-43 */
49#define MSM7X00_GPIO_OUT_3 MSM_GPIO1_SHADOW_REG(0x08) /* gpio 94-68 */
50#define MSM7X00_GPIO_OUT_4 MSM_GPIO1_SHADOW_REG(0x0C) /* gpio 106-95 */
51#define MSM7X00_GPIO_OUT_5 MSM_GPIO1_SHADOW_REG(0x50) /* gpio 107-121 */
52
53/* same pin map as above, output enable */
54#define MSM7X00_GPIO_OE_0 MSM_GPIO1_SHADOW_REG(0x10)
55#define MSM7X00_GPIO_OE_1 MSM_GPIO2_SHADOW_REG(0x08)
56#define MSM7X00_GPIO_OE_2 MSM_GPIO1_SHADOW_REG(0x14)
57#define MSM7X00_GPIO_OE_3 MSM_GPIO1_SHADOW_REG(0x18)
58#define MSM7X00_GPIO_OE_4 MSM_GPIO1_SHADOW_REG(0x1C)
59#define MSM7X00_GPIO_OE_5 MSM_GPIO1_SHADOW_REG(0x54)
60
61/* same pin map as above, input read */
62#define MSM7X00_GPIO_IN_0 MSM_GPIO1_SHADOW_REG(0x34)
63#define MSM7X00_GPIO_IN_1 MSM_GPIO2_SHADOW_REG(0x20)
64#define MSM7X00_GPIO_IN_2 MSM_GPIO1_SHADOW_REG(0x38)
65#define MSM7X00_GPIO_IN_3 MSM_GPIO1_SHADOW_REG(0x3C)
66#define MSM7X00_GPIO_IN_4 MSM_GPIO1_SHADOW_REG(0x40)
67#define MSM7X00_GPIO_IN_5 MSM_GPIO1_SHADOW_REG(0x44)
68
69/* same pin map as above, 1=edge 0=level interrup */
70#define MSM7X00_GPIO_INT_EDGE_0 MSM_GPIO1_SHADOW_REG(0x60)
71#define MSM7X00_GPIO_INT_EDGE_1 MSM_GPIO2_SHADOW_REG(0x50)
72#define MSM7X00_GPIO_INT_EDGE_2 MSM_GPIO1_SHADOW_REG(0x64)
73#define MSM7X00_GPIO_INT_EDGE_3 MSM_GPIO1_SHADOW_REG(0x68)
74#define MSM7X00_GPIO_INT_EDGE_4 MSM_GPIO1_SHADOW_REG(0x6C)
75#define MSM7X00_GPIO_INT_EDGE_5 MSM_GPIO1_SHADOW_REG(0xC0)
76
77/* same pin map as above, 1=positive 0=negative */
78#define MSM7X00_GPIO_INT_POS_0 MSM_GPIO1_SHADOW_REG(0x70)
79#define MSM7X00_GPIO_INT_POS_1 MSM_GPIO2_SHADOW_REG(0x58)
80#define MSM7X00_GPIO_INT_POS_2 MSM_GPIO1_SHADOW_REG(0x74)
81#define MSM7X00_GPIO_INT_POS_3 MSM_GPIO1_SHADOW_REG(0x78)
82#define MSM7X00_GPIO_INT_POS_4 MSM_GPIO1_SHADOW_REG(0x7C)
83#define MSM7X00_GPIO_INT_POS_5 MSM_GPIO1_SHADOW_REG(0xBC)
84
85/* same pin map as above, interrupt enable */
86#define MSM7X00_GPIO_INT_EN_0 MSM_GPIO1_SHADOW_REG(0x80)
87#define MSM7X00_GPIO_INT_EN_1 MSM_GPIO2_SHADOW_REG(0x60)
88#define MSM7X00_GPIO_INT_EN_2 MSM_GPIO1_SHADOW_REG(0x84)
89#define MSM7X00_GPIO_INT_EN_3 MSM_GPIO1_SHADOW_REG(0x88)
90#define MSM7X00_GPIO_INT_EN_4 MSM_GPIO1_SHADOW_REG(0x8C)
91#define MSM7X00_GPIO_INT_EN_5 MSM_GPIO1_SHADOW_REG(0xB8)
92
93/* same pin map as above, write 1 to clear interrupt */
94#define MSM7X00_GPIO_INT_CLEAR_0 MSM_GPIO1_SHADOW_REG(0x90)
95#define MSM7X00_GPIO_INT_CLEAR_1 MSM_GPIO2_SHADOW_REG(0x68)
96#define MSM7X00_GPIO_INT_CLEAR_2 MSM_GPIO1_SHADOW_REG(0x94)
97#define MSM7X00_GPIO_INT_CLEAR_3 MSM_GPIO1_SHADOW_REG(0x98)
98#define MSM7X00_GPIO_INT_CLEAR_4 MSM_GPIO1_SHADOW_REG(0x9C)
99#define MSM7X00_GPIO_INT_CLEAR_5 MSM_GPIO1_SHADOW_REG(0xB4)
100
101/* same pin map as above, 1=interrupt pending */
102#define MSM7X00_GPIO_INT_STATUS_0 MSM_GPIO1_SHADOW_REG(0xA0)
103#define MSM7X00_GPIO_INT_STATUS_1 MSM_GPIO2_SHADOW_REG(0x70)
104#define MSM7X00_GPIO_INT_STATUS_2 MSM_GPIO1_SHADOW_REG(0xA4)
105#define MSM7X00_GPIO_INT_STATUS_3 MSM_GPIO1_SHADOW_REG(0xA8)
106#define MSM7X00_GPIO_INT_STATUS_4 MSM_GPIO1_SHADOW_REG(0xAC)
107#define MSM7X00_GPIO_INT_STATUS_5 MSM_GPIO1_SHADOW_REG(0xB0)
108
109/*
110 * QSD8X50 registers
111 */
112/* output value */
113#define QSD8X50_GPIO_OUT_0 MSM_GPIO1_SHADOW_REG(0x00) /* gpio 15-0 */
114#define QSD8X50_GPIO_OUT_1 MSM_GPIO2_SHADOW_REG(0x00) /* gpio 42-16 */
115#define QSD8X50_GPIO_OUT_2 MSM_GPIO1_SHADOW_REG(0x04) /* gpio 67-43 */
116#define QSD8X50_GPIO_OUT_3 MSM_GPIO1_SHADOW_REG(0x08) /* gpio 94-68 */
117#define QSD8X50_GPIO_OUT_4 MSM_GPIO1_SHADOW_REG(0x0C) /* gpio 103-95 */
118#define QSD8X50_GPIO_OUT_5 MSM_GPIO1_SHADOW_REG(0x10) /* gpio 121-104 */
119#define QSD8X50_GPIO_OUT_6 MSM_GPIO1_SHADOW_REG(0x14) /* gpio 152-122 */
120#define QSD8X50_GPIO_OUT_7 MSM_GPIO1_SHADOW_REG(0x18) /* gpio 164-153 */
121
122/* same pin map as above, output enable */
123#define QSD8X50_GPIO_OE_0 MSM_GPIO1_SHADOW_REG(0x20)
124#define QSD8X50_GPIO_OE_1 MSM_GPIO2_SHADOW_REG(0x08)
125#define QSD8X50_GPIO_OE_2 MSM_GPIO1_SHADOW_REG(0x24)
126#define QSD8X50_GPIO_OE_3 MSM_GPIO1_SHADOW_REG(0x28)
127#define QSD8X50_GPIO_OE_4 MSM_GPIO1_SHADOW_REG(0x2C)
128#define QSD8X50_GPIO_OE_5 MSM_GPIO1_SHADOW_REG(0x30)
129#define QSD8X50_GPIO_OE_6 MSM_GPIO1_SHADOW_REG(0x34)
130#define QSD8X50_GPIO_OE_7 MSM_GPIO1_SHADOW_REG(0x38)
131
132/* same pin map as above, input read */
133#define QSD8X50_GPIO_IN_0 MSM_GPIO1_SHADOW_REG(0x50)
134#define QSD8X50_GPIO_IN_1 MSM_GPIO2_SHADOW_REG(0x20)
135#define QSD8X50_GPIO_IN_2 MSM_GPIO1_SHADOW_REG(0x54)
136#define QSD8X50_GPIO_IN_3 MSM_GPIO1_SHADOW_REG(0x58)
137#define QSD8X50_GPIO_IN_4 MSM_GPIO1_SHADOW_REG(0x5C)
138#define QSD8X50_GPIO_IN_5 MSM_GPIO1_SHADOW_REG(0x60)
139#define QSD8X50_GPIO_IN_6 MSM_GPIO1_SHADOW_REG(0x64)
140#define QSD8X50_GPIO_IN_7 MSM_GPIO1_SHADOW_REG(0x68)
141
142/* same pin map as above, 1=edge 0=level interrup */
143#define QSD8X50_GPIO_INT_EDGE_0 MSM_GPIO1_SHADOW_REG(0x70)
144#define QSD8X50_GPIO_INT_EDGE_1 MSM_GPIO2_SHADOW_REG(0x50)
145#define QSD8X50_GPIO_INT_EDGE_2 MSM_GPIO1_SHADOW_REG(0x74)
146#define QSD8X50_GPIO_INT_EDGE_3 MSM_GPIO1_SHADOW_REG(0x78)
147#define QSD8X50_GPIO_INT_EDGE_4 MSM_GPIO1_SHADOW_REG(0x7C)
148#define QSD8X50_GPIO_INT_EDGE_5 MSM_GPIO1_SHADOW_REG(0x80)
149#define QSD8X50_GPIO_INT_EDGE_6 MSM_GPIO1_SHADOW_REG(0x84)
150#define QSD8X50_GPIO_INT_EDGE_7 MSM_GPIO1_SHADOW_REG(0x88)
151
152/* same pin map as above, 1=positive 0=negative */
153#define QSD8X50_GPIO_INT_POS_0 MSM_GPIO1_SHADOW_REG(0x90)
154#define QSD8X50_GPIO_INT_POS_1 MSM_GPIO2_SHADOW_REG(0x58)
155#define QSD8X50_GPIO_INT_POS_2 MSM_GPIO1_SHADOW_REG(0x94)
156#define QSD8X50_GPIO_INT_POS_3 MSM_GPIO1_SHADOW_REG(0x98)
157#define QSD8X50_GPIO_INT_POS_4 MSM_GPIO1_SHADOW_REG(0x9C)
158#define QSD8X50_GPIO_INT_POS_5 MSM_GPIO1_SHADOW_REG(0xA0)
159#define QSD8X50_GPIO_INT_POS_6 MSM_GPIO1_SHADOW_REG(0xA4)
160#define QSD8X50_GPIO_INT_POS_7 MSM_GPIO1_SHADOW_REG(0xA8)
161
162/* same pin map as above, interrupt enable */
163#define QSD8X50_GPIO_INT_EN_0 MSM_GPIO1_SHADOW_REG(0xB0)
164#define QSD8X50_GPIO_INT_EN_1 MSM_GPIO2_SHADOW_REG(0x60)
165#define QSD8X50_GPIO_INT_EN_2 MSM_GPIO1_SHADOW_REG(0xB4)
166#define QSD8X50_GPIO_INT_EN_3 MSM_GPIO1_SHADOW_REG(0xB8)
167#define QSD8X50_GPIO_INT_EN_4 MSM_GPIO1_SHADOW_REG(0xBC)
168#define QSD8X50_GPIO_INT_EN_5 MSM_GPIO1_SHADOW_REG(0xC0)
169#define QSD8X50_GPIO_INT_EN_6 MSM_GPIO1_SHADOW_REG(0xC4)
170#define QSD8X50_GPIO_INT_EN_7 MSM_GPIO1_SHADOW_REG(0xC8)
171
172/* same pin map as above, write 1 to clear interrupt */
173#define QSD8X50_GPIO_INT_CLEAR_0 MSM_GPIO1_SHADOW_REG(0xD0)
174#define QSD8X50_GPIO_INT_CLEAR_1 MSM_GPIO2_SHADOW_REG(0x68)
175#define QSD8X50_GPIO_INT_CLEAR_2 MSM_GPIO1_SHADOW_REG(0xD4)
176#define QSD8X50_GPIO_INT_CLEAR_3 MSM_GPIO1_SHADOW_REG(0xD8)
177#define QSD8X50_GPIO_INT_CLEAR_4 MSM_GPIO1_SHADOW_REG(0xDC)
178#define QSD8X50_GPIO_INT_CLEAR_5 MSM_GPIO1_SHADOW_REG(0xE0)
179#define QSD8X50_GPIO_INT_CLEAR_6 MSM_GPIO1_SHADOW_REG(0xE4)
180#define QSD8X50_GPIO_INT_CLEAR_7 MSM_GPIO1_SHADOW_REG(0xE8)
181
182/* same pin map as above, 1=interrupt pending */
183#define QSD8X50_GPIO_INT_STATUS_0 MSM_GPIO1_SHADOW_REG(0xF0)
184#define QSD8X50_GPIO_INT_STATUS_1 MSM_GPIO2_SHADOW_REG(0x70)
185#define QSD8X50_GPIO_INT_STATUS_2 MSM_GPIO1_SHADOW_REG(0xF4)
186#define QSD8X50_GPIO_INT_STATUS_3 MSM_GPIO1_SHADOW_REG(0xF8)
187#define QSD8X50_GPIO_INT_STATUS_4 MSM_GPIO1_SHADOW_REG(0xFC)
188#define QSD8X50_GPIO_INT_STATUS_5 MSM_GPIO1_SHADOW_REG(0x100)
189#define QSD8X50_GPIO_INT_STATUS_6 MSM_GPIO1_SHADOW_REG(0x104)
190#define QSD8X50_GPIO_INT_STATUS_7 MSM_GPIO1_SHADOW_REG(0x108)
191
192/*
193 * MSM7X30 registers
194 */
195/* output value */
196#define MSM7X30_GPIO_OUT_0 MSM_GPIO1_REG(0x00) /* gpio 15-0 */
197#define MSM7X30_GPIO_OUT_1 MSM_GPIO2_REG(0x00) /* gpio 43-16 */
198#define MSM7X30_GPIO_OUT_2 MSM_GPIO1_REG(0x04) /* gpio 67-44 */
199#define MSM7X30_GPIO_OUT_3 MSM_GPIO1_REG(0x08) /* gpio 94-68 */
200#define MSM7X30_GPIO_OUT_4 MSM_GPIO1_REG(0x0C) /* gpio 106-95 */
201#define MSM7X30_GPIO_OUT_5 MSM_GPIO1_REG(0x50) /* gpio 133-107 */
202#define MSM7X30_GPIO_OUT_6 MSM_GPIO1_REG(0xC4) /* gpio 150-134 */
203#define MSM7X30_GPIO_OUT_7 MSM_GPIO1_REG(0x214) /* gpio 181-151 */
204
205/* same pin map as above, output enable */
206#define MSM7X30_GPIO_OE_0 MSM_GPIO1_REG(0x10)
207#define MSM7X30_GPIO_OE_1 MSM_GPIO2_REG(0x08)
208#define MSM7X30_GPIO_OE_2 MSM_GPIO1_REG(0x14)
209#define MSM7X30_GPIO_OE_3 MSM_GPIO1_REG(0x18)
210#define MSM7X30_GPIO_OE_4 MSM_GPIO1_REG(0x1C)
211#define MSM7X30_GPIO_OE_5 MSM_GPIO1_REG(0x54)
212#define MSM7X30_GPIO_OE_6 MSM_GPIO1_REG(0xC8)
213#define MSM7X30_GPIO_OE_7 MSM_GPIO1_REG(0x218)
214
215/* same pin map as above, input read */
216#define MSM7X30_GPIO_IN_0 MSM_GPIO1_REG(0x34)
217#define MSM7X30_GPIO_IN_1 MSM_GPIO2_REG(0x20)
218#define MSM7X30_GPIO_IN_2 MSM_GPIO1_REG(0x38)
219#define MSM7X30_GPIO_IN_3 MSM_GPIO1_REG(0x3C)
220#define MSM7X30_GPIO_IN_4 MSM_GPIO1_REG(0x40)
221#define MSM7X30_GPIO_IN_5 MSM_GPIO1_REG(0x44)
222#define MSM7X30_GPIO_IN_6 MSM_GPIO1_REG(0xCC)
223#define MSM7X30_GPIO_IN_7 MSM_GPIO1_REG(0x21C)
224
225/* same pin map as above, 1=edge 0=level interrup */
226#define MSM7X30_GPIO_INT_EDGE_0 MSM_GPIO1_REG(0x60)
227#define MSM7X30_GPIO_INT_EDGE_1 MSM_GPIO2_REG(0x50)
228#define MSM7X30_GPIO_INT_EDGE_2 MSM_GPIO1_REG(0x64)
229#define MSM7X30_GPIO_INT_EDGE_3 MSM_GPIO1_REG(0x68)
230#define MSM7X30_GPIO_INT_EDGE_4 MSM_GPIO1_REG(0x6C)
231#define MSM7X30_GPIO_INT_EDGE_5 MSM_GPIO1_REG(0xC0)
232#define MSM7X30_GPIO_INT_EDGE_6 MSM_GPIO1_REG(0xD0)
233#define MSM7X30_GPIO_INT_EDGE_7 MSM_GPIO1_REG(0x240)
234
235/* same pin map as above, 1=positive 0=negative */
236#define MSM7X30_GPIO_INT_POS_0 MSM_GPIO1_REG(0x70)
237#define MSM7X30_GPIO_INT_POS_1 MSM_GPIO2_REG(0x58)
238#define MSM7X30_GPIO_INT_POS_2 MSM_GPIO1_REG(0x74)
239#define MSM7X30_GPIO_INT_POS_3 MSM_GPIO1_REG(0x78)
240#define MSM7X30_GPIO_INT_POS_4 MSM_GPIO1_REG(0x7C)
241#define MSM7X30_GPIO_INT_POS_5 MSM_GPIO1_REG(0xBC)
242#define MSM7X30_GPIO_INT_POS_6 MSM_GPIO1_REG(0xD4)
243#define MSM7X30_GPIO_INT_POS_7 MSM_GPIO1_REG(0x228)
244
245/* same pin map as above, interrupt enable */
246#define MSM7X30_GPIO_INT_EN_0 MSM_GPIO1_REG(0x80)
247#define MSM7X30_GPIO_INT_EN_1 MSM_GPIO2_REG(0x60)
248#define MSM7X30_GPIO_INT_EN_2 MSM_GPIO1_REG(0x84)
249#define MSM7X30_GPIO_INT_EN_3 MSM_GPIO1_REG(0x88)
250#define MSM7X30_GPIO_INT_EN_4 MSM_GPIO1_REG(0x8C)
251#define MSM7X30_GPIO_INT_EN_5 MSM_GPIO1_REG(0xB8)
252#define MSM7X30_GPIO_INT_EN_6 MSM_GPIO1_REG(0xD8)
253#define MSM7X30_GPIO_INT_EN_7 MSM_GPIO1_REG(0x22C)
254
255/* same pin map as above, write 1 to clear interrupt */
256#define MSM7X30_GPIO_INT_CLEAR_0 MSM_GPIO1_REG(0x90)
257#define MSM7X30_GPIO_INT_CLEAR_1 MSM_GPIO2_REG(0x68)
258#define MSM7X30_GPIO_INT_CLEAR_2 MSM_GPIO1_REG(0x94)
259#define MSM7X30_GPIO_INT_CLEAR_3 MSM_GPIO1_REG(0x98)
260#define MSM7X30_GPIO_INT_CLEAR_4 MSM_GPIO1_REG(0x9C)
261#define MSM7X30_GPIO_INT_CLEAR_5 MSM_GPIO1_REG(0xB4)
262#define MSM7X30_GPIO_INT_CLEAR_6 MSM_GPIO1_REG(0xDC)
263#define MSM7X30_GPIO_INT_CLEAR_7 MSM_GPIO1_REG(0x230)
264
265/* same pin map as above, 1=interrupt pending */
266#define MSM7X30_GPIO_INT_STATUS_0 MSM_GPIO1_REG(0xA0)
267#define MSM7X30_GPIO_INT_STATUS_1 MSM_GPIO2_REG(0x70)
268#define MSM7X30_GPIO_INT_STATUS_2 MSM_GPIO1_REG(0xA4)
269#define MSM7X30_GPIO_INT_STATUS_3 MSM_GPIO1_REG(0xA8)
270#define MSM7X30_GPIO_INT_STATUS_4 MSM_GPIO1_REG(0xAC)
271#define MSM7X30_GPIO_INT_STATUS_5 MSM_GPIO1_REG(0xB0)
272#define MSM7X30_GPIO_INT_STATUS_6 MSM_GPIO1_REG(0xE0)
273#define MSM7X30_GPIO_INT_STATUS_7 MSM_GPIO1_REG(0x234)
274
275#define FIRST_GPIO_IRQ MSM_GPIO_TO_INT(0)
276
277#define MSM_GPIO_BANK(soc, bank, first, last) \
278 { \
279 .regs = { \
280 .out = soc##_GPIO_OUT_##bank, \
281 .in = soc##_GPIO_IN_##bank, \
282 .int_status = soc##_GPIO_INT_STATUS_##bank, \
283 .int_clear = soc##_GPIO_INT_CLEAR_##bank, \
284 .int_en = soc##_GPIO_INT_EN_##bank, \
285 .int_edge = soc##_GPIO_INT_EDGE_##bank, \
286 .int_pos = soc##_GPIO_INT_POS_##bank, \
287 .oe = soc##_GPIO_OE_##bank, \
288 }, \
289 .chip = { \
290 .base = (first), \
291 .ngpio = (last) - (first) + 1, \
292 .get = msm_gpio_get, \
293 .set = msm_gpio_set, \
294 .direction_input = msm_gpio_direction_input, \
295 .direction_output = msm_gpio_direction_output, \
296 .to_irq = msm_gpio_to_irq, \
297 .request = msm_gpio_request, \
298 .free = msm_gpio_free, \
299 } \
300 }
301
302#define MSM_GPIO_BROKEN_INT_CLEAR 1
303
304struct msm_gpio_regs {
305 void __iomem *out;
306 void __iomem *in;
307 void __iomem *int_status;
308 void __iomem *int_clear;
309 void __iomem *int_en;
310 void __iomem *int_edge;
311 void __iomem *int_pos;
312 void __iomem *oe;
313};
314
315struct msm_gpio_chip {
316 spinlock_t lock;
317 struct gpio_chip chip;
318 struct msm_gpio_regs regs;
319#if MSM_GPIO_BROKEN_INT_CLEAR
320 unsigned int_status_copy;
321#endif
322 unsigned int both_edge_detect;
323 unsigned int int_enable[2]; /* 0: awake, 1: sleep */
324};
325
326static int msm_gpio_write(struct msm_gpio_chip *msm_chip,
327 unsigned offset, unsigned on)
328{
329 unsigned mask = BIT(offset);
330 unsigned val;
331
332 val = readl(msm_chip->regs.out);
333 if (on)
334 writel(val | mask, msm_chip->regs.out);
335 else
336 writel(val & ~mask, msm_chip->regs.out);
337 return 0;
338}
339
340static void msm_gpio_update_both_edge_detect(struct msm_gpio_chip *msm_chip)
341{
342 int loop_limit = 100;
343 unsigned pol, val, val2, intstat;
344 do {
345 val = readl(msm_chip->regs.in);
346 pol = readl(msm_chip->regs.int_pos);
347 pol = (pol & ~msm_chip->both_edge_detect) |
348 (~val & msm_chip->both_edge_detect);
349 writel(pol, msm_chip->regs.int_pos);
350 intstat = readl(msm_chip->regs.int_status);
351 val2 = readl(msm_chip->regs.in);
352 if (((val ^ val2) & msm_chip->both_edge_detect & ~intstat) == 0)
353 return;
354 } while (loop_limit-- > 0);
355 printk(KERN_ERR "msm_gpio_update_both_edge_detect, "
356 "failed to reach stable state %x != %x\n", val, val2);
357}
358
359static int msm_gpio_clear_detect_status(struct msm_gpio_chip *msm_chip,
360 unsigned offset)
361{
362 unsigned bit = BIT(offset);
363
364#if MSM_GPIO_BROKEN_INT_CLEAR
365 /* Save interrupts that already triggered before we loose them. */
366 /* Any interrupt that triggers between the read of int_status */
367 /* and the write to int_clear will still be lost though. */
368 msm_chip->int_status_copy |= readl(msm_chip->regs.int_status);
369 msm_chip->int_status_copy &= ~bit;
370#endif
371 writel(bit, msm_chip->regs.int_clear);
372 msm_gpio_update_both_edge_detect(msm_chip);
373 return 0;
374}
375
376static int msm_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
377{
378 struct msm_gpio_chip *msm_chip;
379 unsigned long irq_flags;
380
381 msm_chip = container_of(chip, struct msm_gpio_chip, chip);
382 spin_lock_irqsave(&msm_chip->lock, irq_flags);
383 writel(readl(msm_chip->regs.oe) & ~BIT(offset), msm_chip->regs.oe);
384 spin_unlock_irqrestore(&msm_chip->lock, irq_flags);
385 return 0;
386}
387
388static int
389msm_gpio_direction_output(struct gpio_chip *chip, unsigned offset, int value)
390{
391 struct msm_gpio_chip *msm_chip;
392 unsigned long irq_flags;
393
394 msm_chip = container_of(chip, struct msm_gpio_chip, chip);
395 spin_lock_irqsave(&msm_chip->lock, irq_flags);
396 msm_gpio_write(msm_chip, offset, value);
397 writel(readl(msm_chip->regs.oe) | BIT(offset), msm_chip->regs.oe);
398 spin_unlock_irqrestore(&msm_chip->lock, irq_flags);
399 return 0;
400}
401
402static int msm_gpio_get(struct gpio_chip *chip, unsigned offset)
403{
404 struct msm_gpio_chip *msm_chip;
405
406 msm_chip = container_of(chip, struct msm_gpio_chip, chip);
407 return (readl(msm_chip->regs.in) & (1U << offset)) ? 1 : 0;
408}
409
410static void msm_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
411{
412 struct msm_gpio_chip *msm_chip;
413 unsigned long irq_flags;
414
415 msm_chip = container_of(chip, struct msm_gpio_chip, chip);
416 spin_lock_irqsave(&msm_chip->lock, irq_flags);
417 msm_gpio_write(msm_chip, offset, value);
418 spin_unlock_irqrestore(&msm_chip->lock, irq_flags);
419}
420
421static int msm_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
422{
423 return MSM_GPIO_TO_INT(chip->base + offset);
424}
425
426#ifdef CONFIG_MSM_GPIOMUX
427static int msm_gpio_request(struct gpio_chip *chip, unsigned offset)
428{
429 return msm_gpiomux_get(chip->base + offset);
430}
431
432static void msm_gpio_free(struct gpio_chip *chip, unsigned offset)
433{
434 msm_gpiomux_put(chip->base + offset);
435}
436#else
437#define msm_gpio_request NULL
438#define msm_gpio_free NULL
439#endif
440
441static struct msm_gpio_chip *msm_gpio_chips;
442static int msm_gpio_count;
443
444static struct msm_gpio_chip msm_gpio_chips_msm7x01[] = {
445 MSM_GPIO_BANK(MSM7X00, 0, 0, 15),
446 MSM_GPIO_BANK(MSM7X00, 1, 16, 42),
447 MSM_GPIO_BANK(MSM7X00, 2, 43, 67),
448 MSM_GPIO_BANK(MSM7X00, 3, 68, 94),
449 MSM_GPIO_BANK(MSM7X00, 4, 95, 106),
450 MSM_GPIO_BANK(MSM7X00, 5, 107, 121),
451};
452
453static struct msm_gpio_chip msm_gpio_chips_msm7x30[] = {
454 MSM_GPIO_BANK(MSM7X30, 0, 0, 15),
455 MSM_GPIO_BANK(MSM7X30, 1, 16, 43),
456 MSM_GPIO_BANK(MSM7X30, 2, 44, 67),
457 MSM_GPIO_BANK(MSM7X30, 3, 68, 94),
458 MSM_GPIO_BANK(MSM7X30, 4, 95, 106),
459 MSM_GPIO_BANK(MSM7X30, 5, 107, 133),
460 MSM_GPIO_BANK(MSM7X30, 6, 134, 150),
461 MSM_GPIO_BANK(MSM7X30, 7, 151, 181),
462};
463
464static struct msm_gpio_chip msm_gpio_chips_qsd8x50[] = {
465 MSM_GPIO_BANK(QSD8X50, 0, 0, 15),
466 MSM_GPIO_BANK(QSD8X50, 1, 16, 42),
467 MSM_GPIO_BANK(QSD8X50, 2, 43, 67),
468 MSM_GPIO_BANK(QSD8X50, 3, 68, 94),
469 MSM_GPIO_BANK(QSD8X50, 4, 95, 103),
470 MSM_GPIO_BANK(QSD8X50, 5, 104, 121),
471 MSM_GPIO_BANK(QSD8X50, 6, 122, 152),
472 MSM_GPIO_BANK(QSD8X50, 7, 153, 164),
473};
474
475static void msm_gpio_irq_ack(struct irq_data *d)
476{
477 unsigned long irq_flags;
478 struct msm_gpio_chip *msm_chip = irq_data_get_irq_chip_data(d);
479 spin_lock_irqsave(&msm_chip->lock, irq_flags);
480 msm_gpio_clear_detect_status(msm_chip,
481 d->irq - gpio_to_irq(msm_chip->chip.base));
482 spin_unlock_irqrestore(&msm_chip->lock, irq_flags);
483}
484
485static void msm_gpio_irq_mask(struct irq_data *d)
486{
487 unsigned long irq_flags;
488 struct msm_gpio_chip *msm_chip = irq_data_get_irq_chip_data(d);
489 unsigned offset = d->irq - gpio_to_irq(msm_chip->chip.base);
490
491 spin_lock_irqsave(&msm_chip->lock, irq_flags);
492 /* level triggered interrupts are also latched */
493 if (!(readl(msm_chip->regs.int_edge) & BIT(offset)))
494 msm_gpio_clear_detect_status(msm_chip, offset);
495 msm_chip->int_enable[0] &= ~BIT(offset);
496 writel(msm_chip->int_enable[0], msm_chip->regs.int_en);
497 spin_unlock_irqrestore(&msm_chip->lock, irq_flags);
498}
499
500static void msm_gpio_irq_unmask(struct irq_data *d)
501{
502 unsigned long irq_flags;
503 struct msm_gpio_chip *msm_chip = irq_data_get_irq_chip_data(d);
504 unsigned offset = d->irq - gpio_to_irq(msm_chip->chip.base);
505
506 spin_lock_irqsave(&msm_chip->lock, irq_flags);
507 /* level triggered interrupts are also latched */
508 if (!(readl(msm_chip->regs.int_edge) & BIT(offset)))
509 msm_gpio_clear_detect_status(msm_chip, offset);
510 msm_chip->int_enable[0] |= BIT(offset);
511 writel(msm_chip->int_enable[0], msm_chip->regs.int_en);
512 spin_unlock_irqrestore(&msm_chip->lock, irq_flags);
513}
514
515static int msm_gpio_irq_set_wake(struct irq_data *d, unsigned int on)
516{
517 unsigned long irq_flags;
518 struct msm_gpio_chip *msm_chip = irq_data_get_irq_chip_data(d);
519 unsigned offset = d->irq - gpio_to_irq(msm_chip->chip.base);
520
521 spin_lock_irqsave(&msm_chip->lock, irq_flags);
522
523 if (on)
524 msm_chip->int_enable[1] |= BIT(offset);
525 else
526 msm_chip->int_enable[1] &= ~BIT(offset);
527
528 spin_unlock_irqrestore(&msm_chip->lock, irq_flags);
529 return 0;
530}
531
532static int msm_gpio_irq_set_type(struct irq_data *d, unsigned int flow_type)
533{
534 unsigned long irq_flags;
535 struct msm_gpio_chip *msm_chip = irq_data_get_irq_chip_data(d);
536 unsigned offset = d->irq - gpio_to_irq(msm_chip->chip.base);
537 unsigned val, mask = BIT(offset);
538
539 spin_lock_irqsave(&msm_chip->lock, irq_flags);
540 val = readl(msm_chip->regs.int_edge);
541 if (flow_type & IRQ_TYPE_EDGE_BOTH) {
542 writel(val | mask, msm_chip->regs.int_edge);
543 __irq_set_handler_locked(d->irq, handle_edge_irq);
544 } else {
545 writel(val & ~mask, msm_chip->regs.int_edge);
546 __irq_set_handler_locked(d->irq, handle_level_irq);
547 }
548 if ((flow_type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) {
549 msm_chip->both_edge_detect |= mask;
550 msm_gpio_update_both_edge_detect(msm_chip);
551 } else {
552 msm_chip->both_edge_detect &= ~mask;
553 val = readl(msm_chip->regs.int_pos);
554 if (flow_type & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_HIGH))
555 writel(val | mask, msm_chip->regs.int_pos);
556 else
557 writel(val & ~mask, msm_chip->regs.int_pos);
558 }
559 spin_unlock_irqrestore(&msm_chip->lock, irq_flags);
560 return 0;
561}
562
563static void msm_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
564{
565 int i, j, mask;
566 unsigned val;
567
568 for (i = 0; i < msm_gpio_count; i++) {
569 struct msm_gpio_chip *msm_chip = &msm_gpio_chips[i];
570 val = readl(msm_chip->regs.int_status);
571 val &= msm_chip->int_enable[0];
572 while (val) {
573 mask = val & -val;
574 j = fls(mask) - 1;
575 /* printk("%s %08x %08x bit %d gpio %d irq %d\n",
576 __func__, v, m, j, msm_chip->chip.start + j,
577 FIRST_GPIO_IRQ + msm_chip->chip.start + j); */
578 val &= ~mask;
579 generic_handle_irq(FIRST_GPIO_IRQ +
580 msm_chip->chip.base + j);
581 }
582 }
583 desc->irq_data.chip->irq_ack(&desc->irq_data);
584}
585
586static struct irq_chip msm_gpio_irq_chip = {
587 .name = "msmgpio",
588 .irq_ack = msm_gpio_irq_ack,
589 .irq_mask = msm_gpio_irq_mask,
590 .irq_unmask = msm_gpio_irq_unmask,
591 .irq_set_wake = msm_gpio_irq_set_wake,
592 .irq_set_type = msm_gpio_irq_set_type,
593};
594
595static int __init msm_init_gpio(void)
596{
597 int i, j = 0;
598
599 if (cpu_is_msm7x01()) {
600 msm_gpio_chips = msm_gpio_chips_msm7x01;
601 msm_gpio_count = ARRAY_SIZE(msm_gpio_chips_msm7x01);
602 } else if (cpu_is_msm7x30()) {
603 msm_gpio_chips = msm_gpio_chips_msm7x30;
604 msm_gpio_count = ARRAY_SIZE(msm_gpio_chips_msm7x30);
605 } else if (cpu_is_qsd8x50()) {
606 msm_gpio_chips = msm_gpio_chips_qsd8x50;
607 msm_gpio_count = ARRAY_SIZE(msm_gpio_chips_qsd8x50);
608 } else {
609 return 0;
610 }
611
612 for (i = FIRST_GPIO_IRQ; i < FIRST_GPIO_IRQ + NR_GPIO_IRQS; i++) {
613 if (i - FIRST_GPIO_IRQ >=
614 msm_gpio_chips[j].chip.base +
615 msm_gpio_chips[j].chip.ngpio)
616 j++;
617 irq_set_chip_data(i, &msm_gpio_chips[j]);
618 irq_set_chip_and_handler(i, &msm_gpio_irq_chip,
619 handle_edge_irq);
620 set_irq_flags(i, IRQF_VALID);
621 }
622
623 for (i = 0; i < msm_gpio_count; i++) {
624 spin_lock_init(&msm_gpio_chips[i].lock);
625 writel(0, msm_gpio_chips[i].regs.int_en);
626 gpiochip_add(&msm_gpio_chips[i].chip);
627 }
628
629 irq_set_chained_handler(INT_GPIO_GROUP1, msm_gpio_irq_handler);
630 irq_set_chained_handler(INT_GPIO_GROUP2, msm_gpio_irq_handler);
631 irq_set_irq_wake(INT_GPIO_GROUP1, 1);
632 irq_set_irq_wake(INT_GPIO_GROUP2, 2);
633 return 0;
634}
635
636postcore_initcall(msm_init_gpio);
diff --git a/drivers/gpio/gpio-msm-v2.c b/drivers/gpio/gpio-msm-v2.c
new file mode 100644
index 00000000000..5cb1227d69c
--- /dev/null
+++ b/drivers/gpio/gpio-msm-v2.c
@@ -0,0 +1,433 @@
1/* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 *
12 * You should have received a copy of the GNU General Public License
13 * along with this program; if not, write to the Free Software
14 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
15 * 02110-1301, USA.
16 *
17 */
18#define pr_fmt(fmt) "%s: " fmt, __func__
19
20#include <linux/bitmap.h>
21#include <linux/bitops.h>
22#include <linux/gpio.h>
23#include <linux/init.h>
24#include <linux/interrupt.h>
25#include <linux/io.h>
26#include <linux/irq.h>
27#include <linux/module.h>
28#include <linux/platform_device.h>
29#include <linux/spinlock.h>
30
31#include <asm/mach/irq.h>
32
33#include <mach/msm_gpiomux.h>
34#include <mach/msm_iomap.h>
35
36/* Bits of interest in the GPIO_IN_OUT register.
37 */
38enum {
39 GPIO_IN = 0,
40 GPIO_OUT = 1
41};
42
43/* Bits of interest in the GPIO_INTR_STATUS register.
44 */
45enum {
46 INTR_STATUS = 0,
47};
48
49/* Bits of interest in the GPIO_CFG register.
50 */
51enum {
52 GPIO_OE = 9,
53};
54
55/* Bits of interest in the GPIO_INTR_CFG register.
56 * When a GPIO triggers, two separate decisions are made, controlled
57 * by two separate flags.
58 *
59 * - First, INTR_RAW_STATUS_EN controls whether or not the GPIO_INTR_STATUS
60 * register for that GPIO will be updated to reflect the triggering of that
61 * gpio. If this bit is 0, this register will not be updated.
62 * - Second, INTR_ENABLE controls whether an interrupt is triggered.
63 *
64 * If INTR_ENABLE is set and INTR_RAW_STATUS_EN is NOT set, an interrupt
65 * can be triggered but the status register will not reflect it.
66 */
67enum {
68 INTR_ENABLE = 0,
69 INTR_POL_CTL = 1,
70 INTR_DECT_CTL = 2,
71 INTR_RAW_STATUS_EN = 3,
72};
73
74/* Codes of interest in GPIO_INTR_CFG_SU.
75 */
76enum {
77 TARGET_PROC_SCORPION = 4,
78 TARGET_PROC_NONE = 7,
79};
80
81
82#define GPIO_INTR_CFG_SU(gpio) (MSM_TLMM_BASE + 0x0400 + (0x04 * (gpio)))
83#define GPIO_CONFIG(gpio) (MSM_TLMM_BASE + 0x1000 + (0x10 * (gpio)))
84#define GPIO_IN_OUT(gpio) (MSM_TLMM_BASE + 0x1004 + (0x10 * (gpio)))
85#define GPIO_INTR_CFG(gpio) (MSM_TLMM_BASE + 0x1008 + (0x10 * (gpio)))
86#define GPIO_INTR_STATUS(gpio) (MSM_TLMM_BASE + 0x100c + (0x10 * (gpio)))
87
88/**
89 * struct msm_gpio_dev: the MSM8660 SoC GPIO device structure
90 *
91 * @enabled_irqs: a bitmap used to optimize the summary-irq handler. By
92 * keeping track of which gpios are unmasked as irq sources, we avoid
93 * having to do readl calls on hundreds of iomapped registers each time
94 * the summary interrupt fires in order to locate the active interrupts.
95 *
96 * @wake_irqs: a bitmap for tracking which interrupt lines are enabled
97 * as wakeup sources. When the device is suspended, interrupts which are
98 * not wakeup sources are disabled.
99 *
100 * @dual_edge_irqs: a bitmap used to track which irqs are configured
101 * as dual-edge, as this is not supported by the hardware and requires
102 * some special handling in the driver.
103 */
104struct msm_gpio_dev {
105 struct gpio_chip gpio_chip;
106 DECLARE_BITMAP(enabled_irqs, NR_GPIO_IRQS);
107 DECLARE_BITMAP(wake_irqs, NR_GPIO_IRQS);
108 DECLARE_BITMAP(dual_edge_irqs, NR_GPIO_IRQS);
109};
110
111static DEFINE_SPINLOCK(tlmm_lock);
112
113static inline struct msm_gpio_dev *to_msm_gpio_dev(struct gpio_chip *chip)
114{
115 return container_of(chip, struct msm_gpio_dev, gpio_chip);
116}
117
118static inline void set_gpio_bits(unsigned n, void __iomem *reg)
119{
120 writel(readl(reg) | n, reg);
121}
122
123static inline void clear_gpio_bits(unsigned n, void __iomem *reg)
124{
125 writel(readl(reg) & ~n, reg);
126}
127
128static int msm_gpio_get(struct gpio_chip *chip, unsigned offset)
129{
130 return readl(GPIO_IN_OUT(offset)) & BIT(GPIO_IN);
131}
132
133static void msm_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
134{
135 writel(val ? BIT(GPIO_OUT) : 0, GPIO_IN_OUT(offset));
136}
137
138static int msm_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
139{
140 unsigned long irq_flags;
141
142 spin_lock_irqsave(&tlmm_lock, irq_flags);
143 clear_gpio_bits(BIT(GPIO_OE), GPIO_CONFIG(offset));
144 spin_unlock_irqrestore(&tlmm_lock, irq_flags);
145 return 0;
146}
147
148static int msm_gpio_direction_output(struct gpio_chip *chip,
149 unsigned offset,
150 int val)
151{
152 unsigned long irq_flags;
153
154 spin_lock_irqsave(&tlmm_lock, irq_flags);
155 msm_gpio_set(chip, offset, val);
156 set_gpio_bits(BIT(GPIO_OE), GPIO_CONFIG(offset));
157 spin_unlock_irqrestore(&tlmm_lock, irq_flags);
158 return 0;
159}
160
161static int msm_gpio_request(struct gpio_chip *chip, unsigned offset)
162{
163 return msm_gpiomux_get(chip->base + offset);
164}
165
166static void msm_gpio_free(struct gpio_chip *chip, unsigned offset)
167{
168 msm_gpiomux_put(chip->base + offset);
169}
170
171static int msm_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
172{
173 return MSM_GPIO_TO_INT(chip->base + offset);
174}
175
176static inline int msm_irq_to_gpio(struct gpio_chip *chip, unsigned irq)
177{
178 return irq - MSM_GPIO_TO_INT(chip->base);
179}
180
181static struct msm_gpio_dev msm_gpio = {
182 .gpio_chip = {
183 .base = 0,
184 .ngpio = NR_GPIO_IRQS,
185 .direction_input = msm_gpio_direction_input,
186 .direction_output = msm_gpio_direction_output,
187 .get = msm_gpio_get,
188 .set = msm_gpio_set,
189 .to_irq = msm_gpio_to_irq,
190 .request = msm_gpio_request,
191 .free = msm_gpio_free,
192 },
193};
194
195/* For dual-edge interrupts in software, since the hardware has no
196 * such support:
197 *
198 * At appropriate moments, this function may be called to flip the polarity
199 * settings of both-edge irq lines to try and catch the next edge.
200 *
201 * The attempt is considered successful if:
202 * - the status bit goes high, indicating that an edge was caught, or
203 * - the input value of the gpio doesn't change during the attempt.
204 * If the value changes twice during the process, that would cause the first
205 * test to fail but would force the second, as two opposite
206 * transitions would cause a detection no matter the polarity setting.
207 *
208 * The do-loop tries to sledge-hammer closed the timing hole between
209 * the initial value-read and the polarity-write - if the line value changes
210 * during that window, an interrupt is lost, the new polarity setting is
211 * incorrect, and the first success test will fail, causing a retry.
212 *
213 * Algorithm comes from Google's msmgpio driver, see mach-msm/gpio.c.
214 */
215static void msm_gpio_update_dual_edge_pos(unsigned gpio)
216{
217 int loop_limit = 100;
218 unsigned val, val2, intstat;
219
220 do {
221 val = readl(GPIO_IN_OUT(gpio)) & BIT(GPIO_IN);
222 if (val)
223 clear_gpio_bits(BIT(INTR_POL_CTL), GPIO_INTR_CFG(gpio));
224 else
225 set_gpio_bits(BIT(INTR_POL_CTL), GPIO_INTR_CFG(gpio));
226 val2 = readl(GPIO_IN_OUT(gpio)) & BIT(GPIO_IN);
227 intstat = readl(GPIO_INTR_STATUS(gpio)) & BIT(INTR_STATUS);
228 if (intstat || val == val2)
229 return;
230 } while (loop_limit-- > 0);
231 pr_err("dual-edge irq failed to stabilize, "
232 "interrupts dropped. %#08x != %#08x\n",
233 val, val2);
234}
235
236static void msm_gpio_irq_ack(struct irq_data *d)
237{
238 int gpio = msm_irq_to_gpio(&msm_gpio.gpio_chip, d->irq);
239
240 writel(BIT(INTR_STATUS), GPIO_INTR_STATUS(gpio));
241 if (test_bit(gpio, msm_gpio.dual_edge_irqs))
242 msm_gpio_update_dual_edge_pos(gpio);
243}
244
245static void msm_gpio_irq_mask(struct irq_data *d)
246{
247 int gpio = msm_irq_to_gpio(&msm_gpio.gpio_chip, d->irq);
248 unsigned long irq_flags;
249
250 spin_lock_irqsave(&tlmm_lock, irq_flags);
251 writel(TARGET_PROC_NONE, GPIO_INTR_CFG_SU(gpio));
252 clear_gpio_bits(INTR_RAW_STATUS_EN | INTR_ENABLE, GPIO_INTR_CFG(gpio));
253 __clear_bit(gpio, msm_gpio.enabled_irqs);
254 spin_unlock_irqrestore(&tlmm_lock, irq_flags);
255}
256
257static void msm_gpio_irq_unmask(struct irq_data *d)
258{
259 int gpio = msm_irq_to_gpio(&msm_gpio.gpio_chip, d->irq);
260 unsigned long irq_flags;
261
262 spin_lock_irqsave(&tlmm_lock, irq_flags);
263 __set_bit(gpio, msm_gpio.enabled_irqs);
264 set_gpio_bits(INTR_RAW_STATUS_EN | INTR_ENABLE, GPIO_INTR_CFG(gpio));
265 writel(TARGET_PROC_SCORPION, GPIO_INTR_CFG_SU(gpio));
266 spin_unlock_irqrestore(&tlmm_lock, irq_flags);
267}
268
269static int msm_gpio_irq_set_type(struct irq_data *d, unsigned int flow_type)
270{
271 int gpio = msm_irq_to_gpio(&msm_gpio.gpio_chip, d->irq);
272 unsigned long irq_flags;
273 uint32_t bits;
274
275 spin_lock_irqsave(&tlmm_lock, irq_flags);
276
277 bits = readl(GPIO_INTR_CFG(gpio));
278
279 if (flow_type & IRQ_TYPE_EDGE_BOTH) {
280 bits |= BIT(INTR_DECT_CTL);
281 __irq_set_handler_locked(d->irq, handle_edge_irq);
282 if ((flow_type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH)
283 __set_bit(gpio, msm_gpio.dual_edge_irqs);
284 else
285 __clear_bit(gpio, msm_gpio.dual_edge_irqs);
286 } else {
287 bits &= ~BIT(INTR_DECT_CTL);
288 __irq_set_handler_locked(d->irq, handle_level_irq);
289 __clear_bit(gpio, msm_gpio.dual_edge_irqs);
290 }
291
292 if (flow_type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_LEVEL_HIGH))
293 bits |= BIT(INTR_POL_CTL);
294 else
295 bits &= ~BIT(INTR_POL_CTL);
296
297 writel(bits, GPIO_INTR_CFG(gpio));
298
299 if ((flow_type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH)
300 msm_gpio_update_dual_edge_pos(gpio);
301
302 spin_unlock_irqrestore(&tlmm_lock, irq_flags);
303
304 return 0;
305}
306
307/*
308 * When the summary IRQ is raised, any number of GPIO lines may be high.
309 * It is the job of the summary handler to find all those GPIO lines
310 * which have been set as summary IRQ lines and which are triggered,
311 * and to call their interrupt handlers.
312 */
313static void msm_summary_irq_handler(unsigned int irq, struct irq_desc *desc)
314{
315 unsigned long i;
316 struct irq_chip *chip = irq_desc_get_chip(desc);
317
318 chained_irq_enter(chip, desc);
319
320 for (i = find_first_bit(msm_gpio.enabled_irqs, NR_GPIO_IRQS);
321 i < NR_GPIO_IRQS;
322 i = find_next_bit(msm_gpio.enabled_irqs, NR_GPIO_IRQS, i + 1)) {
323 if (readl(GPIO_INTR_STATUS(i)) & BIT(INTR_STATUS))
324 generic_handle_irq(msm_gpio_to_irq(&msm_gpio.gpio_chip,
325 i));
326 }
327
328 chained_irq_exit(chip, desc);
329}
330
331static int msm_gpio_irq_set_wake(struct irq_data *d, unsigned int on)
332{
333 int gpio = msm_irq_to_gpio(&msm_gpio.gpio_chip, d->irq);
334
335 if (on) {
336 if (bitmap_empty(msm_gpio.wake_irqs, NR_GPIO_IRQS))
337 irq_set_irq_wake(TLMM_SCSS_SUMMARY_IRQ, 1);
338 set_bit(gpio, msm_gpio.wake_irqs);
339 } else {
340 clear_bit(gpio, msm_gpio.wake_irqs);
341 if (bitmap_empty(msm_gpio.wake_irqs, NR_GPIO_IRQS))
342 irq_set_irq_wake(TLMM_SCSS_SUMMARY_IRQ, 0);
343 }
344
345 return 0;
346}
347
348static struct irq_chip msm_gpio_irq_chip = {
349 .name = "msmgpio",
350 .irq_mask = msm_gpio_irq_mask,
351 .irq_unmask = msm_gpio_irq_unmask,
352 .irq_ack = msm_gpio_irq_ack,
353 .irq_set_type = msm_gpio_irq_set_type,
354 .irq_set_wake = msm_gpio_irq_set_wake,
355};
356
357static int __devinit msm_gpio_probe(struct platform_device *dev)
358{
359 int i, irq, ret;
360
361 bitmap_zero(msm_gpio.enabled_irqs, NR_GPIO_IRQS);
362 bitmap_zero(msm_gpio.wake_irqs, NR_GPIO_IRQS);
363 bitmap_zero(msm_gpio.dual_edge_irqs, NR_GPIO_IRQS);
364 msm_gpio.gpio_chip.label = dev->name;
365 ret = gpiochip_add(&msm_gpio.gpio_chip);
366 if (ret < 0)
367 return ret;
368
369 for (i = 0; i < msm_gpio.gpio_chip.ngpio; ++i) {
370 irq = msm_gpio_to_irq(&msm_gpio.gpio_chip, i);
371 irq_set_chip_and_handler(irq, &msm_gpio_irq_chip,
372 handle_level_irq);
373 set_irq_flags(irq, IRQF_VALID);
374 }
375
376 irq_set_chained_handler(TLMM_SCSS_SUMMARY_IRQ,
377 msm_summary_irq_handler);
378 return 0;
379}
380
381static int __devexit msm_gpio_remove(struct platform_device *dev)
382{
383 int ret = gpiochip_remove(&msm_gpio.gpio_chip);
384
385 if (ret < 0)
386 return ret;
387
388 irq_set_handler(TLMM_SCSS_SUMMARY_IRQ, NULL);
389
390 return 0;
391}
392
393static struct platform_driver msm_gpio_driver = {
394 .probe = msm_gpio_probe,
395 .remove = __devexit_p(msm_gpio_remove),
396 .driver = {
397 .name = "msmgpio",
398 .owner = THIS_MODULE,
399 },
400};
401
402static struct platform_device msm_device_gpio = {
403 .name = "msmgpio",
404 .id = -1,
405};
406
407static int __init msm_gpio_init(void)
408{
409 int rc;
410
411 rc = platform_driver_register(&msm_gpio_driver);
412 if (!rc) {
413 rc = platform_device_register(&msm_device_gpio);
414 if (rc)
415 platform_driver_unregister(&msm_gpio_driver);
416 }
417
418 return rc;
419}
420
421static void __exit msm_gpio_exit(void)
422{
423 platform_device_unregister(&msm_device_gpio);
424 platform_driver_unregister(&msm_gpio_driver);
425}
426
427postcore_initcall(msm_gpio_init);
428module_exit(msm_gpio_exit);
429
430MODULE_AUTHOR("Gregory Bean <gbean@codeaurora.org>");
431MODULE_DESCRIPTION("Driver for Qualcomm MSM TLMMv2 SoC GPIOs");
432MODULE_LICENSE("GPL v2");
433MODULE_ALIAS("platform:msmgpio");
diff --git a/drivers/gpio/gpio-mxc.c b/drivers/gpio/gpio-mxc.c
new file mode 100644
index 00000000000..4340acae3bd
--- /dev/null
+++ b/drivers/gpio/gpio-mxc.c
@@ -0,0 +1,460 @@
1/*
2 * MXC GPIO support. (c) 2008 Daniel Mack <daniel@caiaq.de>
3 * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
4 *
5 * Based on code from Freescale,
6 * Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * as published by the Free Software Foundation; either version 2
11 * of the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
20 */
21
22#include <linux/init.h>
23#include <linux/interrupt.h>
24#include <linux/io.h>
25#include <linux/irq.h>
26#include <linux/gpio.h>
27#include <linux/platform_device.h>
28#include <linux/slab.h>
29#include <linux/basic_mmio_gpio.h>
30#include <linux/of.h>
31#include <linux/of_device.h>
32#include <asm-generic/bug.h>
33
34enum mxc_gpio_hwtype {
35 IMX1_GPIO, /* runs on i.mx1 */
36 IMX21_GPIO, /* runs on i.mx21 and i.mx27 */
37 IMX31_GPIO, /* runs on all other i.mx */
38};
39
40/* device type dependent stuff */
41struct mxc_gpio_hwdata {
42 unsigned dr_reg;
43 unsigned gdir_reg;
44 unsigned psr_reg;
45 unsigned icr1_reg;
46 unsigned icr2_reg;
47 unsigned imr_reg;
48 unsigned isr_reg;
49 unsigned low_level;
50 unsigned high_level;
51 unsigned rise_edge;
52 unsigned fall_edge;
53};
54
55struct mxc_gpio_port {
56 struct list_head node;
57 void __iomem *base;
58 int irq;
59 int irq_high;
60 int virtual_irq_start;
61 struct bgpio_chip bgc;
62 u32 both_edges;
63};
64
65static struct mxc_gpio_hwdata imx1_imx21_gpio_hwdata = {
66 .dr_reg = 0x1c,
67 .gdir_reg = 0x00,
68 .psr_reg = 0x24,
69 .icr1_reg = 0x28,
70 .icr2_reg = 0x2c,
71 .imr_reg = 0x30,
72 .isr_reg = 0x34,
73 .low_level = 0x03,
74 .high_level = 0x02,
75 .rise_edge = 0x00,
76 .fall_edge = 0x01,
77};
78
79static struct mxc_gpio_hwdata imx31_gpio_hwdata = {
80 .dr_reg = 0x00,
81 .gdir_reg = 0x04,
82 .psr_reg = 0x08,
83 .icr1_reg = 0x0c,
84 .icr2_reg = 0x10,
85 .imr_reg = 0x14,
86 .isr_reg = 0x18,
87 .low_level = 0x00,
88 .high_level = 0x01,
89 .rise_edge = 0x02,
90 .fall_edge = 0x03,
91};
92
93static enum mxc_gpio_hwtype mxc_gpio_hwtype;
94static struct mxc_gpio_hwdata *mxc_gpio_hwdata;
95
96#define GPIO_DR (mxc_gpio_hwdata->dr_reg)
97#define GPIO_GDIR (mxc_gpio_hwdata->gdir_reg)
98#define GPIO_PSR (mxc_gpio_hwdata->psr_reg)
99#define GPIO_ICR1 (mxc_gpio_hwdata->icr1_reg)
100#define GPIO_ICR2 (mxc_gpio_hwdata->icr2_reg)
101#define GPIO_IMR (mxc_gpio_hwdata->imr_reg)
102#define GPIO_ISR (mxc_gpio_hwdata->isr_reg)
103
104#define GPIO_INT_LOW_LEV (mxc_gpio_hwdata->low_level)
105#define GPIO_INT_HIGH_LEV (mxc_gpio_hwdata->high_level)
106#define GPIO_INT_RISE_EDGE (mxc_gpio_hwdata->rise_edge)
107#define GPIO_INT_FALL_EDGE (mxc_gpio_hwdata->fall_edge)
108#define GPIO_INT_NONE 0x4
109
110static struct platform_device_id mxc_gpio_devtype[] = {
111 {
112 .name = "imx1-gpio",
113 .driver_data = IMX1_GPIO,
114 }, {
115 .name = "imx21-gpio",
116 .driver_data = IMX21_GPIO,
117 }, {
118 .name = "imx31-gpio",
119 .driver_data = IMX31_GPIO,
120 }, {
121 /* sentinel */
122 }
123};
124
125static const struct of_device_id mxc_gpio_dt_ids[] = {
126 { .compatible = "fsl,imx1-gpio", .data = &mxc_gpio_devtype[IMX1_GPIO], },
127 { .compatible = "fsl,imx21-gpio", .data = &mxc_gpio_devtype[IMX21_GPIO], },
128 { .compatible = "fsl,imx31-gpio", .data = &mxc_gpio_devtype[IMX31_GPIO], },
129 { /* sentinel */ }
130};
131
132/*
133 * MX2 has one interrupt *for all* gpio ports. The list is used
134 * to save the references to all ports, so that mx2_gpio_irq_handler
135 * can walk through all interrupt status registers.
136 */
137static LIST_HEAD(mxc_gpio_ports);
138
139/* Note: This driver assumes 32 GPIOs are handled in one register */
140
141static int gpio_set_irq_type(struct irq_data *d, u32 type)
142{
143 u32 gpio = irq_to_gpio(d->irq);
144 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
145 struct mxc_gpio_port *port = gc->private;
146 u32 bit, val;
147 int edge;
148 void __iomem *reg = port->base;
149
150 port->both_edges &= ~(1 << (gpio & 31));
151 switch (type) {
152 case IRQ_TYPE_EDGE_RISING:
153 edge = GPIO_INT_RISE_EDGE;
154 break;
155 case IRQ_TYPE_EDGE_FALLING:
156 edge = GPIO_INT_FALL_EDGE;
157 break;
158 case IRQ_TYPE_EDGE_BOTH:
159 val = gpio_get_value(gpio);
160 if (val) {
161 edge = GPIO_INT_LOW_LEV;
162 pr_debug("mxc: set GPIO %d to low trigger\n", gpio);
163 } else {
164 edge = GPIO_INT_HIGH_LEV;
165 pr_debug("mxc: set GPIO %d to high trigger\n", gpio);
166 }
167 port->both_edges |= 1 << (gpio & 31);
168 break;
169 case IRQ_TYPE_LEVEL_LOW:
170 edge = GPIO_INT_LOW_LEV;
171 break;
172 case IRQ_TYPE_LEVEL_HIGH:
173 edge = GPIO_INT_HIGH_LEV;
174 break;
175 default:
176 return -EINVAL;
177 }
178
179 reg += GPIO_ICR1 + ((gpio & 0x10) >> 2); /* lower or upper register */
180 bit = gpio & 0xf;
181 val = readl(reg) & ~(0x3 << (bit << 1));
182 writel(val | (edge << (bit << 1)), reg);
183 writel(1 << (gpio & 0x1f), port->base + GPIO_ISR);
184
185 return 0;
186}
187
188static void mxc_flip_edge(struct mxc_gpio_port *port, u32 gpio)
189{
190 void __iomem *reg = port->base;
191 u32 bit, val;
192 int edge;
193
194 reg += GPIO_ICR1 + ((gpio & 0x10) >> 2); /* lower or upper register */
195 bit = gpio & 0xf;
196 val = readl(reg);
197 edge = (val >> (bit << 1)) & 3;
198 val &= ~(0x3 << (bit << 1));
199 if (edge == GPIO_INT_HIGH_LEV) {
200 edge = GPIO_INT_LOW_LEV;
201 pr_debug("mxc: switch GPIO %d to low trigger\n", gpio);
202 } else if (edge == GPIO_INT_LOW_LEV) {
203 edge = GPIO_INT_HIGH_LEV;
204 pr_debug("mxc: switch GPIO %d to high trigger\n", gpio);
205 } else {
206 pr_err("mxc: invalid configuration for GPIO %d: %x\n",
207 gpio, edge);
208 return;
209 }
210 writel(val | (edge << (bit << 1)), reg);
211}
212
213/* handle 32 interrupts in one status register */
214static void mxc_gpio_irq_handler(struct mxc_gpio_port *port, u32 irq_stat)
215{
216 u32 gpio_irq_no_base = port->virtual_irq_start;
217
218 while (irq_stat != 0) {
219 int irqoffset = fls(irq_stat) - 1;
220
221 if (port->both_edges & (1 << irqoffset))
222 mxc_flip_edge(port, irqoffset);
223
224 generic_handle_irq(gpio_irq_no_base + irqoffset);
225
226 irq_stat &= ~(1 << irqoffset);
227 }
228}
229
230/* MX1 and MX3 has one interrupt *per* gpio port */
231static void mx3_gpio_irq_handler(u32 irq, struct irq_desc *desc)
232{
233 u32 irq_stat;
234 struct mxc_gpio_port *port = irq_get_handler_data(irq);
235
236 irq_stat = readl(port->base + GPIO_ISR) & readl(port->base + GPIO_IMR);
237
238 mxc_gpio_irq_handler(port, irq_stat);
239}
240
241/* MX2 has one interrupt *for all* gpio ports */
242static void mx2_gpio_irq_handler(u32 irq, struct irq_desc *desc)
243{
244 u32 irq_msk, irq_stat;
245 struct mxc_gpio_port *port;
246
247 /* walk through all interrupt status registers */
248 list_for_each_entry(port, &mxc_gpio_ports, node) {
249 irq_msk = readl(port->base + GPIO_IMR);
250 if (!irq_msk)
251 continue;
252
253 irq_stat = readl(port->base + GPIO_ISR) & irq_msk;
254 if (irq_stat)
255 mxc_gpio_irq_handler(port, irq_stat);
256 }
257}
258
259/*
260 * Set interrupt number "irq" in the GPIO as a wake-up source.
261 * While system is running, all registered GPIO interrupts need to have
262 * wake-up enabled. When system is suspended, only selected GPIO interrupts
263 * need to have wake-up enabled.
264 * @param irq interrupt source number
265 * @param enable enable as wake-up if equal to non-zero
266 * @return This function returns 0 on success.
267 */
268static int gpio_set_wake_irq(struct irq_data *d, u32 enable)
269{
270 u32 gpio = irq_to_gpio(d->irq);
271 u32 gpio_idx = gpio & 0x1F;
272 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
273 struct mxc_gpio_port *port = gc->private;
274
275 if (enable) {
276 if (port->irq_high && (gpio_idx >= 16))
277 enable_irq_wake(port->irq_high);
278 else
279 enable_irq_wake(port->irq);
280 } else {
281 if (port->irq_high && (gpio_idx >= 16))
282 disable_irq_wake(port->irq_high);
283 else
284 disable_irq_wake(port->irq);
285 }
286
287 return 0;
288}
289
290static void __init mxc_gpio_init_gc(struct mxc_gpio_port *port)
291{
292 struct irq_chip_generic *gc;
293 struct irq_chip_type *ct;
294
295 gc = irq_alloc_generic_chip("gpio-mxc", 1, port->virtual_irq_start,
296 port->base, handle_level_irq);
297 gc->private = port;
298
299 ct = gc->chip_types;
300 ct->chip.irq_ack = irq_gc_ack_set_bit;
301 ct->chip.irq_mask = irq_gc_mask_clr_bit;
302 ct->chip.irq_unmask = irq_gc_mask_set_bit;
303 ct->chip.irq_set_type = gpio_set_irq_type;
304 ct->chip.irq_set_wake = gpio_set_wake_irq;
305 ct->regs.ack = GPIO_ISR;
306 ct->regs.mask = GPIO_IMR;
307
308 irq_setup_generic_chip(gc, IRQ_MSK(32), IRQ_GC_INIT_NESTED_LOCK,
309 IRQ_NOREQUEST, 0);
310}
311
312static void __devinit mxc_gpio_get_hw(struct platform_device *pdev)
313{
314 const struct of_device_id *of_id =
315 of_match_device(mxc_gpio_dt_ids, &pdev->dev);
316 enum mxc_gpio_hwtype hwtype;
317
318 if (of_id)
319 pdev->id_entry = of_id->data;
320 hwtype = pdev->id_entry->driver_data;
321
322 if (mxc_gpio_hwtype) {
323 /*
324 * The driver works with a reasonable presupposition,
325 * that is all gpio ports must be the same type when
326 * running on one soc.
327 */
328 BUG_ON(mxc_gpio_hwtype != hwtype);
329 return;
330 }
331
332 if (hwtype == IMX31_GPIO)
333 mxc_gpio_hwdata = &imx31_gpio_hwdata;
334 else
335 mxc_gpio_hwdata = &imx1_imx21_gpio_hwdata;
336
337 mxc_gpio_hwtype = hwtype;
338}
339
340static int __devinit mxc_gpio_probe(struct platform_device *pdev)
341{
342 struct device_node *np = pdev->dev.of_node;
343 struct mxc_gpio_port *port;
344 struct resource *iores;
345 int err;
346
347 mxc_gpio_get_hw(pdev);
348
349 port = kzalloc(sizeof(struct mxc_gpio_port), GFP_KERNEL);
350 if (!port)
351 return -ENOMEM;
352
353 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
354 if (!iores) {
355 err = -ENODEV;
356 goto out_kfree;
357 }
358
359 if (!request_mem_region(iores->start, resource_size(iores),
360 pdev->name)) {
361 err = -EBUSY;
362 goto out_kfree;
363 }
364
365 port->base = ioremap(iores->start, resource_size(iores));
366 if (!port->base) {
367 err = -ENOMEM;
368 goto out_release_mem;
369 }
370
371 port->irq_high = platform_get_irq(pdev, 1);
372 port->irq = platform_get_irq(pdev, 0);
373 if (port->irq < 0) {
374 err = -EINVAL;
375 goto out_iounmap;
376 }
377
378 /* disable the interrupt and clear the status */
379 writel(0, port->base + GPIO_IMR);
380 writel(~0, port->base + GPIO_ISR);
381
382 if (mxc_gpio_hwtype == IMX21_GPIO) {
383 /* setup one handler for all GPIO interrupts */
384 if (pdev->id == 0)
385 irq_set_chained_handler(port->irq,
386 mx2_gpio_irq_handler);
387 } else {
388 /* setup one handler for each entry */
389 irq_set_chained_handler(port->irq, mx3_gpio_irq_handler);
390 irq_set_handler_data(port->irq, port);
391 if (port->irq_high > 0) {
392 /* setup handler for GPIO 16 to 31 */
393 irq_set_chained_handler(port->irq_high,
394 mx3_gpio_irq_handler);
395 irq_set_handler_data(port->irq_high, port);
396 }
397 }
398
399 err = bgpio_init(&port->bgc, &pdev->dev, 4,
400 port->base + GPIO_PSR,
401 port->base + GPIO_DR, NULL,
402 port->base + GPIO_GDIR, NULL, false);
403 if (err)
404 goto out_iounmap;
405
406 port->bgc.gc.base = pdev->id * 32;
407 port->bgc.dir = port->bgc.read_reg(port->bgc.reg_dir);
408 port->bgc.data = port->bgc.read_reg(port->bgc.reg_set);
409
410 err = gpiochip_add(&port->bgc.gc);
411 if (err)
412 goto out_bgpio_remove;
413
414 /*
415 * In dt case, we use gpio number range dynamically
416 * allocated by gpio core.
417 */
418 port->virtual_irq_start = MXC_GPIO_IRQ_START + (np ? port->bgc.gc.base :
419 pdev->id * 32);
420
421 /* gpio-mxc can be a generic irq chip */
422 mxc_gpio_init_gc(port);
423
424 list_add_tail(&port->node, &mxc_gpio_ports);
425
426 return 0;
427
428out_bgpio_remove:
429 bgpio_remove(&port->bgc);
430out_iounmap:
431 iounmap(port->base);
432out_release_mem:
433 release_mem_region(iores->start, resource_size(iores));
434out_kfree:
435 kfree(port);
436 dev_info(&pdev->dev, "%s failed with errno %d\n", __func__, err);
437 return err;
438}
439
440static struct platform_driver mxc_gpio_driver = {
441 .driver = {
442 .name = "gpio-mxc",
443 .owner = THIS_MODULE,
444 .of_match_table = mxc_gpio_dt_ids,
445 },
446 .probe = mxc_gpio_probe,
447 .id_table = mxc_gpio_devtype,
448};
449
450static int __init gpio_mxc_init(void)
451{
452 return platform_driver_register(&mxc_gpio_driver);
453}
454postcore_initcall(gpio_mxc_init);
455
456MODULE_AUTHOR("Freescale Semiconductor, "
457 "Daniel Mack <danielncaiaq.de>, "
458 "Juergen Beisert <kernel@pengutronix.de>");
459MODULE_DESCRIPTION("Freescale MXC GPIO");
460MODULE_LICENSE("GPL");
diff --git a/drivers/gpio/gpio-mxs.c b/drivers/gpio/gpio-mxs.c
new file mode 100644
index 00000000000..af55a8577c2
--- /dev/null
+++ b/drivers/gpio/gpio-mxs.c
@@ -0,0 +1,289 @@
1/*
2 * MXC GPIO support. (c) 2008 Daniel Mack <daniel@caiaq.de>
3 * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
4 *
5 * Based on code from Freescale,
6 * Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * as published by the Free Software Foundation; either version 2
11 * of the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
20 * MA 02110-1301, USA.
21 */
22
23#include <linux/init.h>
24#include <linux/interrupt.h>
25#include <linux/io.h>
26#include <linux/irq.h>
27#include <linux/gpio.h>
28#include <linux/platform_device.h>
29#include <linux/slab.h>
30#include <linux/basic_mmio_gpio.h>
31#include <mach/mxs.h>
32
33#define MXS_SET 0x4
34#define MXS_CLR 0x8
35
36#define PINCTRL_DOUT(n) ((cpu_is_mx23() ? 0x0500 : 0x0700) + (n) * 0x10)
37#define PINCTRL_DIN(n) ((cpu_is_mx23() ? 0x0600 : 0x0900) + (n) * 0x10)
38#define PINCTRL_DOE(n) ((cpu_is_mx23() ? 0x0700 : 0x0b00) + (n) * 0x10)
39#define PINCTRL_PIN2IRQ(n) ((cpu_is_mx23() ? 0x0800 : 0x1000) + (n) * 0x10)
40#define PINCTRL_IRQEN(n) ((cpu_is_mx23() ? 0x0900 : 0x1100) + (n) * 0x10)
41#define PINCTRL_IRQLEV(n) ((cpu_is_mx23() ? 0x0a00 : 0x1200) + (n) * 0x10)
42#define PINCTRL_IRQPOL(n) ((cpu_is_mx23() ? 0x0b00 : 0x1300) + (n) * 0x10)
43#define PINCTRL_IRQSTAT(n) ((cpu_is_mx23() ? 0x0c00 : 0x1400) + (n) * 0x10)
44
45#define GPIO_INT_FALL_EDGE 0x0
46#define GPIO_INT_LOW_LEV 0x1
47#define GPIO_INT_RISE_EDGE 0x2
48#define GPIO_INT_HIGH_LEV 0x3
49#define GPIO_INT_LEV_MASK (1 << 0)
50#define GPIO_INT_POL_MASK (1 << 1)
51
52struct mxs_gpio_port {
53 void __iomem *base;
54 int id;
55 int irq;
56 int virtual_irq_start;
57 struct bgpio_chip bgc;
58};
59
60/* Note: This driver assumes 32 GPIOs are handled in one register */
61
62static int mxs_gpio_set_irq_type(struct irq_data *d, unsigned int type)
63{
64 u32 gpio = irq_to_gpio(d->irq);
65 u32 pin_mask = 1 << (gpio & 31);
66 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
67 struct mxs_gpio_port *port = gc->private;
68 void __iomem *pin_addr;
69 int edge;
70
71 switch (type) {
72 case IRQ_TYPE_EDGE_RISING:
73 edge = GPIO_INT_RISE_EDGE;
74 break;
75 case IRQ_TYPE_EDGE_FALLING:
76 edge = GPIO_INT_FALL_EDGE;
77 break;
78 case IRQ_TYPE_LEVEL_LOW:
79 edge = GPIO_INT_LOW_LEV;
80 break;
81 case IRQ_TYPE_LEVEL_HIGH:
82 edge = GPIO_INT_HIGH_LEV;
83 break;
84 default:
85 return -EINVAL;
86 }
87
88 /* set level or edge */
89 pin_addr = port->base + PINCTRL_IRQLEV(port->id);
90 if (edge & GPIO_INT_LEV_MASK)
91 writel(pin_mask, pin_addr + MXS_SET);
92 else
93 writel(pin_mask, pin_addr + MXS_CLR);
94
95 /* set polarity */
96 pin_addr = port->base + PINCTRL_IRQPOL(port->id);
97 if (edge & GPIO_INT_POL_MASK)
98 writel(pin_mask, pin_addr + MXS_SET);
99 else
100 writel(pin_mask, pin_addr + MXS_CLR);
101
102 writel(1 << (gpio & 0x1f),
103 port->base + PINCTRL_IRQSTAT(port->id) + MXS_CLR);
104
105 return 0;
106}
107
108/* MXS has one interrupt *per* gpio port */
109static void mxs_gpio_irq_handler(u32 irq, struct irq_desc *desc)
110{
111 u32 irq_stat;
112 struct mxs_gpio_port *port = irq_get_handler_data(irq);
113 u32 gpio_irq_no_base = port->virtual_irq_start;
114
115 desc->irq_data.chip->irq_ack(&desc->irq_data);
116
117 irq_stat = readl(port->base + PINCTRL_IRQSTAT(port->id)) &
118 readl(port->base + PINCTRL_IRQEN(port->id));
119
120 while (irq_stat != 0) {
121 int irqoffset = fls(irq_stat) - 1;
122 generic_handle_irq(gpio_irq_no_base + irqoffset);
123 irq_stat &= ~(1 << irqoffset);
124 }
125}
126
127/*
128 * Set interrupt number "irq" in the GPIO as a wake-up source.
129 * While system is running, all registered GPIO interrupts need to have
130 * wake-up enabled. When system is suspended, only selected GPIO interrupts
131 * need to have wake-up enabled.
132 * @param irq interrupt source number
133 * @param enable enable as wake-up if equal to non-zero
134 * @return This function returns 0 on success.
135 */
136static int mxs_gpio_set_wake_irq(struct irq_data *d, unsigned int enable)
137{
138 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
139 struct mxs_gpio_port *port = gc->private;
140
141 if (enable)
142 enable_irq_wake(port->irq);
143 else
144 disable_irq_wake(port->irq);
145
146 return 0;
147}
148
149static void __init mxs_gpio_init_gc(struct mxs_gpio_port *port)
150{
151 struct irq_chip_generic *gc;
152 struct irq_chip_type *ct;
153
154 gc = irq_alloc_generic_chip("gpio-mxs", 1, port->virtual_irq_start,
155 port->base, handle_level_irq);
156 gc->private = port;
157
158 ct = gc->chip_types;
159 ct->chip.irq_ack = irq_gc_ack_set_bit;
160 ct->chip.irq_mask = irq_gc_mask_clr_bit;
161 ct->chip.irq_unmask = irq_gc_mask_set_bit;
162 ct->chip.irq_set_type = mxs_gpio_set_irq_type;
163 ct->chip.irq_set_wake = mxs_gpio_set_wake_irq;
164 ct->regs.ack = PINCTRL_IRQSTAT(port->id) + MXS_CLR;
165 ct->regs.mask = PINCTRL_IRQEN(port->id);
166
167 irq_setup_generic_chip(gc, IRQ_MSK(32), 0, IRQ_NOREQUEST, 0);
168}
169
170static int mxs_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
171{
172 struct bgpio_chip *bgc = to_bgpio_chip(gc);
173 struct mxs_gpio_port *port =
174 container_of(bgc, struct mxs_gpio_port, bgc);
175
176 return port->virtual_irq_start + offset;
177}
178
179static int __devinit mxs_gpio_probe(struct platform_device *pdev)
180{
181 static void __iomem *base;
182 struct mxs_gpio_port *port;
183 struct resource *iores = NULL;
184 int err;
185
186 port = kzalloc(sizeof(struct mxs_gpio_port), GFP_KERNEL);
187 if (!port)
188 return -ENOMEM;
189
190 port->id = pdev->id;
191 port->virtual_irq_start = MXS_GPIO_IRQ_START + port->id * 32;
192
193 /*
194 * map memory region only once, as all the gpio ports
195 * share the same one
196 */
197 if (!base) {
198 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
199 if (!iores) {
200 err = -ENODEV;
201 goto out_kfree;
202 }
203
204 if (!request_mem_region(iores->start, resource_size(iores),
205 pdev->name)) {
206 err = -EBUSY;
207 goto out_kfree;
208 }
209
210 base = ioremap(iores->start, resource_size(iores));
211 if (!base) {
212 err = -ENOMEM;
213 goto out_release_mem;
214 }
215 }
216 port->base = base;
217
218 port->irq = platform_get_irq(pdev, 0);
219 if (port->irq < 0) {
220 err = -EINVAL;
221 goto out_iounmap;
222 }
223
224 /*
225 * select the pin interrupt functionality but initially
226 * disable the interrupts
227 */
228 writel(~0U, port->base + PINCTRL_PIN2IRQ(port->id));
229 writel(0, port->base + PINCTRL_IRQEN(port->id));
230
231 /* clear address has to be used to clear IRQSTAT bits */
232 writel(~0U, port->base + PINCTRL_IRQSTAT(port->id) + MXS_CLR);
233
234 /* gpio-mxs can be a generic irq chip */
235 mxs_gpio_init_gc(port);
236
237 /* setup one handler for each entry */
238 irq_set_chained_handler(port->irq, mxs_gpio_irq_handler);
239 irq_set_handler_data(port->irq, port);
240
241 err = bgpio_init(&port->bgc, &pdev->dev, 4,
242 port->base + PINCTRL_DIN(port->id),
243 port->base + PINCTRL_DOUT(port->id), NULL,
244 port->base + PINCTRL_DOE(port->id), NULL, false);
245 if (err)
246 goto out_iounmap;
247
248 port->bgc.gc.to_irq = mxs_gpio_to_irq;
249 port->bgc.gc.base = port->id * 32;
250
251 err = gpiochip_add(&port->bgc.gc);
252 if (err)
253 goto out_bgpio_remove;
254
255 return 0;
256
257out_bgpio_remove:
258 bgpio_remove(&port->bgc);
259out_iounmap:
260 if (iores)
261 iounmap(port->base);
262out_release_mem:
263 if (iores)
264 release_mem_region(iores->start, resource_size(iores));
265out_kfree:
266 kfree(port);
267 dev_info(&pdev->dev, "%s failed with errno %d\n", __func__, err);
268 return err;
269}
270
271static struct platform_driver mxs_gpio_driver = {
272 .driver = {
273 .name = "gpio-mxs",
274 .owner = THIS_MODULE,
275 },
276 .probe = mxs_gpio_probe,
277};
278
279static int __init mxs_gpio_init(void)
280{
281 return platform_driver_register(&mxs_gpio_driver);
282}
283postcore_initcall(mxs_gpio_init);
284
285MODULE_AUTHOR("Freescale Semiconductor, "
286 "Daniel Mack <danielncaiaq.de>, "
287 "Juergen Beisert <kernel@pengutronix.de>");
288MODULE_DESCRIPTION("Freescale MXS GPIO");
289MODULE_LICENSE("GPL");
diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c
index 35bebde23e8..118ec12d2d5 100644
--- a/drivers/gpio/gpio-omap.c
+++ b/drivers/gpio/gpio-omap.c
@@ -34,8 +34,8 @@ struct gpio_bank {
34 u16 irq; 34 u16 irq;
35 u16 virtual_irq_start; 35 u16 virtual_irq_start;
36 int method; 36 int method;
37#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS)
38 u32 suspend_wakeup; 37 u32 suspend_wakeup;
38#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS)
39 u32 saved_wakeup; 39 u32 saved_wakeup;
40#endif 40#endif
41 u32 non_wakeup_gpios; 41 u32 non_wakeup_gpios;
@@ -54,6 +54,11 @@ struct gpio_bank {
54 struct device *dev; 54 struct device *dev;
55 bool dbck_flag; 55 bool dbck_flag;
56 int stride; 56 int stride;
57 u32 width;
58
59 void (*set_dataout)(struct gpio_bank *bank, int gpio, int enable);
60
61 struct omap_gpio_reg_offs *regs;
57}; 62};
58 63
59#ifdef CONFIG_ARCH_OMAP3 64#ifdef CONFIG_ARCH_OMAP3
@@ -79,121 +84,18 @@ static struct omap3_gpio_regs gpio_context[OMAP34XX_NR_GPIOS];
79 */ 84 */
80static struct gpio_bank *gpio_bank; 85static struct gpio_bank *gpio_bank;
81 86
82static int bank_width;
83
84/* TODO: Analyze removing gpio_bank_count usage from driver code */ 87/* TODO: Analyze removing gpio_bank_count usage from driver code */
85int gpio_bank_count; 88int gpio_bank_count;
86 89
87static inline struct gpio_bank *get_gpio_bank(int gpio) 90#define GPIO_INDEX(bank, gpio) (gpio % bank->width)
88{ 91#define GPIO_BIT(bank, gpio) (1 << GPIO_INDEX(bank, gpio))
89 if (cpu_is_omap15xx()) {
90 if (OMAP_GPIO_IS_MPUIO(gpio))
91 return &gpio_bank[0];
92 return &gpio_bank[1];
93 }
94 if (cpu_is_omap16xx()) {
95 if (OMAP_GPIO_IS_MPUIO(gpio))
96 return &gpio_bank[0];
97 return &gpio_bank[1 + (gpio >> 4)];
98 }
99 if (cpu_is_omap7xx()) {
100 if (OMAP_GPIO_IS_MPUIO(gpio))
101 return &gpio_bank[0];
102 return &gpio_bank[1 + (gpio >> 5)];
103 }
104 if (cpu_is_omap24xx())
105 return &gpio_bank[gpio >> 5];
106 if (cpu_is_omap34xx() || cpu_is_omap44xx())
107 return &gpio_bank[gpio >> 5];
108 BUG();
109 return NULL;
110}
111
112static inline int get_gpio_index(int gpio)
113{
114 if (cpu_is_omap7xx())
115 return gpio & 0x1f;
116 if (cpu_is_omap24xx())
117 return gpio & 0x1f;
118 if (cpu_is_omap34xx() || cpu_is_omap44xx())
119 return gpio & 0x1f;
120 return gpio & 0x0f;
121}
122
123static inline int gpio_valid(int gpio)
124{
125 if (gpio < 0)
126 return -1;
127 if (cpu_class_is_omap1() && OMAP_GPIO_IS_MPUIO(gpio)) {
128 if (gpio >= OMAP_MAX_GPIO_LINES + 16)
129 return -1;
130 return 0;
131 }
132 if (cpu_is_omap15xx() && gpio < 16)
133 return 0;
134 if ((cpu_is_omap16xx()) && gpio < 64)
135 return 0;
136 if (cpu_is_omap7xx() && gpio < 192)
137 return 0;
138 if (cpu_is_omap2420() && gpio < 128)
139 return 0;
140 if (cpu_is_omap2430() && gpio < 160)
141 return 0;
142 if ((cpu_is_omap34xx() || cpu_is_omap44xx()) && gpio < 192)
143 return 0;
144 return -1;
145}
146
147static int check_gpio(int gpio)
148{
149 if (unlikely(gpio_valid(gpio) < 0)) {
150 printk(KERN_ERR "omap-gpio: invalid GPIO %d\n", gpio);
151 dump_stack();
152 return -1;
153 }
154 return 0;
155}
156 92
157static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input) 93static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input)
158{ 94{
159 void __iomem *reg = bank->base; 95 void __iomem *reg = bank->base;
160 u32 l; 96 u32 l;
161 97
162 switch (bank->method) { 98 reg += bank->regs->direction;
163#ifdef CONFIG_ARCH_OMAP1
164 case METHOD_MPUIO:
165 reg += OMAP_MPUIO_IO_CNTL / bank->stride;
166 break;
167#endif
168#ifdef CONFIG_ARCH_OMAP15XX
169 case METHOD_GPIO_1510:
170 reg += OMAP1510_GPIO_DIR_CONTROL;
171 break;
172#endif
173#ifdef CONFIG_ARCH_OMAP16XX
174 case METHOD_GPIO_1610:
175 reg += OMAP1610_GPIO_DIRECTION;
176 break;
177#endif
178#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
179 case METHOD_GPIO_7XX:
180 reg += OMAP7XX_GPIO_DIR_CONTROL;
181 break;
182#endif
183#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
184 case METHOD_GPIO_24XX:
185 reg += OMAP24XX_GPIO_OE;
186 break;
187#endif
188#if defined(CONFIG_ARCH_OMAP4)
189 case METHOD_GPIO_44XX:
190 reg += OMAP4_GPIO_OE;
191 break;
192#endif
193 default:
194 WARN_ON(1);
195 return;
196 }
197 l = __raw_readl(reg); 99 l = __raw_readl(reg);
198 if (is_input) 100 if (is_input)
199 l |= 1 << gpio; 101 l |= 1 << gpio;
@@ -202,165 +104,48 @@ static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input)
202 __raw_writel(l, reg); 104 __raw_writel(l, reg);
203} 105}
204 106
205static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable) 107
108/* set data out value using dedicate set/clear register */
109static void _set_gpio_dataout_reg(struct gpio_bank *bank, int gpio, int enable)
206{ 110{
207 void __iomem *reg = bank->base; 111 void __iomem *reg = bank->base;
208 u32 l = 0; 112 u32 l = GPIO_BIT(bank, gpio);
113
114 if (enable)
115 reg += bank->regs->set_dataout;
116 else
117 reg += bank->regs->clr_dataout;
209 118
210 switch (bank->method) {
211#ifdef CONFIG_ARCH_OMAP1
212 case METHOD_MPUIO:
213 reg += OMAP_MPUIO_OUTPUT / bank->stride;
214 l = __raw_readl(reg);
215 if (enable)
216 l |= 1 << gpio;
217 else
218 l &= ~(1 << gpio);
219 break;
220#endif
221#ifdef CONFIG_ARCH_OMAP15XX
222 case METHOD_GPIO_1510:
223 reg += OMAP1510_GPIO_DATA_OUTPUT;
224 l = __raw_readl(reg);
225 if (enable)
226 l |= 1 << gpio;
227 else
228 l &= ~(1 << gpio);
229 break;
230#endif
231#ifdef CONFIG_ARCH_OMAP16XX
232 case METHOD_GPIO_1610:
233 if (enable)
234 reg += OMAP1610_GPIO_SET_DATAOUT;
235 else
236 reg += OMAP1610_GPIO_CLEAR_DATAOUT;
237 l = 1 << gpio;
238 break;
239#endif
240#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
241 case METHOD_GPIO_7XX:
242 reg += OMAP7XX_GPIO_DATA_OUTPUT;
243 l = __raw_readl(reg);
244 if (enable)
245 l |= 1 << gpio;
246 else
247 l &= ~(1 << gpio);
248 break;
249#endif
250#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
251 case METHOD_GPIO_24XX:
252 if (enable)
253 reg += OMAP24XX_GPIO_SETDATAOUT;
254 else
255 reg += OMAP24XX_GPIO_CLEARDATAOUT;
256 l = 1 << gpio;
257 break;
258#endif
259#ifdef CONFIG_ARCH_OMAP4
260 case METHOD_GPIO_44XX:
261 if (enable)
262 reg += OMAP4_GPIO_SETDATAOUT;
263 else
264 reg += OMAP4_GPIO_CLEARDATAOUT;
265 l = 1 << gpio;
266 break;
267#endif
268 default:
269 WARN_ON(1);
270 return;
271 }
272 __raw_writel(l, reg); 119 __raw_writel(l, reg);
273} 120}
274 121
275static int _get_gpio_datain(struct gpio_bank *bank, int gpio) 122/* set data out value using mask register */
123static void _set_gpio_dataout_mask(struct gpio_bank *bank, int gpio, int enable)
276{ 124{
277 void __iomem *reg; 125 void __iomem *reg = bank->base + bank->regs->dataout;
126 u32 gpio_bit = GPIO_BIT(bank, gpio);
127 u32 l;
278 128
279 if (check_gpio(gpio) < 0) 129 l = __raw_readl(reg);
280 return -EINVAL; 130 if (enable)
281 reg = bank->base; 131 l |= gpio_bit;
282 switch (bank->method) { 132 else
283#ifdef CONFIG_ARCH_OMAP1 133 l &= ~gpio_bit;
284 case METHOD_MPUIO: 134 __raw_writel(l, reg);
285 reg += OMAP_MPUIO_INPUT_LATCH / bank->stride;
286 break;
287#endif
288#ifdef CONFIG_ARCH_OMAP15XX
289 case METHOD_GPIO_1510:
290 reg += OMAP1510_GPIO_DATA_INPUT;
291 break;
292#endif
293#ifdef CONFIG_ARCH_OMAP16XX
294 case METHOD_GPIO_1610:
295 reg += OMAP1610_GPIO_DATAIN;
296 break;
297#endif
298#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
299 case METHOD_GPIO_7XX:
300 reg += OMAP7XX_GPIO_DATA_INPUT;
301 break;
302#endif
303#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
304 case METHOD_GPIO_24XX:
305 reg += OMAP24XX_GPIO_DATAIN;
306 break;
307#endif
308#ifdef CONFIG_ARCH_OMAP4
309 case METHOD_GPIO_44XX:
310 reg += OMAP4_GPIO_DATAIN;
311 break;
312#endif
313 default:
314 return -EINVAL;
315 }
316 return (__raw_readl(reg)
317 & (1 << get_gpio_index(gpio))) != 0;
318} 135}
319 136
320static int _get_gpio_dataout(struct gpio_bank *bank, int gpio) 137static int _get_gpio_datain(struct gpio_bank *bank, int gpio)
321{ 138{
322 void __iomem *reg; 139 void __iomem *reg = bank->base + bank->regs->datain;
323 140
324 if (check_gpio(gpio) < 0) 141 return (__raw_readl(reg) & GPIO_BIT(bank, gpio)) != 0;
325 return -EINVAL; 142}
326 reg = bank->base;
327 143
328 switch (bank->method) { 144static int _get_gpio_dataout(struct gpio_bank *bank, int gpio)
329#ifdef CONFIG_ARCH_OMAP1 145{
330 case METHOD_MPUIO: 146 void __iomem *reg = bank->base + bank->regs->dataout;
331 reg += OMAP_MPUIO_OUTPUT / bank->stride;
332 break;
333#endif
334#ifdef CONFIG_ARCH_OMAP15XX
335 case METHOD_GPIO_1510:
336 reg += OMAP1510_GPIO_DATA_OUTPUT;
337 break;
338#endif
339#ifdef CONFIG_ARCH_OMAP16XX
340 case METHOD_GPIO_1610:
341 reg += OMAP1610_GPIO_DATAOUT;
342 break;
343#endif
344#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
345 case METHOD_GPIO_7XX:
346 reg += OMAP7XX_GPIO_DATA_OUTPUT;
347 break;
348#endif
349#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
350 case METHOD_GPIO_24XX:
351 reg += OMAP24XX_GPIO_DATAOUT;
352 break;
353#endif
354#ifdef CONFIG_ARCH_OMAP4
355 case METHOD_GPIO_44XX:
356 reg += OMAP4_GPIO_DATAOUT;
357 break;
358#endif
359 default:
360 return -EINVAL;
361 }
362 147
363 return (__raw_readl(reg) & (1 << get_gpio_index(gpio))) != 0; 148 return (__raw_readl(reg) & GPIO_BIT(bank, gpio)) != 0;
364} 149}
365 150
366#define MOD_REG_BIT(reg, bit_mask, set) \ 151#define MOD_REG_BIT(reg, bit_mask, set) \
@@ -383,7 +168,7 @@ do { \
383static void _set_gpio_debounce(struct gpio_bank *bank, unsigned gpio, 168static void _set_gpio_debounce(struct gpio_bank *bank, unsigned gpio,
384 unsigned debounce) 169 unsigned debounce)
385{ 170{
386 void __iomem *reg = bank->base; 171 void __iomem *reg;
387 u32 val; 172 u32 val;
388 u32 l; 173 u32 l;
389 174
@@ -397,21 +182,12 @@ static void _set_gpio_debounce(struct gpio_bank *bank, unsigned gpio,
397 else 182 else
398 debounce = (debounce / 0x1f) - 1; 183 debounce = (debounce / 0x1f) - 1;
399 184
400 l = 1 << get_gpio_index(gpio); 185 l = GPIO_BIT(bank, gpio);
401
402 if (bank->method == METHOD_GPIO_44XX)
403 reg += OMAP4_GPIO_DEBOUNCINGTIME;
404 else
405 reg += OMAP24XX_GPIO_DEBOUNCE_VAL;
406 186
187 reg = bank->base + bank->regs->debounce;
407 __raw_writel(debounce, reg); 188 __raw_writel(debounce, reg);
408 189
409 reg = bank->base; 190 reg = bank->base + bank->regs->debounce_en;
410 if (bank->method == METHOD_GPIO_44XX)
411 reg += OMAP4_GPIO_DEBOUNCENABLE;
412 else
413 reg += OMAP24XX_GPIO_DEBOUNCE_EN;
414
415 val = __raw_readl(reg); 191 val = __raw_readl(reg);
416 192
417 if (debounce) { 193 if (debounce) {
@@ -629,9 +405,6 @@ static int gpio_irq_type(struct irq_data *d, unsigned type)
629 else 405 else
630 gpio = d->irq - IH_GPIO_BASE; 406 gpio = d->irq - IH_GPIO_BASE;
631 407
632 if (check_gpio(gpio) < 0)
633 return -EINVAL;
634
635 if (type & ~IRQ_TYPE_SENSE_MASK) 408 if (type & ~IRQ_TYPE_SENSE_MASK)
636 return -EINVAL; 409 return -EINVAL;
637 410
@@ -642,7 +415,7 @@ static int gpio_irq_type(struct irq_data *d, unsigned type)
642 415
643 bank = irq_data_get_irq_chip_data(d); 416 bank = irq_data_get_irq_chip_data(d);
644 spin_lock_irqsave(&bank->lock, flags); 417 spin_lock_irqsave(&bank->lock, flags);
645 retval = _set_gpio_triggering(bank, get_gpio_index(gpio), type); 418 retval = _set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), type);
646 spin_unlock_irqrestore(&bank->lock, flags); 419 spin_unlock_irqrestore(&bank->lock, flags);
647 420
648 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) 421 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
@@ -657,195 +430,81 @@ static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
657{ 430{
658 void __iomem *reg = bank->base; 431 void __iomem *reg = bank->base;
659 432
660 switch (bank->method) { 433 reg += bank->regs->irqstatus;
661#ifdef CONFIG_ARCH_OMAP1
662 case METHOD_MPUIO:
663 /* MPUIO irqstatus is reset by reading the status register,
664 * so do nothing here */
665 return;
666#endif
667#ifdef CONFIG_ARCH_OMAP15XX
668 case METHOD_GPIO_1510:
669 reg += OMAP1510_GPIO_INT_STATUS;
670 break;
671#endif
672#ifdef CONFIG_ARCH_OMAP16XX
673 case METHOD_GPIO_1610:
674 reg += OMAP1610_GPIO_IRQSTATUS1;
675 break;
676#endif
677#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
678 case METHOD_GPIO_7XX:
679 reg += OMAP7XX_GPIO_INT_STATUS;
680 break;
681#endif
682#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
683 case METHOD_GPIO_24XX:
684 reg += OMAP24XX_GPIO_IRQSTATUS1;
685 break;
686#endif
687#if defined(CONFIG_ARCH_OMAP4)
688 case METHOD_GPIO_44XX:
689 reg += OMAP4_GPIO_IRQSTATUS0;
690 break;
691#endif
692 default:
693 WARN_ON(1);
694 return;
695 }
696 __raw_writel(gpio_mask, reg); 434 __raw_writel(gpio_mask, reg);
697 435
698 /* Workaround for clearing DSP GPIO interrupts to allow retention */ 436 /* Workaround for clearing DSP GPIO interrupts to allow retention */
699 if (cpu_is_omap24xx() || cpu_is_omap34xx()) 437 if (bank->regs->irqstatus2) {
700 reg = bank->base + OMAP24XX_GPIO_IRQSTATUS2; 438 reg = bank->base + bank->regs->irqstatus2;
701 else if (cpu_is_omap44xx())
702 reg = bank->base + OMAP4_GPIO_IRQSTATUS1;
703
704 if (cpu_is_omap24xx() || cpu_is_omap34xx() || cpu_is_omap44xx()) {
705 __raw_writel(gpio_mask, reg); 439 __raw_writel(gpio_mask, reg);
440 }
706 441
707 /* Flush posted write for the irq status to avoid spurious interrupts */ 442 /* Flush posted write for the irq status to avoid spurious interrupts */
708 __raw_readl(reg); 443 __raw_readl(reg);
709 }
710} 444}
711 445
712static inline void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio) 446static inline void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio)
713{ 447{
714 _clear_gpio_irqbank(bank, 1 << get_gpio_index(gpio)); 448 _clear_gpio_irqbank(bank, GPIO_BIT(bank, gpio));
715} 449}
716 450
717static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank) 451static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank)
718{ 452{
719 void __iomem *reg = bank->base; 453 void __iomem *reg = bank->base;
720 int inv = 0;
721 u32 l; 454 u32 l;
722 u32 mask; 455 u32 mask = (1 << bank->width) - 1;
723
724 switch (bank->method) {
725#ifdef CONFIG_ARCH_OMAP1
726 case METHOD_MPUIO:
727 reg += OMAP_MPUIO_GPIO_MASKIT / bank->stride;
728 mask = 0xffff;
729 inv = 1;
730 break;
731#endif
732#ifdef CONFIG_ARCH_OMAP15XX
733 case METHOD_GPIO_1510:
734 reg += OMAP1510_GPIO_INT_MASK;
735 mask = 0xffff;
736 inv = 1;
737 break;
738#endif
739#ifdef CONFIG_ARCH_OMAP16XX
740 case METHOD_GPIO_1610:
741 reg += OMAP1610_GPIO_IRQENABLE1;
742 mask = 0xffff;
743 break;
744#endif
745#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
746 case METHOD_GPIO_7XX:
747 reg += OMAP7XX_GPIO_INT_MASK;
748 mask = 0xffffffff;
749 inv = 1;
750 break;
751#endif
752#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
753 case METHOD_GPIO_24XX:
754 reg += OMAP24XX_GPIO_IRQENABLE1;
755 mask = 0xffffffff;
756 break;
757#endif
758#if defined(CONFIG_ARCH_OMAP4)
759 case METHOD_GPIO_44XX:
760 reg += OMAP4_GPIO_IRQSTATUSSET0;
761 mask = 0xffffffff;
762 break;
763#endif
764 default:
765 WARN_ON(1);
766 return 0;
767 }
768 456
457 reg += bank->regs->irqenable;
769 l = __raw_readl(reg); 458 l = __raw_readl(reg);
770 if (inv) 459 if (bank->regs->irqenable_inv)
771 l = ~l; 460 l = ~l;
772 l &= mask; 461 l &= mask;
773 return l; 462 return l;
774} 463}
775 464
776static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask, int enable) 465static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
777{ 466{
778 void __iomem *reg = bank->base; 467 void __iomem *reg = bank->base;
779 u32 l; 468 u32 l;
780 469
781 switch (bank->method) { 470 if (bank->regs->set_irqenable) {
782#ifdef CONFIG_ARCH_OMAP1 471 reg += bank->regs->set_irqenable;
783 case METHOD_MPUIO: 472 l = gpio_mask;
784 reg += OMAP_MPUIO_GPIO_MASKIT / bank->stride; 473 } else {
785 l = __raw_readl(reg); 474 reg += bank->regs->irqenable;
786 if (enable)
787 l &= ~(gpio_mask);
788 else
789 l |= gpio_mask;
790 break;
791#endif
792#ifdef CONFIG_ARCH_OMAP15XX
793 case METHOD_GPIO_1510:
794 reg += OMAP1510_GPIO_INT_MASK;
795 l = __raw_readl(reg); 475 l = __raw_readl(reg);
796 if (enable) 476 if (bank->regs->irqenable_inv)
797 l &= ~(gpio_mask); 477 l &= ~gpio_mask;
798 else 478 else
799 l |= gpio_mask; 479 l |= gpio_mask;
800 break; 480 }
801#endif 481
802#ifdef CONFIG_ARCH_OMAP16XX 482 __raw_writel(l, reg);
803 case METHOD_GPIO_1610: 483}
804 if (enable) 484
805 reg += OMAP1610_GPIO_SET_IRQENABLE1; 485static void _disable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
806 else 486{
807 reg += OMAP1610_GPIO_CLEAR_IRQENABLE1; 487 void __iomem *reg = bank->base;
488 u32 l;
489
490 if (bank->regs->clr_irqenable) {
491 reg += bank->regs->clr_irqenable;
808 l = gpio_mask; 492 l = gpio_mask;
809 break; 493 } else {
810#endif 494 reg += bank->regs->irqenable;
811#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
812 case METHOD_GPIO_7XX:
813 reg += OMAP7XX_GPIO_INT_MASK;
814 l = __raw_readl(reg); 495 l = __raw_readl(reg);
815 if (enable) 496 if (bank->regs->irqenable_inv)
816 l &= ~(gpio_mask);
817 else
818 l |= gpio_mask; 497 l |= gpio_mask;
819 break;
820#endif
821#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
822 case METHOD_GPIO_24XX:
823 if (enable)
824 reg += OMAP24XX_GPIO_SETIRQENABLE1;
825 else
826 reg += OMAP24XX_GPIO_CLEARIRQENABLE1;
827 l = gpio_mask;
828 break;
829#endif
830#ifdef CONFIG_ARCH_OMAP4
831 case METHOD_GPIO_44XX:
832 if (enable)
833 reg += OMAP4_GPIO_IRQSTATUSSET0;
834 else 498 else
835 reg += OMAP4_GPIO_IRQSTATUSCLR0; 499 l &= ~gpio_mask;
836 l = gpio_mask;
837 break;
838#endif
839 default:
840 WARN_ON(1);
841 return;
842 } 500 }
501
843 __raw_writel(l, reg); 502 __raw_writel(l, reg);
844} 503}
845 504
846static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable) 505static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable)
847{ 506{
848 _enable_gpio_irqbank(bank, 1 << get_gpio_index(gpio), enable); 507 _enable_gpio_irqbank(bank, GPIO_BIT(bank, gpio));
849} 508}
850 509
851/* 510/*
@@ -858,50 +517,32 @@ static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int ena
858 */ 517 */
859static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable) 518static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable)
860{ 519{
861 unsigned long uninitialized_var(flags); 520 u32 gpio_bit = GPIO_BIT(bank, gpio);
521 unsigned long flags;
862 522
863 switch (bank->method) { 523 if (bank->non_wakeup_gpios & gpio_bit) {
864#ifdef CONFIG_ARCH_OMAP16XX 524 dev_err(bank->dev,
865 case METHOD_MPUIO: 525 "Unable to modify wakeup on non-wakeup GPIO%d\n", gpio);
866 case METHOD_GPIO_1610:
867 spin_lock_irqsave(&bank->lock, flags);
868 if (enable)
869 bank->suspend_wakeup |= (1 << gpio);
870 else
871 bank->suspend_wakeup &= ~(1 << gpio);
872 spin_unlock_irqrestore(&bank->lock, flags);
873 return 0;
874#endif
875#ifdef CONFIG_ARCH_OMAP2PLUS
876 case METHOD_GPIO_24XX:
877 case METHOD_GPIO_44XX:
878 if (bank->non_wakeup_gpios & (1 << gpio)) {
879 printk(KERN_ERR "Unable to modify wakeup on "
880 "non-wakeup GPIO%d\n",
881 (bank - gpio_bank) * 32 + gpio);
882 return -EINVAL;
883 }
884 spin_lock_irqsave(&bank->lock, flags);
885 if (enable)
886 bank->suspend_wakeup |= (1 << gpio);
887 else
888 bank->suspend_wakeup &= ~(1 << gpio);
889 spin_unlock_irqrestore(&bank->lock, flags);
890 return 0;
891#endif
892 default:
893 printk(KERN_ERR "Can't enable GPIO wakeup for method %i\n",
894 bank->method);
895 return -EINVAL; 526 return -EINVAL;
896 } 527 }
528
529 spin_lock_irqsave(&bank->lock, flags);
530 if (enable)
531 bank->suspend_wakeup |= gpio_bit;
532 else
533 bank->suspend_wakeup &= ~gpio_bit;
534
535 spin_unlock_irqrestore(&bank->lock, flags);
536
537 return 0;
897} 538}
898 539
899static void _reset_gpio(struct gpio_bank *bank, int gpio) 540static void _reset_gpio(struct gpio_bank *bank, int gpio)
900{ 541{
901 _set_gpio_direction(bank, get_gpio_index(gpio), 1); 542 _set_gpio_direction(bank, GPIO_INDEX(bank, gpio), 1);
902 _set_gpio_irqenable(bank, gpio, 0); 543 _set_gpio_irqenable(bank, gpio, 0);
903 _clear_gpio_irqstatus(bank, gpio); 544 _clear_gpio_irqstatus(bank, gpio);
904 _set_gpio_triggering(bank, get_gpio_index(gpio), IRQ_TYPE_NONE); 545 _set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), IRQ_TYPE_NONE);
905} 546}
906 547
907/* Use disable_irq_wake() and enable_irq_wake() functions from drivers */ 548/* Use disable_irq_wake() and enable_irq_wake() functions from drivers */
@@ -911,10 +552,8 @@ static int gpio_wake_enable(struct irq_data *d, unsigned int enable)
911 struct gpio_bank *bank; 552 struct gpio_bank *bank;
912 int retval; 553 int retval;
913 554
914 if (check_gpio(gpio) < 0)
915 return -ENODEV;
916 bank = irq_data_get_irq_chip_data(d); 555 bank = irq_data_get_irq_chip_data(d);
917 retval = _set_gpio_wakeup(bank, get_gpio_index(gpio), enable); 556 retval = _set_gpio_wakeup(bank, gpio, enable);
918 557
919 return retval; 558 return retval;
920} 559}
@@ -1030,31 +669,7 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
1030 chained_irq_enter(chip, desc); 669 chained_irq_enter(chip, desc);
1031 670
1032 bank = irq_get_handler_data(irq); 671 bank = irq_get_handler_data(irq);
1033#ifdef CONFIG_ARCH_OMAP1 672 isr_reg = bank->base + bank->regs->irqstatus;
1034 if (bank->method == METHOD_MPUIO)
1035 isr_reg = bank->base +
1036 OMAP_MPUIO_GPIO_INT / bank->stride;
1037#endif
1038#ifdef CONFIG_ARCH_OMAP15XX
1039 if (bank->method == METHOD_GPIO_1510)
1040 isr_reg = bank->base + OMAP1510_GPIO_INT_STATUS;
1041#endif
1042#if defined(CONFIG_ARCH_OMAP16XX)
1043 if (bank->method == METHOD_GPIO_1610)
1044 isr_reg = bank->base + OMAP1610_GPIO_IRQSTATUS1;
1045#endif
1046#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
1047 if (bank->method == METHOD_GPIO_7XX)
1048 isr_reg = bank->base + OMAP7XX_GPIO_INT_STATUS;
1049#endif
1050#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
1051 if (bank->method == METHOD_GPIO_24XX)
1052 isr_reg = bank->base + OMAP24XX_GPIO_IRQSTATUS1;
1053#endif
1054#if defined(CONFIG_ARCH_OMAP4)
1055 if (bank->method == METHOD_GPIO_44XX)
1056 isr_reg = bank->base + OMAP4_GPIO_IRQSTATUS0;
1057#endif
1058 673
1059 if (WARN_ON(!isr_reg)) 674 if (WARN_ON(!isr_reg))
1060 goto exit; 675 goto exit;
@@ -1076,9 +691,9 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
1076 /* clear edge sensitive interrupts before handler(s) are 691 /* clear edge sensitive interrupts before handler(s) are
1077 called so that we don't miss any interrupt occurred while 692 called so that we don't miss any interrupt occurred while
1078 executing them */ 693 executing them */
1079 _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 0); 694 _disable_gpio_irqbank(bank, isr_saved & ~level_mask);
1080 _clear_gpio_irqbank(bank, isr_saved & ~level_mask); 695 _clear_gpio_irqbank(bank, isr_saved & ~level_mask);
1081 _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 1); 696 _enable_gpio_irqbank(bank, isr_saved & ~level_mask);
1082 697
1083 /* if there is only edge sensitive GPIO pin interrupts 698 /* if there is only edge sensitive GPIO pin interrupts
1084 configured, we could unmask GPIO bank interrupt immediately */ 699 configured, we could unmask GPIO bank interrupt immediately */
@@ -1094,7 +709,7 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
1094 709
1095 gpio_irq = bank->virtual_irq_start; 710 gpio_irq = bank->virtual_irq_start;
1096 for (; isr != 0; isr >>= 1, gpio_irq++) { 711 for (; isr != 0; isr >>= 1, gpio_irq++) {
1097 gpio_index = get_gpio_index(irq_to_gpio(gpio_irq)); 712 gpio_index = GPIO_INDEX(bank, irq_to_gpio(gpio_irq));
1098 713
1099 if (!(isr & 1)) 714 if (!(isr & 1))
1100 continue; 715 continue;
@@ -1150,7 +765,7 @@ static void gpio_mask_irq(struct irq_data *d)
1150 765
1151 spin_lock_irqsave(&bank->lock, flags); 766 spin_lock_irqsave(&bank->lock, flags);
1152 _set_gpio_irqenable(bank, gpio, 0); 767 _set_gpio_irqenable(bank, gpio, 0);
1153 _set_gpio_triggering(bank, get_gpio_index(gpio), IRQ_TYPE_NONE); 768 _set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), IRQ_TYPE_NONE);
1154 spin_unlock_irqrestore(&bank->lock, flags); 769 spin_unlock_irqrestore(&bank->lock, flags);
1155} 770}
1156 771
@@ -1158,13 +773,13 @@ static void gpio_unmask_irq(struct irq_data *d)
1158{ 773{
1159 unsigned int gpio = d->irq - IH_GPIO_BASE; 774 unsigned int gpio = d->irq - IH_GPIO_BASE;
1160 struct gpio_bank *bank = irq_data_get_irq_chip_data(d); 775 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
1161 unsigned int irq_mask = 1 << get_gpio_index(gpio); 776 unsigned int irq_mask = GPIO_BIT(bank, gpio);
1162 u32 trigger = irqd_get_trigger_type(d); 777 u32 trigger = irqd_get_trigger_type(d);
1163 unsigned long flags; 778 unsigned long flags;
1164 779
1165 spin_lock_irqsave(&bank->lock, flags); 780 spin_lock_irqsave(&bank->lock, flags);
1166 if (trigger) 781 if (trigger)
1167 _set_gpio_triggering(bank, get_gpio_index(gpio), trigger); 782 _set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), trigger);
1168 783
1169 /* For level-triggered GPIOs, the clearing must be done after 784 /* For level-triggered GPIOs, the clearing must be done after
1170 * the HW source is cleared, thus after the handler has run */ 785 * the HW source is cleared, thus after the handler has run */
@@ -1191,45 +806,8 @@ static struct irq_chip gpio_irq_chip = {
1191 806
1192#ifdef CONFIG_ARCH_OMAP1 807#ifdef CONFIG_ARCH_OMAP1
1193 808
1194/* MPUIO uses the always-on 32k clock */
1195
1196static void mpuio_ack_irq(struct irq_data *d)
1197{
1198 /* The ISR is reset automatically, so do nothing here. */
1199}
1200
1201static void mpuio_mask_irq(struct irq_data *d)
1202{
1203 unsigned int gpio = OMAP_MPUIO(d->irq - IH_MPUIO_BASE);
1204 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
1205
1206 _set_gpio_irqenable(bank, gpio, 0);
1207}
1208
1209static void mpuio_unmask_irq(struct irq_data *d)
1210{
1211 unsigned int gpio = OMAP_MPUIO(d->irq - IH_MPUIO_BASE);
1212 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
1213
1214 _set_gpio_irqenable(bank, gpio, 1);
1215}
1216
1217static struct irq_chip mpuio_irq_chip = {
1218 .name = "MPUIO",
1219 .irq_ack = mpuio_ack_irq,
1220 .irq_mask = mpuio_mask_irq,
1221 .irq_unmask = mpuio_unmask_irq,
1222 .irq_set_type = gpio_irq_type,
1223#ifdef CONFIG_ARCH_OMAP16XX
1224 /* REVISIT: assuming only 16xx supports MPUIO wake events */
1225 .irq_set_wake = gpio_wake_enable,
1226#endif
1227};
1228
1229
1230#define bank_is_mpuio(bank) ((bank)->method == METHOD_MPUIO) 809#define bank_is_mpuio(bank) ((bank)->method == METHOD_MPUIO)
1231 810
1232
1233#ifdef CONFIG_ARCH_OMAP16XX 811#ifdef CONFIG_ARCH_OMAP16XX
1234 812
1235#include <linux/platform_device.h> 813#include <linux/platform_device.h>
@@ -1289,7 +867,7 @@ static struct platform_device omap_mpuio_device = {
1289 867
1290static inline void mpuio_init(void) 868static inline void mpuio_init(void)
1291{ 869{
1292 struct gpio_bank *bank = get_gpio_bank(OMAP_MPUIO(0)); 870 struct gpio_bank *bank = &gpio_bank[0];
1293 platform_set_drvdata(&omap_mpuio_device, bank); 871 platform_set_drvdata(&omap_mpuio_device, bank);
1294 872
1295 if (platform_driver_register(&omap_mpuio_driver) == 0) 873 if (platform_driver_register(&omap_mpuio_driver) == 0)
@@ -1302,8 +880,6 @@ static inline void mpuio_init(void) {}
1302 880
1303#else 881#else
1304 882
1305extern struct irq_chip mpuio_irq_chip;
1306
1307#define bank_is_mpuio(bank) 0 883#define bank_is_mpuio(bank) 0
1308static inline void mpuio_init(void) {} 884static inline void mpuio_init(void) {}
1309 885
@@ -1329,31 +905,8 @@ static int gpio_input(struct gpio_chip *chip, unsigned offset)
1329 905
1330static int gpio_is_input(struct gpio_bank *bank, int mask) 906static int gpio_is_input(struct gpio_bank *bank, int mask)
1331{ 907{
1332 void __iomem *reg = bank->base; 908 void __iomem *reg = bank->base + bank->regs->direction;
1333 909
1334 switch (bank->method) {
1335 case METHOD_MPUIO:
1336 reg += OMAP_MPUIO_IO_CNTL / bank->stride;
1337 break;
1338 case METHOD_GPIO_1510:
1339 reg += OMAP1510_GPIO_DIR_CONTROL;
1340 break;
1341 case METHOD_GPIO_1610:
1342 reg += OMAP1610_GPIO_DIRECTION;
1343 break;
1344 case METHOD_GPIO_7XX:
1345 reg += OMAP7XX_GPIO_DIR_CONTROL;
1346 break;
1347 case METHOD_GPIO_24XX:
1348 reg += OMAP24XX_GPIO_OE;
1349 break;
1350 case METHOD_GPIO_44XX:
1351 reg += OMAP4_GPIO_OE;
1352 break;
1353 default:
1354 WARN_ONCE(1, "gpio_is_input: incorrect OMAP GPIO method");
1355 return -EINVAL;
1356 }
1357 return __raw_readl(reg) & mask; 910 return __raw_readl(reg) & mask;
1358} 911}
1359 912
@@ -1365,9 +918,9 @@ static int gpio_get(struct gpio_chip *chip, unsigned offset)
1365 u32 mask; 918 u32 mask;
1366 919
1367 gpio = chip->base + offset; 920 gpio = chip->base + offset;
1368 bank = get_gpio_bank(gpio); 921 bank = container_of(chip, struct gpio_bank, chip);
1369 reg = bank->base; 922 reg = bank->base;
1370 mask = 1 << get_gpio_index(gpio); 923 mask = GPIO_BIT(bank, gpio);
1371 924
1372 if (gpio_is_input(bank, mask)) 925 if (gpio_is_input(bank, mask))
1373 return _get_gpio_datain(bank, gpio); 926 return _get_gpio_datain(bank, gpio);
@@ -1382,7 +935,7 @@ static int gpio_output(struct gpio_chip *chip, unsigned offset, int value)
1382 935
1383 bank = container_of(chip, struct gpio_bank, chip); 936 bank = container_of(chip, struct gpio_bank, chip);
1384 spin_lock_irqsave(&bank->lock, flags); 937 spin_lock_irqsave(&bank->lock, flags);
1385 _set_gpio_dataout(bank, offset, value); 938 bank->set_dataout(bank, offset, value);
1386 _set_gpio_direction(bank, offset, 0); 939 _set_gpio_direction(bank, offset, 0);
1387 spin_unlock_irqrestore(&bank->lock, flags); 940 spin_unlock_irqrestore(&bank->lock, flags);
1388 return 0; 941 return 0;
@@ -1416,7 +969,7 @@ static void gpio_set(struct gpio_chip *chip, unsigned offset, int value)
1416 969
1417 bank = container_of(chip, struct gpio_bank, chip); 970 bank = container_of(chip, struct gpio_bank, chip);
1418 spin_lock_irqsave(&bank->lock, flags); 971 spin_lock_irqsave(&bank->lock, flags);
1419 _set_gpio_dataout(bank, offset, value); 972 bank->set_dataout(bank, offset, value);
1420 spin_unlock_irqrestore(&bank->lock, flags); 973 spin_unlock_irqrestore(&bank->lock, flags);
1421} 974}
1422 975
@@ -1432,19 +985,17 @@ static int gpio_2irq(struct gpio_chip *chip, unsigned offset)
1432 985
1433static void __init omap_gpio_show_rev(struct gpio_bank *bank) 986static void __init omap_gpio_show_rev(struct gpio_bank *bank)
1434{ 987{
988 static bool called;
1435 u32 rev; 989 u32 rev;
1436 990
1437 if (cpu_is_omap16xx() && !(bank->method != METHOD_MPUIO)) 991 if (called || bank->regs->revision == USHRT_MAX)
1438 rev = __raw_readw(bank->base + OMAP1610_GPIO_REVISION);
1439 else if (cpu_is_omap24xx() || cpu_is_omap34xx())
1440 rev = __raw_readl(bank->base + OMAP24XX_GPIO_REVISION);
1441 else if (cpu_is_omap44xx())
1442 rev = __raw_readl(bank->base + OMAP4_GPIO_REVISION);
1443 else
1444 return; 992 return;
1445 993
1446 printk(KERN_INFO "OMAP GPIO hardware version %d.%d\n", 994 rev = __raw_readw(bank->base + bank->regs->revision);
995 pr_info("OMAP GPIO hardware version %d.%d\n",
1447 (rev >> 4) & 0x0f, rev & 0x0f); 996 (rev >> 4) & 0x0f, rev & 0x0f);
997
998 called = true;
1448} 999}
1449 1000
1450/* This lock class tells lockdep that GPIO irqs are in a different 1001/* This lock class tells lockdep that GPIO irqs are in a different
@@ -1526,6 +1077,30 @@ static void omap_gpio_mod_init(struct gpio_bank *bank, int id)
1526 } 1077 }
1527} 1078}
1528 1079
1080static __init void
1081omap_mpuio_alloc_gc(struct gpio_bank *bank, unsigned int irq_start,
1082 unsigned int num)
1083{
1084 struct irq_chip_generic *gc;
1085 struct irq_chip_type *ct;
1086
1087 gc = irq_alloc_generic_chip("MPUIO", 1, irq_start, bank->base,
1088 handle_simple_irq);
1089 ct = gc->chip_types;
1090
1091 /* NOTE: No ack required, reading IRQ status clears it. */
1092 ct->chip.irq_mask = irq_gc_mask_set_bit;
1093 ct->chip.irq_unmask = irq_gc_mask_clr_bit;
1094 ct->chip.irq_set_type = gpio_irq_type;
1095 /* REVISIT: assuming only 16xx supports MPUIO wake events */
1096 if (cpu_is_omap16xx())
1097 ct->chip.irq_set_wake = gpio_wake_enable,
1098
1099 ct->regs.mask = OMAP_MPUIO_GPIO_INT / bank->stride;
1100 irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE,
1101 IRQ_NOREQUEST | IRQ_NOPROBE, 0);
1102}
1103
1529static void __devinit omap_gpio_chip_init(struct gpio_bank *bank) 1104static void __devinit omap_gpio_chip_init(struct gpio_bank *bank)
1530{ 1105{
1531 int j; 1106 int j;
@@ -1553,22 +1128,23 @@ static void __devinit omap_gpio_chip_init(struct gpio_bank *bank)
1553 } else { 1128 } else {
1554 bank->chip.label = "gpio"; 1129 bank->chip.label = "gpio";
1555 bank->chip.base = gpio; 1130 bank->chip.base = gpio;
1556 gpio += bank_width; 1131 gpio += bank->width;
1557 } 1132 }
1558 bank->chip.ngpio = bank_width; 1133 bank->chip.ngpio = bank->width;
1559 1134
1560 gpiochip_add(&bank->chip); 1135 gpiochip_add(&bank->chip);
1561 1136
1562 for (j = bank->virtual_irq_start; 1137 for (j = bank->virtual_irq_start;
1563 j < bank->virtual_irq_start + bank_width; j++) { 1138 j < bank->virtual_irq_start + bank->width; j++) {
1564 irq_set_lockdep_class(j, &gpio_lock_class); 1139 irq_set_lockdep_class(j, &gpio_lock_class);
1565 irq_set_chip_data(j, bank); 1140 irq_set_chip_data(j, bank);
1566 if (bank_is_mpuio(bank)) 1141 if (bank_is_mpuio(bank)) {
1567 irq_set_chip(j, &mpuio_irq_chip); 1142 omap_mpuio_alloc_gc(bank, j, bank->width);
1568 else 1143 } else {
1569 irq_set_chip(j, &gpio_irq_chip); 1144 irq_set_chip(j, &gpio_irq_chip);
1570 irq_set_handler(j, handle_simple_irq); 1145 irq_set_handler(j, handle_simple_irq);
1571 set_irq_flags(j, IRQF_VALID); 1146 set_irq_flags(j, IRQF_VALID);
1147 }
1572 } 1148 }
1573 irq_set_chained_handler(bank->irq, gpio_irq_handler); 1149 irq_set_chained_handler(bank->irq, gpio_irq_handler);
1574 irq_set_handler_data(bank->irq, bank); 1150 irq_set_handler_data(bank->irq, bank);
@@ -1610,7 +1186,14 @@ static int __devinit omap_gpio_probe(struct platform_device *pdev)
1610 bank->dev = &pdev->dev; 1186 bank->dev = &pdev->dev;
1611 bank->dbck_flag = pdata->dbck_flag; 1187 bank->dbck_flag = pdata->dbck_flag;
1612 bank->stride = pdata->bank_stride; 1188 bank->stride = pdata->bank_stride;
1613 bank_width = pdata->bank_width; 1189 bank->width = pdata->bank_width;
1190
1191 bank->regs = pdata->regs;
1192
1193 if (bank->regs->set_dataout && bank->regs->clr_dataout)
1194 bank->set_dataout = _set_gpio_dataout_reg;
1195 else
1196 bank->set_dataout = _set_gpio_dataout_mask;
1614 1197
1615 spin_lock_init(&bank->lock); 1198 spin_lock_init(&bank->lock);
1616 1199
diff --git a/drivers/gpio/pca953x.c b/drivers/gpio/gpio-pca953x.c
index 0451d7ac94a..0550dcb8581 100644
--- a/drivers/gpio/pca953x.c
+++ b/drivers/gpio/gpio-pca953x.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * pca953x.c - 4/8/16 bit I/O ports 2 * PCA953x 4/8/16 bit I/O ports
3 * 3 *
4 * Copyright (C) 2005 Ben Gardner <bgardner@wabtec.com> 4 * Copyright (C) 2005 Ben Gardner <bgardner@wabtec.com>
5 * Copyright (C) 2007 Marvell International Ltd. 5 * Copyright (C) 2007 Marvell International Ltd.
@@ -21,7 +21,6 @@
21#include <linux/slab.h> 21#include <linux/slab.h>
22#ifdef CONFIG_OF_GPIO 22#ifdef CONFIG_OF_GPIO
23#include <linux/of_platform.h> 23#include <linux/of_platform.h>
24#include <linux/of_gpio.h>
25#endif 24#endif
26 25
27#define PCA953X_INPUT 0 26#define PCA953X_INPUT 0
@@ -85,7 +84,6 @@ struct pca953x_chip {
85#endif 84#endif
86 85
87 struct i2c_client *client; 86 struct i2c_client *client;
88 struct pca953x_platform_data *dyn_pdata;
89 struct gpio_chip gpio_chip; 87 struct gpio_chip gpio_chip;
90 const char *const *names; 88 const char *const *names;
91 int chip_type; 89 int chip_type;
@@ -437,7 +435,7 @@ static irqreturn_t pca953x_irq_handler(int irq, void *devid)
437 435
438 do { 436 do {
439 level = __ffs(pending); 437 level = __ffs(pending);
440 generic_handle_irq(level + chip->irq_base); 438 handle_nested_irq(level + chip->irq_base);
441 439
442 pending &= ~(1 << level); 440 pending &= ~(1 << level);
443 } while (pending); 441 } while (pending);
@@ -446,13 +444,13 @@ static irqreturn_t pca953x_irq_handler(int irq, void *devid)
446} 444}
447 445
448static int pca953x_irq_setup(struct pca953x_chip *chip, 446static int pca953x_irq_setup(struct pca953x_chip *chip,
449 const struct i2c_device_id *id) 447 const struct i2c_device_id *id,
448 int irq_base)
450{ 449{
451 struct i2c_client *client = chip->client; 450 struct i2c_client *client = chip->client;
452 struct pca953x_platform_data *pdata = client->dev.platform_data;
453 int ret, offset = 0; 451 int ret, offset = 0;
454 452
455 if (pdata->irq_base != -1 453 if (irq_base != -1
456 && (id->driver_data & PCA_INT)) { 454 && (id->driver_data & PCA_INT)) {
457 int lvl; 455 int lvl;
458 456
@@ -474,15 +472,19 @@ static int pca953x_irq_setup(struct pca953x_chip *chip,
474 * this purpose. 472 * this purpose.
475 */ 473 */
476 chip->irq_stat &= chip->reg_direction; 474 chip->irq_stat &= chip->reg_direction;
477 chip->irq_base = pdata->irq_base;
478 mutex_init(&chip->irq_lock); 475 mutex_init(&chip->irq_lock);
479 476
477 chip->irq_base = irq_alloc_descs(-1, irq_base, chip->gpio_chip.ngpio, -1);
478 if (chip->irq_base < 0)
479 goto out_failed;
480
480 for (lvl = 0; lvl < chip->gpio_chip.ngpio; lvl++) { 481 for (lvl = 0; lvl < chip->gpio_chip.ngpio; lvl++) {
481 int irq = lvl + chip->irq_base; 482 int irq = lvl + chip->irq_base;
482 483
484 irq_clear_status_flags(irq, IRQ_NOREQUEST);
483 irq_set_chip_data(irq, chip); 485 irq_set_chip_data(irq, chip);
484 irq_set_chip_and_handler(irq, &pca953x_irq_chip, 486 irq_set_chip(irq, &pca953x_irq_chip);
485 handle_simple_irq); 487 irq_set_nested_thread(irq, true);
486#ifdef CONFIG_ARM 488#ifdef CONFIG_ARM
487 set_irq_flags(irq, IRQF_VALID); 489 set_irq_flags(irq, IRQF_VALID);
488#else 490#else
@@ -493,8 +495,7 @@ static int pca953x_irq_setup(struct pca953x_chip *chip,
493 ret = request_threaded_irq(client->irq, 495 ret = request_threaded_irq(client->irq,
494 NULL, 496 NULL,
495 pca953x_irq_handler, 497 pca953x_irq_handler,
496 IRQF_TRIGGER_RISING | 498 IRQF_TRIGGER_LOW | IRQF_ONESHOT,
497 IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
498 dev_name(&client->dev), chip); 499 dev_name(&client->dev), chip);
499 if (ret) { 500 if (ret) {
500 dev_err(&client->dev, "failed to request irq %d\n", 501 dev_err(&client->dev, "failed to request irq %d\n",
@@ -514,17 +515,19 @@ out_failed:
514 515
515static void pca953x_irq_teardown(struct pca953x_chip *chip) 516static void pca953x_irq_teardown(struct pca953x_chip *chip)
516{ 517{
517 if (chip->irq_base != -1) 518 if (chip->irq_base != -1) {
519 irq_free_descs(chip->irq_base, chip->gpio_chip.ngpio);
518 free_irq(chip->client->irq, chip); 520 free_irq(chip->client->irq, chip);
521 }
519} 522}
520#else /* CONFIG_GPIO_PCA953X_IRQ */ 523#else /* CONFIG_GPIO_PCA953X_IRQ */
521static int pca953x_irq_setup(struct pca953x_chip *chip, 524static int pca953x_irq_setup(struct pca953x_chip *chip,
522 const struct i2c_device_id *id) 525 const struct i2c_device_id *id,
526 int irq_base)
523{ 527{
524 struct i2c_client *client = chip->client; 528 struct i2c_client *client = chip->client;
525 struct pca953x_platform_data *pdata = client->dev.platform_data;
526 529
527 if (pdata->irq_base != -1 && (id->driver_data & PCA_INT)) 530 if (irq_base != -1 && (id->driver_data & PCA_INT))
528 dev_warn(&client->dev, "interrupt support not compiled in\n"); 531 dev_warn(&client->dev, "interrupt support not compiled in\n");
529 532
530 return 0; 533 return 0;
@@ -541,46 +544,40 @@ static void pca953x_irq_teardown(struct pca953x_chip *chip)
541#ifdef CONFIG_OF_GPIO 544#ifdef CONFIG_OF_GPIO
542/* 545/*
543 * Translate OpenFirmware node properties into platform_data 546 * Translate OpenFirmware node properties into platform_data
547 * WARNING: This is DEPRECATED and will be removed eventually!
544 */ 548 */
545static struct pca953x_platform_data * 549void
546pca953x_get_alt_pdata(struct i2c_client *client) 550pca953x_get_alt_pdata(struct i2c_client *client, int *gpio_base, int *invert)
547{ 551{
548 struct pca953x_platform_data *pdata;
549 struct device_node *node; 552 struct device_node *node;
550 const __be32 *val; 553 const __be32 *val;
551 int size; 554 int size;
552 555
553 node = client->dev.of_node; 556 node = client->dev.of_node;
554 if (node == NULL) 557 if (node == NULL)
555 return NULL; 558 return;
556
557 pdata = kzalloc(sizeof(struct pca953x_platform_data), GFP_KERNEL);
558 if (pdata == NULL) {
559 dev_err(&client->dev, "Unable to allocate platform_data\n");
560 return NULL;
561 }
562 559
563 pdata->gpio_base = -1; 560 *gpio_base = -1;
564 val = of_get_property(node, "linux,gpio-base", &size); 561 val = of_get_property(node, "linux,gpio-base", &size);
562 WARN(val, "%s: device-tree property 'linux,gpio-base' is deprecated!", __func__);
565 if (val) { 563 if (val) {
566 if (size != sizeof(*val)) 564 if (size != sizeof(*val))
567 dev_warn(&client->dev, "%s: wrong linux,gpio-base\n", 565 dev_warn(&client->dev, "%s: wrong linux,gpio-base\n",
568 node->full_name); 566 node->full_name);
569 else 567 else
570 pdata->gpio_base = be32_to_cpup(val); 568 *gpio_base = be32_to_cpup(val);
571 } 569 }
572 570
573 val = of_get_property(node, "polarity", NULL); 571 val = of_get_property(node, "polarity", NULL);
572 WARN(val, "%s: device-tree property 'polarity' is deprecated!", __func__);
574 if (val) 573 if (val)
575 pdata->invert = *val; 574 *invert = *val;
576
577 return pdata;
578} 575}
579#else 576#else
580static struct pca953x_platform_data * 577void
581pca953x_get_alt_pdata(struct i2c_client *client) 578pca953x_get_alt_pdata(struct i2c_client *client, int *gpio_base, int *invert)
582{ 579{
583 return NULL; 580 *gpio_base = -1;
584} 581}
585#endif 582#endif
586 583
@@ -642,6 +639,7 @@ static int __devinit pca953x_probe(struct i2c_client *client,
642{ 639{
643 struct pca953x_platform_data *pdata; 640 struct pca953x_platform_data *pdata;
644 struct pca953x_chip *chip; 641 struct pca953x_chip *chip;
642 int irq_base=0, invert=0;
645 int ret = 0; 643 int ret = 0;
646 644
647 chip = kzalloc(sizeof(struct pca953x_chip), GFP_KERNEL); 645 chip = kzalloc(sizeof(struct pca953x_chip), GFP_KERNEL);
@@ -649,26 +647,22 @@ static int __devinit pca953x_probe(struct i2c_client *client,
649 return -ENOMEM; 647 return -ENOMEM;
650 648
651 pdata = client->dev.platform_data; 649 pdata = client->dev.platform_data;
652 if (pdata == NULL) { 650 if (pdata) {
653 pdata = pca953x_get_alt_pdata(client); 651 irq_base = pdata->irq_base;
654 /* 652 chip->gpio_start = pdata->gpio_base;
655 * Unlike normal platform_data, this is allocated 653 invert = pdata->invert;
656 * dynamically and must be freed in the driver 654 chip->names = pdata->names;
657 */ 655 } else {
658 chip->dyn_pdata = pdata; 656 pca953x_get_alt_pdata(client, &chip->gpio_start, &invert);
659 } 657#ifdef CONFIG_OF_GPIO
660 658 /* If I2C node has no interrupts property, disable GPIO interrupts */
661 if (pdata == NULL) { 659 if (of_find_property(client->dev.of_node, "interrupts", NULL) == NULL)
662 dev_dbg(&client->dev, "no platform data\n"); 660 irq_base = -1;
663 ret = -EINVAL; 661#endif
664 goto out_failed;
665 } 662 }
666 663
667 chip->client = client; 664 chip->client = client;
668 665
669 chip->gpio_start = pdata->gpio_base;
670
671 chip->names = pdata->names;
672 chip->chip_type = id->driver_data & (PCA953X_TYPE | PCA957X_TYPE); 666 chip->chip_type = id->driver_data & (PCA953X_TYPE | PCA957X_TYPE);
673 667
674 mutex_init(&chip->i2c_lock); 668 mutex_init(&chip->i2c_lock);
@@ -679,13 +673,13 @@ static int __devinit pca953x_probe(struct i2c_client *client,
679 pca953x_setup_gpio(chip, id->driver_data & PCA_GPIO_MASK); 673 pca953x_setup_gpio(chip, id->driver_data & PCA_GPIO_MASK);
680 674
681 if (chip->chip_type == PCA953X_TYPE) 675 if (chip->chip_type == PCA953X_TYPE)
682 device_pca953x_init(chip, pdata->invert); 676 device_pca953x_init(chip, invert);
683 else if (chip->chip_type == PCA957X_TYPE) 677 else if (chip->chip_type == PCA957X_TYPE)
684 device_pca957x_init(chip, pdata->invert); 678 device_pca957x_init(chip, invert);
685 else 679 else
686 goto out_failed; 680 goto out_failed;
687 681
688 ret = pca953x_irq_setup(chip, id); 682 ret = pca953x_irq_setup(chip, id, irq_base);
689 if (ret) 683 if (ret)
690 goto out_failed; 684 goto out_failed;
691 685
@@ -693,7 +687,7 @@ static int __devinit pca953x_probe(struct i2c_client *client,
693 if (ret) 687 if (ret)
694 goto out_failed_irq; 688 goto out_failed_irq;
695 689
696 if (pdata->setup) { 690 if (pdata && pdata->setup) {
697 ret = pdata->setup(client, chip->gpio_chip.base, 691 ret = pdata->setup(client, chip->gpio_chip.base,
698 chip->gpio_chip.ngpio, pdata->context); 692 chip->gpio_chip.ngpio, pdata->context);
699 if (ret < 0) 693 if (ret < 0)
@@ -706,7 +700,6 @@ static int __devinit pca953x_probe(struct i2c_client *client,
706out_failed_irq: 700out_failed_irq:
707 pca953x_irq_teardown(chip); 701 pca953x_irq_teardown(chip);
708out_failed: 702out_failed:
709 kfree(chip->dyn_pdata);
710 kfree(chip); 703 kfree(chip);
711 return ret; 704 return ret;
712} 705}
@@ -717,7 +710,7 @@ static int pca953x_remove(struct i2c_client *client)
717 struct pca953x_chip *chip = i2c_get_clientdata(client); 710 struct pca953x_chip *chip = i2c_get_clientdata(client);
718 int ret = 0; 711 int ret = 0;
719 712
720 if (pdata->teardown) { 713 if (pdata && pdata->teardown) {
721 ret = pdata->teardown(client, chip->gpio_chip.base, 714 ret = pdata->teardown(client, chip->gpio_chip.base,
722 chip->gpio_chip.ngpio, pdata->context); 715 chip->gpio_chip.ngpio, pdata->context);
723 if (ret < 0) { 716 if (ret < 0) {
@@ -735,7 +728,6 @@ static int pca953x_remove(struct i2c_client *client)
735 } 728 }
736 729
737 pca953x_irq_teardown(chip); 730 pca953x_irq_teardown(chip);
738 kfree(chip->dyn_pdata);
739 kfree(chip); 731 kfree(chip);
740 return 0; 732 return 0;
741} 733}
diff --git a/drivers/gpio/pcf857x.c b/drivers/gpio/gpio-pcf857x.c
index 879b473aab5..7369fdda92b 100644
--- a/drivers/gpio/pcf857x.c
+++ b/drivers/gpio/gpio-pcf857x.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * pcf857x - driver for pcf857x, pca857x, and pca967x I2C GPIO expanders 2 * Driver for pcf857x, pca857x, and pca967x I2C GPIO expanders
3 * 3 *
4 * Copyright (C) 2007 David Brownell 4 * Copyright (C) 2007 David Brownell
5 * 5 *
diff --git a/drivers/gpio/pch_gpio.c b/drivers/gpio/gpio-pch.c
index 36919e77c49..36919e77c49 100644
--- a/drivers/gpio/pch_gpio.c
+++ b/drivers/gpio/gpio-pch.c
diff --git a/drivers/gpio/pl061.c b/drivers/gpio/gpio-pl061.c
index 6fcb28cdd86..2c5a18f32bf 100644
--- a/drivers/gpio/pl061.c
+++ b/drivers/gpio/gpio-pl061.c
@@ -1,7 +1,5 @@
1/* 1/*
2 * linux/drivers/gpio/pl061.c 2 * Copyright (C) 2008, 2009 Provigent Ltd.
3 *
4 * Copyright (C) 2008, 2009 Provigent Ltd.
5 * 3 *
6 * This program is free software; you can redistribute it and/or modify 4 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as 5 * it under the terms of the GNU General Public License version 2 as
diff --git a/drivers/gpio/gpio-plat-samsung.c b/drivers/gpio/gpio-plat-samsung.c
index ea37c046178..ef67f1952a7 100644
--- a/drivers/gpio/gpio-plat-samsung.c
+++ b/drivers/gpio/gpio-plat-samsung.c
@@ -1,5 +1,4 @@
1/* arch/arm/plat-samsung/gpiolib.c 1/*
2 *
3 * Copyright 2008 Openmoko, Inc. 2 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics 3 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk> 4 * Ben Dooks <ben@simtec.co.uk>
diff --git a/drivers/gpio/rdc321x-gpio.c b/drivers/gpio/gpio-rdc321x.c
index 2762698e020..2762698e020 100644
--- a/drivers/gpio/rdc321x-gpio.c
+++ b/drivers/gpio/gpio-rdc321x.c
diff --git a/drivers/gpio/gpio-s5pc100.c b/drivers/gpio/gpio-s5pc100.c
index 2842394b28b..7f87b0c76e0 100644
--- a/drivers/gpio/gpio-s5pc100.c
+++ b/drivers/gpio/gpio-s5pc100.c
@@ -1,4 +1,5 @@
1/* linux/arch/arm/mach-s5pc100/gpiolib.c 1/*
2 * S5PC100 - GPIOlib support
2 * 3 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd. 4 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com 5 * http://www.samsung.com
@@ -6,8 +7,6 @@
6 * Copyright 2009 Samsung Electronics Co 7 * Copyright 2009 Samsung Electronics Co
7 * Kyungmin Park <kyungmin.park@samsung.com> 8 * Kyungmin Park <kyungmin.park@samsung.com>
8 * 9 *
9 * S5PC100 - GPIOlib support
10 *
11 * This program is free software; you can redistribute it and/or modify 10 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as 11 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation. 12 * published by the Free Software Foundation.
diff --git a/drivers/gpio/gpio-s5pv210.c b/drivers/gpio/gpio-s5pv210.c
index 1ba20a703e0..eb12f1602de 100644
--- a/drivers/gpio/gpio-s5pv210.c
+++ b/drivers/gpio/gpio-s5pv210.c
@@ -1,10 +1,9 @@
1/* linux/arch/arm/mach-s5pv210/gpiolib.c 1/*
2 * S5PV210 - GPIOlib support
2 * 3 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd. 4 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/ 5 * http://www.samsung.com/
5 * 6 *
6 * S5PV210 - GPIOlib support
7 *
8 * This program is free software; you can redistribute it and/or modify 7 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as 8 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation. 9 * published by the Free Software Foundation.
diff --git a/drivers/gpio/sch_gpio.c b/drivers/gpio/gpio-sch.c
index 56060421cdf..16351584549 100644
--- a/drivers/gpio/sch_gpio.c
+++ b/drivers/gpio/gpio-sch.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * sch_gpio.c - GPIO interface for Intel Poulsbo SCH 2 * GPIO interface for Intel Poulsbo SCH
3 * 3 *
4 * Copyright (c) 2010 CompuLab Ltd 4 * Copyright (c) 2010 CompuLab Ltd
5 * Author: Denis Turischev <denis@compulab.co.il> 5 * Author: Denis Turischev <denis@compulab.co.il>
diff --git a/drivers/gpio/stmpe-gpio.c b/drivers/gpio/gpio-stmpe.c
index 4c980b57332..4c980b57332 100644
--- a/drivers/gpio/stmpe-gpio.c
+++ b/drivers/gpio/gpio-stmpe.c
diff --git a/drivers/gpio/sx150x.c b/drivers/gpio/gpio-sx150x.c
index a4f73534394..a4f73534394 100644
--- a/drivers/gpio/sx150x.c
+++ b/drivers/gpio/gpio-sx150x.c
diff --git a/drivers/gpio/tc3589x-gpio.c b/drivers/gpio/gpio-tc3589x.c
index 2a82e8999a4..2a82e8999a4 100644
--- a/drivers/gpio/tc3589x-gpio.c
+++ b/drivers/gpio/gpio-tc3589x.c
diff --git a/drivers/gpio/gpio-tegra.c b/drivers/gpio/gpio-tegra.c
new file mode 100644
index 00000000000..3a0893f9cdc
--- /dev/null
+++ b/drivers/gpio/gpio-tegra.c
@@ -0,0 +1,552 @@
1/*
2 * arch/arm/mach-tegra/gpio.c
3 *
4 * Copyright (c) 2010 Google, Inc
5 *
6 * Author:
7 * Erik Gilling <konkers@google.com>
8 *
9 * Copyright (c) 2011 NVIDIA Corporation.
10 *
11 * This software is licensed under the terms of the GNU General Public
12 * License version 2, as published by the Free Software Foundation, and
13 * may be copied, distributed, and modified under those terms.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 */
21
22#include <linux/init.h>
23#include <linux/irq.h>
24#include <linux/interrupt.h>
25#include <linux/delay.h>
26
27#include <linux/io.h>
28#include <linux/gpio.h>
29#include <linux/of.h>
30#include <linux/syscore_ops.h>
31
32#include <asm/mach/irq.h>
33
34#include <mach/iomap.h>
35#include <mach/pinmux.h>
36
37#include "../../../arch/arm/mach-tegra/pm-irq.h"
38
39#define GPIO_BANK(x) ((x) >> 5)
40#define GPIO_PORT(x) (((x) >> 3) & 0x3)
41#define GPIO_BIT(x) ((x) & 0x7)
42
43#define GPIO_CNF(x) (GPIO_REG(x) + 0x00)
44#define GPIO_OE(x) (GPIO_REG(x) + 0x10)
45#define GPIO_OUT(x) (GPIO_REG(x) + 0X20)
46#define GPIO_IN(x) (GPIO_REG(x) + 0x30)
47#define GPIO_INT_STA(x) (GPIO_REG(x) + 0x40)
48#define GPIO_INT_ENB(x) (GPIO_REG(x) + 0x50)
49#define GPIO_INT_LVL(x) (GPIO_REG(x) + 0x60)
50#define GPIO_INT_CLR(x) (GPIO_REG(x) + 0x70)
51
52#if defined(CONFIG_ARCH_TEGRA_2x_SOC)
53#define GPIO_REG(x) (IO_TO_VIRT(TEGRA_GPIO_BASE) + \
54 GPIO_BANK(x) * 0x80 + \
55 GPIO_PORT(x) * 4)
56
57#define GPIO_MSK_CNF(x) (GPIO_REG(x) + 0x800)
58#define GPIO_MSK_OE(x) (GPIO_REG(x) + 0x810)
59#define GPIO_MSK_OUT(x) (GPIO_REG(x) + 0X820)
60#define GPIO_MSK_INT_STA(x) (GPIO_REG(x) + 0x840)
61#define GPIO_MSK_INT_ENB(x) (GPIO_REG(x) + 0x850)
62#define GPIO_MSK_INT_LVL(x) (GPIO_REG(x) + 0x860)
63#else
64#define GPIO_REG(x) (IO_TO_VIRT(TEGRA_GPIO_BASE) + \
65 GPIO_BANK(x) * 0x100 + \
66 GPIO_PORT(x) * 4)
67
68#define GPIO_MSK_CNF(x) (GPIO_REG(x) + 0x80)
69#define GPIO_MSK_OE(x) (GPIO_REG(x) + 0x90)
70#define GPIO_MSK_OUT(x) (GPIO_REG(x) + 0XA0)
71#define GPIO_MSK_INT_STA(x) (GPIO_REG(x) + 0xC0)
72#define GPIO_MSK_INT_ENB(x) (GPIO_REG(x) + 0xD0)
73#define GPIO_MSK_INT_LVL(x) (GPIO_REG(x) + 0xE0)
74#endif
75
76#define GPIO_INT_LVL_MASK 0x010101
77#define GPIO_INT_LVL_EDGE_RISING 0x000101
78#define GPIO_INT_LVL_EDGE_FALLING 0x000100
79#define GPIO_INT_LVL_EDGE_BOTH 0x010100
80#define GPIO_INT_LVL_LEVEL_HIGH 0x000001
81#define GPIO_INT_LVL_LEVEL_LOW 0x000000
82
83struct tegra_gpio_bank {
84 int bank;
85 int irq;
86 spinlock_t lvl_lock[4];
87#ifdef CONFIG_PM_SLEEP
88 u32 cnf[4];
89 u32 out[4];
90 u32 oe[4];
91 u32 int_enb[4];
92 u32 int_lvl[4];
93#endif
94};
95
96static struct tegra_gpio_bank tegra_gpio_banks[] = {
97 {.bank = 0, .irq = INT_GPIO1},
98 {.bank = 1, .irq = INT_GPIO2},
99 {.bank = 2, .irq = INT_GPIO3},
100 {.bank = 3, .irq = INT_GPIO4},
101 {.bank = 4, .irq = INT_GPIO5},
102 {.bank = 5, .irq = INT_GPIO6},
103 {.bank = 6, .irq = INT_GPIO7},
104#ifndef CONFIG_ARCH_TEGRA_2x_SOC
105 {.bank = 7, .irq = INT_GPIO8},
106#endif
107};
108
109static int tegra_gpio_compose(int bank, int port, int bit)
110{
111 return (bank << 5) | ((port & 0x3) << 3) | (bit & 0x7);
112}
113
114void tegra_gpio_set_tristate(int gpio_nr, enum tegra_tristate ts)
115{
116 int pin_group = tegra_pinmux_get_pingroup(gpio_nr);
117 tegra_pinmux_set_tristate(pin_group, ts);
118}
119
120static void tegra_gpio_mask_write(u32 reg, int gpio, int value)
121{
122 u32 val;
123
124 val = 0x100 << GPIO_BIT(gpio);
125 if (value)
126 val |= 1 << GPIO_BIT(gpio);
127 __raw_writel(val, reg);
128}
129
130int tegra_gpio_get_bank_int_nr(int gpio)
131{
132 int bank;
133 int irq;
134 if (gpio >= TEGRA_NR_GPIOS) {
135 pr_warn("%s : Invalid gpio ID - %d\n", __func__, gpio);
136 return -EINVAL;
137 }
138 bank = gpio >> 5;
139 irq = tegra_gpio_banks[bank].irq;
140 return irq;
141}
142
143void tegra_gpio_enable(int gpio)
144{
145 if (gpio >= TEGRA_NR_GPIOS) {
146 pr_warn("%s : Invalid gpio ID - %d\n", __func__, gpio);
147 return;
148 }
149 tegra_gpio_mask_write(GPIO_MSK_CNF(gpio), gpio, 1);
150}
151EXPORT_SYMBOL_GPL(tegra_gpio_enable);
152
153void tegra_gpio_disable(int gpio)
154{
155 if (gpio >= TEGRA_NR_GPIOS) {
156 pr_warn("%s : Invalid gpio ID - %d\n", __func__, gpio);
157 return;
158 }
159 tegra_gpio_mask_write(GPIO_MSK_CNF(gpio), gpio, 0);
160}
161EXPORT_SYMBOL_GPL(tegra_gpio_disable);
162
163void tegra_gpio_init_configure(unsigned gpio, bool is_input, int value)
164{
165 if (gpio >= TEGRA_NR_GPIOS) {
166 pr_warn("%s : Invalid gpio ID - %d\n", __func__, gpio);
167 return;
168 }
169 if (is_input) {
170 tegra_gpio_mask_write(GPIO_MSK_OE(gpio), gpio, 0);
171 } else {
172 tegra_gpio_mask_write(GPIO_MSK_OUT(gpio), gpio, value);
173 tegra_gpio_mask_write(GPIO_MSK_OE(gpio), gpio, 1);
174 }
175 tegra_gpio_mask_write(GPIO_MSK_CNF(gpio), gpio, 1);
176}
177
178static void tegra_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
179{
180 tegra_gpio_mask_write(GPIO_MSK_OUT(offset), offset, value);
181}
182
183static int tegra_gpio_get(struct gpio_chip *chip, unsigned offset)
184{
185 if ((__raw_readl(GPIO_OE(offset)) >> GPIO_BIT(offset)) & 0x1)
186 return (__raw_readl(GPIO_OUT(offset)) >>
187 GPIO_BIT(offset)) & 0x1;
188 return (__raw_readl(GPIO_IN(offset)) >> GPIO_BIT(offset)) & 0x1;
189}
190
191static int tegra_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
192{
193 tegra_gpio_mask_write(GPIO_MSK_OE(offset), offset, 0);
194 return 0;
195}
196
197static int tegra_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
198 int value)
199{
200 tegra_gpio_set(chip, offset, value);
201 tegra_gpio_mask_write(GPIO_MSK_OE(offset), offset, 1);
202 return 0;
203}
204
205static int tegra_gpio_set_debounce(struct gpio_chip *chip, unsigned offset,
206 unsigned debounce)
207{
208 return -ENOSYS;
209}
210
211static int tegra_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
212{
213 return TEGRA_GPIO_TO_IRQ(offset);
214}
215
216static struct gpio_chip tegra_gpio_chip = {
217 .label = "tegra-gpio",
218 .direction_input = tegra_gpio_direction_input,
219 .get = tegra_gpio_get,
220 .direction_output = tegra_gpio_direction_output,
221 .set = tegra_gpio_set,
222 .set_debounce = tegra_gpio_set_debounce,
223 .to_irq = tegra_gpio_to_irq,
224 .base = 0,
225 .ngpio = TEGRA_NR_GPIOS,
226};
227
228static void tegra_gpio_irq_ack(struct irq_data *d)
229{
230 int gpio = d->irq - INT_GPIO_BASE;
231
232 __raw_writel(1 << GPIO_BIT(gpio), GPIO_INT_CLR(gpio));
233
234#ifdef CONFIG_TEGRA_FPGA_PLATFORM
235 /* FPGA platforms have a serializer between the GPIO
236 block and interrupt controller. Allow time for
237 clearing of the GPIO interrupt to propagate to the
238 interrupt controller before re-enabling the IRQ
239 to prevent double interrupts. */
240 udelay(15);
241#endif
242}
243
244static void tegra_gpio_irq_mask(struct irq_data *d)
245{
246 int gpio = d->irq - INT_GPIO_BASE;
247
248 tegra_gpio_mask_write(GPIO_MSK_INT_ENB(gpio), gpio, 0);
249}
250
251static void tegra_gpio_irq_unmask(struct irq_data *d)
252{
253 int gpio = d->irq - INT_GPIO_BASE;
254
255 tegra_gpio_mask_write(GPIO_MSK_INT_ENB(gpio), gpio, 1);
256}
257
258static int tegra_gpio_irq_set_type(struct irq_data *d, unsigned int type)
259{
260 int gpio = d->irq - INT_GPIO_BASE;
261 struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d);
262 int port = GPIO_PORT(gpio);
263 int lvl_type;
264 int val;
265 unsigned long flags;
266
267 switch (type & IRQ_TYPE_SENSE_MASK) {
268 case IRQ_TYPE_EDGE_RISING:
269 lvl_type = GPIO_INT_LVL_EDGE_RISING;
270 break;
271
272 case IRQ_TYPE_EDGE_FALLING:
273 lvl_type = GPIO_INT_LVL_EDGE_FALLING;
274 break;
275
276 case IRQ_TYPE_EDGE_BOTH:
277 lvl_type = GPIO_INT_LVL_EDGE_BOTH;
278 break;
279
280 case IRQ_TYPE_LEVEL_HIGH:
281 lvl_type = GPIO_INT_LVL_LEVEL_HIGH;
282 break;
283
284 case IRQ_TYPE_LEVEL_LOW:
285 lvl_type = GPIO_INT_LVL_LEVEL_LOW;
286 break;
287
288 default:
289 return -EINVAL;
290 }
291
292 spin_lock_irqsave(&bank->lvl_lock[port], flags);
293
294 val = __raw_readl(GPIO_INT_LVL(gpio));
295 val &= ~(GPIO_INT_LVL_MASK << GPIO_BIT(gpio));
296 val |= lvl_type << GPIO_BIT(gpio);
297 __raw_writel(val, GPIO_INT_LVL(gpio));
298
299 spin_unlock_irqrestore(&bank->lvl_lock[port], flags);
300
301 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
302 __irq_set_handler_locked(d->irq, handle_level_irq);
303 else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
304 __irq_set_handler_locked(d->irq, handle_edge_irq);
305
306 tegra_pm_irq_set_wake_type(d->irq, type);
307
308 return 0;
309}
310
311static void tegra_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
312{
313 struct tegra_gpio_bank *bank;
314 int port;
315 int pin;
316 struct irq_chip *chip = irq_desc_get_chip(desc);
317
318 chained_irq_enter(chip, desc);
319
320 bank = irq_get_handler_data(irq);
321
322 for (port = 0; port < 4; port++) {
323 int gpio = tegra_gpio_compose(bank->bank, port, 0);
324 unsigned long sta = __raw_readl(GPIO_INT_STA(gpio)) &
325 __raw_readl(GPIO_INT_ENB(gpio));
326
327 for_each_set_bit(pin, &sta, 8)
328 generic_handle_irq(gpio_to_irq(gpio + pin));
329 }
330
331 chained_irq_exit(chip, desc);
332
333}
334
335#ifdef CONFIG_PM_SLEEP
336static void tegra_gpio_resume(void)
337{
338 unsigned long flags;
339 int b;
340 int p;
341
342 local_irq_save(flags);
343
344 for (b = 0; b < ARRAY_SIZE(tegra_gpio_banks); b++) {
345 struct tegra_gpio_bank *bank = &tegra_gpio_banks[b];
346
347 for (p = 0; p < ARRAY_SIZE(bank->oe); p++) {
348 unsigned int gpio = (b<<5) | (p<<3);
349 __raw_writel(bank->cnf[p], GPIO_CNF(gpio));
350 __raw_writel(bank->out[p], GPIO_OUT(gpio));
351 __raw_writel(bank->oe[p], GPIO_OE(gpio));
352 __raw_writel(bank->int_lvl[p], GPIO_INT_LVL(gpio));
353 __raw_writel(bank->int_enb[p], GPIO_INT_ENB(gpio));
354 }
355 }
356
357 local_irq_restore(flags);
358}
359
360static int tegra_gpio_suspend(void)
361{
362 unsigned long flags;
363 int b;
364 int p;
365
366 local_irq_save(flags);
367 for (b = 0; b < ARRAY_SIZE(tegra_gpio_banks); b++) {
368 struct tegra_gpio_bank *bank = &tegra_gpio_banks[b];
369
370 for (p = 0; p < ARRAY_SIZE(bank->oe); p++) {
371 unsigned int gpio = (b<<5) | (p<<3);
372 bank->cnf[p] = __raw_readl(GPIO_CNF(gpio));
373 bank->out[p] = __raw_readl(GPIO_OUT(gpio));
374 bank->oe[p] = __raw_readl(GPIO_OE(gpio));
375 bank->int_enb[p] = __raw_readl(GPIO_INT_ENB(gpio));
376 bank->int_lvl[p] = __raw_readl(GPIO_INT_LVL(gpio));
377 }
378 }
379 local_irq_restore(flags);
380
381 return 0;
382}
383
384static int tegra_gpio_irq_set_wake(struct irq_data *d, unsigned int enable)
385{
386 struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d);
387 int ret = 0;
388
389 ret = tegra_pm_irq_set_wake(d->irq, enable);
390
391 if (ret)
392 return ret;
393
394 ret = irq_set_irq_wake(bank->irq, enable);
395
396 if (ret)
397 tegra_pm_irq_set_wake(d->irq, !enable);
398
399 return ret;
400}
401#else
402#define tegra_gpio_irq_set_wake NULL
403#define tegra_gpio_suspend NULL
404#define tegra_gpio_resume NULL
405#endif
406
407static struct syscore_ops tegra_gpio_syscore_ops = {
408 .suspend = tegra_gpio_suspend,
409 .resume = tegra_gpio_resume,
410};
411
412int tegra_gpio_resume_init(void)
413{
414 register_syscore_ops(&tegra_gpio_syscore_ops);
415
416 return 0;
417}
418
419static struct irq_chip tegra_gpio_irq_chip = {
420 .name = "GPIO",
421 .irq_ack = tegra_gpio_irq_ack,
422 .irq_mask = tegra_gpio_irq_mask,
423 .irq_unmask = tegra_gpio_irq_unmask,
424 .irq_set_type = tegra_gpio_irq_set_type,
425 .irq_set_wake = tegra_gpio_irq_set_wake,
426 .flags = IRQCHIP_MASK_ON_SUSPEND,
427};
428
429
430/* This lock class tells lockdep that GPIO irqs are in a different
431 * category than their parents, so it won't report false recursion.
432 */
433static struct lock_class_key gpio_lock_class;
434
435static int __init tegra_gpio_init(void)
436{
437 struct tegra_gpio_bank *bank;
438 int gpio;
439 int i;
440 int j;
441
442 for (i = 0; i < ARRAY_SIZE(tegra_gpio_banks); i++) {
443 for (j = 0; j < 4; j++) {
444 int gpio = tegra_gpio_compose(i, j, 0);
445 __raw_writel(0x00, GPIO_INT_ENB(gpio));
446 __raw_writel(0x00, GPIO_INT_STA(gpio));
447 }
448 }
449
450#ifdef CONFIG_OF_GPIO
451 /*
452 * This isn't ideal, but it gets things hooked up until this
453 * driver is converted into a platform_device
454 */
455 tegra_gpio_chip.of_node = of_find_compatible_node(NULL, NULL,
456 "nvidia,tegra20-gpio");
457#endif /* CONFIG_OF_GPIO */
458
459 gpiochip_add(&tegra_gpio_chip);
460
461 for (gpio = 0; gpio < TEGRA_NR_GPIOS; gpio++) {
462 int irq = TEGRA_GPIO_TO_IRQ(gpio);
463 /* No validity check; all Tegra GPIOs are valid IRQs */
464
465 bank = &tegra_gpio_banks[GPIO_BANK(gpio)];
466
467 irq_set_lockdep_class(irq, &gpio_lock_class);
468 irq_set_chip_data(irq, bank);
469 irq_set_chip_and_handler(irq, &tegra_gpio_irq_chip,
470 handle_simple_irq);
471 set_irq_flags(irq, IRQF_VALID);
472 }
473
474 for (i = 0; i < ARRAY_SIZE(tegra_gpio_banks); i++) {
475 bank = &tegra_gpio_banks[i];
476
477 for (j = 0; j < 4; j++)
478 spin_lock_init(&bank->lvl_lock[j]);
479
480 irq_set_handler_data(bank->irq, bank);
481 irq_set_chained_handler(bank->irq, tegra_gpio_irq_handler);
482
483 }
484
485 return 0;
486}
487
488postcore_initcall(tegra_gpio_init);
489
490void __init tegra_gpio_config(struct tegra_gpio_table *table, int num)
491{
492 int i;
493
494 for (i = 0; i < num; i++) {
495 int gpio = table[i].gpio;
496
497 if (table[i].enable)
498 tegra_gpio_enable(gpio);
499 else
500 tegra_gpio_disable(gpio);
501 }
502}
503
504#ifdef CONFIG_DEBUG_FS
505
506#include <linux/debugfs.h>
507#include <linux/seq_file.h>
508
509static int dbg_gpio_show(struct seq_file *s, void *unused)
510{
511 int i;
512 int j;
513
514 seq_printf(s, "Bank:Port CNF OE OUT IN INT_STA INT_ENB INT_LVL\n");
515 for (i = 0; i < ARRAY_SIZE(tegra_gpio_banks); i++) {
516 for (j = 0; j < 4; j++) {
517 int gpio = tegra_gpio_compose(i, j, 0);
518 seq_printf(s,
519 "%d:%d %02x %02x %02x %02x %02x %02x %06x\n",
520 i, j,
521 __raw_readl(GPIO_CNF(gpio)),
522 __raw_readl(GPIO_OE(gpio)),
523 __raw_readl(GPIO_OUT(gpio)),
524 __raw_readl(GPIO_IN(gpio)),
525 __raw_readl(GPIO_INT_STA(gpio)),
526 __raw_readl(GPIO_INT_ENB(gpio)),
527 __raw_readl(GPIO_INT_LVL(gpio)));
528 }
529 }
530 return 0;
531}
532
533static int dbg_gpio_open(struct inode *inode, struct file *file)
534{
535 return single_open(file, dbg_gpio_show, &inode->i_private);
536}
537
538static const struct file_operations debug_fops = {
539 .open = dbg_gpio_open,
540 .read = seq_read,
541 .llseek = seq_lseek,
542 .release = single_release,
543};
544
545static int __init tegra_gpio_debuginit(void)
546{
547 (void) debugfs_create_file("tegra_gpio", S_IRUGO,
548 NULL, NULL, &debug_fops);
549 return 0;
550}
551late_initcall(tegra_gpio_debuginit);
552#endif
diff --git a/drivers/gpio/timbgpio.c b/drivers/gpio/gpio-timberdale.c
index 0265872e57d..c593bd46bfb 100644
--- a/drivers/gpio/timbgpio.c
+++ b/drivers/gpio/gpio-timberdale.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * timbgpio.c timberdale FPGA GPIO driver 2 * Timberdale FPGA GPIO driver
3 * Copyright (c) 2009 Intel Corporation 3 * Copyright (c) 2009 Intel Corporation
4 * 4 *
5 * This program is free software; you can redistribute it and/or modify 5 * This program is free software; you can redistribute it and/or modify
diff --git a/drivers/gpio/tps65910-gpio.c b/drivers/gpio/gpio-tps65910.c
index 15097ca616d..7eef648a335 100644
--- a/drivers/gpio/tps65910-gpio.c
+++ b/drivers/gpio/gpio-tps65910.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * tps65910-gpio.c -- TI TPS6591x 2 * TI TPS6591x GPIO driver
3 * 3 *
4 * Copyright 2010 Texas Instruments Inc. 4 * Copyright 2010 Texas Instruments Inc.
5 * 5 *
@@ -52,7 +52,7 @@ static int tps65910_gpio_output(struct gpio_chip *gc, unsigned offset,
52 struct tps65910 *tps65910 = container_of(gc, struct tps65910, gpio); 52 struct tps65910 *tps65910 = container_of(gc, struct tps65910, gpio);
53 53
54 /* Set the initial value */ 54 /* Set the initial value */
55 tps65910_gpio_set(gc, 0, value); 55 tps65910_gpio_set(gc, offset, value);
56 56
57 return tps65910_set_bits(tps65910, TPS65910_GPIO0 + offset, 57 return tps65910_set_bits(tps65910, TPS65910_GPIO0 + offset,
58 GPIO_CFG_MASK); 58 GPIO_CFG_MASK);
@@ -69,6 +69,7 @@ static int tps65910_gpio_input(struct gpio_chip *gc, unsigned offset)
69void tps65910_gpio_init(struct tps65910 *tps65910, int gpio_base) 69void tps65910_gpio_init(struct tps65910 *tps65910, int gpio_base)
70{ 70{
71 int ret; 71 int ret;
72 struct tps65910_board *board_data;
72 73
73 if (!gpio_base) 74 if (!gpio_base)
74 return; 75 return;
@@ -80,10 +81,10 @@ void tps65910_gpio_init(struct tps65910 *tps65910, int gpio_base)
80 81
81 switch(tps65910_chip_id(tps65910)) { 82 switch(tps65910_chip_id(tps65910)) {
82 case TPS65910: 83 case TPS65910:
83 tps65910->gpio.ngpio = 6; 84 tps65910->gpio.ngpio = TPS65910_NUM_GPIO;
84 break; 85 break;
85 case TPS65911: 86 case TPS65911:
86 tps65910->gpio.ngpio = 9; 87 tps65910->gpio.ngpio = TPS65911_NUM_GPIO;
87 break; 88 break;
88 default: 89 default:
89 return; 90 return;
@@ -95,6 +96,21 @@ void tps65910_gpio_init(struct tps65910 *tps65910, int gpio_base)
95 tps65910->gpio.set = tps65910_gpio_set; 96 tps65910->gpio.set = tps65910_gpio_set;
96 tps65910->gpio.get = tps65910_gpio_get; 97 tps65910->gpio.get = tps65910_gpio_get;
97 98
99 /* Configure sleep control for gpios */
100 board_data = dev_get_platdata(tps65910->dev);
101 if (board_data) {
102 int i;
103 for (i = 0; i < tps65910->gpio.ngpio; ++i) {
104 if (board_data->en_gpio_sleep[i]) {
105 ret = tps65910_set_bits(tps65910,
106 TPS65910_GPIO0 + i, GPIO_SLEEP_MASK);
107 if (ret < 0)
108 dev_warn(tps65910->dev,
109 "GPIO Sleep setting failed\n");
110 }
111 }
112 }
113
98 ret = gpiochip_add(&tps65910->gpio); 114 ret = gpiochip_add(&tps65910->gpio);
99 115
100 if (ret) 116 if (ret)
diff --git a/drivers/gpio/gpio-tps65912.c b/drivers/gpio/gpio-tps65912.c
new file mode 100644
index 00000000000..79e66c00235
--- /dev/null
+++ b/drivers/gpio/gpio-tps65912.c
@@ -0,0 +1,156 @@
1/*
2 * Copyright 2011 Texas Instruments Inc.
3 *
4 * Author: Margarita Olaya <magi@slimlogic.co.uk>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 *
11 * This driver is based on wm8350 implementation.
12 */
13
14#include <linux/kernel.h>
15#include <linux/module.h>
16#include <linux/errno.h>
17#include <linux/gpio.h>
18#include <linux/mfd/core.h>
19#include <linux/platform_device.h>
20#include <linux/seq_file.h>
21#include <linux/slab.h>
22#include <linux/mfd/tps65912.h>
23
24struct tps65912_gpio_data {
25 struct tps65912 *tps65912;
26 struct gpio_chip gpio_chip;
27};
28
29static int tps65912_gpio_get(struct gpio_chip *gc, unsigned offset)
30{
31 struct tps65912 *tps65912 = container_of(gc, struct tps65912, gpio);
32 int val;
33
34 val = tps65912_reg_read(tps65912, TPS65912_GPIO1 + offset);
35
36 if (val & GPIO_STS_MASK)
37 return 1;
38
39 return 0;
40}
41
42static void tps65912_gpio_set(struct gpio_chip *gc, unsigned offset,
43 int value)
44{
45 struct tps65912 *tps65912 = container_of(gc, struct tps65912, gpio);
46
47 if (value)
48 tps65912_set_bits(tps65912, TPS65912_GPIO1 + offset,
49 GPIO_SET_MASK);
50 else
51 tps65912_clear_bits(tps65912, TPS65912_GPIO1 + offset,
52 GPIO_SET_MASK);
53}
54
55static int tps65912_gpio_output(struct gpio_chip *gc, unsigned offset,
56 int value)
57{
58 struct tps65912 *tps65912 = container_of(gc, struct tps65912, gpio);
59
60 /* Set the initial value */
61 tps65912_gpio_set(gc, offset, value);
62
63 return tps65912_set_bits(tps65912, TPS65912_GPIO1 + offset,
64 GPIO_CFG_MASK);
65}
66
67static int tps65912_gpio_input(struct gpio_chip *gc, unsigned offset)
68{
69 struct tps65912 *tps65912 = container_of(gc, struct tps65912, gpio);
70
71 return tps65912_clear_bits(tps65912, TPS65912_GPIO1 + offset,
72 GPIO_CFG_MASK);
73
74}
75
76static struct gpio_chip template_chip = {
77 .label = "tps65912",
78 .owner = THIS_MODULE,
79 .direction_input = tps65912_gpio_input,
80 .direction_output = tps65912_gpio_output,
81 .get = tps65912_gpio_get,
82 .set = tps65912_gpio_set,
83 .can_sleep = 1,
84 .ngpio = 5,
85 .base = -1,
86};
87
88static int __devinit tps65912_gpio_probe(struct platform_device *pdev)
89{
90 struct tps65912 *tps65912 = dev_get_drvdata(pdev->dev.parent);
91 struct tps65912_board *pdata = tps65912->dev->platform_data;
92 struct tps65912_gpio_data *tps65912_gpio;
93 int ret;
94
95 tps65912_gpio = kzalloc(sizeof(*tps65912_gpio), GFP_KERNEL);
96 if (tps65912_gpio == NULL)
97 return -ENOMEM;
98
99 tps65912_gpio->tps65912 = tps65912;
100 tps65912_gpio->gpio_chip = template_chip;
101 tps65912_gpio->gpio_chip.dev = &pdev->dev;
102 if (pdata && pdata->gpio_base)
103 tps65912_gpio->gpio_chip.base = pdata->gpio_base;
104
105 ret = gpiochip_add(&tps65912_gpio->gpio_chip);
106 if (ret < 0) {
107 dev_err(&pdev->dev, "Failed to register gpiochip, %d\n", ret);
108 goto err;
109 }
110
111 platform_set_drvdata(pdev, tps65912_gpio);
112
113 return ret;
114
115err:
116 kfree(tps65912_gpio);
117 return ret;
118}
119
120static int __devexit tps65912_gpio_remove(struct platform_device *pdev)
121{
122 struct tps65912_gpio_data *tps65912_gpio = platform_get_drvdata(pdev);
123 int ret;
124
125 ret = gpiochip_remove(&tps65912_gpio->gpio_chip);
126 if (ret == 0)
127 kfree(tps65912_gpio);
128
129 return ret;
130}
131
132static struct platform_driver tps65912_gpio_driver = {
133 .driver = {
134 .name = "tps65912-gpio",
135 .owner = THIS_MODULE,
136 },
137 .probe = tps65912_gpio_probe,
138 .remove = __devexit_p(tps65912_gpio_remove),
139};
140
141static int __init tps65912_gpio_init(void)
142{
143 return platform_driver_register(&tps65912_gpio_driver);
144}
145subsys_initcall(tps65912_gpio_init);
146
147static void __exit tps65912_gpio_exit(void)
148{
149 platform_driver_unregister(&tps65912_gpio_driver);
150}
151module_exit(tps65912_gpio_exit);
152
153MODULE_AUTHOR("Margarita Olaya Cabrera <magi@slimlogic.co.uk>");
154MODULE_DESCRIPTION("GPIO interface for TPS65912 PMICs");
155MODULE_LICENSE("GPL v2");
156MODULE_ALIAS("platform:tps65912-gpio");
diff --git a/drivers/gpio/twl4030-gpio.c b/drivers/gpio/gpio-twl4030.c
index 57635ac35a7..b8b4f228757 100644
--- a/drivers/gpio/twl4030-gpio.c
+++ b/drivers/gpio/gpio-twl4030.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * twl4030_gpio.c -- access to GPIOs on TWL4030/TPS659x0 chips 2 * Access to GPIOs on TWL4030/TPS659x0 chips
3 * 3 *
4 * Copyright (C) 2006-2007 Texas Instruments, Inc. 4 * Copyright (C) 2006-2007 Texas Instruments, Inc.
5 * Copyright (C) 2006 MontaVista Software, Inc. 5 * Copyright (C) 2006 MontaVista Software, Inc.
diff --git a/drivers/gpio/gpio-u300.c b/drivers/gpio/gpio-u300.c
index d92790140fe..53e8255cb0b 100644
--- a/drivers/gpio/gpio-u300.c
+++ b/drivers/gpio/gpio-u300.c
@@ -1,11 +1,8 @@
1/* 1/*
2 * 2 * U300 GPIO module.
3 * arch/arm/mach-u300/gpio.c
4 *
5 * 3 *
6 * Copyright (C) 2007-2009 ST-Ericsson AB 4 * Copyright (C) 2007-2009 ST-Ericsson AB
7 * License terms: GNU General Public License (GPL) version 2 5 * License terms: GNU General Public License (GPL) version 2
8 * U300 GPIO module.
9 * This can driver either of the two basic GPIO cores 6 * This can driver either of the two basic GPIO cores
10 * available in the U300 platforms: 7 * available in the U300 platforms:
11 * COH 901 335 - Used in DB3150 (U300 1.0) and DB3200 (U330 1.0) 8 * COH 901 335 - Used in DB3150 (U300 1.0) and DB3200 (U330 1.0)
@@ -581,8 +578,8 @@ static int __init gpio_probe(struct platform_device *pdev)
581 if (!memres) 578 if (!memres)
582 goto err_no_resource; 579 goto err_no_resource;
583 580
584 if (request_mem_region(memres->start, memres->end - memres->start, "GPIO Controller") 581 if (!request_mem_region(memres->start, resource_size(memres),
585 == NULL) { 582 "GPIO Controller")) {
586 err = -ENODEV; 583 err = -ENODEV;
587 goto err_no_ioregion; 584 goto err_no_ioregion;
588 } 585 }
@@ -640,7 +637,7 @@ static int __init gpio_probe(struct platform_device *pdev)
640 free_irq(gpio_ports[i].irq, &gpio_ports[i]); 637 free_irq(gpio_ports[i].irq, &gpio_ports[i]);
641 iounmap(virtbase); 638 iounmap(virtbase);
642 err_no_ioremap: 639 err_no_ioremap:
643 release_mem_region(memres->start, memres->end - memres->start); 640 release_mem_region(memres->start, resource_size(memres));
644 err_no_ioregion: 641 err_no_ioregion:
645 err_no_resource: 642 err_no_resource:
646 clk_disable(clk); 643 clk_disable(clk);
@@ -660,7 +657,7 @@ static int __exit gpio_remove(struct platform_device *pdev)
660 for (i = 0 ; i < U300_GPIO_NUM_PORTS; i++) 657 for (i = 0 ; i < U300_GPIO_NUM_PORTS; i++)
661 free_irq(gpio_ports[i].irq, &gpio_ports[i]); 658 free_irq(gpio_ports[i].irq, &gpio_ports[i]);
662 iounmap(virtbase); 659 iounmap(virtbase);
663 release_mem_region(memres->start, memres->end - memres->start); 660 release_mem_region(memres->start, resource_size(memres));
664 clk_disable(clk); 661 clk_disable(clk);
665 clk_put(clk); 662 clk_put(clk);
666 return 0; 663 return 0;
diff --git a/drivers/gpio/ucb1400_gpio.c b/drivers/gpio/gpio-ucb1400.c
index 50e6bd1392c..50e6bd1392c 100644
--- a/drivers/gpio/ucb1400_gpio.c
+++ b/drivers/gpio/gpio-ucb1400.c
diff --git a/drivers/gpio/vr41xx_giu.c b/drivers/gpio/gpio-vr41xx.c
index a365be040b3..98723cb9ac6 100644
--- a/drivers/gpio/vr41xx_giu.c
+++ b/drivers/gpio/gpio-vr41xx.c
@@ -518,7 +518,7 @@ static int __devinit giu_probe(struct platform_device *pdev)
518 if (!res) 518 if (!res)
519 return -EBUSY; 519 return -EBUSY;
520 520
521 giu_base = ioremap(res->start, res->end - res->start + 1); 521 giu_base = ioremap(res->start, resource_size(res));
522 if (!giu_base) 522 if (!giu_base)
523 return -ENOMEM; 523 return -ENOMEM;
524 524
diff --git a/drivers/gpio/vx855_gpio.c b/drivers/gpio/gpio-vx855.c
index ef5aabd8b8b..ef5aabd8b8b 100644
--- a/drivers/gpio/vx855_gpio.c
+++ b/drivers/gpio/gpio-vx855.c
diff --git a/drivers/gpio/wm831x-gpio.c b/drivers/gpio/gpio-wm831x.c
index 2bcfb0be09f..deb949e75ec 100644
--- a/drivers/gpio/wm831x-gpio.c
+++ b/drivers/gpio/gpio-wm831x.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * wm831x-gpio.c -- gpiolib support for Wolfson WM831x PMICs 2 * gpiolib support for Wolfson WM831x PMICs
3 * 3 *
4 * Copyright 2009 Wolfson Microelectronics PLC. 4 * Copyright 2009 Wolfson Microelectronics PLC.
5 * 5 *
diff --git a/drivers/gpio/wm8350-gpiolib.c b/drivers/gpio/gpio-wm8350.c
index 359999290f5..a06af515483 100644
--- a/drivers/gpio/wm8350-gpiolib.c
+++ b/drivers/gpio/gpio-wm8350.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * wm835x-gpiolib.c -- gpiolib support for Wolfson WM835x PMICs 2 * gpiolib support for Wolfson WM835x PMICs
3 * 3 *
4 * Copyright 2009 Wolfson Microelectronics PLC. 4 * Copyright 2009 Wolfson Microelectronics PLC.
5 * 5 *
diff --git a/drivers/gpio/wm8994-gpio.c b/drivers/gpio/gpio-wm8994.c
index c822baacd8f..96198f3fab7 100644
--- a/drivers/gpio/wm8994-gpio.c
+++ b/drivers/gpio/gpio-wm8994.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * wm8994-gpio.c -- gpiolib support for Wolfson WM8994 2 * gpiolib support for Wolfson WM8994
3 * 3 *
4 * Copyright 2009 Wolfson Microelectronics PLC. 4 * Copyright 2009 Wolfson Microelectronics PLC.
5 * 5 *
diff --git a/drivers/gpio/xilinx_gpio.c b/drivers/gpio/gpio-xilinx.c
index 846fbd5e31b..846fbd5e31b 100644
--- a/drivers/gpio/xilinx_gpio.c
+++ b/drivers/gpio/gpio-xilinx.c
diff --git a/drivers/gpio/gpiolib.c b/drivers/gpio/gpiolib.c
index a971e3d043b..a0fa0b25d21 100644
--- a/drivers/gpio/gpiolib.c
+++ b/drivers/gpio/gpiolib.c
@@ -58,6 +58,8 @@ struct gpio_desc {
58#define FLAG_TRIG_FALL 5 /* trigger on falling edge */ 58#define FLAG_TRIG_FALL 5 /* trigger on falling edge */
59#define FLAG_TRIG_RISE 6 /* trigger on rising edge */ 59#define FLAG_TRIG_RISE 6 /* trigger on rising edge */
60#define FLAG_ACTIVE_LOW 7 /* sysfs value has active low */ 60#define FLAG_ACTIVE_LOW 7 /* sysfs value has active low */
61#define FLAG_OPEN_DRAIN 8 /* Gpio is open drain type */
62#define FLAG_OPEN_SOURCE 9 /* Gpio is open source type */
61 63
62#define ID_SHIFT 16 /* add new flags before this one */ 64#define ID_SHIFT 16 /* add new flags before this one */
63 65
@@ -1257,6 +1259,8 @@ void gpio_free(unsigned gpio)
1257 module_put(desc->chip->owner); 1259 module_put(desc->chip->owner);
1258 clear_bit(FLAG_ACTIVE_LOW, &desc->flags); 1260 clear_bit(FLAG_ACTIVE_LOW, &desc->flags);
1259 clear_bit(FLAG_REQUESTED, &desc->flags); 1261 clear_bit(FLAG_REQUESTED, &desc->flags);
1262 clear_bit(FLAG_OPEN_DRAIN, &desc->flags);
1263 clear_bit(FLAG_OPEN_SOURCE, &desc->flags);
1260 } else 1264 } else
1261 WARN_ON(extra_checks); 1265 WARN_ON(extra_checks);
1262 1266
@@ -1278,6 +1282,12 @@ int gpio_request_one(unsigned gpio, unsigned long flags, const char *label)
1278 if (err) 1282 if (err)
1279 return err; 1283 return err;
1280 1284
1285 if (flags & GPIOF_OPEN_DRAIN)
1286 set_bit(FLAG_OPEN_DRAIN, &gpio_desc[gpio].flags);
1287
1288 if (flags & GPIOF_OPEN_SOURCE)
1289 set_bit(FLAG_OPEN_SOURCE, &gpio_desc[gpio].flags);
1290
1281 if (flags & GPIOF_DIR_IN) 1291 if (flags & GPIOF_DIR_IN)
1282 err = gpio_direction_input(gpio); 1292 err = gpio_direction_input(gpio);
1283 else 1293 else
@@ -1427,6 +1437,14 @@ int gpio_direction_output(unsigned gpio, int value)
1427 struct gpio_desc *desc = &gpio_desc[gpio]; 1437 struct gpio_desc *desc = &gpio_desc[gpio];
1428 int status = -EINVAL; 1438 int status = -EINVAL;
1429 1439
1440 /* Open drain pin should not be driven to 1 */
1441 if (value && test_bit(FLAG_OPEN_DRAIN, &desc->flags))
1442 return gpio_direction_input(gpio);
1443
1444 /* Open source pin should not be driven to 0 */
1445 if (!value && test_bit(FLAG_OPEN_SOURCE, &desc->flags))
1446 return gpio_direction_input(gpio);
1447
1430 spin_lock_irqsave(&gpio_lock, flags); 1448 spin_lock_irqsave(&gpio_lock, flags);
1431 1449
1432 if (!gpio_is_valid(gpio)) 1450 if (!gpio_is_valid(gpio))
@@ -1563,6 +1581,57 @@ int __gpio_get_value(unsigned gpio)
1563} 1581}
1564EXPORT_SYMBOL_GPL(__gpio_get_value); 1582EXPORT_SYMBOL_GPL(__gpio_get_value);
1565 1583
1584/*
1585 * _gpio_set_open_drain_value() - Set the open drain gpio's value.
1586 * @gpio: Gpio whose state need to be set.
1587 * @chip: Gpio chip.
1588 * @value: Non-zero for setting it HIGH otherise it will set to LOW.
1589 */
1590static void _gpio_set_open_drain_value(unsigned gpio,
1591 struct gpio_chip *chip, int value)
1592{
1593 int err = 0;
1594 if (value) {
1595 err = chip->direction_input(chip, gpio - chip->base);
1596 if (!err)
1597 clear_bit(FLAG_IS_OUT, &gpio_desc[gpio].flags);
1598 } else {
1599 err = chip->direction_output(chip, gpio - chip->base, 0);
1600 if (!err)
1601 set_bit(FLAG_IS_OUT, &gpio_desc[gpio].flags);
1602 }
1603 trace_gpio_direction(gpio, value, err);
1604 if (err < 0)
1605 pr_err("%s: Error in set_value for open drain gpio%d err %d\n",
1606 __func__, gpio, err);
1607}
1608
1609/*
1610 * _gpio_set_open_source() - Set the open source gpio's value.
1611 * @gpio: Gpio whose state need to be set.
1612 * @chip: Gpio chip.
1613 * @value: Non-zero for setting it HIGH otherise it will set to LOW.
1614 */
1615static void _gpio_set_open_source_value(unsigned gpio,
1616 struct gpio_chip *chip, int value)
1617{
1618 int err = 0;
1619 if (value) {
1620 err = chip->direction_output(chip, gpio - chip->base, 1);
1621 if (!err)
1622 set_bit(FLAG_IS_OUT, &gpio_desc[gpio].flags);
1623 } else {
1624 err = chip->direction_input(chip, gpio - chip->base);
1625 if (!err)
1626 clear_bit(FLAG_IS_OUT, &gpio_desc[gpio].flags);
1627 }
1628 trace_gpio_direction(gpio, !value, err);
1629 if (err < 0)
1630 pr_err("%s: Error in set_value for open source gpio%d err %d\n",
1631 __func__, gpio, err);
1632}
1633
1634
1566/** 1635/**
1567 * __gpio_set_value() - assign a gpio's value 1636 * __gpio_set_value() - assign a gpio's value
1568 * @gpio: gpio whose value will be assigned 1637 * @gpio: gpio whose value will be assigned
@@ -1579,7 +1648,12 @@ void __gpio_set_value(unsigned gpio, int value)
1579 chip = gpio_to_chip(gpio); 1648 chip = gpio_to_chip(gpio);
1580 WARN_ON(chip->can_sleep); 1649 WARN_ON(chip->can_sleep);
1581 trace_gpio_value(gpio, 0, value); 1650 trace_gpio_value(gpio, 0, value);
1582 chip->set(chip, gpio - chip->base, value); 1651 if (test_bit(FLAG_OPEN_DRAIN, &gpio_desc[gpio].flags))
1652 _gpio_set_open_drain_value(gpio, chip, value);
1653 else if (test_bit(FLAG_OPEN_SOURCE, &gpio_desc[gpio].flags))
1654 _gpio_set_open_source_value(gpio, chip, value);
1655 else
1656 chip->set(chip, gpio - chip->base, value);
1583} 1657}
1584EXPORT_SYMBOL_GPL(__gpio_set_value); 1658EXPORT_SYMBOL_GPL(__gpio_set_value);
1585 1659
@@ -1646,7 +1720,12 @@ void gpio_set_value_cansleep(unsigned gpio, int value)
1646 might_sleep_if(extra_checks); 1720 might_sleep_if(extra_checks);
1647 chip = gpio_to_chip(gpio); 1721 chip = gpio_to_chip(gpio);
1648 trace_gpio_value(gpio, 0, value); 1722 trace_gpio_value(gpio, 0, value);
1649 chip->set(chip, gpio - chip->base, value); 1723 if (test_bit(FLAG_OPEN_DRAIN, &gpio_desc[gpio].flags))
1724 _gpio_set_open_drain_value(gpio, chip, value);
1725 else if (test_bit(FLAG_OPEN_SOURCE, &gpio_desc[gpio].flags))
1726 _gpio_set_open_source_value(gpio, chip, value);
1727 else
1728 chip->set(chip, gpio - chip->base, value);
1650} 1729}
1651EXPORT_SYMBOL_GPL(gpio_set_value_cansleep); 1730EXPORT_SYMBOL_GPL(gpio_set_value_cansleep);
1652 1731
generated by cgit v1.2.2 (git 2.25.0) at 2025-09-03 05:21:20 -0400