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path: root/drivers/gpio/gpio-tegra.c
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-rw-r--r--drivers/gpio/gpio-tegra.c552
1 files changed, 552 insertions, 0 deletions
diff --git a/drivers/gpio/gpio-tegra.c b/drivers/gpio/gpio-tegra.c
new file mode 100644
index 00000000000..3a0893f9cdc
--- /dev/null
+++ b/drivers/gpio/gpio-tegra.c
@@ -0,0 +1,552 @@
1/*
2 * arch/arm/mach-tegra/gpio.c
3 *
4 * Copyright (c) 2010 Google, Inc
5 *
6 * Author:
7 * Erik Gilling <konkers@google.com>
8 *
9 * Copyright (c) 2011 NVIDIA Corporation.
10 *
11 * This software is licensed under the terms of the GNU General Public
12 * License version 2, as published by the Free Software Foundation, and
13 * may be copied, distributed, and modified under those terms.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 */
21
22#include <linux/init.h>
23#include <linux/irq.h>
24#include <linux/interrupt.h>
25#include <linux/delay.h>
26
27#include <linux/io.h>
28#include <linux/gpio.h>
29#include <linux/of.h>
30#include <linux/syscore_ops.h>
31
32#include <asm/mach/irq.h>
33
34#include <mach/iomap.h>
35#include <mach/pinmux.h>
36
37#include "../../../arch/arm/mach-tegra/pm-irq.h"
38
39#define GPIO_BANK(x) ((x) >> 5)
40#define GPIO_PORT(x) (((x) >> 3) & 0x3)
41#define GPIO_BIT(x) ((x) & 0x7)
42
43#define GPIO_CNF(x) (GPIO_REG(x) + 0x00)
44#define GPIO_OE(x) (GPIO_REG(x) + 0x10)
45#define GPIO_OUT(x) (GPIO_REG(x) + 0X20)
46#define GPIO_IN(x) (GPIO_REG(x) + 0x30)
47#define GPIO_INT_STA(x) (GPIO_REG(x) + 0x40)
48#define GPIO_INT_ENB(x) (GPIO_REG(x) + 0x50)
49#define GPIO_INT_LVL(x) (GPIO_REG(x) + 0x60)
50#define GPIO_INT_CLR(x) (GPIO_REG(x) + 0x70)
51
52#if defined(CONFIG_ARCH_TEGRA_2x_SOC)
53#define GPIO_REG(x) (IO_TO_VIRT(TEGRA_GPIO_BASE) + \
54 GPIO_BANK(x) * 0x80 + \
55 GPIO_PORT(x) * 4)
56
57#define GPIO_MSK_CNF(x) (GPIO_REG(x) + 0x800)
58#define GPIO_MSK_OE(x) (GPIO_REG(x) + 0x810)
59#define GPIO_MSK_OUT(x) (GPIO_REG(x) + 0X820)
60#define GPIO_MSK_INT_STA(x) (GPIO_REG(x) + 0x840)
61#define GPIO_MSK_INT_ENB(x) (GPIO_REG(x) + 0x850)
62#define GPIO_MSK_INT_LVL(x) (GPIO_REG(x) + 0x860)
63#else
64#define GPIO_REG(x) (IO_TO_VIRT(TEGRA_GPIO_BASE) + \
65 GPIO_BANK(x) * 0x100 + \
66 GPIO_PORT(x) * 4)
67
68#define GPIO_MSK_CNF(x) (GPIO_REG(x) + 0x80)
69#define GPIO_MSK_OE(x) (GPIO_REG(x) + 0x90)
70#define GPIO_MSK_OUT(x) (GPIO_REG(x) + 0XA0)
71#define GPIO_MSK_INT_STA(x) (GPIO_REG(x) + 0xC0)
72#define GPIO_MSK_INT_ENB(x) (GPIO_REG(x) + 0xD0)
73#define GPIO_MSK_INT_LVL(x) (GPIO_REG(x) + 0xE0)
74#endif
75
76#define GPIO_INT_LVL_MASK 0x010101
77#define GPIO_INT_LVL_EDGE_RISING 0x000101
78#define GPIO_INT_LVL_EDGE_FALLING 0x000100
79#define GPIO_INT_LVL_EDGE_BOTH 0x010100
80#define GPIO_INT_LVL_LEVEL_HIGH 0x000001
81#define GPIO_INT_LVL_LEVEL_LOW 0x000000
82
83struct tegra_gpio_bank {
84 int bank;
85 int irq;
86 spinlock_t lvl_lock[4];
87#ifdef CONFIG_PM_SLEEP
88 u32 cnf[4];
89 u32 out[4];
90 u32 oe[4];
91 u32 int_enb[4];
92 u32 int_lvl[4];
93#endif
94};
95
96static struct tegra_gpio_bank tegra_gpio_banks[] = {
97 {.bank = 0, .irq = INT_GPIO1},
98 {.bank = 1, .irq = INT_GPIO2},
99 {.bank = 2, .irq = INT_GPIO3},
100 {.bank = 3, .irq = INT_GPIO4},
101 {.bank = 4, .irq = INT_GPIO5},
102 {.bank = 5, .irq = INT_GPIO6},
103 {.bank = 6, .irq = INT_GPIO7},
104#ifndef CONFIG_ARCH_TEGRA_2x_SOC
105 {.bank = 7, .irq = INT_GPIO8},
106#endif
107};
108
109static int tegra_gpio_compose(int bank, int port, int bit)
110{
111 return (bank << 5) | ((port & 0x3) << 3) | (bit & 0x7);
112}
113
114void tegra_gpio_set_tristate(int gpio_nr, enum tegra_tristate ts)
115{
116 int pin_group = tegra_pinmux_get_pingroup(gpio_nr);
117 tegra_pinmux_set_tristate(pin_group, ts);
118}
119
120static void tegra_gpio_mask_write(u32 reg, int gpio, int value)
121{
122 u32 val;
123
124 val = 0x100 << GPIO_BIT(gpio);
125 if (value)
126 val |= 1 << GPIO_BIT(gpio);
127 __raw_writel(val, reg);
128}
129
130int tegra_gpio_get_bank_int_nr(int gpio)
131{
132 int bank;
133 int irq;
134 if (gpio >= TEGRA_NR_GPIOS) {
135 pr_warn("%s : Invalid gpio ID - %d\n", __func__, gpio);
136 return -EINVAL;
137 }
138 bank = gpio >> 5;
139 irq = tegra_gpio_banks[bank].irq;
140 return irq;
141}
142
143void tegra_gpio_enable(int gpio)
144{
145 if (gpio >= TEGRA_NR_GPIOS) {
146 pr_warn("%s : Invalid gpio ID - %d\n", __func__, gpio);
147 return;
148 }
149 tegra_gpio_mask_write(GPIO_MSK_CNF(gpio), gpio, 1);
150}
151EXPORT_SYMBOL_GPL(tegra_gpio_enable);
152
153void tegra_gpio_disable(int gpio)
154{
155 if (gpio >= TEGRA_NR_GPIOS) {
156 pr_warn("%s : Invalid gpio ID - %d\n", __func__, gpio);
157 return;
158 }
159 tegra_gpio_mask_write(GPIO_MSK_CNF(gpio), gpio, 0);
160}
161EXPORT_SYMBOL_GPL(tegra_gpio_disable);
162
163void tegra_gpio_init_configure(unsigned gpio, bool is_input, int value)
164{
165 if (gpio >= TEGRA_NR_GPIOS) {
166 pr_warn("%s : Invalid gpio ID - %d\n", __func__, gpio);
167 return;
168 }
169 if (is_input) {
170 tegra_gpio_mask_write(GPIO_MSK_OE(gpio), gpio, 0);
171 } else {
172 tegra_gpio_mask_write(GPIO_MSK_OUT(gpio), gpio, value);
173 tegra_gpio_mask_write(GPIO_MSK_OE(gpio), gpio, 1);
174 }
175 tegra_gpio_mask_write(GPIO_MSK_CNF(gpio), gpio, 1);
176}
177
178static void tegra_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
179{
180 tegra_gpio_mask_write(GPIO_MSK_OUT(offset), offset, value);
181}
182
183static int tegra_gpio_get(struct gpio_chip *chip, unsigned offset)
184{
185 if ((__raw_readl(GPIO_OE(offset)) >> GPIO_BIT(offset)) & 0x1)
186 return (__raw_readl(GPIO_OUT(offset)) >>
187 GPIO_BIT(offset)) & 0x1;
188 return (__raw_readl(GPIO_IN(offset)) >> GPIO_BIT(offset)) & 0x1;
189}
190
191static int tegra_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
192{
193 tegra_gpio_mask_write(GPIO_MSK_OE(offset), offset, 0);
194 return 0;
195}
196
197static int tegra_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
198 int value)
199{
200 tegra_gpio_set(chip, offset, value);
201 tegra_gpio_mask_write(GPIO_MSK_OE(offset), offset, 1);
202 return 0;
203}
204
205static int tegra_gpio_set_debounce(struct gpio_chip *chip, unsigned offset,
206 unsigned debounce)
207{
208 return -ENOSYS;
209}
210
211static int tegra_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
212{
213 return TEGRA_GPIO_TO_IRQ(offset);
214}
215
216static struct gpio_chip tegra_gpio_chip = {
217 .label = "tegra-gpio",
218 .direction_input = tegra_gpio_direction_input,
219 .get = tegra_gpio_get,
220 .direction_output = tegra_gpio_direction_output,
221 .set = tegra_gpio_set,
222 .set_debounce = tegra_gpio_set_debounce,
223 .to_irq = tegra_gpio_to_irq,
224 .base = 0,
225 .ngpio = TEGRA_NR_GPIOS,
226};
227
228static void tegra_gpio_irq_ack(struct irq_data *d)
229{
230 int gpio = d->irq - INT_GPIO_BASE;
231
232 __raw_writel(1 << GPIO_BIT(gpio), GPIO_INT_CLR(gpio));
233
234#ifdef CONFIG_TEGRA_FPGA_PLATFORM
235 /* FPGA platforms have a serializer between the GPIO
236 block and interrupt controller. Allow time for
237 clearing of the GPIO interrupt to propagate to the
238 interrupt controller before re-enabling the IRQ
239 to prevent double interrupts. */
240 udelay(15);
241#endif
242}
243
244static void tegra_gpio_irq_mask(struct irq_data *d)
245{
246 int gpio = d->irq - INT_GPIO_BASE;
247
248 tegra_gpio_mask_write(GPIO_MSK_INT_ENB(gpio), gpio, 0);
249}
250
251static void tegra_gpio_irq_unmask(struct irq_data *d)
252{
253 int gpio = d->irq - INT_GPIO_BASE;
254
255 tegra_gpio_mask_write(GPIO_MSK_INT_ENB(gpio), gpio, 1);
256}
257
258static int tegra_gpio_irq_set_type(struct irq_data *d, unsigned int type)
259{
260 int gpio = d->irq - INT_GPIO_BASE;
261 struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d);
262 int port = GPIO_PORT(gpio);
263 int lvl_type;
264 int val;
265 unsigned long flags;
266
267 switch (type & IRQ_TYPE_SENSE_MASK) {
268 case IRQ_TYPE_EDGE_RISING:
269 lvl_type = GPIO_INT_LVL_EDGE_RISING;
270 break;
271
272 case IRQ_TYPE_EDGE_FALLING:
273 lvl_type = GPIO_INT_LVL_EDGE_FALLING;
274 break;
275
276 case IRQ_TYPE_EDGE_BOTH:
277 lvl_type = GPIO_INT_LVL_EDGE_BOTH;
278 break;
279
280 case IRQ_TYPE_LEVEL_HIGH:
281 lvl_type = GPIO_INT_LVL_LEVEL_HIGH;
282 break;
283
284 case IRQ_TYPE_LEVEL_LOW:
285 lvl_type = GPIO_INT_LVL_LEVEL_LOW;
286 break;
287
288 default:
289 return -EINVAL;
290 }
291
292 spin_lock_irqsave(&bank->lvl_lock[port], flags);
293
294 val = __raw_readl(GPIO_INT_LVL(gpio));
295 val &= ~(GPIO_INT_LVL_MASK << GPIO_BIT(gpio));
296 val |= lvl_type << GPIO_BIT(gpio);
297 __raw_writel(val, GPIO_INT_LVL(gpio));
298
299 spin_unlock_irqrestore(&bank->lvl_lock[port], flags);
300
301 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
302 __irq_set_handler_locked(d->irq, handle_level_irq);
303 else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
304 __irq_set_handler_locked(d->irq, handle_edge_irq);
305
306 tegra_pm_irq_set_wake_type(d->irq, type);
307
308 return 0;
309}
310
311static void tegra_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
312{
313 struct tegra_gpio_bank *bank;
314 int port;
315 int pin;
316 struct irq_chip *chip = irq_desc_get_chip(desc);
317
318 chained_irq_enter(chip, desc);
319
320 bank = irq_get_handler_data(irq);
321
322 for (port = 0; port < 4; port++) {
323 int gpio = tegra_gpio_compose(bank->bank, port, 0);
324 unsigned long sta = __raw_readl(GPIO_INT_STA(gpio)) &
325 __raw_readl(GPIO_INT_ENB(gpio));
326
327 for_each_set_bit(pin, &sta, 8)
328 generic_handle_irq(gpio_to_irq(gpio + pin));
329 }
330
331 chained_irq_exit(chip, desc);
332
333}
334
335#ifdef CONFIG_PM_SLEEP
336static void tegra_gpio_resume(void)
337{
338 unsigned long flags;
339 int b;
340 int p;
341
342 local_irq_save(flags);
343
344 for (b = 0; b < ARRAY_SIZE(tegra_gpio_banks); b++) {
345 struct tegra_gpio_bank *bank = &tegra_gpio_banks[b];
346
347 for (p = 0; p < ARRAY_SIZE(bank->oe); p++) {
348 unsigned int gpio = (b<<5) | (p<<3);
349 __raw_writel(bank->cnf[p], GPIO_CNF(gpio));
350 __raw_writel(bank->out[p], GPIO_OUT(gpio));
351 __raw_writel(bank->oe[p], GPIO_OE(gpio));
352 __raw_writel(bank->int_lvl[p], GPIO_INT_LVL(gpio));
353 __raw_writel(bank->int_enb[p], GPIO_INT_ENB(gpio));
354 }
355 }
356
357 local_irq_restore(flags);
358}
359
360static int tegra_gpio_suspend(void)
361{
362 unsigned long flags;
363 int b;
364 int p;
365
366 local_irq_save(flags);
367 for (b = 0; b < ARRAY_SIZE(tegra_gpio_banks); b++) {
368 struct tegra_gpio_bank *bank = &tegra_gpio_banks[b];
369
370 for (p = 0; p < ARRAY_SIZE(bank->oe); p++) {
371 unsigned int gpio = (b<<5) | (p<<3);
372 bank->cnf[p] = __raw_readl(GPIO_CNF(gpio));
373 bank->out[p] = __raw_readl(GPIO_OUT(gpio));
374 bank->oe[p] = __raw_readl(GPIO_OE(gpio));
375 bank->int_enb[p] = __raw_readl(GPIO_INT_ENB(gpio));
376 bank->int_lvl[p] = __raw_readl(GPIO_INT_LVL(gpio));
377 }
378 }
379 local_irq_restore(flags);
380
381 return 0;
382}
383
384static int tegra_gpio_irq_set_wake(struct irq_data *d, unsigned int enable)
385{
386 struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d);
387 int ret = 0;
388
389 ret = tegra_pm_irq_set_wake(d->irq, enable);
390
391 if (ret)
392 return ret;
393
394 ret = irq_set_irq_wake(bank->irq, enable);
395
396 if (ret)
397 tegra_pm_irq_set_wake(d->irq, !enable);
398
399 return ret;
400}
401#else
402#define tegra_gpio_irq_set_wake NULL
403#define tegra_gpio_suspend NULL
404#define tegra_gpio_resume NULL
405#endif
406
407static struct syscore_ops tegra_gpio_syscore_ops = {
408 .suspend = tegra_gpio_suspend,
409 .resume = tegra_gpio_resume,
410};
411
412int tegra_gpio_resume_init(void)
413{
414 register_syscore_ops(&tegra_gpio_syscore_ops);
415
416 return 0;
417}
418
419static struct irq_chip tegra_gpio_irq_chip = {
420 .name = "GPIO",
421 .irq_ack = tegra_gpio_irq_ack,
422 .irq_mask = tegra_gpio_irq_mask,
423 .irq_unmask = tegra_gpio_irq_unmask,
424 .irq_set_type = tegra_gpio_irq_set_type,
425 .irq_set_wake = tegra_gpio_irq_set_wake,
426 .flags = IRQCHIP_MASK_ON_SUSPEND,
427};
428
429
430/* This lock class tells lockdep that GPIO irqs are in a different
431 * category than their parents, so it won't report false recursion.
432 */
433static struct lock_class_key gpio_lock_class;
434
435static int __init tegra_gpio_init(void)
436{
437 struct tegra_gpio_bank *bank;
438 int gpio;
439 int i;
440 int j;
441
442 for (i = 0; i < ARRAY_SIZE(tegra_gpio_banks); i++) {
443 for (j = 0; j < 4; j++) {
444 int gpio = tegra_gpio_compose(i, j, 0);
445 __raw_writel(0x00, GPIO_INT_ENB(gpio));
446 __raw_writel(0x00, GPIO_INT_STA(gpio));
447 }
448 }
449
450#ifdef CONFIG_OF_GPIO
451 /*
452 * This isn't ideal, but it gets things hooked up until this
453 * driver is converted into a platform_device
454 */
455 tegra_gpio_chip.of_node = of_find_compatible_node(NULL, NULL,
456 "nvidia,tegra20-gpio");
457#endif /* CONFIG_OF_GPIO */
458
459 gpiochip_add(&tegra_gpio_chip);
460
461 for (gpio = 0; gpio < TEGRA_NR_GPIOS; gpio++) {
462 int irq = TEGRA_GPIO_TO_IRQ(gpio);
463 /* No validity check; all Tegra GPIOs are valid IRQs */
464
465 bank = &tegra_gpio_banks[GPIO_BANK(gpio)];
466
467 irq_set_lockdep_class(irq, &gpio_lock_class);
468 irq_set_chip_data(irq, bank);
469 irq_set_chip_and_handler(irq, &tegra_gpio_irq_chip,
470 handle_simple_irq);
471 set_irq_flags(irq, IRQF_VALID);
472 }
473
474 for (i = 0; i < ARRAY_SIZE(tegra_gpio_banks); i++) {
475 bank = &tegra_gpio_banks[i];
476
477 for (j = 0; j < 4; j++)
478 spin_lock_init(&bank->lvl_lock[j]);
479
480 irq_set_handler_data(bank->irq, bank);
481 irq_set_chained_handler(bank->irq, tegra_gpio_irq_handler);
482
483 }
484
485 return 0;
486}
487
488postcore_initcall(tegra_gpio_init);
489
490void __init tegra_gpio_config(struct tegra_gpio_table *table, int num)
491{
492 int i;
493
494 for (i = 0; i < num; i++) {
495 int gpio = table[i].gpio;
496
497 if (table[i].enable)
498 tegra_gpio_enable(gpio);
499 else
500 tegra_gpio_disable(gpio);
501 }
502}
503
504#ifdef CONFIG_DEBUG_FS
505
506#include <linux/debugfs.h>
507#include <linux/seq_file.h>
508
509static int dbg_gpio_show(struct seq_file *s, void *unused)
510{
511 int i;
512 int j;
513
514 seq_printf(s, "Bank:Port CNF OE OUT IN INT_STA INT_ENB INT_LVL\n");
515 for (i = 0; i < ARRAY_SIZE(tegra_gpio_banks); i++) {
516 for (j = 0; j < 4; j++) {
517 int gpio = tegra_gpio_compose(i, j, 0);
518 seq_printf(s,
519 "%d:%d %02x %02x %02x %02x %02x %02x %06x\n",
520 i, j,
521 __raw_readl(GPIO_CNF(gpio)),
522 __raw_readl(GPIO_OE(gpio)),
523 __raw_readl(GPIO_OUT(gpio)),
524 __raw_readl(GPIO_IN(gpio)),
525 __raw_readl(GPIO_INT_STA(gpio)),
526 __raw_readl(GPIO_INT_ENB(gpio)),
527 __raw_readl(GPIO_INT_LVL(gpio)));
528 }
529 }
530 return 0;
531}
532
533static int dbg_gpio_open(struct inode *inode, struct file *file)
534{
535 return single_open(file, dbg_gpio_show, &inode->i_private);
536}
537
538static const struct file_operations debug_fops = {
539 .open = dbg_gpio_open,
540 .read = seq_read,
541 .llseek = seq_lseek,
542 .release = single_release,
543};
544
545static int __init tegra_gpio_debuginit(void)
546{
547 (void) debugfs_create_file("tegra_gpio", S_IRUGO,
548 NULL, NULL, &debug_fops);
549 return 0;
550}
551late_initcall(tegra_gpio_debuginit);
552#endif
generated by cgit v1.2.2 (git 2.25.0) at 2025-09-04 20:14:06 -0400