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path: root/drivers/gpio/gpio-omap.c
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Diffstat (limited to 'drivers/gpio/gpio-omap.c')
-rw-r--r--drivers/gpio/gpio-omap.c725
1 files changed, 154 insertions, 571 deletions
diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c
index 35bebde23e8..118ec12d2d5 100644
--- a/drivers/gpio/gpio-omap.c
+++ b/drivers/gpio/gpio-omap.c
@@ -34,8 +34,8 @@ struct gpio_bank {
34 u16 irq; 34 u16 irq;
35 u16 virtual_irq_start; 35 u16 virtual_irq_start;
36 int method; 36 int method;
37#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS)
38 u32 suspend_wakeup; 37 u32 suspend_wakeup;
38#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS)
39 u32 saved_wakeup; 39 u32 saved_wakeup;
40#endif 40#endif
41 u32 non_wakeup_gpios; 41 u32 non_wakeup_gpios;
@@ -54,6 +54,11 @@ struct gpio_bank {
54 struct device *dev; 54 struct device *dev;
55 bool dbck_flag; 55 bool dbck_flag;
56 int stride; 56 int stride;
57 u32 width;
58
59 void (*set_dataout)(struct gpio_bank *bank, int gpio, int enable);
60
61 struct omap_gpio_reg_offs *regs;
57}; 62};
58 63
59#ifdef CONFIG_ARCH_OMAP3 64#ifdef CONFIG_ARCH_OMAP3
@@ -79,121 +84,18 @@ static struct omap3_gpio_regs gpio_context[OMAP34XX_NR_GPIOS];
79 */ 84 */
80static struct gpio_bank *gpio_bank; 85static struct gpio_bank *gpio_bank;
81 86
82static int bank_width;
83
84/* TODO: Analyze removing gpio_bank_count usage from driver code */ 87/* TODO: Analyze removing gpio_bank_count usage from driver code */
85int gpio_bank_count; 88int gpio_bank_count;
86 89
87static inline struct gpio_bank *get_gpio_bank(int gpio) 90#define GPIO_INDEX(bank, gpio) (gpio % bank->width)
88{ 91#define GPIO_BIT(bank, gpio) (1 << GPIO_INDEX(bank, gpio))
89 if (cpu_is_omap15xx()) {
90 if (OMAP_GPIO_IS_MPUIO(gpio))
91 return &gpio_bank[0];
92 return &gpio_bank[1];
93 }
94 if (cpu_is_omap16xx()) {
95 if (OMAP_GPIO_IS_MPUIO(gpio))
96 return &gpio_bank[0];
97 return &gpio_bank[1 + (gpio >> 4)];
98 }
99 if (cpu_is_omap7xx()) {
100 if (OMAP_GPIO_IS_MPUIO(gpio))
101 return &gpio_bank[0];
102 return &gpio_bank[1 + (gpio >> 5)];
103 }
104 if (cpu_is_omap24xx())
105 return &gpio_bank[gpio >> 5];
106 if (cpu_is_omap34xx() || cpu_is_omap44xx())
107 return &gpio_bank[gpio >> 5];
108 BUG();
109 return NULL;
110}
111
112static inline int get_gpio_index(int gpio)
113{
114 if (cpu_is_omap7xx())
115 return gpio & 0x1f;
116 if (cpu_is_omap24xx())
117 return gpio & 0x1f;
118 if (cpu_is_omap34xx() || cpu_is_omap44xx())
119 return gpio & 0x1f;
120 return gpio & 0x0f;
121}
122
123static inline int gpio_valid(int gpio)
124{
125 if (gpio < 0)
126 return -1;
127 if (cpu_class_is_omap1() && OMAP_GPIO_IS_MPUIO(gpio)) {
128 if (gpio >= OMAP_MAX_GPIO_LINES + 16)
129 return -1;
130 return 0;
131 }
132 if (cpu_is_omap15xx() && gpio < 16)
133 return 0;
134 if ((cpu_is_omap16xx()) && gpio < 64)
135 return 0;
136 if (cpu_is_omap7xx() && gpio < 192)
137 return 0;
138 if (cpu_is_omap2420() && gpio < 128)
139 return 0;
140 if (cpu_is_omap2430() && gpio < 160)
141 return 0;
142 if ((cpu_is_omap34xx() || cpu_is_omap44xx()) && gpio < 192)
143 return 0;
144 return -1;
145}
146
147static int check_gpio(int gpio)
148{
149 if (unlikely(gpio_valid(gpio) < 0)) {
150 printk(KERN_ERR "omap-gpio: invalid GPIO %d\n", gpio);
151 dump_stack();
152 return -1;
153 }
154 return 0;
155}
156 92
157static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input) 93static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input)
158{ 94{
159 void __iomem *reg = bank->base; 95 void __iomem *reg = bank->base;
160 u32 l; 96 u32 l;
161 97
162 switch (bank->method) { 98 reg += bank->regs->direction;
163#ifdef CONFIG_ARCH_OMAP1
164 case METHOD_MPUIO:
165 reg += OMAP_MPUIO_IO_CNTL / bank->stride;
166 break;
167#endif
168#ifdef CONFIG_ARCH_OMAP15XX
169 case METHOD_GPIO_1510:
170 reg += OMAP1510_GPIO_DIR_CONTROL;
171 break;
172#endif
173#ifdef CONFIG_ARCH_OMAP16XX
174 case METHOD_GPIO_1610:
175 reg += OMAP1610_GPIO_DIRECTION;
176 break;
177#endif
178#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
179 case METHOD_GPIO_7XX:
180 reg += OMAP7XX_GPIO_DIR_CONTROL;
181 break;
182#endif
183#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
184 case METHOD_GPIO_24XX:
185 reg += OMAP24XX_GPIO_OE;
186 break;
187#endif
188#if defined(CONFIG_ARCH_OMAP4)
189 case METHOD_GPIO_44XX:
190 reg += OMAP4_GPIO_OE;
191 break;
192#endif
193 default:
194 WARN_ON(1);
195 return;
196 }
197 l = __raw_readl(reg); 99 l = __raw_readl(reg);
198 if (is_input) 100 if (is_input)
199 l |= 1 << gpio; 101 l |= 1 << gpio;
@@ -202,165 +104,48 @@ static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input)
202 __raw_writel(l, reg); 104 __raw_writel(l, reg);
203} 105}
204 106
205static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable) 107
108/* set data out value using dedicate set/clear register */
109static void _set_gpio_dataout_reg(struct gpio_bank *bank, int gpio, int enable)
206{ 110{
207 void __iomem *reg = bank->base; 111 void __iomem *reg = bank->base;
208 u32 l = 0; 112 u32 l = GPIO_BIT(bank, gpio);
113
114 if (enable)
115 reg += bank->regs->set_dataout;
116 else
117 reg += bank->regs->clr_dataout;
209 118
210 switch (bank->method) {
211#ifdef CONFIG_ARCH_OMAP1
212 case METHOD_MPUIO:
213 reg += OMAP_MPUIO_OUTPUT / bank->stride;
214 l = __raw_readl(reg);
215 if (enable)
216 l |= 1 << gpio;
217 else
218 l &= ~(1 << gpio);
219 break;
220#endif
221#ifdef CONFIG_ARCH_OMAP15XX
222 case METHOD_GPIO_1510:
223 reg += OMAP1510_GPIO_DATA_OUTPUT;
224 l = __raw_readl(reg);
225 if (enable)
226 l |= 1 << gpio;
227 else
228 l &= ~(1 << gpio);
229 break;
230#endif
231#ifdef CONFIG_ARCH_OMAP16XX
232 case METHOD_GPIO_1610:
233 if (enable)
234 reg += OMAP1610_GPIO_SET_DATAOUT;
235 else
236 reg += OMAP1610_GPIO_CLEAR_DATAOUT;
237 l = 1 << gpio;
238 break;
239#endif
240#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
241 case METHOD_GPIO_7XX:
242 reg += OMAP7XX_GPIO_DATA_OUTPUT;
243 l = __raw_readl(reg);
244 if (enable)
245 l |= 1 << gpio;
246 else
247 l &= ~(1 << gpio);
248 break;
249#endif
250#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
251 case METHOD_GPIO_24XX:
252 if (enable)
253 reg += OMAP24XX_GPIO_SETDATAOUT;
254 else
255 reg += OMAP24XX_GPIO_CLEARDATAOUT;
256 l = 1 << gpio;
257 break;
258#endif
259#ifdef CONFIG_ARCH_OMAP4
260 case METHOD_GPIO_44XX:
261 if (enable)
262 reg += OMAP4_GPIO_SETDATAOUT;
263 else
264 reg += OMAP4_GPIO_CLEARDATAOUT;
265 l = 1 << gpio;
266 break;
267#endif
268 default:
269 WARN_ON(1);
270 return;
271 }
272 __raw_writel(l, reg); 119 __raw_writel(l, reg);
273} 120}
274 121
275static int _get_gpio_datain(struct gpio_bank *bank, int gpio) 122/* set data out value using mask register */
123static void _set_gpio_dataout_mask(struct gpio_bank *bank, int gpio, int enable)
276{ 124{
277 void __iomem *reg; 125 void __iomem *reg = bank->base + bank->regs->dataout;
126 u32 gpio_bit = GPIO_BIT(bank, gpio);
127 u32 l;
278 128
279 if (check_gpio(gpio) < 0) 129 l = __raw_readl(reg);
280 return -EINVAL; 130 if (enable)
281 reg = bank->base; 131 l |= gpio_bit;
282 switch (bank->method) { 132 else
283#ifdef CONFIG_ARCH_OMAP1 133 l &= ~gpio_bit;
284 case METHOD_MPUIO: 134 __raw_writel(l, reg);
285 reg += OMAP_MPUIO_INPUT_LATCH / bank->stride;
286 break;
287#endif
288#ifdef CONFIG_ARCH_OMAP15XX
289 case METHOD_GPIO_1510:
290 reg += OMAP1510_GPIO_DATA_INPUT;
291 break;
292#endif
293#ifdef CONFIG_ARCH_OMAP16XX
294 case METHOD_GPIO_1610:
295 reg += OMAP1610_GPIO_DATAIN;
296 break;
297#endif
298#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
299 case METHOD_GPIO_7XX:
300 reg += OMAP7XX_GPIO_DATA_INPUT;
301 break;
302#endif
303#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
304 case METHOD_GPIO_24XX:
305 reg += OMAP24XX_GPIO_DATAIN;
306 break;
307#endif
308#ifdef CONFIG_ARCH_OMAP4
309 case METHOD_GPIO_44XX:
310 reg += OMAP4_GPIO_DATAIN;
311 break;
312#endif
313 default:
314 return -EINVAL;
315 }
316 return (__raw_readl(reg)
317 & (1 << get_gpio_index(gpio))) != 0;
318} 135}
319 136
320static int _get_gpio_dataout(struct gpio_bank *bank, int gpio) 137static int _get_gpio_datain(struct gpio_bank *bank, int gpio)
321{ 138{
322 void __iomem *reg; 139 void __iomem *reg = bank->base + bank->regs->datain;
323 140
324 if (check_gpio(gpio) < 0) 141 return (__raw_readl(reg) & GPIO_BIT(bank, gpio)) != 0;
325 return -EINVAL; 142}
326 reg = bank->base;
327 143
328 switch (bank->method) { 144static int _get_gpio_dataout(struct gpio_bank *bank, int gpio)
329#ifdef CONFIG_ARCH_OMAP1 145{
330 case METHOD_MPUIO: 146 void __iomem *reg = bank->base + bank->regs->dataout;
331 reg += OMAP_MPUIO_OUTPUT / bank->stride;
332 break;
333#endif
334#ifdef CONFIG_ARCH_OMAP15XX
335 case METHOD_GPIO_1510:
336 reg += OMAP1510_GPIO_DATA_OUTPUT;
337 break;
338#endif
339#ifdef CONFIG_ARCH_OMAP16XX
340 case METHOD_GPIO_1610:
341 reg += OMAP1610_GPIO_DATAOUT;
342 break;
343#endif
344#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
345 case METHOD_GPIO_7XX:
346 reg += OMAP7XX_GPIO_DATA_OUTPUT;
347 break;
348#endif
349#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
350 case METHOD_GPIO_24XX:
351 reg += OMAP24XX_GPIO_DATAOUT;
352 break;
353#endif
354#ifdef CONFIG_ARCH_OMAP4
355 case METHOD_GPIO_44XX:
356 reg += OMAP4_GPIO_DATAOUT;
357 break;
358#endif
359 default:
360 return -EINVAL;
361 }
362 147
363 return (__raw_readl(reg) & (1 << get_gpio_index(gpio))) != 0; 148 return (__raw_readl(reg) & GPIO_BIT(bank, gpio)) != 0;
364} 149}
365 150
366#define MOD_REG_BIT(reg, bit_mask, set) \ 151#define MOD_REG_BIT(reg, bit_mask, set) \
@@ -383,7 +168,7 @@ do { \
383static void _set_gpio_debounce(struct gpio_bank *bank, unsigned gpio, 168static void _set_gpio_debounce(struct gpio_bank *bank, unsigned gpio,
384 unsigned debounce) 169 unsigned debounce)
385{ 170{
386 void __iomem *reg = bank->base; 171 void __iomem *reg;
387 u32 val; 172 u32 val;
388 u32 l; 173 u32 l;
389 174
@@ -397,21 +182,12 @@ static void _set_gpio_debounce(struct gpio_bank *bank, unsigned gpio,
397 else 182 else
398 debounce = (debounce / 0x1f) - 1; 183 debounce = (debounce / 0x1f) - 1;
399 184
400 l = 1 << get_gpio_index(gpio); 185 l = GPIO_BIT(bank, gpio);
401
402 if (bank->method == METHOD_GPIO_44XX)
403 reg += OMAP4_GPIO_DEBOUNCINGTIME;
404 else
405 reg += OMAP24XX_GPIO_DEBOUNCE_VAL;
406 186
187 reg = bank->base + bank->regs->debounce;
407 __raw_writel(debounce, reg); 188 __raw_writel(debounce, reg);
408 189
409 reg = bank->base; 190 reg = bank->base + bank->regs->debounce_en;
410 if (bank->method == METHOD_GPIO_44XX)
411 reg += OMAP4_GPIO_DEBOUNCENABLE;
412 else
413 reg += OMAP24XX_GPIO_DEBOUNCE_EN;
414
415 val = __raw_readl(reg); 191 val = __raw_readl(reg);
416 192
417 if (debounce) { 193 if (debounce) {
@@ -629,9 +405,6 @@ static int gpio_irq_type(struct irq_data *d, unsigned type)
629 else 405 else
630 gpio = d->irq - IH_GPIO_BASE; 406 gpio = d->irq - IH_GPIO_BASE;
631 407
632 if (check_gpio(gpio) < 0)
633 return -EINVAL;
634
635 if (type & ~IRQ_TYPE_SENSE_MASK) 408 if (type & ~IRQ_TYPE_SENSE_MASK)
636 return -EINVAL; 409 return -EINVAL;
637 410
@@ -642,7 +415,7 @@ static int gpio_irq_type(struct irq_data *d, unsigned type)
642 415
643 bank = irq_data_get_irq_chip_data(d); 416 bank = irq_data_get_irq_chip_data(d);
644 spin_lock_irqsave(&bank->lock, flags); 417 spin_lock_irqsave(&bank->lock, flags);
645 retval = _set_gpio_triggering(bank, get_gpio_index(gpio), type); 418 retval = _set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), type);
646 spin_unlock_irqrestore(&bank->lock, flags); 419 spin_unlock_irqrestore(&bank->lock, flags);
647 420
648 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) 421 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
@@ -657,195 +430,81 @@ static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
657{ 430{
658 void __iomem *reg = bank->base; 431 void __iomem *reg = bank->base;
659 432
660 switch (bank->method) { 433 reg += bank->regs->irqstatus;
661#ifdef CONFIG_ARCH_OMAP1
662 case METHOD_MPUIO:
663 /* MPUIO irqstatus is reset by reading the status register,
664 * so do nothing here */
665 return;
666#endif
667#ifdef CONFIG_ARCH_OMAP15XX
668 case METHOD_GPIO_1510:
669 reg += OMAP1510_GPIO_INT_STATUS;
670 break;
671#endif
672#ifdef CONFIG_ARCH_OMAP16XX
673 case METHOD_GPIO_1610:
674 reg += OMAP1610_GPIO_IRQSTATUS1;
675 break;
676#endif
677#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
678 case METHOD_GPIO_7XX:
679 reg += OMAP7XX_GPIO_INT_STATUS;
680 break;
681#endif
682#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
683 case METHOD_GPIO_24XX:
684 reg += OMAP24XX_GPIO_IRQSTATUS1;
685 break;
686#endif
687#if defined(CONFIG_ARCH_OMAP4)
688 case METHOD_GPIO_44XX:
689 reg += OMAP4_GPIO_IRQSTATUS0;
690 break;
691#endif
692 default:
693 WARN_ON(1);
694 return;
695 }
696 __raw_writel(gpio_mask, reg); 434 __raw_writel(gpio_mask, reg);
697 435
698 /* Workaround for clearing DSP GPIO interrupts to allow retention */ 436 /* Workaround for clearing DSP GPIO interrupts to allow retention */
699 if (cpu_is_omap24xx() || cpu_is_omap34xx()) 437 if (bank->regs->irqstatus2) {
700 reg = bank->base + OMAP24XX_GPIO_IRQSTATUS2; 438 reg = bank->base + bank->regs->irqstatus2;
701 else if (cpu_is_omap44xx())
702 reg = bank->base + OMAP4_GPIO_IRQSTATUS1;
703
704 if (cpu_is_omap24xx() || cpu_is_omap34xx() || cpu_is_omap44xx()) {
705 __raw_writel(gpio_mask, reg); 439 __raw_writel(gpio_mask, reg);
440 }
706 441
707 /* Flush posted write for the irq status to avoid spurious interrupts */ 442 /* Flush posted write for the irq status to avoid spurious interrupts */
708 __raw_readl(reg); 443 __raw_readl(reg);
709 }
710} 444}
711 445
712static inline void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio) 446static inline void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio)
713{ 447{
714 _clear_gpio_irqbank(bank, 1 << get_gpio_index(gpio)); 448 _clear_gpio_irqbank(bank, GPIO_BIT(bank, gpio));
715} 449}
716 450
717static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank) 451static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank)
718{ 452{
719 void __iomem *reg = bank->base; 453 void __iomem *reg = bank->base;
720 int inv = 0;
721 u32 l; 454 u32 l;
722 u32 mask; 455 u32 mask = (1 << bank->width) - 1;
723
724 switch (bank->method) {
725#ifdef CONFIG_ARCH_OMAP1
726 case METHOD_MPUIO:
727 reg += OMAP_MPUIO_GPIO_MASKIT / bank->stride;
728 mask = 0xffff;
729 inv = 1;
730 break;
731#endif
732#ifdef CONFIG_ARCH_OMAP15XX
733 case METHOD_GPIO_1510:
734 reg += OMAP1510_GPIO_INT_MASK;
735 mask = 0xffff;
736 inv = 1;
737 break;
738#endif
739#ifdef CONFIG_ARCH_OMAP16XX
740 case METHOD_GPIO_1610:
741 reg += OMAP1610_GPIO_IRQENABLE1;
742 mask = 0xffff;
743 break;
744#endif
745#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
746 case METHOD_GPIO_7XX:
747 reg += OMAP7XX_GPIO_INT_MASK;
748 mask = 0xffffffff;
749 inv = 1;
750 break;
751#endif
752#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
753 case METHOD_GPIO_24XX:
754 reg += OMAP24XX_GPIO_IRQENABLE1;
755 mask = 0xffffffff;
756 break;
757#endif
758#if defined(CONFIG_ARCH_OMAP4)
759 case METHOD_GPIO_44XX:
760 reg += OMAP4_GPIO_IRQSTATUSSET0;
761 mask = 0xffffffff;
762 break;
763#endif
764 default:
765 WARN_ON(1);
766 return 0;
767 }
768 456
457 reg += bank->regs->irqenable;
769 l = __raw_readl(reg); 458 l = __raw_readl(reg);
770 if (inv) 459 if (bank->regs->irqenable_inv)
771 l = ~l; 460 l = ~l;
772 l &= mask; 461 l &= mask;
773 return l; 462 return l;
774} 463}
775 464
776static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask, int enable) 465static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
777{ 466{
778 void __iomem *reg = bank->base; 467 void __iomem *reg = bank->base;
779 u32 l; 468 u32 l;
780 469
781 switch (bank->method) { 470 if (bank->regs->set_irqenable) {
782#ifdef CONFIG_ARCH_OMAP1 471 reg += bank->regs->set_irqenable;
783 case METHOD_MPUIO: 472 l = gpio_mask;
784 reg += OMAP_MPUIO_GPIO_MASKIT / bank->stride; 473 } else {
785 l = __raw_readl(reg); 474 reg += bank->regs->irqenable;
786 if (enable)
787 l &= ~(gpio_mask);
788 else
789 l |= gpio_mask;
790 break;
791#endif
792#ifdef CONFIG_ARCH_OMAP15XX
793 case METHOD_GPIO_1510:
794 reg += OMAP1510_GPIO_INT_MASK;
795 l = __raw_readl(reg); 475 l = __raw_readl(reg);
796 if (enable) 476 if (bank->regs->irqenable_inv)
797 l &= ~(gpio_mask); 477 l &= ~gpio_mask;
798 else 478 else
799 l |= gpio_mask; 479 l |= gpio_mask;
800 break; 480 }
801#endif 481
802#ifdef CONFIG_ARCH_OMAP16XX 482 __raw_writel(l, reg);
803 case METHOD_GPIO_1610: 483}
804 if (enable) 484
805 reg += OMAP1610_GPIO_SET_IRQENABLE1; 485static void _disable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
806 else 486{
807 reg += OMAP1610_GPIO_CLEAR_IRQENABLE1; 487 void __iomem *reg = bank->base;
488 u32 l;
489
490 if (bank->regs->clr_irqenable) {
491 reg += bank->regs->clr_irqenable;
808 l = gpio_mask; 492 l = gpio_mask;
809 break; 493 } else {
810#endif 494 reg += bank->regs->irqenable;
811#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
812 case METHOD_GPIO_7XX:
813 reg += OMAP7XX_GPIO_INT_MASK;
814 l = __raw_readl(reg); 495 l = __raw_readl(reg);
815 if (enable) 496 if (bank->regs->irqenable_inv)
816 l &= ~(gpio_mask);
817 else
818 l |= gpio_mask; 497 l |= gpio_mask;
819 break;
820#endif
821#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
822 case METHOD_GPIO_24XX:
823 if (enable)
824 reg += OMAP24XX_GPIO_SETIRQENABLE1;
825 else
826 reg += OMAP24XX_GPIO_CLEARIRQENABLE1;
827 l = gpio_mask;
828 break;
829#endif
830#ifdef CONFIG_ARCH_OMAP4
831 case METHOD_GPIO_44XX:
832 if (enable)
833 reg += OMAP4_GPIO_IRQSTATUSSET0;
834 else 498 else
835 reg += OMAP4_GPIO_IRQSTATUSCLR0; 499 l &= ~gpio_mask;
836 l = gpio_mask;
837 break;
838#endif
839 default:
840 WARN_ON(1);
841 return;
842 } 500 }
501
843 __raw_writel(l, reg); 502 __raw_writel(l, reg);
844} 503}
845 504
846static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable) 505static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable)
847{ 506{
848 _enable_gpio_irqbank(bank, 1 << get_gpio_index(gpio), enable); 507 _enable_gpio_irqbank(bank, GPIO_BIT(bank, gpio));
849} 508}
850 509
851/* 510/*
@@ -858,50 +517,32 @@ static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int ena
858 */ 517 */
859static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable) 518static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable)
860{ 519{
861 unsigned long uninitialized_var(flags); 520 u32 gpio_bit = GPIO_BIT(bank, gpio);
521 unsigned long flags;
862 522
863 switch (bank->method) { 523 if (bank->non_wakeup_gpios & gpio_bit) {
864#ifdef CONFIG_ARCH_OMAP16XX 524 dev_err(bank->dev,
865 case METHOD_MPUIO: 525 "Unable to modify wakeup on non-wakeup GPIO%d\n", gpio);
866 case METHOD_GPIO_1610:
867 spin_lock_irqsave(&bank->lock, flags);
868 if (enable)
869 bank->suspend_wakeup |= (1 << gpio);
870 else
871 bank->suspend_wakeup &= ~(1 << gpio);
872 spin_unlock_irqrestore(&bank->lock, flags);
873 return 0;
874#endif
875#ifdef CONFIG_ARCH_OMAP2PLUS
876 case METHOD_GPIO_24XX:
877 case METHOD_GPIO_44XX:
878 if (bank->non_wakeup_gpios & (1 << gpio)) {
879 printk(KERN_ERR "Unable to modify wakeup on "
880 "non-wakeup GPIO%d\n",
881 (bank - gpio_bank) * 32 + gpio);
882 return -EINVAL;
883 }
884 spin_lock_irqsave(&bank->lock, flags);
885 if (enable)
886 bank->suspend_wakeup |= (1 << gpio);
887 else
888 bank->suspend_wakeup &= ~(1 << gpio);
889 spin_unlock_irqrestore(&bank->lock, flags);
890 return 0;
891#endif
892 default:
893 printk(KERN_ERR "Can't enable GPIO wakeup for method %i\n",
894 bank->method);
895 return -EINVAL; 526 return -EINVAL;
896 } 527 }
528
529 spin_lock_irqsave(&bank->lock, flags);
530 if (enable)
531 bank->suspend_wakeup |= gpio_bit;
532 else
533 bank->suspend_wakeup &= ~gpio_bit;
534
535 spin_unlock_irqrestore(&bank->lock, flags);
536
537 return 0;
897} 538}
898 539
899static void _reset_gpio(struct gpio_bank *bank, int gpio) 540static void _reset_gpio(struct gpio_bank *bank, int gpio)
900{ 541{
901 _set_gpio_direction(bank, get_gpio_index(gpio), 1); 542 _set_gpio_direction(bank, GPIO_INDEX(bank, gpio), 1);
902 _set_gpio_irqenable(bank, gpio, 0); 543 _set_gpio_irqenable(bank, gpio, 0);
903 _clear_gpio_irqstatus(bank, gpio); 544 _clear_gpio_irqstatus(bank, gpio);
904 _set_gpio_triggering(bank, get_gpio_index(gpio), IRQ_TYPE_NONE); 545 _set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), IRQ_TYPE_NONE);
905} 546}
906 547
907/* Use disable_irq_wake() and enable_irq_wake() functions from drivers */ 548/* Use disable_irq_wake() and enable_irq_wake() functions from drivers */
@@ -911,10 +552,8 @@ static int gpio_wake_enable(struct irq_data *d, unsigned int enable)
911 struct gpio_bank *bank; 552 struct gpio_bank *bank;
912 int retval; 553 int retval;
913 554
914 if (check_gpio(gpio) < 0)
915 return -ENODEV;
916 bank = irq_data_get_irq_chip_data(d); 555 bank = irq_data_get_irq_chip_data(d);
917 retval = _set_gpio_wakeup(bank, get_gpio_index(gpio), enable); 556 retval = _set_gpio_wakeup(bank, gpio, enable);
918 557
919 return retval; 558 return retval;
920} 559}
@@ -1030,31 +669,7 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
1030 chained_irq_enter(chip, desc); 669 chained_irq_enter(chip, desc);
1031 670
1032 bank = irq_get_handler_data(irq); 671 bank = irq_get_handler_data(irq);
1033#ifdef CONFIG_ARCH_OMAP1 672 isr_reg = bank->base + bank->regs->irqstatus;
1034 if (bank->method == METHOD_MPUIO)
1035 isr_reg = bank->base +
1036 OMAP_MPUIO_GPIO_INT / bank->stride;
1037#endif
1038#ifdef CONFIG_ARCH_OMAP15XX
1039 if (bank->method == METHOD_GPIO_1510)
1040 isr_reg = bank->base + OMAP1510_GPIO_INT_STATUS;
1041#endif
1042#if defined(CONFIG_ARCH_OMAP16XX)
1043 if (bank->method == METHOD_GPIO_1610)
1044 isr_reg = bank->base + OMAP1610_GPIO_IRQSTATUS1;
1045#endif
1046#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
1047 if (bank->method == METHOD_GPIO_7XX)
1048 isr_reg = bank->base + OMAP7XX_GPIO_INT_STATUS;
1049#endif
1050#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
1051 if (bank->method == METHOD_GPIO_24XX)
1052 isr_reg = bank->base + OMAP24XX_GPIO_IRQSTATUS1;
1053#endif
1054#if defined(CONFIG_ARCH_OMAP4)
1055 if (bank->method == METHOD_GPIO_44XX)
1056 isr_reg = bank->base + OMAP4_GPIO_IRQSTATUS0;
1057#endif
1058 673
1059 if (WARN_ON(!isr_reg)) 674 if (WARN_ON(!isr_reg))
1060 goto exit; 675 goto exit;
@@ -1076,9 +691,9 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
1076 /* clear edge sensitive interrupts before handler(s) are 691 /* clear edge sensitive interrupts before handler(s) are
1077 called so that we don't miss any interrupt occurred while 692 called so that we don't miss any interrupt occurred while
1078 executing them */ 693 executing them */
1079 _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 0); 694 _disable_gpio_irqbank(bank, isr_saved & ~level_mask);
1080 _clear_gpio_irqbank(bank, isr_saved & ~level_mask); 695 _clear_gpio_irqbank(bank, isr_saved & ~level_mask);
1081 _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 1); 696 _enable_gpio_irqbank(bank, isr_saved & ~level_mask);
1082 697
1083 /* if there is only edge sensitive GPIO pin interrupts 698 /* if there is only edge sensitive GPIO pin interrupts
1084 configured, we could unmask GPIO bank interrupt immediately */ 699 configured, we could unmask GPIO bank interrupt immediately */
@@ -1094,7 +709,7 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
1094 709
1095 gpio_irq = bank->virtual_irq_start; 710 gpio_irq = bank->virtual_irq_start;
1096 for (; isr != 0; isr >>= 1, gpio_irq++) { 711 for (; isr != 0; isr >>= 1, gpio_irq++) {
1097 gpio_index = get_gpio_index(irq_to_gpio(gpio_irq)); 712 gpio_index = GPIO_INDEX(bank, irq_to_gpio(gpio_irq));
1098 713
1099 if (!(isr & 1)) 714 if (!(isr & 1))
1100 continue; 715 continue;
@@ -1150,7 +765,7 @@ static void gpio_mask_irq(struct irq_data *d)
1150 765
1151 spin_lock_irqsave(&bank->lock, flags); 766 spin_lock_irqsave(&bank->lock, flags);
1152 _set_gpio_irqenable(bank, gpio, 0); 767 _set_gpio_irqenable(bank, gpio, 0);
1153 _set_gpio_triggering(bank, get_gpio_index(gpio), IRQ_TYPE_NONE); 768 _set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), IRQ_TYPE_NONE);
1154 spin_unlock_irqrestore(&bank->lock, flags); 769 spin_unlock_irqrestore(&bank->lock, flags);
1155} 770}
1156 771
@@ -1158,13 +773,13 @@ static void gpio_unmask_irq(struct irq_data *d)
1158{ 773{
1159 unsigned int gpio = d->irq - IH_GPIO_BASE; 774 unsigned int gpio = d->irq - IH_GPIO_BASE;
1160 struct gpio_bank *bank = irq_data_get_irq_chip_data(d); 775 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
1161 unsigned int irq_mask = 1 << get_gpio_index(gpio); 776 unsigned int irq_mask = GPIO_BIT(bank, gpio);
1162 u32 trigger = irqd_get_trigger_type(d); 777 u32 trigger = irqd_get_trigger_type(d);
1163 unsigned long flags; 778 unsigned long flags;
1164 779
1165 spin_lock_irqsave(&bank->lock, flags); 780 spin_lock_irqsave(&bank->lock, flags);
1166 if (trigger) 781 if (trigger)
1167 _set_gpio_triggering(bank, get_gpio_index(gpio), trigger); 782 _set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), trigger);
1168 783
1169 /* For level-triggered GPIOs, the clearing must be done after 784 /* For level-triggered GPIOs, the clearing must be done after
1170 * the HW source is cleared, thus after the handler has run */ 785 * the HW source is cleared, thus after the handler has run */
@@ -1191,45 +806,8 @@ static struct irq_chip gpio_irq_chip = {
1191 806
1192#ifdef CONFIG_ARCH_OMAP1 807#ifdef CONFIG_ARCH_OMAP1
1193 808
1194/* MPUIO uses the always-on 32k clock */
1195
1196static void mpuio_ack_irq(struct irq_data *d)
1197{
1198 /* The ISR is reset automatically, so do nothing here. */
1199}
1200
1201static void mpuio_mask_irq(struct irq_data *d)
1202{
1203 unsigned int gpio = OMAP_MPUIO(d->irq - IH_MPUIO_BASE);
1204 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
1205
1206 _set_gpio_irqenable(bank, gpio, 0);
1207}
1208
1209static void mpuio_unmask_irq(struct irq_data *d)
1210{
1211 unsigned int gpio = OMAP_MPUIO(d->irq - IH_MPUIO_BASE);
1212 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
1213
1214 _set_gpio_irqenable(bank, gpio, 1);
1215}
1216
1217static struct irq_chip mpuio_irq_chip = {
1218 .name = "MPUIO",
1219 .irq_ack = mpuio_ack_irq,
1220 .irq_mask = mpuio_mask_irq,
1221 .irq_unmask = mpuio_unmask_irq,
1222 .irq_set_type = gpio_irq_type,
1223#ifdef CONFIG_ARCH_OMAP16XX
1224 /* REVISIT: assuming only 16xx supports MPUIO wake events */
1225 .irq_set_wake = gpio_wake_enable,
1226#endif
1227};
1228
1229
1230#define bank_is_mpuio(bank) ((bank)->method == METHOD_MPUIO) 809#define bank_is_mpuio(bank) ((bank)->method == METHOD_MPUIO)
1231 810
1232
1233#ifdef CONFIG_ARCH_OMAP16XX 811#ifdef CONFIG_ARCH_OMAP16XX
1234 812
1235#include <linux/platform_device.h> 813#include <linux/platform_device.h>
@@ -1289,7 +867,7 @@ static struct platform_device omap_mpuio_device = {
1289 867
1290static inline void mpuio_init(void) 868static inline void mpuio_init(void)
1291{ 869{
1292 struct gpio_bank *bank = get_gpio_bank(OMAP_MPUIO(0)); 870 struct gpio_bank *bank = &gpio_bank[0];
1293 platform_set_drvdata(&omap_mpuio_device, bank); 871 platform_set_drvdata(&omap_mpuio_device, bank);
1294 872
1295 if (platform_driver_register(&omap_mpuio_driver) == 0) 873 if (platform_driver_register(&omap_mpuio_driver) == 0)
@@ -1302,8 +880,6 @@ static inline void mpuio_init(void) {}
1302 880
1303#else 881#else
1304 882
1305extern struct irq_chip mpuio_irq_chip;
1306
1307#define bank_is_mpuio(bank) 0 883#define bank_is_mpuio(bank) 0
1308static inline void mpuio_init(void) {} 884static inline void mpuio_init(void) {}
1309 885
@@ -1329,31 +905,8 @@ static int gpio_input(struct gpio_chip *chip, unsigned offset)
1329 905
1330static int gpio_is_input(struct gpio_bank *bank, int mask) 906static int gpio_is_input(struct gpio_bank *bank, int mask)
1331{ 907{
1332 void __iomem *reg = bank->base; 908 void __iomem *reg = bank->base + bank->regs->direction;
1333 909
1334 switch (bank->method) {
1335 case METHOD_MPUIO:
1336 reg += OMAP_MPUIO_IO_CNTL / bank->stride;
1337 break;
1338 case METHOD_GPIO_1510:
1339 reg += OMAP1510_GPIO_DIR_CONTROL;
1340 break;
1341 case METHOD_GPIO_1610:
1342 reg += OMAP1610_GPIO_DIRECTION;
1343 break;
1344 case METHOD_GPIO_7XX:
1345 reg += OMAP7XX_GPIO_DIR_CONTROL;
1346 break;
1347 case METHOD_GPIO_24XX:
1348 reg += OMAP24XX_GPIO_OE;
1349 break;
1350 case METHOD_GPIO_44XX:
1351 reg += OMAP4_GPIO_OE;
1352 break;
1353 default:
1354 WARN_ONCE(1, "gpio_is_input: incorrect OMAP GPIO method");
1355 return -EINVAL;
1356 }
1357 return __raw_readl(reg) & mask; 910 return __raw_readl(reg) & mask;
1358} 911}
1359 912
@@ -1365,9 +918,9 @@ static int gpio_get(struct gpio_chip *chip, unsigned offset)
1365 u32 mask; 918 u32 mask;
1366 919
1367 gpio = chip->base + offset; 920 gpio = chip->base + offset;
1368 bank = get_gpio_bank(gpio); 921 bank = container_of(chip, struct gpio_bank, chip);
1369 reg = bank->base; 922 reg = bank->base;
1370 mask = 1 << get_gpio_index(gpio); 923 mask = GPIO_BIT(bank, gpio);
1371 924
1372 if (gpio_is_input(bank, mask)) 925 if (gpio_is_input(bank, mask))
1373 return _get_gpio_datain(bank, gpio); 926 return _get_gpio_datain(bank, gpio);
@@ -1382,7 +935,7 @@ static int gpio_output(struct gpio_chip *chip, unsigned offset, int value)
1382 935
1383 bank = container_of(chip, struct gpio_bank, chip); 936 bank = container_of(chip, struct gpio_bank, chip);
1384 spin_lock_irqsave(&bank->lock, flags); 937 spin_lock_irqsave(&bank->lock, flags);
1385 _set_gpio_dataout(bank, offset, value); 938 bank->set_dataout(bank, offset, value);
1386 _set_gpio_direction(bank, offset, 0); 939 _set_gpio_direction(bank, offset, 0);
1387 spin_unlock_irqrestore(&bank->lock, flags); 940 spin_unlock_irqrestore(&bank->lock, flags);
1388 return 0; 941 return 0;
@@ -1416,7 +969,7 @@ static void gpio_set(struct gpio_chip *chip, unsigned offset, int value)
1416 969
1417 bank = container_of(chip, struct gpio_bank, chip); 970 bank = container_of(chip, struct gpio_bank, chip);
1418 spin_lock_irqsave(&bank->lock, flags); 971 spin_lock_irqsave(&bank->lock, flags);
1419 _set_gpio_dataout(bank, offset, value); 972 bank->set_dataout(bank, offset, value);
1420 spin_unlock_irqrestore(&bank->lock, flags); 973 spin_unlock_irqrestore(&bank->lock, flags);
1421} 974}
1422 975
@@ -1432,19 +985,17 @@ static int gpio_2irq(struct gpio_chip *chip, unsigned offset)
1432 985
1433static void __init omap_gpio_show_rev(struct gpio_bank *bank) 986static void __init omap_gpio_show_rev(struct gpio_bank *bank)
1434{ 987{
988 static bool called;
1435 u32 rev; 989 u32 rev;
1436 990
1437 if (cpu_is_omap16xx() && !(bank->method != METHOD_MPUIO)) 991 if (called || bank->regs->revision == USHRT_MAX)
1438 rev = __raw_readw(bank->base + OMAP1610_GPIO_REVISION);
1439 else if (cpu_is_omap24xx() || cpu_is_omap34xx())
1440 rev = __raw_readl(bank->base + OMAP24XX_GPIO_REVISION);
1441 else if (cpu_is_omap44xx())
1442 rev = __raw_readl(bank->base + OMAP4_GPIO_REVISION);
1443 else
1444 return; 992 return;
1445 993
1446 printk(KERN_INFO "OMAP GPIO hardware version %d.%d\n", 994 rev = __raw_readw(bank->base + bank->regs->revision);
995 pr_info("OMAP GPIO hardware version %d.%d\n",
1447 (rev >> 4) & 0x0f, rev & 0x0f); 996 (rev >> 4) & 0x0f, rev & 0x0f);
997
998 called = true;
1448} 999}
1449 1000
1450/* This lock class tells lockdep that GPIO irqs are in a different 1001/* This lock class tells lockdep that GPIO irqs are in a different
@@ -1526,6 +1077,30 @@ static void omap_gpio_mod_init(struct gpio_bank *bank, int id)
1526 } 1077 }
1527} 1078}
1528 1079
1080static __init void
1081omap_mpuio_alloc_gc(struct gpio_bank *bank, unsigned int irq_start,
1082 unsigned int num)
1083{
1084 struct irq_chip_generic *gc;
1085 struct irq_chip_type *ct;
1086
1087 gc = irq_alloc_generic_chip("MPUIO", 1, irq_start, bank->base,
1088 handle_simple_irq);
1089 ct = gc->chip_types;
1090
1091 /* NOTE: No ack required, reading IRQ status clears it. */
1092 ct->chip.irq_mask = irq_gc_mask_set_bit;
1093 ct->chip.irq_unmask = irq_gc_mask_clr_bit;
1094 ct->chip.irq_set_type = gpio_irq_type;
1095 /* REVISIT: assuming only 16xx supports MPUIO wake events */
1096 if (cpu_is_omap16xx())
1097 ct->chip.irq_set_wake = gpio_wake_enable,
1098
1099 ct->regs.mask = OMAP_MPUIO_GPIO_INT / bank->stride;
1100 irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE,
1101 IRQ_NOREQUEST | IRQ_NOPROBE, 0);
1102}
1103
1529static void __devinit omap_gpio_chip_init(struct gpio_bank *bank) 1104static void __devinit omap_gpio_chip_init(struct gpio_bank *bank)
1530{ 1105{
1531 int j; 1106 int j;
@@ -1553,22 +1128,23 @@ static void __devinit omap_gpio_chip_init(struct gpio_bank *bank)
1553 } else { 1128 } else {
1554 bank->chip.label = "gpio"; 1129 bank->chip.label = "gpio";
1555 bank->chip.base = gpio; 1130 bank->chip.base = gpio;
1556 gpio += bank_width; 1131 gpio += bank->width;
1557 } 1132 }
1558 bank->chip.ngpio = bank_width; 1133 bank->chip.ngpio = bank->width;
1559 1134
1560 gpiochip_add(&bank->chip); 1135 gpiochip_add(&bank->chip);
1561 1136
1562 for (j = bank->virtual_irq_start; 1137 for (j = bank->virtual_irq_start;
1563 j < bank->virtual_irq_start + bank_width; j++) { 1138 j < bank->virtual_irq_start + bank->width; j++) {
1564 irq_set_lockdep_class(j, &gpio_lock_class); 1139 irq_set_lockdep_class(j, &gpio_lock_class);
1565 irq_set_chip_data(j, bank); 1140 irq_set_chip_data(j, bank);
1566 if (bank_is_mpuio(bank)) 1141 if (bank_is_mpuio(bank)) {
1567 irq_set_chip(j, &mpuio_irq_chip); 1142 omap_mpuio_alloc_gc(bank, j, bank->width);
1568 else 1143 } else {
1569 irq_set_chip(j, &gpio_irq_chip); 1144 irq_set_chip(j, &gpio_irq_chip);
1570 irq_set_handler(j, handle_simple_irq); 1145 irq_set_handler(j, handle_simple_irq);
1571 set_irq_flags(j, IRQF_VALID); 1146 set_irq_flags(j, IRQF_VALID);
1147 }
1572 } 1148 }
1573 irq_set_chained_handler(bank->irq, gpio_irq_handler); 1149 irq_set_chained_handler(bank->irq, gpio_irq_handler);
1574 irq_set_handler_data(bank->irq, bank); 1150 irq_set_handler_data(bank->irq, bank);
@@ -1610,7 +1186,14 @@ static int __devinit omap_gpio_probe(struct platform_device *pdev)
1610 bank->dev = &pdev->dev; 1186 bank->dev = &pdev->dev;
1611 bank->dbck_flag = pdata->dbck_flag; 1187 bank->dbck_flag = pdata->dbck_flag;
1612 bank->stride = pdata->bank_stride; 1188 bank->stride = pdata->bank_stride;
1613 bank_width = pdata->bank_width; 1189 bank->width = pdata->bank_width;
1190
1191 bank->regs = pdata->regs;
1192
1193 if (bank->regs->set_dataout && bank->regs->clr_dataout)
1194 bank->set_dataout = _set_gpio_dataout_reg;
1195 else
1196 bank->set_dataout = _set_gpio_dataout_mask;
1614 1197
1615 spin_lock_init(&bank->lock); 1198 spin_lock_init(&bank->lock);
1616 1199
generated by cgit v1.2.2 (git 2.25.0) at 2025-09-04 22:55:43 -0400