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-rw-r--r--drivers/dma/ste_dma40_ll.h79
1 files changed, 31 insertions, 48 deletions
diff --git a/drivers/dma/ste_dma40_ll.h b/drivers/dma/ste_dma40_ll.h
index 9c0fa2f5fe5..37f81e84cd1 100644
--- a/drivers/dma/ste_dma40_ll.h
+++ b/drivers/dma/ste_dma40_ll.h
@@ -1,10 +1,8 @@
1/* 1/*
2 * driver/dma/ste_dma40_ll.h 2 * Copyright (C) ST-Ericsson SA 2007-2010
3 * 3 * Author: Per Friden <per.friden@stericsson.com> for ST-Ericsson SA
4 * Copyright (C) ST-Ericsson 2007-2010 4 * Author: Jonas Aaberg <jonas.aberg@stericsson.com> for ST-Ericsson SA
5 * License terms: GNU General Public License (GPL) version 2 5 * License terms: GNU General Public License (GPL) version 2
6 * Author: Per Friden <per.friden@stericsson.com>
7 * Author: Jonas Aaberg <jonas.aberg@stericsson.com>
8 */ 6 */
9#ifndef STE_DMA40_LL_H 7#ifndef STE_DMA40_LL_H
10#define STE_DMA40_LL_H 8#define STE_DMA40_LL_H
@@ -163,6 +161,9 @@
163#define D40_DREG_PERIPHID0 0xFE0 161#define D40_DREG_PERIPHID0 0xFE0
164#define D40_DREG_PERIPHID1 0xFE4 162#define D40_DREG_PERIPHID1 0xFE4
165#define D40_DREG_PERIPHID2 0xFE8 163#define D40_DREG_PERIPHID2 0xFE8
164#define D40_DREG_PERIPHID2_REV_POS 4
165#define D40_DREG_PERIPHID2_REV_MASK (0xf << D40_DREG_PERIPHID2_REV_POS)
166#define D40_DREG_PERIPHID2_DESIGNER_MASK 0xf
166#define D40_DREG_PERIPHID3 0xFEC 167#define D40_DREG_PERIPHID3 0xFEC
167#define D40_DREG_CELLID0 0xFF0 168#define D40_DREG_CELLID0 0xFF0
168#define D40_DREG_CELLID1 0xFF4 169#define D40_DREG_CELLID1 0xFF4
@@ -199,8 +200,6 @@ struct d40_phy_lli {
199 * 200 *
200 * @src: Register settings for src channel. 201 * @src: Register settings for src channel.
201 * @dst: Register settings for dst channel. 202 * @dst: Register settings for dst channel.
202 * @dst_addr: Physical destination address.
203 * @src_addr: Physical source address.
204 * 203 *
205 * All DMA transfers have a source and a destination. 204 * All DMA transfers have a source and a destination.
206 */ 205 */
@@ -208,8 +207,6 @@ struct d40_phy_lli {
208struct d40_phy_lli_bidir { 207struct d40_phy_lli_bidir {
209 struct d40_phy_lli *src; 208 struct d40_phy_lli *src;
210 struct d40_phy_lli *dst; 209 struct d40_phy_lli *dst;
211 dma_addr_t dst_addr;
212 dma_addr_t src_addr;
213}; 210};
214 211
215 212
@@ -271,29 +268,16 @@ struct d40_def_lcsp {
271 u32 lcsp1; 268 u32 lcsp1;
272}; 269};
273 270
274/**
275 * struct d40_lcla_elem - Info for one LCA element.
276 *
277 * @src_id: logical channel src id
278 * @dst_id: logical channel dst id
279 * @src: LCPA formated src parameters
280 * @dst: LCPA formated dst parameters
281 *
282 */
283struct d40_lcla_elem {
284 int src_id;
285 int dst_id;
286 struct d40_log_lli *src;
287 struct d40_log_lli *dst;
288};
289
290/* Physical channels */ 271/* Physical channels */
291 272
292void d40_phy_cfg(struct stedma40_chan_cfg *cfg, 273void d40_phy_cfg(struct stedma40_chan_cfg *cfg,
293 u32 *src_cfg, u32 *dst_cfg, bool is_log); 274 u32 *src_cfg,
275 u32 *dst_cfg,
276 bool is_log);
294 277
295void d40_log_cfg(struct stedma40_chan_cfg *cfg, 278void d40_log_cfg(struct stedma40_chan_cfg *cfg,
296 u32 *lcsp1, u32 *lcsp2); 279 u32 *lcsp1,
280 u32 *lcsp2);
297 281
298int d40_phy_sg_to_lli(struct scatterlist *sg, 282int d40_phy_sg_to_lli(struct scatterlist *sg,
299 int sg_len, 283 int sg_len,
@@ -302,8 +286,7 @@ int d40_phy_sg_to_lli(struct scatterlist *sg,
302 dma_addr_t lli_phys, 286 dma_addr_t lli_phys,
303 u32 reg_cfg, 287 u32 reg_cfg,
304 u32 data_width, 288 u32 data_width,
305 int psize, 289 int psize);
306 bool term_int);
307 290
308int d40_phy_fill_lli(struct d40_phy_lli *lli, 291int d40_phy_fill_lli(struct d40_phy_lli *lli,
309 dma_addr_t data, 292 dma_addr_t data,
@@ -323,35 +306,35 @@ void d40_phy_lli_write(void __iomem *virtbase,
323/* Logical channels */ 306/* Logical channels */
324 307
325void d40_log_fill_lli(struct d40_log_lli *lli, 308void d40_log_fill_lli(struct d40_log_lli *lli,
326 dma_addr_t data, u32 data_size, 309 dma_addr_t data,
327 u32 lli_next_off, u32 reg_cfg, 310 u32 data_size,
311 u32 reg_cfg,
328 u32 data_width, 312 u32 data_width,
329 bool term_int, bool addr_inc); 313 bool addr_inc);
330 314
331int d40_log_sg_to_dev(struct d40_lcla_elem *lcla, 315int d40_log_sg_to_dev(struct scatterlist *sg,
332 struct scatterlist *sg,
333 int sg_len, 316 int sg_len,
334 struct d40_log_lli_bidir *lli, 317 struct d40_log_lli_bidir *lli,
335 struct d40_def_lcsp *lcsp, 318 struct d40_def_lcsp *lcsp,
336 u32 src_data_width, 319 u32 src_data_width,
337 u32 dst_data_width, 320 u32 dst_data_width,
338 enum dma_data_direction direction, 321 enum dma_data_direction direction,
339 bool term_int, dma_addr_t dev_addr, int max_len, 322 dma_addr_t dev_addr);
340 int llis_per_log); 323
341 324int d40_log_sg_to_lli(struct scatterlist *sg,
342int d40_log_lli_write(struct d40_log_lli_full *lcpa,
343 struct d40_log_lli *lcla_src,
344 struct d40_log_lli *lcla_dst,
345 struct d40_log_lli *lli_dst,
346 struct d40_log_lli *lli_src,
347 int llis_per_log);
348
349int d40_log_sg_to_lli(int lcla_id,
350 struct scatterlist *sg,
351 int sg_len, 325 int sg_len,
352 struct d40_log_lli *lli_sg, 326 struct d40_log_lli *lli_sg,
353 u32 lcsp13, /* src or dst*/ 327 u32 lcsp13, /* src or dst*/
354 u32 data_width, 328 u32 data_width);
355 bool term_int, int max_len, int llis_per_log); 329
330void d40_log_lli_lcpa_write(struct d40_log_lli_full *lcpa,
331 struct d40_log_lli *lli_dst,
332 struct d40_log_lli *lli_src,
333 int next);
334
335void d40_log_lli_lcla_write(struct d40_log_lli *lcla,
336 struct d40_log_lli *lli_dst,
337 struct d40_log_lli *lli_src,
338 int next);
356 339
357#endif /* STE_DMA40_LLI_H */ 340#endif /* STE_DMA40_LLI_H */