diff options
Diffstat (limited to 'drivers/dma/sh/shdma.c')
-rw-r--r-- | drivers/dma/sh/shdma.c | 943 |
1 files changed, 943 insertions, 0 deletions
diff --git a/drivers/dma/sh/shdma.c b/drivers/dma/sh/shdma.c new file mode 100644 index 00000000000..027c9be9765 --- /dev/null +++ b/drivers/dma/sh/shdma.c | |||
@@ -0,0 +1,943 @@ | |||
1 | /* | ||
2 | * Renesas SuperH DMA Engine support | ||
3 | * | ||
4 | * base is drivers/dma/flsdma.c | ||
5 | * | ||
6 | * Copyright (C) 2011-2012 Guennadi Liakhovetski <g.liakhovetski@gmx.de> | ||
7 | * Copyright (C) 2009 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com> | ||
8 | * Copyright (C) 2009 Renesas Solutions, Inc. All rights reserved. | ||
9 | * Copyright (C) 2007 Freescale Semiconductor, Inc. All rights reserved. | ||
10 | * | ||
11 | * This is free software; you can redistribute it and/or modify | ||
12 | * it under the terms of the GNU General Public License as published by | ||
13 | * the Free Software Foundation; either version 2 of the License, or | ||
14 | * (at your option) any later version. | ||
15 | * | ||
16 | * - DMA of SuperH does not have Hardware DMA chain mode. | ||
17 | * - MAX DMA size is 16MB. | ||
18 | * | ||
19 | */ | ||
20 | |||
21 | #include <linux/init.h> | ||
22 | #include <linux/module.h> | ||
23 | #include <linux/slab.h> | ||
24 | #include <linux/interrupt.h> | ||
25 | #include <linux/dmaengine.h> | ||
26 | #include <linux/delay.h> | ||
27 | #include <linux/platform_device.h> | ||
28 | #include <linux/pm_runtime.h> | ||
29 | #include <linux/sh_dma.h> | ||
30 | #include <linux/notifier.h> | ||
31 | #include <linux/kdebug.h> | ||
32 | #include <linux/spinlock.h> | ||
33 | #include <linux/rculist.h> | ||
34 | |||
35 | #include "../dmaengine.h" | ||
36 | #include "shdma.h" | ||
37 | |||
38 | #define SH_DMAE_DRV_NAME "sh-dma-engine" | ||
39 | |||
40 | /* Default MEMCPY transfer size = 2^2 = 4 bytes */ | ||
41 | #define LOG2_DEFAULT_XFER_SIZE 2 | ||
42 | #define SH_DMA_SLAVE_NUMBER 256 | ||
43 | #define SH_DMA_TCR_MAX (16 * 1024 * 1024 - 1) | ||
44 | |||
45 | /* | ||
46 | * Used for write-side mutual exclusion for the global device list, | ||
47 | * read-side synchronization by way of RCU, and per-controller data. | ||
48 | */ | ||
49 | static DEFINE_SPINLOCK(sh_dmae_lock); | ||
50 | static LIST_HEAD(sh_dmae_devices); | ||
51 | |||
52 | static void chclr_write(struct sh_dmae_chan *sh_dc, u32 data) | ||
53 | { | ||
54 | struct sh_dmae_device *shdev = to_sh_dev(sh_dc); | ||
55 | |||
56 | __raw_writel(data, shdev->chan_reg + | ||
57 | shdev->pdata->channel[sh_dc->shdma_chan.id].chclr_offset); | ||
58 | } | ||
59 | |||
60 | static void sh_dmae_writel(struct sh_dmae_chan *sh_dc, u32 data, u32 reg) | ||
61 | { | ||
62 | __raw_writel(data, sh_dc->base + reg / sizeof(u32)); | ||
63 | } | ||
64 | |||
65 | static u32 sh_dmae_readl(struct sh_dmae_chan *sh_dc, u32 reg) | ||
66 | { | ||
67 | return __raw_readl(sh_dc->base + reg / sizeof(u32)); | ||
68 | } | ||
69 | |||
70 | static u16 dmaor_read(struct sh_dmae_device *shdev) | ||
71 | { | ||
72 | u32 __iomem *addr = shdev->chan_reg + DMAOR / sizeof(u32); | ||
73 | |||
74 | if (shdev->pdata->dmaor_is_32bit) | ||
75 | return __raw_readl(addr); | ||
76 | else | ||
77 | return __raw_readw(addr); | ||
78 | } | ||
79 | |||
80 | static void dmaor_write(struct sh_dmae_device *shdev, u16 data) | ||
81 | { | ||
82 | u32 __iomem *addr = shdev->chan_reg + DMAOR / sizeof(u32); | ||
83 | |||
84 | if (shdev->pdata->dmaor_is_32bit) | ||
85 | __raw_writel(data, addr); | ||
86 | else | ||
87 | __raw_writew(data, addr); | ||
88 | } | ||
89 | |||
90 | static void chcr_write(struct sh_dmae_chan *sh_dc, u32 data) | ||
91 | { | ||
92 | struct sh_dmae_device *shdev = to_sh_dev(sh_dc); | ||
93 | |||
94 | __raw_writel(data, sh_dc->base + shdev->chcr_offset / sizeof(u32)); | ||
95 | } | ||
96 | |||
97 | static u32 chcr_read(struct sh_dmae_chan *sh_dc) | ||
98 | { | ||
99 | struct sh_dmae_device *shdev = to_sh_dev(sh_dc); | ||
100 | |||
101 | return __raw_readl(sh_dc->base + shdev->chcr_offset / sizeof(u32)); | ||
102 | } | ||
103 | |||
104 | /* | ||
105 | * Reset DMA controller | ||
106 | * | ||
107 | * SH7780 has two DMAOR register | ||
108 | */ | ||
109 | static void sh_dmae_ctl_stop(struct sh_dmae_device *shdev) | ||
110 | { | ||
111 | unsigned short dmaor; | ||
112 | unsigned long flags; | ||
113 | |||
114 | spin_lock_irqsave(&sh_dmae_lock, flags); | ||
115 | |||
116 | dmaor = dmaor_read(shdev); | ||
117 | dmaor_write(shdev, dmaor & ~(DMAOR_NMIF | DMAOR_AE | DMAOR_DME)); | ||
118 | |||
119 | spin_unlock_irqrestore(&sh_dmae_lock, flags); | ||
120 | } | ||
121 | |||
122 | static int sh_dmae_rst(struct sh_dmae_device *shdev) | ||
123 | { | ||
124 | unsigned short dmaor; | ||
125 | unsigned long flags; | ||
126 | |||
127 | spin_lock_irqsave(&sh_dmae_lock, flags); | ||
128 | |||
129 | dmaor = dmaor_read(shdev) & ~(DMAOR_NMIF | DMAOR_AE | DMAOR_DME); | ||
130 | |||
131 | if (shdev->pdata->chclr_present) { | ||
132 | int i; | ||
133 | for (i = 0; i < shdev->pdata->channel_num; i++) { | ||
134 | struct sh_dmae_chan *sh_chan = shdev->chan[i]; | ||
135 | if (sh_chan) | ||
136 | chclr_write(sh_chan, 0); | ||
137 | } | ||
138 | } | ||
139 | |||
140 | dmaor_write(shdev, dmaor | shdev->pdata->dmaor_init); | ||
141 | |||
142 | dmaor = dmaor_read(shdev); | ||
143 | |||
144 | spin_unlock_irqrestore(&sh_dmae_lock, flags); | ||
145 | |||
146 | if (dmaor & (DMAOR_AE | DMAOR_NMIF)) { | ||
147 | dev_warn(shdev->shdma_dev.dma_dev.dev, "Can't initialize DMAOR.\n"); | ||
148 | return -EIO; | ||
149 | } | ||
150 | if (shdev->pdata->dmaor_init & ~dmaor) | ||
151 | dev_warn(shdev->shdma_dev.dma_dev.dev, | ||
152 | "DMAOR=0x%x hasn't latched the initial value 0x%x.\n", | ||
153 | dmaor, shdev->pdata->dmaor_init); | ||
154 | return 0; | ||
155 | } | ||
156 | |||
157 | static bool dmae_is_busy(struct sh_dmae_chan *sh_chan) | ||
158 | { | ||
159 | u32 chcr = chcr_read(sh_chan); | ||
160 | |||
161 | if ((chcr & (CHCR_DE | CHCR_TE)) == CHCR_DE) | ||
162 | return true; /* working */ | ||
163 | |||
164 | return false; /* waiting */ | ||
165 | } | ||
166 | |||
167 | static unsigned int calc_xmit_shift(struct sh_dmae_chan *sh_chan, u32 chcr) | ||
168 | { | ||
169 | struct sh_dmae_device *shdev = to_sh_dev(sh_chan); | ||
170 | struct sh_dmae_pdata *pdata = shdev->pdata; | ||
171 | int cnt = ((chcr & pdata->ts_low_mask) >> pdata->ts_low_shift) | | ||
172 | ((chcr & pdata->ts_high_mask) >> pdata->ts_high_shift); | ||
173 | |||
174 | if (cnt >= pdata->ts_shift_num) | ||
175 | cnt = 0; | ||
176 | |||
177 | return pdata->ts_shift[cnt]; | ||
178 | } | ||
179 | |||
180 | static u32 log2size_to_chcr(struct sh_dmae_chan *sh_chan, int l2size) | ||
181 | { | ||
182 | struct sh_dmae_device *shdev = to_sh_dev(sh_chan); | ||
183 | struct sh_dmae_pdata *pdata = shdev->pdata; | ||
184 | int i; | ||
185 | |||
186 | for (i = 0; i < pdata->ts_shift_num; i++) | ||
187 | if (pdata->ts_shift[i] == l2size) | ||
188 | break; | ||
189 | |||
190 | if (i == pdata->ts_shift_num) | ||
191 | i = 0; | ||
192 | |||
193 | return ((i << pdata->ts_low_shift) & pdata->ts_low_mask) | | ||
194 | ((i << pdata->ts_high_shift) & pdata->ts_high_mask); | ||
195 | } | ||
196 | |||
197 | static void dmae_set_reg(struct sh_dmae_chan *sh_chan, struct sh_dmae_regs *hw) | ||
198 | { | ||
199 | sh_dmae_writel(sh_chan, hw->sar, SAR); | ||
200 | sh_dmae_writel(sh_chan, hw->dar, DAR); | ||
201 | sh_dmae_writel(sh_chan, hw->tcr >> sh_chan->xmit_shift, TCR); | ||
202 | } | ||
203 | |||
204 | static void dmae_start(struct sh_dmae_chan *sh_chan) | ||
205 | { | ||
206 | struct sh_dmae_device *shdev = to_sh_dev(sh_chan); | ||
207 | u32 chcr = chcr_read(sh_chan); | ||
208 | |||
209 | if (shdev->pdata->needs_tend_set) | ||
210 | sh_dmae_writel(sh_chan, 0xFFFFFFFF, TEND); | ||
211 | |||
212 | chcr |= CHCR_DE | shdev->chcr_ie_bit; | ||
213 | chcr_write(sh_chan, chcr & ~CHCR_TE); | ||
214 | } | ||
215 | |||
216 | static void dmae_init(struct sh_dmae_chan *sh_chan) | ||
217 | { | ||
218 | /* | ||
219 | * Default configuration for dual address memory-memory transfer. | ||
220 | * 0x400 represents auto-request. | ||
221 | */ | ||
222 | u32 chcr = DM_INC | SM_INC | 0x400 | log2size_to_chcr(sh_chan, | ||
223 | LOG2_DEFAULT_XFER_SIZE); | ||
224 | sh_chan->xmit_shift = calc_xmit_shift(sh_chan, chcr); | ||
225 | chcr_write(sh_chan, chcr); | ||
226 | } | ||
227 | |||
228 | static int dmae_set_chcr(struct sh_dmae_chan *sh_chan, u32 val) | ||
229 | { | ||
230 | /* If DMA is active, cannot set CHCR. TODO: remove this superfluous check */ | ||
231 | if (dmae_is_busy(sh_chan)) | ||
232 | return -EBUSY; | ||
233 | |||
234 | sh_chan->xmit_shift = calc_xmit_shift(sh_chan, val); | ||
235 | chcr_write(sh_chan, val); | ||
236 | |||
237 | return 0; | ||
238 | } | ||
239 | |||
240 | static int dmae_set_dmars(struct sh_dmae_chan *sh_chan, u16 val) | ||
241 | { | ||
242 | struct sh_dmae_device *shdev = to_sh_dev(sh_chan); | ||
243 | struct sh_dmae_pdata *pdata = shdev->pdata; | ||
244 | const struct sh_dmae_channel *chan_pdata = &pdata->channel[sh_chan->shdma_chan.id]; | ||
245 | u16 __iomem *addr = shdev->dmars; | ||
246 | unsigned int shift = chan_pdata->dmars_bit; | ||
247 | |||
248 | if (dmae_is_busy(sh_chan)) | ||
249 | return -EBUSY; | ||
250 | |||
251 | if (pdata->no_dmars) | ||
252 | return 0; | ||
253 | |||
254 | /* in the case of a missing DMARS resource use first memory window */ | ||
255 | if (!addr) | ||
256 | addr = (u16 __iomem *)shdev->chan_reg; | ||
257 | addr += chan_pdata->dmars / sizeof(u16); | ||
258 | |||
259 | __raw_writew((__raw_readw(addr) & (0xff00 >> shift)) | (val << shift), | ||
260 | addr); | ||
261 | |||
262 | return 0; | ||
263 | } | ||
264 | |||
265 | static void sh_dmae_start_xfer(struct shdma_chan *schan, | ||
266 | struct shdma_desc *sdesc) | ||
267 | { | ||
268 | struct sh_dmae_chan *sh_chan = container_of(schan, struct sh_dmae_chan, | ||
269 | shdma_chan); | ||
270 | struct sh_dmae_desc *sh_desc = container_of(sdesc, | ||
271 | struct sh_dmae_desc, shdma_desc); | ||
272 | dev_dbg(sh_chan->shdma_chan.dev, "Queue #%d to %d: %u@%x -> %x\n", | ||
273 | sdesc->async_tx.cookie, sh_chan->shdma_chan.id, | ||
274 | sh_desc->hw.tcr, sh_desc->hw.sar, sh_desc->hw.dar); | ||
275 | /* Get the ld start address from ld_queue */ | ||
276 | dmae_set_reg(sh_chan, &sh_desc->hw); | ||
277 | dmae_start(sh_chan); | ||
278 | } | ||
279 | |||
280 | static bool sh_dmae_channel_busy(struct shdma_chan *schan) | ||
281 | { | ||
282 | struct sh_dmae_chan *sh_chan = container_of(schan, struct sh_dmae_chan, | ||
283 | shdma_chan); | ||
284 | return dmae_is_busy(sh_chan); | ||
285 | } | ||
286 | |||
287 | static void sh_dmae_setup_xfer(struct shdma_chan *schan, | ||
288 | int slave_id) | ||
289 | { | ||
290 | struct sh_dmae_chan *sh_chan = container_of(schan, struct sh_dmae_chan, | ||
291 | shdma_chan); | ||
292 | |||
293 | if (slave_id >= 0) { | ||
294 | const struct sh_dmae_slave_config *cfg = | ||
295 | sh_chan->config; | ||
296 | |||
297 | dmae_set_dmars(sh_chan, cfg->mid_rid); | ||
298 | dmae_set_chcr(sh_chan, cfg->chcr); | ||
299 | } else { | ||
300 | dmae_init(sh_chan); | ||
301 | } | ||
302 | } | ||
303 | |||
304 | static const struct sh_dmae_slave_config *dmae_find_slave( | ||
305 | struct sh_dmae_chan *sh_chan, int slave_id) | ||
306 | { | ||
307 | struct sh_dmae_device *shdev = to_sh_dev(sh_chan); | ||
308 | struct sh_dmae_pdata *pdata = shdev->pdata; | ||
309 | const struct sh_dmae_slave_config *cfg; | ||
310 | int i; | ||
311 | |||
312 | if (slave_id >= SH_DMA_SLAVE_NUMBER) | ||
313 | return NULL; | ||
314 | |||
315 | for (i = 0, cfg = pdata->slave; i < pdata->slave_num; i++, cfg++) | ||
316 | if (cfg->slave_id == slave_id) | ||
317 | return cfg; | ||
318 | |||
319 | return NULL; | ||
320 | } | ||
321 | |||
322 | static int sh_dmae_set_slave(struct shdma_chan *schan, | ||
323 | int slave_id, bool try) | ||
324 | { | ||
325 | struct sh_dmae_chan *sh_chan = container_of(schan, struct sh_dmae_chan, | ||
326 | shdma_chan); | ||
327 | const struct sh_dmae_slave_config *cfg = dmae_find_slave(sh_chan, slave_id); | ||
328 | if (!cfg) | ||
329 | return -ENODEV; | ||
330 | |||
331 | if (!try) | ||
332 | sh_chan->config = cfg; | ||
333 | |||
334 | return 0; | ||
335 | } | ||
336 | |||
337 | static void dmae_halt(struct sh_dmae_chan *sh_chan) | ||
338 | { | ||
339 | struct sh_dmae_device *shdev = to_sh_dev(sh_chan); | ||
340 | u32 chcr = chcr_read(sh_chan); | ||
341 | |||
342 | chcr &= ~(CHCR_DE | CHCR_TE | shdev->chcr_ie_bit); | ||
343 | chcr_write(sh_chan, chcr); | ||
344 | } | ||
345 | |||
346 | static int sh_dmae_desc_setup(struct shdma_chan *schan, | ||
347 | struct shdma_desc *sdesc, | ||
348 | dma_addr_t src, dma_addr_t dst, size_t *len) | ||
349 | { | ||
350 | struct sh_dmae_desc *sh_desc = container_of(sdesc, | ||
351 | struct sh_dmae_desc, shdma_desc); | ||
352 | |||
353 | if (*len > schan->max_xfer_len) | ||
354 | *len = schan->max_xfer_len; | ||
355 | |||
356 | sh_desc->hw.sar = src; | ||
357 | sh_desc->hw.dar = dst; | ||
358 | sh_desc->hw.tcr = *len; | ||
359 | |||
360 | return 0; | ||
361 | } | ||
362 | |||
363 | static void sh_dmae_halt(struct shdma_chan *schan) | ||
364 | { | ||
365 | struct sh_dmae_chan *sh_chan = container_of(schan, struct sh_dmae_chan, | ||
366 | shdma_chan); | ||
367 | dmae_halt(sh_chan); | ||
368 | } | ||
369 | |||
370 | static bool sh_dmae_chan_irq(struct shdma_chan *schan, int irq) | ||
371 | { | ||
372 | struct sh_dmae_chan *sh_chan = container_of(schan, struct sh_dmae_chan, | ||
373 | shdma_chan); | ||
374 | |||
375 | if (!(chcr_read(sh_chan) & CHCR_TE)) | ||
376 | return false; | ||
377 | |||
378 | /* DMA stop */ | ||
379 | dmae_halt(sh_chan); | ||
380 | |||
381 | return true; | ||
382 | } | ||
383 | |||
384 | /* Called from error IRQ or NMI */ | ||
385 | static bool sh_dmae_reset(struct sh_dmae_device *shdev) | ||
386 | { | ||
387 | bool ret; | ||
388 | |||
389 | /* halt the dma controller */ | ||
390 | sh_dmae_ctl_stop(shdev); | ||
391 | |||
392 | /* We cannot detect, which channel caused the error, have to reset all */ | ||
393 | ret = shdma_reset(&shdev->shdma_dev); | ||
394 | |||
395 | sh_dmae_rst(shdev); | ||
396 | |||
397 | return ret; | ||
398 | } | ||
399 | |||
400 | static irqreturn_t sh_dmae_err(int irq, void *data) | ||
401 | { | ||
402 | struct sh_dmae_device *shdev = data; | ||
403 | |||
404 | if (!(dmaor_read(shdev) & DMAOR_AE)) | ||
405 | return IRQ_NONE; | ||
406 | |||
407 | sh_dmae_reset(shdev); | ||
408 | return IRQ_HANDLED; | ||
409 | } | ||
410 | |||
411 | static bool sh_dmae_desc_completed(struct shdma_chan *schan, | ||
412 | struct shdma_desc *sdesc) | ||
413 | { | ||
414 | struct sh_dmae_chan *sh_chan = container_of(schan, | ||
415 | struct sh_dmae_chan, shdma_chan); | ||
416 | struct sh_dmae_desc *sh_desc = container_of(sdesc, | ||
417 | struct sh_dmae_desc, shdma_desc); | ||
418 | u32 sar_buf = sh_dmae_readl(sh_chan, SAR); | ||
419 | u32 dar_buf = sh_dmae_readl(sh_chan, DAR); | ||
420 | |||
421 | return (sdesc->direction == DMA_DEV_TO_MEM && | ||
422 | (sh_desc->hw.dar + sh_desc->hw.tcr) == dar_buf) || | ||
423 | (sdesc->direction != DMA_DEV_TO_MEM && | ||
424 | (sh_desc->hw.sar + sh_desc->hw.tcr) == sar_buf); | ||
425 | } | ||
426 | |||
427 | static bool sh_dmae_nmi_notify(struct sh_dmae_device *shdev) | ||
428 | { | ||
429 | /* Fast path out if NMIF is not asserted for this controller */ | ||
430 | if ((dmaor_read(shdev) & DMAOR_NMIF) == 0) | ||
431 | return false; | ||
432 | |||
433 | return sh_dmae_reset(shdev); | ||
434 | } | ||
435 | |||
436 | static int sh_dmae_nmi_handler(struct notifier_block *self, | ||
437 | unsigned long cmd, void *data) | ||
438 | { | ||
439 | struct sh_dmae_device *shdev; | ||
440 | int ret = NOTIFY_DONE; | ||
441 | bool triggered; | ||
442 | |||
443 | /* | ||
444 | * Only concern ourselves with NMI events. | ||
445 | * | ||
446 | * Normally we would check the die chain value, but as this needs | ||
447 | * to be architecture independent, check for NMI context instead. | ||
448 | */ | ||
449 | if (!in_nmi()) | ||
450 | return NOTIFY_DONE; | ||
451 | |||
452 | rcu_read_lock(); | ||
453 | list_for_each_entry_rcu(shdev, &sh_dmae_devices, node) { | ||
454 | /* | ||
455 | * Only stop if one of the controllers has NMIF asserted, | ||
456 | * we do not want to interfere with regular address error | ||
457 | * handling or NMI events that don't concern the DMACs. | ||
458 | */ | ||
459 | triggered = sh_dmae_nmi_notify(shdev); | ||
460 | if (triggered == true) | ||
461 | ret = NOTIFY_OK; | ||
462 | } | ||
463 | rcu_read_unlock(); | ||
464 | |||
465 | return ret; | ||
466 | } | ||
467 | |||
468 | static struct notifier_block sh_dmae_nmi_notifier __read_mostly = { | ||
469 | .notifier_call = sh_dmae_nmi_handler, | ||
470 | |||
471 | /* Run before NMI debug handler and KGDB */ | ||
472 | .priority = 1, | ||
473 | }; | ||
474 | |||
475 | static int __devinit sh_dmae_chan_probe(struct sh_dmae_device *shdev, int id, | ||
476 | int irq, unsigned long flags) | ||
477 | { | ||
478 | const struct sh_dmae_channel *chan_pdata = &shdev->pdata->channel[id]; | ||
479 | struct shdma_dev *sdev = &shdev->shdma_dev; | ||
480 | struct platform_device *pdev = to_platform_device(sdev->dma_dev.dev); | ||
481 | struct sh_dmae_chan *sh_chan; | ||
482 | struct shdma_chan *schan; | ||
483 | int err; | ||
484 | |||
485 | sh_chan = kzalloc(sizeof(struct sh_dmae_chan), GFP_KERNEL); | ||
486 | if (!sh_chan) { | ||
487 | dev_err(sdev->dma_dev.dev, | ||
488 | "No free memory for allocating dma channels!\n"); | ||
489 | return -ENOMEM; | ||
490 | } | ||
491 | |||
492 | schan = &sh_chan->shdma_chan; | ||
493 | schan->max_xfer_len = SH_DMA_TCR_MAX + 1; | ||
494 | |||
495 | shdma_chan_probe(sdev, schan, id); | ||
496 | |||
497 | sh_chan->base = shdev->chan_reg + chan_pdata->offset / sizeof(u32); | ||
498 | |||
499 | /* set up channel irq */ | ||
500 | if (pdev->id >= 0) | ||
501 | snprintf(sh_chan->dev_id, sizeof(sh_chan->dev_id), | ||
502 | "sh-dmae%d.%d", pdev->id, id); | ||
503 | else | ||
504 | snprintf(sh_chan->dev_id, sizeof(sh_chan->dev_id), | ||
505 | "sh-dma%d", id); | ||
506 | |||
507 | err = shdma_request_irq(schan, irq, flags, sh_chan->dev_id); | ||
508 | if (err) { | ||
509 | dev_err(sdev->dma_dev.dev, | ||
510 | "DMA channel %d request_irq error %d\n", | ||
511 | id, err); | ||
512 | goto err_no_irq; | ||
513 | } | ||
514 | |||
515 | shdev->chan[id] = sh_chan; | ||
516 | return 0; | ||
517 | |||
518 | err_no_irq: | ||
519 | /* remove from dmaengine device node */ | ||
520 | shdma_chan_remove(schan); | ||
521 | kfree(sh_chan); | ||
522 | return err; | ||
523 | } | ||
524 | |||
525 | static void sh_dmae_chan_remove(struct sh_dmae_device *shdev) | ||
526 | { | ||
527 | struct dma_device *dma_dev = &shdev->shdma_dev.dma_dev; | ||
528 | struct shdma_chan *schan; | ||
529 | int i; | ||
530 | |||
531 | shdma_for_each_chan(schan, &shdev->shdma_dev, i) { | ||
532 | struct sh_dmae_chan *sh_chan = container_of(schan, | ||
533 | struct sh_dmae_chan, shdma_chan); | ||
534 | BUG_ON(!schan); | ||
535 | |||
536 | shdma_free_irq(&sh_chan->shdma_chan); | ||
537 | |||
538 | shdma_chan_remove(schan); | ||
539 | kfree(sh_chan); | ||
540 | } | ||
541 | dma_dev->chancnt = 0; | ||
542 | } | ||
543 | |||
544 | static void sh_dmae_shutdown(struct platform_device *pdev) | ||
545 | { | ||
546 | struct sh_dmae_device *shdev = platform_get_drvdata(pdev); | ||
547 | sh_dmae_ctl_stop(shdev); | ||
548 | } | ||
549 | |||
550 | static int sh_dmae_runtime_suspend(struct device *dev) | ||
551 | { | ||
552 | return 0; | ||
553 | } | ||
554 | |||
555 | static int sh_dmae_runtime_resume(struct device *dev) | ||
556 | { | ||
557 | struct sh_dmae_device *shdev = dev_get_drvdata(dev); | ||
558 | |||
559 | return sh_dmae_rst(shdev); | ||
560 | } | ||
561 | |||
562 | #ifdef CONFIG_PM | ||
563 | static int sh_dmae_suspend(struct device *dev) | ||
564 | { | ||
565 | return 0; | ||
566 | } | ||
567 | |||
568 | static int sh_dmae_resume(struct device *dev) | ||
569 | { | ||
570 | struct sh_dmae_device *shdev = dev_get_drvdata(dev); | ||
571 | int i, ret; | ||
572 | |||
573 | ret = sh_dmae_rst(shdev); | ||
574 | if (ret < 0) | ||
575 | dev_err(dev, "Failed to reset!\n"); | ||
576 | |||
577 | for (i = 0; i < shdev->pdata->channel_num; i++) { | ||
578 | struct sh_dmae_chan *sh_chan = shdev->chan[i]; | ||
579 | |||
580 | if (!sh_chan->shdma_chan.desc_num) | ||
581 | continue; | ||
582 | |||
583 | if (sh_chan->shdma_chan.slave_id >= 0) { | ||
584 | const struct sh_dmae_slave_config *cfg = sh_chan->config; | ||
585 | dmae_set_dmars(sh_chan, cfg->mid_rid); | ||
586 | dmae_set_chcr(sh_chan, cfg->chcr); | ||
587 | } else { | ||
588 | dmae_init(sh_chan); | ||
589 | } | ||
590 | } | ||
591 | |||
592 | return 0; | ||
593 | } | ||
594 | #else | ||
595 | #define sh_dmae_suspend NULL | ||
596 | #define sh_dmae_resume NULL | ||
597 | #endif | ||
598 | |||
599 | const struct dev_pm_ops sh_dmae_pm = { | ||
600 | .suspend = sh_dmae_suspend, | ||
601 | .resume = sh_dmae_resume, | ||
602 | .runtime_suspend = sh_dmae_runtime_suspend, | ||
603 | .runtime_resume = sh_dmae_runtime_resume, | ||
604 | }; | ||
605 | |||
606 | static dma_addr_t sh_dmae_slave_addr(struct shdma_chan *schan) | ||
607 | { | ||
608 | struct sh_dmae_chan *sh_chan = container_of(schan, | ||
609 | struct sh_dmae_chan, shdma_chan); | ||
610 | |||
611 | /* | ||
612 | * Implicit BUG_ON(!sh_chan->config) | ||
613 | * This is an exclusive slave DMA operation, may only be called after a | ||
614 | * successful slave configuration. | ||
615 | */ | ||
616 | return sh_chan->config->addr; | ||
617 | } | ||
618 | |||
619 | static struct shdma_desc *sh_dmae_embedded_desc(void *buf, int i) | ||
620 | { | ||
621 | return &((struct sh_dmae_desc *)buf)[i].shdma_desc; | ||
622 | } | ||
623 | |||
624 | static const struct shdma_ops sh_dmae_shdma_ops = { | ||
625 | .desc_completed = sh_dmae_desc_completed, | ||
626 | .halt_channel = sh_dmae_halt, | ||
627 | .channel_busy = sh_dmae_channel_busy, | ||
628 | .slave_addr = sh_dmae_slave_addr, | ||
629 | .desc_setup = sh_dmae_desc_setup, | ||
630 | .set_slave = sh_dmae_set_slave, | ||
631 | .setup_xfer = sh_dmae_setup_xfer, | ||
632 | .start_xfer = sh_dmae_start_xfer, | ||
633 | .embedded_desc = sh_dmae_embedded_desc, | ||
634 | .chan_irq = sh_dmae_chan_irq, | ||
635 | }; | ||
636 | |||
637 | static int __devinit sh_dmae_probe(struct platform_device *pdev) | ||
638 | { | ||
639 | struct sh_dmae_pdata *pdata = pdev->dev.platform_data; | ||
640 | unsigned long irqflags = IRQF_DISABLED, | ||
641 | chan_flag[SH_DMAE_MAX_CHANNELS] = {}; | ||
642 | int errirq, chan_irq[SH_DMAE_MAX_CHANNELS]; | ||
643 | int err, i, irq_cnt = 0, irqres = 0, irq_cap = 0; | ||
644 | struct sh_dmae_device *shdev; | ||
645 | struct dma_device *dma_dev; | ||
646 | struct resource *chan, *dmars, *errirq_res, *chanirq_res; | ||
647 | |||
648 | /* get platform data */ | ||
649 | if (!pdata || !pdata->channel_num) | ||
650 | return -ENODEV; | ||
651 | |||
652 | chan = platform_get_resource(pdev, IORESOURCE_MEM, 0); | ||
653 | /* DMARS area is optional */ | ||
654 | dmars = platform_get_resource(pdev, IORESOURCE_MEM, 1); | ||
655 | /* | ||
656 | * IRQ resources: | ||
657 | * 1. there always must be at least one IRQ IO-resource. On SH4 it is | ||
658 | * the error IRQ, in which case it is the only IRQ in this resource: | ||
659 | * start == end. If it is the only IRQ resource, all channels also | ||
660 | * use the same IRQ. | ||
661 | * 2. DMA channel IRQ resources can be specified one per resource or in | ||
662 | * ranges (start != end) | ||
663 | * 3. iff all events (channels and, optionally, error) on this | ||
664 | * controller use the same IRQ, only one IRQ resource can be | ||
665 | * specified, otherwise there must be one IRQ per channel, even if | ||
666 | * some of them are equal | ||
667 | * 4. if all IRQs on this controller are equal or if some specific IRQs | ||
668 | * specify IORESOURCE_IRQ_SHAREABLE in their resources, they will be | ||
669 | * requested with the IRQF_SHARED flag | ||
670 | */ | ||
671 | errirq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); | ||
672 | if (!chan || !errirq_res) | ||
673 | return -ENODEV; | ||
674 | |||
675 | if (!request_mem_region(chan->start, resource_size(chan), pdev->name)) { | ||
676 | dev_err(&pdev->dev, "DMAC register region already claimed\n"); | ||
677 | return -EBUSY; | ||
678 | } | ||
679 | |||
680 | if (dmars && !request_mem_region(dmars->start, resource_size(dmars), pdev->name)) { | ||
681 | dev_err(&pdev->dev, "DMAC DMARS region already claimed\n"); | ||
682 | err = -EBUSY; | ||
683 | goto ermrdmars; | ||
684 | } | ||
685 | |||
686 | err = -ENOMEM; | ||
687 | shdev = kzalloc(sizeof(struct sh_dmae_device), GFP_KERNEL); | ||
688 | if (!shdev) { | ||
689 | dev_err(&pdev->dev, "Not enough memory\n"); | ||
690 | goto ealloc; | ||
691 | } | ||
692 | |||
693 | dma_dev = &shdev->shdma_dev.dma_dev; | ||
694 | |||
695 | shdev->chan_reg = ioremap(chan->start, resource_size(chan)); | ||
696 | if (!shdev->chan_reg) | ||
697 | goto emapchan; | ||
698 | if (dmars) { | ||
699 | shdev->dmars = ioremap(dmars->start, resource_size(dmars)); | ||
700 | if (!shdev->dmars) | ||
701 | goto emapdmars; | ||
702 | } | ||
703 | |||
704 | if (!pdata->slave_only) | ||
705 | dma_cap_set(DMA_MEMCPY, dma_dev->cap_mask); | ||
706 | if (pdata->slave && pdata->slave_num) | ||
707 | dma_cap_set(DMA_SLAVE, dma_dev->cap_mask); | ||
708 | |||
709 | /* Default transfer size of 32 bytes requires 32-byte alignment */ | ||
710 | dma_dev->copy_align = LOG2_DEFAULT_XFER_SIZE; | ||
711 | |||
712 | shdev->shdma_dev.ops = &sh_dmae_shdma_ops; | ||
713 | shdev->shdma_dev.desc_size = sizeof(struct sh_dmae_desc); | ||
714 | err = shdma_init(&pdev->dev, &shdev->shdma_dev, | ||
715 | pdata->channel_num); | ||
716 | if (err < 0) | ||
717 | goto eshdma; | ||
718 | |||
719 | /* platform data */ | ||
720 | shdev->pdata = pdev->dev.platform_data; | ||
721 | |||
722 | if (pdata->chcr_offset) | ||
723 | shdev->chcr_offset = pdata->chcr_offset; | ||
724 | else | ||
725 | shdev->chcr_offset = CHCR; | ||
726 | |||
727 | if (pdata->chcr_ie_bit) | ||
728 | shdev->chcr_ie_bit = pdata->chcr_ie_bit; | ||
729 | else | ||
730 | shdev->chcr_ie_bit = CHCR_IE; | ||
731 | |||
732 | platform_set_drvdata(pdev, shdev); | ||
733 | |||
734 | pm_runtime_enable(&pdev->dev); | ||
735 | err = pm_runtime_get_sync(&pdev->dev); | ||
736 | if (err < 0) | ||
737 | dev_err(&pdev->dev, "%s(): GET = %d\n", __func__, err); | ||
738 | |||
739 | spin_lock_irq(&sh_dmae_lock); | ||
740 | list_add_tail_rcu(&shdev->node, &sh_dmae_devices); | ||
741 | spin_unlock_irq(&sh_dmae_lock); | ||
742 | |||
743 | /* reset dma controller - only needed as a test */ | ||
744 | err = sh_dmae_rst(shdev); | ||
745 | if (err) | ||
746 | goto rst_err; | ||
747 | |||
748 | #if defined(CONFIG_CPU_SH4) || defined(CONFIG_ARCH_SHMOBILE) | ||
749 | chanirq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 1); | ||
750 | |||
751 | if (!chanirq_res) | ||
752 | chanirq_res = errirq_res; | ||
753 | else | ||
754 | irqres++; | ||
755 | |||
756 | if (chanirq_res == errirq_res || | ||
757 | (errirq_res->flags & IORESOURCE_BITS) == IORESOURCE_IRQ_SHAREABLE) | ||
758 | irqflags = IRQF_SHARED; | ||
759 | |||
760 | errirq = errirq_res->start; | ||
761 | |||
762 | err = request_irq(errirq, sh_dmae_err, irqflags, | ||
763 | "DMAC Address Error", shdev); | ||
764 | if (err) { | ||
765 | dev_err(&pdev->dev, | ||
766 | "DMA failed requesting irq #%d, error %d\n", | ||
767 | errirq, err); | ||
768 | goto eirq_err; | ||
769 | } | ||
770 | |||
771 | #else | ||
772 | chanirq_res = errirq_res; | ||
773 | #endif /* CONFIG_CPU_SH4 || CONFIG_ARCH_SHMOBILE */ | ||
774 | |||
775 | if (chanirq_res->start == chanirq_res->end && | ||
776 | !platform_get_resource(pdev, IORESOURCE_IRQ, 1)) { | ||
777 | /* Special case - all multiplexed */ | ||
778 | for (; irq_cnt < pdata->channel_num; irq_cnt++) { | ||
779 | if (irq_cnt < SH_DMAE_MAX_CHANNELS) { | ||
780 | chan_irq[irq_cnt] = chanirq_res->start; | ||
781 | chan_flag[irq_cnt] = IRQF_SHARED; | ||
782 | } else { | ||
783 | irq_cap = 1; | ||
784 | break; | ||
785 | } | ||
786 | } | ||
787 | } else { | ||
788 | do { | ||
789 | for (i = chanirq_res->start; i <= chanirq_res->end; i++) { | ||
790 | if (irq_cnt >= SH_DMAE_MAX_CHANNELS) { | ||
791 | irq_cap = 1; | ||
792 | break; | ||
793 | } | ||
794 | |||
795 | if ((errirq_res->flags & IORESOURCE_BITS) == | ||
796 | IORESOURCE_IRQ_SHAREABLE) | ||
797 | chan_flag[irq_cnt] = IRQF_SHARED; | ||
798 | else | ||
799 | chan_flag[irq_cnt] = IRQF_DISABLED; | ||
800 | dev_dbg(&pdev->dev, | ||
801 | "Found IRQ %d for channel %d\n", | ||
802 | i, irq_cnt); | ||
803 | chan_irq[irq_cnt++] = i; | ||
804 | } | ||
805 | |||
806 | if (irq_cnt >= SH_DMAE_MAX_CHANNELS) | ||
807 | break; | ||
808 | |||
809 | chanirq_res = platform_get_resource(pdev, | ||
810 | IORESOURCE_IRQ, ++irqres); | ||
811 | } while (irq_cnt < pdata->channel_num && chanirq_res); | ||
812 | } | ||
813 | |||
814 | /* Create DMA Channel */ | ||
815 | for (i = 0; i < irq_cnt; i++) { | ||
816 | err = sh_dmae_chan_probe(shdev, i, chan_irq[i], chan_flag[i]); | ||
817 | if (err) | ||
818 | goto chan_probe_err; | ||
819 | } | ||
820 | |||
821 | if (irq_cap) | ||
822 | dev_notice(&pdev->dev, "Attempting to register %d DMA " | ||
823 | "channels when a maximum of %d are supported.\n", | ||
824 | pdata->channel_num, SH_DMAE_MAX_CHANNELS); | ||
825 | |||
826 | pm_runtime_put(&pdev->dev); | ||
827 | |||
828 | err = dma_async_device_register(&shdev->shdma_dev.dma_dev); | ||
829 | if (err < 0) | ||
830 | goto edmadevreg; | ||
831 | |||
832 | return err; | ||
833 | |||
834 | edmadevreg: | ||
835 | pm_runtime_get(&pdev->dev); | ||
836 | |||
837 | chan_probe_err: | ||
838 | sh_dmae_chan_remove(shdev); | ||
839 | |||
840 | #if defined(CONFIG_CPU_SH4) || defined(CONFIG_ARCH_SHMOBILE) | ||
841 | free_irq(errirq, shdev); | ||
842 | eirq_err: | ||
843 | #endif | ||
844 | rst_err: | ||
845 | spin_lock_irq(&sh_dmae_lock); | ||
846 | list_del_rcu(&shdev->node); | ||
847 | spin_unlock_irq(&sh_dmae_lock); | ||
848 | |||
849 | pm_runtime_put(&pdev->dev); | ||
850 | pm_runtime_disable(&pdev->dev); | ||
851 | |||
852 | platform_set_drvdata(pdev, NULL); | ||
853 | shdma_cleanup(&shdev->shdma_dev); | ||
854 | eshdma: | ||
855 | if (dmars) | ||
856 | iounmap(shdev->dmars); | ||
857 | emapdmars: | ||
858 | iounmap(shdev->chan_reg); | ||
859 | synchronize_rcu(); | ||
860 | emapchan: | ||
861 | kfree(shdev); | ||
862 | ealloc: | ||
863 | if (dmars) | ||
864 | release_mem_region(dmars->start, resource_size(dmars)); | ||
865 | ermrdmars: | ||
866 | release_mem_region(chan->start, resource_size(chan)); | ||
867 | |||
868 | return err; | ||
869 | } | ||
870 | |||
871 | static int __devexit sh_dmae_remove(struct platform_device *pdev) | ||
872 | { | ||
873 | struct sh_dmae_device *shdev = platform_get_drvdata(pdev); | ||
874 | struct dma_device *dma_dev = &shdev->shdma_dev.dma_dev; | ||
875 | struct resource *res; | ||
876 | int errirq = platform_get_irq(pdev, 0); | ||
877 | |||
878 | dma_async_device_unregister(dma_dev); | ||
879 | |||
880 | if (errirq > 0) | ||
881 | free_irq(errirq, shdev); | ||
882 | |||
883 | spin_lock_irq(&sh_dmae_lock); | ||
884 | list_del_rcu(&shdev->node); | ||
885 | spin_unlock_irq(&sh_dmae_lock); | ||
886 | |||
887 | pm_runtime_disable(&pdev->dev); | ||
888 | |||
889 | sh_dmae_chan_remove(shdev); | ||
890 | shdma_cleanup(&shdev->shdma_dev); | ||
891 | |||
892 | if (shdev->dmars) | ||
893 | iounmap(shdev->dmars); | ||
894 | iounmap(shdev->chan_reg); | ||
895 | |||
896 | platform_set_drvdata(pdev, NULL); | ||
897 | |||
898 | synchronize_rcu(); | ||
899 | kfree(shdev); | ||
900 | |||
901 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | ||
902 | if (res) | ||
903 | release_mem_region(res->start, resource_size(res)); | ||
904 | res = platform_get_resource(pdev, IORESOURCE_MEM, 1); | ||
905 | if (res) | ||
906 | release_mem_region(res->start, resource_size(res)); | ||
907 | |||
908 | return 0; | ||
909 | } | ||
910 | |||
911 | static struct platform_driver sh_dmae_driver = { | ||
912 | .driver = { | ||
913 | .owner = THIS_MODULE, | ||
914 | .pm = &sh_dmae_pm, | ||
915 | .name = SH_DMAE_DRV_NAME, | ||
916 | }, | ||
917 | .remove = __devexit_p(sh_dmae_remove), | ||
918 | .shutdown = sh_dmae_shutdown, | ||
919 | }; | ||
920 | |||
921 | static int __init sh_dmae_init(void) | ||
922 | { | ||
923 | /* Wire up NMI handling */ | ||
924 | int err = register_die_notifier(&sh_dmae_nmi_notifier); | ||
925 | if (err) | ||
926 | return err; | ||
927 | |||
928 | return platform_driver_probe(&sh_dmae_driver, sh_dmae_probe); | ||
929 | } | ||
930 | module_init(sh_dmae_init); | ||
931 | |||
932 | static void __exit sh_dmae_exit(void) | ||
933 | { | ||
934 | platform_driver_unregister(&sh_dmae_driver); | ||
935 | |||
936 | unregister_die_notifier(&sh_dmae_nmi_notifier); | ||
937 | } | ||
938 | module_exit(sh_dmae_exit); | ||
939 | |||
940 | MODULE_AUTHOR("Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>"); | ||
941 | MODULE_DESCRIPTION("Renesas SH DMA Engine driver"); | ||
942 | MODULE_LICENSE("GPL"); | ||
943 | MODULE_ALIAS("platform:" SH_DMAE_DRV_NAME); | ||