15 files changed, 5926 insertions, 581 deletions

diff --git a/drivers/crypto/Kconfig b/drivers/crypto/Kconfig
index e0b25de1e33..b6994751719 100644
--- a/drivers/crypto/Kconfig
+++ b/drivers/crypto/Kconfig
@@ -18,7 +18,7 @@ config CRYPTO_DEV_PADLOCK
           (so called VIA PadLock ACE, Advanced Cryptography Engine)
           that provides instructions for very fast cryptographic
           operations with supported algorithms.
-          
+
           The instructions are used only when the CPU supports them.
           Otherwise software encryption is used.
 
@@ -292,4 +292,21 @@ config CRYPTO_DEV_S5P
           Select this to offload Samsung S5PV210 or S5PC110 from AES
           algorithms execution.
 
+config CRYPTO_DEV_TEGRA_AES
+        tristate "Support for TEGRA AES hw engine"
+        depends on ARCH_TEGRA_2x_SOC || ARCH_TEGRA_3x_SOC
+        select CRYPTO_AES
+        select TEGRA_ARB_SEMAPHORE
+        help
+          TEGRA processors have AES module accelerator. Select this if you
+          want to use the TEGRA module for AES algorithms.
+
+config CRYPTO_DEV_TEGRA_SE
+        tristate "Tegra SE driver for crypto algorithms"
+        depends on ARCH_TEGRA_3x_SOC
+        select CRYPTO_AES
+        help
+          This option allows you to have support of Security Engine for crypto
+          acceleration.
+
 endif # CRYPTO_HW
diff --git a/drivers/crypto/Makefile b/drivers/crypto/Makefile
index 53ea5015531..e244cfcdd50 100644
--- a/drivers/crypto/Makefile
+++ b/drivers/crypto/Makefile
@@ -1,3 +1,5 @@
+GCOV_PROFILE := y
+
 obj-$(CONFIG_CRYPTO_DEV_PADLOCK_AES) += padlock-aes.o
 obj-$(CONFIG_CRYPTO_DEV_PADLOCK_SHA) += padlock-sha.o
 obj-$(CONFIG_CRYPTO_DEV_GEODE) += geode-aes.o
@@ -13,3 +15,5 @@ obj-$(CONFIG_CRYPTO_DEV_OMAP_SHAM) += omap-sham.o
 obj-$(CONFIG_CRYPTO_DEV_OMAP_AES) += omap-aes.o
 obj-$(CONFIG_CRYPTO_DEV_PICOXCELL) += picoxcell_crypto.o
 obj-$(CONFIG_CRYPTO_DEV_S5P) += s5p-sss.o
+obj-$(CONFIG_CRYPTO_DEV_TEGRA_AES) += tegra-aes.o
+obj-$(CONFIG_CRYPTO_DEV_TEGRA_SE) += tegra-se.o
diff --git a/drivers/crypto/amcc/crypto4xx_core.c b/drivers/crypto/amcc/crypto4xx_core.c
index 18912521a7a..1d103f997dc 100644
--- a/drivers/crypto/amcc/crypto4xx_core.c
+++ b/drivers/crypto/amcc/crypto4xx_core.c
@@ -51,6 +51,7 @@ static void crypto4xx_hw_init(struct crypto4xx_device *dev)
         union ce_io_threshold io_threshold;
         u32 rand_num;
         union ce_pe_dma_cfg pe_dma_cfg;
+        u32 device_ctrl;
 
         writel(PPC4XX_BYTE_ORDER, dev->ce_base + CRYPTO4XX_BYTE_ORDER_CFG);
         /* setup pe dma, include reset sg, pdr and pe, then release reset */
@@ -84,7 +85,9 @@ static void crypto4xx_hw_init(struct crypto4xx_device *dev)
         writel(ring_size.w, dev->ce_base + CRYPTO4XX_RING_SIZE);
         ring_ctrl.w = 0;
         writel(ring_ctrl.w, dev->ce_base + CRYPTO4XX_RING_CTRL);
-        writel(PPC4XX_DC_3DES_EN, dev->ce_base + CRYPTO4XX_DEVICE_CTRL);
+        device_ctrl = readl(dev->ce_base + CRYPTO4XX_DEVICE_CTRL);
+        device_ctrl |= PPC4XX_DC_3DES_EN;
+        writel(device_ctrl, dev->ce_base + CRYPTO4XX_DEVICE_CTRL);
         writel(dev->gdr_pa, dev->ce_base + CRYPTO4XX_GATH_RING_BASE);
         writel(dev->sdr_pa, dev->ce_base + CRYPTO4XX_SCAT_RING_BASE);
         part_ring_size.w = 0;
diff --git a/drivers/crypto/caam/caamalg.c b/drivers/crypto/caam/caamalg.c
index 676d957c22b..4159265b453 100644
--- a/drivers/crypto/caam/caamalg.c
+++ b/drivers/crypto/caam/caamalg.c
@@ -62,10 +62,22 @@
 #define CAAM_MAX_IV_LENGTH              16
 
 /* length of descriptors text */
-#define DESC_AEAD_SHARED_TEXT_LEN       4
-#define DESC_AEAD_ENCRYPT_TEXT_LEN      21
-#define DESC_AEAD_DECRYPT_TEXT_LEN      24
-#define DESC_AEAD_GIVENCRYPT_TEXT_LEN   27
+#define DESC_JOB_IO_LEN                 (CAAM_CMD_SZ * 3 + CAAM_PTR_SZ * 3)
+
+#define DESC_AEAD_BASE                  (4 * CAAM_CMD_SZ)
+#define DESC_AEAD_ENC_LEN               (DESC_AEAD_BASE + 16 * CAAM_CMD_SZ)
+#define DESC_AEAD_DEC_LEN               (DESC_AEAD_BASE + 21 * CAAM_CMD_SZ)
+#define DESC_AEAD_GIVENC_LEN            (DESC_AEAD_ENC_LEN + 7 * CAAM_CMD_SZ)
+
+#define DESC_ABLKCIPHER_BASE            (3 * CAAM_CMD_SZ)
+#define DESC_ABLKCIPHER_ENC_LEN         (DESC_ABLKCIPHER_BASE + \
+                                         20 * CAAM_CMD_SZ)
+#define DESC_ABLKCIPHER_DEC_LEN         (DESC_ABLKCIPHER_BASE + \
+                                         15 * CAAM_CMD_SZ)
+
+#define DESC_MAX_USED_BYTES             (DESC_AEAD_GIVENC_LEN + \
+                                         CAAM_MAX_KEY_SIZE)
+#define DESC_MAX_USED_LEN               (DESC_MAX_USED_BYTES / CAAM_CMD_SZ)
 
 #ifdef DEBUG
 /* for print_hex_dumps with line references */
@@ -76,30 +88,366 @@
 #define debug(format, arg...)
 #endif
 
+/* Set DK bit in class 1 operation if shared */
+static inline void append_dec_op1(u32 *desc, u32 type)
+{
+        u32 *jump_cmd, *uncond_jump_cmd;
+
+        jump_cmd = append_jump(desc, JUMP_TEST_ALL | JUMP_COND_SHRD);
+        append_operation(desc, type | OP_ALG_AS_INITFINAL |
+                         OP_ALG_DECRYPT);
+        uncond_jump_cmd = append_jump(desc, JUMP_TEST_ALL);
+        set_jump_tgt_here(desc, jump_cmd);
+        append_operation(desc, type | OP_ALG_AS_INITFINAL |
+                         OP_ALG_DECRYPT | OP_ALG_AAI_DK);
+        set_jump_tgt_here(desc, uncond_jump_cmd);
+}
+
+/*
+ * Wait for completion of class 1 key loading before allowing
+ * error propagation
+ */
+static inline void append_dec_shr_done(u32 *desc)
+{
+        u32 *jump_cmd;
+
+        jump_cmd = append_jump(desc, JUMP_CLASS_CLASS1 | JUMP_TEST_ALL);
+        set_jump_tgt_here(desc, jump_cmd);
+        append_cmd(desc, SET_OK_PROP_ERRORS | CMD_LOAD);
+}
+
+/*
+ * For aead functions, read payload and write payload,
+ * both of which are specified in req->src and req->dst
+ */
+static inline void aead_append_src_dst(u32 *desc, u32 msg_type)
+{
+        append_seq_fifo_load(desc, 0, FIFOLD_CLASS_BOTH |
+                             KEY_VLF | msg_type | FIFOLD_TYPE_LASTBOTH);
+        append_seq_fifo_store(desc, 0, FIFOST_TYPE_MESSAGE_DATA | KEY_VLF);
+}
+
+/*
+ * For aead encrypt and decrypt, read iv for both classes
+ */
+static inline void aead_append_ld_iv(u32 *desc, int ivsize)
+{
+        append_cmd(desc, CMD_SEQ_LOAD | LDST_SRCDST_BYTE_CONTEXT |
+                   LDST_CLASS_1_CCB | ivsize);
+        append_move(desc, MOVE_SRC_CLASS1CTX | MOVE_DEST_CLASS2INFIFO | ivsize);
+}
+
+/*
+ * For ablkcipher encrypt and decrypt, read from req->src and
+ * write to req->dst
+ */
+static inline void ablkcipher_append_src_dst(u32 *desc)
+{
+        append_math_add(desc, VARSEQOUTLEN, SEQINLEN, REG0, CAAM_CMD_SZ); \
+        append_math_add(desc, VARSEQINLEN, SEQINLEN, REG0, CAAM_CMD_SZ); \
+        append_seq_fifo_load(desc, 0, FIFOLD_CLASS_CLASS1 | \
+                             KEY_VLF | FIFOLD_TYPE_MSG | FIFOLD_TYPE_LAST1); \
+        append_seq_fifo_store(desc, 0, FIFOST_TYPE_MESSAGE_DATA | KEY_VLF); \
+}
+
+/*
+ * If all data, including src (with assoc and iv) or dst (with iv only) are
+ * contiguous
+ */
+#define GIV_SRC_CONTIG          1
+#define GIV_DST_CONTIG          (1 << 1)
+
 /*
  * per-session context
  */
 struct caam_ctx {
         struct device *jrdev;
-        u32 *sh_desc;
-        dma_addr_t shared_desc_phys;
+        u32 sh_desc_enc[DESC_MAX_USED_LEN];
+        u32 sh_desc_dec[DESC_MAX_USED_LEN];
+        u32 sh_desc_givenc[DESC_MAX_USED_LEN];
+        dma_addr_t sh_desc_enc_dma;
+        dma_addr_t sh_desc_dec_dma;
+        dma_addr_t sh_desc_givenc_dma;
         u32 class1_alg_type;
         u32 class2_alg_type;
         u32 alg_op;
-        u8 *key;
-        dma_addr_t key_phys;
+        u8 key[CAAM_MAX_KEY_SIZE];
+        dma_addr_t key_dma;
         unsigned int enckeylen;
         unsigned int split_key_len;
         unsigned int split_key_pad_len;
         unsigned int authsize;
 };
 
-static int aead_authenc_setauthsize(struct crypto_aead *authenc,
+static void append_key_aead(u32 *desc, struct caam_ctx *ctx,
+                            int keys_fit_inline)
+{
+        if (keys_fit_inline) {
+                append_key_as_imm(desc, ctx->key, ctx->split_key_pad_len,
+                                  ctx->split_key_len, CLASS_2 |
+                                  KEY_DEST_MDHA_SPLIT | KEY_ENC);
+                append_key_as_imm(desc, (void *)ctx->key +
+                                  ctx->split_key_pad_len, ctx->enckeylen,
+                                  ctx->enckeylen, CLASS_1 | KEY_DEST_CLASS_REG);
+        } else {
+                append_key(desc, ctx->key_dma, ctx->split_key_len, CLASS_2 |
+                           KEY_DEST_MDHA_SPLIT | KEY_ENC);
+                append_key(desc, ctx->key_dma + ctx->split_key_pad_len,
+                           ctx->enckeylen, CLASS_1 | KEY_DEST_CLASS_REG);
+        }
+}
+
+static void init_sh_desc_key_aead(u32 *desc, struct caam_ctx *ctx,
+                                  int keys_fit_inline)
+{
+        u32 *key_jump_cmd;
+
+        init_sh_desc(desc, HDR_SHARE_WAIT);
+
+        /* Skip if already shared */
+        key_jump_cmd = append_jump(desc, JUMP_JSL | JUMP_TEST_ALL |
+                                   JUMP_COND_SHRD);
+
+        append_key_aead(desc, ctx, keys_fit_inline);
+
+        set_jump_tgt_here(desc, key_jump_cmd);
+
+        /* Propagate errors from shared to job descriptor */
+        append_cmd(desc, SET_OK_PROP_ERRORS | CMD_LOAD);
+}
+
+static int aead_set_sh_desc(struct crypto_aead *aead)
+{
+        struct aead_tfm *tfm = &aead->base.crt_aead;
+        struct caam_ctx *ctx = crypto_aead_ctx(aead);
+        struct device *jrdev = ctx->jrdev;
+        bool keys_fit_inline = 0;
+        u32 *key_jump_cmd, *jump_cmd;
+        u32 geniv, moveiv;
+        u32 *desc;
+
+        if (!ctx->enckeylen || !ctx->authsize)
+                return 0;
+
+        /*
+         * Job Descriptor and Shared Descriptors
+         * must all fit into the 64-word Descriptor h/w Buffer
+         */
+        if (DESC_AEAD_ENC_LEN + DESC_JOB_IO_LEN +
+            ctx->split_key_pad_len + ctx->enckeylen <=
+            CAAM_DESC_BYTES_MAX)
+                keys_fit_inline = 1;
+
+        /* aead_encrypt shared descriptor */
+        desc = ctx->sh_desc_enc;
+
+        init_sh_desc_key_aead(desc, ctx, keys_fit_inline);
+
+        /* Class 2 operation */
+        append_operation(desc, ctx->class2_alg_type |
+                         OP_ALG_AS_INITFINAL | OP_ALG_ENCRYPT);
+
+        /* cryptlen = seqoutlen - authsize */
+        append_math_sub_imm_u32(desc, REG3, SEQOUTLEN, IMM, ctx->authsize);
+
+        /* assoclen + cryptlen = seqinlen - ivsize */
+        append_math_sub_imm_u32(desc, REG2, SEQINLEN, IMM, tfm->ivsize);
+
+        /* assoclen + cryptlen = (assoclen + cryptlen) - cryptlen */
+        append_math_sub(desc, VARSEQINLEN, REG2, REG3, CAAM_CMD_SZ);
+
+        /* read assoc before reading payload */
+        append_seq_fifo_load(desc, 0, FIFOLD_CLASS_CLASS2 | FIFOLD_TYPE_MSG |
+                             KEY_VLF);
+        aead_append_ld_iv(desc, tfm->ivsize);
+
+        /* Class 1 operation */
+        append_operation(desc, ctx->class1_alg_type |
+                         OP_ALG_AS_INITFINAL | OP_ALG_ENCRYPT);
+
+        /* Read and write cryptlen bytes */
+        append_math_add(desc, VARSEQINLEN, ZERO, REG3, CAAM_CMD_SZ);
+        append_math_add(desc, VARSEQOUTLEN, ZERO, REG3, CAAM_CMD_SZ);
+        aead_append_src_dst(desc, FIFOLD_TYPE_MSG1OUT2);
+
+        /* Write ICV */
+        append_seq_store(desc, ctx->authsize, LDST_CLASS_2_CCB |
+                         LDST_SRCDST_BYTE_CONTEXT);
+
+        ctx->sh_desc_enc_dma = dma_map_single(jrdev, desc,
+                                              desc_bytes(desc),
+                                              DMA_TO_DEVICE);
+        if (dma_mapping_error(jrdev, ctx->sh_desc_enc_dma)) {
+                dev_err(jrdev, "unable to map shared descriptor\n");
+                return -ENOMEM;
+        }
+#ifdef DEBUG
+        print_hex_dump(KERN_ERR, "aead enc shdesc@"xstr(__LINE__)": ",
+                       DUMP_PREFIX_ADDRESS, 16, 4, desc,
+                       desc_bytes(desc), 1);
+#endif
+
+        /*
+         * Job Descriptor and Shared Descriptors
+         * must all fit into the 64-word Descriptor h/w Buffer
+         */
+        if (DESC_AEAD_DEC_LEN + DESC_JOB_IO_LEN +
+            ctx->split_key_pad_len + ctx->enckeylen <=
+            CAAM_DESC_BYTES_MAX)
+                keys_fit_inline = 1;
+
+        desc = ctx->sh_desc_dec;
+
+        /* aead_decrypt shared descriptor */
+        init_sh_desc(desc, HDR_SHARE_WAIT);
+
+        /* Skip if already shared */
+        key_jump_cmd = append_jump(desc, JUMP_JSL | JUMP_TEST_ALL |
+                                   JUMP_COND_SHRD);
+
+        append_key_aead(desc, ctx, keys_fit_inline);
+
+        /* Only propagate error immediately if shared */
+        jump_cmd = append_jump(desc, JUMP_TEST_ALL);
+        set_jump_tgt_here(desc, key_jump_cmd);
+        append_cmd(desc, SET_OK_PROP_ERRORS | CMD_LOAD);
+        set_jump_tgt_here(desc, jump_cmd);
+
+        /* Class 2 operation */
+        append_operation(desc, ctx->class2_alg_type |
+                         OP_ALG_AS_INITFINAL | OP_ALG_DECRYPT | OP_ALG_ICV_ON);
+
+        /* assoclen + cryptlen = seqinlen - ivsize */
+        append_math_sub_imm_u32(desc, REG3, SEQINLEN, IMM,
+                                ctx->authsize + tfm->ivsize)
+        /* assoclen = (assoclen + cryptlen) - cryptlen */
+        append_math_sub(desc, REG2, SEQOUTLEN, REG0, CAAM_CMD_SZ);
+        append_math_sub(desc, VARSEQINLEN, REG3, REG2, CAAM_CMD_SZ);
+
+        /* read assoc before reading payload */
+        append_seq_fifo_load(desc, 0, FIFOLD_CLASS_CLASS2 | FIFOLD_TYPE_MSG |
+                             KEY_VLF);
+
+        aead_append_ld_iv(desc, tfm->ivsize);
+
+        append_dec_op1(desc, ctx->class1_alg_type);
+
+        /* Read and write cryptlen bytes */
+        append_math_add(desc, VARSEQINLEN, ZERO, REG2, CAAM_CMD_SZ);
+        append_math_add(desc, VARSEQOUTLEN, ZERO, REG2, CAAM_CMD_SZ);
+        aead_append_src_dst(desc, FIFOLD_TYPE_MSG);
+
+        /* Load ICV */
+        append_seq_fifo_load(desc, ctx->authsize, FIFOLD_CLASS_CLASS2 |
+                             FIFOLD_TYPE_LAST2 | FIFOLD_TYPE_ICV);
+        append_dec_shr_done(desc);
+
+        ctx->sh_desc_dec_dma = dma_map_single(jrdev, desc,
+                                              desc_bytes(desc),
+                                              DMA_TO_DEVICE);
+        if (dma_mapping_error(jrdev, ctx->sh_desc_dec_dma)) {
+                dev_err(jrdev, "unable to map shared descriptor\n");
+                return -ENOMEM;
+        }
+#ifdef DEBUG
+        print_hex_dump(KERN_ERR, "aead dec shdesc@"xstr(__LINE__)": ",
+                       DUMP_PREFIX_ADDRESS, 16, 4, desc,
+                       desc_bytes(desc), 1);
+#endif
+
+        /*
+         * Job Descriptor and Shared Descriptors
+         * must all fit into the 64-word Descriptor h/w Buffer
+         */
+        if (DESC_AEAD_GIVENC_LEN + DESC_JOB_IO_LEN +
+            ctx->split_key_pad_len + ctx->enckeylen <=
+            CAAM_DESC_BYTES_MAX)
+                keys_fit_inline = 1;
+
+        /* aead_givencrypt shared descriptor */
+        desc = ctx->sh_desc_givenc;
+
+        init_sh_desc_key_aead(desc, ctx, keys_fit_inline);
+
+        /* Generate IV */
+        geniv = NFIFOENTRY_STYPE_PAD | NFIFOENTRY_DEST_DECO |
+                NFIFOENTRY_DTYPE_MSG | NFIFOENTRY_LC1 |
+                NFIFOENTRY_PTYPE_RND | (tfm->ivsize << NFIFOENTRY_DLEN_SHIFT);
+        append_load_imm_u32(desc, geniv, LDST_CLASS_IND_CCB |
+                            LDST_SRCDST_WORD_INFO_FIFO | LDST_IMM);
+        append_cmd(desc, CMD_LOAD | DISABLE_AUTO_INFO_FIFO);
+        append_move(desc, MOVE_SRC_INFIFO |
+                    MOVE_DEST_CLASS1CTX | (tfm->ivsize << MOVE_LEN_SHIFT));
+        append_cmd(desc, CMD_LOAD | ENABLE_AUTO_INFO_FIFO);
+
+        /* Copy IV to class 1 context */
+        append_move(desc, MOVE_SRC_CLASS1CTX |
+                    MOVE_DEST_OUTFIFO | (tfm->ivsize << MOVE_LEN_SHIFT));
+
+        /* Return to encryption */
+        append_operation(desc, ctx->class2_alg_type |
+                         OP_ALG_AS_INITFINAL | OP_ALG_ENCRYPT);
+
+        /* ivsize + cryptlen = seqoutlen - authsize */
+        append_math_sub_imm_u32(desc, REG3, SEQOUTLEN, IMM, ctx->authsize);
+
+        /* assoclen = seqinlen - (ivsize + cryptlen) */
+        append_math_sub(desc, VARSEQINLEN, SEQINLEN, REG3, CAAM_CMD_SZ);
+
+        /* read assoc before reading payload */
+        append_seq_fifo_load(desc, 0, FIFOLD_CLASS_CLASS2 | FIFOLD_TYPE_MSG |
+                             KEY_VLF);
+
+        /* Copy iv from class 1 ctx to class 2 fifo*/
+        moveiv = NFIFOENTRY_STYPE_OFIFO | NFIFOENTRY_DEST_CLASS2 |
+                 NFIFOENTRY_DTYPE_MSG | (tfm->ivsize << NFIFOENTRY_DLEN_SHIFT);
+        append_load_imm_u32(desc, moveiv, LDST_CLASS_IND_CCB |
+                            LDST_SRCDST_WORD_INFO_FIFO | LDST_IMM);
+        append_load_imm_u32(desc, tfm->ivsize, LDST_CLASS_2_CCB |
+                            LDST_SRCDST_WORD_DATASZ_REG | LDST_IMM);
+
+        /* Class 1 operation */
+        append_operation(desc, ctx->class1_alg_type |
+                         OP_ALG_AS_INITFINAL | OP_ALG_ENCRYPT);
+
+        /* Will write ivsize + cryptlen */
+        append_math_add(desc, VARSEQOUTLEN, SEQINLEN, REG0, CAAM_CMD_SZ);
+
+        /* Not need to reload iv */
+        append_seq_fifo_load(desc, tfm->ivsize,
+                             FIFOLD_CLASS_SKIP);
+
+        /* Will read cryptlen */
+        append_math_add(desc, VARSEQINLEN, SEQINLEN, REG0, CAAM_CMD_SZ);
+        aead_append_src_dst(desc, FIFOLD_TYPE_MSG1OUT2);
+
+        /* Write ICV */
+        append_seq_store(desc, ctx->authsize, LDST_CLASS_2_CCB |
+                         LDST_SRCDST_BYTE_CONTEXT);
+
+        ctx->sh_desc_givenc_dma = dma_map_single(jrdev, desc,
+                                                 desc_bytes(desc),
+                                                 DMA_TO_DEVICE);
+        if (dma_mapping_error(jrdev, ctx->sh_desc_givenc_dma)) {
+                dev_err(jrdev, "unable to map shared descriptor\n");
+                return -ENOMEM;
+        }
+#ifdef DEBUG
+        print_hex_dump(KERN_ERR, "aead givenc shdesc@"xstr(__LINE__)": ",
+                       DUMP_PREFIX_ADDRESS, 16, 4, desc,
+                       desc_bytes(desc), 1);
+#endif
+
+        return 0;
+}
+
+static int aead_setauthsize(struct crypto_aead *authenc,
                                     unsigned int authsize)
 {
         struct caam_ctx *ctx = crypto_aead_ctx(authenc);
 
         ctx->authsize = authsize;
+        aead_set_sh_desc(authenc);
 
         return 0;
 }
@@ -117,6 +465,7 @@ static void split_key_done(struct device *dev, u32 *desc, u32 err,
 #ifdef DEBUG
         dev_err(dev, "%s %d: err 0x%x\n", __func__, __LINE__, err);
 #endif
+
         if (err) {
                 char tmp[CAAM_ERROR_STR_MAX];
 
@@ -220,73 +569,7 @@ static u32 gen_split_key(struct caam_ctx *ctx, const u8 *key_in, u32 authkeylen)
         return ret;
 }
 
-static int build_sh_desc_ipsec(struct caam_ctx *ctx)
-{
-        struct device *jrdev = ctx->jrdev;
-        u32 *sh_desc;
-        u32 *jump_cmd;
-        bool keys_fit_inline = 0;
-
-        /*
-         * largest Job Descriptor and its Shared Descriptor
-         * must both fit into the 64-word Descriptor h/w Buffer
-         */
-        if ((DESC_AEAD_GIVENCRYPT_TEXT_LEN +
-             DESC_AEAD_SHARED_TEXT_LEN) * CAAM_CMD_SZ +
-            ctx->split_key_pad_len + ctx->enckeylen <= CAAM_DESC_BYTES_MAX)
-                keys_fit_inline = 1;
-
-        /* build shared descriptor for this session */
-        sh_desc = kmalloc(CAAM_CMD_SZ * DESC_AEAD_SHARED_TEXT_LEN +
-                          (keys_fit_inline ?
-                           ctx->split_key_pad_len + ctx->enckeylen :
-                           CAAM_PTR_SZ * 2), GFP_DMA | GFP_KERNEL);
-        if (!sh_desc) {
-                dev_err(jrdev, "could not allocate shared descriptor\n");
-                return -ENOMEM;
-        }
-
-        init_sh_desc(sh_desc, HDR_SAVECTX | HDR_SHARE_SERIAL);
-
-        jump_cmd = append_jump(sh_desc, CLASS_BOTH | JUMP_TEST_ALL |
-                               JUMP_COND_SHRD | JUMP_COND_SELF);
-
-        /*
-         * process keys, starting with class 2/authentication.
-         */
-        if (keys_fit_inline) {
-                append_key_as_imm(sh_desc, ctx->key, ctx->split_key_pad_len,
-                                  ctx->split_key_len,
-                                  CLASS_2 | KEY_DEST_MDHA_SPLIT | KEY_ENC);
-
-                append_key_as_imm(sh_desc, (void *)ctx->key +
-                                  ctx->split_key_pad_len, ctx->enckeylen,
-                                  ctx->enckeylen, CLASS_1 | KEY_DEST_CLASS_REG);
-        } else {
-                append_key(sh_desc, ctx->key_phys, ctx->split_key_len, CLASS_2 |
-                           KEY_DEST_MDHA_SPLIT | KEY_ENC);
-                append_key(sh_desc, ctx->key_phys + ctx->split_key_pad_len,
-                           ctx->enckeylen, CLASS_1 | KEY_DEST_CLASS_REG);
-        }
-
-        /* update jump cmd now that we are at the jump target */
-        set_jump_tgt_here(sh_desc, jump_cmd);
-
-        ctx->shared_desc_phys = dma_map_single(jrdev, sh_desc,
-                                               desc_bytes(sh_desc),
-                                               DMA_TO_DEVICE);
-        if (dma_mapping_error(jrdev, ctx->shared_desc_phys)) {
-                dev_err(jrdev, "unable to map shared descriptor\n");
-                kfree(sh_desc);
-                return -ENOMEM;
-        }
-
-        ctx->sh_desc = sh_desc;
-
-        return 0;
-}
-
-static int aead_authenc_setkey(struct crypto_aead *aead,
+static int aead_setkey(struct crypto_aead *aead,
                                const u8 *key, unsigned int keylen)
 {
         /* Sizes for MDHA pads (*not* keys): MD5, SHA1, 224, 256, 384, 512 */
@@ -326,27 +609,19 @@ static int aead_authenc_setkey(struct crypto_aead *aead,
         print_hex_dump(KERN_ERR, "key in @"xstr(__LINE__)": ",
                        DUMP_PREFIX_ADDRESS, 16, 4, key, keylen, 1);
 #endif
-        ctx->key = kmalloc(ctx->split_key_pad_len + enckeylen,
-                           GFP_KERNEL | GFP_DMA);
-        if (!ctx->key) {
-                dev_err(jrdev, "could not allocate key output memory\n");
-                return -ENOMEM;
-        }
 
         ret = gen_split_key(ctx, key, authkeylen);
         if (ret) {
-                kfree(ctx->key);
                 goto badkey;
         }
 
         /* postpend encryption key to auth split key */
         memcpy(ctx->key + ctx->split_key_pad_len, key + authkeylen, enckeylen);
 
-        ctx->key_phys = dma_map_single(jrdev, ctx->key, ctx->split_key_pad_len +
+        ctx->key_dma = dma_map_single(jrdev, ctx->key, ctx->split_key_pad_len +
                                        enckeylen, DMA_TO_DEVICE);
-        if (dma_mapping_error(jrdev, ctx->key_phys)) {
+        if (dma_mapping_error(jrdev, ctx->key_dma)) {
                 dev_err(jrdev, "unable to map key i/o memory\n");
-                kfree(ctx->key);
                 return -ENOMEM;
         }
 #ifdef DEBUG
@@ -357,11 +632,10 @@ static int aead_authenc_setkey(struct crypto_aead *aead,
 
         ctx->enckeylen = enckeylen;
 
-        ret = build_sh_desc_ipsec(ctx);
+        ret = aead_set_sh_desc(aead);
         if (ret) {
-                dma_unmap_single(jrdev, ctx->key_phys, ctx->split_key_pad_len +
+                dma_unmap_single(jrdev, ctx->key_dma, ctx->split_key_pad_len +
                                  enckeylen, DMA_TO_DEVICE);
-                kfree(ctx->key);
         }
 
         return ret;
@@ -370,6 +644,119 @@ badkey:
         return -EINVAL;
 }
 
+static int ablkcipher_setkey(struct crypto_ablkcipher *ablkcipher,
+                             const u8 *key, unsigned int keylen)
+{
+        struct caam_ctx *ctx = crypto_ablkcipher_ctx(ablkcipher);
+        struct ablkcipher_tfm *tfm = &ablkcipher->base.crt_ablkcipher;
+        struct device *jrdev = ctx->jrdev;
+        int ret = 0;
+        u32 *key_jump_cmd, *jump_cmd;
+        u32 *desc;
+
+#ifdef DEBUG
+        print_hex_dump(KERN_ERR, "key in @"xstr(__LINE__)": ",
+                       DUMP_PREFIX_ADDRESS, 16, 4, key, keylen, 1);
+#endif
+
+        memcpy(ctx->key, key, keylen);
+        ctx->key_dma = dma_map_single(jrdev, ctx->key, keylen,
+                                      DMA_TO_DEVICE);
+        if (dma_mapping_error(jrdev, ctx->key_dma)) {
+                dev_err(jrdev, "unable to map key i/o memory\n");
+                return -ENOMEM;
+        }
+        ctx->enckeylen = keylen;
+
+        /* ablkcipher_encrypt shared descriptor */
+        desc = ctx->sh_desc_enc;
+        init_sh_desc(desc, HDR_SHARE_WAIT);
+        /* Skip if already shared */
+        key_jump_cmd = append_jump(desc, JUMP_JSL | JUMP_TEST_ALL |
+                                   JUMP_COND_SHRD);
+
+        /* Load class1 key only */
+        append_key_as_imm(desc, (void *)ctx->key, ctx->enckeylen,
+                          ctx->enckeylen, CLASS_1 |
+                          KEY_DEST_CLASS_REG);
+
+        set_jump_tgt_here(desc, key_jump_cmd);
+
+        /* Propagate errors from shared to job descriptor */
+        append_cmd(desc, SET_OK_PROP_ERRORS | CMD_LOAD);
+
+        /* Load iv */
+        append_cmd(desc, CMD_SEQ_LOAD | LDST_SRCDST_BYTE_CONTEXT |
+                   LDST_CLASS_1_CCB | tfm->ivsize);
+
+        /* Load operation */
+        append_operation(desc, ctx->class1_alg_type |
+                         OP_ALG_AS_INITFINAL | OP_ALG_ENCRYPT);
+
+        /* Perform operation */
+        ablkcipher_append_src_dst(desc);
+
+        ctx->sh_desc_enc_dma = dma_map_single(jrdev, desc,
+                                              desc_bytes(desc),
+                                              DMA_TO_DEVICE);
+        if (dma_mapping_error(jrdev, ctx->sh_desc_enc_dma)) {
+                dev_err(jrdev, "unable to map shared descriptor\n");
+                return -ENOMEM;
+        }
+#ifdef DEBUG
+        print_hex_dump(KERN_ERR, "ablkcipher enc shdesc@"xstr(__LINE__)": ",
+                       DUMP_PREFIX_ADDRESS, 16, 4, desc,
+                       desc_bytes(desc), 1);
+#endif
+        /* ablkcipher_decrypt shared descriptor */
+        desc = ctx->sh_desc_dec;
+
+        init_sh_desc(desc, HDR_SHARE_WAIT);
+        /* Skip if already shared */
+        key_jump_cmd = append_jump(desc, JUMP_JSL | JUMP_TEST_ALL |
+                                   JUMP_COND_SHRD);
+
+        /* Load class1 key only */
+        append_key_as_imm(desc, (void *)ctx->key, ctx->enckeylen,
+                          ctx->enckeylen, CLASS_1 |
+                          KEY_DEST_CLASS_REG);
+
+        /* For aead, only propagate error immediately if shared */
+        jump_cmd = append_jump(desc, JUMP_TEST_ALL);
+        set_jump_tgt_here(desc, key_jump_cmd);
+        append_cmd(desc, SET_OK_PROP_ERRORS | CMD_LOAD);
+        set_jump_tgt_here(desc, jump_cmd);
+
+        /* load IV */
+        append_cmd(desc, CMD_SEQ_LOAD | LDST_SRCDST_BYTE_CONTEXT |
+                   LDST_CLASS_1_CCB | tfm->ivsize);
+
+        /* Choose operation */
+        append_dec_op1(desc, ctx->class1_alg_type);
+
+        /* Perform operation */
+        ablkcipher_append_src_dst(desc);
+
+        /* Wait for key to load before allowing propagating error */
+        append_dec_shr_done(desc);
+
+        ctx->sh_desc_dec_dma = dma_map_single(jrdev, desc,
+                                              desc_bytes(desc),
+                                              DMA_TO_DEVICE);
+        if (dma_mapping_error(jrdev, ctx->sh_desc_enc_dma)) {
+                dev_err(jrdev, "unable to map shared descriptor\n");
+                return -ENOMEM;
+        }
+
+#ifdef DEBUG
+        print_hex_dump(KERN_ERR, "ablkcipher dec shdesc@"xstr(__LINE__)": ",
+                       DUMP_PREFIX_ADDRESS, 16, 4, desc,
+                       desc_bytes(desc), 1);
+#endif
+
+        return ret;
+}
+
 struct link_tbl_entry {
         u64 ptr;
         u32 len;
@@ -379,64 +766,109 @@ struct link_tbl_entry {
 };
 
 /*
- * ipsec_esp_edesc - s/w-extended ipsec_esp descriptor
+ * aead_edesc - s/w-extended aead descriptor
+ * @assoc_nents: number of segments in associated data (SPI+Seq) scatterlist
  * @src_nents: number of segments in input scatterlist
  * @dst_nents: number of segments in output scatterlist
- * @assoc_nents: number of segments in associated data (SPI+Seq) scatterlist
+ * @iv_dma: dma address of iv for checking continuity and link table
  * @desc: h/w descriptor (variable length; must not exceed MAX_CAAM_DESCSIZE)
  * @link_tbl_bytes: length of dma mapped link_tbl space
  * @link_tbl_dma: bus physical mapped address of h/w link table
  * @hw_desc: the h/w job descriptor followed by any referenced link tables
  */
-struct ipsec_esp_edesc {
+struct aead_edesc {
         int assoc_nents;
         int src_nents;
         int dst_nents;
+        dma_addr_t iv_dma;
         int link_tbl_bytes;
         dma_addr_t link_tbl_dma;
         struct link_tbl_entry *link_tbl;
         u32 hw_desc[0];
 };
 
-static void ipsec_esp_unmap(struct device *dev,
-                            struct ipsec_esp_edesc *edesc,
-                            struct aead_request *areq)
-{
-        dma_unmap_sg(dev, areq->assoc, edesc->assoc_nents, DMA_TO_DEVICE);
+/*
+ * ablkcipher_edesc - s/w-extended ablkcipher descriptor
+ * @src_nents: number of segments in input scatterlist
+ * @dst_nents: number of segments in output scatterlist
+ * @iv_dma: dma address of iv for checking continuity and link table
+ * @desc: h/w descriptor (variable length; must not exceed MAX_CAAM_DESCSIZE)
+ * @link_tbl_bytes: length of dma mapped link_tbl space
+ * @link_tbl_dma: bus physical mapped address of h/w link table
+ * @hw_desc: the h/w job descriptor followed by any referenced link tables
+ */
+struct ablkcipher_edesc {
+        int src_nents;
+        int dst_nents;
+        dma_addr_t iv_dma;
+        int link_tbl_bytes;
+        dma_addr_t link_tbl_dma;
+        struct link_tbl_entry *link_tbl;
+        u32 hw_desc[0];
+};
 
-        if (unlikely(areq->dst != areq->src)) {
-                dma_unmap_sg(dev, areq->src, edesc->src_nents,
-                             DMA_TO_DEVICE);
-                dma_unmap_sg(dev, areq->dst, edesc->dst_nents,
-                             DMA_FROM_DEVICE);
+static void caam_unmap(struct device *dev, struct scatterlist *src,
+                       struct scatterlist *dst, int src_nents, int dst_nents,
+                       dma_addr_t iv_dma, int ivsize, dma_addr_t link_tbl_dma,
+                       int link_tbl_bytes)
+{
+        if (unlikely(dst != src)) {
+                dma_unmap_sg(dev, src, src_nents, DMA_TO_DEVICE);
+                dma_unmap_sg(dev, dst, dst_nents, DMA_FROM_DEVICE);
         } else {
-                dma_unmap_sg(dev, areq->src, edesc->src_nents,
-                             DMA_BIDIRECTIONAL);
+                dma_unmap_sg(dev, src, src_nents, DMA_BIDIRECTIONAL);
         }
 
-        if (edesc->link_tbl_bytes)
-                dma_unmap_single(dev, edesc->link_tbl_dma,
-                                 edesc->link_tbl_bytes,
+        if (iv_dma)
+                dma_unmap_single(dev, iv_dma, ivsize, DMA_TO_DEVICE);
+        if (link_tbl_bytes)
+                dma_unmap_single(dev, link_tbl_dma, link_tbl_bytes,
                                  DMA_TO_DEVICE);
 }
 
-/*
- * ipsec_esp descriptor callbacks
- */
-static void ipsec_esp_encrypt_done(struct device *jrdev, u32 *desc, u32 err,
+static void aead_unmap(struct device *dev,
+                       struct aead_edesc *edesc,
+                       struct aead_request *req)
+{
+        struct crypto_aead *aead = crypto_aead_reqtfm(req);
+        int ivsize = crypto_aead_ivsize(aead);
+
+        dma_unmap_sg(dev, req->assoc, edesc->assoc_nents, DMA_TO_DEVICE);
+
+        caam_unmap(dev, req->src, req->dst,
+                   edesc->src_nents, edesc->dst_nents,
+                   edesc->iv_dma, ivsize, edesc->link_tbl_dma,
+                   edesc->link_tbl_bytes);
+}
+
+static void ablkcipher_unmap(struct device *dev,
+                             struct ablkcipher_edesc *edesc,
+                             struct ablkcipher_request *req)
+{
+        struct crypto_ablkcipher *ablkcipher = crypto_ablkcipher_reqtfm(req);
+        int ivsize = crypto_ablkcipher_ivsize(ablkcipher);
+
+        caam_unmap(dev, req->src, req->dst,
+                   edesc->src_nents, edesc->dst_nents,
+                   edesc->iv_dma, ivsize, edesc->link_tbl_dma,
+                   edesc->link_tbl_bytes);
+}
+
+static void aead_encrypt_done(struct device *jrdev, u32 *desc, u32 err,
                                    void *context)
 {
-        struct aead_request *areq = context;
-        struct ipsec_esp_edesc *edesc;
+        struct aead_request *req = context;
+        struct aead_edesc *edesc;
 #ifdef DEBUG
-        struct crypto_aead *aead = crypto_aead_reqtfm(areq);
-        int ivsize = crypto_aead_ivsize(aead);
+        struct crypto_aead *aead = crypto_aead_reqtfm(req);
         struct caam_ctx *ctx = crypto_aead_ctx(aead);
+        int ivsize = crypto_aead_ivsize(aead);
 
         dev_err(jrdev, "%s %d: err 0x%x\n", __func__, __LINE__, err);
 #endif
-        edesc = (struct ipsec_esp_edesc *)((char *)desc -
-                 offsetof(struct ipsec_esp_edesc, hw_desc));
+
+        edesc = (struct aead_edesc *)((char *)desc -
+                 offsetof(struct aead_edesc, hw_desc));
 
         if (err) {
                 char tmp[CAAM_ERROR_STR_MAX];
@@ -444,39 +876,50 @@ static void ipsec_esp_encrypt_done(struct device *jrdev, u32 *desc, u32 err,
                 dev_err(jrdev, "%08x: %s\n", err, caam_jr_strstatus(tmp, err));
         }
 
-        ipsec_esp_unmap(jrdev, edesc, areq);
+        aead_unmap(jrdev, edesc, req);
 
 #ifdef DEBUG
         print_hex_dump(KERN_ERR, "assoc  @"xstr(__LINE__)": ",
-                       DUMP_PREFIX_ADDRESS, 16, 4, sg_virt(areq->assoc),
-                       areq->assoclen , 1);
+                       DUMP_PREFIX_ADDRESS, 16, 4, sg_virt(req->assoc),
+                       req->assoclen , 1);
         print_hex_dump(KERN_ERR, "dstiv  @"xstr(__LINE__)": ",
-                       DUMP_PREFIX_ADDRESS, 16, 4, sg_virt(areq->src) - ivsize,
+                       DUMP_PREFIX_ADDRESS, 16, 4, sg_virt(req->src) - ivsize,
                        edesc->src_nents ? 100 : ivsize, 1);
         print_hex_dump(KERN_ERR, "dst    @"xstr(__LINE__)": ",
-                       DUMP_PREFIX_ADDRESS, 16, 4, sg_virt(areq->src),
-                       edesc->src_nents ? 100 : areq->cryptlen +
+                       DUMP_PREFIX_ADDRESS, 16, 4, sg_virt(req->src),
+                       edesc->src_nents ? 100 : req->cryptlen +
                        ctx->authsize + 4, 1);
 #endif
 
         kfree(edesc);
 
-        aead_request_complete(areq, err);
+        aead_request_complete(req, err);
 }
 
-static void ipsec_esp_decrypt_done(struct device *jrdev, u32 *desc, u32 err,
+static void aead_decrypt_done(struct device *jrdev, u32 *desc, u32 err,
                                    void *context)
 {
-        struct aead_request *areq = context;
-        struct ipsec_esp_edesc *edesc;
+        struct aead_request *req = context;
+        struct aead_edesc *edesc;
 #ifdef DEBUG
-        struct crypto_aead *aead = crypto_aead_reqtfm(areq);
+        struct crypto_aead *aead = crypto_aead_reqtfm(req);
         struct caam_ctx *ctx = crypto_aead_ctx(aead);
+        int ivsize = crypto_aead_ivsize(aead);
 
         dev_err(jrdev, "%s %d: err 0x%x\n", __func__, __LINE__, err);
 #endif
-        edesc = (struct ipsec_esp_edesc *)((char *)desc -
-                 offsetof(struct ipsec_esp_edesc, hw_desc));
+
+        edesc = (struct aead_edesc *)((char *)desc -
+                 offsetof(struct aead_edesc, hw_desc));
+
+#ifdef DEBUG
+        print_hex_dump(KERN_ERR, "dstiv  @"xstr(__LINE__)": ",
+                       DUMP_PREFIX_ADDRESS, 16, 4, req->iv,
+                       ivsize, 1);
+        print_hex_dump(KERN_ERR, "dst    @"xstr(__LINE__)": ",
+                       DUMP_PREFIX_ADDRESS, 16, 4, sg_virt(req->dst),
+                       req->cryptlen, 1);
+#endif
 
         if (err) {
                 char tmp[CAAM_ERROR_STR_MAX];
@@ -484,7 +927,7 @@ static void ipsec_esp_decrypt_done(struct device *jrdev, u32 *desc, u32 err,
                 dev_err(jrdev, "%08x: %s\n", err, caam_jr_strstatus(tmp, err));
         }
 
-        ipsec_esp_unmap(jrdev, edesc, areq);
+        aead_unmap(jrdev, edesc, req);
 
         /*
          * verify hw auth check passed else return -EBADMSG
@@ -495,255 +938,413 @@ static void ipsec_esp_decrypt_done(struct device *jrdev, u32 *desc, u32 err,
 #ifdef DEBUG
         print_hex_dump(KERN_ERR, "iphdrout@"xstr(__LINE__)": ",
                        DUMP_PREFIX_ADDRESS, 16, 4,
-                       ((char *)sg_virt(areq->assoc) - sizeof(struct iphdr)),
-                       sizeof(struct iphdr) + areq->assoclen +
-                       ((areq->cryptlen > 1500) ? 1500 : areq->cryptlen) +
+                       ((char *)sg_virt(req->assoc) - sizeof(struct iphdr)),
+                       sizeof(struct iphdr) + req->assoclen +
+                       ((req->cryptlen > 1500) ? 1500 : req->cryptlen) +
                        ctx->authsize + 36, 1);
         if (!err && edesc->link_tbl_bytes) {
-                struct scatterlist *sg = sg_last(areq->src, edesc->src_nents);
+                struct scatterlist *sg = sg_last(req->src, edesc->src_nents);
                 print_hex_dump(KERN_ERR, "sglastout@"xstr(__LINE__)": ",
                                DUMP_PREFIX_ADDRESS, 16, 4, sg_virt(sg),
                         sg->length + ctx->authsize + 16, 1);
         }
 #endif
+
         kfree(edesc);
 
-        aead_request_complete(areq, err);
+        aead_request_complete(req, err);
+}
+
+static void ablkcipher_encrypt_done(struct device *jrdev, u32 *desc, u32 err,
+                                   void *context)
+{
+        struct ablkcipher_request *req = context;
+        struct ablkcipher_edesc *edesc;
+#ifdef DEBUG
+        struct crypto_ablkcipher *ablkcipher = crypto_ablkcipher_reqtfm(req);
+        int ivsize = crypto_ablkcipher_ivsize(ablkcipher);
+
+        dev_err(jrdev, "%s %d: err 0x%x\n", __func__, __LINE__, err);
+#endif
+
+        edesc = (struct ablkcipher_edesc *)((char *)desc -
+                 offsetof(struct ablkcipher_edesc, hw_desc));
+
+        if (err) {
+                char tmp[CAAM_ERROR_STR_MAX];
+
+                dev_err(jrdev, "%08x: %s\n", err, caam_jr_strstatus(tmp, err));
+        }
+
+#ifdef DEBUG
+        print_hex_dump(KERN_ERR, "dstiv  @"xstr(__LINE__)": ",
+                       DUMP_PREFIX_ADDRESS, 16, 4, req->info,
+                       edesc->src_nents > 1 ? 100 : ivsize, 1);
+        print_hex_dump(KERN_ERR, "dst    @"xstr(__LINE__)": ",
+                       DUMP_PREFIX_ADDRESS, 16, 4, sg_virt(req->src),
+                       edesc->dst_nents > 1 ? 100 : req->nbytes, 1);
+#endif
+
+        ablkcipher_unmap(jrdev, edesc, req);
+        kfree(edesc);
+
+        ablkcipher_request_complete(req, err);
+}
+
+static void ablkcipher_decrypt_done(struct device *jrdev, u32 *desc, u32 err,
+                                    void *context)
+{
+        struct ablkcipher_request *req = context;
+        struct ablkcipher_edesc *edesc;
+#ifdef DEBUG
+        struct crypto_ablkcipher *ablkcipher = crypto_ablkcipher_reqtfm(req);
+        int ivsize = crypto_ablkcipher_ivsize(ablkcipher);
+
+        dev_err(jrdev, "%s %d: err 0x%x\n", __func__, __LINE__, err);
+#endif
+
+        edesc = (struct ablkcipher_edesc *)((char *)desc -
+                 offsetof(struct ablkcipher_edesc, hw_desc));
+        if (err) {
+                char tmp[CAAM_ERROR_STR_MAX];
+
+                dev_err(jrdev, "%08x: %s\n", err, caam_jr_strstatus(tmp, err));
+        }
+
+#ifdef DEBUG
+        print_hex_dump(KERN_ERR, "dstiv  @"xstr(__LINE__)": ",
+                       DUMP_PREFIX_ADDRESS, 16, 4, req->info,
+                       ivsize, 1);
+        print_hex_dump(KERN_ERR, "dst    @"xstr(__LINE__)": ",
+                       DUMP_PREFIX_ADDRESS, 16, 4, sg_virt(req->src),
+                       edesc->dst_nents > 1 ? 100 : req->nbytes, 1);
+#endif
+
+        ablkcipher_unmap(jrdev, edesc, req);
+        kfree(edesc);
+
+        ablkcipher_request_complete(req, err);
+}
+
+static void sg_to_link_tbl_one(struct link_tbl_entry *link_tbl_ptr,
+                               dma_addr_t dma, u32 len, u32 offset)
+{
+        link_tbl_ptr->ptr = dma;
+        link_tbl_ptr->len = len;
+        link_tbl_ptr->reserved = 0;
+        link_tbl_ptr->buf_pool_id = 0;
+        link_tbl_ptr->offset = offset;
+#ifdef DEBUG
+        print_hex_dump(KERN_ERR, "link_tbl_ptr@"xstr(__LINE__)": ",
+                       DUMP_PREFIX_ADDRESS, 16, 4, link_tbl_ptr,
+                       sizeof(struct link_tbl_entry), 1);
+#endif
 }
 
 /*
  * convert scatterlist to h/w link table format
- * scatterlist must have been previously dma mapped
+ * but does not have final bit; instead, returns last entry
  */
-static void sg_to_link_tbl(struct scatterlist *sg, int sg_count,
-                           struct link_tbl_entry *link_tbl_ptr, u32 offset)
+static struct link_tbl_entry *sg_to_link_tbl(struct scatterlist *sg,
+                                             int sg_count, struct link_tbl_entry
+                                             *link_tbl_ptr, u32 offset)
 {
         while (sg_count) {
-                link_tbl_ptr->ptr = sg_dma_address(sg);
-                link_tbl_ptr->len = sg_dma_len(sg);
-                link_tbl_ptr->reserved = 0;
-                link_tbl_ptr->buf_pool_id = 0;
-                link_tbl_ptr->offset = offset;
+                sg_to_link_tbl_one(link_tbl_ptr, sg_dma_address(sg),
+                                   sg_dma_len(sg), offset);
                 link_tbl_ptr++;
                 sg = sg_next(sg);
                 sg_count--;
         }
+        return link_tbl_ptr - 1;
+}
 
-        /* set Final bit (marks end of link table) */
-        link_tbl_ptr--;
+/*
+ * convert scatterlist to h/w link table format
+ * scatterlist must have been previously dma mapped
+ */
+static void sg_to_link_tbl_last(struct scatterlist *sg, int sg_count,
+                                struct link_tbl_entry *link_tbl_ptr, u32 offset)
+{
+        link_tbl_ptr = sg_to_link_tbl(sg, sg_count, link_tbl_ptr, offset);
         link_tbl_ptr->len |= 0x40000000;
 }
 
 /*
- * fill in and submit ipsec_esp job descriptor
+ * Fill in aead job descriptor
  */
-static int ipsec_esp(struct ipsec_esp_edesc *edesc, struct aead_request *areq,
-                     u32 encrypt,
-                     void (*callback) (struct device *dev, u32 *desc,
-                                       u32 err, void *context))
+static void init_aead_job(u32 *sh_desc, dma_addr_t ptr,
+                          struct aead_edesc *edesc,
+                          struct aead_request *req,
+                          bool all_contig, bool encrypt)
 {
-        struct crypto_aead *aead = crypto_aead_reqtfm(areq);
+        struct crypto_aead *aead = crypto_aead_reqtfm(req);
         struct caam_ctx *ctx = crypto_aead_ctx(aead);
-        struct device *jrdev = ctx->jrdev;
-        u32 *desc = edesc->hw_desc, options;
-        int ret, sg_count, assoc_sg_count;
         int ivsize = crypto_aead_ivsize(aead);
         int authsize = ctx->authsize;
-        dma_addr_t ptr, dst_dma, src_dma;
-#ifdef DEBUG
-        u32 *sh_desc = ctx->sh_desc;
+        u32 *desc = edesc->hw_desc;
+        u32 out_options = 0, in_options;
+        dma_addr_t dst_dma, src_dma;
+        int len, link_tbl_index = 0;
 
+#ifdef DEBUG
         debug("assoclen %d cryptlen %d authsize %d\n",
-              areq->assoclen, areq->cryptlen, authsize);
+              req->assoclen, req->cryptlen, authsize);
         print_hex_dump(KERN_ERR, "assoc  @"xstr(__LINE__)": ",
-                       DUMP_PREFIX_ADDRESS, 16, 4, sg_virt(areq->assoc),
-                       areq->assoclen , 1);
+                       DUMP_PREFIX_ADDRESS, 16, 4, sg_virt(req->assoc),
+                       req->assoclen , 1);
         print_hex_dump(KERN_ERR, "presciv@"xstr(__LINE__)": ",
-                       DUMP_PREFIX_ADDRESS, 16, 4, sg_virt(areq->src) - ivsize,
+                       DUMP_PREFIX_ADDRESS, 16, 4, req->iv,
                        edesc->src_nents ? 100 : ivsize, 1);
         print_hex_dump(KERN_ERR, "src    @"xstr(__LINE__)": ",
-                       DUMP_PREFIX_ADDRESS, 16, 4, sg_virt(areq->src),
-                        edesc->src_nents ? 100 : areq->cryptlen + authsize, 1);
+                       DUMP_PREFIX_ADDRESS, 16, 4, sg_virt(req->src),
+                        edesc->src_nents ? 100 : req->cryptlen, 1);
         print_hex_dump(KERN_ERR, "shrdesc@"xstr(__LINE__)": ",
                        DUMP_PREFIX_ADDRESS, 16, 4, sh_desc,
                        desc_bytes(sh_desc), 1);
 #endif
-        assoc_sg_count = dma_map_sg(jrdev, areq->assoc, edesc->assoc_nents ?: 1,
-                                    DMA_TO_DEVICE);
-        if (areq->src == areq->dst)
-                sg_count = dma_map_sg(jrdev, areq->src, edesc->src_nents ? : 1,
-                                      DMA_BIDIRECTIONAL);
-        else
-                sg_count = dma_map_sg(jrdev, areq->src, edesc->src_nents ? : 1,
-                                      DMA_TO_DEVICE);
 
-        /* start auth operation */
-        append_operation(desc, ctx->class2_alg_type | OP_ALG_AS_INITFINAL |
-                         (encrypt ? : OP_ALG_ICV_ON));
+        len = desc_len(sh_desc);
+        init_job_desc_shared(desc, ptr, len, HDR_SHARE_DEFER | HDR_REVERSE);
 
-        /* Load FIFO with data for Class 2 CHA */
-        options = FIFOLD_CLASS_CLASS2 | FIFOLD_TYPE_MSG;
-        if (!edesc->assoc_nents) {
-                ptr = sg_dma_address(areq->assoc);
+        if (all_contig) {
+                src_dma = sg_dma_address(req->assoc);
+                in_options = 0;
         } else {
-                sg_to_link_tbl(areq->assoc, edesc->assoc_nents,
-                               edesc->link_tbl, 0);
-                ptr = edesc->link_tbl_dma;
-                options |= LDST_SGF;
+                src_dma = edesc->link_tbl_dma;
+                link_tbl_index += (edesc->assoc_nents ? : 1) + 1 +
+                                  (edesc->src_nents ? : 1);
+                in_options = LDST_SGF;
         }
-        append_fifo_load(desc, ptr, areq->assoclen, options);
-
-        /* copy iv from cipher/class1 input context to class2 infifo */
-        append_move(desc, MOVE_SRC_CLASS1CTX | MOVE_DEST_CLASS2INFIFO | ivsize);
-
-        if (!encrypt) {
-                u32 *jump_cmd, *uncond_jump_cmd;
-
-                /* JUMP if shared */
-                jump_cmd = append_jump(desc, JUMP_TEST_ALL | JUMP_COND_SHRD);
+        if (encrypt)
+                append_seq_in_ptr(desc, src_dma, req->assoclen + ivsize +
+                                  req->cryptlen - authsize, in_options);
+        else
+                append_seq_in_ptr(desc, src_dma, req->assoclen + ivsize +
+                                  req->cryptlen, in_options);
 
-                /* start class 1 (cipher) operation, non-shared version */
-                append_operation(desc, ctx->class1_alg_type |
-                                 OP_ALG_AS_INITFINAL);
+        if (likely(req->src == req->dst)) {
+                if (all_contig) {
+                        dst_dma = sg_dma_address(req->src);
+                } else {
+                        dst_dma = src_dma + sizeof(struct link_tbl_entry) *
+                                  ((edesc->assoc_nents ? : 1) + 1);
+                        out_options = LDST_SGF;
+                }
+        } else {
+                if (!edesc->dst_nents) {
+                        dst_dma = sg_dma_address(req->dst);
+                } else {
+                        dst_dma = edesc->link_tbl_dma +
+                                  link_tbl_index *
+                                  sizeof(struct link_tbl_entry);
+                        out_options = LDST_SGF;
+                }
+        }
+        if (encrypt)
+                append_seq_out_ptr(desc, dst_dma, req->cryptlen, out_options);
+        else
+                append_seq_out_ptr(desc, dst_dma, req->cryptlen - authsize,
+                                   out_options);
+}
 
-                uncond_jump_cmd = append_jump(desc, 0);
+/*
+ * Fill in aead givencrypt job descriptor
+ */
+static void init_aead_giv_job(u32 *sh_desc, dma_addr_t ptr,
+                              struct aead_edesc *edesc,
+                              struct aead_request *req,
+                              int contig)
+{
+        struct crypto_aead *aead = crypto_aead_reqtfm(req);
+        struct caam_ctx *ctx = crypto_aead_ctx(aead);
+        int ivsize = crypto_aead_ivsize(aead);
+        int authsize = ctx->authsize;
+        u32 *desc = edesc->hw_desc;
+        u32 out_options = 0, in_options;
+        dma_addr_t dst_dma, src_dma;
+        int len, link_tbl_index = 0;
 
-                set_jump_tgt_here(desc, jump_cmd);
+#ifdef DEBUG
+        debug("assoclen %d cryptlen %d authsize %d\n",
+              req->assoclen, req->cryptlen, authsize);
+        print_hex_dump(KERN_ERR, "assoc  @"xstr(__LINE__)": ",
+                       DUMP_PREFIX_ADDRESS, 16, 4, sg_virt(req->assoc),
+                       req->assoclen , 1);
+        print_hex_dump(KERN_ERR, "presciv@"xstr(__LINE__)": ",
+                       DUMP_PREFIX_ADDRESS, 16, 4, req->iv, ivsize, 1);
+        print_hex_dump(KERN_ERR, "src    @"xstr(__LINE__)": ",
+                       DUMP_PREFIX_ADDRESS, 16, 4, sg_virt(req->src),
+                        edesc->src_nents > 1 ? 100 : req->cryptlen, 1);
+        print_hex_dump(KERN_ERR, "shrdesc@"xstr(__LINE__)": ",
+                       DUMP_PREFIX_ADDRESS, 16, 4, sh_desc,
+                       desc_bytes(sh_desc), 1);
+#endif
 
-                /* start class 1 (cipher) operation, shared version */
-                append_operation(desc, ctx->class1_alg_type |
-                                 OP_ALG_AS_INITFINAL | OP_ALG_AAI_DK);
-                set_jump_tgt_here(desc, uncond_jump_cmd);
-        } else
-                append_operation(desc, ctx->class1_alg_type |
-                                 OP_ALG_AS_INITFINAL | encrypt);
+        len = desc_len(sh_desc);
+        init_job_desc_shared(desc, ptr, len, HDR_SHARE_DEFER | HDR_REVERSE);
 
-        /* load payload & instruct to class2 to snoop class 1 if encrypting */
-        options = 0;
-        if (!edesc->src_nents) {
-                src_dma = sg_dma_address(areq->src);
+        if (contig & GIV_SRC_CONTIG) {
+                src_dma = sg_dma_address(req->assoc);
+                in_options = 0;
         } else {
-                sg_to_link_tbl(areq->src, edesc->src_nents, edesc->link_tbl +
-                               edesc->assoc_nents, 0);
-                src_dma = edesc->link_tbl_dma + edesc->assoc_nents *
-                          sizeof(struct link_tbl_entry);
-                options |= LDST_SGF;
+                src_dma = edesc->link_tbl_dma;
+                link_tbl_index += edesc->assoc_nents + 1 + edesc->src_nents;
+                in_options = LDST_SGF;
         }
-        append_seq_in_ptr(desc, src_dma, areq->cryptlen + authsize, options);
-        append_seq_fifo_load(desc, areq->cryptlen, FIFOLD_CLASS_BOTH |
-                             FIFOLD_TYPE_LASTBOTH |
-                             (encrypt ? FIFOLD_TYPE_MSG1OUT2
-                                      : FIFOLD_TYPE_MSG));
-
-        /* specify destination */
-        if (areq->src == areq->dst) {
-                dst_dma = src_dma;
+        append_seq_in_ptr(desc, src_dma, req->assoclen + ivsize +
+                          req->cryptlen - authsize, in_options);
+
+        if (contig & GIV_DST_CONTIG) {
+                dst_dma = edesc->iv_dma;
         } else {
-                sg_count = dma_map_sg(jrdev, areq->dst, edesc->dst_nents ? : 1,
-                                      DMA_FROM_DEVICE);
-                if (!edesc->dst_nents) {
-                        dst_dma = sg_dma_address(areq->dst);
-                        options = 0;
+                if (likely(req->src == req->dst)) {
+                        dst_dma = src_dma + sizeof(struct link_tbl_entry) *
+                                  edesc->assoc_nents;
+                        out_options = LDST_SGF;
                 } else {
-                        sg_to_link_tbl(areq->dst, edesc->dst_nents,
-                                       edesc->link_tbl + edesc->assoc_nents +
-                                       edesc->src_nents, 0);
-                        dst_dma = edesc->link_tbl_dma + (edesc->assoc_nents +
-                                  edesc->src_nents) *
+                        dst_dma = edesc->link_tbl_dma +
+                                  link_tbl_index *
                                   sizeof(struct link_tbl_entry);
-                        options = LDST_SGF;
+                        out_options = LDST_SGF;
                 }
         }
-        append_seq_out_ptr(desc, dst_dma, areq->cryptlen + authsize, options);
-        append_seq_fifo_store(desc, areq->cryptlen, FIFOST_TYPE_MESSAGE_DATA);
 
-        /* ICV */
-        if (encrypt)
-                append_seq_store(desc, authsize, LDST_CLASS_2_CCB |
-                                 LDST_SRCDST_BYTE_CONTEXT);
-        else
-                append_seq_fifo_load(desc, authsize, FIFOLD_CLASS_CLASS2 |
-                                     FIFOLD_TYPE_LAST2 | FIFOLD_TYPE_ICV);
+        append_seq_out_ptr(desc, dst_dma, ivsize + req->cryptlen, out_options);
+}
+
+/*
+ * Fill in ablkcipher job descriptor
+ */
+static void init_ablkcipher_job(u32 *sh_desc, dma_addr_t ptr,
+                                struct ablkcipher_edesc *edesc,
+                                struct ablkcipher_request *req,
+                                bool iv_contig)
+{
+        struct crypto_ablkcipher *ablkcipher = crypto_ablkcipher_reqtfm(req);
+        int ivsize = crypto_ablkcipher_ivsize(ablkcipher);
+        u32 *desc = edesc->hw_desc;
+        u32 out_options = 0, in_options;
+        dma_addr_t dst_dma, src_dma;
+        int len, link_tbl_index = 0;
 
 #ifdef DEBUG
-        debug("job_desc_len %d\n", desc_len(desc));
-        print_hex_dump(KERN_ERR, "jobdesc@"xstr(__LINE__)": ",
-                       DUMP_PREFIX_ADDRESS, 16, 4, desc, desc_bytes(desc) , 1);
-        print_hex_dump(KERN_ERR, "jdlinkt@"xstr(__LINE__)": ",
-                       DUMP_PREFIX_ADDRESS, 16, 4, edesc->link_tbl,
-                        edesc->link_tbl_bytes, 1);
+        print_hex_dump(KERN_ERR, "presciv@"xstr(__LINE__)": ",
+                       DUMP_PREFIX_ADDRESS, 16, 4, req->info,
+                       ivsize, 1);
+        print_hex_dump(KERN_ERR, "src    @"xstr(__LINE__)": ",
+                       DUMP_PREFIX_ADDRESS, 16, 4, sg_virt(req->src),
+                       edesc->src_nents ? 100 : req->nbytes, 1);
 #endif
 
-        ret = caam_jr_enqueue(jrdev, desc, callback, areq);
-        if (!ret)
-                ret = -EINPROGRESS;
-        else {
-                ipsec_esp_unmap(jrdev, edesc, areq);
-                kfree(edesc);
+        len = desc_len(sh_desc);
+        init_job_desc_shared(desc, ptr, len, HDR_SHARE_DEFER | HDR_REVERSE);
+
+        if (iv_contig) {
+                src_dma = edesc->iv_dma;
+                in_options = 0;
+        } else {
+                src_dma = edesc->link_tbl_dma;
+                link_tbl_index += (iv_contig ? 0 : 1) + edesc->src_nents;
+                in_options = LDST_SGF;
         }
+        append_seq_in_ptr(desc, src_dma, req->nbytes + ivsize, in_options);
 
-        return ret;
+        if (likely(req->src == req->dst)) {
+                if (!edesc->src_nents && iv_contig) {
+                        dst_dma = sg_dma_address(req->src);
+                } else {
+                        dst_dma = edesc->link_tbl_dma +
+                                sizeof(struct link_tbl_entry);
+                        out_options = LDST_SGF;
+                }
+        } else {
+                if (!edesc->dst_nents) {
+                        dst_dma = sg_dma_address(req->dst);
+                } else {
+                        dst_dma = edesc->link_tbl_dma +
+                                link_tbl_index * sizeof(struct link_tbl_entry);
+                        out_options = LDST_SGF;
+                }
+        }
+        append_seq_out_ptr(desc, dst_dma, req->nbytes, out_options);
 }
 
 /*
  * derive number of elements in scatterlist
  */
-static int sg_count(struct scatterlist *sg_list, int nbytes, int *chained)
+static int sg_count(struct scatterlist *sg_list, int nbytes)
 {
         struct scatterlist *sg = sg_list;
         int sg_nents = 0;
 
-        *chained = 0;
         while (nbytes > 0) {
                 sg_nents++;
                 nbytes -= sg->length;
                 if (!sg_is_last(sg) && (sg + 1)->length == 0)
-                        *chained = 1;
+                        BUG(); /* Not support chaining */
                 sg = scatterwalk_sg_next(sg);
         }
 
+        if (likely(sg_nents == 1))
+                return 0;
+
         return sg_nents;
 }
 
 /*
- * allocate and map the ipsec_esp extended descriptor
+ * allocate and map the aead extended descriptor
  */
-static struct ipsec_esp_edesc *ipsec_esp_edesc_alloc(struct aead_request *areq,
-                                                     int desc_bytes)
+static struct aead_edesc *aead_edesc_alloc(struct aead_request *req,
+                                           int desc_bytes, bool *all_contig_ptr)
 {
-        struct crypto_aead *aead = crypto_aead_reqtfm(areq);
+        struct crypto_aead *aead = crypto_aead_reqtfm(req);
         struct caam_ctx *ctx = crypto_aead_ctx(aead);
         struct device *jrdev = ctx->jrdev;
-        gfp_t flags = areq->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP ? GFP_KERNEL :
-                      GFP_ATOMIC;
-        int assoc_nents, src_nents, dst_nents = 0, chained, link_tbl_bytes;
-        struct ipsec_esp_edesc *edesc;
-
-        assoc_nents = sg_count(areq->assoc, areq->assoclen, &chained);
-        BUG_ON(chained);
-        if (likely(assoc_nents == 1))
-                assoc_nents = 0;
-
-        src_nents = sg_count(areq->src, areq->cryptlen + ctx->authsize,
-                             &chained);
-        BUG_ON(chained);
-        if (src_nents == 1)
-                src_nents = 0;
-
-        if (unlikely(areq->dst != areq->src)) {
-                dst_nents = sg_count(areq->dst, areq->cryptlen + ctx->authsize,
-                                     &chained);
-                BUG_ON(chained);
-                if (dst_nents == 1)
-                        dst_nents = 0;
+        gfp_t flags = (req->base.flags & (CRYPTO_TFM_REQ_MAY_BACKLOG |
+                       CRYPTO_TFM_REQ_MAY_SLEEP)) ? GFP_KERNEL : GFP_ATOMIC;
+        int assoc_nents, src_nents, dst_nents = 0;
+        struct aead_edesc *edesc;
+        dma_addr_t iv_dma = 0;
+        int sgc;
+        bool all_contig = true;
+        int ivsize = crypto_aead_ivsize(aead);
+        int link_tbl_index, link_tbl_len = 0, link_tbl_bytes;
+
+        assoc_nents = sg_count(req->assoc, req->assoclen);
+        src_nents = sg_count(req->src, req->cryptlen);
+
+        if (unlikely(req->dst != req->src))
+                dst_nents = sg_count(req->dst, req->cryptlen);
+
+        sgc = dma_map_sg(jrdev, req->assoc, assoc_nents ? : 1,
+                         DMA_BIDIRECTIONAL);
+        if (likely(req->src == req->dst)) {
+                sgc = dma_map_sg(jrdev, req->src, src_nents ? : 1,
+                                 DMA_BIDIRECTIONAL);
+        } else {
+                sgc = dma_map_sg(jrdev, req->src, src_nents ? : 1,
+                                 DMA_TO_DEVICE);
+                sgc = dma_map_sg(jrdev, req->dst, dst_nents ? : 1,
+                                 DMA_FROM_DEVICE);
         }
 
-        link_tbl_bytes = (assoc_nents + src_nents + dst_nents) *
-                         sizeof(struct link_tbl_entry);
-        debug("link_tbl_bytes %d\n", link_tbl_bytes);
+        /* Check if data are contiguous */
+        iv_dma = dma_map_single(jrdev, req->iv, ivsize, DMA_TO_DEVICE);
+        if (assoc_nents || sg_dma_address(req->assoc) + req->assoclen !=
+            iv_dma || src_nents || iv_dma + ivsize !=
+            sg_dma_address(req->src)) {
+                all_contig = false;
+                assoc_nents = assoc_nents ? : 1;
+                src_nents = src_nents ? : 1;
+                link_tbl_len = assoc_nents + 1 + src_nents;
+        }
+        link_tbl_len += dst_nents;
+
+        link_tbl_bytes = link_tbl_len * sizeof(struct link_tbl_entry);
 
         /* allocate space for base edesc and hw desc commands, link tables */
-        edesc = kmalloc(sizeof(struct ipsec_esp_edesc) + desc_bytes +
+        edesc = kmalloc(sizeof(struct aead_edesc) + desc_bytes +
                         link_tbl_bytes, GFP_DMA | flags);
         if (!edesc) {
                 dev_err(jrdev, "could not allocate extended descriptor\n");
@@ -753,142 +1354,450 @@ static struct ipsec_esp_edesc *ipsec_esp_edesc_alloc(struct aead_request *areq,
         edesc->assoc_nents = assoc_nents;
         edesc->src_nents = src_nents;
         edesc->dst_nents = dst_nents;
-        edesc->link_tbl = (void *)edesc + sizeof(struct ipsec_esp_edesc) +
+        edesc->iv_dma = iv_dma;
+        edesc->link_tbl_bytes = link_tbl_bytes;
+        edesc->link_tbl = (void *)edesc + sizeof(struct aead_edesc) +
                           desc_bytes;
         edesc->link_tbl_dma = dma_map_single(jrdev, edesc->link_tbl,
                                              link_tbl_bytes, DMA_TO_DEVICE);
-        edesc->link_tbl_bytes = link_tbl_bytes;
+        *all_contig_ptr = all_contig;
+
+        link_tbl_index = 0;
+        if (!all_contig) {
+                sg_to_link_tbl(req->assoc,
+                               (assoc_nents ? : 1),
+                               edesc->link_tbl +
+                               link_tbl_index, 0);
+                link_tbl_index += assoc_nents ? : 1;
+                sg_to_link_tbl_one(edesc->link_tbl + link_tbl_index,
+                                   iv_dma, ivsize, 0);
+                link_tbl_index += 1;
+                sg_to_link_tbl_last(req->src,
+                                    (src_nents ? : 1),
+                                    edesc->link_tbl +
+                                    link_tbl_index, 0);
+                link_tbl_index += src_nents ? : 1;
+        }
+        if (dst_nents) {
+                sg_to_link_tbl_last(req->dst, dst_nents,
+                                    edesc->link_tbl + link_tbl_index, 0);
+        }
 
         return edesc;
 }
 
-static int aead_authenc_encrypt(struct aead_request *areq)
+static int aead_encrypt(struct aead_request *req)
 {
-        struct ipsec_esp_edesc *edesc;
-        struct crypto_aead *aead = crypto_aead_reqtfm(areq);
+        struct aead_edesc *edesc;
+        struct crypto_aead *aead = crypto_aead_reqtfm(req);
         struct caam_ctx *ctx = crypto_aead_ctx(aead);
         struct device *jrdev = ctx->jrdev;
-        int ivsize = crypto_aead_ivsize(aead);
+        bool all_contig;
         u32 *desc;
-        dma_addr_t iv_dma;
+        int ret = 0;
+
+        req->cryptlen += ctx->authsize;
 
         /* allocate extended descriptor */
-        edesc = ipsec_esp_edesc_alloc(areq, DESC_AEAD_ENCRYPT_TEXT_LEN *
-                                      CAAM_CMD_SZ);
+        edesc = aead_edesc_alloc(req, DESC_JOB_IO_LEN *
+                                 CAAM_CMD_SZ, &all_contig);
         if (IS_ERR(edesc))
                 return PTR_ERR(edesc);
 
-        desc = edesc->hw_desc;
-
-        /* insert shared descriptor pointer */
-        init_job_desc_shared(desc, ctx->shared_desc_phys,
-                             desc_len(ctx->sh_desc), HDR_SHARE_DEFER);
-
-        iv_dma = dma_map_single(jrdev, areq->iv, ivsize, DMA_TO_DEVICE);
-        /* check dma error */
+        /* Create and submit job descriptor */
+        init_aead_job(ctx->sh_desc_enc, ctx->sh_desc_enc_dma, edesc, req,
+                      all_contig, true);
+#ifdef DEBUG
+        print_hex_dump(KERN_ERR, "aead jobdesc@"xstr(__LINE__)": ",
+                       DUMP_PREFIX_ADDRESS, 16, 4, edesc->hw_desc,
+                       desc_bytes(edesc->hw_desc), 1);
+#endif
 
-        append_load(desc, iv_dma, ivsize,
-                    LDST_CLASS_1_CCB | LDST_SRCDST_BYTE_CONTEXT);
+        desc = edesc->hw_desc;
+        ret = caam_jr_enqueue(jrdev, desc, aead_encrypt_done, req);
+        if (!ret) {
+                ret = -EINPROGRESS;
+        } else {
+                aead_unmap(jrdev, edesc, req);
+                kfree(edesc);
+        }
 
-        return ipsec_esp(edesc, areq, OP_ALG_ENCRYPT, ipsec_esp_encrypt_done);
+        return ret;
 }
 
-static int aead_authenc_decrypt(struct aead_request *req)
+static int aead_decrypt(struct aead_request *req)
 {
+        struct aead_edesc *edesc;
         struct crypto_aead *aead = crypto_aead_reqtfm(req);
-        int ivsize = crypto_aead_ivsize(aead);
         struct caam_ctx *ctx = crypto_aead_ctx(aead);
         struct device *jrdev = ctx->jrdev;
-        struct ipsec_esp_edesc *edesc;
+        bool all_contig;
         u32 *desc;
-        dma_addr_t iv_dma;
-
-        req->cryptlen -= ctx->authsize;
+        int ret = 0;
 
         /* allocate extended descriptor */
-        edesc = ipsec_esp_edesc_alloc(req, DESC_AEAD_DECRYPT_TEXT_LEN *
-                                      CAAM_CMD_SZ);
+        edesc = aead_edesc_alloc(req, DESC_JOB_IO_LEN *
+                                 CAAM_CMD_SZ, &all_contig);
         if (IS_ERR(edesc))
                 return PTR_ERR(edesc);
 
+#ifdef DEBUG
+        print_hex_dump(KERN_ERR, "dec src@"xstr(__LINE__)": ",
+                       DUMP_PREFIX_ADDRESS, 16, 4, sg_virt(req->src),
+                       req->cryptlen, 1);
+#endif
+
+        /* Create and submit job descriptor*/
+        init_aead_job(ctx->sh_desc_dec,
+                      ctx->sh_desc_dec_dma, edesc, req, all_contig, false);
+#ifdef DEBUG
+        print_hex_dump(KERN_ERR, "aead jobdesc@"xstr(__LINE__)": ",
+                       DUMP_PREFIX_ADDRESS, 16, 4, edesc->hw_desc,
+                       desc_bytes(edesc->hw_desc), 1);
+#endif
+
         desc = edesc->hw_desc;
+        ret = caam_jr_enqueue(jrdev, desc, aead_decrypt_done, req);
+        if (!ret) {
+                ret = -EINPROGRESS;
+        } else {
+                aead_unmap(jrdev, edesc, req);
+                kfree(edesc);
+        }
 
-        /* insert shared descriptor pointer */
-        init_job_desc_shared(desc, ctx->shared_desc_phys,
-                             desc_len(ctx->sh_desc), HDR_SHARE_DEFER);
+        return ret;
+}
 
-        iv_dma = dma_map_single(jrdev, req->iv, ivsize, DMA_TO_DEVICE);
-        /* check dma error */
+/*
+ * allocate and map the aead extended descriptor for aead givencrypt
+ */
+static struct aead_edesc *aead_giv_edesc_alloc(struct aead_givcrypt_request
+                                               *greq, int desc_bytes,
+                                               u32 *contig_ptr)
+{
+        struct aead_request *req = &greq->areq;
+        struct crypto_aead *aead = crypto_aead_reqtfm(req);
+        struct caam_ctx *ctx = crypto_aead_ctx(aead);
+        struct device *jrdev = ctx->jrdev;
+        gfp_t flags = (req->base.flags & (CRYPTO_TFM_REQ_MAY_BACKLOG |
+                       CRYPTO_TFM_REQ_MAY_SLEEP)) ? GFP_KERNEL : GFP_ATOMIC;
+        int assoc_nents, src_nents, dst_nents = 0;
+        struct aead_edesc *edesc;
+        dma_addr_t iv_dma = 0;
+        int sgc;
+        u32 contig = GIV_SRC_CONTIG | GIV_DST_CONTIG;
+        int ivsize = crypto_aead_ivsize(aead);
+        int link_tbl_index, link_tbl_len = 0, link_tbl_bytes;
+
+        assoc_nents = sg_count(req->assoc, req->assoclen);
+        src_nents = sg_count(req->src, req->cryptlen);
 
-        append_load(desc, iv_dma, ivsize,
-                    LDST_CLASS_1_CCB | LDST_SRCDST_BYTE_CONTEXT);
+        if (unlikely(req->dst != req->src))
+                dst_nents = sg_count(req->dst, req->cryptlen);
 
-        return ipsec_esp(edesc, req, !OP_ALG_ENCRYPT, ipsec_esp_decrypt_done);
+        sgc = dma_map_sg(jrdev, req->assoc, assoc_nents ? : 1,
+                         DMA_BIDIRECTIONAL);
+        if (likely(req->src == req->dst)) {
+                sgc = dma_map_sg(jrdev, req->src, src_nents ? : 1,
+                                 DMA_BIDIRECTIONAL);
+        } else {
+                sgc = dma_map_sg(jrdev, req->src, src_nents ? : 1,
+                                 DMA_TO_DEVICE);
+                sgc = dma_map_sg(jrdev, req->dst, dst_nents ? : 1,
+                                 DMA_FROM_DEVICE);
+        }
+
+        /* Check if data are contiguous */
+        iv_dma = dma_map_single(jrdev, greq->giv, ivsize, DMA_TO_DEVICE);
+        if (assoc_nents || sg_dma_address(req->assoc) + req->assoclen !=
+            iv_dma || src_nents || iv_dma + ivsize != sg_dma_address(req->src))
+                contig &= ~GIV_SRC_CONTIG;
+        if (dst_nents || iv_dma + ivsize != sg_dma_address(req->dst))
+                contig &= ~GIV_DST_CONTIG;
+                if (unlikely(req->src != req->dst)) {
+                        dst_nents = dst_nents ? : 1;
+                        link_tbl_len += 1;
+                }
+        if (!(contig & GIV_SRC_CONTIG)) {
+                assoc_nents = assoc_nents ? : 1;
+                src_nents = src_nents ? : 1;
+                link_tbl_len += assoc_nents + 1 + src_nents;
+                if (likely(req->src == req->dst))
+                        contig &= ~GIV_DST_CONTIG;
+        }
+        link_tbl_len += dst_nents;
+
+        link_tbl_bytes = link_tbl_len * sizeof(struct link_tbl_entry);
+
+        /* allocate space for base edesc and hw desc commands, link tables */
+        edesc = kmalloc(sizeof(struct aead_edesc) + desc_bytes +
+                        link_tbl_bytes, GFP_DMA | flags);
+        if (!edesc) {
+                dev_err(jrdev, "could not allocate extended descriptor\n");
+                return ERR_PTR(-ENOMEM);
+        }
+
+        edesc->assoc_nents = assoc_nents;
+        edesc->src_nents = src_nents;
+        edesc->dst_nents = dst_nents;
+        edesc->iv_dma = iv_dma;
+        edesc->link_tbl_bytes = link_tbl_bytes;
+        edesc->link_tbl = (void *)edesc + sizeof(struct aead_edesc) +
+                          desc_bytes;
+        edesc->link_tbl_dma = dma_map_single(jrdev, edesc->link_tbl,
+                                             link_tbl_bytes, DMA_TO_DEVICE);
+        *contig_ptr = contig;
+
+        link_tbl_index = 0;
+        if (!(contig & GIV_SRC_CONTIG)) {
+                sg_to_link_tbl(req->assoc, assoc_nents,
+                               edesc->link_tbl +
+                               link_tbl_index, 0);
+                link_tbl_index += assoc_nents;
+                sg_to_link_tbl_one(edesc->link_tbl + link_tbl_index,
+                                   iv_dma, ivsize, 0);
+                link_tbl_index += 1;
+                sg_to_link_tbl_last(req->src, src_nents,
+                                    edesc->link_tbl +
+                                    link_tbl_index, 0);
+                link_tbl_index += src_nents;
+        }
+        if (unlikely(req->src != req->dst && !(contig & GIV_DST_CONTIG))) {
+                sg_to_link_tbl_one(edesc->link_tbl + link_tbl_index,
+                                   iv_dma, ivsize, 0);
+                link_tbl_index += 1;
+                sg_to_link_tbl_last(req->dst, dst_nents,
+                                    edesc->link_tbl + link_tbl_index, 0);
+        }
+
+        return edesc;
 }
 
-static int aead_authenc_givencrypt(struct aead_givcrypt_request *req)
+static int aead_givencrypt(struct aead_givcrypt_request *areq)
 {
-        struct aead_request *areq = &req->areq;
-        struct ipsec_esp_edesc *edesc;
-        struct crypto_aead *aead = crypto_aead_reqtfm(areq);
+        struct aead_request *req = &areq->areq;
+        struct aead_edesc *edesc;
+        struct crypto_aead *aead = crypto_aead_reqtfm(req);
         struct caam_ctx *ctx = crypto_aead_ctx(aead);
         struct device *jrdev = ctx->jrdev;
-        int ivsize = crypto_aead_ivsize(aead);
-        dma_addr_t iv_dma;
+        u32 contig;
         u32 *desc;
+        int ret = 0;
 
-        iv_dma = dma_map_single(jrdev, req->giv, ivsize, DMA_FROM_DEVICE);
-
-        debug("%s: giv %p\n", __func__, req->giv);
+        req->cryptlen += ctx->authsize;
 
         /* allocate extended descriptor */
-        edesc = ipsec_esp_edesc_alloc(areq, DESC_AEAD_GIVENCRYPT_TEXT_LEN *
-                                      CAAM_CMD_SZ);
+        edesc = aead_giv_edesc_alloc(areq, DESC_JOB_IO_LEN *
+                                     CAAM_CMD_SZ, &contig);
+
         if (IS_ERR(edesc))
                 return PTR_ERR(edesc);
 
+#ifdef DEBUG
+        print_hex_dump(KERN_ERR, "giv src@"xstr(__LINE__)": ",
+                       DUMP_PREFIX_ADDRESS, 16, 4, sg_virt(req->src),
+                       req->cryptlen, 1);
+#endif
+
+        /* Create and submit job descriptor*/
+        init_aead_giv_job(ctx->sh_desc_givenc,
+                          ctx->sh_desc_givenc_dma, edesc, req, contig);
+#ifdef DEBUG
+        print_hex_dump(KERN_ERR, "aead jobdesc@"xstr(__LINE__)": ",
+                       DUMP_PREFIX_ADDRESS, 16, 4, edesc->hw_desc,
+                       desc_bytes(edesc->hw_desc), 1);
+#endif
+
         desc = edesc->hw_desc;
+        ret = caam_jr_enqueue(jrdev, desc, aead_encrypt_done, req);
+        if (!ret) {
+                ret = -EINPROGRESS;
+        } else {
+                aead_unmap(jrdev, edesc, req);
+                kfree(edesc);
+        }
 
-        /* insert shared descriptor pointer */
-        init_job_desc_shared(desc, ctx->shared_desc_phys,
-                             desc_len(ctx->sh_desc), HDR_SHARE_DEFER);
+        return ret;
+}
 
-        /*
-         * LOAD IMM Info FIFO
-         * to DECO, Last, Padding, Random, Message, 16 bytes
-         */
-        append_load_imm_u32(desc, NFIFOENTRY_DEST_DECO | NFIFOENTRY_LC1 |
-                            NFIFOENTRY_STYPE_PAD | NFIFOENTRY_DTYPE_MSG |
-                            NFIFOENTRY_PTYPE_RND | ivsize,
-                            LDST_SRCDST_WORD_INFO_FIFO);
+/*
+ * allocate and map the ablkcipher extended descriptor for ablkcipher
+ */
+static struct ablkcipher_edesc *ablkcipher_edesc_alloc(struct ablkcipher_request
+                                                       *req, int desc_bytes,
+                                                       bool *iv_contig_out)
+{
+        struct crypto_ablkcipher *ablkcipher = crypto_ablkcipher_reqtfm(req);
+        struct caam_ctx *ctx = crypto_ablkcipher_ctx(ablkcipher);
+        struct device *jrdev = ctx->jrdev;
+        gfp_t flags = (req->base.flags & (CRYPTO_TFM_REQ_MAY_BACKLOG |
+                                          CRYPTO_TFM_REQ_MAY_SLEEP)) ?
+                       GFP_KERNEL : GFP_ATOMIC;
+        int src_nents, dst_nents = 0, link_tbl_bytes;
+        struct ablkcipher_edesc *edesc;
+        dma_addr_t iv_dma = 0;
+        bool iv_contig = false;
+        int sgc;
+        int ivsize = crypto_ablkcipher_ivsize(ablkcipher);
+        int link_tbl_index;
+
+        src_nents = sg_count(req->src, req->nbytes);
+
+        if (unlikely(req->dst != req->src))
+                dst_nents = sg_count(req->dst, req->nbytes);
+
+        if (likely(req->src == req->dst)) {
+                sgc = dma_map_sg(jrdev, req->src, src_nents ? : 1,
+                                 DMA_BIDIRECTIONAL);
+        } else {
+                sgc = dma_map_sg(jrdev, req->src, src_nents ? : 1,
+                                 DMA_TO_DEVICE);
+                sgc = dma_map_sg(jrdev, req->dst, dst_nents ? : 1,
+                                 DMA_FROM_DEVICE);
+        }
 
         /*
-         * disable info fifo entries since the above serves as the entry
-         * this way, the MOVE command won't generate an entry.
-         * Note that this isn't required in more recent versions of
-         * SEC as a MOVE that doesn't do info FIFO entries is available.
+         * Check if iv can be contiguous with source and destination.
+         * If so, include it. If not, create scatterlist.
          */
-        append_cmd(desc, CMD_LOAD | DISABLE_AUTO_INFO_FIFO);
+        iv_dma = dma_map_single(jrdev, req->info, ivsize, DMA_TO_DEVICE);
+        if (!src_nents && iv_dma + ivsize == sg_dma_address(req->src))
+                iv_contig = true;
+        else
+                src_nents = src_nents ? : 1;
+        link_tbl_bytes = ((iv_contig ? 0 : 1) + src_nents + dst_nents) *
+                         sizeof(struct link_tbl_entry);
 
-        /* MOVE DECO Alignment -> C1 Context 16 bytes */
-        append_move(desc, MOVE_SRC_INFIFO | MOVE_DEST_CLASS1CTX | ivsize);
+        /* allocate space for base edesc and hw desc commands, link tables */
+        edesc = kmalloc(sizeof(struct ablkcipher_edesc) + desc_bytes +
+                        link_tbl_bytes, GFP_DMA | flags);
+        if (!edesc) {
+                dev_err(jrdev, "could not allocate extended descriptor\n");
+                return ERR_PTR(-ENOMEM);
+        }
 
-        /* re-enable info fifo entries */
-        append_cmd(desc, CMD_LOAD | ENABLE_AUTO_INFO_FIFO);
+        edesc->src_nents = src_nents;
+        edesc->dst_nents = dst_nents;
+        edesc->link_tbl_bytes = link_tbl_bytes;
+        edesc->link_tbl = (void *)edesc + sizeof(struct ablkcipher_edesc) +
+                          desc_bytes;
+
+        link_tbl_index = 0;
+        if (!iv_contig) {
+                sg_to_link_tbl_one(edesc->link_tbl, iv_dma, ivsize, 0);
+                sg_to_link_tbl_last(req->src, src_nents,
+                                    edesc->link_tbl + 1, 0);
+                link_tbl_index += 1 + src_nents;
+        }
+
+        if (unlikely(dst_nents)) {
+                sg_to_link_tbl_last(req->dst, dst_nents,
+                        edesc->link_tbl + link_tbl_index, 0);
+        }
+
+        edesc->link_tbl_dma = dma_map_single(jrdev, edesc->link_tbl,
+                                             link_tbl_bytes, DMA_TO_DEVICE);
+        edesc->iv_dma = iv_dma;
+
+#ifdef DEBUG
+        print_hex_dump(KERN_ERR, "ablkcipher link_tbl@"xstr(__LINE__)": ",
+                       DUMP_PREFIX_ADDRESS, 16, 4, edesc->link_tbl,
+                       link_tbl_bytes, 1);
+#endif
+
+        *iv_contig_out = iv_contig;
+        return edesc;
+}
+
+static int ablkcipher_encrypt(struct ablkcipher_request *req)
+{
+        struct ablkcipher_edesc *edesc;
+        struct crypto_ablkcipher *ablkcipher = crypto_ablkcipher_reqtfm(req);
+        struct caam_ctx *ctx = crypto_ablkcipher_ctx(ablkcipher);
+        struct device *jrdev = ctx->jrdev;
+        bool iv_contig;
+        u32 *desc;
+        int ret = 0;
+
+        /* allocate extended descriptor */
+        edesc = ablkcipher_edesc_alloc(req, DESC_JOB_IO_LEN *
+                                       CAAM_CMD_SZ, &iv_contig);
+        if (IS_ERR(edesc))
+                return PTR_ERR(edesc);
 
-        /* MOVE C1 Context -> OFIFO 16 bytes */
-        append_move(desc, MOVE_SRC_CLASS1CTX | MOVE_DEST_OUTFIFO | ivsize);
+        /* Create and submit job descriptor*/
+        init_ablkcipher_job(ctx->sh_desc_enc,
+                ctx->sh_desc_enc_dma, edesc, req, iv_contig);
+#ifdef DEBUG
+        print_hex_dump(KERN_ERR, "ablkcipher jobdesc@"xstr(__LINE__)": ",
+                       DUMP_PREFIX_ADDRESS, 16, 4, edesc->hw_desc,
+                       desc_bytes(edesc->hw_desc), 1);
+#endif
+        desc = edesc->hw_desc;
+        ret = caam_jr_enqueue(jrdev, desc, ablkcipher_encrypt_done, req);
 
-        append_fifo_store(desc, iv_dma, ivsize, FIFOST_TYPE_MESSAGE_DATA);
+        if (!ret) {
+                ret = -EINPROGRESS;
+        } else {
+                ablkcipher_unmap(jrdev, edesc, req);
+                kfree(edesc);
+        }
 
-        return ipsec_esp(edesc, areq, OP_ALG_ENCRYPT, ipsec_esp_encrypt_done);
+        return ret;
 }
 
+static int ablkcipher_decrypt(struct ablkcipher_request *req)
+{
+        struct ablkcipher_edesc *edesc;
+        struct crypto_ablkcipher *ablkcipher = crypto_ablkcipher_reqtfm(req);
+        struct caam_ctx *ctx = crypto_ablkcipher_ctx(ablkcipher);
+        struct device *jrdev = ctx->jrdev;
+        bool iv_contig;
+        u32 *desc;
+        int ret = 0;
+
+        /* allocate extended descriptor */
+        edesc = ablkcipher_edesc_alloc(req, DESC_JOB_IO_LEN *
+                                       CAAM_CMD_SZ, &iv_contig);
+        if (IS_ERR(edesc))
+                return PTR_ERR(edesc);
+
+        /* Create and submit job descriptor*/
+        init_ablkcipher_job(ctx->sh_desc_dec,
+                ctx->sh_desc_dec_dma, edesc, req, iv_contig);
+        desc = edesc->hw_desc;
+#ifdef DEBUG
+        print_hex_dump(KERN_ERR, "ablkcipher jobdesc@"xstr(__LINE__)": ",
+                       DUMP_PREFIX_ADDRESS, 16, 4, edesc->hw_desc,
+                       desc_bytes(edesc->hw_desc), 1);
+#endif
+
+        ret = caam_jr_enqueue(jrdev, desc, ablkcipher_decrypt_done, req);
+        if (!ret) {
+                ret = -EINPROGRESS;
+        } else {
+                ablkcipher_unmap(jrdev, edesc, req);
+                kfree(edesc);
+        }
+
+        return ret;
+}
+
+#define template_aead           template_u.aead
+#define template_ablkcipher     template_u.ablkcipher
 struct caam_alg_template {
         char name[CRYPTO_MAX_ALG_NAME];
         char driver_name[CRYPTO_MAX_ALG_NAME];
         unsigned int blocksize;
-        struct aead_alg aead;
+        u32 type;
+        union {
+                struct ablkcipher_alg ablkcipher;
+                struct aead_alg aead;
+                struct blkcipher_alg blkcipher;
+                struct cipher_alg cipher;
+                struct compress_alg compress;
+                struct rng_alg rng;
+        } template_u;
         u32 class1_alg_type;
         u32 class2_alg_type;
         u32 alg_op;
@@ -900,12 +1809,13 @@ static struct caam_alg_template driver_algs[] = {
                 .name = "authenc(hmac(sha1),cbc(aes))",
                 .driver_name = "authenc-hmac-sha1-cbc-aes-caam",
                 .blocksize = AES_BLOCK_SIZE,
-                .aead = {
-                        .setkey = aead_authenc_setkey,
-                        .setauthsize = aead_authenc_setauthsize,
-                        .encrypt = aead_authenc_encrypt,
-                        .decrypt = aead_authenc_decrypt,
-                        .givencrypt = aead_authenc_givencrypt,
+                .type = CRYPTO_ALG_TYPE_AEAD,
+                .template_aead = {
+                        .setkey = aead_setkey,
+                        .setauthsize = aead_setauthsize,
+                        .encrypt = aead_encrypt,
+                        .decrypt = aead_decrypt,
+                        .givencrypt = aead_givencrypt,
                         .geniv = "<built-in>",
                         .ivsize = AES_BLOCK_SIZE,
                         .maxauthsize = SHA1_DIGEST_SIZE,
@@ -918,12 +1828,13 @@ static struct caam_alg_template driver_algs[] = {
                 .name = "authenc(hmac(sha256),cbc(aes))",
                 .driver_name = "authenc-hmac-sha256-cbc-aes-caam",
                 .blocksize = AES_BLOCK_SIZE,
-                .aead = {
-                        .setkey = aead_authenc_setkey,
-                        .setauthsize = aead_authenc_setauthsize,
-                        .encrypt = aead_authenc_encrypt,
-                        .decrypt = aead_authenc_decrypt,
-                        .givencrypt = aead_authenc_givencrypt,
+                .type = CRYPTO_ALG_TYPE_AEAD,
+                .template_aead = {
+                        .setkey = aead_setkey,
+                        .setauthsize = aead_setauthsize,
+                        .encrypt = aead_encrypt,
+                        .decrypt = aead_decrypt,
+                        .givencrypt = aead_givencrypt,
                         .geniv = "<built-in>",
                         .ivsize = AES_BLOCK_SIZE,
                         .maxauthsize = SHA256_DIGEST_SIZE,
@@ -937,12 +1848,13 @@ static struct caam_alg_template driver_algs[] = {
                 .name = "authenc(hmac(sha512),cbc(aes))",
                 .driver_name = "authenc-hmac-sha512-cbc-aes-caam",
                 .blocksize = AES_BLOCK_SIZE,
-                .aead = {
-                        .setkey = aead_authenc_setkey,
-                        .setauthsize = aead_authenc_setauthsize,
-                        .encrypt = aead_authenc_encrypt,
-                        .decrypt = aead_authenc_decrypt,
-                        .givencrypt = aead_authenc_givencrypt,
+                .type = CRYPTO_ALG_TYPE_AEAD,
+                .template_aead = {
+                        .setkey = aead_setkey,
+                        .setauthsize = aead_setauthsize,
+                        .encrypt = aead_encrypt,
+                        .decrypt = aead_decrypt,
+                        .givencrypt = aead_givencrypt,
                         .geniv = "<built-in>",
                         .ivsize = AES_BLOCK_SIZE,
                         .maxauthsize = SHA512_DIGEST_SIZE,
@@ -956,12 +1868,13 @@ static struct caam_alg_template driver_algs[] = {
                 .name = "authenc(hmac(sha1),cbc(des3_ede))",
                 .driver_name = "authenc-hmac-sha1-cbc-des3_ede-caam",
                 .blocksize = DES3_EDE_BLOCK_SIZE,
-                .aead = {
-                        .setkey = aead_authenc_setkey,
-                        .setauthsize = aead_authenc_setauthsize,
-                        .encrypt = aead_authenc_encrypt,
-                        .decrypt = aead_authenc_decrypt,
-                        .givencrypt = aead_authenc_givencrypt,
+                .type = CRYPTO_ALG_TYPE_AEAD,
+                .template_aead = {
+                        .setkey = aead_setkey,
+                        .setauthsize = aead_setauthsize,
+                        .encrypt = aead_encrypt,
+                        .decrypt = aead_decrypt,
+                        .givencrypt = aead_givencrypt,
                         .geniv = "<built-in>",
                         .ivsize = DES3_EDE_BLOCK_SIZE,
                         .maxauthsize = SHA1_DIGEST_SIZE,
@@ -974,12 +1887,13 @@ static struct caam_alg_template driver_algs[] = {
                 .name = "authenc(hmac(sha256),cbc(des3_ede))",
                 .driver_name = "authenc-hmac-sha256-cbc-des3_ede-caam",
                 .blocksize = DES3_EDE_BLOCK_SIZE,
-                .aead = {
-                        .setkey = aead_authenc_setkey,
-                        .setauthsize = aead_authenc_setauthsize,
-                        .encrypt = aead_authenc_encrypt,
-                        .decrypt = aead_authenc_decrypt,
-                        .givencrypt = aead_authenc_givencrypt,
+                .type = CRYPTO_ALG_TYPE_AEAD,
+                .template_aead = {
+                        .setkey = aead_setkey,
+                        .setauthsize = aead_setauthsize,
+                        .encrypt = aead_encrypt,
+                        .decrypt = aead_decrypt,
+                        .givencrypt = aead_givencrypt,
                         .geniv = "<built-in>",
                         .ivsize = DES3_EDE_BLOCK_SIZE,
                         .maxauthsize = SHA256_DIGEST_SIZE,
@@ -993,12 +1907,13 @@ static struct caam_alg_template driver_algs[] = {
                 .name = "authenc(hmac(sha512),cbc(des3_ede))",
                 .driver_name = "authenc-hmac-sha512-cbc-des3_ede-caam",
                 .blocksize = DES3_EDE_BLOCK_SIZE,
-                .aead = {
-                        .setkey = aead_authenc_setkey,
-                        .setauthsize = aead_authenc_setauthsize,
-                        .encrypt = aead_authenc_encrypt,
-                        .decrypt = aead_authenc_decrypt,
-                        .givencrypt = aead_authenc_givencrypt,
+                .type = CRYPTO_ALG_TYPE_AEAD,
+                .template_aead = {
+                        .setkey = aead_setkey,
+                        .setauthsize = aead_setauthsize,
+                        .encrypt = aead_encrypt,
+                        .decrypt = aead_decrypt,
+                        .givencrypt = aead_givencrypt,
                         .geniv = "<built-in>",
                         .ivsize = DES3_EDE_BLOCK_SIZE,
                         .maxauthsize = SHA512_DIGEST_SIZE,
@@ -1012,12 +1927,13 @@ static struct caam_alg_template driver_algs[] = {
                 .name = "authenc(hmac(sha1),cbc(des))",
                 .driver_name = "authenc-hmac-sha1-cbc-des-caam",
                 .blocksize = DES_BLOCK_SIZE,
-                .aead = {
-                        .setkey = aead_authenc_setkey,
-                        .setauthsize = aead_authenc_setauthsize,
-                        .encrypt = aead_authenc_encrypt,
-                        .decrypt = aead_authenc_decrypt,
-                        .givencrypt = aead_authenc_givencrypt,
+                .type = CRYPTO_ALG_TYPE_AEAD,
+                .template_aead = {
+                        .setkey = aead_setkey,
+                        .setauthsize = aead_setauthsize,
+                        .encrypt = aead_encrypt,
+                        .decrypt = aead_decrypt,
+                        .givencrypt = aead_givencrypt,
                         .geniv = "<built-in>",
                         .ivsize = DES_BLOCK_SIZE,
                         .maxauthsize = SHA1_DIGEST_SIZE,
@@ -1030,12 +1946,13 @@ static struct caam_alg_template driver_algs[] = {
                 .name = "authenc(hmac(sha256),cbc(des))",
                 .driver_name = "authenc-hmac-sha256-cbc-des-caam",
                 .blocksize = DES_BLOCK_SIZE,
-                .aead = {
-                        .setkey = aead_authenc_setkey,
-                        .setauthsize = aead_authenc_setauthsize,
-                        .encrypt = aead_authenc_encrypt,
-                        .decrypt = aead_authenc_decrypt,
-                        .givencrypt = aead_authenc_givencrypt,
+                .type = CRYPTO_ALG_TYPE_AEAD,
+                .template_aead = {
+                        .setkey = aead_setkey,
+                        .setauthsize = aead_setauthsize,
+                        .encrypt = aead_encrypt,
+                        .decrypt = aead_decrypt,
+                        .givencrypt = aead_givencrypt,
                         .geniv = "<built-in>",
                         .ivsize = DES_BLOCK_SIZE,
                         .maxauthsize = SHA256_DIGEST_SIZE,
@@ -1049,12 +1966,13 @@ static struct caam_alg_template driver_algs[] = {
                 .name = "authenc(hmac(sha512),cbc(des))",
                 .driver_name = "authenc-hmac-sha512-cbc-des-caam",
                 .blocksize = DES_BLOCK_SIZE,
-                .aead = {
-                        .setkey = aead_authenc_setkey,
-                        .setauthsize = aead_authenc_setauthsize,
-                        .encrypt = aead_authenc_encrypt,
-                        .decrypt = aead_authenc_decrypt,
-                        .givencrypt = aead_authenc_givencrypt,
+                .type = CRYPTO_ALG_TYPE_AEAD,
+                .template_aead = {
+                        .setkey = aead_setkey,
+                        .setauthsize = aead_setauthsize,
+                        .encrypt = aead_encrypt,
+                        .decrypt = aead_decrypt,
+                        .givencrypt = aead_givencrypt,
                         .geniv = "<built-in>",
                         .ivsize = DES_BLOCK_SIZE,
                         .maxauthsize = SHA512_DIGEST_SIZE,
@@ -1064,6 +1982,55 @@ static struct caam_alg_template driver_algs[] = {
                                    OP_ALG_AAI_HMAC_PRECOMP,
                 .alg_op = OP_ALG_ALGSEL_SHA512 | OP_ALG_AAI_HMAC,
         },
+        /* ablkcipher descriptor */
+        {
+                .name = "cbc(aes)",
+                .driver_name = "cbc-aes-caam",
+                .blocksize = AES_BLOCK_SIZE,
+                .type = CRYPTO_ALG_TYPE_ABLKCIPHER,
+                .template_ablkcipher = {
+                        .setkey = ablkcipher_setkey,
+                        .encrypt = ablkcipher_encrypt,
+                        .decrypt = ablkcipher_decrypt,
+                        .geniv = "eseqiv",
+                        .min_keysize = AES_MIN_KEY_SIZE,
+                        .max_keysize = AES_MAX_KEY_SIZE,
+                        .ivsize = AES_BLOCK_SIZE,
+                        },
+                .class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_CBC,
+        },
+        {
+                .name = "cbc(des3_ede)",
+                .driver_name = "cbc-3des-caam",
+                .blocksize = DES3_EDE_BLOCK_SIZE,
+                .type = CRYPTO_ALG_TYPE_ABLKCIPHER,
+                .template_ablkcipher = {
+                        .setkey = ablkcipher_setkey,
+                        .encrypt = ablkcipher_encrypt,
+                        .decrypt = ablkcipher_decrypt,
+                        .geniv = "eseqiv",
+                        .min_keysize = DES3_EDE_KEY_SIZE,
+                        .max_keysize = DES3_EDE_KEY_SIZE,
+                        .ivsize = DES3_EDE_BLOCK_SIZE,
+                        },
+                .class1_alg_type = OP_ALG_ALGSEL_3DES | OP_ALG_AAI_CBC,
+        },
+        {
+                .name = "cbc(des)",
+                .driver_name = "cbc-des-caam",
+                .blocksize = DES_BLOCK_SIZE,
+                .type = CRYPTO_ALG_TYPE_ABLKCIPHER,
+                .template_ablkcipher = {
+                        .setkey = ablkcipher_setkey,
+                        .encrypt = ablkcipher_encrypt,
+                        .decrypt = ablkcipher_decrypt,
+                        .geniv = "eseqiv",
+                        .min_keysize = DES_KEY_SIZE,
+                        .max_keysize = DES_KEY_SIZE,
+                        .ivsize = DES_BLOCK_SIZE,
+                        },
+                .class1_alg_type = OP_ALG_ALGSEL_DES | OP_ALG_AAI_CBC,
+        }
 };
 
 struct caam_crypto_alg {
@@ -1102,16 +2069,19 @@ static void caam_cra_exit(struct crypto_tfm *tfm)
 {
         struct caam_ctx *ctx = crypto_tfm_ctx(tfm);
 
-        if (!dma_mapping_error(ctx->jrdev, ctx->shared_desc_phys))
-                dma_unmap_single(ctx->jrdev, ctx->shared_desc_phys,
-                                 desc_bytes(ctx->sh_desc), DMA_TO_DEVICE);
-        kfree(ctx->sh_desc);
-
-        if (!dma_mapping_error(ctx->jrdev, ctx->key_phys))
-                dma_unmap_single(ctx->jrdev, ctx->key_phys,
-                                 ctx->split_key_pad_len + ctx->enckeylen,
+        if (ctx->sh_desc_enc_dma &&
+            !dma_mapping_error(ctx->jrdev, ctx->sh_desc_enc_dma))
+                dma_unmap_single(ctx->jrdev, ctx->sh_desc_enc_dma,
+                                 desc_bytes(ctx->sh_desc_enc), DMA_TO_DEVICE);
+        if (ctx->sh_desc_dec_dma &&
+            !dma_mapping_error(ctx->jrdev, ctx->sh_desc_dec_dma))
+                dma_unmap_single(ctx->jrdev, ctx->sh_desc_dec_dma,
+                                 desc_bytes(ctx->sh_desc_dec), DMA_TO_DEVICE);
+        if (ctx->sh_desc_givenc_dma &&
+            !dma_mapping_error(ctx->jrdev, ctx->sh_desc_givenc_dma))
+                dma_unmap_single(ctx->jrdev, ctx->sh_desc_givenc_dma,
+                                 desc_bytes(ctx->sh_desc_givenc),
                                  DMA_TO_DEVICE);
-        kfree(ctx->key);
 }
 
 static void __exit caam_algapi_exit(void)
@@ -1175,12 +2145,20 @@ static struct caam_crypto_alg *caam_alg_alloc(struct device *ctrldev,
         alg->cra_init = caam_cra_init;
         alg->cra_exit = caam_cra_exit;
         alg->cra_priority = CAAM_CRA_PRIORITY;
-        alg->cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC;
         alg->cra_blocksize = template->blocksize;
         alg->cra_alignmask = 0;
-        alg->cra_type = &crypto_aead_type;
         alg->cra_ctxsize = sizeof(struct caam_ctx);
-        alg->cra_u.aead = template->aead;
+        alg->cra_flags = CRYPTO_ALG_ASYNC | template->type;
+        switch (template->type) {
+        case CRYPTO_ALG_TYPE_ABLKCIPHER:
+                alg->cra_type = &crypto_ablkcipher_type;
+                alg->cra_ablkcipher = template->template_ablkcipher;
+                break;
+        case CRYPTO_ALG_TYPE_AEAD:
+                alg->cra_type = &crypto_aead_type;
+                alg->cra_aead = template->template_aead;
+                break;
+        }
 
         t_alg->class1_alg_type = template->class1_alg_type;
         t_alg->class2_alg_type = template->class2_alg_type;
diff --git a/drivers/crypto/caam/compat.h b/drivers/crypto/caam/compat.h
index 950450346f7..d38f2afaa96 100644
--- a/drivers/crypto/caam/compat.h
+++ b/drivers/crypto/caam/compat.h
@@ -31,5 +31,6 @@
 #include <crypto/aead.h>
 #include <crypto/authenc.h>
 #include <crypto/scatterwalk.h>
+#include <crypto/internal/skcipher.h>
 
 #endif /* !defined(CAAM_COMPAT_H) */
diff --git a/drivers/crypto/caam/ctrl.c b/drivers/crypto/caam/ctrl.c
index 9009713a3c2..73988bb7322 100644
--- a/drivers/crypto/caam/ctrl.c
+++ b/drivers/crypto/caam/ctrl.c
@@ -52,9 +52,11 @@ static int caam_probe(struct platform_device *pdev)
         struct caam_ctrl __iomem *ctrl;
         struct caam_full __iomem *topregs;
         struct caam_drv_private *ctrlpriv;
-        struct caam_perfmon *perfmon;
         struct caam_deco **deco;
         u32 deconum;
+#ifdef CONFIG_DEBUG_FS
+        struct caam_perfmon *perfmon;
+#endif
 
         ctrlpriv = kzalloc(sizeof(struct caam_drv_private), GFP_KERNEL);
         if (!ctrlpriv)
@@ -164,52 +166,52 @@ static int caam_probe(struct platform_device *pdev)
         /* Controller-level - performance monitor counters */
         ctrlpriv->ctl_rq_dequeued =
                 debugfs_create_u64("rq_dequeued",
-                                   S_IFCHR | S_IRUSR | S_IRGRP | S_IROTH,
+                                   S_IRUSR | S_IRGRP | S_IROTH,
                                    ctrlpriv->ctl, &perfmon->req_dequeued);
         ctrlpriv->ctl_ob_enc_req =
                 debugfs_create_u64("ob_rq_encrypted",
-                                   S_IFCHR | S_IRUSR | S_IRGRP | S_IROTH,
+                                   S_IRUSR | S_IRGRP | S_IROTH,
                                    ctrlpriv->ctl, &perfmon->ob_enc_req);
         ctrlpriv->ctl_ib_dec_req =
                 debugfs_create_u64("ib_rq_decrypted",
-                                   S_IFCHR | S_IRUSR | S_IRGRP | S_IROTH,
+                                   S_IRUSR | S_IRGRP | S_IROTH,
                                    ctrlpriv->ctl, &perfmon->ib_dec_req);
         ctrlpriv->ctl_ob_enc_bytes =
                 debugfs_create_u64("ob_bytes_encrypted",
-                                   S_IFCHR | S_IRUSR | S_IRGRP | S_IROTH,
+                                   S_IRUSR | S_IRGRP | S_IROTH,
                                    ctrlpriv->ctl, &perfmon->ob_enc_bytes);
         ctrlpriv->ctl_ob_prot_bytes =
                 debugfs_create_u64("ob_bytes_protected",
-                                   S_IFCHR | S_IRUSR | S_IRGRP | S_IROTH,
+                                   S_IRUSR | S_IRGRP | S_IROTH,
                                    ctrlpriv->ctl, &perfmon->ob_prot_bytes);
         ctrlpriv->ctl_ib_dec_bytes =
                 debugfs_create_u64("ib_bytes_decrypted",
-                                   S_IFCHR | S_IRUSR | S_IRGRP | S_IROTH,
+                                   S_IRUSR | S_IRGRP | S_IROTH,
                                    ctrlpriv->ctl, &perfmon->ib_dec_bytes);
         ctrlpriv->ctl_ib_valid_bytes =
                 debugfs_create_u64("ib_bytes_validated",
-                                   S_IFCHR | S_IRUSR | S_IRGRP | S_IROTH,
+                                   S_IRUSR | S_IRGRP | S_IROTH,
                                    ctrlpriv->ctl, &perfmon->ib_valid_bytes);
 
         /* Controller level - global status values */
         ctrlpriv->ctl_faultaddr =
                 debugfs_create_u64("fault_addr",
-                                   S_IFCHR | S_IRUSR | S_IRGRP | S_IROTH,
+                                   S_IRUSR | S_IRGRP | S_IROTH,
                                    ctrlpriv->ctl, &perfmon->faultaddr);
         ctrlpriv->ctl_faultdetail =
                 debugfs_create_u32("fault_detail",
-                                   S_IFCHR | S_IRUSR | S_IRGRP | S_IROTH,
+                                   S_IRUSR | S_IRGRP | S_IROTH,
                                    ctrlpriv->ctl, &perfmon->faultdetail);
         ctrlpriv->ctl_faultstatus =
                 debugfs_create_u32("fault_status",
-                                   S_IFCHR | S_IRUSR | S_IRGRP | S_IROTH,
+                                   S_IRUSR | S_IRGRP | S_IROTH,
                                    ctrlpriv->ctl, &perfmon->status);
 
         /* Internal covering keys (useful in non-secure mode only) */
         ctrlpriv->ctl_kek_wrap.data = &ctrlpriv->ctrl->kek[0];
         ctrlpriv->ctl_kek_wrap.size = KEK_KEY_SIZE * sizeof(u32);
         ctrlpriv->ctl_kek = debugfs_create_blob("kek",
-                                                S_IFCHR | S_IRUSR |
+                                                S_IRUSR |
                                                 S_IRGRP | S_IROTH,
                                                 ctrlpriv->ctl,
                                                 &ctrlpriv->ctl_kek_wrap);
@@ -217,7 +219,7 @@ static int caam_probe(struct platform_device *pdev)
         ctrlpriv->ctl_tkek_wrap.data = &ctrlpriv->ctrl->tkek[0];
         ctrlpriv->ctl_tkek_wrap.size = KEK_KEY_SIZE * sizeof(u32);
         ctrlpriv->ctl_tkek = debugfs_create_blob("tkek",
-                                                 S_IFCHR | S_IRUSR |
+                                                 S_IRUSR |
                                                  S_IRGRP | S_IROTH,
                                                  ctrlpriv->ctl,
                                                  &ctrlpriv->ctl_tkek_wrap);
@@ -225,7 +227,7 @@ static int caam_probe(struct platform_device *pdev)
         ctrlpriv->ctl_tdsk_wrap.data = &ctrlpriv->ctrl->tdsk[0];
         ctrlpriv->ctl_tdsk_wrap.size = KEK_KEY_SIZE * sizeof(u32);
         ctrlpriv->ctl_tdsk = debugfs_create_blob("tdsk",
-                                                 S_IFCHR | S_IRUSR |
+                                                 S_IRUSR |
                                                  S_IRGRP | S_IROTH,
                                                  ctrlpriv->ctl,
                                                  &ctrlpriv->ctl_tdsk_wrap);
diff --git a/drivers/crypto/caam/desc_constr.h b/drivers/crypto/caam/desc_constr.h
index 46915800c26..0991323cf3f 100644
--- a/drivers/crypto/caam/desc_constr.h
+++ b/drivers/crypto/caam/desc_constr.h
@@ -9,7 +9,7 @@
 #define IMMEDIATE (1 << 23)
 #define CAAM_CMD_SZ sizeof(u32)
 #define CAAM_PTR_SZ sizeof(dma_addr_t)
-#define CAAM_DESC_BYTES_MAX (CAAM_CMD_SZ * 64)
+#define CAAM_DESC_BYTES_MAX (CAAM_CMD_SZ * MAX_CAAM_DESCSIZE)
 
 #ifdef DEBUG
 #define PRINT_POS do { printk(KERN_DEBUG "%02d: %s\n", desc_len(desc),\
@@ -18,6 +18,9 @@
 #define PRINT_POS
 #endif
 
+#define SET_OK_PROP_ERRORS (IMMEDIATE | LDST_CLASS_DECO | \
+                            LDST_SRCDST_WORD_DECOCTRL | \
+                            (LDOFF_CHG_SHARE_OK_PROP << LDST_OFFSET_SHIFT))
 #define DISABLE_AUTO_INFO_FIFO (IMMEDIATE | LDST_CLASS_DECO | \
                                 LDST_SRCDST_WORD_DECOCTRL | \
                                 (LDOFF_DISABLE_AUTO_NFIFO << LDST_OFFSET_SHIFT))
@@ -203,3 +206,56 @@ static inline void append_##cmd##_imm_##type(u32 *desc, type immediate, \
         append_cmd(desc, immediate); \
 }
 APPEND_CMD_RAW_IMM(load, LOAD, u32);
+
+/*
+ * Append math command. Only the last part of destination and source need to
+ * be specified
+ */
+#define APPEND_MATH(op, desc, dest, src_0, src_1, len) \
+append_cmd(desc, CMD_MATH | MATH_FUN_##op | MATH_DEST_##dest | \
+           MATH_SRC0_##src_0 | MATH_SRC1_##src_1 | (u32) (len & MATH_LEN_MASK));
+
+#define append_math_add(desc, dest, src0, src1, len) \
+        APPEND_MATH(ADD, desc, dest, src0, src1, len)
+#define append_math_sub(desc, dest, src0, src1, len) \
+        APPEND_MATH(SUB, desc, dest, src0, src1, len)
+#define append_math_add_c(desc, dest, src0, src1, len) \
+        APPEND_MATH(ADDC, desc, dest, src0, src1, len)
+#define append_math_sub_b(desc, dest, src0, src1, len) \
+        APPEND_MATH(SUBB, desc, dest, src0, src1, len)
+#define append_math_and(desc, dest, src0, src1, len) \
+        APPEND_MATH(AND, desc, dest, src0, src1, len)
+#define append_math_or(desc, dest, src0, src1, len) \
+        APPEND_MATH(OR, desc, dest, src0, src1, len)
+#define append_math_xor(desc, dest, src0, src1, len) \
+        APPEND_MATH(XOR, desc, dest, src0, src1, len)
+#define append_math_lshift(desc, dest, src0, src1, len) \
+        APPEND_MATH(LSHIFT, desc, dest, src0, src1, len)
+#define append_math_rshift(desc, dest, src0, src1, len) \
+        APPEND_MATH(RSHIFT, desc, dest, src0, src1, len)
+
+/* Exactly one source is IMM. Data is passed in as u32 value */
+#define APPEND_MATH_IMM_u32(op, desc, dest, src_0, src_1, data) \
+do { \
+        APPEND_MATH(op, desc, dest, src_0, src_1, CAAM_CMD_SZ); \
+        append_cmd(desc, data); \
+} while (0);
+
+#define append_math_add_imm_u32(desc, dest, src0, src1, data) \
+        APPEND_MATH_IMM_u32(ADD, desc, dest, src0, src1, data)
+#define append_math_sub_imm_u32(desc, dest, src0, src1, data) \
+        APPEND_MATH_IMM_u32(SUB, desc, dest, src0, src1, data)
+#define append_math_add_c_imm_u32(desc, dest, src0, src1, data) \
+        APPEND_MATH_IMM_u32(ADDC, desc, dest, src0, src1, data)
+#define append_math_sub_b_imm_u32(desc, dest, src0, src1, data) \
+        APPEND_MATH_IMM_u32(SUBB, desc, dest, src0, src1, data)
+#define append_math_and_imm_u32(desc, dest, src0, src1, data) \
+        APPEND_MATH_IMM_u32(AND, desc, dest, src0, src1, data)
+#define append_math_or_imm_u32(desc, dest, src0, src1, data) \
+        APPEND_MATH_IMM_u32(OR, desc, dest, src0, src1, data)
+#define append_math_xor_imm_u32(desc, dest, src0, src1, data) \
+        APPEND_MATH_IMM_u32(XOR, desc, dest, src0, src1, data)
+#define append_math_lshift_imm_u32(desc, dest, src0, src1, data) \
+        APPEND_MATH_IMM_u32(LSHIFT, desc, dest, src0, src1, data)
+#define append_math_rshift_imm_u32(desc, dest, src0, src1, data) \
+        APPEND_MATH_IMM_u32(RSHIFT, desc, dest, src0, src1, data)
diff --git a/drivers/crypto/mv_cesa.c b/drivers/crypto/mv_cesa.c
index 3cf303ee3fe..38a3297ae2b 100644
--- a/drivers/crypto/mv_cesa.c
+++ b/drivers/crypto/mv_cesa.c
@@ -342,11 +342,13 @@ static void mv_process_hash_current(int first_block)
                 else
                         op.config |= CFG_MID_FRAG;
 
-                writel(req_ctx->state[0], cpg->reg + DIGEST_INITIAL_VAL_A);
-                writel(req_ctx->state[1], cpg->reg + DIGEST_INITIAL_VAL_B);
-                writel(req_ctx->state[2], cpg->reg + DIGEST_INITIAL_VAL_C);
-                writel(req_ctx->state[3], cpg->reg + DIGEST_INITIAL_VAL_D);
-                writel(req_ctx->state[4], cpg->reg + DIGEST_INITIAL_VAL_E);
+                if (first_block) {
+                        writel(req_ctx->state[0], cpg->reg + DIGEST_INITIAL_VAL_A);
+                        writel(req_ctx->state[1], cpg->reg + DIGEST_INITIAL_VAL_B);
+                        writel(req_ctx->state[2], cpg->reg + DIGEST_INITIAL_VAL_C);
+                        writel(req_ctx->state[3], cpg->reg + DIGEST_INITIAL_VAL_D);
+                        writel(req_ctx->state[4], cpg->reg + DIGEST_INITIAL_VAL_E);
+                }
         }
 
         memcpy(cpg->sram + SRAM_CONFIG, &op, sizeof(struct sec_accel_config));
diff --git a/drivers/crypto/n2_core.c b/drivers/crypto/n2_core.c
index 2e5b2044c96..d0183ddb307 100644
--- a/drivers/crypto/n2_core.c
+++ b/drivers/crypto/n2_core.c
@@ -1,6 +1,6 @@
 /* n2_core.c: Niagara2 Stream Processing Unit (SPU) crypto support.
  *
- * Copyright (C) 2010 David S. Miller <davem@davemloft.net>
+ * Copyright (C) 2010, 2011 David S. Miller <davem@davemloft.net>
  */
 
 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
@@ -31,8 +31,8 @@
 #include "n2_core.h"
 
 #define DRV_MODULE_NAME         "n2_crypto"
-#define DRV_MODULE_VERSION      "0.1"
-#define DRV_MODULE_RELDATE      "April 29, 2010"
+#define DRV_MODULE_VERSION      "0.2"
+#define DRV_MODULE_RELDATE      "July 28, 2011"
 
 static char version[] __devinitdata =
         DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
@@ -1823,22 +1823,17 @@ static int spu_mdesc_scan(struct mdesc_handle *mdesc, struct platform_device *de
 static int __devinit get_irq_props(struct mdesc_handle *mdesc, u64 node,
                                    struct spu_mdesc_info *ip)
 {
-        const u64 *intr, *ino;
-        int intr_len, ino_len;
+        const u64 *ino;
+        int ino_len;
         int i;
 
-        intr = mdesc_get_property(mdesc, node, "intr", &intr_len);
-        if (!intr)
-                return -ENODEV;
-
         ino = mdesc_get_property(mdesc, node, "ino", &ino_len);
-        if (!ino)
+        if (!ino) {
+                printk("NO 'ino'\n");
                 return -ENODEV;
+        }
 
-        if (intr_len != ino_len)
-                return -EINVAL;
-
-        ip->num_intrs = intr_len / sizeof(u64);
+        ip->num_intrs = ino_len / sizeof(u64);
         ip->ino_table = kzalloc((sizeof(struct ino_blob) *
                                  ip->num_intrs),
                                 GFP_KERNEL);
@@ -1847,7 +1842,7 @@ static int __devinit get_irq_props(struct mdesc_handle *mdesc, u64 node,
 
         for (i = 0; i < ip->num_intrs; i++) {
                 struct ino_blob *b = &ip->ino_table[i];
-                b->intr = intr[i];
+                b->intr = i + 1;
                 b->ino = ino[i];
         }
 
@@ -2204,6 +2199,10 @@ static struct of_device_id n2_crypto_match[] = {
                 .name = "n2cp",
                 .compatible = "SUNW,vf-cwq",
         },
+        {
+                .name = "n2cp",
+                .compatible = "SUNW,kt-cwq",
+        },
         {},
 };
 
@@ -2228,6 +2227,10 @@ static struct of_device_id n2_mau_match[] = {
                 .name = "ncp",
                 .compatible = "SUNW,vf-mau",
         },
+        {
+                .name = "ncp",
+                .compatible = "SUNW,kt-mau",
+        },
         {},
 };
 
diff --git a/drivers/crypto/omap-sham.c b/drivers/crypto/omap-sham.c
index ba8f1ea84c5..6399a8f1938 100644
--- a/drivers/crypto/omap-sham.c
+++ b/drivers/crypto/omap-sham.c
@@ -72,17 +72,20 @@
 
 #define DEFAULT_TIMEOUT_INTERVAL        HZ
 
-#define FLAGS_FINUP             0x0002
-#define FLAGS_FINAL             0x0004
-#define FLAGS_SG                0x0008
-#define FLAGS_SHA1              0x0010
-#define FLAGS_DMA_ACTIVE        0x0020
-#define FLAGS_OUTPUT_READY      0x0040
-#define FLAGS_INIT              0x0100
-#define FLAGS_CPU               0x0200
-#define FLAGS_HMAC              0x0400
-#define FLAGS_ERROR             0x0800
-#define FLAGS_BUSY              0x1000
+/* mostly device flags */
+#define FLAGS_BUSY              0
+#define FLAGS_FINAL             1
+#define FLAGS_DMA_ACTIVE        2
+#define FLAGS_OUTPUT_READY      3
+#define FLAGS_INIT              4
+#define FLAGS_CPU               5
+#define FLAGS_DMA_READY         6
+/* context flags */
+#define FLAGS_FINUP             16
+#define FLAGS_SG                17
+#define FLAGS_SHA1              18
+#define FLAGS_HMAC              19
+#define FLAGS_ERROR             20
 
 #define OP_UPDATE       1
 #define OP_FINAL        2
@@ -144,7 +147,6 @@ struct omap_sham_dev {
         int                     dma;
         int                     dma_lch;
         struct tasklet_struct   done_task;
-        struct tasklet_struct   queue_task;
 
         unsigned long           flags;
         struct crypto_queue     queue;
@@ -223,7 +225,7 @@ static void omap_sham_copy_ready_hash(struct ahash_request *req)
         if (!hash)
                 return;
 
-        if (likely(ctx->flags & FLAGS_SHA1)) {
+        if (likely(ctx->flags & BIT(FLAGS_SHA1))) {
                 /* SHA1 results are in big endian */
                 for (i = 0; i < SHA1_DIGEST_SIZE / sizeof(u32); i++)
                         hash[i] = be32_to_cpu(in[i]);
@@ -238,7 +240,7 @@ static int omap_sham_hw_init(struct omap_sham_dev *dd)
 {
         clk_enable(dd->iclk);
 
-        if (!(dd->flags & FLAGS_INIT)) {
+        if (!test_bit(FLAGS_INIT, &dd->flags)) {
                 omap_sham_write_mask(dd, SHA_REG_MASK,
                         SHA_REG_MASK_SOFTRESET, SHA_REG_MASK_SOFTRESET);
 
@@ -246,7 +248,7 @@ static int omap_sham_hw_init(struct omap_sham_dev *dd)
                                         SHA_REG_SYSSTATUS_RESETDONE))
                         return -ETIMEDOUT;
 
-                dd->flags |= FLAGS_INIT;
+                set_bit(FLAGS_INIT, &dd->flags);
                 dd->err = 0;
         }
 
@@ -269,7 +271,7 @@ static void omap_sham_write_ctrl(struct omap_sham_dev *dd, size_t length,
          * Setting ALGO_CONST only for the first iteration
          * and CLOSE_HASH only for the last one.
          */
-        if (ctx->flags & FLAGS_SHA1)
+        if (ctx->flags & BIT(FLAGS_SHA1))
                 val |= SHA_REG_CTRL_ALGO;
         if (!ctx->digcnt)
                 val |= SHA_REG_CTRL_ALGO_CONST;
@@ -301,7 +303,9 @@ static int omap_sham_xmit_cpu(struct omap_sham_dev *dd, const u8 *buf,
                 return -ETIMEDOUT;
 
         if (final)
-                ctx->flags |= FLAGS_FINAL; /* catch last interrupt */
+                set_bit(FLAGS_FINAL, &dd->flags); /* catch last interrupt */
+
+        set_bit(FLAGS_CPU, &dd->flags);
 
         len32 = DIV_ROUND_UP(length, sizeof(u32));
 
@@ -334,9 +338,9 @@ static int omap_sham_xmit_dma(struct omap_sham_dev *dd, dma_addr_t dma_addr,
         ctx->digcnt += length;
 
         if (final)
-                ctx->flags |= FLAGS_FINAL; /* catch last interrupt */
+                set_bit(FLAGS_FINAL, &dd->flags); /* catch last interrupt */
 
-        dd->flags |= FLAGS_DMA_ACTIVE;
+        set_bit(FLAGS_DMA_ACTIVE, &dd->flags);
 
         omap_start_dma(dd->dma_lch);
 
@@ -392,7 +396,7 @@ static int omap_sham_xmit_dma_map(struct omap_sham_dev *dd,
                 return -EINVAL;
         }
 
-        ctx->flags &= ~FLAGS_SG;
+        ctx->flags &= ~BIT(FLAGS_SG);
 
         /* next call does not fail... so no unmap in the case of error */
         return omap_sham_xmit_dma(dd, ctx->dma_addr, length, final);
@@ -406,7 +410,7 @@ static int omap_sham_update_dma_slow(struct omap_sham_dev *dd)
 
         omap_sham_append_sg(ctx);
 
-        final = (ctx->flags & FLAGS_FINUP) && !ctx->total;
+        final = (ctx->flags & BIT(FLAGS_FINUP)) && !ctx->total;
 
         dev_dbg(dd->dev, "slow: bufcnt: %u, digcnt: %d, final: %d\n",
                                          ctx->bufcnt, ctx->digcnt, final);
@@ -452,7 +456,7 @@ static int omap_sham_update_dma_start(struct omap_sham_dev *dd)
         length = min(ctx->total, sg->length);
 
         if (sg_is_last(sg)) {
-                if (!(ctx->flags & FLAGS_FINUP)) {
+                if (!(ctx->flags & BIT(FLAGS_FINUP))) {
                         /* not last sg must be SHA1_MD5_BLOCK_SIZE aligned */
                         tail = length & (SHA1_MD5_BLOCK_SIZE - 1);
                         /* without finup() we need one block to close hash */
@@ -467,12 +471,12 @@ static int omap_sham_update_dma_start(struct omap_sham_dev *dd)
                 return -EINVAL;
         }
 
-        ctx->flags |= FLAGS_SG;
+        ctx->flags |= BIT(FLAGS_SG);
 
         ctx->total -= length;
         ctx->offset = length; /* offset where to start slow */
 
-        final = (ctx->flags & FLAGS_FINUP) && !ctx->total;
+        final = (ctx->flags & BIT(FLAGS_FINUP)) && !ctx->total;
 
         /* next call does not fail... so no unmap in the case of error */
         return omap_sham_xmit_dma(dd, sg_dma_address(ctx->sg), length, final);
@@ -495,7 +499,7 @@ static int omap_sham_update_dma_stop(struct omap_sham_dev *dd)
         struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
 
         omap_stop_dma(dd->dma_lch);
-        if (ctx->flags & FLAGS_SG) {
+        if (ctx->flags & BIT(FLAGS_SG)) {
                 dma_unmap_sg(dd->dev, ctx->sg, 1, DMA_TO_DEVICE);
                 if (ctx->sg->length == ctx->offset) {
                         ctx->sg = sg_next(ctx->sg);
@@ -537,18 +541,18 @@ static int omap_sham_init(struct ahash_request *req)
                 crypto_ahash_digestsize(tfm));
 
         if (crypto_ahash_digestsize(tfm) == SHA1_DIGEST_SIZE)
-                ctx->flags |= FLAGS_SHA1;
+                ctx->flags |= BIT(FLAGS_SHA1);
 
         ctx->bufcnt = 0;
         ctx->digcnt = 0;
         ctx->buflen = BUFLEN;
 
-        if (tctx->flags & FLAGS_HMAC) {
+        if (tctx->flags & BIT(FLAGS_HMAC)) {
                 struct omap_sham_hmac_ctx *bctx = tctx->base;
 
                 memcpy(ctx->buffer, bctx->ipad, SHA1_MD5_BLOCK_SIZE);
                 ctx->bufcnt = SHA1_MD5_BLOCK_SIZE;
-                ctx->flags |= FLAGS_HMAC;
+                ctx->flags |= BIT(FLAGS_HMAC);
         }
 
         return 0;
@@ -562,9 +566,9 @@ static int omap_sham_update_req(struct omap_sham_dev *dd)
         int err;
 
         dev_dbg(dd->dev, "update_req: total: %u, digcnt: %d, finup: %d\n",
-                 ctx->total, ctx->digcnt, (ctx->flags & FLAGS_FINUP) != 0);
+                 ctx->total, ctx->digcnt, (ctx->flags & BIT(FLAGS_FINUP)) != 0);
 
-        if (ctx->flags & FLAGS_CPU)
+        if (ctx->flags & BIT(FLAGS_CPU))
                 err = omap_sham_update_cpu(dd);
         else
                 err = omap_sham_update_dma_start(dd);
@@ -624,7 +628,7 @@ static int omap_sham_finish(struct ahash_request *req)
 
         if (ctx->digcnt) {
                 omap_sham_copy_ready_hash(req);
-                if (ctx->flags & FLAGS_HMAC)
+                if (ctx->flags & BIT(FLAGS_HMAC))
                         err = omap_sham_finish_hmac(req);
         }
 
@@ -639,18 +643,23 @@ static void omap_sham_finish_req(struct ahash_request *req, int err)
         struct omap_sham_dev *dd = ctx->dd;
 
         if (!err) {
-                omap_sham_copy_hash(ctx->dd->req, 1);
-                if (ctx->flags & FLAGS_FINAL)
+                omap_sham_copy_hash(req, 1);
+                if (test_bit(FLAGS_FINAL, &dd->flags))
                         err = omap_sham_finish(req);
         } else {
-                ctx->flags |= FLAGS_ERROR;
+                ctx->flags |= BIT(FLAGS_ERROR);
         }
 
+        /* atomic operation is not needed here */
+        dd->flags &= ~(BIT(FLAGS_BUSY) | BIT(FLAGS_FINAL) | BIT(FLAGS_CPU) |
+                        BIT(FLAGS_DMA_READY) | BIT(FLAGS_OUTPUT_READY));
         clk_disable(dd->iclk);
-        dd->flags &= ~FLAGS_BUSY;
 
         if (req->base.complete)
                 req->base.complete(&req->base, err);
+
+        /* handle new request */
+        tasklet_schedule(&dd->done_task);
 }
 
 static int omap_sham_handle_queue(struct omap_sham_dev *dd,
@@ -658,21 +667,20 @@ static int omap_sham_handle_queue(struct omap_sham_dev *dd,
 {
         struct crypto_async_request *async_req, *backlog;
         struct omap_sham_reqctx *ctx;
-        struct ahash_request *prev_req;
         unsigned long flags;
         int err = 0, ret = 0;
 
         spin_lock_irqsave(&dd->lock, flags);
         if (req)
                 ret = ahash_enqueue_request(&dd->queue, req);
-        if (dd->flags & FLAGS_BUSY) {
+        if (test_bit(FLAGS_BUSY, &dd->flags)) {
                 spin_unlock_irqrestore(&dd->lock, flags);
                 return ret;
         }
         backlog = crypto_get_backlog(&dd->queue);
         async_req = crypto_dequeue_request(&dd->queue);
         if (async_req)
-                dd->flags |= FLAGS_BUSY;
+                set_bit(FLAGS_BUSY, &dd->flags);
         spin_unlock_irqrestore(&dd->lock, flags);
 
         if (!async_req)
@@ -682,16 +690,12 @@ static int omap_sham_handle_queue(struct omap_sham_dev *dd,
                 backlog->complete(backlog, -EINPROGRESS);
 
         req = ahash_request_cast(async_req);
-
-        prev_req = dd->req;
         dd->req = req;
-
         ctx = ahash_request_ctx(req);
 
         dev_dbg(dd->dev, "handling new req, op: %lu, nbytes: %d\n",
                                                 ctx->op, req->nbytes);
 
-
         err = omap_sham_hw_init(dd);
         if (err)
                 goto err1;
@@ -712,18 +716,16 @@ static int omap_sham_handle_queue(struct omap_sham_dev *dd,
 
         if (ctx->op == OP_UPDATE) {
                 err = omap_sham_update_req(dd);
-                if (err != -EINPROGRESS && (ctx->flags & FLAGS_FINUP))
+                if (err != -EINPROGRESS && (ctx->flags & BIT(FLAGS_FINUP)))
                         /* no final() after finup() */
                         err = omap_sham_final_req(dd);
         } else if (ctx->op == OP_FINAL) {
                 err = omap_sham_final_req(dd);
         }
 err1:
-        if (err != -EINPROGRESS) {
+        if (err != -EINPROGRESS)
                 /* done_task will not finish it, so do it here */
                 omap_sham_finish_req(req, err);
-                tasklet_schedule(&dd->queue_task);
-        }
 
         dev_dbg(dd->dev, "exit, err: %d\n", err);
 
@@ -752,7 +754,7 @@ static int omap_sham_update(struct ahash_request *req)
         ctx->sg = req->src;
         ctx->offset = 0;
 
-        if (ctx->flags & FLAGS_FINUP) {
+        if (ctx->flags & BIT(FLAGS_FINUP)) {
                 if ((ctx->digcnt + ctx->bufcnt + ctx->total) < 9) {
                         /*
                         * OMAP HW accel works only with buffers >= 9
@@ -765,7 +767,7 @@ static int omap_sham_update(struct ahash_request *req)
                         /*
                         * faster to use CPU for short transfers
                         */
-                        ctx->flags |= FLAGS_CPU;
+                        ctx->flags |= BIT(FLAGS_CPU);
                 }
         } else if (ctx->bufcnt + ctx->total < ctx->buflen) {
                 omap_sham_append_sg(ctx);
@@ -802,9 +804,9 @@ static int omap_sham_final(struct ahash_request *req)
 {
         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
 
-        ctx->flags |= FLAGS_FINUP;
+        ctx->flags |= BIT(FLAGS_FINUP);
 
-        if (ctx->flags & FLAGS_ERROR)
+        if (ctx->flags & BIT(FLAGS_ERROR))
                 return 0; /* uncompleted hash is not needed */
 
         /* OMAP HW accel works only with buffers >= 9 */
@@ -823,7 +825,7 @@ static int omap_sham_finup(struct ahash_request *req)
         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
         int err1, err2;
 
-        ctx->flags |= FLAGS_FINUP;
+        ctx->flags |= BIT(FLAGS_FINUP);
 
         err1 = omap_sham_update(req);
         if (err1 == -EINPROGRESS || err1 == -EBUSY)
@@ -895,7 +897,7 @@ static int omap_sham_cra_init_alg(struct crypto_tfm *tfm, const char *alg_base)
 
         if (alg_base) {
                 struct omap_sham_hmac_ctx *bctx = tctx->base;
-                tctx->flags |= FLAGS_HMAC;
+                tctx->flags |= BIT(FLAGS_HMAC);
                 bctx->shash = crypto_alloc_shash(alg_base, 0,
                                                 CRYPTO_ALG_NEED_FALLBACK);
                 if (IS_ERR(bctx->shash)) {
@@ -932,7 +934,7 @@ static void omap_sham_cra_exit(struct crypto_tfm *tfm)
         crypto_free_shash(tctx->fallback);
         tctx->fallback = NULL;
 
-        if (tctx->flags & FLAGS_HMAC) {
+        if (tctx->flags & BIT(FLAGS_HMAC)) {
                 struct omap_sham_hmac_ctx *bctx = tctx->base;
                 crypto_free_shash(bctx->shash);
         }
@@ -1036,51 +1038,46 @@ static struct ahash_alg algs[] = {
 static void omap_sham_done_task(unsigned long data)
 {
         struct omap_sham_dev *dd = (struct omap_sham_dev *)data;
-        struct ahash_request *req = dd->req;
-        struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
-        int ready = 0, err = 0;
+        int err = 0;
 
-        if (ctx->flags & FLAGS_OUTPUT_READY) {
-                ctx->flags &= ~FLAGS_OUTPUT_READY;
-                ready = 1;
+        if (!test_bit(FLAGS_BUSY, &dd->flags)) {
+                omap_sham_handle_queue(dd, NULL);
+                return;
         }
 
-        if (dd->flags & FLAGS_DMA_ACTIVE) {
-                dd->flags &= ~FLAGS_DMA_ACTIVE;
-                omap_sham_update_dma_stop(dd);
-                if (!dd->err)
+        if (test_bit(FLAGS_CPU, &dd->flags)) {
+                if (test_and_clear_bit(FLAGS_OUTPUT_READY, &dd->flags))
+                        goto finish;
+        } else if (test_bit(FLAGS_DMA_READY, &dd->flags)) {
+                if (test_and_clear_bit(FLAGS_DMA_ACTIVE, &dd->flags)) {
+                        omap_sham_update_dma_stop(dd);
+                        if (dd->err) {
+                                err = dd->err;
+                                goto finish;
+                        }
+                }
+                if (test_and_clear_bit(FLAGS_OUTPUT_READY, &dd->flags)) {
+                        /* hash or semi-hash ready */
+                        clear_bit(FLAGS_DMA_READY, &dd->flags);
                         err = omap_sham_update_dma_start(dd);
+                        if (err != -EINPROGRESS)
+                                goto finish;
+                }
         }
 
-        err = dd->err ? : err;
-
-        if (err != -EINPROGRESS && (ready || err)) {
-                dev_dbg(dd->dev, "update done: err: %d\n", err);
-                /* finish curent request */
-                omap_sham_finish_req(req, err);
-                /* start new request */
-                omap_sham_handle_queue(dd, NULL);
-        }
-}
-
-static void omap_sham_queue_task(unsigned long data)
-{
-        struct omap_sham_dev *dd = (struct omap_sham_dev *)data;
+        return;
 
-        omap_sham_handle_queue(dd, NULL);
+finish:
+        dev_dbg(dd->dev, "update done: err: %d\n", err);
+        /* finish curent request */
+        omap_sham_finish_req(dd->req, err);
 }
 
 static irqreturn_t omap_sham_irq(int irq, void *dev_id)
 {
         struct omap_sham_dev *dd = dev_id;
-        struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
-
-        if (!ctx) {
-                dev_err(dd->dev, "unknown interrupt.\n");
-                return IRQ_HANDLED;
-        }
 
-        if (unlikely(ctx->flags & FLAGS_FINAL))
+        if (unlikely(test_bit(FLAGS_FINAL, &dd->flags)))
                 /* final -> allow device to go to power-saving mode */
                 omap_sham_write_mask(dd, SHA_REG_CTRL, 0, SHA_REG_CTRL_LENGTH);
 
@@ -1088,8 +1085,12 @@ static irqreturn_t omap_sham_irq(int irq, void *dev_id)
                                  SHA_REG_CTRL_OUTPUT_READY);
         omap_sham_read(dd, SHA_REG_CTRL);
 
-        ctx->flags |= FLAGS_OUTPUT_READY;
-        dd->err = 0;
+        if (!test_bit(FLAGS_BUSY, &dd->flags)) {
+                dev_warn(dd->dev, "Interrupt when no active requests.\n");
+                return IRQ_HANDLED;
+        }
+
+        set_bit(FLAGS_OUTPUT_READY, &dd->flags);
         tasklet_schedule(&dd->done_task);
 
         return IRQ_HANDLED;
@@ -1102,9 +1103,10 @@ static void omap_sham_dma_callback(int lch, u16 ch_status, void *data)
         if (ch_status != OMAP_DMA_BLOCK_IRQ) {
                 pr_err("omap-sham DMA error status: 0x%hx\n", ch_status);
                 dd->err = -EIO;
-                dd->flags &= ~FLAGS_INIT; /* request to re-initialize */
+                clear_bit(FLAGS_INIT, &dd->flags);/* request to re-initialize */
         }
 
+        set_bit(FLAGS_DMA_READY, &dd->flags);
         tasklet_schedule(&dd->done_task);
 }
 
@@ -1151,7 +1153,6 @@ static int __devinit omap_sham_probe(struct platform_device *pdev)
         INIT_LIST_HEAD(&dd->list);
         spin_lock_init(&dd->lock);
         tasklet_init(&dd->done_task, omap_sham_done_task, (unsigned long)dd);
-        tasklet_init(&dd->queue_task, omap_sham_queue_task, (unsigned long)dd);
         crypto_init_queue(&dd->queue, OMAP_SHAM_QUEUE_LENGTH);
 
         dd->irq = -1;
@@ -1260,7 +1261,6 @@ static int __devexit omap_sham_remove(struct platform_device *pdev)
         for (i = 0; i < ARRAY_SIZE(algs); i++)
                 crypto_unregister_ahash(&algs[i]);
         tasklet_kill(&dd->done_task);
-        tasklet_kill(&dd->queue_task);
         iounmap(dd->io_base);
         clk_put(dd->iclk);
         omap_sham_dma_cleanup(dd);
diff --git a/drivers/crypto/talitos.c b/drivers/crypto/talitos.c
index 854e2632f9a..8a0bb417aa1 100644
--- a/drivers/crypto/talitos.c
+++ b/drivers/crypto/talitos.c
@@ -1,7 +1,7 @@
 /*
  * talitos - Freescale Integrated Security Engine (SEC) device driver
  *
- * Copyright (c) 2008-2010 Freescale Semiconductor, Inc.
+ * Copyright (c) 2008-2011 Freescale Semiconductor, Inc.
  *
  * Scatterlist Crypto API glue code copied from files with the following:
  * Copyright (c) 2006-2007 Herbert Xu <herbert@gondor.apana.org.au>
@@ -282,6 +282,7 @@ static int init_device(struct device *dev)
 /**
  * talitos_submit - submits a descriptor to the device for processing
  * @dev:        the SEC device to be used
+ * @ch:         the SEC device channel to be used
  * @desc:       the descriptor to be processed by the device
  * @callback:   whom to call when processing is complete
  * @context:    a handle for use by caller (optional)
@@ -290,7 +291,7 @@ static int init_device(struct device *dev)
  * callback must check err and feedback in descriptor header
  * for device processing status.
  */
-static int talitos_submit(struct device *dev, struct talitos_desc *desc,
+static int talitos_submit(struct device *dev, int ch, struct talitos_desc *desc,
                           void (*callback)(struct device *dev,
                                            struct talitos_desc *desc,
                                            void *context, int error),
@@ -298,15 +299,9 @@ static int talitos_submit(struct device *dev, struct talitos_desc *desc,
 {
         struct talitos_private *priv = dev_get_drvdata(dev);
         struct talitos_request *request;
-        unsigned long flags, ch;
+        unsigned long flags;
         int head;
 
-        /* select done notification */
-        desc->hdr |= DESC_HDR_DONE_NOTIFY;
-
-        /* emulate SEC's round-robin channel fifo polling scheme */
-        ch = atomic_inc_return(&priv->last_chan) & (priv->num_channels - 1);
-
         spin_lock_irqsave(&priv->chan[ch].head_lock, flags);
 
         if (!atomic_inc_not_zero(&priv->chan[ch].submit_count)) {
@@ -706,6 +701,7 @@ static void talitos_unregister_rng(struct device *dev)
 
 struct talitos_ctx {
         struct device *dev;
+        int ch;
         __be32 desc_hdr_template;
         u8 key[TALITOS_MAX_KEY_SIZE];
         u8 iv[TALITOS_MAX_IV_LENGTH];
@@ -1117,7 +1113,7 @@ static int ipsec_esp(struct talitos_edesc *edesc, struct aead_request *areq,
         map_single_talitos_ptr(dev, &desc->ptr[6], ivsize, ctx->iv, 0,
                                DMA_FROM_DEVICE);
 
-        ret = talitos_submit(dev, desc, callback, areq);
+        ret = talitos_submit(dev, ctx->ch, desc, callback, areq);
         if (ret != -EINPROGRESS) {
                 ipsec_esp_unmap(dev, edesc, areq);
                 kfree(edesc);
@@ -1382,22 +1378,11 @@ static int ablkcipher_setkey(struct crypto_ablkcipher *cipher,
                              const u8 *key, unsigned int keylen)
 {
         struct talitos_ctx *ctx = crypto_ablkcipher_ctx(cipher);
-        struct ablkcipher_alg *alg = crypto_ablkcipher_alg(cipher);
-
-        if (keylen > TALITOS_MAX_KEY_SIZE)
-                goto badkey;
-
-        if (keylen < alg->min_keysize || keylen > alg->max_keysize)
-                goto badkey;
 
         memcpy(&ctx->key, key, keylen);
         ctx->keylen = keylen;
 
         return 0;
-
-badkey:
-        crypto_ablkcipher_set_flags(cipher, CRYPTO_TFM_RES_BAD_KEY_LEN);
-        return -EINVAL;
 }
 
 static void common_nonsnoop_unmap(struct device *dev,
@@ -1433,7 +1418,6 @@ static void ablkcipher_done(struct device *dev,
 
 static int common_nonsnoop(struct talitos_edesc *edesc,
                            struct ablkcipher_request *areq,
-                           u8 *giv,
                            void (*callback) (struct device *dev,
                                              struct talitos_desc *desc,
                                              void *context, int error))
@@ -1453,7 +1437,7 @@ static int common_nonsnoop(struct talitos_edesc *edesc,
 
         /* cipher iv */
         ivsize = crypto_ablkcipher_ivsize(cipher);
-        map_single_talitos_ptr(dev, &desc->ptr[1], ivsize, giv ?: areq->info, 0,
+        map_single_talitos_ptr(dev, &desc->ptr[1], ivsize, areq->info, 0,
                                DMA_TO_DEVICE);
 
         /* cipher key */
@@ -1524,7 +1508,7 @@ static int common_nonsnoop(struct talitos_edesc *edesc,
         to_talitos_ptr(&desc->ptr[6], 0);
         desc->ptr[6].j_extent = 0;
 
-        ret = talitos_submit(dev, desc, callback, areq);
+        ret = talitos_submit(dev, ctx->ch, desc, callback, areq);
         if (ret != -EINPROGRESS) {
                 common_nonsnoop_unmap(dev, edesc, areq);
                 kfree(edesc);
@@ -1556,7 +1540,7 @@ static int ablkcipher_encrypt(struct ablkcipher_request *areq)
         /* set encrypt */
         edesc->desc.hdr = ctx->desc_hdr_template | DESC_HDR_MODE0_ENCRYPT;
 
-        return common_nonsnoop(edesc, areq, NULL, ablkcipher_done);
+        return common_nonsnoop(edesc, areq, ablkcipher_done);
 }
 
 static int ablkcipher_decrypt(struct ablkcipher_request *areq)
@@ -1572,7 +1556,7 @@ static int ablkcipher_decrypt(struct ablkcipher_request *areq)
 
         edesc->desc.hdr = ctx->desc_hdr_template | DESC_HDR_DIR_INBOUND;
 
-        return common_nonsnoop(edesc, areq, NULL, ablkcipher_done);
+        return common_nonsnoop(edesc, areq, ablkcipher_done);
 }
 
 static void common_nonsnoop_hash_unmap(struct device *dev,
@@ -1703,7 +1687,7 @@ static int common_nonsnoop_hash(struct talitos_edesc *edesc,
         /* last DWORD empty */
         desc->ptr[6] = zero_entry;
 
-        ret = talitos_submit(dev, desc, callback, areq);
+        ret = talitos_submit(dev, ctx->ch, desc, callback, areq);
         if (ret != -EINPROGRESS) {
                 common_nonsnoop_hash_unmap(dev, edesc, areq);
                 kfree(edesc);
@@ -2244,6 +2228,7 @@ static int talitos_cra_init(struct crypto_tfm *tfm)
         struct crypto_alg *alg = tfm->__crt_alg;
         struct talitos_crypto_alg *talitos_alg;
         struct talitos_ctx *ctx = crypto_tfm_ctx(tfm);
+        struct talitos_private *priv;
 
         if ((alg->cra_flags & CRYPTO_ALG_TYPE_MASK) == CRYPTO_ALG_TYPE_AHASH)
                 talitos_alg = container_of(__crypto_ahash_alg(alg),
@@ -2256,9 +2241,17 @@ static int talitos_cra_init(struct crypto_tfm *tfm)
         /* update context with ptr to dev */
         ctx->dev = talitos_alg->dev;
 
+        /* assign SEC channel to tfm in round-robin fashion */
+        priv = dev_get_drvdata(ctx->dev);
+        ctx->ch = atomic_inc_return(&priv->last_chan) &
+                  (priv->num_channels - 1);
+
         /* copy descriptor header template value */
         ctx->desc_hdr_template = talitos_alg->algt.desc_hdr_template;
 
+        /* select done notification */
+        ctx->desc_hdr_template |= DESC_HDR_DONE_NOTIFY;
+
         return 0;
 }
 
diff --git a/drivers/crypto/tegra-aes.c b/drivers/crypto/tegra-aes.c
new file mode 100644
index 00000000000..22a96ed343e
--- /dev/null
+++ b/drivers/crypto/tegra-aes.c
@@ -0,0 +1,1496 @@
+/*
+ * drivers/crypto/tegra-aes.c
+ *
+ * aes driver for NVIDIA tegra aes hardware
+ *
+ * Copyright (c) 2010-2011, NVIDIA Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/errno.h>
+#include <linux/kernel.h>
+#include <linux/clk.h>
+#include <linux/platform_device.h>
+#include <linux/scatterlist.h>
+#include <linux/dma-mapping.h>
+#include <linux/io.h>
+#include <linux/mutex.h>
+#include <linux/interrupt.h>
+#include <linux/completion.h>
+#include <linux/workqueue.h>
+#include <linux/delay.h>
+
+#include <mach/arb_sema.h>
+#include <mach/clk.h>
+#include "../video/tegra/nvmap/nvmap.h"
+
+#include <crypto/scatterwalk.h>
+#include <crypto/aes.h>
+#include <crypto/internal/rng.h>
+
+#include "tegra-aes.h"
+
+#define FLAGS_MODE_MASK         0x00ff
+#define FLAGS_ENCRYPT           BIT(0)
+#define FLAGS_CBC               BIT(1)
+#define FLAGS_GIV               BIT(2)
+#define FLAGS_RNG               BIT(3)
+#define FLAGS_OFB               BIT(4)
+#define FLAGS_INIT              BIT(5)
+#define FLAGS_BUSY              1
+
+/*
+ * Defines AES engine Max process bytes size in one go, which takes 1 msec.
+ * AES engine spends about 176 cycles/16-bytes or 11 cycles/byte
+ * The duration CPU can use the BSE to 1 msec, then the number of available
+ * cycles of AVP/BSE is 216K. In this duration, AES can process 216/11 ~= 19KB
+ * Based on this AES_HW_DMA_BUFFER_SIZE_BYTES is configured to 16KB.
+ */
+#define AES_HW_DMA_BUFFER_SIZE_BYTES    0x4000
+
+/*
+ * The key table length is 64 bytes
+ * (This includes first upto 32 bytes key + 16 bytes original initial vector
+ * and 16 bytes updated initial vector)
+ */
+#define AES_HW_KEY_TABLE_LENGTH_BYTES   64
+
+#define AES_HW_IV_SIZE  16
+#define AES_HW_KEYSCHEDULE_LEN  256
+#define ARB_SEMA_TIMEOUT        500
+
+/*
+ * The memory being used is divides as follows:
+ * 1. Key - 32 bytes
+ * 2. Original IV - 16 bytes
+ * 3. Updated IV - 16 bytes
+ * 4. Key schedule - 256 bytes
+ *
+ * 1+2+3 constitute the hw key table.
+ */
+#define AES_IVKEY_SIZE (AES_HW_KEY_TABLE_LENGTH_BYTES + AES_HW_KEYSCHEDULE_LEN)
+
+#define DEFAULT_RNG_BLK_SZ      16
+
+/* As of now only 5 commands are USED for AES encryption/Decryption */
+#define AES_HW_MAX_ICQ_LENGTH   4
+
+#define ICQBITSHIFT_BLKCNT      0
+
+/* memdma_vd command */
+#define MEMDMA_DIR_DTOVRAM      0
+#define MEMDMA_DIR_VTODRAM      1
+#define MEMDMABITSHIFT_DIR      25
+#define MEMDMABITSHIFT_NUM_WORDS        12
+
+/* Define AES Interactive command Queue commands Bit positions */
+enum {
+        ICQBITSHIFT_KEYTABLEADDR = 0,
+        ICQBITSHIFT_KEYTABLEID = 17,
+        ICQBITSHIFT_VRAMSEL = 23,
+        ICQBITSHIFT_TABLESEL = 24,
+        ICQBITSHIFT_OPCODE = 26,
+};
+
+/* Define Ucq opcodes required for AES operation */
+enum {
+        UCQOPCODE_BLKSTARTENGINE = 0x0E,
+        UCQOPCODE_DMASETUP = 0x10,
+        UCQOPCODE_DMACOMPLETE = 0x11,
+        UCQOPCODE_SETTABLE = 0x15,
+        UCQOPCODE_MEMDMAVD = 0x22,
+};
+
+/* Define Aes command values */
+enum {
+        UCQCMD_VRAM_SEL = 0x1,
+        UCQCMD_CRYPTO_TABLESEL = 0x3,
+        UCQCMD_KEYSCHEDTABLESEL = 0x4,
+        UCQCMD_KEYTABLESEL = 0x8,
+};
+
+#define UCQCMD_KEYTABLEADDRMASK 0x1FFFF
+
+#define AES_NR_KEYSLOTS 8
+#define SSK_SLOT_NUM    4
+
+struct tegra_aes_slot {
+        struct list_head node;
+        int slot_num;
+        bool available;
+};
+
+struct tegra_aes_reqctx {
+        unsigned long mode;
+};
+
+#define TEGRA_AES_QUEUE_LENGTH  500
+
+struct tegra_aes_engine {
+        struct tegra_aes_dev *dd;
+        struct tegra_aes_ctx *ctx;
+        struct clk *iclk;
+        struct clk *pclk;
+        struct ablkcipher_request *req;
+        struct scatterlist *in_sg;
+        struct completion op_complete;
+        struct scatterlist *out_sg;
+        void __iomem *io_base;
+        void __iomem *ivkey_base;
+        unsigned long phys_base;
+        unsigned long iram_phys;
+        void *iram_virt;
+        dma_addr_t ivkey_phys_base;
+        dma_addr_t dma_buf_in;
+        dma_addr_t dma_buf_out;
+        size_t total;
+        size_t in_offset;
+        size_t out_offset;
+        u32 engine_offset;
+        u32 *buf_in;
+        u32 *buf_out;
+        int res_id;
+        unsigned long busy;
+        u8 irq;
+        u32 status;
+};
+
+struct tegra_aes_dev {
+        struct device *dev;
+        struct tegra_aes_slot *slots;
+        struct tegra_aes_engine bsev;
+        struct tegra_aes_engine bsea;
+        struct nvmap_client *client;
+        struct nvmap_handle_ref *h_ref;
+        struct crypto_queue queue;
+        spinlock_t lock;
+        u64 ctr;
+        unsigned long flags;
+        u8 dt[DEFAULT_RNG_BLK_SZ];
+};
+
+static struct tegra_aes_dev *aes_dev;
+
+struct tegra_aes_ctx {
+        struct tegra_aes_dev *dd;
+        struct tegra_aes_engine *eng;
+        struct tegra_aes_slot *slot;
+        int key[AES_MAX_KEY_SIZE];
+        int keylen;
+        bool use_ssk;
+        u8 dt[DEFAULT_RNG_BLK_SZ];
+};
+
+static struct tegra_aes_ctx rng_ctx;
+
+/* keep registered devices data here */
+static LIST_HEAD(slot_list);
+static DEFINE_SPINLOCK(list_lock);
+
+/* Engine specific work queues */
+static void bsev_workqueue_handler(struct work_struct *work);
+static void bsea_workqueue_handler(struct work_struct *work);
+
+static DECLARE_WORK(bsev_work, bsev_workqueue_handler);
+static DECLARE_WORK(bsea_work, bsea_workqueue_handler);
+
+static struct workqueue_struct *bsev_wq;
+static struct workqueue_struct *bsea_wq;
+
+extern unsigned long long tegra_chip_uid(void);
+
+static inline u32 aes_readl(struct tegra_aes_engine *engine, u32 offset)
+{
+        return readl(engine->io_base + offset);
+}
+
+static inline void aes_writel(struct tegra_aes_engine *engine,
+        u32 val, u32 offset)
+{
+        writel(val, engine->io_base + offset);
+}
+
+static int alloc_iram(struct tegra_aes_dev *dd)
+{
+        size_t size;
+        int err;
+
+        dd->h_ref = NULL;
+
+        /* [key+iv+u-iv=64B] * 8 = 512Bytes */
+        size = AES_MAX_KEY_SIZE;
+        dd->client = nvmap_create_client(nvmap_dev, "aes_bsea");
+        if (IS_ERR(dd->client)) {
+                dev_err(dd->dev, "nvmap_create_client failed\n");
+                goto out;
+        }
+
+        dd->h_ref = nvmap_create_handle(dd->client, size);
+        if (IS_ERR(dd->h_ref)) {
+                dev_err(dd->dev, "nvmap_create_handle failed\n");
+                goto out;
+        }
+
+        /* Allocate memory in the iram */
+        err = nvmap_alloc_handle_id(dd->client, nvmap_ref_to_id(dd->h_ref),
+                NVMAP_HEAP_CARVEOUT_IRAM, size, 0);
+        if (err) {
+                dev_err(dd->dev, "nvmap_alloc_handle_id failed\n");
+                nvmap_free_handle_id(dd->client, nvmap_ref_to_id(dd->h_ref));
+                goto out;
+        }
+        dd->bsea.iram_phys = nvmap_handle_address(dd->client,
+                                        nvmap_ref_to_id(dd->h_ref));
+
+        dd->bsea.iram_virt = nvmap_mmap(dd->h_ref);     /* get virtual address */
+        if (!dd->bsea.iram_virt) {
+                dev_err(dd->dev, "%s: no mem, BSEA IRAM alloc failure\n",
+                        __func__);
+                goto out;
+        }
+
+        memset(dd->bsea.iram_virt, 0, size);
+        return 0;
+
+out:
+        if (dd->bsea.iram_virt)
+                nvmap_munmap(dd->h_ref, dd->bsea.iram_virt);
+
+        if (dd->client) {
+                nvmap_free_handle_id(dd->client, nvmap_ref_to_id(dd->h_ref));
+                nvmap_client_put(dd->client);
+        }
+
+        return -ENOMEM;
+}
+
+static void free_iram(struct tegra_aes_dev *dd)
+{
+        if (dd->bsea.iram_virt)
+                nvmap_munmap(dd->h_ref, dd->bsea.iram_virt);
+
+        if (dd->client) {
+                nvmap_free_handle_id(dd->client, nvmap_ref_to_id(dd->h_ref));
+                nvmap_client_put(dd->client);
+        }
+}
+
+static int aes_hw_init(struct tegra_aes_engine *engine)
+{
+        struct tegra_aes_dev *dd = aes_dev;
+        int ret = 0;
+
+        if (engine->pclk) {
+                ret = clk_enable(engine->pclk);
+                if (ret < 0) {
+                        dev_err(dd->dev, "%s: pclock enable fail(%d)\n",
+                        __func__, ret);
+                        return ret;
+                }
+        }
+
+        if (engine->iclk) {
+                ret = clk_enable(engine->iclk);
+                if (ret < 0) {
+                        dev_err(dd->dev, "%s: iclock enable fail(%d)\n",
+                        __func__, ret);
+                        if (engine->pclk)
+                                clk_disable(engine->pclk);
+                        return ret;
+                }
+        }
+
+        return ret;
+}
+
+static void aes_hw_deinit(struct tegra_aes_engine *engine)
+{
+        if (engine->pclk)
+                clk_disable(engine->pclk);
+
+        if (engine->iclk)
+                clk_disable(engine->iclk);
+}
+
+#define MIN_RETRIES     3
+static int aes_start_crypt(struct tegra_aes_engine *eng, u32 in_addr,
+        u32 out_addr, int nblocks, int mode, bool upd_iv)
+{
+        u32 cmdq[AES_HW_MAX_ICQ_LENGTH];
+        int qlen = 0, i, eng_busy, icq_empty, ret;
+        u32 value;
+        int retries = MIN_RETRIES;
+
+start:
+        do {
+                value = aes_readl(eng, INTR_STATUS);
+                eng_busy = value & BIT(0);
+                icq_empty = value & BIT(3);
+        } while (eng_busy || (!icq_empty));
+
+        aes_writel(eng, 0xFFFFFFFF, INTR_STATUS);
+
+        /* error, dma xfer complete */
+        aes_writel(eng, 0x33, INT_ENB);
+        enable_irq(eng->irq);
+
+        cmdq[qlen++] = UCQOPCODE_DMASETUP << ICQBITSHIFT_OPCODE;
+        cmdq[qlen++] = in_addr;
+        cmdq[qlen++] = UCQOPCODE_BLKSTARTENGINE << ICQBITSHIFT_OPCODE |
+                (nblocks-1) << ICQBITSHIFT_BLKCNT;
+        cmdq[qlen++] = UCQOPCODE_DMACOMPLETE << ICQBITSHIFT_OPCODE;
+
+        value = aes_readl(eng, CMDQUE_CONTROL);
+        /* access SDRAM through AHB */
+        value &= (~CMDQ_CTRL_SRC_STM_SEL_FIELD & ~CMDQ_CTRL_DST_STM_SEL_FIELD);
+        value |= (CMDQ_CTRL_SRC_STM_SEL_FIELD | CMDQ_CTRL_DST_STM_SEL_FIELD |
+                CMDQ_CTRL_ICMDQEN_FIELD | CMDQ_CTRL_ERROR_FLUSH_ENB);
+        aes_writel(eng, value, CMDQUE_CONTROL);
+
+        value = 0;
+        if (mode & FLAGS_CBC) {
+                value = ((0x1 << SECURE_INPUT_ALG_SEL_SHIFT) |
+                        ((eng->ctx->keylen * 8) << SECURE_INPUT_KEY_LEN_SHIFT) |
+                        ((u32)upd_iv << SECURE_IV_SELECT_SHIFT) |
+                        (((mode & FLAGS_ENCRYPT) ? 2 : 3)
+                                << SECURE_XOR_POS_SHIFT) |
+                        (0 << SECURE_INPUT_SEL_SHIFT) |
+                        (((mode & FLAGS_ENCRYPT) ? 2 : 3)
+                                << SECURE_VCTRAM_SEL_SHIFT) |
+                        ((mode & FLAGS_ENCRYPT) ? 1 : 0)
+                                << SECURE_CORE_SEL_SHIFT |
+                        (0 << SECURE_RNG_ENB_SHIFT) |
+                        (0 << SECURE_HASH_ENB_SHIFT));
+        } else if (mode & FLAGS_OFB) {
+                value = ((0x1 << SECURE_INPUT_ALG_SEL_SHIFT) |
+                        ((eng->ctx->keylen * 8) << SECURE_INPUT_KEY_LEN_SHIFT) |
+                        ((u32)upd_iv << SECURE_IV_SELECT_SHIFT) |
+                        ((u32)0 << SECURE_IV_SELECT_SHIFT) |
+                        (SECURE_XOR_POS_FIELD) |
+                        (2 << SECURE_INPUT_SEL_SHIFT) |
+                        (0 << SECURE_VCTRAM_SEL_SHIFT) |
+                        (SECURE_CORE_SEL_FIELD) |
+                        (0 << SECURE_RNG_ENB_SHIFT) |
+                        (0 << SECURE_HASH_ENB_SHIFT));
+        } else if (mode & FLAGS_RNG){
+                value = ((0x1 << SECURE_INPUT_ALG_SEL_SHIFT) |
+                        ((eng->ctx->keylen * 8) << SECURE_INPUT_KEY_LEN_SHIFT) |
+                        ((u32)upd_iv << SECURE_IV_SELECT_SHIFT) |
+                        (0 << SECURE_XOR_POS_SHIFT) |
+                        (0 << SECURE_INPUT_SEL_SHIFT) |
+                        ((mode & FLAGS_ENCRYPT) ? 1 : 0)
+                                << SECURE_CORE_SEL_SHIFT |
+                        (1 << SECURE_RNG_ENB_SHIFT) |
+                        (0 << SECURE_HASH_ENB_SHIFT));
+        } else {
+                value = ((0x1 << SECURE_INPUT_ALG_SEL_SHIFT) |
+                        ((eng->ctx->keylen * 8) << SECURE_INPUT_KEY_LEN_SHIFT) |
+                        ((u32)upd_iv << SECURE_IV_SELECT_SHIFT) |
+                        (0 << SECURE_XOR_POS_SHIFT) |
+                        (0 << SECURE_INPUT_SEL_SHIFT) |
+                        (((mode & FLAGS_ENCRYPT) ? 1 : 0)
+                                << SECURE_CORE_SEL_SHIFT) |
+                        (0 << SECURE_RNG_ENB_SHIFT) |
+                                (0 << SECURE_HASH_ENB_SHIFT));
+        }
+        aes_writel(eng, value, SECURE_INPUT_SELECT);
+
+        aes_writel(eng, out_addr, SECURE_DEST_ADDR);
+        INIT_COMPLETION(eng->op_complete);
+
+        for (i = 0; i < qlen - 1; i++) {
+                do {
+                        value = aes_readl(eng, INTR_STATUS);
+                        eng_busy = value & BIT(0);
+                        icq_empty = value & BIT(3);
+                } while (eng_busy || (!icq_empty));
+                aes_writel(eng, cmdq[i], ICMDQUE_WR);
+        }
+
+        ret = wait_for_completion_timeout(&eng->op_complete,
+                msecs_to_jiffies(150));
+        if (ret == 0) {
+                dev_err(aes_dev->dev, "engine%d timed out (0x%x)\n",
+                        eng->res_id, aes_readl(eng, INTR_STATUS));
+                disable_irq(eng->irq);
+                return -ETIMEDOUT;
+        }
+
+        disable_irq(eng->irq);
+        aes_writel(eng, cmdq[qlen - 1], ICMDQUE_WR);
+
+        if ((eng->status != 0) && (retries-- > 0)) {
+                qlen = 0;
+                goto start;
+        }
+
+        return 0;
+}
+
+static void aes_release_key_slot(struct tegra_aes_ctx *ctx)
+{
+        spin_lock(&list_lock);
+        ctx->slot->available = true;
+        ctx->slot = NULL;
+        spin_unlock(&list_lock);
+}
+
+static struct tegra_aes_slot *aes_find_key_slot(struct tegra_aes_dev *dd)
+{
+        struct tegra_aes_slot *slot = NULL;
+        bool found = 0;
+
+        spin_lock(&list_lock);
+        list_for_each_entry(slot, &slot_list, node) {
+                dev_dbg(dd->dev, "empty:%d, num:%d\n", slot->available,
+                        slot->slot_num);
+                if (slot->available) {
+                        slot->available = false;
+                        found = 1;
+                        break;
+                }
+        }
+
+        spin_unlock(&list_lock);
+        return found ? slot : NULL;
+}
+
+static int aes_set_key(struct tegra_aes_engine *eng, int slot_num)
+{
+        struct tegra_aes_dev *dd = aes_dev;
+        u32 value, cmdq[2];
+        int i, eng_busy, icq_empty, dma_busy;
+
+        if (!eng) {
+                dev_err(dd->dev, "%s: context invalid\n", __func__);
+                return -EINVAL;
+        }
+
+        /* enable key schedule generation in hardware */
+        value = aes_readl(eng, SECURE_CONFIG_EXT);
+        value &= ~SECURE_KEY_SCH_DIS_FIELD;
+        aes_writel(eng, value, SECURE_CONFIG_EXT);
+
+        /* select the key slot */
+        value = aes_readl(eng, SECURE_CONFIG);
+        value &= ~SECURE_KEY_INDEX_FIELD;
+        value |= (slot_num << SECURE_KEY_INDEX_SHIFT);
+        aes_writel(eng, value, SECURE_CONFIG);
+
+        if (slot_num == SSK_SLOT_NUM)
+                goto out;
+
+        if (eng->res_id == TEGRA_ARB_BSEV) {
+                memset(dd->bsev.ivkey_base, 0, AES_HW_KEY_TABLE_LENGTH_BYTES);
+                memcpy(dd->bsev.ivkey_base, eng->ctx->key, eng->ctx->keylen);
+
+                /* copy the key table from sdram to vram */
+                cmdq[0] = 0;
+                cmdq[0] = UCQOPCODE_MEMDMAVD << ICQBITSHIFT_OPCODE |
+                                (MEMDMA_DIR_DTOVRAM << MEMDMABITSHIFT_DIR) |
+                        (AES_HW_KEY_TABLE_LENGTH_BYTES/sizeof(u32))
+                        << MEMDMABITSHIFT_NUM_WORDS;
+                cmdq[1] = (u32)eng->ivkey_phys_base;
+                for (i = 0; i < ARRAY_SIZE(cmdq); i++)
+                        aes_writel(eng, cmdq[i], ICMDQUE_WR);
+                do {
+                        value = aes_readl(eng, INTR_STATUS);
+                        eng_busy = value & BIT(0);
+                        icq_empty = value & BIT(3);
+                        dma_busy = value & BIT(23);
+                } while (eng_busy & (!icq_empty) & dma_busy);
+
+                /* settable command to get key into internal registers */
+                value = 0;
+                value = UCQOPCODE_SETTABLE << ICQBITSHIFT_OPCODE |
+                        UCQCMD_CRYPTO_TABLESEL << ICQBITSHIFT_TABLESEL |
+                        UCQCMD_VRAM_SEL << ICQBITSHIFT_VRAMSEL |
+                        (UCQCMD_KEYTABLESEL | slot_num)
+                        << ICQBITSHIFT_KEYTABLEID;
+                aes_writel(eng, value, ICMDQUE_WR);
+                do {
+                        value = aes_readl(eng, INTR_STATUS);
+                        eng_busy = value & BIT(0);
+                        icq_empty = value & BIT(3);
+                } while (eng_busy & (!icq_empty));
+        } else {
+                memset(dd->bsea.iram_virt, 0, AES_HW_KEY_TABLE_LENGTH_BYTES);
+                memcpy(dd->bsea.iram_virt, eng->ctx->key, eng->ctx->keylen);
+
+                /* set iram access cfg bit 0 if address >128K */
+                if (dd->bsea.iram_phys > 0x00020000)
+                        aes_writel(eng, BIT(0), IRAM_ACCESS_CFG);
+                else
+                        aes_writel(eng, 0, IRAM_ACCESS_CFG);
+
+                /* settable command to get key into internal registers */
+                value = 0;
+                value = UCQOPCODE_SETTABLE << ICQBITSHIFT_OPCODE |
+                        UCQCMD_CRYPTO_TABLESEL << ICQBITSHIFT_TABLESEL |
+                        (UCQCMD_KEYTABLESEL | slot_num)
+                        << ICQBITSHIFT_KEYTABLEID |
+                        dd->bsea.iram_phys >> 2;
+                        aes_writel(eng, value, ICMDQUE_WR);
+                do {
+                        value = aes_readl(eng, INTR_STATUS);
+                        eng_busy = value & BIT(0);
+                        icq_empty = value & BIT(3);
+                } while (eng_busy & (!icq_empty));
+        }
+
+out:
+        return 0;
+}
+
+static int tegra_aes_handle_req(struct tegra_aes_engine *eng)
+{
+        struct tegra_aes_dev *dd = aes_dev;
+        struct tegra_aes_ctx *ctx;
+        struct crypto_async_request *async_req, *backlog;
+        struct tegra_aes_reqctx *rctx;
+        struct ablkcipher_request *req;
+        unsigned long irq_flags;
+        int dma_max = AES_HW_DMA_BUFFER_SIZE_BYTES;
+        int nblocks, total, ret = 0, count = 0;
+        dma_addr_t addr_in, addr_out;
+        struct scatterlist *in_sg, *out_sg;
+
+        spin_lock_irqsave(&dd->lock, irq_flags);
+        backlog = crypto_get_backlog(&dd->queue);
+        async_req = crypto_dequeue_request(&dd->queue);
+        if (!async_req)
+                clear_bit(FLAGS_BUSY, &eng->busy);
+        spin_unlock_irqrestore(&dd->lock, irq_flags);
+
+        if (!async_req)
+                return -ENODATA;
+
+        if (backlog)
+                backlog->complete(backlog, -EINPROGRESS);
+
+        req = ablkcipher_request_cast(async_req);
+        dev_dbg(dd->dev, "%s: get new req (engine #%d)\n", __func__,
+                eng->res_id);
+
+        if (!req->src || !req->dst)
+                return -EINVAL;
+
+        /* take the hardware semaphore */
+        if (tegra_arb_mutex_lock_timeout(eng->res_id, ARB_SEMA_TIMEOUT) < 0) {
+                dev_err(dd->dev, "aes hardware (%d) not available\n",
+                eng->res_id);
+                return -EBUSY;
+        }
+
+        /* assign new request to device */
+        eng->req = req;
+        eng->total = req->nbytes;
+        eng->in_offset = 0;
+        eng->in_sg = req->src;
+        eng->out_offset = 0;
+        eng->out_sg = req->dst;
+
+        in_sg = eng->in_sg;
+        out_sg = eng->out_sg;
+        total = eng->total;
+
+        rctx = ablkcipher_request_ctx(req);
+        ctx = crypto_ablkcipher_ctx(crypto_ablkcipher_reqtfm(req));
+        rctx->mode &= FLAGS_MODE_MASK;
+        dd->flags = (dd->flags & ~FLAGS_MODE_MASK) | rctx->mode;
+        eng->ctx = ctx;
+
+        if (((dd->flags & FLAGS_CBC) || (dd->flags & FLAGS_OFB)) && req->info) {
+                /* set iv to the aes hw slot
+                 * Hw generates updated iv only after iv is set in slot.
+                 * So key and iv is passed asynchronously.
+                */
+                memcpy(eng->buf_in, (u8 *)req->info, AES_BLOCK_SIZE);
+
+                ret = aes_start_crypt(eng, (u32)eng->dma_buf_in,
+                        (u32)eng->dma_buf_out, 1, FLAGS_CBC, false);
+                if (ret < 0) {
+                        dev_err(dd->dev, "aes_start_crypt fail(%d)\n", ret);
+                        goto out;
+                }
+        }
+
+        while (total) {
+                dev_dbg(dd->dev, "remain: %d\n", total);
+                ret = dma_map_sg(dd->dev, in_sg, 1, DMA_TO_DEVICE);
+                if (!ret) {
+                        dev_err(dd->dev, "dma_map_sg() error\n");
+                        goto out;
+                }
+
+                ret = dma_map_sg(dd->dev, out_sg, 1, DMA_FROM_DEVICE);
+                if (!ret) {
+                        dev_err(dd->dev, "dma_map_sg() error\n");
+                        dma_unmap_sg(dd->dev, eng->in_sg,
+                                1, DMA_TO_DEVICE);
+                        goto out;
+                }
+
+                addr_in = sg_dma_address(in_sg);
+                addr_out = sg_dma_address(out_sg);
+                count = min((int)sg_dma_len(in_sg), (int)dma_max);
+                WARN_ON(sg_dma_len(in_sg) != sg_dma_len(out_sg));
+                nblocks = DIV_ROUND_UP(count, AES_BLOCK_SIZE);
+
+                ret = aes_start_crypt(eng, addr_in, addr_out, nblocks,
+                        dd->flags, true);
+
+                dma_unmap_sg(dd->dev, out_sg, 1, DMA_FROM_DEVICE);
+                dma_unmap_sg(dd->dev, in_sg, 1, DMA_TO_DEVICE);
+                if (ret < 0) {
+                        dev_err(dd->dev, "aes_start_crypt fail(%d)\n", ret);
+                        goto out;
+                }
+
+                dev_dbg(dd->dev, "out: copied %d\n", count);
+                total -= count;
+                in_sg = sg_next(in_sg);
+                out_sg = sg_next(out_sg);
+                WARN_ON(((total != 0) && (!in_sg || !out_sg)));
+        }
+
+out:
+        /* release the hardware semaphore */
+        tegra_arb_mutex_unlock(eng->res_id);
+        eng->total = total;
+
+        if (eng->req->base.complete)
+                eng->req->base.complete(&eng->req->base, ret);
+
+        dev_dbg(dd->dev, "%s: exit\n", __func__);
+        return ret;
+}
+
+static int tegra_aes_key_save(struct tegra_aes_ctx *ctx)
+{
+        struct tegra_aes_dev *dd = aes_dev;
+        int retry_count, eng_busy, ret, eng_no;
+        struct tegra_aes_engine *eng[2] = {&dd->bsev, &dd->bsea};
+        unsigned long flags;
+
+        /* check for engine free state */
+        for (eng_no = 0; eng_no < ARRAY_SIZE(eng); eng_no++) {
+                for (retry_count = 0; retry_count <= 10; retry_count++) {
+                        spin_lock_irqsave(&dd->lock, flags);
+                        eng_busy = test_and_set_bit(FLAGS_BUSY,
+                                                        &eng[eng_no]->busy);
+                        spin_unlock_irqrestore(&dd->lock, flags);
+
+                        if (!eng_busy)
+                                break;
+
+                        if (retry_count == 10) {
+                                dev_err(dd->dev,
+                                        "%s: eng=%d busy, wait timeout\n",
+                                        __func__, eng[eng_no]->res_id);
+                                ret = -EBUSY;
+                                goto out;
+                        }
+                        mdelay(5);
+                }
+        }
+
+        /* save key in the engine */
+        for (eng_no = 0;  eng_no < ARRAY_SIZE(eng); eng_no++) {
+                ret = aes_hw_init(eng[eng_no]);
+                if (ret < 0) {
+                        dev_err(dd->dev, "%s: eng=%d hw init fail(%d)\n",
+                        __func__, eng[eng_no]->res_id, ret);
+                        goto out;
+                }
+                eng[eng_no]->ctx = ctx;
+                if (ctx->use_ssk)
+                        aes_set_key(eng[eng_no], SSK_SLOT_NUM);
+                else
+                        aes_set_key(eng[eng_no], ctx->slot->slot_num);
+
+                aes_hw_deinit(eng[eng_no]);
+        }
+out:
+        spin_lock_irqsave(&dd->lock, flags);
+        while (--eng_no >= 0)
+                clear_bit(FLAGS_BUSY, &eng[eng_no]->busy);
+        spin_unlock_irqrestore(&dd->lock, flags);
+
+        return ret;
+}
+
+static int tegra_aes_setkey(struct crypto_ablkcipher *tfm, const u8 *key,
+        unsigned int keylen)
+{
+        struct tegra_aes_ctx *ctx = crypto_ablkcipher_ctx(tfm);
+        struct tegra_aes_dev *dd = aes_dev;
+        struct tegra_aes_slot *key_slot;
+        int ret = 0;
+
+        if (!ctx || !dd) {
+                pr_err("ctx=0x%x, dd=0x%x\n",
+                        (unsigned int)ctx, (unsigned int)dd);
+                return -EINVAL;
+        }
+
+        if ((keylen != AES_KEYSIZE_128) && (keylen != AES_KEYSIZE_192) &&
+                (keylen != AES_KEYSIZE_256)) {
+                dev_err(dd->dev, "unsupported key size\n");
+                return -EINVAL;
+        }
+
+        /* take the hardware semaphore */
+        if (tegra_arb_mutex_lock_timeout(dd->bsev.res_id, ARB_SEMA_TIMEOUT) < 0) {
+                dev_err(dd->dev, "aes hardware (%d) not available\n", dd->bsev.res_id);
+                return -EBUSY;
+        }
+
+        if (tegra_arb_mutex_lock_timeout(dd->bsea.res_id, ARB_SEMA_TIMEOUT) < 0) {
+                dev_err(dd->dev, "aes hardware (%d) not available\n", dd->bsea.res_id);
+                tegra_arb_mutex_unlock(dd->bsev.res_id);
+                return -EBUSY;
+        }
+
+        dev_dbg(dd->dev, "keylen: %d\n", keylen);
+        ctx->dd = dd;
+
+        if (key) {
+                if (!ctx->slot) {
+                        key_slot = aes_find_key_slot(dd);
+                        if (!key_slot) {
+                                dev_err(dd->dev, "no empty slot\n");
+                                ret = -EBUSY;
+                                goto out;
+                        }
+                        ctx->slot = key_slot;
+                }
+
+                /* copy the key to the proper slot */
+                memset(ctx->key, 0, AES_MAX_KEY_SIZE);
+                memcpy(ctx->key, key, keylen);
+                ctx->keylen = keylen;
+                ctx->use_ssk = false;
+        } else {
+                ctx->use_ssk = true;
+                ctx->keylen = AES_KEYSIZE_128;
+        }
+
+        ret = tegra_aes_key_save(ctx);
+        if (ret != 0)
+                dev_err(dd->dev, "%s failed\n", __func__);
+out:
+        tegra_arb_mutex_unlock(dd->bsev.res_id);
+        tegra_arb_mutex_unlock(dd->bsea.res_id);
+        dev_dbg(dd->dev, "done\n");
+        return ret;
+}
+
+static void bsev_workqueue_handler(struct work_struct *work)
+{
+        struct tegra_aes_dev *dd = aes_dev;
+        struct tegra_aes_engine *engine = &dd->bsev;
+        int ret;
+
+        aes_hw_init(engine);
+
+        /* empty the crypto queue and then return */
+        do {
+                ret = tegra_aes_handle_req(engine);
+        } while (!ret);
+
+        aes_hw_deinit(engine);
+}
+
+static void bsea_workqueue_handler(struct work_struct *work)
+{
+        struct tegra_aes_dev *dd = aes_dev;
+        struct tegra_aes_engine *engine = &dd->bsea;
+        int ret;
+
+        aes_hw_init(engine);
+
+        /* empty the crypto queue and then return */
+        do {
+                ret = tegra_aes_handle_req(engine);
+        } while (!ret);
+
+        aes_hw_deinit(engine);
+}
+
+#define INT_ERROR_MASK  0xFFF000
+static irqreturn_t aes_bsev_irq(int irq, void *dev_id)
+{
+        struct tegra_aes_dev *dd = (struct tegra_aes_dev *)dev_id;
+        u32 value = aes_readl(&dd->bsev, INTR_STATUS);
+
+        dev_dbg(dd->dev, "bsev irq_stat: 0x%x", value);
+        dd->bsev.status = 0;
+        if (value & INT_ERROR_MASK) {
+                aes_writel(&dd->bsev, INT_ERROR_MASK, INTR_STATUS);
+                dd->bsev.status = value & INT_ERROR_MASK;
+        }
+
+        value = aes_readl(&dd->bsev, INTR_STATUS);
+        if (!(value & ENGINE_BUSY_FIELD))
+                complete(&dd->bsev.op_complete);
+
+        return IRQ_HANDLED;
+}
+
+static irqreturn_t aes_bsea_irq(int irq, void *dev_id)
+{
+        struct tegra_aes_dev *dd = (struct tegra_aes_dev *)dev_id;
+        u32 value = aes_readl(&dd->bsea, INTR_STATUS);
+
+        dev_dbg(dd->dev, "bsea irq_stat: 0x%x", value);
+        dd->bsea.status = 0;
+        if (value & INT_ERROR_MASK) {
+                aes_writel(&dd->bsea, INT_ERROR_MASK, INTR_STATUS);
+                dd->bsea.status = value & INT_ERROR_MASK;
+        }
+
+        value = aes_readl(&dd->bsea, INTR_STATUS);
+        if (!(value & ENGINE_BUSY_FIELD))
+                complete(&dd->bsea.op_complete);
+
+        return IRQ_HANDLED;
+}
+
+static int tegra_aes_crypt(struct ablkcipher_request *req, unsigned long mode)
+{
+        struct tegra_aes_reqctx *rctx = ablkcipher_request_ctx(req);
+        struct tegra_aes_dev *dd = aes_dev;
+        unsigned long flags;
+        int err = 0;
+        int bsev_busy;
+        int bsea_busy;
+
+        dev_dbg(dd->dev, "nbytes: %d, enc: %d, cbc: %d, ofb: %d\n", req->nbytes,
+                !!(mode & FLAGS_ENCRYPT),
+                !!(mode & FLAGS_CBC),
+                !!(mode & FLAGS_OFB));
+
+        rctx->mode = mode;
+
+        spin_lock_irqsave(&dd->lock, flags);
+        err = ablkcipher_enqueue_request(&dd->queue, req);
+        bsev_busy = test_and_set_bit(FLAGS_BUSY, &dd->bsev.busy);
+        bsea_busy = test_and_set_bit(FLAGS_BUSY, &dd->bsea.busy);
+        spin_unlock_irqrestore(&dd->lock, flags);
+
+        if (!bsev_busy)
+                queue_work(bsev_wq, &bsev_work);
+        if (!bsea_busy)
+                queue_work(bsea_wq, &bsea_work);
+
+        return err;
+}
+
+static int tegra_aes_ecb_encrypt(struct ablkcipher_request *req)
+{
+        return tegra_aes_crypt(req, FLAGS_ENCRYPT);
+}
+
+static int tegra_aes_ecb_decrypt(struct ablkcipher_request *req)
+{
+        return tegra_aes_crypt(req, 0);
+}
+
+static int tegra_aes_cbc_encrypt(struct ablkcipher_request *req)
+{
+        return tegra_aes_crypt(req, FLAGS_ENCRYPT | FLAGS_CBC);
+}
+
+static int tegra_aes_cbc_decrypt(struct ablkcipher_request *req)
+{
+        return tegra_aes_crypt(req, FLAGS_CBC);
+}
+static int tegra_aes_ofb_encrypt(struct ablkcipher_request *req)
+{
+        return tegra_aes_crypt(req, FLAGS_ENCRYPT | FLAGS_OFB);
+}
+
+static int tegra_aes_ofb_decrypt(struct ablkcipher_request *req)
+{
+        return tegra_aes_crypt(req, FLAGS_OFB);
+}
+
+static int tegra_aes_get_random(struct crypto_rng *tfm, u8 *rdata,
+        unsigned int dlen)
+{
+        struct tegra_aes_dev *dd = aes_dev;
+        struct tegra_aes_engine *eng = rng_ctx.eng;
+        unsigned long flags;
+        int ret, i;
+        u8 *dest = rdata, *dt = rng_ctx.dt;
+
+        /* take the hardware semaphore */
+        if (tegra_arb_mutex_lock_timeout(eng->res_id, ARB_SEMA_TIMEOUT) < 0) {
+                dev_err(dd->dev, "aes hardware (%d) not available\n",
+                eng->res_id);
+                return -EBUSY;
+        }
+
+        ret = aes_hw_init(eng);
+        if (ret < 0) {
+                dev_err(dd->dev, "%s: hw init fail(%d)\n", __func__, ret);
+                dlen = ret;
+                goto fail;
+        }
+
+        memset(eng->buf_in, 0, AES_BLOCK_SIZE);
+        memcpy(eng->buf_in, dt, DEFAULT_RNG_BLK_SZ);
+
+        ret = aes_start_crypt(eng, (u32)eng->dma_buf_in, (u32)eng->dma_buf_out,
+                1, FLAGS_ENCRYPT | FLAGS_RNG, true);
+        if (ret < 0) {
+                dev_err(dd->dev, "aes_start_crypt fail(%d)\n", ret);
+                dlen = ret;
+                goto out;
+        }
+        memcpy(dest, eng->buf_out, dlen);
+
+        /* update the DT */
+        for (i = DEFAULT_RNG_BLK_SZ - 1; i >= 0; i--) {
+                dt[i] += 1;
+                if (dt[i] != 0)
+                        break;
+        }
+
+out:
+        aes_hw_deinit(eng);
+
+        spin_lock_irqsave(&dd->lock, flags);
+        clear_bit(FLAGS_BUSY, &eng->busy);
+        spin_unlock_irqrestore(&dd->lock, flags);
+
+fail:
+        /* release the hardware semaphore */
+        tegra_arb_mutex_unlock(eng->res_id);
+        dev_dbg(dd->dev, "%s: done\n", __func__);
+        return dlen;
+}
+
+static int tegra_aes_rng_reset(struct crypto_rng *tfm, u8 *seed,
+        unsigned int slen)
+{
+        struct tegra_aes_dev *dd = aes_dev;
+        struct tegra_aes_ctx *ctx = &rng_ctx;
+        struct tegra_aes_engine *eng = NULL;
+        struct tegra_aes_slot *key_slot;
+        int bsea_busy = false;
+        unsigned long flags;
+        struct timespec ts;
+        u64 nsec, tmp[2];
+        int ret = 0;
+        u8 *dt;
+
+        if (!dd)
+                return -EINVAL;
+
+        if (slen < (DEFAULT_RNG_BLK_SZ + AES_KEYSIZE_128)) {
+                return -ENOMEM;
+        }
+
+        spin_lock_irqsave(&dd->lock, flags);
+        bsea_busy = test_and_set_bit(FLAGS_BUSY, &dd->bsea.busy);
+        spin_unlock_irqrestore(&dd->lock, flags);
+
+        if (!bsea_busy)
+                eng = &dd->bsea;
+        else
+                return -EBUSY;
+
+        ctx->eng = eng;
+        dd->flags = FLAGS_ENCRYPT | FLAGS_RNG;
+
+        if (!ctx->slot) {
+                key_slot = aes_find_key_slot(dd);
+                if (!key_slot) {
+                        dev_err(dd->dev, "no empty slot\n");
+                        return -ENOMEM;
+                }
+                ctx->slot = key_slot;
+        }
+
+        /* take the hardware semaphore */
+        if (tegra_arb_mutex_lock_timeout(eng->res_id, ARB_SEMA_TIMEOUT) < 0) {
+                dev_err(dd->dev, "aes hardware (%d) not available\n",
+                eng->res_id);
+                return -EBUSY;
+        }
+
+        ret = aes_hw_init(eng);
+        if (ret < 0) {
+                dev_err(dd->dev, "%s: hw init fail(%d)\n", __func__, ret);
+                goto fail;
+        }
+
+        memcpy(ctx->key, seed + DEFAULT_RNG_BLK_SZ, AES_KEYSIZE_128);
+
+        eng->ctx = ctx;
+        eng->ctx->keylen = AES_KEYSIZE_128;
+        aes_set_key(eng, ctx->slot->slot_num);
+
+        /* set seed to the aes hw slot */
+        memset(eng->buf_in, 0, AES_BLOCK_SIZE);
+        memcpy(eng->buf_in, seed, DEFAULT_RNG_BLK_SZ);
+        ret = aes_start_crypt(eng, (u32)eng->dma_buf_in,
+          (u32)eng->dma_buf_out, 1, FLAGS_CBC, false);
+        if (ret < 0) {
+                dev_err(dd->dev, "aes_start_crypt fail(%d)\n", ret);
+                goto out;
+        }
+
+        if (slen >= (2 * DEFAULT_RNG_BLK_SZ + AES_KEYSIZE_128)) {
+                dt = seed + DEFAULT_RNG_BLK_SZ + AES_KEYSIZE_128;
+        } else {
+                getnstimeofday(&ts);
+                nsec = timespec_to_ns(&ts);
+                do_div(nsec, 1000);
+                nsec ^= dd->ctr << 56;
+                dd->ctr++;
+                tmp[0] = nsec;
+                tmp[1] = tegra_chip_uid();
+                dt = (u8 *)tmp;
+        }
+        memcpy(ctx->dt, dt, DEFAULT_RNG_BLK_SZ);
+
+out:
+        aes_hw_deinit(eng);
+
+fail:
+        /* release the hardware semaphore */
+        tegra_arb_mutex_unlock(eng->res_id);
+
+        dev_dbg(dd->dev, "%s: done\n", __func__);
+        return ret;
+}
+
+static int tegra_aes_cra_init(struct crypto_tfm *tfm)
+{
+        tfm->crt_ablkcipher.reqsize = sizeof(struct tegra_aes_reqctx);
+        return 0;
+}
+
+void tegra_aes_cra_exit(struct crypto_tfm *tfm)
+{
+        struct tegra_aes_ctx *ctx = crypto_ablkcipher_ctx((struct crypto_ablkcipher *)tfm);
+
+        if (ctx && ctx->slot)
+                aes_release_key_slot(ctx);
+}
+
+static struct crypto_alg algs[] = {
+        {
+                .cra_name = "disabled_ecb(aes)",
+                .cra_driver_name = "ecb-aes-tegra",
+                .cra_priority = 100,
+                .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
+                .cra_blocksize = AES_BLOCK_SIZE,
+                .cra_ctxsize = sizeof(struct tegra_aes_ctx),
+                .cra_alignmask = 3,
+                .cra_type = &crypto_ablkcipher_type,
+                .cra_module = THIS_MODULE,
+                .cra_init = tegra_aes_cra_init,
+                .cra_exit = tegra_aes_cra_exit,
+                .cra_u.ablkcipher = {
+                        .min_keysize = AES_MIN_KEY_SIZE,
+                        .max_keysize = AES_MAX_KEY_SIZE,
+                        .setkey = tegra_aes_setkey,
+                        .encrypt = tegra_aes_ecb_encrypt,
+                        .decrypt = tegra_aes_ecb_decrypt,
+                },
+        }, {
+                .cra_name = "disabled_cbc(aes)",
+                .cra_driver_name = "cbc-aes-tegra",
+                .cra_priority = 100,
+                .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
+                .cra_blocksize = AES_BLOCK_SIZE,
+                .cra_ctxsize  = sizeof(struct tegra_aes_ctx),
+                .cra_alignmask = 3,
+                .cra_type = &crypto_ablkcipher_type,
+                .cra_module = THIS_MODULE,
+                .cra_init = tegra_aes_cra_init,
+                .cra_exit = tegra_aes_cra_exit,
+                .cra_u.ablkcipher = {
+                        .min_keysize = AES_MIN_KEY_SIZE,
+                        .max_keysize = AES_MAX_KEY_SIZE,
+                        .ivsize = AES_MIN_KEY_SIZE,
+                        .setkey = tegra_aes_setkey,
+                        .encrypt = tegra_aes_cbc_encrypt,
+                        .decrypt = tegra_aes_cbc_decrypt,
+                }
+        }, {
+                .cra_name = "disabled_ofb(aes)",
+                .cra_driver_name = "ofb-aes-tegra",
+                .cra_priority = 100,
+                .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
+                .cra_blocksize = AES_BLOCK_SIZE,
+                .cra_ctxsize  = sizeof(struct tegra_aes_ctx),
+                .cra_alignmask = 3,
+                .cra_type = &crypto_ablkcipher_type,
+                .cra_module = THIS_MODULE,
+                .cra_init = tegra_aes_cra_init,
+                .cra_exit = tegra_aes_cra_exit,
+                .cra_u.ablkcipher = {
+                        .min_keysize = AES_MIN_KEY_SIZE,
+                        .max_keysize = AES_MAX_KEY_SIZE,
+                        .ivsize = AES_MIN_KEY_SIZE,
+                        .setkey = tegra_aes_setkey,
+                        .encrypt = tegra_aes_ofb_encrypt,
+                        .decrypt = tegra_aes_ofb_decrypt,
+                }
+        }, {
+                .cra_name = "disabled_ansi_cprng",
+                .cra_driver_name = "rng-aes-tegra",
+                .cra_priority = 100,
+                .cra_flags = CRYPTO_ALG_TYPE_RNG,
+                .cra_ctxsize = sizeof(struct tegra_aes_ctx),
+                .cra_type = &crypto_rng_type,
+                .cra_module = THIS_MODULE,
+                .cra_init = tegra_aes_cra_init,
+                .cra_exit = tegra_aes_cra_exit,
+                .cra_u.rng = {
+                        .rng_make_random = tegra_aes_get_random,
+                        .rng_reset = tegra_aes_rng_reset,
+                        .seedsize = AES_KEYSIZE_128 + (2 * DEFAULT_RNG_BLK_SZ),
+                }
+        }
+};
+
+static int tegra_aes_probe(struct platform_device *pdev)
+{
+        struct device *dev = &pdev->dev;
+        struct tegra_aes_dev *dd;
+        struct resource *res[2];
+        int err = -ENOMEM, i = 0, j;
+
+        if (aes_dev)
+                return -EEXIST;
+
+        dd = kzalloc(sizeof(struct tegra_aes_dev), GFP_KERNEL);
+        if (dd == NULL) {
+                dev_err(dev, "unable to alloc data struct.\n");
+                return -ENOMEM;;
+        }
+        dd->dev = dev;
+        platform_set_drvdata(pdev, dd);
+
+        dd->slots = kzalloc(sizeof(struct tegra_aes_slot) * AES_NR_KEYSLOTS,
+                GFP_KERNEL);
+        if (dd->slots == NULL) {
+                dev_err(dev, "unable to alloc slot struct.\n");
+                goto out;
+        }
+
+        spin_lock_init(&dd->lock);
+        crypto_init_queue(&dd->queue, TEGRA_AES_QUEUE_LENGTH);
+
+        /* Get the module base address */
+        res[0] = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+        res[1] = platform_get_resource(pdev, IORESOURCE_MEM, 1);
+        if (!res[0] || !res[1]) {
+                dev_err(dev, "invalid resource type: base\n");
+                err = -ENODEV;
+                goto out;
+        }
+        dd->bsev.phys_base = res[0]->start;
+        dd->bsev.io_base = ioremap(dd->bsev.phys_base, resource_size(res[0]));
+        dd->bsea.phys_base = res[1]->start;
+        dd->bsea.io_base = ioremap(dd->bsea.phys_base, resource_size(res[1]));
+
+        if (!dd->bsev.io_base || !dd->bsea.io_base) {
+                dev_err(dev, "can't ioremap phys_base\n");
+                err = -ENOMEM;
+                goto out;
+        }
+
+        err = alloc_iram(dd);
+        if (err < 0) {
+                dev_err(dev, "Failed to allocate IRAM for BSEA\n");
+                goto out;
+        }
+
+        dd->bsev.res_id = TEGRA_ARB_BSEV;
+        dd->bsea.res_id = TEGRA_ARB_BSEA;
+
+        dd->bsev.pclk = clk_get(dev, "bsev");
+        if (IS_ERR(dd->bsev.pclk)) {
+                dev_err(dev, "v: pclock intialization failed.\n");
+                err = -ENODEV;
+                goto out;
+        }
+
+        dd->bsev.iclk = clk_get(dev, "vde");
+        if (IS_ERR(dd->bsev.iclk)) {
+                dev_err(dev, "v: iclock intialization failed.\n");
+                err = -ENODEV;
+                goto out;
+        }
+
+        dd->bsea.pclk = clk_get(dev, "bsea");
+        if (IS_ERR(dd->bsea.pclk)) {
+                dev_err(dev, "a: pclock intialization failed.\n");
+                err = -ENODEV;
+                goto out;
+        }
+
+        dd->bsea.iclk = clk_get(dev, "sclk");
+        if (IS_ERR(dd->bsea.iclk)) {
+                dev_err(dev, "a: iclock intialization failed.\n");
+                err = -ENODEV;
+                goto out;
+        }
+
+        err = clk_set_rate(dd->bsev.iclk, ULONG_MAX);
+        if (err) {
+                dev_err(dd->dev, "bsev iclk set_rate fail(%d)\n", err);
+                goto out;
+        }
+
+        err = clk_set_rate(dd->bsea.iclk, ULONG_MAX);
+        if (err) {
+                dev_err(dd->dev, "bsea iclk set_rate fail(%d)\n", err);
+                goto out;
+        }
+
+        /*
+         * the foll contiguous memory is allocated as follows -
+         * - hardware key table
+         * - key schedule
+         */
+        dd->bsea.ivkey_base = NULL;
+        dd->bsev.ivkey_base = dma_alloc_coherent(dev, AES_MAX_KEY_SIZE,
+                &dd->bsev.ivkey_phys_base, GFP_KERNEL);
+        if (!dd->bsev.ivkey_base) {
+                dev_err(dev, "can not allocate iv/key buffer for BSEV\n");
+                err = -ENOMEM;
+                goto out;
+        }
+        memset(dd->bsev.ivkey_base, 0, AES_MAX_KEY_SIZE);
+
+        dd->bsev.buf_in = dma_alloc_coherent(dev, AES_HW_DMA_BUFFER_SIZE_BYTES,
+                &dd->bsev.dma_buf_in, GFP_KERNEL);
+        dd->bsea.buf_in = dma_alloc_coherent(dev, AES_HW_DMA_BUFFER_SIZE_BYTES,
+                &dd->bsea.dma_buf_in, GFP_KERNEL);
+        if (!dd->bsev.buf_in || !dd->bsea.buf_in) {
+                dev_err(dev, "can not allocate dma-in buffer\n");
+                err = -ENOMEM;
+                goto out;
+        }
+
+        dd->bsev.buf_out = dma_alloc_coherent(dev, AES_HW_DMA_BUFFER_SIZE_BYTES,
+                &dd->bsev.dma_buf_out, GFP_KERNEL);
+        dd->bsea.buf_out = dma_alloc_coherent(dev, AES_HW_DMA_BUFFER_SIZE_BYTES,
+                &dd->bsea.dma_buf_out, GFP_KERNEL);
+        if (!dd->bsev.buf_out || !dd->bsea.buf_out) {
+                dev_err(dev, "can not allocate dma-out buffer\n");
+                err = -ENOMEM;
+                goto out;
+        }
+
+        init_completion(&dd->bsev.op_complete);
+        init_completion(&dd->bsea.op_complete);
+
+        bsev_wq = alloc_workqueue("bsev_wq", WQ_HIGHPRI | WQ_UNBOUND, 1);
+        bsea_wq = alloc_workqueue("bsea_wq", WQ_HIGHPRI | WQ_UNBOUND, 1);
+        if (!bsev_wq || !bsea_wq) {
+                dev_err(dev, "alloc_workqueue failed\n");
+                goto out;
+        }
+
+        /* get the irq */
+        dd->bsev.irq = INT_VDE_BSE_V;
+        err = request_irq(dd->bsev.irq, aes_bsev_irq, IRQF_TRIGGER_HIGH,
+                "tegra-aes", dd);
+        if (err) {
+                dev_err(dev, "request_irq failed fir BSEV Engine\n");
+                goto out;
+        }
+        disable_irq(dd->bsev.irq);
+
+        dd->bsea.irq = INT_VDE_BSE_A;
+        err = request_irq(dd->bsea.irq, aes_bsea_irq, IRQF_TRIGGER_HIGH,
+                "tegra-aes", dd);
+        if (err) {
+                dev_err(dev, "request_irq failed for BSEA Engine\n");
+                goto out;
+        }
+        disable_irq(dd->bsea.irq);
+
+        spin_lock_init(&list_lock);
+        spin_lock(&list_lock);
+        for (i = 0; i < AES_NR_KEYSLOTS; i++) {
+                if (i == SSK_SLOT_NUM)
+                        continue;
+                dd->slots[i].available = true;
+                dd->slots[i].slot_num = i;
+                INIT_LIST_HEAD(&dd->slots[i].node);
+                list_add_tail(&dd->slots[i].node, &slot_list);
+        }
+        spin_unlock(&list_lock);
+
+        aes_dev = dd;
+
+        for (i = 0; i < ARRAY_SIZE(algs); i++) {
+                INIT_LIST_HEAD(&algs[i].cra_list);
+                err = crypto_register_alg(&algs[i]);
+                if (err)
+                        goto out;
+        }
+
+        dev_info(dev, "registered");
+        return 0;
+
+out:
+        for (j = 0; j < i; j++)
+                crypto_unregister_alg(&algs[j]);
+
+        free_iram(dd);
+
+        if (dd->bsev.ivkey_base) {
+                dma_free_coherent(dev, SZ_512, dd->bsev.ivkey_base,
+                        dd->bsev.ivkey_phys_base);
+        }
+
+        if (dd->bsev.buf_in && dd->bsea.buf_in) {
+                dma_free_coherent(dev, AES_HW_DMA_BUFFER_SIZE_BYTES,
+                        dd->bsev.buf_in, dd->bsev.dma_buf_in);
+                dma_free_coherent(dev, AES_HW_DMA_BUFFER_SIZE_BYTES,
+                        dd->bsea.buf_in, dd->bsea.dma_buf_in);
+        }
+
+        if (dd->bsev.buf_out && dd->bsea.buf_out) {
+                dma_free_coherent(dev, AES_HW_DMA_BUFFER_SIZE_BYTES,
+                        dd->bsev.buf_out, dd->bsev.dma_buf_out);
+                dma_free_coherent(dev, AES_HW_DMA_BUFFER_SIZE_BYTES,
+                        dd->bsea.buf_out, dd->bsea.dma_buf_out);
+        }
+
+        if (dd->bsev.io_base && dd->bsea.io_base) {
+                iounmap(dd->bsev.io_base);
+                iounmap(dd->bsea.io_base);
+        }
+
+        if (dd->bsev.pclk)
+                clk_put(dd->bsev.pclk);
+
+        if (dd->bsev.iclk)
+                clk_put(dd->bsev.iclk);
+
+        if (dd->bsea.pclk)
+                clk_put(dd->bsea.pclk);
+
+        if (bsev_wq)
+                destroy_workqueue(bsev_wq);
+
+        if (bsea_wq)
+                destroy_workqueue(bsea_wq);
+
+        if (dd->bsev.irq)
+                free_irq(dd->bsev.irq, dd);
+
+        if (dd->bsea.irq)
+                free_irq(dd->bsea.irq, dd);
+
+        spin_lock(&list_lock);
+        list_del(&slot_list);
+        spin_unlock(&list_lock);
+
+        kfree(dd->slots);
+        kfree(dd);
+        aes_dev = NULL;
+
+        dev_err(dev, "%s: initialization failed.\n", __func__);
+        return err;
+}
+
+static int __devexit tegra_aes_remove(struct platform_device *pdev)
+{
+        struct device *dev = &pdev->dev;
+        struct tegra_aes_dev *dd = platform_get_drvdata(pdev);
+        int i;
+
+        if (!dd)
+                return -ENODEV;
+
+        cancel_work_sync(&bsev_work);
+        cancel_work_sync(&bsea_work);
+        destroy_workqueue(bsev_wq);
+        destroy_workqueue(bsea_wq);
+        free_irq(dd->bsev.irq, dd);
+        free_irq(dd->bsea.irq, dd);
+        spin_lock(&list_lock);
+        list_del(&slot_list);
+        spin_unlock(&list_lock);
+
+        for (i = 0; i < ARRAY_SIZE(algs); i++)
+                crypto_unregister_alg(&algs[i]);
+
+        free_iram(dd);
+        dma_free_coherent(dev, SZ_512, dd->bsev.ivkey_base,
+                dd->bsev.ivkey_phys_base);
+        dma_free_coherent(dev, AES_HW_DMA_BUFFER_SIZE_BYTES, dd->bsev.buf_in,
+                dd->bsev.dma_buf_in);
+        dma_free_coherent(dev, AES_HW_DMA_BUFFER_SIZE_BYTES, dd->bsea.buf_in,
+                dd->bsea.dma_buf_in);
+        dma_free_coherent(dev, AES_HW_DMA_BUFFER_SIZE_BYTES, dd->bsev.buf_out,
+                dd->bsev.dma_buf_out);
+        dma_free_coherent(dev, AES_HW_DMA_BUFFER_SIZE_BYTES, dd->bsea.buf_out,
+                dd->bsea.dma_buf_out);
+
+        iounmap(dd->bsev.io_base);
+        iounmap(dd->bsea.io_base);
+        clk_put(dd->bsev.iclk);
+        clk_put(dd->bsev.pclk);
+        clk_put(dd->bsea.pclk);
+        kfree(dd->slots);
+        kfree(dd);
+        aes_dev = NULL;
+
+        return 0;
+}
+
+static struct platform_driver tegra_aes_driver = {
+        .probe  = tegra_aes_probe,
+        .remove = __devexit_p(tegra_aes_remove),
+        .driver = {
+                .name   = "tegra-aes",
+                .owner  = THIS_MODULE,
+        },
+};
+
+static int __init tegra_aes_mod_init(void)
+{
+        INIT_LIST_HEAD(&slot_list);
+        return  platform_driver_register(&tegra_aes_driver);
+}
+
+static void __exit tegra_aes_mod_exit(void)
+{
+        platform_driver_unregister(&tegra_aes_driver);
+}
+
+module_init(tegra_aes_mod_init);
+module_exit(tegra_aes_mod_exit);
+
+MODULE_DESCRIPTION("Tegra AES hw acceleration support.");
+MODULE_AUTHOR("NVIDIA Corporation");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/crypto/tegra-aes.h b/drivers/crypto/tegra-aes.h
new file mode 100644
index 00000000000..45696467cdf
--- /dev/null
+++ b/drivers/crypto/tegra-aes.h
@@ -0,0 +1,100 @@
+/*
+ * Copyright (c) 2010, NVIDIA Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+#ifndef __CRYPTODEV_TEGRA_AES_H
+#define __CRYPTODEV_TEGRA_AES_H
+
+#define ICMDQUE_WR              0x1000
+#define CMDQUE_CONTROL          0x1008
+#define INTR_STATUS             0x1018
+#define INT_ENB                 0x1040
+#define CONFIG                  0x1044
+#define IRAM_ACCESS_CFG         0x10A0
+#define SECURE_DEST_ADDR        0x1100
+#define SECURE_INPUT_SELECT     0x1104
+#define SECURE_CONFIG           0x1108
+#define SECURE_CONFIG_EXT       0x110C
+#define SECURE_SECURITY         0x1110
+#define SECURE_HASH_RESULT0     0x1120
+#define SECURE_HASH_RESULT1     0x1124
+#define SECURE_HASH_RESULT2     0x1128
+#define SECURE_HASH_RESULT3     0x112C
+#define SECURE_SEC_SEL0         0x1140
+#define SECURE_SEC_SEL1         0x1144
+#define SECURE_SEC_SEL2         0x1148
+#define SECURE_SEC_SEL3         0x114C
+#define SECURE_SEC_SEL4         0x1150
+#define SECURE_SEC_SEL5         0x1154
+#define SECURE_SEC_SEL6         0x1158
+#define SECURE_SEC_SEL7         0x115C
+
+/* interrupt status reg masks and shifts */
+#define DMA_BUSY_FIELD          BIT(9)
+#define ICQ_EMPTY_FIELD         BIT(3)
+#define ENGINE_BUSY_FIELD       BIT(0)
+
+/* secure select reg masks and shifts */
+#define SECURE_SEL0_KEYREAD_ENB0_FIELD  BIT(0)
+
+/* secure config ext masks and shifts */
+#define SECURE_KEY_SCH_DIS_FIELD        BIT(15)
+
+/* secure config masks and shifts */
+#define SECURE_KEY_INDEX_SHIFT          20
+#define SECURE_KEY_INDEX_FIELD          (0x1F << SECURE_KEY_INDEX_SHIFT)
+#define SECURE_BLOCK_CNT_FIELD          (0xFFFFF)
+
+/* stream interface select masks and shifts */
+#define CMDQ_CTRL_DST_STM_SEL_FIELD     BIT(5)
+#define CMDQ_CTRL_SRC_STM_SEL_FIELD     BIT(4)
+#define CMDQ_CTRL_ERROR_FLUSH_ENB       BIT(2)
+#define CMDQ_CTRL_ICMDQEN_FIELD         BIT(1)
+#define CMDQ_CTRL_UCMDQEN_FIELD         BIT(0)
+
+/* config regsiter masks and shifts */
+#define CONFIG_ENDIAN_ENB_FIELD         BIT(10)
+#define CONFIG_MODE_SEL_FIELD           BIT(0)
+
+/* extended config */
+#define SECURE_OFFSET_CNT_FIELD         (0xFF << 24)
+#define SECURE_KEYSCHED_GEN_FIELD       BIT(15)
+
+/* init vector select */
+#define SECURE_IV_SELECT_SHIFT          10
+#define SECURE_IV_SELECT_FIELD          BIT(10)
+
+/* secure engine input */
+#define SECURE_INPUT_ALG_SEL_SHIFT      28
+#define SECURE_INPUT_ALG_SEL_FIELD      (0xF << SECURE_INPUT_ALG_SEL_SHIFT)
+#define SECURE_INPUT_KEY_LEN_SHIFT      16
+#define SECURE_INPUT_KEY_LEN_FIELD      (0xFFF << SECURE_INPUT_KEY_LEN_SHIFT)
+#define SECURE_RNG_ENB_SHIFT            11
+#define SECURE_RNG_ENB_FIELD            BIT(11)
+#define SECURE_CORE_SEL_SHIFT           9
+#define SECURE_CORE_SEL_FIELD           BIT(9)
+#define SECURE_VCTRAM_SEL_SHIFT         7
+#define SECURE_VCTRAM_SEL_FIELD         (0x3 << SECURE_VCTRAM_SEL_SHIFT)
+#define SECURE_INPUT_SEL_SHIFT          5
+#define SECURE_INPUT_SEL_FIELD          (0x3 << SECURE_INPUT_SEL_SHIFT)
+#define SECURE_XOR_POS_SHIFT            3
+#define SECURE_XOR_POS_FIELD            (0x3 << SECURE_XOR_POS_SHIFT)
+#define SECURE_HASH_ENB_SHIFT           2
+#define SECURE_HASH_ENB_FIELD           BIT(2)
+#define SECURE_ON_THE_FLY_FIELD         BIT(0)
+
+#endif
diff --git a/drivers/crypto/tegra-se.c b/drivers/crypto/tegra-se.c
new file mode 100644
index 00000000000..3d2e9187b94
--- /dev/null
+++ b/drivers/crypto/tegra-se.c
@@ -0,0 +1,2455 @@
+/*
+ * Cryptographic API.
+ * drivers/crypto/tegra-se.c
+ *
+ * Support for Tegra Security Engine hardware crypto algorithms.
+ *
+ * Copyright (c) 2011, NVIDIA Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/errno.h>
+#include <linux/kernel.h>
+#include <linux/clk.h>
+#include <linux/platform_device.h>
+#include <linux/scatterlist.h>
+#include <linux/dma-mapping.h>
+#include <linux/io.h>
+#include <linux/mutex.h>
+#include <linux/interrupt.h>
+#include <linux/types.h>
+#include <linux/errno.h>
+#include <crypto/scatterwalk.h>
+#include <crypto/algapi.h>
+#include <crypto/aes.h>
+#include <crypto/internal/rng.h>
+#include <crypto/internal/hash.h>
+#include <crypto/sha.h>
+#include <linux/pm_runtime.h>
+
+#include "tegra-se.h"
+
+#define DRIVER_NAME     "tegra-se"
+
+/* Security Engine operation modes */
+enum tegra_se_aes_op_mode {
+        SE_AES_OP_MODE_CBC,     /* Cipher Block Chaining (CBC) mode */
+        SE_AES_OP_MODE_ECB,     /* Electronic Codebook (ECB) mode */
+        SE_AES_OP_MODE_CTR,     /* Counter (CTR) mode */
+        SE_AES_OP_MODE_OFB,     /* Output feedback (CFB) mode */
+        SE_AES_OP_MODE_RNG_X931,        /* Random number generator (RNG) mode */
+        SE_AES_OP_MODE_CMAC,    /* Cipher-based MAC (CMAC) mode */
+        SE_AES_OP_MODE_SHA1,    /* Secure Hash Algorithm-1 (SHA1) mode */
+        SE_AES_OP_MODE_SHA224,  /* Secure Hash Algorithm-224  (SHA224) mode */
+        SE_AES_OP_MODE_SHA256,  /* Secure Hash Algorithm-256  (SHA256) mode */
+        SE_AES_OP_MODE_SHA384,  /* Secure Hash Algorithm-384  (SHA384) mode */
+        SE_AES_OP_MODE_SHA512   /* Secure Hash Algorithm-512  (SHA512) mode */
+};
+
+/* Security Engine key table type */
+enum tegra_se_key_table_type {
+        SE_KEY_TABLE_TYPE_KEY,  /* Key */
+        SE_KEY_TABLE_TYPE_ORGIV,        /* Original IV */
+        SE_KEY_TABLE_TYPE_UPDTDIV       /* Updated IV */
+};
+
+/* Security Engine request context */
+struct tegra_se_req_context {
+        enum tegra_se_aes_op_mode op_mode; /* Security Engine operation mode */
+        bool encrypt;   /* Operation type */
+};
+
+struct tegra_se_dev {
+        struct device *dev;
+        void __iomem *io_reg;   /* se device memory/io */
+        void __iomem *pmc_io_reg;       /* pmc device memory/io */
+        int irq;        /* irq allocated */
+        spinlock_t lock;        /* spin lock */
+        struct clk *pclk;       /* Security Engine clock */
+        struct crypto_queue queue; /* Security Engine crypto queue */
+        struct tegra_se_slot *slot_list;        /* pointer to key slots */
+        u64 ctr;
+        u32 *src_ll_buf;        /* pointer to source linked list buffer */
+        dma_addr_t src_ll_buf_adr; /* Source linked list buffer dma address */
+        u32 src_ll_size;        /* Size of source linked list buffer */
+        u32 *dst_ll_buf;        /* pointer to destination linked list buffer */
+        dma_addr_t dst_ll_buf_adr; /* Destination linked list dma address */
+        u32 dst_ll_size;        /* Size of destination linked list buffer */
+        u32 *ctx_save_buf;      /* LP context buffer pointer*/
+        dma_addr_t ctx_save_buf_adr;    /* LP context buffer dma address*/
+        struct completion complete;     /* Tells the task completion */
+        bool work_q_busy;       /* Work queue busy status */
+};
+
+static struct tegra_se_dev *sg_tegra_se_dev;
+
+/* Security Engine AES context */
+struct tegra_se_aes_context {
+        struct tegra_se_dev *se_dev;    /* Security Engine device */
+        struct tegra_se_slot *slot;     /* Security Engine key slot */
+        u32 keylen;     /* key length in bits */
+        u32 op_mode;    /* AES operation mode */
+};
+
+/* Security Engine random number generator context */
+struct tegra_se_rng_context {
+        struct tegra_se_dev *se_dev;    /* Security Engine device */
+        struct tegra_se_slot *slot;     /* Security Engine key slot */
+        u32 *dt_buf;    /* Destination buffer pointer */
+        dma_addr_t dt_buf_adr;  /* Destination buffer dma address */
+        u32 *rng_buf;   /* RNG buffer pointer */
+        dma_addr_t rng_buf_adr; /* RNG buffer dma address */
+        bool use_org_iv;        /* Tells whether original IV is be used
+                                or not. If it is false updated IV is used*/
+};
+
+/* Security Engine SHA context */
+struct tegra_se_sha_context {
+        struct tegra_se_dev     *se_dev;        /* Security Engine device */
+        u32 op_mode;    /* SHA operation mode */
+};
+
+/* Security Engine AES CMAC context */
+struct tegra_se_aes_cmac_context {
+        struct tegra_se_dev *se_dev;    /* Security Engine device */
+        struct tegra_se_slot *slot;     /* Security Engine key slot */
+        u32 keylen;     /* key length in bits */
+        u8 K1[TEGRA_SE_KEY_128_SIZE];   /* Key1 */
+        u8 K2[TEGRA_SE_KEY_128_SIZE];   /* Key2 */
+        dma_addr_t dma_addr;    /* DMA address of local buffer */
+        u32 buflen;     /* local buffer length */
+        u8      *buffer;        /* local buffer pointer */
+};
+
+/* Security Engine key slot */
+struct tegra_se_slot {
+        struct list_head node;
+        u8 slot_num;    /* Key slot number */
+        bool available; /* Tells whether key slot is free to use */
+};
+
+static struct tegra_se_slot ssk_slot = {
+        .slot_num = 15,
+        .available = false,
+};
+
+static struct tegra_se_slot srk_slot = {
+        .slot_num = 0,
+        .available = false,
+};
+
+/* Security Engine Linked List */
+struct tegra_se_ll {
+        dma_addr_t addr; /* DMA buffer address */
+        u32 data_len; /* Data length in DMA buffer */
+};
+
+static LIST_HEAD(key_slot);
+static DEFINE_SPINLOCK(key_slot_lock);
+static DEFINE_MUTEX(se_hw_lock);
+
+/* create a work for handling the async transfers */
+static void tegra_se_work_handler(struct work_struct *work);
+static DECLARE_WORK(se_work, tegra_se_work_handler);
+static struct workqueue_struct *se_work_q;
+
+#define PMC_SCRATCH43_REG_OFFSET 0x22c
+#define GET_MSB(x)  ((x) >> (8*sizeof(x)-1))
+static void tegra_se_leftshift_onebit(u8 *in_buf, u32 size, u8 *org_msb)
+{
+        u8 carry;
+        u32 i;
+
+        *org_msb = GET_MSB(in_buf[0]);
+
+        /* left shift one bit */
+        in_buf[0] <<= 1;
+        for (carry = 0, i = 1; i < size; i++) {
+                carry = GET_MSB(in_buf[i]);
+                in_buf[i-1] |= carry;
+                in_buf[i] <<= 1;
+        }
+}
+
+extern unsigned long long tegra_chip_uid(void);
+
+static inline void se_writel(struct tegra_se_dev *se_dev,
+        unsigned int val, unsigned int reg_offset)
+{
+        writel(val, se_dev->io_reg + reg_offset);
+}
+
+static inline unsigned int se_readl(struct tegra_se_dev *se_dev,
+        unsigned int reg_offset)
+{
+        unsigned int val;
+
+        val = readl(se_dev->io_reg + reg_offset);
+
+        return val;
+}
+
+static void tegra_se_free_key_slot(struct tegra_se_slot *slot)
+{
+        if (slot) {
+                spin_lock(&key_slot_lock);
+                slot->available = true;
+                spin_unlock(&key_slot_lock);
+        }
+}
+
+static struct tegra_se_slot *tegra_se_alloc_key_slot(void)
+{
+        struct tegra_se_slot *slot = NULL;
+        bool found = false;
+
+        spin_lock(&key_slot_lock);
+        list_for_each_entry(slot, &key_slot, node) {
+                if (slot->available) {
+                        slot->available = false;
+                        found = true;
+                        break;
+                }
+        }
+        spin_unlock(&key_slot_lock);
+        return found ? slot : NULL;
+}
+
+static int tegra_init_key_slot(struct tegra_se_dev *se_dev)
+{
+        int i;
+
+        se_dev->slot_list = kzalloc(sizeof(struct tegra_se_slot) *
+                                        TEGRA_SE_KEYSLOT_COUNT, GFP_KERNEL);
+        if (se_dev->slot_list == NULL) {
+                dev_err(se_dev->dev, "slot list memory allocation failed\n");
+                return -ENOMEM;
+        }
+        spin_lock_init(&key_slot_lock);
+        spin_lock(&key_slot_lock);
+        for (i = 0; i < TEGRA_SE_KEYSLOT_COUNT; i++) {
+                /*
+                 * Slot 0 and 15 are reserved and will not be added to the
+                 * free slots pool. Slot 0 is used for SRK generation and
+                 * Slot 15 is used for SSK operation
+                 */
+                if ((i == srk_slot.slot_num) || (i == ssk_slot.slot_num))
+                        continue;
+                se_dev->slot_list[i].available = true;
+                se_dev->slot_list[i].slot_num = i;
+                INIT_LIST_HEAD(&se_dev->slot_list[i].node);
+                list_add_tail(&se_dev->slot_list[i].node, &key_slot);
+        }
+        spin_unlock(&key_slot_lock);
+
+        return 0;
+}
+
+static void tegra_se_key_read_disable(u8 slot_num)
+{
+        struct tegra_se_dev *se_dev = sg_tegra_se_dev;
+        u32 val;
+
+        val = se_readl(se_dev,
+                        (SE_KEY_TABLE_ACCESS_REG_OFFSET + (slot_num * 4)));
+        val &= ~(1 << SE_KEY_READ_DISABLE_SHIFT);
+        se_writel(se_dev,
+                val, (SE_KEY_TABLE_ACCESS_REG_OFFSET + (slot_num * 4)));
+}
+
+static void tegra_se_key_read_disable_all(void)
+{
+        struct tegra_se_dev *se_dev = sg_tegra_se_dev;
+        u8 slot_num;
+
+        mutex_lock(&se_hw_lock);
+        pm_runtime_get_sync(se_dev->dev);
+
+        for (slot_num = 0; slot_num < TEGRA_SE_KEYSLOT_COUNT; slot_num++)
+                tegra_se_key_read_disable(slot_num);
+
+        pm_runtime_put(se_dev->dev);
+        mutex_unlock(&se_hw_lock);
+}
+
+static void tegra_se_config_algo(struct tegra_se_dev *se_dev,
+        enum tegra_se_aes_op_mode mode, bool encrypt, u32 key_len)
+{
+        u32 val = 0;
+
+        switch (mode) {
+        case SE_AES_OP_MODE_CBC:
+        case SE_AES_OP_MODE_CMAC:
+                if (encrypt) {
+                        val = SE_CONFIG_ENC_ALG(ALG_AES_ENC);
+                        if (key_len == TEGRA_SE_KEY_256_SIZE)
+                                val |= SE_CONFIG_ENC_MODE(MODE_KEY256);
+                        else if (key_len == TEGRA_SE_KEY_192_SIZE)
+                                val |= SE_CONFIG_ENC_MODE(MODE_KEY192);
+                        else
+                                val |= SE_CONFIG_ENC_MODE(MODE_KEY128);
+                        val |= SE_CONFIG_DEC_ALG(ALG_NOP);
+                } else {
+                        val = SE_CONFIG_DEC_ALG(ALG_AES_DEC);
+                        if (key_len == TEGRA_SE_KEY_256_SIZE)
+                                val |= SE_CONFIG_DEC_MODE(MODE_KEY256);
+                        else if (key_len == TEGRA_SE_KEY_192_SIZE)
+                                val |= SE_CONFIG_DEC_MODE(MODE_KEY192);
+                        else
+                                val |= SE_CONFIG_DEC_MODE(MODE_KEY128);
+                }
+                if (mode == SE_AES_OP_MODE_CMAC)
+                        val |= SE_CONFIG_DST(DST_HASHREG);
+                else
+                        val |= SE_CONFIG_DST(DST_MEMORY);
+                break;
+        case SE_AES_OP_MODE_RNG_X931:
+                val = SE_CONFIG_ENC_ALG(ALG_RNG) |
+                        SE_CONFIG_ENC_MODE(MODE_KEY128) |
+                                SE_CONFIG_DST(DST_MEMORY);
+                break;
+        case SE_AES_OP_MODE_ECB:
+                if (encrypt) {
+                        val = SE_CONFIG_ENC_ALG(ALG_AES_ENC);
+                        if (key_len == TEGRA_SE_KEY_256_SIZE)
+                                val |= SE_CONFIG_ENC_MODE(MODE_KEY256);
+                        else if (key_len == TEGRA_SE_KEY_192_SIZE)
+                                val |= SE_CONFIG_ENC_MODE(MODE_KEY192);
+                        else
+                                val |= SE_CONFIG_ENC_MODE(MODE_KEY128);
+                } else {
+                        val = SE_CONFIG_DEC_ALG(ALG_AES_DEC);
+                        if (key_len == TEGRA_SE_KEY_256_SIZE)
+                                val |= SE_CONFIG_DEC_MODE(MODE_KEY256);
+                        else if (key_len == TEGRA_SE_KEY_192_SIZE)
+                                val |= SE_CONFIG_DEC_MODE(MODE_KEY192);
+                        else
+                                val |= SE_CONFIG_DEC_MODE(MODE_KEY128);
+                }
+                val |= SE_CONFIG_DST(DST_MEMORY);
+                break;
+        case SE_AES_OP_MODE_CTR:
+                if (encrypt) {
+                        val = SE_CONFIG_ENC_ALG(ALG_AES_ENC);
+                        if (key_len == TEGRA_SE_KEY_256_SIZE)
+                                val |= SE_CONFIG_ENC_MODE(MODE_KEY256);
+                        else if (key_len == TEGRA_SE_KEY_192_SIZE)
+                                val |= SE_CONFIG_ENC_MODE(MODE_KEY192);
+                        else
+                                val |= SE_CONFIG_ENC_MODE(MODE_KEY128);
+                } else {
+                        val = SE_CONFIG_DEC_ALG(ALG_AES_DEC);
+                        if (key_len == TEGRA_SE_KEY_256_SIZE) {
+                                val |= SE_CONFIG_DEC_MODE(MODE_KEY256);
+                                val |= SE_CONFIG_ENC_MODE(MODE_KEY256);
+                        } else if (key_len == TEGRA_SE_KEY_192_SIZE) {
+                                val |= SE_CONFIG_DEC_MODE(MODE_KEY192);
+                                val |= SE_CONFIG_ENC_MODE(MODE_KEY192);
+                        } else {
+                                val |= SE_CONFIG_DEC_MODE(MODE_KEY128);
+                                val |= SE_CONFIG_ENC_MODE(MODE_KEY128);
+                        }
+                }
+                val |= SE_CONFIG_DST(DST_MEMORY);
+                break;
+        case SE_AES_OP_MODE_OFB:
+                if (encrypt) {
+                        val = SE_CONFIG_ENC_ALG(ALG_AES_ENC);
+                        if (key_len == TEGRA_SE_KEY_256_SIZE)
+                                val |= SE_CONFIG_ENC_MODE(MODE_KEY256);
+                        else if (key_len == TEGRA_SE_KEY_192_SIZE)
+                                val |= SE_CONFIG_ENC_MODE(MODE_KEY192);
+                        else
+                                val |= SE_CONFIG_ENC_MODE(MODE_KEY128);
+                } else {
+                        val = SE_CONFIG_DEC_ALG(ALG_AES_DEC);
+                        if (key_len == TEGRA_SE_KEY_256_SIZE) {
+                                val |= SE_CONFIG_DEC_MODE(MODE_KEY256);
+                                val |= SE_CONFIG_ENC_MODE(MODE_KEY256);
+                        } else if (key_len == TEGRA_SE_KEY_192_SIZE) {
+                                val |= SE_CONFIG_DEC_MODE(MODE_KEY192);
+                                val |= SE_CONFIG_ENC_MODE(MODE_KEY192);
+                        } else {
+                                val |= SE_CONFIG_DEC_MODE(MODE_KEY128);
+                                val |= SE_CONFIG_ENC_MODE(MODE_KEY128);
+                        }
+                }
+                val |= SE_CONFIG_DST(DST_MEMORY);
+                break;
+        case SE_AES_OP_MODE_SHA1:
+                val = SE_CONFIG_ENC_ALG(ALG_SHA) |
+                        SE_CONFIG_ENC_MODE(MODE_SHA1) |
+                                SE_CONFIG_DST(DST_HASHREG);
+                break;
+        case SE_AES_OP_MODE_SHA224:
+                val = SE_CONFIG_ENC_ALG(ALG_SHA) |
+                        SE_CONFIG_ENC_MODE(MODE_SHA224) |
+                                SE_CONFIG_DST(DST_HASHREG);
+                break;
+        case SE_AES_OP_MODE_SHA256:
+                val = SE_CONFIG_ENC_ALG(ALG_SHA) |
+                        SE_CONFIG_ENC_MODE(MODE_SHA256) |
+                                SE_CONFIG_DST(DST_HASHREG);
+                break;
+        case SE_AES_OP_MODE_SHA384:
+                val = SE_CONFIG_ENC_ALG(ALG_SHA) |
+                        SE_CONFIG_ENC_MODE(MODE_SHA384) |
+                                SE_CONFIG_DST(DST_HASHREG);
+                break;
+        case SE_AES_OP_MODE_SHA512:
+                val = SE_CONFIG_ENC_ALG(ALG_SHA) |
+                        SE_CONFIG_ENC_MODE(MODE_SHA512) |
+                                SE_CONFIG_DST(DST_HASHREG);
+                break;
+        default:
+                dev_warn(se_dev->dev, "Invalid operation mode\n");
+                break;
+        }
+
+        se_writel(se_dev, val, SE_CONFIG_REG_OFFSET);
+}
+
+static void tegra_se_write_seed(struct tegra_se_dev *se_dev, u32 *pdata)
+{
+        u32 i;
+
+        for (i = 0; i < SE_CRYPTO_CTR_REG_COUNT; i++)
+                se_writel(se_dev, pdata[i], SE_CRYPTO_CTR_REG_OFFSET + (i * 4));
+}
+
+static void tegra_se_write_key_table(u8 *pdata, u32 data_len,
+        u8 slot_num, enum tegra_se_key_table_type type)
+{
+        struct tegra_se_dev *se_dev = sg_tegra_se_dev;
+        u32 data_size = SE_KEYTABLE_REG_MAX_DATA;
+        u32 *pdata_buf = (u32 *)pdata;
+        u8 pkt = 0, quad = 0;
+        u32 val = 0, i;
+
+        if ((type == SE_KEY_TABLE_TYPE_KEY) && (slot_num == ssk_slot.slot_num))
+                return;
+
+        if (type == SE_KEY_TABLE_TYPE_ORGIV)
+                quad = QUAD_ORG_IV;
+        else if (type == SE_KEY_TABLE_TYPE_UPDTDIV)
+                quad = QUAD_UPDTD_IV;
+        else
+                quad = QUAD_KEYS_128;
+
+        /* write data to the key table */
+        do {
+                for (i = 0; i < data_size; i += 4, data_len -= 4)
+                        se_writel(se_dev, *pdata_buf++,
+                                SE_KEYTABLE_DATA0_REG_OFFSET + i);
+
+                pkt = SE_KEYTABLE_SLOT(slot_num) | SE_KEYTABLE_QUAD(quad);
+                val = SE_KEYTABLE_OP_TYPE(OP_WRITE) |
+                        SE_KEYTABLE_TABLE_SEL(TABLE_KEYIV) |
+                                SE_KEYTABLE_PKT(pkt);
+
+                se_writel(se_dev, val, SE_KEYTABLE_REG_OFFSET);
+
+                data_size = data_len;
+                quad = QUAD_KEYS_256;
+
+        } while (data_len);
+}
+
+static void tegra_se_config_crypto(struct tegra_se_dev *se_dev,
+        enum tegra_se_aes_op_mode mode, bool encrypt, u8 slot_num, bool org_iv)
+{
+        u32 val = 0;
+
+        switch (mode) {
+        case SE_AES_OP_MODE_CMAC:
+        case SE_AES_OP_MODE_CBC:
+                if (encrypt) {
+                        val = SE_CRYPTO_INPUT_SEL(INPUT_AHB) |
+                                SE_CRYPTO_VCTRAM_SEL(VCTRAM_AESOUT) |
+                                SE_CRYPTO_XOR_POS(XOR_TOP) |
+                                SE_CRYPTO_CORE_SEL(CORE_ENCRYPT);
+                } else {
+                        val = SE_CRYPTO_INPUT_SEL(INPUT_AHB) |
+                                SE_CRYPTO_VCTRAM_SEL(VCTRAM_PREVAHB) |
+                                SE_CRYPTO_XOR_POS(XOR_BOTTOM) |
+                                SE_CRYPTO_CORE_SEL(CORE_DECRYPT);
+                }
+                break;
+        case SE_AES_OP_MODE_RNG_X931:
+                val = SE_CRYPTO_INPUT_SEL(INPUT_AHB) |
+                        SE_CRYPTO_XOR_POS(XOR_BYPASS) |
+                        SE_CRYPTO_CORE_SEL(CORE_ENCRYPT);
+                break;
+        case SE_AES_OP_MODE_ECB:
+                if (encrypt) {
+                        val = SE_CRYPTO_INPUT_SEL(INPUT_AHB) |
+                                SE_CRYPTO_XOR_POS(XOR_BYPASS) |
+                                SE_CRYPTO_CORE_SEL(CORE_ENCRYPT);
+                } else {
+                        val = SE_CRYPTO_INPUT_SEL(INPUT_AHB) |
+                                SE_CRYPTO_XOR_POS(XOR_BYPASS) |
+                                SE_CRYPTO_CORE_SEL(CORE_DECRYPT);
+                }
+                break;
+        case SE_AES_OP_MODE_CTR:
+                val = SE_CRYPTO_INPUT_SEL(INPUT_LNR_CTR) |
+                        SE_CRYPTO_VCTRAM_SEL(VCTRAM_AHB) |
+                        SE_CRYPTO_XOR_POS(XOR_BOTTOM) |
+                        SE_CRYPTO_CORE_SEL(CORE_ENCRYPT);
+                break;
+        case SE_AES_OP_MODE_OFB:
+                val = SE_CRYPTO_INPUT_SEL(INPUT_AESOUT) |
+                        SE_CRYPTO_VCTRAM_SEL(VCTRAM_AHB) |
+                        SE_CRYPTO_XOR_POS(XOR_BOTTOM) |
+                        SE_CRYPTO_CORE_SEL(CORE_ENCRYPT);
+                break;
+        default:
+                dev_warn(se_dev->dev, "Invalid operation mode\n");
+                break;
+        }
+
+        if (mode == SE_AES_OP_MODE_CTR) {
+                val |= SE_CRYPTO_HASH(HASH_DISABLE) |
+                        SE_CRYPTO_KEY_INDEX(slot_num) |
+                        SE_CRYPTO_CTR_CNTN(1);
+        } else {
+                val |= SE_CRYPTO_HASH(HASH_DISABLE) |
+                        SE_CRYPTO_KEY_INDEX(slot_num) |
+                        (org_iv ? SE_CRYPTO_IV_SEL(IV_ORIGINAL) :
+                        SE_CRYPTO_IV_SEL(IV_UPDATED));
+        }
+
+        /* enable hash for CMAC */
+        if (mode == SE_AES_OP_MODE_CMAC)
+                val |= SE_CRYPTO_HASH(HASH_ENABLE);
+
+        se_writel(se_dev, val, SE_CRYPTO_REG_OFFSET);
+
+        if (mode == SE_AES_OP_MODE_CTR)
+                se_writel(se_dev, 1, SE_SPARE_0_REG_OFFSET);
+
+        if (mode == SE_AES_OP_MODE_OFB)
+                se_writel(se_dev, 1, SE_SPARE_0_REG_OFFSET);
+
+}
+
+static void tegra_se_config_sha(struct tegra_se_dev *se_dev, u32 count)
+{
+        int i;
+
+        se_writel(se_dev, (count * 8), SE_SHA_MSG_LENGTH_REG_OFFSET);
+        se_writel(se_dev, (count * 8), SE_SHA_MSG_LEFT_REG_OFFSET);
+        for (i = 1; i < 4; i++) {
+                se_writel(se_dev, 0, SE_SHA_MSG_LENGTH_REG_OFFSET + (4 * i));
+                se_writel(se_dev, 0, SE_SHA_MSG_LEFT_REG_OFFSET + (4 * i));
+        }
+        se_writel(se_dev, SHA_ENABLE, SE_SHA_CONFIG_REG_OFFSET);
+}
+
+static int tegra_se_start_operation(struct tegra_se_dev *se_dev, u32 nbytes,
+        bool context_save)
+{
+        u32 nblocks = nbytes / TEGRA_SE_AES_BLOCK_SIZE;
+        int ret = 0;
+        u32 val = 0;
+
+        /* clear any pending interrupts */
+        val = se_readl(se_dev, SE_INT_STATUS_REG_OFFSET);
+        se_writel(se_dev, val, SE_INT_STATUS_REG_OFFSET);
+        se_writel(se_dev, se_dev->src_ll_buf_adr, SE_IN_LL_ADDR_REG_OFFSET);
+        se_writel(se_dev, se_dev->dst_ll_buf_adr, SE_OUT_LL_ADDR_REG_OFFSET);
+
+        if (nblocks)
+                se_writel(se_dev, nblocks-1, SE_BLOCK_COUNT_REG_OFFSET);
+
+        /* enable interupts */
+        val = SE_INT_ERROR(INT_ENABLE) | SE_INT_OP_DONE(INT_ENABLE);
+        se_writel(se_dev, val, SE_INT_ENABLE_REG_OFFSET);
+
+        INIT_COMPLETION(se_dev->complete);
+
+        if (context_save)
+                se_writel(se_dev, SE_OPERATION(OP_CTX_SAVE),
+                        SE_OPERATION_REG_OFFSET);
+        else
+                se_writel(se_dev, SE_OPERATION(OP_SRART),
+                        SE_OPERATION_REG_OFFSET);
+
+        ret = wait_for_completion_timeout(&se_dev->complete,
+                        msecs_to_jiffies(1000));
+        if (ret == 0) {
+                dev_err(se_dev->dev, "operation timed out no interrupt\n");
+                return -ETIMEDOUT;
+        }
+
+        return 0;
+}
+
+static void tegra_se_read_hash_result(struct tegra_se_dev *se_dev,
+        u8 *pdata, u32 nbytes, bool swap32)
+{
+        u32 *result = (u32 *)pdata;
+        u32 i;
+
+        for (i = 0; i < nbytes/4; i++) {
+                result[i] = se_readl(se_dev, SE_HASH_RESULT_REG_OFFSET +
+                                (i * sizeof(u32)));
+                if (swap32)
+                        result[i] = be32_to_cpu(result[i]);
+        }
+}
+
+static int tegra_se_count_sgs(struct scatterlist *sl, u32 total_bytes)
+{
+        int i = 0;
+
+        if (!total_bytes)
+                return 0;
+
+        do {
+                total_bytes -= min(sl[i].length, total_bytes);
+                i++;
+        } while (total_bytes);
+
+        return i;
+}
+
+static int tegra_se_alloc_ll_buf(struct tegra_se_dev *se_dev,
+        u32 num_src_sgs, u32 num_dst_sgs)
+{
+        if (se_dev->src_ll_buf || se_dev->dst_ll_buf) {
+                dev_err(se_dev->dev, "trying to allocate memory to allocated memory\n");
+                return -EBUSY;
+        }
+
+        if (num_src_sgs) {
+                se_dev->src_ll_size =
+                        (sizeof(struct tegra_se_ll) * num_src_sgs) +
+                                sizeof(u32);
+                se_dev->src_ll_buf = dma_alloc_coherent(se_dev->dev,
+                                        se_dev->src_ll_size,
+                                        &se_dev->src_ll_buf_adr, GFP_KERNEL);
+                if (!se_dev->src_ll_buf) {
+                        dev_err(se_dev->dev, "can not allocate src lldma buffer\n");
+                        return -ENOMEM;
+                }
+        }
+        if (num_dst_sgs) {
+                se_dev->dst_ll_size =
+                                (sizeof(struct tegra_se_ll) * num_dst_sgs) +
+                                        sizeof(u32);
+                se_dev->dst_ll_buf = dma_alloc_coherent(se_dev->dev,
+                                        se_dev->dst_ll_size,
+                                        &se_dev->dst_ll_buf_adr, GFP_KERNEL);
+                if (!se_dev->dst_ll_buf) {
+                        dev_err(se_dev->dev, "can not allocate dst ll dma buffer\n");
+                        return -ENOMEM;
+                }
+        }
+
+        return 0;
+}
+
+static void tegra_se_free_ll_buf(struct tegra_se_dev *se_dev)
+{
+        if (se_dev->src_ll_buf) {
+                dma_free_coherent(se_dev->dev, se_dev->src_ll_size,
+                        se_dev->src_ll_buf, se_dev->src_ll_buf_adr);
+                se_dev->src_ll_buf = NULL;
+        }
+
+        if (se_dev->dst_ll_buf) {
+                dma_free_coherent(se_dev->dev, se_dev->dst_ll_size,
+                        se_dev->dst_ll_buf, se_dev->dst_ll_buf_adr);
+                se_dev->dst_ll_buf = NULL;
+        }
+}
+
+static int tegra_se_setup_ablk_req(struct tegra_se_dev *se_dev,
+        struct ablkcipher_request *req)
+{
+        struct scatterlist *src_sg, *dst_sg;
+        struct tegra_se_ll *src_ll, *dst_ll;
+        u32 total, num_src_sgs, num_dst_sgs;
+        int ret = 0;
+
+        num_src_sgs = tegra_se_count_sgs(req->src, req->nbytes);
+        num_dst_sgs = tegra_se_count_sgs(req->dst, req->nbytes);
+
+        if ((num_src_sgs > SE_MAX_SRC_SG_COUNT) ||
+                (num_dst_sgs > SE_MAX_DST_SG_COUNT)) {
+                        dev_err(se_dev->dev, "num of SG buffers are more\n");
+                        return -EINVAL;
+        }
+
+        *se_dev->src_ll_buf = num_src_sgs-1;
+        *se_dev->dst_ll_buf = num_dst_sgs-1;
+
+        src_ll = (struct tegra_se_ll *)(se_dev->src_ll_buf + 1);
+        dst_ll = (struct tegra_se_ll *)(se_dev->dst_ll_buf + 1);
+
+        src_sg = req->src;
+        dst_sg = req->dst;
+        total = req->nbytes;
+
+        while (total) {
+                ret = dma_map_sg(se_dev->dev, src_sg, 1, DMA_TO_DEVICE);
+                if (!ret) {
+                        dev_err(se_dev->dev, "dma_map_sg() error\n");
+                        return -EINVAL;
+                }
+
+                ret = dma_map_sg(se_dev->dev, dst_sg, 1, DMA_FROM_DEVICE);
+                if (!ret) {
+                        dev_err(se_dev->dev, "dma_map_sg() error\n");
+                        dma_unmap_sg(se_dev->dev, src_sg, 1, DMA_TO_DEVICE);
+                        return -EINVAL;
+                }
+
+                WARN_ON(src_sg->length != dst_sg->length);
+                src_ll->addr = sg_dma_address(src_sg);
+                src_ll->data_len = min(src_sg->length, total);
+                dst_ll->addr = sg_dma_address(dst_sg);
+                dst_ll->data_len = min(dst_sg->length, total);
+                total -= min(src_sg->length, total);
+
+                src_sg = sg_next(src_sg);
+                dst_sg = sg_next(dst_sg);
+                dst_ll++;
+                src_ll++;
+                WARN_ON(((total != 0) && (!src_sg || !dst_sg)));
+        }
+        return ret;
+}
+
+static void tegra_se_dequeue_complete_req(struct tegra_se_dev *se_dev,
+        struct ablkcipher_request *req)
+{
+        struct scatterlist *src_sg, *dst_sg;
+        u32 total;
+
+        if (req) {
+                src_sg = req->src;
+                dst_sg = req->dst;
+                total = req->nbytes;
+                while (total) {
+                        dma_unmap_sg(se_dev->dev, dst_sg, 1, DMA_FROM_DEVICE);
+                        dma_unmap_sg(se_dev->dev, src_sg, 1, DMA_TO_DEVICE);
+                        total -= min(src_sg->length, total);
+                        src_sg = sg_next(src_sg);
+                        dst_sg = sg_next(dst_sg);
+                }
+        }
+}
+
+static void tegra_se_process_new_req(struct crypto_async_request *async_req)
+{
+        struct tegra_se_dev *se_dev = sg_tegra_se_dev;
+        struct ablkcipher_request *req = ablkcipher_request_cast(async_req);
+        struct tegra_se_req_context *req_ctx = ablkcipher_request_ctx(req);
+        struct tegra_se_aes_context *aes_ctx =
+                        crypto_ablkcipher_ctx(crypto_ablkcipher_reqtfm(req));
+        int ret = 0;
+
+        /* take access to the hw */
+        mutex_lock(&se_hw_lock);
+
+        /* write IV */
+        if (req->info) {
+                if (req_ctx->op_mode == SE_AES_OP_MODE_CTR) {
+                        tegra_se_write_seed(se_dev, (u32 *)req->info);
+                } else {
+                        tegra_se_write_key_table(req->info,
+                                TEGRA_SE_AES_IV_SIZE,
+                                aes_ctx->slot->slot_num,
+                                SE_KEY_TABLE_TYPE_ORGIV);
+                }
+        }
+        tegra_se_setup_ablk_req(se_dev, req);
+        tegra_se_config_algo(se_dev, req_ctx->op_mode, req_ctx->encrypt,
+                aes_ctx->keylen);
+        tegra_se_config_crypto(se_dev, req_ctx->op_mode, req_ctx->encrypt,
+                        aes_ctx->slot->slot_num, req->info ? true : false);
+        ret = tegra_se_start_operation(se_dev, req->nbytes, false);
+        tegra_se_dequeue_complete_req(se_dev, req);
+
+        mutex_unlock(&se_hw_lock);
+        req->base.complete(&req->base, ret);
+}
+
+static irqreturn_t tegra_se_irq(int irq, void *dev)
+{
+        struct tegra_se_dev *se_dev = dev;
+        u32 val;
+
+        val = se_readl(se_dev, SE_INT_STATUS_REG_OFFSET);
+        se_writel(se_dev, val, SE_INT_STATUS_REG_OFFSET);
+
+        if (val & SE_INT_ERROR(INT_SET))
+                dev_err(se_dev->dev, "tegra_se_irq::error");
+
+        if (val & SE_INT_OP_DONE(INT_SET))
+                complete(&se_dev->complete);
+
+        return IRQ_HANDLED;
+}
+
+static void tegra_se_work_handler(struct work_struct *work)
+{
+        struct tegra_se_dev *se_dev = sg_tegra_se_dev;
+        struct crypto_async_request *async_req = NULL;
+        struct crypto_async_request *backlog = NULL;
+
+        pm_runtime_get_sync(se_dev->dev);
+
+        do {
+                spin_lock_irq(&se_dev->lock);
+                backlog = crypto_get_backlog(&se_dev->queue);
+                async_req = crypto_dequeue_request(&se_dev->queue);
+                if (!async_req)
+                        se_dev->work_q_busy = false;
+
+                spin_unlock_irq(&se_dev->lock);
+
+                if (backlog) {
+                        backlog->complete(backlog, -EINPROGRESS);
+                        backlog = NULL;
+                }
+
+                if (async_req) {
+                        tegra_se_process_new_req(async_req);
+                        async_req = NULL;
+                }
+        } while (se_dev->work_q_busy);
+        pm_runtime_put(se_dev->dev);
+}
+
+static int tegra_se_aes_queue_req(struct ablkcipher_request *req)
+{
+        struct tegra_se_dev *se_dev = sg_tegra_se_dev;
+        unsigned long flags;
+        bool idle = true;
+        int err = 0;
+
+        if (!req->nbytes)
+                return -EINVAL;
+
+        spin_lock_irqsave(&se_dev->lock, flags);
+        err = ablkcipher_enqueue_request(&se_dev->queue, req);
+        if (se_dev->work_q_busy)
+                idle = false;
+        spin_unlock_irqrestore(&se_dev->lock, flags);
+
+        if (idle) {
+                spin_lock_irq(&se_dev->lock);
+                se_dev->work_q_busy = true;
+                spin_unlock_irq(&se_dev->lock);
+                queue_work(se_work_q, &se_work);
+        }
+
+        return err;
+}
+
+static int tegra_se_aes_cbc_encrypt(struct ablkcipher_request *req)
+{
+        struct tegra_se_req_context *req_ctx = ablkcipher_request_ctx(req);
+
+        req_ctx->encrypt = true;
+        req_ctx->op_mode = SE_AES_OP_MODE_CBC;
+
+        return tegra_se_aes_queue_req(req);
+}
+
+static int tegra_se_aes_cbc_decrypt(struct ablkcipher_request *req)
+{
+        struct tegra_se_req_context *req_ctx = ablkcipher_request_ctx(req);
+
+        req_ctx->encrypt = false;
+        req_ctx->op_mode = SE_AES_OP_MODE_CBC;
+
+        return tegra_se_aes_queue_req(req);
+}
+
+static int tegra_se_aes_ecb_encrypt(struct ablkcipher_request *req)
+{
+        struct tegra_se_req_context *req_ctx = ablkcipher_request_ctx(req);
+
+        req_ctx->encrypt = true;
+        req_ctx->op_mode = SE_AES_OP_MODE_ECB;
+
+        return tegra_se_aes_queue_req(req);
+}
+
+static int tegra_se_aes_ecb_decrypt(struct ablkcipher_request *req)
+{
+        struct tegra_se_req_context *req_ctx = ablkcipher_request_ctx(req);
+
+        req_ctx->encrypt = false;
+        req_ctx->op_mode = SE_AES_OP_MODE_ECB;
+
+        return tegra_se_aes_queue_req(req);
+}
+
+static int tegra_se_aes_ctr_encrypt(struct ablkcipher_request *req)
+{
+        struct tegra_se_req_context *req_ctx = ablkcipher_request_ctx(req);
+
+        req_ctx->encrypt = true;
+        req_ctx->op_mode = SE_AES_OP_MODE_CTR;
+
+        return tegra_se_aes_queue_req(req);
+}
+
+static int tegra_se_aes_ctr_decrypt(struct ablkcipher_request *req)
+{
+        struct tegra_se_req_context *req_ctx = ablkcipher_request_ctx(req);
+
+        req_ctx->encrypt = false;
+        req_ctx->op_mode = SE_AES_OP_MODE_CTR;
+
+        return tegra_se_aes_queue_req(req);
+}
+
+static int tegra_se_aes_ofb_encrypt(struct ablkcipher_request *req)
+{
+        struct tegra_se_req_context *req_ctx = ablkcipher_request_ctx(req);
+
+        req_ctx->encrypt = true;
+        req_ctx->op_mode = SE_AES_OP_MODE_OFB;
+
+        return tegra_se_aes_queue_req(req);
+}
+
+static int tegra_se_aes_ofb_decrypt(struct ablkcipher_request *req)
+{
+        struct tegra_se_req_context *req_ctx = ablkcipher_request_ctx(req);
+
+        req_ctx->encrypt = false;
+        req_ctx->op_mode = SE_AES_OP_MODE_OFB;
+
+        return tegra_se_aes_queue_req(req);
+}
+
+static int tegra_se_aes_setkey(struct crypto_ablkcipher *tfm,
+        const u8 *key, u32 keylen)
+{
+        struct tegra_se_aes_context *ctx = crypto_ablkcipher_ctx(tfm);
+        struct tegra_se_dev *se_dev = ctx->se_dev;
+        struct tegra_se_slot *pslot;
+        u8 *pdata = (u8 *)key;
+
+        if (!ctx) {
+                dev_err(se_dev->dev, "invalid context");
+                return -EINVAL;
+        }
+
+        if ((keylen != TEGRA_SE_KEY_128_SIZE) &&
+                (keylen != TEGRA_SE_KEY_192_SIZE) &&
+                (keylen != TEGRA_SE_KEY_256_SIZE)) {
+                dev_err(se_dev->dev, "invalid key size");
+                return -EINVAL;
+        }
+
+        if (key) {
+                if (!ctx->slot || (ctx->slot &&
+                    ctx->slot->slot_num == ssk_slot.slot_num)) {
+                        pslot = tegra_se_alloc_key_slot();
+                        if (!pslot) {
+                                dev_err(se_dev->dev, "no free key slot\n");
+                                return -ENOMEM;
+                        }
+                        ctx->slot = pslot;
+                }
+                ctx->keylen = keylen;
+        } else {
+                tegra_se_free_key_slot(ctx->slot);
+                ctx->slot = &ssk_slot;
+                ctx->keylen = AES_KEYSIZE_128;
+        }
+
+        /* take access to the hw */
+        mutex_lock(&se_hw_lock);
+        pm_runtime_get_sync(se_dev->dev);
+
+        /* load the key */
+        tegra_se_write_key_table(pdata, keylen, ctx->slot->slot_num,
+                SE_KEY_TABLE_TYPE_KEY);
+
+        pm_runtime_put(se_dev->dev);
+        mutex_unlock(&se_hw_lock);
+
+        return 0;
+}
+
+static int tegra_se_aes_cra_init(struct crypto_tfm *tfm)
+{
+        struct tegra_se_aes_context *ctx = crypto_tfm_ctx(tfm);
+
+        ctx->se_dev = sg_tegra_se_dev;
+        tfm->crt_ablkcipher.reqsize = sizeof(struct tegra_se_req_context);
+
+        return 0;
+}
+
+static void tegra_se_aes_cra_exit(struct crypto_tfm *tfm)
+{
+        struct tegra_se_aes_context *ctx = crypto_tfm_ctx(tfm);
+
+        tegra_se_free_key_slot(ctx->slot);
+        ctx->slot = NULL;
+}
+
+static int tegra_se_rng_init(struct crypto_tfm *tfm)
+{
+        struct tegra_se_rng_context *rng_ctx = crypto_tfm_ctx(tfm);
+        struct tegra_se_dev *se_dev = sg_tegra_se_dev;
+
+        rng_ctx->se_dev = se_dev;
+        rng_ctx->dt_buf = dma_alloc_coherent(se_dev->dev, TEGRA_SE_RNG_DT_SIZE,
+                &rng_ctx->dt_buf_adr, GFP_KERNEL);
+        if (!rng_ctx->dt_buf) {
+                dev_err(se_dev->dev, "can not allocate rng dma buffer");
+                return -ENOMEM;
+        }
+
+        rng_ctx->rng_buf = dma_alloc_coherent(rng_ctx->se_dev->dev,
+                TEGRA_SE_RNG_DT_SIZE, &rng_ctx->rng_buf_adr, GFP_KERNEL);
+        if (!rng_ctx->rng_buf) {
+                dev_err(se_dev->dev, "can not allocate rng dma buffer");
+                dma_free_coherent(rng_ctx->se_dev->dev, TEGRA_SE_RNG_DT_SIZE,
+                                        rng_ctx->dt_buf, rng_ctx->dt_buf_adr);
+                return -ENOMEM;
+        }
+
+        rng_ctx->slot = tegra_se_alloc_key_slot();
+
+        if (!rng_ctx->slot) {
+                dev_err(rng_ctx->se_dev->dev, "no free slot\n");
+                dma_free_coherent(rng_ctx->se_dev->dev, TEGRA_SE_RNG_DT_SIZE,
+                                        rng_ctx->dt_buf, rng_ctx->dt_buf_adr);
+                dma_free_coherent(rng_ctx->se_dev->dev, TEGRA_SE_RNG_DT_SIZE,
+                                        rng_ctx->rng_buf, rng_ctx->rng_buf_adr);
+                return -ENOMEM;
+        }
+
+        return 0;
+}
+
+static void tegra_se_rng_exit(struct crypto_tfm *tfm)
+{
+        struct tegra_se_rng_context *rng_ctx = crypto_tfm_ctx(tfm);
+
+        if (rng_ctx->dt_buf) {
+                dma_free_coherent(rng_ctx->se_dev->dev, TEGRA_SE_RNG_DT_SIZE,
+                        rng_ctx->dt_buf, rng_ctx->dt_buf_adr);
+        }
+
+        if (rng_ctx->rng_buf) {
+                dma_free_coherent(rng_ctx->se_dev->dev, TEGRA_SE_RNG_DT_SIZE,
+                        rng_ctx->rng_buf, rng_ctx->rng_buf_adr);
+        }
+
+        tegra_se_free_key_slot(rng_ctx->slot);
+        rng_ctx->slot = NULL;
+        rng_ctx->se_dev = NULL;
+}
+
+static int tegra_se_rng_get_random(struct crypto_rng *tfm, u8 *rdata, u32 dlen)
+{
+        struct tegra_se_rng_context *rng_ctx = crypto_rng_ctx(tfm);
+        struct tegra_se_dev *se_dev = rng_ctx->se_dev;
+        struct tegra_se_ll *src_ll, *dst_ll;
+        unsigned char *dt_buf = (unsigned char *)rng_ctx->dt_buf;
+        u8 *rdata_addr;
+        int ret = 0, i, j, num_blocks, data_len = 0;
+
+        num_blocks = (dlen / TEGRA_SE_RNG_DT_SIZE);
+
+        data_len = (dlen % TEGRA_SE_RNG_DT_SIZE);
+        if (data_len == 0)
+                num_blocks = num_blocks - 1;
+
+        /* take access to the hw */
+        mutex_lock(&se_hw_lock);
+        pm_runtime_get_sync(se_dev->dev);
+
+        *se_dev->src_ll_buf = 0;
+        *se_dev->dst_ll_buf = 0;
+        src_ll = (struct tegra_se_ll *)(se_dev->src_ll_buf + 1);
+        dst_ll = (struct tegra_se_ll *)(se_dev->dst_ll_buf + 1);
+        src_ll->addr = rng_ctx->dt_buf_adr;
+        src_ll->data_len = TEGRA_SE_RNG_DT_SIZE;
+        dst_ll->addr = rng_ctx->rng_buf_adr;
+        dst_ll->data_len = TEGRA_SE_RNG_DT_SIZE;
+
+        tegra_se_config_algo(se_dev, SE_AES_OP_MODE_RNG_X931, true,
+                TEGRA_SE_KEY_128_SIZE);
+        tegra_se_config_crypto(se_dev, SE_AES_OP_MODE_RNG_X931, true,
+                                rng_ctx->slot->slot_num, rng_ctx->use_org_iv);
+        for (j = 0; j <= num_blocks; j++) {
+                ret = tegra_se_start_operation(se_dev,
+                                TEGRA_SE_RNG_DT_SIZE, false);
+
+                if (!ret) {
+                        rdata_addr = (rdata + (j * TEGRA_SE_RNG_DT_SIZE));
+
+                        if (data_len && num_blocks == j) {
+                                memcpy(rdata_addr, rng_ctx->rng_buf, data_len);
+                        } else {
+                                memcpy(rdata_addr,
+                                        rng_ctx->rng_buf, TEGRA_SE_RNG_DT_SIZE);
+                        }
+
+                        /* update DT vector */
+                        for (i = TEGRA_SE_RNG_DT_SIZE - 1; i >= 0; i--) {
+                                dt_buf[i] += 1;
+                                if (dt_buf[i] != 0)
+                                        break;
+                        }
+                } else {
+                        dlen = 0;
+                }
+                if (rng_ctx->use_org_iv) {
+                        rng_ctx->use_org_iv = false;
+                        tegra_se_config_crypto(se_dev,
+                                SE_AES_OP_MODE_RNG_X931, true,
+                                rng_ctx->slot->slot_num, rng_ctx->use_org_iv);
+                }
+        }
+
+        pm_runtime_put(se_dev->dev);
+        mutex_unlock(&se_hw_lock);
+
+        return dlen;
+}
+
+static int tegra_se_rng_reset(struct crypto_rng *tfm, u8 *seed, u32 slen)
+{
+        struct tegra_se_rng_context *rng_ctx = crypto_rng_ctx(tfm);
+        struct tegra_se_dev *se_dev = rng_ctx->se_dev;
+        u8 *iv = seed;
+        u8 *key = (u8 *)(seed + TEGRA_SE_RNG_IV_SIZE);
+        u8 *dt = key + TEGRA_SE_RNG_KEY_SIZE;
+        struct timespec ts;
+        u64 nsec, tmp[2];
+
+        BUG_ON(!seed);
+
+        /* take access to the hw */
+        mutex_lock(&se_hw_lock);
+        pm_runtime_get_sync(se_dev->dev);
+
+        tegra_se_write_key_table(key, TEGRA_SE_RNG_KEY_SIZE,
+                rng_ctx->slot->slot_num, SE_KEY_TABLE_TYPE_KEY);
+
+        tegra_se_write_key_table(iv, TEGRA_SE_RNG_IV_SIZE,
+                rng_ctx->slot->slot_num, SE_KEY_TABLE_TYPE_ORGIV);
+
+        pm_runtime_put(se_dev->dev);
+        mutex_unlock(&se_hw_lock);
+
+        if (slen < TEGRA_SE_RNG_SEED_SIZE) {
+                getnstimeofday(&ts);
+                nsec = timespec_to_ns(&ts);
+                do_div(nsec, 1000);
+                nsec ^= se_dev->ctr << 56;
+                se_dev->ctr++;
+                tmp[0] = nsec;
+                tmp[1] = tegra_chip_uid();
+                memcpy(rng_ctx->dt_buf, (u8 *)tmp, TEGRA_SE_RNG_DT_SIZE);
+        } else {
+                memcpy(rng_ctx->dt_buf, dt, TEGRA_SE_RNG_DT_SIZE);
+        }
+
+        rng_ctx->use_org_iv = true;
+
+        return 0;
+}
+
+int tegra_se_sha_init(struct ahash_request *req)
+{
+        return 0;
+}
+
+int tegra_se_sha_update(struct ahash_request *req)
+{
+        return 0;
+}
+
+int tegra_se_sha_finup(struct ahash_request *req)
+{
+        return 0;
+}
+
+int tegra_se_sha_final(struct ahash_request *req)
+{
+        struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
+        struct tegra_se_sha_context *sha_ctx = crypto_ahash_ctx(tfm);
+        struct tegra_se_dev *se_dev = sg_tegra_se_dev;
+        struct scatterlist *src_sg;
+        struct tegra_se_ll *src_ll;
+        u32 total, num_sgs;
+        int err = 0;
+
+        if (!req->nbytes)
+                return -EINVAL;
+
+        if (crypto_ahash_digestsize(tfm) == SHA1_DIGEST_SIZE)
+                sha_ctx->op_mode = SE_AES_OP_MODE_SHA1;
+
+        if (crypto_ahash_digestsize(tfm) == SHA224_DIGEST_SIZE)
+                sha_ctx->op_mode = SE_AES_OP_MODE_SHA224;
+
+        if (crypto_ahash_digestsize(tfm) == SHA256_DIGEST_SIZE)
+                sha_ctx->op_mode = SE_AES_OP_MODE_SHA256;
+
+        if (crypto_ahash_digestsize(tfm) == SHA384_DIGEST_SIZE)
+                sha_ctx->op_mode = SE_AES_OP_MODE_SHA384;
+
+        if (crypto_ahash_digestsize(tfm) == SHA512_DIGEST_SIZE)
+                sha_ctx->op_mode = SE_AES_OP_MODE_SHA512;
+
+        /* take access to the hw */
+        mutex_lock(&se_hw_lock);
+        pm_runtime_get_sync(se_dev->dev);
+
+        num_sgs = tegra_se_count_sgs(req->src, req->nbytes);
+        if ((num_sgs > SE_MAX_SRC_SG_COUNT)) {
+                dev_err(se_dev->dev, "num of SG buffers are more\n");
+                pm_runtime_put(se_dev->dev);
+                mutex_unlock(&se_hw_lock);
+                return -EINVAL;
+        }
+        *se_dev->src_ll_buf = num_sgs-1;
+        src_ll = (struct tegra_se_ll *)(se_dev->src_ll_buf + 1);
+        src_sg = req->src;
+        total = req->nbytes;
+
+        while (total) {
+                err = dma_map_sg(se_dev->dev, src_sg, 1, DMA_TO_DEVICE);
+                if (!err) {
+                        dev_err(se_dev->dev, "dma_map_sg() error\n");
+                        pm_runtime_put(se_dev->dev);
+                        mutex_unlock(&se_hw_lock);
+                        return -EINVAL;
+                }
+                src_ll->addr = sg_dma_address(src_sg);
+                src_ll->data_len = src_sg->length;
+
+                total -= src_sg->length;
+                src_sg = sg_next(src_sg);
+                src_ll++;
+        }
+
+        tegra_se_config_algo(se_dev, sha_ctx->op_mode, false, 0);
+        tegra_se_config_sha(se_dev, req->nbytes);
+        err = tegra_se_start_operation(se_dev, 0, false);
+        if (!err) {
+                tegra_se_read_hash_result(se_dev, req->result,
+                        crypto_ahash_digestsize(tfm), true);
+                if ((sha_ctx->op_mode == SE_AES_OP_MODE_SHA384) ||
+                        (sha_ctx->op_mode == SE_AES_OP_MODE_SHA512)) {
+                        u32 *result = (u32 *)req->result;
+                        u32 temp, i;
+
+                        for (i = 0; i < crypto_ahash_digestsize(tfm)/4;
+                                i += 2) {
+                                temp = result[i];
+                                result[i] = result[i+1];
+                                result[i+1] = temp;
+                        }
+                }
+        }
+
+        src_sg = req->src;
+        total = req->nbytes;
+        while (total) {
+                dma_unmap_sg(se_dev->dev, src_sg, 1, DMA_TO_DEVICE);
+                total -= src_sg->length;
+                src_sg = sg_next(src_sg);
+        }
+        pm_runtime_put(se_dev->dev);
+        mutex_unlock(&se_hw_lock);
+
+        return err;
+}
+
+static int tegra_se_sha_digest(struct ahash_request *req)
+{
+        return tegra_se_sha_init(req) ?: tegra_se_sha_final(req);
+}
+
+int tegra_se_sha_cra_init(struct crypto_tfm *tfm)
+{
+        crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm),
+                                 sizeof(struct tegra_se_sha_context));
+        return 0;
+}
+
+void tegra_se_sha_cra_exit(struct crypto_tfm *tfm)
+{
+        /* do nothing */
+}
+
+int tegra_se_aes_cmac_init(struct ahash_request *req)
+{
+
+        return 0;
+}
+
+int tegra_se_aes_cmac_update(struct ahash_request *req)
+{
+        return 0;
+}
+
+int tegra_se_aes_cmac_final(struct ahash_request *req)
+{
+        struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
+        struct tegra_se_aes_cmac_context *cmac_ctx = crypto_ahash_ctx(tfm);
+        struct tegra_se_dev *se_dev = sg_tegra_se_dev;
+        struct scatterlist *src_sg;
+        struct tegra_se_ll *src_ll;
+        struct sg_mapping_iter miter;
+        u32 num_sgs, blocks_to_process, last_block_bytes = 0, bytes_to_copy = 0;
+        u8 piv[TEGRA_SE_AES_IV_SIZE];
+        int total, ret = 0, i = 0, mapped_sg_count = 0;
+        bool padding_needed = false;
+        unsigned long flags;
+        unsigned int sg_flags = SG_MITER_ATOMIC;
+        u8 *temp_buffer = NULL;
+        bool use_orig_iv = true;
+
+        /* take access to the hw */
+        mutex_lock(&se_hw_lock);
+        pm_runtime_get_sync(se_dev->dev);
+
+        blocks_to_process = req->nbytes / TEGRA_SE_AES_BLOCK_SIZE;
+        /* num of bytes less than block size */
+        if ((req->nbytes % TEGRA_SE_AES_BLOCK_SIZE) || !blocks_to_process) {
+                padding_needed = true;
+                last_block_bytes = req->nbytes % TEGRA_SE_AES_BLOCK_SIZE;
+        } else {
+                /* decrement num of blocks */
+                blocks_to_process--;
+                if (blocks_to_process) {
+                        /* there are blocks to process and find last block
+                                bytes */
+                        last_block_bytes = req->nbytes -
+                                (blocks_to_process * TEGRA_SE_AES_BLOCK_SIZE);
+                } else {
+                        /* this is the last block and equal to block size */
+                        last_block_bytes = req->nbytes;
+                }
+        }
+
+        /* first process all blocks except last block */
+        if (blocks_to_process) {
+                num_sgs = tegra_se_count_sgs(req->src, req->nbytes);
+                if (num_sgs > SE_MAX_SRC_SG_COUNT) {
+                        dev_err(se_dev->dev, "num of SG buffers are more\n");
+                        goto out;
+                }
+                *se_dev->src_ll_buf = num_sgs - 1;
+                src_ll = (struct tegra_se_ll *)(se_dev->src_ll_buf + 1);
+                src_sg = req->src;
+                total = blocks_to_process * TEGRA_SE_AES_BLOCK_SIZE;
+                while (total > 0) {
+                        ret = dma_map_sg(se_dev->dev, src_sg, 1, DMA_TO_DEVICE);
+                        mapped_sg_count++;
+                        if (!ret) {
+                                dev_err(se_dev->dev, "dma_map_sg() error\n");
+                                goto out;
+                        }
+                        src_ll->addr = sg_dma_address(src_sg);
+                        if (total > src_sg->length)
+                                src_ll->data_len = src_sg->length;
+                        else
+                                src_ll->data_len = total;
+
+                        total -= src_sg->length;
+                        if (total > 0) {
+                                src_sg = sg_next(src_sg);
+                                src_ll++;
+                        }
+                        WARN_ON(((total != 0) && (!src_sg)));
+                }
+                tegra_se_config_algo(se_dev, SE_AES_OP_MODE_CMAC, true,
+                        cmac_ctx->keylen);
+                /* write zero IV */
+                memset(piv, 0, TEGRA_SE_AES_IV_SIZE);
+                tegra_se_write_key_table(piv, TEGRA_SE_AES_IV_SIZE,
+                                        cmac_ctx->slot->slot_num,
+                                        SE_KEY_TABLE_TYPE_ORGIV);
+                tegra_se_config_crypto(se_dev, SE_AES_OP_MODE_CMAC, true,
+                                        cmac_ctx->slot->slot_num, true);
+                tegra_se_start_operation(se_dev,
+                        blocks_to_process * TEGRA_SE_AES_BLOCK_SIZE, false);
+                src_sg = req->src;
+                while (mapped_sg_count--) {
+                        dma_unmap_sg(se_dev->dev, src_sg, 1, DMA_TO_DEVICE);
+                        src_sg = sg_next(src_sg);
+                }
+                use_orig_iv = false;
+        }
+
+        /* get the last block bytes from the sg_dma buffer using miter */
+        src_sg = req->src;
+        num_sgs = tegra_se_count_sgs(req->src, req->nbytes);
+        sg_flags |= SG_MITER_FROM_SG;
+        sg_miter_start(&miter, req->src, num_sgs, sg_flags);
+        local_irq_save(flags);
+        total = 0;
+        cmac_ctx->buffer = dma_alloc_coherent(se_dev->dev,
+                                TEGRA_SE_AES_BLOCK_SIZE,
+                                &cmac_ctx->dma_addr, GFP_KERNEL);
+
+        if (!cmac_ctx->buffer)
+                goto out;
+
+        temp_buffer = cmac_ctx->buffer;
+        while (sg_miter_next(&miter) && total < req->nbytes) {
+                unsigned int len;
+                len = min(miter.length, req->nbytes - total);
+                if ((req->nbytes - (total + len)) <= last_block_bytes) {
+                        bytes_to_copy =
+                                last_block_bytes -
+                                (req->nbytes - (total + len));
+                        memcpy(temp_buffer, miter.addr + (len - bytes_to_copy),
+                                bytes_to_copy);
+                        last_block_bytes -= bytes_to_copy;
+                        temp_buffer += bytes_to_copy;
+                }
+                total += len;
+        }
+        sg_miter_stop(&miter);
+        local_irq_restore(flags);
+
+        /* process last block */
+        if (padding_needed) {
+                /* pad with 0x80, 0, 0 ... */
+                last_block_bytes = req->nbytes % TEGRA_SE_AES_BLOCK_SIZE;
+                cmac_ctx->buffer[last_block_bytes] = 0x80;
+                for (i = last_block_bytes+1; i < TEGRA_SE_AES_BLOCK_SIZE; i++)
+                        cmac_ctx->buffer[i] = 0;
+                /* XOR with K2 */
+                for (i = 0; i < TEGRA_SE_AES_BLOCK_SIZE; i++)
+                        cmac_ctx->buffer[i] ^= cmac_ctx->K2[i];
+        } else {
+                /* XOR with K1 */
+                for (i = 0; i < TEGRA_SE_AES_BLOCK_SIZE; i++)
+                        cmac_ctx->buffer[i] ^= cmac_ctx->K1[i];
+        }
+        *se_dev->src_ll_buf = 0;
+        src_ll = (struct tegra_se_ll *)(se_dev->src_ll_buf + 1);
+        src_ll->addr = cmac_ctx->dma_addr;
+        src_ll->data_len = TEGRA_SE_AES_BLOCK_SIZE;
+
+        if (use_orig_iv) {
+                /* use zero IV, this is when num of bytes is
+                        less <= block size */
+                memset(piv, 0, TEGRA_SE_AES_IV_SIZE);
+                tegra_se_write_key_table(piv, TEGRA_SE_AES_IV_SIZE,
+                                        cmac_ctx->slot->slot_num,
+                                        SE_KEY_TABLE_TYPE_ORGIV);
+        }
+
+        tegra_se_config_algo(se_dev, SE_AES_OP_MODE_CMAC, true,
+                                cmac_ctx->keylen);
+        tegra_se_config_crypto(se_dev, SE_AES_OP_MODE_CMAC, true,
+                                cmac_ctx->slot->slot_num, use_orig_iv);
+        tegra_se_start_operation(se_dev, TEGRA_SE_AES_BLOCK_SIZE, false);
+        tegra_se_read_hash_result(se_dev, req->result,
+                                TEGRA_SE_AES_CMAC_DIGEST_SIZE, false);
+
+out:
+        pm_runtime_put(se_dev->dev);
+        mutex_unlock(&se_hw_lock);
+
+        if (cmac_ctx->buffer)
+                dma_free_coherent(se_dev->dev, TEGRA_SE_AES_BLOCK_SIZE,
+                        cmac_ctx->buffer, cmac_ctx->dma_addr);
+
+        return 0;
+}
+
+int tegra_se_aes_cmac_setkey(struct crypto_ahash *tfm, const u8 *key,
+                unsigned int keylen)
+{
+        struct tegra_se_aes_cmac_context *ctx = crypto_ahash_ctx(tfm);
+        struct tegra_se_dev *se_dev = sg_tegra_se_dev;
+        struct tegra_se_ll *src_ll, *dst_ll;
+        struct tegra_se_slot *pslot;
+        u8 piv[TEGRA_SE_AES_IV_SIZE];
+        u32 *pbuf;
+        dma_addr_t pbuf_adr;
+        int ret = 0;
+        u8 const rb = 0x87;
+        u8 msb;
+
+        if (!ctx) {
+                dev_err(se_dev->dev, "invalid context");
+                return -EINVAL;
+        }
+
+        if ((keylen != TEGRA_SE_KEY_128_SIZE) &&
+                (keylen != TEGRA_SE_KEY_192_SIZE) &&
+                (keylen != TEGRA_SE_KEY_256_SIZE)) {
+                dev_err(se_dev->dev, "invalid key size");
+                return -EINVAL;
+        }
+
+        if (key) {
+                if (!ctx->slot || (ctx->slot &&
+                    ctx->slot->slot_num == ssk_slot.slot_num)) {
+                        pslot = tegra_se_alloc_key_slot();
+                        if (!pslot) {
+                                dev_err(se_dev->dev, "no free key slot\n");
+                                return -ENOMEM;
+                        }
+                        ctx->slot = pslot;
+                }
+                ctx->keylen = keylen;
+        } else {
+                tegra_se_free_key_slot(ctx->slot);
+                ctx->slot = &ssk_slot;
+                ctx->keylen = AES_KEYSIZE_128;
+        }
+
+        pbuf = dma_alloc_coherent(se_dev->dev, TEGRA_SE_AES_BLOCK_SIZE,
+                &pbuf_adr, GFP_KERNEL);
+        if (!pbuf) {
+                dev_err(se_dev->dev, "can not allocate dma buffer");
+                return -ENOMEM;
+        }
+        memset(pbuf, 0, TEGRA_SE_AES_BLOCK_SIZE);
+
+        /* take access to the hw */
+        mutex_lock(&se_hw_lock);
+        pm_runtime_get_sync(se_dev->dev);
+
+        *se_dev->src_ll_buf = 0;
+        *se_dev->dst_ll_buf = 0;
+        src_ll = (struct tegra_se_ll *)(se_dev->src_ll_buf + 1);
+        dst_ll = (struct tegra_se_ll *)(se_dev->dst_ll_buf + 1);
+
+        src_ll->addr = pbuf_adr;
+        src_ll->data_len = TEGRA_SE_AES_BLOCK_SIZE;
+        dst_ll->addr = pbuf_adr;
+        dst_ll->data_len = TEGRA_SE_AES_BLOCK_SIZE;
+
+        /* load the key */
+        tegra_se_write_key_table((u8 *)key, keylen,
+                                ctx->slot->slot_num, SE_KEY_TABLE_TYPE_KEY);
+
+        /* write zero IV */
+        memset(piv, 0, TEGRA_SE_AES_IV_SIZE);
+
+        /* load IV */
+        tegra_se_write_key_table(piv, TEGRA_SE_AES_IV_SIZE,
+                                ctx->slot->slot_num, SE_KEY_TABLE_TYPE_ORGIV);
+
+        /* config crypto algo */
+        tegra_se_config_algo(se_dev, SE_AES_OP_MODE_CBC, true, keylen);
+
+        tegra_se_config_crypto(se_dev, SE_AES_OP_MODE_CBC, true,
+                ctx->slot->slot_num, true);
+
+        ret = tegra_se_start_operation(se_dev, TEGRA_SE_AES_BLOCK_SIZE, false);
+        if (ret) {
+                dev_err(se_dev->dev, "tegra_se_aes_cmac_setkey:: start op failed\n");
+                goto out;
+        }
+
+        /* compute K1 subkey */
+        memcpy(ctx->K1, pbuf, TEGRA_SE_AES_BLOCK_SIZE);
+        tegra_se_leftshift_onebit(ctx->K1, TEGRA_SE_AES_BLOCK_SIZE, &msb);
+        if (msb)
+                ctx->K1[TEGRA_SE_AES_BLOCK_SIZE - 1] ^= rb;
+
+        /* compute K2 subkey */
+        memcpy(ctx->K2, ctx->K1, TEGRA_SE_AES_BLOCK_SIZE);
+        tegra_se_leftshift_onebit(ctx->K2, TEGRA_SE_AES_BLOCK_SIZE, &msb);
+
+        if (msb)
+                ctx->K2[TEGRA_SE_AES_BLOCK_SIZE - 1] ^= rb;
+
+out:
+        pm_runtime_put(se_dev->dev);
+        mutex_unlock(&se_hw_lock);
+
+        if (pbuf) {
+                dma_free_coherent(se_dev->dev, TEGRA_SE_AES_BLOCK_SIZE,
+                        pbuf, pbuf_adr);
+        }
+
+        return 0;
+}
+
+int tegra_se_aes_cmac_digest(struct ahash_request *req)
+{
+        return tegra_se_aes_cmac_init(req) ?: tegra_se_aes_cmac_final(req);
+}
+
+int tegra_se_aes_cmac_finup(struct ahash_request *req)
+{
+        return 0;
+}
+
+int tegra_se_aes_cmac_cra_init(struct crypto_tfm *tfm)
+{
+        crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm),
+                                 sizeof(struct tegra_se_aes_cmac_context));
+
+        return 0;
+}
+void tegra_se_aes_cmac_cra_exit(struct crypto_tfm *tfm)
+{
+        struct tegra_se_aes_cmac_context *ctx = crypto_tfm_ctx(tfm);
+
+        tegra_se_free_key_slot(ctx->slot);
+        ctx->slot = NULL;
+}
+
+static struct crypto_alg aes_algs[] = {
+        {
+                .cra_name = "cbc(aes)",
+                .cra_driver_name = "cbc-aes-tegra",
+                .cra_priority = 300,
+                .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
+                .cra_blocksize = TEGRA_SE_AES_BLOCK_SIZE,
+                .cra_ctxsize  = sizeof(struct tegra_se_aes_context),
+                .cra_alignmask = 0,
+                .cra_type = &crypto_ablkcipher_type,
+                .cra_module = THIS_MODULE,
+                .cra_init = tegra_se_aes_cra_init,
+                .cra_exit = tegra_se_aes_cra_exit,
+                .cra_u.ablkcipher = {
+                        .min_keysize = TEGRA_SE_AES_MIN_KEY_SIZE,
+                        .max_keysize = TEGRA_SE_AES_MAX_KEY_SIZE,
+                        .ivsize = TEGRA_SE_AES_IV_SIZE,
+                        .setkey = tegra_se_aes_setkey,
+                        .encrypt = tegra_se_aes_cbc_encrypt,
+                        .decrypt = tegra_se_aes_cbc_decrypt,
+                }
+        }, {
+                .cra_name = "ecb(aes)",
+                .cra_driver_name = "ecb-aes-tegra",
+                .cra_priority = 300,
+                .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
+                .cra_blocksize = TEGRA_SE_AES_BLOCK_SIZE,
+                .cra_ctxsize  = sizeof(struct tegra_se_aes_context),
+                .cra_alignmask = 0,
+                .cra_type = &crypto_ablkcipher_type,
+                .cra_module = THIS_MODULE,
+                .cra_init = tegra_se_aes_cra_init,
+                .cra_exit = tegra_se_aes_cra_exit,
+                .cra_u.ablkcipher = {
+                        .min_keysize = TEGRA_SE_AES_MIN_KEY_SIZE,
+                        .max_keysize = TEGRA_SE_AES_MAX_KEY_SIZE,
+                        .ivsize = TEGRA_SE_AES_IV_SIZE,
+                        .setkey = tegra_se_aes_setkey,
+                        .encrypt = tegra_se_aes_ecb_encrypt,
+                        .decrypt = tegra_se_aes_ecb_decrypt,
+                }
+        }, {
+                .cra_name = "ctr(aes)",
+                .cra_driver_name = "ctr-aes-tegra",
+                .cra_priority = 300,
+                .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
+                .cra_blocksize = TEGRA_SE_AES_BLOCK_SIZE,
+                .cra_ctxsize  = sizeof(struct tegra_se_aes_context),
+                .cra_alignmask = 0,
+                .cra_type = &crypto_ablkcipher_type,
+                .cra_module = THIS_MODULE,
+                .cra_init = tegra_se_aes_cra_init,
+                .cra_exit = tegra_se_aes_cra_exit,
+                .cra_u.ablkcipher = {
+                        .min_keysize = TEGRA_SE_AES_MIN_KEY_SIZE,
+                        .max_keysize = TEGRA_SE_AES_MAX_KEY_SIZE,
+                        .ivsize = TEGRA_SE_AES_IV_SIZE,
+                        .setkey = tegra_se_aes_setkey,
+                        .encrypt = tegra_se_aes_ctr_encrypt,
+                        .decrypt = tegra_se_aes_ctr_decrypt,
+                        .geniv = "eseqiv",
+                }
+        }, {
+                .cra_name = "ofb(aes)",
+                .cra_driver_name = "ofb-aes-tegra",
+                .cra_priority = 300,
+                .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
+                .cra_blocksize = TEGRA_SE_AES_BLOCK_SIZE,
+                .cra_ctxsize  = sizeof(struct tegra_se_aes_context),
+                .cra_alignmask = 0,
+                .cra_type = &crypto_ablkcipher_type,
+                .cra_module = THIS_MODULE,
+                .cra_init = tegra_se_aes_cra_init,
+                .cra_exit = tegra_se_aes_cra_exit,
+                .cra_u.ablkcipher = {
+                        .min_keysize = TEGRA_SE_AES_MIN_KEY_SIZE,
+                        .max_keysize = TEGRA_SE_AES_MAX_KEY_SIZE,
+                        .ivsize = TEGRA_SE_AES_IV_SIZE,
+                        .setkey = tegra_se_aes_setkey,
+                        .encrypt = tegra_se_aes_ofb_encrypt,
+                        .decrypt = tegra_se_aes_ofb_decrypt,
+                        .geniv = "eseqiv",
+                }
+        }, {
+                .cra_name = "ansi_cprng",
+                .cra_driver_name = "rng-aes-tegra",
+                .cra_priority = 100,
+                .cra_flags = CRYPTO_ALG_TYPE_RNG,
+                .cra_ctxsize = sizeof(struct tegra_se_rng_context),
+                .cra_type = &crypto_rng_type,
+                .cra_module = THIS_MODULE,
+                .cra_init = tegra_se_rng_init,
+                .cra_exit = tegra_se_rng_exit,
+                .cra_u = {
+                        .rng = {
+                                .rng_make_random = tegra_se_rng_get_random,
+                                .rng_reset = tegra_se_rng_reset,
+                                .seedsize = TEGRA_SE_RNG_SEED_SIZE,
+                        }
+                }
+        }
+};
+
+static struct ahash_alg hash_algs[] = {
+        {
+                .init = tegra_se_aes_cmac_init,
+                .update = tegra_se_aes_cmac_update,
+                .final = tegra_se_aes_cmac_final,
+                .finup = tegra_se_aes_cmac_finup,
+                .digest = tegra_se_aes_cmac_digest,
+                .setkey = tegra_se_aes_cmac_setkey,
+                .halg.digestsize = TEGRA_SE_AES_CMAC_DIGEST_SIZE,
+                .halg.base = {
+                        .cra_name = "cmac(aes)",
+                        .cra_driver_name = "tegra-se-cmac(aes)",
+                        .cra_priority = 100,
+                        .cra_flags = CRYPTO_ALG_TYPE_AHASH,
+                        .cra_blocksize = TEGRA_SE_AES_BLOCK_SIZE,
+                        .cra_ctxsize = sizeof(struct tegra_se_aes_cmac_context),
+                        .cra_alignmask = 0,
+                        .cra_module     = THIS_MODULE,
+                        .cra_init       = tegra_se_aes_cmac_cra_init,
+                        .cra_exit       = tegra_se_aes_cmac_cra_exit,
+                }
+        }, {
+                .init = tegra_se_sha_init,
+                .update = tegra_se_sha_update,
+                .final = tegra_se_sha_final,
+                .finup = tegra_se_sha_finup,
+                .digest = tegra_se_sha_digest,
+                .halg.digestsize = SHA1_DIGEST_SIZE,
+                .halg.base = {
+                        .cra_name = "sha1",
+                        .cra_driver_name = "tegra-se-sha1",
+                        .cra_priority = 100,
+                        .cra_flags = CRYPTO_ALG_TYPE_AHASH,
+                        .cra_blocksize = SHA1_BLOCK_SIZE,
+                        .cra_ctxsize = sizeof(struct tegra_se_sha_context),
+                        .cra_alignmask = 0,
+                        .cra_module = THIS_MODULE,
+                        .cra_init = tegra_se_sha_cra_init,
+                        .cra_exit = tegra_se_sha_cra_exit,
+                }
+        }, {
+                .init = tegra_se_sha_init,
+                .update = tegra_se_sha_update,
+                .final = tegra_se_sha_final,
+                .finup = tegra_se_sha_finup,
+                .digest = tegra_se_sha_digest,
+                .halg.digestsize = SHA224_DIGEST_SIZE,
+                .halg.base = {
+                        .cra_name = "sha224",
+                        .cra_driver_name = "tegra-se-sha224",
+                        .cra_priority = 100,
+                        .cra_flags = CRYPTO_ALG_TYPE_AHASH,
+                        .cra_blocksize = SHA224_BLOCK_SIZE,
+                        .cra_ctxsize = sizeof(struct tegra_se_sha_context),
+                        .cra_alignmask = 0,
+                        .cra_module = THIS_MODULE,
+                        .cra_init = tegra_se_sha_cra_init,
+                        .cra_exit = tegra_se_sha_cra_exit,
+                }
+        }, {
+                .init = tegra_se_sha_init,
+                .update = tegra_se_sha_update,
+                .final = tegra_se_sha_final,
+                .finup = tegra_se_sha_finup,
+                .digest = tegra_se_sha_digest,
+                .halg.digestsize = SHA256_DIGEST_SIZE,
+                .halg.base = {
+                        .cra_name = "sha256",
+                        .cra_driver_name = "tegra-se-sha256",
+                        .cra_priority = 100,
+                        .cra_flags = CRYPTO_ALG_TYPE_AHASH,
+                        .cra_blocksize = SHA256_BLOCK_SIZE,
+                        .cra_ctxsize = sizeof(struct tegra_se_sha_context),
+                        .cra_alignmask = 0,
+                        .cra_module = THIS_MODULE,
+                        .cra_init = tegra_se_sha_cra_init,
+                        .cra_exit = tegra_se_sha_cra_exit,
+                }
+        }, {
+                .init = tegra_se_sha_init,
+                .update = tegra_se_sha_update,
+                .final = tegra_se_sha_final,
+                .finup = tegra_se_sha_finup,
+                .digest = tegra_se_sha_digest,
+                .halg.digestsize = SHA384_DIGEST_SIZE,
+                .halg.base = {
+                        .cra_name = "sha384",
+                        .cra_driver_name = "tegra-se-sha384",
+                        .cra_priority = 100,
+                        .cra_flags = CRYPTO_ALG_TYPE_AHASH,
+                        .cra_blocksize = SHA384_BLOCK_SIZE,
+                        .cra_ctxsize = sizeof(struct tegra_se_sha_context),
+                        .cra_alignmask = 0,
+                        .cra_module = THIS_MODULE,
+                        .cra_init = tegra_se_sha_cra_init,
+                        .cra_exit = tegra_se_sha_cra_exit,
+                }
+        }, {
+                .init = tegra_se_sha_init,
+                .update = tegra_se_sha_update,
+                .final = tegra_se_sha_final,
+                .finup = tegra_se_sha_finup,
+                .digest = tegra_se_sha_digest,
+                .halg.digestsize = SHA512_DIGEST_SIZE,
+                .halg.base = {
+                        .cra_name = "sha512",
+                        .cra_driver_name = "tegra-se-sha512",
+                        .cra_priority = 100,
+                        .cra_flags = CRYPTO_ALG_TYPE_AHASH,
+                        .cra_blocksize = SHA512_BLOCK_SIZE,
+                        .cra_ctxsize = sizeof(struct tegra_se_sha_context),
+                        .cra_alignmask = 0,
+                        .cra_module = THIS_MODULE,
+                        .cra_init = tegra_se_sha_cra_init,
+                        .cra_exit = tegra_se_sha_cra_exit,
+                }
+        }
+};
+
+static int tegra_se_probe(struct platform_device *pdev)
+{
+        struct tegra_se_dev *se_dev = NULL;
+        struct resource *res = NULL;
+        int err = 0, i = 0, j = 0, k = 0;
+
+        se_dev = kzalloc(sizeof(struct tegra_se_dev), GFP_KERNEL);
+        if (!se_dev) {
+                dev_err(&pdev->dev, "memory allocation failed\n");
+                return -ENOMEM;
+        }
+
+        spin_lock_init(&se_dev->lock);
+        crypto_init_queue(&se_dev->queue, TEGRA_SE_CRYPTO_QUEUE_LENGTH);
+        platform_set_drvdata(pdev, se_dev);
+        se_dev->dev = &pdev->dev;
+
+        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+        if (!res) {
+                err = -ENXIO;
+                dev_err(se_dev->dev, "platform_get_resource failed\n");
+                goto fail;
+        }
+
+        se_dev->io_reg = ioremap(res->start, resource_size(res));
+        if (!se_dev->io_reg) {
+                err = -ENOMEM;
+                dev_err(se_dev->dev, "ioremap failed\n");
+                goto fail;
+        }
+
+        res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
+        if (!res) {
+                err = -ENXIO;
+                dev_err(se_dev->dev, "platform_get_resource failed\n");
+                goto err_pmc;
+        }
+
+        se_dev->pmc_io_reg = ioremap(res->start, resource_size(res));
+        if (!se_dev->pmc_io_reg) {
+                err = -ENOMEM;
+                dev_err(se_dev->dev, "pmc ioremap failed\n");
+                goto err_pmc;
+        }
+
+        se_dev->irq = platform_get_irq(pdev, 0);
+        if (!se_dev->irq) {
+                err = -ENODEV;
+                dev_err(se_dev->dev, "platform_get_irq failed\n");
+                goto err_irq;
+        }
+
+        err = request_irq(se_dev->irq, tegra_se_irq, IRQF_DISABLED,
+                        DRIVER_NAME, se_dev);
+        if (err) {
+                dev_err(se_dev->dev, "request_irq failed - irq[%d] err[%d]\n",
+                        se_dev->irq, err);
+                goto err_irq;
+        }
+
+        /* Initialize the clock */
+        se_dev->pclk = clk_get(se_dev->dev, "se");
+        if (IS_ERR(se_dev->pclk)) {
+                dev_err(se_dev->dev, "clock intialization failed (%d)\n",
+                        (int)se_dev->pclk);
+                err = -ENODEV;
+                goto clean;
+        }
+
+        err = clk_set_rate(se_dev->pclk, ULONG_MAX);
+        if (err) {
+                dev_err(se_dev->dev, "clock set_rate failed.\n");
+                goto clean;
+        }
+
+        err = tegra_init_key_slot(se_dev);
+        if (err) {
+                dev_err(se_dev->dev, "init_key_slot failed\n");
+                goto clean;
+        }
+
+        init_completion(&se_dev->complete);
+        se_work_q = alloc_workqueue("se_work_q", WQ_HIGHPRI | WQ_UNBOUND, 16);
+        if (!se_work_q) {
+                dev_err(se_dev->dev, "alloc_workqueue failed\n");
+                goto clean;
+        }
+
+        sg_tegra_se_dev = se_dev;
+        pm_runtime_enable(se_dev->dev);
+        tegra_se_key_read_disable_all();
+
+        err = tegra_se_alloc_ll_buf(se_dev, SE_MAX_SRC_SG_COUNT,
+                SE_MAX_DST_SG_COUNT);
+        if (err) {
+                dev_err(se_dev->dev, "can not allocate ll dma buffer\n");
+                goto clean;
+        }
+
+        for (i = 0; i < ARRAY_SIZE(aes_algs); i++) {
+                INIT_LIST_HEAD(&aes_algs[i].cra_list);
+                err = crypto_register_alg(&aes_algs[i]);
+                if (err) {
+                        dev_err(se_dev->dev,
+                                "crypto_register_alg failed index[%d]\n", i);
+                        goto clean;
+                }
+        }
+
+        for (j = 0; j < ARRAY_SIZE(hash_algs); j++) {
+                err = crypto_register_ahash(&hash_algs[j]);
+                if (err) {
+                        dev_err(se_dev->dev,
+                        "crypto_register_sha alg failed index[%d]\n", i);
+                        goto clean;
+                }
+        }
+
+#if defined(CONFIG_PM)
+        se_dev->ctx_save_buf = dma_alloc_coherent(se_dev->dev,
+                SE_CONTEXT_BUFER_SIZE, &se_dev->ctx_save_buf_adr, GFP_KERNEL);
+        if (!se_dev->ctx_save_buf) {
+                dev_err(se_dev->dev, "Context save buffer alloc filed\n");
+                goto clean;
+        }
+#endif
+
+        dev_info(se_dev->dev, "%s: complete", __func__);
+        return 0;
+
+clean:
+        pm_runtime_disable(se_dev->dev);
+        for (k = 0; k < i; k++)
+                crypto_unregister_alg(&aes_algs[k]);
+
+        for (k = 0; k < j; k++)
+                crypto_unregister_ahash(&hash_algs[j]);
+
+        tegra_se_free_ll_buf(se_dev);
+
+        if (se_work_q)
+                destroy_workqueue(se_work_q);
+
+        if (se_dev->pclk)
+                clk_put(se_dev->pclk);
+
+        free_irq(se_dev->irq, &pdev->dev);
+
+err_irq:
+        iounmap(se_dev->pmc_io_reg);
+err_pmc:
+        iounmap(se_dev->io_reg);
+
+fail:
+        platform_set_drvdata(pdev, NULL);
+        kfree(se_dev);
+        sg_tegra_se_dev = NULL;
+
+        return err;
+}
+
+static int __devexit tegra_se_remove(struct platform_device *pdev)
+{
+        struct tegra_se_dev *se_dev = platform_get_drvdata(pdev);
+        int i;
+
+        if (!se_dev)
+                return -ENODEV;
+
+        pm_runtime_disable(se_dev->dev);
+
+        cancel_work_sync(&se_work);
+        if (se_work_q)
+                destroy_workqueue(se_work_q);
+        free_irq(se_dev->irq, &pdev->dev);
+        for (i = 0; i < ARRAY_SIZE(aes_algs); i++)
+                crypto_unregister_alg(&aes_algs[i]);
+        for (i = 0; i < ARRAY_SIZE(hash_algs); i++)
+                crypto_unregister_ahash(&hash_algs[i]);
+        if (se_dev->pclk)
+                clk_put(se_dev->pclk);
+        tegra_se_free_ll_buf(se_dev);
+        if (se_dev->ctx_save_buf) {
+                dma_free_coherent(se_dev->dev, SE_CONTEXT_BUFER_SIZE,
+                        se_dev->ctx_save_buf, se_dev->ctx_save_buf_adr);
+                se_dev->ctx_save_buf = NULL;
+        }
+        iounmap(se_dev->io_reg);
+        iounmap(se_dev->pmc_io_reg);
+        kfree(se_dev);
+        sg_tegra_se_dev = NULL;
+
+        return 0;
+}
+
+#if defined(CONFIG_PM)
+static int tegra_se_resume(struct device *dev)
+{
+        return 0;
+}
+
+static int tegra_se_generate_rng_key(struct tegra_se_dev *se_dev)
+{
+        int ret = 0;
+        u32 val = 0;
+
+        *se_dev->src_ll_buf = 0;
+        *se_dev->dst_ll_buf = 0;
+
+        /* Configure algorithm */
+        val = SE_CONFIG_ENC_ALG(ALG_RNG) | SE_CONFIG_ENC_MODE(MODE_KEY128) |
+                SE_CONFIG_DST(DST_KEYTAB);
+        se_writel(se_dev, val, SE_CONFIG_REG_OFFSET);
+
+        /* Configure destination key index number */
+        val = SE_CRYPTO_KEYTABLE_DST_KEY_INDEX(srk_slot.slot_num) |
+                SE_CRYPTO_KEYTABLE_DST_WORD_QUAD(KEYS_0_3);
+        se_writel(se_dev, val, SE_CRYPTO_KEYTABLE_DST_REG_OFFSET);
+
+        /* Configure crypto */
+        val = SE_CRYPTO_INPUT_SEL(INPUT_LFSR) | SE_CRYPTO_XOR_POS(XOR_BYPASS) |
+                SE_CRYPTO_CORE_SEL(CORE_ENCRYPT) |
+                SE_CRYPTO_HASH(HASH_DISABLE) |
+                SE_CRYPTO_KEY_INDEX(ssk_slot.slot_num) |
+                SE_CRYPTO_IV_SEL(IV_ORIGINAL);
+        se_writel(se_dev, val, SE_CRYPTO_REG_OFFSET);
+
+        ret = tegra_se_start_operation(se_dev, TEGRA_SE_KEY_128_SIZE, false);
+
+        return ret;
+}
+
+static int tegra_se_generate_srk(struct tegra_se_dev *se_dev)
+{
+        int ret = 0;
+        u32 val = 0;
+
+        mutex_lock(&se_hw_lock);
+        pm_runtime_get_sync(se_dev->dev);
+
+        ret = tegra_se_generate_rng_key(se_dev);
+        if (ret) {
+                pm_runtime_put(se_dev->dev);
+                mutex_unlock(&se_hw_lock);
+                return ret;
+        }
+
+        *se_dev->src_ll_buf = 0;
+        *se_dev->dst_ll_buf = 0;
+
+        val = SE_CONFIG_ENC_ALG(ALG_RNG) | SE_CONFIG_ENC_MODE(MODE_KEY128) |
+                SE_CONFIG_DEC_ALG(ALG_NOP) | SE_CONFIG_DST(DST_SRK);
+
+        se_writel(se_dev, val, SE_CONFIG_REG_OFFSET);
+
+        val = SE_CRYPTO_XOR_POS(XOR_BYPASS) |
+                SE_CRYPTO_CORE_SEL(CORE_ENCRYPT) |
+                SE_CRYPTO_HASH(HASH_DISABLE) |
+                SE_CRYPTO_KEY_INDEX(srk_slot.slot_num) |
+                SE_CRYPTO_IV_SEL(IV_UPDATED);
+
+        se_writel(se_dev, val, SE_CRYPTO_REG_OFFSET);
+        ret = tegra_se_start_operation(se_dev, TEGRA_SE_KEY_128_SIZE, false);
+
+        pm_runtime_put(se_dev->dev);
+        mutex_unlock(&se_hw_lock);
+
+        return ret;
+}
+
+static int tegra_se_lp_generate_random_data(struct tegra_se_dev *se_dev)
+{
+        struct tegra_se_ll *src_ll, *dst_ll;
+        int ret = 0;
+        u32 val;
+
+        mutex_lock(&se_hw_lock);
+        pm_runtime_get_sync(se_dev->dev);
+
+        *se_dev->src_ll_buf = 0;
+        *se_dev->dst_ll_buf = 0;
+        src_ll = (struct tegra_se_ll *)(se_dev->src_ll_buf + 1);
+        dst_ll = (struct tegra_se_ll *)(se_dev->dst_ll_buf + 1);
+        src_ll->addr = se_dev->ctx_save_buf_adr;
+        src_ll->data_len = SE_CONTEXT_SAVE_RANDOM_DATA_SIZE;
+        dst_ll->addr = se_dev->ctx_save_buf_adr;
+        dst_ll->data_len = SE_CONTEXT_SAVE_RANDOM_DATA_SIZE;
+
+        tegra_se_config_algo(se_dev, SE_AES_OP_MODE_RNG_X931, true,
+                TEGRA_SE_KEY_128_SIZE);
+
+        /* Configure crypto */
+        val = SE_CRYPTO_INPUT_SEL(INPUT_LFSR) | SE_CRYPTO_XOR_POS(XOR_BYPASS) |
+                SE_CRYPTO_CORE_SEL(CORE_ENCRYPT) |
+                SE_CRYPTO_HASH(HASH_DISABLE) |
+                SE_CRYPTO_KEY_INDEX(srk_slot.slot_num) |
+                SE_CRYPTO_IV_SEL(IV_ORIGINAL);
+
+        se_writel(se_dev, val, SE_CRYPTO_REG_OFFSET);
+        ret = tegra_se_start_operation(se_dev,
+                SE_CONTEXT_SAVE_RANDOM_DATA_SIZE, false);
+
+        pm_runtime_put(se_dev->dev);
+        mutex_unlock(&se_hw_lock);
+
+        return ret;
+
+}
+
+static int tegra_se_lp_encrypt_context_data(struct tegra_se_dev *se_dev,
+        u32 context_offset, u32 data_size)
+{
+        struct tegra_se_ll *src_ll, *dst_ll;
+        int ret = 0;
+
+        mutex_lock(&se_hw_lock);
+        pm_runtime_get_sync(se_dev->dev);
+
+        *se_dev->src_ll_buf = 0;
+        *se_dev->dst_ll_buf = 0;
+        src_ll = (struct tegra_se_ll *)(se_dev->src_ll_buf + 1);
+        dst_ll = (struct tegra_se_ll *)(se_dev->dst_ll_buf + 1);
+        src_ll->addr = se_dev->ctx_save_buf_adr + context_offset;
+        src_ll->data_len = data_size;
+        dst_ll->addr = se_dev->ctx_save_buf_adr + context_offset;
+        dst_ll->data_len = data_size;
+
+        se_writel(se_dev, SE_CONTEXT_SAVE_SRC(MEM),
+                SE_CONTEXT_SAVE_CONFIG_REG_OFFSET);
+
+        ret = tegra_se_start_operation(se_dev, data_size, true);
+
+        pm_runtime_put(se_dev->dev);
+
+        mutex_unlock(&se_hw_lock);
+
+        return ret;
+}
+
+static int tegra_se_lp_sticky_bits_context_save(struct tegra_se_dev *se_dev)
+{
+        struct tegra_se_ll *dst_ll;
+        int ret = 0;
+
+        mutex_lock(&se_hw_lock);
+        pm_runtime_get_sync(se_dev->dev);
+
+        *se_dev->src_ll_buf = 0;
+        *se_dev->dst_ll_buf = 0;
+        dst_ll = (struct tegra_se_ll *)(se_dev->dst_ll_buf + 1);
+        dst_ll->addr = (se_dev->ctx_save_buf_adr +
+                SE_CONTEXT_SAVE_STICKY_BITS_OFFSET);
+        dst_ll->data_len = SE_CONTEXT_SAVE_STICKY_BITS_SIZE;
+
+        se_writel(se_dev, SE_CONTEXT_SAVE_SRC(STICKY_BITS),
+                SE_CONTEXT_SAVE_CONFIG_REG_OFFSET);
+
+        ret = tegra_se_start_operation(se_dev,
+                SE_CONTEXT_SAVE_STICKY_BITS_SIZE, true);
+
+        pm_runtime_put(se_dev->dev);
+        mutex_unlock(&se_hw_lock);
+
+        return ret;
+}
+
+static int tegra_se_lp_keytable_context_save(struct tegra_se_dev *se_dev)
+{
+        struct tegra_se_ll *dst_ll;
+        int ret = 0, i, j;
+        u32 val = 0;
+
+        /* take access to the hw */
+        mutex_lock(&se_hw_lock);
+        pm_runtime_get_sync(se_dev->dev);
+
+        *se_dev->dst_ll_buf = 0;
+        dst_ll = (struct tegra_se_ll *)(se_dev->dst_ll_buf + 1);
+        dst_ll->addr = (se_dev->ctx_save_buf_adr + SE_CONTEXT_SAVE_KEYS_OFFSET);
+        dst_ll->data_len = TEGRA_SE_KEY_128_SIZE;
+
+        for (i = 0; i < TEGRA_SE_KEYSLOT_COUNT; i++) {
+                for (j = 0; j < 2; j++) {
+                        val = SE_CONTEXT_SAVE_SRC(KEYTABLE) |
+                                SE_CONTEXT_SAVE_KEY_INDEX(i) |
+                                SE_CONTEXT_SAVE_WORD_QUAD(j);
+                        se_writel(se_dev,
+                                val, SE_CONTEXT_SAVE_CONFIG_REG_OFFSET);
+                        ret = tegra_se_start_operation(se_dev,
+                                TEGRA_SE_KEY_128_SIZE, true);
+                        if (ret)
+                                break;
+                        dst_ll->addr += TEGRA_SE_KEY_128_SIZE;
+                }
+        }
+
+        pm_runtime_put(se_dev->dev);
+        mutex_unlock(&se_hw_lock);
+
+        return ret;
+}
+
+static int tegra_se_lp_iv_context_save(struct tegra_se_dev *se_dev,
+        bool org_iv, u32 context_offset)
+{
+        struct tegra_se_ll *dst_ll;
+        int ret = 0, i;
+        u32 val = 0;
+
+        mutex_lock(&se_hw_lock);
+        pm_runtime_get_sync(se_dev->dev);
+
+        *se_dev->dst_ll_buf = 0;
+        dst_ll = (struct tegra_se_ll *)(se_dev->dst_ll_buf + 1);
+        dst_ll->addr = (se_dev->ctx_save_buf_adr + context_offset);
+        dst_ll->data_len = TEGRA_SE_AES_IV_SIZE;
+
+        for (i = 0; i < TEGRA_SE_KEYSLOT_COUNT; i++) {
+                val = SE_CONTEXT_SAVE_SRC(KEYTABLE) |
+                        SE_CONTEXT_SAVE_KEY_INDEX(i) |
+                        (org_iv ? SE_CONTEXT_SAVE_WORD_QUAD(ORIG_IV) :
+                        SE_CONTEXT_SAVE_WORD_QUAD(UPD_IV));
+                se_writel(se_dev, val, SE_CONTEXT_SAVE_CONFIG_REG_OFFSET);
+                ret = tegra_se_start_operation(se_dev,
+                        TEGRA_SE_AES_IV_SIZE, true);
+                if (ret)
+                        break;
+                dst_ll->addr += TEGRA_SE_AES_IV_SIZE;
+        }
+
+        pm_runtime_put(se_dev->dev);
+        mutex_unlock(&se_hw_lock);
+
+        return ret;
+}
+
+static int tegra_se_save_SRK(struct tegra_se_dev *se_dev)
+{
+        int ret = 0;
+
+        mutex_lock(&se_hw_lock);
+        pm_runtime_get_sync(se_dev->dev);
+
+        se_writel(se_dev, SE_CONTEXT_SAVE_SRC(SRK),
+                SE_CONTEXT_SAVE_CONFIG_REG_OFFSET);
+        ret = tegra_se_start_operation(se_dev, 0, true);
+
+        pm_runtime_put(se_dev->dev);
+        mutex_unlock(&se_hw_lock);
+
+        return ret;
+}
+
+static int tegra_se_suspend(struct device *dev)
+{
+        struct platform_device *pdev = to_platform_device(dev);
+        struct tegra_se_dev *se_dev = platform_get_drvdata(pdev);
+        int err = 0, i;
+        unsigned char *dt_buf = NULL;
+        u8 pdata[SE_CONTEXT_KNOWN_PATTERN_SIZE] = {
+                0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
+                0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f};
+
+        if (!se_dev)
+                return -ENODEV;
+
+        /* Generate SRK */
+        err = tegra_se_generate_srk(se_dev);
+        if (err) {
+                dev_err(se_dev->dev, "\n LP SRK genration failed\n");
+                goto out;
+        }
+
+        /* Generate random data*/
+        err = tegra_se_lp_generate_random_data(se_dev);
+        if (err) {
+                dev_err(se_dev->dev, "\n LP random pattern generation failed\n");
+                goto out;
+        }
+
+        /* Encrypt random data */
+        err = tegra_se_lp_encrypt_context_data(se_dev,
+                SE_CONTEXT_SAVE_RANDOM_DATA_OFFSET,
+                SE_CONTEXT_SAVE_RANDOM_DATA_SIZE);
+        if (err) {
+                dev_err(se_dev->dev, "\n LP random pattern encryption failed\n");
+                goto out;
+        }
+
+        /* Sticky bits context save*/
+        err = tegra_se_lp_sticky_bits_context_save(se_dev);
+        if (err) {
+                dev_err(se_dev->dev, "\n LP sticky bits context save failure\n");
+                goto out;
+        }
+
+        /* Key table context save*/
+        err = tegra_se_lp_keytable_context_save(se_dev);
+        if (err) {
+                dev_err(se_dev->dev, "\n LP key table  save failure\n");
+                goto out;
+        }
+
+        /* Original iv context save*/
+        err = tegra_se_lp_iv_context_save(se_dev,
+                true, SE_CONTEXT_ORIGINAL_IV_OFFSET);
+        if (err) {
+                dev_err(se_dev->dev, "\n LP original iv save failure\n");
+                goto out;
+        }
+
+        /* UPdated iv context save*/
+        err = tegra_se_lp_iv_context_save(se_dev,
+                false, SE_CONTEXT_UPDATED_IV_OFFSET);
+        if (err) {
+                dev_err(se_dev->dev, "\n LP updated iv save failure\n");
+                goto out;
+        }
+
+        /* Encrypt known pattern */
+        dt_buf = (unsigned char *)se_dev->ctx_save_buf;
+        dt_buf += SE_CONTEXT_KNOWN_PATTERN_OFFSET;
+        for (i = 0; i < SE_CONTEXT_KNOWN_PATTERN_SIZE; i++)
+                dt_buf[i] = pdata[i];
+        err = tegra_se_lp_encrypt_context_data(se_dev,
+                SE_CONTEXT_KNOWN_PATTERN_OFFSET, SE_CONTEXT_KNOWN_PATTERN_SIZE);
+        if (err) {
+                dev_err(se_dev->dev, "LP known pattern save failure\n");
+                goto out;
+        }
+
+        /* Write lp context buffer address into PMC scratch register */
+        writel(se_dev->ctx_save_buf_adr,
+                se_dev->pmc_io_reg + PMC_SCRATCH43_REG_OFFSET);
+
+        /* Saves SRK in secure scratch */
+        err = tegra_se_save_SRK(se_dev);
+        if (err) {
+                dev_err(se_dev->dev, "LP SRK save failure\n");
+                goto out;
+        }
+
+out:
+        return err;
+}
+#endif
+
+#if defined(CONFIG_PM_RUNTIME)
+static int tegra_se_runtime_suspend(struct device *dev)
+{
+        /*
+         * do a dummy read, to avoid scenarios where you have unposted writes
+         * still on the bus, before disabling clocks
+         */
+        se_readl(sg_tegra_se_dev, SE_CONFIG_REG_OFFSET);
+
+        clk_disable(sg_tegra_se_dev->pclk);
+        return 0;
+}
+
+static int tegra_se_runtime_resume(struct device *dev)
+{
+        clk_enable(sg_tegra_se_dev->pclk);
+        return 0;
+}
+
+static const struct dev_pm_ops tegra_se_dev_pm_ops = {
+        .runtime_suspend = tegra_se_runtime_suspend,
+        .runtime_resume = tegra_se_runtime_resume,
+#if defined(CONFIG_PM)
+        .suspend = tegra_se_suspend,
+        .resume = tegra_se_resume,
+#endif
+};
+#endif
+
+static struct platform_driver tegra_se_driver = {
+        .probe  = tegra_se_probe,
+        .remove = __devexit_p(tegra_se_remove),
+        .driver = {
+                .name   = "tegra-se",
+                .owner  = THIS_MODULE,
+#if defined(CONFIG_PM_RUNTIME)
+                .pm = &tegra_se_dev_pm_ops,
+#endif
+        },
+};
+
+static int __init tegra_se_module_init(void)
+{
+        return  platform_driver_register(&tegra_se_driver);
+}
+
+static void __exit tegra_se_module_exit(void)
+{
+        platform_driver_unregister(&tegra_se_driver);
+}
+
+module_init(tegra_se_module_init);
+module_exit(tegra_se_module_exit);
+
+MODULE_DESCRIPTION("Tegra Crypto algorithm support");
+MODULE_AUTHOR("NVIDIA Corporation");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("tegra-se");
+
diff --git a/drivers/crypto/tegra-se.h b/drivers/crypto/tegra-se.h
new file mode 100644
index 00000000000..8c54df8991e
--- /dev/null
+++ b/drivers/crypto/tegra-se.h
@@ -0,0 +1,235 @@
+/*
+ * Driver for Tegra Security Engine
+ *
+ * Copyright (c) 2011, NVIDIA Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+#ifndef _CRYPTO_TEGRA_SE_H
+#define _CRYPTO_TEGRA_SE_H
+
+#include <crypto/hash.h>
+#include <crypto/sha.h>
+
+#define PFX     "tegra-se: "
+
+#define TEGRA_SE_CRA_PRIORITY   300
+#define TEGRA_SE_COMPOSITE_PRIORITY 400
+#define TEGRA_SE_CRYPTO_QUEUE_LENGTH 50
+#define SE_MAX_SRC_SG_COUNT             50
+#define SE_MAX_DST_SG_COUNT             50
+
+#define TEGRA_SE_KEYSLOT_COUNT          16
+
+/* SE register definitions */
+#define SE_CONFIG_REG_OFFSET            0x014
+#define SE_CONFIG_ENC_ALG_SHIFT         12
+#define SE_CONFIG_DEC_ALG_SHIFT         8
+#define ALG_AES_ENC             1
+#define ALG_RNG                 2
+#define ALG_SHA                 3
+#define ALG_NOP                 0
+#define ALG_AES_DEC             1
+#define SE_CONFIG_ENC_ALG(x)            (x << SE_CONFIG_ENC_ALG_SHIFT)
+#define SE_CONFIG_DEC_ALG(x)            (x << SE_CONFIG_DEC_ALG_SHIFT)
+#define SE_CONFIG_DST_SHIFT                     2
+#define DST_MEMORY              0
+#define DST_HASHREG             1
+#define DST_KEYTAB              2
+#define DST_SRK                 3
+#define SE_CONFIG_DST(x)                        (x << SE_CONFIG_DST_SHIFT)
+#define SE_CONFIG_ENC_MODE_SHIFT        24
+#define SE_CONFIG_DEC_MODE_SHIFT        16
+#define MODE_KEY128             0
+#define MODE_KEY192             1
+#define MODE_KEY256             2
+#define MODE_SHA1               0
+#define MODE_SHA224             4
+#define MODE_SHA256             5
+#define MODE_SHA384             6
+#define MODE_SHA512             7
+#define SE_CONFIG_ENC_MODE(x)           (x << SE_CONFIG_ENC_MODE_SHIFT)
+#define SE_CONFIG_DEC_MODE(x)           (x << SE_CONFIG_DEC_MODE_SHIFT)
+
+#define SE_KEYTABLE_REG_OFFSET          0x31c
+#define SE_KEYTABLE_SLOT_SHIFT          4
+#define SE_KEYTABLE_SLOT(x)                     (x << SE_KEYTABLE_SLOT_SHIFT)
+#define SE_KEYTABLE_QUAD_SHIFT          2
+#define QUAD_KEYS_128   0
+#define QUAD_KEYS_192   1
+#define QUAD_KEYS_256   1
+#define QUAD_ORG_IV             2
+#define QUAD_UPDTD_IV   3
+#define SE_KEYTABLE_QUAD(x)                     (x << SE_KEYTABLE_QUAD_SHIFT)
+#define SE_KEYTABLE_OP_TYPE_SHIFT       9
+#define OP_READ                 0
+#define OP_WRITE                1
+#define SE_KEYTABLE_OP_TYPE(x)          (x << SE_KEYTABLE_OP_TYPE_SHIFT)
+#define SE_KEYTABLE_TABLE_SEL_SHIFT             8
+#define TABLE_KEYIV             0
+#define TABLE_SCHEDULE  1
+#define SE_KEYTABLE_TABLE_SEL(x)        (x << SE_KEYTABLE_TABLE_SEL_SHIFT)
+#define SE_KEYTABLE_PKT_SHIFT           0
+#define SE_KEYTABLE_PKT(x)                      (x << SE_KEYTABLE_PKT_SHIFT)
+
+#define SE_CRYPTO_REG_OFFSET            0x304
+#define SE_CRYPTO_HASH_SHIFT            0
+#define HASH_DISABLE    0
+#define HASH_ENABLE             1
+#define SE_CRYPTO_HASH(x)                       (x << SE_CRYPTO_HASH_SHIFT)
+#define SE_CRYPTO_XOR_POS_SHIFT         1
+#define XOR_BYPASS              0
+#define XOR_TOP                 2
+#define XOR_BOTTOM              3
+#define SE_CRYPTO_XOR_POS(x)            (x << SE_CRYPTO_XOR_POS_SHIFT)
+#define SE_CRYPTO_INPUT_SEL_SHIFT       3
+#define INPUT_AHB               0
+#define INPUT_LFSR              1
+#define INPUT_AESOUT    2
+#define INPUT_LNR_CTR   3
+#define SE_CRYPTO_INPUT_SEL(x)          (x << SE_CRYPTO_INPUT_SEL_SHIFT)
+#define SE_CRYPTO_VCTRAM_SEL_SHIFT      5
+#define VCTRAM_AHB              0
+#define VCTRAM_AESOUT   2
+#define VCTRAM_PREVAHB  3
+#define SE_CRYPTO_VCTRAM_SEL(x)         (x << SE_CRYPTO_VCTRAM_SEL_SHIFT)
+#define SE_CRYPTO_IV_SEL_SHIFT          7
+#define IV_ORIGINAL             0
+#define IV_UPDATED              1
+#define SE_CRYPTO_IV_SEL(x)                     (x << SE_CRYPTO_IV_SEL_SHIFT)
+#define SE_CRYPTO_CORE_SEL_SHIFT        8
+#define CORE_DECRYPT    0
+#define CORE_ENCRYPT    1
+#define SE_CRYPTO_CORE_SEL(x)           (x << SE_CRYPTO_CORE_SEL_SHIFT)
+#define SE_CRYPTO_CTR_VAL_SHIFT         11
+#define SE_CRYPTO_CTR_VAL(x)            (x << SE_CRYPTO_CTR_VAL_SHIFT)
+#define SE_CRYPTO_KEY_INDEX_SHIFT       24
+#define SE_CRYPTO_KEY_INDEX(x)          (x << SE_CRYPTO_KEY_INDEX_SHIFT)
+#define SE_CRYPTO_CTR_CNTN_SHIFT        11
+#define SE_CRYPTO_CTR_CNTN(x)           (x << SE_CRYPTO_CTR_CNTN_SHIFT)
+
+#define SE_CRYPTO_CTR_REG_COUNT         4
+#define SE_CRYPTO_CTR_REG_OFFSET        0x308
+
+#define SE_OPERATION_REG_OFFSET         0x008
+#define SE_OPERATION_SHIFT                      0
+#define OP_ABORT                0
+#define OP_SRART                1
+#define OP_RESTART              2
+#define OP_CTX_SAVE             3
+#define SE_OPERATION(x)                         (x << SE_OPERATION_SHIFT)
+
+#define SE_CONTEXT_SAVE_CONFIG_REG_OFFSET               0x070
+#define SE_CONTEXT_SAVE_WORD_QUAD_SHIFT         0
+#define KEYS_0_3                0
+#define KEYS_4_7                1
+#define ORIG_IV         2
+#define UPD_IV          3
+#define SE_CONTEXT_SAVE_WORD_QUAD(x)    (x << SE_CONTEXT_SAVE_WORD_QUAD_SHIFT)
+
+#define SE_CONTEXT_SAVE_KEY_INDEX_SHIFT         8
+#define SE_CONTEXT_SAVE_KEY_INDEX(x)    (x << SE_CONTEXT_SAVE_KEY_INDEX_SHIFT)
+
+
+#define SE_CONTEXT_SAVE_SRC_SHIFT               30
+#define STICKY_BITS             0
+#define KEYTABLE                1
+#define MEM             2
+#define SRK             3
+#define SE_CONTEXT_SAVE_SRC(x)          (x << SE_CONTEXT_SAVE_SRC_SHIFT)
+
+#define SE_INT_ENABLE_REG_OFFSET        0x00c
+#define SE_INT_STATUS_REG_OFFSET        0x010
+#define INT_DISABLE             0
+#define INT_ENABLE              1
+#define INT_UNSET               0
+#define INT_SET                 1
+#define SE_INT_OP_DONE_SHIFT            4
+#define SE_INT_OP_DONE(x)                       (x << SE_INT_OP_DONE_SHIFT)
+#define SE_INT_ERROR_SHIFT              16
+#define SE_INT_ERROR(x)                 (x << SE_INT_ERROR_SHIFT)
+
+#define SE_CRYPTO_KEYTABLE_DST_REG_OFFSET       0X330
+#define SE_CRYPTO_KEYTABLE_DST_WORD_QUAD_SHIFT          0
+#define SE_CRYPTO_KEYTABLE_DST_WORD_QUAD(x)             \
+                (x << SE_CRYPTO_KEYTABLE_DST_WORD_QUAD_SHIFT)
+
+#define SE_KEY_INDEX_SHIFT              8
+#define SE_CRYPTO_KEYTABLE_DST_KEY_INDEX(x)     (x << SE_KEY_INDEX_SHIFT)
+
+#define SE_IN_LL_ADDR_REG_OFFSET        0x018
+#define SE_OUT_LL_ADDR_REG_OFFSET       0x024
+
+#define SE_KEYTABLE_DATA0_REG_OFFSET    0x320
+#define SE_KEYTABLE_REG_MAX_DATA                16
+
+#define SE_BLOCK_COUNT_REG_OFFSET       0x318
+
+#define SE_SPARE_0_REG_OFFSET           0x80c
+
+#define SE_SHA_CONFIG_REG_OFFSET        0x200
+#define SHA_DISABLE             0
+#define SHA_ENABLE              1
+
+#define SE_SHA_MSG_LENGTH_REG_OFFSET    0x204
+#define SE_SHA_MSG_LEFT_REG_OFFSET              0x214
+
+
+#define SE_HASH_RESULT_REG_COUNT        16
+#define SE_HASH_RESULT_REG_OFFSET       0x030
+
+
+#define TEGRA_SE_KEY_256_SIZE           32
+#define TEGRA_SE_KEY_192_SIZE           24
+#define TEGRA_SE_KEY_128_SIZE           16
+#define TEGRA_SE_AES_BLOCK_SIZE         16
+#define TEGRA_SE_AES_MIN_KEY_SIZE       16
+#define TEGRA_SE_AES_MAX_KEY_SIZE       32
+#define TEGRA_SE_AES_IV_SIZE            16
+#define TEGRA_SE_RNG_IV_SIZE            16
+#define TEGRA_SE_RNG_DT_SIZE            16
+#define TEGRA_SE_RNG_KEY_SIZE           16
+#define TEGRA_SE_RNG_SEED_SIZE          (TEGRA_SE_RNG_IV_SIZE + \
+                                                TEGRA_SE_RNG_KEY_SIZE + \
+                                                TEGRA_SE_RNG_DT_SIZE)
+#define TEGRA_SE_AES_CMAC_DIGEST_SIZE   16
+
+#define SE_KEY_TABLE_ACCESS_REG_OFFSET  0x284
+#define SE_KEY_READ_DISABLE_SHIFT               0
+
+#define SE_CONTEXT_BUFER_SIZE   1072
+#define SE_CONTEXT_SAVE_RANDOM_DATA_OFFSET      0
+#define SE_CONTEXT_SAVE_RANDOM_DATA_SIZE        16
+#define SE_CONTEXT_SAVE_STICKY_BITS_OFFSET      \
+        (SE_CONTEXT_SAVE_RANDOM_DATA_OFFSET + SE_CONTEXT_SAVE_RANDOM_DATA_SIZE)
+#define SE_CONTEXT_SAVE_STICKY_BITS_SIZE        16
+#define SE_CONTEXT_SAVE_KEYS_OFFSET     (SE_CONTEXT_SAVE_STICKY_BITS_OFFSET + \
+                                        SE_CONTEXT_SAVE_STICKY_BITS_SIZE)
+#define SE_CONTEXT_SAVE_KEY_LENGTH      512
+#define SE_CONTEXT_ORIGINAL_IV_OFFSET   (SE_CONTEXT_SAVE_KEYS_OFFSET + \
+                        SE_CONTEXT_SAVE_KEY_LENGTH)
+#define SE_CONTEXT_ORIGINAL_IV_LENGTH   256
+
+#define SE_CONTEXT_UPDATED_IV_OFFSET    (SE_CONTEXT_ORIGINAL_IV_OFFSET + \
+                        SE_CONTEXT_ORIGINAL_IV_LENGTH)
+
+#define SE_CONTEXT_UPDATED_IV_LENGTH    256
+#define SE_CONTEXT_KNOWN_PATTERN_OFFSET (SE_CONTEXT_UPDATED_IV_OFFSET + \
+                        SE_CONTEXT_UPDATED_IV_LENGTH)
+#define SE_CONTEXT_KNOWN_PATTERN_SIZE   16
+
+
+#endif /* _CRYPTO_TEGRA_SE_H */