3 files changed, 5 insertions, 7 deletions

diff --git a/drivers/clocksource/acpi_pm.c b/drivers/clocksource/acpi_pm.c
index effe7974aa9..6b5cf02c35c 100644
--- a/drivers/clocksource/acpi_pm.c
+++ b/drivers/clocksource/acpi_pm.c
@@ -143,7 +143,7 @@ DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_LE,
 #ifndef CONFIG_X86_64
 #include <asm/mach_timer.h>
 #define PMTMR_EXPECTED_RATE \
-  ((CALIBRATE_LATCH * (PMTMR_TICKS_PER_SEC >> 10)) / (CLOCK_TICK_RATE>>10))
+  ((CALIBRATE_LATCH * (PMTMR_TICKS_PER_SEC >> 10)) / (PIT_TICK_RATE>>10))
 /*
  * Some boards have the PMTMR running way too fast. We check
  * the PMTMR rate against PIT channel 2 to catch these cases.
diff --git a/drivers/clocksource/i8253.c b/drivers/clocksource/i8253.c
index 27c49e60b7d..e7cab2da910 100644
--- a/drivers/clocksource/i8253.c
+++ b/drivers/clocksource/i8253.c
@@ -53,7 +53,7 @@ static cycle_t i8253_read(struct clocksource *cs)
         count |= inb_p(PIT_CH0) << 8;
 
         /* VIA686a test code... reset the latch if count > max + 1 */
-        if (count > LATCH) {
+        if (count > PIT_LATCH) {
                 outb_p(0x34, PIT_MODE);
                 outb_p(PIT_LATCH & 0xff, PIT_CH0);
                 outb_p(PIT_LATCH >> 8, PIT_CH0);
@@ -114,8 +114,8 @@ static void init_pit_timer(enum clock_event_mode mode,
         case CLOCK_EVT_MODE_PERIODIC:
                 /* binary, mode 2, LSB/MSB, ch 0 */
                 outb_p(0x34, PIT_MODE);
-                outb_p(LATCH & 0xff , PIT_CH0); /* LSB */
-                outb_p(LATCH >> 8 , PIT_CH0);           /* MSB */
+                outb_p(PIT_LATCH & 0xff , PIT_CH0);     /* LSB */
+                outb_p(PIT_LATCH >> 8 , PIT_CH0);               /* MSB */
                 break;
 
         case CLOCK_EVT_MODE_SHUTDOWN:
diff --git a/drivers/clocksource/tcb_clksrc.c b/drivers/clocksource/tcb_clksrc.c
index 79c47e88d5d..55d0f95f82f 100644
--- a/drivers/clocksource/tcb_clksrc.c
+++ b/drivers/clocksource/tcb_clksrc.c
@@ -59,7 +59,6 @@ static struct clocksource clksrc = {
         .rating         = 200,
         .read           = tc_get_cycles,
         .mask           = CLOCKSOURCE_MASK(32),
-        .shift          = 18,
         .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
 };
 
@@ -256,7 +255,6 @@ static int __init tcb_clksrc_init(void)
                 best_divisor_idx = i;
         }
 
-        clksrc.mult = clocksource_hz2mult(divided_rate, clksrc.shift);
 
         printk(bootinfo, clksrc.name, CONFIG_ATMEL_TCB_CLKSRC_BLOCK,
                         divided_rate / 1000000,
@@ -292,7 +290,7 @@ static int __init tcb_clksrc_init(void)
         __raw_writel(ATMEL_TC_SYNC, tcaddr + ATMEL_TC_BCR);
 
         /* and away we go! */
-        clocksource_register(&clksrc);
+        clocksource_register_hz(&clksrc, divided_rate);
 
         /* channel 2:  periodic and oneshot timer support */
         setup_clkevents(tc, clk32k_divisor_idx);