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path: root/drivers/clocksource/sh_tmu.c
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Diffstat (limited to 'drivers/clocksource/sh_tmu.c')
-rw-r--r--drivers/clocksource/sh_tmu.c16
1 files changed, 6 insertions, 10 deletions
diff --git a/drivers/clocksource/sh_tmu.c b/drivers/clocksource/sh_tmu.c
index 97f54b634be..c1b51d49d10 100644
--- a/drivers/clocksource/sh_tmu.c
+++ b/drivers/clocksource/sh_tmu.c
@@ -45,7 +45,7 @@ struct sh_tmu_priv {
45 struct clocksource cs; 45 struct clocksource cs;
46}; 46};
47 47
48static DEFINE_SPINLOCK(sh_tmu_lock); 48static DEFINE_RAW_SPINLOCK(sh_tmu_lock);
49 49
50#define TSTR -1 /* shared register */ 50#define TSTR -1 /* shared register */
51#define TCOR 0 /* channel register */ 51#define TCOR 0 /* channel register */
@@ -95,7 +95,7 @@ static void sh_tmu_start_stop_ch(struct sh_tmu_priv *p, int start)
95 unsigned long flags, value; 95 unsigned long flags, value;
96 96
97 /* start stop register shared by multiple timer channels */ 97 /* start stop register shared by multiple timer channels */
98 spin_lock_irqsave(&sh_tmu_lock, flags); 98 raw_spin_lock_irqsave(&sh_tmu_lock, flags);
99 value = sh_tmu_read(p, TSTR); 99 value = sh_tmu_read(p, TSTR);
100 100
101 if (start) 101 if (start)
@@ -104,7 +104,7 @@ static void sh_tmu_start_stop_ch(struct sh_tmu_priv *p, int start)
104 value &= ~(1 << cfg->timer_bit); 104 value &= ~(1 << cfg->timer_bit);
105 105
106 sh_tmu_write(p, TSTR, value); 106 sh_tmu_write(p, TSTR, value);
107 spin_unlock_irqrestore(&sh_tmu_lock, flags); 107 raw_spin_unlock_irqrestore(&sh_tmu_lock, flags);
108} 108}
109 109
110static int sh_tmu_enable(struct sh_tmu_priv *p) 110static int sh_tmu_enable(struct sh_tmu_priv *p)
@@ -245,12 +245,7 @@ static void sh_tmu_clock_event_start(struct sh_tmu_priv *p, int periodic)
245 245
246 sh_tmu_enable(p); 246 sh_tmu_enable(p);
247 247
248 /* TODO: calculate good shift from rate and counter bit width */ 248 clockevents_config(ced, p->rate);
249
250 ced->shift = 32;
251 ced->mult = div_sc(p->rate, NSEC_PER_SEC, ced->shift);
252 ced->max_delta_ns = clockevent_delta2ns(0xffffffff, ced);
253 ced->min_delta_ns = 5000;
254 249
255 if (periodic) { 250 if (periodic) {
256 p->periodic = (p->rate + HZ/2) / HZ; 251 p->periodic = (p->rate + HZ/2) / HZ;
@@ -323,7 +318,8 @@ static void sh_tmu_register_clockevent(struct sh_tmu_priv *p,
323 ced->set_mode = sh_tmu_clock_event_mode; 318 ced->set_mode = sh_tmu_clock_event_mode;
324 319
325 dev_info(&p->pdev->dev, "used for clock events\n"); 320 dev_info(&p->pdev->dev, "used for clock events\n");
326 clockevents_register_device(ced); 321
322 clockevents_config_and_register(ced, 1, 0x300, 0xffffffff);
327 323
328 ret = setup_irq(p->irqaction.irq, &p->irqaction); 324 ret = setup_irq(p->irqaction.irq, &p->irqaction);
329 if (ret) { 325 if (ret) {