diff options
Diffstat (limited to 'drivers/char')
-rw-r--r-- | drivers/char/agp/intel-agp.c | 25 |
1 files changed, 24 insertions, 1 deletions
diff --git a/drivers/char/agp/intel-agp.c b/drivers/char/agp/intel-agp.c index a3e10dc7cc2..f499c5e0ca5 100644 --- a/drivers/char/agp/intel-agp.c +++ b/drivers/char/agp/intel-agp.c | |||
@@ -175,6 +175,10 @@ extern int agp_memory_reserved; | |||
175 | #define SNB_GMCH_GMS_STOLEN_448M (0xe << 3) | 175 | #define SNB_GMCH_GMS_STOLEN_448M (0xe << 3) |
176 | #define SNB_GMCH_GMS_STOLEN_480M (0xf << 3) | 176 | #define SNB_GMCH_GMS_STOLEN_480M (0xf << 3) |
177 | #define SNB_GMCH_GMS_STOLEN_512M (0x10 << 3) | 177 | #define SNB_GMCH_GMS_STOLEN_512M (0x10 << 3) |
178 | #define SNB_GTT_SIZE_0M (0 << 8) | ||
179 | #define SNB_GTT_SIZE_1M (1 << 8) | ||
180 | #define SNB_GTT_SIZE_2M (2 << 8) | ||
181 | #define SNB_GTT_SIZE_MASK (3 << 8) | ||
178 | 182 | ||
179 | static const struct aper_size_info_fixed intel_i810_sizes[] = | 183 | static const struct aper_size_info_fixed intel_i810_sizes[] = |
180 | { | 184 | { |
@@ -1438,6 +1442,8 @@ static unsigned long intel_i965_mask_memory(struct agp_bridge_data *bridge, | |||
1438 | 1442 | ||
1439 | static void intel_i965_get_gtt_range(int *gtt_offset, int *gtt_size) | 1443 | static void intel_i965_get_gtt_range(int *gtt_offset, int *gtt_size) |
1440 | { | 1444 | { |
1445 | u16 snb_gmch_ctl; | ||
1446 | |||
1441 | switch (agp_bridge->dev->device) { | 1447 | switch (agp_bridge->dev->device) { |
1442 | case PCI_DEVICE_ID_INTEL_GM45_HB: | 1448 | case PCI_DEVICE_ID_INTEL_GM45_HB: |
1443 | case PCI_DEVICE_ID_INTEL_EAGLELAKE_HB: | 1449 | case PCI_DEVICE_ID_INTEL_EAGLELAKE_HB: |
@@ -1449,9 +1455,26 @@ static void intel_i965_get_gtt_range(int *gtt_offset, int *gtt_size) | |||
1449 | case PCI_DEVICE_ID_INTEL_IRONLAKE_M_HB: | 1455 | case PCI_DEVICE_ID_INTEL_IRONLAKE_M_HB: |
1450 | case PCI_DEVICE_ID_INTEL_IRONLAKE_MA_HB: | 1456 | case PCI_DEVICE_ID_INTEL_IRONLAKE_MA_HB: |
1451 | case PCI_DEVICE_ID_INTEL_IRONLAKE_MC2_HB: | 1457 | case PCI_DEVICE_ID_INTEL_IRONLAKE_MC2_HB: |
1458 | *gtt_offset = *gtt_size = MB(2); | ||
1459 | break; | ||
1452 | case PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB: | 1460 | case PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB: |
1453 | case PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_HB: | 1461 | case PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_HB: |
1454 | *gtt_offset = *gtt_size = MB(2); | 1462 | *gtt_offset = MB(2); |
1463 | |||
1464 | pci_read_config_word(intel_private.pcidev, SNB_GMCH_CTRL, &snb_gmch_ctl); | ||
1465 | switch (snb_gmch_ctl & SNB_GTT_SIZE_MASK) { | ||
1466 | default: | ||
1467 | case SNB_GTT_SIZE_0M: | ||
1468 | printk(KERN_ERR "Bad GTT size mask: 0x%04x.\n", snb_gmch_ctl); | ||
1469 | *gtt_size = MB(0); | ||
1470 | break; | ||
1471 | case SNB_GTT_SIZE_1M: | ||
1472 | *gtt_size = MB(1); | ||
1473 | break; | ||
1474 | case SNB_GTT_SIZE_2M: | ||
1475 | *gtt_size = MB(2); | ||
1476 | break; | ||
1477 | } | ||
1455 | break; | 1478 | break; |
1456 | default: | 1479 | default: |
1457 | *gtt_offset = *gtt_size = KB(512); | 1480 | *gtt_offset = *gtt_size = KB(512); |