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path: root/drivers/char/drm/i915_drv.c
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Diffstat (limited to 'drivers/char/drm/i915_drv.c')
-rw-r--r--drivers/char/drm/i915_drv.c23
1 files changed, 15 insertions, 8 deletions
diff --git a/drivers/char/drm/i915_drv.c b/drivers/char/drm/i915_drv.c
index bb8f1b2fb38..e8f3d682e3b 100644
--- a/drivers/char/drm/i915_drv.c
+++ b/drivers/char/drm/i915_drv.c
@@ -147,7 +147,7 @@ static void i915_save_vga(struct drm_device *dev)
147 i915_write_indexed(cr_index, cr_data, 0x11, 147 i915_write_indexed(cr_index, cr_data, 0x11,
148 i915_read_indexed(cr_index, cr_data, 0x11) & 148 i915_read_indexed(cr_index, cr_data, 0x11) &
149 (~0x80)); 149 (~0x80));
150 for (i = 0; i < 0x24; i++) 150 for (i = 0; i <= 0x24; i++)
151 dev_priv->saveCR[i] = 151 dev_priv->saveCR[i] =
152 i915_read_indexed(cr_index, cr_data, i); 152 i915_read_indexed(cr_index, cr_data, i);
153 /* Make sure we don't turn off CR group 0 writes */ 153 /* Make sure we don't turn off CR group 0 writes */
@@ -156,7 +156,7 @@ static void i915_save_vga(struct drm_device *dev)
156 /* Attribute controller registers */ 156 /* Attribute controller registers */
157 inb(st01); 157 inb(st01);
158 dev_priv->saveAR_INDEX = inb(VGA_AR_INDEX); 158 dev_priv->saveAR_INDEX = inb(VGA_AR_INDEX);
159 for (i = 0; i < 20; i++) 159 for (i = 0; i <= 0x14; i++)
160 dev_priv->saveAR[i] = i915_read_ar(st01, i, 0); 160 dev_priv->saveAR[i] = i915_read_ar(st01, i, 0);
161 inb(st01); 161 inb(st01);
162 outb(dev_priv->saveAR_INDEX, VGA_AR_INDEX); 162 outb(dev_priv->saveAR_INDEX, VGA_AR_INDEX);
@@ -206,7 +206,7 @@ static void i915_restore_vga(struct drm_device *dev)
206 /* CRT controller regs */ 206 /* CRT controller regs */
207 /* Enable CR group 0 writes */ 207 /* Enable CR group 0 writes */
208 i915_write_indexed(cr_index, cr_data, 0x11, dev_priv->saveCR[0x11]); 208 i915_write_indexed(cr_index, cr_data, 0x11, dev_priv->saveCR[0x11]);
209 for (i = 0; i < 0x24; i++) 209 for (i = 0; i <= 0x24; i++)
210 i915_write_indexed(cr_index, cr_data, i, dev_priv->saveCR[i]); 210 i915_write_indexed(cr_index, cr_data, i, dev_priv->saveCR[i]);
211 211
212 /* Graphics controller regs */ 212 /* Graphics controller regs */
@@ -223,7 +223,7 @@ static void i915_restore_vga(struct drm_device *dev)
223 223
224 /* Attribute controller registers */ 224 /* Attribute controller registers */
225 inb(st01); 225 inb(st01);
226 for (i = 0; i < 20; i++) 226 for (i = 0; i <= 0x14; i++)
227 i915_write_ar(st01, i, dev_priv->saveAR[i], 0); 227 i915_write_ar(st01, i, dev_priv->saveAR[i], 0);
228 inb(st01); /* switch back to index mode */ 228 inb(st01); /* switch back to index mode */
229 outb(dev_priv->saveAR_INDEX | 0x20, VGA_AR_INDEX); 229 outb(dev_priv->saveAR_INDEX | 0x20, VGA_AR_INDEX);
@@ -256,6 +256,9 @@ static int i915_suspend(struct drm_device *dev, pm_message_t state)
256 pci_save_state(dev->pdev); 256 pci_save_state(dev->pdev);
257 pci_read_config_byte(dev->pdev, LBB, &dev_priv->saveLBB); 257 pci_read_config_byte(dev->pdev, LBB, &dev_priv->saveLBB);
258 258
259 /* Display arbitration control */
260 dev_priv->saveDSPARB = I915_READ(DSPARB);
261
259 /* Pipe & plane A info */ 262 /* Pipe & plane A info */
260 dev_priv->savePIPEACONF = I915_READ(PIPEACONF); 263 dev_priv->savePIPEACONF = I915_READ(PIPEACONF);
261 dev_priv->savePIPEASRC = I915_READ(PIPEASRC); 264 dev_priv->savePIPEASRC = I915_READ(PIPEASRC);
@@ -349,6 +352,7 @@ static int i915_suspend(struct drm_device *dev, pm_message_t state)
349 dev_priv->saveVGACNTRL = I915_READ(VGACNTRL); 352 dev_priv->saveVGACNTRL = I915_READ(VGACNTRL);
350 353
351 /* Clock gating state */ 354 /* Clock gating state */
355 dev_priv->saveD_STATE = I915_READ(D_STATE);
352 dev_priv->saveDSPCLK_GATE_D = I915_READ(DSPCLK_GATE_D); 356 dev_priv->saveDSPCLK_GATE_D = I915_READ(DSPCLK_GATE_D);
353 357
354 /* Cache mode state */ 358 /* Cache mode state */
@@ -388,6 +392,8 @@ static int i915_resume(struct drm_device *dev)
388 392
389 pci_write_config_byte(dev->pdev, LBB, dev_priv->saveLBB); 393 pci_write_config_byte(dev->pdev, LBB, dev_priv->saveLBB);
390 394
395 I915_WRITE(DSPARB, dev_priv->saveDSPARB);
396
391 /* Pipe & plane A info */ 397 /* Pipe & plane A info */
392 /* Prime the clock */ 398 /* Prime the clock */
393 if (dev_priv->saveDPLL_A & DPLL_VCO_ENABLE) { 399 if (dev_priv->saveDPLL_A & DPLL_VCO_ENABLE) {
@@ -507,6 +513,7 @@ static int i915_resume(struct drm_device *dev)
507 udelay(150); 513 udelay(150);
508 514
509 /* Clock gating state */ 515 /* Clock gating state */
516 I915_WRITE (D_STATE, dev_priv->saveD_STATE);
510 I915_WRITE (DSPCLK_GATE_D, dev_priv->saveDSPCLK_GATE_D); 517 I915_WRITE (DSPCLK_GATE_D, dev_priv->saveDSPCLK_GATE_D);
511 518
512 /* Cache mode state */ 519 /* Cache mode state */
@@ -533,7 +540,8 @@ static struct drm_driver driver = {
533 */ 540 */
534 .driver_features = 541 .driver_features =
535 DRIVER_USE_AGP | DRIVER_REQUIRE_AGP | /* DRIVER_USE_MTRR |*/ 542 DRIVER_USE_AGP | DRIVER_REQUIRE_AGP | /* DRIVER_USE_MTRR |*/
536 DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED, 543 DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_IRQ_VBL |
544 DRIVER_IRQ_VBL2,
537 .load = i915_driver_load, 545 .load = i915_driver_load,
538 .unload = i915_driver_unload, 546 .unload = i915_driver_unload,
539 .lastclose = i915_driver_lastclose, 547 .lastclose = i915_driver_lastclose,
@@ -541,9 +549,8 @@ static struct drm_driver driver = {
541 .suspend = i915_suspend, 549 .suspend = i915_suspend,
542 .resume = i915_resume, 550 .resume = i915_resume,
543 .device_is_agp = i915_driver_device_is_agp, 551 .device_is_agp = i915_driver_device_is_agp,
544 .get_vblank_counter = i915_get_vblank_counter, 552 .vblank_wait = i915_driver_vblank_wait,
545 .enable_vblank = i915_enable_vblank, 553 .vblank_wait2 = i915_driver_vblank_wait2,
546 .disable_vblank = i915_disable_vblank,
547 .irq_preinstall = i915_driver_irq_preinstall, 554 .irq_preinstall = i915_driver_irq_preinstall,
548 .irq_postinstall = i915_driver_irq_postinstall, 555 .irq_postinstall = i915_driver_irq_postinstall,
549 .irq_uninstall = i915_driver_irq_uninstall, 556 .irq_uninstall = i915_driver_irq_uninstall,