diff options
Diffstat (limited to 'drivers/ata')
-rw-r--r-- | drivers/ata/ata_piix.c | 7 | ||||
-rw-r--r-- | drivers/ata/libata-core.c | 36 | ||||
-rw-r--r-- | drivers/ata/libata-eh.c | 1 | ||||
-rw-r--r-- | drivers/ata/libata-scsi.c | 13 | ||||
-rw-r--r-- | drivers/ata/libata-sff.c | 8 | ||||
-rw-r--r-- | drivers/ata/libata-transport.c | 1 | ||||
-rw-r--r-- | drivers/ata/libata.h | 2 | ||||
-rw-r--r-- | drivers/ata/pata_at91.c | 48 | ||||
-rw-r--r-- | drivers/ata/pata_bf54x.c | 167 | ||||
-rw-r--r-- | drivers/ata/sata_fsl.c | 11 | ||||
-rw-r--r-- | drivers/ata/sata_nv.c | 6 | ||||
-rw-r--r-- | drivers/ata/sata_sil24.c | 2 |
12 files changed, 171 insertions, 131 deletions
diff --git a/drivers/ata/ata_piix.c b/drivers/ata/ata_piix.c index 69ac373c72a..fdf27b9fce4 100644 --- a/drivers/ata/ata_piix.c +++ b/drivers/ata/ata_piix.c | |||
@@ -1117,6 +1117,13 @@ static int piix_broken_suspend(void) | |||
1117 | }, | 1117 | }, |
1118 | }, | 1118 | }, |
1119 | { | 1119 | { |
1120 | .ident = "Satellite Pro A120", | ||
1121 | .matches = { | ||
1122 | DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), | ||
1123 | DMI_MATCH(DMI_PRODUCT_NAME, "Satellite Pro A120"), | ||
1124 | }, | ||
1125 | }, | ||
1126 | { | ||
1120 | .ident = "Portege M500", | 1127 | .ident = "Portege M500", |
1121 | .matches = { | 1128 | .matches = { |
1122 | DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), | 1129 | DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), |
diff --git a/drivers/ata/libata-core.c b/drivers/ata/libata-core.c index 11c9aea4f4f..e0bda9ff89c 100644 --- a/drivers/ata/libata-core.c +++ b/drivers/ata/libata-core.c | |||
@@ -4125,6 +4125,8 @@ static const struct ata_blacklist_entry ata_device_blacklist [] = { | |||
4125 | * device and controller are SATA. | 4125 | * device and controller are SATA. |
4126 | */ | 4126 | */ |
4127 | { "PIONEER DVD-RW DVRTD08", NULL, ATA_HORKAGE_NOSETXFER }, | 4127 | { "PIONEER DVD-RW DVRTD08", NULL, ATA_HORKAGE_NOSETXFER }, |
4128 | { "PIONEER DVD-RW DVRTD08A", NULL, ATA_HORKAGE_NOSETXFER }, | ||
4129 | { "PIONEER DVD-RW DVR-215", NULL, ATA_HORKAGE_NOSETXFER }, | ||
4128 | { "PIONEER DVD-RW DVR-212D", NULL, ATA_HORKAGE_NOSETXFER }, | 4130 | { "PIONEER DVD-RW DVR-212D", NULL, ATA_HORKAGE_NOSETXFER }, |
4129 | { "PIONEER DVD-RW DVR-216D", NULL, ATA_HORKAGE_NOSETXFER }, | 4131 | { "PIONEER DVD-RW DVR-216D", NULL, ATA_HORKAGE_NOSETXFER }, |
4130 | 4132 | ||
@@ -5934,29 +5936,31 @@ void ata_host_init(struct ata_host *host, struct device *dev, | |||
5934 | host->ops = ops; | 5936 | host->ops = ops; |
5935 | } | 5937 | } |
5936 | 5938 | ||
5937 | int ata_port_probe(struct ata_port *ap) | 5939 | void __ata_port_probe(struct ata_port *ap) |
5938 | { | 5940 | { |
5939 | int rc = 0; | 5941 | struct ata_eh_info *ehi = &ap->link.eh_info; |
5942 | unsigned long flags; | ||
5940 | 5943 | ||
5941 | /* probe */ | 5944 | /* kick EH for boot probing */ |
5942 | if (ap->ops->error_handler) { | 5945 | spin_lock_irqsave(ap->lock, flags); |
5943 | struct ata_eh_info *ehi = &ap->link.eh_info; | ||
5944 | unsigned long flags; | ||
5945 | 5946 | ||
5946 | /* kick EH for boot probing */ | 5947 | ehi->probe_mask |= ATA_ALL_DEVICES; |
5947 | spin_lock_irqsave(ap->lock, flags); | 5948 | ehi->action |= ATA_EH_RESET; |
5949 | ehi->flags |= ATA_EHI_NO_AUTOPSY | ATA_EHI_QUIET; | ||
5948 | 5950 | ||
5949 | ehi->probe_mask |= ATA_ALL_DEVICES; | 5951 | ap->pflags &= ~ATA_PFLAG_INITIALIZING; |
5950 | ehi->action |= ATA_EH_RESET; | 5952 | ap->pflags |= ATA_PFLAG_LOADING; |
5951 | ehi->flags |= ATA_EHI_NO_AUTOPSY | ATA_EHI_QUIET; | 5953 | ata_port_schedule_eh(ap); |
5952 | 5954 | ||
5953 | ap->pflags &= ~ATA_PFLAG_INITIALIZING; | 5955 | spin_unlock_irqrestore(ap->lock, flags); |
5954 | ap->pflags |= ATA_PFLAG_LOADING; | 5956 | } |
5955 | ata_port_schedule_eh(ap); | ||
5956 | 5957 | ||
5957 | spin_unlock_irqrestore(ap->lock, flags); | 5958 | int ata_port_probe(struct ata_port *ap) |
5959 | { | ||
5960 | int rc = 0; | ||
5958 | 5961 | ||
5959 | /* wait for EH to finish */ | 5962 | if (ap->ops->error_handler) { |
5963 | __ata_port_probe(ap); | ||
5960 | ata_port_wait_eh(ap); | 5964 | ata_port_wait_eh(ap); |
5961 | } else { | 5965 | } else { |
5962 | DPRINTK("ata%u: bus probe begin\n", ap->print_id); | 5966 | DPRINTK("ata%u: bus probe begin\n", ap->print_id); |
diff --git a/drivers/ata/libata-eh.c b/drivers/ata/libata-eh.c index a9b28203800..c61316e9d2f 100644 --- a/drivers/ata/libata-eh.c +++ b/drivers/ata/libata-eh.c | |||
@@ -863,6 +863,7 @@ void ata_port_wait_eh(struct ata_port *ap) | |||
863 | goto retry; | 863 | goto retry; |
864 | } | 864 | } |
865 | } | 865 | } |
866 | EXPORT_SYMBOL_GPL(ata_port_wait_eh); | ||
866 | 867 | ||
867 | static int ata_eh_nr_in_flight(struct ata_port *ap) | 868 | static int ata_eh_nr_in_flight(struct ata_port *ap) |
868 | { | 869 | { |
diff --git a/drivers/ata/libata-scsi.c b/drivers/ata/libata-scsi.c index 508a60bfe5c..1ee00c8b5b0 100644 --- a/drivers/ata/libata-scsi.c +++ b/drivers/ata/libata-scsi.c | |||
@@ -3838,6 +3838,19 @@ void ata_sas_port_stop(struct ata_port *ap) | |||
3838 | } | 3838 | } |
3839 | EXPORT_SYMBOL_GPL(ata_sas_port_stop); | 3839 | EXPORT_SYMBOL_GPL(ata_sas_port_stop); |
3840 | 3840 | ||
3841 | int ata_sas_async_port_init(struct ata_port *ap) | ||
3842 | { | ||
3843 | int rc = ap->ops->port_start(ap); | ||
3844 | |||
3845 | if (!rc) { | ||
3846 | ap->print_id = ata_print_id++; | ||
3847 | __ata_port_probe(ap); | ||
3848 | } | ||
3849 | |||
3850 | return rc; | ||
3851 | } | ||
3852 | EXPORT_SYMBOL_GPL(ata_sas_async_port_init); | ||
3853 | |||
3841 | /** | 3854 | /** |
3842 | * ata_sas_port_init - Initialize a SATA device | 3855 | * ata_sas_port_init - Initialize a SATA device |
3843 | * @ap: SATA port to initialize | 3856 | * @ap: SATA port to initialize |
diff --git a/drivers/ata/libata-sff.c b/drivers/ata/libata-sff.c index 9691dd0966d..d8af325a6bd 100644 --- a/drivers/ata/libata-sff.c +++ b/drivers/ata/libata-sff.c | |||
@@ -720,13 +720,13 @@ static void ata_pio_sector(struct ata_queued_cmd *qc) | |||
720 | 720 | ||
721 | /* FIXME: use a bounce buffer */ | 721 | /* FIXME: use a bounce buffer */ |
722 | local_irq_save(flags); | 722 | local_irq_save(flags); |
723 | buf = kmap_atomic(page, KM_IRQ0); | 723 | buf = kmap_atomic(page); |
724 | 724 | ||
725 | /* do the actual data transfer */ | 725 | /* do the actual data transfer */ |
726 | ap->ops->sff_data_xfer(qc->dev, buf + offset, qc->sect_size, | 726 | ap->ops->sff_data_xfer(qc->dev, buf + offset, qc->sect_size, |
727 | do_write); | 727 | do_write); |
728 | 728 | ||
729 | kunmap_atomic(buf, KM_IRQ0); | 729 | kunmap_atomic(buf); |
730 | local_irq_restore(flags); | 730 | local_irq_restore(flags); |
731 | } else { | 731 | } else { |
732 | buf = page_address(page); | 732 | buf = page_address(page); |
@@ -865,13 +865,13 @@ next_sg: | |||
865 | 865 | ||
866 | /* FIXME: use bounce buffer */ | 866 | /* FIXME: use bounce buffer */ |
867 | local_irq_save(flags); | 867 | local_irq_save(flags); |
868 | buf = kmap_atomic(page, KM_IRQ0); | 868 | buf = kmap_atomic(page); |
869 | 869 | ||
870 | /* do the actual data transfer */ | 870 | /* do the actual data transfer */ |
871 | consumed = ap->ops->sff_data_xfer(dev, buf + offset, | 871 | consumed = ap->ops->sff_data_xfer(dev, buf + offset, |
872 | count, rw); | 872 | count, rw); |
873 | 873 | ||
874 | kunmap_atomic(buf, KM_IRQ0); | 874 | kunmap_atomic(buf); |
875 | local_irq_restore(flags); | 875 | local_irq_restore(flags); |
876 | } else { | 876 | } else { |
877 | buf = page_address(page); | 877 | buf = page_address(page); |
diff --git a/drivers/ata/libata-transport.c b/drivers/ata/libata-transport.c index 9a7f0ea565d..74aaee30e26 100644 --- a/drivers/ata/libata-transport.c +++ b/drivers/ata/libata-transport.c | |||
@@ -291,6 +291,7 @@ int ata_tport_add(struct device *parent, | |||
291 | goto tport_err; | 291 | goto tport_err; |
292 | } | 292 | } |
293 | 293 | ||
294 | device_enable_async_suspend(dev); | ||
294 | pm_runtime_set_active(dev); | 295 | pm_runtime_set_active(dev); |
295 | pm_runtime_enable(dev); | 296 | pm_runtime_enable(dev); |
296 | 297 | ||
diff --git a/drivers/ata/libata.h b/drivers/ata/libata.h index 814486d35c4..2e26fcaf635 100644 --- a/drivers/ata/libata.h +++ b/drivers/ata/libata.h | |||
@@ -105,6 +105,7 @@ extern int ata_cmd_ioctl(struct scsi_device *scsidev, void __user *arg); | |||
105 | extern struct ata_port *ata_port_alloc(struct ata_host *host); | 105 | extern struct ata_port *ata_port_alloc(struct ata_host *host); |
106 | extern const char *sata_spd_string(unsigned int spd); | 106 | extern const char *sata_spd_string(unsigned int spd); |
107 | extern int ata_port_probe(struct ata_port *ap); | 107 | extern int ata_port_probe(struct ata_port *ap); |
108 | extern void __ata_port_probe(struct ata_port *ap); | ||
108 | 109 | ||
109 | /* libata-acpi.c */ | 110 | /* libata-acpi.c */ |
110 | #ifdef CONFIG_ATA_ACPI | 111 | #ifdef CONFIG_ATA_ACPI |
@@ -151,7 +152,6 @@ extern void ata_eh_acquire(struct ata_port *ap); | |||
151 | extern void ata_eh_release(struct ata_port *ap); | 152 | extern void ata_eh_release(struct ata_port *ap); |
152 | extern enum blk_eh_timer_return ata_scsi_timed_out(struct scsi_cmnd *cmd); | 153 | extern enum blk_eh_timer_return ata_scsi_timed_out(struct scsi_cmnd *cmd); |
153 | extern void ata_scsi_error(struct Scsi_Host *host); | 154 | extern void ata_scsi_error(struct Scsi_Host *host); |
154 | extern void ata_port_wait_eh(struct ata_port *ap); | ||
155 | extern void ata_eh_fastdrain_timerfn(unsigned long arg); | 155 | extern void ata_eh_fastdrain_timerfn(unsigned long arg); |
156 | extern void ata_qc_schedule_eh(struct ata_queued_cmd *qc); | 156 | extern void ata_qc_schedule_eh(struct ata_queued_cmd *qc); |
157 | extern void ata_dev_disable(struct ata_device *dev); | 157 | extern void ata_dev_disable(struct ata_device *dev); |
diff --git a/drivers/ata/pata_at91.c b/drivers/ata/pata_at91.c index a7d91a72ee3..53d3770a0b1 100644 --- a/drivers/ata/pata_at91.c +++ b/drivers/ata/pata_at91.c | |||
@@ -207,11 +207,11 @@ static void set_smc_timing(struct device *dev, struct ata_device *adev, | |||
207 | { | 207 | { |
208 | int ret = 0; | 208 | int ret = 0; |
209 | int use_iordy; | 209 | int use_iordy; |
210 | struct sam9_smc_config smc; | ||
210 | unsigned int t6z; /* data tristate time in ns */ | 211 | unsigned int t6z; /* data tristate time in ns */ |
211 | unsigned int cycle; /* SMC Cycle width in MCK ticks */ | 212 | unsigned int cycle; /* SMC Cycle width in MCK ticks */ |
212 | unsigned int setup; /* SMC Setup width in MCK ticks */ | 213 | unsigned int setup; /* SMC Setup width in MCK ticks */ |
213 | unsigned int pulse; /* CFIOR and CFIOW pulse width in MCK ticks */ | 214 | unsigned int pulse; /* CFIOR and CFIOW pulse width in MCK ticks */ |
214 | unsigned int cs_setup = 0;/* CS4 or CS5 setup width in MCK ticks */ | ||
215 | unsigned int cs_pulse; /* CS4 or CS5 pulse width in MCK ticks*/ | 215 | unsigned int cs_pulse; /* CS4 or CS5 pulse width in MCK ticks*/ |
216 | unsigned int tdf_cycles; /* SMC TDF MCK ticks */ | 216 | unsigned int tdf_cycles; /* SMC TDF MCK ticks */ |
217 | unsigned long mck_hz; /* MCK frequency in Hz */ | 217 | unsigned long mck_hz; /* MCK frequency in Hz */ |
@@ -244,26 +244,20 @@ static void set_smc_timing(struct device *dev, struct ata_device *adev, | |||
244 | } | 244 | } |
245 | 245 | ||
246 | dev_dbg(dev, "Use IORDY=%u, TDF Cycles=%u\n", use_iordy, tdf_cycles); | 246 | dev_dbg(dev, "Use IORDY=%u, TDF Cycles=%u\n", use_iordy, tdf_cycles); |
247 | info->mode |= AT91_SMC_TDF_(tdf_cycles); | 247 | |
248 | 248 | /* SMC Setup Register */ | |
249 | /* write SMC Setup Register */ | 249 | smc.nwe_setup = smc.nrd_setup = setup; |
250 | at91_sys_write(AT91_SMC_SETUP(info->cs), | 250 | smc.ncs_write_setup = smc.ncs_read_setup = 0; |
251 | AT91_SMC_NWESETUP_(setup) | | 251 | /* SMC Pulse Register */ |
252 | AT91_SMC_NRDSETUP_(setup) | | 252 | smc.nwe_pulse = smc.nrd_pulse = pulse; |
253 | AT91_SMC_NCS_WRSETUP_(cs_setup) | | 253 | smc.ncs_write_pulse = smc.ncs_read_pulse = cs_pulse; |
254 | AT91_SMC_NCS_RDSETUP_(cs_setup)); | 254 | /* SMC Cycle Register */ |
255 | /* write SMC Pulse Register */ | 255 | smc.write_cycle = smc.read_cycle = cycle; |
256 | at91_sys_write(AT91_SMC_PULSE(info->cs), | 256 | /* SMC Mode Register*/ |
257 | AT91_SMC_NWEPULSE_(pulse) | | 257 | smc.tdf_cycles = tdf_cycles; |
258 | AT91_SMC_NRDPULSE_(pulse) | | 258 | smc.mode = info->mode; |
259 | AT91_SMC_NCS_WRPULSE_(cs_pulse) | | 259 | |
260 | AT91_SMC_NCS_RDPULSE_(cs_pulse)); | 260 | sam9_smc_configure(0, info->cs, &smc); |
261 | /* write SMC Cycle Register */ | ||
262 | at91_sys_write(AT91_SMC_CYCLE(info->cs), | ||
263 | AT91_SMC_NWECYCLE_(cycle) | | ||
264 | AT91_SMC_NRDCYCLE_(cycle)); | ||
265 | /* write SMC Mode Register*/ | ||
266 | at91_sys_write(AT91_SMC_MODE(info->cs), info->mode); | ||
267 | } | 261 | } |
268 | 262 | ||
269 | static void pata_at91_set_piomode(struct ata_port *ap, struct ata_device *adev) | 263 | static void pata_at91_set_piomode(struct ata_port *ap, struct ata_device *adev) |
@@ -288,20 +282,20 @@ static unsigned int pata_at91_data_xfer_noirq(struct ata_device *dev, | |||
288 | struct at91_ide_info *info = dev->link->ap->host->private_data; | 282 | struct at91_ide_info *info = dev->link->ap->host->private_data; |
289 | unsigned int consumed; | 283 | unsigned int consumed; |
290 | unsigned long flags; | 284 | unsigned long flags; |
291 | unsigned int mode; | 285 | struct sam9_smc_config smc; |
292 | 286 | ||
293 | local_irq_save(flags); | 287 | local_irq_save(flags); |
294 | mode = at91_sys_read(AT91_SMC_MODE(info->cs)); | 288 | sam9_smc_read_mode(0, info->cs, &smc); |
295 | 289 | ||
296 | /* set 16bit mode before writing data */ | 290 | /* set 16bit mode before writing data */ |
297 | at91_sys_write(AT91_SMC_MODE(info->cs), | 291 | smc.mode = (smc.mode & ~AT91_SMC_DBW) | AT91_SMC_DBW_16; |
298 | (mode & ~AT91_SMC_DBW) | AT91_SMC_DBW_16); | 292 | sam9_smc_write_mode(0, info->cs, &smc); |
299 | 293 | ||
300 | consumed = ata_sff_data_xfer(dev, buf, buflen, rw); | 294 | consumed = ata_sff_data_xfer(dev, buf, buflen, rw); |
301 | 295 | ||
302 | /* restore 8bit mode after data is written */ | 296 | /* restore 8bit mode after data is written */ |
303 | at91_sys_write(AT91_SMC_MODE(info->cs), | 297 | smc.mode = (smc.mode & ~AT91_SMC_DBW) | AT91_SMC_DBW_8; |
304 | (mode & ~AT91_SMC_DBW) | AT91_SMC_DBW_8); | 298 | sam9_smc_write_mode(0, info->cs, &smc); |
305 | 299 | ||
306 | local_irq_restore(flags); | 300 | local_irq_restore(flags); |
307 | return consumed; | 301 | return consumed; |
diff --git a/drivers/ata/pata_bf54x.c b/drivers/ata/pata_bf54x.c index d6a4677fdf7..1e65842e2ca 100644 --- a/drivers/ata/pata_bf54x.c +++ b/drivers/ata/pata_bf54x.c | |||
@@ -251,6 +251,8 @@ static const u32 udma_tenvmin = 20; | |||
251 | static const u32 udma_tackmin = 20; | 251 | static const u32 udma_tackmin = 20; |
252 | static const u32 udma_tssmin = 50; | 252 | static const u32 udma_tssmin = 50; |
253 | 253 | ||
254 | #define BFIN_MAX_SG_SEGMENTS 4 | ||
255 | |||
254 | /** | 256 | /** |
255 | * | 257 | * |
256 | * Function: num_clocks_min | 258 | * Function: num_clocks_min |
@@ -829,79 +831,61 @@ static void bfin_set_devctl(struct ata_port *ap, u8 ctl) | |||
829 | 831 | ||
830 | static void bfin_bmdma_setup(struct ata_queued_cmd *qc) | 832 | static void bfin_bmdma_setup(struct ata_queued_cmd *qc) |
831 | { | 833 | { |
832 | unsigned short config = WDSIZE_16; | 834 | struct ata_port *ap = qc->ap; |
835 | struct dma_desc_array *dma_desc_cpu = (struct dma_desc_array *)ap->bmdma_prd; | ||
836 | void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr; | ||
837 | unsigned short config = DMAFLOW_ARRAY | NDSIZE_5 | RESTART | WDSIZE_16 | DMAEN; | ||
833 | struct scatterlist *sg; | 838 | struct scatterlist *sg; |
834 | unsigned int si; | 839 | unsigned int si; |
840 | unsigned int channel; | ||
841 | unsigned int dir; | ||
842 | unsigned int size = 0; | ||
835 | 843 | ||
836 | dev_dbg(qc->ap->dev, "in atapi dma setup\n"); | 844 | dev_dbg(qc->ap->dev, "in atapi dma setup\n"); |
837 | /* Program the ATA_CTRL register with dir */ | 845 | /* Program the ATA_CTRL register with dir */ |
838 | if (qc->tf.flags & ATA_TFLAG_WRITE) { | 846 | if (qc->tf.flags & ATA_TFLAG_WRITE) { |
839 | /* fill the ATAPI DMA controller */ | 847 | channel = CH_ATAPI_TX; |
840 | set_dma_config(CH_ATAPI_TX, config); | 848 | dir = DMA_TO_DEVICE; |
841 | set_dma_x_modify(CH_ATAPI_TX, 2); | ||
842 | for_each_sg(qc->sg, sg, qc->n_elem, si) { | ||
843 | set_dma_start_addr(CH_ATAPI_TX, sg_dma_address(sg)); | ||
844 | set_dma_x_count(CH_ATAPI_TX, sg_dma_len(sg) >> 1); | ||
845 | } | ||
846 | } else { | 849 | } else { |
850 | channel = CH_ATAPI_RX; | ||
851 | dir = DMA_FROM_DEVICE; | ||
847 | config |= WNR; | 852 | config |= WNR; |
848 | /* fill the ATAPI DMA controller */ | ||
849 | set_dma_config(CH_ATAPI_RX, config); | ||
850 | set_dma_x_modify(CH_ATAPI_RX, 2); | ||
851 | for_each_sg(qc->sg, sg, qc->n_elem, si) { | ||
852 | set_dma_start_addr(CH_ATAPI_RX, sg_dma_address(sg)); | ||
853 | set_dma_x_count(CH_ATAPI_RX, sg_dma_len(sg) >> 1); | ||
854 | } | ||
855 | } | 853 | } |
856 | } | ||
857 | 854 | ||
858 | /** | 855 | dma_map_sg(ap->dev, qc->sg, qc->n_elem, dir); |
859 | * bfin_bmdma_start - Start an IDE DMA transaction | ||
860 | * @qc: Info associated with this ATA transaction. | ||
861 | * | ||
862 | * Note: Original code is ata_bmdma_start(). | ||
863 | */ | ||
864 | 856 | ||
865 | static void bfin_bmdma_start(struct ata_queued_cmd *qc) | 857 | /* fill the ATAPI DMA controller */ |
866 | { | 858 | for_each_sg(qc->sg, sg, qc->n_elem, si) { |
867 | struct ata_port *ap = qc->ap; | 859 | dma_desc_cpu[si].start_addr = sg_dma_address(sg); |
868 | void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr; | 860 | dma_desc_cpu[si].cfg = config; |
869 | struct scatterlist *sg; | 861 | dma_desc_cpu[si].x_count = sg_dma_len(sg) >> 1; |
870 | unsigned int si; | 862 | dma_desc_cpu[si].x_modify = 2; |
863 | size += sg_dma_len(sg); | ||
864 | } | ||
871 | 865 | ||
872 | dev_dbg(qc->ap->dev, "in atapi dma start\n"); | 866 | /* Set the last descriptor to stop mode */ |
873 | if (!(ap->udma_mask || ap->mwdma_mask)) | 867 | dma_desc_cpu[qc->n_elem - 1].cfg &= ~(DMAFLOW | NDSIZE); |
874 | return; | ||
875 | 868 | ||
876 | /* start ATAPI DMA controller*/ | 869 | flush_dcache_range((unsigned int)dma_desc_cpu, |
877 | if (qc->tf.flags & ATA_TFLAG_WRITE) { | 870 | (unsigned int)dma_desc_cpu + |
878 | /* | 871 | qc->n_elem * sizeof(struct dma_desc_array)); |
879 | * On blackfin arch, uncacheable memory is not | ||
880 | * allocated with flag GFP_DMA. DMA buffer from | ||
881 | * common kenel code should be flushed if WB | ||
882 | * data cache is enabled. Otherwise, this loop | ||
883 | * is an empty loop and optimized out. | ||
884 | */ | ||
885 | for_each_sg(qc->sg, sg, qc->n_elem, si) { | ||
886 | flush_dcache_range(sg_dma_address(sg), | ||
887 | sg_dma_address(sg) + sg_dma_len(sg)); | ||
888 | } | ||
889 | enable_dma(CH_ATAPI_TX); | ||
890 | dev_dbg(qc->ap->dev, "enable udma write\n"); | ||
891 | 872 | ||
892 | /* Send ATA DMA write command */ | 873 | /* Enable ATA DMA operation*/ |
893 | bfin_exec_command(ap, &qc->tf); | 874 | set_dma_curr_desc_addr(channel, (unsigned long *)ap->bmdma_prd_dma); |
875 | set_dma_x_count(channel, 0); | ||
876 | set_dma_x_modify(channel, 0); | ||
877 | set_dma_config(channel, config); | ||
878 | |||
879 | SSYNC(); | ||
880 | |||
881 | /* Send ATA DMA command */ | ||
882 | bfin_exec_command(ap, &qc->tf); | ||
894 | 883 | ||
884 | if (qc->tf.flags & ATA_TFLAG_WRITE) { | ||
895 | /* set ATA DMA write direction */ | 885 | /* set ATA DMA write direction */ |
896 | ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base) | 886 | ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base) |
897 | | XFER_DIR)); | 887 | | XFER_DIR)); |
898 | } else { | 888 | } else { |
899 | enable_dma(CH_ATAPI_RX); | ||
900 | dev_dbg(qc->ap->dev, "enable udma read\n"); | ||
901 | |||
902 | /* Send ATA DMA read command */ | ||
903 | bfin_exec_command(ap, &qc->tf); | ||
904 | |||
905 | /* set ATA DMA read direction */ | 889 | /* set ATA DMA read direction */ |
906 | ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base) | 890 | ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base) |
907 | & ~XFER_DIR)); | 891 | & ~XFER_DIR)); |
@@ -913,12 +897,28 @@ static void bfin_bmdma_start(struct ata_queued_cmd *qc) | |||
913 | /* Set ATAPI state machine contorl in terminate sequence */ | 897 | /* Set ATAPI state machine contorl in terminate sequence */ |
914 | ATAPI_SET_CONTROL(base, ATAPI_GET_CONTROL(base) | END_ON_TERM); | 898 | ATAPI_SET_CONTROL(base, ATAPI_GET_CONTROL(base) | END_ON_TERM); |
915 | 899 | ||
916 | /* Set transfer length to buffer len */ | 900 | /* Set transfer length to the total size of sg buffers */ |
917 | for_each_sg(qc->sg, sg, qc->n_elem, si) { | 901 | ATAPI_SET_XFER_LEN(base, size >> 1); |
918 | ATAPI_SET_XFER_LEN(base, (sg_dma_len(sg) >> 1)); | 902 | } |
919 | } | ||
920 | 903 | ||
921 | /* Enable ATA DMA operation*/ | 904 | /** |
905 | * bfin_bmdma_start - Start an IDE DMA transaction | ||
906 | * @qc: Info associated with this ATA transaction. | ||
907 | * | ||
908 | * Note: Original code is ata_bmdma_start(). | ||
909 | */ | ||
910 | |||
911 | static void bfin_bmdma_start(struct ata_queued_cmd *qc) | ||
912 | { | ||
913 | struct ata_port *ap = qc->ap; | ||
914 | void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr; | ||
915 | |||
916 | dev_dbg(qc->ap->dev, "in atapi dma start\n"); | ||
917 | |||
918 | if (!(ap->udma_mask || ap->mwdma_mask)) | ||
919 | return; | ||
920 | |||
921 | /* start ATAPI transfer*/ | ||
922 | if (ap->udma_mask) | 922 | if (ap->udma_mask) |
923 | ATAPI_SET_CONTROL(base, ATAPI_GET_CONTROL(base) | 923 | ATAPI_SET_CONTROL(base, ATAPI_GET_CONTROL(base) |
924 | | ULTRA_START); | 924 | | ULTRA_START); |
@@ -935,34 +935,23 @@ static void bfin_bmdma_start(struct ata_queued_cmd *qc) | |||
935 | static void bfin_bmdma_stop(struct ata_queued_cmd *qc) | 935 | static void bfin_bmdma_stop(struct ata_queued_cmd *qc) |
936 | { | 936 | { |
937 | struct ata_port *ap = qc->ap; | 937 | struct ata_port *ap = qc->ap; |
938 | struct scatterlist *sg; | 938 | unsigned int dir; |
939 | unsigned int si; | ||
940 | 939 | ||
941 | dev_dbg(qc->ap->dev, "in atapi dma stop\n"); | 940 | dev_dbg(qc->ap->dev, "in atapi dma stop\n"); |
941 | |||
942 | if (!(ap->udma_mask || ap->mwdma_mask)) | 942 | if (!(ap->udma_mask || ap->mwdma_mask)) |
943 | return; | 943 | return; |
944 | 944 | ||
945 | /* stop ATAPI DMA controller*/ | 945 | /* stop ATAPI DMA controller*/ |
946 | if (qc->tf.flags & ATA_TFLAG_WRITE) | 946 | if (qc->tf.flags & ATA_TFLAG_WRITE) { |
947 | dir = DMA_TO_DEVICE; | ||
947 | disable_dma(CH_ATAPI_TX); | 948 | disable_dma(CH_ATAPI_TX); |
948 | else { | 949 | } else { |
950 | dir = DMA_FROM_DEVICE; | ||
949 | disable_dma(CH_ATAPI_RX); | 951 | disable_dma(CH_ATAPI_RX); |
950 | if (ap->hsm_task_state & HSM_ST_LAST) { | ||
951 | /* | ||
952 | * On blackfin arch, uncacheable memory is not | ||
953 | * allocated with flag GFP_DMA. DMA buffer from | ||
954 | * common kenel code should be invalidated if | ||
955 | * data cache is enabled. Otherwise, this loop | ||
956 | * is an empty loop and optimized out. | ||
957 | */ | ||
958 | for_each_sg(qc->sg, sg, qc->n_elem, si) { | ||
959 | invalidate_dcache_range( | ||
960 | sg_dma_address(sg), | ||
961 | sg_dma_address(sg) | ||
962 | + sg_dma_len(sg)); | ||
963 | } | ||
964 | } | ||
965 | } | 952 | } |
953 | |||
954 | dma_unmap_sg(ap->dev, qc->sg, qc->n_elem, dir); | ||
966 | } | 955 | } |
967 | 956 | ||
968 | /** | 957 | /** |
@@ -1260,6 +1249,11 @@ static void bfin_port_stop(struct ata_port *ap) | |||
1260 | { | 1249 | { |
1261 | dev_dbg(ap->dev, "in atapi port stop\n"); | 1250 | dev_dbg(ap->dev, "in atapi port stop\n"); |
1262 | if (ap->udma_mask != 0 || ap->mwdma_mask != 0) { | 1251 | if (ap->udma_mask != 0 || ap->mwdma_mask != 0) { |
1252 | dma_free_coherent(ap->dev, | ||
1253 | BFIN_MAX_SG_SEGMENTS * sizeof(struct dma_desc_array), | ||
1254 | ap->bmdma_prd, | ||
1255 | ap->bmdma_prd_dma); | ||
1256 | |||
1263 | free_dma(CH_ATAPI_RX); | 1257 | free_dma(CH_ATAPI_RX); |
1264 | free_dma(CH_ATAPI_TX); | 1258 | free_dma(CH_ATAPI_TX); |
1265 | } | 1259 | } |
@@ -1271,14 +1265,29 @@ static int bfin_port_start(struct ata_port *ap) | |||
1271 | if (!(ap->udma_mask || ap->mwdma_mask)) | 1265 | if (!(ap->udma_mask || ap->mwdma_mask)) |
1272 | return 0; | 1266 | return 0; |
1273 | 1267 | ||
1268 | ap->bmdma_prd = dma_alloc_coherent(ap->dev, | ||
1269 | BFIN_MAX_SG_SEGMENTS * sizeof(struct dma_desc_array), | ||
1270 | &ap->bmdma_prd_dma, | ||
1271 | GFP_KERNEL); | ||
1272 | |||
1273 | if (ap->bmdma_prd == NULL) { | ||
1274 | dev_info(ap->dev, "Unable to allocate DMA descriptor array.\n"); | ||
1275 | goto out; | ||
1276 | } | ||
1277 | |||
1274 | if (request_dma(CH_ATAPI_RX, "BFIN ATAPI RX DMA") >= 0) { | 1278 | if (request_dma(CH_ATAPI_RX, "BFIN ATAPI RX DMA") >= 0) { |
1275 | if (request_dma(CH_ATAPI_TX, | 1279 | if (request_dma(CH_ATAPI_TX, |
1276 | "BFIN ATAPI TX DMA") >= 0) | 1280 | "BFIN ATAPI TX DMA") >= 0) |
1277 | return 0; | 1281 | return 0; |
1278 | 1282 | ||
1279 | free_dma(CH_ATAPI_RX); | 1283 | free_dma(CH_ATAPI_RX); |
1284 | dma_free_coherent(ap->dev, | ||
1285 | BFIN_MAX_SG_SEGMENTS * sizeof(struct dma_desc_array), | ||
1286 | ap->bmdma_prd, | ||
1287 | ap->bmdma_prd_dma); | ||
1280 | } | 1288 | } |
1281 | 1289 | ||
1290 | out: | ||
1282 | ap->udma_mask = 0; | 1291 | ap->udma_mask = 0; |
1283 | ap->mwdma_mask = 0; | 1292 | ap->mwdma_mask = 0; |
1284 | dev_err(ap->dev, "Unable to request ATAPI DMA!" | 1293 | dev_err(ap->dev, "Unable to request ATAPI DMA!" |
@@ -1400,7 +1409,7 @@ static irqreturn_t bfin_ata_interrupt(int irq, void *dev_instance) | |||
1400 | 1409 | ||
1401 | static struct scsi_host_template bfin_sht = { | 1410 | static struct scsi_host_template bfin_sht = { |
1402 | ATA_BASE_SHT(DRV_NAME), | 1411 | ATA_BASE_SHT(DRV_NAME), |
1403 | .sg_tablesize = SG_NONE, | 1412 | .sg_tablesize = BFIN_MAX_SG_SEGMENTS, |
1404 | .dma_boundary = ATA_DMA_BOUNDARY, | 1413 | .dma_boundary = ATA_DMA_BOUNDARY, |
1405 | }; | 1414 | }; |
1406 | 1415 | ||
diff --git a/drivers/ata/sata_fsl.c b/drivers/ata/sata_fsl.c index 5a2c95ba050..0120b0d1e9a 100644 --- a/drivers/ata/sata_fsl.c +++ b/drivers/ata/sata_fsl.c | |||
@@ -140,6 +140,7 @@ enum { | |||
140 | */ | 140 | */ |
141 | HCONTROL_ONLINE_PHY_RST = (1 << 31), | 141 | HCONTROL_ONLINE_PHY_RST = (1 << 31), |
142 | HCONTROL_FORCE_OFFLINE = (1 << 30), | 142 | HCONTROL_FORCE_OFFLINE = (1 << 30), |
143 | HCONTROL_LEGACY = (1 << 28), | ||
143 | HCONTROL_PARITY_PROT_MOD = (1 << 14), | 144 | HCONTROL_PARITY_PROT_MOD = (1 << 14), |
144 | HCONTROL_DPATH_PARITY = (1 << 12), | 145 | HCONTROL_DPATH_PARITY = (1 << 12), |
145 | HCONTROL_SNOOP_ENABLE = (1 << 10), | 146 | HCONTROL_SNOOP_ENABLE = (1 << 10), |
@@ -1223,6 +1224,10 @@ static int sata_fsl_init_controller(struct ata_host *host) | |||
1223 | * part of the port_start() callback | 1224 | * part of the port_start() callback |
1224 | */ | 1225 | */ |
1225 | 1226 | ||
1227 | /* sata controller to operate in enterprise mode */ | ||
1228 | temp = ioread32(hcr_base + HCONTROL); | ||
1229 | iowrite32(temp & ~HCONTROL_LEGACY, hcr_base + HCONTROL); | ||
1230 | |||
1226 | /* ack. any pending IRQs for this controller/port */ | 1231 | /* ack. any pending IRQs for this controller/port */ |
1227 | temp = ioread32(hcr_base + HSTATUS); | 1232 | temp = ioread32(hcr_base + HSTATUS); |
1228 | if (temp & 0x3F) | 1233 | if (temp & 0x3F) |
@@ -1421,6 +1426,12 @@ static int sata_fsl_resume(struct platform_device *op) | |||
1421 | /* Recovery the CHBA register in host controller cmd register set */ | 1426 | /* Recovery the CHBA register in host controller cmd register set */ |
1422 | iowrite32(pp->cmdslot_paddr & 0xffffffff, hcr_base + CHBA); | 1427 | iowrite32(pp->cmdslot_paddr & 0xffffffff, hcr_base + CHBA); |
1423 | 1428 | ||
1429 | iowrite32((ioread32(hcr_base + HCONTROL) | ||
1430 | | HCONTROL_ONLINE_PHY_RST | ||
1431 | | HCONTROL_SNOOP_ENABLE | ||
1432 | | HCONTROL_PMP_ATTACHED), | ||
1433 | hcr_base + HCONTROL); | ||
1434 | |||
1424 | ata_host_resume(host); | 1435 | ata_host_resume(host); |
1425 | return 0; | 1436 | return 0; |
1426 | } | 1437 | } |
diff --git a/drivers/ata/sata_nv.c b/drivers/ata/sata_nv.c index e0bc9646a38..55d6179dde5 100644 --- a/drivers/ata/sata_nv.c +++ b/drivers/ata/sata_nv.c | |||
@@ -599,9 +599,9 @@ MODULE_LICENSE("GPL"); | |||
599 | MODULE_DEVICE_TABLE(pci, nv_pci_tbl); | 599 | MODULE_DEVICE_TABLE(pci, nv_pci_tbl); |
600 | MODULE_VERSION(DRV_VERSION); | 600 | MODULE_VERSION(DRV_VERSION); |
601 | 601 | ||
602 | static int adma_enabled; | 602 | static bool adma_enabled; |
603 | static int swncq_enabled = 1; | 603 | static bool swncq_enabled = 1; |
604 | static int msi_enabled; | 604 | static bool msi_enabled; |
605 | 605 | ||
606 | static void nv_adma_register_mode(struct ata_port *ap) | 606 | static void nv_adma_register_mode(struct ata_port *ap) |
607 | { | 607 | { |
diff --git a/drivers/ata/sata_sil24.c b/drivers/ata/sata_sil24.c index 1e9140626a8..e7e610aa9a7 100644 --- a/drivers/ata/sata_sil24.c +++ b/drivers/ata/sata_sil24.c | |||
@@ -417,7 +417,7 @@ static struct ata_port_operations sil24_ops = { | |||
417 | #endif | 417 | #endif |
418 | }; | 418 | }; |
419 | 419 | ||
420 | static int sata_sil24_msi; /* Disable MSI */ | 420 | static bool sata_sil24_msi; /* Disable MSI */ |
421 | module_param_named(msi, sata_sil24_msi, bool, S_IRUGO); | 421 | module_param_named(msi, sata_sil24_msi, bool, S_IRUGO); |
422 | MODULE_PARM_DESC(msi, "Enable MSI (Default: false)"); | 422 | MODULE_PARM_DESC(msi, "Enable MSI (Default: false)"); |
423 | 423 | ||