1654 files changed, 37314 insertions, 39094 deletions

diff --git a/arch/Kconfig b/arch/Kconfig
index 5b448a74d0f..a6f14f622d1 100644
--- a/arch/Kconfig
+++ b/arch/Kconfig
@@ -120,6 +120,9 @@ config HAVE_KRETPROBES
 
 config HAVE_OPTPROBES
         bool
+
+config HAVE_NMI_WATCHDOG
+        bool
 #
 # An arch should select this if it provides all these things:
 #
diff --git a/arch/alpha/include/asm/mman.h b/arch/alpha/include/asm/mman.h
index 72db984f878..cbeb3616a28 100644
--- a/arch/alpha/include/asm/mman.h
+++ b/arch/alpha/include/asm/mman.h
@@ -56,6 +56,10 @@
 #define MADV_HUGEPAGE   14              /* Worth backing with hugepages */
 #define MADV_NOHUGEPAGE 15              /* Not worth backing with hugepages */
 
+#define MADV_DONTDUMP   16              /* Explicity exclude from the core dump,
+                                           overrides the coredump filter bits */
+#define MADV_DODUMP     17              /* Clear the MADV_NODUMP flag */
+
 /* compatibility flags */
 #define MAP_FILE        0
 
diff --git a/arch/alpha/include/asm/pci.h b/arch/alpha/include/asm/pci.h
index 28d0497fd3c..d01afb78919 100644
--- a/arch/alpha/include/asm/pci.h
+++ b/arch/alpha/include/asm/pci.h
@@ -7,6 +7,7 @@
 #include <linux/dma-mapping.h>
 #include <asm/scatterlist.h>
 #include <asm/machvec.h>
+#include <asm-generic/pci-bridge.h>
 
 /*
  * The following structure is used to manage multiple PCI busses.
@@ -99,12 +100,6 @@ static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel)
         return channel ? 15 : 14;
 }
 
-extern void pcibios_resource_to_bus(struct pci_dev *, struct pci_bus_region *,
-                                    struct resource *);
-
-extern void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
-                                    struct pci_bus_region *region);
-
 #define pci_domain_nr(bus) ((struct pci_controller *)(bus)->sysdata)->index
 
 static inline int pci_proc_domain(struct pci_bus *bus)
diff --git a/arch/alpha/kernel/binfmt_loader.c b/arch/alpha/kernel/binfmt_loader.c
index 3fcfad41013..d1f474d1d44 100644
--- a/arch/alpha/kernel/binfmt_loader.c
+++ b/arch/alpha/kernel/binfmt_loader.c
@@ -46,6 +46,7 @@ static struct linux_binfmt loader_format = {
 
 static int __init init_loader_binfmt(void)
 {
-        return insert_binfmt(&loader_format);
+        insert_binfmt(&loader_format);
+        return 0;
 }
 arch_initcall(init_loader_binfmt);
diff --git a/arch/alpha/kernel/pci.c b/arch/alpha/kernel/pci.c
index 8c723c1b086..1a629636cc1 100644
--- a/arch/alpha/kernel/pci.c
+++ b/arch/alpha/kernel/pci.c
@@ -43,12 +43,10 @@ const char *const pci_mem_names[] = {
 
 const char pci_hae0_name[] = "HAE0";
 
-/* Indicate whether we respect the PCI setup left by console. */
 /*
- * Make this long-lived  so that we know when shutting down
- * whether we probed only or not.
+ * If PCI_PROBE_ONLY in pci_flags is set, we don't change any PCI resource
+ * assignments.
  */
-int pci_probe_only;
 
 /*
  * The PCI controller list.
@@ -215,7 +213,7 @@ pdev_save_srm_config(struct pci_dev *dev)
         struct pdev_srm_saved_conf *tmp;
         static int printed = 0;
 
-        if (!alpha_using_srm || pci_probe_only)
+        if (!alpha_using_srm || pci_has_flag(PCI_PROBE_ONLY))
                 return;
 
         if (!printed) {
@@ -242,7 +240,7 @@ pci_restore_srm_config(void)
         struct pdev_srm_saved_conf *tmp;
 
         /* No need to restore if probed only. */
-        if (pci_probe_only)
+        if (pci_has_flag(PCI_PROBE_ONLY))
                 return;
 
         /* Restore SRM config. */
@@ -253,46 +251,17 @@ pci_restore_srm_config(void)
 #endif
 
 void __devinit
-pcibios_fixup_resource(struct resource *res, struct resource *root)
-{
-        res->start += root->start;
-        res->end += root->start;
-}
-
-void __devinit
-pcibios_fixup_device_resources(struct pci_dev *dev, struct pci_bus *bus)
-{
-        /* Update device resources.  */
-        struct pci_controller *hose = (struct pci_controller *)bus->sysdata;
-        int i;
-
-        for (i = 0; i < PCI_NUM_RESOURCES; i++) {
-                if (!dev->resource[i].start)
-                        continue;
-                if (dev->resource[i].flags & IORESOURCE_IO)
-                        pcibios_fixup_resource(&dev->resource[i],
-                                               hose->io_space);
-                else if (dev->resource[i].flags & IORESOURCE_MEM)
-                        pcibios_fixup_resource(&dev->resource[i],
-                                               hose->mem_space);
-        }
-}
-
-void __devinit
 pcibios_fixup_bus(struct pci_bus *bus)
 {
         struct pci_dev *dev = bus->self;
 
-        if (pci_probe_only && dev &&
+        if (pci_has_flag(PCI_PROBE_ONLY) && dev &&
                    (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
                 pci_read_bridge_bases(bus);
-                pcibios_fixup_device_resources(dev, bus);
         } 
 
         list_for_each_entry(dev, &bus->devices, bus_list) {
                 pdev_save_srm_config(dev);
-                if ((dev->class >> 8) != PCI_CLASS_BRIDGE_PCI)
-                        pcibios_fixup_device_resources(dev, bus);
         }
 }
 
@@ -302,42 +271,6 @@ pcibios_update_irq(struct pci_dev *dev, int irq)
         pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
 }
 
-void
-pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
-                         struct resource *res)
-{
-        struct pci_controller *hose = (struct pci_controller *)dev->sysdata;
-        unsigned long offset = 0;
-
-        if (res->flags & IORESOURCE_IO)
-                offset = hose->io_space->start;
-        else if (res->flags & IORESOURCE_MEM)
-                offset = hose->mem_space->start;
-
-        region->start = res->start - offset;
-        region->end = res->end - offset;
-}
-
-void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
-                             struct pci_bus_region *region)
-{
-        struct pci_controller *hose = (struct pci_controller *)dev->sysdata;
-        unsigned long offset = 0;
-
-        if (res->flags & IORESOURCE_IO)
-                offset = hose->io_space->start;
-        else if (res->flags & IORESOURCE_MEM)
-                offset = hose->mem_space->start;
-
-        res->start = region->start + offset;
-        res->end = region->end + offset;
-}
-
-#ifdef CONFIG_HOTPLUG
-EXPORT_SYMBOL(pcibios_resource_to_bus);
-EXPORT_SYMBOL(pcibios_bus_to_resource);
-#endif
-
 int
 pcibios_enable_device(struct pci_dev *dev, int mask)
 {
@@ -374,7 +307,8 @@ pcibios_claim_one_bus(struct pci_bus *b)
 
                         if (r->parent || !r->start || !r->flags)
                                 continue;
-                        if (pci_probe_only || (r->flags & IORESOURCE_PCI_FIXED))
+                        if (pci_has_flag(PCI_PROBE_ONLY) ||
+                            (r->flags & IORESOURCE_PCI_FIXED))
                                 pci_claim_resource(dev, i);
                 }
         }
@@ -416,8 +350,10 @@ common_init_pci(void)
                         hose->mem_space->end = end;
 
                 INIT_LIST_HEAD(&resources);
-                pci_add_resource(&resources, hose->io_space);
-                pci_add_resource(&resources, hose->mem_space);
+                pci_add_resource_offset(&resources, hose->io_space,
+                                        hose->io_space->start);
+                pci_add_resource_offset(&resources, hose->mem_space,
+                                        hose->mem_space->start);
 
                 bus = pci_scan_root_bus(NULL, next_busno, alpha_mv.pci_ops,
                                         hose, &resources);
diff --git a/arch/alpha/kernel/pci_impl.h b/arch/alpha/kernel/pci_impl.h
index 85457b2d451..2b0ac429f5e 100644
--- a/arch/alpha/kernel/pci_impl.h
+++ b/arch/alpha/kernel/pci_impl.h
@@ -173,9 +173,6 @@ extern void pci_restore_srm_config(void);
 extern struct pci_controller *hose_head, **hose_tail;
 extern struct pci_controller *pci_isa_hose;
 
-/* Indicate that we trust the console to configure things properly.  */
-extern int pci_probe_only;
-
 extern unsigned long alpha_agpgart_size;
 
 extern void common_init_pci(void);
diff --git a/arch/alpha/kernel/sys_marvel.c b/arch/alpha/kernel/sys_marvel.c
index 95cfc83ece8..fc8b1250861 100644
--- a/arch/alpha/kernel/sys_marvel.c
+++ b/arch/alpha/kernel/sys_marvel.c
@@ -384,7 +384,8 @@ marvel_init_pci(void)
 
         marvel_register_error_handlers();
 
-        pci_probe_only = 1;
+        /* Indicate that we trust the console to configure things properly */
+        pci_set_flags(PCI_PROBE_ONLY);
         common_init_pci();
         locate_and_init_vga(NULL);
 
diff --git a/arch/alpha/kernel/sys_titan.c b/arch/alpha/kernel/sys_titan.c
index f47b30a2a11..b8eafa05353 100644
--- a/arch/alpha/kernel/sys_titan.c
+++ b/arch/alpha/kernel/sys_titan.c
@@ -331,7 +331,8 @@ titan_init_pci(void)
          */
         titan_late_init();
  
-        pci_probe_only = 1;
+        /* Indicate that we trust the console to configure things properly */
+        pci_set_flags(PCI_PROBE_ONLY);
         common_init_pci();
         SMC669_Init(0);
         locate_and_init_vga(NULL);
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index dfb0312f4e7..94422601ea5 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -186,6 +186,9 @@ config GENERIC_ISA_DMA
 config FIQ
         bool
 
+config NEED_RET_TO_USER
+        bool
+
 config ARCH_MTD_XIP
         bool
 
@@ -322,9 +325,10 @@ config ARCH_AT91
         select ARCH_REQUIRE_GPIOLIB
         select HAVE_CLK
         select CLKDEV_LOOKUP
+        select IRQ_DOMAIN
         help
           This enables support for systems based on the Atmel AT91RM9200,
-          AT91SAM9 and AT91CAP9 processors.
+          AT91SAM9 processors.
 
 config ARCH_BCMRING
         bool "Broadcom BCMRING"
@@ -479,6 +483,7 @@ config ARCH_IOP13XX
         select ARCH_SUPPORTS_MSI
         select VMSPLIT_1G
         select NEED_MACH_MEMORY_H
+        select NEED_RET_TO_USER
         help
           Support for Intel's IOP13XX (XScale) family of processors.
 
@@ -486,6 +491,7 @@ config ARCH_IOP32X
         bool "IOP32x-based"
         depends on MMU
         select CPU_XSCALE
+        select NEED_RET_TO_USER
         select PLAT_IOP
         select PCI
         select ARCH_REQUIRE_GPIOLIB
@@ -497,6 +503,7 @@ config ARCH_IOP33X
         bool "IOP33x-based"
         depends on MMU
         select CPU_XSCALE
+        select NEED_RET_TO_USER
         select PLAT_IOP
         select PCI
         select ARCH_REQUIRE_GPIOLIB
@@ -754,7 +761,7 @@ config ARCH_SA1100
         select ARCH_HAS_CPUFREQ
         select CPU_FREQ
         select GENERIC_CLOCKEVENTS
-        select HAVE_CLK
+        select CLKDEV_LOOKUP
         select HAVE_SCHED_CLOCK
         select TICK_ONESHOT
         select ARCH_REQUIRE_GPIOLIB
@@ -763,22 +770,21 @@ config ARCH_SA1100
         help
           Support for StrongARM 11x0 based boards.
 
-config ARCH_S3C2410
-        bool "Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443, S3C2450"
+config ARCH_S3C24XX
+        bool "Samsung S3C24XX SoCs"
         select GENERIC_GPIO
         select ARCH_HAS_CPUFREQ
         select HAVE_CLK
         select CLKDEV_LOOKUP
         select ARCH_USES_GETTIMEOFFSET
         select HAVE_S3C2410_I2C if I2C
+        select HAVE_S3C_RTC if RTC_CLASS
+        select HAVE_S3C2410_WATCHDOG if WATCHDOG
         help
-          Samsung S3C2410X CPU based systems, such as the Simtec Electronics
-          BAST (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or
-          the Samsung SMDK2410 development board (and derivatives).
-
-          Note, the S3C2416 and the S3C2450 are so close that they even share
-          the same SoC ID code. This means that there is no separate machine
-          directory (no arch/arm/mach-s3c2450) as the S3C2416 was first.
+          Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
+          and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
+          (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
+          Samsung SMDK2410 development board (and derivatives).
 
 config ARCH_S3C64XX
         bool "Samsung S3C64XX"
@@ -901,6 +907,7 @@ config ARCH_U300
 
 config ARCH_U8500
         bool "ST-Ericsson U8500 Series"
+        depends on MMU
         select CPU_V7
         select ARM_AMBA
         select GENERIC_CLOCKEVENTS
@@ -1066,12 +1073,10 @@ source "arch/arm/plat-s5p/Kconfig"
 
 source "arch/arm/plat-spear/Kconfig"
 
-if ARCH_S3C2410
-source "arch/arm/mach-s3c2410/Kconfig"
+source "arch/arm/mach-s3c24xx/Kconfig"
+if ARCH_S3C24XX
 source "arch/arm/mach-s3c2412/Kconfig"
-source "arch/arm/mach-s3c2416/Kconfig"
 source "arch/arm/mach-s3c2440/Kconfig"
-source "arch/arm/mach-s3c2443/Kconfig"
 endif
 
 if ARCH_S3C64XX
@@ -1127,6 +1132,7 @@ config PLAT_VERSATILE
 config ARM_TIMER_SP804
         bool
         select CLKSRC_MMIO
+        select HAVE_SCHED_CLOCK
 
 source arch/arm/mm/Kconfig
 
@@ -1577,7 +1583,8 @@ config LOCAL_TIMERS
 config ARCH_NR_GPIO
         int
         default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
-        default 350 if ARCH_U8500
+        default 355 if ARCH_U8500
+        default 264 if MACH_H4700
         default 0
         help
           Maximum number of GPIOs in the system.
@@ -1588,7 +1595,7 @@ source kernel/Kconfig.preempt
 
 config HZ
         int
-        default 200 if ARCH_EBSA110 || ARCH_S3C2410 || ARCH_S5P64X0 || \
+        default 200 if ARCH_EBSA110 || ARCH_S3C24XX || ARCH_S5P64X0 || \
                 ARCH_S5PV210 || ARCH_EXYNOS4
         default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER
         default AT91_TIMER_HZ if ARCH_AT91
@@ -2114,7 +2121,7 @@ config CPU_FREQ_S3C
 
 config CPU_FREQ_S3C24XX
         bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)"
-        depends on ARCH_S3C2410 && CPU_FREQ && EXPERIMENTAL
+        depends on ARCH_S3C24XX && CPU_FREQ && EXPERIMENTAL
         select CPU_FREQ_S3C
         help
           This enables the CPUfreq driver for the Samsung S3C24XX family
diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
index e0d236d7ff7..66ca8014ff3 100644
--- a/arch/arm/Kconfig.debug
+++ b/arch/arm/Kconfig.debug
@@ -81,47 +81,14 @@ choice
         prompt "Kernel low-level debugging port"
         depends on DEBUG_LL
 
-        config DEBUG_LL_UART_NONE
-                bool "No low-level debugging UART"
-                help
-                  Say Y here if your platform doesn't provide a UART option
-                  below. This relies on your platform choosing the right UART
-                  definition internally in order for low-level debugging to
-                  work.
-
-        config DEBUG_ICEDCC
-                bool "Kernel low-level debugging via EmbeddedICE DCC channel"
-                help
-                  Say Y here if you want the debug print routines to direct
-                  their output to the EmbeddedICE macrocell's DCC channel using
-                  co-processor 14. This is known to work on the ARM9 style ICE
-                  channel and on the XScale with the PEEDI.
-
-                  Note that the system will appear to hang during boot if there
-                  is nothing connected to read from the DCC.
-
         config AT91_DEBUG_LL_DBGU0
                 bool "Kernel low-level debugging on rm9200, 9260/9g20, 9261/9g10 and 9rl"
                 depends on HAVE_AT91_DBGU0
 
         config AT91_DEBUG_LL_DBGU1
-                bool "Kernel low-level debugging on 9263, 9g45 and cap9"
+                bool "Kernel low-level debugging on 9263 and 9g45"
                 depends on HAVE_AT91_DBGU1
 
-        config DEBUG_FOOTBRIDGE_COM1
-                bool "Kernel low-level debugging messages via footbridge 8250 at PCI COM1"
-                depends on FOOTBRIDGE
-                help
-                  Say Y here if you want the debug print routines to direct
-                  their output to the 8250 at PCI COM1.
-
-        config DEBUG_DC21285_PORT
-                bool "Kernel low-level debugging messages via footbridge serial port"
-                depends on FOOTBRIDGE
-                help
-                  Say Y here if you want the debug print routines to direct
-                  their output to the serial port in the DC21285 (Footbridge).
-
         config DEBUG_CLPS711X_UART1
                 bool "Kernel low-level debugging messages via UART1"
                 depends on ARCH_CLPS711X
@@ -136,6 +103,20 @@ choice
                   Say Y here if you want the debug print routines to direct
                   their output to the second serial port on these devices.
 
+        config DEBUG_DC21285_PORT
+                bool "Kernel low-level debugging messages via footbridge serial port"
+                depends on FOOTBRIDGE
+                help
+                  Say Y here if you want the debug print routines to direct
+                  their output to the serial port in the DC21285 (Footbridge).
+
+        config DEBUG_FOOTBRIDGE_COM1
+                bool "Kernel low-level debugging messages via footbridge 8250 at PCI COM1"
+                depends on FOOTBRIDGE
+                help
+                  Say Y here if you want the debug print routines to direct
+                  their output to the 8250 at PCI COM1.
+
         config DEBUG_HIGHBANK_UART
                 bool "Kernel low-level debugging messages via Highbank UART"
                 depends on ARCH_HIGHBANK
@@ -199,45 +180,49 @@ choice
                   Say Y here if you want kernel low-level debugging support
                   on i.MX50 or i.MX53.
 
-        config DEBUG_IMX6Q_UART
-                bool "i.MX6Q Debug UART"
+        config DEBUG_IMX6Q_UART4
+                bool "i.MX6Q Debug UART4"
                 depends on SOC_IMX6Q
                 help
                   Say Y here if you want kernel low-level debugging support
-                  on i.MX6Q.
+                  on i.MX6Q UART4.
 
-        config DEBUG_S3C_UART0
-                depends on PLAT_SAMSUNG
-                bool "Use S3C UART 0 for low-level debug"
+        config DEBUG_MSM_UART1
+                bool "Kernel low-level debugging messages via MSM UART1"
+                depends on ARCH_MSM7X00A || ARCH_MSM7X30 || ARCH_QSD8X50
                 help
                   Say Y here if you want the debug print routines to direct
-                  their output to UART 0. The port must have been initialised
-                  by the boot-loader before use.
-
-                  The uncompressor code port configuration is now handled
-                  by CONFIG_S3C_LOWLEVEL_UART_PORT.
+                  their output to the first serial port on MSM devices.
 
-        config DEBUG_S3C_UART1
-                depends on PLAT_SAMSUNG
-                bool "Use S3C UART 1 for low-level debug"
+        config DEBUG_MSM_UART2
+                bool "Kernel low-level debugging messages via MSM UART2"
+                depends on ARCH_MSM7X00A || ARCH_MSM7X30 || ARCH_QSD8X50
                 help
                   Say Y here if you want the debug print routines to direct
-                  their output to UART 1. The port must have been initialised
-                  by the boot-loader before use.
+                  their output to the second serial port on MSM devices.
 
-                  The uncompressor code port configuration is now handled
-                  by CONFIG_S3C_LOWLEVEL_UART_PORT.
+        config DEBUG_MSM_UART3
+                bool "Kernel low-level debugging messages via MSM UART3"
+                depends on ARCH_MSM7X00A || ARCH_MSM7X30 || ARCH_QSD8X50
+                help
+                  Say Y here if you want the debug print routines to direct
+                  their output to the third serial port on MSM devices.
 
-        config DEBUG_S3C_UART2
-                depends on PLAT_SAMSUNG
-                bool "Use S3C UART 2 for low-level debug"
+        config DEBUG_MSM8660_UART
+                bool "Kernel low-level debugging messages via MSM 8660 UART"
+                depends on ARCH_MSM8X60
+                select MSM_HAS_DEBUG_UART_HS
                 help
                   Say Y here if you want the debug print routines to direct
-                  their output to UART 2. The port must have been initialised
-                  by the boot-loader before use.
+                  their output to the serial port on MSM 8660 devices.
 
-                  The uncompressor code port configuration is now handled
-                  by CONFIG_S3C_LOWLEVEL_UART_PORT.
+        config DEBUG_MSM8960_UART
+                bool "Kernel low-level debugging messages via MSM 8960 UART"
+                depends on ARCH_MSM8960
+                select MSM_HAS_DEBUG_UART_HS
+                help
+                  Say Y here if you want the debug print routines to direct
+                  their output to the serial port on MSM 8960 devices.
 
         config DEBUG_REALVIEW_STD_PORT
                 bool "RealView Default UART"
@@ -255,42 +240,57 @@ choice
                   their output to the standard serial port on the RealView
                   PB1176 platform.
 
-        config DEBUG_MSM_UART1
-                bool "Kernel low-level debugging messages via MSM UART1"
-                depends on ARCH_MSM7X00A || ARCH_MSM7X30 || ARCH_QSD8X50
+        config DEBUG_S3C_UART0
+                depends on PLAT_SAMSUNG
+                bool "Use S3C UART 0 for low-level debug"
                 help
                   Say Y here if you want the debug print routines to direct
-                  their output to the first serial port on MSM devices.
+                  their output to UART 0. The port must have been initialised
+                  by the boot-loader before use.
 
-        config DEBUG_MSM_UART2
-                bool "Kernel low-level debugging messages via MSM UART2"
-                depends on ARCH_MSM7X00A || ARCH_MSM7X30 || ARCH_QSD8X50
+                  The uncompressor code port configuration is now handled
+                  by CONFIG_S3C_LOWLEVEL_UART_PORT.
+
+        config DEBUG_S3C_UART1
+                depends on PLAT_SAMSUNG
+                bool "Use S3C UART 1 for low-level debug"
                 help
                   Say Y here if you want the debug print routines to direct
-                  their output to the second serial port on MSM devices.
+                  their output to UART 1. The port must have been initialised
+                  by the boot-loader before use.
 
-        config DEBUG_MSM_UART3
-                bool "Kernel low-level debugging messages via MSM UART3"
-                depends on ARCH_MSM7X00A || ARCH_MSM7X30 || ARCH_QSD8X50
+                  The uncompressor code port configuration is now handled
+                  by CONFIG_S3C_LOWLEVEL_UART_PORT.
+
+        config DEBUG_S3C_UART2
+                depends on PLAT_SAMSUNG
+                bool "Use S3C UART 2 for low-level debug"
                 help
                   Say Y here if you want the debug print routines to direct
-                  their output to the third serial port on MSM devices.
+                  their output to UART 2. The port must have been initialised
+                  by the boot-loader before use.
 
-        config DEBUG_MSM8660_UART
-                bool "Kernel low-level debugging messages via MSM 8660 UART"
-                depends on ARCH_MSM8X60
-                select MSM_HAS_DEBUG_UART_HS
+                  The uncompressor code port configuration is now handled
+                  by CONFIG_S3C_LOWLEVEL_UART_PORT.
+
+        config DEBUG_LL_UART_NONE
+                bool "No low-level debugging UART"
                 help
-                  Say Y here if you want the debug print routines to direct
-                  their output to the serial port on MSM 8660 devices.
+                  Say Y here if your platform doesn't provide a UART option
+                  below. This relies on your platform choosing the right UART
+                  definition internally in order for low-level debugging to
+                  work.
 
-        config DEBUG_MSM8960_UART
-                bool "Kernel low-level debugging messages via MSM 8960 UART"
-                depends on ARCH_MSM8960
-                select MSM_HAS_DEBUG_UART_HS
+        config DEBUG_ICEDCC
+                bool "Kernel low-level debugging via EmbeddedICE DCC channel"
                 help
                   Say Y here if you want the debug print routines to direct
-                  their output to the serial port on MSM 8960 devices.
+                  their output to the EmbeddedICE macrocell's DCC channel using
+                  co-processor 14. This is known to work on the ARM9 style ICE
+                  channel and on the XScale with the PEEDI.
+
+                  Note that the system will appear to hang during boot if there
+                  is nothing connected to read from the DCC.
 
 endchoice
 
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 1683bfb9166..0106f75530c 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -174,7 +174,7 @@ machine-$(CONFIG_ARCH_PRIMA2)		:= prima2
 machine-$(CONFIG_ARCH_PXA)              := pxa
 machine-$(CONFIG_ARCH_REALVIEW)         := realview
 machine-$(CONFIG_ARCH_RPC)              := rpc
-machine-$(CONFIG_ARCH_S3C2410)          := s3c2410 s3c2412 s3c2416 s3c2440 s3c2443
+machine-$(CONFIG_ARCH_S3C24XX)          := s3c24xx s3c2412 s3c2440
 machine-$(CONFIG_ARCH_S3C64XX)          := s3c64xx
 machine-$(CONFIG_ARCH_S5P64X0)          := s5p64x0
 machine-$(CONFIG_ARCH_S5PC100)          := s5pc100
diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S
index c5d60250d43..5f6045f1766 100644
--- a/arch/arm/boot/compressed/head.S
+++ b/arch/arm/boot/compressed/head.S
@@ -58,7 +58,7 @@
                 add     \rb, \rb, #0x00010000   @ Ser1
 #endif
                 .endm
-#elif defined(CONFIG_ARCH_S3C2410)
+#elif defined(CONFIG_ARCH_S3C24XX)
                 .macro loadsp, rb, tmp
                 mov     \rb, #0x50000000
                 add     \rb, \rb, #0x4000 * CONFIG_S3C_LOWLEVEL_UART_PORT
diff --git a/arch/arm/boot/dts/am3517_mt_ventoux.dts b/arch/arm/boot/dts/am3517_mt_ventoux.dts
new file mode 100644
index 00000000000..5eb26d7d9b4
--- /dev/null
+++ b/arch/arm/boot/dts/am3517_mt_ventoux.dts
@@ -0,0 +1,27 @@
+/*
+ * Copyright (C) 2011 Ilya Yanok, EmCraft Systems
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+/dts-v1/;
+
+/include/ "omap3.dtsi"
+
+/ {
+        model = "TeeJet Mt.Ventoux";
+        compatible = "teejet,mt_ventoux", "ti,omap3";
+
+        memory {
+                device_type = "memory";
+                reg = <0x80000000 0x10000000>; /* 256 MB */
+        };
+
+        /* AM35xx doesn't have IVA */
+        soc {
+                iva {
+                        status = "disabled";
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/at91sam9g20.dtsi b/arch/arm/boot/dts/at91sam9g20.dtsi
index 07603b8c950..a100db03ec9 100644
--- a/arch/arm/boot/dts/at91sam9g20.dtsi
+++ b/arch/arm/boot/dts/at91sam9g20.dtsi
@@ -23,6 +23,11 @@
                 serial4 = &usart3;
                 serial5 = &usart4;
                 serial6 = &usart5;
+                gpio0 = &pioA;
+                gpio1 = &pioB;
+                gpio2 = &pioC;
+                tcb0 = &tcb0;
+                tcb1 = &tcb1;
         };
         cpus {
                 cpu@0 {
@@ -47,24 +52,69 @@
                         ranges;
 
                         aic: interrupt-controller@fffff000 {
-                                #interrupt-cells = <1>;
+                                #interrupt-cells = <2>;
                                 compatible = "atmel,at91rm9200-aic";
                                 interrupt-controller;
                                 interrupt-parent;
                                 reg = <0xfffff000 0x200>;
                         };
 
+                        pit: timer@fffffd30 {
+                                compatible = "atmel,at91sam9260-pit";
+                                reg = <0xfffffd30 0xf>;
+                                interrupts = <1 4>;
+                        };
+
+                        tcb0: timer@fffa0000 {
+                                compatible = "atmel,at91rm9200-tcb";
+                                reg = <0xfffa0000 0x100>;
+                                interrupts = <17 4 18 4 19 4>;
+                        };
+
+                        tcb1: timer@fffdc000 {
+                                compatible = "atmel,at91rm9200-tcb";
+                                reg = <0xfffdc000 0x100>;
+                                interrupts = <26 4 27 4 28 4>;
+                        };
+
+                        pioA: gpio@fffff400 {
+                                compatible = "atmel,at91rm9200-gpio";
+                                reg = <0xfffff400 0x100>;
+                                interrupts = <2 4>;
+                                #gpio-cells = <2>;
+                                gpio-controller;
+                                interrupt-controller;
+                        };
+
+                        pioB: gpio@fffff600 {
+                                compatible = "atmel,at91rm9200-gpio";
+                                reg = <0xfffff600 0x100>;
+                                interrupts = <3 4>;
+                                #gpio-cells = <2>;
+                                gpio-controller;
+                                interrupt-controller;
+                        };
+
+                        pioC: gpio@fffff800 {
+                                compatible = "atmel,at91rm9200-gpio";
+                                reg = <0xfffff800 0x100>;
+                                interrupts = <4 4>;
+                                #gpio-cells = <2>;
+                                gpio-controller;
+                                interrupt-controller;
+                        };
+
                         dbgu: serial@fffff200 {
                                 compatible = "atmel,at91sam9260-usart";
                                 reg = <0xfffff200 0x200>;
-                                interrupts = <1>;
+                                interrupts = <1 4>;
                                 status = "disabled";
                         };
 
                         usart0: serial@fffb0000 {
                                 compatible = "atmel,at91sam9260-usart";
                                 reg = <0xfffb0000 0x200>;
-                                interrupts = <6>;
+                                interrupts = <6 4>;
                                 atmel,use-dma-rx;
                                 atmel,use-dma-tx;
                                 status = "disabled";
@@ -73,7 +123,7 @@
                         usart1: serial@fffb4000 {
                                 compatible = "atmel,at91sam9260-usart";
                                 reg = <0xfffb4000 0x200>;
-                                interrupts = <7>;
+                                interrupts = <7 4>;
                                 atmel,use-dma-rx;
                                 atmel,use-dma-tx;
                                 status = "disabled";
@@ -82,7 +132,7 @@
                         usart2: serial@fffb8000 {
                                 compatible = "atmel,at91sam9260-usart";
                                 reg = <0xfffb8000 0x200>;
-                                interrupts = <8>;
+                                interrupts = <8 4>;
                                 atmel,use-dma-rx;
                                 atmel,use-dma-tx;
                                 status = "disabled";
@@ -91,7 +141,7 @@
                         usart3: serial@fffd0000 {
                                 compatible = "atmel,at91sam9260-usart";
                                 reg = <0xfffd0000 0x200>;
-                                interrupts = <23>;
+                                interrupts = <23 4>;
                                 atmel,use-dma-rx;
                                 atmel,use-dma-tx;
                                 status = "disabled";
@@ -100,7 +150,7 @@
                         usart4: serial@fffd4000 {
                                 compatible = "atmel,at91sam9260-usart";
                                 reg = <0xfffd4000 0x200>;
-                                interrupts = <24>;
+                                interrupts = <24 4>;
                                 atmel,use-dma-rx;
                                 atmel,use-dma-tx;
                                 status = "disabled";
@@ -109,7 +159,7 @@
                         usart5: serial@fffd8000 {
                                 compatible = "atmel,at91sam9260-usart";
                                 reg = <0xfffd8000 0x200>;
-                                interrupts = <25>;
+                                interrupts = <25 4>;
                                 atmel,use-dma-rx;
                                 atmel,use-dma-tx;
                                 status = "disabled";
@@ -118,7 +168,7 @@
                         macb0: ethernet@fffc4000 {
                                 compatible = "cdns,at32ap7000-macb", "cdns,macb";
                                 reg = <0xfffc4000 0x100>;
-                                interrupts = <21>;
+                                interrupts = <21 4>;
                                 status = "disabled";
                         };
                 };
diff --git a/arch/arm/boot/dts/at91sam9g25ek.dts b/arch/arm/boot/dts/at91sam9g25ek.dts
new file mode 100644
index 00000000000..e64eb932083
--- /dev/null
+++ b/arch/arm/boot/dts/at91sam9g25ek.dts
@@ -0,0 +1,37 @@
+/*
+ * at91sam9g25ek.dts - Device Tree file for AT91SAM9G25-EK board
+ *
+ *  Copyright (C) 2012 Atmel,
+ *                2012 Nicolas Ferre <nicolas.ferre@atmel.com>
+ *
+ * Licensed under GPLv2 or later.
+ */
+/dts-v1/;
+/include/ "at91sam9x5.dtsi"
+/include/ "at91sam9x5cm.dtsi"
+
+/ {
+        model = "Atmel AT91SAM9G25-EK";
+        compatible = "atmel,at91sam9g25ek", "atmel,at91sam9x5ek", "atmel,at91sam9x5", "atmel,at91sam9";
+
+        chosen {
+                bootargs = "128M console=ttyS0,115200 mtdparts=atmel_nand:8M(bootstrap/uboot/kernel)ro,-(rootfs) root=/dev/mtdblock1 rw rootfstype=ubifs ubi.mtd=1 root=ubi0:rootfs";
+        };
+
+        ahb {
+                apb {
+                        dbgu: serial@fffff200 {
+                                status = "okay";
+                        };
+
+                        usart0: serial@f801c000 {
+                                status = "okay";
+                        };
+
+                        macb0: ethernet@f802c000 {
+                                phy-mode = "rmii";
+                                status = "okay";
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi
index fffa005300a..f779667159b 100644
--- a/arch/arm/boot/dts/at91sam9g45.dtsi
+++ b/arch/arm/boot/dts/at91sam9g45.dtsi
@@ -22,6 +22,13 @@
                 serial2 = &usart1;
                 serial3 = &usart2;
                 serial4 = &usart3;
+                gpio0 = &pioA;
+                gpio1 = &pioB;
+                gpio2 = &pioC;
+                gpio3 = &pioD;
+                gpio4 = &pioE;
+                tcb0 = &tcb0;
+                tcb1 = &tcb1;
         };
         cpus {
                 cpu@0 {
@@ -46,30 +53,94 @@
                         ranges;
 
                         aic: interrupt-controller@fffff000 {
-                                #interrupt-cells = <1>;
+                                #interrupt-cells = <2>;
                                 compatible = "atmel,at91rm9200-aic";
                                 interrupt-controller;
                                 interrupt-parent;
                                 reg = <0xfffff000 0x200>;
                         };
 
+                        pit: timer@fffffd30 {
+                                compatible = "atmel,at91sam9260-pit";
+                                reg = <0xfffffd30 0xf>;
+                                interrupts = <1 4>;
+                        };
+
+
+                        tcb0: timer@fff7c000 {
+                                compatible = "atmel,at91rm9200-tcb";
+                                reg = <0xfff7c000 0x100>;
+                                interrupts = <18 4>;
+                        };
+
+                        tcb1: timer@fffd4000 {
+                                compatible = "atmel,at91rm9200-tcb";
+                                reg = <0xfffd4000 0x100>;
+                                interrupts = <18 4>;
+                        };
+
                         dma: dma-controller@ffffec00 {
                                 compatible = "atmel,at91sam9g45-dma";
                                 reg = <0xffffec00 0x200>;
-                                interrupts = <21>;
+                                interrupts = <21 4>;
+                        };
+
+                        pioA: gpio@fffff200 {
+                                compatible = "atmel,at91rm9200-gpio";
+                                reg = <0xfffff200 0x100>;
+                                interrupts = <2 4>;
+                                #gpio-cells = <2>;
+                                gpio-controller;
+                                interrupt-controller;
+                        };
+
+                        pioB: gpio@fffff400 {
+                                compatible = "atmel,at91rm9200-gpio";
+                                reg = <0xfffff400 0x100>;
+                                interrupts = <3 4>;
+                                #gpio-cells = <2>;
+                                gpio-controller;
+                                interrupt-controller;
+                        };
+
+                        pioC: gpio@fffff600 {
+                                compatible = "atmel,at91rm9200-gpio";
+                                reg = <0xfffff600 0x100>;
+                                interrupts = <4 4>;
+                                #gpio-cells = <2>;
+                                gpio-controller;
+                                interrupt-controller;
+                        };
+
+                        pioD: gpio@fffff800 {
+                                compatible = "atmel,at91rm9200-gpio";
+                                reg = <0xfffff800 0x100>;
+                                interrupts = <5 4>;
+                                #gpio-cells = <2>;
+                                gpio-controller;
+                                interrupt-controller;
+                        };
+
+                        pioE: gpio@fffffa00 {
+                                compatible = "atmel,at91rm9200-gpio";
+                                reg = <0xfffffa00 0x100>;
+                                interrupts = <5 4>;
+                                #gpio-cells = <2>;
+                                gpio-controller;
+                                interrupt-controller;
                         };
 
                         dbgu: serial@ffffee00 {
                                 compatible = "atmel,at91sam9260-usart";
                                 reg = <0xffffee00 0x200>;
-                                interrupts = <1>;
+                                interrupts = <1 4>;
                                 status = "disabled";
                         };
 
                         usart0: serial@fff8c000 {
                                 compatible = "atmel,at91sam9260-usart";
                                 reg = <0xfff8c000 0x200>;
-                                interrupts = <7>;
+                                interrupts = <7 4>;
                                 atmel,use-dma-rx;
                                 atmel,use-dma-tx;
                                 status = "disabled";
@@ -78,7 +149,7 @@
                         usart1: serial@fff90000 {
                                 compatible = "atmel,at91sam9260-usart";
                                 reg = <0xfff90000 0x200>;
-                                interrupts = <8>;
+                                interrupts = <8 4>;
                                 atmel,use-dma-rx;
                                 atmel,use-dma-tx;
                                 status = "disabled";
@@ -87,7 +158,7 @@
                         usart2: serial@fff94000 {
                                 compatible = "atmel,at91sam9260-usart";
                                 reg = <0xfff94000 0x200>;
-                                interrupts = <9>;
+                                interrupts = <9 4>;
                                 atmel,use-dma-rx;
                                 atmel,use-dma-tx;
                                 status = "disabled";
@@ -96,7 +167,7 @@
                         usart3: serial@fff98000 {
                                 compatible = "atmel,at91sam9260-usart";
                                 reg = <0xfff98000 0x200>;
-                                interrupts = <10>;
+                                interrupts = <10 4>;
                                 atmel,use-dma-rx;
                                 atmel,use-dma-tx;
                                 status = "disabled";
@@ -105,7 +176,7 @@
                         macb0: ethernet@fffbc000 {
                                 compatible = "cdns,at32ap7000-macb", "cdns,macb";
                                 reg = <0xfffbc000 0x100>;
-                                interrupts = <25>;
+                                interrupts = <25 4>;
                                 status = "disabled";
                         };
                 };
diff --git a/arch/arm/boot/dts/at91sam9m10g45ek.dts b/arch/arm/boot/dts/at91sam9m10g45ek.dts
index a387e7704ce..15e25f903ca 100644
--- a/arch/arm/boot/dts/at91sam9m10g45ek.dts
+++ b/arch/arm/boot/dts/at91sam9m10g45ek.dts
@@ -37,4 +37,76 @@
                         };
                 };
         };
+
+        leds {
+                compatible = "gpio-leds";
+
+                d8 {
+                        label = "d8";
+                        gpios = <&pioD 30 0>;
+                        linux,default-trigger = "heartbeat";
+                };
+
+                d6 {
+                        label = "d6";
+                        gpios = <&pioD 0 1>;
+                        linux,default-trigger = "nand-disk";
+                };
+
+                d7 {
+                        label = "d7";
+                        gpios = <&pioD 31 1>;
+                        linux,default-trigger = "mmc0";
+                };
+        };
+
+        gpio_keys {
+                compatible = "gpio-keys";
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                left_click {
+                        label = "left_click";
+                        gpios = <&pioB 6 1>;
+                        linux,code = <272>;
+                        gpio-key,wakeup;
+                };
+
+                right_click {
+                        label = "right_click";
+                        gpios = <&pioB 7 1>;
+                        linux,code = <273>;
+                        gpio-key,wakeup;
+                };
+
+                left {
+                        label = "Joystick Left";
+                        gpios = <&pioB 14 1>;
+                        linux,code = <105>;
+                };
+
+                right {
+                        label = "Joystick Right";
+                        gpios = <&pioB 15 1>;
+                        linux,code = <106>;
+                };
+
+                up {
+                        label = "Joystick Up";
+                        gpios = <&pioB 16 1>;
+                        linux,code = <103>;
+                };
+
+                down {
+                        label = "Joystick Down";
+                        gpios = <&pioB 17 1>;
+                        linux,code = <108>;
+                };
+
+                enter {
+                        label = "Joystick Press";
+                        gpios = <&pioB 18 1>;
+                        linux,code = <28>;
+                };
+        };
 };
diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi
new file mode 100644
index 00000000000..a02e636d8a5
--- /dev/null
+++ b/arch/arm/boot/dts/at91sam9x5.dtsi
@@ -0,0 +1,176 @@
+/*
+ * at91sam9x5.dtsi - Device Tree Include file for AT91SAM9x5 family SoC
+ *                   applies to AT91SAM9G15, AT91SAM9G25, AT91SAM9G35,
+ *                   AT91SAM9X25, AT91SAM9X35 SoC
+ *
+ *  Copyright (C) 2012 Atmel,
+ *                2012 Nicolas Ferre <nicolas.ferre@atmel.com>
+ *
+ * Licensed under GPLv2 or later.
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+        model = "Atmel AT91SAM9x5 family SoC";
+        compatible = "atmel,at91sam9x5";
+        interrupt-parent = <&aic>;
+
+        aliases {
+                serial0 = &dbgu;
+                serial1 = &usart0;
+                serial2 = &usart1;
+                serial3 = &usart2;
+                gpio0 = &pioA;
+                gpio1 = &pioB;
+                gpio2 = &pioC;
+                gpio3 = &pioD;
+                tcb0 = &tcb0;
+                tcb1 = &tcb1;
+        };
+        cpus {
+                cpu@0 {
+                        compatible = "arm,arm926ejs";
+                };
+        };
+
+        memory@20000000 {
+                reg = <0x20000000 0x10000000>;
+        };
+
+        ahb {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges;
+
+                apb {
+                        compatible = "simple-bus";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges;
+
+                        aic: interrupt-controller@fffff000 {
+                                #interrupt-cells = <2>;
+                                compatible = "atmel,at91rm9200-aic";
+                                interrupt-controller;
+                                interrupt-parent;
+                                reg = <0xfffff000 0x200>;
+                        };
+
+                        pit: timer@fffffe30 {
+                                compatible = "atmel,at91sam9260-pit";
+                                reg = <0xfffffe30 0xf>;
+                                interrupts = <1 4>;
+                        };
+
+                        tcb0: timer@f8008000 {
+                                compatible = "atmel,at91sam9x5-tcb";
+                                reg = <0xf8008000 0x100>;
+                                interrupts = <17 4>;
+                        };
+
+                        tcb1: timer@f800c000 {
+                                compatible = "atmel,at91sam9x5-tcb";
+                                reg = <0xf800c000 0x100>;
+                                interrupts = <17 4>;
+                        };
+
+                        dma0: dma-controller@ffffec00 {
+                                compatible = "atmel,at91sam9g45-dma";
+                                reg = <0xffffec00 0x200>;
+                                interrupts = <20 4>;
+                        };
+
+                        dma1: dma-controller@ffffee00 {
+                                compatible = "atmel,at91sam9g45-dma";
+                                reg = <0xffffee00 0x200>;
+                                interrupts = <21 4>;
+                        };
+
+                        pioA: gpio@fffff400 {
+                                compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
+                                reg = <0xfffff400 0x100>;
+                                interrupts = <2 4>;
+                                #gpio-cells = <2>;
+                                gpio-controller;
+                                interrupt-controller;
+                        };
+
+                        pioB: gpio@fffff600 {
+                                compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
+                                reg = <0xfffff600 0x100>;
+                                interrupts = <2 4>;
+                                #gpio-cells = <2>;
+                                gpio-controller;
+                                interrupt-controller;
+                        };
+
+                        pioC: gpio@fffff800 {
+                                compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
+                                reg = <0xfffff800 0x100>;
+                                interrupts = <3 4>;
+                                #gpio-cells = <2>;
+                                gpio-controller;
+                                interrupt-controller;
+                        };
+
+                        pioD: gpio@fffffa00 {
+                                compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
+                                reg = <0xfffffa00 0x100>;
+                                interrupts = <3 4>;
+                                #gpio-cells = <2>;
+                                gpio-controller;
+                                interrupt-controller;
+                        };
+
+                        dbgu: serial@fffff200 {
+                                compatible = "atmel,at91sam9260-usart";
+                                reg = <0xfffff200 0x200>;
+                                interrupts = <1 4>;
+                                status = "disabled";
+                        };
+
+                        usart0: serial@f801c000 {
+                                compatible = "atmel,at91sam9260-usart";
+                                reg = <0xf801c000 0x200>;
+                                interrupts = <5 4>;
+                                atmel,use-dma-rx;
+                                atmel,use-dma-tx;
+                                status = "disabled";
+                        };
+
+                        usart1: serial@f8020000 {
+                                compatible = "atmel,at91sam9260-usart";
+                                reg = <0xf8020000 0x200>;
+                                interrupts = <6 4>;
+                                atmel,use-dma-rx;
+                                atmel,use-dma-tx;
+                                status = "disabled";
+                        };
+
+                        usart2: serial@f8024000 {
+                                compatible = "atmel,at91sam9260-usart";
+                                reg = <0xf8024000 0x200>;
+                                interrupts = <7 4>;
+                                atmel,use-dma-rx;
+                                atmel,use-dma-tx;
+                                status = "disabled";
+                        };
+
+                        macb0: ethernet@f802c000 {
+                                compatible = "cdns,at32ap7000-macb", "cdns,macb";
+                                reg = <0xf802c000 0x100>;
+                                interrupts = <24 4>;
+                                status = "disabled";
+                        };
+
+                        macb1: ethernet@f8030000 {
+                                compatible = "cdns,at32ap7000-macb", "cdns,macb";
+                                reg = <0xf8030000 0x100>;
+                                interrupts = <27 4>;
+                                status = "disabled";
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/at91sam9x5cm.dtsi b/arch/arm/boot/dts/at91sam9x5cm.dtsi
new file mode 100644
index 00000000000..64ae3e89025
--- /dev/null
+++ b/arch/arm/boot/dts/at91sam9x5cm.dtsi
@@ -0,0 +1,29 @@
+/*
+ * at91sam9x5cm.dtsi - Device Tree Include file for AT91SAM9x5 CPU Module
+ *
+ *  Copyright (C) 2012 Atmel,
+ *                2012 Nicolas Ferre <nicolas.ferre@atmel.com>
+ *
+ * Licensed under GPLv2 or later.
+ */
+
+/ {
+        memory@20000000 {
+                reg = <0x20000000 0x8000000>;
+        };
+
+        leds {
+                compatible = "gpio-leds";
+
+                pb18 {
+                        label = "pb18";
+                        gpios = <&pioB 18 1>;
+                        linux,default-trigger = "heartbeat";
+                };
+
+                pd21 {
+                        label = "pd21";
+                        gpios = <&pioD 21 0>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/highbank.dts b/arch/arm/boot/dts/highbank.dts
index 305635bd45c..37c0ff9c8b9 100644
--- a/arch/arm/boot/dts/highbank.dts
+++ b/arch/arm/boot/dts/highbank.dts
@@ -72,15 +72,15 @@
                 ranges;
 
                 timer@fff10600 {
-                        compatible = "arm,smp-twd";
+                        compatible = "arm,cortex-a9-twd-timer";
                         reg = <0xfff10600 0x20>;
-                        interrupts = <1 13 0xf04>;
+                        interrupts = <1 13 0xf01>;
                 };
 
                 watchdog@fff10620 {
-                        compatible = "arm,cortex-a9-wdt";
+                        compatible = "arm,cortex-a9-twd-wdt";
                         reg = <0xfff10620 0x20>;
-                        interrupts = <1 14 0xf04>;
+                        interrupts = <1 14 0xf01>;
                 };
 
                 intc: interrupt-controller@fff11000 {
diff --git a/arch/arm/boot/dts/imx27-phytec-phycore.dts b/arch/arm/boot/dts/imx27-phytec-phycore.dts
new file mode 100644
index 00000000000..a51a08fc2af
--- /dev/null
+++ b/arch/arm/boot/dts/imx27-phytec-phycore.dts
@@ -0,0 +1,76 @@
+/*
+ * Copyright 2012 Sascha Hauer, Pengutronix
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+/include/ "imx27.dtsi"
+
+/ {
+        model = "Phytec pcm038";
+        compatible = "phytec,imx27-pcm038", "fsl,imx27";
+
+        memory {
+                reg = <0x0 0x0>;
+        };
+
+        soc {
+                aipi@10000000 { /* aipi */
+
+                        wdog@10002000 {
+                                status = "okay";
+                        };
+
+                        uart@1000a000 {
+                                fsl,uart-has-rtscts;
+                                status = "okay";
+                        };
+
+                        uart@1000b000 {
+                                fsl,uart-has-rtscts;
+                                status = "okay";
+                        };
+
+                        uart@1000c000 {
+                                fsl,uart-has-rtscts;
+                                status = "okay";
+                        };
+
+                        fec@1002b000 {
+                                status = "okay";
+                        };
+
+                        i2c@1001d000 {
+                                clock-frequency = <400000>;
+                                status = "okay";
+                                at24@4c {
+                                        compatible = "at,24c32";
+                                        pagesize = <32>;
+                                        reg = <0x52>;
+                                };
+                                pcf8563@51 {
+                                        compatible = "nxp,pcf8563";
+                                        reg = <0x51>;
+                                };
+                                lm75@4a {
+                                        compatible = "national,lm75";
+                                        reg = <0x4a>;
+                                };
+                        };
+                };
+        };
+
+        nor_flash@c0000000 {
+                compatible = "cfi-flash";
+                bank-width = <2>;
+                reg = <0xc0000000 0x02000000>;
+                #address-cells = <1>;
+                #size-cells = <1>;
+        };
+};
diff --git a/arch/arm/boot/dts/imx27.dtsi b/arch/arm/boot/dts/imx27.dtsi
new file mode 100644
index 00000000000..bc5e7d5ddd5
--- /dev/null
+++ b/arch/arm/boot/dts/imx27.dtsi
@@ -0,0 +1,217 @@
+/*
+ * Copyright 2012 Sascha Hauer, Pengutronix
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+        aliases {
+                serial0 = &uart1;
+                serial1 = &uart2;
+                serial2 = &uart3;
+                serial3 = &uart4;
+                serial4 = &uart5;
+                serial5 = &uart6;
+        };
+
+        avic: avic-interrupt-controller@e0000000 {
+                compatible = "fsl,imx27-avic", "fsl,avic";
+                interrupt-controller;
+                #interrupt-cells = <1>;
+                reg = <0x10040000 0x1000>;
+        };
+
+        clocks {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                osc26m {
+                        compatible = "fsl,imx-osc26m", "fixed-clock";
+                        clock-frequency = <26000000>;
+                };
+        };
+
+        soc {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "simple-bus";
+                interrupt-parent = <&avic>;
+                ranges;
+
+                aipi@10000000 { /* AIPI1 */
+                        compatible = "fsl,aipi-bus", "simple-bus";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        reg = <0x10000000 0x10000000>;
+                        ranges;
+
+                        wdog@10002000 {
+                                compatible = "fsl,imx27-wdt", "fsl,imx21-wdt";
+                                reg = <0x10002000 0x4000>;
+                                interrupts = <27>;
+                                status = "disabled";
+                        };
+
+                        uart1: uart@1000a000 {
+                                compatible = "fsl,imx27-uart", "fsl,imx21-uart";
+                                reg = <0x1000a000 0x1000>;
+                                interrupts = <20>;
+                                status = "disabled";
+                        };
+
+                        uart2: uart@1000b000 {
+                                compatible = "fsl,imx27-uart", "fsl,imx21-uart";
+                                reg = <0x1000b000 0x1000>;
+                                interrupts = <19>;
+                                status = "disabled";
+                        };
+
+                        uart3: uart@1000c000 {
+                                compatible = "fsl,imx27-uart", "fsl,imx21-uart";
+                                reg = <0x1000c000 0x1000>;
+                                interrupts = <18>;
+                                status = "disabled";
+                        };
+
+                        uart4: uart@1000d000 {
+                                compatible = "fsl,imx27-uart", "fsl,imx21-uart";
+                                reg = <0x1000d000 0x1000>;
+                                interrupts = <17>;
+                                status = "disabled";
+                        };
+
+                        cspi1: cspi@1000e000 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                compatible = "fsl,imx27-cspi";
+                                reg = <0x1000e000 0x1000>;
+                                interrupts = <16>;
+                                status = "disabled";
+                        };
+
+                        cspi2: cspi@1000f000 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                compatible = "fsl,imx27-cspi";
+                                reg = <0x1000f000 0x1000>;
+                                interrupts = <15>;
+                                status = "disabled";
+                        };
+
+                        i2c1: i2c@10012000 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                compatible = "fsl,imx27-i2c", "fsl,imx1-i2c";
+                                reg = <0x10012000 0x1000>;
+                                interrupts = <12>;
+                                status = "disabled";
+                        };
+
+                        gpio1: gpio@10015000 {
+                                compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
+                                reg = <0x10015000 0x100>;
+                                interrupts = <8>;
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                interrupt-controller;
+                                #interrupt-cells = <1>;
+                        };
+
+                        gpio2: gpio@10015100 {
+                                compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
+                                reg = <0x10015100 0x100>;
+                                interrupts = <8>;
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                interrupt-controller;
+                                #interrupt-cells = <1>;
+                        };
+
+                        gpio3: gpio@10015200 {
+                                compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
+                                reg = <0x10015200 0x100>;
+                                interrupts = <8>;
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                interrupt-controller;
+                                #interrupt-cells = <1>;
+                        };
+
+                        gpio4: gpio@10015300 {
+                                compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
+                                reg = <0x10015300 0x100>;
+                                interrupts = <8>;
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                interrupt-controller;
+                                #interrupt-cells = <1>;
+                        };
+
+                        gpio5: gpio@10015400 {
+                                compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
+                                reg = <0x10015400 0x100>;
+                                interrupts = <8>;
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                interrupt-controller;
+                                #interrupt-cells = <1>;
+                        };
+
+                        gpio6: gpio@10015500 {
+                                compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
+                                reg = <0x10015500 0x100>;
+                                interrupts = <8>;
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                interrupt-controller;
+                                #interrupt-cells = <1>;
+                        };
+
+                        cspi3: cspi@10017000 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                compatible = "fsl,imx27-cspi";
+                                reg = <0x10017000 0x1000>;
+                                interrupts = <6>;
+                                status = "disabled";
+                        };
+
+                        uart5: uart@1001b000 {
+                                compatible = "fsl,imx27-uart", "fsl,imx21-uart";
+                                reg = <0x1001b000 0x1000>;
+                                interrupts = <49>;
+                                status = "disabled";
+                        };
+
+                        uart6: uart@1001c000 {
+                                compatible = "fsl,imx27-uart", "fsl,imx21-uart";
+                                reg = <0x1001c000 0x1000>;
+                                interrupts = <48>;
+                                status = "disabled";
+                        };
+
+                        i2c2: i2c@1001d000 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                compatible = "fsl,imx27-i2c", "fsl,imx1-i2c";
+                                reg = <0x1001d000 0x1000>;
+                                interrupts = <1>;
+                                status = "disabled";
+                        };
+
+                        fec: fec@1002b000 {
+                                compatible = "fsl,imx27-fec";
+                                reg = <0x1002b000 0x4000>;
+                                interrupts = <50>;
+                                status = "disabled";
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/imx51-babbage.dts b/arch/arm/boot/dts/imx51-babbage.dts
index 564cb8c19f1..9949e6060de 100644
--- a/arch/arm/boot/dts/imx51-babbage.dts
+++ b/arch/arm/boot/dts/imx51-babbage.dts
@@ -56,8 +56,95 @@
                                                 compatible = "fsl,mc13892";
                                                 spi-max-frequency = <6000000>;
                                                 reg = <0>;
-                                                mc13xxx-irq-gpios = <&gpio1 8 0>;
-                                                fsl,mc13xxx-uses-regulator;
+                                                interrupt-parent = <&gpio1>;
+                                                interrupts = <8>;
+
+                                                regulators {
+                                                        sw1_reg: sw1 {
+                                                                regulator-min-microvolt = <600000>;
+                                                                regulator-max-microvolt = <1375000>;
+                                                                regulator-boot-on;
+                                                                regulator-always-on;
+                                                        };
+
+                                                        sw2_reg: sw2 {
+                                                                regulator-min-microvolt = <900000>;
+                                                                regulator-max-microvolt = <1850000>;
+                                                                regulator-boot-on;
+                                                                regulator-always-on;
+                                                        };
+
+                                                        sw3_reg: sw3 {
+                                                                regulator-min-microvolt = <1100000>;
+                                                                regulator-max-microvolt = <1850000>;
+                                                                regulator-boot-on;
+                                                                regulator-always-on;
+                                                        };
+
+                                                        sw4_reg: sw4 {
+                                                                regulator-min-microvolt = <1100000>;
+                                                                regulator-max-microvolt = <1850000>;
+                                                                regulator-boot-on;
+                                                                regulator-always-on;
+                                                        };
+
+                                                        vpll_reg: vpll {
+                                                                regulator-min-microvolt = <1050000>;
+                                                                regulator-max-microvolt = <1800000>;
+                                                                regulator-boot-on;
+                                                                regulator-always-on;
+                                                        };
+
+                                                        vdig_reg: vdig {
+                                                                regulator-min-microvolt = <1650000>;
+                                                                regulator-max-microvolt = <1650000>;
+                                                                regulator-boot-on;
+                                                        };
+
+                                                        vsd_reg: vsd {
+                                                                regulator-min-microvolt = <1800000>;
+                                                                regulator-max-microvolt = <3150000>;
+                                                        };
+
+                                                        vusb2_reg: vusb2 {
+                                                                regulator-min-microvolt = <2400000>;
+                                                                regulator-max-microvolt = <2775000>;
+                                                                regulator-boot-on;
+                                                                regulator-always-on;
+                                                        };
+
+                                                        vvideo_reg: vvideo {
+                                                                regulator-min-microvolt = <2775000>;
+                                                                regulator-max-microvolt = <2775000>;
+                                                        };
+
+                                                        vaudio_reg: vaudio {
+                                                                regulator-min-microvolt = <2300000>;
+                                                                regulator-max-microvolt = <3000000>;
+                                                        };
+
+                                                        vcam_reg: vcam {
+                                                                regulator-min-microvolt = <2500000>;
+                                                                regulator-max-microvolt = <3000000>;
+                                                        };
+
+                                                        vgen1_reg: vgen1 {
+                                                                regulator-min-microvolt = <1200000>;
+                                                                regulator-max-microvolt = <1200000>;
+                                                        };
+
+                                                        vgen2_reg: vgen2 {
+                                                                regulator-min-microvolt = <1200000>;
+                                                                regulator-max-microvolt = <3150000>;
+                                                                regulator-always-on;
+                                                        };
+
+                                                        vgen3_reg: vgen3 {
+                                                                regulator-min-microvolt = <1800000>;
+                                                                regulator-max-microvolt = <2900000>;
+                                                                regulator-always-on;
+                                                        };
+                                                };
                                         };
 
                                         flash: at45db321d@1 {
diff --git a/arch/arm/boot/dts/imx6q-arm2.dts b/arch/arm/boot/dts/imx6q-arm2.dts
index c3977e0478b..ce1c8238c89 100644
--- a/arch/arm/boot/dts/imx6q-arm2.dts
+++ b/arch/arm/boot/dts/imx6q-arm2.dts
@@ -36,11 +36,13 @@
                         usdhc@02198000 { /* uSDHC3 */
                                 cd-gpios = <&gpio6 11 0>;
                                 wp-gpios = <&gpio6 14 0>;
+                                vmmc-supply = <&reg_3p3v>;
                                 status = "okay";
                         };
 
                         usdhc@0219c000 { /* uSDHC4 */
                                 fsl,card-wired;
+                                vmmc-supply = <&reg_3p3v>;
                                 status = "okay";
                         };
 
@@ -50,6 +52,18 @@
                 };
         };
 
+        regulators {
+                compatible = "simple-bus";
+
+                reg_3p3v: 3p3v {
+                        compatible = "regulator-fixed";
+                        regulator-name = "3P3V";
+                        regulator-min-microvolt = <3300000>;
+                        regulator-max-microvolt = <3300000>;
+                        regulator-always-on;
+                };
+        };
+
         leds {
                 compatible = "gpio-leds";
 
diff --git a/arch/arm/boot/dts/imx6q-sabrelite.dts b/arch/arm/boot/dts/imx6q-sabrelite.dts
index 08d920de728..4663a4e5a28 100644
--- a/arch/arm/boot/dts/imx6q-sabrelite.dts
+++ b/arch/arm/boot/dts/imx6q-sabrelite.dts
@@ -32,18 +32,52 @@
                         usdhc@02198000 { /* uSDHC3 */
                                 cd-gpios = <&gpio7 0 0>;
                                 wp-gpios = <&gpio7 1 0>;
+                                vmmc-supply = <&reg_3p3v>;
                                 status = "okay";
                         };
 
                         usdhc@0219c000 { /* uSDHC4 */
                                 cd-gpios = <&gpio2 6 0>;
                                 wp-gpios = <&gpio2 7 0>;
+                                vmmc-supply = <&reg_3p3v>;
                                 status = "okay";
                         };
 
                         uart2: uart@021e8000 {
                                 status = "okay";
                         };
+
+                        i2c@021a0000 { /* I2C1 */
+                                status = "okay";
+                                clock-frequency = <100000>;
+
+                                codec: sgtl5000@0a {
+                                        compatible = "fsl,sgtl5000";
+                                        reg = <0x0a>;
+                                        VDDA-supply = <&reg_2p5v>;
+                                        VDDIO-supply = <&reg_3p3v>;
+                                };
+                        };
+                };
+        };
+
+        regulators {
+                compatible = "simple-bus";
+
+                reg_2p5v: 2p5v {
+                        compatible = "regulator-fixed";
+                        regulator-name = "2P5V";
+                        regulator-min-microvolt = <2500000>;
+                        regulator-max-microvolt = <2500000>;
+                        regulator-always-on;
+                };
+
+                reg_3p3v: 3p3v {
+                        compatible = "regulator-fixed";
+                        regulator-name = "3P3V";
+                        regulator-min-microvolt = <3300000>;
+                        regulator-max-microvolt = <3300000>;
+                        regulator-always-on;
                 };
         };
 };
diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
index 263e8f3664b..4905f51a106 100644
--- a/arch/arm/boot/dts/imx6q.dtsi
+++ b/arch/arm/boot/dts/imx6q.dtsi
@@ -88,9 +88,9 @@
                 ranges;
 
                 timer@00a00600 {
-                        compatible = "arm,smp-twd";
-                        reg = <0x00a00600 0x100>;
-                        interrupts = <1 13 0xf4>;
+                        compatible = "arm,cortex-a9-twd-timer";
+                        reg = <0x00a00600 0x20>;
+                        interrupts = <1 13 0xf01>;
                 };
 
                 L2: l2-cache@00a02000 {
diff --git a/arch/arm/boot/dts/kirkwood-dreamplug.dts b/arch/arm/boot/dts/kirkwood-dreamplug.dts
new file mode 100644
index 00000000000..8a5dff807b4
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood-dreamplug.dts
@@ -0,0 +1,25 @@
+/dts-v1/;
+
+/include/ "kirkwood.dtsi"
+
+/ {
+        model = "Globalscale Technologies Dreamplug";
+        compatible = "globalscale,dreamplug-003-ds2001", "globalscale,dreamplug", "marvell,kirkwood-88f6281", "marvell,kirkwood";
+
+        memory {
+                device_type = "memory";
+                reg = <0x00000000 0x20000000>;
+        };
+
+        chosen {
+                bootargs = "console=ttyS0,115200n8 earlyprintk";
+        };
+
+        serial@f1012000 {
+                compatible = "ns16550a";
+                reg = <0xf1012000 0xff>;
+                reg-shift = <2>;
+                interrupts = <33>;
+                clock-frequency = <200000000>;
+        };
+};
diff --git a/arch/arm/boot/dts/kirkwood.dtsi b/arch/arm/boot/dts/kirkwood.dtsi
new file mode 100644
index 00000000000..771c6bbeb29
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood.dtsi
@@ -0,0 +1,6 @@
+/include/ "skeleton.dtsi"
+
+/ {
+        compatible = "marvell,kirkwood";
+};
+
diff --git a/arch/arm/boot/dts/omap3-beagle.dts b/arch/arm/boot/dts/omap3-beagle.dts
index 9486be62bcd..9f72cd4cf30 100644
--- a/arch/arm/boot/dts/omap3-beagle.dts
+++ b/arch/arm/boot/dts/omap3-beagle.dts
@@ -13,15 +13,6 @@
         model = "TI OMAP3 BeagleBoard";
         compatible = "ti,omap3-beagle", "ti,omap3";
 
-        /*
-         * Since the initial device tree board file does not create any
-         * devices (MMC, network...), the only way to boot is to provide a
-         * ramdisk.
-         */
-        chosen {
-                bootargs = "root=/dev/ram0 rw console=ttyO2,115200n8 initrd=0x81600000,20M ramdisk_size=20480 no_console_suspend debug earlyprintk";
-        };
-
         memory {
                 device_type = "memory";
                 reg = <0x80000000 0x20000000>; /* 512 MB */
diff --git a/arch/arm/boot/dts/omap3-evm.dts b/arch/arm/boot/dts/omap3-evm.dts
new file mode 100644
index 00000000000..2eee16ec59b
--- /dev/null
+++ b/arch/arm/boot/dts/omap3-evm.dts
@@ -0,0 +1,20 @@
+/*
+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+/dts-v1/;
+
+/include/ "omap3.dtsi"
+
+/ {
+        model = "TI OMAP3 EVM (OMAP3530, AM/DM37x)";
+        compatible = "ti,omap3-evm", "ti,omap3";
+
+        memory {
+                device_type = "memory";
+                reg = <0x80000000 0x10000000>; /* 256 MB */
+        };
+};
diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi
index 216c3317461..c6121357c1e 100644
--- a/arch/arm/boot/dts/omap3.dtsi
+++ b/arch/arm/boot/dts/omap3.dtsi
@@ -61,34 +61,57 @@
                 ranges;
                 ti,hwmods = "l3_main";
 
-                intc: interrupt-controller@1 {
-                        compatible = "ti,omap3-intc";
+                intc: interrupt-controller@48200000 {
+                        compatible = "ti,omap2-intc";
                         interrupt-controller;
                         #interrupt-cells = <1>;
+                        ti,intc-size = <96>;
+                        reg = <0x48200000 0x1000>;
                 };
 
-                uart1: serial@0x4806a000 {
+                uart1: serial@4806a000 {
                         compatible = "ti,omap3-uart";
                         ti,hwmods = "uart1";
                         clock-frequency = <48000000>;
                 };
 
-                uart2: serial@0x4806c000 {
+                uart2: serial@4806c000 {
                         compatible = "ti,omap3-uart";
                         ti,hwmods = "uart2";
                         clock-frequency = <48000000>;
                 };
 
-                uart3: serial@0x49020000 {
+                uart3: serial@49020000 {
                         compatible = "ti,omap3-uart";
                         ti,hwmods = "uart3";
                         clock-frequency = <48000000>;
                 };
 
-                uart4: serial@0x49042000 {
+                uart4: serial@49042000 {
                         compatible = "ti,omap3-uart";
                         ti,hwmods = "uart4";
                         clock-frequency = <48000000>;
                 };
+
+                i2c1: i2c@48070000 {
+                        compatible = "ti,omap3-i2c";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        ti,hwmods = "i2c1";
+                };
+
+                i2c2: i2c@48072000 {
+                        compatible = "ti,omap3-i2c";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        ti,hwmods = "i2c2";
+                };
+
+                i2c3: i2c@48060000 {
+                        compatible = "ti,omap3-i2c";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        ti,hwmods = "i2c3";
+                };
         };
 };
diff --git a/arch/arm/boot/dts/omap4-panda.dts b/arch/arm/boot/dts/omap4-panda.dts
index c7026578ce7..9755ad5917f 100644
--- a/arch/arm/boot/dts/omap4-panda.dts
+++ b/arch/arm/boot/dts/omap4-panda.dts
@@ -13,15 +13,6 @@
         model = "TI OMAP4 PandaBoard";
         compatible = "ti,omap4-panda", "ti,omap4430", "ti,omap4";
 
-        /*
-         * Since the initial device tree board file does not create any
-         * devices (MMC, network...), the only way to boot is to provide a
-         * ramdisk.
-         */
-        chosen {
-                bootargs = "root=/dev/ram0 rw console=ttyO2,115200n8 initrd=0x81600000,20M ramdisk_size=20480 no_console_suspend debug";
-        };
-
         memory {
                 device_type = "memory";
                 reg = <0x80000000 0x40000000>; /* 1 GB */
diff --git a/arch/arm/boot/dts/omap4-sdp.dts b/arch/arm/boot/dts/omap4-sdp.dts
index 066e28c9032..63c6b2b2bf4 100644
--- a/arch/arm/boot/dts/omap4-sdp.dts
+++ b/arch/arm/boot/dts/omap4-sdp.dts
@@ -13,15 +13,6 @@
         model = "TI OMAP4 SDP board";
         compatible = "ti,omap4-sdp", "ti,omap4430", "ti,omap4";
 
-        /*
-         * Since the initial device tree board file does not create any
-         * devices (MMC, network...), the only way to boot is to provide a
-         * ramdisk.
-         */
-        chosen {
-                bootargs = "root=/dev/ram0 rw console=ttyO2,115200n8 initrd=0x81600000,20M ramdisk_size=20480 no_console_suspend debug";
-        };
-
         memory {
                 device_type = "memory";
                 reg = <0x80000000 0x40000000>; /* 1 GB */
diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
index e8fe75fac7c..3d35559e77b 100644
--- a/arch/arm/boot/dts/omap4.dtsi
+++ b/arch/arm/boot/dts/omap4.dtsi
@@ -99,33 +99,61 @@
                 gic: interrupt-controller@48241000 {
                         compatible = "arm,cortex-a9-gic";
                         interrupt-controller;
-                        #interrupt-cells = <1>;
+                        #interrupt-cells = <3>;
                         reg = <0x48241000 0x1000>,
                               <0x48240100 0x0100>;
                 };
 
-                uart1: serial@0x4806a000 {
+                uart1: serial@4806a000 {
                         compatible = "ti,omap4-uart";
                         ti,hwmods = "uart1";
                         clock-frequency = <48000000>;
                 };
 
-                uart2: serial@0x4806c000 {
+                uart2: serial@4806c000 {
                         compatible = "ti,omap4-uart";
                         ti,hwmods = "uart2";
                         clock-frequency = <48000000>;
                 };
 
-                uart3: serial@0x48020000 {
+                uart3: serial@48020000 {
                         compatible = "ti,omap4-uart";
                         ti,hwmods = "uart3";
                         clock-frequency = <48000000>;
                 };
 
-                uart4: serial@0x4806e000 {
+                uart4: serial@4806e000 {
                         compatible = "ti,omap4-uart";
                         ti,hwmods = "uart4";
                         clock-frequency = <48000000>;
                 };
+
+                i2c1: i2c@48070000 {
+                        compatible = "ti,omap4-i2c";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        ti,hwmods = "i2c1";
+                };
+
+                i2c2: i2c@48072000 {
+                        compatible = "ti,omap4-i2c";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        ti,hwmods = "i2c2";
+                };
+
+                i2c3: i2c@48060000 {
+                        compatible = "ti,omap4-i2c";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        ti,hwmods = "i2c3";
+                };
+
+                i2c4: i2c@48350000 {
+                        compatible = "ti,omap4-i2c";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        ti,hwmods = "i2c4";
+                };
         };
 };
diff --git a/arch/arm/boot/dts/pxa168-aspenite.dts b/arch/arm/boot/dts/pxa168-aspenite.dts
new file mode 100644
index 00000000000..e762facb3fa
--- /dev/null
+++ b/arch/arm/boot/dts/pxa168-aspenite.dts
@@ -0,0 +1,38 @@
+/*
+ *  Copyright (C) 2012 Marvell Technology Group Ltd.
+ *  Author: Haojian Zhuang <haojian.zhuang@marvell.com>
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  publishhed by the Free Software Foundation.
+ */
+
+/dts-v1/;
+/include/ "pxa168.dtsi"
+
+/ {
+        model = "Marvell PXA168 Aspenite Development Board";
+        compatible = "mrvl,pxa168-aspenite", "mrvl,pxa168";
+
+        chosen {
+                bootargs = "console=ttyS0,115200 root=/dev/nfs nfsroot=192.168.1.100:/nfsroot/ ip=192.168.1.101:192.168.1.100::255.255.255.0::eth0:on";
+        };
+
+        memory {
+                reg = <0x00000000 0x04000000>;
+        };
+
+        soc {
+                apb@d4000000 {
+                        uart1: uart@d4017000 {
+                                status = "okay";
+                        };
+                        twsi1: i2c@d4011000 {
+                                status = "okay";
+                        };
+                        rtc: rtc@d4010000 {
+                                status = "okay";
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/pxa168.dtsi b/arch/arm/boot/dts/pxa168.dtsi
new file mode 100644
index 00000000000..d32d5128f22
--- /dev/null
+++ b/arch/arm/boot/dts/pxa168.dtsi
@@ -0,0 +1,98 @@
+/*
+ *  Copyright (C) 2012 Marvell Technology Group Ltd.
+ *  Author: Haojian Zhuang <haojian.zhuang@marvell.com>
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  publishhed by the Free Software Foundation.
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+        aliases {
+                serial0 = &uart1;
+                serial1 = &uart2;
+                serial2 = &uart3;
+                i2c0 = &twsi1;
+                i2c1 = &twsi2;
+        };
+
+        intc: intc-interrupt-controller@d4282000 {
+                compatible = "mrvl,mmp-intc", "mrvl,intc";
+                interrupt-controller;
+                #interrupt-cells = <1>;
+                reg = <0xd4282000 0x1000>;
+        };
+
+        soc {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "simple-bus";
+                interrupt-parent = <&intc>;
+                ranges;
+
+                apb@d4000000 {  /* APB */
+                        compatible = "mrvl,apb-bus", "simple-bus";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        reg = <0xd4000000 0x00200000>;
+                        ranges;
+
+                        uart1: uart@d4017000 {
+                                compatible = "mrvl,mmp-uart", "mrvl,pxa-uart";
+                                reg = <0xd4017000 0x1000>;
+                                interrupts = <27>;
+                                status = "disabled";
+                        };
+
+                        uart2: uart@d4018000 {
+                                compatible = "mrvl,mmp-uart", "mrvl,pxa-uart";
+                                reg = <0xd4018000 0x1000>;
+                                interrupts = <28>;
+                                status = "disabled";
+                        };
+
+                        uart3: uart@d4026000 {
+                                compatible = "mrvl,mmp-uart", "mrvl,pxa-uart";
+                                reg = <0xd4026000 0x1000>;
+                                interrupts = <29>;
+                                status = "disabled";
+                        };
+
+                        gpio: gpio@d4019000 {
+                                compatible = "mrvl,mmp-gpio", "mrvl,pxa-gpio";
+                                reg = <0xd4019000 0x1000>;
+                                interrupts = <49>;
+                                interrupt-names = "gpio_mux";
+                                gpio-controller;
+                                #gpio-cells = <1>;
+                                interrupt-controller;
+                                #interrupt-cells = <1>;
+                        };
+
+                        twsi1: i2c@d4011000 {
+                                compatible = "mrvl,mmp-twsi", "mrvl,pxa-i2c";
+                                reg = <0xd4011000 0x1000>;
+                                interrupts = <7>;
+                                mrvl,i2c-fast-mode;
+                                status = "disabled";
+                        };
+
+                        twsi2: i2c@d4025000 {
+                                compatible = "mrvl,mmp-twsi", "mrvl,pxa-i2c";
+                                reg = <0xd4025000 0x1000>;
+                                interrupts = <58>;
+                                status = "disabled";
+                        };
+
+                        rtc: rtc@d4010000 {
+                                compatible = "mrvl,mmp-rtc";
+                                reg = <0xd4010000 0x1000>;
+                                interrupts = <5 6>;
+                                interrupt-names = "rtc 1Hz", "rtc alarm";
+                                status = "disabled";
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/tegra-cardhu.dts b/arch/arm/boot/dts/tegra-cardhu.dts
index 70c41fc897d..73263501f58 100644
--- a/arch/arm/boot/dts/tegra-cardhu.dts
+++ b/arch/arm/boot/dts/tegra-cardhu.dts
@@ -33,4 +33,22 @@
         i2c@7000d000 {
                 clock-frequency = <100000>;
         };
+
+        sdhci@78000000 {
+                cd-gpios = <&gpio 69 0>; /* gpio PI5 */
+                wp-gpios = <&gpio 155 0>; /* gpio PT3 */
+                power-gpios = <&gpio 31 0>; /* gpio PD7 */
+        };
+
+        sdhci@78000200 {
+                status = "disable";
+        };
+
+        sdhci@78000400 {
+                status = "disable";
+        };
+
+        sdhci@78000400 {
+                support-8bit;
+        };
 };
diff --git a/arch/arm/boot/dts/tegra-harmony.dts b/arch/arm/boot/dts/tegra-harmony.dts
index 80afa1b70b8..6e8447dc020 100644
--- a/arch/arm/boot/dts/tegra-harmony.dts
+++ b/arch/arm/boot/dts/tegra-harmony.dts
@@ -10,19 +10,25 @@
                 reg = < 0x00000000 0x40000000 >;
         };
 
+        pmc@7000f400 {
+                nvidia,invert-interrupt;
+        };
+
         i2c@7000c000 {
                 clock-frequency = <400000>;
 
-                codec: wm8903@1a {
+                wm8903: wm8903@1a {
                         compatible = "wlf,wm8903";
                         reg = <0x1a>;
-                        interrupts = < 347 >;
+                        interrupt-parent = <&gpio>;
+                        interrupts = < 187 0x04 >;
 
                         gpio-controller;
                         #gpio-cells = <2>;
 
-                        /* 0x8000 = Not configured */
-                        gpio-cfg = < 0x8000 0x8000 0 0x8000 0x8000 >;
+                        micdet-cfg = <0>;
+                        micdet-delay = <100>;
+                        gpio-cfg = < 0xffffffff 0xffffffff 0 0xffffffff 0xffffffff >;
                 };
         };
 
@@ -38,13 +44,32 @@
                 clock-frequency = <400000>;
         };
 
-        sound {
-                compatible = "nvidia,harmony-sound", "nvidia,tegra-wm8903";
+        i2s@70002a00 {
+                status = "disable";
+        };
 
-                spkr-en-gpios = <&codec 2 0>;
-                hp-det-gpios = <&gpio 178 0>;
-                int-mic-en-gpios = <&gpio 184 0>;
-                ext-mic-en-gpios = <&gpio 185 0>;
+        sound {
+                compatible = "nvidia,tegra-audio-wm8903-harmony",
+                             "nvidia,tegra-audio-wm8903";
+                nvidia,model = "NVIDIA Tegra Harmony";
+
+                nvidia,audio-routing =
+                        "Headphone Jack", "HPOUTR",
+                        "Headphone Jack", "HPOUTL",
+                        "Int Spk", "ROP",
+                        "Int Spk", "RON",
+                        "Int Spk", "LOP",
+                        "Int Spk", "LON",
+                        "Mic Jack", "MICBIAS",
+                        "IN1L", "Mic Jack";
+
+                nvidia,i2s-controller = <&tegra_i2s1>;
+                nvidia,audio-codec = <&wm8903>;
+
+                nvidia,spkr-en-gpios = <&wm8903 2 0>;
+                nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
+                nvidia,int-mic-en-gpios = <&gpio 184 0>; /*gpio PX0 */
+                nvidia,ext-mic-en-gpios = <&gpio 185 0>; /* gpio PX1 */
         };
 
         serial@70006000 {
diff --git a/arch/arm/boot/dts/tegra-paz00.dts b/arch/arm/boot/dts/tegra-paz00.dts
index 825d2957da0..6c02abb469d 100644
--- a/arch/arm/boot/dts/tegra-paz00.dts
+++ b/arch/arm/boot/dts/tegra-paz00.dts
@@ -12,6 +12,13 @@
 
         i2c@7000c000 {
                 clock-frequency = <400000>;
+
+                alc5632: alc5632@1e {
+                        compatible = "realtek,alc5632";
+                        reg = <0x1e>;
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                };
         };
 
         i2c@7000c400 {
@@ -35,6 +42,35 @@
 
         i2c@7000d000 {
                 clock-frequency = <400000>;
+
+                adt7461@4c {
+                        compatible = "adi,adt7461";
+                        reg = <0x4c>;
+                };
+        };
+
+        i2s@70002a00 {
+                status = "disable";
+        };
+
+        sound {
+                compatible = "nvidia,tegra-audio-alc5632-paz00",
+                        "nvidia,tegra-audio-alc5632";
+
+                nvidia,model = "Compal PAZ00";
+
+                nvidia,audio-routing =
+                        "Int Spk", "SPKOUT",
+                        "Int Spk", "SPKOUTN",
+                        "Headset Mic", "MICBIAS1",
+                        "MIC1", "Headset Mic",
+                        "Headset Stereophone", "HPR",
+                        "Headset Stereophone", "HPL",
+                        "DMICDAT", "Digital Mic";
+
+                nvidia,audio-codec = <&alc5632>;
+                nvidia,i2s-controller = <&tegra_i2s1>;
+                nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
         };
 
         serial@70006000 {
@@ -74,4 +110,25 @@
         sdhci@c8000600 {
                 support-8bit;
         };
+
+        gpio-keys {
+                compatible = "gpio-keys";
+
+                power {
+                        label = "Power";
+                        gpios = <&gpio 79 1>; /* gpio PJ7, active low */
+                        linux,code = <116>; /* KEY_POWER */
+                        gpio-key,wakeup;
+                };
+        };
+
+        gpio-leds {
+                compatible = "gpio-leds";
+
+                wifi {
+                        label = "wifi-led";
+                        gpios = <&gpio 24 0>;
+                        linux,default-trigger = "rfkill0";
+                };
+        };
 };
diff --git a/arch/arm/boot/dts/tegra-seaboard.dts b/arch/arm/boot/dts/tegra-seaboard.dts
index b55a02e34ba..876d5c92ce3 100644
--- a/arch/arm/boot/dts/tegra-seaboard.dts
+++ b/arch/arm/boot/dts/tegra-seaboard.dts
@@ -13,6 +13,20 @@
 
         i2c@7000c000 {
                 clock-frequency = <400000>;
+
+                wm8903: wm8903@1a {
+                        compatible = "wlf,wm8903";
+                        reg = <0x1a>;
+                        interrupt-parent = <&gpio>;
+                        interrupts = < 187 0x04 >;
+
+                        gpio-controller;
+                        #gpio-cells = <2>;
+
+                        micdet-cfg = <0>;
+                        micdet-delay = <100>;
+                        gpio-cfg = < 0xffffffff 0xffffffff 0 0xffffffff 0xffffffff >;
+                };
         };
 
         i2c@7000c400 {
@@ -32,6 +46,32 @@
                 };
         };
 
+        i2s@70002a00 {
+                status = "disable";
+        };
+
+        sound {
+                compatible = "nvidia,tegra-audio-wm8903-seaboard",
+                             "nvidia,tegra-audio-wm8903";
+                nvidia,model = "NVIDIA Tegra Seaboard";
+
+                nvidia,audio-routing =
+                        "Headphone Jack", "HPOUTR",
+                        "Headphone Jack", "HPOUTL",
+                        "Int Spk", "ROP",
+                        "Int Spk", "RON",
+                        "Int Spk", "LOP",
+                        "Int Spk", "LON",
+                        "Mic Jack", "MICBIAS",
+                        "IN1R", "Mic Jack";
+
+                nvidia,i2s-controller = <&tegra_i2s1>;
+                nvidia,audio-codec = <&wm8903>;
+
+                nvidia,spkr-en-gpios = <&wm8903 2 0>;
+                nvidia,hp-det-gpios = <&gpio 185 0>; /* gpio PX1 */
+        };
+
         serial@70006000 {
                 status = "disable";
         };
@@ -93,4 +133,42 @@
                         gpio-key,wakeup;
                 };
         };
+
+        emc@7000f400 {
+                emc-table@190000 {
+                        reg = < 190000 >;
+                        compatible = "nvidia,tegra20-emc-table";
+                        clock-frequency = < 190000 >;
+                        nvidia,emc-registers = < 0x0000000c 0x00000026
+                                0x00000009 0x00000003 0x00000004 0x00000004
+                                0x00000002 0x0000000c 0x00000003 0x00000003
+                                0x00000002 0x00000001 0x00000004 0x00000005
+                                0x00000004 0x00000009 0x0000000d 0x0000059f
+                                0x00000000 0x00000003 0x00000003 0x00000003
+                                0x00000003 0x00000001 0x0000000b 0x000000c8
+                                0x00000003 0x00000007 0x00000004 0x0000000f
+                                0x00000002 0x00000000 0x00000000 0x00000002
+                                0x00000000 0x00000000 0x00000083 0xa06204ae
+                                0x007dc010 0x00000000 0x00000000 0x00000000
+                                0x00000000 0x00000000 0x00000000 0x00000000 >;
+                };
+
+                emc-table@380000 {
+                        reg = < 380000 >;
+                        compatible = "nvidia,tegra20-emc-table";
+                        clock-frequency = < 380000 >;
+                        nvidia,emc-registers = < 0x00000017 0x0000004b
+                                0x00000012 0x00000006 0x00000004 0x00000005
+                                0x00000003 0x0000000c 0x00000006 0x00000006
+                                0x00000003 0x00000001 0x00000004 0x00000005
+                                0x00000004 0x00000009 0x0000000d 0x00000b5f
+                                0x00000000 0x00000003 0x00000003 0x00000006
+                                0x00000006 0x00000001 0x00000011 0x000000c8
+                                0x00000003 0x0000000e 0x00000007 0x0000000f
+                                0x00000002 0x00000000 0x00000000 0x00000002
+                                0x00000000 0x00000000 0x00000083 0xe044048b
+                                0x007d8010 0x00000000 0x00000000 0x00000000
+                                0x00000000 0x00000000 0x00000000 0x00000000 >;
+                };
+        };
 };
diff --git a/arch/arm/boot/dts/tegra-trimslice.dts b/arch/arm/boot/dts/tegra-trimslice.dts
index 3b3ee7db99f..252476867b5 100644
--- a/arch/arm/boot/dts/tegra-trimslice.dts
+++ b/arch/arm/boot/dts/tegra-trimslice.dts
@@ -26,6 +26,18 @@
                 status = "disable";
         };
 
+        i2s@70002800 {
+                status = "disable";
+        };
+
+        i2s@70002a00 {
+                status = "disable";
+        };
+
+        das@70000c00 {
+                status = "disable";
+        };
+
         serial@70006000 {
                 clock-frequency = < 216000000 >;
         };
diff --git a/arch/arm/boot/dts/tegra-ventana.dts b/arch/arm/boot/dts/tegra-ventana.dts
index c7d3b87f29d..2dcff8728e9 100644
--- a/arch/arm/boot/dts/tegra-ventana.dts
+++ b/arch/arm/boot/dts/tegra-ventana.dts
@@ -12,6 +12,20 @@
 
         i2c@7000c000 {
                 clock-frequency = <400000>;
+
+                wm8903: wm8903@1a {
+                        compatible = "wlf,wm8903";
+                        reg = <0x1a>;
+                        interrupt-parent = <&gpio>;
+                        interrupts = < 187 0x04 >;
+
+                        gpio-controller;
+                        #gpio-cells = <2>;
+
+                        micdet-cfg = <0>;
+                        micdet-delay = <100>;
+                        gpio-cfg = < 0xffffffff 0xffffffff 0 0xffffffff 0xffffffff >;
+                };
         };
 
         i2c@7000c400 {
@@ -26,6 +40,34 @@
                 clock-frequency = <400000>;
         };
 
+        i2s@70002a00 {
+                status = "disable";
+        };
+
+        sound {
+                compatible = "nvidia,tegra-audio-wm8903-ventana",
+                             "nvidia,tegra-audio-wm8903";
+                nvidia,model = "NVIDIA Tegra Ventana";
+
+                nvidia,audio-routing =
+                        "Headphone Jack", "HPOUTR",
+                        "Headphone Jack", "HPOUTL",
+                        "Int Spk", "ROP",
+                        "Int Spk", "RON",
+                        "Int Spk", "LOP",
+                        "Int Spk", "LON",
+                        "Mic Jack", "MICBIAS",
+                        "IN1L", "Mic Jack";
+
+                nvidia,i2s-controller = <&tegra_i2s1>;
+                nvidia,audio-codec = <&wm8903>;
+
+                nvidia,spkr-en-gpios = <&wm8903 2 0>;
+                nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
+                nvidia,int-mic-en-gpios = <&gpio 184 0>; /*gpio PX0 */
+                nvidia,ext-mic-en-gpios = <&gpio 185 0>; /* gpio PX1 */
+        };
+
         serial@70006000 {
                 status = "disable";
         };
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
index 3da7afd4532..aff8a175aa4 100644
--- a/arch/arm/boot/dts/tegra20.dtsi
+++ b/arch/arm/boot/dts/tegra20.dtsi
@@ -4,6 +4,11 @@
         compatible = "nvidia,tegra20";
         interrupt-parent = <&intc>;
 
+        pmc@7000f400 {
+                compatible = "nvidia,tegra20-pmc";
+                reg = <0x7000e400 0x400>;
+        };
+
         intc: interrupt-controller@50041000 {
                 compatible = "arm,cortex-a9-gic";
                 interrupt-controller;
@@ -12,6 +17,33 @@
                       < 0x50040100 0x0100 >;
         };
 
+        pmu {
+                compatible = "arm,cortex-a9-pmu";
+                interrupts = <0 56 0x04
+                              0 57 0x04>;
+        };
+
+        apbdma: dma@6000a000 {
+                compatible = "nvidia,tegra20-apbdma";
+                reg = <0x6000a000 0x1200>;
+                interrupts = < 0 104 0x04
+                               0 105 0x04
+                               0 106 0x04
+                               0 107 0x04
+                               0 108 0x04
+                               0 109 0x04
+                               0 110 0x04
+                               0 111 0x04
+                               0 112 0x04
+                               0 113 0x04
+                               0 114 0x04
+                               0 115 0x04
+                               0 116 0x04
+                               0 117 0x04
+                               0 118 0x04
+                               0 119 0x04 >;
+        };
+
         i2c@7000c000 {
                 #address-cells = <1>;
                 #size-cells = <0>;
@@ -44,18 +76,18 @@
                 interrupts = < 0 53 0x04 >;
         };
 
-        i2s@70002800 {
+        tegra_i2s1: i2s@70002800 {
                 compatible = "nvidia,tegra20-i2s";
                 reg = <0x70002800 0x200>;
                 interrupts = < 0 13 0x04 >;
-                dma-channel = < 2 >;
+                nvidia,dma-request-selector = < &apbdma 2 >;
         };
 
-        i2s@70002a00 {
+        tegra_i2s2: i2s@70002a00 {
                 compatible = "nvidia,tegra20-i2s";
                 reg = <0x70002a00 0x200>;
                 interrupts = < 0 3 0x04 >;
-                dma-channel = < 1 >;
+                nvidia,dma-request-selector = < &apbdma 1 >;
         };
 
         das@70000c00 {
@@ -75,6 +107,8 @@
                                0 89 0x04 >;
                 #gpio-cells = <2>;
                 gpio-controller;
+                #interrupt-cells = <2>;
+                interrupt-controller;
         };
 
         pinmux: pinmux@70000000 {
@@ -120,6 +154,13 @@
                 interrupts = < 0 91 0x04 >;
         };
 
+        emc@7000f400 {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                compatible = "nvidia,tegra20-emc";
+                reg = <0x7000f400 0x200>;
+        };
+
         sdhci@c8000000 {
                 compatible = "nvidia,tegra20-sdhci";
                 reg = <0xc8000000 0x200>;
diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi
index ee7db9892e0..62a7b39f1c9 100644
--- a/arch/arm/boot/dts/tegra30.dtsi
+++ b/arch/arm/boot/dts/tegra30.dtsi
@@ -4,6 +4,11 @@
         compatible = "nvidia,tegra30";
         interrupt-parent = <&intc>;
 
+        pmc@7000f400 {
+                compatible = "nvidia,tegra20-pmc", "nvidia,tegra30-pmc";
+                reg = <0x7000e400 0x400>;
+        };
+
         intc: interrupt-controller@50041000 {
                 compatible = "arm,cortex-a9-gic";
                 interrupt-controller;
@@ -12,6 +17,51 @@
                       < 0x50040100 0x0100 >;
         };
 
+        pmu {
+                compatible = "arm,cortex-a9-pmu";
+                interrupts = <0 144 0x04
+                              0 145 0x04
+                              0 146 0x04
+                              0 147 0x04>;
+        };
+
+        apbdma: dma@6000a000 {
+                compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma";
+                reg = <0x6000a000 0x1400>;
+                interrupts = < 0 104 0x04
+                               0 105 0x04
+                               0 106 0x04
+                               0 107 0x04
+                               0 108 0x04
+                               0 109 0x04
+                               0 110 0x04
+                               0 111 0x04
+                               0 112 0x04
+                               0 113 0x04
+                               0 114 0x04
+                               0 115 0x04
+                               0 116 0x04
+                               0 117 0x04
+                               0 118 0x04
+                               0 119 0x04
+                               0 128 0x04
+                               0 129 0x04
+                               0 130 0x04
+                               0 131 0x04
+                               0 132 0x04
+                               0 133 0x04
+                               0 134 0x04
+                               0 135 0x04
+                               0 136 0x04
+                               0 137 0x04
+                               0 138 0x04
+                               0 139 0x04
+                               0 140 0x04
+                               0 141 0x04
+                               0 142 0x04
+                               0 143 0x04 >;
+        };
+
         i2c@7000c000 {
                 #address-cells = <1>;
                 #size-cells = <0>;
@@ -55,9 +105,18 @@
         gpio: gpio@6000d000 {
                 compatible = "nvidia,tegra30-gpio", "nvidia,tegra20-gpio";
                 reg = < 0x6000d000 0x1000 >;
-                interrupts = < 0 32 0x04 0 33 0x04 0 34 0x04 0 35 0x04 0 55 0x04 0 87 0x04 0 89 0x04 >;
+                interrupts = < 0 32 0x04
+                               0 33 0x04
+                               0 34 0x04
+                               0 35 0x04
+                               0 55 0x04
+                               0 87 0x04
+                               0 89 0x04
+                               0 125 0x04 >;
                 #gpio-cells = <2>;
                 gpio-controller;
+                #interrupt-cells = <2>;
+                interrupt-controller;
         };
 
         serial@70006000 {
diff --git a/arch/arm/boot/dts/usb_a9g20.dts b/arch/arm/boot/dts/usb_a9g20.dts
index f04b535477f..d74545a2a77 100644
--- a/arch/arm/boot/dts/usb_a9g20.dts
+++ b/arch/arm/boot/dts/usb_a9g20.dts
@@ -32,4 +32,27 @@
                         };
                 };
         };
+
+        leds {
+                compatible = "gpio-leds";
+
+                user_led {
+                        label = "user_led";
+                        gpios = <&pioB 21 1>;
+                        linux,default-trigger = "heartbeat";
+                };
+        };
+
+        gpio_keys {
+                compatible = "gpio-keys";
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                user_pb {
+                        label = "user_pb";
+                        gpios = <&pioB 10 1>;
+                        linux,code = <28>;
+                        gpio-key,wakeup;
+                };
+        };
 };
diff --git a/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi b/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi
new file mode 100644
index 00000000000..16076e2d093
--- /dev/null
+++ b/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi
@@ -0,0 +1,201 @@
+/*
+ * ARM Ltd. Versatile Express
+ *
+ * Motherboard Express uATX
+ * V2M-P1
+ *
+ * HBI-0190D
+ *
+ * RS1 memory map ("ARM Cortex-A Series memory map" in the board's
+ * Technical Reference Manual)
+ *
+ * WARNING! The hardware described in this file is independent from the
+ * original variant (vexpress-v2m.dtsi), but there is a strong
+ * correspondence between the two configurations.
+ *
+ * TAKE CARE WHEN MAINTAINING THIS FILE TO PROPAGATE ANY RELEVANT
+ * CHANGES TO vexpress-v2m.dtsi!
+ */
+
+/ {
+        aliases {
+                arm,v2m_timer = &v2m_timer01;
+        };
+
+        motherboard {
+                compatible = "simple-bus";
+                arm,v2m-memory-map = "rs1";
+                #address-cells = <2>; /* SMB chipselect number and offset */
+                #size-cells = <1>;
+                #interrupt-cells = <1>;
+
+                flash@0,00000000 {
+                        compatible = "arm,vexpress-flash", "cfi-flash";
+                        reg = <0 0x00000000 0x04000000>,
+                              <4 0x00000000 0x04000000>;
+                        bank-width = <4>;
+                };
+
+                psram@1,00000000 {
+                        compatible = "arm,vexpress-psram", "mtd-ram";
+                        reg = <1 0x00000000 0x02000000>;
+                        bank-width = <4>;
+                };
+
+                vram@2,00000000 {
+                        compatible = "arm,vexpress-vram";
+                        reg = <2 0x00000000 0x00800000>;
+                };
+
+                ethernet@2,02000000 {
+                        compatible = "smsc,lan9118", "smsc,lan9115";
+                        reg = <2 0x02000000 0x10000>;
+                        interrupts = <15>;
+                        phy-mode = "mii";
+                        reg-io-width = <4>;
+                        smsc,irq-active-high;
+                        smsc,irq-push-pull;
+                };
+
+                usb@2,03000000 {
+                        compatible = "nxp,usb-isp1761";
+                        reg = <2 0x03000000 0x20000>;
+                        interrupts = <16>;
+                        port1-otg;
+                };
+
+                iofpga@3,00000000 {
+                        compatible = "arm,amba-bus", "simple-bus";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges = <0 3 0 0x200000>;
+
+                        sysreg@010000 {
+                                compatible = "arm,vexpress-sysreg";
+                                reg = <0x010000 0x1000>;
+                        };
+
+                        sysctl@020000 {
+                                compatible = "arm,sp810", "arm,primecell";
+                                reg = <0x020000 0x1000>;
+                        };
+
+                        /* PCI-E I2C bus */
+                        v2m_i2c_pcie: i2c@030000 {
+                                compatible = "arm,versatile-i2c";
+                                reg = <0x030000 0x1000>;
+
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+
+                                pcie-switch@60 {
+                                        compatible = "idt,89hpes32h8";
+                                        reg = <0x60>;
+                                };
+                        };
+
+                        aaci@040000 {
+                                compatible = "arm,pl041", "arm,primecell";
+                                reg = <0x040000 0x1000>;
+                                interrupts = <11>;
+                        };
+
+                        mmci@050000 {
+                                compatible = "arm,pl180", "arm,primecell";
+                                reg = <0x050000 0x1000>;
+                                interrupts = <9 10>;
+                        };
+
+                        kmi@060000 {
+                                compatible = "arm,pl050", "arm,primecell";
+                                reg = <0x060000 0x1000>;
+                                interrupts = <12>;
+                        };
+
+                        kmi@070000 {
+                                compatible = "arm,pl050", "arm,primecell";
+                                reg = <0x070000 0x1000>;
+                                interrupts = <13>;
+                        };
+
+                        v2m_serial0: uart@090000 {
+                                compatible = "arm,pl011", "arm,primecell";
+                                reg = <0x090000 0x1000>;
+                                interrupts = <5>;
+                        };
+
+                        v2m_serial1: uart@0a0000 {
+                                compatible = "arm,pl011", "arm,primecell";
+                                reg = <0x0a0000 0x1000>;
+                                interrupts = <6>;
+                        };
+
+                        v2m_serial2: uart@0b0000 {
+                                compatible = "arm,pl011", "arm,primecell";
+                                reg = <0x0b0000 0x1000>;
+                                interrupts = <7>;
+                        };
+
+                        v2m_serial3: uart@0c0000 {
+                                compatible = "arm,pl011", "arm,primecell";
+                                reg = <0x0c0000 0x1000>;
+                                interrupts = <8>;
+                        };
+
+                        wdt@0f0000 {
+                                compatible = "arm,sp805", "arm,primecell";
+                                reg = <0x0f0000 0x1000>;
+                                interrupts = <0>;
+                        };
+
+                        v2m_timer01: timer@110000 {
+                                compatible = "arm,sp804", "arm,primecell";
+                                reg = <0x110000 0x1000>;
+                                interrupts = <2>;
+                        };
+
+                        v2m_timer23: timer@120000 {
+                                compatible = "arm,sp804", "arm,primecell";
+                                reg = <0x120000 0x1000>;
+                        };
+
+                        /* DVI I2C bus */
+                        v2m_i2c_dvi: i2c@160000 {
+                                compatible = "arm,versatile-i2c";
+                                reg = <0x160000 0x1000>;
+
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+
+                                dvi-transmitter@39 {
+                                        compatible = "sil,sii9022-tpi", "sil,sii9022";
+                                        reg = <0x39>;
+                                };
+
+                                dvi-transmitter@60 {
+                                        compatible = "sil,sii9022-cpi", "sil,sii9022";
+                                        reg = <0x60>;
+                                };
+                        };
+
+                        rtc@170000 {
+                                compatible = "arm,pl031", "arm,primecell";
+                                reg = <0x170000 0x1000>;
+                                interrupts = <4>;
+                        };
+
+                        compact-flash@1a0000 {
+                                compatible = "arm,vexpress-cf", "ata-generic";
+                                reg = <0x1a0000 0x100
+                                       0x1a0100 0xf00>;
+                                reg-shift = <2>;
+                        };
+
+                        clcd@1f0000 {
+                                compatible = "arm,pl111", "arm,primecell";
+                                reg = <0x1f0000 0x1000>;
+                                interrupts = <14>;
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/vexpress-v2m.dtsi b/arch/arm/boot/dts/vexpress-v2m.dtsi
new file mode 100644
index 00000000000..a6c9c7c82d5
--- /dev/null
+++ b/arch/arm/boot/dts/vexpress-v2m.dtsi
@@ -0,0 +1,200 @@
+/*
+ * ARM Ltd. Versatile Express
+ *
+ * Motherboard Express uATX
+ * V2M-P1
+ *
+ * HBI-0190D
+ *
+ * Original memory map ("Legacy memory map" in the board's
+ * Technical Reference Manual)
+ *
+ * WARNING! The hardware described in this file is independent from the
+ * RS1 variant (vexpress-v2m-rs1.dtsi), but there is a strong
+ * correspondence between the two configurations.
+ *
+ * TAKE CARE WHEN MAINTAINING THIS FILE TO PROPAGATE ANY RELEVANT
+ * CHANGES TO vexpress-v2m-rs1.dtsi!
+ */
+
+/ {
+        aliases {
+                arm,v2m_timer = &v2m_timer01;
+        };
+
+        motherboard {
+                compatible = "simple-bus";
+                #address-cells = <2>; /* SMB chipselect number and offset */
+                #size-cells = <1>;
+                #interrupt-cells = <1>;
+
+                flash@0,00000000 {
+                        compatible = "arm,vexpress-flash", "cfi-flash";
+                        reg = <0 0x00000000 0x04000000>,
+                              <1 0x00000000 0x04000000>;
+                        bank-width = <4>;
+                };
+
+                psram@2,00000000 {
+                        compatible = "arm,vexpress-psram", "mtd-ram";
+                        reg = <2 0x00000000 0x02000000>;
+                        bank-width = <4>;
+                };
+
+                vram@3,00000000 {
+                        compatible = "arm,vexpress-vram";
+                        reg = <3 0x00000000 0x00800000>;
+                };
+
+                ethernet@3,02000000 {
+                        compatible = "smsc,lan9118", "smsc,lan9115";
+                        reg = <3 0x02000000 0x10000>;
+                        interrupts = <15>;
+                        phy-mode = "mii";
+                        reg-io-width = <4>;
+                        smsc,irq-active-high;
+                        smsc,irq-push-pull;
+                };
+
+                usb@3,03000000 {
+                        compatible = "nxp,usb-isp1761";
+                        reg = <3 0x03000000 0x20000>;
+                        interrupts = <16>;
+                        port1-otg;
+                };
+
+                iofpga@7,00000000 {
+                        compatible = "arm,amba-bus", "simple-bus";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges = <0 7 0 0x20000>;
+
+                        sysreg@00000 {
+                                compatible = "arm,vexpress-sysreg";
+                                reg = <0x00000 0x1000>;
+                        };
+
+                        sysctl@01000 {
+                                compatible = "arm,sp810", "arm,primecell";
+                                reg = <0x01000 0x1000>;
+                        };
+
+                        /* PCI-E I2C bus */
+                        v2m_i2c_pcie: i2c@02000 {
+                                compatible = "arm,versatile-i2c";
+                                reg = <0x02000 0x1000>;
+
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+
+                                pcie-switch@60 {
+                                        compatible = "idt,89hpes32h8";
+                                        reg = <0x60>;
+                                };
+                        };
+
+                        aaci@04000 {
+                                compatible = "arm,pl041", "arm,primecell";
+                                reg = <0x04000 0x1000>;
+                                interrupts = <11>;
+                        };
+
+                        mmci@05000 {
+                                compatible = "arm,pl180", "arm,primecell";
+                                reg = <0x05000 0x1000>;
+                                interrupts = <9 10>;
+                        };
+
+                        kmi@06000 {
+                                compatible = "arm,pl050", "arm,primecell";
+                                reg = <0x06000 0x1000>;
+                                interrupts = <12>;
+                        };
+
+                        kmi@07000 {
+                                compatible = "arm,pl050", "arm,primecell";
+                                reg = <0x07000 0x1000>;
+                                interrupts = <13>;
+                        };
+
+                        v2m_serial0: uart@09000 {
+                                compatible = "arm,pl011", "arm,primecell";
+                                reg = <0x09000 0x1000>;
+                                interrupts = <5>;
+                        };
+
+                        v2m_serial1: uart@0a000 {
+                                compatible = "arm,pl011", "arm,primecell";
+                                reg = <0x0a000 0x1000>;
+                                interrupts = <6>;
+                        };
+
+                        v2m_serial2: uart@0b000 {
+                                compatible = "arm,pl011", "arm,primecell";
+                                reg = <0x0b000 0x1000>;
+                                interrupts = <7>;
+                        };
+
+                        v2m_serial3: uart@0c000 {
+                                compatible = "arm,pl011", "arm,primecell";
+                                reg = <0x0c000 0x1000>;
+                                interrupts = <8>;
+                        };
+
+                        wdt@0f000 {
+                                compatible = "arm,sp805", "arm,primecell";
+                                reg = <0x0f000 0x1000>;
+                                interrupts = <0>;
+                        };
+
+                        v2m_timer01: timer@11000 {
+                                compatible = "arm,sp804", "arm,primecell";
+                                reg = <0x11000 0x1000>;
+                                interrupts = <2>;
+                        };
+
+                        v2m_timer23: timer@12000 {
+                                compatible = "arm,sp804", "arm,primecell";
+                                reg = <0x12000 0x1000>;
+                        };
+
+                        /* DVI I2C bus */
+                        v2m_i2c_dvi: i2c@16000 {
+                                compatible = "arm,versatile-i2c";
+                                reg = <0x16000 0x1000>;
+
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+
+                                dvi-transmitter@39 {
+                                        compatible = "sil,sii9022-tpi", "sil,sii9022";
+                                        reg = <0x39>;
+                                };
+
+                                dvi-transmitter@60 {
+                                        compatible = "sil,sii9022-cpi", "sil,sii9022";
+                                        reg = <0x60>;
+                                };
+                        };
+
+                        rtc@17000 {
+                                compatible = "arm,pl031", "arm,primecell";
+                                reg = <0x17000 0x1000>;
+                                interrupts = <4>;
+                        };
+
+                        compact-flash@1a000 {
+                                compatible = "arm,vexpress-cf", "ata-generic";
+                                reg = <0x1a000 0x100
+                                       0x1a100 0xf00>;
+                                reg-shift = <2>;
+                        };
+
+                        clcd@1f000 {
+                                compatible = "arm,pl111", "arm,primecell";
+                                reg = <0x1f000 0x1000>;
+                                interrupts = <14>;
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts b/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts
new file mode 100644
index 00000000000..941b161ab78
--- /dev/null
+++ b/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts
@@ -0,0 +1,157 @@
+/*
+ * ARM Ltd. Versatile Express
+ *
+ * CoreTile Express A15x2 (version with Test Chip 1)
+ * Cortex-A15 MPCore (V2P-CA15)
+ *
+ * HBI-0237A
+ */
+
+/dts-v1/;
+
+/ {
+        model = "V2P-CA15";
+        arm,hbi = <0x237>;
+        compatible = "arm,vexpress,v2p-ca15,tc1", "arm,vexpress,v2p-ca15", "arm,vexpress";
+        interrupt-parent = <&gic>;
+        #address-cells = <1>;
+        #size-cells = <1>;
+
+        chosen { };
+
+        aliases {
+                serial0 = &v2m_serial0;
+                serial1 = &v2m_serial1;
+                serial2 = &v2m_serial2;
+                serial3 = &v2m_serial3;
+                i2c0 = &v2m_i2c_dvi;
+                i2c1 = &v2m_i2c_pcie;
+        };
+
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                cpu@0 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a15";
+                        reg = <0>;
+                };
+
+                cpu@1 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a15";
+                        reg = <1>;
+                };
+        };
+
+        memory@80000000 {
+                device_type = "memory";
+                reg = <0x80000000 0x40000000>;
+        };
+
+        hdlcd@2b000000 {
+                compatible = "arm,hdlcd";
+                reg = <0x2b000000 0x1000>;
+                interrupts = <0 85 4>;
+        };
+
+        memory-controller@2b0a0000 {
+                compatible = "arm,pl341", "arm,primecell";
+                reg = <0x2b0a0000 0x1000>;
+        };
+
+        wdt@2b060000 {
+                compatible = "arm,sp805", "arm,primecell";
+                reg = <0x2b060000 0x1000>;
+                interrupts = <98>;
+        };
+
+        gic: interrupt-controller@2c001000 {
+                compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
+                #interrupt-cells = <3>;
+                #address-cells = <0>;
+                interrupt-controller;
+                reg = <0x2c001000 0x1000>,
+                      <0x2c002000 0x100>;
+        };
+
+        memory-controller@7ffd0000 {
+                compatible = "arm,pl354", "arm,primecell";
+                reg = <0x7ffd0000 0x1000>;
+                interrupts = <0 86 4>,
+                             <0 87 4>;
+        };
+
+        dma@7ffb0000 {
+                compatible = "arm,pl330", "arm,primecell";
+                reg = <0x7ffb0000 0x1000>;
+                interrupts = <0 92 4>,
+                             <0 88 4>,
+                             <0 89 4>,
+                             <0 90 4>,
+                             <0 91 4>;
+        };
+
+        pmu {
+                compatible = "arm,cortex-a15-pmu", "arm,cortex-a9-pmu";
+                interrupts = <0 68 4>,
+                             <0 69 4>;
+        };
+
+        motherboard {
+                ranges = <0 0 0x08000000 0x04000000>,
+                         <1 0 0x14000000 0x04000000>,
+                         <2 0 0x18000000 0x04000000>,
+                         <3 0 0x1c000000 0x04000000>,
+                         <4 0 0x0c000000 0x04000000>,
+                         <5 0 0x10000000 0x04000000>;
+
+                interrupt-map-mask = <0 0 63>;
+                interrupt-map = <0 0  0 &gic 0  0 4>,
+                                <0 0  1 &gic 0  1 4>,
+                                <0 0  2 &gic 0  2 4>,
+                                <0 0  3 &gic 0  3 4>,
+                                <0 0  4 &gic 0  4 4>,
+                                <0 0  5 &gic 0  5 4>,
+                                <0 0  6 &gic 0  6 4>,
+                                <0 0  7 &gic 0  7 4>,
+                                <0 0  8 &gic 0  8 4>,
+                                <0 0  9 &gic 0  9 4>,
+                                <0 0 10 &gic 0 10 4>,
+                                <0 0 11 &gic 0 11 4>,
+                                <0 0 12 &gic 0 12 4>,
+                                <0 0 13 &gic 0 13 4>,
+                                <0 0 14 &gic 0 14 4>,
+                                <0 0 15 &gic 0 15 4>,
+                                <0 0 16 &gic 0 16 4>,
+                                <0 0 17 &gic 0 17 4>,
+                                <0 0 18 &gic 0 18 4>,
+                                <0 0 19 &gic 0 19 4>,
+                                <0 0 20 &gic 0 20 4>,
+                                <0 0 21 &gic 0 21 4>,
+                                <0 0 22 &gic 0 22 4>,
+                                <0 0 23 &gic 0 23 4>,
+                                <0 0 24 &gic 0 24 4>,
+                                <0 0 25 &gic 0 25 4>,
+                                <0 0 26 &gic 0 26 4>,
+                                <0 0 27 &gic 0 27 4>,
+                                <0 0 28 &gic 0 28 4>,
+                                <0 0 29 &gic 0 29 4>,
+                                <0 0 30 &gic 0 30 4>,
+                                <0 0 31 &gic 0 31 4>,
+                                <0 0 32 &gic 0 32 4>,
+                                <0 0 33 &gic 0 33 4>,
+                                <0 0 34 &gic 0 34 4>,
+                                <0 0 35 &gic 0 35 4>,
+                                <0 0 36 &gic 0 36 4>,
+                                <0 0 37 &gic 0 37 4>,
+                                <0 0 38 &gic 0 38 4>,
+                                <0 0 39 &gic 0 39 4>,
+                                <0 0 40 &gic 0 40 4>,
+                                <0 0 41 &gic 0 41 4>,
+                                <0 0 42 &gic 0 42 4>;
+        };
+};
+
+/include/ "vexpress-v2m-rs1.dtsi"
diff --git a/arch/arm/boot/dts/vexpress-v2p-ca5s.dts b/arch/arm/boot/dts/vexpress-v2p-ca5s.dts
new file mode 100644
index 00000000000..6905e66d474
--- /dev/null
+++ b/arch/arm/boot/dts/vexpress-v2p-ca5s.dts
@@ -0,0 +1,162 @@
+/*
+ * ARM Ltd. Versatile Express
+ *
+ * CoreTile Express A5x2
+ * Cortex-A5 MPCore (V2P-CA5s)
+ *
+ * HBI-0225B
+ */
+
+/dts-v1/;
+
+/ {
+        model = "V2P-CA5s";
+        arm,hbi = <0x225>;
+        compatible = "arm,vexpress,v2p-ca5s", "arm,vexpress";
+        interrupt-parent = <&gic>;
+        #address-cells = <1>;
+        #size-cells = <1>;
+
+        chosen { };
+
+        aliases {
+                serial0 = &v2m_serial0;
+                serial1 = &v2m_serial1;
+                serial2 = &v2m_serial2;
+                serial3 = &v2m_serial3;
+                i2c0 = &v2m_i2c_dvi;
+                i2c1 = &v2m_i2c_pcie;
+        };
+
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                cpu@0 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a5";
+                        reg = <0>;
+                        next-level-cache = <&L2>;
+                };
+
+                cpu@1 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a5";
+                        reg = <1>;
+                        next-level-cache = <&L2>;
+                };
+        };
+
+        memory@80000000 {
+                device_type = "memory";
+                reg = <0x80000000 0x40000000>;
+        };
+
+        hdlcd@2a110000 {
+                compatible = "arm,hdlcd";
+                reg = <0x2a110000 0x1000>;
+                interrupts = <0 85 4>;
+        };
+
+        memory-controller@2a150000 {
+                compatible = "arm,pl341", "arm,primecell";
+                reg = <0x2a150000 0x1000>;
+        };
+
+        memory-controller@2a190000 {
+                compatible = "arm,pl354", "arm,primecell";
+                reg = <0x2a190000 0x1000>;
+                interrupts = <0 86 4>,
+                             <0 87 4>;
+        };
+
+        scu@2c000000 {
+                compatible = "arm,cortex-a5-scu";
+                reg = <0x2c000000 0x58>;
+        };
+
+        timer@2c000600 {
+                compatible = "arm,cortex-a5-twd-timer";
+                reg = <0x2c000600 0x38>;
+                interrupts = <1 2 0x304>,
+                             <1 3 0x304>;
+        };
+
+        gic: interrupt-controller@2c001000 {
+                compatible = "arm,corex-a5-gic", "arm,cortex-a9-gic";
+                #interrupt-cells = <3>;
+                #address-cells = <0>;
+                interrupt-controller;
+                reg = <0x2c001000 0x1000>,
+                      <0x2c000100 0x100>;
+        };
+
+        L2: cache-controller@2c0f0000 {
+                compatible = "arm,pl310-cache";
+                reg = <0x2c0f0000 0x1000>;
+                interrupts = <0 84 4>;
+                cache-level = <2>;
+        };
+
+        pmu {
+                compatible = "arm,cortex-a5-pmu", "arm,cortex-a9-pmu";
+                interrupts = <0 68 4>,
+                             <0 69 4>;
+        };
+
+        motherboard {
+                ranges = <0 0 0x08000000 0x04000000>,
+                         <1 0 0x14000000 0x04000000>,
+                         <2 0 0x18000000 0x04000000>,
+                         <3 0 0x1c000000 0x04000000>,
+                         <4 0 0x0c000000 0x04000000>,
+                         <5 0 0x10000000 0x04000000>;
+
+                interrupt-map-mask = <0 0 63>;
+                interrupt-map = <0 0  0 &gic 0  0 4>,
+                                <0 0  1 &gic 0  1 4>,
+                                <0 0  2 &gic 0  2 4>,
+                                <0 0  3 &gic 0  3 4>,
+                                <0 0  4 &gic 0  4 4>,
+                                <0 0  5 &gic 0  5 4>,
+                                <0 0  6 &gic 0  6 4>,
+                                <0 0  7 &gic 0  7 4>,
+                                <0 0  8 &gic 0  8 4>,
+                                <0 0  9 &gic 0  9 4>,
+                                <0 0 10 &gic 0 10 4>,
+                                <0 0 11 &gic 0 11 4>,
+                                <0 0 12 &gic 0 12 4>,
+                                <0 0 13 &gic 0 13 4>,
+                                <0 0 14 &gic 0 14 4>,
+                                <0 0 15 &gic 0 15 4>,
+                                <0 0 16 &gic 0 16 4>,
+                                <0 0 17 &gic 0 17 4>,
+                                <0 0 18 &gic 0 18 4>,
+                                <0 0 19 &gic 0 19 4>,
+                                <0 0 20 &gic 0 20 4>,
+                                <0 0 21 &gic 0 21 4>,
+                                <0 0 22 &gic 0 22 4>,
+                                <0 0 23 &gic 0 23 4>,
+                                <0 0 24 &gic 0 24 4>,
+                                <0 0 25 &gic 0 25 4>,
+                                <0 0 26 &gic 0 26 4>,
+                                <0 0 27 &gic 0 27 4>,
+                                <0 0 28 &gic 0 28 4>,
+                                <0 0 29 &gic 0 29 4>,
+                                <0 0 30 &gic 0 30 4>,
+                                <0 0 31 &gic 0 31 4>,
+                                <0 0 32 &gic 0 32 4>,
+                                <0 0 33 &gic 0 33 4>,
+                                <0 0 34 &gic 0 34 4>,
+                                <0 0 35 &gic 0 35 4>,
+                                <0 0 36 &gic 0 36 4>,
+                                <0 0 37 &gic 0 37 4>,
+                                <0 0 38 &gic 0 38 4>,
+                                <0 0 39 &gic 0 39 4>,
+                                <0 0 40 &gic 0 40 4>,
+                                <0 0 41 &gic 0 41 4>,
+                                <0 0 42 &gic 0 42 4>;
+        };
+};
+
+/include/ "vexpress-v2m-rs1.dtsi"
diff --git a/arch/arm/boot/dts/vexpress-v2p-ca9.dts b/arch/arm/boot/dts/vexpress-v2p-ca9.dts
new file mode 100644
index 00000000000..da778693be5
--- /dev/null
+++ b/arch/arm/boot/dts/vexpress-v2p-ca9.dts
@@ -0,0 +1,192 @@
+/*
+ * ARM Ltd. Versatile Express
+ *
+ * CoreTile Express A9x4
+ * Cortex-A9 MPCore (V2P-CA9)
+ *
+ * HBI-0191B
+ */
+
+/dts-v1/;
+
+/ {
+        model = "V2P-CA9";
+        arm,hbi = <0x191>;
+        compatible = "arm,vexpress,v2p-ca9", "arm,vexpress";
+        interrupt-parent = <&gic>;
+        #address-cells = <1>;
+        #size-cells = <1>;
+
+        chosen { };
+
+        aliases {
+                serial0 = &v2m_serial0;
+                serial1 = &v2m_serial1;
+                serial2 = &v2m_serial2;
+                serial3 = &v2m_serial3;
+                i2c0 = &v2m_i2c_dvi;
+                i2c1 = &v2m_i2c_pcie;
+        };
+
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                cpu@0 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a9";
+                        reg = <0>;
+                        next-level-cache = <&L2>;
+                };
+
+                cpu@1 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a9";
+                        reg = <1>;
+                        next-level-cache = <&L2>;
+                };
+
+                cpu@2 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a9";
+                        reg = <2>;
+                        next-level-cache = <&L2>;
+                };
+
+                cpu@3 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a9";
+                        reg = <3>;
+                        next-level-cache = <&L2>;
+                };
+        };
+
+        memory@60000000 {
+                device_type = "memory";
+                reg = <0x60000000 0x40000000>;
+        };
+
+        clcd@10020000 {
+                compatible = "arm,pl111", "arm,primecell";
+                reg = <0x10020000 0x1000>;
+                interrupts = <0 44 4>;
+        };
+
+        memory-controller@100e0000 {
+                compatible = "arm,pl341", "arm,primecell";
+                reg = <0x100e0000 0x1000>;
+        };
+
+        memory-controller@100e1000 {
+                compatible = "arm,pl354", "arm,primecell";
+                reg = <0x100e1000 0x1000>;
+                interrupts = <0 45 4>,
+                             <0 46 4>;
+        };
+
+        timer@100e4000 {
+                compatible = "arm,sp804", "arm,primecell";
+                reg = <0x100e4000 0x1000>;
+                interrupts = <0 48 4>,
+                             <0 49 4>;
+        };
+
+        watchdog@100e5000 {
+                compatible = "arm,sp805", "arm,primecell";
+                reg = <0x100e5000 0x1000>;
+                interrupts = <0 51 4>;
+        };
+
+        scu@1e000000 {
+                compatible = "arm,cortex-a9-scu";
+                reg = <0x1e000000 0x58>;
+        };
+
+        timer@1e000600 {
+                compatible = "arm,cortex-a9-twd-timer";
+                reg = <0x1e000600 0x20>;
+                interrupts = <1 2 0xf04>,
+                             <1 3 0xf04>;
+        };
+
+        gic: interrupt-controller@1e001000 {
+                compatible = "arm,cortex-a9-gic";
+                #interrupt-cells = <3>;
+                #address-cells = <0>;
+                interrupt-controller;
+                reg = <0x1e001000 0x1000>,
+                      <0x1e000100 0x100>;
+        };
+
+        L2: cache-controller@1e00a000 {
+                compatible = "arm,pl310-cache";
+                reg = <0x1e00a000 0x1000>;
+                interrupts = <0 43 4>;
+                cache-level = <2>;
+                arm,data-latency = <1 1 1>;
+                arm,tag-latency = <1 1 1>;
+        };
+
+        pmu {
+                compatible = "arm,cortex-a9-pmu";
+                interrupts = <0 60 4>,
+                             <0 61 4>,
+                             <0 62 4>,
+                             <0 63 4>;
+        };
+
+        motherboard {
+                ranges = <0 0 0x40000000 0x04000000>,
+                         <1 0 0x44000000 0x04000000>,
+                         <2 0 0x48000000 0x04000000>,
+                         <3 0 0x4c000000 0x04000000>,
+                         <7 0 0x10000000 0x00020000>;
+
+                interrupt-map-mask = <0 0 63>;
+                interrupt-map = <0 0  0 &gic 0  0 4>,
+                                <0 0  1 &gic 0  1 4>,
+                                <0 0  2 &gic 0  2 4>,
+                                <0 0  3 &gic 0  3 4>,
+                                <0 0  4 &gic 0  4 4>,
+                                <0 0  5 &gic 0  5 4>,
+                                <0 0  6 &gic 0  6 4>,
+                                <0 0  7 &gic 0  7 4>,
+                                <0 0  8 &gic 0  8 4>,
+                                <0 0  9 &gic 0  9 4>,
+                                <0 0 10 &gic 0 10 4>,
+                                <0 0 11 &gic 0 11 4>,
+                                <0 0 12 &gic 0 12 4>,
+                                <0 0 13 &gic 0 13 4>,
+                                <0 0 14 &gic 0 14 4>,
+                                <0 0 15 &gic 0 15 4>,
+                                <0 0 16 &gic 0 16 4>,
+                                <0 0 17 &gic 0 17 4>,
+                                <0 0 18 &gic 0 18 4>,
+                                <0 0 19 &gic 0 19 4>,
+                                <0 0 20 &gic 0 20 4>,
+                                <0 0 21 &gic 0 21 4>,
+                                <0 0 22 &gic 0 22 4>,
+                                <0 0 23 &gic 0 23 4>,
+                                <0 0 24 &gic 0 24 4>,
+                                <0 0 25 &gic 0 25 4>,
+                                <0 0 26 &gic 0 26 4>,
+                                <0 0 27 &gic 0 27 4>,
+                                <0 0 28 &gic 0 28 4>,
+                                <0 0 29 &gic 0 29 4>,
+                                <0 0 30 &gic 0 30 4>,
+                                <0 0 31 &gic 0 31 4>,
+                                <0 0 32 &gic 0 32 4>,
+                                <0 0 33 &gic 0 33 4>,
+                                <0 0 34 &gic 0 34 4>,
+                                <0 0 35 &gic 0 35 4>,
+                                <0 0 36 &gic 0 36 4>,
+                                <0 0 37 &gic 0 37 4>,
+                                <0 0 38 &gic 0 38 4>,
+                                <0 0 39 &gic 0 39 4>,
+                                <0 0 40 &gic 0 40 4>,
+                                <0 0 41 &gic 0 41 4>,
+                                <0 0 42 &gic 0 42 4>;
+        };
+};
+
+/include/ "vexpress-v2m.dtsi"
diff --git a/arch/arm/common/it8152.c b/arch/arm/common/it8152.c
index fb1f1cfce60..dcb13494ca0 100644
--- a/arch/arm/common/it8152.c
+++ b/arch/arm/common/it8152.c
@@ -299,8 +299,8 @@ int __init it8152_pci_setup(int nr, struct pci_sys_data *sys)
                 goto err1;
         }
 
-        pci_add_resource(&sys->resources, &it8152_io);
-        pci_add_resource(&sys->resources, &it8152_mem);
+        pci_add_resource_offset(&sys->resources, &it8152_io, sys->io_offset);
+        pci_add_resource_offset(&sys->resources, &it8152_mem, sys->mem_offset);
 
         if (platform_notify || platform_notify_remove) {
                 printk(KERN_ERR "PCI: Can't use platform_notify\n");
diff --git a/arch/arm/common/timer-sp.c b/arch/arm/common/timer-sp.c
index 8794a34eae6..df13a3ffff3 100644
--- a/arch/arm/common/timer-sp.c
+++ b/arch/arm/common/timer-sp.c
@@ -26,6 +26,7 @@
 #include <linux/irq.h>
 #include <linux/io.h>
 
+#include <asm/sched_clock.h>
 #include <asm/hardware/arm_timer.h>
 
 static long __init sp804_get_clock_rate(const char *name)
@@ -67,7 +68,16 @@ static long __init sp804_get_clock_rate(const char *name)
         return rate;
 }
 
-void __init sp804_clocksource_init(void __iomem *base, const char *name)
+static void __iomem *sched_clock_base;
+
+static u32 sp804_read(void)
+{
+        return ~readl_relaxed(sched_clock_base + TIMER_VALUE);
+}
+
+void __init __sp804_clocksource_and_sched_clock_init(void __iomem *base,
+                                                     const char *name,
+                                                     int use_sched_clock)
 {
         long rate = sp804_get_clock_rate(name);
 
@@ -83,6 +93,11 @@ void __init sp804_clocksource_init(void __iomem *base, const char *name)
 
         clocksource_mmio_init(base + TIMER_VALUE, name,
                 rate, 200, 32, clocksource_mmio_readl_down);
+
+        if (use_sched_clock) {
+                sched_clock_base = base;
+                setup_sched_clock(sp804_read, 32, rate);
+        }
 }
 
 
diff --git a/arch/arm/configs/at91cap9_defconfig b/arch/arm/configs/at91cap9_defconfig
deleted file mode 100644
index 8826eb218e7..00000000000
--- a/arch/arm/configs/at91cap9_defconfig
+++ /dev/null
@@ -1,108 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-# CONFIG_LOCALVERSION_AUTO is not set
-# CONFIG_SWAP is not set
-CONFIG_SYSVIPC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_SLAB=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_IOSCHED_DEADLINE is not set
-# CONFIG_IOSCHED_CFQ is not set
-CONFIG_ARCH_AT91=y
-CONFIG_ARCH_AT91CAP9=y
-CONFIG_MACH_AT91CAP9ADK=y
-CONFIG_MTD_AT91_DATAFLASH_CARD=y
-CONFIG_AT91_PROGRAMMABLE_CLOCKS=y
-# CONFIG_ARM_THUMB is not set
-CONFIG_AEABI=y
-CONFIG_LEDS=y
-CONFIG_LEDS_CPU=y
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="console=ttyS0,115200 root=/dev/ram0 rw"
-CONFIG_FPE_NWFPE=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_BOOTP=y
-CONFIG_IP_PNP_RARP=y
-# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
-# CONFIG_INET_XFRM_MODE_TUNNEL is not set
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_LRO is not set
-# CONFIG_INET_DIAG is not set
-# CONFIG_IPV6 is not set
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-CONFIG_MTD=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_CHAR=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_CFI=y
-CONFIG_MTD_JEDECPROBE=y
-CONFIG_MTD_CFI_AMDSTD=y
-CONFIG_MTD_PHYSMAP=y
-CONFIG_MTD_DATAFLASH=y
-CONFIG_MTD_NAND=y
-CONFIG_MTD_NAND_ATMEL=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_SIZE=8192
-CONFIG_SCSI=y
-CONFIG_BLK_DEV_SD=y
-CONFIG_SCSI_MULTI_LUN=y
-CONFIG_NETDEVICES=y
-CONFIG_MII=y
-CONFIG_MACB=y
-# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
-CONFIG_INPUT_EVDEV=y
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_INPUT_TOUCHSCREEN=y
-CONFIG_TOUCHSCREEN_ADS7846=y
-# CONFIG_SERIO is not set
-CONFIG_SERIAL_ATMEL=y
-CONFIG_SERIAL_ATMEL_CONSOLE=y
-CONFIG_HW_RANDOM=y
-CONFIG_I2C=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_SPI=y
-CONFIG_SPI_ATMEL=y
-# CONFIG_HWMON is not set
-CONFIG_WATCHDOG=y
-CONFIG_WATCHDOG_NOWAYOUT=y
-CONFIG_FB=y
-CONFIG_FB_ATMEL=y
-CONFIG_LOGO=y
-# CONFIG_LOGO_LINUX_MONO is not set
-# CONFIG_LOGO_LINUX_CLUT224 is not set
-# CONFIG_USB_HID is not set
-CONFIG_USB=y
-CONFIG_USB_DEVICEFS=y
-CONFIG_USB_MON=y
-CONFIG_USB_OHCI_HCD=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_ETH=m
-CONFIG_USB_FILE_STORAGE=m
-CONFIG_MMC=y
-CONFIG_MMC_AT91=m
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_AT91SAM9=y
-CONFIG_EXT2_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_TMPFS=y
-CONFIG_JFFS2_FS=y
-CONFIG_CRAMFS=y
-CONFIG_NFS_FS=y
-CONFIG_ROOT_NFS=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_CODEPAGE_850=y
-CONFIG_NLS_ISO8859_1=y
-CONFIG_DEBUG_FS=y
-CONFIG_DEBUG_KERNEL=y
-CONFIG_DEBUG_INFO=y
-CONFIG_DEBUG_USER=y
diff --git a/arch/arm/configs/imx_v4_v5_defconfig b/arch/arm/configs/imx_v4_v5_defconfig
index a22e9307906..b5ac644e12a 100644
--- a/arch/arm/configs/imx_v4_v5_defconfig
+++ b/arch/arm/configs/imx_v4_v5_defconfig
@@ -45,6 +45,7 @@ CONFIG_FPE_NWFPE=y
 CONFIG_FPE_NWFPE_XP=y
 CONFIG_PM_DEBUG=y
 CONFIG_NET=y
+CONFIG_SMSC911X=y
 CONFIG_PACKET=y
 CONFIG_UNIX=y
 CONFIG_INET=y
@@ -68,6 +69,7 @@ CONFIG_MTD_CFI=y
 CONFIG_MTD_CFI_ADV_OPTIONS=y
 CONFIG_MTD_CFI_GEOMETRY=y
 # CONFIG_MTD_MAP_BANK_WIDTH_1 is not set
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
 # CONFIG_MTD_CFI_I2 is not set
 CONFIG_MTD_CFI_INTELEXT=y
 CONFIG_MTD_PHYSMAP=y
@@ -78,6 +80,8 @@ CONFIG_MISC_DEVICES=y
 CONFIG_EEPROM_AT24=y
 CONFIG_EEPROM_AT25=y
 CONFIG_NETDEVICES=y
+CONFIG_CS89x0=y
+CONFIG_CS89x0_PLATFORM=y
 CONFIG_DM9000=y
 CONFIG_SMC91X=y
 CONFIG_SMC911X=y
@@ -115,6 +119,21 @@ CONFIG_FB_IMX=y
 CONFIG_BACKLIGHT_LCD_SUPPORT=y
 CONFIG_LCD_CLASS_DEVICE=y
 CONFIG_BACKLIGHT_CLASS_DEVICE=y
+CONFIG_LCD_L4F00242T03=y
+CONFIG_MEDIA_SUPPORT=y
+CONFIG_VIDEO_DEV=y
+CONFIG_VIDEO_V4L2_COMMON=y
+CONFIG_VIDEO_MEDIA=y
+CONFIG_VIDEO_V4L2=y
+CONFIG_VIDEOBUF_GEN=y
+CONFIG_VIDEOBUF_DMA_CONTIG=y
+CONFIG_VIDEOBUF2_CORE=y
+CONFIG_VIDEO_CAPTURE_DRIVERS=y
+CONFIG_V4L_PLATFORM_DRIVERS=y
+CONFIG_SOC_CAMERA=y
+CONFIG_SOC_CAMERA_OV2640=y
+CONFIG_VIDEO_MX2_HOSTSUPPORT=y
+CONFIG_VIDEO_MX2=y
 CONFIG_BACKLIGHT_PWM=y
 CONFIG_FRAMEBUFFER_CONSOLE=y
 CONFIG_FONTS=y
diff --git a/arch/arm/configs/imx_v6_v7_defconfig b/arch/arm/configs/imx_v6_v7_defconfig
index 3a4fb2e5fc6..dc6f6411bbf 100644
--- a/arch/arm/configs/imx_v6_v7_defconfig
+++ b/arch/arm/configs/imx_v6_v7_defconfig
@@ -5,6 +5,7 @@ CONFIG_SYSVIPC=y
 CONFIG_LOG_BUF_SHIFT=18
 CONFIG_CGROUPS=y
 CONFIG_RELAY=y
+CONFIG_BLK_DEV_INITRD=y
 CONFIG_EXPERT=y
 # CONFIG_SLUB_DEBUG is not set
 # CONFIG_COMPAT_BRK is not set
@@ -12,7 +13,6 @@ CONFIG_MODULES=y
 CONFIG_MODULE_UNLOAD=y
 CONFIG_MODVERSIONS=y
 CONFIG_MODULE_SRCVERSION_ALL=y
-# CONFIG_LBDAF is not set
 # CONFIG_BLK_DEV_BSG is not set
 CONFIG_ARCH_MXC=y
 CONFIG_MACH_MX31LILLY=y
@@ -26,7 +26,6 @@ CONFIG_MACH_ARMADILLO5X0=y
 CONFIG_MACH_KZM_ARM11_01=y
 CONFIG_MACH_PCM043=y
 CONFIG_MACH_MX35_3DS=y
-CONFIG_MACH_EUKREA_CPUIMX35=y
 CONFIG_MACH_VPR200=y
 CONFIG_MACH_IMX51_DT=y
 CONFIG_MACH_MX51_3DS=y
@@ -82,8 +81,9 @@ CONFIG_PATA_IMX=y
 CONFIG_NETDEVICES=y
 # CONFIG_NET_VENDOR_BROADCOM is not set
 # CONFIG_NET_VENDOR_CHELSIO is not set
+CONFIG_CS89x0=y
+CONFIG_CS89x0_PLATFORM=y
 # CONFIG_NET_VENDOR_FARADAY is not set
-CONFIG_FEC=y
 # CONFIG_NET_VENDOR_INTEL is not set
 # CONFIG_NET_VENDOR_MARVELL is not set
 # CONFIG_NET_VENDOR_MICREL is not set
@@ -126,7 +126,40 @@ CONFIG_WATCHDOG=y
 CONFIG_IMX2_WDT=y
 CONFIG_MFD_MC13XXX=y
 CONFIG_REGULATOR=y
+CONFIG_REGULATOR_FIXED_VOLTAGE=y
+CONFIG_REGULATOR_MC13783=y
 CONFIG_REGULATOR_MC13892=y
+CONFIG_MEDIA_SUPPORT=y
+CONFIG_VIDEO_V4L2=y
+CONFIG_VIDEO_DEV=y
+CONFIG_VIDEO_V4L2_COMMON=y
+CONFIG_VIDEOBUF_GEN=y
+CONFIG_VIDEOBUF2_CORE=y
+CONFIG_VIDEOBUF2_MEMOPS=y
+CONFIG_VIDEOBUF2_DMA_CONTIG=y
+CONFIG_VIDEO_CAPTURE_DRIVERS=y
+CONFIG_V4L_PLATFORM_DRIVERS=y
+CONFIG_SOC_CAMERA=y
+CONFIG_SOC_CAMERA_OV2640=y
+CONFIG_MX3_VIDEO=y
+CONFIG_VIDEO_MX3=y
+CONFIG_FB=y
+CONFIG_FB_MX3=y
+CONFIG_BACKLIGHT_LCD_SUPPORT=y
+CONFIG_LCD_CLASS_DEVICE=y
+CONFIG_LCD_L4F00242T03=y
+CONFIG_BACKLIGHT_CLASS_DEVICE=y
+CONFIG_BACKLIGHT_GENERIC=y
+CONFIG_DUMMY_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
+CONFIG_FONTS=y
+CONFIG_FONT_8x8=y
+CONFIG_FONT_8x16=y
+CONFIG_LOGO=y
+CONFIG_LOGO_LINUX_MONO=y
+CONFIG_LOGO_LINUX_VGA16=y
+CONFIG_LOGO_LINUX_CLUT224=y
 CONFIG_USB=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_EHCI_MXC=y
diff --git a/arch/arm/configs/lpc32xx_defconfig b/arch/arm/configs/lpc32xx_defconfig
new file mode 100644
index 00000000000..fb2088171ca
--- /dev/null
+++ b/arch/arm/configs/lpc32xx_defconfig
@@ -0,0 +1,145 @@
+CONFIG_EXPERIMENTAL=y
+CONFIG_SYSVIPC=y
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_EMBEDDED=y
+CONFIG_SLAB=y
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_BLK_DEV_BSG is not set
+CONFIG_PARTITION_ADVANCED=y
+CONFIG_ARCH_LPC32XX=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_PREEMPT=y
+CONFIG_AEABI=y
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_CMDLINE="console=ttyS0,115200n81 root=/dev/ram0"
+CONFIG_CPU_IDLE=y
+CONFIG_FPE_NWFPE=y
+CONFIG_VFP=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_BINFMT_AOUT=y
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
+# CONFIG_INET_DIAG is not set
+# CONFIG_IPV6 is not set
+# CONFIG_WIRELESS is not set
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+# CONFIG_FW_LOADER is not set
+CONFIG_MTD=y
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLOCK=y
+CONFIG_MTD_NAND=y
+CONFIG_MTD_NAND_MUSEUM_IDS=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_CRYPTOLOOP=y
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=1
+CONFIG_BLK_DEV_RAM_SIZE=16384
+CONFIG_MISC_DEVICES=y
+CONFIG_EEPROM_AT25=y
+CONFIG_SCSI=y
+CONFIG_BLK_DEV_SD=y
+CONFIG_NETDEVICES=y
+CONFIG_MII=y
+CONFIG_PHYLIB=y
+CONFIG_SMSC_PHY=y
+# CONFIG_WLAN is not set
+# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=240
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=320
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_MOUSE is not set
+CONFIG_INPUT_TOUCHSCREEN=y
+CONFIG_TOUCHSCREEN_LPC32XX=y
+# CONFIG_LEGACY_PTYS is not set
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+# CONFIG_HW_RANDOM is not set
+CONFIG_I2C=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_PNX=y
+CONFIG_SPI=y
+CONFIG_SPI_PL022=y
+CONFIG_GPIO_SYSFS=y
+# CONFIG_HWMON is not set
+CONFIG_WATCHDOG=y
+CONFIG_PNX4008_WATCHDOG=y
+CONFIG_FB=y
+CONFIG_FB_ARMCLCD=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
+CONFIG_LOGO=y
+# CONFIG_LOGO_LINUX_MONO is not set
+# CONFIG_LOGO_LINUX_VGA16 is not set
+CONFIG_SOUND=y
+CONFIG_SND=y
+CONFIG_SND_SEQUENCER=y
+CONFIG_SND_MIXER_OSS=y
+CONFIG_SND_PCM_OSS=y
+CONFIG_SND_SEQUENCER_OSS=y
+CONFIG_SND_DYNAMIC_MINORS=y
+# CONFIG_SND_VERBOSE_PROCFS is not set
+# CONFIG_SND_DRIVERS is not set
+# CONFIG_SND_ARM is not set
+# CONFIG_SND_SPI is not set
+CONFIG_SND_SOC=y
+# CONFIG_HID_SUPPORT is not set
+CONFIG_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_LIBUSUAL=y
+CONFIG_MMC=y
+# CONFIG_MMC_BLOCK_BOUNCE is not set
+CONFIG_MMC_ARMMMCI=y
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
+CONFIG_LEDS_GPIO=y
+CONFIG_LEDS_TRIGGERS=y
+CONFIG_LEDS_TRIGGER_HEARTBEAT=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_INTF_DEV_UIE_EMUL=y
+CONFIG_RTC_DRV_LPC32XX=y
+CONFIG_EXT2_FS=y
+CONFIG_AUTOFS4_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_TMPFS=y
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_WBUF_VERIFY=y
+CONFIG_CRAMFS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+CONFIG_ROOT_NFS=y
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_ASCII=y
+CONFIG_NLS_ISO8859_1=y
+CONFIG_NLS_UTF8=y
+# CONFIG_SCHED_DEBUG is not set
+# CONFIG_DEBUG_PREEMPT is not set
+CONFIG_DEBUG_INFO=y
+# CONFIG_FTRACE is not set
+# CONFIG_ARM_UNWIND is not set
+CONFIG_DEBUG_LL=y
+CONFIG_EARLY_PRINTK=y
+CONFIG_CRYPTO_ANSI_CPRNG=y
+# CONFIG_CRYPTO_HW is not set
+CONFIG_CRC_CCITT=y
diff --git a/arch/arm/configs/magician_defconfig b/arch/arm/configs/magician_defconfig
index 443675d317e..a691ef4c600 100644
--- a/arch/arm/configs/magician_defconfig
+++ b/arch/arm/configs/magician_defconfig
@@ -101,7 +101,7 @@ CONFIG_MFD_ASIC3=y
 CONFIG_HTC_EGPIO=y
 CONFIG_HTC_PASIC3=y
 CONFIG_REGULATOR=y
-CONFIG_REGULATOR_BQ24022=y
+CONFIG_REGULATOR_GPIO=y
 CONFIG_FB=y
 CONFIG_FB_PXA=y
 CONFIG_FB_PXA_OVERLAY=y
diff --git a/arch/arm/configs/mini2440_defconfig b/arch/arm/configs/mini2440_defconfig
index 2472a958583..42da9183acc 100644
--- a/arch/arm/configs/mini2440_defconfig
+++ b/arch/arm/configs/mini2440_defconfig
@@ -13,7 +13,7 @@ CONFIG_MODULE_UNLOAD=y
 CONFIG_MODULE_FORCE_UNLOAD=y
 # CONFIG_BLK_DEV_BSG is not set
 CONFIG_BLK_DEV_INTEGRITY=y
-CONFIG_ARCH_S3C2410=y
+CONFIG_ARCH_S3C24XX=y
 CONFIG_S3C_ADC=y
 CONFIG_S3C24XX_PWM=y
 CONFIG_MACH_MINI2440=y
diff --git a/arch/arm/configs/mxs_defconfig b/arch/arm/configs/mxs_defconfig
index 6ee781bf6bf..1ebbf451c48 100644
--- a/arch/arm/configs/mxs_defconfig
+++ b/arch/arm/configs/mxs_defconfig
@@ -77,10 +77,10 @@ CONFIG_DEVPTS_MULTIPLE_INSTANCES=y
 CONFIG_SERIAL_AMBA_PL011=y
 CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
 # CONFIG_HW_RANDOM is not set
-CONFIG_I2C=m
+CONFIG_I2C=y
 # CONFIG_I2C_COMPAT is not set
-CONFIG_I2C_CHARDEV=m
-CONFIG_I2C_MXS=m
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_MXS=y
 CONFIG_SPI=y
 CONFIG_SPI_GPIO=m
 CONFIG_DEBUG_GPIO=y
@@ -90,6 +90,20 @@ CONFIG_GPIO_SYSFS=y
 CONFIG_DISPLAY_SUPPORT=m
 # CONFIG_HID_SUPPORT is not set
 # CONFIG_USB_SUPPORT is not set
+CONFIG_SOUND=y
+CONFIG_SND=y
+CONFIG_SND_TIMER=y
+CONFIG_SND_PCM=y
+CONFIG_SND_JACK=y
+CONFIG_SND_DRIVERS=y
+CONFIG_SND_ARM=y
+CONFIG_SND_SOC=y
+CONFIG_SND_MXS_SOC=y
+CONFIG_SND_SOC_MXS_SGTL5000=y
+CONFIG_SND_SOC_I2C_AND_SPI=y
+CONFIG_SND_SOC_SGTL5000=y
+CONFIG_REGULATOR=y
+CONFIG_REGULATOR_FIXED_VOLTAGE=y
 CONFIG_MMC=y
 CONFIG_MMC_MXS=y
 CONFIG_RTC_CLASS=y
diff --git a/arch/arm/configs/s3c2410_defconfig b/arch/arm/configs/s3c2410_defconfig
index f9096c1b0a6..193448f3128 100644
--- a/arch/arm/configs/s3c2410_defconfig
+++ b/arch/arm/configs/s3c2410_defconfig
@@ -3,40 +3,47 @@ CONFIG_SYSVIPC=y
 CONFIG_IKCONFIG=m
 CONFIG_IKCONFIG_PROC=y
 CONFIG_LOG_BUF_SHIFT=16
-CONFIG_SYSFS_DEPRECATED_V2=y
 CONFIG_BLK_DEV_INITRD=y
 CONFIG_SLAB=y
 CONFIG_MODULES=y
 CONFIG_MODULE_UNLOAD=y
 # CONFIG_BLK_DEV_BSG is not set
-CONFIG_ARCH_S3C2410=y
+CONFIG_PARTITION_ADVANCED=y
+CONFIG_BSD_DISKLABEL=y
+CONFIG_SOLARIS_X86_PARTITION=y
+CONFIG_ARCH_S3C24XX=y
 CONFIG_S3C_BOOT_ERROR_RESET=y
 CONFIG_S3C_ADC=y
 CONFIG_S3C24XX_PWM=y
-CONFIG_ARCH_SMDK2410=y
+CONFIG_CPU_S3C2412=y
+CONFIG_CPU_S3C2416=y
+CONFIG_CPU_S3C2440=y
+CONFIG_CPU_S3C2442=y
+CONFIG_CPU_S3C2443=y
+CONFIG_MACH_AML_M5900=y
+CONFIG_ARCH_BAST=y
 CONFIG_ARCH_H1940=y
 CONFIG_MACH_N30=y
-CONFIG_ARCH_BAST=y
 CONFIG_MACH_OTOM=y
-CONFIG_MACH_AML_M5900=y
+CONFIG_MACH_QT2410=y
+CONFIG_ARCH_SMDK2410=y
 CONFIG_MACH_TCT_HAMMER=y
 CONFIG_MACH_VR1000=y
-CONFIG_MACH_QT2410=y
 CONFIG_MACH_JIVE=y
 CONFIG_MACH_SMDK2412=y
 CONFIG_MACH_VSTMS=y
 CONFIG_MACH_SMDK2416=y
 CONFIG_MACH_ANUBIS=y
-CONFIG_MACH_NEO1973_GTA02=y
+CONFIG_MACH_AT2440EVB=y
+CONFIG_MACH_MINI2440=y
+CONFIG_MACH_NEXCODER_2440=y
 CONFIG_MACH_OSIRIS=y
 CONFIG_MACH_OSIRIS_DVS=m
 CONFIG_MACH_RX3715=y
 CONFIG_ARCH_S3C2440=y
-CONFIG_MACH_NEXCODER_2440=y
-CONFIG_SMDK2440_CPU2442=y
-CONFIG_MACH_AT2440EVB=y
-CONFIG_MACH_MINI2440=y
+CONFIG_MACH_NEO1973_GTA02=y
 CONFIG_MACH_RX1950=y
+CONFIG_SMDK2440_CPU2442=y
 CONFIG_MACH_SMDK2443=y
 # CONFIG_ARM_THUMB is not set
 CONFIG_ZBOOT_ROM_TEXT=0x0
@@ -45,7 +52,6 @@ CONFIG_CMDLINE="root=/dev/hda1 ro init=/bin/bash console=ttySAC0"
 CONFIG_FPE_NWFPE=y
 CONFIG_FPE_NWFPE_XP=y
 CONFIG_BINFMT_AOUT=y
-CONFIG_PM=y
 CONFIG_APM_EMULATION=m
 CONFIG_NET=y
 CONFIG_PACKET=y
@@ -58,7 +64,6 @@ CONFIG_IP_PNP=y
 CONFIG_IP_PNP_DHCP=y
 CONFIG_IP_PNP_BOOTP=y
 CONFIG_NET_IPIP=m
-CONFIG_NET_IPGRE=m
 CONFIG_INET_AH=m
 CONFIG_INET_ESP=m
 CONFIG_INET_IPCOMP=m
@@ -80,7 +85,6 @@ CONFIG_IPV6_MIP6=m
 CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION=m
 CONFIG_IPV6_TUNNEL=m
 CONFIG_NETFILTER=y
-CONFIG_NETFILTER_NETLINK_QUEUE=m
 CONFIG_NF_CONNTRACK=m
 CONFIG_NF_CONNTRACK_EVENTS=y
 CONFIG_NF_CT_PROTO_DCCP=m
@@ -138,7 +142,6 @@ CONFIG_IP_VS=m
 CONFIG_NF_CONNTRACK_IPV4=m
 CONFIG_IP_NF_QUEUE=m
 CONFIG_IP_NF_IPTABLES=m
-CONFIG_IP_NF_MATCH_ADDRTYPE=m
 CONFIG_IP_NF_MATCH_AH=m
 CONFIG_IP_NF_MATCH_ECN=m
 CONFIG_IP_NF_MATCH_TTL=m
@@ -150,7 +153,6 @@ CONFIG_NF_NAT=m
 CONFIG_IP_NF_TARGET_MASQUERADE=m
 CONFIG_IP_NF_TARGET_NETMAP=m
 CONFIG_IP_NF_TARGET_REDIRECT=m
-CONFIG_NF_NAT_SNMP_BASIC=m
 CONFIG_IP_NF_MANGLE=m
 CONFIG_IP_NF_TARGET_CLUSTERIP=m
 CONFIG_IP_NF_TARGET_ECN=m
@@ -177,8 +179,6 @@ CONFIG_IP6_NF_TARGET_REJECT=m
 CONFIG_IP6_NF_MANGLE=m
 CONFIG_IP6_NF_RAW=m
 CONFIG_BT=m
-CONFIG_BT_L2CAP=m
-CONFIG_BT_SCO=m
 CONFIG_BT_RFCOMM=m
 CONFIG_BT_RFCOMM_TTY=y
 CONFIG_BT_BNEP=m
@@ -199,7 +199,6 @@ CONFIG_MAC80211_MESH=y
 CONFIG_MAC80211_LEDS=y
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 CONFIG_MTD=y
-CONFIG_MTD_PARTITIONS=y
 CONFIG_MTD_REDBOOT_PARTS=y
 CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED=y
 CONFIG_MTD_CMDLINE_PARTS=y
@@ -221,9 +220,6 @@ CONFIG_BLK_DEV_NBD=m
 CONFIG_BLK_DEV_UB=m
 CONFIG_BLK_DEV_RAM=y
 CONFIG_ATA_OVER_ETH=m
-CONFIG_EEPROM_AT25=m
-CONFIG_EEPROM_LEGACY=m
-CONFIG_EEPROM_93CX6=m
 CONFIG_IDE=y
 CONFIG_BLK_DEV_IDECD=y
 CONFIG_BLK_DEV_IDETAPE=m
@@ -240,7 +236,6 @@ CONFIG_SCSI_MULTI_LUN=y
 CONFIG_SCSI_CONSTANTS=y
 CONFIG_SCSI_SCAN_ASYNC=y
 CONFIG_NETDEVICES=y
-CONFIG_NET_ETHERNET=y
 CONFIG_DM9000=y
 CONFIG_INPUT_EVDEV=y
 CONFIG_MOUSE_APPLETOUCH=m
@@ -274,7 +269,6 @@ CONFIG_JOYSTICK_XPAD_LEDS=y
 CONFIG_INPUT_TOUCHSCREEN=y
 CONFIG_TOUCHSCREEN_USB_COMPOSITE=m
 CONFIG_INPUT_MISC=y
-CONFIG_INPUT_ATI_REMOTE=m
 CONFIG_INPUT_ATI_REMOTE2=m
 CONFIG_INPUT_KEYSPAN_REMOTE=m
 CONFIG_INPUT_POWERMATE=m
@@ -300,7 +294,6 @@ CONFIG_I2C_SIMTEC=y
 CONFIG_SPI=y
 CONFIG_SPI_GPIO=m
 CONFIG_SPI_S3C24XX=m
-CONFIG_SPI_S3C24XX_GPIO=m
 CONFIG_SPI_SPIDEV=m
 CONFIG_SPI_TLE62X0=m
 CONFIG_SENSORS_LM75=m
@@ -315,7 +308,6 @@ CONFIG_FB_MODE_HELPERS=y
 CONFIG_FB_S3C2410=y
 CONFIG_FB_SM501=y
 CONFIG_BACKLIGHT_PWM=m
-# CONFIG_VGA_CONSOLE is not set
 CONFIG_FRAMEBUFFER_CONSOLE=y
 CONFIG_SOUND=y
 CONFIG_SND=y
@@ -330,10 +322,6 @@ CONFIG_SND_VERBOSE_PRINTK=y
 CONFIG_SND_USB_AUDIO=m
 CONFIG_SND_USB_CAIAQ=m
 CONFIG_SND_SOC=y
-CONFIG_SND_S3C24XX_SOC=y
-CONFIG_SND_S3C24XX_SOC_JIVE_WM8750=m
-CONFIG_SND_S3C24XX_SOC_SMDK2443_WM9710=m
-CONFIG_SND_S3C24XX_SOC_LN2440SBC_ALC650=m
 # CONFIG_USB_HID is not set
 CONFIG_USB=y
 CONFIG_USB_DEVICEFS=y
@@ -387,9 +375,7 @@ CONFIG_MMC_TEST=m
 CONFIG_MMC_SDHCI=m
 CONFIG_MMC_SPI=m
 CONFIG_MMC_S3C=y
-CONFIG_LEDS_CLASS=m
 CONFIG_LEDS_S3C24XX=m
-CONFIG_LEDS_H1940=m
 CONFIG_LEDS_PCA9532=m
 CONFIG_LEDS_GPIO=m
 CONFIG_LEDS_PCA955X=m
@@ -410,8 +396,6 @@ CONFIG_EXT3_FS=y
 CONFIG_EXT3_FS_POSIX_ACL=y
 CONFIG_EXT4_FS=m
 CONFIG_EXT4_FS_POSIX_ACL=y
-CONFIG_INOTIFY=y
-CONFIG_AUTOFS_FS=m
 CONFIG_AUTOFS4_FS=m
 CONFIG_FUSE_FS=m
 CONFIG_ISO9660_FS=y
@@ -436,9 +420,6 @@ CONFIG_NFSD=m
 CONFIG_NFSD_V3_ACL=y
 CONFIG_NFSD_V4=y
 CONFIG_CIFS=m
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_BSD_DISKLABEL=y
-CONFIG_SOLARIS_X86_PARTITION=y
 CONFIG_NLS_CODEPAGE_437=y
 CONFIG_NLS_CODEPAGE_737=m
 CONFIG_NLS_CODEPAGE_775=m
@@ -481,9 +462,7 @@ CONFIG_MAGIC_SYSRQ=y
 CONFIG_DEBUG_KERNEL=y
 CONFIG_DEBUG_MUTEXES=y
 CONFIG_DEBUG_INFO=y
-# CONFIG_RCU_CPU_STALL_DETECTOR is not set
 CONFIG_SYSCTL_SYSCALL_CHECK=y
 CONFIG_DEBUG_USER=y
-CONFIG_DEBUG_ERRORS=y
 CONFIG_DEBUG_LL=y
 # CONFIG_CRYPTO_ANSI_CPRNG is not set
diff --git a/arch/arm/configs/tct_hammer_defconfig b/arch/arm/configs/tct_hammer_defconfig
index 95c0f0d63db..1d24f8458be 100644
--- a/arch/arm/configs/tct_hammer_defconfig
+++ b/arch/arm/configs/tct_hammer_defconfig
@@ -14,7 +14,7 @@ CONFIG_SLOB=y
 CONFIG_MODULES=y
 CONFIG_MODULE_UNLOAD=y
 # CONFIG_BLK_DEV_BSG is not set
-CONFIG_ARCH_S3C2410=y
+CONFIG_ARCH_S3C24XX=y
 CONFIG_MACH_TCT_HAMMER=y
 CONFIG_ZBOOT_ROM_TEXT=0x0
 CONFIG_ZBOOT_ROM_BSS=0x0
diff --git a/arch/arm/configs/tegra_defconfig b/arch/arm/configs/tegra_defconfig
index fd5d3041d71..351d6708c3a 100644
--- a/arch/arm/configs/tegra_defconfig
+++ b/arch/arm/configs/tegra_defconfig
@@ -11,11 +11,14 @@ CONFIG_RT_GROUP_SCHED=y
 CONFIG_BLK_DEV_INITRD=y
 # CONFIG_ELF_CORE is not set
 CONFIG_EMBEDDED=y
+CONFIG_PERF_EVENTS=y
 CONFIG_SLAB=y
 CONFIG_MODULES=y
 CONFIG_MODULE_UNLOAD=y
 CONFIG_MODULE_FORCE_UNLOAD=y
 # CONFIG_BLK_DEV_BSG is not set
+CONFIG_PARTITION_ADVANCED=y
+CONFIG_EFI_PARTITION=y
 # CONFIG_IOSCHED_DEADLINE is not set
 # CONFIG_IOSCHED_CFQ is not set
 CONFIG_ARCH_TEGRA=y
@@ -27,18 +30,20 @@ CONFIG_MACH_PAZ00=y
 CONFIG_MACH_TRIMSLICE=y
 CONFIG_MACH_WARIO=y
 CONFIG_MACH_VENTANA=y
-CONFIG_TEGRA_DEBUG_UARTD=y
-CONFIG_ARM_ERRATA_742230=y
+CONFIG_TEGRA_EMC_SCALING_ENABLE=y
 CONFIG_NO_HZ=y
 CONFIG_HIGH_RES_TIMERS=y
 CONFIG_SMP=y
-CONFIG_NR_CPUS=2
 CONFIG_PREEMPT=y
 CONFIG_AEABI=y
 # CONFIG_OABI_COMPAT is not set
 CONFIG_HIGHMEM=y
 CONFIG_ZBOOT_ROM_TEXT=0x0
 CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_AUTO_ZRELADDR=y
+CONFIG_CPU_FREQ=y
+CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
+CONFIG_CPU_IDLE=y
 CONFIG_VFP=y
 CONFIG_NET=y
 CONFIG_PACKET=y
@@ -68,7 +73,6 @@ CONFIG_IPV6_MULTIPLE_TABLES=y
 # CONFIG_FIRMWARE_IN_KERNEL is not set
 CONFIG_PROC_DEVICETREE=y
 CONFIG_BLK_DEV_LOOP=y
-CONFIG_MISC_DEVICES=y
 CONFIG_AD525X_DPOT=y
 CONFIG_AD525X_DPOT_I2C=y
 CONFIG_ICS932S401=y
@@ -76,6 +80,7 @@ CONFIG_APDS9802ALS=y
 CONFIG_ISL29003=y
 CONFIG_SCSI=y
 CONFIG_BLK_DEV_SD=y
+CONFIG_BLK_DEV_SR=y
 # CONFIG_SCSI_LOWLEVEL is not set
 CONFIG_NETDEVICES=y
 CONFIG_DUMMY=y
@@ -85,8 +90,7 @@ CONFIG_USB_USBNET=y
 CONFIG_USB_NET_SMSC75XX=y
 CONFIG_USB_NET_SMSC95XX=y
 # CONFIG_WLAN is not set
-# CONFIG_INPUT is not set
-# CONFIG_SERIO is not set
+CONFIG_INPUT_EVDEV=y
 # CONFIG_VT is not set
 # CONFIG_LEGACY_PTYS is not set
 # CONFIG_DEVKMEM is not set
@@ -96,13 +100,15 @@ CONFIG_SERIAL_OF_PLATFORM=y
 # CONFIG_HW_RANDOM is not set
 CONFIG_I2C=y
 # CONFIG_I2C_COMPAT is not set
-# CONFIG_I2C_HELPER_AUTO is not set
 CONFIG_I2C_TEGRA=y
 CONFIG_SPI=y
 CONFIG_SPI_TEGRA=y
 CONFIG_SENSORS_LM90=y
 CONFIG_MFD_TPS6586X=y
 CONFIG_REGULATOR=y
+CONFIG_REGULATOR_FIXED_VOLTAGE=y
+CONFIG_REGULATOR_VIRTUAL_CONSUMER=y
+CONFIG_REGULATOR_GPIO=y
 CONFIG_REGULATOR_TPS6586X=y
 CONFIG_SOUND=y
 CONFIG_SND=y
@@ -116,11 +122,13 @@ CONFIG_SND_SOC=y
 CONFIG_SND_SOC_TEGRA=y
 CONFIG_SND_SOC_TEGRA_WM8903=y
 CONFIG_SND_SOC_TEGRA_TRIMSLICE=y
+CONFIG_SND_SOC_TEGRA_ALC5632=y
 CONFIG_USB=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_EHCI_TEGRA=y
 CONFIG_USB_STORAGE=y
 CONFIG_MMC=y
+CONFIG_MMC_BLOCK_MINORS=16
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_PLTFM=y
 CONFIG_MMC_SDHCI_TEGRA=y
@@ -130,6 +138,11 @@ CONFIG_STAGING=y
 CONFIG_IIO=y
 CONFIG_SENSORS_ISL29018=y
 CONFIG_SENSORS_AK8975=y
+CONFIG_MFD_NVEC=y
+CONFIG_KEYBOARD_NVEC=y
+CONFIG_SERIO_NVEC_PS2=y
+CONFIG_TEGRA_IOMMU_GART=y
+CONFIG_TEGRA_IOMMU_SMMU=y
 CONFIG_EXT2_FS=y
 CONFIG_EXT2_FS_XATTR=y
 CONFIG_EXT2_FS_POSIX_ACL=y
@@ -138,13 +151,12 @@ CONFIG_EXT3_FS=y
 # CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
 CONFIG_EXT3_FS_POSIX_ACL=y
 CONFIG_EXT3_FS_SECURITY=y
+CONFIG_EXT4_FS=y
 # CONFIG_DNOTIFY is not set
 CONFIG_VFAT_FS=y
 CONFIG_TMPFS=y
 CONFIG_NFS_FS=y
 CONFIG_ROOT_NFS=y
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_EFI_PARTITION=y
 CONFIG_NLS_CODEPAGE_437=y
 CONFIG_NLS_ISO8859_1=y
 CONFIG_PRINTK_TIME=y
@@ -162,9 +174,8 @@ CONFIG_DEBUG_SG=y
 CONFIG_DEBUG_LL=y
 CONFIG_EARLY_PRINTK=y
 CONFIG_CRYPTO_ECB=y
-CONFIG_CRYPTO_AES=y
 CONFIG_CRYPTO_ARC4=y
 CONFIG_CRYPTO_TWOFISH=y
 # CONFIG_CRYPTO_ANSI_CPRNG is not set
+CONFIG_CRYPTO_DEV_TEGRA_AES=y
 CONFIG_CRC_CCITT=y
-CONFIG_CRC16=y
diff --git a/arch/arm/include/asm/hardware/arm_timer.h b/arch/arm/include/asm/hardware/arm_timer.h
index c0f4e7bf22d..d6030ff599d 100644
--- a/arch/arm/include/asm/hardware/arm_timer.h
+++ b/arch/arm/include/asm/hardware/arm_timer.h
@@ -9,7 +9,12 @@
  *
  * Integrator AP has 16-bit timers, Integrator CP, Versatile and Realview
  * can have 16-bit or 32-bit selectable via a bit in the control register.
+ *
+ * Every SP804 contains two identical timers.
  */
+#define TIMER_1_BASE    0x00
+#define TIMER_2_BASE    0x20
+
 #define TIMER_LOAD      0x00                    /* ACVR rw */
 #define TIMER_VALUE     0x04                    /* ACVR ro */
 #define TIMER_CTRL      0x08                    /* ACVR rw */
diff --git a/arch/arm/include/asm/hardware/entry-macro-iomd.S b/arch/arm/include/asm/hardware/entry-macro-iomd.S
index e0af4983723..8c215acd9b5 100644
--- a/arch/arm/include/asm/hardware/entry-macro-iomd.S
+++ b/arch/arm/include/asm/hardware/entry-macro-iomd.S
@@ -11,14 +11,6 @@
 /* IOC / IOMD based hardware */
 #include <asm/hardware/iomd.h>
 
-                .macro  disable_fiq
-                mov     r12, #ioc_base_high
-                .if     ioc_base_low
-                orr     r12, r12, #ioc_base_low
-                .endif
-                strb    r12, [r12, #0x38]       @ Disable FIQ register
-                .endm
-
                 .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
                 ldrb    \irqstat, [\base, #IOMD_IRQREQB]        @ get high priority first
                 ldr     \tmp, =irq_prio_h
diff --git a/arch/arm/include/asm/hardware/timer-sp.h b/arch/arm/include/asm/hardware/timer-sp.h
index 4384d81eee7..2dd9d3f83f2 100644
--- a/arch/arm/include/asm/hardware/timer-sp.h
+++ b/arch/arm/include/asm/hardware/timer-sp.h
@@ -1,2 +1,15 @@
-void sp804_clocksource_init(void __iomem *, const char *);
+void __sp804_clocksource_and_sched_clock_init(void __iomem *,
+                                              const char *, int);
+
+static inline void sp804_clocksource_init(void __iomem *base, const char *name)
+{
+        __sp804_clocksource_and_sched_clock_init(base, name, 0);
+}
+
+static inline void sp804_clocksource_and_sched_clock_init(void __iomem *base,
+                                                          const char *name)
+{
+        __sp804_clocksource_and_sched_clock_init(base, name, 1);
+}
+
 void sp804_clockevents_init(void __iomem *, unsigned int, const char *);
diff --git a/arch/arm/include/asm/localtimer.h b/arch/arm/include/asm/localtimer.h
index c6a18424888..f77ffc1eb0c 100644
--- a/arch/arm/include/asm/localtimer.h
+++ b/arch/arm/include/asm/localtimer.h
@@ -11,47 +11,24 @@
 #define __ASM_ARM_LOCALTIMER_H
 
 #include <linux/errno.h>
-#include <linux/interrupt.h>
 
 struct clock_event_device;
 
-/*
- * Setup a per-cpu timer, whether it be a local timer or dummy broadcast
- */
-void percpu_timer_setup(void);
+struct local_timer_ops {
+        int  (*setup)(struct clock_event_device *);
+        void (*stop)(struct clock_event_device *);
+};
 
 #ifdef CONFIG_LOCAL_TIMERS
-
-#ifdef CONFIG_HAVE_ARM_TWD
-
-#include "smp_twd.h"
-
-#define local_timer_stop(c)     twd_timer_stop((c))
-
-#else
-
-/*
- * Stop the local timer
- */
-void local_timer_stop(struct clock_event_device *);
-
-#endif
-
 /*
- * Setup a local timer interrupt for a CPU.
+ * Register a local timer driver
  */
-int local_timer_setup(struct clock_event_device *);
-
+int local_timer_register(struct local_timer_ops *);
 #else
-
-static inline int local_timer_setup(struct clock_event_device *evt)
+static inline int local_timer_register(struct local_timer_ops *ops)
 {
         return -ENXIO;
 }
-
-static inline void local_timer_stop(struct clock_event_device *evt)
-{
-}
 #endif
 
 #endif
diff --git a/arch/arm/include/asm/pci.h b/arch/arm/include/asm/pci.h
index da337ba57ff..a98a2e112fa 100644
--- a/arch/arm/include/asm/pci.h
+++ b/arch/arm/include/asm/pci.h
@@ -57,14 +57,6 @@ static inline void pci_dma_burst_advice(struct pci_dev *pdev,
 extern int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
                                enum pci_mmap_state mmap_state, int write_combine);
 
-extern void
-pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
-                         struct resource *res);
-
-extern void
-pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
-                        struct pci_bus_region *region);
-
 /*
  * Dummy implementation; always return 0.
  */
diff --git a/arch/arm/include/asm/pgtable-nommu.h b/arch/arm/include/asm/pgtable-nommu.h
index ffc0e85775b..7ec60d6075b 100644
--- a/arch/arm/include/asm/pgtable-nommu.h
+++ b/arch/arm/include/asm/pgtable-nommu.h
@@ -79,7 +79,6 @@ extern unsigned int kobjsize(const void *objp);
  * No page table caches to initialise.
  */
 #define pgtable_cache_init()    do { } while (0)
-#define io_remap_page_range     remap_page_range
 #define io_remap_pfn_range      remap_pfn_range
 
 
diff --git a/arch/arm/include/asm/smp_twd.h b/arch/arm/include/asm/smp_twd.h
index ef9ffba97ad..0f01f4677bd 100644
--- a/arch/arm/include/asm/smp_twd.h
+++ b/arch/arm/include/asm/smp_twd.h
@@ -18,11 +18,28 @@
 #define TWD_TIMER_CONTROL_PERIODIC      (1 << 1)
 #define TWD_TIMER_CONTROL_IT_ENABLE     (1 << 2)
 
-struct clock_event_device;
+#include <linux/ioport.h>
 
-extern void __iomem *twd_base;
+struct twd_local_timer {
+        struct resource res[2];
+};
 
-void twd_timer_setup(struct clock_event_device *);
-void twd_timer_stop(struct clock_event_device *);
+#define DEFINE_TWD_LOCAL_TIMER(name,base,irq)   \
+struct twd_local_timer name __initdata = {      \
+        .res    = {                             \
+                DEFINE_RES_MEM(base, 0x10),     \
+                DEFINE_RES_IRQ(irq),            \
+        },                                      \
+};
+
+int twd_local_timer_register(struct twd_local_timer *);
+
+#ifdef CONFIG_HAVE_ARM_TWD
+void twd_local_timer_of_register(void);
+#else
+static inline void twd_local_timer_of_register(void)
+{
+}
+#endif
 
 #endif
diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h
index e4c96cc6ec0..424aa458c48 100644
--- a/arch/arm/include/asm/system.h
+++ b/arch/arm/include/asm/system.h
@@ -110,6 +110,7 @@ extern void cpu_init(void);
 
 void soft_restart(unsigned long);
 extern void (*arm_pm_restart)(char str, const char *cmd);
+extern void (*arm_pm_idle)(void);
 
 #define UDBG_UNDEFINED  (1 << 0)
 #define UDBG_SYSCALL    (1 << 1)
diff --git a/arch/arm/kernel/Makefile b/arch/arm/kernel/Makefile
index 43b740d0e37..f16d7652f34 100644
--- a/arch/arm/kernel/Makefile
+++ b/arch/arm/kernel/Makefile
@@ -62,9 +62,6 @@ obj-$(CONFIG_SWP_EMULATE)	+= swp_emulate.o
 CFLAGS_swp_emulate.o            := -Wa,-march=armv7-a
 obj-$(CONFIG_HAVE_HW_BREAKPOINT)        += hw_breakpoint.o
 
-obj-$(CONFIG_CRUNCH)            += crunch.o crunch-bits.o
-AFLAGS_crunch-bits.o            := -Wa,-mcpu=ep9312
-
 obj-$(CONFIG_CPU_XSCALE)        += xscale-cp0.o
 obj-$(CONFIG_CPU_XSC3)          += xscale-cp0.o
 obj-$(CONFIG_CPU_MOHAWK)        += xscale-cp0.o
diff --git a/arch/arm/kernel/bios32.c b/arch/arm/kernel/bios32.c
index f58ba358990..632df9a66f8 100644
--- a/arch/arm/kernel/bios32.c
+++ b/arch/arm/kernel/bios32.c
@@ -16,7 +16,6 @@
 #include <asm/mach/pci.h>
 
 static int debug_pci;
-static int use_firmware;
 
 /*
  * We can't use pci_find_device() here since we are
@@ -295,28 +294,6 @@ static inline int pdev_bad_for_parity(struct pci_dev *dev)
 }
 
 /*
- * Adjust the device resources from bus-centric to Linux-centric.
- */
-static void __devinit
-pdev_fixup_device_resources(struct pci_sys_data *root, struct pci_dev *dev)
-{
-        resource_size_t offset;
-        int i;
-
-        for (i = 0; i < PCI_NUM_RESOURCES; i++) {
-                if (dev->resource[i].start == 0)
-                        continue;
-                if (dev->resource[i].flags & IORESOURCE_MEM)
-                        offset = root->mem_offset;
-                else
-                        offset = root->io_offset;
-
-                dev->resource[i].start += offset;
-                dev->resource[i].end   += offset;
-        }
-}
-
-/*
  * pcibios_fixup_bus - Called after each bus is probed,
  * but before its children are examined.
  */
@@ -333,8 +310,6 @@ void pcibios_fixup_bus(struct pci_bus *bus)
         list_for_each_entry(dev, &bus->devices, bus_list) {
                 u16 status;
 
-                pdev_fixup_device_resources(root, dev);
-
                 pci_read_config_word(dev, PCI_STATUS, &status);
 
                 /*
@@ -400,43 +375,6 @@ EXPORT_SYMBOL(pcibios_fixup_bus);
 #endif
 
 /*
- * Convert from Linux-centric to bus-centric addresses for bridge devices.
- */
-void
-pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
-                         struct resource *res)
-{
-        struct pci_sys_data *root = dev->sysdata;
-        unsigned long offset = 0;
-
-        if (res->flags & IORESOURCE_IO)
-                offset = root->io_offset;
-        if (res->flags & IORESOURCE_MEM)
-                offset = root->mem_offset;
-
-        region->start = res->start - offset;
-        region->end   = res->end - offset;
-}
-EXPORT_SYMBOL(pcibios_resource_to_bus);
-
-void __devinit
-pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
-                        struct pci_bus_region *region)
-{
-        struct pci_sys_data *root = dev->sysdata;
-        unsigned long offset = 0;
-
-        if (res->flags & IORESOURCE_IO)
-                offset = root->io_offset;
-        if (res->flags & IORESOURCE_MEM)
-                offset = root->mem_offset;
-
-        res->start = region->start + offset;
-        res->end   = region->end + offset;
-}
-EXPORT_SYMBOL(pcibios_bus_to_resource);
-
-/*
  * Swizzle the device pin each time we cross a bridge.
  * This might update pin and returns the slot number.
  */
@@ -497,10 +435,10 @@ static void __init pcibios_init_hw(struct hw_pci *hw)
 
                 if (ret > 0) {
                         if (list_empty(&sys->resources)) {
-                                pci_add_resource(&sys->resources,
-                                                 &ioport_resource);
-                                pci_add_resource(&sys->resources,
-                                                 &iomem_resource);
+                                pci_add_resource_offset(&sys->resources,
+                                         &ioport_resource, sys->io_offset);
+                                pci_add_resource_offset(&sys->resources,
+                                         &iomem_resource, sys->mem_offset);
                         }
 
                         sys->bus = hw->scan(nr, sys);
@@ -525,6 +463,7 @@ void __init pci_common_init(struct hw_pci *hw)
 
         INIT_LIST_HEAD(&hw->buses);
 
+        pci_add_flags(PCI_REASSIGN_ALL_RSRC);
         if (hw->preinit)
                 hw->preinit();
         pcibios_init_hw(hw);
@@ -536,7 +475,7 @@ void __init pci_common_init(struct hw_pci *hw)
         list_for_each_entry(sys, &hw->buses, node) {
                 struct pci_bus *bus = sys->bus;
 
-                if (!use_firmware) {
+                if (!pci_has_flag(PCI_PROBE_ONLY)) {
                         /*
                          * Size the bridge windows.
                          */
@@ -573,7 +512,7 @@ char * __init pcibios_setup(char *str)
                 debug_pci = 1;
                 return NULL;
         } else if (!strcmp(str, "firmware")) {
-                use_firmware = 1;
+                pci_add_flags(PCI_PROBE_ONLY);
                 return NULL;
         }
         return str;
diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S
index be16a48007b..22f0ed324f3 100644
--- a/arch/arm/kernel/entry-armv.S
+++ b/arch/arm/kernel/entry-armv.S
@@ -19,7 +19,9 @@
 #include <asm/glue-df.h>
 #include <asm/glue-pf.h>
 #include <asm/vfpmacros.h>
+#ifndef CONFIG_MULTI_IRQ_HANDLER
 #include <mach/entry-macro.S>
+#endif
 #include <asm/thread_notify.h>
 #include <asm/unwind.h>
 #include <asm/unistd.h>
@@ -1101,7 +1103,6 @@ __stubs_start:
  * get out of that mode without clobbering one register.
  */
 vector_fiq:
-        disable_fiq
         subs    pc, lr, #4
 
 /*=============================================================================
diff --git a/arch/arm/kernel/entry-common.S b/arch/arm/kernel/entry-common.S
index 9fd0ba90c1d..54ee265dd81 100644
--- a/arch/arm/kernel/entry-common.S
+++ b/arch/arm/kernel/entry-common.S
@@ -10,9 +10,15 @@
 
 #include <asm/unistd.h>
 #include <asm/ftrace.h>
-#include <mach/entry-macro.S>
 #include <asm/unwind.h>
 
+#ifdef CONFIG_NEED_RET_TO_USER
+#include <mach/entry-macro.S>
+#else
+        .macro  arch_ret_to_user, tmp1, tmp2
+        .endm
+#endif
+
 #include "entry-header.S"
 
 
diff --git a/arch/arm/kernel/process.c b/arch/arm/kernel/process.c
index c2ae3cd331f..d3eca452453 100644
--- a/arch/arm/kernel/process.c
+++ b/arch/arm/kernel/process.c
@@ -61,8 +61,6 @@ extern void setup_mm_for_reboot(void);
 
 static volatile int hlt_counter;
 
-#include <mach/system.h>
-
 void disable_hlt(void)
 {
         hlt_counter++;
@@ -181,13 +179,17 @@ void cpu_idle_wait(void)
 EXPORT_SYMBOL_GPL(cpu_idle_wait);
 
 /*
- * This is our default idle handler.  We need to disable
- * interrupts here to ensure we don't miss a wakeup call.
+ * This is our default idle handler.
  */
+
+void (*arm_pm_idle)(void);
+
 static void default_idle(void)
 {
-        if (!need_resched())
-                arch_idle();
+        if (arm_pm_idle)
+                arm_pm_idle();
+        else
+                cpu_do_idle();
         local_irq_enable();
 }
 
@@ -215,6 +217,10 @@ void cpu_idle(void)
                                 cpu_die();
 #endif
 
+                        /*
+                         * We need to disable interrupts here
+                         * to ensure we don't miss a wakeup call.
+                         */
                         local_irq_disable();
 #ifdef CONFIG_PL310_ERRATA_769419
                         wmb();
@@ -222,19 +228,18 @@ void cpu_idle(void)
                         if (hlt_counter) {
                                 local_irq_enable();
                                 cpu_relax();
-                        } else {
+                        } else if (!need_resched()) {
                                 stop_critical_timings();
                                 if (cpuidle_idle_call())
                                         pm_idle();
                                 start_critical_timings();
                                 /*
-                                 * This will eventually be removed - pm_idle
-                                 * functions should always return with IRQs
-                                 * enabled.
+                                 * pm_idle functions must always
+                                 * return with IRQs enabled.
                                  */
                                 WARN_ON(irqs_disabled());
+                        } else
                                 local_irq_enable();
-                        }
                 }
                 leds_event(led_idle_end);
                 rcu_idle_exit();
@@ -533,8 +538,7 @@ int vectors_user_mapping(void)
         struct mm_struct *mm = current->mm;
         return install_special_mapping(mm, 0xffff0000, PAGE_SIZE,
                                        VM_READ | VM_EXEC |
-                                       VM_MAYREAD | VM_MAYEXEC |
-                                       VM_ALWAYSDUMP | VM_RESERVED,
+                                       VM_MAYREAD | VM_MAYEXEC | VM_RESERVED,
                                        NULL);
 }
 
diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c
index d616ed51e7a..8f8cce2c46c 100644
--- a/arch/arm/kernel/smp.c
+++ b/arch/arm/kernel/smp.c
@@ -246,6 +246,8 @@ static void __cpuinit smp_store_cpu_info(unsigned int cpuid)
         store_cpu_topology(cpuid);
 }
 
+static void percpu_timer_setup(void);
+
 /*
  * This is the secondary CPU boot entry.  We're using this CPUs
  * idle thread stack, but a set of temporary page tables.
@@ -452,7 +454,20 @@ static void __cpuinit broadcast_timer_setup(struct clock_event_device *evt)
         clockevents_register_device(evt);
 }
 
-void __cpuinit percpu_timer_setup(void)
+static struct local_timer_ops *lt_ops;
+
+#ifdef CONFIG_LOCAL_TIMERS
+int local_timer_register(struct local_timer_ops *ops)
+{
+        if (lt_ops)
+                return -EBUSY;
+
+        lt_ops = ops;
+        return 0;
+}
+#endif
+
+static void __cpuinit percpu_timer_setup(void)
 {
         unsigned int cpu = smp_processor_id();
         struct clock_event_device *evt = &per_cpu(percpu_clockevent, cpu);
@@ -460,7 +475,7 @@ void __cpuinit percpu_timer_setup(void)
         evt->cpumask = cpumask_of(cpu);
         evt->broadcast = smp_timer_broadcast;
 
-        if (local_timer_setup(evt))
+        if (!lt_ops || lt_ops->setup(evt))
                 broadcast_timer_setup(evt);
 }
 
@@ -475,7 +490,8 @@ static void percpu_timer_stop(void)
         unsigned int cpu = smp_processor_id();
         struct clock_event_device *evt = &per_cpu(percpu_clockevent, cpu);
 
-        local_timer_stop(evt);
+        if (lt_ops)
+                lt_ops->stop(evt);
 }
 #endif
 
diff --git a/arch/arm/kernel/smp_twd.c b/arch/arm/kernel/smp_twd.c
index 7a79b24597b..fef42b21cec 100644
--- a/arch/arm/kernel/smp_twd.c
+++ b/arch/arm/kernel/smp_twd.c
@@ -18,20 +18,23 @@
 #include <linux/smp.h>
 #include <linux/jiffies.h>
 #include <linux/clockchips.h>
-#include <linux/irq.h>
+#include <linux/interrupt.h>
 #include <linux/io.h>
+#include <linux/of_irq.h>
+#include <linux/of_address.h>
 
 #include <asm/smp_twd.h>
 #include <asm/localtimer.h>
 #include <asm/hardware/gic.h>
 
 /* set up by the platform code */
-void __iomem *twd_base;
+static void __iomem *twd_base;
 
 static struct clk *twd_clk;
 static unsigned long twd_timer_rate;
 
 static struct clock_event_device __percpu **twd_evt;
+static int twd_ppi;
 
 static void twd_set_mode(enum clock_event_mode mode,
                         struct clock_event_device *clk)
@@ -77,7 +80,7 @@ static int twd_set_next_event(unsigned long evt,
  * If a local timer interrupt has occurred, acknowledge and return 1.
  * Otherwise, return 0.
  */
-int twd_timer_ack(void)
+static int twd_timer_ack(void)
 {
         if (__raw_readl(twd_base + TWD_TIMER_INTSTAT)) {
                 __raw_writel(1, twd_base + TWD_TIMER_INTSTAT);
@@ -87,7 +90,7 @@ int twd_timer_ack(void)
         return 0;
 }
 
-void twd_timer_stop(struct clock_event_device *clk)
+static void twd_timer_stop(struct clock_event_device *clk)
 {
         twd_set_mode(CLOCK_EVT_MODE_UNUSED, clk);
         disable_percpu_irq(clk->irq);
@@ -222,28 +225,10 @@ static struct clk *twd_get_clock(void)
 /*
  * Setup the local clock events for a CPU.
  */
-void __cpuinit twd_timer_setup(struct clock_event_device *clk)
+static int __cpuinit twd_timer_setup(struct clock_event_device *clk)
 {
         struct clock_event_device **this_cpu_clk;
 
-        if (!twd_evt) {
-                int err;
-
-                twd_evt = alloc_percpu(struct clock_event_device *);
-                if (!twd_evt) {
-                        pr_err("twd: can't allocate memory\n");
-                        return;
-                }
-
-                err = request_percpu_irq(clk->irq, twd_handler,
-                                         "twd", twd_evt);
-                if (err) {
-                        pr_err("twd: can't register interrupt %d (%d)\n",
-                               clk->irq, err);
-                        return;
-                }
-        }
-
         if (!twd_clk)
                 twd_clk = twd_get_clock();
 
@@ -260,6 +245,7 @@ void __cpuinit twd_timer_setup(struct clock_event_device *clk)
         clk->rating = 350;
         clk->set_mode = twd_set_mode;
         clk->set_next_event = twd_set_next_event;
+        clk->irq = twd_ppi;
 
         this_cpu_clk = __this_cpu_ptr(twd_evt);
         *this_cpu_clk = clk;
@@ -267,4 +253,95 @@ void __cpuinit twd_timer_setup(struct clock_event_device *clk)
         clockevents_config_and_register(clk, twd_timer_rate,
                                         0xf, 0xffffffff);
         enable_percpu_irq(clk->irq, 0);
+
+        return 0;
+}
+
+static struct local_timer_ops twd_lt_ops __cpuinitdata = {
+        .setup  = twd_timer_setup,
+        .stop   = twd_timer_stop,
+};
+
+static int __init twd_local_timer_common_register(void)
+{
+        int err;
+
+        twd_evt = alloc_percpu(struct clock_event_device *);
+        if (!twd_evt) {
+                err = -ENOMEM;
+                goto out_free;
+        }
+
+        err = request_percpu_irq(twd_ppi, twd_handler, "twd", twd_evt);
+        if (err) {
+                pr_err("twd: can't register interrupt %d (%d)\n", twd_ppi, err);
+                goto out_free;
+        }
+
+        err = local_timer_register(&twd_lt_ops);
+        if (err)
+                goto out_irq;
+
+        return 0;
+
+out_irq:
+        free_percpu_irq(twd_ppi, twd_evt);
+out_free:
+        iounmap(twd_base);
+        twd_base = NULL;
+        free_percpu(twd_evt);
+
+        return err;
 }
+
+int __init twd_local_timer_register(struct twd_local_timer *tlt)
+{
+        if (twd_base || twd_evt)
+                return -EBUSY;
+
+        twd_ppi = tlt->res[1].start;
+
+        twd_base = ioremap(tlt->res[0].start, resource_size(&tlt->res[0]));
+        if (!twd_base)
+                return -ENOMEM;
+
+        return twd_local_timer_common_register();
+}
+
+#ifdef CONFIG_OF
+const static struct of_device_id twd_of_match[] __initconst = {
+        { .compatible = "arm,cortex-a9-twd-timer",      },
+        { .compatible = "arm,cortex-a5-twd-timer",      },
+        { .compatible = "arm,arm11mp-twd-timer",        },
+        { },
+};
+
+void __init twd_local_timer_of_register(void)
+{
+        struct device_node *np;
+        int err;
+
+        np = of_find_matching_node(NULL, twd_of_match);
+        if (!np) {
+                err = -ENODEV;
+                goto out;
+        }
+
+        twd_ppi = irq_of_parse_and_map(np, 0);
+        if (!twd_ppi) {
+                err = -EINVAL;
+                goto out;
+        }
+
+        twd_base = of_iomap(np, 0);
+        if (!twd_base) {
+                err = -ENOMEM;
+                goto out;
+        }
+
+        err = twd_local_timer_common_register();
+
+out:
+        WARN(err, "twd_local_timer_of_register failed (%d)\n", err);
+}
+#endif
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index 71feb00a1e9..e55cdcbd81f 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -102,13 +102,13 @@ config ARCH_AT91SAM9G45
         select HAVE_AT91_DBGU1
         select AT91_SAM9G45_RESET
 
-config ARCH_AT91CAP9
-        bool "AT91CAP9"
+config ARCH_AT91SAM9X5
+        bool "AT91SAM9x5 family"
         select CPU_ARM926T
         select GENERIC_CLOCKEVENTS
         select HAVE_FB_ATMEL
         select HAVE_NET_MACB
-        select HAVE_AT91_DBGU1
+        select HAVE_AT91_DBGU0
         select AT91_SAM9G45_RESET
 
 config ARCH_AT91X40
@@ -447,21 +447,6 @@ endif
 
 # ----------------------------------------------------------
 
-if ARCH_AT91CAP9
-
-comment "AT91CAP9 Board Type"
-
-config MACH_AT91CAP9ADK
-        bool "Atmel AT91CAP9A-DK Evaluation Kit"
-        select HAVE_AT91_DATAFLASH_CARD
-        help
-          Select this if you are using Atmel's AT91CAP9A-DK Evaluation Kit.
-          <http://www.atmel.com/dyn/products/tools_card.asp?tool_id=4138>
-
-endif
-
-# ----------------------------------------------------------
-
 if ARCH_AT91X40
 
 comment "AT91X40 Board Type"
@@ -544,7 +529,7 @@ config AT91_EARLY_DBGU0
         depends on HAVE_AT91_DBGU0
 
 config AT91_EARLY_DBGU1
-        bool "DBGU on 9263, 9g45 and cap9"
+        bool "DBGU on 9263 and 9g45"
         depends on HAVE_AT91_DBGU1
 
 config AT91_EARLY_USART0
diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile
index 705e1fbded3..8512e53bed9 100644
--- a/arch/arm/mach-at91/Makefile
+++ b/arch/arm/mach-at91/Makefile
@@ -20,7 +20,7 @@ obj-$(CONFIG_ARCH_AT91SAM9263)	+= at91sam9263.o at91sam926x_time.o at91sam9263_d
 obj-$(CONFIG_ARCH_AT91SAM9RL)   += at91sam9rl.o at91sam926x_time.o at91sam9rl_devices.o sam9_smc.o
 obj-$(CONFIG_ARCH_AT91SAM9G20)  += at91sam9260.o at91sam926x_time.o at91sam9260_devices.o sam9_smc.o
 obj-$(CONFIG_ARCH_AT91SAM9G45)  += at91sam9g45.o at91sam926x_time.o at91sam9g45_devices.o sam9_smc.o
-obj-$(CONFIG_ARCH_AT91CAP9)     += at91cap9.o at91sam926x_time.o at91cap9_devices.o sam9_smc.o
+obj-$(CONFIG_ARCH_AT91SAM9X5)   += at91sam9x5.o at91sam926x_time.o sam9_smc.o
 obj-$(CONFIG_ARCH_AT91X40)      += at91x40.o at91x40_time.o
 
 # AT91RM9200 board-specific support
@@ -81,9 +81,6 @@ obj-$(CONFIG_MACH_AT91SAM9M10G45EK) += board-sam9m10g45ek.o
 # AT91SAM board with device-tree
 obj-$(CONFIG_MACH_AT91SAM_DT) += board-dt.o
 
-# AT91CAP9 board-specific support
-obj-$(CONFIG_MACH_AT91CAP9ADK)  += board-cap9adk.o
-
 # AT91X40 board-specific support
 obj-$(CONFIG_MACH_AT91EB01)     += board-eb01.o
 
diff --git a/arch/arm/mach-at91/Makefile.boot b/arch/arm/mach-at91/Makefile.boot
index 8ddafadfdc7..0da66ca4a4f 100644
--- a/arch/arm/mach-at91/Makefile.boot
+++ b/arch/arm/mach-at91/Makefile.boot
@@ -3,11 +3,7 @@
 #   PARAMS_PHYS must be within 4MB of ZRELADDR
 #   INITRD_PHYS must be in RAM
 
-ifeq ($(CONFIG_ARCH_AT91CAP9),y)
-   zreladdr-y   += 0x70008000
-params_phys-y   := 0x70000100
-initrd_phys-y   := 0x70410000
-else ifeq ($(CONFIG_ARCH_AT91SAM9G45),y)
+ifeq ($(CONFIG_ARCH_AT91SAM9G45),y)
    zreladdr-y   += 0x70008000
 params_phys-y   := 0x70000100
 initrd_phys-y   := 0x70410000
@@ -17,4 +13,10 @@ params_phys-y	:= 0x20000100
 initrd_phys-y   := 0x20410000
 endif
 
-dtb-$(CONFIG_MACH_AT91SAM_DT) += at91sam9m10g45ek.dtb usb_a9g20.dtb
+# Keep dtb files sorted alphabetically for each SoC
+# sam9g20
+dtb-$(CONFIG_MACH_AT91SAM_DT) += usb_a9g20.dtb
+# sam9g45
+dtb-$(CONFIG_MACH_AT91SAM_DT) += at91sam9m10g45ek.dtb
+# sam9x5
+dtb-$(CONFIG_MACH_AT91SAM_DT) += at91sam9g25ek.dtb
diff --git a/arch/arm/mach-at91/at91cap9.c b/arch/arm/mach-at91/at91cap9.c
deleted file mode 100644
index a42edc25a87..00000000000
--- a/arch/arm/mach-at91/at91cap9.c
+++ /dev/null
@@ -1,396 +0,0 @@
-/*
- * arch/arm/mach-at91/at91cap9.c
- *
- *  Copyright (C) 2007 Stelian Pop <stelian.pop@leadtechdesign.com>
- *  Copyright (C) 2007 Lead Tech Design <www.leadtechdesign.com>
- *  Copyright (C) 2007 Atmel Corporation.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- */
-
-#include <linux/module.h>
-
-#include <asm/irq.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-
-#include <mach/cpu.h>
-#include <mach/at91cap9.h>
-#include <mach/at91_pmc.h>
-
-#include "soc.h"
-#include "generic.h"
-#include "clock.h"
-#include "sam9_smc.h"
-
-/* --------------------------------------------------------------------
- *  Clocks
- * -------------------------------------------------------------------- */
-
-/*
- * The peripheral clocks.
- */
-static struct clk pioABCD_clk = {
-        .name           = "pioABCD_clk",
-        .pmc_mask       = 1 << AT91CAP9_ID_PIOABCD,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk mpb0_clk = {
-        .name           = "mpb0_clk",
-        .pmc_mask       = 1 << AT91CAP9_ID_MPB0,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk mpb1_clk = {
-        .name           = "mpb1_clk",
-        .pmc_mask       = 1 << AT91CAP9_ID_MPB1,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk mpb2_clk = {
-        .name           = "mpb2_clk",
-        .pmc_mask       = 1 << AT91CAP9_ID_MPB2,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk mpb3_clk = {
-        .name           = "mpb3_clk",
-        .pmc_mask       = 1 << AT91CAP9_ID_MPB3,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk mpb4_clk = {
-        .name           = "mpb4_clk",
-        .pmc_mask       = 1 << AT91CAP9_ID_MPB4,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk usart0_clk = {
-        .name           = "usart0_clk",
-        .pmc_mask       = 1 << AT91CAP9_ID_US0,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk usart1_clk = {
-        .name           = "usart1_clk",
-        .pmc_mask       = 1 << AT91CAP9_ID_US1,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk usart2_clk = {
-        .name           = "usart2_clk",
-        .pmc_mask       = 1 << AT91CAP9_ID_US2,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk mmc0_clk = {
-        .name           = "mci0_clk",
-        .pmc_mask       = 1 << AT91CAP9_ID_MCI0,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk mmc1_clk = {
-        .name           = "mci1_clk",
-        .pmc_mask       = 1 << AT91CAP9_ID_MCI1,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk can_clk = {
-        .name           = "can_clk",
-        .pmc_mask       = 1 << AT91CAP9_ID_CAN,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk twi_clk = {
-        .name           = "twi_clk",
-        .pmc_mask       = 1 << AT91CAP9_ID_TWI,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk spi0_clk = {
-        .name           = "spi0_clk",
-        .pmc_mask       = 1 << AT91CAP9_ID_SPI0,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk spi1_clk = {
-        .name           = "spi1_clk",
-        .pmc_mask       = 1 << AT91CAP9_ID_SPI1,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk ssc0_clk = {
-        .name           = "ssc0_clk",
-        .pmc_mask       = 1 << AT91CAP9_ID_SSC0,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk ssc1_clk = {
-        .name           = "ssc1_clk",
-        .pmc_mask       = 1 << AT91CAP9_ID_SSC1,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk ac97_clk = {
-        .name           = "ac97_clk",
-        .pmc_mask       = 1 << AT91CAP9_ID_AC97C,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk tcb_clk = {
-        .name           = "tcb_clk",
-        .pmc_mask       = 1 << AT91CAP9_ID_TCB,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk pwm_clk = {
-        .name           = "pwm_clk",
-        .pmc_mask       = 1 << AT91CAP9_ID_PWMC,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk macb_clk = {
-        .name           = "pclk",
-        .pmc_mask       = 1 << AT91CAP9_ID_EMAC,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk aestdes_clk = {
-        .name           = "aestdes_clk",
-        .pmc_mask       = 1 << AT91CAP9_ID_AESTDES,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk adc_clk = {
-        .name           = "adc_clk",
-        .pmc_mask       = 1 << AT91CAP9_ID_ADC,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk isi_clk = {
-        .name           = "isi_clk",
-        .pmc_mask       = 1 << AT91CAP9_ID_ISI,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk lcdc_clk = {
-        .name           = "lcdc_clk",
-        .pmc_mask       = 1 << AT91CAP9_ID_LCDC,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk dma_clk = {
-        .name           = "dma_clk",
-        .pmc_mask       = 1 << AT91CAP9_ID_DMA,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk udphs_clk = {
-        .name           = "udphs_clk",
-        .pmc_mask       = 1 << AT91CAP9_ID_UDPHS,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk ohci_clk = {
-        .name           = "ohci_clk",
-        .pmc_mask       = 1 << AT91CAP9_ID_UHP,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-
-static struct clk *periph_clocks[] __initdata = {
-        &pioABCD_clk,
-        &mpb0_clk,
-        &mpb1_clk,
-        &mpb2_clk,
-        &mpb3_clk,
-        &mpb4_clk,
-        &usart0_clk,
-        &usart1_clk,
-        &usart2_clk,
-        &mmc0_clk,
-        &mmc1_clk,
-        &can_clk,
-        &twi_clk,
-        &spi0_clk,
-        &spi1_clk,
-        &ssc0_clk,
-        &ssc1_clk,
-        &ac97_clk,
-        &tcb_clk,
-        &pwm_clk,
-        &macb_clk,
-        &aestdes_clk,
-        &adc_clk,
-        &isi_clk,
-        &lcdc_clk,
-        &dma_clk,
-        &udphs_clk,
-        &ohci_clk,
-        // irq0 .. irq1
-};
-
-static struct clk_lookup periph_clocks_lookups[] = {
-        /* One additional fake clock for macb_hclk */
-        CLKDEV_CON_ID("hclk", &macb_clk),
-        CLKDEV_CON_DEV_ID("hclk", "atmel_usba_udc", &utmi_clk),
-        CLKDEV_CON_DEV_ID("pclk", "atmel_usba_udc", &udphs_clk),
-        CLKDEV_CON_DEV_ID("mci_clk", "at91_mci.0", &mmc0_clk),
-        CLKDEV_CON_DEV_ID("mci_clk", "at91_mci.1", &mmc1_clk),
-        CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.0", &spi0_clk),
-        CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.1", &spi1_clk),
-        CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tcb_clk),
-        CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc0_clk),
-        CLKDEV_CON_DEV_ID("pclk", "ssc.1", &ssc1_clk),
-        /* fake hclk clock */
-        CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &ohci_clk),
-        CLKDEV_CON_ID("pioA", &pioABCD_clk),
-        CLKDEV_CON_ID("pioB", &pioABCD_clk),
-        CLKDEV_CON_ID("pioC", &pioABCD_clk),
-        CLKDEV_CON_ID("pioD", &pioABCD_clk),
-};
-
-static struct clk_lookup usart_clocks_lookups[] = {
-        CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck),
-        CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk),
-        CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk),
-        CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk),
-};
-
-/*
- * The four programmable clocks.
- * You must configure pin multiplexing to bring these signals out.
- */
-static struct clk pck0 = {
-        .name           = "pck0",
-        .pmc_mask       = AT91_PMC_PCK0,
-        .type           = CLK_TYPE_PROGRAMMABLE,
-        .id             = 0,
-};
-static struct clk pck1 = {
-        .name           = "pck1",
-        .pmc_mask       = AT91_PMC_PCK1,
-        .type           = CLK_TYPE_PROGRAMMABLE,
-        .id             = 1,
-};
-static struct clk pck2 = {
-        .name           = "pck2",
-        .pmc_mask       = AT91_PMC_PCK2,
-        .type           = CLK_TYPE_PROGRAMMABLE,
-        .id             = 2,
-};
-static struct clk pck3 = {
-        .name           = "pck3",
-        .pmc_mask       = AT91_PMC_PCK3,
-        .type           = CLK_TYPE_PROGRAMMABLE,
-        .id             = 3,
-};
-
-static void __init at91cap9_register_clocks(void)
-{
-        int i;
-
-        for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
-                clk_register(periph_clocks[i]);
-
-        clkdev_add_table(periph_clocks_lookups,
-                         ARRAY_SIZE(periph_clocks_lookups));
-        clkdev_add_table(usart_clocks_lookups,
-                         ARRAY_SIZE(usart_clocks_lookups));
-
-        clk_register(&pck0);
-        clk_register(&pck1);
-        clk_register(&pck2);
-        clk_register(&pck3);
-}
-
-static struct clk_lookup console_clock_lookup;
-
-void __init at91cap9_set_console_clock(int id)
-{
-        if (id >= ARRAY_SIZE(usart_clocks_lookups))
-                return;
-
-        console_clock_lookup.con_id = "usart";
-        console_clock_lookup.clk = usart_clocks_lookups[id].clk;
-        clkdev_add(&console_clock_lookup);
-}
-
-/* --------------------------------------------------------------------
- *  GPIO
- * -------------------------------------------------------------------- */
-
-static struct at91_gpio_bank at91cap9_gpio[] __initdata = {
-        {
-                .id             = AT91CAP9_ID_PIOABCD,
-                .regbase        = AT91CAP9_BASE_PIOA,
-        }, {
-                .id             = AT91CAP9_ID_PIOABCD,
-                .regbase        = AT91CAP9_BASE_PIOB,
-        }, {
-                .id             = AT91CAP9_ID_PIOABCD,
-                .regbase        = AT91CAP9_BASE_PIOC,
-        }, {
-                .id             = AT91CAP9_ID_PIOABCD,
-                .regbase        = AT91CAP9_BASE_PIOD,
-        }
-};
-
-/* --------------------------------------------------------------------
- *  AT91CAP9 processor initialization
- * -------------------------------------------------------------------- */
-
-static void __init at91cap9_map_io(void)
-{
-        at91_init_sram(0, AT91CAP9_SRAM_BASE, AT91CAP9_SRAM_SIZE);
-}
-
-static void __init at91cap9_ioremap_registers(void)
-{
-        at91_ioremap_shdwc(AT91CAP9_BASE_SHDWC);
-        at91_ioremap_rstc(AT91CAP9_BASE_RSTC);
-        at91sam926x_ioremap_pit(AT91CAP9_BASE_PIT);
-        at91sam9_ioremap_smc(0, AT91CAP9_BASE_SMC);
-}
-
-static void __init at91cap9_initialize(void)
-{
-        arm_pm_restart = at91sam9g45_restart;
-        at91_extern_irq = (1 << AT91CAP9_ID_IRQ0) | (1 << AT91CAP9_ID_IRQ1);
-
-        /* Register GPIO subsystem */
-        at91_gpio_init(at91cap9_gpio, 4);
-
-        /* Remember the silicon revision */
-        if (cpu_is_at91cap9_revB())
-                system_rev = 0xB;
-        else if (cpu_is_at91cap9_revC())
-                system_rev = 0xC;
-}
-
-/* --------------------------------------------------------------------
- *  Interrupt initialization
- * -------------------------------------------------------------------- */
-
-/*
- * The default interrupt priority levels (0 = lowest, 7 = highest).
- */
-static unsigned int at91cap9_default_irq_priority[NR_AIC_IRQS] __initdata = {
-        7,      /* Advanced Interrupt Controller (FIQ) */
-        7,      /* System Peripherals */
-        1,      /* Parallel IO Controller A, B, C and D */
-        0,      /* MP Block Peripheral 0 */
-        0,      /* MP Block Peripheral 1 */
-        0,      /* MP Block Peripheral 2 */
-        0,      /* MP Block Peripheral 3 */
-        0,      /* MP Block Peripheral 4 */
-        5,      /* USART 0 */
-        5,      /* USART 1 */
-        5,      /* USART 2 */
-        0,      /* Multimedia Card Interface 0 */
-        0,      /* Multimedia Card Interface 1 */
-        3,      /* CAN */
-        6,      /* Two-Wire Interface */
-        5,      /* Serial Peripheral Interface 0 */
-        5,      /* Serial Peripheral Interface 1 */
-        4,      /* Serial Synchronous Controller 0 */
-        4,      /* Serial Synchronous Controller 1 */
-        5,      /* AC97 Controller */
-        0,      /* Timer Counter 0, 1 and 2 */
-        0,      /* Pulse Width Modulation Controller */
-        3,      /* Ethernet */
-        0,      /* Advanced Encryption Standard, Triple DES*/
-        0,      /* Analog-to-Digital Converter */
-        0,      /* Image Sensor Interface */
-        3,      /* LCD Controller */
-        0,      /* DMA Controller */
-        2,      /* USB Device Port */
-        2,      /* USB Host port */
-        0,      /* Advanced Interrupt Controller (IRQ0) */
-        0,      /* Advanced Interrupt Controller (IRQ1) */
-};
-
-struct at91_init_soc __initdata at91cap9_soc = {
-        .map_io = at91cap9_map_io,
-        .default_irq_priority = at91cap9_default_irq_priority,
-        .ioremap_registers = at91cap9_ioremap_registers,
-        .register_clocks = at91cap9_register_clocks,
-        .init = at91cap9_initialize,
-};
diff --git a/arch/arm/mach-at91/at91cap9_devices.c b/arch/arm/mach-at91/at91cap9_devices.c
deleted file mode 100644
index d298fb7cb21..00000000000
--- a/arch/arm/mach-at91/at91cap9_devices.c
+++ /dev/null
@@ -1,1273 +0,0 @@
-/*
- * arch/arm/mach-at91/at91cap9_devices.c
- *
- *  Copyright (C) 2007 Stelian Pop <stelian.pop@leadtechdesign.com>
- *  Copyright (C) 2007 Lead Tech Design <www.leadtechdesign.com>
- *  Copyright (C) 2007 Atmel Corporation.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- */
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/mach/irq.h>
-
-#include <linux/dma-mapping.h>
-#include <linux/gpio.h>
-#include <linux/platform_device.h>
-#include <linux/i2c-gpio.h>
-
-#include <video/atmel_lcdc.h>
-
-#include <mach/board.h>
-#include <mach/cpu.h>
-#include <mach/at91cap9.h>
-#include <mach/at91cap9_matrix.h>
-#include <mach/at91sam9_smc.h>
-
-#include "generic.h"
-
-
-/* --------------------------------------------------------------------
- *  USB Host
- * -------------------------------------------------------------------- */
-
-#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
-static u64 ohci_dmamask = DMA_BIT_MASK(32);
-static struct at91_usbh_data usbh_data;
-
-static struct resource usbh_resources[] = {
-        [0] = {
-                .start  = AT91CAP9_UHP_BASE,
-                .end    = AT91CAP9_UHP_BASE + SZ_1M - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = AT91CAP9_ID_UHP,
-                .end    = AT91CAP9_ID_UHP,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device at91_usbh_device = {
-        .name           = "at91_ohci",
-        .id             = -1,
-        .dev            = {
-                                .dma_mask               = &ohci_dmamask,
-                                .coherent_dma_mask      = DMA_BIT_MASK(32),
-                                .platform_data          = &usbh_data,
-        },
-        .resource       = usbh_resources,
-        .num_resources  = ARRAY_SIZE(usbh_resources),
-};
-
-void __init at91_add_device_usbh(struct at91_usbh_data *data)
-{
-        int i;
-
-        if (!data)
-                return;
-
-        if (cpu_is_at91cap9_revB())
-                irq_set_irq_type(AT91CAP9_ID_UHP, IRQ_TYPE_LEVEL_HIGH);
-
-        /* Enable VBus control for UHP ports */
-        for (i = 0; i < data->ports; i++) {
-                if (gpio_is_valid(data->vbus_pin[i]))
-                        at91_set_gpio_output(data->vbus_pin[i], 0);
-        }
-
-        /* Enable overcurrent notification */
-        for (i = 0; i < data->ports; i++) {
-                if (data->overcurrent_pin[i])
-                        at91_set_gpio_input(data->overcurrent_pin[i], 1);
-        }
-
-        usbh_data = *data;
-        platform_device_register(&at91_usbh_device);
-}
-#else
-void __init at91_add_device_usbh(struct at91_usbh_data *data) {}
-#endif
-
-
-/* --------------------------------------------------------------------
- *  USB HS Device (Gadget)
- * -------------------------------------------------------------------- */
-
-#if defined(CONFIG_USB_ATMEL_USBA) || defined(CONFIG_USB_ATMEL_USBA_MODULE)
-
-static struct resource usba_udc_resources[] = {
-        [0] = {
-                .start  = AT91CAP9_UDPHS_FIFO,
-                .end    = AT91CAP9_UDPHS_FIFO + SZ_512K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = AT91CAP9_BASE_UDPHS,
-                .end    = AT91CAP9_BASE_UDPHS + SZ_1K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [2] = {
-                .start  = AT91CAP9_ID_UDPHS,
-                .end    = AT91CAP9_ID_UDPHS,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-#define EP(nam, idx, maxpkt, maxbk, dma, isoc)                  \
-        [idx] = {                                               \
-                .name           = nam,                          \
-                .index          = idx,                          \
-                .fifo_size      = maxpkt,                       \
-                .nr_banks       = maxbk,                        \
-                .can_dma        = dma,                          \
-                .can_isoc       = isoc,                         \
-        }
-
-static struct usba_ep_data usba_udc_ep[] = {
-        EP("ep0", 0,   64, 1, 0, 0),
-        EP("ep1", 1, 1024, 3, 1, 1),
-        EP("ep2", 2, 1024, 3, 1, 1),
-        EP("ep3", 3, 1024, 2, 1, 1),
-        EP("ep4", 4, 1024, 2, 1, 1),
-        EP("ep5", 5, 1024, 2, 1, 0),
-        EP("ep6", 6, 1024, 2, 1, 0),
-        EP("ep7", 7, 1024, 2, 0, 0),
-};
-
-#undef EP
-
-/*
- * pdata doesn't have room for any endpoints, so we need to
- * append room for the ones we need right after it.
- */
-static struct {
-        struct usba_platform_data pdata;
-        struct usba_ep_data ep[8];
-} usba_udc_data;
-
-static struct platform_device at91_usba_udc_device = {
-        .name           = "atmel_usba_udc",
-        .id             = -1,
-        .dev            = {
-                                .platform_data  = &usba_udc_data.pdata,
-        },
-        .resource       = usba_udc_resources,
-        .num_resources  = ARRAY_SIZE(usba_udc_resources),
-};
-
-void __init at91_add_device_usba(struct usba_platform_data *data)
-{
-        if (cpu_is_at91cap9_revB()) {
-                irq_set_irq_type(AT91CAP9_ID_UDPHS, IRQ_TYPE_LEVEL_HIGH);
-                at91_sys_write(AT91_MATRIX_UDPHS, AT91_MATRIX_SELECT_UDPHS |
-                                                  AT91_MATRIX_UDPHS_BYPASS_LOCK);
-        }
-        else
-                at91_sys_write(AT91_MATRIX_UDPHS, AT91_MATRIX_SELECT_UDPHS);
-
-        /*
-         * Invalid pins are 0 on AT91, but the usba driver is shared
-         * with AVR32, which use negative values instead. Once/if
-         * gpio_is_valid() is ported to AT91, revisit this code.
-         */
-        usba_udc_data.pdata.vbus_pin = -EINVAL;
-        usba_udc_data.pdata.num_ep = ARRAY_SIZE(usba_udc_ep);
-        memcpy(usba_udc_data.ep, usba_udc_ep, sizeof(usba_udc_ep));
-
-        if (data && gpio_is_valid(data->vbus_pin)) {
-                at91_set_gpio_input(data->vbus_pin, 0);
-                at91_set_deglitch(data->vbus_pin, 1);
-                usba_udc_data.pdata.vbus_pin = data->vbus_pin;
-        }
-
-        /* Pullup pin is handled internally by USB device peripheral */
-
-        platform_device_register(&at91_usba_udc_device);
-}
-#else
-void __init at91_add_device_usba(struct usba_platform_data *data) {}
-#endif
-
-
-/* --------------------------------------------------------------------
- *  Ethernet
- * -------------------------------------------------------------------- */
-
-#if defined(CONFIG_MACB) || defined(CONFIG_MACB_MODULE)
-static u64 eth_dmamask = DMA_BIT_MASK(32);
-static struct macb_platform_data eth_data;
-
-static struct resource eth_resources[] = {
-        [0] = {
-                .start  = AT91CAP9_BASE_EMAC,
-                .end    = AT91CAP9_BASE_EMAC + SZ_16K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = AT91CAP9_ID_EMAC,
-                .end    = AT91CAP9_ID_EMAC,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device at91cap9_eth_device = {
-        .name           = "macb",
-        .id             = -1,
-        .dev            = {
-                                .dma_mask               = &eth_dmamask,
-                                .coherent_dma_mask      = DMA_BIT_MASK(32),
-                                .platform_data          = &eth_data,
-        },
-        .resource       = eth_resources,
-        .num_resources  = ARRAY_SIZE(eth_resources),
-};
-
-void __init at91_add_device_eth(struct macb_platform_data *data)
-{
-        if (!data)
-                return;
-
-        if (gpio_is_valid(data->phy_irq_pin)) {
-                at91_set_gpio_input(data->phy_irq_pin, 0);
-                at91_set_deglitch(data->phy_irq_pin, 1);
-        }
-
-        /* Pins used for MII and RMII */
-        at91_set_A_periph(AT91_PIN_PB21, 0);    /* ETXCK_EREFCK */
-        at91_set_A_periph(AT91_PIN_PB22, 0);    /* ERXDV */
-        at91_set_A_periph(AT91_PIN_PB25, 0);    /* ERX0 */
-        at91_set_A_periph(AT91_PIN_PB26, 0);    /* ERX1 */
-        at91_set_A_periph(AT91_PIN_PB27, 0);    /* ERXER */
-        at91_set_A_periph(AT91_PIN_PB28, 0);    /* ETXEN */
-        at91_set_A_periph(AT91_PIN_PB23, 0);    /* ETX0 */
-        at91_set_A_periph(AT91_PIN_PB24, 0);    /* ETX1 */
-        at91_set_A_periph(AT91_PIN_PB30, 0);    /* EMDIO */
-        at91_set_A_periph(AT91_PIN_PB29, 0);    /* EMDC */
-
-        if (!data->is_rmii) {
-                at91_set_B_periph(AT91_PIN_PC25, 0);    /* ECRS */
-                at91_set_B_periph(AT91_PIN_PC26, 0);    /* ECOL */
-                at91_set_B_periph(AT91_PIN_PC22, 0);    /* ERX2 */
-                at91_set_B_periph(AT91_PIN_PC23, 0);    /* ERX3 */
-                at91_set_B_periph(AT91_PIN_PC27, 0);    /* ERXCK */
-                at91_set_B_periph(AT91_PIN_PC20, 0);    /* ETX2 */
-                at91_set_B_periph(AT91_PIN_PC21, 0);    /* ETX3 */
-                at91_set_B_periph(AT91_PIN_PC24, 0);    /* ETXER */
-        }
-
-        eth_data = *data;
-        platform_device_register(&at91cap9_eth_device);
-}
-#else
-void __init at91_add_device_eth(struct macb_platform_data *data) {}
-#endif
-
-
-/* --------------------------------------------------------------------
- *  MMC / SD
- * -------------------------------------------------------------------- */
-
-#if defined(CONFIG_MMC_AT91) || defined(CONFIG_MMC_AT91_MODULE)
-static u64 mmc_dmamask = DMA_BIT_MASK(32);
-static struct at91_mmc_data mmc0_data, mmc1_data;
-
-static struct resource mmc0_resources[] = {
-        [0] = {
-                .start  = AT91CAP9_BASE_MCI0,
-                .end    = AT91CAP9_BASE_MCI0 + SZ_16K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = AT91CAP9_ID_MCI0,
-                .end    = AT91CAP9_ID_MCI0,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device at91cap9_mmc0_device = {
-        .name           = "at91_mci",
-        .id             = 0,
-        .dev            = {
-                                .dma_mask               = &mmc_dmamask,
-                                .coherent_dma_mask      = DMA_BIT_MASK(32),
-                                .platform_data          = &mmc0_data,
-        },
-        .resource       = mmc0_resources,
-        .num_resources  = ARRAY_SIZE(mmc0_resources),
-};
-
-static struct resource mmc1_resources[] = {
-        [0] = {
-                .start  = AT91CAP9_BASE_MCI1,
-                .end    = AT91CAP9_BASE_MCI1 + SZ_16K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = AT91CAP9_ID_MCI1,
-                .end    = AT91CAP9_ID_MCI1,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device at91cap9_mmc1_device = {
-        .name           = "at91_mci",
-        .id             = 1,
-        .dev            = {
-                                .dma_mask               = &mmc_dmamask,
-                                .coherent_dma_mask      = DMA_BIT_MASK(32),
-                                .platform_data          = &mmc1_data,
-        },
-        .resource       = mmc1_resources,
-        .num_resources  = ARRAY_SIZE(mmc1_resources),
-};
-
-void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data)
-{
-        if (!data)
-                return;
-
-        /* input/irq */
-        if (gpio_is_valid(data->det_pin)) {
-                at91_set_gpio_input(data->det_pin, 1);
-                at91_set_deglitch(data->det_pin, 1);
-        }
-        if (gpio_is_valid(data->wp_pin))
-                at91_set_gpio_input(data->wp_pin, 1);
-        if (gpio_is_valid(data->vcc_pin))
-                at91_set_gpio_output(data->vcc_pin, 0);
-
-        if (mmc_id == 0) {              /* MCI0 */
-                /* CLK */
-                at91_set_A_periph(AT91_PIN_PA2, 0);
-
-                /* CMD */
-                at91_set_A_periph(AT91_PIN_PA1, 1);
-
-                /* DAT0, maybe DAT1..DAT3 */
-                at91_set_A_periph(AT91_PIN_PA0, 1);
-                if (data->wire4) {
-                        at91_set_A_periph(AT91_PIN_PA3, 1);
-                        at91_set_A_periph(AT91_PIN_PA4, 1);
-                        at91_set_A_periph(AT91_PIN_PA5, 1);
-                }
-
-                mmc0_data = *data;
-                platform_device_register(&at91cap9_mmc0_device);
-        } else {                        /* MCI1 */
-                /* CLK */
-                at91_set_A_periph(AT91_PIN_PA16, 0);
-
-                /* CMD */
-                at91_set_A_periph(AT91_PIN_PA17, 1);
-
-                /* DAT0, maybe DAT1..DAT3 */
-                at91_set_A_periph(AT91_PIN_PA18, 1);
-                if (data->wire4) {
-                        at91_set_A_periph(AT91_PIN_PA19, 1);
-                        at91_set_A_periph(AT91_PIN_PA20, 1);
-                        at91_set_A_periph(AT91_PIN_PA21, 1);
-                }
-
-                mmc1_data = *data;
-                platform_device_register(&at91cap9_mmc1_device);
-        }
-}
-#else
-void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data) {}
-#endif
-
-
-/* --------------------------------------------------------------------
- *  NAND / SmartMedia
- * -------------------------------------------------------------------- */
-
-#if defined(CONFIG_MTD_NAND_ATMEL) || defined(CONFIG_MTD_NAND_ATMEL_MODULE)
-static struct atmel_nand_data nand_data;
-
-#define NAND_BASE       AT91_CHIPSELECT_3
-
-static struct resource nand_resources[] = {
-        [0] = {
-                .start  = NAND_BASE,
-                .end    = NAND_BASE + SZ_256M - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = AT91CAP9_BASE_ECC,
-                .end    = AT91CAP9_BASE_ECC + SZ_512 - 1,
-                .flags  = IORESOURCE_MEM,
-        }
-};
-
-static struct platform_device at91cap9_nand_device = {
-        .name           = "atmel_nand",
-        .id             = -1,
-        .dev            = {
-                                .platform_data  = &nand_data,
-        },
-        .resource       = nand_resources,
-        .num_resources  = ARRAY_SIZE(nand_resources),
-};
-
-void __init at91_add_device_nand(struct atmel_nand_data *data)
-{
-        unsigned long csa;
-
-        if (!data)
-                return;
-
-        csa = at91_sys_read(AT91_MATRIX_EBICSA);
-        at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA);
-
-        /* enable pin */
-        if (gpio_is_valid(data->enable_pin))
-                at91_set_gpio_output(data->enable_pin, 1);
-
-        /* ready/busy pin */
-        if (gpio_is_valid(data->rdy_pin))
-                at91_set_gpio_input(data->rdy_pin, 1);
-
-        /* card detect pin */
-        if (gpio_is_valid(data->det_pin))
-                at91_set_gpio_input(data->det_pin, 1);
-
-        nand_data = *data;
-        platform_device_register(&at91cap9_nand_device);
-}
-#else
-void __init at91_add_device_nand(struct atmel_nand_data *data) {}
-#endif
-
-
-/* --------------------------------------------------------------------
- *  TWI (i2c)
- * -------------------------------------------------------------------- */
-
-/*
- * Prefer the GPIO code since the TWI controller isn't robust
- * (gets overruns and underruns under load) and can only issue
- * repeated STARTs in one scenario (the driver doesn't yet handle them).
- */
-#if defined(CONFIG_I2C_GPIO) || defined(CONFIG_I2C_GPIO_MODULE)
-
-static struct i2c_gpio_platform_data pdata = {
-        .sda_pin                = AT91_PIN_PB4,
-        .sda_is_open_drain      = 1,
-        .scl_pin                = AT91_PIN_PB5,
-        .scl_is_open_drain      = 1,
-        .udelay                 = 2,            /* ~100 kHz */
-};
-
-static struct platform_device at91cap9_twi_device = {
-        .name                   = "i2c-gpio",
-        .id                     = -1,
-        .dev.platform_data      = &pdata,
-};
-
-void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices)
-{
-        at91_set_GPIO_periph(AT91_PIN_PB4, 1);          /* TWD (SDA) */
-        at91_set_multi_drive(AT91_PIN_PB4, 1);
-
-        at91_set_GPIO_periph(AT91_PIN_PB5, 1);          /* TWCK (SCL) */
-        at91_set_multi_drive(AT91_PIN_PB5, 1);
-
-        i2c_register_board_info(0, devices, nr_devices);
-        platform_device_register(&at91cap9_twi_device);
-}
-
-#elif defined(CONFIG_I2C_AT91) || defined(CONFIG_I2C_AT91_MODULE)
-
-static struct resource twi_resources[] = {
-        [0] = {
-                .start  = AT91CAP9_BASE_TWI,
-                .end    = AT91CAP9_BASE_TWI + SZ_16K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = AT91CAP9_ID_TWI,
-                .end    = AT91CAP9_ID_TWI,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device at91cap9_twi_device = {
-        .name           = "at91_i2c",
-        .id             = -1,
-        .resource       = twi_resources,
-        .num_resources  = ARRAY_SIZE(twi_resources),
-};
-
-void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices)
-{
-        /* pins used for TWI interface */
-        at91_set_B_periph(AT91_PIN_PB4, 0);             /* TWD */
-        at91_set_multi_drive(AT91_PIN_PB4, 1);
-
-        at91_set_B_periph(AT91_PIN_PB5, 0);             /* TWCK */
-        at91_set_multi_drive(AT91_PIN_PB5, 1);
-
-        i2c_register_board_info(0, devices, nr_devices);
-        platform_device_register(&at91cap9_twi_device);
-}
-#else
-void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices) {}
-#endif
-
-/* --------------------------------------------------------------------
- *  SPI
- * -------------------------------------------------------------------- */
-
-#if defined(CONFIG_SPI_ATMEL) || defined(CONFIG_SPI_ATMEL_MODULE)
-static u64 spi_dmamask = DMA_BIT_MASK(32);
-
-static struct resource spi0_resources[] = {
-        [0] = {
-                .start  = AT91CAP9_BASE_SPI0,
-                .end    = AT91CAP9_BASE_SPI0 + SZ_16K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = AT91CAP9_ID_SPI0,
-                .end    = AT91CAP9_ID_SPI0,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device at91cap9_spi0_device = {
-        .name           = "atmel_spi",
-        .id             = 0,
-        .dev            = {
-                                .dma_mask               = &spi_dmamask,
-                                .coherent_dma_mask      = DMA_BIT_MASK(32),
-        },
-        .resource       = spi0_resources,
-        .num_resources  = ARRAY_SIZE(spi0_resources),
-};
-
-static const unsigned spi0_standard_cs[4] = { AT91_PIN_PA5, AT91_PIN_PA3, AT91_PIN_PD0, AT91_PIN_PD1 };
-
-static struct resource spi1_resources[] = {
-        [0] = {
-                .start  = AT91CAP9_BASE_SPI1,
-                .end    = AT91CAP9_BASE_SPI1 + SZ_16K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = AT91CAP9_ID_SPI1,
-                .end    = AT91CAP9_ID_SPI1,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device at91cap9_spi1_device = {
-        .name           = "atmel_spi",
-        .id             = 1,
-        .dev            = {
-                                .dma_mask               = &spi_dmamask,
-                                .coherent_dma_mask      = DMA_BIT_MASK(32),
-        },
-        .resource       = spi1_resources,
-        .num_resources  = ARRAY_SIZE(spi1_resources),
-};
-
-static const unsigned spi1_standard_cs[4] = { AT91_PIN_PB15, AT91_PIN_PB16, AT91_PIN_PB17, AT91_PIN_PB18 };
-
-void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices)
-{
-        int i;
-        unsigned long cs_pin;
-        short enable_spi0 = 0;
-        short enable_spi1 = 0;
-
-        /* Choose SPI chip-selects */
-        for (i = 0; i < nr_devices; i++) {
-                if (devices[i].controller_data)
-                        cs_pin = (unsigned long) devices[i].controller_data;
-                else if (devices[i].bus_num == 0)
-                        cs_pin = spi0_standard_cs[devices[i].chip_select];
-                else
-                        cs_pin = spi1_standard_cs[devices[i].chip_select];
-
-                if (devices[i].bus_num == 0)
-                        enable_spi0 = 1;
-                else
-                        enable_spi1 = 1;
-
-                /* enable chip-select pin */
-                at91_set_gpio_output(cs_pin, 1);
-
-                /* pass chip-select pin to driver */
-                devices[i].controller_data = (void *) cs_pin;
-        }
-
-        spi_register_board_info(devices, nr_devices);
-
-        /* Configure SPI bus(es) */
-        if (enable_spi0) {
-                at91_set_B_periph(AT91_PIN_PA0, 0);     /* SPI0_MISO */
-                at91_set_B_periph(AT91_PIN_PA1, 0);     /* SPI0_MOSI */
-                at91_set_B_periph(AT91_PIN_PA2, 0);     /* SPI0_SPCK */
-
-                platform_device_register(&at91cap9_spi0_device);
-        }
-        if (enable_spi1) {
-                at91_set_A_periph(AT91_PIN_PB12, 0);    /* SPI1_MISO */
-                at91_set_A_periph(AT91_PIN_PB13, 0);    /* SPI1_MOSI */
-                at91_set_A_periph(AT91_PIN_PB14, 0);    /* SPI1_SPCK */
-
-                platform_device_register(&at91cap9_spi1_device);
-        }
-}
-#else
-void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices) {}
-#endif
-
-
-/* --------------------------------------------------------------------
- *  Timer/Counter block
- * -------------------------------------------------------------------- */
-
-#ifdef CONFIG_ATMEL_TCLIB
-
-static struct resource tcb_resources[] = {
-        [0] = {
-                .start  = AT91CAP9_BASE_TCB0,
-                .end    = AT91CAP9_BASE_TCB0 + SZ_16K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = AT91CAP9_ID_TCB,
-                .end    = AT91CAP9_ID_TCB,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device at91cap9_tcb_device = {
-        .name           = "atmel_tcb",
-        .id             = 0,
-        .resource       = tcb_resources,
-        .num_resources  = ARRAY_SIZE(tcb_resources),
-};
-
-static void __init at91_add_device_tc(void)
-{
-        platform_device_register(&at91cap9_tcb_device);
-}
-#else
-static void __init at91_add_device_tc(void) { }
-#endif
-
-
-/* --------------------------------------------------------------------
- *  RTT
- * -------------------------------------------------------------------- */
-
-static struct resource rtt_resources[] = {
-        {
-                .start  = AT91CAP9_BASE_RTT,
-                .end    = AT91CAP9_BASE_RTT + SZ_16 - 1,
-                .flags  = IORESOURCE_MEM,
-        }
-};
-
-static struct platform_device at91cap9_rtt_device = {
-        .name           = "at91_rtt",
-        .id             = 0,
-        .resource       = rtt_resources,
-        .num_resources  = ARRAY_SIZE(rtt_resources),
-};
-
-static void __init at91_add_device_rtt(void)
-{
-        platform_device_register(&at91cap9_rtt_device);
-}
-
-
-/* --------------------------------------------------------------------
- *  Watchdog
- * -------------------------------------------------------------------- */
-
-#if defined(CONFIG_AT91SAM9X_WATCHDOG) || defined(CONFIG_AT91SAM9X_WATCHDOG_MODULE)
-static struct resource wdt_resources[] = {
-        {
-                .start  = AT91CAP9_BASE_WDT,
-                .end    = AT91CAP9_BASE_WDT + SZ_16 - 1,
-                .flags  = IORESOURCE_MEM,
-        }
-};
-
-static struct platform_device at91cap9_wdt_device = {
-        .name           = "at91_wdt",
-        .id             = -1,
-        .resource       = wdt_resources,
-        .num_resources  = ARRAY_SIZE(wdt_resources),
-};
-
-static void __init at91_add_device_watchdog(void)
-{
-        platform_device_register(&at91cap9_wdt_device);
-}
-#else
-static void __init at91_add_device_watchdog(void) {}
-#endif
-
-
-/* --------------------------------------------------------------------
- *  PWM
- * --------------------------------------------------------------------*/
-
-#if defined(CONFIG_ATMEL_PWM)
-static u32 pwm_mask;
-
-static struct resource pwm_resources[] = {
-        [0] = {
-                .start  = AT91CAP9_BASE_PWMC,
-                .end    = AT91CAP9_BASE_PWMC + SZ_16K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = AT91CAP9_ID_PWMC,
-                .end    = AT91CAP9_ID_PWMC,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device at91cap9_pwm0_device = {
-        .name   = "atmel_pwm",
-        .id     = -1,
-        .dev    = {
-                .platform_data          = &pwm_mask,
-        },
-        .resource       = pwm_resources,
-        .num_resources  = ARRAY_SIZE(pwm_resources),
-};
-
-void __init at91_add_device_pwm(u32 mask)
-{
-        if (mask & (1 << AT91_PWM0))
-                at91_set_A_periph(AT91_PIN_PB19, 1);    /* enable PWM0 */
-
-        if (mask & (1 << AT91_PWM1))
-                at91_set_B_periph(AT91_PIN_PB8, 1);     /* enable PWM1 */
-
-        if (mask & (1 << AT91_PWM2))
-                at91_set_B_periph(AT91_PIN_PC29, 1);    /* enable PWM2 */
-
-        if (mask & (1 << AT91_PWM3))
-                at91_set_B_periph(AT91_PIN_PA11, 1);    /* enable PWM3 */
-
-        pwm_mask = mask;
-
-        platform_device_register(&at91cap9_pwm0_device);
-}
-#else
-void __init at91_add_device_pwm(u32 mask) {}
-#endif
-
-
-
-/* --------------------------------------------------------------------
- *  AC97
- * -------------------------------------------------------------------- */
-
-#if defined(CONFIG_SND_ATMEL_AC97C) || defined(CONFIG_SND_ATMEL_AC97C_MODULE)
-static u64 ac97_dmamask = DMA_BIT_MASK(32);
-static struct ac97c_platform_data ac97_data;
-
-static struct resource ac97_resources[] = {
-        [0] = {
-                .start  = AT91CAP9_BASE_AC97C,
-                .end    = AT91CAP9_BASE_AC97C + SZ_16K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = AT91CAP9_ID_AC97C,
-                .end    = AT91CAP9_ID_AC97C,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device at91cap9_ac97_device = {
-        .name           = "atmel_ac97c",
-        .id             = 1,
-        .dev            = {
-                                .dma_mask               = &ac97_dmamask,
-                                .coherent_dma_mask      = DMA_BIT_MASK(32),
-                                .platform_data          = &ac97_data,
-        },
-        .resource       = ac97_resources,
-        .num_resources  = ARRAY_SIZE(ac97_resources),
-};
-
-void __init at91_add_device_ac97(struct ac97c_platform_data *data)
-{
-        if (!data)
-                return;
-
-        at91_set_A_periph(AT91_PIN_PA6, 0);     /* AC97FS */
-        at91_set_A_periph(AT91_PIN_PA7, 0);     /* AC97CK */
-        at91_set_A_periph(AT91_PIN_PA8, 0);     /* AC97TX */
-        at91_set_A_periph(AT91_PIN_PA9, 0);     /* AC97RX */
-
-        /* reset */
-        if (gpio_is_valid(data->reset_pin))
-                at91_set_gpio_output(data->reset_pin, 0);
-
-        ac97_data = *data;
-        platform_device_register(&at91cap9_ac97_device);
-}
-#else
-void __init at91_add_device_ac97(struct ac97c_platform_data *data) {}
-#endif
-
-
-/* --------------------------------------------------------------------
- *  LCD Controller
- * -------------------------------------------------------------------- */
-
-#if defined(CONFIG_FB_ATMEL) || defined(CONFIG_FB_ATMEL_MODULE)
-static u64 lcdc_dmamask = DMA_BIT_MASK(32);
-static struct atmel_lcdfb_info lcdc_data;
-
-static struct resource lcdc_resources[] = {
-        [0] = {
-                .start  = AT91CAP9_LCDC_BASE,
-                .end    = AT91CAP9_LCDC_BASE + SZ_4K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = AT91CAP9_ID_LCDC,
-                .end    = AT91CAP9_ID_LCDC,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device at91_lcdc_device = {
-        .name           = "atmel_lcdfb",
-        .id             = 0,
-        .dev            = {
-                                .dma_mask               = &lcdc_dmamask,
-                                .coherent_dma_mask      = DMA_BIT_MASK(32),
-                                .platform_data          = &lcdc_data,
-        },
-        .resource       = lcdc_resources,
-        .num_resources  = ARRAY_SIZE(lcdc_resources),
-};
-
-void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data)
-{
-        if (!data)
-                return;
-
-        if (cpu_is_at91cap9_revB())
-                irq_set_irq_type(AT91CAP9_ID_LCDC, IRQ_TYPE_LEVEL_HIGH);
-
-        at91_set_A_periph(AT91_PIN_PC1, 0);     /* LCDHSYNC */
-        at91_set_A_periph(AT91_PIN_PC2, 0);     /* LCDDOTCK */
-        at91_set_A_periph(AT91_PIN_PC3, 0);     /* LCDDEN */
-        at91_set_B_periph(AT91_PIN_PB9, 0);     /* LCDCC */
-        at91_set_A_periph(AT91_PIN_PC6, 0);     /* LCDD2 */
-        at91_set_A_periph(AT91_PIN_PC7, 0);     /* LCDD3 */
-        at91_set_A_periph(AT91_PIN_PC8, 0);     /* LCDD4 */
-        at91_set_A_periph(AT91_PIN_PC9, 0);     /* LCDD5 */
-        at91_set_A_periph(AT91_PIN_PC10, 0);    /* LCDD6 */
-        at91_set_A_periph(AT91_PIN_PC11, 0);    /* LCDD7 */
-        at91_set_A_periph(AT91_PIN_PC14, 0);    /* LCDD10 */
-        at91_set_A_periph(AT91_PIN_PC15, 0);    /* LCDD11 */
-        at91_set_A_periph(AT91_PIN_PC16, 0);    /* LCDD12 */
-        at91_set_A_periph(AT91_PIN_PC17, 0);    /* LCDD13 */
-        at91_set_A_periph(AT91_PIN_PC18, 0);    /* LCDD14 */
-        at91_set_A_periph(AT91_PIN_PC19, 0);    /* LCDD15 */
-        at91_set_A_periph(AT91_PIN_PC22, 0);    /* LCDD18 */
-        at91_set_A_periph(AT91_PIN_PC23, 0);    /* LCDD19 */
-        at91_set_A_periph(AT91_PIN_PC24, 0);    /* LCDD20 */
-        at91_set_A_periph(AT91_PIN_PC25, 0);    /* LCDD21 */
-        at91_set_A_periph(AT91_PIN_PC26, 0);    /* LCDD22 */
-        at91_set_A_periph(AT91_PIN_PC27, 0);    /* LCDD23 */
-
-        lcdc_data = *data;
-        platform_device_register(&at91_lcdc_device);
-}
-#else
-void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data) {}
-#endif
-
-
-/* --------------------------------------------------------------------
- *  SSC -- Synchronous Serial Controller
- * -------------------------------------------------------------------- */
-
-#if defined(CONFIG_ATMEL_SSC) || defined(CONFIG_ATMEL_SSC_MODULE)
-static u64 ssc0_dmamask = DMA_BIT_MASK(32);
-
-static struct resource ssc0_resources[] = {
-        [0] = {
-                .start  = AT91CAP9_BASE_SSC0,
-                .end    = AT91CAP9_BASE_SSC0 + SZ_16K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = AT91CAP9_ID_SSC0,
-                .end    = AT91CAP9_ID_SSC0,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device at91cap9_ssc0_device = {
-        .name   = "ssc",
-        .id     = 0,
-        .dev    = {
-                .dma_mask               = &ssc0_dmamask,
-                .coherent_dma_mask      = DMA_BIT_MASK(32),
-        },
-        .resource       = ssc0_resources,
-        .num_resources  = ARRAY_SIZE(ssc0_resources),
-};
-
-static inline void configure_ssc0_pins(unsigned pins)
-{
-        if (pins & ATMEL_SSC_TF)
-                at91_set_A_periph(AT91_PIN_PB0, 1);
-        if (pins & ATMEL_SSC_TK)
-                at91_set_A_periph(AT91_PIN_PB1, 1);
-        if (pins & ATMEL_SSC_TD)
-                at91_set_A_periph(AT91_PIN_PB2, 1);
-        if (pins & ATMEL_SSC_RD)
-                at91_set_A_periph(AT91_PIN_PB3, 1);
-        if (pins & ATMEL_SSC_RK)
-                at91_set_A_periph(AT91_PIN_PB4, 1);
-        if (pins & ATMEL_SSC_RF)
-                at91_set_A_periph(AT91_PIN_PB5, 1);
-}
-
-static u64 ssc1_dmamask = DMA_BIT_MASK(32);
-
-static struct resource ssc1_resources[] = {
-        [0] = {
-                .start  = AT91CAP9_BASE_SSC1,
-                .end    = AT91CAP9_BASE_SSC1 + SZ_16K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = AT91CAP9_ID_SSC1,
-                .end    = AT91CAP9_ID_SSC1,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device at91cap9_ssc1_device = {
-        .name   = "ssc",
-        .id     = 1,
-        .dev    = {
-                .dma_mask               = &ssc1_dmamask,
-                .coherent_dma_mask      = DMA_BIT_MASK(32),
-        },
-        .resource       = ssc1_resources,
-        .num_resources  = ARRAY_SIZE(ssc1_resources),
-};
-
-static inline void configure_ssc1_pins(unsigned pins)
-{
-        if (pins & ATMEL_SSC_TF)
-                at91_set_A_periph(AT91_PIN_PB6, 1);
-        if (pins & ATMEL_SSC_TK)
-                at91_set_A_periph(AT91_PIN_PB7, 1);
-        if (pins & ATMEL_SSC_TD)
-                at91_set_A_periph(AT91_PIN_PB8, 1);
-        if (pins & ATMEL_SSC_RD)
-                at91_set_A_periph(AT91_PIN_PB9, 1);
-        if (pins & ATMEL_SSC_RK)
-                at91_set_A_periph(AT91_PIN_PB10, 1);
-        if (pins & ATMEL_SSC_RF)
-                at91_set_A_periph(AT91_PIN_PB11, 1);
-}
-
-/*
- * SSC controllers are accessed through library code, instead of any
- * kind of all-singing/all-dancing driver.  For example one could be
- * used by a particular I2S audio codec's driver, while another one
- * on the same system might be used by a custom data capture driver.
- */
-void __init at91_add_device_ssc(unsigned id, unsigned pins)
-{
-        struct platform_device *pdev;
-
-        /*
-         * NOTE: caller is responsible for passing information matching
-         * "pins" to whatever will be using each particular controller.
-         */
-        switch (id) {
-        case AT91CAP9_ID_SSC0:
-                pdev = &at91cap9_ssc0_device;
-                configure_ssc0_pins(pins);
-                break;
-        case AT91CAP9_ID_SSC1:
-                pdev = &at91cap9_ssc1_device;
-                configure_ssc1_pins(pins);
-                break;
-        default:
-                return;
-        }
-
-        platform_device_register(pdev);
-}
-
-#else
-void __init at91_add_device_ssc(unsigned id, unsigned pins) {}
-#endif
-
-
-/* --------------------------------------------------------------------
- *  UART
- * -------------------------------------------------------------------- */
-
-#if defined(CONFIG_SERIAL_ATMEL)
-static struct resource dbgu_resources[] = {
-        [0] = {
-                .start  = AT91CAP9_BASE_DBGU,
-                .end    = AT91CAP9_BASE_DBGU + SZ_512 - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = AT91_ID_SYS,
-                .end    = AT91_ID_SYS,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct atmel_uart_data dbgu_data = {
-        .use_dma_tx     = 0,
-        .use_dma_rx     = 0,            /* DBGU not capable of receive DMA */
-};
-
-static u64 dbgu_dmamask = DMA_BIT_MASK(32);
-
-static struct platform_device at91cap9_dbgu_device = {
-        .name           = "atmel_usart",
-        .id             = 0,
-        .dev            = {
-                                .dma_mask               = &dbgu_dmamask,
-                                .coherent_dma_mask      = DMA_BIT_MASK(32),
-                                .platform_data          = &dbgu_data,
-        },
-        .resource       = dbgu_resources,
-        .num_resources  = ARRAY_SIZE(dbgu_resources),
-};
-
-static inline void configure_dbgu_pins(void)
-{
-        at91_set_A_periph(AT91_PIN_PC30, 0);            /* DRXD */
-        at91_set_A_periph(AT91_PIN_PC31, 1);            /* DTXD */
-}
-
-static struct resource uart0_resources[] = {
-        [0] = {
-                .start  = AT91CAP9_BASE_US0,
-                .end    = AT91CAP9_BASE_US0 + SZ_16K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = AT91CAP9_ID_US0,
-                .end    = AT91CAP9_ID_US0,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct atmel_uart_data uart0_data = {
-        .use_dma_tx     = 1,
-        .use_dma_rx     = 1,
-};
-
-static u64 uart0_dmamask = DMA_BIT_MASK(32);
-
-static struct platform_device at91cap9_uart0_device = {
-        .name           = "atmel_usart",
-        .id             = 1,
-        .dev            = {
-                                .dma_mask               = &uart0_dmamask,
-                                .coherent_dma_mask      = DMA_BIT_MASK(32),
-                                .platform_data          = &uart0_data,
-        },
-        .resource       = uart0_resources,
-        .num_resources  = ARRAY_SIZE(uart0_resources),
-};
-
-static inline void configure_usart0_pins(unsigned pins)
-{
-        at91_set_A_periph(AT91_PIN_PA22, 1);            /* TXD0 */
-        at91_set_A_periph(AT91_PIN_PA23, 0);            /* RXD0 */
-
-        if (pins & ATMEL_UART_RTS)
-                at91_set_A_periph(AT91_PIN_PA24, 0);    /* RTS0 */
-        if (pins & ATMEL_UART_CTS)
-                at91_set_A_periph(AT91_PIN_PA25, 0);    /* CTS0 */
-}
-
-static struct resource uart1_resources[] = {
-        [0] = {
-                .start  = AT91CAP9_BASE_US1,
-                .end    = AT91CAP9_BASE_US1 + SZ_16K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = AT91CAP9_ID_US1,
-                .end    = AT91CAP9_ID_US1,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct atmel_uart_data uart1_data = {
-        .use_dma_tx     = 1,
-        .use_dma_rx     = 1,
-};
-
-static u64 uart1_dmamask = DMA_BIT_MASK(32);
-
-static struct platform_device at91cap9_uart1_device = {
-        .name           = "atmel_usart",
-        .id             = 2,
-        .dev            = {
-                                .dma_mask               = &uart1_dmamask,
-                                .coherent_dma_mask      = DMA_BIT_MASK(32),
-                                .platform_data          = &uart1_data,
-        },
-        .resource       = uart1_resources,
-        .num_resources  = ARRAY_SIZE(uart1_resources),
-};
-
-static inline void configure_usart1_pins(unsigned pins)
-{
-        at91_set_A_periph(AT91_PIN_PD0, 1);             /* TXD1 */
-        at91_set_A_periph(AT91_PIN_PD1, 0);             /* RXD1 */
-
-        if (pins & ATMEL_UART_RTS)
-                at91_set_B_periph(AT91_PIN_PD7, 0);     /* RTS1 */
-        if (pins & ATMEL_UART_CTS)
-                at91_set_B_periph(AT91_PIN_PD8, 0);     /* CTS1 */
-}
-
-static struct resource uart2_resources[] = {
-        [0] = {
-                .start  = AT91CAP9_BASE_US2,
-                .end    = AT91CAP9_BASE_US2 + SZ_16K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = AT91CAP9_ID_US2,
-                .end    = AT91CAP9_ID_US2,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct atmel_uart_data uart2_data = {
-        .use_dma_tx     = 1,
-        .use_dma_rx     = 1,
-};
-
-static u64 uart2_dmamask = DMA_BIT_MASK(32);
-
-static struct platform_device at91cap9_uart2_device = {
-        .name           = "atmel_usart",
-        .id             = 3,
-        .dev            = {
-                                .dma_mask               = &uart2_dmamask,
-                                .coherent_dma_mask      = DMA_BIT_MASK(32),
-                                .platform_data          = &uart2_data,
-        },
-        .resource       = uart2_resources,
-        .num_resources  = ARRAY_SIZE(uart2_resources),
-};
-
-static inline void configure_usart2_pins(unsigned pins)
-{
-        at91_set_A_periph(AT91_PIN_PD2, 1);             /* TXD2 */
-        at91_set_A_periph(AT91_PIN_PD3, 0);             /* RXD2 */
-
-        if (pins & ATMEL_UART_RTS)
-                at91_set_B_periph(AT91_PIN_PD5, 0);     /* RTS2 */
-        if (pins & ATMEL_UART_CTS)
-                at91_set_B_periph(AT91_PIN_PD6, 0);     /* CTS2 */
-}
-
-static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART];   /* the UARTs to use */
-struct platform_device *atmel_default_console_device;   /* the serial console device */
-
-void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
-{
-        struct platform_device *pdev;
-        struct atmel_uart_data *pdata;
-
-        switch (id) {
-                case 0:         /* DBGU */
-                        pdev = &at91cap9_dbgu_device;
-                        configure_dbgu_pins();
-                        break;
-                case AT91CAP9_ID_US0:
-                        pdev = &at91cap9_uart0_device;
-                        configure_usart0_pins(pins);
-                        break;
-                case AT91CAP9_ID_US1:
-                        pdev = &at91cap9_uart1_device;
-                        configure_usart1_pins(pins);
-                        break;
-                case AT91CAP9_ID_US2:
-                        pdev = &at91cap9_uart2_device;
-                        configure_usart2_pins(pins);
-                        break;
-                default:
-                        return;
-        }
-        pdata = pdev->dev.platform_data;
-        pdata->num = portnr;            /* update to mapped ID */
-
-        if (portnr < ATMEL_MAX_UART)
-                at91_uarts[portnr] = pdev;
-}
-
-void __init at91_set_serial_console(unsigned portnr)
-{
-        if (portnr < ATMEL_MAX_UART) {
-                atmel_default_console_device = at91_uarts[portnr];
-                at91cap9_set_console_clock(at91_uarts[portnr]->id);
-        }
-}
-
-void __init at91_add_device_serial(void)
-{
-        int i;
-
-        for (i = 0; i < ATMEL_MAX_UART; i++) {
-                if (at91_uarts[i])
-                        platform_device_register(at91_uarts[i]);
-        }
-
-        if (!atmel_default_console_device)
-                printk(KERN_INFO "AT91: No default serial console defined.\n");
-}
-#else
-void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) {}
-void __init at91_set_serial_console(unsigned portnr) {}
-void __init at91_add_device_serial(void) {}
-#endif
-
-
-/* -------------------------------------------------------------------- */
-/*
- * These devices are always present and don't need any board-specific
- * setup.
- */
-static int __init at91_add_standard_devices(void)
-{
-        at91_add_device_rtt();
-        at91_add_device_watchdog();
-        at91_add_device_tc();
-        return 0;
-}
-
-arch_initcall(at91_add_standard_devices);
diff --git a/arch/arm/mach-at91/at91rm9200.c b/arch/arm/mach-at91/at91rm9200.c
index 99c3174e24a..0df1045311e 100644
--- a/arch/arm/mach-at91/at91rm9200.c
+++ b/arch/arm/mach-at91/at91rm9200.c
@@ -289,13 +289,22 @@ static struct at91_gpio_bank at91rm9200_gpio[] __initdata = {
         }
 };
 
+static void at91rm9200_idle(void)
+{
+        /*
+         * Disable the processor clock.  The processor will be automatically
+         * re-enabled by an interrupt or by a reset.
+         */
+        at91_pmc_write(AT91_PMC_SCDR, AT91_PMC_PCK);
+}
+
 static void at91rm9200_restart(char mode, const char *cmd)
 {
         /*
          * Perform a hardware reset with the use of the Watchdog timer.
          */
-        at91_sys_write(AT91_ST_WDMR, AT91_ST_RSTEN | AT91_ST_EXTEN | 1);
-        at91_sys_write(AT91_ST_CR, AT91_ST_WDRST);
+        at91_st_write(AT91_ST_WDMR, AT91_ST_RSTEN | AT91_ST_EXTEN | 1);
+        at91_st_write(AT91_ST_CR, AT91_ST_WDRST);
 }
 
 /* --------------------------------------------------------------------
@@ -310,10 +319,13 @@ static void __init at91rm9200_map_io(void)
 
 static void __init at91rm9200_ioremap_registers(void)
 {
+        at91rm9200_ioremap_st(AT91RM9200_BASE_ST);
+        at91_ioremap_ramc(0, AT91RM9200_BASE_MC, 256);
 }
 
 static void __init at91rm9200_initialize(void)
 {
+        arm_pm_idle = at91rm9200_idle;
         arm_pm_restart = at91rm9200_restart;
         at91_extern_irq = (1 << AT91RM9200_ID_IRQ0) | (1 << AT91RM9200_ID_IRQ1)
                         | (1 << AT91RM9200_ID_IRQ2) | (1 << AT91RM9200_ID_IRQ3)
diff --git a/arch/arm/mach-at91/at91rm9200_devices.c b/arch/arm/mach-at91/at91rm9200_devices.c
index 97676bdae99..99ce5c955e3 100644
--- a/arch/arm/mach-at91/at91rm9200_devices.c
+++ b/arch/arm/mach-at91/at91rm9200_devices.c
@@ -21,6 +21,7 @@
 #include <mach/board.h>
 #include <mach/at91rm9200.h>
 #include <mach/at91rm9200_mc.h>
+#include <mach/at91_ramc.h>
 
 #include "generic.h"
 
@@ -241,15 +242,15 @@ void __init at91_add_device_cf(struct at91_cf_data *data)
         data->chipselect = 4;           /* can only use EBI ChipSelect 4 */
 
         /* CF takes over CS4, CS5, CS6 */
-        csa = at91_sys_read(AT91_EBI_CSA);
-        at91_sys_write(AT91_EBI_CSA, csa | AT91_EBI_CS4A_SMC_COMPACTFLASH);
+        csa = at91_ramc_read(0, AT91_EBI_CSA);
+        at91_ramc_write(0, AT91_EBI_CSA, csa | AT91_EBI_CS4A_SMC_COMPACTFLASH);
 
         /*
          * Static memory controller timing adjustments.
          * REVISIT:  these timings are in terms of MCK cycles, so
          * when MCK changes (cpufreq etc) so must these values...
          */
-        at91_sys_write(AT91_SMC_CSR(4),
+        at91_ramc_write(0, AT91_SMC_CSR(4),
                                   AT91_SMC_ACSS_STD
                                 | AT91_SMC_DBW_16
                                 | AT91_SMC_BAT
@@ -407,11 +408,11 @@ void __init at91_add_device_nand(struct atmel_nand_data *data)
                 return;
 
         /* enable the address range of CS3 */
-        csa = at91_sys_read(AT91_EBI_CSA);
-        at91_sys_write(AT91_EBI_CSA, csa | AT91_EBI_CS3A_SMC_SMARTMEDIA);
+        csa = at91_ramc_read(0, AT91_EBI_CSA);
+        at91_ramc_write(0, AT91_EBI_CSA, csa | AT91_EBI_CS3A_SMC_SMARTMEDIA);
 
         /* set the bus interface characteristics */
-        at91_sys_write(AT91_SMC_CSR(3), AT91_SMC_ACSS_STD | AT91_SMC_DBW_8 | AT91_SMC_WSEN
+        at91_ramc_write(0, AT91_SMC_CSR(3), AT91_SMC_ACSS_STD | AT91_SMC_DBW_8 | AT91_SMC_WSEN
                 | AT91_SMC_NWS_(5)
                 | AT91_SMC_TDF_(1)
                 | AT91_SMC_RWSETUP_(0)  /* tDS Data Set up Time 30 - ns */
@@ -1114,7 +1115,6 @@ static inline void configure_usart3_pins(unsigned pins)
 }
 
 static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART];   /* the UARTs to use */
-struct platform_device *atmel_default_console_device;   /* the serial console device */
 
 void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
 {
diff --git a/arch/arm/mach-at91/at91rm9200_time.c b/arch/arm/mach-at91/at91rm9200_time.c
index a028cdf8f97..dd7f782b0b9 100644
--- a/arch/arm/mach-at91/at91rm9200_time.c
+++ b/arch/arm/mach-at91/at91rm9200_time.c
@@ -43,9 +43,9 @@ static inline unsigned long read_CRTR(void)
 {
         unsigned long x1, x2;
 
-        x1 = at91_sys_read(AT91_ST_CRTR);
+        x1 = at91_st_read(AT91_ST_CRTR);
         do {
-                x2 = at91_sys_read(AT91_ST_CRTR);
+                x2 = at91_st_read(AT91_ST_CRTR);
                 if (x1 == x2)
                         break;
                 x1 = x2;
@@ -58,7 +58,7 @@ static inline unsigned long read_CRTR(void)
  */
 static irqreturn_t at91rm9200_timer_interrupt(int irq, void *dev_id)
 {
-        u32     sr = at91_sys_read(AT91_ST_SR) & irqmask;
+        u32     sr = at91_st_read(AT91_ST_SR) & irqmask;
 
         /*
          * irqs should be disabled here, but as the irq is shared they are only
@@ -110,22 +110,22 @@ static void
 clkevt32k_mode(enum clock_event_mode mode, struct clock_event_device *dev)
 {
         /* Disable and flush pending timer interrupts */
-        at91_sys_write(AT91_ST_IDR, AT91_ST_PITS | AT91_ST_ALMS);
-        (void) at91_sys_read(AT91_ST_SR);
+        at91_st_write(AT91_ST_IDR, AT91_ST_PITS | AT91_ST_ALMS);
+        at91_st_read(AT91_ST_SR);
 
         last_crtr = read_CRTR();
         switch (mode) {
         case CLOCK_EVT_MODE_PERIODIC:
                 /* PIT for periodic irqs; fixed rate of 1/HZ */
                 irqmask = AT91_ST_PITS;
-                at91_sys_write(AT91_ST_PIMR, RM9200_TIMER_LATCH);
+                at91_st_write(AT91_ST_PIMR, RM9200_TIMER_LATCH);
                 break;
         case CLOCK_EVT_MODE_ONESHOT:
                 /* ALM for oneshot irqs, set by next_event()
                  * before 32 seconds have passed
                  */
                 irqmask = AT91_ST_ALMS;
-                at91_sys_write(AT91_ST_RTAR, last_crtr);
+                at91_st_write(AT91_ST_RTAR, last_crtr);
                 break;
         case CLOCK_EVT_MODE_SHUTDOWN:
         case CLOCK_EVT_MODE_UNUSED:
@@ -133,7 +133,7 @@ clkevt32k_mode(enum clock_event_mode mode, struct clock_event_device *dev)
                 irqmask = 0;
                 break;
         }
-        at91_sys_write(AT91_ST_IER, irqmask);
+        at91_st_write(AT91_ST_IER, irqmask);
 }
 
 static int
@@ -156,12 +156,12 @@ clkevt32k_next_event(unsigned long delta, struct clock_event_device *dev)
         alm = read_CRTR();
 
         /* Cancel any pending alarm; flush any pending IRQ */
-        at91_sys_write(AT91_ST_RTAR, alm);
-        (void) at91_sys_read(AT91_ST_SR);
+        at91_st_write(AT91_ST_RTAR, alm);
+        at91_st_read(AT91_ST_SR);
 
         /* Schedule alarm by writing RTAR. */
         alm += delta;
-        at91_sys_write(AT91_ST_RTAR, alm);
+        at91_st_write(AT91_ST_RTAR, alm);
 
         return status;
 }
@@ -175,15 +175,24 @@ static struct clock_event_device clkevt = {
         .set_mode       = clkevt32k_mode,
 };
 
+void __iomem *at91_st_base;
+
+void __init at91rm9200_ioremap_st(u32 addr)
+{
+        at91_st_base = ioremap(addr, 256);
+        if (!at91_st_base)
+                panic("Impossible to ioremap ST\n");
+}
+
 /*
  * ST (system timer) module supports both clockevents and clocksource.
  */
 void __init at91rm9200_timer_init(void)
 {
         /* Disable all timer interrupts, and clear any pending ones */
-        at91_sys_write(AT91_ST_IDR,
+        at91_st_write(AT91_ST_IDR,
                 AT91_ST_PITS | AT91_ST_WDOVF | AT91_ST_RTTINC | AT91_ST_ALMS);
-        (void) at91_sys_read(AT91_ST_SR);
+        at91_st_read(AT91_ST_SR);
 
         /* Make IRQs happen for the system timer */
         setup_irq(AT91_ID_SYS, &at91rm9200_timer_irq);
@@ -192,7 +201,7 @@ void __init at91rm9200_timer_init(void)
          * directly for the clocksource and all clockevents, after adjusting
          * its prescaler from the 1 Hz default.
          */
-        at91_sys_write(AT91_ST_RTMR, 1);
+        at91_st_write(AT91_ST_RTMR, 1);
 
         /* Setup timer clockevent, with minimum of two ticks (important!!) */
         clkevt.mult = div_sc(AT91_SLOW_CLOCK, NSEC_PER_SEC, clkevt.shift);
diff --git a/arch/arm/mach-at91/at91sam9260.c b/arch/arm/mach-at91/at91sam9260.c
index d4036ba4361..14b5a9c9a51 100644
--- a/arch/arm/mach-at91/at91sam9260.c
+++ b/arch/arm/mach-at91/at91sam9260.c
@@ -12,6 +12,7 @@
 
 #include <linux/module.h>
 
+#include <asm/proc-fns.h>
 #include <asm/irq.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
@@ -208,6 +209,13 @@ static struct clk_lookup periph_clocks_lookups[] = {
         CLKDEV_CON_DEV_ID("usart", "fffd0000.serial", &usart3_clk),
         CLKDEV_CON_DEV_ID("usart", "fffd4000.serial", &usart4_clk),
         CLKDEV_CON_DEV_ID("usart", "fffd8000.serial", &usart5_clk),
+        /* more tc lookup table for DT entries */
+        CLKDEV_CON_DEV_ID("t0_clk", "fffa0000.timer", &tc0_clk),
+        CLKDEV_CON_DEV_ID("t1_clk", "fffa0000.timer", &tc1_clk),
+        CLKDEV_CON_DEV_ID("t2_clk", "fffa0000.timer", &tc2_clk),
+        CLKDEV_CON_DEV_ID("t0_clk", "fffdc000.timer", &tc3_clk),
+        CLKDEV_CON_DEV_ID("t1_clk", "fffdc000.timer", &tc4_clk),
+        CLKDEV_CON_DEV_ID("t2_clk", "fffdc000.timer", &tc5_clk),
         /* fake hclk clock */
         CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &ohci_clk),
         CLKDEV_CON_ID("pioA", &pioA_clk),
@@ -309,27 +317,27 @@ static void __init at91sam9xe_map_io(void)
 
 static void __init at91sam9260_map_io(void)
 {
-        if (cpu_is_at91sam9xe()) {
+        if (cpu_is_at91sam9xe())
                 at91sam9xe_map_io();
-        } else if (cpu_is_at91sam9g20()) {
-                at91_init_sram(0, AT91SAM9G20_SRAM0_BASE, AT91SAM9G20_SRAM0_SIZE);
-                at91_init_sram(1, AT91SAM9G20_SRAM1_BASE, AT91SAM9G20_SRAM1_SIZE);
-        } else {
-                at91_init_sram(0, AT91SAM9260_SRAM0_BASE, AT91SAM9260_SRAM0_SIZE);
-                at91_init_sram(1, AT91SAM9260_SRAM1_BASE, AT91SAM9260_SRAM1_SIZE);
-        }
+        else if (cpu_is_at91sam9g20())
+                at91_init_sram(0, AT91SAM9G20_SRAM_BASE, AT91SAM9G20_SRAM_SIZE);
+        else
+                at91_init_sram(0, AT91SAM9260_SRAM_BASE, AT91SAM9260_SRAM_SIZE);
 }
 
 static void __init at91sam9260_ioremap_registers(void)
 {
         at91_ioremap_shdwc(AT91SAM9260_BASE_SHDWC);
         at91_ioremap_rstc(AT91SAM9260_BASE_RSTC);
+        at91_ioremap_ramc(0, AT91SAM9260_BASE_SDRAMC, 512);
         at91sam926x_ioremap_pit(AT91SAM9260_BASE_PIT);
         at91sam9_ioremap_smc(0, AT91SAM9260_BASE_SMC);
+        at91_ioremap_matrix(AT91SAM9260_BASE_MATRIX);
 }
 
 static void __init at91sam9260_initialize(void)
 {
+        arm_pm_idle = at91sam9_idle;
         arm_pm_restart = at91sam9_alt_restart;
         at91_extern_irq = (1 << AT91SAM9260_ID_IRQ0) | (1 << AT91SAM9260_ID_IRQ1)
                         | (1 << AT91SAM9260_ID_IRQ2);
diff --git a/arch/arm/mach-at91/at91sam9260_devices.c b/arch/arm/mach-at91/at91sam9260_devices.c
index 5a24f0b4554..7e5651ee9f8 100644
--- a/arch/arm/mach-at91/at91sam9260_devices.c
+++ b/arch/arm/mach-at91/at91sam9260_devices.c
@@ -21,6 +21,7 @@
 #include <mach/cpu.h>
 #include <mach/at91sam9260.h>
 #include <mach/at91sam9260_matrix.h>
+#include <mach/at91_matrix.h>
 #include <mach/at91sam9_smc.h>
 
 #include "generic.h"
@@ -422,8 +423,8 @@ void __init at91_add_device_nand(struct atmel_nand_data *data)
         if (!data)
                 return;
 
-        csa = at91_sys_read(AT91_MATRIX_EBICSA);
-        at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
+        csa = at91_matrix_read(AT91_MATRIX_EBICSA);
+        at91_matrix_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
 
         /* enable pin */
         if (gpio_is_valid(data->enable_pin))
@@ -641,7 +642,7 @@ void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices)
 static struct resource tcb0_resources[] = {
         [0] = {
                 .start  = AT91SAM9260_BASE_TCB0,
-                .end    = AT91SAM9260_BASE_TCB0 + SZ_16K - 1,
+                .end    = AT91SAM9260_BASE_TCB0 + SZ_256 - 1,
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
@@ -671,7 +672,7 @@ static struct platform_device at91sam9260_tcb0_device = {
 static struct resource tcb1_resources[] = {
         [0] = {
                 .start  = AT91SAM9260_BASE_TCB1,
-                .end    = AT91SAM9260_BASE_TCB1 + SZ_16K - 1,
+                .end    = AT91SAM9260_BASE_TCB1 + SZ_256 - 1,
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
@@ -698,8 +699,25 @@ static struct platform_device at91sam9260_tcb1_device = {
         .num_resources  = ARRAY_SIZE(tcb1_resources),
 };
 
+#if defined(CONFIG_OF)
+static struct of_device_id tcb_ids[] = {
+        { .compatible = "atmel,at91rm9200-tcb" },
+        { /*sentinel*/ }
+};
+#endif
+
 static void __init at91_add_device_tc(void)
 {
+#if defined(CONFIG_OF)
+        struct device_node *np;
+
+        np = of_find_matching_node(NULL, tcb_ids);
+        if (np) {
+                of_node_put(np);
+                return;
+        }
+#endif
+
         platform_device_register(&at91sam9260_tcb0_device);
         platform_device_register(&at91sam9260_tcb1_device);
 }
@@ -717,18 +735,42 @@ static struct resource rtt_resources[] = {
                 .start  = AT91SAM9260_BASE_RTT,
                 .end    = AT91SAM9260_BASE_RTT + SZ_16 - 1,
                 .flags  = IORESOURCE_MEM,
-        }
+        }, {
+                .flags  = IORESOURCE_MEM,
+        },
 };
 
 static struct platform_device at91sam9260_rtt_device = {
         .name           = "at91_rtt",
         .id             = 0,
         .resource       = rtt_resources,
-        .num_resources  = ARRAY_SIZE(rtt_resources),
 };
 
+
+#if IS_ENABLED(CONFIG_RTC_DRV_AT91SAM9)
+static void __init at91_add_device_rtt_rtc(void)
+{
+        at91sam9260_rtt_device.name = "rtc-at91sam9";
+        /*
+         * The second resource is needed:
+         * GPBR will serve as the storage for RTC time offset
+         */
+        at91sam9260_rtt_device.num_resources = 2;
+        rtt_resources[1].start = AT91SAM9260_BASE_GPBR +
+                                 4 * CONFIG_RTC_DRV_AT91SAM9_GPBR;
+        rtt_resources[1].end = rtt_resources[1].start + 3;
+}
+#else
+static void __init at91_add_device_rtt_rtc(void)
+{
+        /* Only one resource is needed: RTT not used as RTC */
+        at91sam9260_rtt_device.num_resources = 1;
+}
+#endif
+
 static void __init at91_add_device_rtt(void)
 {
+        at91_add_device_rtt_rtc();
         platform_device_register(&at91sam9260_rtt_device);
 }
 
@@ -1139,7 +1181,6 @@ static inline void configure_usart5_pins(void)
 }
 
 static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART];   /* the UARTs to use */
-struct platform_device *atmel_default_console_device;   /* the serial console device */
 
 void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
 {
@@ -1264,7 +1305,7 @@ void __init at91_add_device_cf(struct at91_cf_data *data)
         if (!data)
                 return;
 
-        csa = at91_sys_read(AT91_MATRIX_EBICSA);
+        csa = at91_matrix_read(AT91_MATRIX_EBICSA);
 
         switch (data->chipselect) {
         case 4:
@@ -1287,7 +1328,7 @@ void __init at91_add_device_cf(struct at91_cf_data *data)
                 return;
         }
 
-        at91_sys_write(AT91_MATRIX_EBICSA, csa);
+        at91_matrix_write(AT91_MATRIX_EBICSA, csa);
 
         if (gpio_is_valid(data->rst_pin)) {
                 at91_set_multi_drive(data->rst_pin, 0);
diff --git a/arch/arm/mach-at91/at91sam9261.c b/arch/arm/mach-at91/at91sam9261.c
index 023c2ff138d..684c5dfd92a 100644
--- a/arch/arm/mach-at91/at91sam9261.c
+++ b/arch/arm/mach-at91/at91sam9261.c
@@ -12,6 +12,7 @@
 
 #include <linux/module.h>
 
+#include <asm/proc-fns.h>
 #include <asm/irq.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
@@ -282,12 +283,15 @@ static void __init at91sam9261_ioremap_registers(void)
 {
         at91_ioremap_shdwc(AT91SAM9261_BASE_SHDWC);
         at91_ioremap_rstc(AT91SAM9261_BASE_RSTC);
+        at91_ioremap_ramc(0, AT91SAM9261_BASE_SDRAMC, 512);
         at91sam926x_ioremap_pit(AT91SAM9261_BASE_PIT);
         at91sam9_ioremap_smc(0, AT91SAM9261_BASE_SMC);
+        at91_ioremap_matrix(AT91SAM9261_BASE_MATRIX);
 }
 
 static void __init at91sam9261_initialize(void)
 {
+        arm_pm_idle = at91sam9_idle;
         arm_pm_restart = at91sam9_alt_restart;
         at91_extern_irq = (1 << AT91SAM9261_ID_IRQ0) | (1 << AT91SAM9261_ID_IRQ1)
                         | (1 << AT91SAM9261_ID_IRQ2);
diff --git a/arch/arm/mach-at91/at91sam9261_devices.c b/arch/arm/mach-at91/at91sam9261_devices.c
index 1e28bed8f42..096da87dc00 100644
--- a/arch/arm/mach-at91/at91sam9261_devices.c
+++ b/arch/arm/mach-at91/at91sam9261_devices.c
@@ -24,6 +24,7 @@
 #include <mach/board.h>
 #include <mach/at91sam9261.h>
 #include <mach/at91sam9261_matrix.h>
+#include <mach/at91_matrix.h>
 #include <mach/at91sam9_smc.h>
 
 #include "generic.h"
@@ -236,8 +237,8 @@ void __init at91_add_device_nand(struct atmel_nand_data *data)
         if (!data)
                 return;
 
-        csa = at91_sys_read(AT91_MATRIX_EBICSA);
-        at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
+        csa = at91_matrix_read(AT91_MATRIX_EBICSA);
+        at91_matrix_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
 
         /* enable pin */
         if (gpio_is_valid(data->enable_pin))
@@ -603,6 +604,8 @@ static struct resource rtt_resources[] = {
                 .start  = AT91SAM9261_BASE_RTT,
                 .end    = AT91SAM9261_BASE_RTT + SZ_16 - 1,
                 .flags  = IORESOURCE_MEM,
+        }, {
+                .flags  = IORESOURCE_MEM,
         }
 };
 
@@ -610,11 +613,32 @@ static struct platform_device at91sam9261_rtt_device = {
         .name           = "at91_rtt",
         .id             = 0,
         .resource       = rtt_resources,
-        .num_resources  = ARRAY_SIZE(rtt_resources),
 };
 
+#if IS_ENABLED(CONFIG_RTC_DRV_AT91SAM9)
+static void __init at91_add_device_rtt_rtc(void)
+{
+        at91sam9261_rtt_device.name = "rtc-at91sam9";
+        /*
+         * The second resource is needed:
+         * GPBR will serve as the storage for RTC time offset
+         */
+        at91sam9261_rtt_device.num_resources = 2;
+        rtt_resources[1].start = AT91SAM9261_BASE_GPBR +
+                                 4 * CONFIG_RTC_DRV_AT91SAM9_GPBR;
+        rtt_resources[1].end = rtt_resources[1].start + 3;
+}
+#else
+static void __init at91_add_device_rtt_rtc(void)
+{
+        /* Only one resource is needed: RTT not used as RTC */
+        at91sam9261_rtt_device.num_resources = 1;
+}
+#endif
+
 static void __init at91_add_device_rtt(void)
 {
+        at91_add_device_rtt_rtc();
         platform_device_register(&at91sam9261_rtt_device);
 }
 
@@ -991,7 +1015,6 @@ static inline void configure_usart2_pins(unsigned pins)
 }
 
 static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART];   /* the UARTs to use */
-struct platform_device *atmel_default_console_device;   /* the serial console device */
 
 void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
 {
diff --git a/arch/arm/mach-at91/at91sam9263.c b/arch/arm/mach-at91/at91sam9263.c
index 75e876c258a..0b4fa5a7f68 100644
--- a/arch/arm/mach-at91/at91sam9263.c
+++ b/arch/arm/mach-at91/at91sam9263.c
@@ -12,6 +12,7 @@
 
 #include <linux/module.h>
 
+#include <asm/proc-fns.h>
 #include <asm/irq.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
@@ -302,13 +303,17 @@ static void __init at91sam9263_ioremap_registers(void)
 {
         at91_ioremap_shdwc(AT91SAM9263_BASE_SHDWC);
         at91_ioremap_rstc(AT91SAM9263_BASE_RSTC);
+        at91_ioremap_ramc(0, AT91SAM9263_BASE_SDRAMC0, 512);
+        at91_ioremap_ramc(1, AT91SAM9263_BASE_SDRAMC1, 512);
         at91sam926x_ioremap_pit(AT91SAM9263_BASE_PIT);
         at91sam9_ioremap_smc(0, AT91SAM9263_BASE_SMC0);
         at91sam9_ioremap_smc(1, AT91SAM9263_BASE_SMC1);
+        at91_ioremap_matrix(AT91SAM9263_BASE_MATRIX);
 }
 
 static void __init at91sam9263_initialize(void)
 {
+        arm_pm_idle = at91sam9_idle;
         arm_pm_restart = at91sam9_alt_restart;
         at91_extern_irq = (1 << AT91SAM9263_ID_IRQ0) | (1 << AT91SAM9263_ID_IRQ1);
 
diff --git a/arch/arm/mach-at91/at91sam9263_devices.c b/arch/arm/mach-at91/at91sam9263_devices.c
index 366a7765635..53688c46f95 100644
--- a/arch/arm/mach-at91/at91sam9263_devices.c
+++ b/arch/arm/mach-at91/at91sam9263_devices.c
@@ -23,6 +23,7 @@
 #include <mach/board.h>
 #include <mach/at91sam9263.h>
 #include <mach/at91sam9263_matrix.h>
+#include <mach/at91_matrix.h>
 #include <mach/at91sam9_smc.h>
 
 #include "generic.h"
@@ -409,7 +410,7 @@ void __init at91_add_device_cf(struct at91_cf_data *data)
          * we assume SMC timings are configured by board code,
          * except True IDE where timings are controlled by driver
          */
-        ebi0_csa = at91_sys_read(AT91_MATRIX_EBI0CSA);
+        ebi0_csa = at91_matrix_read(AT91_MATRIX_EBI0CSA);
         switch (data->chipselect) {
         case 4:
                 at91_set_A_periph(AT91_PIN_PD6, 0);  /* EBI0_NCS4/CFCS0 */
@@ -428,7 +429,7 @@ void __init at91_add_device_cf(struct at91_cf_data *data)
                        data->chipselect);
                 return;
         }
-        at91_sys_write(AT91_MATRIX_EBI0CSA, ebi0_csa);
+        at91_matrix_write(AT91_MATRIX_EBI0CSA, ebi0_csa);
 
         if (gpio_is_valid(data->det_pin)) {
                 at91_set_gpio_input(data->det_pin, 1);
@@ -496,8 +497,8 @@ void __init at91_add_device_nand(struct atmel_nand_data *data)
         if (!data)
                 return;
 
-        csa = at91_sys_read(AT91_MATRIX_EBI0CSA);
-        at91_sys_write(AT91_MATRIX_EBI0CSA, csa | AT91_MATRIX_EBI0_CS3A_SMC_SMARTMEDIA);
+        csa = at91_matrix_read(AT91_MATRIX_EBI0CSA);
+        at91_matrix_write(AT91_MATRIX_EBI0CSA, csa | AT91_MATRIX_EBI0_CS3A_SMC_SMARTMEDIA);
 
         /* enable pin */
         if (gpio_is_valid(data->enable_pin))
@@ -891,7 +892,8 @@ static struct platform_device at91sam9263_isi_device = {
         .num_resources  = ARRAY_SIZE(isi_resources),
 };
 
-void __init at91_add_device_isi(void)
+void __init at91_add_device_isi(struct isi_platform_data *data,
+                bool use_pck_as_mck)
 {
         at91_set_A_periph(AT91_PIN_PE0, 0);     /* ISI_D0 */
         at91_set_A_periph(AT91_PIN_PE1, 0);     /* ISI_D1 */
@@ -904,14 +906,20 @@ void __init at91_add_device_isi(void)
         at91_set_A_periph(AT91_PIN_PE8, 0);     /* ISI_PCK */
         at91_set_A_periph(AT91_PIN_PE9, 0);     /* ISI_HSYNC */
         at91_set_A_periph(AT91_PIN_PE10, 0);    /* ISI_VSYNC */
-        at91_set_B_periph(AT91_PIN_PE11, 0);    /* ISI_MCK (PCK3) */
         at91_set_B_periph(AT91_PIN_PE12, 0);    /* ISI_PD8 */
         at91_set_B_periph(AT91_PIN_PE13, 0);    /* ISI_PD9 */
         at91_set_B_periph(AT91_PIN_PE14, 0);    /* ISI_PD10 */
         at91_set_B_periph(AT91_PIN_PE15, 0);    /* ISI_PD11 */
+
+        if (use_pck_as_mck) {
+                at91_set_B_periph(AT91_PIN_PE11, 0);    /* ISI_MCK (PCK3) */
+
+                /* TODO: register the PCK for ISI_MCK and set its parent */
+        }
 }
 #else
-void __init at91_add_device_isi(void) {}
+void __init at91_add_device_isi(struct isi_platform_data *data,
+                bool use_pck_as_mck) {}
 #endif
 
 
@@ -959,6 +967,8 @@ static struct resource rtt0_resources[] = {
                 .start  = AT91SAM9263_BASE_RTT0,
                 .end    = AT91SAM9263_BASE_RTT0 + SZ_16 - 1,
                 .flags  = IORESOURCE_MEM,
+        }, {
+                .flags  = IORESOURCE_MEM,
         }
 };
 
@@ -966,7 +976,6 @@ static struct platform_device at91sam9263_rtt0_device = {
         .name           = "at91_rtt",
         .id             = 0,
         .resource       = rtt0_resources,
-        .num_resources  = ARRAY_SIZE(rtt0_resources),
 };
 
 static struct resource rtt1_resources[] = {
@@ -974,6 +983,8 @@ static struct resource rtt1_resources[] = {
                 .start  = AT91SAM9263_BASE_RTT1,
                 .end    = AT91SAM9263_BASE_RTT1 + SZ_16 - 1,
                 .flags  = IORESOURCE_MEM,
+        }, {
+                .flags  = IORESOURCE_MEM,
         }
 };
 
@@ -981,11 +992,53 @@ static struct platform_device at91sam9263_rtt1_device = {
         .name           = "at91_rtt",
         .id             = 1,
         .resource       = rtt1_resources,
-        .num_resources  = ARRAY_SIZE(rtt1_resources),
 };
 
+#if IS_ENABLED(CONFIG_RTC_DRV_AT91SAM9)
+static void __init at91_add_device_rtt_rtc(void)
+{
+        struct platform_device *pdev;
+        struct resource *r;
+
+        switch (CONFIG_RTC_DRV_AT91SAM9_RTT) {
+        case 0:
+                /*
+                 * The second resource is needed only for the chosen RTT:
+                 * GPBR will serve as the storage for RTC time offset
+                 */
+                at91sam9263_rtt0_device.num_resources = 2;
+                at91sam9263_rtt1_device.num_resources = 1;
+                pdev = &at91sam9263_rtt0_device;
+                r = rtt0_resources;
+                break;
+        case 1:
+                at91sam9263_rtt0_device.num_resources = 1;
+                at91sam9263_rtt1_device.num_resources = 2;
+                pdev = &at91sam9263_rtt1_device;
+                r = rtt1_resources;
+                break;
+        default:
+                pr_err("at91sam9263: only supports 2 RTT (%d)\n",
+                       CONFIG_RTC_DRV_AT91SAM9_RTT);
+                return;
+        }
+
+        pdev->name = "rtc-at91sam9";
+        r[1].start = AT91SAM9263_BASE_GPBR + 4 * CONFIG_RTC_DRV_AT91SAM9_GPBR;
+        r[1].end = r[1].start + 3;
+}
+#else
+static void __init at91_add_device_rtt_rtc(void)
+{
+        /* Only one resource is needed: RTT not used as RTC */
+        at91sam9263_rtt0_device.num_resources = 1;
+        at91sam9263_rtt1_device.num_resources = 1;
+}
+#endif
+
 static void __init at91_add_device_rtt(void)
 {
+        at91_add_device_rtt_rtc();
         platform_device_register(&at91sam9263_rtt0_device);
         platform_device_register(&at91sam9263_rtt1_device);
 }
@@ -1371,7 +1424,6 @@ static inline void configure_usart2_pins(unsigned pins)
 }
 
 static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART];   /* the UARTs to use */
-struct platform_device *atmel_default_console_device;   /* the serial console device */
 
 void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
 {
diff --git a/arch/arm/mach-at91/at91sam926x_time.c b/arch/arm/mach-at91/at91sam926x_time.c
index d89ead740a9..a94758b4273 100644
--- a/arch/arm/mach-at91/at91sam926x_time.c
+++ b/arch/arm/mach-at91/at91sam926x_time.c
@@ -14,6 +14,9 @@
 #include <linux/kernel.h>
 #include <linux/clk.h>
 #include <linux/clockchips.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
 
 #include <asm/mach/time.h>
 
@@ -133,7 +136,8 @@ static irqreturn_t at91sam926x_pit_interrupt(int irq, void *dev_id)
 static struct irqaction at91sam926x_pit_irq = {
         .name           = "at91_tick",
         .flags          = IRQF_SHARED | IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
-        .handler        = at91sam926x_pit_interrupt
+        .handler        = at91sam926x_pit_interrupt,
+        .irq            = AT91_ID_SYS,
 };
 
 static void at91sam926x_pit_reset(void)
@@ -149,6 +153,51 @@ static void at91sam926x_pit_reset(void)
         pit_write(AT91_PIT_MR, (pit_cycle - 1) | AT91_PIT_PITEN);
 }
 
+#ifdef CONFIG_OF
+static struct of_device_id pit_timer_ids[] = {
+        { .compatible = "atmel,at91sam9260-pit" },
+        { /* sentinel */ }
+};
+
+static int __init of_at91sam926x_pit_init(void)
+{
+        struct device_node      *np;
+        int                     ret;
+
+        np = of_find_matching_node(NULL, pit_timer_ids);
+        if (!np)
+                goto err;
+
+        pit_base_addr = of_iomap(np, 0);
+        if (!pit_base_addr)
+                goto node_err;
+
+        /* Get the interrupts property */
+        ret = irq_of_parse_and_map(np, 0);
+        if (!ret) {
+                pr_crit("AT91: PIT: Unable to get IRQ from DT\n");
+                goto ioremap_err;
+        }
+        at91sam926x_pit_irq.irq = ret;
+
+        of_node_put(np);
+
+        return 0;
+
+ioremap_err:
+        iounmap(pit_base_addr);
+node_err:
+        of_node_put(np);
+err:
+        return -EINVAL;
+}
+#else
+static int __init of_at91sam926x_pit_init(void)
+{
+        return -EINVAL;
+}
+#endif
+
 /*
  * Set up both clocksource and clockevent support.
  */
@@ -156,6 +205,10 @@ static void __init at91sam926x_pit_init(void)
 {
         unsigned long   pit_rate;
         unsigned        bits;
+        int             ret;
+
+        /* For device tree enabled device: initialize here */
+        of_at91sam926x_pit_init();
 
         /*
          * Use our actual MCK to figure out how many MCK/16 ticks per
@@ -177,7 +230,9 @@ static void __init at91sam926x_pit_init(void)
         clocksource_register_hz(&pit_clk, pit_rate);
 
         /* Set up irq handler */
-        setup_irq(AT91_ID_SYS, &at91sam926x_pit_irq);
+        ret = setup_irq(at91sam926x_pit_irq.irq, &at91sam926x_pit_irq);
+        if (ret)
+                pr_crit("AT91: PIT: Unable to setup IRQ\n");
 
         /* Set up and register clockevents */
         pit_clkevt.mult = div_sc(pit_rate, NSEC_PER_SEC, pit_clkevt.shift);
@@ -193,6 +248,15 @@ static void at91sam926x_pit_suspend(void)
 
 void __init at91sam926x_ioremap_pit(u32 addr)
 {
+#if defined(CONFIG_OF)
+        struct device_node *np =
+                of_find_matching_node(NULL, pit_timer_ids);
+
+        if (np) {
+                of_node_put(np);
+                return;
+        }
+#endif
         pit_base_addr = ioremap(addr, 16);
 
         if (!pit_base_addr)
diff --git a/arch/arm/mach-at91/at91sam9_alt_reset.S b/arch/arm/mach-at91/at91sam9_alt_reset.S
index 518e4237717..7af2e108b8a 100644
--- a/arch/arm/mach-at91/at91sam9_alt_reset.S
+++ b/arch/arm/mach-at91/at91sam9_alt_reset.S
@@ -15,16 +15,17 @@
 
 #include <linux/linkage.h>
 #include <mach/hardware.h>
-#include <mach/at91sam9_sdramc.h>
+#include <mach/at91_ramc.h>
 #include <mach/at91_rstc.h>
 
                         .arm
 
                         .globl  at91sam9_alt_restart
 
-at91sam9_alt_restart:   ldr     r0, .at91_va_base_sdramc        @ preload constants
-                        ldr     r1, =at91_rstc_base
-                        ldr     r1, [r1]
+at91sam9_alt_restart:   ldr     r0, =at91_ramc_base             @ preload constants
+                        ldr     r0, [r0]
+                        ldr     r4, =at91_rstc_base
+                        ldr     r1, [r4]
 
                         mov     r2, #1
                         mov     r3, #AT91_SDRAMC_LPCB_POWER_DOWN
@@ -37,6 +38,3 @@ at91sam9_alt_restart:	ldr	r0, .at91_va_base_sdramc	@ preload constants
                         str     r4, [r1, #AT91_RSTC_CR]         @ reset processor
 
                         b       .
-
-.at91_va_base_sdramc:
-        .word AT91_VA_BASE_SYS + AT91_SDRAMC0
diff --git a/arch/arm/mach-at91/at91sam9g45.c b/arch/arm/mach-at91/at91sam9g45.c
index 1cb6a96b1c1..0014573dfe1 100644
--- a/arch/arm/mach-at91/at91sam9g45.c
+++ b/arch/arm/mach-at91/at91sam9g45.c
@@ -229,6 +229,9 @@ static struct clk_lookup periph_clocks_lookups[] = {
         CLKDEV_CON_DEV_ID("usart", "fff90000.serial", &usart1_clk),
         CLKDEV_CON_DEV_ID("usart", "fff94000.serial", &usart2_clk),
         CLKDEV_CON_DEV_ID("usart", "fff98000.serial", &usart3_clk),
+        /* more tc lookup table for DT entries */
+        CLKDEV_CON_DEV_ID("t0_clk", "fff7c000.timer", &tcb0_clk),
+        CLKDEV_CON_DEV_ID("t0_clk", "fffd4000.timer", &tcb0_clk),
         /* fake hclk clock */
         CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &uhphs_clk),
         CLKDEV_CON_ID("pioA", &pioA_clk),
@@ -331,12 +334,16 @@ static void __init at91sam9g45_ioremap_registers(void)
 {
         at91_ioremap_shdwc(AT91SAM9G45_BASE_SHDWC);
         at91_ioremap_rstc(AT91SAM9G45_BASE_RSTC);
+        at91_ioremap_ramc(0, AT91SAM9G45_BASE_DDRSDRC1, 512);
+        at91_ioremap_ramc(1, AT91SAM9G45_BASE_DDRSDRC0, 512);
         at91sam926x_ioremap_pit(AT91SAM9G45_BASE_PIT);
         at91sam9_ioremap_smc(0, AT91SAM9G45_BASE_SMC);
+        at91_ioremap_matrix(AT91SAM9G45_BASE_MATRIX);
 }
 
 static void __init at91sam9g45_initialize(void)
 {
+        arm_pm_idle = at91sam9_idle;
         arm_pm_restart = at91sam9g45_restart;
         at91_extern_irq = (1 << AT91SAM9G45_ID_IRQ0);
 
diff --git a/arch/arm/mach-at91/at91sam9g45_devices.c b/arch/arm/mach-at91/at91sam9g45_devices.c
index 96e2adcd5a8..4320b209678 100644
--- a/arch/arm/mach-at91/at91sam9g45_devices.c
+++ b/arch/arm/mach-at91/at91sam9g45_devices.c
@@ -14,6 +14,7 @@
 
 #include <linux/dma-mapping.h>
 #include <linux/gpio.h>
+#include <linux/clk.h>
 #include <linux/platform_device.h>
 #include <linux/i2c-gpio.h>
 #include <linux/atmel-mci.h>
@@ -24,11 +25,15 @@
 #include <mach/board.h>
 #include <mach/at91sam9g45.h>
 #include <mach/at91sam9g45_matrix.h>
+#include <mach/at91_matrix.h>
 #include <mach/at91sam9_smc.h>
 #include <mach/at_hdmac.h>
 #include <mach/atmel-mci.h>
 
+#include <media/atmel-isi.h>
+
 #include "generic.h"
+#include "clock.h"
 
 
 /* --------------------------------------------------------------------
@@ -553,8 +558,8 @@ void __init at91_add_device_nand(struct atmel_nand_data *data)
         if (!data)
                 return;
 
-        csa = at91_sys_read(AT91_MATRIX_EBICSA);
-        at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA);
+        csa = at91_matrix_read(AT91_MATRIX_EBICSA);
+        at91_matrix_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA);
 
         /* enable pin */
         if (gpio_is_valid(data->enable_pin))
@@ -870,6 +875,96 @@ void __init at91_add_device_ac97(struct ac97c_platform_data *data)
 void __init at91_add_device_ac97(struct ac97c_platform_data *data) {}
 #endif
 
+/* --------------------------------------------------------------------
+ *  Image Sensor Interface
+ * -------------------------------------------------------------------- */
+#if defined(CONFIG_VIDEO_ATMEL_ISI) || defined(CONFIG_VIDEO_ATMEL_ISI_MODULE)
+static u64 isi_dmamask = DMA_BIT_MASK(32);
+static struct isi_platform_data isi_data;
+
+struct resource isi_resources[] = {
+        [0] = {
+                .start  = AT91SAM9G45_BASE_ISI,
+                .end    = AT91SAM9G45_BASE_ISI + SZ_16K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = AT91SAM9G45_ID_ISI,
+                .end    = AT91SAM9G45_ID_ISI,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device at91sam9g45_isi_device = {
+        .name           = "atmel_isi",
+        .id             = 0,
+        .dev            = {
+                        .dma_mask               = &isi_dmamask,
+                        .coherent_dma_mask      = DMA_BIT_MASK(32),
+                        .platform_data          = &isi_data,
+        },
+        .resource       = isi_resources,
+        .num_resources  = ARRAY_SIZE(isi_resources),
+};
+
+static struct clk_lookup isi_mck_lookups[] = {
+        CLKDEV_CON_DEV_ID("isi_mck", "atmel_isi.0", NULL),
+};
+
+void __init at91_add_device_isi(struct isi_platform_data *data,
+                bool use_pck_as_mck)
+{
+        struct clk *pck;
+        struct clk *parent;
+
+        if (!data)
+                return;
+        isi_data = *data;
+
+        at91_set_A_periph(AT91_PIN_PB20, 0);    /* ISI_D0 */
+        at91_set_A_periph(AT91_PIN_PB21, 0);    /* ISI_D1 */
+        at91_set_A_periph(AT91_PIN_PB22, 0);    /* ISI_D2 */
+        at91_set_A_periph(AT91_PIN_PB23, 0);    /* ISI_D3 */
+        at91_set_A_periph(AT91_PIN_PB24, 0);    /* ISI_D4 */
+        at91_set_A_periph(AT91_PIN_PB25, 0);    /* ISI_D5 */
+        at91_set_A_periph(AT91_PIN_PB26, 0);    /* ISI_D6 */
+        at91_set_A_periph(AT91_PIN_PB27, 0);    /* ISI_D7 */
+        at91_set_A_periph(AT91_PIN_PB28, 0);    /* ISI_PCK */
+        at91_set_A_periph(AT91_PIN_PB30, 0);    /* ISI_HSYNC */
+        at91_set_A_periph(AT91_PIN_PB29, 0);    /* ISI_VSYNC */
+        at91_set_B_periph(AT91_PIN_PB8, 0);     /* ISI_PD8 */
+        at91_set_B_periph(AT91_PIN_PB9, 0);     /* ISI_PD9 */
+        at91_set_B_periph(AT91_PIN_PB10, 0);    /* ISI_PD10 */
+        at91_set_B_periph(AT91_PIN_PB11, 0);    /* ISI_PD11 */
+
+        platform_device_register(&at91sam9g45_isi_device);
+
+        if (use_pck_as_mck) {
+                at91_set_B_periph(AT91_PIN_PB31, 0);    /* ISI_MCK (PCK1) */
+
+                pck = clk_get(NULL, "pck1");
+                parent = clk_get(NULL, "plla");
+
+                BUG_ON(IS_ERR(pck) || IS_ERR(parent));
+
+                if (clk_set_parent(pck, parent)) {
+                        pr_err("Failed to set PCK's parent\n");
+                } else {
+                        /* Register PCK as ISI_MCK */
+                        isi_mck_lookups[0].clk = pck;
+                        clkdev_add_table(isi_mck_lookups,
+                                        ARRAY_SIZE(isi_mck_lookups));
+                }
+
+                clk_put(pck);
+                clk_put(parent);
+        }
+}
+#else
+void __init at91_add_device_isi(struct isi_platform_data *data,
+                bool use_pck_as_mck) {}
+#endif
+
 
 /* --------------------------------------------------------------------
  *  LCD Controller
@@ -957,7 +1052,7 @@ void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data) {}
 static struct resource tcb0_resources[] = {
         [0] = {
                 .start  = AT91SAM9G45_BASE_TCB0,
-                .end    = AT91SAM9G45_BASE_TCB0 + SZ_16K - 1,
+                .end    = AT91SAM9G45_BASE_TCB0 + SZ_256 - 1,
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
@@ -978,7 +1073,7 @@ static struct platform_device at91sam9g45_tcb0_device = {
 static struct resource tcb1_resources[] = {
         [0] = {
                 .start  = AT91SAM9G45_BASE_TCB1,
-                .end    = AT91SAM9G45_BASE_TCB1 + SZ_16K - 1,
+                .end    = AT91SAM9G45_BASE_TCB1 + SZ_256 - 1,
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
@@ -995,8 +1090,25 @@ static struct platform_device at91sam9g45_tcb1_device = {
         .num_resources  = ARRAY_SIZE(tcb1_resources),
 };
 
+#if defined(CONFIG_OF)
+static struct of_device_id tcb_ids[] = {
+        { .compatible = "atmel,at91rm9200-tcb" },
+        { /*sentinel*/ }
+};
+#endif
+
 static void __init at91_add_device_tc(void)
 {
+#if defined(CONFIG_OF)
+        struct device_node *np;
+
+        np = of_find_matching_node(NULL, tcb_ids);
+        if (np) {
+                of_node_put(np);
+                return;
+        }
+#endif
+
         platform_device_register(&at91sam9g45_tcb0_device);
         platform_device_register(&at91sam9g45_tcb1_device);
 }
@@ -1099,6 +1211,8 @@ static struct resource rtt_resources[] = {
                 .start  = AT91SAM9G45_BASE_RTT,
                 .end    = AT91SAM9G45_BASE_RTT + SZ_16 - 1,
                 .flags  = IORESOURCE_MEM,
+        }, {
+                .flags  = IORESOURCE_MEM,
         }
 };
 
@@ -1106,11 +1220,32 @@ static struct platform_device at91sam9g45_rtt_device = {
         .name           = "at91_rtt",
         .id             = 0,
         .resource       = rtt_resources,
-        .num_resources  = ARRAY_SIZE(rtt_resources),
 };
 
+#if IS_ENABLED(CONFIG_RTC_DRV_AT91SAM9)
+static void __init at91_add_device_rtt_rtc(void)
+{
+        at91sam9g45_rtt_device.name = "rtc-at91sam9";
+        /*
+         * The second resource is needed:
+         * GPBR will serve as the storage for RTC time offset
+         */
+        at91sam9g45_rtt_device.num_resources = 2;
+        rtt_resources[1].start = AT91SAM9G45_BASE_GPBR +
+                                 4 * CONFIG_RTC_DRV_AT91SAM9_GPBR;
+        rtt_resources[1].end = rtt_resources[1].start + 3;
+}
+#else
+static void __init at91_add_device_rtt_rtc(void)
+{
+        /* Only one resource is needed: RTT not used as RTC */
+        at91sam9g45_rtt_device.num_resources = 1;
+}
+#endif
+
 static void __init at91_add_device_rtt(void)
 {
+        at91_add_device_rtt_rtc();
         platform_device_register(&at91sam9g45_rtt_device);
 }
 
@@ -1565,7 +1700,6 @@ static inline void configure_usart3_pins(unsigned pins)
 }
 
 static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART];   /* the UARTs to use */
-struct platform_device *atmel_default_console_device;   /* the serial console device */
 
 void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
 {
diff --git a/arch/arm/mach-at91/at91sam9g45_reset.S b/arch/arm/mach-at91/at91sam9g45_reset.S
index 0468be10980..9d457182c86 100644
--- a/arch/arm/mach-at91/at91sam9g45_reset.S
+++ b/arch/arm/mach-at91/at91sam9g45_reset.S
@@ -12,7 +12,7 @@
 
 #include <linux/linkage.h>
 #include <mach/hardware.h>
-#include <mach/at91sam9_ddrsdr.h>
+#include <mach/at91_ramc.h>
 #include <mach/at91_rstc.h>
 
                         .arm
@@ -20,9 +20,10 @@
                         .globl  at91sam9g45_restart
 
 at91sam9g45_restart:
-                        ldr     r0, .at91_va_base_sdramc0       @ preload constants
-                        ldr     r1, =at91_rstc_base
-                        ldr     r1, [r1]
+                        ldr     r5, =at91_ramc_base             @ preload constants
+                        ldr     r0, [r5]
+                        ldr     r4, =at91_rstc_base
+                        ldr     r1, [r4]
 
                         mov     r2, #1
                         mov     r3, #AT91_DDRSDRC_LPCB_POWER_DOWN
@@ -35,6 +36,3 @@ at91sam9g45_restart:
                         str     r4, [r1, #AT91_RSTC_CR]         @ reset processor
 
                         b       .
-
-.at91_va_base_sdramc0:
-        .word AT91_VA_BASE_SYS + AT91_DDRSDRC0
diff --git a/arch/arm/mach-at91/at91sam9rl.c b/arch/arm/mach-at91/at91sam9rl.c
index d2c91a841cb..63d9372eb18 100644
--- a/arch/arm/mach-at91/at91sam9rl.c
+++ b/arch/arm/mach-at91/at91sam9rl.c
@@ -11,6 +11,7 @@
 
 #include <linux/module.h>
 
+#include <asm/proc-fns.h>
 #include <asm/irq.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
@@ -287,12 +288,15 @@ static void __init at91sam9rl_ioremap_registers(void)
 {
         at91_ioremap_shdwc(AT91SAM9RL_BASE_SHDWC);
         at91_ioremap_rstc(AT91SAM9RL_BASE_RSTC);
+        at91_ioremap_ramc(0, AT91SAM9RL_BASE_SDRAMC, 512);
         at91sam926x_ioremap_pit(AT91SAM9RL_BASE_PIT);
         at91sam9_ioremap_smc(0, AT91SAM9RL_BASE_SMC);
+        at91_ioremap_matrix(AT91SAM9RL_BASE_MATRIX);
 }
 
 static void __init at91sam9rl_initialize(void)
 {
+        arm_pm_idle = at91sam9_idle;
         arm_pm_restart = at91sam9_alt_restart;
         at91_extern_irq = (1 << AT91SAM9RL_ID_IRQ0);
 
diff --git a/arch/arm/mach-at91/at91sam9rl_devices.c b/arch/arm/mach-at91/at91sam9rl_devices.c
index 9be71c11d0f..eda72e83037 100644
--- a/arch/arm/mach-at91/at91sam9rl_devices.c
+++ b/arch/arm/mach-at91/at91sam9rl_devices.c
@@ -20,6 +20,7 @@
 #include <mach/board.h>
 #include <mach/at91sam9rl.h>
 #include <mach/at91sam9rl_matrix.h>
+#include <mach/at91_matrix.h>
 #include <mach/at91sam9_smc.h>
 #include <mach/at_hdmac.h>
 
@@ -265,8 +266,8 @@ void __init at91_add_device_nand(struct atmel_nand_data *data)
         if (!data)
                 return;
 
-        csa = at91_sys_read(AT91_MATRIX_EBICSA);
-        at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
+        csa = at91_matrix_read(AT91_MATRIX_EBICSA);
+        at91_matrix_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
 
         /* enable pin */
         if (gpio_is_valid(data->enable_pin))
@@ -682,6 +683,8 @@ static struct resource rtt_resources[] = {
                 .start  = AT91SAM9RL_BASE_RTT,
                 .end    = AT91SAM9RL_BASE_RTT + SZ_16 - 1,
                 .flags  = IORESOURCE_MEM,
+        }, {
+                .flags  = IORESOURCE_MEM,
         }
 };
 
@@ -689,11 +692,32 @@ static struct platform_device at91sam9rl_rtt_device = {
         .name           = "at91_rtt",
         .id             = 0,
         .resource       = rtt_resources,
-        .num_resources  = ARRAY_SIZE(rtt_resources),
 };
 
+#if IS_ENABLED(CONFIG_RTC_DRV_AT91SAM9)
+static void __init at91_add_device_rtt_rtc(void)
+{
+        at91sam9rl_rtt_device.name = "rtc-at91sam9";
+        /*
+         * The second resource is needed:
+         * GPBR will serve as the storage for RTC time offset
+         */
+        at91sam9rl_rtt_device.num_resources = 2;
+        rtt_resources[1].start = AT91SAM9RL_BASE_GPBR +
+                                 4 * CONFIG_RTC_DRV_AT91SAM9_GPBR;
+        rtt_resources[1].end = rtt_resources[1].start + 3;
+}
+#else
+static void __init at91_add_device_rtt_rtc(void)
+{
+        /* Only one resource is needed: RTT not used as RTC */
+        at91sam9rl_rtt_device.num_resources = 1;
+}
+#endif
+
 static void __init at91_add_device_rtt(void)
 {
+        at91_add_device_rtt_rtc();
         platform_device_register(&at91sam9rl_rtt_device);
 }
 
@@ -1128,7 +1152,6 @@ static inline void configure_usart3_pins(unsigned pins)
 }
 
 static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART];   /* the UARTs to use */
-struct platform_device *atmel_default_console_device;   /* the serial console device */
 
 void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
 {
diff --git a/arch/arm/mach-at91/at91sam9x5.c b/arch/arm/mach-at91/at91sam9x5.c
new file mode 100644
index 00000000000..a34d96afa74
--- /dev/null
+++ b/arch/arm/mach-at91/at91sam9x5.c
@@ -0,0 +1,368 @@
+/*
+ *  Chip-specific setup code for the AT91SAM9x5 family
+ *
+ *  Copyright (C) 2010-2012 Atmel Corporation.
+ *
+ * Licensed under GPLv2 or later.
+ */
+
+#include <linux/module.h>
+#include <linux/dma-mapping.h>
+
+#include <asm/irq.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <mach/at91sam9x5.h>
+#include <mach/at91_pmc.h>
+#include <mach/cpu.h>
+#include <mach/board.h>
+
+#include "soc.h"
+#include "generic.h"
+#include "clock.h"
+#include "sam9_smc.h"
+
+/* --------------------------------------------------------------------
+ *  Clocks
+ * -------------------------------------------------------------------- */
+
+/*
+ * The peripheral clocks.
+ */
+static struct clk pioAB_clk = {
+        .name           = "pioAB_clk",
+        .pmc_mask       = 1 << AT91SAM9X5_ID_PIOAB,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk pioCD_clk = {
+        .name           = "pioCD_clk",
+        .pmc_mask       = 1 << AT91SAM9X5_ID_PIOCD,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk smd_clk = {
+        .name           = "smd_clk",
+        .pmc_mask       = 1 << AT91SAM9X5_ID_SMD,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk usart0_clk = {
+        .name           = "usart0_clk",
+        .pmc_mask       = 1 << AT91SAM9X5_ID_USART0,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk usart1_clk = {
+        .name           = "usart1_clk",
+        .pmc_mask       = 1 << AT91SAM9X5_ID_USART1,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk usart2_clk = {
+        .name           = "usart2_clk",
+        .pmc_mask       = 1 << AT91SAM9X5_ID_USART2,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+/* USART3 clock - Only for sam9g25/sam9x25 */
+static struct clk usart3_clk = {
+        .name           = "usart3_clk",
+        .pmc_mask       = 1 << AT91SAM9X5_ID_USART3,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk twi0_clk = {
+        .name           = "twi0_clk",
+        .pmc_mask       = 1 << AT91SAM9X5_ID_TWI0,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk twi1_clk = {
+        .name           = "twi1_clk",
+        .pmc_mask       = 1 << AT91SAM9X5_ID_TWI1,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk twi2_clk = {
+        .name           = "twi2_clk",
+        .pmc_mask       = 1 << AT91SAM9X5_ID_TWI2,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk mmc0_clk = {
+        .name           = "mci0_clk",
+        .pmc_mask       = 1 << AT91SAM9X5_ID_MCI0,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk spi0_clk = {
+        .name           = "spi0_clk",
+        .pmc_mask       = 1 << AT91SAM9X5_ID_SPI0,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk spi1_clk = {
+        .name           = "spi1_clk",
+        .pmc_mask       = 1 << AT91SAM9X5_ID_SPI1,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk uart0_clk = {
+        .name           = "uart0_clk",
+        .pmc_mask       = 1 << AT91SAM9X5_ID_UART0,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk uart1_clk = {
+        .name           = "uart1_clk",
+        .pmc_mask       = 1 << AT91SAM9X5_ID_UART1,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk tcb0_clk = {
+        .name           = "tcb0_clk",
+        .pmc_mask       = 1 << AT91SAM9X5_ID_TCB,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk pwm_clk = {
+        .name           = "pwm_clk",
+        .pmc_mask       = 1 << AT91SAM9X5_ID_PWM,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk adc_clk = {
+        .name           = "adc_clk",
+        .pmc_mask       = 1 << AT91SAM9X5_ID_ADC,
+        .type   = CLK_TYPE_PERIPHERAL,
+};
+static struct clk dma0_clk = {
+        .name           = "dma0_clk",
+        .pmc_mask       = 1 << AT91SAM9X5_ID_DMA0,
+        .type   = CLK_TYPE_PERIPHERAL,
+};
+static struct clk dma1_clk = {
+        .name           = "dma1_clk",
+        .pmc_mask       = 1 << AT91SAM9X5_ID_DMA1,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk uhphs_clk = {
+        .name           = "uhphs_clk",
+        .pmc_mask       = 1 << AT91SAM9X5_ID_UHPHS,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk udphs_clk = {
+        .name           = "udphs_clk",
+        .pmc_mask       = 1 << AT91SAM9X5_ID_UDPHS,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+/* emac0 clock - Only for sam9g25/sam9x25/sam9g35/sam9x35 */
+static struct clk macb0_clk = {
+        .name           = "pclk",
+        .pmc_mask       = 1 << AT91SAM9X5_ID_EMAC0,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+/* lcd clock - Only for sam9g15/sam9g35/sam9x35 */
+static struct clk lcdc_clk = {
+        .name           = "lcdc_clk",
+        .pmc_mask       = 1 << AT91SAM9X5_ID_LCDC,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+/* isi clock - Only for sam9g25 */
+static struct clk isi_clk = {
+        .name           = "isi_clk",
+        .pmc_mask       = 1 << AT91SAM9X5_ID_ISI,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk mmc1_clk = {
+        .name           = "mci1_clk",
+        .pmc_mask       = 1 << AT91SAM9X5_ID_MCI1,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+/* emac1 clock - Only for sam9x25 */
+static struct clk macb1_clk = {
+        .name           = "pclk",
+        .pmc_mask       = 1 << AT91SAM9X5_ID_EMAC1,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk ssc_clk = {
+        .name           = "ssc_clk",
+        .pmc_mask       = 1 << AT91SAM9X5_ID_SSC,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+/* can0 clock - Only for sam9x35 */
+static struct clk can0_clk = {
+        .name           = "can0_clk",
+        .pmc_mask       = 1 << AT91SAM9X5_ID_CAN0,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+/* can1 clock - Only for sam9x35 */
+static struct clk can1_clk = {
+        .name           = "can1_clk",
+        .pmc_mask       = 1 << AT91SAM9X5_ID_CAN1,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+
+static struct clk *periph_clocks[] __initdata = {
+        &pioAB_clk,
+        &pioCD_clk,
+        &smd_clk,
+        &usart0_clk,
+        &usart1_clk,
+        &usart2_clk,
+        &twi0_clk,
+        &twi1_clk,
+        &twi2_clk,
+        &mmc0_clk,
+        &spi0_clk,
+        &spi1_clk,
+        &uart0_clk,
+        &uart1_clk,
+        &tcb0_clk,
+        &pwm_clk,
+        &adc_clk,
+        &dma0_clk,
+        &dma1_clk,
+        &uhphs_clk,
+        &udphs_clk,
+        &mmc1_clk,
+        &ssc_clk,
+        // irq0
+};
+
+static struct clk_lookup periph_clocks_lookups[] = {
+        /* lookup table for DT entries */
+        CLKDEV_CON_DEV_ID("usart", "fffff200.serial", &mck),
+        CLKDEV_CON_DEV_ID("usart", "f801c000.serial", &usart0_clk),
+        CLKDEV_CON_DEV_ID("usart", "f8020000.serial", &usart1_clk),
+        CLKDEV_CON_DEV_ID("usart", "f8024000.serial", &usart2_clk),
+        CLKDEV_CON_DEV_ID("usart", "f8028000.serial", &usart3_clk),
+        CLKDEV_CON_DEV_ID("t0_clk", "f8008000.timer", &tcb0_clk),
+        CLKDEV_CON_DEV_ID("t0_clk", "f800c000.timer", &tcb0_clk),
+        CLKDEV_CON_ID("pioA", &pioAB_clk),
+        CLKDEV_CON_ID("pioB", &pioAB_clk),
+        CLKDEV_CON_ID("pioC", &pioCD_clk),
+        CLKDEV_CON_ID("pioD", &pioCD_clk),
+        /* additional fake clock for macb_hclk */
+        CLKDEV_CON_DEV_ID("hclk", "f802c000.ethernet", &macb0_clk),
+        CLKDEV_CON_DEV_ID("hclk", "f8030000.ethernet", &macb1_clk),
+};
+
+/*
+ * The two programmable clocks.
+ * You must configure pin multiplexing to bring these signals out.
+ */
+static struct clk pck0 = {
+        .name           = "pck0",
+        .pmc_mask       = AT91_PMC_PCK0,
+        .type           = CLK_TYPE_PROGRAMMABLE,
+        .id             = 0,
+};
+static struct clk pck1 = {
+        .name           = "pck1",
+        .pmc_mask       = AT91_PMC_PCK1,
+        .type           = CLK_TYPE_PROGRAMMABLE,
+        .id             = 1,
+};
+
+static void __init at91sam9x5_register_clocks(void)
+{
+        int i;
+
+        for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
+                clk_register(periph_clocks[i]);
+
+        clkdev_add_table(periph_clocks_lookups,
+                         ARRAY_SIZE(periph_clocks_lookups));
+
+        if (cpu_is_at91sam9g25()
+        || cpu_is_at91sam9x25())
+                clk_register(&usart3_clk);
+
+        if (cpu_is_at91sam9g25()
+        || cpu_is_at91sam9x25()
+        || cpu_is_at91sam9g35()
+        || cpu_is_at91sam9x35())
+                clk_register(&macb0_clk);
+
+        if (cpu_is_at91sam9g15()
+        || cpu_is_at91sam9g35()
+        || cpu_is_at91sam9x35())
+                clk_register(&lcdc_clk);
+
+        if (cpu_is_at91sam9g25())
+                clk_register(&isi_clk);
+
+        if (cpu_is_at91sam9x25())
+                clk_register(&macb1_clk);
+
+        if (cpu_is_at91sam9x25()
+        || cpu_is_at91sam9x35()) {
+                clk_register(&can0_clk);
+                clk_register(&can1_clk);
+        }
+
+        clk_register(&pck0);
+        clk_register(&pck1);
+}
+
+/* --------------------------------------------------------------------
+ *  AT91SAM9x5 processor initialization
+ * -------------------------------------------------------------------- */
+
+static void __init at91sam9x5_map_io(void)
+{
+        at91_init_sram(0, AT91SAM9X5_SRAM_BASE, AT91SAM9X5_SRAM_SIZE);
+}
+
+static void __init at91sam9x5_ioremap_registers(void)
+{
+        at91_ioremap_ramc(0, AT91SAM9X5_BASE_DDRSDRC0, 512);
+}
+
+void __init at91sam9x5_initialize(void)
+{
+        arm_pm_restart = at91sam9g45_restart;
+        at91_extern_irq = (1 << AT91SAM9X5_ID_IRQ0);
+
+        /* Register GPIO subsystem (using DT) */
+        at91_gpio_init(NULL, 0);
+}
+
+/* --------------------------------------------------------------------
+ *  AT91SAM9x5 devices (temporary before modification of code)
+ * -------------------------------------------------------------------- */
+void __init at91_add_device_nand(struct atmel_nand_data *data) {}
+
+/* --------------------------------------------------------------------
+ *  Interrupt initialization
+ * -------------------------------------------------------------------- */
+/*
+ * The default interrupt priority levels (0 = lowest, 7 = highest).
+ */
+static unsigned int at91sam9x5_default_irq_priority[NR_AIC_IRQS] __initdata = {
+        7,      /* Advanced Interrupt Controller (FIQ) */
+        7,      /* System Peripherals */
+        1,      /* Parallel IO Controller A and B */
+        1,      /* Parallel IO Controller C and D */
+        4,      /* Soft Modem */
+        5,      /* USART 0 */
+        5,      /* USART 1 */
+        5,      /* USART 2 */
+        5,      /* USART 3 */
+        6,      /* Two-Wire Interface 0 */
+        6,      /* Two-Wire Interface 1 */
+        6,      /* Two-Wire Interface 2 */
+        0,      /* Multimedia Card Interface 0 */
+        5,      /* Serial Peripheral Interface 0 */
+        5,      /* Serial Peripheral Interface 1 */
+        5,      /* UART 0 */
+        5,      /* UART 1 */
+        0,      /* Timer Counter 0, 1, 2, 3, 4 and 5 */
+        0,      /* Pulse Width Modulation Controller */
+        0,      /* ADC Controller */
+        0,      /* DMA Controller 0 */
+        0,      /* DMA Controller 1 */
+        2,      /* USB Host High Speed port */
+        2,      /* USB Device High speed port */
+        3,      /* Ethernet MAC 0 */
+        3,      /* LDC Controller or Image Sensor Interface */
+        0,      /* Multimedia Card Interface 1 */
+        3,      /* Ethernet MAC 1 */
+        4,      /* Synchronous Serial Interface */
+        4,      /* CAN Controller 0 */
+        4,      /* CAN Controller 1 */
+        0,      /* Advanced Interrupt Controller (IRQ0) */
+};
+
+struct at91_init_soc __initdata at91sam9x5_soc = {
+        .map_io = at91sam9x5_map_io,
+        .default_irq_priority = at91sam9x5_default_irq_priority,
+        .ioremap_registers = at91sam9x5_ioremap_registers,
+        .register_clocks = at91sam9x5_register_clocks,
+        .init = at91sam9x5_initialize,
+};
diff --git a/arch/arm/mach-at91/at91x40.c b/arch/arm/mach-at91/at91x40.c
index 56ba3bd035a..5400a1d6503 100644
--- a/arch/arm/mach-at91/at91x40.c
+++ b/arch/arm/mach-at91/at91x40.c
@@ -13,6 +13,7 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/irq.h>
+#include <asm/proc-fns.h>
 #include <asm/mach/arch.h>
 #include <mach/at91x40.h>
 #include <mach/at91_st.h>
@@ -37,8 +38,19 @@ unsigned long clk_get_rate(struct clk *clk)
         return AT91X40_MASTER_CLOCK;
 }
 
+static void at91x40_idle(void)
+{
+        /*
+         * Disable the processor clock.  The processor will be automatically
+         * re-enabled by an interrupt or by a reset.
+         */
+        __raw_writel(AT91_PS_CR_CPU, AT91_PS_CR);
+        cpu_do_idle();
+}
+
 void __init at91x40_initialize(unsigned long main_clock)
 {
+        arm_pm_idle = at91x40_idle;
         at91_extern_irq = (1 << AT91X40_ID_IRQ0) | (1 << AT91X40_ID_IRQ1)
                         | (1 << AT91X40_ID_IRQ2);
 }
diff --git a/arch/arm/mach-at91/at91x40_time.c b/arch/arm/mach-at91/at91x40_time.c
index dfff2895f4b..6ca680a1d5d 100644
--- a/arch/arm/mach-at91/at91x40_time.c
+++ b/arch/arm/mach-at91/at91x40_time.c
@@ -28,6 +28,12 @@
 #include <asm/mach/time.h>
 #include <mach/at91_tc.h>
 
+#define at91_tc_read(field) \
+        __raw_readl(AT91_TC + field)
+
+#define at91_tc_write(field, value) \
+        __raw_writel(value, AT91_TC + field);
+
 /*
  *      3 counter/timer units present.
  */
@@ -37,12 +43,12 @@
 
 static unsigned long at91x40_gettimeoffset(void)
 {
-        return (at91_sys_read(AT91_TC + AT91_TC_CLK1BASE + AT91_TC_CV) * 1000000 / (AT91X40_MASTER_CLOCK / 128));
+        return (at91_tc_read(AT91_TC_CLK1BASE + AT91_TC_CV) * 1000000 / (AT91X40_MASTER_CLOCK / 128));
 }
 
 static irqreturn_t at91x40_timer_interrupt(int irq, void *dev_id)
 {
-        at91_sys_read(AT91_TC + AT91_TC_CLK1BASE + AT91_TC_SR);
+        at91_tc_read(AT91_TC_CLK1BASE + AT91_TC_SR);
         timer_tick();
         return IRQ_HANDLED;
 }
@@ -57,20 +63,20 @@ void __init at91x40_timer_init(void)
 {
         unsigned int v;
 
-        at91_sys_write(AT91_TC + AT91_TC_BCR, 0);
-        v = at91_sys_read(AT91_TC + AT91_TC_BMR);
+        at91_tc_write(AT91_TC_BCR, 0);
+        v = at91_tc_read(AT91_TC_BMR);
         v = (v & ~AT91_TC_TC1XC1S) | AT91_TC_TC1XC1S_NONE;
-        at91_sys_write(AT91_TC + AT91_TC_BMR, v);
+        at91_tc_write(AT91_TC_BMR, v);
 
-        at91_sys_write(AT91_TC + AT91_TC_CLK1BASE + AT91_TC_CCR, AT91_TC_CLKDIS);
-        at91_sys_write(AT91_TC + AT91_TC_CLK1BASE + AT91_TC_CMR, (AT91_TC_TIMER_CLOCK4 | AT91_TC_CPCTRG));
-        at91_sys_write(AT91_TC + AT91_TC_CLK1BASE + AT91_TC_IDR, 0xffffffff);
-        at91_sys_write(AT91_TC + AT91_TC_CLK1BASE + AT91_TC_RC, (AT91X40_MASTER_CLOCK / 128) / HZ - 1);
-        at91_sys_write(AT91_TC + AT91_TC_CLK1BASE + AT91_TC_IER, (1<<4));
+        at91_tc_write(AT91_TC_CLK1BASE + AT91_TC_CCR, AT91_TC_CLKDIS);
+        at91_tc_write(AT91_TC_CLK1BASE + AT91_TC_CMR, (AT91_TC_TIMER_CLOCK4 | AT91_TC_CPCTRG));
+        at91_tc_write(AT91_TC_CLK1BASE + AT91_TC_IDR, 0xffffffff);
+        at91_tc_write(AT91_TC_CLK1BASE + AT91_TC_RC, (AT91X40_MASTER_CLOCK / 128) / HZ - 1);
+        at91_tc_write(AT91_TC_CLK1BASE + AT91_TC_IER, (1<<4));
 
         setup_irq(AT91X40_ID_TC1, &at91x40_timer_irq);
 
-        at91_sys_write(AT91_TC + AT91_TC_CLK1BASE + AT91_TC_CCR, (AT91_TC_SWTRG | AT91_TC_CLKEN));
+        at91_tc_write(AT91_TC_CLK1BASE + AT91_TC_CCR, (AT91_TC_SWTRG | AT91_TC_CLKEN));
 }
 
 struct sys_timer at91x40_timer = {
diff --git a/arch/arm/mach-at91/board-cap9adk.c b/arch/arm/mach-at91/board-cap9adk.c
deleted file mode 100644
index ac3de4f7c31..00000000000
--- a/arch/arm/mach-at91/board-cap9adk.c
+++ /dev/null
@@ -1,396 +0,0 @@
-/*
- * linux/arch/arm/mach-at91/board-cap9adk.c
- *
- *  Copyright (C) 2007 Stelian Pop <stelian.pop@leadtechdesign.com>
- *  Copyright (C) 2007 Lead Tech Design <www.leadtechdesign.com>
- *  Copyright (C) 2005 SAN People
- *  Copyright (C) 2007 Atmel Corporation.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-
-#include <linux/types.h>
-#include <linux/gpio.h>
-#include <linux/init.h>
-#include <linux/mm.h>
-#include <linux/module.h>
-#include <linux/platform_device.h>
-#include <linux/spi/spi.h>
-#include <linux/spi/ads7846.h>
-#include <linux/fb.h>
-#include <linux/mtd/physmap.h>
-
-#include <video/atmel_lcdc.h>
-
-#include <mach/hardware.h>
-#include <asm/setup.h>
-#include <asm/mach-types.h>
-
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-
-#include <mach/board.h>
-#include <mach/at91cap9_matrix.h>
-#include <mach/at91sam9_smc.h>
-#include <mach/system_rev.h>
-
-#include "sam9_smc.h"
-#include "generic.h"
-
-
-static void __init cap9adk_init_early(void)
-{
-        /* Initialize processor: 12 MHz crystal */
-        at91_initialize(12000000);
-
-        /* Setup the LEDs: USER1 and USER2 LED for cpu/timer... */
-        at91_init_leds(AT91_PIN_PA10, AT91_PIN_PA11);
-        /* ... POWER LED always on */
-        at91_set_gpio_output(AT91_PIN_PC29, 1);
-
-        /* Setup the serial ports and console */
-        at91_register_uart(0, 0, 0);            /* DBGU = ttyS0 */
-        at91_set_serial_console(0);
-}
-
-/*
- * USB Host port
- */
-static struct at91_usbh_data __initdata cap9adk_usbh_data = {
-        .ports          = 2,
-        .vbus_pin       = {-EINVAL, -EINVAL},
-        .overcurrent_pin= {-EINVAL, -EINVAL},
-};
-
-/*
- * USB HS Device port
- */
-static struct usba_platform_data __initdata cap9adk_usba_udc_data = {
-        .vbus_pin       = AT91_PIN_PB31,
-};
-
-/*
- * ADS7846 Touchscreen
- */
-#if defined(CONFIG_TOUCHSCREEN_ADS7846) || defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE)
-static int ads7843_pendown_state(void)
-{
-        return !at91_get_gpio_value(AT91_PIN_PC4);      /* Touchscreen PENIRQ */
-}
-
-static struct ads7846_platform_data ads_info = {
-        .model                  = 7843,
-        .x_min                  = 150,
-        .x_max                  = 3830,
-        .y_min                  = 190,
-        .y_max                  = 3830,
-        .vref_delay_usecs       = 100,
-        .x_plate_ohms           = 450,
-        .y_plate_ohms           = 250,
-        .pressure_max           = 15000,
-        .debounce_max           = 1,
-        .debounce_rep           = 0,
-        .debounce_tol           = (~0),
-        .get_pendown_state      = ads7843_pendown_state,
-};
-
-static void __init cap9adk_add_device_ts(void)
-{
-        at91_set_gpio_input(AT91_PIN_PC4, 1);   /* Touchscreen PENIRQ */
-        at91_set_gpio_input(AT91_PIN_PC5, 1);   /* Touchscreen BUSY */
-}
-#else
-static void __init cap9adk_add_device_ts(void) {}
-#endif
-
-
-/*
- * SPI devices.
- */
-static struct spi_board_info cap9adk_spi_devices[] = {
-#if defined(CONFIG_MTD_AT91_DATAFLASH_CARD)
-        {       /* DataFlash card */
-                .modalias       = "mtd_dataflash",
-                .chip_select    = 0,
-                .max_speed_hz   = 15 * 1000 * 1000,
-                .bus_num        = 0,
-        },
-#endif
-#if defined(CONFIG_TOUCHSCREEN_ADS7846) || defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE)
-        {
-                .modalias       = "ads7846",
-                .chip_select    = 3,            /* can be 2 or 3, depending on J2 jumper */
-                .max_speed_hz   = 125000 * 26,  /* (max sample rate @ 3V) * (cmd + data + overhead) */
-                .bus_num        = 0,
-                .platform_data  = &ads_info,
-                .irq            = AT91_PIN_PC4,
-        },
-#endif
-};
-
-
-/*
- * MCI (SD/MMC)
- */
-static struct at91_mmc_data __initdata cap9adk_mmc_data = {
-        .wire4          = 1,
-        .det_pin        = -EINVAL,
-        .wp_pin         = -EINVAL,
-        .vcc_pin        = -EINVAL,
-};
-
-
-/*
- * MACB Ethernet device
- */
-static struct macb_platform_data __initdata cap9adk_macb_data = {
-        .phy_irq_pin    = -EINVAL,
-        .is_rmii        = 1,
-};
-
-
-/*
- * NAND flash
- */
-static struct mtd_partition __initdata cap9adk_nand_partitions[] = {
-        {
-                .name   = "NAND partition",
-                .offset = 0,
-                .size   = MTDPART_SIZ_FULL,
-        },
-};
-
-static struct atmel_nand_data __initdata cap9adk_nand_data = {
-        .ale            = 21,
-        .cle            = 22,
-        .det_pin        = -EINVAL,
-        .rdy_pin        = -EINVAL,
-        .enable_pin     = AT91_PIN_PD15,
-        .parts          = cap9adk_nand_partitions,
-        .num_parts      = ARRAY_SIZE(cap9adk_nand_partitions),
-};
-
-static struct sam9_smc_config __initdata cap9adk_nand_smc_config = {
-        .ncs_read_setup         = 1,
-        .nrd_setup              = 2,
-        .ncs_write_setup        = 1,
-        .nwe_setup              = 2,
-
-        .ncs_read_pulse         = 6,
-        .nrd_pulse              = 4,
-        .ncs_write_pulse        = 6,
-        .nwe_pulse              = 4,
-
-        .read_cycle             = 8,
-        .write_cycle            = 8,
-
-        .mode                   = AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE,
-        .tdf_cycles             = 1,
-};
-
-static void __init cap9adk_add_device_nand(void)
-{
-        unsigned long csa;
-
-        csa = at91_sys_read(AT91_MATRIX_EBICSA);
-        at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_EBI_VDDIOMSEL_3_3V);
-
-        cap9adk_nand_data.bus_width_16 = board_have_nand_16bit();
-        /* setup bus-width (8 or 16) */
-        if (cap9adk_nand_data.bus_width_16)
-                cap9adk_nand_smc_config.mode |= AT91_SMC_DBW_16;
-        else
-                cap9adk_nand_smc_config.mode |= AT91_SMC_DBW_8;
-
-        /* configure chip-select 3 (NAND) */
-        sam9_smc_configure(0, 3, &cap9adk_nand_smc_config);
-
-        at91_add_device_nand(&cap9adk_nand_data);
-}
-
-
-/*
- * NOR flash
- */
-static struct mtd_partition cap9adk_nor_partitions[] = {
-        {
-                .name           = "NOR partition",
-                .offset         = 0,
-                .size           = MTDPART_SIZ_FULL,
-        },
-};
-
-static struct physmap_flash_data cap9adk_nor_data = {
-        .width          = 2,
-        .parts          = cap9adk_nor_partitions,
-        .nr_parts       = ARRAY_SIZE(cap9adk_nor_partitions),
-};
-
-#define NOR_BASE        AT91_CHIPSELECT_0
-#define NOR_SIZE        SZ_8M
-
-static struct resource nor_flash_resources[] = {
-        {
-                .start  = NOR_BASE,
-                .end    = NOR_BASE + NOR_SIZE - 1,
-                .flags  = IORESOURCE_MEM,
-        }
-};
-
-static struct platform_device cap9adk_nor_flash = {
-        .name           = "physmap-flash",
-        .id             = 0,
-        .dev            = {
-                                .platform_data  = &cap9adk_nor_data,
-        },
-        .resource       = nor_flash_resources,
-        .num_resources  = ARRAY_SIZE(nor_flash_resources),
-};
-
-static struct sam9_smc_config __initdata cap9adk_nor_smc_config = {
-        .ncs_read_setup         = 2,
-        .nrd_setup              = 4,
-        .ncs_write_setup        = 2,
-        .nwe_setup              = 4,
-
-        .ncs_read_pulse         = 10,
-        .nrd_pulse              = 8,
-        .ncs_write_pulse        = 10,
-        .nwe_pulse              = 8,
-
-        .read_cycle             = 16,
-        .write_cycle            = 16,
-
-        .mode                   = AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_BAT_WRITE | AT91_SMC_DBW_16,
-        .tdf_cycles             = 1,
-};
-
-static __init void cap9adk_add_device_nor(void)
-{
-        unsigned long csa;
-
-        csa = at91_sys_read(AT91_MATRIX_EBICSA);
-        at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_EBI_VDDIOMSEL_3_3V);
-
-        /* configure chip-select 0 (NOR) */
-        sam9_smc_configure(0, 0, &cap9adk_nor_smc_config);
-
-        platform_device_register(&cap9adk_nor_flash);
-}
-
-
-/*
- * LCD Controller
- */
-#if defined(CONFIG_FB_ATMEL) || defined(CONFIG_FB_ATMEL_MODULE)
-static struct fb_videomode at91_tft_vga_modes[] = {
-        {
-                .name           = "TX09D50VM1CCA @ 60",
-                .refresh        = 60,
-                .xres           = 240,          .yres           = 320,
-                .pixclock       = KHZ2PICOS(4965),
-
-                .left_margin    = 1,            .right_margin   = 33,
-                .upper_margin   = 1,            .lower_margin   = 0,
-                .hsync_len      = 5,            .vsync_len      = 1,
-
-                .sync           = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
-                .vmode          = FB_VMODE_NONINTERLACED,
-        },
-};
-
-static struct fb_monspecs at91fb_default_monspecs = {
-        .manufacturer   = "HIT",
-        .monitor        = "TX09D70VM1CCA",
-
-        .modedb         = at91_tft_vga_modes,
-        .modedb_len     = ARRAY_SIZE(at91_tft_vga_modes),
-        .hfmin          = 15000,
-        .hfmax          = 64000,
-        .vfmin          = 50,
-        .vfmax          = 150,
-};
-
-#define AT91CAP9_DEFAULT_LCDCON2        (ATMEL_LCDC_MEMOR_LITTLE \
-                                        | ATMEL_LCDC_DISTYPE_TFT    \
-                                        | ATMEL_LCDC_CLKMOD_ALWAYSACTIVE)
-
-static void at91_lcdc_power_control(int on)
-{
-        if (on)
-                at91_set_gpio_value(AT91_PIN_PC0, 0);   /* power up */
-        else
-                at91_set_gpio_value(AT91_PIN_PC0, 1);   /* power down */
-}
-
-/* Driver datas */
-static struct atmel_lcdfb_info __initdata cap9adk_lcdc_data = {
-        .default_bpp                    = 16,
-        .default_dmacon                 = ATMEL_LCDC_DMAEN,
-        .default_lcdcon2                = AT91CAP9_DEFAULT_LCDCON2,
-        .default_monspecs               = &at91fb_default_monspecs,
-        .atmel_lcdfb_power_control      = at91_lcdc_power_control,
-        .guard_time                     = 1,
-};
-
-#else
-static struct atmel_lcdfb_info __initdata cap9adk_lcdc_data;
-#endif
-
-
-/*
- * AC97
- */
-static struct ac97c_platform_data cap9adk_ac97_data = {
-        .reset_pin      = -EINVAL,
-};
-
-
-static void __init cap9adk_board_init(void)
-{
-        /* Serial */
-        at91_add_device_serial();
-        /* USB Host */
-        at91_add_device_usbh(&cap9adk_usbh_data);
-        /* USB HS */
-        at91_add_device_usba(&cap9adk_usba_udc_data);
-        /* SPI */
-        at91_add_device_spi(cap9adk_spi_devices, ARRAY_SIZE(cap9adk_spi_devices));
-        /* Touchscreen */
-        cap9adk_add_device_ts();
-        /* MMC */
-        at91_add_device_mmc(1, &cap9adk_mmc_data);
-        /* Ethernet */
-        at91_add_device_eth(&cap9adk_macb_data);
-        /* NAND */
-        cap9adk_add_device_nand();
-        /* NOR Flash */
-        cap9adk_add_device_nor();
-        /* I2C */
-        at91_add_device_i2c(NULL, 0);
-        /* LCD Controller */
-        at91_add_device_lcdc(&cap9adk_lcdc_data);
-        /* AC97 */
-        at91_add_device_ac97(&cap9adk_ac97_data);
-}
-
-MACHINE_START(AT91CAP9ADK, "Atmel AT91CAP9A-DK")
-        /* Maintainer: Stelian Pop <stelian.pop@leadtechdesign.com> */
-        .timer          = &at91sam926x_timer,
-        .map_io         = at91_map_io,
-        .init_early     = cap9adk_init_early,
-        .init_irq       = at91_init_irq_default,
-        .init_machine   = cap9adk_board_init,
-MACHINE_END
diff --git a/arch/arm/mach-at91/board-cpu9krea.c b/arch/arm/mach-at91/board-cpu9krea.c
index 9ab3d1ea326..989e1c5a9ca 100644
--- a/arch/arm/mach-at91/board-cpu9krea.c
+++ b/arch/arm/mach-at91/board-cpu9krea.c
@@ -43,6 +43,7 @@
 #include <mach/board.h>
 #include <mach/at91sam9_smc.h>
 #include <mach/at91sam9260_matrix.h>
+#include <mach/at91_matrix.h>
 
 #include "sam9_smc.h"
 #include "generic.h"
@@ -238,8 +239,8 @@ static __init void cpu9krea_add_device_nor(void)
 {
         unsigned long csa;
 
-        csa = at91_sys_read(AT91_MATRIX_EBICSA);
-        at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_VDDIOMSEL_3_3V);
+        csa = at91_matrix_read(AT91_MATRIX_EBICSA);
+        at91_matrix_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_VDDIOMSEL_3_3V);
 
         /* configure chip-select 0 (NOR) */
         sam9_smc_configure(0, 0, &cpu9krea_nor_smc_config);
diff --git a/arch/arm/mach-at91/board-cpuat91.c b/arch/arm/mach-at91/board-cpuat91.c
index 368e1427ad9..e094cc81fe2 100644
--- a/arch/arm/mach-at91/board-cpuat91.c
+++ b/arch/arm/mach-at91/board-cpuat91.c
@@ -38,6 +38,7 @@
 
 #include <mach/board.h>
 #include <mach/at91rm9200_mc.h>
+#include <mach/at91_ramc.h>
 #include <mach/cpu.h>
 
 #include "generic.h"
diff --git a/arch/arm/mach-at91/board-dt.c b/arch/arm/mach-at91/board-dt.c
index bb6b434ec0c..583b72472ad 100644
--- a/arch/arm/mach-at91/board-dt.c
+++ b/arch/arm/mach-at91/board-dt.c
@@ -15,7 +15,7 @@
 #include <linux/init.h>
 #include <linux/module.h>
 #include <linux/gpio.h>
-#include <linux/irqdomain.h>
+#include <linux/of.h>
 #include <linux/of_irq.h>
 #include <linux/of_platform.h>
 
@@ -38,12 +38,6 @@ static void __init ek_init_early(void)
 {
         /* Initialize processor: 12.000 MHz crystal */
         at91_initialize(12000000);
-
-        /* DGBU on ttyS0. (Rx & Tx only) */
-        at91_register_uart(0, 0, 0);
-
-        /* set serial console to ttyS0 (ie, DBGU) */
-        at91_set_serial_console(0);
 }
 
 /* det_pin is not connected */
@@ -88,15 +82,17 @@ static void __init ek_add_device_nand(void)
         at91_add_device_nand(&ek_nand_data);
 }
 
-static const struct of_device_id aic_of_match[] __initconst = {
-        { .compatible = "atmel,at91rm9200-aic", },
-        {},
+static const struct of_device_id irq_of_match[] __initconst = {
+
+        { .compatible = "atmel,at91rm9200-aic", .data = at91_aic_of_init },
+        { .compatible = "atmel,at91rm9200-gpio", .data = at91_gpio_of_irq_setup },
+        { .compatible = "atmel,at91sam9x5-gpio", .data = at91_gpio_of_irq_setup },
+        { /*sentinel*/ }
 };
 
 static void __init at91_dt_init_irq(void)
 {
-        irq_domain_generate_simple(aic_of_match, 0xfffff000, 0);
-        at91_init_irq_default();
+        of_irq_init(irq_of_match);
 }
 
 static void __init at91_dt_device_init(void)
@@ -109,6 +105,7 @@ static void __init at91_dt_device_init(void)
 
 static const char *at91_dt_board_compat[] __initdata = {
         "atmel,at91sam9m10g45ek",
+        "atmel,at91sam9x5ek",
         "calao,usb-a9g20",
         NULL
 };
diff --git a/arch/arm/mach-at91/board-eco920.c b/arch/arm/mach-at91/board-eco920.c
index 07ef35b0ec2..f23aabef855 100644
--- a/arch/arm/mach-at91/board-eco920.c
+++ b/arch/arm/mach-at91/board-eco920.c
@@ -26,6 +26,7 @@
 
 #include <mach/board.h>
 #include <mach/at91rm9200_mc.h>
+#include <mach/at91_ramc.h>
 #include <mach/cpu.h>
 
 #include "generic.h"
@@ -110,7 +111,7 @@ static void __init eco920_board_init(void)
         at91_add_device_mmc(0, &eco920_mmc_data);
         platform_device_register(&eco920_flash);
 
-        at91_sys_write(AT91_SMC_CSR(7), AT91_SMC_RWHOLD_(1)
+        at91_ramc_write(0, AT91_SMC_CSR(7),     AT91_SMC_RWHOLD_(1)
                                 | AT91_SMC_RWSETUP_(1)
                                 | AT91_SMC_DBW_8
                                 | AT91_SMC_WSEN
@@ -122,7 +123,7 @@ static void __init eco920_board_init(void)
         at91_set_deglitch(AT91_PIN_PA23, 1);
 
 /* Initialization of the Static Memory Controller for Chip Select 3 */
-        at91_sys_write(AT91_SMC_CSR(3),
+        at91_ramc_write(0, AT91_SMC_CSR(3),
                 AT91_SMC_DBW_16  |      /* 16 bit */
                 AT91_SMC_WSEN    |
                 AT91_SMC_NWS_(5) |      /* wait states */
diff --git a/arch/arm/mach-at91/board-flexibity.c b/arch/arm/mach-at91/board-flexibity.c
index eec02cd57ce..1815152001f 100644
--- a/arch/arm/mach-at91/board-flexibity.c
+++ b/arch/arm/mach-at91/board-flexibity.c
@@ -1,7 +1,7 @@
 /*
  * linux/arch/arm/mach-at91/board-flexibity.c
  *
- *  Copyright (C) 2010 Flexibity
+ *  Copyright (C) 2010-2011 Flexibity
  *  Copyright (C) 2005 SAN People
  *  Copyright (C) 2006 Atmel
  *
@@ -62,6 +62,13 @@ static struct at91_udc_data __initdata flexibity_udc_data = {
         .pullup_pin     = -EINVAL,              /* pull-up driven by UDC */
 };
 
+/* I2C devices */
+static struct i2c_board_info __initdata flexibity_i2c_devices[] = {
+        {
+                I2C_BOARD_INFO("ds1307", 0x68),
+        },
+};
+
 /* SPI devices */
 static struct spi_board_info flexibity_spi_devices[] = {
         {       /* DataFlash chip */
@@ -141,6 +148,9 @@ static void __init flexibity_board_init(void)
         at91_add_device_usbh(&flexibity_usbh_data);
         /* USB Device */
         at91_add_device_udc(&flexibity_udc_data);
+        /* I2C */
+        at91_add_device_i2c(flexibity_i2c_devices,
+                ARRAY_SIZE(flexibity_i2c_devices));
         /* SPI */
         at91_add_device_spi(flexibity_spi_devices,
                 ARRAY_SIZE(flexibity_spi_devices));
diff --git a/arch/arm/mach-at91/board-kb9202.c b/arch/arm/mach-at91/board-kb9202.c
index d75a4a2ad9c..bb991458201 100644
--- a/arch/arm/mach-at91/board-kb9202.c
+++ b/arch/arm/mach-at91/board-kb9202.c
@@ -38,6 +38,7 @@
 #include <mach/board.h>
 #include <mach/cpu.h>
 #include <mach/at91rm9200_mc.h>
+#include <mach/at91_ramc.h>
 
 #include "generic.h"
 
diff --git a/arch/arm/mach-at91/board-picotux200.c b/arch/arm/mach-at91/board-picotux200.c
index ab024fa11d5..59e35dd1486 100644
--- a/arch/arm/mach-at91/board-picotux200.c
+++ b/arch/arm/mach-at91/board-picotux200.c
@@ -39,6 +39,7 @@
 
 #include <mach/board.h>
 #include <mach/at91rm9200_mc.h>
+#include <mach/at91_ramc.h>
 
 #include "generic.h"
 
diff --git a/arch/arm/mach-at91/board-rm9200dk.c b/arch/arm/mach-at91/board-rm9200dk.c
index 782f37946af..9083df04e7e 100644
--- a/arch/arm/mach-at91/board-rm9200dk.c
+++ b/arch/arm/mach-at91/board-rm9200dk.c
@@ -41,6 +41,7 @@
 #include <mach/hardware.h>
 #include <mach/board.h>
 #include <mach/at91rm9200_mc.h>
+#include <mach/at91_ramc.h>
 
 #include "generic.h"
 
diff --git a/arch/arm/mach-at91/board-rm9200ek.c b/arch/arm/mach-at91/board-rm9200ek.c
index ef7c12a9224..11cbaa8946f 100644
--- a/arch/arm/mach-at91/board-rm9200ek.c
+++ b/arch/arm/mach-at91/board-rm9200ek.c
@@ -41,6 +41,7 @@
 #include <mach/hardware.h>
 #include <mach/board.h>
 #include <mach/at91rm9200_mc.h>
+#include <mach/at91_ramc.h>
 
 #include "generic.h"
 
diff --git a/arch/arm/mach-at91/board-sam9m10g45ek.c b/arch/arm/mach-at91/board-sam9m10g45ek.c
index ea0d1b9c2b7..57497e2b887 100644
--- a/arch/arm/mach-at91/board-sam9m10g45ek.c
+++ b/arch/arm/mach-at91/board-sam9m10g45ek.c
@@ -24,11 +24,13 @@
 #include <linux/gpio_keys.h>
 #include <linux/input.h>
 #include <linux/leds.h>
-#include <linux/clk.h>
 #include <linux/atmel-mci.h>
+#include <linux/delay.h>
 
 #include <mach/hardware.h>
 #include <video/atmel_lcdc.h>
+#include <media/soc_camera.h>
+#include <media/atmel-isi.h>
 
 #include <asm/setup.h>
 #include <asm/mach-types.h>
@@ -185,6 +187,71 @@ static void __init ek_add_device_nand(void)
 
 
 /*
+ *  ISI
+ */
+static struct isi_platform_data __initdata isi_data = {
+        .frate                  = ISI_CFG1_FRATE_CAPTURE_ALL,
+        /* to use codec and preview path simultaneously */
+        .full_mode              = 1,
+        .data_width_flags       = ISI_DATAWIDTH_8 | ISI_DATAWIDTH_10,
+        /* ISI_MCK is provided by programmable clock or external clock */
+        .mck_hz                 = 25000000,
+};
+
+
+/*
+ * soc-camera OV2640
+ */
+#if defined(CONFIG_SOC_CAMERA_OV2640) || \
+        defined(CONFIG_SOC_CAMERA_OV2640_MODULE)
+static unsigned long isi_camera_query_bus_param(struct soc_camera_link *link)
+{
+        /* ISI board for ek using default 8-bits connection */
+        return SOCAM_DATAWIDTH_8;
+}
+
+static int i2c_camera_power(struct device *dev, int on)
+{
+        /* enable or disable the camera */
+        pr_debug("%s: %s the camera\n", __func__, on ? "ENABLE" : "DISABLE");
+        at91_set_gpio_output(AT91_PIN_PD13, !on);
+
+        if (!on)
+                goto out;
+
+        /* If enabled, give a reset impulse */
+        at91_set_gpio_output(AT91_PIN_PD12, 0);
+        msleep(20);
+        at91_set_gpio_output(AT91_PIN_PD12, 1);
+        msleep(100);
+
+out:
+        return 0;
+}
+
+static struct i2c_board_info i2c_camera = {
+        I2C_BOARD_INFO("ov2640", 0x30),
+};
+
+static struct soc_camera_link iclink_ov2640 = {
+        .bus_id                 = 0,
+        .board_info             = &i2c_camera,
+        .i2c_adapter_id         = 0,
+        .power                  = i2c_camera_power,
+        .query_bus_param        = isi_camera_query_bus_param,
+};
+
+static struct platform_device isi_ov2640 = {
+        .name   = "soc-camera-pdrv",
+        .id     = 0,
+        .dev    = {
+                .platform_data = &iclink_ov2640,
+        },
+};
+#endif
+
+
+/*
  * LCD Controller
  */
 #if defined(CONFIG_FB_ATMEL) || defined(CONFIG_FB_ATMEL_MODULE)
@@ -377,7 +444,12 @@ static struct gpio_led ek_pwm_led[] = {
 #endif
 };
 
-
+static struct platform_device *devices[] __initdata = {
+#if defined(CONFIG_SOC_CAMERA_OV2640) || \
+        defined(CONFIG_SOC_CAMERA_OV2640_MODULE)
+        &isi_ov2640,
+#endif
+};
 
 static void __init ek_board_init(void)
 {
@@ -399,6 +471,8 @@ static void __init ek_board_init(void)
         ek_add_device_nand();
         /* I2C */
         at91_add_device_i2c(0, NULL, 0);
+        /* ISI, using programmable clock as ISI_MCK */
+        at91_add_device_isi(&isi_data, true);
         /* LCD Controller */
         at91_add_device_lcdc(&ek_lcdc_data);
         /* Touch Screen */
@@ -410,6 +484,8 @@ static void __init ek_board_init(void)
         /* LEDs */
         at91_gpio_leds(ek_leds, ARRAY_SIZE(ek_leds));
         at91_pwm_leds(ek_pwm_led, ARRAY_SIZE(ek_pwm_led));
+        /* Other platform devices */
+        platform_add_devices(devices, ARRAY_SIZE(devices));
 }
 
 MACHINE_START(AT91SAM9M10G45EK, "Atmel AT91SAM9M10G45-EK")
diff --git a/arch/arm/mach-at91/board-snapper9260.c b/arch/arm/mach-at91/board-snapper9260.c
index 4770db08e5a..3c2e3fcc310 100644
--- a/arch/arm/mach-at91/board-snapper9260.c
+++ b/arch/arm/mach-at91/board-snapper9260.c
@@ -145,11 +145,11 @@ static struct i2c_board_info __initdata snapper9260_i2c_devices[] = {
                 /* Audio codec */
                 I2C_BOARD_INFO("tlv320aic23", 0x1a),
         },
-        {
+};
+
+static struct i2c_board_info __initdata snapper9260_i2c_isl1208 = {
                 /* RTC */
                 I2C_BOARD_INFO("isl1208", 0x6f),
-                .irq = gpio_to_irq(AT91_PIN_PA31),
-        },
 };
 
 static void __init snapper9260_add_device_nand(void)
@@ -163,6 +163,10 @@ static void __init snapper9260_board_init(void)
 {
         at91_add_device_i2c(snapper9260_i2c_devices,
                             ARRAY_SIZE(snapper9260_i2c_devices));
+
+        snapper9260_i2c_isl1208.irq = gpio_to_irq(AT91_PIN_PA31);
+        i2c_register_board_info(0, &snapper9260_i2c_isl1208, 1);
+
         at91_add_device_serial();
         at91_add_device_usbh(&snapper9260_usbh_data);
         at91_add_device_udc(&snapper9260_udc_data);
diff --git a/arch/arm/mach-at91/board-yl-9200.c b/arch/arm/mach-at91/board-yl-9200.c
index bbd553e1cd9..52f460768f7 100644
--- a/arch/arm/mach-at91/board-yl-9200.c
+++ b/arch/arm/mach-at91/board-yl-9200.c
@@ -45,6 +45,7 @@
 #include <mach/hardware.h>
 #include <mach/board.h>
 #include <mach/at91rm9200_mc.h>
+#include <mach/at91_ramc.h>
 #include <mach/cpu.h>
 
 #include "generic.h"
@@ -393,7 +394,7 @@ static void yl9200_init_video(void)
         at91_set_A_periph(AT91_PIN_PC6, 0);
 
         /* Initialization of the Static Memory Controller for Chip Select 2 */
-        at91_sys_write(AT91_SMC_CSR(2), AT91_SMC_DBW_16         /* 16 bit */
+        at91_ramc_write(0, AT91_SMC_CSR(2), AT91_SMC_DBW_16             /* 16 bit */
                         | AT91_SMC_WSEN | AT91_SMC_NWS_(0x4)    /* wait states */
                         | AT91_SMC_TDF_(0x100)                  /* float time */
         );
diff --git a/arch/arm/mach-at91/clock.c b/arch/arm/mach-at91/clock.c
index 61873f3aa92..be51ca7f694 100644
--- a/arch/arm/mach-at91/clock.c
+++ b/arch/arm/mach-at91/clock.c
@@ -28,9 +28,12 @@
 #include <mach/at91_pmc.h>
 #include <mach/cpu.h>
 
+#include <asm/proc-fns.h>
+
 #include "clock.h"
 #include "generic.h"
 
+void __iomem *at91_pmc_base;
 
 /*
  * There's a lot more which can be done with clocks, including cpufreq
@@ -47,26 +50,38 @@
 /*
  * Chips have some kind of clocks : group them by functionality
  */
-#define cpu_has_utmi()          (  cpu_is_at91cap9() \
-                                || cpu_is_at91sam9rl() \
-                                || cpu_is_at91sam9g45())
+#define cpu_has_utmi()          (  cpu_is_at91sam9rl() \
+                                || cpu_is_at91sam9g45() \
+                                || cpu_is_at91sam9x5())
 
 #define cpu_has_800M_plla()     (  cpu_is_at91sam9g20() \
-                                || cpu_is_at91sam9g45())
+                                || cpu_is_at91sam9g45() \
+                                || cpu_is_at91sam9x5())
 
 #define cpu_has_300M_plla()     (cpu_is_at91sam9g10())
 
 #define cpu_has_pllb()          (!(cpu_is_at91sam9rl() \
-                                || cpu_is_at91sam9g45()))
+                                || cpu_is_at91sam9g45() \
+                                || cpu_is_at91sam9x5()))
 
-#define cpu_has_upll()          (cpu_is_at91sam9g45())
+#define cpu_has_upll()          (cpu_is_at91sam9g45() \
+                                || cpu_is_at91sam9x5())
 
 /* USB host HS & FS */
 #define cpu_has_uhp()           (!cpu_is_at91sam9rl())
 
 /* USB device FS only */
 #define cpu_has_udpfs()         (!(cpu_is_at91sam9rl() \
-                                || cpu_is_at91sam9g45()))
+                                || cpu_is_at91sam9g45() \
+                                || cpu_is_at91sam9x5()))
+
+#define cpu_has_plladiv2()      (cpu_is_at91sam9g45() \
+                                || cpu_is_at91sam9x5())
+
+#define cpu_has_mdiv3()         (cpu_is_at91sam9g45() \
+                                || cpu_is_at91sam9x5())
+
+#define cpu_has_alt_prescaler() (cpu_is_at91sam9x5())
 
 static LIST_HEAD(clocks);
 static DEFINE_SPINLOCK(clk_lock);
@@ -111,11 +126,11 @@ static void pllb_mode(struct clk *clk, int is_on)
                 value = 0;
 
         // REVISIT: Add work-around for AT91RM9200 Errata #26 ?
-        at91_sys_write(AT91_CKGR_PLLBR, value);
+        at91_pmc_write(AT91_CKGR_PLLBR, value);
 
         do {
                 cpu_relax();
-        } while ((at91_sys_read(AT91_PMC_SR) & AT91_PMC_LOCKB) != is_on);
+        } while ((at91_pmc_read(AT91_PMC_SR) & AT91_PMC_LOCKB) != is_on);
 }
 
 static struct clk pllb = {
@@ -130,31 +145,24 @@ static struct clk pllb = {
 static void pmc_sys_mode(struct clk *clk, int is_on)
 {
         if (is_on)
-                at91_sys_write(AT91_PMC_SCER, clk->pmc_mask);
+                at91_pmc_write(AT91_PMC_SCER, clk->pmc_mask);
         else
-                at91_sys_write(AT91_PMC_SCDR, clk->pmc_mask);
+                at91_pmc_write(AT91_PMC_SCDR, clk->pmc_mask);
 }
 
 static void pmc_uckr_mode(struct clk *clk, int is_on)
 {
-        unsigned int uckr = at91_sys_read(AT91_CKGR_UCKR);
-
-        if (cpu_is_at91sam9g45()) {
-                if (is_on)
-                        uckr |= AT91_PMC_BIASEN;
-                else
-                        uckr &= ~AT91_PMC_BIASEN;
-        }
+        unsigned int uckr = at91_pmc_read(AT91_CKGR_UCKR);
 
         if (is_on) {
                 is_on = AT91_PMC_LOCKU;
-                at91_sys_write(AT91_CKGR_UCKR, uckr | clk->pmc_mask);
+                at91_pmc_write(AT91_CKGR_UCKR, uckr | clk->pmc_mask);
         } else
-                at91_sys_write(AT91_CKGR_UCKR, uckr & ~(clk->pmc_mask));
+                at91_pmc_write(AT91_CKGR_UCKR, uckr & ~(clk->pmc_mask));
 
         do {
                 cpu_relax();
-        } while ((at91_sys_read(AT91_PMC_SR) & AT91_PMC_LOCKU) != is_on);
+        } while ((at91_pmc_read(AT91_PMC_SR) & AT91_PMC_LOCKU) != is_on);
 }
 
 /* USB function clocks (PLLB must be 48 MHz) */
@@ -190,9 +198,9 @@ struct clk mck = {
 static void pmc_periph_mode(struct clk *clk, int is_on)
 {
         if (is_on)
-                at91_sys_write(AT91_PMC_PCER, clk->pmc_mask);
+                at91_pmc_write(AT91_PMC_PCER, clk->pmc_mask);
         else
-                at91_sys_write(AT91_PMC_PCDR, clk->pmc_mask);
+                at91_pmc_write(AT91_PMC_PCDR, clk->pmc_mask);
 }
 
 static struct clk __init *at91_css_to_clk(unsigned long css)
@@ -210,11 +218,24 @@ static struct clk __init *at91_css_to_clk(unsigned long css)
                                 return &utmi_clk;
                         else if (cpu_has_pllb())
                                 return &pllb;
+                        break;
+                /* alternate PMC: can use master clock */
+                case AT91_PMC_CSS_MASTER:
+                        return &mck;
         }
 
         return NULL;
 }
 
+static int pmc_prescaler_divider(u32 reg)
+{
+        if (cpu_has_alt_prescaler()) {
+                return 1 << ((reg & AT91_PMC_ALT_PRES) >> PMC_ALT_PRES_OFFSET);
+        } else {
+                return 1 << ((reg & AT91_PMC_PRES) >> PMC_PRES_OFFSET);
+        }
+}
+
 static void __clk_enable(struct clk *clk)
 {
         if (clk->parent)
@@ -316,12 +337,22 @@ int clk_set_rate(struct clk *clk, unsigned long rate)
 {
         unsigned long   flags;
         unsigned        prescale;
+        unsigned long   prescale_offset, css_mask;
         unsigned long   actual;
 
         if (!clk_is_programmable(clk))
                 return -EINVAL;
         if (clk->users)
                 return -EBUSY;
+
+        if (cpu_has_alt_prescaler()) {
+                prescale_offset = PMC_ALT_PRES_OFFSET;
+                css_mask = AT91_PMC_ALT_PCKR_CSS;
+        } else {
+                prescale_offset = PMC_PRES_OFFSET;
+                css_mask = AT91_PMC_CSS;
+        }
+
         spin_lock_irqsave(&clk_lock, flags);
 
         actual = clk->parent->rate_hz;
@@ -329,10 +360,10 @@ int clk_set_rate(struct clk *clk, unsigned long rate)
                 if (actual && actual <= rate) {
                         u32     pckr;
 
-                        pckr = at91_sys_read(AT91_PMC_PCKR(clk->id));
-                        pckr &= AT91_PMC_CSS;   /* clock selection */
-                        pckr |= prescale << 2;
-                        at91_sys_write(AT91_PMC_PCKR(clk->id), pckr);
+                        pckr = at91_pmc_read(AT91_PMC_PCKR(clk->id));
+                        pckr &= css_mask;       /* keep clock selection */
+                        pckr |= prescale << prescale_offset;
+                        at91_pmc_write(AT91_PMC_PCKR(clk->id), pckr);
                         clk->rate_hz = actual;
                         break;
                 }
@@ -366,7 +397,7 @@ int clk_set_parent(struct clk *clk, struct clk *parent)
 
         clk->rate_hz = parent->rate_hz;
         clk->parent = parent;
-        at91_sys_write(AT91_PMC_PCKR(clk->id), parent->id);
+        at91_pmc_write(AT91_PMC_PCKR(clk->id), parent->id);
 
         spin_unlock_irqrestore(&clk_lock, flags);
         return 0;
@@ -378,11 +409,17 @@ static void __init init_programmable_clock(struct clk *clk)
 {
         struct clk      *parent;
         u32             pckr;
+        unsigned int    css_mask;
+
+        if (cpu_has_alt_prescaler())
+                css_mask = AT91_PMC_ALT_PCKR_CSS;
+        else
+                css_mask = AT91_PMC_CSS;
 
-        pckr = at91_sys_read(AT91_PMC_PCKR(clk->id));
-        parent = at91_css_to_clk(pckr & AT91_PMC_CSS);
+        pckr = at91_pmc_read(AT91_PMC_PCKR(clk->id));
+        parent = at91_css_to_clk(pckr & css_mask);
         clk->parent = parent;
-        clk->rate_hz = parent->rate_hz / (1 << ((pckr & AT91_PMC_PRES) >> 2));
+        clk->rate_hz = parent->rate_hz / pmc_prescaler_divider(pckr);
 }
 
 #endif  /* CONFIG_AT91_PROGRAMMABLE_CLOCKS */
@@ -396,19 +433,24 @@ static int at91_clk_show(struct seq_file *s, void *unused)
         u32             scsr, pcsr, uckr = 0, sr;
         struct clk      *clk;
 
-        seq_printf(s, "SCSR = %8x\n", scsr = at91_sys_read(AT91_PMC_SCSR));
-        seq_printf(s, "PCSR = %8x\n", pcsr = at91_sys_read(AT91_PMC_PCSR));
-        seq_printf(s, "MOR  = %8x\n", at91_sys_read(AT91_CKGR_MOR));
-        seq_printf(s, "MCFR = %8x\n", at91_sys_read(AT91_CKGR_MCFR));
-        seq_printf(s, "PLLA = %8x\n", at91_sys_read(AT91_CKGR_PLLAR));
+        scsr = at91_pmc_read(AT91_PMC_SCSR);
+        pcsr = at91_pmc_read(AT91_PMC_PCSR);
+        sr = at91_pmc_read(AT91_PMC_SR);
+        seq_printf(s, "SCSR = %8x\n", scsr);
+        seq_printf(s, "PCSR = %8x\n", pcsr);
+        seq_printf(s, "MOR  = %8x\n", at91_pmc_read(AT91_CKGR_MOR));
+        seq_printf(s, "MCFR = %8x\n", at91_pmc_read(AT91_CKGR_MCFR));
+        seq_printf(s, "PLLA = %8x\n", at91_pmc_read(AT91_CKGR_PLLAR));
         if (cpu_has_pllb())
-                seq_printf(s, "PLLB = %8x\n", at91_sys_read(AT91_CKGR_PLLBR));
-        if (cpu_has_utmi())
-                seq_printf(s, "UCKR = %8x\n", uckr = at91_sys_read(AT91_CKGR_UCKR));
-        seq_printf(s, "MCKR = %8x\n", at91_sys_read(AT91_PMC_MCKR));
+                seq_printf(s, "PLLB = %8x\n", at91_pmc_read(AT91_CKGR_PLLBR));
+        if (cpu_has_utmi()) {
+                uckr = at91_pmc_read(AT91_CKGR_UCKR);
+                seq_printf(s, "UCKR = %8x\n", uckr);
+        }
+        seq_printf(s, "MCKR = %8x\n", at91_pmc_read(AT91_PMC_MCKR));
         if (cpu_has_upll())
-                seq_printf(s, "USB  = %8x\n", at91_sys_read(AT91_PMC_USB));
-        seq_printf(s, "SR   = %8x\n", sr = at91_sys_read(AT91_PMC_SR));
+                seq_printf(s, "USB  = %8x\n", at91_pmc_read(AT91_PMC_USB));
+        seq_printf(s, "SR   = %8x\n", sr);
 
         seq_printf(s, "\n");
 
@@ -596,16 +638,14 @@ static void __init at91_pllb_usbfs_clock_init(unsigned long main_clock)
         if (cpu_is_at91rm9200()) {
                 uhpck.pmc_mask = AT91RM9200_PMC_UHP;
                 udpck.pmc_mask = AT91RM9200_PMC_UDP;
-                at91_sys_write(AT91_PMC_SCER, AT91RM9200_PMC_MCKUDP);
+                at91_pmc_write(AT91_PMC_SCER, AT91RM9200_PMC_MCKUDP);
         } else if (cpu_is_at91sam9260() || cpu_is_at91sam9261() ||
                    cpu_is_at91sam9263() || cpu_is_at91sam9g20() ||
                    cpu_is_at91sam9g10()) {
                 uhpck.pmc_mask = AT91SAM926x_PMC_UHP;
                 udpck.pmc_mask = AT91SAM926x_PMC_UDP;
-        } else if (cpu_is_at91cap9()) {
-                uhpck.pmc_mask = AT91CAP9_PMC_UHP;
         }
-        at91_sys_write(AT91_CKGR_PLLBR, 0);
+        at91_pmc_write(AT91_CKGR_PLLBR, 0);
 
         udpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init);
         uhpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init);
@@ -622,13 +662,13 @@ static void __init at91_upll_usbfs_clock_init(unsigned long main_clock)
         /* Setup divider by 10 to reach 48 MHz */
         usbr |= ((10 - 1) << 8) & AT91_PMC_OHCIUSBDIV;
 
-        at91_sys_write(AT91_PMC_USB, usbr);
+        at91_pmc_write(AT91_PMC_USB, usbr);
 
         /* Now set uhpck values */
         uhpck.parent = &utmi_clk;
         uhpck.pmc_mask = AT91SAM926x_PMC_UHP;
         uhpck.rate_hz = utmi_clk.rate_hz;
-        uhpck.rate_hz /= 1 + ((at91_sys_read(AT91_PMC_USB) & AT91_PMC_OHCIUSBDIV) >> 8);
+        uhpck.rate_hz /= 1 + ((at91_pmc_read(AT91_PMC_USB) & AT91_PMC_OHCIUSBDIV) >> 8);
 }
 
 int __init at91_clock_init(unsigned long main_clock)
@@ -637,6 +677,10 @@ int __init at91_clock_init(unsigned long main_clock)
         int i;
         int pll_overclock = false;
 
+        at91_pmc_base = ioremap(AT91_PMC, 256);
+        if (!at91_pmc_base)
+                panic("Impossible to ioremap AT91_PMC 0x%x\n", AT91_PMC);
+
         /*
          * When the bootloader initialized the main oscillator correctly,
          * there's no problem using the cycle counter.  But if it didn't,
@@ -645,14 +689,14 @@ int __init at91_clock_init(unsigned long main_clock)
          */
         if (!main_clock) {
                 do {
-                        tmp = at91_sys_read(AT91_CKGR_MCFR);
+                        tmp = at91_pmc_read(AT91_CKGR_MCFR);
                 } while (!(tmp & AT91_PMC_MAINRDY));
                 main_clock = (tmp & AT91_PMC_MAINF) * (AT91_SLOW_CLOCK / 16);
         }
         main_clk.rate_hz = main_clock;
 
         /* report if PLLA is more than mildly overclocked */
-        plla.rate_hz = at91_pll_rate(&plla, main_clock, at91_sys_read(AT91_CKGR_PLLAR));
+        plla.rate_hz = at91_pll_rate(&plla, main_clock, at91_pmc_read(AT91_CKGR_PLLAR));
         if (cpu_has_300M_plla()) {
                 if (plla.rate_hz > 300000000)
                         pll_overclock = true;
@@ -666,8 +710,8 @@ int __init at91_clock_init(unsigned long main_clock)
         if (pll_overclock)
                 pr_info("Clocks: PLLA overclocked, %ld MHz\n", plla.rate_hz / 1000000);
 
-        if (cpu_is_at91sam9g45()) {
-                mckr = at91_sys_read(AT91_PMC_MCKR);
+        if (cpu_has_plladiv2()) {
+                mckr = at91_pmc_read(AT91_PMC_MCKR);
                 plla.rate_hz /= (1 << ((mckr & AT91_PMC_PLLADIV2) >> 12));      /* plla divisor by 2 */
         }
 
@@ -688,6 +732,10 @@ int __init at91_clock_init(unsigned long main_clock)
                  * (obtain the USB High Speed 480 MHz when input is 12 MHz)
                  */
                 utmi_clk.rate_hz = 40 * utmi_clk.parent->rate_hz;
+
+                /* UTMI bias and PLL are managed at the same time */
+                if (cpu_has_upll())
+                        utmi_clk.pmc_mask |= AT91_PMC_BIASEN;
         }
 
         /*
@@ -703,10 +751,10 @@ int __init at91_clock_init(unsigned long main_clock)
          * MCK and CPU derive from one of those primary clocks.
          * For now, assume this parentage won't change.
          */
-        mckr = at91_sys_read(AT91_PMC_MCKR);
+        mckr = at91_pmc_read(AT91_PMC_MCKR);
         mck.parent = at91_css_to_clk(mckr & AT91_PMC_CSS);
         freq = mck.parent->rate_hz;
-        freq /= (1 << ((mckr & AT91_PMC_PRES) >> 2));                           /* prescale */
+        freq /= pmc_prescaler_divider(mckr);                                    /* prescale */
         if (cpu_is_at91rm9200()) {
                 mck.rate_hz = freq / (1 + ((mckr & AT91_PMC_MDIV) >> 8));       /* mdiv */
         } else if (cpu_is_at91sam9g20()) {
@@ -714,13 +762,19 @@ int __init at91_clock_init(unsigned long main_clock)
                         freq / ((mckr & AT91_PMC_MDIV) >> 7) : freq;    /* mdiv ; (x >> 7) = ((x >> 8) * 2) */
                 if (mckr & AT91_PMC_PDIV)
                         freq /= 2;              /* processor clock division */
-        } else if (cpu_is_at91sam9g45()) {
+        } else if (cpu_has_mdiv3()) {
                 mck.rate_hz = (mckr & AT91_PMC_MDIV) == AT91SAM9_PMC_MDIV_3 ?
                         freq / 3 : freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8)); /* mdiv */
         } else {
                 mck.rate_hz = freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8));              /* mdiv */
         }
 
+        if (cpu_has_alt_prescaler()) {
+                /* Programmable clocks can use MCK */
+                mck.type |= CLK_TYPE_PRIMARY;
+                mck.id = 4;
+        }
+
         /* Register the PMC's standard clocks */
         for (i = 0; i < ARRAY_SIZE(standard_pmc_clocks); i++)
                 at91_clk_add(standard_pmc_clocks[i]);
@@ -770,9 +824,15 @@ static int __init at91_clock_reset(void)
                 pr_debug("Clocks: disable unused %s\n", clk->name);
         }
 
-        at91_sys_write(AT91_PMC_PCDR, pcdr);
-        at91_sys_write(AT91_PMC_SCDR, scdr);
+        at91_pmc_write(AT91_PMC_PCDR, pcdr);
+        at91_pmc_write(AT91_PMC_SCDR, scdr);
 
         return 0;
 }
 late_initcall(at91_clock_reset);
+
+void at91sam9_idle(void)
+{
+        at91_pmc_write(AT91_PMC_SCDR, AT91_PMC_PCK);
+        cpu_do_idle();
+}
diff --git a/arch/arm/mach-at91/cpuidle.c b/arch/arm/mach-at91/cpuidle.c
index a851e6c9842..555d956b3a5 100644
--- a/arch/arm/mach-at91/cpuidle.c
+++ b/arch/arm/mach-at91/cpuidle.c
@@ -39,20 +39,15 @@ static int at91_enter_idle(struct cpuidle_device *dev,
 {
         struct timeval before, after;
         int idle_time;
-        u32 saved_lpr;
 
         local_irq_disable();
         do_gettimeofday(&before);
         if (index == 0)
                 /* Wait for interrupt state */
                 cpu_do_idle();
-        else if (index == 1) {
-                asm("b 1f; .align 5; 1:");
-                asm("mcr p15, 0, r0, c7, c10, 4");      /* drain write buffer */
-                saved_lpr = sdram_selfrefresh_enable();
-                cpu_do_idle();
-                sdram_selfrefresh_disable(saved_lpr);
-        }
+        else if (index == 1)
+                at91_standby();
+
         do_gettimeofday(&after);
         local_irq_enable();
         idle_time = (after.tv_sec - before.tv_sec) * USEC_PER_SEC +
diff --git a/arch/arm/mach-at91/generic.h b/arch/arm/mach-at91/generic.h
index 594133451c0..459f01a4a54 100644
--- a/arch/arm/mach-at91/generic.h
+++ b/arch/arm/mach-at91/generic.h
@@ -9,6 +9,7 @@
  */
 
 #include <linux/clkdev.h>
+#include <linux/of.h>
 
  /* Map io */
 extern void __init at91_map_io(void);
@@ -25,9 +26,13 @@ extern void __init at91_init_irq_default(void);
 extern void __init at91_init_interrupts(unsigned int priority[]);
 extern void __init at91x40_init_interrupts(unsigned int priority[]);
 extern void __init at91_aic_init(unsigned int priority[]);
+extern int  __init at91_aic_of_init(struct device_node *node,
+                                    struct device_node *parent);
+
 
  /* Timer */
 struct sys_timer;
+extern void at91rm9200_ioremap_st(u32 addr);
 extern struct sys_timer at91rm9200_timer;
 extern void at91sam926x_ioremap_pit(u32 addr);
 extern struct sys_timer at91sam926x_timer;
@@ -45,7 +50,6 @@ extern void __init at91sam9261_set_console_clock(int id);
 extern void __init at91sam9263_set_console_clock(int id);
 extern void __init at91sam9rl_set_console_clock(int id);
 extern void __init at91sam9g45_set_console_clock(int id);
-extern void __init at91cap9_set_console_clock(int id);
 #ifdef CONFIG_AT91_PMC_UNIT
 extern int __init at91_clock_init(unsigned long main_clock);
 #else
@@ -57,6 +61,9 @@ struct device;
 extern void at91_irq_suspend(void);
 extern void at91_irq_resume(void);
 
+/* idle */
+extern void at91sam9_idle(void);
+
 /* reset */
 extern void at91_ioremap_rstc(u32 base_addr);
 extern void at91sam9_alt_restart(char, const char *);
@@ -65,6 +72,12 @@ extern void at91sam9g45_restart(char, const char *);
 /* shutdown */
 extern void at91_ioremap_shdwc(u32 base_addr);
 
+/* Matrix */
+extern void at91_ioremap_matrix(u32 base_addr);
+
+/* Ram Controler */
+extern void at91_ioremap_ramc(int id, u32 addr, u32 size);
+
  /* GPIO */
 #define AT91RM9200_PQFP         3       /* AT91RM9200 PQFP package has 3 banks */
 #define AT91RM9200_BGA          4       /* AT91RM9200 BGA package has 4 banks */
@@ -75,5 +88,7 @@ struct at91_gpio_bank {
 };
 extern void __init at91_gpio_init(struct at91_gpio_bank *, int nr_banks);
 extern void __init at91_gpio_irq_setup(void);
+extern int  __init at91_gpio_of_irq_setup(struct device_node *node,
+                                          struct device_node *parent);
 
 extern int at91_extern_irq;
diff --git a/arch/arm/mach-at91/gpio.c b/arch/arm/mach-at91/gpio.c
index 74d6783eeab..325837a264c 100644
--- a/arch/arm/mach-at91/gpio.c
+++ b/arch/arm/mach-at91/gpio.c
@@ -11,6 +11,7 @@
 
 #include <linux/clk.h>
 #include <linux/errno.h>
+#include <linux/device.h>
 #include <linux/gpio.h>
 #include <linux/interrupt.h>
 #include <linux/irq.h>
@@ -20,6 +21,10 @@
 #include <linux/list.h>
 #include <linux/module.h>
 #include <linux/io.h>
+#include <linux/irqdomain.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <linux/of_gpio.h>
 
 #include <mach/hardware.h>
 #include <mach/at91_pio.h>
@@ -29,9 +34,12 @@
 struct at91_gpio_chip {
         struct gpio_chip        chip;
         struct at91_gpio_chip   *next;          /* Bank sharing same clock */
-        int                     id;             /* ID of register bank */
-        void __iomem            *regbase;       /* Base of register bank */
+        int                     pioc_hwirq;     /* PIO bank interrupt identifier on AIC */
+        int                     pioc_virq;      /* PIO bank Linux virtual interrupt */
+        int                     pioc_idx;       /* PIO bank index */
+        void __iomem            *regbase;       /* PIO bank virtual address */
         struct clk              *clock;         /* associated clock */
+        struct irq_domain       *domain;        /* associated irq domain */
 };
 
 #define to_at91_gpio_chip(c) container_of(c, struct at91_gpio_chip, chip)
@@ -43,8 +51,9 @@ static int at91_gpiolib_direction_output(struct gpio_chip *chip,
                                          unsigned offset, int val);
 static int at91_gpiolib_direction_input(struct gpio_chip *chip,
                                         unsigned offset);
+static int at91_gpiolib_to_irq(struct gpio_chip *chip, unsigned offset);
 
-#define AT91_GPIO_CHIP(name, base_gpio, nr_gpio)                        \
+#define AT91_GPIO_CHIP(name, nr_gpio)                                   \
         {                                                               \
                 .chip = {                                               \
                         .label            = name,                       \
@@ -53,20 +62,28 @@ static int at91_gpiolib_direction_input(struct gpio_chip *chip,
                         .get              = at91_gpiolib_get,           \
                         .set              = at91_gpiolib_set,           \
                         .dbg_show         = at91_gpiolib_dbg_show,      \
-                        .base             = base_gpio,                  \
+                        .to_irq           = at91_gpiolib_to_irq,        \
                         .ngpio            = nr_gpio,                    \
                 },                                                      \
         }
 
 static struct at91_gpio_chip gpio_chip[] = {
-        AT91_GPIO_CHIP("pioA", 0x00, 32),
-        AT91_GPIO_CHIP("pioB", 0x20, 32),
-        AT91_GPIO_CHIP("pioC", 0x40, 32),
-        AT91_GPIO_CHIP("pioD", 0x60, 32),
-        AT91_GPIO_CHIP("pioE", 0x80, 32),
+        AT91_GPIO_CHIP("pioA", 32),
+        AT91_GPIO_CHIP("pioB", 32),
+        AT91_GPIO_CHIP("pioC", 32),
+        AT91_GPIO_CHIP("pioD", 32),
+        AT91_GPIO_CHIP("pioE", 32),
 };
 
 static int gpio_banks;
+static unsigned long at91_gpio_caps;
+
+/* All PIO controllers support PIO3 features */
+#define AT91_GPIO_CAP_PIO3      (1 <<  0)
+
+#define has_pio3()      (at91_gpio_caps & AT91_GPIO_CAP_PIO3)
+
+/*--------------------------------------------------------------------------*/
 
 static inline void __iomem *pin_to_controller(unsigned pin)
 {
@@ -83,6 +100,25 @@ static inline unsigned pin_to_mask(unsigned pin)
 }
 
 
+static char peripheral_function(void __iomem *pio, unsigned mask)
+{
+        char    ret = 'X';
+        u8      select;
+
+        if (pio) {
+                if (has_pio3()) {
+                        select = !!(__raw_readl(pio + PIO_ABCDSR1) & mask);
+                        select |= (!!(__raw_readl(pio + PIO_ABCDSR2) & mask) << 1);
+                        ret = 'A' + select;
+                } else {
+                        ret = __raw_readl(pio + PIO_ABSR) & mask ?
+                                                        'B' : 'A';
+                }
+        }
+
+        return ret;
+}
+
 /*--------------------------------------------------------------------------*/
 
 /* Not all hardware capabilities are exposed through these calls; they
@@ -130,7 +166,14 @@ int __init_or_module at91_set_A_periph(unsigned pin, int use_pullup)
 
         __raw_writel(mask, pio + PIO_IDR);
         __raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR));
-        __raw_writel(mask, pio + PIO_ASR);
+        if (has_pio3()) {
+                __raw_writel(__raw_readl(pio + PIO_ABCDSR1) & ~mask,
+                                                        pio + PIO_ABCDSR1);
+                __raw_writel(__raw_readl(pio + PIO_ABCDSR2) & ~mask,
+                                                        pio + PIO_ABCDSR2);
+        } else {
+                __raw_writel(mask, pio + PIO_ASR);
+        }
         __raw_writel(mask, pio + PIO_PDR);
         return 0;
 }
@@ -150,7 +193,14 @@ int __init_or_module at91_set_B_periph(unsigned pin, int use_pullup)
 
         __raw_writel(mask, pio + PIO_IDR);
         __raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR));
-        __raw_writel(mask, pio + PIO_BSR);
+        if (has_pio3()) {
+                __raw_writel(__raw_readl(pio + PIO_ABCDSR1) | mask,
+                                                        pio + PIO_ABCDSR1);
+                __raw_writel(__raw_readl(pio + PIO_ABCDSR2) & ~mask,
+                                                        pio + PIO_ABCDSR2);
+        } else {
+                __raw_writel(mask, pio + PIO_BSR);
+        }
         __raw_writel(mask, pio + PIO_PDR);
         return 0;
 }
@@ -158,8 +208,50 @@ EXPORT_SYMBOL(at91_set_B_periph);
 
 
 /*
- * mux the pin to the gpio controller (instead of "A" or "B" peripheral), and
- * configure it for an input.
+ * mux the pin to the "C" internal peripheral role.
+ */
+int __init_or_module at91_set_C_periph(unsigned pin, int use_pullup)
+{
+        void __iomem    *pio = pin_to_controller(pin);
+        unsigned        mask = pin_to_mask(pin);
+
+        if (!pio || !has_pio3())
+                return -EINVAL;
+
+        __raw_writel(mask, pio + PIO_IDR);
+        __raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR));
+        __raw_writel(__raw_readl(pio + PIO_ABCDSR1) & ~mask, pio + PIO_ABCDSR1);
+        __raw_writel(__raw_readl(pio + PIO_ABCDSR2) | mask, pio + PIO_ABCDSR2);
+        __raw_writel(mask, pio + PIO_PDR);
+        return 0;
+}
+EXPORT_SYMBOL(at91_set_C_periph);
+
+
+/*
+ * mux the pin to the "D" internal peripheral role.
+ */
+int __init_or_module at91_set_D_periph(unsigned pin, int use_pullup)
+{
+        void __iomem    *pio = pin_to_controller(pin);
+        unsigned        mask = pin_to_mask(pin);
+
+        if (!pio || !has_pio3())
+                return -EINVAL;
+
+        __raw_writel(mask, pio + PIO_IDR);
+        __raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR));
+        __raw_writel(__raw_readl(pio + PIO_ABCDSR1) | mask, pio + PIO_ABCDSR1);
+        __raw_writel(__raw_readl(pio + PIO_ABCDSR2) | mask, pio + PIO_ABCDSR2);
+        __raw_writel(mask, pio + PIO_PDR);
+        return 0;
+}
+EXPORT_SYMBOL(at91_set_D_periph);
+
+
+/*
+ * mux the pin to the gpio controller (instead of "A", "B", "C"
+ * or "D" peripheral), and configure it for an input.
  */
 int __init_or_module at91_set_gpio_input(unsigned pin, int use_pullup)
 {
@@ -179,8 +271,8 @@ EXPORT_SYMBOL(at91_set_gpio_input);
 
 
 /*
- * mux the pin to the gpio controller (instead of "A" or "B" peripheral),
- * and configure it for an output.
+ * mux the pin to the gpio controller (instead of "A", "B", "C"
+ * or "D" peripheral), and configure it for an output.
  */
 int __init_or_module at91_set_gpio_output(unsigned pin, int value)
 {
@@ -210,12 +302,37 @@ int __init_or_module at91_set_deglitch(unsigned pin, int is_on)
 
         if (!pio)
                 return -EINVAL;
+
+        if (has_pio3() && is_on)
+                __raw_writel(mask, pio + PIO_IFSCDR);
         __raw_writel(mask, pio + (is_on ? PIO_IFER : PIO_IFDR));
         return 0;
 }
 EXPORT_SYMBOL(at91_set_deglitch);
 
 /*
+ * enable/disable the debounce filter;
+ */
+int __init_or_module at91_set_debounce(unsigned pin, int is_on, int div)
+{
+        void __iomem    *pio = pin_to_controller(pin);
+        unsigned        mask = pin_to_mask(pin);
+
+        if (!pio || !has_pio3())
+                return -EINVAL;
+
+        if (is_on) {
+                __raw_writel(mask, pio + PIO_IFSCER);
+                __raw_writel(div & PIO_SCDR_DIV, pio + PIO_SCDR);
+                __raw_writel(mask, pio + PIO_IFER);
+        } else {
+                __raw_writel(mask, pio + PIO_IFDR);
+        }
+        return 0;
+}
+EXPORT_SYMBOL(at91_set_debounce);
+
+/*
  * enable/disable the multi-driver; This is only valid for output and
  * allows the output pin to run as an open collector output.
  */
@@ -233,6 +350,41 @@ int __init_or_module at91_set_multi_drive(unsigned pin, int is_on)
 EXPORT_SYMBOL(at91_set_multi_drive);
 
 /*
+ * enable/disable the pull-down.
+ * If pull-up already enabled while calling the function, we disable it.
+ */
+int __init_or_module at91_set_pulldown(unsigned pin, int is_on)
+{
+        void __iomem    *pio = pin_to_controller(pin);
+        unsigned        mask = pin_to_mask(pin);
+
+        if (!pio || !has_pio3())
+                return -EINVAL;
+
+        /* Disable pull-up anyway */
+        __raw_writel(mask, pio + PIO_PUDR);
+        __raw_writel(mask, pio + (is_on ? PIO_PPDER : PIO_PPDDR));
+        return 0;
+}
+EXPORT_SYMBOL(at91_set_pulldown);
+
+/*
+ * disable Schmitt trigger
+ */
+int __init_or_module at91_disable_schmitt_trig(unsigned pin)
+{
+        void __iomem    *pio = pin_to_controller(pin);
+        unsigned        mask = pin_to_mask(pin);
+
+        if (!pio || !has_pio3())
+                return -EINVAL;
+
+        __raw_writel(__raw_readl(pio + PIO_SCHMITT) | mask, pio + PIO_SCHMITT);
+        return 0;
+}
+EXPORT_SYMBOL(at91_disable_schmitt_trig);
+
+/*
  * assuming the pin is muxed as a gpio output, set its value.
  */
 int at91_set_gpio_value(unsigned pin, int value)
@@ -273,9 +425,9 @@ static u32 backups[MAX_GPIO_BANKS];
 
 static int gpio_irq_set_wake(struct irq_data *d, unsigned state)
 {
-        unsigned        pin = irq_to_gpio(d->irq);
-        unsigned        mask = pin_to_mask(pin);
-        unsigned        bank = pin / 32;
+        struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
+        unsigned        mask = 1 << d->hwirq;
+        unsigned        bank = at91_gpio->pioc_idx;
 
         if (unlikely(bank >= MAX_GPIO_BANKS))
                 return -EINVAL;
@@ -285,7 +437,7 @@ static int gpio_irq_set_wake(struct irq_data *d, unsigned state)
         else
                 wakeups[bank] &= ~mask;
 
-        irq_set_irq_wake(gpio_chip[bank].id, state);
+        irq_set_irq_wake(at91_gpio->pioc_virq, state);
 
         return 0;
 }
@@ -301,9 +453,10 @@ void at91_gpio_suspend(void)
                 __raw_writel(backups[i], pio + PIO_IDR);
                 __raw_writel(wakeups[i], pio + PIO_IER);
 
-                if (!wakeups[i])
+                if (!wakeups[i]) {
+                        clk_unprepare(gpio_chip[i].clock);
                         clk_disable(gpio_chip[i].clock);
-                else {
+                } else {
 #ifdef CONFIG_PM_DEBUG
                         printk(KERN_DEBUG "GPIO-%c may wake for %08x\n", 'A'+i, wakeups[i]);
 #endif
@@ -318,8 +471,10 @@ void at91_gpio_resume(void)
         for (i = 0; i < gpio_banks; i++) {
                 void __iomem    *pio = gpio_chip[i].regbase;
 
-                if (!wakeups[i])
-                        clk_enable(gpio_chip[i].clock);
+                if (!wakeups[i]) {
+                        if (clk_prepare(gpio_chip[i].clock) == 0)
+                                clk_enable(gpio_chip[i].clock);
+                }
 
                 __raw_writel(wakeups[i], pio + PIO_IDR);
                 __raw_writel(backups[i], pio + PIO_IER);
@@ -335,7 +490,10 @@ void at91_gpio_resume(void)
  * To use any AT91_PIN_* as an externally triggered IRQ, first call
  * at91_set_gpio_input() then maybe enable its glitch filter.
  * Then just request_irq() with the pin ID; it works like any ARM IRQ
- * handler, though it always triggers on rising and falling edges.
+ * handler.
+ * First implementation always triggers on rising and falling edges
+ * whereas the newer PIO3 can be additionally configured to trigger on
+ * level, edge with any polarity.
  *
  * Alternatively, certain pins may be used directly as IRQ0..IRQ6 after
  * configuring them with at91_set_a_periph() or at91_set_b_periph().
@@ -344,9 +502,9 @@ void at91_gpio_resume(void)
 
 static void gpio_irq_mask(struct irq_data *d)
 {
-        unsigned        pin = irq_to_gpio(d->irq);
-        void __iomem    *pio = pin_to_controller(pin);
-        unsigned        mask = pin_to_mask(pin);
+        struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
+        void __iomem    *pio = at91_gpio->regbase;
+        unsigned        mask = 1 << d->hwirq;
 
         if (pio)
                 __raw_writel(mask, pio + PIO_IDR);
@@ -354,9 +512,9 @@ static void gpio_irq_mask(struct irq_data *d)
 
 static void gpio_irq_unmask(struct irq_data *d)
 {
-        unsigned        pin = irq_to_gpio(d->irq);
-        void __iomem    *pio = pin_to_controller(pin);
-        unsigned        mask = pin_to_mask(pin);
+        struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
+        void __iomem    *pio = at91_gpio->regbase;
+        unsigned        mask = 1 << d->hwirq;
 
         if (pio)
                 __raw_writel(mask, pio + PIO_IER);
@@ -373,23 +531,66 @@ static int gpio_irq_type(struct irq_data *d, unsigned type)
         }
 }
 
+/* Alternate irq type for PIO3 support */
+static int alt_gpio_irq_type(struct irq_data *d, unsigned type)
+{
+        struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
+        void __iomem    *pio = at91_gpio->regbase;
+        unsigned        mask = 1 << d->hwirq;
+
+        switch (type) {
+        case IRQ_TYPE_EDGE_RISING:
+                __raw_writel(mask, pio + PIO_ESR);
+                __raw_writel(mask, pio + PIO_REHLSR);
+                break;
+        case IRQ_TYPE_EDGE_FALLING:
+                __raw_writel(mask, pio + PIO_ESR);
+                __raw_writel(mask, pio + PIO_FELLSR);
+                break;
+        case IRQ_TYPE_LEVEL_LOW:
+                __raw_writel(mask, pio + PIO_LSR);
+                __raw_writel(mask, pio + PIO_FELLSR);
+                break;
+        case IRQ_TYPE_LEVEL_HIGH:
+                __raw_writel(mask, pio + PIO_LSR);
+                __raw_writel(mask, pio + PIO_REHLSR);
+                break;
+        case IRQ_TYPE_EDGE_BOTH:
+                /*
+                 * disable additional interrupt modes:
+                 * fall back to default behavior
+                 */
+                __raw_writel(mask, pio + PIO_AIMDR);
+                return 0;
+        case IRQ_TYPE_NONE:
+        default:
+                pr_warn("AT91: No type for irq %d\n", gpio_to_irq(d->irq));
+                return -EINVAL;
+        }
+
+        /* enable additional interrupt modes */
+        __raw_writel(mask, pio + PIO_AIMER);
+
+        return 0;
+}
+
 static struct irq_chip gpio_irqchip = {
         .name           = "GPIO",
         .irq_disable    = gpio_irq_mask,
         .irq_mask       = gpio_irq_mask,
         .irq_unmask     = gpio_irq_unmask,
-        .irq_set_type   = gpio_irq_type,
+        /* .irq_set_type is set dynamically */
         .irq_set_wake   = gpio_irq_set_wake,
 };
 
 static void gpio_irq_handler(unsigned irq, struct irq_desc *desc)
 {
-        unsigned        irq_pin;
         struct irq_data *idata = irq_desc_get_irq_data(desc);
         struct irq_chip *chip = irq_data_get_irq_chip(idata);
         struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(idata);
         void __iomem    *pio = at91_gpio->regbase;
-        u32             isr;
+        unsigned long   isr;
+        int             n;
 
         /* temporarily mask (level sensitive) parent IRQ */
         chip->irq_ack(idata);
@@ -407,13 +608,10 @@ static void gpio_irq_handler(unsigned irq, struct irq_desc *desc)
                         continue;
                 }
 
-                irq_pin = gpio_to_irq(at91_gpio->chip.base);
-
-                while (isr) {
-                        if (isr & 1)
-                                generic_handle_irq(irq_pin);
-                        irq_pin++;
-                        isr >>= 1;
+                n = find_first_bit(&isr, BITS_PER_LONG);
+                while (n < BITS_PER_LONG) {
+                        generic_handle_irq(irq_find_mapping(at91_gpio->domain, n));
+                        n = find_next_bit(&isr, BITS_PER_LONG, n + 1);
                 }
         }
         chip->irq_unmask(idata);
@@ -424,6 +622,33 @@ static void gpio_irq_handler(unsigned irq, struct irq_desc *desc)
 
 #ifdef CONFIG_DEBUG_FS
 
+static void gpio_printf(struct seq_file *s, void __iomem *pio, unsigned mask)
+{
+        char    *trigger = NULL;
+        char    *polarity = NULL;
+
+        if (__raw_readl(pio + PIO_IMR) & mask) {
+                if (!has_pio3() || !(__raw_readl(pio + PIO_AIMMR) & mask )) {
+                        trigger = "edge";
+                        polarity = "both";
+                } else {
+                        if (__raw_readl(pio + PIO_ELSR) & mask) {
+                                trigger = "level";
+                                polarity = __raw_readl(pio + PIO_FRLHSR) & mask ?
+                                        "high" : "low";
+                        } else {
+                                trigger = "edge";
+                                polarity = __raw_readl(pio + PIO_FRLHSR) & mask ?
+                                                "rising" : "falling";
+                        }
+                }
+                seq_printf(s, "IRQ:%s-%s\t", trigger, polarity);
+        } else {
+                seq_printf(s, "GPIO:%s\t\t",
+                                __raw_readl(pio + PIO_PDSR) & mask ? "1" : "0");
+        }
+}
+
 static int at91_gpio_show(struct seq_file *s, void *unused)
 {
         int bank, j;
@@ -431,7 +656,7 @@ static int at91_gpio_show(struct seq_file *s, void *unused)
         /* print heading */
         seq_printf(s, "Pin\t");
         for (bank = 0; bank < gpio_banks; bank++) {
-                seq_printf(s, "PIO%c\t", 'A' + bank);
+                seq_printf(s, "PIO%c\t\t", 'A' + bank);
         };
         seq_printf(s, "\n\n");
 
@@ -445,11 +670,10 @@ static int at91_gpio_show(struct seq_file *s, void *unused)
                         unsigned        mask = pin_to_mask(pin);
 
                         if (__raw_readl(pio + PIO_PSR) & mask)
-                                seq_printf(s, "GPIO:%s", __raw_readl(pio + PIO_PDSR) & mask ? "1" : "0");
+                                gpio_printf(s, pio, mask);
                         else
-                                seq_printf(s, "%s", __raw_readl(pio + PIO_ABSR) & mask ? "B" : "A");
-
-                        seq_printf(s, "\t");
+                                seq_printf(s, "%c\t\t",
+                                                peripheral_function(pio, mask));
                 }
 
                 seq_printf(s, "\n");
@@ -488,46 +712,152 @@ postcore_initcall(at91_gpio_debugfs_init);
  */
 static struct lock_class_key gpio_lock_class;
 
+#if defined(CONFIG_OF)
+static int at91_gpio_irq_map(struct irq_domain *h, unsigned int virq,
+                                                        irq_hw_number_t hw)
+{
+        struct at91_gpio_chip   *at91_gpio = h->host_data;
+
+        irq_set_lockdep_class(virq, &gpio_lock_class);
+
+        /*
+         * Can use the "simple" and not "edge" handler since it's
+         * shorter, and the AIC handles interrupts sanely.
+         */
+        irq_set_chip_and_handler(virq, &gpio_irqchip,
+                                 handle_simple_irq);
+        set_irq_flags(virq, IRQF_VALID);
+        irq_set_chip_data(virq, at91_gpio);
+
+        return 0;
+}
+
+static struct irq_domain_ops at91_gpio_ops = {
+        .map    = at91_gpio_irq_map,
+        .xlate  = irq_domain_xlate_twocell,
+};
+
+int __init at91_gpio_of_irq_setup(struct device_node *node,
+                                     struct device_node *parent)
+{
+        struct at91_gpio_chip   *prev = NULL;
+        int                     alias_idx = of_alias_get_id(node, "gpio");
+        struct at91_gpio_chip   *at91_gpio = &gpio_chip[alias_idx];
+
+        /* Setup proper .irq_set_type function */
+        if (has_pio3())
+                gpio_irqchip.irq_set_type = alt_gpio_irq_type;
+        else
+                gpio_irqchip.irq_set_type = gpio_irq_type;
+
+        /* Disable irqs of this PIO controller */
+        __raw_writel(~0, at91_gpio->regbase + PIO_IDR);
+
+        /* Setup irq domain */
+        at91_gpio->domain = irq_domain_add_linear(node, at91_gpio->chip.ngpio,
+                                                &at91_gpio_ops, at91_gpio);
+        if (!at91_gpio->domain)
+                panic("at91_gpio.%d: couldn't allocate irq domain (DT).\n",
+                        at91_gpio->pioc_idx);
+
+        /* Setup chained handler */
+        if (at91_gpio->pioc_idx)
+                prev = &gpio_chip[at91_gpio->pioc_idx - 1];
+
+        /* The toplevel handler handles one bank of GPIOs, except
+         * on some SoC it can handles up to three...
+         * We only set up the handler for the first of the list.
+         */
+        if (prev && prev->next == at91_gpio)
+                return 0;
+
+        at91_gpio->pioc_virq = irq_create_mapping(irq_find_host(parent),
+                                                        at91_gpio->pioc_hwirq);
+        irq_set_chip_data(at91_gpio->pioc_virq, at91_gpio);
+        irq_set_chained_handler(at91_gpio->pioc_virq, gpio_irq_handler);
+
+        return 0;
+}
+#else
+int __init at91_gpio_of_irq_setup(struct device_node *node,
+                                     struct device_node *parent)
+{
+        return -EINVAL;
+}
+#endif
+
+/*
+ * irqdomain initialization: pile up irqdomains on top of AIC range
+ */
+static void __init at91_gpio_irqdomain(struct at91_gpio_chip *at91_gpio)
+{
+        int irq_base;
+
+        irq_base = irq_alloc_descs(-1, 0, at91_gpio->chip.ngpio, 0);
+        if (irq_base < 0)
+                panic("at91_gpio.%d: error %d: couldn't allocate IRQ numbers.\n",
+                        at91_gpio->pioc_idx, irq_base);
+        at91_gpio->domain = irq_domain_add_legacy(NULL, at91_gpio->chip.ngpio,
+                                                  irq_base, 0,
+                                                  &irq_domain_simple_ops, NULL);
+        if (!at91_gpio->domain)
+                panic("at91_gpio.%d: couldn't allocate irq domain.\n",
+                        at91_gpio->pioc_idx);
+}
+
 /*
  * Called from the processor-specific init to enable GPIO interrupt support.
  */
 void __init at91_gpio_irq_setup(void)
 {
-        unsigned                pioc, irq = gpio_to_irq(0);
+        unsigned                pioc;
+        int                     gpio_irqnbr = 0;
         struct at91_gpio_chip   *this, *prev;
 
+        /* Setup proper .irq_set_type function */
+        if (has_pio3())
+                gpio_irqchip.irq_set_type = alt_gpio_irq_type;
+        else
+                gpio_irqchip.irq_set_type = gpio_irq_type;
+
         for (pioc = 0, this = gpio_chip, prev = NULL;
                         pioc++ < gpio_banks;
                         prev = this, this++) {
-                unsigned        id = this->id;
-                unsigned        i;
+                int offset;
 
                 __raw_writel(~0, this->regbase + PIO_IDR);
 
-                for (i = 0, irq = gpio_to_irq(this->chip.base); i < 32;
-                     i++, irq++) {
-                        irq_set_lockdep_class(irq, &gpio_lock_class);
+                /* setup irq domain for this GPIO controller */
+                at91_gpio_irqdomain(this);
+
+                for (offset = 0; offset < this->chip.ngpio; offset++) {
+                        unsigned int virq = irq_find_mapping(this->domain, offset);
+                        irq_set_lockdep_class(virq, &gpio_lock_class);
 
                         /*
                          * Can use the "simple" and not "edge" handler since it's
                          * shorter, and the AIC handles interrupts sanely.
                          */
-                        irq_set_chip_and_handler(irq, &gpio_irqchip,
+                        irq_set_chip_and_handler(virq, &gpio_irqchip,
                                                  handle_simple_irq);
-                        set_irq_flags(irq, IRQF_VALID);
+                        set_irq_flags(virq, IRQF_VALID);
+                        irq_set_chip_data(virq, this);
+
+                        gpio_irqnbr++;
                 }
 
                 /* The toplevel handler handles one bank of GPIOs, except
-                 * AT91SAM9263_ID_PIOCDE handles three... PIOC is first in
-                 * the list, so we only set up that handler.
+                 * on some SoC it can handles up to three...
+                 * We only set up the handler for the first of the list.
                  */
                 if (prev && prev->next == this)
                         continue;
 
-                irq_set_chip_data(id, this);
-                irq_set_chained_handler(id, gpio_irq_handler);
+                this->pioc_virq = irq_create_mapping(NULL, this->pioc_hwirq);
+                irq_set_chip_data(this->pioc_virq, this);
+                irq_set_chained_handler(this->pioc_virq, gpio_irq_handler);
         }
-        pr_info("AT91: %d gpio irqs in %d banks\n", irq - gpio_to_irq(0), gpio_banks);
+        pr_info("AT91: %d gpio irqs in %d banks\n", gpio_irqnbr, gpio_banks);
 }
 
 /* gpiolib support */
@@ -593,48 +923,175 @@ static void at91_gpiolib_dbg_show(struct seq_file *s, struct gpio_chip *chip)
                                            at91_get_gpio_value(pin) ?
                                            "set" : "clear");
                         else
-                                seq_printf(s, "[periph %s]\n",
-                                           __raw_readl(pio + PIO_ABSR) &
-                                           mask ? "B" : "A");
+                                seq_printf(s, "[periph %c]\n",
+                                           peripheral_function(pio, mask));
                 }
         }
 }
 
+static int at91_gpiolib_to_irq(struct gpio_chip *chip, unsigned offset)
+{
+        struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
+        int virq;
+
+        if (offset < chip->ngpio)
+                virq = irq_create_mapping(at91_gpio->domain, offset);
+        else
+                virq = -ENXIO;
+
+        dev_dbg(chip->dev, "%s: request IRQ for GPIO %d, return %d\n",
+                                chip->label, offset + chip->base, virq);
+        return virq;
+}
+
+static int __init at91_gpio_setup_clk(int idx)
+{
+        struct at91_gpio_chip *at91_gpio = &gpio_chip[idx];
+
+        /* retreive PIO controller's clock */
+        at91_gpio->clock = clk_get_sys(NULL, at91_gpio->chip.label);
+        if (IS_ERR(at91_gpio->clock)) {
+                pr_err("at91_gpio.%d, failed to get clock, ignoring.\n", idx);
+                goto err;
+        }
+
+        if (clk_prepare(at91_gpio->clock))
+                goto clk_prep_err;
+
+        /* enable PIO controller's clock */
+        if (clk_enable(at91_gpio->clock)) {
+                pr_err("at91_gpio.%d, failed to enable clock, ignoring.\n", idx);
+                goto clk_err;
+        }
+
+        return 0;
+
+clk_err:
+        clk_unprepare(at91_gpio->clock);
+clk_prep_err:
+        clk_put(at91_gpio->clock);
+err:
+        return -EINVAL;
+}
+
+#ifdef CONFIG_OF_GPIO
+static void __init of_at91_gpio_init_one(struct device_node *np)
+{
+        int alias_idx;
+        struct at91_gpio_chip *at91_gpio;
+
+        if (!np)
+                return;
+
+        alias_idx = of_alias_get_id(np, "gpio");
+        if (alias_idx >= MAX_GPIO_BANKS) {
+                pr_err("at91_gpio, failed alias idx(%d) > MAX_GPIO_BANKS(%d), ignoring.\n",
+                                                alias_idx, MAX_GPIO_BANKS);
+                return;
+        }
+
+        at91_gpio = &gpio_chip[alias_idx];
+        at91_gpio->chip.base = alias_idx * at91_gpio->chip.ngpio;
+
+        at91_gpio->regbase = of_iomap(np, 0);
+        if (!at91_gpio->regbase) {
+                pr_err("at91_gpio.%d, failed to map registers, ignoring.\n",
+                                                                alias_idx);
+                return;
+        }
+
+        /* Get the interrupts property */
+        if (of_property_read_u32(np, "interrupts", &at91_gpio->pioc_hwirq)) {
+                pr_err("at91_gpio.%d, failed to get interrupts property, ignoring.\n",
+                                                                alias_idx);
+                goto ioremap_err;
+        }
+
+        /* Get capabilities from compatibility property */
+        if (of_device_is_compatible(np, "atmel,at91sam9x5-gpio"))
+                at91_gpio_caps |= AT91_GPIO_CAP_PIO3;
+
+        /* Setup clock */
+        if (at91_gpio_setup_clk(alias_idx))
+                goto ioremap_err;
+
+        at91_gpio->chip.of_node = np;
+        gpio_banks = max(gpio_banks, alias_idx + 1);
+        at91_gpio->pioc_idx = alias_idx;
+        return;
+
+ioremap_err:
+        iounmap(at91_gpio->regbase);
+}
+
+static int __init of_at91_gpio_init(void)
+{
+        struct device_node *np = NULL;
+
+        /*
+         * This isn't ideal, but it gets things hooked up until this
+         * driver is converted into a platform_device
+         */
+        for_each_compatible_node(np, NULL, "atmel,at91rm9200-gpio")
+                of_at91_gpio_init_one(np);
+
+        return gpio_banks > 0 ? 0 : -EINVAL;
+}
+#else
+static int __init of_at91_gpio_init(void)
+{
+        return -EINVAL;
+}
+#endif
+
+static void __init at91_gpio_init_one(int idx, u32 regbase, int pioc_hwirq)
+{
+        struct at91_gpio_chip *at91_gpio = &gpio_chip[idx];
+
+        at91_gpio->chip.base = idx * at91_gpio->chip.ngpio;
+        at91_gpio->pioc_hwirq = pioc_hwirq;
+        at91_gpio->pioc_idx = idx;
+
+        at91_gpio->regbase = ioremap(regbase, 512);
+        if (!at91_gpio->regbase) {
+                pr_err("at91_gpio.%d, failed to map registers, ignoring.\n", idx);
+                return;
+        }
+
+        if (at91_gpio_setup_clk(idx))
+                goto ioremap_err;
+
+        gpio_banks = max(gpio_banks, idx + 1);
+        return;
+
+ioremap_err:
+        iounmap(at91_gpio->regbase);
+}
+
 /*
  * Called from the processor-specific init to enable GPIO pin support.
  */
 void __init at91_gpio_init(struct at91_gpio_bank *data, int nr_banks)
 {
-        unsigned                i;
+        unsigned i;
         struct at91_gpio_chip *at91_gpio, *last = NULL;
 
         BUG_ON(nr_banks > MAX_GPIO_BANKS);
 
-        gpio_banks = nr_banks;
+        if (of_at91_gpio_init() < 0) {
+                /* No GPIO controller found in device tree */
+                for (i = 0; i < nr_banks; i++)
+                        at91_gpio_init_one(i, data[i].regbase, data[i].id);
+        }
 
-        for (i = 0; i < nr_banks; i++) {
+        for (i = 0; i < gpio_banks; i++) {
                 at91_gpio = &gpio_chip[i];
 
-                at91_gpio->id = data[i].id;
-                at91_gpio->chip.base = i * 32;
-
-                at91_gpio->regbase = ioremap(data[i].regbase, 512);
-                if (!at91_gpio->regbase) {
-                        pr_err("at91_gpio.%d, failed to map registers, ignoring.\n", i);
-                        continue;
-                }
-
-                at91_gpio->clock = clk_get_sys(NULL, at91_gpio->chip.label);
-                if (!at91_gpio->clock) {
-                        pr_err("at91_gpio.%d, failed to get clock, ignoring.\n", i);
-                        continue;
-                }
-
-                /* enable PIO controller's clock */
-                clk_enable(at91_gpio->clock);
-
-                /* AT91SAM9263_ID_PIOCDE groups PIOC, PIOD, PIOE */
-                if (last && last->id == at91_gpio->id)
+                /*
+                 * GPIO controller are grouped on some SoC:
+                 * PIOC, PIOD and PIOE can share the same IRQ line
+                 */
+                if (last && last->pioc_hwirq == at91_gpio->pioc_hwirq)
                         last->next = at91_gpio;
                 last = at91_gpio;
 
diff --git a/arch/arm/mach-at91/include/mach/at91_matrix.h b/arch/arm/mach-at91/include/mach/at91_matrix.h
new file mode 100644
index 00000000000..02fae9de746
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/at91_matrix.h
@@ -0,0 +1,23 @@
+/*
+ * Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+ *
+ * Under GPLv2
+ */
+
+#ifndef __MACH_AT91_MATRIX_H__
+#define __MACH_AT91_MATRIX_H__
+
+#ifndef __ASSEMBLY__
+extern void __iomem *at91_matrix_base;
+
+#define at91_matrix_read(field) \
+        __raw_readl(at91_matrix_base + field)
+
+#define at91_matrix_write(field, value) \
+        __raw_writel(value, at91_matrix_base + field);
+
+#else
+.extern at91_matrix_base
+#endif
+
+#endif /* __MACH_AT91_MATRIX_H__ */
diff --git a/arch/arm/mach-at91/include/mach/at91_pio.h b/arch/arm/mach-at91/include/mach/at91_pio.h
index c6a31bf8a5c..732b11c37f1 100644
--- a/arch/arm/mach-at91/include/mach/at91_pio.h
+++ b/arch/arm/mach-at91/include/mach/at91_pio.h
@@ -40,10 +40,35 @@
 #define PIO_PUER        0x64    /* Pull-up Enable Register */
 #define PIO_PUSR        0x68    /* Pull-up Status Register */
 #define PIO_ASR         0x70    /* Peripheral A Select Register */
+#define PIO_ABCDSR1     0x70    /* Peripheral ABCD Select Register 1 [some sam9 only] */
 #define PIO_BSR         0x74    /* Peripheral B Select Register */
+#define PIO_ABCDSR2     0x74    /* Peripheral ABCD Select Register 2 [some sam9 only] */
 #define PIO_ABSR        0x78    /* AB Status Register */
+#define PIO_IFSCDR      0x80    /* Input Filter Slow Clock Disable Register */
+#define PIO_IFSCER      0x84    /* Input Filter Slow Clock Enable Register */
+#define PIO_IFSCSR      0x88    /* Input Filter Slow Clock Status Register */
+#define PIO_SCDR        0x8c    /* Slow Clock Divider Debouncing Register */
+#define         PIO_SCDR_DIV    (0x3fff <<  0)          /* Slow Clock Divider Mask */
+#define PIO_PPDDR       0x90    /* Pad Pull-down Disable Register */
+#define PIO_PPDER       0x94    /* Pad Pull-down Enable Register */
+#define PIO_PPDSR       0x98    /* Pad Pull-down Status Register */
 #define PIO_OWER        0xa0    /* Output Write Enable Register */
 #define PIO_OWDR        0xa4    /* Output Write Disable Register */
 #define PIO_OWSR        0xa8    /* Output Write Status Register */
+#define PIO_AIMER       0xb0    /* Additional Interrupt Modes Enable Register */
+#define PIO_AIMDR       0xb4    /* Additional Interrupt Modes Disable Register */
+#define PIO_AIMMR       0xb8    /* Additional Interrupt Modes Mask Register */
+#define PIO_ESR         0xc0    /* Edge Select Register */
+#define PIO_LSR         0xc4    /* Level Select Register */
+#define PIO_ELSR        0xc8    /* Edge/Level Status Register */
+#define PIO_FELLSR      0xd0    /* Falling Edge/Low Level Select Register */
+#define PIO_REHLSR      0xd4    /* Rising Edge/ High Level Select Register */
+#define PIO_FRLHSR      0xd8    /* Fall/Rise - Low/High Status Register */
+#define PIO_SCHMITT     0x100   /* Schmitt Trigger Register */
+
+#define ABCDSR_PERIPH_A 0x0
+#define ABCDSR_PERIPH_B 0x1
+#define ABCDSR_PERIPH_C 0x2
+#define ABCDSR_PERIPH_D 0x3
 
 #endif
diff --git a/arch/arm/mach-at91/include/mach/at91_pmc.h b/arch/arm/mach-at91/include/mach/at91_pmc.h
index e46f93e34aa..36604782a78 100644
--- a/arch/arm/mach-at91/include/mach/at91_pmc.h
+++ b/arch/arm/mach-at91/include/mach/at91_pmc.h
@@ -16,17 +16,27 @@
 #ifndef AT91_PMC_H
 #define AT91_PMC_H
 
-#define AT91_PMC_SCER           (AT91_PMC + 0x00)       /* System Clock Enable Register */
-#define AT91_PMC_SCDR           (AT91_PMC + 0x04)       /* System Clock Disable Register */
+#ifndef __ASSEMBLY__
+extern void __iomem *at91_pmc_base;
 
-#define AT91_PMC_SCSR           (AT91_PMC + 0x08)       /* System Clock Status Register */
+#define at91_pmc_read(field) \
+        __raw_readl(at91_pmc_base + field)
+
+#define at91_pmc_write(field, value) \
+        __raw_writel(value, at91_pmc_base + field)
+#else
+.extern at91_aic_base
+#endif
+
+#define AT91_PMC_SCER           0x00                    /* System Clock Enable Register */
+#define AT91_PMC_SCDR           0x04                    /* System Clock Disable Register */
+
+#define AT91_PMC_SCSR           0x08                    /* System Clock Status Register */
 #define         AT91_PMC_PCK            (1 <<  0)               /* Processor Clock */
 #define         AT91RM9200_PMC_UDP      (1 <<  1)               /* USB Devcice Port Clock [AT91RM9200 only] */
 #define         AT91RM9200_PMC_MCKUDP   (1 <<  2)               /* USB Device Port Master Clock Automatic Disable on Suspend [AT91RM9200 only] */
-#define         AT91CAP9_PMC_DDR        (1 <<  2)               /* DDR Clock [CAP9 revC & some SAM9 only] */
 #define         AT91RM9200_PMC_UHP      (1 <<  4)               /* USB Host Port Clock [AT91RM9200 only] */
 #define         AT91SAM926x_PMC_UHP     (1 <<  6)               /* USB Host Port Clock [AT91SAM926x only] */
-#define         AT91CAP9_PMC_UHP        (1 <<  6)               /* USB Host Port Clock [AT91CAP9 only] */
 #define         AT91SAM926x_PMC_UDP     (1 <<  7)               /* USB Devcice Port Clock [AT91SAM926x only] */
 #define         AT91_PMC_PCK0           (1 <<  8)               /* Programmable Clock 0 */
 #define         AT91_PMC_PCK1           (1 <<  9)               /* Programmable Clock 1 */
@@ -36,27 +46,31 @@
 #define         AT91_PMC_HCK0           (1 << 16)               /* AHB Clock (USB host) [AT91SAM9261 only] */
 #define         AT91_PMC_HCK1           (1 << 17)               /* AHB Clock (LCD) [AT91SAM9261 only] */
 
-#define AT91_PMC_PCER           (AT91_PMC + 0x10)       /* Peripheral Clock Enable Register */
-#define AT91_PMC_PCDR           (AT91_PMC + 0x14)       /* Peripheral Clock Disable Register */
-#define AT91_PMC_PCSR           (AT91_PMC + 0x18)       /* Peripheral Clock Status Register */
+#define AT91_PMC_PCER           0x10                    /* Peripheral Clock Enable Register */
+#define AT91_PMC_PCDR           0x14                    /* Peripheral Clock Disable Register */
+#define AT91_PMC_PCSR           0x18                    /* Peripheral Clock Status Register */
 
-#define AT91_CKGR_UCKR          (AT91_PMC + 0x1C)       /* UTMI Clock Register [some SAM9, CAP9] */
+#define AT91_CKGR_UCKR          0x1C                    /* UTMI Clock Register [some SAM9] */
 #define         AT91_PMC_UPLLEN         (1   << 16)             /* UTMI PLL Enable */
 #define         AT91_PMC_UPLLCOUNT      (0xf << 20)             /* UTMI PLL Start-up Time */
 #define         AT91_PMC_BIASEN         (1   << 24)             /* UTMI BIAS Enable */
 #define         AT91_PMC_BIASCOUNT      (0xf << 28)             /* UTMI BIAS Start-up Time */
 
-#define AT91_CKGR_MOR           (AT91_PMC + 0x20)       /* Main Oscillator Register [not on SAM9RL] */
-#define         AT91_PMC_MOSCEN         (1    << 0)             /* Main Oscillator Enable */
-#define         AT91_PMC_OSCBYPASS      (1    << 1)             /* Oscillator Bypass [SAM9x, CAP9] */
-#define         AT91_PMC_OSCOUNT        (0xff << 8)             /* Main Oscillator Start-up Time */
+#define AT91_CKGR_MOR           0x20                    /* Main Oscillator Register [not on SAM9RL] */
+#define         AT91_PMC_MOSCEN         (1    <<  0)            /* Main Oscillator Enable */
+#define         AT91_PMC_OSCBYPASS      (1    <<  1)            /* Oscillator Bypass */
+#define         AT91_PMC_MOSCRCEN       (1    <<  3)            /* Main On-Chip RC Oscillator Enable [some SAM9] */
+#define         AT91_PMC_OSCOUNT        (0xff <<  8)            /* Main Oscillator Start-up Time */
+#define         AT91_PMC_KEY            (0x37 << 16)            /* MOR Writing Key */
+#define         AT91_PMC_MOSCSEL        (1    << 24)            /* Main Oscillator Selection [some SAM9] */
+#define         AT91_PMC_CFDEN          (1    << 25)            /* Clock Failure Detector Enable [some SAM9] */
 
-#define AT91_CKGR_MCFR          (AT91_PMC + 0x24)       /* Main Clock Frequency Register */
+#define AT91_CKGR_MCFR          0x24                    /* Main Clock Frequency Register */
 #define         AT91_PMC_MAINF          (0xffff <<  0)          /* Main Clock Frequency */
 #define         AT91_PMC_MAINRDY        (1      << 16)          /* Main Clock Ready */
 
-#define AT91_CKGR_PLLAR         (AT91_PMC + 0x28)       /* PLL A Register */
-#define AT91_CKGR_PLLBR         (AT91_PMC + 0x2c)       /* PLL B Register */
+#define AT91_CKGR_PLLAR         0x28                    /* PLL A Register */
+#define AT91_CKGR_PLLBR         0x2c                    /* PLL B Register */
 #define         AT91_PMC_DIV            (0xff  <<  0)           /* Divider */
 #define         AT91_PMC_PLLCOUNT       (0x3f  <<  8)           /* PLL Counter */
 #define         AT91_PMC_OUT            (3     << 14)           /* PLL Clock Frequency Range */
@@ -67,27 +81,37 @@
 #define                 AT91_PMC_USBDIV_4               (2 << 28)
 #define         AT91_PMC_USB96M         (1     << 28)           /* Divider by 2 Enable (PLLB only) */
 
-#define AT91_PMC_MCKR           (AT91_PMC + 0x30)       /* Master Clock Register */
+#define AT91_PMC_MCKR           0x30                    /* Master Clock Register */
 #define         AT91_PMC_CSS            (3 <<  0)               /* Master Clock Selection */
 #define                 AT91_PMC_CSS_SLOW               (0 << 0)
 #define                 AT91_PMC_CSS_MAIN               (1 << 0)
 #define                 AT91_PMC_CSS_PLLA               (2 << 0)
 #define                 AT91_PMC_CSS_PLLB               (3 << 0)
 #define                 AT91_PMC_CSS_UPLL               (3 << 0)        /* [some SAM9 only] */
-#define         AT91_PMC_PRES           (7 <<  2)               /* Master Clock Prescaler */
-#define                 AT91_PMC_PRES_1                 (0 << 2)
-#define                 AT91_PMC_PRES_2                 (1 << 2)
-#define                 AT91_PMC_PRES_4                 (2 << 2)
-#define                 AT91_PMC_PRES_8                 (3 << 2)
-#define                 AT91_PMC_PRES_16                (4 << 2)
-#define                 AT91_PMC_PRES_32                (5 << 2)
-#define                 AT91_PMC_PRES_64                (6 << 2)
+#define         PMC_PRES_OFFSET         2
+#define         AT91_PMC_PRES           (7 <<  PMC_PRES_OFFSET)         /* Master Clock Prescaler */
+#define                 AT91_PMC_PRES_1                 (0 << PMC_PRES_OFFSET)
+#define                 AT91_PMC_PRES_2                 (1 << PMC_PRES_OFFSET)
+#define                 AT91_PMC_PRES_4                 (2 << PMC_PRES_OFFSET)
+#define                 AT91_PMC_PRES_8                 (3 << PMC_PRES_OFFSET)
+#define                 AT91_PMC_PRES_16                (4 << PMC_PRES_OFFSET)
+#define                 AT91_PMC_PRES_32                (5 << PMC_PRES_OFFSET)
+#define                 AT91_PMC_PRES_64                (6 << PMC_PRES_OFFSET)
+#define         PMC_ALT_PRES_OFFSET     4
+#define         AT91_PMC_ALT_PRES       (7 <<  PMC_ALT_PRES_OFFSET)             /* Master Clock Prescaler [alternate location] */
+#define                 AT91_PMC_ALT_PRES_1             (0 << PMC_ALT_PRES_OFFSET)
+#define                 AT91_PMC_ALT_PRES_2             (1 << PMC_ALT_PRES_OFFSET)
+#define                 AT91_PMC_ALT_PRES_4             (2 << PMC_ALT_PRES_OFFSET)
+#define                 AT91_PMC_ALT_PRES_8             (3 << PMC_ALT_PRES_OFFSET)
+#define                 AT91_PMC_ALT_PRES_16            (4 << PMC_ALT_PRES_OFFSET)
+#define                 AT91_PMC_ALT_PRES_32            (5 << PMC_ALT_PRES_OFFSET)
+#define                 AT91_PMC_ALT_PRES_64            (6 << PMC_ALT_PRES_OFFSET)
 #define         AT91_PMC_MDIV           (3 <<  8)               /* Master Clock Division */
 #define                 AT91RM9200_PMC_MDIV_1           (0 << 8)        /* [AT91RM9200 only] */
 #define                 AT91RM9200_PMC_MDIV_2           (1 << 8)
 #define                 AT91RM9200_PMC_MDIV_3           (2 << 8)
 #define                 AT91RM9200_PMC_MDIV_4           (3 << 8)
-#define                 AT91SAM9_PMC_MDIV_1             (0 << 8)        /* [SAM9,CAP9 only] */
+#define                 AT91SAM9_PMC_MDIV_1             (0 << 8)        /* [SAM9 only] */
 #define                 AT91SAM9_PMC_MDIV_2             (1 << 8)
 #define                 AT91SAM9_PMC_MDIV_4             (2 << 8)
 #define                 AT91SAM9_PMC_MDIV_6             (3 << 8)        /* [some SAM9 only] */
@@ -99,35 +123,55 @@
 #define                 AT91_PMC_PLLADIV2_OFF           (0 << 12)
 #define                 AT91_PMC_PLLADIV2_ON            (1 << 12)
 
-#define AT91_PMC_USB            (AT91_PMC + 0x38)       /* USB Clock Register [some SAM9 only] */
+#define AT91_PMC_USB            0x38                    /* USB Clock Register [some SAM9 only] */
 #define         AT91_PMC_USBS           (0x1 <<  0)             /* USB OHCI Input clock selection */
 #define                 AT91_PMC_USBS_PLLA              (0 << 0)
 #define                 AT91_PMC_USBS_UPLL              (1 << 0)
 #define         AT91_PMC_OHCIUSBDIV     (0xF <<  8)             /* Divider for USB OHCI Clock */
 
-#define AT91_PMC_PCKR(n)        (AT91_PMC + 0x40 + ((n) * 4))   /* Programmable Clock 0-N Registers */
+#define AT91_PMC_SMD            0x3c                    /* Soft Modem Clock Register [some SAM9 only] */
+#define         AT91_PMC_SMDS           (0x1  <<  0)            /* SMD input clock selection */
+#define         AT91_PMC_SMD_DIV        (0x1f <<  8)            /* SMD input clock divider */
+#define         AT91_PMC_SMDDIV(n)      (((n) <<  8) & AT91_PMC_SMD_DIV)
+
+#define AT91_PMC_PCKR(n)        (0x40 + ((n) * 4))      /* Programmable Clock 0-N Registers */
+#define         AT91_PMC_ALT_PCKR_CSS   (0x7 <<  0)             /* Programmable Clock Source Selection [alternate length] */
+#define                 AT91_PMC_CSS_MASTER             (4 << 0)        /* [some SAM9 only] */
 #define         AT91_PMC_CSSMCK         (0x1 <<  8)             /* CSS or Master Clock Selection */
 #define                 AT91_PMC_CSSMCK_CSS             (0 << 8)
 #define                 AT91_PMC_CSSMCK_MCK             (1 << 8)
 
-#define AT91_PMC_IER            (AT91_PMC + 0x60)       /* Interrupt Enable Register */
-#define AT91_PMC_IDR            (AT91_PMC + 0x64)       /* Interrupt Disable Register */
-#define AT91_PMC_SR             (AT91_PMC + 0x68)       /* Status Register */
+#define AT91_PMC_IER            0x60                    /* Interrupt Enable Register */
+#define AT91_PMC_IDR            0x64                    /* Interrupt Disable Register */
+#define AT91_PMC_SR             0x68                    /* Status Register */
 #define         AT91_PMC_MOSCS          (1 <<  0)               /* MOSCS Flag */
 #define         AT91_PMC_LOCKA          (1 <<  1)               /* PLLA Lock */
 #define         AT91_PMC_LOCKB          (1 <<  2)               /* PLLB Lock */
 #define         AT91_PMC_MCKRDY         (1 <<  3)               /* Master Clock */
-#define         AT91_PMC_LOCKU          (1 <<  6)               /* UPLL Lock [some SAM9, AT91CAP9 only] */
-#define         AT91_PMC_OSCSEL         (1 <<  7)               /* Slow Clock Oscillator [AT91CAP9 revC only] */
+#define         AT91_PMC_LOCKU          (1 <<  6)               /* UPLL Lock [some SAM9] */
 #define         AT91_PMC_PCK0RDY        (1 <<  8)               /* Programmable Clock 0 */
 #define         AT91_PMC_PCK1RDY        (1 <<  9)               /* Programmable Clock 1 */
 #define         AT91_PMC_PCK2RDY        (1 << 10)               /* Programmable Clock 2 */
 #define         AT91_PMC_PCK3RDY        (1 << 11)               /* Programmable Clock 3 */
-#define AT91_PMC_IMR            (AT91_PMC + 0x6c)       /* Interrupt Mask Register */
+#define         AT91_PMC_MOSCSELS       (1 << 16)               /* Main Oscillator Selection [some SAM9] */
+#define         AT91_PMC_MOSCRCS        (1 << 17)               /* Main On-Chip RC [some SAM9] */
+#define         AT91_PMC_CFDEV          (1 << 18)               /* Clock Failure Detector Event [some SAM9] */
+#define AT91_PMC_IMR            0x6c                    /* Interrupt Mask Register */
+
+#define AT91_PMC_PROT           0xe4                    /* Write Protect Mode Register [some SAM9] */
+#define         AT91_PMC_WPEN           (0x1  <<  0)            /* Write Protect Enable */
+#define         AT91_PMC_WPKEY          (0xffffff << 8)         /* Write Protect Key */
+#define         AT91_PMC_PROTKEY        (0x504d43 << 8)         /* Activation Code */
 
-#define AT91_PMC_PROT           (AT91_PMC + 0xe4)       /* Protect Register [AT91CAP9 revC only] */
-#define         AT91_PMC_PROTKEY        0x504d4301      /* Activation Code */
+#define AT91_PMC_WPSR           0xe8                    /* Write Protect Status Register [some SAM9] */
+#define         AT91_PMC_WPVS           (0x1  <<  0)            /* Write Protect Violation Status */
+#define         AT91_PMC_WPVSRC         (0xffff  <<  8)         /* Write Protect Violation Source */
 
-#define AT91_PMC_VER            (AT91_PMC + 0xfc)       /* PMC Module Version [AT91CAP9 only] */
+#define AT91_PMC_PCR            0x10c                   /* Peripheral Control Register [some SAM9] */
+#define         AT91_PMC_PCR_PID        (0x3f  <<  0)           /* Peripheral ID */
+#define         AT91_PMC_PCR_CMD        (0x1  <<  12)           /* Command */
+#define         AT91_PMC_PCR_DIV        (0x3  <<  16)           /* Divisor Value */
+#define         AT91_PMC_PCRDIV(n)      (((n) <<  16) & AT91_PMC_PCR_DIV)
+#define         AT91_PMC_PCR_EN         (0x1  <<  28)           /* Enable */
 
 #endif
diff --git a/arch/arm/mach-at91/include/mach/at91_ramc.h b/arch/arm/mach-at91/include/mach/at91_ramc.h
new file mode 100644
index 00000000000..d8aeb278614
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/at91_ramc.h
@@ -0,0 +1,32 @@
+/*
+ * Header file for the Atmel RAM Controller
+ *
+ * Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+ *
+ * Under GPLv2 only
+ */
+
+#ifndef __AT91_RAMC_H__
+#define __AT91_RAMC_H__
+
+#ifndef __ASSEMBLY__
+extern void __iomem *at91_ramc_base[];
+
+#define at91_ramc_read(id, field) \
+        __raw_readl(at91_ramc_base[id] + field)
+
+#define at91_ramc_write(id, field, value) \
+        __raw_writel(value, at91_ramc_base[id] + field)
+#else
+.extern at91_ramc_base
+#endif
+
+#define AT91_MEMCTRL_MC         0
+#define AT91_MEMCTRL_SDRAMC     1
+#define AT91_MEMCTRL_DDRSDR     2
+
+#include <mach/at91rm9200_sdramc.h>
+#include <mach/at91sam9_ddrsdr.h>
+#include <mach/at91sam9_sdramc.h>
+
+#endif /* __AT91_RAMC_H__ */
diff --git a/arch/arm/mach-at91/include/mach/at91_st.h b/arch/arm/mach-at91/include/mach/at91_st.h
index 8847173e410..969aac27109 100644
--- a/arch/arm/mach-at91/include/mach/at91_st.h
+++ b/arch/arm/mach-at91/include/mach/at91_st.h
@@ -16,34 +16,46 @@
 #ifndef AT91_ST_H
 #define AT91_ST_H
 
-#define AT91_ST_CR              (AT91_ST + 0x00)        /* Control Register */
+#ifndef __ASSEMBLY__
+extern void __iomem *at91_st_base;
+
+#define at91_st_read(field) \
+        __raw_readl(at91_st_base + field)
+
+#define at91_st_write(field, value) \
+        __raw_writel(value, at91_st_base + field);
+#else
+.extern at91_st_base
+#endif
+
+#define AT91_ST_CR              0x00                    /* Control Register */
 #define         AT91_ST_WDRST           (1 << 0)                /* Watchdog Timer Restart */
 
-#define AT91_ST_PIMR            (AT91_ST + 0x04)        /* Period Interval Mode Register */
+#define AT91_ST_PIMR            0x04                    /* Period Interval Mode Register */
 #define         AT91_ST_PIV             (0xffff <<  0)          /* Period Interval Value */
 
-#define AT91_ST_WDMR            (AT91_ST + 0x08)        /* Watchdog Mode Register */
+#define AT91_ST_WDMR            0x08                    /* Watchdog Mode Register */
 #define         AT91_ST_WDV             (0xffff <<  0)          /* Watchdog Counter Value */
 #define         AT91_ST_RSTEN           (1      << 16)          /* Reset Enable */
 #define         AT91_ST_EXTEN           (1      << 17)          /* External Signal Assertion Enable */
 
-#define AT91_ST_RTMR            (AT91_ST + 0x0c)        /* Real-time Mode Register */
+#define AT91_ST_RTMR            0x0c                    /* Real-time Mode Register */
 #define         AT91_ST_RTPRES          (0xffff <<  0)          /* Real-time Prescalar Value */
 
-#define AT91_ST_SR              (AT91_ST + 0x10)        /* Status Register */
+#define AT91_ST_SR              0x10                    /* Status Register */
 #define         AT91_ST_PITS            (1 << 0)                /* Period Interval Timer Status */
 #define         AT91_ST_WDOVF           (1 << 1)                /* Watchdog Overflow */
 #define         AT91_ST_RTTINC          (1 << 2)                /* Real-time Timer Increment */
 #define         AT91_ST_ALMS            (1 << 3)                /* Alarm Status */
 
-#define AT91_ST_IER             (AT91_ST + 0x14)        /* Interrupt Enable Register */
-#define AT91_ST_IDR             (AT91_ST + 0x18)        /* Interrupt Disable Register */
-#define AT91_ST_IMR             (AT91_ST + 0x1c)        /* Interrupt Mask Register */
+#define AT91_ST_IER             0x14                    /* Interrupt Enable Register */
+#define AT91_ST_IDR             0x18                    /* Interrupt Disable Register */
+#define AT91_ST_IMR             0x1c                    /* Interrupt Mask Register */
 
-#define AT91_ST_RTAR            (AT91_ST + 0x20)        /* Real-time Alarm Register */
+#define AT91_ST_RTAR            0x20                    /* Real-time Alarm Register */
 #define         AT91_ST_ALMV            (0xfffff << 0)          /* Alarm Value */
 
-#define AT91_ST_CRTR            (AT91_ST + 0x24)        /* Current Real-time Register */
+#define AT91_ST_CRTR            0x24                    /* Current Real-time Register */
 #define         AT91_ST_CRTV            (0xfffff << 0)          /* Current Real-Time Value */
 
 #endif
diff --git a/arch/arm/mach-at91/include/mach/at91cap9.h b/arch/arm/mach-at91/include/mach/at91cap9.h
deleted file mode 100644
index 61d952902f2..00000000000
--- a/arch/arm/mach-at91/include/mach/at91cap9.h
+++ /dev/null
@@ -1,122 +0,0 @@
-/*
- * arch/arm/mach-at91/include/mach/at91cap9.h
- *
- *  Copyright (C) 2007 Stelian Pop <stelian.pop@leadtechdesign.com>
- *  Copyright (C) 2007 Lead Tech Design <www.leadtechdesign.com>
- *  Copyright (C) 2007 Atmel Corporation.
- *
- * Common definitions.
- * Based on AT91CAP9 datasheet revision B (Preliminary).
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-
-#ifndef AT91CAP9_H
-#define AT91CAP9_H
-
-/*
- * Peripheral identifiers/interrupts.
- */
-#define AT91CAP9_ID_PIOABCD     2       /* Parallel IO Controller A, B, C and D */
-#define AT91CAP9_ID_MPB0        3       /* MP Block Peripheral 0 */
-#define AT91CAP9_ID_MPB1        4       /* MP Block Peripheral 1 */
-#define AT91CAP9_ID_MPB2        5       /* MP Block Peripheral 2 */
-#define AT91CAP9_ID_MPB3        6       /* MP Block Peripheral 3 */
-#define AT91CAP9_ID_MPB4        7       /* MP Block Peripheral 4 */
-#define AT91CAP9_ID_US0         8       /* USART 0 */
-#define AT91CAP9_ID_US1         9       /* USART 1 */
-#define AT91CAP9_ID_US2         10      /* USART 2 */
-#define AT91CAP9_ID_MCI0        11      /* Multimedia Card Interface 0 */
-#define AT91CAP9_ID_MCI1        12      /* Multimedia Card Interface 1 */
-#define AT91CAP9_ID_CAN         13      /* CAN */
-#define AT91CAP9_ID_TWI         14      /* Two-Wire Interface */
-#define AT91CAP9_ID_SPI0        15      /* Serial Peripheral Interface 0 */
-#define AT91CAP9_ID_SPI1        16      /* Serial Peripheral Interface 0 */
-#define AT91CAP9_ID_SSC0        17      /* Serial Synchronous Controller 0 */
-#define AT91CAP9_ID_SSC1        18      /* Serial Synchronous Controller 1 */
-#define AT91CAP9_ID_AC97C       19      /* AC97 Controller */
-#define AT91CAP9_ID_TCB         20      /* Timer Counter 0, 1 and 2 */
-#define AT91CAP9_ID_PWMC        21      /* Pulse Width Modulation Controller */
-#define AT91CAP9_ID_EMAC        22      /* Ethernet */
-#define AT91CAP9_ID_AESTDES     23      /* Advanced Encryption Standard, Triple DES */
-#define AT91CAP9_ID_ADC         24      /* Analog-to-Digital Converter */
-#define AT91CAP9_ID_ISI         25      /* Image Sensor Interface */
-#define AT91CAP9_ID_LCDC        26      /* LCD Controller */
-#define AT91CAP9_ID_DMA         27      /* DMA Controller */
-#define AT91CAP9_ID_UDPHS       28      /* USB High Speed Device Port */
-#define AT91CAP9_ID_UHP         29      /* USB Host Port */
-#define AT91CAP9_ID_IRQ0        30      /* Advanced Interrupt Controller (IRQ0) */
-#define AT91CAP9_ID_IRQ1        31      /* Advanced Interrupt Controller (IRQ1) */
-
-/*
- * User Peripheral physical base addresses.
- */
-#define AT91CAP9_BASE_UDPHS             0xfff78000
-#define AT91CAP9_BASE_TCB0              0xfff7c000
-#define AT91CAP9_BASE_TC0               0xfff7c000
-#define AT91CAP9_BASE_TC1               0xfff7c040
-#define AT91CAP9_BASE_TC2               0xfff7c080
-#define AT91CAP9_BASE_MCI0              0xfff80000
-#define AT91CAP9_BASE_MCI1              0xfff84000
-#define AT91CAP9_BASE_TWI               0xfff88000
-#define AT91CAP9_BASE_US0               0xfff8c000
-#define AT91CAP9_BASE_US1               0xfff90000
-#define AT91CAP9_BASE_US2               0xfff94000
-#define AT91CAP9_BASE_SSC0              0xfff98000
-#define AT91CAP9_BASE_SSC1              0xfff9c000
-#define AT91CAP9_BASE_AC97C             0xfffa0000
-#define AT91CAP9_BASE_SPI0              0xfffa4000
-#define AT91CAP9_BASE_SPI1              0xfffa8000
-#define AT91CAP9_BASE_CAN               0xfffac000
-#define AT91CAP9_BASE_PWMC              0xfffb8000
-#define AT91CAP9_BASE_EMAC              0xfffbc000
-#define AT91CAP9_BASE_ADC               0xfffc0000
-#define AT91CAP9_BASE_ISI               0xfffc4000
-
-/*
- * System Peripherals (offset from AT91_BASE_SYS)
- */
-#define AT91_BCRAMC     (0xffffe400 - AT91_BASE_SYS)
-#define AT91_DDRSDRC0   (0xffffe600 - AT91_BASE_SYS)
-#define AT91_MATRIX     (0xffffea00 - AT91_BASE_SYS)
-#define AT91_PMC        (0xfffffc00 - AT91_BASE_SYS)
-#define AT91_GPBR       (cpu_is_at91cap9_revB() ?       \
-                        (0xfffffd50 - AT91_BASE_SYS) :  \
-                        (0xfffffd60 - AT91_BASE_SYS))
-
-#define AT91CAP9_BASE_ECC       0xffffe200
-#define AT91CAP9_BASE_DMA       0xffffec00
-#define AT91CAP9_BASE_SMC       0xffffe800
-#define AT91CAP9_BASE_DBGU      AT91_BASE_DBGU1
-#define AT91CAP9_BASE_PIOA      0xfffff200
-#define AT91CAP9_BASE_PIOB      0xfffff400
-#define AT91CAP9_BASE_PIOC      0xfffff600
-#define AT91CAP9_BASE_PIOD      0xfffff800
-#define AT91CAP9_BASE_RSTC      0xfffffd00
-#define AT91CAP9_BASE_SHDWC     0xfffffd10
-#define AT91CAP9_BASE_RTT       0xfffffd20
-#define AT91CAP9_BASE_PIT       0xfffffd30
-#define AT91CAP9_BASE_WDT       0xfffffd40
-
-#define AT91_USART0     AT91CAP9_BASE_US0
-#define AT91_USART1     AT91CAP9_BASE_US1
-#define AT91_USART2     AT91CAP9_BASE_US2
-
-
-/*
- * Internal Memory.
- */
-#define AT91CAP9_SRAM_BASE      0x00100000      /* Internal SRAM base address */
-#define AT91CAP9_SRAM_SIZE      (32 * SZ_1K)    /* Internal SRAM size (32Kb) */
-
-#define AT91CAP9_ROM_BASE       0x00400000      /* Internal ROM base address */
-#define AT91CAP9_ROM_SIZE       (32 * SZ_1K)    /* Internal ROM size (32Kb) */
-
-#define AT91CAP9_LCDC_BASE      0x00500000      /* LCD Controller */
-#define AT91CAP9_UDPHS_FIFO     0x00600000      /* USB High Speed Device Port */
-#define AT91CAP9_UHP_BASE       0x00700000      /* USB Host controller */
-
-#endif
diff --git a/arch/arm/mach-at91/include/mach/at91cap9_matrix.h b/arch/arm/mach-at91/include/mach/at91cap9_matrix.h
deleted file mode 100644
index 4b9d4aff4b4..00000000000
--- a/arch/arm/mach-at91/include/mach/at91cap9_matrix.h
+++ /dev/null
@@ -1,137 +0,0 @@
-/*
- * arch/arm/mach-at91/include/mach/at91cap9_matrix.h
- *
- *  Copyright (C) 2007 Stelian Pop <stelian.pop@leadtechdesign.com>
- *  Copyright (C) 2007 Lead Tech Design <www.leadtechdesign.com>
- *  Copyright (C) 2006 Atmel Corporation.
- *
- * Memory Controllers (MATRIX, EBI) - System peripherals registers.
- * Based on AT91CAP9 datasheet revision B (Preliminary).
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-
-#ifndef AT91CAP9_MATRIX_H
-#define AT91CAP9_MATRIX_H
-
-#define AT91_MATRIX_MCFG0       (AT91_MATRIX + 0x00)    /* Master Configuration Register 0 */
-#define AT91_MATRIX_MCFG1       (AT91_MATRIX + 0x04)    /* Master Configuration Register 1 */
-#define AT91_MATRIX_MCFG2       (AT91_MATRIX + 0x08)    /* Master Configuration Register 2 */
-#define AT91_MATRIX_MCFG3       (AT91_MATRIX + 0x0C)    /* Master Configuration Register 3 */
-#define AT91_MATRIX_MCFG4       (AT91_MATRIX + 0x10)    /* Master Configuration Register 4 */
-#define AT91_MATRIX_MCFG5       (AT91_MATRIX + 0x14)    /* Master Configuration Register 5 */
-#define AT91_MATRIX_MCFG6       (AT91_MATRIX + 0x18)    /* Master Configuration Register 6 */
-#define AT91_MATRIX_MCFG7       (AT91_MATRIX + 0x1C)    /* Master Configuration Register 7 */
-#define AT91_MATRIX_MCFG8       (AT91_MATRIX + 0x20)    /* Master Configuration Register 8 */
-#define AT91_MATRIX_MCFG9       (AT91_MATRIX + 0x24)    /* Master Configuration Register 9 */
-#define AT91_MATRIX_MCFG10      (AT91_MATRIX + 0x28)    /* Master Configuration Register 10 */
-#define AT91_MATRIX_MCFG11      (AT91_MATRIX + 0x2C)    /* Master Configuration Register 11 */
-#define         AT91_MATRIX_ULBT        (7 << 0)        /* Undefined Length Burst Type */
-#define                 AT91_MATRIX_ULBT_INFINITE       (0 << 0)
-#define                 AT91_MATRIX_ULBT_SINGLE         (1 << 0)
-#define                 AT91_MATRIX_ULBT_FOUR           (2 << 0)
-#define                 AT91_MATRIX_ULBT_EIGHT          (3 << 0)
-#define                 AT91_MATRIX_ULBT_SIXTEEN        (4 << 0)
-
-#define AT91_MATRIX_SCFG0       (AT91_MATRIX + 0x40)    /* Slave Configuration Register 0 */
-#define AT91_MATRIX_SCFG1       (AT91_MATRIX + 0x44)    /* Slave Configuration Register 1 */
-#define AT91_MATRIX_SCFG2       (AT91_MATRIX + 0x48)    /* Slave Configuration Register 2 */
-#define AT91_MATRIX_SCFG3       (AT91_MATRIX + 0x4C)    /* Slave Configuration Register 3 */
-#define AT91_MATRIX_SCFG4       (AT91_MATRIX + 0x50)    /* Slave Configuration Register 4 */
-#define AT91_MATRIX_SCFG5       (AT91_MATRIX + 0x54)    /* Slave Configuration Register 5 */
-#define AT91_MATRIX_SCFG6       (AT91_MATRIX + 0x58)    /* Slave Configuration Register 6 */
-#define AT91_MATRIX_SCFG7       (AT91_MATRIX + 0x5C)    /* Slave Configuration Register 7 */
-#define AT91_MATRIX_SCFG8       (AT91_MATRIX + 0x60)    /* Slave Configuration Register 8 */
-#define AT91_MATRIX_SCFG9       (AT91_MATRIX + 0x64)    /* Slave Configuration Register 9 */
-#define         AT91_MATRIX_SLOT_CYCLE          (0xff << 0)     /* Maximum Number of Allowed Cycles for a Burst */
-#define         AT91_MATRIX_DEFMSTR_TYPE        (3    << 16)    /* Default Master Type */
-#define                 AT91_MATRIX_DEFMSTR_TYPE_NONE   (0 << 16)
-#define                 AT91_MATRIX_DEFMSTR_TYPE_LAST   (1 << 16)
-#define                 AT91_MATRIX_DEFMSTR_TYPE_FIXED  (2 << 16)
-#define         AT91_MATRIX_FIXED_DEFMSTR       (0xf  << 18)    /* Fixed Index of Default Master */
-#define         AT91_MATRIX_ARBT                (3    << 24)    /* Arbitration Type */
-#define                 AT91_MATRIX_ARBT_ROUND_ROBIN    (0 << 24)
-#define                 AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24)
-
-#define AT91_MATRIX_PRAS0       (AT91_MATRIX + 0x80)    /* Priority Register A for Slave 0 */
-#define AT91_MATRIX_PRBS0       (AT91_MATRIX + 0x84)    /* Priority Register B for Slave 0 */
-#define AT91_MATRIX_PRAS1       (AT91_MATRIX + 0x88)    /* Priority Register A for Slave 1 */
-#define AT91_MATRIX_PRBS1       (AT91_MATRIX + 0x8C)    /* Priority Register B for Slave 1 */
-#define AT91_MATRIX_PRAS2       (AT91_MATRIX + 0x90)    /* Priority Register A for Slave 2 */
-#define AT91_MATRIX_PRBS2       (AT91_MATRIX + 0x94)    /* Priority Register B for Slave 2 */
-#define AT91_MATRIX_PRAS3       (AT91_MATRIX + 0x98)    /* Priority Register A for Slave 3 */
-#define AT91_MATRIX_PRBS3       (AT91_MATRIX + 0x9C)    /* Priority Register B for Slave 3 */
-#define AT91_MATRIX_PRAS4       (AT91_MATRIX + 0xA0)    /* Priority Register A for Slave 4 */
-#define AT91_MATRIX_PRBS4       (AT91_MATRIX + 0xA4)    /* Priority Register B for Slave 4 */
-#define AT91_MATRIX_PRAS5       (AT91_MATRIX + 0xA8)    /* Priority Register A for Slave 5 */
-#define AT91_MATRIX_PRBS5       (AT91_MATRIX + 0xAC)    /* Priority Register B for Slave 5 */
-#define AT91_MATRIX_PRAS6       (AT91_MATRIX + 0xB0)    /* Priority Register A for Slave 6 */
-#define AT91_MATRIX_PRBS6       (AT91_MATRIX + 0xB4)    /* Priority Register B for Slave 6 */
-#define AT91_MATRIX_PRAS7       (AT91_MATRIX + 0xB8)    /* Priority Register A for Slave 7 */
-#define AT91_MATRIX_PRBS7       (AT91_MATRIX + 0xBC)    /* Priority Register B for Slave 7 */
-#define AT91_MATRIX_PRAS8       (AT91_MATRIX + 0xC0)    /* Priority Register A for Slave 8 */
-#define AT91_MATRIX_PRBS8       (AT91_MATRIX + 0xC4)    /* Priority Register B for Slave 8 */
-#define AT91_MATRIX_PRAS9       (AT91_MATRIX + 0xC8)    /* Priority Register A for Slave 9 */
-#define AT91_MATRIX_PRBS9       (AT91_MATRIX + 0xCC)    /* Priority Register B for Slave 9 */
-#define         AT91_MATRIX_M0PR                (3 << 0)        /* Master 0 Priority */
-#define         AT91_MATRIX_M1PR                (3 << 4)        /* Master 1 Priority */
-#define         AT91_MATRIX_M2PR                (3 << 8)        /* Master 2 Priority */
-#define         AT91_MATRIX_M3PR                (3 << 12)       /* Master 3 Priority */
-#define         AT91_MATRIX_M4PR                (3 << 16)       /* Master 4 Priority */
-#define         AT91_MATRIX_M5PR                (3 << 20)       /* Master 5 Priority */
-#define         AT91_MATRIX_M6PR                (3 << 24)       /* Master 6 Priority */
-#define         AT91_MATRIX_M7PR                (3 << 28)       /* Master 7 Priority */
-#define         AT91_MATRIX_M8PR                (3 << 0)        /* Master 8 Priority (in Register B) */
-#define         AT91_MATRIX_M9PR                (3 << 4)        /* Master 9 Priority (in Register B) */
-#define         AT91_MATRIX_M10PR               (3 << 8)        /* Master 10 Priority (in Register B) */
-#define         AT91_MATRIX_M11PR               (3 << 12)       /* Master 11 Priority (in Register B) */
-
-#define AT91_MATRIX_MRCR        (AT91_MATRIX + 0x100)   /* Master Remap Control Register */
-#define         AT91_MATRIX_RCB0                (1 << 0)        /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
-#define         AT91_MATRIX_RCB1                (1 << 1)        /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
-#define         AT91_MATRIX_RCB2                (1 << 2)
-#define         AT91_MATRIX_RCB3                (1 << 3)
-#define         AT91_MATRIX_RCB4                (1 << 4)
-#define         AT91_MATRIX_RCB5                (1 << 5)
-#define         AT91_MATRIX_RCB6                (1 << 6)
-#define         AT91_MATRIX_RCB7                (1 << 7)
-#define         AT91_MATRIX_RCB8                (1 << 8)
-#define         AT91_MATRIX_RCB9                (1 << 9)
-#define         AT91_MATRIX_RCB10               (1 << 10)
-#define         AT91_MATRIX_RCB11               (1 << 11)
-
-#define AT91_MPBS0_SFR          (AT91_MATRIX + 0x114)   /* MPBlock Slave 0 Special Function Register */
-#define AT91_MPBS1_SFR          (AT91_MATRIX + 0x11C)   /* MPBlock Slave 1 Special Function Register */
-
-#define AT91_MATRIX_UDPHS       (AT91_MATRIX + 0x118)   /* USBHS Special Function Register [AT91CAP9 only] */
-#define         AT91_MATRIX_SELECT_UDPHS        (0 << 31)       /* select High Speed UDP */
-#define         AT91_MATRIX_SELECT_UDP          (1 << 31)       /* select standard UDP */
-#define         AT91_MATRIX_UDPHS_BYPASS_LOCK   (1 << 30)       /* bypass lock bit */
-
-#define AT91_MATRIX_EBICSA      (AT91_MATRIX + 0x120)   /* EBI Chip Select Assignment Register */
-#define         AT91_MATRIX_EBI_CS1A            (1 << 1)        /* Chip Select 1 Assignment */
-#define                 AT91_MATRIX_EBI_CS1A_SMC                (0 << 1)
-#define                 AT91_MATRIX_EBI_CS1A_BCRAMC             (1 << 1)
-#define         AT91_MATRIX_EBI_CS3A            (1 << 3)        /* Chip Select 3 Assignment */
-#define                 AT91_MATRIX_EBI_CS3A_SMC                (0 << 3)
-#define                 AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA     (1 << 3)
-#define         AT91_MATRIX_EBI_CS4A            (1 << 4)        /* Chip Select 4 Assignment */
-#define                 AT91_MATRIX_EBI_CS4A_SMC                (0 << 4)
-#define                 AT91_MATRIX_EBI_CS4A_SMC_CF1            (1 << 4)
-#define         AT91_MATRIX_EBI_CS5A            (1 << 5)        /* Chip Select 5 Assignment */
-#define                 AT91_MATRIX_EBI_CS5A_SMC                (0 << 5)
-#define                 AT91_MATRIX_EBI_CS5A_SMC_CF2            (1 << 5)
-#define         AT91_MATRIX_EBI_DBPUC           (1 << 8)        /* Data Bus Pull-up Configuration */
-#define         AT91_MATRIX_EBI_DQSPDC          (1 << 9)        /* Data Qualifier Strobe Pull-Down Configuration */
-#define         AT91_MATRIX_EBI_VDDIOMSEL       (1 << 16)       /* Memory voltage selection */
-#define                 AT91_MATRIX_EBI_VDDIOMSEL_1_8V          (0 << 16)
-#define                 AT91_MATRIX_EBI_VDDIOMSEL_3_3V          (1 << 16)
-
-#define AT91_MPBS2_SFR          (AT91_MATRIX + 0x12C)   /* MPBlock Slave 2 Special Function Register */
-#define AT91_MPBS3_SFR          (AT91_MATRIX + 0x130)   /* MPBlock Slave 3 Special Function Register */
-#define AT91_APB_SFR            (AT91_MATRIX + 0x134)   /* APB Bridge Special Function Register */
-
-#endif
diff --git a/arch/arm/mach-at91/include/mach/at91rm9200.h b/arch/arm/mach-at91/include/mach/at91rm9200.h
index bacb5114181..603e6aac2a4 100644
--- a/arch/arm/mach-at91/include/mach/at91rm9200.h
+++ b/arch/arm/mach-at91/include/mach/at91rm9200.h
@@ -77,26 +77,22 @@
 
 
 /*
- * System Peripherals (offset from AT91_BASE_SYS)
+ * System Peripherals
  */
-#define AT91_PMC        (0xfffffc00 - AT91_BASE_SYS)    /* Power Management Controller */
-#define AT91_ST         (0xfffffd00 - AT91_BASE_SYS)    /* System Timer */
-#define AT91_MC         (0xffffff00 - AT91_BASE_SYS)    /* Memory Controllers */
-
 #define AT91RM9200_BASE_DBGU    AT91_BASE_DBGU0 /* Debug Unit */
 #define AT91RM9200_BASE_PIOA    0xfffff400      /* PIO Controller A */
 #define AT91RM9200_BASE_PIOB    0xfffff600      /* PIO Controller B */
 #define AT91RM9200_BASE_PIOC    0xfffff800      /* PIO Controller C */
 #define AT91RM9200_BASE_PIOD    0xfffffa00      /* PIO Controller D */
+#define AT91RM9200_BASE_ST      0xfffffd00      /* System Timer */
 #define AT91RM9200_BASE_RTC     0xfffffe00      /* Real-Time Clock */
+#define AT91RM9200_BASE_MC      0xffffff00      /* Memory Controllers */
 
 #define AT91_USART0     AT91RM9200_BASE_US0
 #define AT91_USART1     AT91RM9200_BASE_US1
 #define AT91_USART2     AT91RM9200_BASE_US2
 #define AT91_USART3     AT91RM9200_BASE_US3
 
-#define AT91_MATRIX     0       /* not supported */
-
 /*
  * Internal Memory.
  */
diff --git a/arch/arm/mach-at91/include/mach/at91rm9200_mc.h b/arch/arm/mach-at91/include/mach/at91rm9200_mc.h
index d34e4ed8934..aeaadfb452a 100644
--- a/arch/arm/mach-at91/include/mach/at91rm9200_mc.h
+++ b/arch/arm/mach-at91/include/mach/at91rm9200_mc.h
@@ -17,10 +17,10 @@
 #define AT91RM9200_MC_H
 
 /* Memory Controller */
-#define AT91_MC_RCR             (AT91_MC + 0x00)        /* MC Remap Control Register */
+#define AT91_MC_RCR             0x00                    /* MC Remap Control Register */
 #define         AT91_MC_RCB             (1 <<  0)               /* Remap Command Bit */
 
-#define AT91_MC_ASR             (AT91_MC + 0x04)        /* MC Abort Status Register */
+#define AT91_MC_ASR             0x04                    /* MC Abort Status Register */
 #define         AT91_MC_UNADD           (1 <<  0)               /* Undefined Address Abort Status */
 #define         AT91_MC_MISADD          (1 <<  1)               /* Misaligned Address Abort Status */
 #define         AT91_MC_ABTSZ           (3 <<  8)               /* Abort Size Status */
@@ -40,16 +40,16 @@
 #define         AT91_MC_SVMST2          (1 << 26)               /* Saved UHP Abort Source */
 #define         AT91_MC_SVMST3          (1 << 27)               /* Saved EMAC Abort Source */
 
-#define AT91_MC_AASR            (AT91_MC + 0x08)        /* MC Abort Address Status Register */
+#define AT91_MC_AASR            0x08                    /* MC Abort Address Status Register */
 
-#define AT91_MC_MPR             (AT91_MC + 0x0c)        /* MC Master Priority Register */
+#define AT91_MC_MPR             0x0c                    /* MC Master Priority Register */
 #define         AT91_MPR_MSTP0          (7 <<  0)               /* ARM920T Priority */
 #define         AT91_MPR_MSTP1          (7 <<  4)               /* PDC Priority */
 #define         AT91_MPR_MSTP2          (7 <<  8)               /* UHP Priority */
 #define         AT91_MPR_MSTP3          (7 << 12)               /* EMAC Priority */
 
 /* External Bus Interface (EBI) registers */
-#define AT91_EBI_CSA            (AT91_MC + 0x60)        /* Chip Select Assignment Register */
+#define AT91_EBI_CSA            0x60                    /* Chip Select Assignment Register */
 #define         AT91_EBI_CS0A           (1 << 0)                /* Chip Select 0 Assignment */
 #define                 AT91_EBI_CS0A_SMC               (0 << 0)
 #define                 AT91_EBI_CS0A_BFC               (1 << 0)
@@ -66,7 +66,7 @@
 #define         AT91_EBI_DBPUC          (1 << 0)                /* Data Bus Pull-Up Configuration */
 
 /* Static Memory Controller (SMC) registers */
-#define AT91_SMC_CSR(n)         (AT91_MC + 0x70 + ((n) * 4))/* SMC Chip Select Register */
+#define AT91_SMC_CSR(n)         (0x70 + ((n) * 4))      /* SMC Chip Select Register */
 #define         AT91_SMC_NWS            (0x7f <<  0)            /* Number of Wait States */
 #define                 AT91_SMC_NWS_(x)        ((x) << 0)
 #define         AT91_SMC_WSEN           (1    <<  7)            /* Wait State Enable */
@@ -87,52 +87,8 @@
 #define         AT91_SMC_RWHOLD         (7 << 28)               /* Read & Write Signal Hold Time */
 #define                 AT91_SMC_RWHOLD_(x)     ((x) << 28)
 
-/* SDRAM Controller registers */
-#define AT91_SDRAMC_MR          (AT91_MC + 0x90)        /* Mode Register */
-#define         AT91_SDRAMC_MODE        (0xf << 0)              /* Command Mode */
-#define                 AT91_SDRAMC_MODE_NORMAL         (0 << 0)
-#define                 AT91_SDRAMC_MODE_NOP            (1 << 0)
-#define                 AT91_SDRAMC_MODE_PRECHARGE      (2 << 0)
-#define                 AT91_SDRAMC_MODE_LMR            (3 << 0)
-#define                 AT91_SDRAMC_MODE_REFRESH        (4 << 0)
-#define         AT91_SDRAMC_DBW         (1   << 4)              /* Data Bus Width */
-#define                 AT91_SDRAMC_DBW_32      (0 << 4)
-#define                 AT91_SDRAMC_DBW_16      (1 << 4)
-
-#define AT91_SDRAMC_TR          (AT91_MC + 0x94)        /* Refresh Timer Register */
-#define         AT91_SDRAMC_COUNT       (0xfff << 0)            /* Refresh Timer Count */
-
-#define AT91_SDRAMC_CR          (AT91_MC + 0x98)        /* Configuration Register */
-#define         AT91_SDRAMC_NC          (3   <<  0)             /* Number of Column Bits */
-#define                 AT91_SDRAMC_NC_8        (0 << 0)
-#define                 AT91_SDRAMC_NC_9        (1 << 0)
-#define                 AT91_SDRAMC_NC_10       (2 << 0)
-#define                 AT91_SDRAMC_NC_11       (3 << 0)
-#define         AT91_SDRAMC_NR          (3   <<  2)             /* Number of Row Bits */
-#define                 AT91_SDRAMC_NR_11       (0 << 2)
-#define                 AT91_SDRAMC_NR_12       (1 << 2)
-#define                 AT91_SDRAMC_NR_13       (2 << 2)
-#define         AT91_SDRAMC_NB          (1   <<  4)             /* Number of Banks */
-#define                 AT91_SDRAMC_NB_2        (0 << 4)
-#define                 AT91_SDRAMC_NB_4        (1 << 4)
-#define         AT91_SDRAMC_CAS         (3   <<  5)             /* CAS Latency */
-#define                 AT91_SDRAMC_CAS_2       (2 << 5)
-#define         AT91_SDRAMC_TWR         (0xf <<  7)             /* Write Recovery Delay */
-#define         AT91_SDRAMC_TRC         (0xf << 11)             /* Row Cycle Delay */
-#define         AT91_SDRAMC_TRP         (0xf << 15)             /* Row Precharge Delay */
-#define         AT91_SDRAMC_TRCD        (0xf << 19)             /* Row to Column Delay */
-#define         AT91_SDRAMC_TRAS        (0xf << 23)             /* Active to Precharge Delay */
-#define         AT91_SDRAMC_TXSR        (0xf << 27)             /* Exit Self Refresh to Active Delay */
-
-#define AT91_SDRAMC_SRR         (AT91_MC + 0x9c)        /* Self Refresh Register */
-#define AT91_SDRAMC_LPR         (AT91_MC + 0xa0)        /* Low Power Register */
-#define AT91_SDRAMC_IER         (AT91_MC + 0xa4)        /* Interrupt Enable Register */
-#define AT91_SDRAMC_IDR         (AT91_MC + 0xa8)        /* Interrupt Disable Register */
-#define AT91_SDRAMC_IMR         (AT91_MC + 0xac)        /* Interrupt Mask Register */
-#define AT91_SDRAMC_ISR         (AT91_MC + 0xb0)        /* Interrupt Status Register */
-
 /* Burst Flash Controller register */
-#define AT91_BFC_MR             (AT91_MC + 0xc0)        /* Mode Register */
+#define AT91_BFC_MR             0xc0                    /* Mode Register */
 #define         AT91_BFC_BFCOM          (3   <<  0)             /* Burst Flash Controller Operating Mode */
 #define                 AT91_BFC_BFCOM_DISABLED (0 << 0)
 #define                 AT91_BFC_BFCOM_ASYNC    (1 << 0)
diff --git a/arch/arm/mach-at91/include/mach/at91rm9200_sdramc.h b/arch/arm/mach-at91/include/mach/at91rm9200_sdramc.h
new file mode 100644
index 00000000000..aa047f458f1
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/at91rm9200_sdramc.h
@@ -0,0 +1,63 @@
+/*
+ * arch/arm/mach-at91/include/mach/at91rm9200_sdramc.h
+ *
+ * Copyright (C) 2005 Ivan Kokshaysky
+ * Copyright (C) SAN People
+ *
+ * Memory Controllers (SDRAMC only) - System peripherals registers.
+ * Based on AT91RM9200 datasheet revision E.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef AT91RM9200_SDRAMC_H
+#define AT91RM9200_SDRAMC_H
+
+/* SDRAM Controller registers */
+#define AT91RM9200_SDRAMC_MR            0x90                    /* Mode Register */
+#define         AT91RM9200_SDRAMC_MODE  (0xf << 0)              /* Command Mode */
+#define                 AT91RM9200_SDRAMC_MODE_NORMAL           (0 << 0)
+#define                 AT91RM9200_SDRAMC_MODE_NOP              (1 << 0)
+#define                 AT91RM9200_SDRAMC_MODE_PRECHARGE        (2 << 0)
+#define                 AT91RM9200_SDRAMC_MODE_LMR              (3 << 0)
+#define                 AT91RM9200_SDRAMC_MODE_REFRESH  (4 << 0)
+#define         AT91RM9200_SDRAMC_DBW           (1   << 4)              /* Data Bus Width */
+#define                 AT91RM9200_SDRAMC_DBW_32        (0 << 4)
+#define                 AT91RM9200_SDRAMC_DBW_16        (1 << 4)
+
+#define AT91RM9200_SDRAMC_TR            0x94                    /* Refresh Timer Register */
+#define         AT91RM9200_SDRAMC_COUNT (0xfff << 0)            /* Refresh Timer Count */
+
+#define AT91RM9200_SDRAMC_CR            0x98                    /* Configuration Register */
+#define         AT91RM9200_SDRAMC_NC            (3   <<  0)             /* Number of Column Bits */
+#define                 AT91RM9200_SDRAMC_NC_8  (0 << 0)
+#define                 AT91RM9200_SDRAMC_NC_9  (1 << 0)
+#define                 AT91RM9200_SDRAMC_NC_10 (2 << 0)
+#define                 AT91RM9200_SDRAMC_NC_11 (3 << 0)
+#define         AT91RM9200_SDRAMC_NR            (3   <<  2)             /* Number of Row Bits */
+#define                 AT91RM9200_SDRAMC_NR_11 (0 << 2)
+#define                 AT91RM9200_SDRAMC_NR_12 (1 << 2)
+#define                 AT91RM9200_SDRAMC_NR_13 (2 << 2)
+#define         AT91RM9200_SDRAMC_NB            (1   <<  4)             /* Number of Banks */
+#define                 AT91RM9200_SDRAMC_NB_2  (0 << 4)
+#define                 AT91RM9200_SDRAMC_NB_4  (1 << 4)
+#define         AT91RM9200_SDRAMC_CAS           (3   <<  5)             /* CAS Latency */
+#define                 AT91RM9200_SDRAMC_CAS_2 (2 << 5)
+#define         AT91RM9200_SDRAMC_TWR           (0xf <<  7)             /* Write Recovery Delay */
+#define         AT91RM9200_SDRAMC_TRC           (0xf << 11)             /* Row Cycle Delay */
+#define         AT91RM9200_SDRAMC_TRP           (0xf << 15)             /* Row Precharge Delay */
+#define         AT91RM9200_SDRAMC_TRCD  (0xf << 19)             /* Row to Column Delay */
+#define         AT91RM9200_SDRAMC_TRAS  (0xf << 23)             /* Active to Precharge Delay */
+#define         AT91RM9200_SDRAMC_TXSR  (0xf << 27)             /* Exit Self Refresh to Active Delay */
+
+#define AT91RM9200_SDRAMC_SRR           0x9c                    /* Self Refresh Register */
+#define AT91RM9200_SDRAMC_LPR           0xa0                    /* Low Power Register */
+#define AT91RM9200_SDRAMC_IER           0xa4                    /* Interrupt Enable Register */
+#define AT91RM9200_SDRAMC_IDR           0xa8                    /* Interrupt Disable Register */
+#define AT91RM9200_SDRAMC_IMR           0xac                    /* Interrupt Mask Register */
+#define AT91RM9200_SDRAMC_ISR           0xb0                    /* Interrupt Status Register */
+
+#endif
diff --git a/arch/arm/mach-at91/include/mach/at91sam9260.h b/arch/arm/mach-at91/include/mach/at91sam9260.h
index fa5ca278ade..08ae9afd00f 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9260.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9260.h
@@ -78,15 +78,12 @@
 #define AT91SAM9260_BASE_ADC            0xfffe0000
 
 /*
- * System Peripherals (offset from AT91_BASE_SYS)
+ * System Peripherals
  */
-#define AT91_SDRAMC0    (0xffffea00 - AT91_BASE_SYS)
-#define AT91_MATRIX     (0xffffee00 - AT91_BASE_SYS)
-#define AT91_PMC        (0xfffffc00 - AT91_BASE_SYS)
-#define AT91_GPBR       (0xfffffd50 - AT91_BASE_SYS)
-
 #define AT91SAM9260_BASE_ECC    0xffffe800
+#define AT91SAM9260_BASE_SDRAMC 0xffffea00
 #define AT91SAM9260_BASE_SMC    0xffffec00
+#define AT91SAM9260_BASE_MATRIX 0xffffee00
 #define AT91SAM9260_BASE_DBGU   AT91_BASE_DBGU0
 #define AT91SAM9260_BASE_PIOA   0xfffff400
 #define AT91SAM9260_BASE_PIOB   0xfffff600
@@ -96,6 +93,7 @@
 #define AT91SAM9260_BASE_RTT    0xfffffd20
 #define AT91SAM9260_BASE_PIT    0xfffffd30
 #define AT91SAM9260_BASE_WDT    0xfffffd40
+#define AT91SAM9260_BASE_GPBR   0xfffffd50
 
 #define AT91_USART0     AT91SAM9260_BASE_US0
 #define AT91_USART1     AT91SAM9260_BASE_US1
@@ -115,6 +113,8 @@
 #define AT91SAM9260_SRAM0_SIZE  SZ_4K           /* Internal SRAM 0 size (4Kb) */
 #define AT91SAM9260_SRAM1_BASE  0x00300000      /* Internal SRAM 1 base address */
 #define AT91SAM9260_SRAM1_SIZE  SZ_4K           /* Internal SRAM 1 size (4Kb) */
+#define AT91SAM9260_SRAM_BASE   0x002FF000      /* Internal SRAM base address */
+#define AT91SAM9260_SRAM_SIZE   SZ_8K           /* Internal SRAM size (8Kb) */
 
 #define AT91SAM9260_UHP_BASE    0x00500000      /* USB Host controller */
 
@@ -128,6 +128,8 @@
 #define AT91SAM9G20_SRAM0_SIZE  SZ_16K          /* Internal SRAM 0 size (16Kb) */
 #define AT91SAM9G20_SRAM1_BASE  0x00300000      /* Internal SRAM 1 base address */
 #define AT91SAM9G20_SRAM1_SIZE  SZ_16K          /* Internal SRAM 1 size (16Kb) */
+#define AT91SAM9G20_SRAM_BASE   0x002FC000      /* Internal SRAM base address */
+#define AT91SAM9G20_SRAM_SIZE   SZ_32K          /* Internal SRAM size (32Kb) */
 
 #define AT91SAM9G20_UHP_BASE    0x00500000      /* USB Host controller */
 
diff --git a/arch/arm/mach-at91/include/mach/at91sam9260_matrix.h b/arch/arm/mach-at91/include/mach/at91sam9260_matrix.h
index 020f02ed921..f459df42062 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9260_matrix.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9260_matrix.h
@@ -15,12 +15,12 @@
 #ifndef AT91SAM9260_MATRIX_H
 #define AT91SAM9260_MATRIX_H
 
-#define AT91_MATRIX_MCFG0       (AT91_MATRIX + 0x00)    /* Master Configuration Register 0 */
-#define AT91_MATRIX_MCFG1       (AT91_MATRIX + 0x04)    /* Master Configuration Register 1 */
-#define AT91_MATRIX_MCFG2       (AT91_MATRIX + 0x08)    /* Master Configuration Register 2 */
-#define AT91_MATRIX_MCFG3       (AT91_MATRIX + 0x0C)    /* Master Configuration Register 3 */
-#define AT91_MATRIX_MCFG4       (AT91_MATRIX + 0x10)    /* Master Configuration Register 4 */
-#define AT91_MATRIX_MCFG5       (AT91_MATRIX + 0x14)    /* Master Configuration Register 5 */
+#define AT91_MATRIX_MCFG0       0x00                    /* Master Configuration Register 0 */
+#define AT91_MATRIX_MCFG1       0x04                    /* Master Configuration Register 1 */
+#define AT91_MATRIX_MCFG2       0x08                    /* Master Configuration Register 2 */
+#define AT91_MATRIX_MCFG3       0x0C                    /* Master Configuration Register 3 */
+#define AT91_MATRIX_MCFG4       0x10                    /* Master Configuration Register 4 */
+#define AT91_MATRIX_MCFG5       0x14                    /* Master Configuration Register 5 */
 #define         AT91_MATRIX_ULBT                (7 << 0)        /* Undefined Length Burst Type */
 #define                 AT91_MATRIX_ULBT_INFINITE       (0 << 0)
 #define                 AT91_MATRIX_ULBT_SINGLE         (1 << 0)
@@ -28,11 +28,11 @@
 #define                 AT91_MATRIX_ULBT_EIGHT          (3 << 0)
 #define                 AT91_MATRIX_ULBT_SIXTEEN        (4 << 0)
 
-#define AT91_MATRIX_SCFG0       (AT91_MATRIX + 0x40)    /* Slave Configuration Register 0 */
-#define AT91_MATRIX_SCFG1       (AT91_MATRIX + 0x44)    /* Slave Configuration Register 1 */
-#define AT91_MATRIX_SCFG2       (AT91_MATRIX + 0x48)    /* Slave Configuration Register 2 */
-#define AT91_MATRIX_SCFG3       (AT91_MATRIX + 0x4C)    /* Slave Configuration Register 3 */
-#define AT91_MATRIX_SCFG4       (AT91_MATRIX + 0x50)    /* Slave Configuration Register 4 */
+#define AT91_MATRIX_SCFG0       0x40                    /* Slave Configuration Register 0 */
+#define AT91_MATRIX_SCFG1       0x44                    /* Slave Configuration Register 1 */
+#define AT91_MATRIX_SCFG2       0x48                    /* Slave Configuration Register 2 */
+#define AT91_MATRIX_SCFG3       0x4C                    /* Slave Configuration Register 3 */
+#define AT91_MATRIX_SCFG4       0x50                    /* Slave Configuration Register 4 */
 #define         AT91_MATRIX_SLOT_CYCLE          (0xff <<  0)    /* Maximum Number of Allowed Cycles for a Burst */
 #define         AT91_MATRIX_DEFMSTR_TYPE        (3    << 16)    /* Default Master Type */
 #define                 AT91_MATRIX_DEFMSTR_TYPE_NONE   (0 << 16)
@@ -43,11 +43,11 @@
 #define                 AT91_MATRIX_ARBT_ROUND_ROBIN    (0 << 24)
 #define                 AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24)
 
-#define AT91_MATRIX_PRAS0       (AT91_MATRIX + 0x80)    /* Priority Register A for Slave 0 */
-#define AT91_MATRIX_PRAS1       (AT91_MATRIX + 0x88)    /* Priority Register A for Slave 1 */
-#define AT91_MATRIX_PRAS2       (AT91_MATRIX + 0x90)    /* Priority Register A for Slave 2 */
-#define AT91_MATRIX_PRAS3       (AT91_MATRIX + 0x98)    /* Priority Register A for Slave 3 */
-#define AT91_MATRIX_PRAS4       (AT91_MATRIX + 0xA0)    /* Priority Register A for Slave 4 */
+#define AT91_MATRIX_PRAS0       0x80                    /* Priority Register A for Slave 0 */
+#define AT91_MATRIX_PRAS1       0x88                    /* Priority Register A for Slave 1 */
+#define AT91_MATRIX_PRAS2       0x90                    /* Priority Register A for Slave 2 */
+#define AT91_MATRIX_PRAS3       0x98                    /* Priority Register A for Slave 3 */
+#define AT91_MATRIX_PRAS4       0xA0                    /* Priority Register A for Slave 4 */
 #define         AT91_MATRIX_M0PR                (3 << 0)        /* Master 0 Priority */
 #define         AT91_MATRIX_M1PR                (3 << 4)        /* Master 1 Priority */
 #define         AT91_MATRIX_M2PR                (3 << 8)        /* Master 2 Priority */
@@ -55,11 +55,11 @@
 #define         AT91_MATRIX_M4PR                (3 << 16)       /* Master 4 Priority */
 #define         AT91_MATRIX_M5PR                (3 << 20)       /* Master 5 Priority */
 
-#define AT91_MATRIX_MRCR        (AT91_MATRIX + 0x100)   /* Master Remap Control Register */
+#define AT91_MATRIX_MRCR        0x100                   /* Master Remap Control Register */
 #define         AT91_MATRIX_RCB0                (1 << 0)        /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
 #define         AT91_MATRIX_RCB1                (1 << 1)        /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
 
-#define AT91_MATRIX_EBICSA      (AT91_MATRIX + 0x11C)   /* EBI Chip Select Assignment Register */
+#define AT91_MATRIX_EBICSA      0x11C                   /* EBI Chip Select Assignment Register */
 #define         AT91_MATRIX_CS1A                (1 << 1)        /* Chip Select 1 Assignment */
 #define                 AT91_MATRIX_CS1A_SMC            (0 << 1)
 #define                 AT91_MATRIX_CS1A_SDRAMC         (1 << 1)
diff --git a/arch/arm/mach-at91/include/mach/at91sam9261.h b/arch/arm/mach-at91/include/mach/at91sam9261.h
index 7cde2d36570..44fbdc12ee6 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9261.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9261.h
@@ -63,14 +63,11 @@
 
 
 /*
- * System Peripherals (offset from AT91_BASE_SYS)
+ * System Peripherals
  */
-#define AT91_SDRAMC0    (0xffffea00 - AT91_BASE_SYS)
-#define AT91_MATRIX     (0xffffee00 - AT91_BASE_SYS)
-#define AT91_PMC        (0xfffffc00 - AT91_BASE_SYS)
-#define AT91_GPBR       (0xfffffd50 - AT91_BASE_SYS)
-
 #define AT91SAM9261_BASE_SMC    0xffffec00
+#define AT91SAM9261_BASE_MATRIX 0xffffee00
+#define AT91SAM9261_BASE_SDRAMC 0xffffea00
 #define AT91SAM9261_BASE_DBGU   AT91_BASE_DBGU0
 #define AT91SAM9261_BASE_PIOA   0xfffff400
 #define AT91SAM9261_BASE_PIOB   0xfffff600
@@ -80,6 +77,7 @@
 #define AT91SAM9261_BASE_RTT    0xfffffd20
 #define AT91SAM9261_BASE_PIT    0xfffffd30
 #define AT91SAM9261_BASE_WDT    0xfffffd40
+#define AT91SAM9261_BASE_GPBR   0xfffffd50
 
 #define AT91_USART0     AT91SAM9261_BASE_US0
 #define AT91_USART1     AT91SAM9261_BASE_US1
diff --git a/arch/arm/mach-at91/include/mach/at91sam9261_matrix.h b/arch/arm/mach-at91/include/mach/at91sam9261_matrix.h
index 69c6501915d..a50cdf8b8ca 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9261_matrix.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9261_matrix.h
@@ -15,15 +15,15 @@
 #ifndef AT91SAM9261_MATRIX_H
 #define AT91SAM9261_MATRIX_H
 
-#define AT91_MATRIX_MCFG        (AT91_MATRIX + 0x00)    /* Master Configuration Register */
+#define AT91_MATRIX_MCFG        0x00                    /* Master Configuration Register */
 #define         AT91_MATRIX_RCB0        (1 << 0)                /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
 #define         AT91_MATRIX_RCB1        (1 << 1)                /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
 
-#define AT91_MATRIX_SCFG0       (AT91_MATRIX + 0x04)    /* Slave Configuration Register 0 */
-#define AT91_MATRIX_SCFG1       (AT91_MATRIX + 0x08)    /* Slave Configuration Register 1 */
-#define AT91_MATRIX_SCFG2       (AT91_MATRIX + 0x0C)    /* Slave Configuration Register 2 */
-#define AT91_MATRIX_SCFG3       (AT91_MATRIX + 0x10)    /* Slave Configuration Register 3 */
-#define AT91_MATRIX_SCFG4       (AT91_MATRIX + 0x14)    /* Slave Configuration Register 4 */
+#define AT91_MATRIX_SCFG0       0x04                    /* Slave Configuration Register 0 */
+#define AT91_MATRIX_SCFG1       0x08                    /* Slave Configuration Register 1 */
+#define AT91_MATRIX_SCFG2       0x0C                    /* Slave Configuration Register 2 */
+#define AT91_MATRIX_SCFG3       0x10                    /* Slave Configuration Register 3 */
+#define AT91_MATRIX_SCFG4       0x14                    /* Slave Configuration Register 4 */
 #define         AT91_MATRIX_SLOT_CYCLE          (0xff << 0)     /* Maximum Number of Allowed Cycles for a Burst */
 #define         AT91_MATRIX_DEFMSTR_TYPE        (3    << 16)    /* Default Master Type */
 #define                 AT91_MATRIX_DEFMSTR_TYPE_NONE   (0 << 16)
@@ -31,7 +31,7 @@
 #define                 AT91_MATRIX_DEFMSTR_TYPE_FIXED  (2 << 16)
 #define         AT91_MATRIX_FIXED_DEFMSTR       (7    << 18)    /* Fixed Index of Default Master */
 
-#define AT91_MATRIX_TCR         (AT91_MATRIX + 0x24)    /* TCM Configuration Register */
+#define AT91_MATRIX_TCR         0x24                    /* TCM Configuration Register */
 #define         AT91_MATRIX_ITCM_SIZE           (0xf << 0)      /* Size of ITCM enabled memory block */
 #define                 AT91_MATRIX_ITCM_0              (0 << 0)
 #define                 AT91_MATRIX_ITCM_16             (5 << 0)
@@ -43,7 +43,7 @@
 #define                 AT91_MATRIX_DTCM_32             (6 << 4)
 #define                 AT91_MATRIX_DTCM_64             (7 << 4)
 
-#define AT91_MATRIX_EBICSA      (AT91_MATRIX + 0x30)    /* EBI Chip Select Assignment Register */
+#define AT91_MATRIX_EBICSA      0x30                    /* EBI Chip Select Assignment Register */
 #define         AT91_MATRIX_CS1A                (1 << 1)        /* Chip Select 1 Assignment */
 #define                 AT91_MATRIX_CS1A_SMC            (0 << 1)
 #define                 AT91_MATRIX_CS1A_SDRAMC         (1 << 1)
@@ -58,7 +58,7 @@
 #define                 AT91_MATRIX_CS5A_SMC_CF2        (1 << 5)
 #define         AT91_MATRIX_DBPUC               (1 << 8)        /* Data Bus Pull-up Configuration */
 
-#define AT91_MATRIX_USBPUCR     (AT91_MATRIX + 0x34)    /* USB Pad Pull-Up Control Register */
+#define AT91_MATRIX_USBPUCR     0x34                    /* USB Pad Pull-Up Control Register */
 #define         AT91_MATRIX_USBPUCR_PUON        (1 << 30)       /* USB Device PAD Pull-up Enable */
 
 #endif
diff --git a/arch/arm/mach-at91/include/mach/at91sam9263.h b/arch/arm/mach-at91/include/mach/at91sam9263.h
index 5949abda962..d96cbb2e03c 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9263.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9263.h
@@ -72,18 +72,15 @@
 #define AT91SAM9263_BASE_2DGE           0xfffc8000
 
 /*
- * System Peripherals (offset from AT91_BASE_SYS)
+ * System Peripherals
  */
-#define AT91_SDRAMC0    (0xffffe200 - AT91_BASE_SYS)
-#define AT91_SDRAMC1    (0xffffe800 - AT91_BASE_SYS)
-#define AT91_MATRIX     (0xffffec00 - AT91_BASE_SYS)
-#define AT91_PMC        (0xfffffc00 - AT91_BASE_SYS)
-#define AT91_GPBR       (0xfffffd60 - AT91_BASE_SYS)
-
 #define AT91SAM9263_BASE_ECC0   0xffffe000
+#define AT91SAM9263_BASE_SDRAMC0 0xffffe200
 #define AT91SAM9263_BASE_SMC0   0xffffe400
 #define AT91SAM9263_BASE_ECC1   0xffffe600
+#define AT91SAM9263_BASE_SDRAMC1 0xffffe800
 #define AT91SAM9263_BASE_SMC1   0xffffea00
+#define AT91SAM9263_BASE_MATRIX 0xffffec00
 #define AT91SAM9263_BASE_DBGU   AT91_BASE_DBGU1
 #define AT91SAM9263_BASE_PIOA   0xfffff200
 #define AT91SAM9263_BASE_PIOB   0xfffff400
@@ -96,6 +93,7 @@
 #define AT91SAM9263_BASE_PIT    0xfffffd30
 #define AT91SAM9263_BASE_WDT    0xfffffd40
 #define AT91SAM9263_BASE_RTT1   0xfffffd50
+#define AT91SAM9263_BASE_GPBR   0xfffffd60
 
 #define AT91_USART0     AT91SAM9263_BASE_US0
 #define AT91_USART1     AT91SAM9263_BASE_US1
diff --git a/arch/arm/mach-at91/include/mach/at91sam9263_matrix.h b/arch/arm/mach-at91/include/mach/at91sam9263_matrix.h
index 9b3efd3eb2f..ebb5fdb565e 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9263_matrix.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9263_matrix.h
@@ -15,15 +15,15 @@
 #ifndef AT91SAM9263_MATRIX_H
 #define AT91SAM9263_MATRIX_H
 
-#define AT91_MATRIX_MCFG0       (AT91_MATRIX + 0x00)    /* Master Configuration Register 0 */
-#define AT91_MATRIX_MCFG1       (AT91_MATRIX + 0x04)    /* Master Configuration Register 1 */
-#define AT91_MATRIX_MCFG2       (AT91_MATRIX + 0x08)    /* Master Configuration Register 2 */
-#define AT91_MATRIX_MCFG3       (AT91_MATRIX + 0x0C)    /* Master Configuration Register 3 */
-#define AT91_MATRIX_MCFG4       (AT91_MATRIX + 0x10)    /* Master Configuration Register 4 */
-#define AT91_MATRIX_MCFG5       (AT91_MATRIX + 0x14)    /* Master Configuration Register 5 */
-#define AT91_MATRIX_MCFG6       (AT91_MATRIX + 0x18)    /* Master Configuration Register 6 */
-#define AT91_MATRIX_MCFG7       (AT91_MATRIX + 0x1C)    /* Master Configuration Register 7 */
-#define AT91_MATRIX_MCFG8       (AT91_MATRIX + 0x20)    /* Master Configuration Register 8 */
+#define AT91_MATRIX_MCFG0       0x00                    /* Master Configuration Register 0 */
+#define AT91_MATRIX_MCFG1       0x04                    /* Master Configuration Register 1 */
+#define AT91_MATRIX_MCFG2       0x08                    /* Master Configuration Register 2 */
+#define AT91_MATRIX_MCFG3       0x0C                    /* Master Configuration Register 3 */
+#define AT91_MATRIX_MCFG4       0x10                    /* Master Configuration Register 4 */
+#define AT91_MATRIX_MCFG5       0x14                    /* Master Configuration Register 5 */
+#define AT91_MATRIX_MCFG6       0x18                    /* Master Configuration Register 6 */
+#define AT91_MATRIX_MCFG7       0x1C                    /* Master Configuration Register 7 */
+#define AT91_MATRIX_MCFG8       0x20                    /* Master Configuration Register 8 */
 #define         AT91_MATRIX_ULBT        (7 << 0)        /* Undefined Length Burst Type */
 #define                 AT91_MATRIX_ULBT_INFINITE       (0 << 0)
 #define                 AT91_MATRIX_ULBT_SINGLE         (1 << 0)
@@ -31,14 +31,14 @@
 #define                 AT91_MATRIX_ULBT_EIGHT          (3 << 0)
 #define                 AT91_MATRIX_ULBT_SIXTEEN        (4 << 0)
 
-#define AT91_MATRIX_SCFG0       (AT91_MATRIX + 0x40)    /* Slave Configuration Register 0 */
-#define AT91_MATRIX_SCFG1       (AT91_MATRIX + 0x44)    /* Slave Configuration Register 1 */
-#define AT91_MATRIX_SCFG2       (AT91_MATRIX + 0x48)    /* Slave Configuration Register 2 */
-#define AT91_MATRIX_SCFG3       (AT91_MATRIX + 0x4C)    /* Slave Configuration Register 3 */
-#define AT91_MATRIX_SCFG4       (AT91_MATRIX + 0x50)    /* Slave Configuration Register 4 */
-#define AT91_MATRIX_SCFG5       (AT91_MATRIX + 0x54)    /* Slave Configuration Register 5 */
-#define AT91_MATRIX_SCFG6       (AT91_MATRIX + 0x58)    /* Slave Configuration Register 6 */
-#define AT91_MATRIX_SCFG7       (AT91_MATRIX + 0x5C)    /* Slave Configuration Register 7 */
+#define AT91_MATRIX_SCFG0       0x40                    /* Slave Configuration Register 0 */
+#define AT91_MATRIX_SCFG1       0x44                    /* Slave Configuration Register 1 */
+#define AT91_MATRIX_SCFG2       0x48                    /* Slave Configuration Register 2 */
+#define AT91_MATRIX_SCFG3       0x4C                    /* Slave Configuration Register 3 */
+#define AT91_MATRIX_SCFG4       0x50                    /* Slave Configuration Register 4 */
+#define AT91_MATRIX_SCFG5       0x54                    /* Slave Configuration Register 5 */
+#define AT91_MATRIX_SCFG6       0x58                    /* Slave Configuration Register 6 */
+#define AT91_MATRIX_SCFG7       0x5C                    /* Slave Configuration Register 7 */
 #define         AT91_MATRIX_SLOT_CYCLE          (0xff << 0)     /* Maximum Number of Allowed Cycles for a Burst */
 #define         AT91_MATRIX_DEFMSTR_TYPE        (3    << 16)    /* Default Master Type */
 #define                 AT91_MATRIX_DEFMSTR_TYPE_NONE   (0 << 16)
@@ -49,22 +49,22 @@
 #define                 AT91_MATRIX_ARBT_ROUND_ROBIN    (0 << 24)
 #define                 AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24)
 
-#define AT91_MATRIX_PRAS0       (AT91_MATRIX + 0x80)    /* Priority Register A for Slave 0 */
-#define AT91_MATRIX_PRBS0       (AT91_MATRIX + 0x84)    /* Priority Register B for Slave 0 */
-#define AT91_MATRIX_PRAS1       (AT91_MATRIX + 0x88)    /* Priority Register A for Slave 1 */
-#define AT91_MATRIX_PRBS1       (AT91_MATRIX + 0x8C)    /* Priority Register B for Slave 1 */
-#define AT91_MATRIX_PRAS2       (AT91_MATRIX + 0x90)    /* Priority Register A for Slave 2 */
-#define AT91_MATRIX_PRBS2       (AT91_MATRIX + 0x94)    /* Priority Register B for Slave 2 */
-#define AT91_MATRIX_PRAS3       (AT91_MATRIX + 0x98)    /* Priority Register A for Slave 3 */
-#define AT91_MATRIX_PRBS3       (AT91_MATRIX + 0x9C)    /* Priority Register B for Slave 3 */
-#define AT91_MATRIX_PRAS4       (AT91_MATRIX + 0xA0)    /* Priority Register A for Slave 4 */
-#define AT91_MATRIX_PRBS4       (AT91_MATRIX + 0xA4)    /* Priority Register B for Slave 4 */
-#define AT91_MATRIX_PRAS5       (AT91_MATRIX + 0xA8)    /* Priority Register A for Slave 5 */
-#define AT91_MATRIX_PRBS5       (AT91_MATRIX + 0xAC)    /* Priority Register B for Slave 5 */
-#define AT91_MATRIX_PRAS6       (AT91_MATRIX + 0xB0)    /* Priority Register A for Slave 6 */
-#define AT91_MATRIX_PRBS6       (AT91_MATRIX + 0xB4)    /* Priority Register B for Slave 6 */
-#define AT91_MATRIX_PRAS7       (AT91_MATRIX + 0xB8)    /* Priority Register A for Slave 7 */
-#define AT91_MATRIX_PRBS7       (AT91_MATRIX + 0xBC)    /* Priority Register B for Slave 7 */
+#define AT91_MATRIX_PRAS0       0x80                    /* Priority Register A for Slave 0 */
+#define AT91_MATRIX_PRBS0       0x84                    /* Priority Register B for Slave 0 */
+#define AT91_MATRIX_PRAS1       0x88                    /* Priority Register A for Slave 1 */
+#define AT91_MATRIX_PRBS1       0x8C                    /* Priority Register B for Slave 1 */
+#define AT91_MATRIX_PRAS2       0x90                    /* Priority Register A for Slave 2 */
+#define AT91_MATRIX_PRBS2       0x94                    /* Priority Register B for Slave 2 */
+#define AT91_MATRIX_PRAS3       0x98                    /* Priority Register A for Slave 3 */
+#define AT91_MATRIX_PRBS3       0x9C                    /* Priority Register B for Slave 3 */
+#define AT91_MATRIX_PRAS4       0xA0                    /* Priority Register A for Slave 4 */
+#define AT91_MATRIX_PRBS4       0xA4                    /* Priority Register B for Slave 4 */
+#define AT91_MATRIX_PRAS5       0xA8                    /* Priority Register A for Slave 5 */
+#define AT91_MATRIX_PRBS5       0xAC                    /* Priority Register B for Slave 5 */
+#define AT91_MATRIX_PRAS6       0xB0                    /* Priority Register A for Slave 6 */
+#define AT91_MATRIX_PRBS6       0xB4                    /* Priority Register B for Slave 6 */
+#define AT91_MATRIX_PRAS7       0xB8                    /* Priority Register A for Slave 7 */
+#define AT91_MATRIX_PRBS7       0xBC                    /* Priority Register B for Slave 7 */
 #define         AT91_MATRIX_M0PR                (3 << 0)        /* Master 0 Priority */
 #define         AT91_MATRIX_M1PR                (3 << 4)        /* Master 1 Priority */
 #define         AT91_MATRIX_M2PR                (3 << 8)        /* Master 2 Priority */
@@ -75,7 +75,7 @@
 #define         AT91_MATRIX_M7PR                (3 << 28)       /* Master 7 Priority */
 #define         AT91_MATRIX_M8PR                (3 << 0)        /* Master 8 Priority (in Register B) */
 
-#define AT91_MATRIX_MRCR        (AT91_MATRIX + 0x100)   /* Master Remap Control Register */
+#define AT91_MATRIX_MRCR        0x100                   /* Master Remap Control Register */
 #define         AT91_MATRIX_RCB0                (1 << 0)        /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
 #define         AT91_MATRIX_RCB1                (1 << 1)        /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
 #define         AT91_MATRIX_RCB2                (1 << 2)
@@ -86,7 +86,7 @@
 #define         AT91_MATRIX_RCB7                (1 << 7)
 #define         AT91_MATRIX_RCB8                (1 << 8)
 
-#define AT91_MATRIX_TCMR        (AT91_MATRIX + 0x114)   /* TCM Configuration Register */
+#define AT91_MATRIX_TCMR        0x114                   /* TCM Configuration Register */
 #define         AT91_MATRIX_ITCM_SIZE           (0xf << 0)      /* Size of ITCM enabled memory block */
 #define                 AT91_MATRIX_ITCM_0              (0 << 0)
 #define                 AT91_MATRIX_ITCM_16             (5 << 0)
@@ -96,7 +96,7 @@
 #define                 AT91_MATRIX_DTCM_16             (5 << 4)
 #define                 AT91_MATRIX_DTCM_32             (6 << 4)
 
-#define AT91_MATRIX_EBI0CSA     (AT91_MATRIX + 0x120)   /* EBI0 Chip Select Assignment Register */
+#define AT91_MATRIX_EBI0CSA     0x120                   /* EBI0 Chip Select Assignment Register */
 #define         AT91_MATRIX_EBI0_CS1A           (1 << 1)        /* Chip Select 1 Assignment */
 #define                 AT91_MATRIX_EBI0_CS1A_SMC               (0 << 1)
 #define                 AT91_MATRIX_EBI0_CS1A_SDRAMC            (1 << 1)
@@ -114,7 +114,7 @@
 #define                 AT91_MATRIX_EBI0_VDDIOMSEL_1_8V         (0 << 16)
 #define                 AT91_MATRIX_EBI0_VDDIOMSEL_3_3V         (1 << 16)
 
-#define AT91_MATRIX_EBI1CSA     (AT91_MATRIX + 0x124)   /* EBI1 Chip Select Assignment Register */
+#define AT91_MATRIX_EBI1CSA     0x124                   /* EBI1 Chip Select Assignment Register */
 #define         AT91_MATRIX_EBI1_CS1A           (1 << 1)        /* Chip Select 1 Assignment */
 #define                 AT91_MATRIX_EBI1_CS1A_SMC               (0 << 1)
 #define                 AT91_MATRIX_EBI1_CS1A_SDRAMC            (1 << 1)
diff --git a/arch/arm/mach-at91/include/mach/at91sam9_ddrsdr.h b/arch/arm/mach-at91/include/mach/at91sam9_ddrsdr.h
index e2f8da8ce5b..0210797abf2 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9_ddrsdr.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9_ddrsdr.h
@@ -59,7 +59,6 @@
 #define         AT91_DDRSDRC_TRP        (0xf << 16)             /* Row precharge delay */
 #define         AT91_DDRSDRC_TRRD       (0xf << 20)             /* Active BankA to BankB */
 #define         AT91_DDRSDRC_TWTR       (0x7 << 24)             /* Internal Write to Read delay */
-#define         AT91CAP9_DDRSDRC_TWTR   (1   << 24)             /* Internal Write to Read delay */
 #define         AT91_DDRSDRC_RED_WRRD   (0x1 << 27)             /* Reduce Write to Read Delay [SAM9 Only] */
 #define         AT91_DDRSDRC_TMRD       (0xf << 28)             /* Load mode to active/refresh delay */
 
@@ -76,7 +75,6 @@
 #define         AT91_DDRSDRC_TRTP       (0x7  << 12)            /* Read to Precharge delay */
 
 #define AT91_DDRSDRC_LPR        0x1C    /* Low Power Register */
-#define AT91CAP9_DDRSDRC_LPR    0x18    /* Low Power Register */
 #define         AT91_DDRSDRC_LPCB       (3 << 0)                /* Low-power Configurations */
 #define                 AT91_DDRSDRC_LPCB_DISABLE               0
 #define                 AT91_DDRSDRC_LPCB_SELF_REFRESH          1
@@ -94,11 +92,9 @@
 #define         AT91_DDRSDRC_UPD_MR     (3 << 20)        /* Update load mode register and extended mode register */
 
 #define AT91_DDRSDRC_MDR        0x20    /* Memory Device Register */
-#define AT91CAP9_DDRSDRC_MDR    0x1C    /* Memory Device Register */
 #define         AT91_DDRSDRC_MD         (3 << 0)                /* Memory Device Type */
 #define                 AT91_DDRSDRC_MD_SDR             0
 #define                 AT91_DDRSDRC_MD_LOW_POWER_SDR   1
-#define                 AT91CAP9_DDRSDRC_MD_DDR         2
 #define                 AT91_DDRSDRC_MD_LOW_POWER_DDR   3
 #define                 AT91_DDRSDRC_MD_DDR2            6       /* [SAM9 Only] */
 #define         AT91_DDRSDRC_DBW        (1 << 4)                /* Data Bus Width */
@@ -106,16 +102,10 @@
 #define                 AT91_DDRSDRC_DBW_16BITS         (1 <<  4)
 
 #define AT91_DDRSDRC_DLL        0x24    /* DLL Information Register */
-#define AT91CAP9_DDRSDRC_DLL    0x20    /* DLL Information Register */
 #define         AT91_DDRSDRC_MDINC      (1 << 0)                /* Master Delay increment */
 #define         AT91_DDRSDRC_MDDEC      (1 << 1)                /* Master Delay decrement */
 #define         AT91_DDRSDRC_MDOVF      (1 << 2)                /* Master Delay Overflow */
-#define         AT91CAP9_DDRSDRC_SDCOVF (1 << 3)                /* Slave Delay Correction Overflow */
-#define         AT91CAP9_DDRSDRC_SDCUDF (1 << 4)                /* Slave Delay Correction Underflow */
-#define         AT91CAP9_DDRSDRC_SDERF  (1 << 5)                /* Slave Delay Correction error */
 #define         AT91_DDRSDRC_MDVAL      (0xff <<  8)            /* Master Delay value */
-#define         AT91CAP9_DDRSDRC_SDVAL  (0xff << 16)            /* Slave Delay value */
-#define         AT91CAP9_DDRSDRC_SDCVAL (0xff << 24)            /* Slave Delay Correction value */
 
 #define AT91_DDRSDRC_HS         0x2C    /* High Speed Register [SAM9 Only] */
 #define         AT91_DDRSDRC_DIS_ATCP_RD        (1 << 2)        /* Anticip read access is disabled */
@@ -131,10 +121,4 @@
 #define         AT91_DDRSDRC_WPVS       (1 << 0)                /* Write protect violation status */
 #define         AT91_DDRSDRC_WPVSRC     (0xffff << 8)           /* Write protect violation source */
 
-/* Register access macros */
-#define at91_ramc_read(num, reg) \
-        at91_sys_read(AT91_DDRSDRC##num + reg)
-#define at91_ramc_write(num, reg, value) \
-        at91_sys_write(AT91_DDRSDRC##num + reg, value)
-
 #endif
diff --git a/arch/arm/mach-at91/include/mach/at91sam9_sdramc.h b/arch/arm/mach-at91/include/mach/at91sam9_sdramc.h
index 100f5a59292..3d085a9a745 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9_sdramc.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9_sdramc.h
@@ -82,10 +82,4 @@
 #define                 AT91_SDRAMC_MD_SDRAM            0
 #define                 AT91_SDRAMC_MD_LOW_POWER_SDRAM  1
 
-/* Register access macros */
-#define at91_ramc_read(num, reg) \
-        at91_sys_read(AT91_SDRAMC##num + reg)
-#define at91_ramc_write(num, reg, value) \
-        at91_sys_write(AT91_SDRAMC##num + reg, value)
-
 #endif
diff --git a/arch/arm/mach-at91/include/mach/at91sam9g45.h b/arch/arm/mach-at91/include/mach/at91sam9g45.h
index dd9c95ea086..d052abcff85 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9g45.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9g45.h
@@ -84,17 +84,14 @@
 #define AT91SAM9G45_BASE_TC5            0xfffd4080
 
 /*
- * System Peripherals (offset from AT91_BASE_SYS)
+ * System Peripherals
  */
-#define AT91_DDRSDRC1   (0xffffe400 - AT91_BASE_SYS)
-#define AT91_DDRSDRC0   (0xffffe600 - AT91_BASE_SYS)
-#define AT91_MATRIX     (0xffffea00 - AT91_BASE_SYS)
-#define AT91_PMC        (0xfffffc00 - AT91_BASE_SYS)
-#define AT91_GPBR       (0xfffffd60 - AT91_BASE_SYS)
-
 #define AT91SAM9G45_BASE_ECC    0xffffe200
+#define AT91SAM9G45_BASE_DDRSDRC1 0xffffe400
+#define AT91SAM9G45_BASE_DDRSDRC0 0xffffe600
 #define AT91SAM9G45_BASE_DMA    0xffffec00
 #define AT91SAM9G45_BASE_SMC    0xffffe800
+#define AT91SAM9G45_BASE_MATRIX 0xffffea00
 #define AT91SAM9G45_BASE_DBGU   AT91_BASE_DBGU1
 #define AT91SAM9G45_BASE_PIOA   0xfffff200
 #define AT91SAM9G45_BASE_PIOB   0xfffff400
@@ -107,6 +104,7 @@
 #define AT91SAM9G45_BASE_PIT    0xfffffd30
 #define AT91SAM9G45_BASE_WDT    0xfffffd40
 #define AT91SAM9G45_BASE_RTC    0xfffffdb0
+#define AT91SAM9G45_BASE_GPBR   0xfffffd60
 
 #define AT91_USART0     AT91SAM9G45_BASE_US0
 #define AT91_USART1     AT91SAM9G45_BASE_US1
diff --git a/arch/arm/mach-at91/include/mach/at91sam9g45_matrix.h b/arch/arm/mach-at91/include/mach/at91sam9g45_matrix.h
index c972d60e0ae..b76e2ed2fbc 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9g45_matrix.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9g45_matrix.h
@@ -15,18 +15,18 @@
 #ifndef AT91SAM9G45_MATRIX_H
 #define AT91SAM9G45_MATRIX_H
 
-#define AT91_MATRIX_MCFG0       (AT91_MATRIX + 0x00)    /* Master Configuration Register 0 */
-#define AT91_MATRIX_MCFG1       (AT91_MATRIX + 0x04)    /* Master Configuration Register 1 */
-#define AT91_MATRIX_MCFG2       (AT91_MATRIX + 0x08)    /* Master Configuration Register 2 */
-#define AT91_MATRIX_MCFG3       (AT91_MATRIX + 0x0C)    /* Master Configuration Register 3 */
-#define AT91_MATRIX_MCFG4       (AT91_MATRIX + 0x10)    /* Master Configuration Register 4 */
-#define AT91_MATRIX_MCFG5       (AT91_MATRIX + 0x14)    /* Master Configuration Register 5 */
-#define AT91_MATRIX_MCFG6       (AT91_MATRIX + 0x18)    /* Master Configuration Register 6 */
-#define AT91_MATRIX_MCFG7       (AT91_MATRIX + 0x1C)    /* Master Configuration Register 7 */
-#define AT91_MATRIX_MCFG8       (AT91_MATRIX + 0x20)    /* Master Configuration Register 8 */
-#define AT91_MATRIX_MCFG9       (AT91_MATRIX + 0x24)    /* Master Configuration Register 9 */
-#define AT91_MATRIX_MCFG10      (AT91_MATRIX + 0x28)    /* Master Configuration Register 10 */
-#define AT91_MATRIX_MCFG11      (AT91_MATRIX + 0x2C)    /* Master Configuration Register 11 */
+#define AT91_MATRIX_MCFG0       0x00                    /* Master Configuration Register 0 */
+#define AT91_MATRIX_MCFG1       0x04                    /* Master Configuration Register 1 */
+#define AT91_MATRIX_MCFG2       0x08                    /* Master Configuration Register 2 */
+#define AT91_MATRIX_MCFG3       0x0C                    /* Master Configuration Register 3 */
+#define AT91_MATRIX_MCFG4       0x10                    /* Master Configuration Register 4 */
+#define AT91_MATRIX_MCFG5       0x14                    /* Master Configuration Register 5 */
+#define AT91_MATRIX_MCFG6       0x18                    /* Master Configuration Register 6 */
+#define AT91_MATRIX_MCFG7       0x1C                    /* Master Configuration Register 7 */
+#define AT91_MATRIX_MCFG8       0x20                    /* Master Configuration Register 8 */
+#define AT91_MATRIX_MCFG9       0x24                    /* Master Configuration Register 9 */
+#define AT91_MATRIX_MCFG10      0x28                    /* Master Configuration Register 10 */
+#define AT91_MATRIX_MCFG11      0x2C                    /* Master Configuration Register 11 */
 #define         AT91_MATRIX_ULBT        (7 << 0)        /* Undefined Length Burst Type */
 #define                 AT91_MATRIX_ULBT_INFINITE       (0 << 0)
 #define                 AT91_MATRIX_ULBT_SINGLE         (1 << 0)
@@ -37,14 +37,14 @@
 #define                 AT91_MATRIX_ULBT_SIXTYFOUR      (6 << 0)
 #define                 AT91_MATRIX_ULBT_128            (7 << 0)
 
-#define AT91_MATRIX_SCFG0       (AT91_MATRIX + 0x40)    /* Slave Configuration Register 0 */
-#define AT91_MATRIX_SCFG1       (AT91_MATRIX + 0x44)    /* Slave Configuration Register 1 */
-#define AT91_MATRIX_SCFG2       (AT91_MATRIX + 0x48)    /* Slave Configuration Register 2 */
-#define AT91_MATRIX_SCFG3       (AT91_MATRIX + 0x4C)    /* Slave Configuration Register 3 */
-#define AT91_MATRIX_SCFG4       (AT91_MATRIX + 0x50)    /* Slave Configuration Register 4 */
-#define AT91_MATRIX_SCFG5       (AT91_MATRIX + 0x54)    /* Slave Configuration Register 5 */
-#define AT91_MATRIX_SCFG6       (AT91_MATRIX + 0x58)    /* Slave Configuration Register 6 */
-#define AT91_MATRIX_SCFG7       (AT91_MATRIX + 0x5C)    /* Slave Configuration Register 7 */
+#define AT91_MATRIX_SCFG0       0x40                    /* Slave Configuration Register 0 */
+#define AT91_MATRIX_SCFG1       0x44                    /* Slave Configuration Register 1 */
+#define AT91_MATRIX_SCFG2       0x48                    /* Slave Configuration Register 2 */
+#define AT91_MATRIX_SCFG3       0x4C                    /* Slave Configuration Register 3 */
+#define AT91_MATRIX_SCFG4       0x50                    /* Slave Configuration Register 4 */
+#define AT91_MATRIX_SCFG5       0x54                    /* Slave Configuration Register 5 */
+#define AT91_MATRIX_SCFG6       0x58                    /* Slave Configuration Register 6 */
+#define AT91_MATRIX_SCFG7       0x5C                    /* Slave Configuration Register 7 */
 #define         AT91_MATRIX_SLOT_CYCLE          (0x1ff << 0)    /* Maximum Number of Allowed Cycles for a Burst */
 #define         AT91_MATRIX_DEFMSTR_TYPE        (3    << 16)    /* Default Master Type */
 #define                 AT91_MATRIX_DEFMSTR_TYPE_NONE   (0 << 16)
@@ -52,22 +52,22 @@
 #define                 AT91_MATRIX_DEFMSTR_TYPE_FIXED  (2 << 16)
 #define         AT91_MATRIX_FIXED_DEFMSTR       (0xf  << 18)    /* Fixed Index of Default Master */
 
-#define AT91_MATRIX_PRAS0       (AT91_MATRIX + 0x80)    /* Priority Register A for Slave 0 */
-#define AT91_MATRIX_PRBS0       (AT91_MATRIX + 0x84)    /* Priority Register B for Slave 0 */
-#define AT91_MATRIX_PRAS1       (AT91_MATRIX + 0x88)    /* Priority Register A for Slave 1 */
-#define AT91_MATRIX_PRBS1       (AT91_MATRIX + 0x8C)    /* Priority Register B for Slave 1 */
-#define AT91_MATRIX_PRAS2       (AT91_MATRIX + 0x90)    /* Priority Register A for Slave 2 */
-#define AT91_MATRIX_PRBS2       (AT91_MATRIX + 0x94)    /* Priority Register B for Slave 2 */
-#define AT91_MATRIX_PRAS3       (AT91_MATRIX + 0x98)    /* Priority Register A for Slave 3 */
-#define AT91_MATRIX_PRBS3       (AT91_MATRIX + 0x9C)    /* Priority Register B for Slave 3 */
-#define AT91_MATRIX_PRAS4       (AT91_MATRIX + 0xA0)    /* Priority Register A for Slave 4 */
-#define AT91_MATRIX_PRBS4       (AT91_MATRIX + 0xA4)    /* Priority Register B for Slave 4 */
-#define AT91_MATRIX_PRAS5       (AT91_MATRIX + 0xA8)    /* Priority Register A for Slave 5 */
-#define AT91_MATRIX_PRBS5       (AT91_MATRIX + 0xAC)    /* Priority Register B for Slave 5 */
-#define AT91_MATRIX_PRAS6       (AT91_MATRIX + 0xB0)    /* Priority Register A for Slave 6 */
-#define AT91_MATRIX_PRBS6       (AT91_MATRIX + 0xB4)    /* Priority Register B for Slave 6 */
-#define AT91_MATRIX_PRAS7       (AT91_MATRIX + 0xB8)    /* Priority Register A for Slave 7 */
-#define AT91_MATRIX_PRBS7       (AT91_MATRIX + 0xBC)    /* Priority Register B for Slave 7 */
+#define AT91_MATRIX_PRAS0       0x80                    /* Priority Register A for Slave 0 */
+#define AT91_MATRIX_PRBS0       0x84                    /* Priority Register B for Slave 0 */
+#define AT91_MATRIX_PRAS1       0x88                    /* Priority Register A for Slave 1 */
+#define AT91_MATRIX_PRBS1       0x8C                    /* Priority Register B for Slave 1 */
+#define AT91_MATRIX_PRAS2       0x90                    /* Priority Register A for Slave 2 */
+#define AT91_MATRIX_PRBS2       0x94                    /* Priority Register B for Slave 2 */
+#define AT91_MATRIX_PRAS3       0x98                    /* Priority Register A for Slave 3 */
+#define AT91_MATRIX_PRBS3       0x9C                    /* Priority Register B for Slave 3 */
+#define AT91_MATRIX_PRAS4       0xA0                    /* Priority Register A for Slave 4 */
+#define AT91_MATRIX_PRBS4       0xA4                    /* Priority Register B for Slave 4 */
+#define AT91_MATRIX_PRAS5       0xA8                    /* Priority Register A for Slave 5 */
+#define AT91_MATRIX_PRBS5       0xAC                    /* Priority Register B for Slave 5 */
+#define AT91_MATRIX_PRAS6       0xB0                    /* Priority Register A for Slave 6 */
+#define AT91_MATRIX_PRBS6       0xB4                    /* Priority Register B for Slave 6 */
+#define AT91_MATRIX_PRAS7       0xB8                    /* Priority Register A for Slave 7 */
+#define AT91_MATRIX_PRBS7       0xBC                    /* Priority Register B for Slave 7 */
 #define         AT91_MATRIX_M0PR                (3 << 0)        /* Master 0 Priority */
 #define         AT91_MATRIX_M1PR                (3 << 4)        /* Master 1 Priority */
 #define         AT91_MATRIX_M2PR                (3 << 8)        /* Master 2 Priority */
@@ -81,7 +81,7 @@
 #define         AT91_MATRIX_M10PR               (3 << 8)        /* Master 10 Priority (in Register B) */
 #define         AT91_MATRIX_M11PR               (3 << 12)       /* Master 11 Priority (in Register B) */
 
-#define AT91_MATRIX_MRCR        (AT91_MATRIX + 0x100)   /* Master Remap Control Register */
+#define AT91_MATRIX_MRCR        0x100                   /* Master Remap Control Register */
 #define         AT91_MATRIX_RCB0                (1 << 0)        /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
 #define         AT91_MATRIX_RCB1                (1 << 1)        /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
 #define         AT91_MATRIX_RCB2                (1 << 2)
@@ -95,7 +95,7 @@
 #define         AT91_MATRIX_RCB10               (1 << 10)
 #define         AT91_MATRIX_RCB11               (1 << 11)
 
-#define AT91_MATRIX_TCMR        (AT91_MATRIX + 0x110)   /* TCM Configuration Register */
+#define AT91_MATRIX_TCMR        0x110                   /* TCM Configuration Register */
 #define         AT91_MATRIX_ITCM_SIZE           (0xf << 0)      /* Size of ITCM enabled memory block */
 #define                 AT91_MATRIX_ITCM_0              (0 << 0)
 #define                 AT91_MATRIX_ITCM_32             (6 << 0)
@@ -107,12 +107,12 @@
 #define                 AT91_MATRIX_TCM_NO_WS           (0x0 << 11)
 #define                 AT91_MATRIX_TCM_ONE_WS          (0x1 << 11)
 
-#define AT91_MATRIX_VIDEO       (AT91_MATRIX + 0x118)   /* Video Mode Configuration Register */
+#define AT91_MATRIX_VIDEO       0x118                   /* Video Mode Configuration Register */
 #define         AT91C_VDEC_SEL                  (0x1 <<  0) /* Video Mode Selection */
 #define                 AT91C_VDEC_SEL_OFF              (0 << 0)
 #define                 AT91C_VDEC_SEL_ON               (1 << 0)
 
-#define AT91_MATRIX_EBICSA      (AT91_MATRIX + 0x128)   /* EBI Chip Select Assignment Register */
+#define AT91_MATRIX_EBICSA      0x128                   /* EBI Chip Select Assignment Register */
 #define         AT91_MATRIX_EBI_CS1A            (1 << 1)        /* Chip Select 1 Assignment */
 #define                 AT91_MATRIX_EBI_CS1A_SMC                (0 << 1)
 #define                 AT91_MATRIX_EBI_CS1A_SDRAMC             (1 << 1)
@@ -138,13 +138,13 @@
 #define                 AT91_MATRIX_EBI_DDR_IOSR_REDUCED        (0 << 18)
 #define                 AT91_MATRIX_EBI_DDR_IOSR_NORMAL         (1 << 18)
 
-#define AT91_MATRIX_WPMR        (AT91_MATRIX + 0x1E4)   /* Write Protect Mode Register */
+#define AT91_MATRIX_WPMR        0x1E4                   /* Write Protect Mode Register */
 #define         AT91_MATRIX_WPMR_WPEN           (1 << 0)        /* Write Protect ENable */
 #define                 AT91_MATRIX_WPMR_WP_WPDIS               (0 << 0)
 #define                 AT91_MATRIX_WPMR_WP_WPEN                (1 << 0)
 #define         AT91_MATRIX_WPMR_WPKEY          (0xFFFFFF << 8) /* Write Protect KEY */
 
-#define AT91_MATRIX_WPSR        (AT91_MATRIX + 0x1E8)   /* Write Protect Status Register */
+#define AT91_MATRIX_WPSR        0x1E8                   /* Write Protect Status Register */
 #define         AT91_MATRIX_WPSR_WPVS           (1 << 0)        /* Write Protect Violation Status */
 #define                 AT91_MATRIX_WPSR_NO_WPV         (0 << 0)
 #define                 AT91_MATRIX_WPSR_WPV            (1 << 0)
diff --git a/arch/arm/mach-at91/include/mach/at91sam9rl.h b/arch/arm/mach-at91/include/mach/at91sam9rl.h
index d7bead7118d..e0073eb1014 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9rl.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9rl.h
@@ -69,15 +69,13 @@
 /*
  * System Peripherals (offset from AT91_BASE_SYS)
  */
-#define AT91_SDRAMC0    (0xffffea00 - AT91_BASE_SYS)
-#define AT91_MATRIX     (0xffffee00 - AT91_BASE_SYS)
-#define AT91_PMC        (0xfffffc00 - AT91_BASE_SYS)
 #define AT91_SCKCR      (0xfffffd50 - AT91_BASE_SYS)
-#define AT91_GPBR       (0xfffffd60 - AT91_BASE_SYS)
 
 #define AT91SAM9RL_BASE_DMA     0xffffe600
 #define AT91SAM9RL_BASE_ECC     0xffffe800
+#define AT91SAM9RL_BASE_SDRAMC  0xffffea00
 #define AT91SAM9RL_BASE_SMC     0xffffec00
+#define AT91SAM9RL_BASE_MATRIX  0xffffee00
 #define AT91SAM9RL_BASE_DBGU    AT91_BASE_DBGU0
 #define AT91SAM9RL_BASE_PIOA    0xfffff400
 #define AT91SAM9RL_BASE_PIOB    0xfffff600
@@ -88,6 +86,7 @@
 #define AT91SAM9RL_BASE_RTT     0xfffffd20
 #define AT91SAM9RL_BASE_PIT     0xfffffd30
 #define AT91SAM9RL_BASE_WDT     0xfffffd40
+#define AT91SAM9RL_BASE_GPBR    0xfffffd60
 #define AT91SAM9RL_BASE_RTC     0xfffffe00
 
 #define AT91_USART0     AT91SAM9RL_BASE_US0
diff --git a/arch/arm/mach-at91/include/mach/at91sam9rl_matrix.h b/arch/arm/mach-at91/include/mach/at91sam9rl_matrix.h
index 5f9149071fe..6d160adadaf 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9rl_matrix.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9rl_matrix.h
@@ -14,12 +14,12 @@
 #ifndef AT91SAM9RL_MATRIX_H
 #define AT91SAM9RL_MATRIX_H
 
-#define AT91_MATRIX_MCFG0       (AT91_MATRIX + 0x00)    /* Master Configuration Register 0 */
-#define AT91_MATRIX_MCFG1       (AT91_MATRIX + 0x04)    /* Master Configuration Register 1 */
-#define AT91_MATRIX_MCFG2       (AT91_MATRIX + 0x08)    /* Master Configuration Register 2 */
-#define AT91_MATRIX_MCFG3       (AT91_MATRIX + 0x0C)    /* Master Configuration Register 3 */
-#define AT91_MATRIX_MCFG4       (AT91_MATRIX + 0x10)    /* Master Configuration Register 4 */
-#define AT91_MATRIX_MCFG5       (AT91_MATRIX + 0x14)    /* Master Configuration Register 5 */
+#define AT91_MATRIX_MCFG0       0x00                    /* Master Configuration Register 0 */
+#define AT91_MATRIX_MCFG1       0x04                    /* Master Configuration Register 1 */
+#define AT91_MATRIX_MCFG2       0x08                    /* Master Configuration Register 2 */
+#define AT91_MATRIX_MCFG3       0x0C                    /* Master Configuration Register 3 */
+#define AT91_MATRIX_MCFG4       0x10                    /* Master Configuration Register 4 */
+#define AT91_MATRIX_MCFG5       0x14                    /* Master Configuration Register 5 */
 #define         AT91_MATRIX_ULBT        (7 << 0)        /* Undefined Length Burst Type */
 #define                 AT91_MATRIX_ULBT_INFINITE       (0 << 0)
 #define                 AT91_MATRIX_ULBT_SINGLE         (1 << 0)
@@ -27,12 +27,12 @@
 #define                 AT91_MATRIX_ULBT_EIGHT          (3 << 0)
 #define                 AT91_MATRIX_ULBT_SIXTEEN        (4 << 0)
 
-#define AT91_MATRIX_SCFG0       (AT91_MATRIX + 0x40)    /* Slave Configuration Register 0 */
-#define AT91_MATRIX_SCFG1       (AT91_MATRIX + 0x44)    /* Slave Configuration Register 1 */
-#define AT91_MATRIX_SCFG2       (AT91_MATRIX + 0x48)    /* Slave Configuration Register 2 */
-#define AT91_MATRIX_SCFG3       (AT91_MATRIX + 0x4C)    /* Slave Configuration Register 3 */
-#define AT91_MATRIX_SCFG4       (AT91_MATRIX + 0x50)    /* Slave Configuration Register 4 */
-#define AT91_MATRIX_SCFG5       (AT91_MATRIX + 0x54)    /* Slave Configuration Register 5 */
+#define AT91_MATRIX_SCFG0       0x40                    /* Slave Configuration Register 0 */
+#define AT91_MATRIX_SCFG1       0x44                    /* Slave Configuration Register 1 */
+#define AT91_MATRIX_SCFG2       0x48                    /* Slave Configuration Register 2 */
+#define AT91_MATRIX_SCFG3       0x4C                    /* Slave Configuration Register 3 */
+#define AT91_MATRIX_SCFG4       0x50                    /* Slave Configuration Register 4 */
+#define AT91_MATRIX_SCFG5       0x54                    /* Slave Configuration Register 5 */
 #define         AT91_MATRIX_SLOT_CYCLE          (0xff << 0)     /* Maximum Number of Allowed Cycles for a Burst */
 #define         AT91_MATRIX_DEFMSTR_TYPE        (3    << 16)    /* Default Master Type */
 #define                 AT91_MATRIX_DEFMSTR_TYPE_NONE   (0 << 16)
@@ -43,12 +43,12 @@
 #define                 AT91_MATRIX_ARBT_ROUND_ROBIN    (0 << 24)
 #define                 AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24)
 
-#define AT91_MATRIX_PRAS0       (AT91_MATRIX + 0x80)    /* Priority Register A for Slave 0 */
-#define AT91_MATRIX_PRAS1       (AT91_MATRIX + 0x88)    /* Priority Register A for Slave 1 */
-#define AT91_MATRIX_PRAS2       (AT91_MATRIX + 0x90)    /* Priority Register A for Slave 2 */
-#define AT91_MATRIX_PRAS3       (AT91_MATRIX + 0x98)    /* Priority Register A for Slave 3 */
-#define AT91_MATRIX_PRAS4       (AT91_MATRIX + 0xA0)    /* Priority Register A for Slave 4 */
-#define AT91_MATRIX_PRAS5       (AT91_MATRIX + 0xA8)    /* Priority Register A for Slave 5 */
+#define AT91_MATRIX_PRAS0       0x80                    /* Priority Register A for Slave 0 */
+#define AT91_MATRIX_PRAS1       0x88                    /* Priority Register A for Slave 1 */
+#define AT91_MATRIX_PRAS2       0x90                    /* Priority Register A for Slave 2 */
+#define AT91_MATRIX_PRAS3       0x98                    /* Priority Register A for Slave 3 */
+#define AT91_MATRIX_PRAS4       0xA0                    /* Priority Register A for Slave 4 */
+#define AT91_MATRIX_PRAS5       0xA8                    /* Priority Register A for Slave 5 */
 #define         AT91_MATRIX_M0PR                (3 << 0)        /* Master 0 Priority */
 #define         AT91_MATRIX_M1PR                (3 << 4)        /* Master 1 Priority */
 #define         AT91_MATRIX_M2PR                (3 << 8)        /* Master 2 Priority */
@@ -56,7 +56,7 @@
 #define         AT91_MATRIX_M4PR                (3 << 16)       /* Master 4 Priority */
 #define         AT91_MATRIX_M5PR                (3 << 20)       /* Master 5 Priority */
 
-#define AT91_MATRIX_MRCR        (AT91_MATRIX + 0x100)   /* Master Remap Control Register */
+#define AT91_MATRIX_MRCR        0x100                   /* Master Remap Control Register */
 #define         AT91_MATRIX_RCB0                (1 << 0)        /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
 #define         AT91_MATRIX_RCB1                (1 << 1)        /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
 #define         AT91_MATRIX_RCB2                (1 << 2)
@@ -64,7 +64,7 @@
 #define         AT91_MATRIX_RCB4                (1 << 4)
 #define         AT91_MATRIX_RCB5                (1 << 5)
 
-#define AT91_MATRIX_TCMR        (AT91_MATRIX + 0x114)   /* TCM Configuration Register */
+#define AT91_MATRIX_TCMR        0x114                   /* TCM Configuration Register */
 #define         AT91_MATRIX_ITCM_SIZE           (0xf << 0)      /* Size of ITCM enabled memory block */
 #define                 AT91_MATRIX_ITCM_0              (0 << 0)
 #define                 AT91_MATRIX_ITCM_16             (5 << 0)
@@ -74,7 +74,7 @@
 #define                 AT91_MATRIX_DTCM_16             (5 << 4)
 #define                 AT91_MATRIX_DTCM_32             (6 << 4)
 
-#define AT91_MATRIX_EBICSA      (AT91_MATRIX + 0x120)   /* EBI0 Chip Select Assignment Register */
+#define AT91_MATRIX_EBICSA      0x120                   /* EBI0 Chip Select Assignment Register */
 #define         AT91_MATRIX_CS1A                (1 << 1)        /* Chip Select 1 Assignment */
 #define                 AT91_MATRIX_CS1A_SMC            (0 << 1)
 #define                 AT91_MATRIX_CS1A_SDRAMC         (1 << 1)
diff --git a/arch/arm/mach-at91/include/mach/at91sam9x5.h b/arch/arm/mach-at91/include/mach/at91sam9x5.h
new file mode 100644
index 00000000000..a297a77d88e
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/at91sam9x5.h
@@ -0,0 +1,79 @@
+/*
+ * Chip-specific header file for the AT91SAM9x5 family
+ *
+ *  Copyright (C) 2009-2012 Atmel Corporation.
+ *
+ * Common definitions.
+ * Based on AT91SAM9x5 datasheet.
+ *
+ * Licensed under GPLv2 or later.
+ */
+
+#ifndef AT91SAM9X5_H
+#define AT91SAM9X5_H
+
+/*
+ * Peripheral identifiers/interrupts.
+ */
+#define AT91SAM9X5_ID_PIOAB     2       /* Parallel I/O Controller A and B */
+#define AT91SAM9X5_ID_PIOCD     3       /* Parallel I/O Controller C and D */
+#define AT91SAM9X5_ID_SMD       4       /* SMD Soft Modem (SMD) */
+#define AT91SAM9X5_ID_USART0    5       /* USART 0 */
+#define AT91SAM9X5_ID_USART1    6       /* USART 1 */
+#define AT91SAM9X5_ID_USART2    7       /* USART 2 */
+#define AT91SAM9X5_ID_USART3    8       /* USART 3 */
+#define AT91SAM9X5_ID_TWI0      9       /* Two-Wire Interface 0 */
+#define AT91SAM9X5_ID_TWI1      10      /* Two-Wire Interface 1 */
+#define AT91SAM9X5_ID_TWI2      11      /* Two-Wire Interface 2 */
+#define AT91SAM9X5_ID_MCI0      12      /* High Speed Multimedia Card Interface 0 */
+#define AT91SAM9X5_ID_SPI0      13      /* Serial Peripheral Interface 0 */
+#define AT91SAM9X5_ID_SPI1      14      /* Serial Peripheral Interface 1 */
+#define AT91SAM9X5_ID_UART0     15      /* UART 0 */
+#define AT91SAM9X5_ID_UART1     16      /* UART 1 */
+#define AT91SAM9X5_ID_TCB       17      /* Timer Counter 0, 1, 2, 3, 4 and 5 */
+#define AT91SAM9X5_ID_PWM       18      /* Pulse Width Modulation Controller */
+#define AT91SAM9X5_ID_ADC       19      /* ADC Controller */
+#define AT91SAM9X5_ID_DMA0      20      /* DMA Controller 0 */
+#define AT91SAM9X5_ID_DMA1      21      /* DMA Controller 1 */
+#define AT91SAM9X5_ID_UHPHS     22      /* USB Host High Speed */
+#define AT91SAM9X5_ID_UDPHS     23      /* USB Device High Speed */
+#define AT91SAM9X5_ID_EMAC0     24      /* Ethernet MAC0 */
+#define AT91SAM9X5_ID_LCDC      25      /* LCD Controller */
+#define AT91SAM9X5_ID_ISI       25      /* Image Sensor Interface */
+#define AT91SAM9X5_ID_MCI1      26      /* High Speed Multimedia Card Interface 1 */
+#define AT91SAM9X5_ID_EMAC1     27      /* Ethernet MAC1 */
+#define AT91SAM9X5_ID_SSC       28      /* Synchronous Serial Controller */
+#define AT91SAM9X5_ID_CAN0      29      /* CAN Controller 0 */
+#define AT91SAM9X5_ID_CAN1      30      /* CAN Controller 1 */
+#define AT91SAM9X5_ID_IRQ0      31      /* Advanced Interrupt Controller */
+
+/*
+ * User Peripheral physical base addresses.
+ */
+#define AT91SAM9X5_BASE_USART0  0xf801c000
+#define AT91SAM9X5_BASE_USART1  0xf8020000
+#define AT91SAM9X5_BASE_USART2  0xf8024000
+
+/*
+ * System Peripherals
+ */
+#define AT91SAM9X5_BASE_DDRSDRC0        0xffffe800
+
+/*
+ * Base addresses for early serial code (uncompress.h)
+ */
+#define AT91_DBGU       AT91_BASE_DBGU0
+#define AT91_USART0     AT91SAM9X5_BASE_USART0
+#define AT91_USART1     AT91SAM9X5_BASE_USART1
+#define AT91_USART2     AT91SAM9X5_BASE_USART2
+
+/*
+ * Internal Memory.
+ */
+#define AT91SAM9X5_SRAM_BASE    0x00300000      /* Internal SRAM base address */
+#define AT91SAM9X5_SRAM_SIZE    SZ_32K          /* Internal SRAM size (32Kb) */
+
+#define AT91SAM9X5_ROM_BASE     0x00400000      /* Internal ROM base address */
+#define AT91SAM9X5_ROM_SIZE     SZ_64K          /* Internal ROM size (64Kb) */
+
+#endif
diff --git a/arch/arm/mach-at91/include/mach/at91sam9x5_matrix.h b/arch/arm/mach-at91/include/mach/at91sam9x5_matrix.h
new file mode 100644
index 00000000000..a606d396647
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/at91sam9x5_matrix.h
@@ -0,0 +1,53 @@
+/*
+ * Matrix-centric header file for the AT91SAM9x5 family
+ *
+ *  Copyright (C) 2009-2012 Atmel Corporation.
+ *
+ * Only EBI related registers.
+ * Write Protect register definitions may be useful.
+ *
+ * Licensed under GPLv2 or later.
+ */
+
+#ifndef AT91SAM9X5_MATRIX_H
+#define AT91SAM9X5_MATRIX_H
+
+#define AT91_MATRIX_EBICSA      (AT91_MATRIX + 0x120)   /* EBI Chip Select Assignment Register */
+#define         AT91_MATRIX_EBI_CS1A            (1 << 1)        /* Chip Select 1 Assignment */
+#define                 AT91_MATRIX_EBI_CS1A_SMC                (0 << 1)
+#define                 AT91_MATRIX_EBI_CS1A_SDRAMC             (1 << 1)
+#define         AT91_MATRIX_EBI_CS3A            (1 << 3)        /* Chip Select 3 Assignment */
+#define                 AT91_MATRIX_EBI_CS3A_SMC                (0 << 3)
+#define                 AT91_MATRIX_EBI_CS3A_SMC_NANDFLASH      (1 << 3)
+#define         AT91_MATRIX_EBI_DBPUC           (1 << 8)        /* Data Bus Pull-up Configuration */
+#define                 AT91_MATRIX_EBI_DBPU_ON                 (0 << 8)
+#define                 AT91_MATRIX_EBI_DBPU_OFF                (1 << 8)
+#define         AT91_MATRIX_EBI_VDDIOMSEL       (1 << 16)       /* Memory voltage selection */
+#define                 AT91_MATRIX_EBI_VDDIOMSEL_1_8V          (0 << 16)
+#define                 AT91_MATRIX_EBI_VDDIOMSEL_3_3V          (1 << 16)
+#define         AT91_MATRIX_EBI_EBI_IOSR        (1 << 17)       /* EBI I/O slew rate selection */
+#define                 AT91_MATRIX_EBI_EBI_IOSR_REDUCED        (0 << 17)
+#define                 AT91_MATRIX_EBI_EBI_IOSR_NORMAL         (1 << 17)
+#define         AT91_MATRIX_EBI_DDR_IOSR        (1 << 18)       /* DDR2 dedicated port I/O slew rate selection */
+#define                 AT91_MATRIX_EBI_DDR_IOSR_REDUCED        (0 << 18)
+#define                 AT91_MATRIX_EBI_DDR_IOSR_NORMAL         (1 << 18)
+#define         AT91_MATRIX_NFD0_SELECT         (1 << 24)       /* NAND Flash Data Bus Selection */
+#define                 AT91_MATRIX_NFD0_ON_D0                  (0 << 24)
+#define                 AT91_MATRIX_NFD0_ON_D16                 (1 << 24)
+#define         AT91_MATRIX_DDR_MP_EN           (1 << 25)       /* DDR Multi-port Enable */
+#define                 AT91_MATRIX_MP_OFF                      (0 << 25)
+#define                 AT91_MATRIX_MP_ON                       (1 << 25)
+
+#define AT91_MATRIX_WPMR        (AT91_MATRIX + 0x1E4)   /* Write Protect Mode Register */
+#define         AT91_MATRIX_WPMR_WPEN           (1 << 0)        /* Write Protect ENable */
+#define                 AT91_MATRIX_WPMR_WP_WPDIS               (0 << 0)
+#define                 AT91_MATRIX_WPMR_WP_WPEN                (1 << 0)
+#define         AT91_MATRIX_WPMR_WPKEY          (0xFFFFFF << 8) /* Write Protect KEY */
+
+#define AT91_MATRIX_WPSR        (AT91_MATRIX + 0x1E8)   /* Write Protect Status Register */
+#define         AT91_MATRIX_WPSR_WPVS           (1 << 0)        /* Write Protect Violation Status */
+#define                 AT91_MATRIX_WPSR_NO_WPV         (0 << 0)
+#define                 AT91_MATRIX_WPSR_WPV            (1 << 0)
+#define         AT91_MATRIX_WPSR_WPVSRC         (0xFFFF << 8)   /* Write Protect Violation Source */
+
+#endif
diff --git a/arch/arm/mach-at91/include/mach/at91x40.h b/arch/arm/mach-at91/include/mach/at91x40.h
index a57829f4fd1..90680217064 100644
--- a/arch/arm/mach-at91/include/mach/at91x40.h
+++ b/arch/arm/mach-at91/include/mach/at91x40.h
@@ -28,18 +28,18 @@
 #define AT91X40_ID_IRQ2         18      /* External IRQ 2 */
 
 /*
- * System Peripherals (offset from AT91_BASE_SYS)
+ * System Peripherals
  */
 #define AT91_BASE_SYS   0xffc00000
 
-#define AT91_EBI        (0xffe00000 - AT91_BASE_SYS)    /* External Bus Interface */
-#define AT91_SF         (0xfff00000 - AT91_BASE_SYS)    /* Special Function */
-#define AT91_USART1     (0xfffcc000 - AT91_BASE_SYS)    /* USART 1 */
-#define AT91_USART0     (0xfffd0000 - AT91_BASE_SYS)    /* USART 0 */
-#define AT91_TC         (0xfffe0000 - AT91_BASE_SYS)    /* Timer Counter */
-#define AT91_PIOA       (0xffff0000 - AT91_BASE_SYS)    /* PIO Controller A */
-#define AT91_PS         (0xffff4000 - AT91_BASE_SYS)    /* Power Save */
-#define AT91_WD         (0xffff8000 - AT91_BASE_SYS)    /* Watchdog Timer */
+#define AT91_EBI        0xffe00000      /* External Bus Interface */
+#define AT91_SF         0xfff00000      /* Special Function */
+#define AT91_USART1     0xfffcc000      /* USART 1 */
+#define AT91_USART0     0xfffd0000      /* USART 0 */
+#define AT91_TC         0xfffe0000      /* Timer Counter */
+#define AT91_PIOA       0xffff0000      /* PIO Controller A */
+#define AT91_PS         0xffff4000      /* Power Save */
+#define AT91_WD         0xffff8000      /* Watchdog Timer */
 
 /*
  * The AT91x40 series doesn't have a debug unit like the other AT91 parts.
diff --git a/arch/arm/mach-at91/include/mach/board.h b/arch/arm/mach-at91/include/mach/board.h
index 3b33f07b1e1..dc8d6d4f17c 100644
--- a/arch/arm/mach-at91/include/mach/board.h
+++ b/arch/arm/mach-at91/include/mach/board.h
@@ -107,6 +107,8 @@ struct atmel_nand_data {
         u8              ale;            /* address line number connected to ALE */
         u8              cle;            /* address line number connected to CLE */
         u8              bus_width_16;   /* buswidth is 16 bit */
+        u8              correction_cap; /* PMECC correction capability */
+        u16             sector_size;    /* Sector size for PMECC */
         struct mtd_partition *parts;
         unsigned int    num_parts;
 };
@@ -179,7 +181,9 @@ extern void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data);
 extern void __init at91_add_device_ac97(struct ac97c_platform_data *data);
 
  /* ISI */
-extern void __init at91_add_device_isi(void);
+struct isi_platform_data;
+extern void __init at91_add_device_isi(struct isi_platform_data *data,
+                bool use_pck_as_mck);
 
  /* Touchscreen Controller */
 struct at91_tsadcc_data {
diff --git a/arch/arm/mach-at91/include/mach/cpu.h b/arch/arm/mach-at91/include/mach/cpu.h
index f6ce936dba2..0118c333855 100644
--- a/arch/arm/mach-at91/include/mach/cpu.h
+++ b/arch/arm/mach-at91/include/mach/cpu.h
@@ -25,7 +25,6 @@
 #define ARCH_ID_AT91SAM9G45MRL  0x819b05a2      /* aka 9G45-ES2 & non ES lots */
 #define ARCH_ID_AT91SAM9G45ES   0x819b05a1      /* 9G45-ES (Engineering Sample) */
 #define ARCH_ID_AT91SAM9X5      0x819a05a0
-#define ARCH_ID_AT91CAP9        0x039A03A0
 
 #define ARCH_ID_AT91SAM9XE128   0x329973a0
 #define ARCH_ID_AT91SAM9XE256   0x329a93a0
@@ -51,10 +50,6 @@
 #define ARCH_FAMILY_AT91SAM9    0x01900000
 #define ARCH_FAMILY_AT91SAM9XE  0x02900000
 
-/* PMC revision */
-#define ARCH_REVISION_CAP9_B    0x399
-#define ARCH_REVISION_CAP9_C    0x601
-
 /* RM9200 type */
 #define ARCH_REVISON_9200_BGA   (0 << 0)
 #define ARCH_REVISON_9200_PQFP  (1 << 0)
@@ -63,9 +58,6 @@ enum at91_soc_type {
         /* 920T */
         AT91_SOC_RM9200,
 
-        /* CAP */
-        AT91_SOC_CAP9,
-
         /* SAM92xx */
         AT91_SOC_SAM9260, AT91_SOC_SAM9261, AT91_SOC_SAM9263,
 
@@ -86,9 +78,6 @@ enum at91_soc_subtype {
         /* RM9200 */
         AT91_SOC_RM9200_BGA, AT91_SOC_RM9200_PQFP,
 
-        /* CAP9 */
-        AT91_SOC_CAP9_REV_B, AT91_SOC_CAP9_REV_C,
-
         /* SAM9260 */
         AT91_SOC_SAM9XE,
 
@@ -195,16 +184,6 @@ static inline int at91_soc_is_detected(void)
 #define cpu_is_at91sam9x25()    (0)
 #endif
 
-#ifdef CONFIG_ARCH_AT91CAP9
-#define cpu_is_at91cap9()       (at91_soc_initdata.type == AT91_SOC_CAP9)
-#define cpu_is_at91cap9_revB()  (at91_soc_initdata.subtype == AT91_SOC_CAP9_REV_B)
-#define cpu_is_at91cap9_revC()  (at91_soc_initdata.subtype == AT91_SOC_CAP9_REV_C)
-#else
-#define cpu_is_at91cap9()       (0)
-#define cpu_is_at91cap9_revB()  (0)
-#define cpu_is_at91cap9_revC()  (0)
-#endif
-
 /*
  * Since this is ARM, we will never run on any AVR32 CPU. But these
  * definitions may reduce clutter in common drivers.
diff --git a/arch/arm/mach-at91/include/mach/entry-macro.S b/arch/arm/mach-at91/include/mach/entry-macro.S
index 423eea0ed74..903bf205a33 100644
--- a/arch/arm/mach-at91/include/mach/entry-macro.S
+++ b/arch/arm/mach-at91/include/mach/entry-macro.S
@@ -13,17 +13,11 @@
 #include <mach/hardware.h>
 #include <mach/at91_aic.h>
 
-        .macro  disable_fiq
-        .endm
-
         .macro  get_irqnr_preamble, base, tmp
         ldr     \base, =at91_aic_base           @ base virtual address of AIC peripheral
         ldr     \base, [\base]
         .endm
 
-        .macro  arch_ret_to_user, tmp1, tmp2
-        .endm
-
         .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
         ldr     \irqnr, [\base, #AT91_AIC_IVR]          @ read IRQ vector register: de-asserts nIRQ to processor (and clears interrupt)
         ldr     \irqstat, [\base, #AT91_AIC_ISR]        @ read interrupt source number
diff --git a/arch/arm/mach-at91/include/mach/gpio.h b/arch/arm/mach-at91/include/mach/gpio.h
index e3fd225121c..eed465ab0dd 100644
--- a/arch/arm/mach-at91/include/mach/gpio.h
+++ b/arch/arm/mach-at91/include/mach/gpio.h
@@ -191,10 +191,15 @@
 extern int __init_or_module at91_set_GPIO_periph(unsigned pin, int use_pullup);
 extern int __init_or_module at91_set_A_periph(unsigned pin, int use_pullup);
 extern int __init_or_module at91_set_B_periph(unsigned pin, int use_pullup);
+extern int __init_or_module at91_set_C_periph(unsigned pin, int use_pullup);
+extern int __init_or_module at91_set_D_periph(unsigned pin, int use_pullup);
 extern int __init_or_module at91_set_gpio_input(unsigned pin, int use_pullup);
 extern int __init_or_module at91_set_gpio_output(unsigned pin, int value);
 extern int __init_or_module at91_set_deglitch(unsigned pin, int is_on);
+extern int __init_or_module at91_set_debounce(unsigned pin, int is_on, int div);
 extern int __init_or_module at91_set_multi_drive(unsigned pin, int is_on);
+extern int __init_or_module at91_set_pulldown(unsigned pin, int is_on);
+extern int __init_or_module at91_disable_schmitt_trig(unsigned pin);
 
 /* callable at any time */
 extern int at91_set_gpio_value(unsigned pin, int value);
@@ -204,18 +209,6 @@ extern int at91_get_gpio_value(unsigned pin);
 extern void at91_gpio_suspend(void);
 extern void at91_gpio_resume(void);
 
-/*-------------------------------------------------------------------------*/
-
-/* wrappers for "new style" GPIO calls. the old AT91-specific ones should
- * eventually be removed (along with this errno.h inclusion), and the
- * gpio request/free calls should probably be implemented.
- */
-
-#include <asm/errno.h>
-
-#define gpio_to_irq(gpio) (gpio + NR_AIC_IRQS)
-#define irq_to_gpio(irq)  (irq - NR_AIC_IRQS)
-
 #endif  /* __ASSEMBLY__ */
 
 #endif
diff --git a/arch/arm/mach-at91/include/mach/hardware.h b/arch/arm/mach-at91/include/mach/hardware.h
index 2d0e4e99856..e9e29a6c386 100644
--- a/arch/arm/mach-at91/include/mach/hardware.h
+++ b/arch/arm/mach-at91/include/mach/hardware.h
@@ -19,7 +19,7 @@
 /* DBGU base */
 /* rm9200, 9260/9g20, 9261/9g10, 9rl */
 #define AT91_BASE_DBGU0 0xfffff200
-/* 9263, 9g45, cap9 */
+/* 9263, 9g45 */
 #define AT91_BASE_DBGU1 0xffffee00
 
 #if defined(CONFIG_ARCH_AT91RM9200)
@@ -34,8 +34,8 @@
 #include <mach/at91sam9rl.h>
 #elif defined(CONFIG_ARCH_AT91SAM9G45)
 #include <mach/at91sam9g45.h>
-#elif defined(CONFIG_ARCH_AT91CAP9)
-#include <mach/at91cap9.h>
+#elif defined(CONFIG_ARCH_AT91SAM9X5)
+#include <mach/at91sam9x5.h>
 #elif defined(CONFIG_ARCH_AT91X40)
 #include <mach/at91x40.h>
 #else
@@ -59,9 +59,10 @@
 
 /*
  * On all at91 have the Advanced Interrupt Controller starts at address
- * 0xfffff000
+ * 0xfffff000 and the Power Management Controller starts at 0xfffffc00
  */
 #define AT91_AIC        0xfffff000
+#define AT91_PMC        0xfffffc00
 
 /*
  * Peripheral identifiers/interrupts.
diff --git a/arch/arm/mach-at91/include/mach/io.h b/arch/arm/mach-at91/include/mach/io.h
index 4ca09ef7ca2..4003001eca3 100644
--- a/arch/arm/mach-at91/include/mach/io.h
+++ b/arch/arm/mach-at91/include/mach/io.h
@@ -28,22 +28,4 @@
 #define __io(a)         __typesafe_io(a)
 #define __mem_pci(a)    (a)
 
-#ifndef __ASSEMBLY__
-
-static inline unsigned int at91_sys_read(unsigned int reg_offset)
-{
-        void __iomem *addr = (void __iomem *)AT91_VA_BASE_SYS;
-
-        return __raw_readl(addr + reg_offset);
-}
-
-static inline void at91_sys_write(unsigned int reg_offset, unsigned long value)
-{
-        void __iomem *addr = (void __iomem *)AT91_VA_BASE_SYS;
-
-        __raw_writel(value, addr + reg_offset);
-}
-
-#endif
-
 #endif
diff --git a/arch/arm/mach-at91/include/mach/system.h b/arch/arm/mach-at91/include/mach/system.h
deleted file mode 100644
index cbd64f3bcec..00000000000
--- a/arch/arm/mach-at91/include/mach/system.h
+++ /dev/null
@@ -1,50 +0,0 @@
-/*
- * arch/arm/mach-at91/include/mach/system.h
- *
- *  Copyright (C) 2003 SAN People
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-
-#ifndef __ASM_ARCH_SYSTEM_H
-#define __ASM_ARCH_SYSTEM_H
-
-#include <mach/hardware.h>
-#include <mach/at91_st.h>
-#include <mach/at91_dbgu.h>
-#include <mach/at91_pmc.h>
-
-static inline void arch_idle(void)
-{
-        /*
-         * Disable the processor clock.  The processor will be automatically
-         * re-enabled by an interrupt or by a reset.
-         */
-#ifdef AT91_PS
-        at91_sys_write(AT91_PS_CR, AT91_PS_CR_CPU);
-#else
-        at91_sys_write(AT91_PMC_SCDR, AT91_PMC_PCK);
-#endif
-#ifndef CONFIG_CPU_ARM920T
-        /*
-         * Set the processor (CP15) into 'Wait for Interrupt' mode.
-         * Post-RM9200 processors need this in conjunction with the above
-         * to save power when idle.
-         */
-        cpu_do_idle();
-#endif
-}
-
-#endif
diff --git a/arch/arm/mach-at91/irq.c b/arch/arm/mach-at91/irq.c
index be6b639ecd7..cfcfcbe3626 100644
--- a/arch/arm/mach-at91/irq.c
+++ b/arch/arm/mach-at91/irq.c
@@ -24,6 +24,12 @@
 #include <linux/module.h>
 #include <linux/mm.h>
 #include <linux/types.h>
+#include <linux/irq.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <linux/irqdomain.h>
+#include <linux/err.h>
 
 #include <mach/hardware.h>
 #include <asm/irq.h>
@@ -34,22 +40,24 @@
 #include <asm/mach/map.h>
 
 void __iomem *at91_aic_base;
+static struct irq_domain *at91_aic_domain;
+static struct device_node *at91_aic_np;
 
 static void at91_aic_mask_irq(struct irq_data *d)
 {
         /* Disable interrupt on AIC */
-        at91_aic_write(AT91_AIC_IDCR, 1 << d->irq);
+        at91_aic_write(AT91_AIC_IDCR, 1 << d->hwirq);
 }
 
 static void at91_aic_unmask_irq(struct irq_data *d)
 {
         /* Enable interrupt on AIC */
-        at91_aic_write(AT91_AIC_IECR, 1 << d->irq);
+        at91_aic_write(AT91_AIC_IECR, 1 << d->hwirq);
 }
 
 unsigned int at91_extern_irq;
 
-#define is_extern_irq(irq) ((1 << (irq)) & at91_extern_irq)
+#define is_extern_irq(hwirq) ((1 << (hwirq)) & at91_extern_irq)
 
 static int at91_aic_set_type(struct irq_data *d, unsigned type)
 {
@@ -63,13 +71,13 @@ static int at91_aic_set_type(struct irq_data *d, unsigned type)
                 srctype = AT91_AIC_SRCTYPE_RISING;
                 break;
         case IRQ_TYPE_LEVEL_LOW:
-                if ((d->irq == AT91_ID_FIQ) || is_extern_irq(d->irq))           /* only supported on external interrupts */
+                if ((d->hwirq == AT91_ID_FIQ) || is_extern_irq(d->hwirq))               /* only supported on external interrupts */
                         srctype = AT91_AIC_SRCTYPE_LOW;
                 else
                         return -EINVAL;
                 break;
         case IRQ_TYPE_EDGE_FALLING:
-                if ((d->irq == AT91_ID_FIQ) || is_extern_irq(d->irq))           /* only supported on external interrupts */
+                if ((d->hwirq == AT91_ID_FIQ) || is_extern_irq(d->hwirq))               /* only supported on external interrupts */
                         srctype = AT91_AIC_SRCTYPE_FALLING;
                 else
                         return -EINVAL;
@@ -78,8 +86,8 @@ static int at91_aic_set_type(struct irq_data *d, unsigned type)
                 return -EINVAL;
         }
 
-        smr = at91_aic_read(AT91_AIC_SMR(d->irq)) & ~AT91_AIC_SRCTYPE;
-        at91_aic_write(AT91_AIC_SMR(d->irq), smr | srctype);
+        smr = at91_aic_read(AT91_AIC_SMR(d->hwirq)) & ~AT91_AIC_SRCTYPE;
+        at91_aic_write(AT91_AIC_SMR(d->hwirq), smr | srctype);
         return 0;
 }
 
@@ -90,13 +98,13 @@ static u32 backups;
 
 static int at91_aic_set_wake(struct irq_data *d, unsigned value)
 {
-        if (unlikely(d->irq >= 32))
+        if (unlikely(d->hwirq >= NR_AIC_IRQS))
                 return -EINVAL;
 
         if (value)
-                wakeups |= (1 << d->irq);
+                wakeups |= (1 << d->hwirq);
         else
-                wakeups &= ~(1 << d->irq);
+                wakeups &= ~(1 << d->hwirq);
 
         return 0;
 }
@@ -127,46 +135,112 @@ static struct irq_chip at91_aic_chip = {
         .irq_set_wake   = at91_aic_set_wake,
 };
 
+static void __init at91_aic_hw_init(unsigned int spu_vector)
+{
+        int i;
+
+        /*
+         * Perform 8 End Of Interrupt Command to make sure AIC
+         * will not Lock out nIRQ
+         */
+        for (i = 0; i < 8; i++)
+                at91_aic_write(AT91_AIC_EOICR, 0);
+
+        /*
+         * Spurious Interrupt ID in Spurious Vector Register.
+         * When there is no current interrupt, the IRQ Vector Register
+         * reads the value stored in AIC_SPU
+         */
+        at91_aic_write(AT91_AIC_SPU, spu_vector);
+
+        /* No debugging in AIC: Debug (Protect) Control Register */
+        at91_aic_write(AT91_AIC_DCR, 0);
+
+        /* Disable and clear all interrupts initially */
+        at91_aic_write(AT91_AIC_IDCR, 0xFFFFFFFF);
+        at91_aic_write(AT91_AIC_ICCR, 0xFFFFFFFF);
+}
+
+#if defined(CONFIG_OF)
+static int at91_aic_irq_map(struct irq_domain *h, unsigned int virq,
+                                                        irq_hw_number_t hw)
+{
+        /* Put virq number in Source Vector Register */
+        at91_aic_write(AT91_AIC_SVR(hw), virq);
+
+        /* Active Low interrupt, without priority */
+        at91_aic_write(AT91_AIC_SMR(hw), AT91_AIC_SRCTYPE_LOW);
+
+        irq_set_chip_and_handler(virq, &at91_aic_chip, handle_level_irq);
+        set_irq_flags(virq, IRQF_VALID | IRQF_PROBE);
+
+        return 0;
+}
+
+static struct irq_domain_ops at91_aic_irq_ops = {
+        .map    = at91_aic_irq_map,
+        .xlate  = irq_domain_xlate_twocell,
+};
+
+int __init at91_aic_of_init(struct device_node *node,
+                                     struct device_node *parent)
+{
+        at91_aic_base = of_iomap(node, 0);
+        at91_aic_np = node;
+
+        at91_aic_domain = irq_domain_add_linear(at91_aic_np, NR_AIC_IRQS,
+                                                &at91_aic_irq_ops, NULL);
+        if (!at91_aic_domain)
+                panic("Unable to add AIC irq domain (DT)\n");
+
+        irq_set_default_host(at91_aic_domain);
+
+        at91_aic_hw_init(NR_AIC_IRQS);
+
+        return 0;
+}
+#endif
+
 /*
  * Initialize the AIC interrupt controller.
  */
 void __init at91_aic_init(unsigned int priority[NR_AIC_IRQS])
 {
         unsigned int i;
+        int irq_base;
 
         at91_aic_base = ioremap(AT91_AIC, 512);
-
         if (!at91_aic_base)
-                panic("Impossible to ioremap AT91_AIC\n");
+                panic("Unable to ioremap AIC registers\n");
+
+        /* Add irq domain for AIC */
+        irq_base = irq_alloc_descs(-1, 0, NR_AIC_IRQS, 0);
+        if (irq_base < 0) {
+                WARN(1, "Cannot allocate irq_descs, assuming pre-allocated\n");
+                irq_base = 0;
+        }
+        at91_aic_domain = irq_domain_add_legacy(at91_aic_np, NR_AIC_IRQS,
+                                                irq_base, 0,
+                                                &irq_domain_simple_ops, NULL);
+
+        if (!at91_aic_domain)
+                panic("Unable to add AIC irq domain\n");
+
+        irq_set_default_host(at91_aic_domain);
 
         /*
          * The IVR is used by macro get_irqnr_and_base to read and verify.
          * The irq number is NR_AIC_IRQS when a spurious interrupt has occurred.
          */
         for (i = 0; i < NR_AIC_IRQS; i++) {
-                /* Put irq number in Source Vector Register: */
+                /* Put hardware irq number in Source Vector Register: */
                 at91_aic_write(AT91_AIC_SVR(i), i);
                 /* Active Low interrupt, with the specified priority */
                 at91_aic_write(AT91_AIC_SMR(i), AT91_AIC_SRCTYPE_LOW | priority[i]);
 
                 irq_set_chip_and_handler(i, &at91_aic_chip, handle_level_irq);
                 set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
-
-                /* Perform 8 End Of Interrupt Command to make sure AIC will not Lock out nIRQ */
-                if (i < 8)
-                        at91_aic_write(AT91_AIC_EOICR, 0);
         }
 
-        /*
-         * Spurious Interrupt ID in Spurious Vector Register is NR_AIC_IRQS
-         * When there is no current interrupt, the IRQ Vector Register reads the value stored in AIC_SPU
-         */
-        at91_aic_write(AT91_AIC_SPU, NR_AIC_IRQS);
-
-        /* No debugging in AIC: Debug (Protect) Control Register */
-        at91_aic_write(AT91_AIC_DCR, 0);
-
-        /* Disable and clear all interrupts initially */
-        at91_aic_write(AT91_AIC_IDCR, 0xFFFFFFFF);
-        at91_aic_write(AT91_AIC_ICCR, 0xFFFFFFFF);
+        at91_aic_hw_init(NR_AIC_IRQS);
 }
diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c
index 1606379ac28..6c9d5e69ac2 100644
--- a/arch/arm/mach-at91/pm.c
+++ b/arch/arm/mach-at91/pm.c
@@ -136,7 +136,7 @@ static int at91_pm_verify_clocks(void)
         unsigned long scsr;
         int i;
 
-        scsr = at91_sys_read(AT91_PMC_SCSR);
+        scsr = at91_pmc_read(AT91_PMC_SCSR);
 
         /* USB must not be using PLLB */
         if (cpu_is_at91rm9200()) {
@@ -150,11 +150,6 @@ static int at91_pm_verify_clocks(void)
                         pr_err("AT91: PM - Suspend-to-RAM with USB still active\n");
                         return 0;
                 }
-        } else if (cpu_is_at91cap9()) {
-                if ((scsr & AT91CAP9_PMC_UHP) != 0) {
-                        pr_err("AT91: PM - Suspend-to-RAM with USB still active\n");
-                        return 0;
-                }
         }
 
 #ifdef CONFIG_AT91_PROGRAMMABLE_CLOCKS
@@ -165,7 +160,7 @@ static int at91_pm_verify_clocks(void)
                 if ((scsr & (AT91_PMC_PCK0 << i)) == 0)
                         continue;
 
-                css = at91_sys_read(AT91_PMC_PCKR(i)) & AT91_PMC_CSS;
+                css = at91_pmc_read(AT91_PMC_PCKR(i)) & AT91_PMC_CSS;
                 if (css != AT91_PMC_CSS_SLOW) {
                         pr_err("AT91: PM - Suspend-to-RAM with PCK%d src %d\n", i, css);
                         return 0;
@@ -193,23 +188,36 @@ int at91_suspend_entering_slow_clock(void)
 EXPORT_SYMBOL(at91_suspend_entering_slow_clock);
 
 
-static void (*slow_clock)(void);
+static void (*slow_clock)(void __iomem *pmc, void __iomem *ramc0,
+                          void __iomem *ramc1, int memctrl);
 
 #ifdef CONFIG_AT91_SLOW_CLOCK
-extern void at91_slow_clock(void);
+extern void at91_slow_clock(void __iomem *pmc, void __iomem *ramc0,
+                            void __iomem *ramc1, int memctrl);
 extern u32 at91_slow_clock_sz;
 #endif
 
+void __iomem *at91_ramc_base[2];
+
+void __init at91_ioremap_ramc(int id, u32 addr, u32 size)
+{
+        if (id < 0 || id > 1) {
+                pr_emerg("Wrong RAM controller id (%d), cannot continue\n", id);
+                BUG();
+        }
+        at91_ramc_base[id] = ioremap(addr, size);
+        if (!at91_ramc_base[id])
+                panic("Impossible to ioremap ramc.%d 0x%x\n", id, addr);
+}
 
 static int at91_pm_enter(suspend_state_t state)
 {
-        u32 saved_lpr;
         at91_gpio_suspend();
         at91_irq_suspend();
 
         pr_debug("AT91: PM - wake mask %08x, pm state %d\n",
                         /* remember all the always-wake irqs */
-                        (at91_sys_read(AT91_PMC_PCSR)
+                        (at91_pmc_read(AT91_PMC_PCSR)
                                         | (1 << AT91_ID_FIQ)
                                         | (1 << AT91_ID_SYS)
                                         | (at91_extern_irq))
@@ -234,11 +242,18 @@ static int at91_pm_enter(suspend_state_t state)
                          * turning off the main oscillator; reverse on wakeup.
                          */
                         if (slow_clock) {
+                                int memctrl = AT91_MEMCTRL_SDRAMC;
+
+                                if (cpu_is_at91rm9200())
+                                        memctrl = AT91_MEMCTRL_MC;
+                                else if (cpu_is_at91sam9g45())
+                                        memctrl = AT91_MEMCTRL_DDRSDR;
 #ifdef CONFIG_AT91_SLOW_CLOCK
                                 /* copy slow_clock handler to SRAM, and call it */
                                 memcpy(slow_clock, at91_slow_clock, at91_slow_clock_sz);
 #endif
-                                slow_clock();
+                                slow_clock(at91_pmc_base, at91_ramc_base[0],
+                                           at91_ramc_base[1], memctrl);
                                 break;
                         } else {
                                 pr_info("AT91: PM - no slow clock mode enabled ...\n");
@@ -259,16 +274,7 @@ static int at91_pm_enter(suspend_state_t state)
                          * For ARM 926 based chips, this requirement is weaker
                          * as at91sam9 can access a RAM in self-refresh mode.
                          */
-                        asm volatile (  "mov r0, #0\n\t"
-                                        "b 1f\n\t"
-                                        ".align 5\n\t"
-                                        "1: mcr p15, 0, r0, c7, c10, 4\n\t"
-                                        : /* no output */
-                                        : /* no input */
-                                        : "r0");
-                        saved_lpr = sdram_selfrefresh_enable();
-                        wait_for_interrupt_enable();
-                        sdram_selfrefresh_disable(saved_lpr);
+                        at91_standby();
                         break;
 
                 case PM_SUSPEND_ON:
@@ -316,7 +322,7 @@ static int __init at91_pm_init(void)
 
 #ifdef CONFIG_ARCH_AT91RM9200
         /* AT91RM9200 SDRAM low-power mode cannot be used with self-refresh. */
-        at91_sys_write(AT91_SDRAMC_LPR, 0);
+        at91_ramc_write(0, AT91RM9200_SDRAMC_LPR, 0);
 #endif
 
         suspend_set_ops(&at91_pm_ops);
diff --git a/arch/arm/mach-at91/pm.h b/arch/arm/mach-at91/pm.h
index 7eb40d24242..89f56f3a802 100644
--- a/arch/arm/mach-at91/pm.h
+++ b/arch/arm/mach-at91/pm.h
@@ -1,5 +1,19 @@
+/*
+ * AT91 Power Management
+ *
+ * Copyright (C) 2005 David Brownell
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+#ifndef __ARCH_ARM_MACH_AT91_PM
+#define __ARCH_ARM_MACH_AT91_PM
+
+#include <mach/at91_ramc.h>
 #ifdef CONFIG_ARCH_AT91RM9200
-#include <mach/at91rm9200_mc.h>
+#include <mach/at91rm9200_sdramc.h>
 
 /*
  * The AT91RM9200 goes into self-refresh mode with this command, and will
@@ -11,51 +25,37 @@
  * still in self-refresh is "not recommended", but seems to work.
  */
 
-static inline u32 sdram_selfrefresh_enable(void)
+static inline void at91rm9200_standby(void)
 {
-        u32 saved_lpr = at91_sys_read(AT91_SDRAMC_LPR);
-
-        at91_sys_write(AT91_SDRAMC_LPR, 0);
-        at91_sys_write(AT91_SDRAMC_SRR, 1);
-        return saved_lpr;
+        u32 lpr = at91_ramc_read(0, AT91RM9200_SDRAMC_LPR);
+
+        asm volatile(
+                "b    1f\n\t"
+                ".align    5\n\t"
+                "1:  mcr    p15, 0, %0, c7, c10, 4\n\t"
+                "    str    %0, [%1, %2]\n\t"
+                "    str    %3, [%1, %4]\n\t"
+                "    mcr    p15, 0, %0, c7, c0, 4\n\t"
+                "    str    %5, [%1, %2]"
+                :
+                : "r" (0), "r" (AT91_BASE_SYS), "r" (AT91RM9200_SDRAMC_LPR),
+                  "r" (1), "r" (AT91RM9200_SDRAMC_SRR),
+                  "r" (lpr));
 }
 
-#define sdram_selfrefresh_disable(saved_lpr)    at91_sys_write(AT91_SDRAMC_LPR, saved_lpr)
-#define wait_for_interrupt_enable()             asm volatile ("mcr p15, 0, %0, c7, c0, 4" \
-                                                                : : "r" (0))
-
-#elif defined(CONFIG_ARCH_AT91CAP9)
-#include <mach/at91sam9_ddrsdr.h>
-
-
-static inline u32 sdram_selfrefresh_enable(void)
-{
-        u32 saved_lpr, lpr;
-
-        saved_lpr = at91_ramc_read(0, AT91CAP9_DDRSDRC_LPR);
-
-        lpr = saved_lpr & ~AT91_DDRSDRC_LPCB;
-        at91_ramc_write(0, AT91CAP9_DDRSDRC_LPR, lpr | AT91_DDRSDRC_LPCB_SELF_REFRESH);
-        return saved_lpr;
-}
-
-#define sdram_selfrefresh_disable(saved_lpr)    at91_ramc_write(0, AT91CAP9_DDRSDRC_LPR, saved_lpr)
-#define wait_for_interrupt_enable()             cpu_do_idle()
+#define at91_standby at91rm9200_standby
 
 #elif defined(CONFIG_ARCH_AT91SAM9G45)
-#include <mach/at91sam9_ddrsdr.h>
 
 /* We manage both DDRAM/SDRAM controllers, we need more than one value to
  * remember.
  */
-static u32 saved_lpr1;
-
-static inline u32 sdram_selfrefresh_enable(void)
+static inline void at91sam9g45_standby(void)
 {
-        /* Those tow values allow us to delay self-refresh activation
+        /* Those two values allow us to delay self-refresh activation
          * to the maximum. */
         u32 lpr0, lpr1;
-        u32 saved_lpr0;
+        u32 saved_lpr0, saved_lpr1;
 
         saved_lpr1 = at91_ramc_read(1, AT91_DDRSDRC_LPR);
         lpr1 = saved_lpr1 & ~AT91_DDRSDRC_LPCB;
@@ -69,18 +69,15 @@ static inline u32 sdram_selfrefresh_enable(void)
         at91_ramc_write(0, AT91_DDRSDRC_LPR, lpr0);
         at91_ramc_write(1, AT91_DDRSDRC_LPR, lpr1);
 
-        return saved_lpr0;
+        cpu_do_idle();
+
+        at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr0);
+        at91_ramc_write(1, AT91_DDRSDRC_LPR, saved_lpr1);
 }
 
-#define sdram_selfrefresh_disable(saved_lpr0)   \
-        do { \
-                at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr0); \
-                at91_ramc_write(1, AT91_DDRSDRC_LPR, saved_lpr1); \
-        } while (0)
-#define wait_for_interrupt_enable()             cpu_do_idle()
+#define at91_standby at91sam9g45_standby
 
 #else
-#include <mach/at91sam9_sdramc.h>
 
 #ifdef CONFIG_ARCH_AT91SAM9263
 /*
@@ -90,18 +87,23 @@ static inline u32 sdram_selfrefresh_enable(void)
 #warning Assuming EB1 SDRAM controller is *NOT* used
 #endif
 
-static inline u32 sdram_selfrefresh_enable(void)
+static inline void at91sam9_standby(void)
 {
         u32 saved_lpr, lpr;
 
         saved_lpr = at91_ramc_read(0, AT91_SDRAMC_LPR);
 
         lpr = saved_lpr & ~AT91_SDRAMC_LPCB;
-        at91_ramc_write(0, AT91_SDRAMC_LPR, lpr | AT91_SDRAMC_LPCB_SELF_REFRESH);
-        return saved_lpr;
+        at91_ramc_write(0, AT91_SDRAMC_LPR, lpr |
+                        AT91_SDRAMC_LPCB_SELF_REFRESH);
+
+        cpu_do_idle();
+
+        at91_ramc_write(0, AT91_SDRAMC_LPR, saved_lpr);
 }
 
-#define sdram_selfrefresh_disable(saved_lpr)    at91_ramc_write(0, AT91_SDRAMC_LPR, saved_lpr)
-#define wait_for_interrupt_enable()             cpu_do_idle()
+#define at91_standby at91sam9_standby
+
+#endif
 
 #endif
diff --git a/arch/arm/mach-at91/pm_slowclock.S b/arch/arm/mach-at91/pm_slowclock.S
index 92dfb846139..db5452123f1 100644
--- a/arch/arm/mach-at91/pm_slowclock.S
+++ b/arch/arm/mach-at91/pm_slowclock.S
@@ -15,15 +15,7 @@
 #include <linux/linkage.h>
 #include <mach/hardware.h>
 #include <mach/at91_pmc.h>
-
-#if defined(CONFIG_ARCH_AT91RM9200)
-#include <mach/at91rm9200_mc.h>
-#elif defined(CONFIG_ARCH_AT91CAP9) \
-        || defined(CONFIG_ARCH_AT91SAM9G45)
-#include <mach/at91sam9_ddrsdr.h>
-#else
-#include <mach/at91sam9_sdramc.h>
-#endif
+#include <mach/at91_ramc.h>
 
 
 #ifdef CONFIG_ARCH_AT91SAM9263
@@ -47,17 +39,23 @@
 #define PLLALOCK_TIMEOUT        1000
 #define PLLBLOCK_TIMEOUT        1000
 
+pmc     .req    r0
+sdramc  .req    r1
+ramc1   .req    r2
+memctrl .req    r3
+tmp1    .req    r4
+tmp2    .req    r5
 
 /*
  * Wait until master clock is ready (after switching master clock source)
  */
         .macro wait_mckrdy
-        mov     r4, #MCKRDY_TIMEOUT
-1:      sub     r4, r4, #1
-        cmp     r4, #0
+        mov     tmp2, #MCKRDY_TIMEOUT
+1:      sub     tmp2, tmp2, #1
+        cmp     tmp2, #0
         beq     2f
-        ldr     r3, [r1, #(AT91_PMC_SR - AT91_PMC)]
-        tst     r3, #AT91_PMC_MCKRDY
+        ldr     tmp1, [pmc, #AT91_PMC_SR]
+        tst     tmp1, #AT91_PMC_MCKRDY
         beq     1b
 2:
         .endm
@@ -66,12 +64,12 @@
  * Wait until master oscillator has stabilized.
  */
         .macro wait_moscrdy
-        mov     r4, #MOSCRDY_TIMEOUT
-1:      sub     r4, r4, #1
-        cmp     r4, #0
+        mov     tmp2, #MOSCRDY_TIMEOUT
+1:      sub     tmp2, tmp2, #1
+        cmp     tmp2, #0
         beq     2f
-        ldr     r3, [r1, #(AT91_PMC_SR - AT91_PMC)]
-        tst     r3, #AT91_PMC_MOSCS
+        ldr     tmp1, [pmc, #AT91_PMC_SR]
+        tst     tmp1, #AT91_PMC_MOSCS
         beq     1b
 2:
         .endm
@@ -80,12 +78,12 @@
  * Wait until PLLA has locked.
  */
         .macro wait_pllalock
-        mov     r4, #PLLALOCK_TIMEOUT
-1:      sub     r4, r4, #1
-        cmp     r4, #0
+        mov     tmp2, #PLLALOCK_TIMEOUT
+1:      sub     tmp2, tmp2, #1
+        cmp     tmp2, #0
         beq     2f
-        ldr     r3, [r1, #(AT91_PMC_SR - AT91_PMC)]
-        tst     r3, #AT91_PMC_LOCKA
+        ldr     tmp1, [pmc, #AT91_PMC_SR]
+        tst     tmp1, #AT91_PMC_LOCKA
         beq     1b
 2:
         .endm
@@ -94,80 +92,98 @@
  * Wait until PLLB has locked.
  */
         .macro wait_pllblock
-        mov     r4, #PLLBLOCK_TIMEOUT
-1:      sub     r4, r4, #1
-        cmp     r4, #0
+        mov     tmp2, #PLLBLOCK_TIMEOUT
+1:      sub     tmp2, tmp2, #1
+        cmp     tmp2, #0
         beq     2f
-        ldr     r3, [r1, #(AT91_PMC_SR - AT91_PMC)]
-        tst     r3, #AT91_PMC_LOCKB
+        ldr     tmp1, [pmc, #AT91_PMC_SR]
+        tst     tmp1, #AT91_PMC_LOCKB
         beq     1b
 2:
         .endm
 
         .text
 
+/* void at91_slow_clock(void __iomem *pmc, void __iomem *sdramc,
+ *                      void __iomem *ramc1, int memctrl)
+ */
 ENTRY(at91_slow_clock)
         /* Save registers on stack */
-        stmfd   sp!, {r0 - r12, lr}
+        stmfd   sp!, {r4 - r12, lr}
 
         /*
          * Register usage:
-         *  R1 = Base address of AT91_PMC
-         *  R2 = Base address of RAM Controller (SDRAM, DDRSDR, or AT91_SYS)
-         *  R3 = temporary register
+         *  R0 = Base address of AT91_PMC
+         *  R1 = Base address of RAM Controller (SDRAM, DDRSDR, or AT91_SYS)
+         *  R2 = Base address of second RAM Controller or 0 if not present
+         *  R3 = Memory controller
          *  R4 = temporary register
-         *  R5 = Base address of second RAM Controller or 0 if not present
+         *  R5 = temporary register
          */
-        ldr     r1, .at91_va_base_pmc
-        ldr     r2, .at91_va_base_sdramc
-        ldr     r5, .at91_va_base_ramc1
 
         /* Drain write buffer */
-        mov     r0, #0
-        mcr     p15, 0, r0, c7, c10, 4
+        mov     tmp1, #0
+        mcr     p15, 0, tmp1, c7, c10, 4
+
+        cmp     memctrl, #AT91_MEMCTRL_MC
+        bne     ddr_sr_enable
 
-#ifdef CONFIG_ARCH_AT91RM9200
+        /*
+         * at91rm9200 Memory controller
+         */
         /* Put SDRAM in self-refresh mode */
-        mov     r3, #1
-        str     r3, [r2, #AT91_SDRAMC_SRR]
-#elif defined(CONFIG_ARCH_AT91CAP9) \
-        || defined(CONFIG_ARCH_AT91SAM9G45)
+        mov     tmp1, #1
+        str     tmp1, [sdramc, #AT91RM9200_SDRAMC_SRR]
+        b       sdr_sr_done
+
+        /*
+         * DDRSDR Memory controller
+         */
+ddr_sr_enable:
+        cmp     memctrl, #AT91_MEMCTRL_DDRSDR
+        bne     sdr_sr_enable
 
         /* prepare for DDRAM self-refresh mode */
-        ldr     r3, [r2, #AT91_DDRSDRC_LPR]
-        str     r3, .saved_sam9_lpr
-        bic     r3, #AT91_DDRSDRC_LPCB
-        orr     r3, #AT91_DDRSDRC_LPCB_SELF_REFRESH
+        ldr     tmp1, [sdramc, #AT91_DDRSDRC_LPR]
+        str     tmp1, .saved_sam9_lpr
+        bic     tmp1, #AT91_DDRSDRC_LPCB
+        orr     tmp1, #AT91_DDRSDRC_LPCB_SELF_REFRESH
 
         /* figure out if we use the second ram controller */
-        cmp     r5, #0
-        ldrne   r4, [r5, #AT91_DDRSDRC_LPR]
-        strne   r4, .saved_sam9_lpr1
-        bicne   r4, #AT91_DDRSDRC_LPCB
-        orrne   r4, #AT91_DDRSDRC_LPCB_SELF_REFRESH
+        cmp     ramc1, #0
+        ldrne   tmp2, [ramc1, #AT91_DDRSDRC_LPR]
+        strne   tmp2, .saved_sam9_lpr1
+        bicne   tmp2, #AT91_DDRSDRC_LPCB
+        orrne   tmp2, #AT91_DDRSDRC_LPCB_SELF_REFRESH
 
         /* Enable DDRAM self-refresh mode */
-        str     r3, [r2, #AT91_DDRSDRC_LPR]
-        strne   r4, [r5, #AT91_DDRSDRC_LPR]
-#else
+        str     tmp1, [sdramc, #AT91_DDRSDRC_LPR]
+        strne   tmp2, [ramc1, #AT91_DDRSDRC_LPR]
+
+        b       sdr_sr_done
+
+        /*
+         * SDRAMC Memory controller
+         */
+sdr_sr_enable:
         /* Enable SDRAM self-refresh mode */
-        ldr     r3, [r2, #AT91_SDRAMC_LPR]
-        str     r3, .saved_sam9_lpr
+        ldr     tmp1, [sdramc, #AT91_SDRAMC_LPR]
+        str     tmp1, .saved_sam9_lpr
 
-        bic     r3, #AT91_SDRAMC_LPCB
-        orr     r3, #AT91_SDRAMC_LPCB_SELF_REFRESH
-        str     r3, [r2, #AT91_SDRAMC_LPR]
-#endif
+        bic     tmp1, #AT91_SDRAMC_LPCB
+        orr     tmp1, #AT91_SDRAMC_LPCB_SELF_REFRESH
+        str     tmp1, [sdramc, #AT91_SDRAMC_LPR]
 
+sdr_sr_done:
         /* Save Master clock setting */
-        ldr     r3, [r1, #(AT91_PMC_MCKR - AT91_PMC)]
-        str     r3, .saved_mckr
+        ldr     tmp1, [pmc, #AT91_PMC_MCKR]
+        str     tmp1, .saved_mckr
 
         /*
          * Set the Master clock source to slow clock
          */
-        bic     r3, r3, #AT91_PMC_CSS
-        str     r3, [r1, #(AT91_PMC_MCKR - AT91_PMC)]
+        bic     tmp1, tmp1, #AT91_PMC_CSS
+        str     tmp1, [pmc, #AT91_PMC_MCKR]
 
         wait_mckrdy
 
@@ -177,61 +193,61 @@ ENTRY(at91_slow_clock)
          *
          * See AT91RM9200 errata #27 and #28 for details.
          */
-        mov     r3, #0
-        str     r3, [r1, #(AT91_PMC_MCKR - AT91_PMC)]
+        mov     tmp1, #0
+        str     tmp1, [pmc, #AT91_PMC_MCKR]
 
         wait_mckrdy
 #endif
 
         /* Save PLLA setting and disable it */
-        ldr     r3, [r1, #(AT91_CKGR_PLLAR - AT91_PMC)]
-        str     r3, .saved_pllar
+        ldr     tmp1, [pmc, #AT91_CKGR_PLLAR]
+        str     tmp1, .saved_pllar
 
-        mov     r3, #AT91_PMC_PLLCOUNT
-        orr     r3, r3, #(1 << 29)              /* bit 29 always set */
-        str     r3, [r1, #(AT91_CKGR_PLLAR - AT91_PMC)]
+        mov     tmp1, #AT91_PMC_PLLCOUNT
+        orr     tmp1, tmp1, #(1 << 29)          /* bit 29 always set */
+        str     tmp1, [pmc, #AT91_CKGR_PLLAR]
 
         /* Save PLLB setting and disable it */
-        ldr     r3, [r1, #(AT91_CKGR_PLLBR - AT91_PMC)]
-        str     r3, .saved_pllbr
+        ldr     tmp1, [pmc, #AT91_CKGR_PLLBR]
+        str     tmp1, .saved_pllbr
 
-        mov     r3, #AT91_PMC_PLLCOUNT
-        str     r3, [r1, #(AT91_CKGR_PLLBR - AT91_PMC)]
+        mov     tmp1, #AT91_PMC_PLLCOUNT
+        str     tmp1, [pmc, #AT91_CKGR_PLLBR]
 
         /* Turn off the main oscillator */
-        ldr     r3, [r1, #(AT91_CKGR_MOR - AT91_PMC)]
-        bic     r3, r3, #AT91_PMC_MOSCEN
-        str     r3, [r1, #(AT91_CKGR_MOR - AT91_PMC)]
+        ldr     tmp1, [pmc, #AT91_CKGR_MOR]
+        bic     tmp1, tmp1, #AT91_PMC_MOSCEN
+        str     tmp1, [pmc, #AT91_CKGR_MOR]
 
         /* Wait for interrupt */
-        mcr     p15, 0, r0, c7, c0, 4
+        mcr     p15, 0, tmp1, c7, c0, 4
 
         /* Turn on the main oscillator */
-        ldr     r3, [r1, #(AT91_CKGR_MOR - AT91_PMC)]
-        orr     r3, r3, #AT91_PMC_MOSCEN
-        str     r3, [r1, #(AT91_CKGR_MOR - AT91_PMC)]
+        ldr     tmp1, [pmc, #AT91_CKGR_MOR]
+        orr     tmp1, tmp1, #AT91_PMC_MOSCEN
+        str     tmp1, [pmc, #AT91_CKGR_MOR]
 
         wait_moscrdy
 
         /* Restore PLLB setting */
-        ldr     r3, .saved_pllbr
-        str     r3, [r1, #(AT91_CKGR_PLLBR - AT91_PMC)]
+        ldr     tmp1, .saved_pllbr
+        str     tmp1, [pmc, #AT91_CKGR_PLLBR]
 
-        tst     r3, #(AT91_PMC_MUL &  0xff0000)
+        tst     tmp1, #(AT91_PMC_MUL &  0xff0000)
         bne     1f
-        tst     r3, #(AT91_PMC_MUL & ~0xff0000)
+        tst     tmp1, #(AT91_PMC_MUL & ~0xff0000)
         beq     2f
 1:
         wait_pllblock
 2:
 
         /* Restore PLLA setting */
-        ldr     r3, .saved_pllar
-        str     r3, [r1, #(AT91_CKGR_PLLAR - AT91_PMC)]
+        ldr     tmp1, .saved_pllar
+        str     tmp1, [pmc, #AT91_CKGR_PLLAR]
 
-        tst     r3, #(AT91_PMC_MUL &  0xff0000)
+        tst     tmp1, #(AT91_PMC_MUL &  0xff0000)
         bne     3f
-        tst     r3, #(AT91_PMC_MUL & ~0xff0000)
+        tst     tmp1, #(AT91_PMC_MUL & ~0xff0000)
         beq     4f
 3:
         wait_pllalock
@@ -244,11 +260,11 @@ ENTRY(at91_slow_clock)
          *
          * See AT91RM9200 errata #27 and #28 for details.
          */
-        ldr     r3, .saved_mckr
-        tst     r3, #AT91_PMC_PRES
+        ldr     tmp1, .saved_mckr
+        tst     tmp1, #AT91_PMC_PRES
         beq     2f
-        and     r3, r3, #AT91_PMC_PRES
-        str     r3, [r1, #(AT91_PMC_MCKR - AT91_PMC)]
+        and     tmp1, tmp1, #AT91_PMC_PRES
+        str     tmp1, [pmc, #AT91_PMC_MCKR]
 
         wait_mckrdy
 #endif
@@ -256,32 +272,45 @@ ENTRY(at91_slow_clock)
         /*
          * Restore master clock setting
          */
-2:      ldr     r3, .saved_mckr
-        str     r3, [r1, #(AT91_PMC_MCKR - AT91_PMC)]
+2:      ldr     tmp1, .saved_mckr
+        str     tmp1, [pmc, #AT91_PMC_MCKR]
 
         wait_mckrdy
 
-#ifdef CONFIG_ARCH_AT91RM9200
-        /* Do nothing - self-refresh is automatically disabled. */
-#elif defined(CONFIG_ARCH_AT91CAP9) \
-        || defined(CONFIG_ARCH_AT91SAM9G45)
+        /*
+         * at91rm9200 Memory controller
+         * Do nothing - self-refresh is automatically disabled.
+         */
+        cmp     memctrl, #AT91_MEMCTRL_MC
+        beq     ram_restored
+
+        /*
+         * DDRSDR Memory controller
+         */
+        cmp     memctrl, #AT91_MEMCTRL_DDRSDR
+        bne     sdr_en_restore
         /* Restore LPR on AT91 with DDRAM */
-        ldr     r3, .saved_sam9_lpr
-        str     r3, [r2, #AT91_DDRSDRC_LPR]
+        ldr     tmp1, .saved_sam9_lpr
+        str     tmp1, [sdramc, #AT91_DDRSDRC_LPR]
 
         /* if we use the second ram controller */
-        cmp     r5, #0
-        ldrne   r4, .saved_sam9_lpr1
-        strne   r4, [r5, #AT91_DDRSDRC_LPR]
+        cmp     ramc1, #0
+        ldrne   tmp2, .saved_sam9_lpr1
+        strne   tmp2, [ramc1, #AT91_DDRSDRC_LPR]
+
+        b       ram_restored
 
-#else
+        /*
+         * SDRAMC Memory controller
+         */
+sdr_en_restore:
         /* Restore LPR on AT91 with SDRAM */
-        ldr     r3, .saved_sam9_lpr
-        str     r3, [r2, #AT91_SDRAMC_LPR]
-#endif
+        ldr     tmp1, .saved_sam9_lpr
+        str     tmp1, [sdramc, #AT91_SDRAMC_LPR]
 
+ram_restored:
         /* Restore registers, and return */
-        ldmfd   sp!, {r0 - r12, pc}
+        ldmfd   sp!, {r4 - r12, pc}
 
 
 .saved_mckr:
@@ -299,27 +328,5 @@ ENTRY(at91_slow_clock)
 .saved_sam9_lpr1:
         .word 0
 
-.at91_va_base_pmc:
-        .word AT91_VA_BASE_SYS + AT91_PMC
-
-#ifdef CONFIG_ARCH_AT91RM9200
-.at91_va_base_sdramc:
-        .word AT91_VA_BASE_SYS
-#elif defined(CONFIG_ARCH_AT91CAP9) \
-        || defined(CONFIG_ARCH_AT91SAM9G45)
-.at91_va_base_sdramc:
-        .word AT91_VA_BASE_SYS + AT91_DDRSDRC0
-#else
-.at91_va_base_sdramc:
-        .word AT91_VA_BASE_SYS + AT91_SDRAMC0
-#endif
-
-.at91_va_base_ramc1:
-#if defined(CONFIG_ARCH_AT91SAM9G45)
-        .word AT91_VA_BASE_SYS + AT91_DDRSDRC1
-#else
-        .word 0
-#endif
-
 ENTRY(at91_slow_clock_sz)
         .word .-at91_slow_clock
diff --git a/arch/arm/mach-at91/setup.c b/arch/arm/mach-at91/setup.c
index 69d3fc4c46f..372396c2ecb 100644
--- a/arch/arm/mach-at91/setup.c
+++ b/arch/arm/mach-at91/setup.c
@@ -86,20 +86,6 @@ static void __init soc_detect(u32 dbgu_base)
         socid = cidr & ~AT91_CIDR_VERSION;
 
         switch (socid) {
-        case ARCH_ID_AT91CAP9: {
-#ifdef CONFIG_AT91_PMC_UNIT
-                u32 pmc_ver = at91_sys_read(AT91_PMC_VER);
-
-                if (pmc_ver == ARCH_REVISION_CAP9_B)
-                        at91_soc_initdata.subtype = AT91_SOC_CAP9_REV_B;
-                else if (pmc_ver == ARCH_REVISION_CAP9_C)
-                        at91_soc_initdata.subtype = AT91_SOC_CAP9_REV_C;
-#endif
-                at91_soc_initdata.type = AT91_SOC_CAP9;
-                at91_boot_soc = at91cap9_soc;
-                break;
-        }
-
         case ARCH_ID_AT91RM9200:
                 at91_soc_initdata.type = AT91_SOC_RM9200;
                 at91_boot_soc = at91rm9200_soc;
@@ -200,7 +186,6 @@ static void __init soc_detect(u32 dbgu_base)
 
 static const char *soc_name[] = {
         [AT91_SOC_RM9200]       = "at91rm9200",
-        [AT91_SOC_CAP9]         = "at91cap9",
         [AT91_SOC_SAM9260]      = "at91sam9260",
         [AT91_SOC_SAM9261]      = "at91sam9261",
         [AT91_SOC_SAM9263]      = "at91sam9263",
@@ -221,8 +206,6 @@ EXPORT_SYMBOL(at91_get_soc_type);
 static const char *soc_subtype_name[] = {
         [AT91_SOC_RM9200_BGA]   = "at91rm9200 BGA",
         [AT91_SOC_RM9200_PQFP]  = "at91rm9200 PQFP",
-        [AT91_SOC_CAP9_REV_B]   = "at91cap9 revB",
-        [AT91_SOC_CAP9_REV_C]   = "at91cap9 revC",
         [AT91_SOC_SAM9XE]       = "at91sam9xe",
         [AT91_SOC_SAM9G45ES]    = "at91sam9g45es",
         [AT91_SOC_SAM9M10]      = "at91sam9m10",
@@ -293,6 +276,15 @@ void __init at91_ioremap_rstc(u32 base_addr)
                 panic("Impossible to ioremap at91_rstc_base\n");
 }
 
+void __iomem *at91_matrix_base;
+
+void __init at91_ioremap_matrix(u32 base_addr)
+{
+        at91_matrix_base = ioremap(base_addr, 512);
+        if (!at91_matrix_base)
+                panic("Impossible to ioremap at91_matrix_base\n");
+}
+
 void __init at91_initialize(unsigned long main_clock)
 {
         at91_boot_soc.ioremap_registers();
diff --git a/arch/arm/mach-at91/soc.h b/arch/arm/mach-at91/soc.h
index 4588ae6f7ac..5db4aa45404 100644
--- a/arch/arm/mach-at91/soc.h
+++ b/arch/arm/mach-at91/soc.h
@@ -13,7 +13,6 @@ struct at91_init_soc {
 };
 
 extern struct at91_init_soc at91_boot_soc;
-extern struct at91_init_soc at91cap9_soc;
 extern struct at91_init_soc at91rm9200_soc;
 extern struct at91_init_soc at91sam9260_soc;
 extern struct at91_init_soc at91sam9261_soc;
@@ -27,10 +26,6 @@ static inline int at91_soc_is_enabled(void)
         return at91_boot_soc.init != NULL;
 }
 
-#if !defined(CONFIG_ARCH_AT91CAP9)
-#define at91cap9_soc    at91_boot_soc
-#endif
-
 #if !defined(CONFIG_ARCH_AT91RM9200)
 #define at91rm9200_soc  at91_boot_soc
 #endif
diff --git a/arch/arm/mach-bcmring/core.c b/arch/arm/mach-bcmring/core.c
index 6b67b7e8426..22e4e0a28ad 100644
--- a/arch/arm/mach-bcmring/core.c
+++ b/arch/arm/mach-bcmring/core.c
@@ -52,27 +52,8 @@
 #include <mach/csp/chipcHw_inline.h>
 #include <mach/csp/tmrHw_reg.h>
 
-#define AMBA_DEVICE(name, initname, base, plat, size)       \
-static struct amba_device name##_device = {     \
-   .dev = {                                     \
-      .coherent_dma_mask = ~0,                  \
-      .init_name = initname,                    \
-      .platform_data = plat                     \
-   },                                           \
-   .res = {                                     \
-      .start = MM_ADDR_IO_##base,               \
-                .end = MM_ADDR_IO_##base + (size) - 1,    \
-      .flags = IORESOURCE_MEM                   \
-   },                                           \
-   .dma_mask = ~0,                              \
-   .irq = {                                     \
-      IRQ_##base                                \
-   }                                            \
-}
-
-
-AMBA_DEVICE(uartA, "uarta", UARTA, NULL, SZ_4K);
-AMBA_DEVICE(uartB, "uartb", UARTB, NULL, SZ_4K);
+static AMBA_APB_DEVICE(uartA, "uarta", MM_ADDR_IO_UARTA, { IRQ_UARTA }, NULL);
+static AMBA_APB_DEVICE(uartB, "uartb", MM_ADDR_IO_UARTB, { IRQ_UARTB }, NULL);
 
 static struct clk pll1_clk = {
         .name = "PLL1",
diff --git a/arch/arm/mach-bcmring/include/mach/entry-macro.S b/arch/arm/mach-bcmring/include/mach/entry-macro.S
index 94c950d783b..2f316f0e6e6 100644
--- a/arch/arm/mach-bcmring/include/mach/entry-macro.S
+++ b/arch/arm/mach-bcmring/include/mach/entry-macro.S
@@ -21,9 +21,6 @@
 #include <mach/hardware.h>
 #include <mach/csp/mm_io.h>
 
-                .macro  disable_fiq
-                .endm
-
                 .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
                 ldr     \base, =(MM_IO_BASE_INTC0)
                 ldr     \irqstat, [\base, #0]           @ get status
@@ -77,6 +74,3 @@
 
                 .macro  get_irqnr_preamble, base, tmp
                 .endm
-
-                .macro  arch_ret_to_user, tmp1, tmp2
-                .endm
diff --git a/arch/arm/mach-bcmring/include/mach/system.h b/arch/arm/mach-bcmring/include/mach/system.h
deleted file mode 100644
index cb78250db64..00000000000
--- a/arch/arm/mach-bcmring/include/mach/system.h
+++ /dev/null
@@ -1,28 +0,0 @@
-/*
- *
- *  Copyright (C) 1999 ARM Limited
- *  Copyright (C) 2000 Deep Blue Solutions Ltd
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#ifndef __ASM_ARCH_SYSTEM_H
-#define __ASM_ARCH_SYSTEM_H
-
-static inline void arch_idle(void)
-{
-        cpu_do_idle();
-}
-
-#endif
diff --git a/arch/arm/mach-clps711x/common.c b/arch/arm/mach-clps711x/common.c
index ab1711b9b4d..8736c1acc16 100644
--- a/arch/arm/mach-clps711x/common.c
+++ b/arch/arm/mach-clps711x/common.c
@@ -225,3 +225,19 @@ void clps711x_restart(char mode, const char *cmd)
 {
         soft_restart(0);
 }
+
+static void clps711x_idle(void)
+{
+        clps_writel(1, HALT);
+        __asm__ __volatile__(
+        "mov    r0, r0\n\
+        mov     r0, r0");
+}
+
+static int __init clps711x_idle_init(void)
+{
+        arm_pm_idle = clps711x_idle;
+        return 0;
+}
+
+arch_initcall(clps711x_idle_init);
diff --git a/arch/arm/mach-clps711x/include/mach/entry-macro.S b/arch/arm/mach-clps711x/include/mach/entry-macro.S
index 90fa2f70489..125af59d7a2 100644
--- a/arch/arm/mach-clps711x/include/mach/entry-macro.S
+++ b/arch/arm/mach-clps711x/include/mach/entry-macro.S
@@ -10,15 +10,9 @@
 #include <mach/hardware.h>
 #include <asm/hardware/clps7111.h>
 
-                .macro  disable_fiq
-                .endm
-
                 .macro  get_irqnr_preamble, base, tmp
                 .endm
 
-                .macro  arch_ret_to_user, tmp1, tmp2
-                .endm
-
 #if (INTSR2 - INTSR1) != (INTMR2 - INTMR1)
 #error INTSR stride != INTMR stride
 #endif
diff --git a/arch/arm/mach-clps711x/include/mach/system.h b/arch/arm/mach-clps711x/include/mach/system.h
deleted file mode 100644
index 23d6ef8c84d..00000000000
--- a/arch/arm/mach-clps711x/include/mach/system.h
+++ /dev/null
@@ -1,35 +0,0 @@
-/*
- *  arch/arm/mach-clps711x/include/mach/system.h
- *
- *  Copyright (C) 2000 Deep Blue Solutions Ltd
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#ifndef __ASM_ARCH_SYSTEM_H
-#define __ASM_ARCH_SYSTEM_H
-
-#include <linux/io.h>
-#include <mach/hardware.h>
-#include <asm/hardware/clps7111.h>
-
-static inline void arch_idle(void)
-{
-        clps_writel(1, HALT);
-        __asm__ __volatile__(
-        "mov    r0, r0\n\
-        mov     r0, r0");
-}
-
-#endif
diff --git a/arch/arm/mach-cns3xxx/include/mach/entry-macro.S b/arch/arm/mach-cns3xxx/include/mach/entry-macro.S
deleted file mode 100644
index 01c57df5f71..00000000000
--- a/arch/arm/mach-cns3xxx/include/mach/entry-macro.S
+++ /dev/null
@@ -1,15 +0,0 @@
-/*
- * Low-level IRQ helper macros for Cavium Networks platforms
- *
- * Copyright 2008 Cavium Networks
- *
- * This file is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License, Version 2, as
- * published by the Free Software Foundation.
- */
-
-                .macro  disable_fiq
-                .endm
-
-                .macro  arch_ret_to_user, tmp1, tmp2
-                .endm
diff --git a/arch/arm/mach-cns3xxx/include/mach/system.h b/arch/arm/mach-cns3xxx/include/mach/system.h
deleted file mode 100644
index 9e56b7dc133..00000000000
--- a/arch/arm/mach-cns3xxx/include/mach/system.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * Copyright 2000 Deep Blue Solutions Ltd
- * Copyright 2003 ARM Limited
- * Copyright 2008 Cavium Networks
- *
- * This file is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License, Version 2, as
- * published by the Free Software Foundation.
- */
-
-#ifndef __MACH_SYSTEM_H
-#define __MACH_SYSTEM_H
-
-#include <asm/proc-fns.h>
-
-static inline void arch_idle(void)
-{
-        /*
-         * This should do all the clock switching
-         * and wait for interrupt tricks
-         */
-        cpu_do_idle();
-}
-
-#endif
diff --git a/arch/arm/mach-cns3xxx/pcie.c b/arch/arm/mach-cns3xxx/pcie.c
index e159d69967c..79d001f831e 100644
--- a/arch/arm/mach-cns3xxx/pcie.c
+++ b/arch/arm/mach-cns3xxx/pcie.c
@@ -155,8 +155,8 @@ static int cns3xxx_pci_setup(int nr, struct pci_sys_data *sys)
         BUG_ON(request_resource(&iomem_resource, res_io) ||
                request_resource(&iomem_resource, res_mem));
 
-        pci_add_resource(&sys->resources, res_io);
-        pci_add_resource(&sys->resources, res_mem);
+        pci_add_resource_offset(&sys->resources, res_io, sys->io_offset);
+        pci_add_resource_offset(&sys->resources, res_mem, sys->mem_offset);
 
         return 1;
 }
diff --git a/arch/arm/mach-davinci/board-dm355-evm.c b/arch/arm/mach-davinci/board-dm355-evm.c
index 275341f159f..82ed753fb36 100644
--- a/arch/arm/mach-davinci/board-dm355-evm.c
+++ b/arch/arm/mach-davinci/board-dm355-evm.c
@@ -26,13 +26,14 @@
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 
-#include <mach/dm355.h>
 #include <mach/i2c.h>
 #include <mach/serial.h>
 #include <mach/nand.h>
 #include <mach/mmc.h>
 #include <mach/usb.h>
 
+#include "davinci.h"
+
 /* NOTE:  this is geared for the standard config, with a socketed
  * 2 GByte Micron NAND (MT29F16G08FAA) using 128KB sectors.  If you
  * swap chips, maybe with a different block size, partitioning may
diff --git a/arch/arm/mach-davinci/board-dm355-leopard.c b/arch/arm/mach-davinci/board-dm355-leopard.c
index e99db28181a..d74a8b3445f 100644
--- a/arch/arm/mach-davinci/board-dm355-leopard.c
+++ b/arch/arm/mach-davinci/board-dm355-leopard.c
@@ -23,13 +23,14 @@
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 
-#include <mach/dm355.h>
 #include <mach/i2c.h>
 #include <mach/serial.h>
 #include <mach/nand.h>
 #include <mach/mmc.h>
 #include <mach/usb.h>
 
+#include "davinci.h"
+
 /* NOTE:  this is geared for the standard config, with a socketed
  * 2 GByte Micron NAND (MT29F16G08FAA) using 128KB sectors.  If you
  * swap chips, maybe with a different block size, partitioning may
diff --git a/arch/arm/mach-davinci/board-dm365-evm.c b/arch/arm/mach-davinci/board-dm365-evm.c
index 849311d3cb7..5bce2b83bb4 100644
--- a/arch/arm/mach-davinci/board-dm365-evm.c
+++ b/arch/arm/mach-davinci/board-dm365-evm.c
@@ -32,7 +32,6 @@
 #include <asm/mach/arch.h>
 
 #include <mach/mux.h>
-#include <mach/dm365.h>
 #include <mach/common.h>
 #include <mach/i2c.h>
 #include <mach/serial.h>
@@ -42,6 +41,8 @@
 
 #include <media/tvp514x.h>
 
+#include "davinci.h"
+
 static inline int have_imager(void)
 {
         /* REVISIT when it's supported, trigger via Kconfig */
diff --git a/arch/arm/mach-davinci/board-dm644x-evm.c b/arch/arm/mach-davinci/board-dm644x-evm.c
index 1247ecdcf75..864f676ecca 100644
--- a/arch/arm/mach-davinci/board-dm644x-evm.c
+++ b/arch/arm/mach-davinci/board-dm644x-evm.c
@@ -30,7 +30,6 @@
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 
-#include <mach/dm644x.h>
 #include <mach/common.h>
 #include <mach/i2c.h>
 #include <mach/serial.h>
@@ -40,6 +39,8 @@
 #include <mach/usb.h>
 #include <mach/aemif.h>
 
+#include "davinci.h"
+
 #define DM644X_EVM_PHY_ID               "davinci_mdio-0:01"
 #define LXT971_PHY_ID   (0x001378e2)
 #define LXT971_PHY_MASK (0xfffffff0)
@@ -189,7 +190,7 @@ static struct platform_device davinci_fb_device = {
         .num_resources = 0,
 };
 
-static struct tvp514x_platform_data tvp5146_pdata = {
+static struct tvp514x_platform_data dm644xevm_tvp5146_pdata = {
         .clk_polarity = 0,
         .hs_polarity = 1,
         .vs_polarity = 1
@@ -197,7 +198,7 @@ static struct tvp514x_platform_data tvp5146_pdata = {
 
 #define TVP514X_STD_ALL (V4L2_STD_NTSC | V4L2_STD_PAL)
 /* Inputs available at the TVP5146 */
-static struct v4l2_input tvp5146_inputs[] = {
+static struct v4l2_input dm644xevm_tvp5146_inputs[] = {
         {
                 .index = 0,
                 .name = "Composite",
@@ -217,7 +218,7 @@ static struct v4l2_input tvp5146_inputs[] = {
  * ouput that goes to vpfe. There is a one to one correspondence
  * with tvp5146_inputs
  */
-static struct vpfe_route tvp5146_routes[] = {
+static struct vpfe_route dm644xevm_tvp5146_routes[] = {
         {
                 .input = INPUT_CVBS_VI2B,
                 .output = OUTPUT_10BIT_422_EMBEDDED_SYNC,
@@ -228,13 +229,13 @@ static struct vpfe_route tvp5146_routes[] = {
         },
 };
 
-static struct vpfe_subdev_info vpfe_sub_devs[] = {
+static struct vpfe_subdev_info dm644xevm_vpfe_sub_devs[] = {
         {
                 .name = "tvp5146",
                 .grp_id = 0,
-                .num_inputs = ARRAY_SIZE(tvp5146_inputs),
-                .inputs = tvp5146_inputs,
-                .routes = tvp5146_routes,
+                .num_inputs = ARRAY_SIZE(dm644xevm_tvp5146_inputs),
+                .inputs = dm644xevm_tvp5146_inputs,
+                .routes = dm644xevm_tvp5146_routes,
                 .can_route = 1,
                 .ccdc_if_params = {
                         .if_type = VPFE_BT656,
@@ -243,15 +244,15 @@ static struct vpfe_subdev_info vpfe_sub_devs[] = {
                 },
                 .board_info = {
                         I2C_BOARD_INFO("tvp5146", 0x5d),
-                        .platform_data = &tvp5146_pdata,
+                        .platform_data = &dm644xevm_tvp5146_pdata,
                 },
         },
 };
 
-static struct vpfe_config vpfe_cfg = {
-        .num_subdevs = ARRAY_SIZE(vpfe_sub_devs),
+static struct vpfe_config dm644xevm_capture_cfg = {
+        .num_subdevs = ARRAY_SIZE(dm644xevm_vpfe_sub_devs),
         .i2c_adapter_id = 1,
-        .sub_devs = vpfe_sub_devs,
+        .sub_devs = dm644xevm_vpfe_sub_devs,
         .card_name = "DM6446 EVM",
         .ccdc = "DM6446 CCDC",
 };
@@ -624,8 +625,6 @@ static struct davinci_uart_config uart_config __initdata = {
 static void __init
 davinci_evm_map_io(void)
 {
-        /* setup input configuration for VPFE input devices */
-        dm644x_set_vpfe_config(&vpfe_cfg);
         dm644x_init();
 }
 
@@ -697,6 +696,7 @@ static __init void davinci_evm_init(void)
         evm_init_i2c();
 
         davinci_setup_mmc(0, &dm6446evm_mmc_config);
+        dm644x_init_video(&dm644xevm_capture_cfg);
 
         davinci_serial_init(&uart_config);
         dm644x_init_asp(&dm644x_evm_snd_data);
diff --git a/arch/arm/mach-davinci/board-dm646x-evm.c b/arch/arm/mach-davinci/board-dm646x-evm.c
index 872ac69fa04..d72ab948d63 100644
--- a/arch/arm/mach-davinci/board-dm646x-evm.c
+++ b/arch/arm/mach-davinci/board-dm646x-evm.c
@@ -36,7 +36,6 @@
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 
-#include <mach/dm646x.h>
 #include <mach/common.h>
 #include <mach/serial.h>
 #include <mach/i2c.h>
@@ -45,6 +44,7 @@
 #include <mach/cdce949.h>
 #include <mach/aemif.h>
 
+#include "davinci.h"
 #include "clock.h"
 
 #define NAND_BLOCK_SIZE         SZ_128K
@@ -410,8 +410,6 @@ static struct davinci_i2c_platform_data i2c_pdata = {
         .bus_delay      = 0 /* usec */,
 };
 
-#define VIDCLKCTL_OFFSET        (DAVINCI_SYSTEM_MODULE_BASE + 0x38)
-#define VSCLKDIS_OFFSET         (DAVINCI_SYSTEM_MODULE_BASE + 0x6c)
 #define VCH2CLK_MASK            (BIT_MASK(10) | BIT_MASK(9) | BIT_MASK(8))
 #define VCH2CLK_SYSCLK8         (BIT(9))
 #define VCH2CLK_AUXCLK          (BIT(9) | BIT(8))
@@ -429,8 +427,6 @@ static struct davinci_i2c_platform_data i2c_pdata = {
 #define TVP5147_CH0             "tvp514x-0"
 #define TVP5147_CH1             "tvp514x-1"
 
-static void __iomem *vpif_vidclkctl_reg;
-static void __iomem *vpif_vsclkdis_reg;
 /* spin lock for updating above registers */
 static spinlock_t vpif_reg_lock;
 
@@ -441,14 +437,14 @@ static int set_vpif_clock(int mux_mode, int hd)
         int val = 0;
         int err = 0;
 
-        if (!vpif_vidclkctl_reg || !vpif_vsclkdis_reg || !cpld_client)
+        if (!cpld_client)
                 return -ENXIO;
 
         /* disable the clock */
         spin_lock_irqsave(&vpif_reg_lock, flags);
-        value = __raw_readl(vpif_vsclkdis_reg);
+        value = __raw_readl(DAVINCI_SYSMOD_VIRT(SYSMOD_VSCLKDIS));
         value |= (VIDCH3CLK | VIDCH2CLK);
-        __raw_writel(value, vpif_vsclkdis_reg);
+        __raw_writel(value, DAVINCI_SYSMOD_VIRT(SYSMOD_VSCLKDIS));
         spin_unlock_irqrestore(&vpif_reg_lock, flags);
 
         val = i2c_smbus_read_byte(cpld_client);
@@ -464,7 +460,7 @@ static int set_vpif_clock(int mux_mode, int hd)
         if (err)
                 return err;
 
-        value = __raw_readl(vpif_vidclkctl_reg);
+        value = __raw_readl(DAVINCI_SYSMOD_VIRT(SYSMOD_VIDCLKCTL));
         value &= ~(VCH2CLK_MASK);
         value &= ~(VCH3CLK_MASK);
 
@@ -473,13 +469,13 @@ static int set_vpif_clock(int mux_mode, int hd)
         else
                 value |= (VCH2CLK_AUXCLK | VCH3CLK_AUXCLK);
 
-        __raw_writel(value, vpif_vidclkctl_reg);
+        __raw_writel(value, DAVINCI_SYSMOD_VIRT(SYSMOD_VIDCLKCTL));
 
         spin_lock_irqsave(&vpif_reg_lock, flags);
-        value = __raw_readl(vpif_vsclkdis_reg);
+        value = __raw_readl(DAVINCI_SYSMOD_VIRT(SYSMOD_VSCLKDIS));
         /* enable the clock */
         value &= ~(VIDCH3CLK | VIDCH2CLK);
-        __raw_writel(value, vpif_vsclkdis_reg);
+        __raw_writel(value, DAVINCI_SYSMOD_VIRT(SYSMOD_VSCLKDIS));
         spin_unlock_irqrestore(&vpif_reg_lock, flags);
 
         return 0;
@@ -564,7 +560,7 @@ static int setup_vpif_input_channel_mode(int mux_mode)
         int val;
         u32 value;
 
-        if (!vpif_vidclkctl_reg || !cpld_client)
+        if (!cpld_client)
                 return -ENXIO;
 
         val = i2c_smbus_read_byte(cpld_client);
@@ -572,7 +568,7 @@ static int setup_vpif_input_channel_mode(int mux_mode)
                 return val;
 
         spin_lock_irqsave(&vpif_reg_lock, flags);
-        value = __raw_readl(vpif_vidclkctl_reg);
+        value = __raw_readl(DAVINCI_SYSMOD_VIRT(SYSMOD_VIDCLKCTL));
         if (mux_mode) {
                 val &= VPIF_INPUT_TWO_CHANNEL;
                 value |= VIDCH1CLK;
@@ -580,7 +576,7 @@ static int setup_vpif_input_channel_mode(int mux_mode)
                 val |= VPIF_INPUT_ONE_CHANNEL;
                 value &= ~VIDCH1CLK;
         }
-        __raw_writel(value, vpif_vidclkctl_reg);
+        __raw_writel(value, DAVINCI_SYSMOD_VIRT(SYSMOD_VIDCLKCTL));
         spin_unlock_irqrestore(&vpif_reg_lock, flags);
 
         err = i2c_smbus_write_byte(cpld_client, val);
@@ -674,12 +670,6 @@ static struct vpif_capture_config dm646x_vpif_capture_cfg = {
 
 static void __init evm_init_video(void)
 {
-        vpif_vidclkctl_reg = ioremap(VIDCLKCTL_OFFSET, 4);
-        vpif_vsclkdis_reg = ioremap(VSCLKDIS_OFFSET, 4);
-        if (!vpif_vidclkctl_reg || !vpif_vsclkdis_reg) {
-                pr_err("Can't map VPIF VIDCLKCTL or VSCLKDIS registers\n");
-                return;
-        }
         spin_lock_init(&vpif_reg_lock);
 
         dm646x_setup_vpif(&dm646x_vpif_display_config,
diff --git a/arch/arm/mach-davinci/board-neuros-osd2.c b/arch/arm/mach-davinci/board-neuros-osd2.c
index 8d34f513d41..a772bb45570 100644
--- a/arch/arm/mach-davinci/board-neuros-osd2.c
+++ b/arch/arm/mach-davinci/board-neuros-osd2.c
@@ -30,7 +30,6 @@
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 
-#include <mach/dm644x.h>
 #include <mach/common.h>
 #include <mach/i2c.h>
 #include <mach/serial.h>
@@ -39,6 +38,8 @@
 #include <mach/mmc.h>
 #include <mach/usb.h>
 
+#include "davinci.h"
+
 #define NEUROS_OSD2_PHY_ID              "davinci_mdio-0:01"
 #define LXT971_PHY_ID                   0x001378e2
 #define LXT971_PHY_MASK                 0xfffffff0
diff --git a/arch/arm/mach-davinci/board-sffsdr.c b/arch/arm/mach-davinci/board-sffsdr.c
index 31da3c5b2ba..76e67509610 100644
--- a/arch/arm/mach-davinci/board-sffsdr.c
+++ b/arch/arm/mach-davinci/board-sffsdr.c
@@ -35,13 +35,14 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/flash.h>
 
-#include <mach/dm644x.h>
 #include <mach/common.h>
 #include <mach/i2c.h>
 #include <mach/serial.h>
 #include <mach/mux.h>
 #include <mach/usb.h>
 
+#include "davinci.h"
+
 #define SFFSDR_PHY_ID           "davinci_mdio-0:01"
 static struct mtd_partition davinci_sffsdr_nandflash_partition[] = {
         /* U-Boot Environment: Block 0
diff --git a/arch/arm/mach-davinci/cpufreq.c b/arch/arm/mach-davinci/cpufreq.c
index 5bba7070f27..031048fec9f 100644
--- a/arch/arm/mach-davinci/cpufreq.c
+++ b/arch/arm/mach-davinci/cpufreq.c
@@ -95,7 +95,7 @@ static int davinci_target(struct cpufreq_policy *policy,
         if (freqs.old == freqs.new)
                 return ret;
 
-        dev_dbg(&cpufreq.dev, "transition: %u --> %u\n", freqs.old, freqs.new);
+        dev_dbg(cpufreq.dev, "transition: %u --> %u\n", freqs.old, freqs.new);
 
         ret = cpufreq_frequency_table_target(policy, pdata->freq_table,
                                                 freqs.new, relation, &idx);
diff --git a/arch/arm/mach-davinci/da850.c b/arch/arm/mach-davinci/da850.c
index 992c4c41018..b44dc844e15 100644
--- a/arch/arm/mach-davinci/da850.c
+++ b/arch/arm/mach-davinci/da850.c
@@ -1026,7 +1026,7 @@ static int da850_round_armrate(struct clk *clk, unsigned long rate)
 }
 #endif
 
-int da850_register_pm(struct platform_device *pdev)
+int __init da850_register_pm(struct platform_device *pdev)
 {
         int ret;
         struct davinci_pm_config *pdata = pdev->dev.platform_data;
diff --git a/arch/arm/mach-davinci/davinci.h b/arch/arm/mach-davinci/davinci.h
new file mode 100644
index 00000000000..9d708034b57
--- /dev/null
+++ b/arch/arm/mach-davinci/davinci.h
@@ -0,0 +1,96 @@
+/*
+ * This file contains the processor specific definitions
+ * of the TI DM644x, DM355, DM365, and DM646x.
+ *
+ * Copyright (C) 2011 Texas Instruments Incorporated
+ * Copyright (c) 2007 Deep Root Systems, LLC
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#ifndef __DAVINCI_H
+#define __DAVINCI_H
+
+#include <linux/clk.h>
+#include <linux/videodev2.h>
+#include <linux/davinci_emac.h>
+#include <linux/platform_device.h>
+#include <linux/spi/spi.h>
+
+#include <mach/asp.h>
+#include <mach/keyscan.h>
+#include <mach/hardware.h>
+
+#include <media/davinci/vpfe_capture.h>
+#include <media/davinci/vpif_types.h>
+
+#define DAVINCI_SYSTEM_MODULE_BASE      0x01c40000
+#define SYSMOD_VIDCLKCTL                0x38
+#define SYSMOD_VDD3P3VPWDN              0x48
+#define SYSMOD_VSCLKDIS                 0x6c
+#define SYSMOD_PUPDCTL1                 0x7c
+
+extern void __iomem *davinci_sysmod_base;
+#define DAVINCI_SYSMOD_VIRT(x)  (davinci_sysmod_base + (x))
+void davinci_map_sysmod(void);
+
+/* DM355 base addresses */
+#define DM355_ASYNC_EMIF_CONTROL_BASE   0x01e10000
+#define DM355_ASYNC_EMIF_DATA_CE0_BASE  0x02000000
+
+#define ASP1_TX_EVT_EN  1
+#define ASP1_RX_EVT_EN  2
+
+/* DM365 base addresses */
+#define DM365_ASYNC_EMIF_CONTROL_BASE   0x01d10000
+#define DM365_ASYNC_EMIF_DATA_CE0_BASE  0x02000000
+#define DM365_ASYNC_EMIF_DATA_CE1_BASE  0x04000000
+
+/* DM644x base addresses */
+#define DM644X_ASYNC_EMIF_CONTROL_BASE  0x01e00000
+#define DM644X_ASYNC_EMIF_DATA_CE0_BASE 0x02000000
+#define DM644X_ASYNC_EMIF_DATA_CE1_BASE 0x04000000
+#define DM644X_ASYNC_EMIF_DATA_CE2_BASE 0x06000000
+#define DM644X_ASYNC_EMIF_DATA_CE3_BASE 0x08000000
+
+/* DM646x base addresses */
+#define DM646X_ASYNC_EMIF_CONTROL_BASE  0x20008000
+#define DM646X_ASYNC_EMIF_CS2_SPACE_BASE 0x42000000
+
+/* DM355 function declarations */
+void __init dm355_init(void);
+void dm355_init_spi0(unsigned chipselect_mask,
+                struct spi_board_info *info, unsigned len);
+void __init dm355_init_asp1(u32 evt_enable, struct snd_platform_data *pdata);
+void dm355_set_vpfe_config(struct vpfe_config *cfg);
+
+/* DM365 function declarations */
+void __init dm365_init(void);
+void __init dm365_init_asp(struct snd_platform_data *pdata);
+void __init dm365_init_vc(struct snd_platform_data *pdata);
+void __init dm365_init_ks(struct davinci_ks_platform_data *pdata);
+void __init dm365_init_rtc(void);
+void dm365_init_spi0(unsigned chipselect_mask,
+                        struct spi_board_info *info, unsigned len);
+void dm365_set_vpfe_config(struct vpfe_config *cfg);
+
+/* DM644x function declarations */
+void __init dm644x_init(void);
+void __init dm644x_init_asp(struct snd_platform_data *pdata);
+int __init dm644x_init_video(struct vpfe_config *);
+
+/* DM646x function declarations */
+void __init dm646x_init(void);
+void __init dm646x_init_mcasp0(struct snd_platform_data *pdata);
+void __init dm646x_init_mcasp1(struct snd_platform_data *pdata);
+int __init dm646x_init_edma(struct edma_rsv_info *rsv);
+void dm646x_video_init(void);
+void dm646x_setup_vpif(struct vpif_display_config *,
+                       struct vpif_capture_config *);
+#endif /*__DAVINCI_H */
diff --git a/arch/arm/mach-davinci/devices.c b/arch/arm/mach-davinci/devices.c
index 50c0156b426..d2f9666284a 100644
--- a/arch/arm/mach-davinci/devices.c
+++ b/arch/arm/mach-davinci/devices.c
@@ -23,6 +23,7 @@
 #include <mach/mmc.h>
 #include <mach/time.h>
 
+#include "davinci.h"
 #include "clock.h"
 
 #define DAVINCI_I2C_BASE             0x01C21000
@@ -33,8 +34,19 @@
 #define DM365_MMCSD0_BASE            0x01D11000
 #define DM365_MMCSD1_BASE            0x01D00000
 
-/* System control register offsets */
-#define DM64XX_VDD3P3V_PWDN     0x48
+void __iomem  *davinci_sysmod_base;
+
+void davinci_map_sysmod(void)
+{
+        davinci_sysmod_base = ioremap_nocache(DAVINCI_SYSTEM_MODULE_BASE,
+                                              0x800);
+        /*
+         * Throw a bug since a lot of board initialization code depends
+         * on system module availability. ioremap() failing this early
+         * need careful looking into anyway.
+         */
+        BUG_ON(!davinci_sysmod_base);
+}
 
 static struct resource i2c_resources[] = {
         {
@@ -212,12 +224,12 @@ void __init davinci_setup_mmc(int module, struct davinci_mmc_config *config)
                         davinci_cfg_reg(DM355_SD1_DATA2);
                         davinci_cfg_reg(DM355_SD1_DATA3);
                 } else if (cpu_is_davinci_dm365()) {
-                        void __iomem *pupdctl1 =
-                                IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE + 0x7c);
-
                         /* Configure pull down control */
-                        __raw_writel((__raw_readl(pupdctl1) & ~0xfc0),
-                                        pupdctl1);
+                        unsigned v;
+
+                        v = __raw_readl(DAVINCI_SYSMOD_VIRT(SYSMOD_PUPDCTL1));
+                        __raw_writel(v & ~0xfc0,
+                                        DAVINCI_SYSMOD_VIRT(SYSMOD_PUPDCTL1));
 
                         mmcsd1_resources[0].start = DM365_MMCSD1_BASE;
                         mmcsd1_resources[0].end = DM365_MMCSD1_BASE +
@@ -246,11 +258,9 @@ void __init davinci_setup_mmc(int module, struct davinci_mmc_config *config)
                         mmcsd0_resources[2].start = IRQ_DM365_SDIOINT0;
                 } else if (cpu_is_davinci_dm644x()) {
                         /* REVISIT: should this be in board-init code? */
-                        void __iomem *base =
-                                IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE);
-
                         /* Power-on 3.3V IO cells */
-                        __raw_writel(0, base + DM64XX_VDD3P3V_PWDN);
+                        __raw_writel(0,
+                                DAVINCI_SYSMOD_VIRT(SYSMOD_VDD3P3VPWDN));
                         /*Set up the pull regiter for MMC */
                         davinci_cfg_reg(DM644X_MSTK);
                 }
diff --git a/arch/arm/mach-davinci/dm355.c b/arch/arm/mach-davinci/dm355.c
index 19667cfc5de..fd3d09aa6cd 100644
--- a/arch/arm/mach-davinci/dm355.c
+++ b/arch/arm/mach-davinci/dm355.c
@@ -18,7 +18,6 @@
 
 #include <asm/mach/map.h>
 
-#include <mach/dm355.h>
 #include <mach/cputype.h>
 #include <mach/edma.h>
 #include <mach/psc.h>
@@ -31,6 +30,7 @@
 #include <mach/spi.h>
 #include <mach/gpio-davinci.h>
 
+#include "davinci.h"
 #include "clock.h"
 #include "mux.h"
 
@@ -871,6 +871,7 @@ void __init dm355_init_asp1(u32 evt_enable, struct snd_platform_data *pdata)
 void __init dm355_init(void)
 {
         davinci_common_init(&davinci_soc_info_dm355);
+        davinci_map_sysmod();
 }
 
 static int __init dm355_init_devices(void)
diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-davinci/dm365.c
index f15b435cc65..1a2e953082b 100644
--- a/arch/arm/mach-davinci/dm365.c
+++ b/arch/arm/mach-davinci/dm365.c
@@ -21,7 +21,6 @@
 
 #include <asm/mach/map.h>
 
-#include <mach/dm365.h>
 #include <mach/cputype.h>
 #include <mach/edma.h>
 #include <mach/psc.h>
@@ -35,11 +34,28 @@
 #include <mach/spi.h>
 #include <mach/gpio-davinci.h>
 
+#include "davinci.h"
 #include "clock.h"
 #include "mux.h"
 
 #define DM365_REF_FREQ          24000000        /* 24 MHz on the DM365 EVM */
 
+/* Base of key scan register bank */
+#define DM365_KEYSCAN_BASE              0x01c69400
+
+#define DM365_RTC_BASE                  0x01c69000
+
+#define DAVINCI_DM365_VC_BASE           0x01d0c000
+#define DAVINCI_DMA_VC_TX               2
+#define DAVINCI_DMA_VC_RX               3
+
+#define DM365_EMAC_BASE                 0x01d07000
+#define DM365_EMAC_MDIO_BASE            (DM365_EMAC_BASE + 0x4000)
+#define DM365_EMAC_CNTRL_OFFSET         0x0000
+#define DM365_EMAC_CNTRL_MOD_OFFSET     0x3000
+#define DM365_EMAC_CNTRL_RAM_OFFSET     0x1000
+#define DM365_EMAC_CNTRL_RAM_SIZE       0x2000
+
 static struct pll_data pll1_data = {
         .num            = 1,
         .phys_base      = DAVINCI_PLL1_BASE,
@@ -1122,6 +1138,7 @@ void __init dm365_init_rtc(void)
 void __init dm365_init(void)
 {
         davinci_common_init(&davinci_soc_info_dm365);
+        davinci_map_sysmod();
 }
 
 static struct resource dm365_vpss_resources[] = {
diff --git a/arch/arm/mach-davinci/dm644x.c b/arch/arm/mach-davinci/dm644x.c
index 43a48ee1917..23e81cafba8 100644
--- a/arch/arm/mach-davinci/dm644x.c
+++ b/arch/arm/mach-davinci/dm644x.c
@@ -15,7 +15,6 @@
 
 #include <asm/mach/map.h>
 
-#include <mach/dm644x.h>
 #include <mach/cputype.h>
 #include <mach/edma.h>
 #include <mach/irqs.h>
@@ -27,6 +26,7 @@
 #include <mach/asp.h>
 #include <mach/gpio-davinci.h>
 
+#include "davinci.h"
 #include "clock.h"
 #include "mux.h"
 
@@ -35,6 +35,13 @@
  */
 #define DM644X_REF_FREQ         27000000
 
+#define DM644X_EMAC_BASE                0x01c80000
+#define DM644X_EMAC_MDIO_BASE           (DM644X_EMAC_BASE + 0x4000)
+#define DM644X_EMAC_CNTRL_OFFSET        0x0000
+#define DM644X_EMAC_CNTRL_MOD_OFFSET    0x1000
+#define DM644X_EMAC_CNTRL_RAM_OFFSET    0x2000
+#define DM644X_EMAC_CNTRL_RAM_SIZE      0x2000
+
 static struct pll_data pll1_data = {
         .num       = 1,
         .phys_base = DAVINCI_PLL1_BASE,
@@ -587,13 +594,15 @@ static struct platform_device dm644x_asp_device = {
         .resource       = dm644x_asp_resources,
 };
 
+#define DM644X_VPSS_BASE        0x01c73400
+
 static struct resource dm644x_vpss_resources[] = {
         {
                 /* VPSS Base address */
                 .name           = "vpss",
-                .start          = 0x01c73400,
-                .end            = 0x01c73400 + 0xff,
-                .flags          = IORESOURCE_MEM,
+                .start          = DM644X_VPSS_BASE,
+                .end            = DM644X_VPSS_BASE + 0xff,
+                .flags          = IORESOURCE_MEM,
         },
 };
 
@@ -605,7 +614,7 @@ static struct platform_device dm644x_vpss_device = {
         .resource               = dm644x_vpss_resources,
 };
 
-static struct resource vpfe_resources[] = {
+static struct resource dm644x_vpfe_resources[] = {
         {
                 .start          = IRQ_VDINT0,
                 .end            = IRQ_VDINT0,
@@ -639,22 +648,17 @@ static struct platform_device dm644x_ccdc_dev = {
         },
 };
 
-static struct platform_device vpfe_capture_dev = {
+static struct platform_device dm644x_vpfe_dev = {
         .name           = CAPTURE_DRV_NAME,
         .id             = -1,
-        .num_resources  = ARRAY_SIZE(vpfe_resources),
-        .resource       = vpfe_resources,
+        .num_resources  = ARRAY_SIZE(dm644x_vpfe_resources),
+        .resource       = dm644x_vpfe_resources,
         .dev = {
                 .dma_mask               = &vpfe_capture_dma_mask,
                 .coherent_dma_mask      = DMA_BIT_MASK(32),
         },
 };
 
-void dm644x_set_vpfe_config(struct vpfe_config *cfg)
-{
-        vpfe_capture_dev.dev.platform_data = cfg;
-}
-
 /*----------------------------------------------------------------------*/
 
 static struct map_desc dm644x_io_desc[] = {
@@ -779,16 +783,29 @@ void __init dm644x_init_asp(struct snd_platform_data *pdata)
 void __init dm644x_init(void)
 {
         davinci_common_init(&davinci_soc_info_dm644x);
+        davinci_map_sysmod();
 }
 
-static int __init dm644x_init_devices(void)
+int __init dm644x_init_video(struct vpfe_config *vpfe_cfg)
 {
-        if (!cpu_is_davinci_dm644x())
-                return 0;
+        dm644x_vpfe_dev.dev.platform_data = vpfe_cfg;
 
         /* Add ccdc clock aliases */
         clk_add_alias("master", dm644x_ccdc_dev.name, "vpss_master", NULL);
         clk_add_alias("slave", dm644x_ccdc_dev.name, "vpss_slave", NULL);
+
+        platform_device_register(&dm644x_vpss_device);
+        platform_device_register(&dm644x_ccdc_dev);
+        platform_device_register(&dm644x_vpfe_dev);
+
+        return 0;
+}
+
+static int __init dm644x_init_devices(void)
+{
+        if (!cpu_is_davinci_dm644x())
+                return 0;
+
         platform_device_register(&dm644x_edma_device);
 
         platform_device_register(&dm644x_mdio_device);
@@ -796,10 +813,6 @@ static int __init dm644x_init_devices(void)
         clk_add_alias(NULL, dev_name(&dm644x_mdio_device.dev),
                       NULL, &dm644x_emac_device.dev);
 
-        platform_device_register(&dm644x_vpss_device);
-        platform_device_register(&dm644x_ccdc_dev);
-        platform_device_register(&vpfe_capture_dev);
-
         return 0;
 }
 postcore_initcall(dm644x_init_devices);
diff --git a/arch/arm/mach-davinci/dm646x.c b/arch/arm/mach-davinci/dm646x.c
index 00f774394b1..9eb87c1d1ed 100644
--- a/arch/arm/mach-davinci/dm646x.c
+++ b/arch/arm/mach-davinci/dm646x.c
@@ -16,7 +16,6 @@
 
 #include <asm/mach/map.h>
 
-#include <mach/dm646x.h>
 #include <mach/cputype.h>
 #include <mach/edma.h>
 #include <mach/irqs.h>
@@ -28,12 +27,11 @@
 #include <mach/asp.h>
 #include <mach/gpio-davinci.h>
 
+#include "davinci.h"
 #include "clock.h"
 #include "mux.h"
 
 #define DAVINCI_VPIF_BASE       (0x01C12000)
-#define VDD3P3V_PWDN_OFFSET     (0x48)
-#define VSCLKDIS_OFFSET         (0x6C)
 
 #define VDD3P3V_VID_MASK        (BIT_MASK(3) | BIT_MASK(2) | BIT_MASK(1) |\
                                         BIT_MASK(0))
@@ -46,6 +44,13 @@
 #define DM646X_REF_FREQ         27000000
 #define DM646X_AUX_FREQ         24000000
 
+#define DM646X_EMAC_BASE                0x01c80000
+#define DM646X_EMAC_MDIO_BASE           (DM646X_EMAC_BASE + 0x4000)
+#define DM646X_EMAC_CNTRL_OFFSET        0x0000
+#define DM646X_EMAC_CNTRL_MOD_OFFSET    0x1000
+#define DM646X_EMAC_CNTRL_RAM_OFFSET    0x2000
+#define DM646X_EMAC_CNTRL_RAM_SIZE      0x2000
+
 static struct pll_data pll1_data = {
         .num       = 1,
         .phys_base = DAVINCI_PLL1_BASE,
@@ -873,15 +878,14 @@ void dm646x_setup_vpif(struct vpif_display_config *display_config,
                        struct vpif_capture_config *capture_config)
 {
         unsigned int value;
-        void __iomem *base = IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE);
 
-        value = __raw_readl(base + VSCLKDIS_OFFSET);
+        value = __raw_readl(DAVINCI_SYSMOD_VIRT(SYSMOD_VSCLKDIS));
         value &= ~VSCLKDIS_MASK;
-        __raw_writel(value, base + VSCLKDIS_OFFSET);
+        __raw_writel(value, DAVINCI_SYSMOD_VIRT(SYSMOD_VSCLKDIS));
 
-        value = __raw_readl(base + VDD3P3V_PWDN_OFFSET);
+        value = __raw_readl(DAVINCI_SYSMOD_VIRT(SYSMOD_VDD3P3VPWDN));
         value &= ~VDD3P3V_VID_MASK;
-        __raw_writel(value, base + VDD3P3V_PWDN_OFFSET);
+        __raw_writel(value, DAVINCI_SYSMOD_VIRT(SYSMOD_VDD3P3VPWDN));
 
         davinci_cfg_reg(DM646X_STSOMUX_DISABLE);
         davinci_cfg_reg(DM646X_STSIMUX_DISABLE);
@@ -905,6 +909,7 @@ int __init dm646x_init_edma(struct edma_rsv_info *rsv)
 void __init dm646x_init(void)
 {
         davinci_common_init(&davinci_soc_info_dm646x);
+        davinci_map_sysmod();
 }
 
 static int __init dm646x_init_devices(void)
diff --git a/arch/arm/mach-davinci/dma.c b/arch/arm/mach-davinci/dma.c
index da90103a313..fd33919c95d 100644
--- a/arch/arm/mach-davinci/dma.c
+++ b/arch/arm/mach-davinci/dma.c
@@ -1508,12 +1508,8 @@ static int __init edma_probe(struct platform_device *pdev)
                         goto fail;
                 }
 
-                /* Everything lives on transfer controller 1 until otherwise
-                 * specified. This way, long transfers on the low priority queue
-                 * started by the codec engine will not cause audio defects.
-                 */
                 for (i = 0; i < edma_cc[j]->num_channels; i++)
-                        map_dmach_queue(j, i, EVENTQ_1);
+                        map_dmach_queue(j, i, info[j]->default_queue);
 
                 queue_tc_mapping = info[j]->queue_tc_mapping;
                 queue_priority_mapping = info[j]->queue_priority_mapping;
diff --git a/arch/arm/mach-davinci/include/mach/dm355.h b/arch/arm/mach-davinci/include/mach/dm355.h
deleted file mode 100644
index 36dff4a0ce3..00000000000
--- a/arch/arm/mach-davinci/include/mach/dm355.h
+++ /dev/null
@@ -1,32 +0,0 @@
-/*
- * Chip specific defines for DM355 SoC
- *
- * Author: Kevin Hilman, Deep Root Systems, LLC
- *
- * 2007 (c) Deep Root Systems, LLC. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-#ifndef __ASM_ARCH_DM355_H
-#define __ASM_ARCH_DM355_H
-
-#include <mach/hardware.h>
-#include <mach/asp.h>
-#include <media/davinci/vpfe_capture.h>
-
-#define DM355_ASYNC_EMIF_CONTROL_BASE   0x01E10000
-#define DM355_ASYNC_EMIF_DATA_CE0_BASE  0x02000000
-
-#define ASP1_TX_EVT_EN  1
-#define ASP1_RX_EVT_EN  2
-
-struct spi_board_info;
-
-void __init dm355_init(void);
-void dm355_init_spi0(unsigned chipselect_mask,
-                struct spi_board_info *info, unsigned len);
-void __init dm355_init_asp1(u32 evt_enable, struct snd_platform_data *pdata);
-void dm355_set_vpfe_config(struct vpfe_config *cfg);
-
-#endif /* __ASM_ARCH_DM355_H */
diff --git a/arch/arm/mach-davinci/include/mach/dm365.h b/arch/arm/mach-davinci/include/mach/dm365.h
index 2563bf4e93a..b9bf3d6a442 100644
--- a/arch/arm/mach-davinci/include/mach/dm365.h
+++ b/arch/arm/mach-davinci/include/mach/dm365.h
@@ -1,52 +1 @@
-/*
- * Copyright (C) 2009 Texas Instruments Incorporated
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-#ifndef __ASM_ARCH_DM365_H
-#define __ASM_ARCH_DM665_H
-
-#include <linux/platform_device.h>
-#include <linux/davinci_emac.h>
-#include <mach/hardware.h>
-#include <mach/asp.h>
-#include <mach/keyscan.h>
-#include <media/davinci/vpfe_capture.h>
-
-#define DM365_EMAC_BASE                 (0x01D07000)
-#define DM365_EMAC_MDIO_BASE            (DM365_EMAC_BASE + 0x4000)
-#define DM365_EMAC_CNTRL_OFFSET         (0x0000)
-#define DM365_EMAC_CNTRL_MOD_OFFSET     (0x3000)
-#define DM365_EMAC_CNTRL_RAM_OFFSET     (0x1000)
-#define DM365_EMAC_CNTRL_RAM_SIZE       (0x2000)
-
-/* Base of key scan register bank */
-#define DM365_KEYSCAN_BASE              (0x01C69400)
-
-#define DM365_RTC_BASE                  (0x01C69000)
-
-#define DAVINCI_DM365_VC_BASE           (0x01D0C000)
-#define DAVINCI_DMA_VC_TX               2
-#define DAVINCI_DMA_VC_RX               3
-
-#define DM365_ASYNC_EMIF_CONTROL_BASE   0x01D10000
-#define DM365_ASYNC_EMIF_DATA_CE0_BASE  0x02000000
-#define DM365_ASYNC_EMIF_DATA_CE1_BASE  0x04000000
-
-void __init dm365_init(void);
-void __init dm365_init_asp(struct snd_platform_data *pdata);
-void __init dm365_init_vc(struct snd_platform_data *pdata);
-void __init dm365_init_ks(struct davinci_ks_platform_data *pdata);
-void __init dm365_init_rtc(void);
-void dm365_init_spi0(unsigned chipselect_mask,
-                        struct spi_board_info *info, unsigned len);
-
-void dm365_set_vpfe_config(struct vpfe_config *cfg);
-#endif /* __ASM_ARCH_DM365_H */
+/* empty, remove once unused */
diff --git a/arch/arm/mach-davinci/include/mach/dm644x.h b/arch/arm/mach-davinci/include/mach/dm644x.h
deleted file mode 100644
index 5a1b26d4e68..00000000000
--- a/arch/arm/mach-davinci/include/mach/dm644x.h
+++ /dev/null
@@ -1,47 +0,0 @@
-/*
- * This file contains the processor specific definitions
- * of the TI DM644x.
- *
- * Copyright (C) 2008 Texas Instruments.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- *
- */
-#ifndef __ASM_ARCH_DM644X_H
-#define __ASM_ARCH_DM644X_H
-
-#include <linux/davinci_emac.h>
-#include <mach/hardware.h>
-#include <mach/asp.h>
-#include <media/davinci/vpfe_capture.h>
-
-#define DM644X_EMAC_BASE                (0x01C80000)
-#define DM644X_EMAC_MDIO_BASE           (DM644X_EMAC_BASE + 0x4000)
-#define DM644X_EMAC_CNTRL_OFFSET        (0x0000)
-#define DM644X_EMAC_CNTRL_MOD_OFFSET    (0x1000)
-#define DM644X_EMAC_CNTRL_RAM_OFFSET    (0x2000)
-#define DM644X_EMAC_CNTRL_RAM_SIZE      (0x2000)
-
-#define DM644X_ASYNC_EMIF_CONTROL_BASE  0x01E00000
-#define DM644X_ASYNC_EMIF_DATA_CE0_BASE 0x02000000
-#define DM644X_ASYNC_EMIF_DATA_CE1_BASE 0x04000000
-#define DM644X_ASYNC_EMIF_DATA_CE2_BASE 0x06000000
-#define DM644X_ASYNC_EMIF_DATA_CE3_BASE 0x08000000
-
-void __init dm644x_init(void);
-void __init dm644x_init_asp(struct snd_platform_data *pdata);
-void dm644x_set_vpfe_config(struct vpfe_config *cfg);
-
-#endif /* __ASM_ARCH_DM644X_H */
diff --git a/arch/arm/mach-davinci/include/mach/dm646x.h b/arch/arm/mach-davinci/include/mach/dm646x.h
index a8ee6c9f0bb..b9bf3d6a442 100644
--- a/arch/arm/mach-davinci/include/mach/dm646x.h
+++ b/arch/arm/mach-davinci/include/mach/dm646x.h
@@ -1,41 +1 @@
-/*
- * Chip specific defines for DM646x SoC
- *
- * Author: Kevin Hilman, Deep Root Systems, LLC
- *
- * 2007 (c) Deep Root Systems, LLC. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-#ifndef __ASM_ARCH_DM646X_H
-#define __ASM_ARCH_DM646X_H
-
-#include <mach/hardware.h>
-#include <mach/asp.h>
-#include <linux/i2c.h>
-#include <linux/videodev2.h>
-#include <linux/davinci_emac.h>
-#include <media/davinci/vpif_types.h>
-
-#define DM646X_EMAC_BASE                (0x01C80000)
-#define DM646X_EMAC_MDIO_BASE           (DM646X_EMAC_BASE + 0x4000)
-#define DM646X_EMAC_CNTRL_OFFSET        (0x0000)
-#define DM646X_EMAC_CNTRL_MOD_OFFSET    (0x1000)
-#define DM646X_EMAC_CNTRL_RAM_OFFSET    (0x2000)
-#define DM646X_EMAC_CNTRL_RAM_SIZE      (0x2000)
-
-#define DM646X_ASYNC_EMIF_CONTROL_BASE  0x20008000
-#define DM646X_ASYNC_EMIF_CS2_SPACE_BASE 0x42000000
-
-void __init dm646x_init(void);
-void __init dm646x_init_mcasp0(struct snd_platform_data *pdata);
-void __init dm646x_init_mcasp1(struct snd_platform_data *pdata);
-int __init dm646x_init_edma(struct edma_rsv_info *rsv);
-
-void dm646x_video_init(void);
-
-void dm646x_setup_vpif(struct vpif_display_config *,
-                       struct vpif_capture_config *);
-
-#endif /* __ASM_ARCH_DM646X_H */
+/* empty, remove once unused */
diff --git a/arch/arm/mach-davinci/include/mach/edma.h b/arch/arm/mach-davinci/include/mach/edma.h
index 20c77f29bf0..7e84c906cef 100644
--- a/arch/arm/mach-davinci/include/mach/edma.h
+++ b/arch/arm/mach-davinci/include/mach/edma.h
@@ -250,6 +250,11 @@ struct edma_soc_info {
         unsigned        n_slot;
         unsigned        n_tc;
         unsigned        n_cc;
+        /*
+         * Default queue is expected to be a low-priority queue.
+         * This way, long transfers on the default queue started
+         * by the codec engine will not cause audio defects.
+         */
         enum dma_event_q        default_queue;
 
         /* Resource reservation for other cores */
diff --git a/arch/arm/mach-davinci/include/mach/entry-macro.S b/arch/arm/mach-davinci/include/mach/entry-macro.S
index e14c0dc0e12..c1661d2feca 100644
--- a/arch/arm/mach-davinci/include/mach/entry-macro.S
+++ b/arch/arm/mach-davinci/include/mach/entry-macro.S
@@ -11,17 +11,11 @@
 #include <mach/io.h>
 #include <mach/irqs.h>
 
-                .macro  disable_fiq
-                .endm
-
                 .macro  get_irqnr_preamble, base, tmp
                 ldr \base, =davinci_intc_base
                 ldr \base, [\base]
                 .endm
 
-                .macro  arch_ret_to_user, tmp1, tmp2
-                .endm
-
                 .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
 #if defined(CONFIG_AINTC) && defined(CONFIG_CP_INTC)
                 ldr \tmp, =davinci_intc_type
diff --git a/arch/arm/mach-davinci/include/mach/hardware.h b/arch/arm/mach-davinci/include/mach/hardware.h
index 414e0b93e74..0209b1fc22a 100644
--- a/arch/arm/mach-davinci/include/mach/hardware.h
+++ b/arch/arm/mach-davinci/include/mach/hardware.h
@@ -19,8 +19,6 @@
  * and the chip/board init code should then explicitly include
  * <chipname>.h
  */
-#define DAVINCI_SYSTEM_MODULE_BASE        0x01C40000
-
 /*
  * I/O mapping
  */
diff --git a/arch/arm/mach-davinci/include/mach/system.h b/arch/arm/mach-davinci/include/mach/system.h
deleted file mode 100644
index fcb7a015aba..00000000000
--- a/arch/arm/mach-davinci/include/mach/system.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/*
- * DaVinci system defines
- *
- * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com>
- *
- * 2007 (c) MontaVista Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-#ifndef __ASM_ARCH_SYSTEM_H
-#define __ASM_ARCH_SYSTEM_H
-
-#include <mach/common.h>
-
-static inline void arch_idle(void)
-{
-        cpu_do_idle();
-}
-
-#endif /* __ASM_ARCH_SYSTEM_H */
diff --git a/arch/arm/mach-dove/include/mach/entry-macro.S b/arch/arm/mach-dove/include/mach/entry-macro.S
index e84c78c2a8b..72d622baaad 100644
--- a/arch/arm/mach-dove/include/mach/entry-macro.S
+++ b/arch/arm/mach-dove/include/mach/entry-macro.S
@@ -10,12 +10,6 @@
 
 #include <mach/bridge-regs.h>
 
-        .macro  disable_fiq
-        .endm
-
-        .macro  arch_ret_to_user, tmp1, tmp2
-        .endm
-
         .macro  get_irqnr_preamble, base, tmp
         ldr     \base, =IRQ_VIRT_BASE
         .endm
diff --git a/arch/arm/mach-dove/include/mach/system.h b/arch/arm/mach-dove/include/mach/system.h
deleted file mode 100644
index 3027954f616..00000000000
--- a/arch/arm/mach-dove/include/mach/system.h
+++ /dev/null
@@ -1,17 +0,0 @@
-/*
- * arch/arm/mach-dove/include/mach/system.h
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#ifndef __ASM_ARCH_SYSTEM_H
-#define __ASM_ARCH_SYSTEM_H
-
-static inline void arch_idle(void)
-{
-        cpu_do_idle();
-}
-
-#endif
diff --git a/arch/arm/mach-dove/pcie.c b/arch/arm/mach-dove/pcie.c
index 52e96d397ba..48a032005ea 100644
--- a/arch/arm/mach-dove/pcie.c
+++ b/arch/arm/mach-dove/pcie.c
@@ -69,7 +69,7 @@ static int __init dove_pcie_setup(int nr, struct pci_sys_data *sys)
         pp->res[0].flags = IORESOURCE_IO;
         if (request_resource(&ioport_resource, &pp->res[0]))
                 panic("Request PCIe IO resource failed\n");
-        pci_add_resource(&sys->resources, &pp->res[0]);
+        pci_add_resource_offset(&sys->resources, &pp->res[0], sys->io_offset);
 
         /*
          * IORESOURCE_MEM
@@ -88,7 +88,7 @@ static int __init dove_pcie_setup(int nr, struct pci_sys_data *sys)
         pp->res[1].flags = IORESOURCE_MEM;
         if (request_resource(&iomem_resource, &pp->res[1]))
                 panic("Request PCIe Memory resource failed\n");
-        pci_add_resource(&sys->resources, &pp->res[1]);
+        pci_add_resource_offset(&sys->resources, &pp->res[1], sys->mem_offset);
 
         return 1;
 }
diff --git a/arch/arm/mach-ebsa110/core.c b/arch/arm/mach-ebsa110/core.c
index 294aad07f7a..804c9122b7b 100644
--- a/arch/arm/mach-ebsa110/core.c
+++ b/arch/arm/mach-ebsa110/core.c
@@ -271,8 +271,33 @@ static struct platform_device *ebsa110_devices[] = {
         &am79c961_device,
 };
 
+/*
+ * EBSA110 idling methodology:
+ *
+ * We can not execute the "wait for interrupt" instruction since that
+ * will stop our MCLK signal (which provides the clock for the glue
+ * logic, and therefore the timer interrupt).
+ *
+ * Instead, we spin, polling the IRQ_STAT register for the occurrence
+ * of any interrupt with core clock down to the memory clock.
+ */
+static void ebsa110_idle(void)
+{
+        const char *irq_stat = (char *)0xff000000;
+
+        /* disable clock switching */
+        asm volatile ("mcr p15, 0, ip, c15, c2, 2" : : : "cc");
+
+        /* wait for an interrupt to occur */
+        while (!*irq_stat);
+
+        /* enable clock switching */
+        asm volatile ("mcr p15, 0, ip, c15, c1, 2" : : : "cc");
+}
+
 static int __init ebsa110_init(void)
 {
+        arm_pm_idle = ebsa110_idle;
         return platform_add_devices(ebsa110_devices, ARRAY_SIZE(ebsa110_devices));
 }
 
diff --git a/arch/arm/mach-ebsa110/include/mach/entry-macro.S b/arch/arm/mach-ebsa110/include/mach/entry-macro.S
index cc3e5992f6b..14b110de78a 100644
--- a/arch/arm/mach-ebsa110/include/mach/entry-macro.S
+++ b/arch/arm/mach-ebsa110/include/mach/entry-macro.S
@@ -12,16 +12,10 @@
 
 #define IRQ_STAT                0xff000000      /* read */
 
-        .macro  disable_fiq
-        .endm
-
         .macro  get_irqnr_preamble, base, tmp
         mov     \base, #IRQ_STAT
         .endm
 
-        .macro  arch_ret_to_user, tmp1, tmp2
-        .endm
-
         .macro  get_irqnr_and_base, irqnr, stat, base, tmp
         ldrb    \stat, [\base]                  @ get interrupts
         mov     \irqnr, #0
diff --git a/arch/arm/mach-ebsa110/include/mach/system.h b/arch/arm/mach-ebsa110/include/mach/system.h
deleted file mode 100644
index 2e4af65edb6..00000000000
--- a/arch/arm/mach-ebsa110/include/mach/system.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/*
- *  arch/arm/mach-ebsa110/include/mach/system.h
- *
- *  Copyright (C) 1996-2000 Russell King.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#ifndef __ASM_ARCH_SYSTEM_H
-#define __ASM_ARCH_SYSTEM_H
-
-/*
- * EBSA110 idling methodology:
- *
- * We can not execute the "wait for interrupt" instruction since that
- * will stop our MCLK signal (which provides the clock for the glue
- * logic, and therefore the timer interrupt).
- *
- * Instead, we spin, polling the IRQ_STAT register for the occurrence
- * of any interrupt with core clock down to the memory clock.
- */
-static inline void arch_idle(void)
-{
-        const char *irq_stat = (char *)0xff000000;
-
-        /* disable clock switching */
-        asm volatile ("mcr p15, 0, ip, c15, c2, 2" : : : "cc");
-
-        /* wait for an interrupt to occur */
-        while (!*irq_stat);
-
-        /* enable clock switching */
-        asm volatile ("mcr p15, 0, ip, c15, c1, 2" : : : "cc");
-}
-
-#endif
diff --git a/arch/arm/mach-ep93xx/Makefile b/arch/arm/mach-ep93xx/Makefile
index 574209d9e24..0dc51f9462d 100644
--- a/arch/arm/mach-ep93xx/Makefile
+++ b/arch/arm/mach-ep93xx/Makefile
@@ -8,6 +8,9 @@ obj-			:=
 
 obj-$(CONFIG_EP93XX_DMA)        += dma.o
 
+obj-$(CONFIG_CRUNCH)            += crunch.o crunch-bits.o
+AFLAGS_crunch-bits.o            := -Wa,-mcpu=ep9312
+
 obj-$(CONFIG_MACH_ADSSPHERE)    += adssphere.o
 obj-$(CONFIG_MACH_EDB93XX)      += edb93xx.o
 obj-$(CONFIG_MACH_GESBC9312)    += gesbc9312.o
diff --git a/arch/arm/mach-ep93xx/adssphere.c b/arch/arm/mach-ep93xx/adssphere.c
index 681e939407d..2d45947a303 100644
--- a/arch/arm/mach-ep93xx/adssphere.c
+++ b/arch/arm/mach-ep93xx/adssphere.c
@@ -20,6 +20,7 @@
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 
+#include "soc.h"
 
 static struct ep93xx_eth_data __initdata adssphere_eth_data = {
         .phy_id         = 1,
diff --git a/arch/arm/mach-ep93xx/clock.c b/arch/arm/mach-ep93xx/clock.c
index ca4de710509..c95dbce2468 100644
--- a/arch/arm/mach-ep93xx/clock.c
+++ b/arch/arm/mach-ep93xx/clock.c
@@ -25,6 +25,7 @@
 
 #include <asm/div64.h>
 
+#include "soc.h"
 
 struct clk {
         struct clk      *parent;
diff --git a/arch/arm/mach-ep93xx/core.c b/arch/arm/mach-ep93xx/core.c
index 24203f9a679..8d258958871 100644
--- a/arch/arm/mach-ep93xx/core.c
+++ b/arch/arm/mach-ep93xx/core.c
@@ -46,6 +46,7 @@
 
 #include <asm/hardware/vic.h>
 
+#include "soc.h"
 
 /*************************************************************************
  * Static I/O mappings that are needed for all EP93xx platforms
@@ -204,7 +205,6 @@ void ep93xx_syscon_swlocked_write(unsigned int val, void __iomem *reg)
 
         spin_unlock_irqrestore(&syscon_swlock, flags);
 }
-EXPORT_SYMBOL(ep93xx_syscon_swlocked_write);
 
 void ep93xx_devcfg_set_clear(unsigned int set_bits, unsigned int clear_bits)
 {
@@ -221,7 +221,6 @@ void ep93xx_devcfg_set_clear(unsigned int set_bits, unsigned int clear_bits)
 
         spin_unlock_irqrestore(&syscon_swlock, flags);
 }
-EXPORT_SYMBOL(ep93xx_devcfg_set_clear);
 
 /**
  * ep93xx_chip_revision() - returns the EP93xx chip revision
@@ -279,48 +278,14 @@ static struct amba_pl010_data ep93xx_uart_data = {
         .set_mctrl      = ep93xx_uart_set_mctrl,
 };
 
-static struct amba_device uart1_device = {
-        .dev            = {
-                .init_name      = "apb:uart1",
-                .platform_data  = &ep93xx_uart_data,
-        },
-        .res            = {
-                .start  = EP93XX_UART1_PHYS_BASE,
-                .end    = EP93XX_UART1_PHYS_BASE + 0x0fff,
-                .flags  = IORESOURCE_MEM,
-        },
-        .irq            = { IRQ_EP93XX_UART1, NO_IRQ },
-        .periphid       = 0x00041010,
-};
-
-static struct amba_device uart2_device = {
-        .dev            = {
-                .init_name      = "apb:uart2",
-                .platform_data  = &ep93xx_uart_data,
-        },
-        .res            = {
-                .start  = EP93XX_UART2_PHYS_BASE,
-                .end    = EP93XX_UART2_PHYS_BASE + 0x0fff,
-                .flags  = IORESOURCE_MEM,
-        },
-        .irq            = { IRQ_EP93XX_UART2, NO_IRQ },
-        .periphid       = 0x00041010,
-};
+static AMBA_APB_DEVICE(uart1, "apb:uart1", 0x00041010, EP93XX_UART1_PHYS_BASE,
+        { IRQ_EP93XX_UART1 }, &ep93xx_uart_data);
 
-static struct amba_device uart3_device = {
-        .dev            = {
-                .init_name      = "apb:uart3",
-                .platform_data  = &ep93xx_uart_data,
-        },
-        .res            = {
-                .start  = EP93XX_UART3_PHYS_BASE,
-                .end    = EP93XX_UART3_PHYS_BASE + 0x0fff,
-                .flags  = IORESOURCE_MEM,
-        },
-        .irq            = { IRQ_EP93XX_UART3, NO_IRQ },
-        .periphid       = 0x00041010,
-};
+static AMBA_APB_DEVICE(uart2, "apb:uart2", 0x00041010, EP93XX_UART2_PHYS_BASE,
+        { IRQ_EP93XX_UART2 }, &ep93xx_uart_data);
 
+static AMBA_APB_DEVICE(uart3, "apb:uart3", 0x00041010, EP93XX_UART3_PHYS_BASE,
+        { IRQ_EP93XX_UART3 }, &ep93xx_uart_data);
 
 static struct resource ep93xx_rtc_resource[] = {
         {
@@ -682,9 +647,19 @@ static struct platform_device ep93xx_fb_device = {
         .resource               = ep93xx_fb_resource,
 };
 
+/* The backlight use a single register in the framebuffer's register space */
+#define EP93XX_RASTER_REG_BRIGHTNESS 0x20
+
+static struct resource ep93xx_bl_resources[] = {
+        DEFINE_RES_MEM(EP93XX_RASTER_PHYS_BASE +
+                       EP93XX_RASTER_REG_BRIGHTNESS, 0x04),
+};
+
 static struct platform_device ep93xx_bl_device = {
         .name           = "ep93xx-bl",
         .id             = -1,
+        .num_resources  = ARRAY_SIZE(ep93xx_bl_resources),
+        .resource       = ep93xx_bl_resources,
 };
 
 /**
@@ -817,23 +792,12 @@ void __init ep93xx_register_i2s(void)
 #define EP93XX_I2SCLKDIV_MASK           (EP93XX_SYSCON_I2SCLKDIV_ORIDE | \
                                          EP93XX_SYSCON_I2SCLKDIV_SPOL)
 
-int ep93xx_i2s_acquire(unsigned i2s_pins, unsigned i2s_config)
+int ep93xx_i2s_acquire(void)
 {
         unsigned val;
 
-        /* Sanity check */
-        if (i2s_pins & ~EP93XX_SYSCON_DEVCFG_I2S_MASK)
-                return -EINVAL;
-        if (i2s_config & ~EP93XX_I2SCLKDIV_MASK)
-                return -EINVAL;
-
-        /* Must have only one of I2SONSSP/I2SONAC97 set */
-        if ((i2s_pins & EP93XX_SYSCON_DEVCFG_I2SONSSP) ==
-            (i2s_pins & EP93XX_SYSCON_DEVCFG_I2SONAC97))
-                return -EINVAL;
-
-        ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_I2S_MASK);
-        ep93xx_devcfg_set_bits(i2s_pins);
+        ep93xx_devcfg_set_clear(EP93XX_SYSCON_DEVCFG_I2SONAC97,
+                        EP93XX_SYSCON_DEVCFG_I2S_MASK);
 
         /*
          * This is potentially racy with the clock api for i2s_mclk, sclk and 
@@ -843,7 +807,7 @@ int ep93xx_i2s_acquire(unsigned i2s_pins, unsigned i2s_config)
          */
         val = __raw_readl(EP93XX_SYSCON_I2SCLKDIV);
         val &= ~EP93XX_I2SCLKDIV_MASK;
-        val |= i2s_config;
+        val |= EP93XX_SYSCON_I2SCLKDIV_ORIDE | EP93XX_SYSCON_I2SCLKDIV_SPOL;
         ep93xx_syscon_swlocked_write(val, EP93XX_SYSCON_I2SCLKDIV);
 
         return 0;
@@ -890,11 +854,32 @@ void __init ep93xx_register_ac97(void)
         platform_device_register(&ep93xx_pcm_device);
 }
 
+/*************************************************************************
+ * EP93xx Watchdog
+ *************************************************************************/
+static struct resource ep93xx_wdt_resources[] = {
+        DEFINE_RES_MEM(EP93XX_WATCHDOG_PHYS_BASE, 0x08),
+};
+
+static struct platform_device ep93xx_wdt_device = {
+        .name           = "ep93xx-wdt",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(ep93xx_wdt_resources),
+        .resource       = ep93xx_wdt_resources,
+};
+
 void __init ep93xx_init_devices(void)
 {
         /* Disallow access to MaverickCrunch initially */
         ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_CPENA);
 
+        /* Default all ports to GPIO */
+        ep93xx_devcfg_set_bits(EP93XX_SYSCON_DEVCFG_KEYS |
+                               EP93XX_SYSCON_DEVCFG_GONK |
+                               EP93XX_SYSCON_DEVCFG_EONIDE |
+                               EP93XX_SYSCON_DEVCFG_GONIDE |
+                               EP93XX_SYSCON_DEVCFG_HONIDE);
+
         /* Get the GPIO working early, other devices need it */
         platform_device_register(&ep93xx_gpio_device);
 
@@ -905,6 +890,7 @@ void __init ep93xx_init_devices(void)
         platform_device_register(&ep93xx_rtc_device);
         platform_device_register(&ep93xx_ohci_device);
         platform_device_register(&ep93xx_leds);
+        platform_device_register(&ep93xx_wdt_device);
 }
 
 void ep93xx_restart(char mode, const char *cmd)
diff --git a/arch/arm/kernel/crunch-bits.S b/arch/arm/mach-ep93xx/crunch-bits.S
index 0ec9bb48fab..0ec9bb48fab 100644
--- a/arch/arm/kernel/crunch-bits.S
+++ b/arch/arm/mach-ep93xx/crunch-bits.S
diff --git a/arch/arm/kernel/crunch.c b/arch/arm/mach-ep93xx/crunch.c
index 25ef223ba7f..74753e2df60 100644
--- a/arch/arm/kernel/crunch.c
+++ b/arch/arm/mach-ep93xx/crunch.c
@@ -16,9 +16,11 @@
 #include <linux/sched.h>
 #include <linux/init.h>
 #include <linux/io.h>
-#include <mach/ep93xx-regs.h>
+
 #include <asm/thread_notify.h>
 
+#include "soc.h"
+
 struct crunch_state *crunch_owner;
 
 void crunch_task_release(struct thread_info *thread)
diff --git a/arch/arm/mach-ep93xx/dma.c b/arch/arm/mach-ep93xx/dma.c
index 5a257088125..16976d7bdc8 100644
--- a/arch/arm/mach-ep93xx/dma.c
+++ b/arch/arm/mach-ep93xx/dma.c
@@ -28,6 +28,8 @@
 #include <mach/dma.h>
 #include <mach/hardware.h>
 
+#include "soc.h"
+
 #define DMA_CHANNEL(_name, _base, _irq) \
         { .name = (_name), .base = (_base), .irq = (_irq) }
 
diff --git a/arch/arm/mach-ep93xx/edb93xx.c b/arch/arm/mach-ep93xx/edb93xx.c
index d115653edca..da9047d726f 100644
--- a/arch/arm/mach-ep93xx/edb93xx.c
+++ b/arch/arm/mach-ep93xx/edb93xx.c
@@ -43,6 +43,7 @@
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 
+#include "soc.h"
 
 static void __init edb93xx_register_flash(void)
 {
diff --git a/arch/arm/mach-ep93xx/gesbc9312.c b/arch/arm/mach-ep93xx/gesbc9312.c
index af46970dc58..fcdffbe49dc 100644
--- a/arch/arm/mach-ep93xx/gesbc9312.c
+++ b/arch/arm/mach-ep93xx/gesbc9312.c
@@ -20,6 +20,7 @@
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 
+#include "soc.h"
 
 static struct ep93xx_eth_data __initdata gesbc9312_eth_data = {
         .phy_id         = 1,
diff --git a/arch/arm/mach-ep93xx/include/mach/entry-macro.S b/arch/arm/mach-ep93xx/include/mach/entry-macro.S
deleted file mode 100644
index 9be6edcf904..00000000000
--- a/arch/arm/mach-ep93xx/include/mach/entry-macro.S
+++ /dev/null
@@ -1,17 +0,0 @@
-/*
- * arch/arm/mach-ep93xx/include/mach/entry-macro.S
- * IRQ demultiplexing for EP93xx
- *
- * Copyright (C) 2006 Lennert Buytenhek <buytenh@wantstofly.org>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or (at
- * your option) any later version.
- */
-
-                .macro  disable_fiq
-                .endm
-
-                .macro  arch_ret_to_user, tmp1, tmp2
-                .endm
diff --git a/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h b/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h
index c4a7b84ef06..c64d7424660 100644
--- a/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h
+++ b/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h
@@ -6,40 +6,6 @@
 #define __ASM_ARCH_EP93XX_REGS_H
 
 /*
- * EP93xx Physical Memory Map:
- *
- * The ASDO pin is sampled at system reset to select a synchronous or
- * asynchronous boot configuration.  When ASDO is "1" (i.e. pulled-up)
- * the synchronous boot mode is selected.  When ASDO is "0" (i.e
- * pulled-down) the asynchronous boot mode is selected.
- *
- * In synchronous boot mode nSDCE3 is decoded starting at physical address
- * 0x00000000 and nCS0 is decoded starting at 0xf0000000.  For asynchronous
- * boot mode they are swapped with nCS0 decoded at 0x00000000 ann nSDCE3
- * decoded at 0xf0000000.
- *
- * There is known errata for the EP93xx dealing with External Memory
- * Configurations.  Please refer to "AN273: EP93xx Silicon Rev E Design
- * Guidelines" for more information.  This document can be found at:
- *
- *      http://www.cirrus.com/en/pubs/appNote/AN273REV4.pdf
- */
-
-#define EP93XX_CS0_PHYS_BASE_ASYNC      0x00000000      /* ASDO Pin = 0 */
-#define EP93XX_SDCE3_PHYS_BASE_SYNC     0x00000000      /* ASDO Pin = 1 */
-#define EP93XX_CS1_PHYS_BASE            0x10000000
-#define EP93XX_CS2_PHYS_BASE            0x20000000
-#define EP93XX_CS3_PHYS_BASE            0x30000000
-#define EP93XX_PCMCIA_PHYS_BASE         0x40000000
-#define EP93XX_CS6_PHYS_BASE            0x60000000
-#define EP93XX_CS7_PHYS_BASE            0x70000000
-#define EP93XX_SDCE0_PHYS_BASE          0xc0000000
-#define EP93XX_SDCE1_PHYS_BASE          0xd0000000
-#define EP93XX_SDCE2_PHYS_BASE          0xe0000000
-#define EP93XX_SDCE3_PHYS_BASE_ASYNC    0xf0000000      /* ASDO Pin = 0 */
-#define EP93XX_CS0_PHYS_BASE_SYNC       0xf0000000      /* ASDO Pin = 1 */
-
-/*
  * EP93xx linux memory map:
  *
  * virt         phys            size
@@ -62,58 +28,7 @@
 #define EP93XX_APB_PHYS(x)              (EP93XX_APB_PHYS_BASE + (x))
 #define EP93XX_APB_IOMEM(x)             IOMEM(EP93XX_APB_VIRT_BASE + (x))
 
-
-/* AHB peripherals */
-#define EP93XX_DMA_BASE                 EP93XX_AHB_IOMEM(0x00000000)
-
-#define EP93XX_ETHERNET_PHYS_BASE       EP93XX_AHB_PHYS(0x00010000)
-#define EP93XX_ETHERNET_BASE            EP93XX_AHB_IOMEM(0x00010000)
-
-#define EP93XX_USB_PHYS_BASE            EP93XX_AHB_PHYS(0x00020000)
-#define EP93XX_USB_BASE                 EP93XX_AHB_IOMEM(0x00020000)
-
-#define EP93XX_RASTER_PHYS_BASE         EP93XX_AHB_PHYS(0x00030000)
-#define EP93XX_RASTER_BASE              EP93XX_AHB_IOMEM(0x00030000)
-
-#define EP93XX_GRAPHICS_ACCEL_BASE      EP93XX_AHB_IOMEM(0x00040000)
-
-#define EP93XX_SDRAM_CONTROLLER_BASE    EP93XX_AHB_IOMEM(0x00060000)
-
-#define EP93XX_PCMCIA_CONTROLLER_BASE   EP93XX_AHB_IOMEM(0x00080000)
-
-#define EP93XX_BOOT_ROM_BASE            EP93XX_AHB_IOMEM(0x00090000)
-
-#define EP93XX_IDE_BASE                 EP93XX_AHB_IOMEM(0x000a0000)
-
-#define EP93XX_VIC1_BASE                EP93XX_AHB_IOMEM(0x000b0000)
-
-#define EP93XX_VIC2_BASE                EP93XX_AHB_IOMEM(0x000c0000)
-
-
-/* APB peripherals */
-#define EP93XX_TIMER_BASE               EP93XX_APB_IOMEM(0x00010000)
-
-#define EP93XX_I2S_PHYS_BASE            EP93XX_APB_PHYS(0x00020000)
-#define EP93XX_I2S_BASE                 EP93XX_APB_IOMEM(0x00020000)
-
-#define EP93XX_SECURITY_BASE            EP93XX_APB_IOMEM(0x00030000)
-
-#define EP93XX_GPIO_PHYS_BASE           EP93XX_APB_PHYS(0x00040000)
-#define EP93XX_GPIO_BASE                EP93XX_APB_IOMEM(0x00040000)
-#define EP93XX_GPIO_REG(x)              (EP93XX_GPIO_BASE + (x))
-#define EP93XX_GPIO_F_INT_STATUS        EP93XX_GPIO_REG(0x5c)
-#define EP93XX_GPIO_A_INT_STATUS        EP93XX_GPIO_REG(0xa0)
-#define EP93XX_GPIO_B_INT_STATUS        EP93XX_GPIO_REG(0xbc)
-#define EP93XX_GPIO_EEDRIVE             EP93XX_GPIO_REG(0xc8)
-
-#define EP93XX_AAC_PHYS_BASE            EP93XX_APB_PHYS(0x00080000)
-#define EP93XX_AAC_BASE                 EP93XX_APB_IOMEM(0x00080000)
-
-#define EP93XX_SPI_PHYS_BASE            EP93XX_APB_PHYS(0x000a0000)
-#define EP93XX_SPI_BASE                 EP93XX_APB_IOMEM(0x000a0000)
-
-#define EP93XX_IRDA_BASE                EP93XX_APB_IOMEM(0x000b0000)
-
+/* APB UARTs */
 #define EP93XX_UART1_PHYS_BASE          EP93XX_APB_PHYS(0x000c0000)
 #define EP93XX_UART1_BASE               EP93XX_APB_IOMEM(0x000c0000)
 
@@ -123,108 +38,4 @@
 #define EP93XX_UART3_PHYS_BASE          EP93XX_APB_PHYS(0x000e0000)
 #define EP93XX_UART3_BASE               EP93XX_APB_IOMEM(0x000e0000)
 
-#define EP93XX_KEY_MATRIX_PHYS_BASE     EP93XX_APB_PHYS(0x000f0000)
-#define EP93XX_KEY_MATRIX_BASE          EP93XX_APB_IOMEM(0x000f0000)
-
-#define EP93XX_ADC_BASE                 EP93XX_APB_IOMEM(0x00100000)
-#define EP93XX_TOUCHSCREEN_BASE         EP93XX_APB_IOMEM(0x00100000)
-
-#define EP93XX_PWM_PHYS_BASE            EP93XX_APB_PHYS(0x00110000)
-#define EP93XX_PWM_BASE                 EP93XX_APB_IOMEM(0x00110000)
-
-#define EP93XX_RTC_PHYS_BASE            EP93XX_APB_PHYS(0x00120000)
-#define EP93XX_RTC_BASE                 EP93XX_APB_IOMEM(0x00120000)
-
-#define EP93XX_SYSCON_BASE              EP93XX_APB_IOMEM(0x00130000)
-#define EP93XX_SYSCON_REG(x)            (EP93XX_SYSCON_BASE + (x))
-#define EP93XX_SYSCON_POWER_STATE       EP93XX_SYSCON_REG(0x00)
-#define EP93XX_SYSCON_PWRCNT            EP93XX_SYSCON_REG(0x04)
-#define EP93XX_SYSCON_PWRCNT_FIR_EN     (1<<31)
-#define EP93XX_SYSCON_PWRCNT_UARTBAUD   (1<<29)
-#define EP93XX_SYSCON_PWRCNT_USH_EN     (1<<28)
-#define EP93XX_SYSCON_PWRCNT_DMA_M2M1   (1<<27)
-#define EP93XX_SYSCON_PWRCNT_DMA_M2M0   (1<<26)
-#define EP93XX_SYSCON_PWRCNT_DMA_M2P8   (1<<25)
-#define EP93XX_SYSCON_PWRCNT_DMA_M2P9   (1<<24)
-#define EP93XX_SYSCON_PWRCNT_DMA_M2P6   (1<<23)
-#define EP93XX_SYSCON_PWRCNT_DMA_M2P7   (1<<22)
-#define EP93XX_SYSCON_PWRCNT_DMA_M2P4   (1<<21)
-#define EP93XX_SYSCON_PWRCNT_DMA_M2P5   (1<<20)
-#define EP93XX_SYSCON_PWRCNT_DMA_M2P2   (1<<19)
-#define EP93XX_SYSCON_PWRCNT_DMA_M2P3   (1<<18)
-#define EP93XX_SYSCON_PWRCNT_DMA_M2P0   (1<<17)
-#define EP93XX_SYSCON_PWRCNT_DMA_M2P1   (1<<16)
-#define EP93XX_SYSCON_HALT              EP93XX_SYSCON_REG(0x08)
-#define EP93XX_SYSCON_STANDBY           EP93XX_SYSCON_REG(0x0c)
-#define EP93XX_SYSCON_CLKSET1           EP93XX_SYSCON_REG(0x20)
-#define EP93XX_SYSCON_CLKSET1_NBYP1     (1<<23)
-#define EP93XX_SYSCON_CLKSET2           EP93XX_SYSCON_REG(0x24)
-#define EP93XX_SYSCON_CLKSET2_NBYP2     (1<<19)
-#define EP93XX_SYSCON_CLKSET2_PLL2_EN   (1<<18)
-#define EP93XX_SYSCON_DEVCFG            EP93XX_SYSCON_REG(0x80)
-#define EP93XX_SYSCON_DEVCFG_SWRST      (1<<31)
-#define EP93XX_SYSCON_DEVCFG_D1ONG      (1<<30)
-#define EP93XX_SYSCON_DEVCFG_D0ONG      (1<<29)
-#define EP93XX_SYSCON_DEVCFG_IONU2      (1<<28)
-#define EP93XX_SYSCON_DEVCFG_GONK       (1<<27)
-#define EP93XX_SYSCON_DEVCFG_TONG       (1<<26)
-#define EP93XX_SYSCON_DEVCFG_MONG       (1<<25)
-#define EP93XX_SYSCON_DEVCFG_U3EN       (1<<24)
-#define EP93XX_SYSCON_DEVCFG_CPENA      (1<<23)
-#define EP93XX_SYSCON_DEVCFG_A2ONG      (1<<22)
-#define EP93XX_SYSCON_DEVCFG_A1ONG      (1<<21)
-#define EP93XX_SYSCON_DEVCFG_U2EN       (1<<20)
-#define EP93XX_SYSCON_DEVCFG_EXVC       (1<<19)
-#define EP93XX_SYSCON_DEVCFG_U1EN       (1<<18)
-#define EP93XX_SYSCON_DEVCFG_TIN        (1<<17)
-#define EP93XX_SYSCON_DEVCFG_HC3IN      (1<<15)
-#define EP93XX_SYSCON_DEVCFG_HC3EN      (1<<14)
-#define EP93XX_SYSCON_DEVCFG_HC1IN      (1<<13)
-#define EP93XX_SYSCON_DEVCFG_HC1EN      (1<<12)
-#define EP93XX_SYSCON_DEVCFG_HONIDE     (1<<11)
-#define EP93XX_SYSCON_DEVCFG_GONIDE     (1<<10)
-#define EP93XX_SYSCON_DEVCFG_PONG       (1<<9)
-#define EP93XX_SYSCON_DEVCFG_EONIDE     (1<<8)
-#define EP93XX_SYSCON_DEVCFG_I2SONSSP   (1<<7)
-#define EP93XX_SYSCON_DEVCFG_I2SONAC97  (1<<6)
-#define EP93XX_SYSCON_DEVCFG_RASONP3    (1<<4)
-#define EP93XX_SYSCON_DEVCFG_RAS        (1<<3)
-#define EP93XX_SYSCON_DEVCFG_ADCPD      (1<<2)
-#define EP93XX_SYSCON_DEVCFG_KEYS       (1<<1)
-#define EP93XX_SYSCON_DEVCFG_SHENA      (1<<0)
-#define EP93XX_SYSCON_VIDCLKDIV         EP93XX_SYSCON_REG(0x84)
-#define EP93XX_SYSCON_CLKDIV_ENABLE     (1<<15)
-#define EP93XX_SYSCON_CLKDIV_ESEL       (1<<14)
-#define EP93XX_SYSCON_CLKDIV_PSEL       (1<<13)
-#define EP93XX_SYSCON_CLKDIV_PDIV_SHIFT 8
-#define EP93XX_SYSCON_I2SCLKDIV         EP93XX_SYSCON_REG(0x8c)
-#define EP93XX_SYSCON_I2SCLKDIV_SENA    (1<<31)
-#define EP93XX_SYSCON_I2SCLKDIV_ORIDE   (1<<29)
-#define EP93XX_SYSCON_I2SCLKDIV_SPOL    (1<<19)
-#define EP93XX_I2SCLKDIV_SDIV           (1 << 16)
-#define EP93XX_I2SCLKDIV_LRDIV32        (0 << 17)
-#define EP93XX_I2SCLKDIV_LRDIV64        (1 << 17)
-#define EP93XX_I2SCLKDIV_LRDIV128       (2 << 17)
-#define EP93XX_I2SCLKDIV_LRDIV_MASK     (3 << 17)
-#define EP93XX_SYSCON_KEYTCHCLKDIV      EP93XX_SYSCON_REG(0x90)
-#define EP93XX_SYSCON_KEYTCHCLKDIV_TSEN (1<<31)
-#define EP93XX_SYSCON_KEYTCHCLKDIV_ADIV (1<<16)
-#define EP93XX_SYSCON_KEYTCHCLKDIV_KEN  (1<<15)
-#define EP93XX_SYSCON_KEYTCHCLKDIV_KDIV (1<<0)
-#define EP93XX_SYSCON_SYSCFG            EP93XX_SYSCON_REG(0x9c)
-#define EP93XX_SYSCON_SYSCFG_REV_MASK   (0xf0000000)
-#define EP93XX_SYSCON_SYSCFG_REV_SHIFT  (28)
-#define EP93XX_SYSCON_SYSCFG_SBOOT      (1<<8)
-#define EP93XX_SYSCON_SYSCFG_LCSN7      (1<<7)
-#define EP93XX_SYSCON_SYSCFG_LCSN6      (1<<6)
-#define EP93XX_SYSCON_SYSCFG_LASDO      (1<<5)
-#define EP93XX_SYSCON_SYSCFG_LEEDA      (1<<4)
-#define EP93XX_SYSCON_SYSCFG_LEECLK     (1<<3)
-#define EP93XX_SYSCON_SYSCFG_LCSN2      (1<<1)
-#define EP93XX_SYSCON_SYSCFG_LCSN1      (1<<0)
-#define EP93XX_SYSCON_SWLOCK            EP93XX_SYSCON_REG(0xc0)
-
-#define EP93XX_WATCHDOG_BASE            EP93XX_APB_IOMEM(0x00140000)
-
-
 #endif
diff --git a/arch/arm/mach-ep93xx/include/mach/gpio-ep93xx.h b/arch/arm/mach-ep93xx/include/mach/gpio-ep93xx.h
index 8aff2ea3587..6d7c571a519 100644
--- a/arch/arm/mach-ep93xx/include/mach/gpio-ep93xx.h
+++ b/arch/arm/mach-ep93xx/include/mach/gpio-ep93xx.h
@@ -3,6 +3,16 @@
 #ifndef __GPIO_EP93XX_H
 #define __GPIO_EP93XX_H
 
+#include <mach/ep93xx-regs.h>
+
+#define EP93XX_GPIO_PHYS_BASE           EP93XX_APB_PHYS(0x00040000)
+#define EP93XX_GPIO_BASE                EP93XX_APB_IOMEM(0x00040000)
+#define EP93XX_GPIO_REG(x)              (EP93XX_GPIO_BASE + (x))
+#define EP93XX_GPIO_F_INT_STATUS        EP93XX_GPIO_REG(0x5c)
+#define EP93XX_GPIO_A_INT_STATUS        EP93XX_GPIO_REG(0xa0)
+#define EP93XX_GPIO_B_INT_STATUS        EP93XX_GPIO_REG(0xbc)
+#define EP93XX_GPIO_EEDRIVE             EP93XX_GPIO_REG(0xc8)
+
 /* GPIO port A.  */
 #define EP93XX_GPIO_LINE_A(x)           ((x) + 0)
 #define EP93XX_GPIO_LINE_EGPIO0         EP93XX_GPIO_LINE_A(0)
diff --git a/arch/arm/mach-ep93xx/include/mach/hardware.h b/arch/arm/mach-ep93xx/include/mach/hardware.h
index 4df842897ea..efcd47815a9 100644
--- a/arch/arm/mach-ep93xx/include/mach/hardware.h
+++ b/arch/arm/mach-ep93xx/include/mach/hardware.h
@@ -5,7 +5,6 @@
 #ifndef __ASM_ARCH_HARDWARE_H
 #define __ASM_ARCH_HARDWARE_H
 
-#include <mach/ep93xx-regs.h>
 #include <mach/platform.h>
 
 /*
diff --git a/arch/arm/mach-ep93xx/include/mach/platform.h b/arch/arm/mach-ep93xx/include/mach/platform.h
index d4c934931f9..602bd87fd0a 100644
--- a/arch/arm/mach-ep93xx/include/mach/platform.h
+++ b/arch/arm/mach-ep93xx/include/mach/platform.h
@@ -21,20 +21,6 @@ struct ep93xx_eth_data
 void ep93xx_map_io(void);
 void ep93xx_init_irq(void);
 
-/* EP93xx System Controller software locked register write */
-void ep93xx_syscon_swlocked_write(unsigned int val, void __iomem *reg);
-void ep93xx_devcfg_set_clear(unsigned int set_bits, unsigned int clear_bits);
-
-static inline void ep93xx_devcfg_set_bits(unsigned int bits)
-{
-        ep93xx_devcfg_set_clear(bits, 0x00);
-}
-
-static inline void ep93xx_devcfg_clear_bits(unsigned int bits)
-{
-        ep93xx_devcfg_set_clear(0x00, bits);
-}
-
 #define EP93XX_CHIP_REV_D0      3
 #define EP93XX_CHIP_REV_D1      4
 #define EP93XX_CHIP_REV_E0      5
@@ -59,7 +45,7 @@ void ep93xx_register_keypad(struct ep93xx_keypad_platform_data *data);
 int ep93xx_keypad_acquire_gpio(struct platform_device *pdev);
 void ep93xx_keypad_release_gpio(struct platform_device *pdev);
 void ep93xx_register_i2s(void);
-int ep93xx_i2s_acquire(unsigned i2s_pins, unsigned i2s_config);
+int ep93xx_i2s_acquire(void);
 void ep93xx_i2s_release(void);
 void ep93xx_register_ac97(void);
 
diff --git a/arch/arm/mach-ep93xx/include/mach/system.h b/arch/arm/mach-ep93xx/include/mach/system.h
deleted file mode 100644
index b5bec7cb9b5..00000000000
--- a/arch/arm/mach-ep93xx/include/mach/system.h
+++ /dev/null
@@ -1,7 +0,0 @@
-/*
- * arch/arm/mach-ep93xx/include/mach/system.h
- */
-static inline void arch_idle(void)
-{
-        cpu_do_idle();
-}
diff --git a/arch/arm/mach-ep93xx/micro9.c b/arch/arm/mach-ep93xx/micro9.c
index 7b98084f0c9..dc431c5f04c 100644
--- a/arch/arm/mach-ep93xx/micro9.c
+++ b/arch/arm/mach-ep93xx/micro9.c
@@ -22,6 +22,7 @@
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 
+#include "soc.h"
 
 /*************************************************************************
  * Micro9 NOR Flash
diff --git a/arch/arm/mach-ep93xx/simone.c b/arch/arm/mach-ep93xx/simone.c
index f4e553eca21..f40c2987e54 100644
--- a/arch/arm/mach-ep93xx/simone.c
+++ b/arch/arm/mach-ep93xx/simone.c
@@ -29,6 +29,8 @@
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 
+#include "soc.h"
+
 static struct ep93xx_eth_data __initdata simone_eth_data = {
         .phy_id         = 1,
 };
diff --git a/arch/arm/mach-ep93xx/snappercl15.c b/arch/arm/mach-ep93xx/snappercl15.c
index fd846331ddf..0c00852ef16 100644
--- a/arch/arm/mach-ep93xx/snappercl15.c
+++ b/arch/arm/mach-ep93xx/snappercl15.c
@@ -35,6 +35,8 @@
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 
+#include "soc.h"
+
 #define SNAPPERCL15_NAND_BASE   (EP93XX_CS7_PHYS_BASE + SZ_16M)
 
 #define SNAPPERCL15_NAND_WPN    (1 << 8)  /* Write protect (active low) */
diff --git a/arch/arm/mach-ep93xx/soc.h b/arch/arm/mach-ep93xx/soc.h
new file mode 100644
index 00000000000..979fba72292
--- /dev/null
+++ b/arch/arm/mach-ep93xx/soc.h
@@ -0,0 +1,213 @@
+/*
+ * arch/arm/mach-ep93xx/soc.h
+ *
+ * Copyright (C) 2012 Open Kernel Labs <www.ok-labs.com>
+ * Copyright (C) 2012 Ryan Mallon <rmallon@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or (at
+ * your option) any later version.
+ */
+
+#ifndef _EP93XX_SOC_H
+#define _EP93XX_SOC_H
+
+#include <mach/ep93xx-regs.h>
+
+/*
+ * EP93xx Physical Memory Map:
+ *
+ * The ASDO pin is sampled at system reset to select a synchronous or
+ * asynchronous boot configuration.  When ASDO is "1" (i.e. pulled-up)
+ * the synchronous boot mode is selected.  When ASDO is "0" (i.e
+ * pulled-down) the asynchronous boot mode is selected.
+ *
+ * In synchronous boot mode nSDCE3 is decoded starting at physical address
+ * 0x00000000 and nCS0 is decoded starting at 0xf0000000.  For asynchronous
+ * boot mode they are swapped with nCS0 decoded at 0x00000000 ann nSDCE3
+ * decoded at 0xf0000000.
+ *
+ * There is known errata for the EP93xx dealing with External Memory
+ * Configurations.  Please refer to "AN273: EP93xx Silicon Rev E Design
+ * Guidelines" for more information.  This document can be found at:
+ *
+ *      http://www.cirrus.com/en/pubs/appNote/AN273REV4.pdf
+ */
+
+#define EP93XX_CS0_PHYS_BASE_ASYNC      0x00000000      /* ASDO Pin = 0 */
+#define EP93XX_SDCE3_PHYS_BASE_SYNC     0x00000000      /* ASDO Pin = 1 */
+#define EP93XX_CS1_PHYS_BASE            0x10000000
+#define EP93XX_CS2_PHYS_BASE            0x20000000
+#define EP93XX_CS3_PHYS_BASE            0x30000000
+#define EP93XX_PCMCIA_PHYS_BASE         0x40000000
+#define EP93XX_CS6_PHYS_BASE            0x60000000
+#define EP93XX_CS7_PHYS_BASE            0x70000000
+#define EP93XX_SDCE0_PHYS_BASE          0xc0000000
+#define EP93XX_SDCE1_PHYS_BASE          0xd0000000
+#define EP93XX_SDCE2_PHYS_BASE          0xe0000000
+#define EP93XX_SDCE3_PHYS_BASE_ASYNC    0xf0000000      /* ASDO Pin = 0 */
+#define EP93XX_CS0_PHYS_BASE_SYNC       0xf0000000      /* ASDO Pin = 1 */
+
+/* AHB peripherals */
+#define EP93XX_DMA_BASE                 EP93XX_AHB_IOMEM(0x00000000)
+
+#define EP93XX_ETHERNET_PHYS_BASE       EP93XX_AHB_PHYS(0x00010000)
+#define EP93XX_ETHERNET_BASE            EP93XX_AHB_IOMEM(0x00010000)
+
+#define EP93XX_USB_PHYS_BASE            EP93XX_AHB_PHYS(0x00020000)
+#define EP93XX_USB_BASE                 EP93XX_AHB_IOMEM(0x00020000)
+
+#define EP93XX_RASTER_PHYS_BASE         EP93XX_AHB_PHYS(0x00030000)
+#define EP93XX_RASTER_BASE              EP93XX_AHB_IOMEM(0x00030000)
+
+#define EP93XX_GRAPHICS_ACCEL_BASE      EP93XX_AHB_IOMEM(0x00040000)
+
+#define EP93XX_SDRAM_CONTROLLER_BASE    EP93XX_AHB_IOMEM(0x00060000)
+
+#define EP93XX_PCMCIA_CONTROLLER_BASE   EP93XX_AHB_IOMEM(0x00080000)
+
+#define EP93XX_BOOT_ROM_BASE            EP93XX_AHB_IOMEM(0x00090000)
+
+#define EP93XX_IDE_BASE                 EP93XX_AHB_IOMEM(0x000a0000)
+
+#define EP93XX_VIC1_BASE                EP93XX_AHB_IOMEM(0x000b0000)
+
+#define EP93XX_VIC2_BASE                EP93XX_AHB_IOMEM(0x000c0000)
+
+/* APB peripherals */
+#define EP93XX_TIMER_BASE               EP93XX_APB_IOMEM(0x00010000)
+
+#define EP93XX_I2S_PHYS_BASE            EP93XX_APB_PHYS(0x00020000)
+#define EP93XX_I2S_BASE                 EP93XX_APB_IOMEM(0x00020000)
+
+#define EP93XX_SECURITY_BASE            EP93XX_APB_IOMEM(0x00030000)
+
+#define EP93XX_AAC_PHYS_BASE            EP93XX_APB_PHYS(0x00080000)
+#define EP93XX_AAC_BASE                 EP93XX_APB_IOMEM(0x00080000)
+
+#define EP93XX_SPI_PHYS_BASE            EP93XX_APB_PHYS(0x000a0000)
+#define EP93XX_SPI_BASE                 EP93XX_APB_IOMEM(0x000a0000)
+
+#define EP93XX_IRDA_BASE                EP93XX_APB_IOMEM(0x000b0000)
+
+#define EP93XX_KEY_MATRIX_PHYS_BASE     EP93XX_APB_PHYS(0x000f0000)
+#define EP93XX_KEY_MATRIX_BASE          EP93XX_APB_IOMEM(0x000f0000)
+
+#define EP93XX_ADC_BASE                 EP93XX_APB_IOMEM(0x00100000)
+#define EP93XX_TOUCHSCREEN_BASE         EP93XX_APB_IOMEM(0x00100000)
+
+#define EP93XX_PWM_PHYS_BASE            EP93XX_APB_PHYS(0x00110000)
+#define EP93XX_PWM_BASE                 EP93XX_APB_IOMEM(0x00110000)
+
+#define EP93XX_RTC_PHYS_BASE            EP93XX_APB_PHYS(0x00120000)
+#define EP93XX_RTC_BASE                 EP93XX_APB_IOMEM(0x00120000)
+
+#define EP93XX_WATCHDOG_PHYS_BASE       EP93XX_APB_PHYS(0x00140000)
+#define EP93XX_WATCHDOG_BASE            EP93XX_APB_IOMEM(0x00140000)
+
+/* System controller */
+#define EP93XX_SYSCON_BASE              EP93XX_APB_IOMEM(0x00130000)
+#define EP93XX_SYSCON_REG(x)            (EP93XX_SYSCON_BASE + (x))
+#define EP93XX_SYSCON_POWER_STATE       EP93XX_SYSCON_REG(0x00)
+#define EP93XX_SYSCON_PWRCNT            EP93XX_SYSCON_REG(0x04)
+#define EP93XX_SYSCON_PWRCNT_FIR_EN     (1<<31)
+#define EP93XX_SYSCON_PWRCNT_UARTBAUD   (1<<29)
+#define EP93XX_SYSCON_PWRCNT_USH_EN     (1<<28)
+#define EP93XX_SYSCON_PWRCNT_DMA_M2M1   (1<<27)
+#define EP93XX_SYSCON_PWRCNT_DMA_M2M0   (1<<26)
+#define EP93XX_SYSCON_PWRCNT_DMA_M2P8   (1<<25)
+#define EP93XX_SYSCON_PWRCNT_DMA_M2P9   (1<<24)
+#define EP93XX_SYSCON_PWRCNT_DMA_M2P6   (1<<23)
+#define EP93XX_SYSCON_PWRCNT_DMA_M2P7   (1<<22)
+#define EP93XX_SYSCON_PWRCNT_DMA_M2P4   (1<<21)
+#define EP93XX_SYSCON_PWRCNT_DMA_M2P5   (1<<20)
+#define EP93XX_SYSCON_PWRCNT_DMA_M2P2   (1<<19)
+#define EP93XX_SYSCON_PWRCNT_DMA_M2P3   (1<<18)
+#define EP93XX_SYSCON_PWRCNT_DMA_M2P0   (1<<17)
+#define EP93XX_SYSCON_PWRCNT_DMA_M2P1   (1<<16)
+#define EP93XX_SYSCON_HALT              EP93XX_SYSCON_REG(0x08)
+#define EP93XX_SYSCON_STANDBY           EP93XX_SYSCON_REG(0x0c)
+#define EP93XX_SYSCON_CLKSET1           EP93XX_SYSCON_REG(0x20)
+#define EP93XX_SYSCON_CLKSET1_NBYP1     (1<<23)
+#define EP93XX_SYSCON_CLKSET2           EP93XX_SYSCON_REG(0x24)
+#define EP93XX_SYSCON_CLKSET2_NBYP2     (1<<19)
+#define EP93XX_SYSCON_CLKSET2_PLL2_EN   (1<<18)
+#define EP93XX_SYSCON_DEVCFG            EP93XX_SYSCON_REG(0x80)
+#define EP93XX_SYSCON_DEVCFG_SWRST      (1<<31)
+#define EP93XX_SYSCON_DEVCFG_D1ONG      (1<<30)
+#define EP93XX_SYSCON_DEVCFG_D0ONG      (1<<29)
+#define EP93XX_SYSCON_DEVCFG_IONU2      (1<<28)
+#define EP93XX_SYSCON_DEVCFG_GONK       (1<<27)
+#define EP93XX_SYSCON_DEVCFG_TONG       (1<<26)
+#define EP93XX_SYSCON_DEVCFG_MONG       (1<<25)
+#define EP93XX_SYSCON_DEVCFG_U3EN       (1<<24)
+#define EP93XX_SYSCON_DEVCFG_CPENA      (1<<23)
+#define EP93XX_SYSCON_DEVCFG_A2ONG      (1<<22)
+#define EP93XX_SYSCON_DEVCFG_A1ONG      (1<<21)
+#define EP93XX_SYSCON_DEVCFG_U2EN       (1<<20)
+#define EP93XX_SYSCON_DEVCFG_EXVC       (1<<19)
+#define EP93XX_SYSCON_DEVCFG_U1EN       (1<<18)
+#define EP93XX_SYSCON_DEVCFG_TIN        (1<<17)
+#define EP93XX_SYSCON_DEVCFG_HC3IN      (1<<15)
+#define EP93XX_SYSCON_DEVCFG_HC3EN      (1<<14)
+#define EP93XX_SYSCON_DEVCFG_HC1IN      (1<<13)
+#define EP93XX_SYSCON_DEVCFG_HC1EN      (1<<12)
+#define EP93XX_SYSCON_DEVCFG_HONIDE     (1<<11)
+#define EP93XX_SYSCON_DEVCFG_GONIDE     (1<<10)
+#define EP93XX_SYSCON_DEVCFG_PONG       (1<<9)
+#define EP93XX_SYSCON_DEVCFG_EONIDE     (1<<8)
+#define EP93XX_SYSCON_DEVCFG_I2SONSSP   (1<<7)
+#define EP93XX_SYSCON_DEVCFG_I2SONAC97  (1<<6)
+#define EP93XX_SYSCON_DEVCFG_RASONP3    (1<<4)
+#define EP93XX_SYSCON_DEVCFG_RAS        (1<<3)
+#define EP93XX_SYSCON_DEVCFG_ADCPD      (1<<2)
+#define EP93XX_SYSCON_DEVCFG_KEYS       (1<<1)
+#define EP93XX_SYSCON_DEVCFG_SHENA      (1<<0)
+#define EP93XX_SYSCON_VIDCLKDIV         EP93XX_SYSCON_REG(0x84)
+#define EP93XX_SYSCON_CLKDIV_ENABLE     (1<<15)
+#define EP93XX_SYSCON_CLKDIV_ESEL       (1<<14)
+#define EP93XX_SYSCON_CLKDIV_PSEL       (1<<13)
+#define EP93XX_SYSCON_CLKDIV_PDIV_SHIFT 8
+#define EP93XX_SYSCON_I2SCLKDIV         EP93XX_SYSCON_REG(0x8c)
+#define EP93XX_SYSCON_I2SCLKDIV_SENA    (1<<31)
+#define EP93XX_SYSCON_I2SCLKDIV_ORIDE   (1<<29)
+#define EP93XX_SYSCON_I2SCLKDIV_SPOL    (1<<19)
+#define EP93XX_I2SCLKDIV_SDIV           (1 << 16)
+#define EP93XX_I2SCLKDIV_LRDIV32        (0 << 17)
+#define EP93XX_I2SCLKDIV_LRDIV64        (1 << 17)
+#define EP93XX_I2SCLKDIV_LRDIV128       (2 << 17)
+#define EP93XX_I2SCLKDIV_LRDIV_MASK     (3 << 17)
+#define EP93XX_SYSCON_KEYTCHCLKDIV      EP93XX_SYSCON_REG(0x90)
+#define EP93XX_SYSCON_KEYTCHCLKDIV_TSEN (1<<31)
+#define EP93XX_SYSCON_KEYTCHCLKDIV_ADIV (1<<16)
+#define EP93XX_SYSCON_KEYTCHCLKDIV_KEN  (1<<15)
+#define EP93XX_SYSCON_KEYTCHCLKDIV_KDIV (1<<0)
+#define EP93XX_SYSCON_SYSCFG            EP93XX_SYSCON_REG(0x9c)
+#define EP93XX_SYSCON_SYSCFG_REV_MASK   (0xf0000000)
+#define EP93XX_SYSCON_SYSCFG_REV_SHIFT  (28)
+#define EP93XX_SYSCON_SYSCFG_SBOOT      (1<<8)
+#define EP93XX_SYSCON_SYSCFG_LCSN7      (1<<7)
+#define EP93XX_SYSCON_SYSCFG_LCSN6      (1<<6)
+#define EP93XX_SYSCON_SYSCFG_LASDO      (1<<5)
+#define EP93XX_SYSCON_SYSCFG_LEEDA      (1<<4)
+#define EP93XX_SYSCON_SYSCFG_LEECLK     (1<<3)
+#define EP93XX_SYSCON_SYSCFG_LCSN2      (1<<1)
+#define EP93XX_SYSCON_SYSCFG_LCSN1      (1<<0)
+#define EP93XX_SYSCON_SWLOCK            EP93XX_SYSCON_REG(0xc0)
+
+/* EP93xx System Controller software locked register write */
+void ep93xx_syscon_swlocked_write(unsigned int val, void __iomem *reg);
+void ep93xx_devcfg_set_clear(unsigned int set_bits, unsigned int clear_bits);
+
+static inline void ep93xx_devcfg_set_bits(unsigned int bits)
+{
+        ep93xx_devcfg_set_clear(bits, 0x00);
+}
+
+static inline void ep93xx_devcfg_clear_bits(unsigned int bits)
+{
+        ep93xx_devcfg_set_clear(0x00, bits);
+}
+
+#endif /* _EP93XX_SOC_H */
diff --git a/arch/arm/mach-ep93xx/ts72xx.c b/arch/arm/mach-ep93xx/ts72xx.c
index 79f8ecf07a1..5ea790942e9 100644
--- a/arch/arm/mach-ep93xx/ts72xx.c
+++ b/arch/arm/mach-ep93xx/ts72xx.c
@@ -28,6 +28,7 @@
 #include <asm/mach/map.h>
 #include <asm/mach/arch.h>
 
+#include "soc.h"
 
 static struct map_desc ts72xx_io_desc[] __initdata = {
         {
diff --git a/arch/arm/mach-ep93xx/vision_ep9307.c b/arch/arm/mach-ep93xx/vision_ep9307.c
index d67d0b4feb6..ba156eb225e 100644
--- a/arch/arm/mach-ep93xx/vision_ep9307.c
+++ b/arch/arm/mach-ep93xx/vision_ep9307.c
@@ -39,6 +39,8 @@
 #include <asm/mach/map.h>
 #include <asm/mach/arch.h>
 
+#include "soc.h"
+
 /*************************************************************************
  * Static I/O mappings for the FPGA
  *************************************************************************/
diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index dfad6538b27..2bf7d6e2398 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -42,6 +42,7 @@ config SOC_EXYNOS4212
         bool "SAMSUNG EXYNOS4212"
         default y
         depends on ARCH_EXYNOS4
+        select SAMSUNG_DMADEV
         select S5P_PM if PM
         select S5P_SLEEP if PM
         help
@@ -51,6 +52,7 @@ config SOC_EXYNOS4412
         bool "SAMSUNG EXYNOS4412"
         default y
         depends on ARCH_EXYNOS4
+        select SAMSUNG_DMADEV
         help
           Enable EXYNOS4412 SoC support
 
@@ -179,7 +181,9 @@ config MACH_SMDKV310
         select S5P_DEV_FIMC1
         select S5P_DEV_FIMC2
         select S5P_DEV_FIMC3
+        select S5P_DEV_G2D
         select S5P_DEV_I2C_HDMIPHY
+        select S5P_DEV_JPEG
         select S5P_DEV_MFC
         select S5P_DEV_TV
         select S5P_DEV_USB_EHCI
@@ -225,7 +229,9 @@ config MACH_UNIVERSAL_C210
         select S5P_DEV_FIMC1
         select S5P_DEV_FIMC2
         select S5P_DEV_FIMC3
+        select S5P_DEV_G2D
         select S5P_DEV_CSIS0
+        select S5P_DEV_JPEG
         select S5P_DEV_FIMD0
         select S3C_DEV_HSMMC
         select S3C_DEV_HSMMC2
@@ -262,11 +268,14 @@ config MACH_NURI
         select S3C_DEV_I2C1
         select S3C_DEV_I2C3
         select S3C_DEV_I2C5
+        select S3C_DEV_I2C6
         select S5P_DEV_CSIS0
+        select S5P_DEV_JPEG
         select S5P_DEV_FIMC0
         select S5P_DEV_FIMC1
         select S5P_DEV_FIMC2
         select S5P_DEV_FIMC3
+        select S5P_DEV_G2D
         select S5P_DEV_MFC
         select S5P_DEV_USB_EHCI
         select S5P_SETUP_MIPIPHY
@@ -276,6 +285,7 @@ config MACH_NURI
         select EXYNOS4_SETUP_I2C1
         select EXYNOS4_SETUP_I2C3
         select EXYNOS4_SETUP_I2C5
+        select EXYNOS4_SETUP_I2C6
         select EXYNOS4_SETUP_SDHCI
         select EXYNOS4_SETUP_USB_PHY
         select S5P_SETUP_MIPIPHY
@@ -296,7 +306,9 @@ config MACH_ORIGEN
         select S5P_DEV_FIMC2
         select S5P_DEV_FIMC3
         select S5P_DEV_FIMD0
+        select S5P_DEV_G2D
         select S5P_DEV_I2C_HDMIPHY
+        select S5P_DEV_JPEG
         select S5P_DEV_MFC
         select S5P_DEV_TV
         select S5P_DEV_USB_EHCI
@@ -325,6 +337,7 @@ config MACH_SMDK4212
         select SAMSUNG_DEV_BACKLIGHT
         select SAMSUNG_DEV_KEYPAD
         select SAMSUNG_DEV_PWM
+        select EXYNOS4_DEV_DMA
         select EXYNOS4_SETUP_I2C1
         select EXYNOS4_SETUP_I2C3
         select EXYNOS4_SETUP_I2C7
diff --git a/arch/arm/mach-exynos/Makefile b/arch/arm/mach-exynos/Makefile
index d9191f9a7af..9a4c0989650 100644
--- a/arch/arm/mach-exynos/Makefile
+++ b/arch/arm/mach-exynos/Makefile
@@ -12,7 +12,8 @@ obj-				:=
 
 # Core
 
-obj-$(CONFIG_ARCH_EXYNOS4)      += common.o clock.o
+obj-$(CONFIG_ARCH_EXYNOS)       += common.o
+obj-$(CONFIG_ARCH_EXYNOS4)      += clock-exynos4.o
 obj-$(CONFIG_CPU_EXYNOS4210)    += clock-exynos4210.o
 obj-$(CONFIG_SOC_EXYNOS4212)    += clock-exynos4212.o
 
diff --git a/arch/arm/mach-exynos/clock-exynos4.c b/arch/arm/mach-exynos/clock-exynos4.c
new file mode 100644
index 00000000000..200159dcb34
--- /dev/null
+++ b/arch/arm/mach-exynos/clock-exynos4.c
@@ -0,0 +1,1577 @@
+/*
+ * Copyright (c) 2010-2012 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * EXYNOS4 - Clock support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/syscore_ops.h>
+
+#include <plat/cpu-freq.h>
+#include <plat/clock.h>
+#include <plat/cpu.h>
+#include <plat/pll.h>
+#include <plat/s5p-clock.h>
+#include <plat/clock-clksrc.h>
+#include <plat/pm.h>
+
+#include <mach/map.h>
+#include <mach/regs-clock.h>
+#include <mach/sysmmu.h>
+
+#include "common.h"
+#include "clock-exynos4.h"
+
+#ifdef CONFIG_PM_SLEEP
+static struct sleep_save exynos4_clock_save[] = {
+        SAVE_ITEM(EXYNOS4_CLKDIV_LEFTBUS),
+        SAVE_ITEM(EXYNOS4_CLKGATE_IP_LEFTBUS),
+        SAVE_ITEM(EXYNOS4_CLKDIV_RIGHTBUS),
+        SAVE_ITEM(EXYNOS4_CLKGATE_IP_RIGHTBUS),
+        SAVE_ITEM(EXYNOS4_CLKSRC_TOP0),
+        SAVE_ITEM(EXYNOS4_CLKSRC_TOP1),
+        SAVE_ITEM(EXYNOS4_CLKSRC_CAM),
+        SAVE_ITEM(EXYNOS4_CLKSRC_TV),
+        SAVE_ITEM(EXYNOS4_CLKSRC_MFC),
+        SAVE_ITEM(EXYNOS4_CLKSRC_G3D),
+        SAVE_ITEM(EXYNOS4_CLKSRC_LCD0),
+        SAVE_ITEM(EXYNOS4_CLKSRC_MAUDIO),
+        SAVE_ITEM(EXYNOS4_CLKSRC_FSYS),
+        SAVE_ITEM(EXYNOS4_CLKSRC_PERIL0),
+        SAVE_ITEM(EXYNOS4_CLKSRC_PERIL1),
+        SAVE_ITEM(EXYNOS4_CLKDIV_CAM),
+        SAVE_ITEM(EXYNOS4_CLKDIV_TV),
+        SAVE_ITEM(EXYNOS4_CLKDIV_MFC),
+        SAVE_ITEM(EXYNOS4_CLKDIV_G3D),
+        SAVE_ITEM(EXYNOS4_CLKDIV_LCD0),
+        SAVE_ITEM(EXYNOS4_CLKDIV_MAUDIO),
+        SAVE_ITEM(EXYNOS4_CLKDIV_FSYS0),
+        SAVE_ITEM(EXYNOS4_CLKDIV_FSYS1),
+        SAVE_ITEM(EXYNOS4_CLKDIV_FSYS2),
+        SAVE_ITEM(EXYNOS4_CLKDIV_FSYS3),
+        SAVE_ITEM(EXYNOS4_CLKDIV_PERIL0),
+        SAVE_ITEM(EXYNOS4_CLKDIV_PERIL1),
+        SAVE_ITEM(EXYNOS4_CLKDIV_PERIL2),
+        SAVE_ITEM(EXYNOS4_CLKDIV_PERIL3),
+        SAVE_ITEM(EXYNOS4_CLKDIV_PERIL4),
+        SAVE_ITEM(EXYNOS4_CLKDIV_PERIL5),
+        SAVE_ITEM(EXYNOS4_CLKDIV_TOP),
+        SAVE_ITEM(EXYNOS4_CLKSRC_MASK_TOP),
+        SAVE_ITEM(EXYNOS4_CLKSRC_MASK_CAM),
+        SAVE_ITEM(EXYNOS4_CLKSRC_MASK_TV),
+        SAVE_ITEM(EXYNOS4_CLKSRC_MASK_LCD0),
+        SAVE_ITEM(EXYNOS4_CLKSRC_MASK_MAUDIO),
+        SAVE_ITEM(EXYNOS4_CLKSRC_MASK_FSYS),
+        SAVE_ITEM(EXYNOS4_CLKSRC_MASK_PERIL0),
+        SAVE_ITEM(EXYNOS4_CLKSRC_MASK_PERIL1),
+        SAVE_ITEM(EXYNOS4_CLKDIV2_RATIO),
+        SAVE_ITEM(EXYNOS4_CLKGATE_SCLKCAM),
+        SAVE_ITEM(EXYNOS4_CLKGATE_IP_CAM),
+        SAVE_ITEM(EXYNOS4_CLKGATE_IP_TV),
+        SAVE_ITEM(EXYNOS4_CLKGATE_IP_MFC),
+        SAVE_ITEM(EXYNOS4_CLKGATE_IP_G3D),
+        SAVE_ITEM(EXYNOS4_CLKGATE_IP_LCD0),
+        SAVE_ITEM(EXYNOS4_CLKGATE_IP_FSYS),
+        SAVE_ITEM(EXYNOS4_CLKGATE_IP_GPS),
+        SAVE_ITEM(EXYNOS4_CLKGATE_IP_PERIL),
+        SAVE_ITEM(EXYNOS4_CLKGATE_BLOCK),
+        SAVE_ITEM(EXYNOS4_CLKSRC_MASK_DMC),
+        SAVE_ITEM(EXYNOS4_CLKSRC_DMC),
+        SAVE_ITEM(EXYNOS4_CLKDIV_DMC0),
+        SAVE_ITEM(EXYNOS4_CLKDIV_DMC1),
+        SAVE_ITEM(EXYNOS4_CLKGATE_IP_DMC),
+        SAVE_ITEM(EXYNOS4_CLKSRC_CPU),
+        SAVE_ITEM(EXYNOS4_CLKDIV_CPU),
+        SAVE_ITEM(EXYNOS4_CLKDIV_CPU + 0x4),
+        SAVE_ITEM(EXYNOS4_CLKGATE_SCLKCPU),
+        SAVE_ITEM(EXYNOS4_CLKGATE_IP_CPU),
+};
+#endif
+
+static struct clk exynos4_clk_sclk_hdmi27m = {
+        .name           = "sclk_hdmi27m",
+        .rate           = 27000000,
+};
+
+static struct clk exynos4_clk_sclk_hdmiphy = {
+        .name           = "sclk_hdmiphy",
+};
+
+static struct clk exynos4_clk_sclk_usbphy0 = {
+        .name           = "sclk_usbphy0",
+        .rate           = 27000000,
+};
+
+static struct clk exynos4_clk_sclk_usbphy1 = {
+        .name           = "sclk_usbphy1",
+};
+
+static struct clk dummy_apb_pclk = {
+        .name           = "apb_pclk",
+        .id             = -1,
+};
+
+static int exynos4_clksrc_mask_top_ctrl(struct clk *clk, int enable)
+{
+        return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_TOP, clk, enable);
+}
+
+static int exynos4_clksrc_mask_cam_ctrl(struct clk *clk, int enable)
+{
+        return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_CAM, clk, enable);
+}
+
+static int exynos4_clksrc_mask_lcd0_ctrl(struct clk *clk, int enable)
+{
+        return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_LCD0, clk, enable);
+}
+
+int exynos4_clksrc_mask_fsys_ctrl(struct clk *clk, int enable)
+{
+        return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_FSYS, clk, enable);
+}
+
+static int exynos4_clksrc_mask_peril0_ctrl(struct clk *clk, int enable)
+{
+        return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_PERIL0, clk, enable);
+}
+
+static int exynos4_clksrc_mask_peril1_ctrl(struct clk *clk, int enable)
+{
+        return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_PERIL1, clk, enable);
+}
+
+static int exynos4_clk_ip_mfc_ctrl(struct clk *clk, int enable)
+{
+        return s5p_gatectrl(EXYNOS4_CLKGATE_IP_MFC, clk, enable);
+}
+
+static int exynos4_clksrc_mask_tv_ctrl(struct clk *clk, int enable)
+{
+        return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_TV, clk, enable);
+}
+
+static int exynos4_clk_ip_cam_ctrl(struct clk *clk, int enable)
+{
+        return s5p_gatectrl(EXYNOS4_CLKGATE_IP_CAM, clk, enable);
+}
+
+static int exynos4_clk_ip_tv_ctrl(struct clk *clk, int enable)
+{
+        return s5p_gatectrl(EXYNOS4_CLKGATE_IP_TV, clk, enable);
+}
+
+static int exynos4_clk_ip_image_ctrl(struct clk *clk, int enable)
+{
+        return s5p_gatectrl(EXYNOS4_CLKGATE_IP_IMAGE, clk, enable);
+}
+
+static int exynos4_clk_ip_lcd0_ctrl(struct clk *clk, int enable)
+{
+        return s5p_gatectrl(EXYNOS4_CLKGATE_IP_LCD0, clk, enable);
+}
+
+int exynos4_clk_ip_lcd1_ctrl(struct clk *clk, int enable)
+{
+        return s5p_gatectrl(EXYNOS4210_CLKGATE_IP_LCD1, clk, enable);
+}
+
+int exynos4_clk_ip_fsys_ctrl(struct clk *clk, int enable)
+{
+        return s5p_gatectrl(EXYNOS4_CLKGATE_IP_FSYS, clk, enable);
+}
+
+static int exynos4_clk_ip_peril_ctrl(struct clk *clk, int enable)
+{
+        return s5p_gatectrl(EXYNOS4_CLKGATE_IP_PERIL, clk, enable);
+}
+
+static int exynos4_clk_ip_perir_ctrl(struct clk *clk, int enable)
+{
+        return s5p_gatectrl(EXYNOS4_CLKGATE_IP_PERIR, clk, enable);
+}
+
+static int exynos4_clk_hdmiphy_ctrl(struct clk *clk, int enable)
+{
+        return s5p_gatectrl(S5P_HDMI_PHY_CONTROL, clk, enable);
+}
+
+static int exynos4_clk_dac_ctrl(struct clk *clk, int enable)
+{
+        return s5p_gatectrl(S5P_DAC_PHY_CONTROL, clk, enable);
+}
+
+/* Core list of CMU_CPU side */
+
+static struct clksrc_clk exynos4_clk_mout_apll = {
+        .clk    = {
+                .name           = "mout_apll",
+        },
+        .sources = &clk_src_apll,
+        .reg_src = { .reg = EXYNOS4_CLKSRC_CPU, .shift = 0, .size = 1 },
+};
+
+static struct clksrc_clk exynos4_clk_sclk_apll = {
+        .clk    = {
+                .name           = "sclk_apll",
+                .parent         = &exynos4_clk_mout_apll.clk,
+        },
+        .reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 24, .size = 3 },
+};
+
+static struct clksrc_clk exynos4_clk_mout_epll = {
+        .clk    = {
+                .name           = "mout_epll",
+        },
+        .sources = &clk_src_epll,
+        .reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 4, .size = 1 },
+};
+
+struct clksrc_clk exynos4_clk_mout_mpll = {
+        .clk    = {
+                .name           = "mout_mpll",
+        },
+        .sources = &clk_src_mpll,
+
+        /* reg_src will be added in each SoCs' clock */
+};
+
+static struct clk *exynos4_clkset_moutcore_list[] = {
+        [0] = &exynos4_clk_mout_apll.clk,
+        [1] = &exynos4_clk_mout_mpll.clk,
+};
+
+static struct clksrc_sources exynos4_clkset_moutcore = {
+        .sources        = exynos4_clkset_moutcore_list,
+        .nr_sources     = ARRAY_SIZE(exynos4_clkset_moutcore_list),
+};
+
+static struct clksrc_clk exynos4_clk_moutcore = {
+        .clk    = {
+                .name           = "moutcore",
+        },
+        .sources = &exynos4_clkset_moutcore,
+        .reg_src = { .reg = EXYNOS4_CLKSRC_CPU, .shift = 16, .size = 1 },
+};
+
+static struct clksrc_clk exynos4_clk_coreclk = {
+        .clk    = {
+                .name           = "core_clk",
+                .parent         = &exynos4_clk_moutcore.clk,
+        },
+        .reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 0, .size = 3 },
+};
+
+static struct clksrc_clk exynos4_clk_armclk = {
+        .clk    = {
+                .name           = "armclk",
+                .parent         = &exynos4_clk_coreclk.clk,
+        },
+};
+
+static struct clksrc_clk exynos4_clk_aclk_corem0 = {
+        .clk    = {
+                .name           = "aclk_corem0",
+                .parent         = &exynos4_clk_coreclk.clk,
+        },
+        .reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 4, .size = 3 },
+};
+
+static struct clksrc_clk exynos4_clk_aclk_cores = {
+        .clk    = {
+                .name           = "aclk_cores",
+                .parent         = &exynos4_clk_coreclk.clk,
+        },
+        .reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 4, .size = 3 },
+};
+
+static struct clksrc_clk exynos4_clk_aclk_corem1 = {
+        .clk    = {
+                .name           = "aclk_corem1",
+                .parent         = &exynos4_clk_coreclk.clk,
+        },
+        .reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 8, .size = 3 },
+};
+
+static struct clksrc_clk exynos4_clk_periphclk = {
+        .clk    = {
+                .name           = "periphclk",
+                .parent         = &exynos4_clk_coreclk.clk,
+        },
+        .reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 12, .size = 3 },
+};
+
+/* Core list of CMU_CORE side */
+
+static struct clk *exynos4_clkset_corebus_list[] = {
+        [0] = &exynos4_clk_mout_mpll.clk,
+        [1] = &exynos4_clk_sclk_apll.clk,
+};
+
+struct clksrc_sources exynos4_clkset_mout_corebus = {
+        .sources        = exynos4_clkset_corebus_list,
+        .nr_sources     = ARRAY_SIZE(exynos4_clkset_corebus_list),
+};
+
+static struct clksrc_clk exynos4_clk_mout_corebus = {
+        .clk    = {
+                .name           = "mout_corebus",
+        },
+        .sources = &exynos4_clkset_mout_corebus,
+        .reg_src = { .reg = EXYNOS4_CLKSRC_DMC, .shift = 4, .size = 1 },
+};
+
+static struct clksrc_clk exynos4_clk_sclk_dmc = {
+        .clk    = {
+                .name           = "sclk_dmc",
+                .parent         = &exynos4_clk_mout_corebus.clk,
+        },
+        .reg_div = { .reg = EXYNOS4_CLKDIV_DMC0, .shift = 12, .size = 3 },
+};
+
+static struct clksrc_clk exynos4_clk_aclk_cored = {
+        .clk    = {
+                .name           = "aclk_cored",
+                .parent         = &exynos4_clk_sclk_dmc.clk,
+        },
+        .reg_div = { .reg = EXYNOS4_CLKDIV_DMC0, .shift = 16, .size = 3 },
+};
+
+static struct clksrc_clk exynos4_clk_aclk_corep = {
+        .clk    = {
+                .name           = "aclk_corep",
+                .parent         = &exynos4_clk_aclk_cored.clk,
+        },
+        .reg_div = { .reg = EXYNOS4_CLKDIV_DMC0, .shift = 20, .size = 3 },
+};
+
+static struct clksrc_clk exynos4_clk_aclk_acp = {
+        .clk    = {
+                .name           = "aclk_acp",
+                .parent         = &exynos4_clk_mout_corebus.clk,
+        },
+        .reg_div = { .reg = EXYNOS4_CLKDIV_DMC0, .shift = 0, .size = 3 },
+};
+
+static struct clksrc_clk exynos4_clk_pclk_acp = {
+        .clk    = {
+                .name           = "pclk_acp",
+                .parent         = &exynos4_clk_aclk_acp.clk,
+        },
+        .reg_div = { .reg = EXYNOS4_CLKDIV_DMC0, .shift = 4, .size = 3 },
+};
+
+/* Core list of CMU_TOP side */
+
+struct clk *exynos4_clkset_aclk_top_list[] = {
+        [0] = &exynos4_clk_mout_mpll.clk,
+        [1] = &exynos4_clk_sclk_apll.clk,
+};
+
+static struct clksrc_sources exynos4_clkset_aclk = {
+        .sources        = exynos4_clkset_aclk_top_list,
+        .nr_sources     = ARRAY_SIZE(exynos4_clkset_aclk_top_list),
+};
+
+static struct clksrc_clk exynos4_clk_aclk_200 = {
+        .clk    = {
+                .name           = "aclk_200",
+        },
+        .sources = &exynos4_clkset_aclk,
+        .reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 12, .size = 1 },
+        .reg_div = { .reg = EXYNOS4_CLKDIV_TOP, .shift = 0, .size = 3 },
+};
+
+static struct clksrc_clk exynos4_clk_aclk_100 = {
+        .clk    = {
+                .name           = "aclk_100",
+        },
+        .sources = &exynos4_clkset_aclk,
+        .reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 16, .size = 1 },
+        .reg_div = { .reg = EXYNOS4_CLKDIV_TOP, .shift = 4, .size = 4 },
+};
+
+static struct clksrc_clk exynos4_clk_aclk_160 = {
+        .clk    = {
+                .name           = "aclk_160",
+        },
+        .sources = &exynos4_clkset_aclk,
+        .reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 20, .size = 1 },
+        .reg_div = { .reg = EXYNOS4_CLKDIV_TOP, .shift = 8, .size = 3 },
+};
+
+struct clksrc_clk exynos4_clk_aclk_133 = {
+        .clk    = {
+                .name           = "aclk_133",
+        },
+        .sources = &exynos4_clkset_aclk,
+        .reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 24, .size = 1 },
+        .reg_div = { .reg = EXYNOS4_CLKDIV_TOP, .shift = 12, .size = 3 },
+};
+
+static struct clk *exynos4_clkset_vpllsrc_list[] = {
+        [0] = &clk_fin_vpll,
+        [1] = &exynos4_clk_sclk_hdmi27m,
+};
+
+static struct clksrc_sources exynos4_clkset_vpllsrc = {
+        .sources        = exynos4_clkset_vpllsrc_list,
+        .nr_sources     = ARRAY_SIZE(exynos4_clkset_vpllsrc_list),
+};
+
+static struct clksrc_clk exynos4_clk_vpllsrc = {
+        .clk    = {
+                .name           = "vpll_src",
+                .enable         = exynos4_clksrc_mask_top_ctrl,
+                .ctrlbit        = (1 << 0),
+        },
+        .sources = &exynos4_clkset_vpllsrc,
+        .reg_src = { .reg = EXYNOS4_CLKSRC_TOP1, .shift = 0, .size = 1 },
+};
+
+static struct clk *exynos4_clkset_sclk_vpll_list[] = {
+        [0] = &exynos4_clk_vpllsrc.clk,
+        [1] = &clk_fout_vpll,
+};
+
+static struct clksrc_sources exynos4_clkset_sclk_vpll = {
+        .sources        = exynos4_clkset_sclk_vpll_list,
+        .nr_sources     = ARRAY_SIZE(exynos4_clkset_sclk_vpll_list),
+};
+
+static struct clksrc_clk exynos4_clk_sclk_vpll = {
+        .clk    = {
+                .name           = "sclk_vpll",
+        },
+        .sources = &exynos4_clkset_sclk_vpll,
+        .reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 8, .size = 1 },
+};
+
+static struct clk exynos4_init_clocks_off[] = {
+        {
+                .name           = "timers",
+                .parent         = &exynos4_clk_aclk_100.clk,
+                .enable         = exynos4_clk_ip_peril_ctrl,
+                .ctrlbit        = (1<<24),
+        }, {
+                .name           = "csis",
+                .devname        = "s5p-mipi-csis.0",
+                .enable         = exynos4_clk_ip_cam_ctrl,
+                .ctrlbit        = (1 << 4),
+        }, {
+                .name           = "csis",
+                .devname        = "s5p-mipi-csis.1",
+                .enable         = exynos4_clk_ip_cam_ctrl,
+                .ctrlbit        = (1 << 5),
+        }, {
+                .name           = "jpeg",
+                .id             = 0,
+                .enable         = exynos4_clk_ip_cam_ctrl,
+                .ctrlbit        = (1 << 6),
+        }, {
+                .name           = "fimc",
+                .devname        = "exynos4-fimc.0",
+                .enable         = exynos4_clk_ip_cam_ctrl,
+                .ctrlbit        = (1 << 0),
+        }, {
+                .name           = "fimc",
+                .devname        = "exynos4-fimc.1",
+                .enable         = exynos4_clk_ip_cam_ctrl,
+                .ctrlbit        = (1 << 1),
+        }, {
+                .name           = "fimc",
+                .devname        = "exynos4-fimc.2",
+                .enable         = exynos4_clk_ip_cam_ctrl,
+                .ctrlbit        = (1 << 2),
+        }, {
+                .name           = "fimc",
+                .devname        = "exynos4-fimc.3",
+                .enable         = exynos4_clk_ip_cam_ctrl,
+                .ctrlbit        = (1 << 3),
+        }, {
+                .name           = "fimd",
+                .devname        = "exynos4-fb.0",
+                .enable         = exynos4_clk_ip_lcd0_ctrl,
+                .ctrlbit        = (1 << 0),
+        }, {
+                .name           = "hsmmc",
+                .devname        = "s3c-sdhci.0",
+                .parent         = &exynos4_clk_aclk_133.clk,
+                .enable         = exynos4_clk_ip_fsys_ctrl,
+                .ctrlbit        = (1 << 5),
+        }, {
+                .name           = "hsmmc",
+                .devname        = "s3c-sdhci.1",
+                .parent         = &exynos4_clk_aclk_133.clk,
+                .enable         = exynos4_clk_ip_fsys_ctrl,
+                .ctrlbit        = (1 << 6),
+        }, {
+                .name           = "hsmmc",
+                .devname        = "s3c-sdhci.2",
+                .parent         = &exynos4_clk_aclk_133.clk,
+                .enable         = exynos4_clk_ip_fsys_ctrl,
+                .ctrlbit        = (1 << 7),
+        }, {
+                .name           = "hsmmc",
+                .devname        = "s3c-sdhci.3",
+                .parent         = &exynos4_clk_aclk_133.clk,
+                .enable         = exynos4_clk_ip_fsys_ctrl,
+                .ctrlbit        = (1 << 8),
+        }, {
+                .name           = "dwmmc",
+                .parent         = &exynos4_clk_aclk_133.clk,
+                .enable         = exynos4_clk_ip_fsys_ctrl,
+                .ctrlbit        = (1 << 9),
+        }, {
+                .name           = "dac",
+                .devname        = "s5p-sdo",
+                .enable         = exynos4_clk_ip_tv_ctrl,
+                .ctrlbit        = (1 << 2),
+        }, {
+                .name           = "mixer",
+                .devname        = "s5p-mixer",
+                .enable         = exynos4_clk_ip_tv_ctrl,
+                .ctrlbit        = (1 << 1),
+        }, {
+                .name           = "vp",
+                .devname        = "s5p-mixer",
+                .enable         = exynos4_clk_ip_tv_ctrl,
+                .ctrlbit        = (1 << 0),
+        }, {
+                .name           = "hdmi",
+                .devname        = "exynos4-hdmi",
+                .enable         = exynos4_clk_ip_tv_ctrl,
+                .ctrlbit        = (1 << 3),
+        }, {
+                .name           = "hdmiphy",
+                .devname        = "exynos4-hdmi",
+                .enable         = exynos4_clk_hdmiphy_ctrl,
+                .ctrlbit        = (1 << 0),
+        }, {
+                .name           = "dacphy",
+                .devname        = "s5p-sdo",
+                .enable         = exynos4_clk_dac_ctrl,
+                .ctrlbit        = (1 << 0),
+        }, {
+                .name           = "adc",
+                .enable         = exynos4_clk_ip_peril_ctrl,
+                .ctrlbit        = (1 << 15),
+        }, {
+                .name           = "keypad",
+                .enable         = exynos4_clk_ip_perir_ctrl,
+                .ctrlbit        = (1 << 16),
+        }, {
+                .name           = "rtc",
+                .enable         = exynos4_clk_ip_perir_ctrl,
+                .ctrlbit        = (1 << 15),
+        }, {
+                .name           = "watchdog",
+                .parent         = &exynos4_clk_aclk_100.clk,
+                .enable         = exynos4_clk_ip_perir_ctrl,
+                .ctrlbit        = (1 << 14),
+        }, {
+                .name           = "usbhost",
+                .enable         = exynos4_clk_ip_fsys_ctrl ,
+                .ctrlbit        = (1 << 12),
+        }, {
+                .name           = "otg",
+                .enable         = exynos4_clk_ip_fsys_ctrl,
+                .ctrlbit        = (1 << 13),
+        }, {
+                .name           = "spi",
+                .devname        = "s3c64xx-spi.0",
+                .enable         = exynos4_clk_ip_peril_ctrl,
+                .ctrlbit        = (1 << 16),
+        }, {
+                .name           = "spi",
+                .devname        = "s3c64xx-spi.1",
+                .enable         = exynos4_clk_ip_peril_ctrl,
+                .ctrlbit        = (1 << 17),
+        }, {
+                .name           = "spi",
+                .devname        = "s3c64xx-spi.2",
+                .enable         = exynos4_clk_ip_peril_ctrl,
+                .ctrlbit        = (1 << 18),
+        }, {
+                .name           = "iis",
+                .devname        = "samsung-i2s.0",
+                .enable         = exynos4_clk_ip_peril_ctrl,
+                .ctrlbit        = (1 << 19),
+        }, {
+                .name           = "iis",
+                .devname        = "samsung-i2s.1",
+                .enable         = exynos4_clk_ip_peril_ctrl,
+                .ctrlbit        = (1 << 20),
+        }, {
+                .name           = "iis",
+                .devname        = "samsung-i2s.2",
+                .enable         = exynos4_clk_ip_peril_ctrl,
+                .ctrlbit        = (1 << 21),
+        }, {
+                .name           = "ac97",
+                .devname        = "samsung-ac97",
+                .enable         = exynos4_clk_ip_peril_ctrl,
+                .ctrlbit        = (1 << 27),
+        }, {
+                .name           = "fimg2d",
+                .enable         = exynos4_clk_ip_image_ctrl,
+                .ctrlbit        = (1 << 0),
+        }, {
+                .name           = "mfc",
+                .devname        = "s5p-mfc",
+                .enable         = exynos4_clk_ip_mfc_ctrl,
+                .ctrlbit        = (1 << 0),
+        }, {
+                .name           = "i2c",
+                .devname        = "s3c2440-i2c.0",
+                .parent         = &exynos4_clk_aclk_100.clk,
+                .enable         = exynos4_clk_ip_peril_ctrl,
+                .ctrlbit        = (1 << 6),
+        }, {
+                .name           = "i2c",
+                .devname        = "s3c2440-i2c.1",
+                .parent         = &exynos4_clk_aclk_100.clk,
+                .enable         = exynos4_clk_ip_peril_ctrl,
+                .ctrlbit        = (1 << 7),
+        }, {
+                .name           = "i2c",
+                .devname        = "s3c2440-i2c.2",
+                .parent         = &exynos4_clk_aclk_100.clk,
+                .enable         = exynos4_clk_ip_peril_ctrl,
+                .ctrlbit        = (1 << 8),
+        }, {
+                .name           = "i2c",
+                .devname        = "s3c2440-i2c.3",
+                .parent         = &exynos4_clk_aclk_100.clk,
+                .enable         = exynos4_clk_ip_peril_ctrl,
+                .ctrlbit        = (1 << 9),
+        }, {
+                .name           = "i2c",
+                .devname        = "s3c2440-i2c.4",
+                .parent         = &exynos4_clk_aclk_100.clk,
+                .enable         = exynos4_clk_ip_peril_ctrl,
+                .ctrlbit        = (1 << 10),
+        }, {
+                .name           = "i2c",
+                .devname        = "s3c2440-i2c.5",
+                .parent         = &exynos4_clk_aclk_100.clk,
+                .enable         = exynos4_clk_ip_peril_ctrl,
+                .ctrlbit        = (1 << 11),
+        }, {
+                .name           = "i2c",
+                .devname        = "s3c2440-i2c.6",
+                .parent         = &exynos4_clk_aclk_100.clk,
+                .enable         = exynos4_clk_ip_peril_ctrl,
+                .ctrlbit        = (1 << 12),
+        }, {
+                .name           = "i2c",
+                .devname        = "s3c2440-i2c.7",
+                .parent         = &exynos4_clk_aclk_100.clk,
+                .enable         = exynos4_clk_ip_peril_ctrl,
+                .ctrlbit        = (1 << 13),
+        }, {
+                .name           = "i2c",
+                .devname        = "s3c2440-hdmiphy-i2c",
+                .parent         = &exynos4_clk_aclk_100.clk,
+                .enable         = exynos4_clk_ip_peril_ctrl,
+                .ctrlbit        = (1 << 14),
+        }, {
+                .name           = "SYSMMU_MDMA",
+                .enable         = exynos4_clk_ip_image_ctrl,
+                .ctrlbit        = (1 << 5),
+        }, {
+                .name           = "SYSMMU_FIMC0",
+                .enable         = exynos4_clk_ip_cam_ctrl,
+                .ctrlbit        = (1 << 7),
+        }, {
+                .name           = "SYSMMU_FIMC1",
+                .enable         = exynos4_clk_ip_cam_ctrl,
+                .ctrlbit        = (1 << 8),
+        }, {
+                .name           = "SYSMMU_FIMC2",
+                .enable         = exynos4_clk_ip_cam_ctrl,
+                .ctrlbit        = (1 << 9),
+        }, {
+                .name           = "SYSMMU_FIMC3",
+                .enable         = exynos4_clk_ip_cam_ctrl,
+                .ctrlbit        = (1 << 10),
+        }, {
+                .name           = "SYSMMU_JPEG",
+                .enable         = exynos4_clk_ip_cam_ctrl,
+                .ctrlbit        = (1 << 11),
+        }, {
+                .name           = "SYSMMU_FIMD0",
+                .enable         = exynos4_clk_ip_lcd0_ctrl,
+                .ctrlbit        = (1 << 4),
+        }, {
+                .name           = "SYSMMU_FIMD1",
+                .enable         = exynos4_clk_ip_lcd1_ctrl,
+                .ctrlbit        = (1 << 4),
+        }, {
+                .name           = "SYSMMU_PCIe",
+                .enable         = exynos4_clk_ip_fsys_ctrl,
+                .ctrlbit        = (1 << 18),
+        }, {
+                .name           = "SYSMMU_G2D",
+                .enable         = exynos4_clk_ip_image_ctrl,
+                .ctrlbit        = (1 << 3),
+        }, {
+                .name           = "SYSMMU_ROTATOR",
+                .enable         = exynos4_clk_ip_image_ctrl,
+                .ctrlbit        = (1 << 4),
+        }, {
+                .name           = "SYSMMU_TV",
+                .enable         = exynos4_clk_ip_tv_ctrl,
+                .ctrlbit        = (1 << 4),
+        }, {
+                .name           = "SYSMMU_MFC_L",
+                .enable         = exynos4_clk_ip_mfc_ctrl,
+                .ctrlbit        = (1 << 1),
+        }, {
+                .name           = "SYSMMU_MFC_R",
+                .enable         = exynos4_clk_ip_mfc_ctrl,
+                .ctrlbit        = (1 << 2),
+        }
+};
+
+static struct clk exynos4_init_clocks_on[] = {
+        {
+                .name           = "uart",
+                .devname        = "s5pv210-uart.0",
+                .enable         = exynos4_clk_ip_peril_ctrl,
+                .ctrlbit        = (1 << 0),
+        }, {
+                .name           = "uart",
+                .devname        = "s5pv210-uart.1",
+                .enable         = exynos4_clk_ip_peril_ctrl,
+                .ctrlbit        = (1 << 1),
+        }, {
+                .name           = "uart",
+                .devname        = "s5pv210-uart.2",
+                .enable         = exynos4_clk_ip_peril_ctrl,
+                .ctrlbit        = (1 << 2),
+        }, {
+                .name           = "uart",
+                .devname        = "s5pv210-uart.3",
+                .enable         = exynos4_clk_ip_peril_ctrl,
+                .ctrlbit        = (1 << 3),
+        }, {
+                .name           = "uart",
+                .devname        = "s5pv210-uart.4",
+                .enable         = exynos4_clk_ip_peril_ctrl,
+                .ctrlbit        = (1 << 4),
+        }, {
+                .name           = "uart",
+                .devname        = "s5pv210-uart.5",
+                .enable         = exynos4_clk_ip_peril_ctrl,
+                .ctrlbit        = (1 << 5),
+        }
+};
+
+static struct clk exynos4_clk_pdma0 = {
+        .name           = "dma",
+        .devname        = "dma-pl330.0",
+        .enable         = exynos4_clk_ip_fsys_ctrl,
+        .ctrlbit        = (1 << 0),
+};
+
+static struct clk exynos4_clk_pdma1 = {
+        .name           = "dma",
+        .devname        = "dma-pl330.1",
+        .enable         = exynos4_clk_ip_fsys_ctrl,
+        .ctrlbit        = (1 << 1),
+};
+
+static struct clk exynos4_clk_mdma1 = {
+        .name           = "dma",
+        .devname        = "dma-pl330.2",
+        .enable         = exynos4_clk_ip_image_ctrl,
+        .ctrlbit        = ((1 << 8) | (1 << 5) | (1 << 2)),
+};
+
+struct clk *exynos4_clkset_group_list[] = {
+        [0] = &clk_ext_xtal_mux,
+        [1] = &clk_xusbxti,
+        [2] = &exynos4_clk_sclk_hdmi27m,
+        [3] = &exynos4_clk_sclk_usbphy0,
+        [4] = &exynos4_clk_sclk_usbphy1,
+        [5] = &exynos4_clk_sclk_hdmiphy,
+        [6] = &exynos4_clk_mout_mpll.clk,
+        [7] = &exynos4_clk_mout_epll.clk,
+        [8] = &exynos4_clk_sclk_vpll.clk,
+};
+
+struct clksrc_sources exynos4_clkset_group = {
+        .sources        = exynos4_clkset_group_list,
+        .nr_sources     = ARRAY_SIZE(exynos4_clkset_group_list),
+};
+
+static struct clk *exynos4_clkset_mout_g2d0_list[] = {
+        [0] = &exynos4_clk_mout_mpll.clk,
+        [1] = &exynos4_clk_sclk_apll.clk,
+};
+
+static struct clksrc_sources exynos4_clkset_mout_g2d0 = {
+        .sources        = exynos4_clkset_mout_g2d0_list,
+        .nr_sources     = ARRAY_SIZE(exynos4_clkset_mout_g2d0_list),
+};
+
+static struct clksrc_clk exynos4_clk_mout_g2d0 = {
+        .clk    = {
+                .name           = "mout_g2d0",
+        },
+        .sources = &exynos4_clkset_mout_g2d0,
+        .reg_src = { .reg = EXYNOS4_CLKSRC_IMAGE, .shift = 0, .size = 1 },
+};
+
+static struct clk *exynos4_clkset_mout_g2d1_list[] = {
+        [0] = &exynos4_clk_mout_epll.clk,
+        [1] = &exynos4_clk_sclk_vpll.clk,
+};
+
+static struct clksrc_sources exynos4_clkset_mout_g2d1 = {
+        .sources        = exynos4_clkset_mout_g2d1_list,
+        .nr_sources     = ARRAY_SIZE(exynos4_clkset_mout_g2d1_list),
+};
+
+static struct clksrc_clk exynos4_clk_mout_g2d1 = {
+        .clk    = {
+                .name           = "mout_g2d1",
+        },
+        .sources = &exynos4_clkset_mout_g2d1,
+        .reg_src = { .reg = EXYNOS4_CLKSRC_IMAGE, .shift = 4, .size = 1 },
+};
+
+static struct clk *exynos4_clkset_mout_g2d_list[] = {
+        [0] = &exynos4_clk_mout_g2d0.clk,
+        [1] = &exynos4_clk_mout_g2d1.clk,
+};
+
+static struct clksrc_sources exynos4_clkset_mout_g2d = {
+        .sources        = exynos4_clkset_mout_g2d_list,
+        .nr_sources     = ARRAY_SIZE(exynos4_clkset_mout_g2d_list),
+};
+
+static struct clk *exynos4_clkset_mout_mfc0_list[] = {
+        [0] = &exynos4_clk_mout_mpll.clk,
+        [1] = &exynos4_clk_sclk_apll.clk,
+};
+
+static struct clksrc_sources exynos4_clkset_mout_mfc0 = {
+        .sources        = exynos4_clkset_mout_mfc0_list,
+        .nr_sources     = ARRAY_SIZE(exynos4_clkset_mout_mfc0_list),
+};
+
+static struct clksrc_clk exynos4_clk_mout_mfc0 = {
+        .clk    = {
+                .name           = "mout_mfc0",
+        },
+        .sources = &exynos4_clkset_mout_mfc0,
+        .reg_src = { .reg = EXYNOS4_CLKSRC_MFC, .shift = 0, .size = 1 },
+};
+
+static struct clk *exynos4_clkset_mout_mfc1_list[] = {
+        [0] = &exynos4_clk_mout_epll.clk,
+        [1] = &exynos4_clk_sclk_vpll.clk,
+};
+
+static struct clksrc_sources exynos4_clkset_mout_mfc1 = {
+        .sources        = exynos4_clkset_mout_mfc1_list,
+        .nr_sources     = ARRAY_SIZE(exynos4_clkset_mout_mfc1_list),
+};
+
+static struct clksrc_clk exynos4_clk_mout_mfc1 = {
+        .clk    = {
+                .name           = "mout_mfc1",
+        },
+        .sources = &exynos4_clkset_mout_mfc1,
+        .reg_src = { .reg = EXYNOS4_CLKSRC_MFC, .shift = 4, .size = 1 },
+};
+
+static struct clk *exynos4_clkset_mout_mfc_list[] = {
+        [0] = &exynos4_clk_mout_mfc0.clk,
+        [1] = &exynos4_clk_mout_mfc1.clk,
+};
+
+static struct clksrc_sources exynos4_clkset_mout_mfc = {
+        .sources        = exynos4_clkset_mout_mfc_list,
+        .nr_sources     = ARRAY_SIZE(exynos4_clkset_mout_mfc_list),
+};
+
+static struct clk *exynos4_clkset_sclk_dac_list[] = {
+        [0] = &exynos4_clk_sclk_vpll.clk,
+        [1] = &exynos4_clk_sclk_hdmiphy,
+};
+
+static struct clksrc_sources exynos4_clkset_sclk_dac = {
+        .sources        = exynos4_clkset_sclk_dac_list,
+        .nr_sources     = ARRAY_SIZE(exynos4_clkset_sclk_dac_list),
+};
+
+static struct clksrc_clk exynos4_clk_sclk_dac = {
+        .clk            = {
+                .name           = "sclk_dac",
+                .enable         = exynos4_clksrc_mask_tv_ctrl,
+                .ctrlbit        = (1 << 8),
+        },
+        .sources = &exynos4_clkset_sclk_dac,
+        .reg_src = { .reg = EXYNOS4_CLKSRC_TV, .shift = 8, .size = 1 },
+};
+
+static struct clksrc_clk exynos4_clk_sclk_pixel = {
+        .clk            = {
+                .name           = "sclk_pixel",
+                .parent         = &exynos4_clk_sclk_vpll.clk,
+        },
+        .reg_div = { .reg = EXYNOS4_CLKDIV_TV, .shift = 0, .size = 4 },
+};
+
+static struct clk *exynos4_clkset_sclk_hdmi_list[] = {
+        [0] = &exynos4_clk_sclk_pixel.clk,
+        [1] = &exynos4_clk_sclk_hdmiphy,
+};
+
+static struct clksrc_sources exynos4_clkset_sclk_hdmi = {
+        .sources        = exynos4_clkset_sclk_hdmi_list,
+        .nr_sources     = ARRAY_SIZE(exynos4_clkset_sclk_hdmi_list),
+};
+
+static struct clksrc_clk exynos4_clk_sclk_hdmi = {
+        .clk            = {
+                .name           = "sclk_hdmi",
+                .enable         = exynos4_clksrc_mask_tv_ctrl,
+                .ctrlbit        = (1 << 0),
+        },
+        .sources = &exynos4_clkset_sclk_hdmi,
+        .reg_src = { .reg = EXYNOS4_CLKSRC_TV, .shift = 0, .size = 1 },
+};
+
+static struct clk *exynos4_clkset_sclk_mixer_list[] = {
+        [0] = &exynos4_clk_sclk_dac.clk,
+        [1] = &exynos4_clk_sclk_hdmi.clk,
+};
+
+static struct clksrc_sources exynos4_clkset_sclk_mixer = {
+        .sources        = exynos4_clkset_sclk_mixer_list,
+        .nr_sources     = ARRAY_SIZE(exynos4_clkset_sclk_mixer_list),
+};
+
+static struct clksrc_clk exynos4_clk_sclk_mixer = {
+        .clk    = {
+                .name           = "sclk_mixer",
+                .enable         = exynos4_clksrc_mask_tv_ctrl,
+                .ctrlbit        = (1 << 4),
+        },
+        .sources = &exynos4_clkset_sclk_mixer,
+        .reg_src = { .reg = EXYNOS4_CLKSRC_TV, .shift = 4, .size = 1 },
+};
+
+static struct clksrc_clk *exynos4_sclk_tv[] = {
+        &exynos4_clk_sclk_dac,
+        &exynos4_clk_sclk_pixel,
+        &exynos4_clk_sclk_hdmi,
+        &exynos4_clk_sclk_mixer,
+};
+
+static struct clksrc_clk exynos4_clk_dout_mmc0 = {
+        .clk    = {
+                .name           = "dout_mmc0",
+        },
+        .sources = &exynos4_clkset_group,
+        .reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 0, .size = 4 },
+        .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS1, .shift = 0, .size = 4 },
+};
+
+static struct clksrc_clk exynos4_clk_dout_mmc1 = {
+        .clk    = {
+                .name           = "dout_mmc1",
+        },
+        .sources = &exynos4_clkset_group,
+        .reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 4, .size = 4 },
+        .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS1, .shift = 16, .size = 4 },
+};
+
+static struct clksrc_clk exynos4_clk_dout_mmc2 = {
+        .clk    = {
+                .name           = "dout_mmc2",
+        },
+        .sources = &exynos4_clkset_group,
+        .reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 8, .size = 4 },
+        .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS2, .shift = 0, .size = 4 },
+};
+
+static struct clksrc_clk exynos4_clk_dout_mmc3 = {
+        .clk    = {
+                .name           = "dout_mmc3",
+        },
+        .sources = &exynos4_clkset_group,
+        .reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 12, .size = 4 },
+        .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS2, .shift = 16, .size = 4 },
+};
+
+static struct clksrc_clk exynos4_clk_dout_mmc4 = {
+        .clk            = {
+                .name           = "dout_mmc4",
+        },
+        .sources = &exynos4_clkset_group,
+        .reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 16, .size = 4 },
+        .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS3, .shift = 0, .size = 4 },
+};
+
+static struct clksrc_clk exynos4_clksrcs[] = {
+        {
+                .clk    = {
+                        .name           = "sclk_pwm",
+                        .enable         = exynos4_clksrc_mask_peril0_ctrl,
+                        .ctrlbit        = (1 << 24),
+                },
+                .sources = &exynos4_clkset_group,
+                .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL0, .shift = 24, .size = 4 },
+                .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL3, .shift = 0, .size = 4 },
+        }, {
+                .clk    = {
+                        .name           = "sclk_csis",
+                        .devname        = "s5p-mipi-csis.0",
+                        .enable         = exynos4_clksrc_mask_cam_ctrl,
+                        .ctrlbit        = (1 << 24),
+                },
+                .sources = &exynos4_clkset_group,
+                .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 24, .size = 4 },
+                .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 24, .size = 4 },
+        }, {
+                .clk    = {
+                        .name           = "sclk_csis",
+                        .devname        = "s5p-mipi-csis.1",
+                        .enable         = exynos4_clksrc_mask_cam_ctrl,
+                        .ctrlbit        = (1 << 28),
+                },
+                .sources = &exynos4_clkset_group,
+                .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 28, .size = 4 },
+                .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 28, .size = 4 },
+        }, {
+                .clk    = {
+                        .name           = "sclk_cam0",
+                        .enable         = exynos4_clksrc_mask_cam_ctrl,
+                        .ctrlbit        = (1 << 16),
+                },
+                .sources = &exynos4_clkset_group,
+                .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 16, .size = 4 },
+                .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 16, .size = 4 },
+        }, {
+                .clk    = {
+                        .name           = "sclk_cam1",
+                        .enable         = exynos4_clksrc_mask_cam_ctrl,
+                        .ctrlbit        = (1 << 20),
+                },
+                .sources = &exynos4_clkset_group,
+                .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 20, .size = 4 },
+                .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 20, .size = 4 },
+        }, {
+                .clk    = {
+                        .name           = "sclk_fimc",
+                        .devname        = "exynos4-fimc.0",
+                        .enable         = exynos4_clksrc_mask_cam_ctrl,
+                        .ctrlbit        = (1 << 0),
+                },
+                .sources = &exynos4_clkset_group,
+                .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 0, .size = 4 },
+                .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 0, .size = 4 },
+        }, {
+                .clk    = {
+                        .name           = "sclk_fimc",
+                        .devname        = "exynos4-fimc.1",
+                        .enable         = exynos4_clksrc_mask_cam_ctrl,
+                        .ctrlbit        = (1 << 4),
+                },
+                .sources = &exynos4_clkset_group,
+                .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 4, .size = 4 },
+                .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 4, .size = 4 },
+        }, {
+                .clk    = {
+                        .name           = "sclk_fimc",
+                        .devname        = "exynos4-fimc.2",
+                        .enable         = exynos4_clksrc_mask_cam_ctrl,
+                        .ctrlbit        = (1 << 8),
+                },
+                .sources = &exynos4_clkset_group,
+                .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 8, .size = 4 },
+                .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 8, .size = 4 },
+        }, {
+                .clk    = {
+                        .name           = "sclk_fimc",
+                        .devname        = "exynos4-fimc.3",
+                        .enable         = exynos4_clksrc_mask_cam_ctrl,
+                        .ctrlbit        = (1 << 12),
+                },
+                .sources = &exynos4_clkset_group,
+                .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 12, .size = 4 },
+                .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 12, .size = 4 },
+        }, {
+                .clk    = {
+                        .name           = "sclk_fimd",
+                        .devname        = "exynos4-fb.0",
+                        .enable         = exynos4_clksrc_mask_lcd0_ctrl,
+                        .ctrlbit        = (1 << 0),
+                },
+                .sources = &exynos4_clkset_group,
+                .reg_src = { .reg = EXYNOS4_CLKSRC_LCD0, .shift = 0, .size = 4 },
+                .reg_div = { .reg = EXYNOS4_CLKDIV_LCD0, .shift = 0, .size = 4 },
+        }, {
+                .clk    = {
+                        .name           = "sclk_fimg2d",
+                },
+                .sources = &exynos4_clkset_mout_g2d,
+                .reg_src = { .reg = EXYNOS4_CLKSRC_IMAGE, .shift = 8, .size = 1 },
+                .reg_div = { .reg = EXYNOS4_CLKDIV_IMAGE, .shift = 0, .size = 4 },
+        }, {
+                .clk    = {
+                        .name           = "sclk_mfc",
+                        .devname        = "s5p-mfc",
+                },
+                .sources = &exynos4_clkset_mout_mfc,
+                .reg_src = { .reg = EXYNOS4_CLKSRC_MFC, .shift = 8, .size = 1 },
+                .reg_div = { .reg = EXYNOS4_CLKDIV_MFC, .shift = 0, .size = 4 },
+        }, {
+                .clk    = {
+                        .name           = "sclk_dwmmc",
+                        .parent         = &exynos4_clk_dout_mmc4.clk,
+                        .enable         = exynos4_clksrc_mask_fsys_ctrl,
+                        .ctrlbit        = (1 << 16),
+                },
+                .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS3, .shift = 8, .size = 8 },
+        }
+};
+
+static struct clksrc_clk exynos4_clk_sclk_uart0 = {
+        .clk    = {
+                .name           = "uclk1",
+                .devname        = "exynos4210-uart.0",
+                .enable         = exynos4_clksrc_mask_peril0_ctrl,
+                .ctrlbit        = (1 << 0),
+        },
+        .sources = &exynos4_clkset_group,
+        .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL0, .shift = 0, .size = 4 },
+        .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL0, .shift = 0, .size = 4 },
+};
+
+static struct clksrc_clk exynos4_clk_sclk_uart1 = {
+        .clk    = {
+                .name           = "uclk1",
+                .devname        = "exynos4210-uart.1",
+                .enable         = exynos4_clksrc_mask_peril0_ctrl,
+                .ctrlbit        = (1 << 4),
+        },
+        .sources = &exynos4_clkset_group,
+        .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL0, .shift = 4, .size = 4 },
+        .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL0, .shift = 4, .size = 4 },
+};
+
+static struct clksrc_clk exynos4_clk_sclk_uart2 = {
+        .clk    = {
+                .name           = "uclk1",
+                .devname        = "exynos4210-uart.2",
+                .enable         = exynos4_clksrc_mask_peril0_ctrl,
+                .ctrlbit        = (1 << 8),
+        },
+        .sources = &exynos4_clkset_group,
+        .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL0, .shift = 8, .size = 4 },
+        .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL0, .shift = 8, .size = 4 },
+};
+
+static struct clksrc_clk exynos4_clk_sclk_uart3 = {
+        .clk    = {
+                .name           = "uclk1",
+                .devname        = "exynos4210-uart.3",
+                .enable         = exynos4_clksrc_mask_peril0_ctrl,
+                .ctrlbit        = (1 << 12),
+        },
+        .sources = &exynos4_clkset_group,
+        .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL0, .shift = 12, .size = 4 },
+        .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL0, .shift = 12, .size = 4 },
+};
+
+static struct clksrc_clk exynos4_clk_sclk_mmc0 = {
+        .clk    = {
+                .name           = "sclk_mmc",
+                .devname        = "s3c-sdhci.0",
+                .parent         = &exynos4_clk_dout_mmc0.clk,
+                .enable         = exynos4_clksrc_mask_fsys_ctrl,
+                .ctrlbit        = (1 << 0),
+        },
+        .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS1, .shift = 8, .size = 8 },
+};
+
+static struct clksrc_clk exynos4_clk_sclk_mmc1 = {
+        .clk    = {
+                .name           = "sclk_mmc",
+                .devname        = "s3c-sdhci.1",
+                .parent         = &exynos4_clk_dout_mmc1.clk,
+                .enable         = exynos4_clksrc_mask_fsys_ctrl,
+                .ctrlbit        = (1 << 4),
+        },
+        .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS1, .shift = 24, .size = 8 },
+};
+
+static struct clksrc_clk exynos4_clk_sclk_mmc2 = {
+        .clk    = {
+                .name           = "sclk_mmc",
+                .devname        = "s3c-sdhci.2",
+                .parent         = &exynos4_clk_dout_mmc2.clk,
+                .enable         = exynos4_clksrc_mask_fsys_ctrl,
+                .ctrlbit        = (1 << 8),
+        },
+        .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS2, .shift = 8, .size = 8 },
+};
+
+static struct clksrc_clk exynos4_clk_sclk_mmc3 = {
+        .clk    = {
+                .name           = "sclk_mmc",
+                .devname        = "s3c-sdhci.3",
+                .parent         = &exynos4_clk_dout_mmc3.clk,
+                .enable         = exynos4_clksrc_mask_fsys_ctrl,
+                .ctrlbit        = (1 << 12),
+        },
+        .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS2, .shift = 24, .size = 8 },
+};
+
+static struct clksrc_clk exynos4_clk_sclk_spi0 = {
+        .clk    = {
+                .name           = "sclk_spi",
+                .devname        = "s3c64xx-spi.0",
+                .enable         = exynos4_clksrc_mask_peril1_ctrl,
+                .ctrlbit        = (1 << 16),
+        },
+        .sources = &exynos4_clkset_group,
+        .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 16, .size = 4 },
+        .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 0, .size = 4 },
+};
+
+static struct clksrc_clk exynos4_clk_sclk_spi1 = {
+        .clk    = {
+                .name           = "sclk_spi",
+                .devname        = "s3c64xx-spi.1",
+                .enable         = exynos4_clksrc_mask_peril1_ctrl,
+                .ctrlbit        = (1 << 20),
+        },
+        .sources = &exynos4_clkset_group,
+        .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 20, .size = 4 },
+        .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 16, .size = 4 },
+};
+
+static struct clksrc_clk exynos4_clk_sclk_spi2 = {
+        .clk    = {
+                .name           = "sclk_spi",
+                .devname        = "s3c64xx-spi.2",
+                .enable         = exynos4_clksrc_mask_peril1_ctrl,
+                .ctrlbit        = (1 << 24),
+        },
+        .sources = &exynos4_clkset_group,
+        .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 24, .size = 4 },
+        .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL2, .shift = 0, .size = 4 },
+};
+
+/* Clock initialization code */
+static struct clksrc_clk *exynos4_sysclks[] = {
+        &exynos4_clk_mout_apll,
+        &exynos4_clk_sclk_apll,
+        &exynos4_clk_mout_epll,
+        &exynos4_clk_mout_mpll,
+        &exynos4_clk_moutcore,
+        &exynos4_clk_coreclk,
+        &exynos4_clk_armclk,
+        &exynos4_clk_aclk_corem0,
+        &exynos4_clk_aclk_cores,
+        &exynos4_clk_aclk_corem1,
+        &exynos4_clk_periphclk,
+        &exynos4_clk_mout_corebus,
+        &exynos4_clk_sclk_dmc,
+        &exynos4_clk_aclk_cored,
+        &exynos4_clk_aclk_corep,
+        &exynos4_clk_aclk_acp,
+        &exynos4_clk_pclk_acp,
+        &exynos4_clk_vpllsrc,
+        &exynos4_clk_sclk_vpll,
+        &exynos4_clk_aclk_200,
+        &exynos4_clk_aclk_100,
+        &exynos4_clk_aclk_160,
+        &exynos4_clk_aclk_133,
+        &exynos4_clk_dout_mmc0,
+        &exynos4_clk_dout_mmc1,
+        &exynos4_clk_dout_mmc2,
+        &exynos4_clk_dout_mmc3,
+        &exynos4_clk_dout_mmc4,
+        &exynos4_clk_mout_mfc0,
+        &exynos4_clk_mout_mfc1,
+};
+
+static struct clk *exynos4_clk_cdev[] = {
+        &exynos4_clk_pdma0,
+        &exynos4_clk_pdma1,
+        &exynos4_clk_mdma1,
+};
+
+static struct clksrc_clk *exynos4_clksrc_cdev[] = {
+        &exynos4_clk_sclk_uart0,
+        &exynos4_clk_sclk_uart1,
+        &exynos4_clk_sclk_uart2,
+        &exynos4_clk_sclk_uart3,
+        &exynos4_clk_sclk_mmc0,
+        &exynos4_clk_sclk_mmc1,
+        &exynos4_clk_sclk_mmc2,
+        &exynos4_clk_sclk_mmc3,
+        &exynos4_clk_sclk_spi0,
+        &exynos4_clk_sclk_spi1,
+        &exynos4_clk_sclk_spi2,
+
+};
+
+static struct clk_lookup exynos4_clk_lookup[] = {
+        CLKDEV_INIT("exynos4210-uart.0", "clk_uart_baud0", &exynos4_clk_sclk_uart0.clk),
+        CLKDEV_INIT("exynos4210-uart.1", "clk_uart_baud0", &exynos4_clk_sclk_uart1.clk),
+        CLKDEV_INIT("exynos4210-uart.2", "clk_uart_baud0", &exynos4_clk_sclk_uart2.clk),
+        CLKDEV_INIT("exynos4210-uart.3", "clk_uart_baud0", &exynos4_clk_sclk_uart3.clk),
+        CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &exynos4_clk_sclk_mmc0.clk),
+        CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &exynos4_clk_sclk_mmc1.clk),
+        CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &exynos4_clk_sclk_mmc2.clk),
+        CLKDEV_INIT("s3c-sdhci.3", "mmc_busclk.2", &exynos4_clk_sclk_mmc3.clk),
+        CLKDEV_INIT("dma-pl330.0", "apb_pclk", &exynos4_clk_pdma0),
+        CLKDEV_INIT("dma-pl330.1", "apb_pclk", &exynos4_clk_pdma1),
+        CLKDEV_INIT("dma-pl330.2", "apb_pclk", &exynos4_clk_mdma1),
+        CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk0", &exynos4_clk_sclk_spi0.clk),
+        CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk0", &exynos4_clk_sclk_spi1.clk),
+        CLKDEV_INIT("s3c64xx-spi.2", "spi_busclk0", &exynos4_clk_sclk_spi2.clk),
+};
+
+static int xtal_rate;
+
+static unsigned long exynos4_fout_apll_get_rate(struct clk *clk)
+{
+        if (soc_is_exynos4210())
+                return s5p_get_pll45xx(xtal_rate, __raw_readl(EXYNOS4_APLL_CON0),
+                                        pll_4508);
+        else if (soc_is_exynos4212() || soc_is_exynos4412())
+                return s5p_get_pll35xx(xtal_rate, __raw_readl(EXYNOS4_APLL_CON0));
+        else
+                return 0;
+}
+
+static struct clk_ops exynos4_fout_apll_ops = {
+        .get_rate = exynos4_fout_apll_get_rate,
+};
+
+static u32 exynos4_vpll_div[][8] = {
+        {  54000000, 3, 53, 3, 1024, 0, 17, 0 },
+        { 108000000, 3, 53, 2, 1024, 0, 17, 0 },
+};
+
+static unsigned long exynos4_vpll_get_rate(struct clk *clk)
+{
+        return clk->rate;
+}
+
+static int exynos4_vpll_set_rate(struct clk *clk, unsigned long rate)
+{
+        unsigned int vpll_con0, vpll_con1 = 0;
+        unsigned int i;
+
+        /* Return if nothing changed */
+        if (clk->rate == rate)
+                return 0;
+
+        vpll_con0 = __raw_readl(EXYNOS4_VPLL_CON0);
+        vpll_con0 &= ~(0x1 << 27 |                                      \
+                        PLL90XX_MDIV_MASK << PLL46XX_MDIV_SHIFT |       \
+                        PLL90XX_PDIV_MASK << PLL46XX_PDIV_SHIFT |       \
+                        PLL90XX_SDIV_MASK << PLL46XX_SDIV_SHIFT);
+
+        vpll_con1 = __raw_readl(EXYNOS4_VPLL_CON1);
+        vpll_con1 &= ~(PLL46XX_MRR_MASK << PLL46XX_MRR_SHIFT |  \
+                        PLL46XX_MFR_MASK << PLL46XX_MFR_SHIFT | \
+                        PLL4650C_KDIV_MASK << PLL46XX_KDIV_SHIFT);
+
+        for (i = 0; i < ARRAY_SIZE(exynos4_vpll_div); i++) {
+                if (exynos4_vpll_div[i][0] == rate) {
+                        vpll_con0 |= exynos4_vpll_div[i][1] << PLL46XX_PDIV_SHIFT;
+                        vpll_con0 |= exynos4_vpll_div[i][2] << PLL46XX_MDIV_SHIFT;
+                        vpll_con0 |= exynos4_vpll_div[i][3] << PLL46XX_SDIV_SHIFT;
+                        vpll_con1 |= exynos4_vpll_div[i][4] << PLL46XX_KDIV_SHIFT;
+                        vpll_con1 |= exynos4_vpll_div[i][5] << PLL46XX_MFR_SHIFT;
+                        vpll_con1 |= exynos4_vpll_div[i][6] << PLL46XX_MRR_SHIFT;
+                        vpll_con0 |= exynos4_vpll_div[i][7] << 27;
+                        break;
+                }
+        }
+
+        if (i == ARRAY_SIZE(exynos4_vpll_div)) {
+                printk(KERN_ERR "%s: Invalid Clock VPLL Frequency\n",
+                                __func__);
+                return -EINVAL;
+        }
+
+        __raw_writel(vpll_con0, EXYNOS4_VPLL_CON0);
+        __raw_writel(vpll_con1, EXYNOS4_VPLL_CON1);
+
+        /* Wait for VPLL lock */
+        while (!(__raw_readl(EXYNOS4_VPLL_CON0) & (1 << PLL46XX_LOCKED_SHIFT)))
+                continue;
+
+        clk->rate = rate;
+        return 0;
+}
+
+static struct clk_ops exynos4_vpll_ops = {
+        .get_rate = exynos4_vpll_get_rate,
+        .set_rate = exynos4_vpll_set_rate,
+};
+
+void __init_or_cpufreq exynos4_setup_clocks(void)
+{
+        struct clk *xtal_clk;
+        unsigned long apll = 0;
+        unsigned long mpll = 0;
+        unsigned long epll = 0;
+        unsigned long vpll = 0;
+        unsigned long vpllsrc;
+        unsigned long xtal;
+        unsigned long armclk;
+        unsigned long sclk_dmc;
+        unsigned long aclk_200;
+        unsigned long aclk_100;
+        unsigned long aclk_160;
+        unsigned long aclk_133;
+        unsigned int ptr;
+
+        printk(KERN_DEBUG "%s: registering clocks\n", __func__);
+
+        xtal_clk = clk_get(NULL, "xtal");
+        BUG_ON(IS_ERR(xtal_clk));
+
+        xtal = clk_get_rate(xtal_clk);
+
+        xtal_rate = xtal;
+
+        clk_put(xtal_clk);
+
+        printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
+
+        if (soc_is_exynos4210()) {
+                apll = s5p_get_pll45xx(xtal, __raw_readl(EXYNOS4_APLL_CON0),
+                                        pll_4508);
+                mpll = s5p_get_pll45xx(xtal, __raw_readl(EXYNOS4_MPLL_CON0),
+                                        pll_4508);
+                epll = s5p_get_pll46xx(xtal, __raw_readl(EXYNOS4_EPLL_CON0),
+                                        __raw_readl(EXYNOS4_EPLL_CON1), pll_4600);
+
+                vpllsrc = clk_get_rate(&exynos4_clk_vpllsrc.clk);
+                vpll = s5p_get_pll46xx(vpllsrc, __raw_readl(EXYNOS4_VPLL_CON0),
+                                        __raw_readl(EXYNOS4_VPLL_CON1), pll_4650c);
+        } else if (soc_is_exynos4212() || soc_is_exynos4412()) {
+                apll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS4_APLL_CON0));
+                mpll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS4_MPLL_CON0));
+                epll = s5p_get_pll36xx(xtal, __raw_readl(EXYNOS4_EPLL_CON0),
+                                        __raw_readl(EXYNOS4_EPLL_CON1));
+
+                vpllsrc = clk_get_rate(&exynos4_clk_vpllsrc.clk);
+                vpll = s5p_get_pll36xx(vpllsrc, __raw_readl(EXYNOS4_VPLL_CON0),
+                                        __raw_readl(EXYNOS4_VPLL_CON1));
+        } else {
+                /* nothing */
+        }
+
+        clk_fout_apll.ops = &exynos4_fout_apll_ops;
+        clk_fout_mpll.rate = mpll;
+        clk_fout_epll.rate = epll;
+        clk_fout_vpll.ops = &exynos4_vpll_ops;
+        clk_fout_vpll.rate = vpll;
+
+        printk(KERN_INFO "EXYNOS4: PLL settings, A=%ld, M=%ld, E=%ld V=%ld",
+                        apll, mpll, epll, vpll);
+
+        armclk = clk_get_rate(&exynos4_clk_armclk.clk);
+        sclk_dmc = clk_get_rate(&exynos4_clk_sclk_dmc.clk);
+
+        aclk_200 = clk_get_rate(&exynos4_clk_aclk_200.clk);
+        aclk_100 = clk_get_rate(&exynos4_clk_aclk_100.clk);
+        aclk_160 = clk_get_rate(&exynos4_clk_aclk_160.clk);
+        aclk_133 = clk_get_rate(&exynos4_clk_aclk_133.clk);
+
+        printk(KERN_INFO "EXYNOS4: ARMCLK=%ld, DMC=%ld, ACLK200=%ld\n"
+                         "ACLK100=%ld, ACLK160=%ld, ACLK133=%ld\n",
+                        armclk, sclk_dmc, aclk_200,
+                        aclk_100, aclk_160, aclk_133);
+
+        clk_f.rate = armclk;
+        clk_h.rate = sclk_dmc;
+        clk_p.rate = aclk_100;
+
+        for (ptr = 0; ptr < ARRAY_SIZE(exynos4_clksrcs); ptr++)
+                s3c_set_clksrc(&exynos4_clksrcs[ptr], true);
+}
+
+static struct clk *exynos4_clks[] __initdata = {
+        &exynos4_clk_sclk_hdmi27m,
+        &exynos4_clk_sclk_hdmiphy,
+        &exynos4_clk_sclk_usbphy0,
+        &exynos4_clk_sclk_usbphy1,
+};
+
+#ifdef CONFIG_PM_SLEEP
+static int exynos4_clock_suspend(void)
+{
+        s3c_pm_do_save(exynos4_clock_save, ARRAY_SIZE(exynos4_clock_save));
+        return 0;
+}
+
+static void exynos4_clock_resume(void)
+{
+        s3c_pm_do_restore_core(exynos4_clock_save, ARRAY_SIZE(exynos4_clock_save));
+}
+
+#else
+#define exynos4_clock_suspend NULL
+#define exynos4_clock_resume NULL
+#endif
+
+static struct syscore_ops exynos4_clock_syscore_ops = {
+        .suspend        = exynos4_clock_suspend,
+        .resume         = exynos4_clock_resume,
+};
+
+void __init exynos4_register_clocks(void)
+{
+        int ptr;
+
+        s3c24xx_register_clocks(exynos4_clks, ARRAY_SIZE(exynos4_clks));
+
+        for (ptr = 0; ptr < ARRAY_SIZE(exynos4_sysclks); ptr++)
+                s3c_register_clksrc(exynos4_sysclks[ptr], 1);
+
+        for (ptr = 0; ptr < ARRAY_SIZE(exynos4_sclk_tv); ptr++)
+                s3c_register_clksrc(exynos4_sclk_tv[ptr], 1);
+
+        for (ptr = 0; ptr < ARRAY_SIZE(exynos4_clksrc_cdev); ptr++)
+                s3c_register_clksrc(exynos4_clksrc_cdev[ptr], 1);
+
+        s3c_register_clksrc(exynos4_clksrcs, ARRAY_SIZE(exynos4_clksrcs));
+        s3c_register_clocks(exynos4_init_clocks_on, ARRAY_SIZE(exynos4_init_clocks_on));
+
+        s3c24xx_register_clocks(exynos4_clk_cdev, ARRAY_SIZE(exynos4_clk_cdev));
+        for (ptr = 0; ptr < ARRAY_SIZE(exynos4_clk_cdev); ptr++)
+                s3c_disable_clocks(exynos4_clk_cdev[ptr], 1);
+
+        s3c_register_clocks(exynos4_init_clocks_off, ARRAY_SIZE(exynos4_init_clocks_off));
+        s3c_disable_clocks(exynos4_init_clocks_off, ARRAY_SIZE(exynos4_init_clocks_off));
+        clkdev_add_table(exynos4_clk_lookup, ARRAY_SIZE(exynos4_clk_lookup));
+
+        register_syscore_ops(&exynos4_clock_syscore_ops);
+        s3c24xx_register_clock(&dummy_apb_pclk);
+
+        s3c_pwmclk_init();
+}
diff --git a/arch/arm/mach-exynos/clock-exynos4.h b/arch/arm/mach-exynos/clock-exynos4.h
new file mode 100644
index 00000000000..cb71c29c14d
--- /dev/null
+++ b/arch/arm/mach-exynos/clock-exynos4.h
@@ -0,0 +1,30 @@
+/*
+ * Copyright (c) 2011-2012 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * Header file for exynos4 clock support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_CLOCK_H
+#define __ASM_ARCH_CLOCK_H __FILE__
+
+#include <linux/clk.h>
+
+extern struct clksrc_clk exynos4_clk_aclk_133;
+extern struct clksrc_clk exynos4_clk_mout_mpll;
+
+extern struct clksrc_sources exynos4_clkset_mout_corebus;
+extern struct clksrc_sources exynos4_clkset_group;
+
+extern struct clk *exynos4_clkset_aclk_top_list[];
+extern struct clk *exynos4_clkset_group_list[];
+
+extern int exynos4_clksrc_mask_fsys_ctrl(struct clk *clk, int enable);
+extern int exynos4_clk_ip_fsys_ctrl(struct clk *clk, int enable);
+extern int exynos4_clk_ip_lcd1_ctrl(struct clk *clk, int enable);
+
+#endif /* __ASM_ARCH_CLOCK_H */
diff --git a/arch/arm/mach-exynos/clock-exynos4210.c b/arch/arm/mach-exynos/clock-exynos4210.c
index 13312ccb2d9..3b131e4b6ef 100644
--- a/arch/arm/mach-exynos/clock-exynos4210.c
+++ b/arch/arm/mach-exynos/clock-exynos4210.c
@@ -1,7 +1,5 @@
 /*
- * linux/arch/arm/mach-exynos4/clock-exynos4210.c
- *
- * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ * Copyright (c) 2011-2012 Samsung Electronics Co., Ltd.
  *              http://www.samsung.com
  *
  * EXYNOS4210 - Clock support
@@ -28,20 +26,20 @@
 #include <mach/hardware.h>
 #include <mach/map.h>
 #include <mach/regs-clock.h>
-#include <mach/exynos4-clock.h>
 
 #include "common.h"
+#include "clock-exynos4.h"
 
 #ifdef CONFIG_PM_SLEEP
 static struct sleep_save exynos4210_clock_save[] = {
-        SAVE_ITEM(S5P_CLKSRC_IMAGE),
-        SAVE_ITEM(S5P_CLKSRC_LCD1),
-        SAVE_ITEM(S5P_CLKDIV_IMAGE),
-        SAVE_ITEM(S5P_CLKDIV_LCD1),
-        SAVE_ITEM(S5P_CLKSRC_MASK_LCD1),
-        SAVE_ITEM(S5P_CLKGATE_IP_IMAGE_4210),
-        SAVE_ITEM(S5P_CLKGATE_IP_LCD1),
-        SAVE_ITEM(S5P_CLKGATE_IP_PERIR_4210),
+        SAVE_ITEM(EXYNOS4_CLKSRC_IMAGE),
+        SAVE_ITEM(EXYNOS4_CLKDIV_IMAGE),
+        SAVE_ITEM(EXYNOS4210_CLKSRC_LCD1),
+        SAVE_ITEM(EXYNOS4210_CLKDIV_LCD1),
+        SAVE_ITEM(EXYNOS4210_CLKSRC_MASK_LCD1),
+        SAVE_ITEM(EXYNOS4210_CLKGATE_IP_IMAGE),
+        SAVE_ITEM(EXYNOS4210_CLKGATE_IP_LCD1),
+        SAVE_ITEM(EXYNOS4210_CLKGATE_IP_PERIR),
 };
 #endif
 
@@ -51,7 +49,7 @@ static struct clksrc_clk *sysclks[] = {
 
 static int exynos4_clksrc_mask_lcd1_ctrl(struct clk *clk, int enable)
 {
-        return s5p_gatectrl(S5P_CLKSRC_MASK_LCD1, clk, enable);
+        return s5p_gatectrl(EXYNOS4210_CLKSRC_MASK_LCD1, clk, enable);
 }
 
 static struct clksrc_clk clksrcs[] = {
@@ -62,9 +60,9 @@ static struct clksrc_clk clksrcs[] = {
                         .enable         = exynos4_clksrc_mask_fsys_ctrl,
                         .ctrlbit        = (1 << 24),
                 },
-                .sources = &clkset_mout_corebus,
-                .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 24, .size = 1 },
-                .reg_div = { .reg = S5P_CLKDIV_FSYS0, .shift = 20, .size = 4 },
+                .sources = &exynos4_clkset_mout_corebus,
+                .reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 24, .size = 1 },
+                .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS0, .shift = 20, .size = 4 },
         }, {
                 .clk            = {
                         .name           = "sclk_fimd",
@@ -72,9 +70,9 @@ static struct clksrc_clk clksrcs[] = {
                         .enable         = exynos4_clksrc_mask_lcd1_ctrl,
                         .ctrlbit        = (1 << 0),
                 },
-                .sources = &clkset_group,
-                .reg_src = { .reg = S5P_CLKSRC_LCD1, .shift = 0, .size = 4 },
-                .reg_div = { .reg = S5P_CLKDIV_LCD1, .shift = 0, .size = 4 },
+                .sources = &exynos4_clkset_group,
+                .reg_src = { .reg = EXYNOS4210_CLKSRC_LCD1, .shift = 0, .size = 4 },
+                .reg_div = { .reg = EXYNOS4210_CLKDIV_LCD1, .shift = 0, .size = 4 },
         },
 };
 
@@ -82,13 +80,13 @@ static struct clk init_clocks_off[] = {
         {
                 .name           = "sataphy",
                 .id             = -1,
-                .parent         = &clk_aclk_133.clk,
+                .parent         = &exynos4_clk_aclk_133.clk,
                 .enable         = exynos4_clk_ip_fsys_ctrl,
                 .ctrlbit        = (1 << 3),
         }, {
                 .name           = "sata",
                 .id             = -1,
-                .parent         = &clk_aclk_133.clk,
+                .parent         = &exynos4_clk_aclk_133.clk,
                 .enable         = exynos4_clk_ip_fsys_ctrl,
                 .ctrlbit        = (1 << 10),
         }, {
@@ -117,7 +115,7 @@ static void exynos4210_clock_resume(void)
 #define exynos4210_clock_resume NULL
 #endif
 
-struct syscore_ops exynos4210_clock_syscore_ops = {
+static struct syscore_ops exynos4210_clock_syscore_ops = {
         .suspend        = exynos4210_clock_suspend,
         .resume         = exynos4210_clock_resume,
 };
@@ -126,9 +124,9 @@ void __init exynos4210_register_clocks(void)
 {
         int ptr;
 
-        clk_mout_mpll.reg_src.reg = S5P_CLKSRC_CPU;
-        clk_mout_mpll.reg_src.shift = 8;
-        clk_mout_mpll.reg_src.size = 1;
+        exynos4_clk_mout_mpll.reg_src.reg = EXYNOS4_CLKSRC_CPU;
+        exynos4_clk_mout_mpll.reg_src.shift = 8;
+        exynos4_clk_mout_mpll.reg_src.size = 1;
 
         for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
                 s3c_register_clksrc(sysclks[ptr], 1);
diff --git a/arch/arm/mach-exynos/clock-exynos4212.c b/arch/arm/mach-exynos/clock-exynos4212.c
index 48af28566fa..3ecc01e06f7 100644
--- a/arch/arm/mach-exynos/clock-exynos4212.c
+++ b/arch/arm/mach-exynos/clock-exynos4212.c
@@ -1,7 +1,5 @@
 /*
- * linux/arch/arm/mach-exynos4/clock-exynos4212.c
- *
- * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ * Copyright (c) 2011-2012 Samsung Electronics Co., Ltd.
  *              http://www.samsung.com
  *
  * EXYNOS4212 - Clock support
@@ -28,22 +26,22 @@
 #include <mach/hardware.h>
 #include <mach/map.h>
 #include <mach/regs-clock.h>
-#include <mach/exynos4-clock.h>
 
 #include "common.h"
+#include "clock-exynos4.h"
 
 #ifdef CONFIG_PM_SLEEP
 static struct sleep_save exynos4212_clock_save[] = {
-        SAVE_ITEM(S5P_CLKSRC_IMAGE),
-        SAVE_ITEM(S5P_CLKDIV_IMAGE),
-        SAVE_ITEM(S5P_CLKGATE_IP_IMAGE_4212),
-        SAVE_ITEM(S5P_CLKGATE_IP_PERIR_4212),
+        SAVE_ITEM(EXYNOS4_CLKSRC_IMAGE),
+        SAVE_ITEM(EXYNOS4_CLKDIV_IMAGE),
+        SAVE_ITEM(EXYNOS4212_CLKGATE_IP_IMAGE),
+        SAVE_ITEM(EXYNOS4212_CLKGATE_IP_PERIR),
 };
 #endif
 
 static struct clk *clk_src_mpll_user_list[] = {
         [0] = &clk_fin_mpll,
-        [1] = &clk_mout_mpll.clk,
+        [1] = &exynos4_clk_mout_mpll.clk,
 };
 
 static struct clksrc_sources clk_src_mpll_user = {
@@ -56,7 +54,7 @@ static struct clksrc_clk clk_mout_mpll_user = {
                 .name           = "mout_mpll_user",
         },
         .sources        = &clk_src_mpll_user,
-        .reg_src        = { .reg = S5P_CLKSRC_CPU, .shift = 24, .size = 1 },
+        .reg_src        = { .reg = EXYNOS4_CLKSRC_CPU, .shift = 24, .size = 1 },
 };
 
 static struct clksrc_clk *sysclks[] = {
@@ -89,7 +87,7 @@ static void exynos4212_clock_resume(void)
 #define exynos4212_clock_resume NULL
 #endif
 
-struct syscore_ops exynos4212_clock_syscore_ops = {
+static struct syscore_ops exynos4212_clock_syscore_ops = {
         .suspend        = exynos4212_clock_suspend,
         .resume         = exynos4212_clock_resume,
 };
@@ -99,15 +97,15 @@ void __init exynos4212_register_clocks(void)
         int ptr;
 
         /* usbphy1 is removed */
-        clkset_group_list[4] = NULL;
+        exynos4_clkset_group_list[4] = NULL;
 
         /* mout_mpll_user is used */
-        clkset_group_list[6] = &clk_mout_mpll_user.clk;
-        clkset_aclk_top_list[0] = &clk_mout_mpll_user.clk;
+        exynos4_clkset_group_list[6] = &clk_mout_mpll_user.clk;
+        exynos4_clkset_aclk_top_list[0] = &clk_mout_mpll_user.clk;
 
-        clk_mout_mpll.reg_src.reg = S5P_CLKSRC_DMC;
-        clk_mout_mpll.reg_src.shift = 12;
-        clk_mout_mpll.reg_src.size = 1;
+        exynos4_clk_mout_mpll.reg_src.reg = EXYNOS4_CLKSRC_DMC;
+        exynos4_clk_mout_mpll.reg_src.shift = 12;
+        exynos4_clk_mout_mpll.reg_src.size = 1;
 
         for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
                 s3c_register_clksrc(sysclks[ptr], 1);
diff --git a/arch/arm/mach-exynos/clock.c b/arch/arm/mach-exynos/clock.c
deleted file mode 100644
index 187287aa57a..00000000000
--- a/arch/arm/mach-exynos/clock.c
+++ /dev/null
@@ -1,1564 +0,0 @@
-/* linux/arch/arm/mach-exynos4/clock.c
- *
- * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com
- *
- * EXYNOS4 - Clock support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#include <linux/kernel.h>
-#include <linux/err.h>
-#include <linux/io.h>
-#include <linux/syscore_ops.h>
-
-#include <plat/cpu-freq.h>
-#include <plat/clock.h>
-#include <plat/cpu.h>
-#include <plat/pll.h>
-#include <plat/s5p-clock.h>
-#include <plat/clock-clksrc.h>
-#include <plat/pm.h>
-
-#include <mach/map.h>
-#include <mach/regs-clock.h>
-#include <mach/sysmmu.h>
-#include <mach/exynos4-clock.h>
-
-#include "common.h"
-
-#ifdef CONFIG_PM_SLEEP
-static struct sleep_save exynos4_clock_save[] = {
-        SAVE_ITEM(S5P_CLKDIV_LEFTBUS),
-        SAVE_ITEM(S5P_CLKGATE_IP_LEFTBUS),
-        SAVE_ITEM(S5P_CLKDIV_RIGHTBUS),
-        SAVE_ITEM(S5P_CLKGATE_IP_RIGHTBUS),
-        SAVE_ITEM(S5P_CLKSRC_TOP0),
-        SAVE_ITEM(S5P_CLKSRC_TOP1),
-        SAVE_ITEM(S5P_CLKSRC_CAM),
-        SAVE_ITEM(S5P_CLKSRC_TV),
-        SAVE_ITEM(S5P_CLKSRC_MFC),
-        SAVE_ITEM(S5P_CLKSRC_G3D),
-        SAVE_ITEM(S5P_CLKSRC_LCD0),
-        SAVE_ITEM(S5P_CLKSRC_MAUDIO),
-        SAVE_ITEM(S5P_CLKSRC_FSYS),
-        SAVE_ITEM(S5P_CLKSRC_PERIL0),
-        SAVE_ITEM(S5P_CLKSRC_PERIL1),
-        SAVE_ITEM(S5P_CLKDIV_CAM),
-        SAVE_ITEM(S5P_CLKDIV_TV),
-        SAVE_ITEM(S5P_CLKDIV_MFC),
-        SAVE_ITEM(S5P_CLKDIV_G3D),
-        SAVE_ITEM(S5P_CLKDIV_LCD0),
-        SAVE_ITEM(S5P_CLKDIV_MAUDIO),
-        SAVE_ITEM(S5P_CLKDIV_FSYS0),
-        SAVE_ITEM(S5P_CLKDIV_FSYS1),
-        SAVE_ITEM(S5P_CLKDIV_FSYS2),
-        SAVE_ITEM(S5P_CLKDIV_FSYS3),
-        SAVE_ITEM(S5P_CLKDIV_PERIL0),
-        SAVE_ITEM(S5P_CLKDIV_PERIL1),
-        SAVE_ITEM(S5P_CLKDIV_PERIL2),
-        SAVE_ITEM(S5P_CLKDIV_PERIL3),
-        SAVE_ITEM(S5P_CLKDIV_PERIL4),
-        SAVE_ITEM(S5P_CLKDIV_PERIL5),
-        SAVE_ITEM(S5P_CLKDIV_TOP),
-        SAVE_ITEM(S5P_CLKSRC_MASK_TOP),
-        SAVE_ITEM(S5P_CLKSRC_MASK_CAM),
-        SAVE_ITEM(S5P_CLKSRC_MASK_TV),
-        SAVE_ITEM(S5P_CLKSRC_MASK_LCD0),
-        SAVE_ITEM(S5P_CLKSRC_MASK_MAUDIO),
-        SAVE_ITEM(S5P_CLKSRC_MASK_FSYS),
-        SAVE_ITEM(S5P_CLKSRC_MASK_PERIL0),
-        SAVE_ITEM(S5P_CLKSRC_MASK_PERIL1),
-        SAVE_ITEM(S5P_CLKDIV2_RATIO),
-        SAVE_ITEM(S5P_CLKGATE_SCLKCAM),
-        SAVE_ITEM(S5P_CLKGATE_IP_CAM),
-        SAVE_ITEM(S5P_CLKGATE_IP_TV),
-        SAVE_ITEM(S5P_CLKGATE_IP_MFC),
-        SAVE_ITEM(S5P_CLKGATE_IP_G3D),
-        SAVE_ITEM(S5P_CLKGATE_IP_LCD0),
-        SAVE_ITEM(S5P_CLKGATE_IP_FSYS),
-        SAVE_ITEM(S5P_CLKGATE_IP_GPS),
-        SAVE_ITEM(S5P_CLKGATE_IP_PERIL),
-        SAVE_ITEM(S5P_CLKGATE_BLOCK),
-        SAVE_ITEM(S5P_CLKSRC_MASK_DMC),
-        SAVE_ITEM(S5P_CLKSRC_DMC),
-        SAVE_ITEM(S5P_CLKDIV_DMC0),
-        SAVE_ITEM(S5P_CLKDIV_DMC1),
-        SAVE_ITEM(S5P_CLKGATE_IP_DMC),
-        SAVE_ITEM(S5P_CLKSRC_CPU),
-        SAVE_ITEM(S5P_CLKDIV_CPU),
-        SAVE_ITEM(S5P_CLKDIV_CPU + 0x4),
-        SAVE_ITEM(S5P_CLKGATE_SCLKCPU),
-        SAVE_ITEM(S5P_CLKGATE_IP_CPU),
-};
-#endif
-
-struct clk clk_sclk_hdmi27m = {
-        .name           = "sclk_hdmi27m",
-        .rate           = 27000000,
-};
-
-struct clk clk_sclk_hdmiphy = {
-        .name           = "sclk_hdmiphy",
-};
-
-struct clk clk_sclk_usbphy0 = {
-        .name           = "sclk_usbphy0",
-        .rate           = 27000000,
-};
-
-struct clk clk_sclk_usbphy1 = {
-        .name           = "sclk_usbphy1",
-};
-
-static struct clk dummy_apb_pclk = {
-        .name           = "apb_pclk",
-        .id             = -1,
-};
-
-static int exynos4_clksrc_mask_top_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(S5P_CLKSRC_MASK_TOP, clk, enable);
-}
-
-static int exynos4_clksrc_mask_cam_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(S5P_CLKSRC_MASK_CAM, clk, enable);
-}
-
-static int exynos4_clksrc_mask_lcd0_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(S5P_CLKSRC_MASK_LCD0, clk, enable);
-}
-
-int exynos4_clksrc_mask_fsys_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(S5P_CLKSRC_MASK_FSYS, clk, enable);
-}
-
-static int exynos4_clksrc_mask_peril0_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(S5P_CLKSRC_MASK_PERIL0, clk, enable);
-}
-
-static int exynos4_clksrc_mask_peril1_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(S5P_CLKSRC_MASK_PERIL1, clk, enable);
-}
-
-static int exynos4_clk_ip_mfc_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(S5P_CLKGATE_IP_MFC, clk, enable);
-}
-
-static int exynos4_clksrc_mask_tv_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(S5P_CLKSRC_MASK_TV, clk, enable);
-}
-
-static int exynos4_clk_ip_cam_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(S5P_CLKGATE_IP_CAM, clk, enable);
-}
-
-static int exynos4_clk_ip_tv_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(S5P_CLKGATE_IP_TV, clk, enable);
-}
-
-static int exynos4_clk_ip_image_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(S5P_CLKGATE_IP_IMAGE, clk, enable);
-}
-
-static int exynos4_clk_ip_lcd0_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(S5P_CLKGATE_IP_LCD0, clk, enable);
-}
-
-int exynos4_clk_ip_lcd1_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(S5P_CLKGATE_IP_LCD1, clk, enable);
-}
-
-int exynos4_clk_ip_fsys_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(S5P_CLKGATE_IP_FSYS, clk, enable);
-}
-
-static int exynos4_clk_ip_peril_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(S5P_CLKGATE_IP_PERIL, clk, enable);
-}
-
-static int exynos4_clk_ip_perir_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(S5P_CLKGATE_IP_PERIR, clk, enable);
-}
-
-static int exynos4_clk_hdmiphy_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(S5P_HDMI_PHY_CONTROL, clk, enable);
-}
-
-static int exynos4_clk_dac_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(S5P_DAC_PHY_CONTROL, clk, enable);
-}
-
-/* Core list of CMU_CPU side */
-
-static struct clksrc_clk clk_mout_apll = {
-        .clk    = {
-                .name           = "mout_apll",
-        },
-        .sources        = &clk_src_apll,
-        .reg_src        = { .reg = S5P_CLKSRC_CPU, .shift = 0, .size = 1 },
-};
-
-struct clksrc_clk clk_sclk_apll = {
-        .clk    = {
-                .name           = "sclk_apll",
-                .parent         = &clk_mout_apll.clk,
-        },
-        .reg_div        = { .reg = S5P_CLKDIV_CPU, .shift = 24, .size = 3 },
-};
-
-struct clksrc_clk clk_mout_epll = {
-        .clk    = {
-                .name           = "mout_epll",
-        },
-        .sources        = &clk_src_epll,
-        .reg_src        = { .reg = S5P_CLKSRC_TOP0, .shift = 4, .size = 1 },
-};
-
-struct clksrc_clk clk_mout_mpll = {
-        .clk = {
-                .name           = "mout_mpll",
-        },
-        .sources        = &clk_src_mpll,
-
-        /* reg_src will be added in each SoCs' clock */
-};
-
-static struct clk *clkset_moutcore_list[] = {
-        [0] = &clk_mout_apll.clk,
-        [1] = &clk_mout_mpll.clk,
-};
-
-static struct clksrc_sources clkset_moutcore = {
-        .sources        = clkset_moutcore_list,
-        .nr_sources     = ARRAY_SIZE(clkset_moutcore_list),
-};
-
-static struct clksrc_clk clk_moutcore = {
-        .clk    = {
-                .name           = "moutcore",
-        },
-        .sources        = &clkset_moutcore,
-        .reg_src        = { .reg = S5P_CLKSRC_CPU, .shift = 16, .size = 1 },
-};
-
-static struct clksrc_clk clk_coreclk = {
-        .clk    = {
-                .name           = "core_clk",
-                .parent         = &clk_moutcore.clk,
-        },
-        .reg_div        = { .reg = S5P_CLKDIV_CPU, .shift = 0, .size = 3 },
-};
-
-static struct clksrc_clk clk_armclk = {
-        .clk    = {
-                .name           = "armclk",
-                .parent         = &clk_coreclk.clk,
-        },
-};
-
-static struct clksrc_clk clk_aclk_corem0 = {
-        .clk    = {
-                .name           = "aclk_corem0",
-                .parent         = &clk_coreclk.clk,
-        },
-        .reg_div        = { .reg = S5P_CLKDIV_CPU, .shift = 4, .size = 3 },
-};
-
-static struct clksrc_clk clk_aclk_cores = {
-        .clk    = {
-                .name           = "aclk_cores",
-                .parent         = &clk_coreclk.clk,
-        },
-        .reg_div        = { .reg = S5P_CLKDIV_CPU, .shift = 4, .size = 3 },
-};
-
-static struct clksrc_clk clk_aclk_corem1 = {
-        .clk    = {
-                .name           = "aclk_corem1",
-                .parent         = &clk_coreclk.clk,
-        },
-        .reg_div        = { .reg = S5P_CLKDIV_CPU, .shift = 8, .size = 3 },
-};
-
-static struct clksrc_clk clk_periphclk = {
-        .clk    = {
-                .name           = "periphclk",
-                .parent         = &clk_coreclk.clk,
-        },
-        .reg_div        = { .reg = S5P_CLKDIV_CPU, .shift = 12, .size = 3 },
-};
-
-/* Core list of CMU_CORE side */
-
-struct clk *clkset_corebus_list[] = {
-        [0] = &clk_mout_mpll.clk,
-        [1] = &clk_sclk_apll.clk,
-};
-
-struct clksrc_sources clkset_mout_corebus = {
-        .sources        = clkset_corebus_list,
-        .nr_sources     = ARRAY_SIZE(clkset_corebus_list),
-};
-
-static struct clksrc_clk clk_mout_corebus = {
-        .clk    = {
-                .name           = "mout_corebus",
-        },
-        .sources        = &clkset_mout_corebus,
-        .reg_src        = { .reg = S5P_CLKSRC_DMC, .shift = 4, .size = 1 },
-};
-
-static struct clksrc_clk clk_sclk_dmc = {
-        .clk    = {
-                .name           = "sclk_dmc",
-                .parent         = &clk_mout_corebus.clk,
-        },
-        .reg_div        = { .reg = S5P_CLKDIV_DMC0, .shift = 12, .size = 3 },
-};
-
-static struct clksrc_clk clk_aclk_cored = {
-        .clk    = {
-                .name           = "aclk_cored",
-                .parent         = &clk_sclk_dmc.clk,
-        },
-        .reg_div        = { .reg = S5P_CLKDIV_DMC0, .shift = 16, .size = 3 },
-};
-
-static struct clksrc_clk clk_aclk_corep = {
-        .clk    = {
-                .name           = "aclk_corep",
-                .parent         = &clk_aclk_cored.clk,
-        },
-        .reg_div        = { .reg = S5P_CLKDIV_DMC0, .shift = 20, .size = 3 },
-};
-
-static struct clksrc_clk clk_aclk_acp = {
-        .clk    = {
-                .name           = "aclk_acp",
-                .parent         = &clk_mout_corebus.clk,
-        },
-        .reg_div        = { .reg = S5P_CLKDIV_DMC0, .shift = 0, .size = 3 },
-};
-
-static struct clksrc_clk clk_pclk_acp = {
-        .clk    = {
-                .name           = "pclk_acp",
-                .parent         = &clk_aclk_acp.clk,
-        },
-        .reg_div        = { .reg = S5P_CLKDIV_DMC0, .shift = 4, .size = 3 },
-};
-
-/* Core list of CMU_TOP side */
-
-struct clk *clkset_aclk_top_list[] = {
-        [0] = &clk_mout_mpll.clk,
-        [1] = &clk_sclk_apll.clk,
-};
-
-struct clksrc_sources clkset_aclk = {
-        .sources        = clkset_aclk_top_list,
-        .nr_sources     = ARRAY_SIZE(clkset_aclk_top_list),
-};
-
-static struct clksrc_clk clk_aclk_200 = {
-        .clk    = {
-                .name           = "aclk_200",
-        },
-        .sources        = &clkset_aclk,
-        .reg_src        = { .reg = S5P_CLKSRC_TOP0, .shift = 12, .size = 1 },
-        .reg_div        = { .reg = S5P_CLKDIV_TOP, .shift = 0, .size = 3 },
-};
-
-static struct clksrc_clk clk_aclk_100 = {
-        .clk    = {
-                .name           = "aclk_100",
-        },
-        .sources        = &clkset_aclk,
-        .reg_src        = { .reg = S5P_CLKSRC_TOP0, .shift = 16, .size = 1 },
-        .reg_div        = { .reg = S5P_CLKDIV_TOP, .shift = 4, .size = 4 },
-};
-
-static struct clksrc_clk clk_aclk_160 = {
-        .clk    = {
-                .name           = "aclk_160",
-        },
-        .sources        = &clkset_aclk,
-        .reg_src        = { .reg = S5P_CLKSRC_TOP0, .shift = 20, .size = 1 },
-        .reg_div        = { .reg = S5P_CLKDIV_TOP, .shift = 8, .size = 3 },
-};
-
-struct clksrc_clk clk_aclk_133 = {
-        .clk    = {
-                .name           = "aclk_133",
-        },
-        .sources        = &clkset_aclk,
-        .reg_src        = { .reg = S5P_CLKSRC_TOP0, .shift = 24, .size = 1 },
-        .reg_div        = { .reg = S5P_CLKDIV_TOP, .shift = 12, .size = 3 },
-};
-
-static struct clk *clkset_vpllsrc_list[] = {
-        [0] = &clk_fin_vpll,
-        [1] = &clk_sclk_hdmi27m,
-};
-
-static struct clksrc_sources clkset_vpllsrc = {
-        .sources        = clkset_vpllsrc_list,
-        .nr_sources     = ARRAY_SIZE(clkset_vpllsrc_list),
-};
-
-static struct clksrc_clk clk_vpllsrc = {
-        .clk    = {
-                .name           = "vpll_src",
-                .enable         = exynos4_clksrc_mask_top_ctrl,
-                .ctrlbit        = (1 << 0),
-        },
-        .sources        = &clkset_vpllsrc,
-        .reg_src        = { .reg = S5P_CLKSRC_TOP1, .shift = 0, .size = 1 },
-};
-
-static struct clk *clkset_sclk_vpll_list[] = {
-        [0] = &clk_vpllsrc.clk,
-        [1] = &clk_fout_vpll,
-};
-
-static struct clksrc_sources clkset_sclk_vpll = {
-        .sources        = clkset_sclk_vpll_list,
-        .nr_sources     = ARRAY_SIZE(clkset_sclk_vpll_list),
-};
-
-struct clksrc_clk clk_sclk_vpll = {
-        .clk    = {
-                .name           = "sclk_vpll",
-        },
-        .sources        = &clkset_sclk_vpll,
-        .reg_src        = { .reg = S5P_CLKSRC_TOP0, .shift = 8, .size = 1 },
-};
-
-static struct clk init_clocks_off[] = {
-        {
-                .name           = "timers",
-                .parent         = &clk_aclk_100.clk,
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1<<24),
-        }, {
-                .name           = "csis",
-                .devname        = "s5p-mipi-csis.0",
-                .enable         = exynos4_clk_ip_cam_ctrl,
-                .ctrlbit        = (1 << 4),
-        }, {
-                .name           = "csis",
-                .devname        = "s5p-mipi-csis.1",
-                .enable         = exynos4_clk_ip_cam_ctrl,
-                .ctrlbit        = (1 << 5),
-        }, {
-                .name           = "fimc",
-                .devname        = "exynos4-fimc.0",
-                .enable         = exynos4_clk_ip_cam_ctrl,
-                .ctrlbit        = (1 << 0),
-        }, {
-                .name           = "fimc",
-                .devname        = "exynos4-fimc.1",
-                .enable         = exynos4_clk_ip_cam_ctrl,
-                .ctrlbit        = (1 << 1),
-        }, {
-                .name           = "fimc",
-                .devname        = "exynos4-fimc.2",
-                .enable         = exynos4_clk_ip_cam_ctrl,
-                .ctrlbit        = (1 << 2),
-        }, {
-                .name           = "fimc",
-                .devname        = "exynos4-fimc.3",
-                .enable         = exynos4_clk_ip_cam_ctrl,
-                .ctrlbit        = (1 << 3),
-        }, {
-                .name           = "fimd",
-                .devname        = "exynos4-fb.0",
-                .enable         = exynos4_clk_ip_lcd0_ctrl,
-                .ctrlbit        = (1 << 0),
-        }, {
-                .name           = "hsmmc",
-                .devname        = "s3c-sdhci.0",
-                .parent         = &clk_aclk_133.clk,
-                .enable         = exynos4_clk_ip_fsys_ctrl,
-                .ctrlbit        = (1 << 5),
-        }, {
-                .name           = "hsmmc",
-                .devname        = "s3c-sdhci.1",
-                .parent         = &clk_aclk_133.clk,
-                .enable         = exynos4_clk_ip_fsys_ctrl,
-                .ctrlbit        = (1 << 6),
-        }, {
-                .name           = "hsmmc",
-                .devname        = "s3c-sdhci.2",
-                .parent         = &clk_aclk_133.clk,
-                .enable         = exynos4_clk_ip_fsys_ctrl,
-                .ctrlbit        = (1 << 7),
-        }, {
-                .name           = "hsmmc",
-                .devname        = "s3c-sdhci.3",
-                .parent         = &clk_aclk_133.clk,
-                .enable         = exynos4_clk_ip_fsys_ctrl,
-                .ctrlbit        = (1 << 8),
-        }, {
-                .name           = "dwmmc",
-                .parent         = &clk_aclk_133.clk,
-                .enable         = exynos4_clk_ip_fsys_ctrl,
-                .ctrlbit        = (1 << 9),
-        }, {
-                .name           = "dac",
-                .devname        = "s5p-sdo",
-                .enable         = exynos4_clk_ip_tv_ctrl,
-                .ctrlbit        = (1 << 2),
-        }, {
-                .name           = "mixer",
-                .devname        = "s5p-mixer",
-                .enable         = exynos4_clk_ip_tv_ctrl,
-                .ctrlbit        = (1 << 1),
-        }, {
-                .name           = "vp",
-                .devname        = "s5p-mixer",
-                .enable         = exynos4_clk_ip_tv_ctrl,
-                .ctrlbit        = (1 << 0),
-        }, {
-                .name           = "hdmi",
-                .devname        = "exynos4-hdmi",
-                .enable         = exynos4_clk_ip_tv_ctrl,
-                .ctrlbit        = (1 << 3),
-        }, {
-                .name           = "hdmiphy",
-                .devname        = "exynos4-hdmi",
-                .enable         = exynos4_clk_hdmiphy_ctrl,
-                .ctrlbit        = (1 << 0),
-        }, {
-                .name           = "dacphy",
-                .devname        = "s5p-sdo",
-                .enable         = exynos4_clk_dac_ctrl,
-                .ctrlbit        = (1 << 0),
-        }, {
-                .name           = "adc",
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1 << 15),
-        }, {
-                .name           = "keypad",
-                .enable         = exynos4_clk_ip_perir_ctrl,
-                .ctrlbit        = (1 << 16),
-        }, {
-                .name           = "rtc",
-                .enable         = exynos4_clk_ip_perir_ctrl,
-                .ctrlbit        = (1 << 15),
-        }, {
-                .name           = "watchdog",
-                .parent         = &clk_aclk_100.clk,
-                .enable         = exynos4_clk_ip_perir_ctrl,
-                .ctrlbit        = (1 << 14),
-        }, {
-                .name           = "usbhost",
-                .enable         = exynos4_clk_ip_fsys_ctrl ,
-                .ctrlbit        = (1 << 12),
-        }, {
-                .name           = "otg",
-                .enable         = exynos4_clk_ip_fsys_ctrl,
-                .ctrlbit        = (1 << 13),
-        }, {
-                .name           = "spi",
-                .devname        = "s3c64xx-spi.0",
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1 << 16),
-        }, {
-                .name           = "spi",
-                .devname        = "s3c64xx-spi.1",
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1 << 17),
-        }, {
-                .name           = "spi",
-                .devname        = "s3c64xx-spi.2",
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1 << 18),
-        }, {
-                .name           = "iis",
-                .devname        = "samsung-i2s.0",
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1 << 19),
-        }, {
-                .name           = "iis",
-                .devname        = "samsung-i2s.1",
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1 << 20),
-        }, {
-                .name           = "iis",
-                .devname        = "samsung-i2s.2",
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1 << 21),
-        }, {
-                .name           = "ac97",
-                .devname        = "samsung-ac97",
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1 << 27),
-        }, {
-                .name           = "fimg2d",
-                .enable         = exynos4_clk_ip_image_ctrl,
-                .ctrlbit        = (1 << 0),
-        }, {
-                .name           = "mfc",
-                .devname        = "s5p-mfc",
-                .enable         = exynos4_clk_ip_mfc_ctrl,
-                .ctrlbit        = (1 << 0),
-        }, {
-                .name           = "i2c",
-                .devname        = "s3c2440-i2c.0",
-                .parent         = &clk_aclk_100.clk,
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1 << 6),
-        }, {
-                .name           = "i2c",
-                .devname        = "s3c2440-i2c.1",
-                .parent         = &clk_aclk_100.clk,
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1 << 7),
-        }, {
-                .name           = "i2c",
-                .devname        = "s3c2440-i2c.2",
-                .parent         = &clk_aclk_100.clk,
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1 << 8),
-        }, {
-                .name           = "i2c",
-                .devname        = "s3c2440-i2c.3",
-                .parent         = &clk_aclk_100.clk,
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1 << 9),
-        }, {
-                .name           = "i2c",
-                .devname        = "s3c2440-i2c.4",
-                .parent         = &clk_aclk_100.clk,
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1 << 10),
-        }, {
-                .name           = "i2c",
-                .devname        = "s3c2440-i2c.5",
-                .parent         = &clk_aclk_100.clk,
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1 << 11),
-        }, {
-                .name           = "i2c",
-                .devname        = "s3c2440-i2c.6",
-                .parent         = &clk_aclk_100.clk,
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1 << 12),
-        }, {
-                .name           = "i2c",
-                .devname        = "s3c2440-i2c.7",
-                .parent         = &clk_aclk_100.clk,
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1 << 13),
-        }, {
-                .name           = "i2c",
-                .devname        = "s3c2440-hdmiphy-i2c",
-                .parent         = &clk_aclk_100.clk,
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1 << 14),
-        }, {
-                .name           = "SYSMMU_MDMA",
-                .enable         = exynos4_clk_ip_image_ctrl,
-                .ctrlbit        = (1 << 5),
-        }, {
-                .name           = "SYSMMU_FIMC0",
-                .enable         = exynos4_clk_ip_cam_ctrl,
-                .ctrlbit        = (1 << 7),
-        }, {
-                .name           = "SYSMMU_FIMC1",
-                .enable         = exynos4_clk_ip_cam_ctrl,
-                .ctrlbit        = (1 << 8),
-        }, {
-                .name           = "SYSMMU_FIMC2",
-                .enable         = exynos4_clk_ip_cam_ctrl,
-                .ctrlbit        = (1 << 9),
-        }, {
-                .name           = "SYSMMU_FIMC3",
-                .enable         = exynos4_clk_ip_cam_ctrl,
-                .ctrlbit        = (1 << 10),
-        }, {
-                .name           = "SYSMMU_JPEG",
-                .enable         = exynos4_clk_ip_cam_ctrl,
-                .ctrlbit        = (1 << 11),
-        }, {
-                .name           = "SYSMMU_FIMD0",
-                .enable         = exynos4_clk_ip_lcd0_ctrl,
-                .ctrlbit        = (1 << 4),
-        }, {
-                .name           = "SYSMMU_FIMD1",
-                .enable         = exynos4_clk_ip_lcd1_ctrl,
-                .ctrlbit        = (1 << 4),
-        }, {
-                .name           = "SYSMMU_PCIe",
-                .enable         = exynos4_clk_ip_fsys_ctrl,
-                .ctrlbit        = (1 << 18),
-        }, {
-                .name           = "SYSMMU_G2D",
-                .enable         = exynos4_clk_ip_image_ctrl,
-                .ctrlbit        = (1 << 3),
-        }, {
-                .name           = "SYSMMU_ROTATOR",
-                .enable         = exynos4_clk_ip_image_ctrl,
-                .ctrlbit        = (1 << 4),
-        }, {
-                .name           = "SYSMMU_TV",
-                .enable         = exynos4_clk_ip_tv_ctrl,
-                .ctrlbit        = (1 << 4),
-        }, {
-                .name           = "SYSMMU_MFC_L",
-                .enable         = exynos4_clk_ip_mfc_ctrl,
-                .ctrlbit        = (1 << 1),
-        }, {
-                .name           = "SYSMMU_MFC_R",
-                .enable         = exynos4_clk_ip_mfc_ctrl,
-                .ctrlbit        = (1 << 2),
-        }
-};
-
-static struct clk init_clocks[] = {
-        {
-                .name           = "uart",
-                .devname        = "s5pv210-uart.0",
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1 << 0),
-        }, {
-                .name           = "uart",
-                .devname        = "s5pv210-uart.1",
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1 << 1),
-        }, {
-                .name           = "uart",
-                .devname        = "s5pv210-uart.2",
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1 << 2),
-        }, {
-                .name           = "uart",
-                .devname        = "s5pv210-uart.3",
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1 << 3),
-        }, {
-                .name           = "uart",
-                .devname        = "s5pv210-uart.4",
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1 << 4),
-        }, {
-                .name           = "uart",
-                .devname        = "s5pv210-uart.5",
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1 << 5),
-        }
-};
-
-static struct clk clk_pdma0 = {
-        .name           = "dma",
-        .devname        = "dma-pl330.0",
-        .enable         = exynos4_clk_ip_fsys_ctrl,
-        .ctrlbit        = (1 << 0),
-};
-
-static struct clk clk_pdma1 = {
-        .name           = "dma",
-        .devname        = "dma-pl330.1",
-        .enable         = exynos4_clk_ip_fsys_ctrl,
-        .ctrlbit        = (1 << 1),
-};
-
-struct clk *clkset_group_list[] = {
-        [0] = &clk_ext_xtal_mux,
-        [1] = &clk_xusbxti,
-        [2] = &clk_sclk_hdmi27m,
-        [3] = &clk_sclk_usbphy0,
-        [4] = &clk_sclk_usbphy1,
-        [5] = &clk_sclk_hdmiphy,
-        [6] = &clk_mout_mpll.clk,
-        [7] = &clk_mout_epll.clk,
-        [8] = &clk_sclk_vpll.clk,
-};
-
-struct clksrc_sources clkset_group = {
-        .sources        = clkset_group_list,
-        .nr_sources     = ARRAY_SIZE(clkset_group_list),
-};
-
-static struct clk *clkset_mout_g2d0_list[] = {
-        [0] = &clk_mout_mpll.clk,
-        [1] = &clk_sclk_apll.clk,
-};
-
-static struct clksrc_sources clkset_mout_g2d0 = {
-        .sources        = clkset_mout_g2d0_list,
-        .nr_sources     = ARRAY_SIZE(clkset_mout_g2d0_list),
-};
-
-static struct clksrc_clk clk_mout_g2d0 = {
-        .clk    = {
-                .name           = "mout_g2d0",
-        },
-        .sources        = &clkset_mout_g2d0,
-        .reg_src        = { .reg = S5P_CLKSRC_IMAGE, .shift = 0, .size = 1 },
-};
-
-static struct clk *clkset_mout_g2d1_list[] = {
-        [0] = &clk_mout_epll.clk,
-        [1] = &clk_sclk_vpll.clk,
-};
-
-static struct clksrc_sources clkset_mout_g2d1 = {
-        .sources        = clkset_mout_g2d1_list,
-        .nr_sources     = ARRAY_SIZE(clkset_mout_g2d1_list),
-};
-
-static struct clksrc_clk clk_mout_g2d1 = {
-        .clk    = {
-                .name           = "mout_g2d1",
-        },
-        .sources        = &clkset_mout_g2d1,
-        .reg_src        = { .reg = S5P_CLKSRC_IMAGE, .shift = 4, .size = 1 },
-};
-
-static struct clk *clkset_mout_g2d_list[] = {
-        [0] = &clk_mout_g2d0.clk,
-        [1] = &clk_mout_g2d1.clk,
-};
-
-static struct clksrc_sources clkset_mout_g2d = {
-        .sources        = clkset_mout_g2d_list,
-        .nr_sources     = ARRAY_SIZE(clkset_mout_g2d_list),
-};
-
-static struct clk *clkset_mout_mfc0_list[] = {
-        [0] = &clk_mout_mpll.clk,
-        [1] = &clk_sclk_apll.clk,
-};
-
-static struct clksrc_sources clkset_mout_mfc0 = {
-        .sources        = clkset_mout_mfc0_list,
-        .nr_sources     = ARRAY_SIZE(clkset_mout_mfc0_list),
-};
-
-static struct clksrc_clk clk_mout_mfc0 = {
-        .clk    = {
-                .name           = "mout_mfc0",
-        },
-        .sources        = &clkset_mout_mfc0,
-        .reg_src        = { .reg = S5P_CLKSRC_MFC, .shift = 0, .size = 1 },
-};
-
-static struct clk *clkset_mout_mfc1_list[] = {
-        [0] = &clk_mout_epll.clk,
-        [1] = &clk_sclk_vpll.clk,
-};
-
-static struct clksrc_sources clkset_mout_mfc1 = {
-        .sources        = clkset_mout_mfc1_list,
-        .nr_sources     = ARRAY_SIZE(clkset_mout_mfc1_list),
-};
-
-static struct clksrc_clk clk_mout_mfc1 = {
-        .clk    = {
-                .name           = "mout_mfc1",
-        },
-        .sources        = &clkset_mout_mfc1,
-        .reg_src        = { .reg = S5P_CLKSRC_MFC, .shift = 4, .size = 1 },
-};
-
-static struct clk *clkset_mout_mfc_list[] = {
-        [0] = &clk_mout_mfc0.clk,
-        [1] = &clk_mout_mfc1.clk,
-};
-
-static struct clksrc_sources clkset_mout_mfc = {
-        .sources        = clkset_mout_mfc_list,
-        .nr_sources     = ARRAY_SIZE(clkset_mout_mfc_list),
-};
-
-static struct clk *clkset_sclk_dac_list[] = {
-        [0] = &clk_sclk_vpll.clk,
-        [1] = &clk_sclk_hdmiphy,
-};
-
-static struct clksrc_sources clkset_sclk_dac = {
-        .sources        = clkset_sclk_dac_list,
-        .nr_sources     = ARRAY_SIZE(clkset_sclk_dac_list),
-};
-
-static struct clksrc_clk clk_sclk_dac = {
-        .clk            = {
-                .name           = "sclk_dac",
-                .enable         = exynos4_clksrc_mask_tv_ctrl,
-                .ctrlbit        = (1 << 8),
-        },
-        .sources = &clkset_sclk_dac,
-        .reg_src = { .reg = S5P_CLKSRC_TV, .shift = 8, .size = 1 },
-};
-
-static struct clksrc_clk clk_sclk_pixel = {
-        .clk            = {
-                .name           = "sclk_pixel",
-                .parent = &clk_sclk_vpll.clk,
-        },
-        .reg_div = { .reg = S5P_CLKDIV_TV, .shift = 0, .size = 4 },
-};
-
-static struct clk *clkset_sclk_hdmi_list[] = {
-        [0] = &clk_sclk_pixel.clk,
-        [1] = &clk_sclk_hdmiphy,
-};
-
-static struct clksrc_sources clkset_sclk_hdmi = {
-        .sources        = clkset_sclk_hdmi_list,
-        .nr_sources     = ARRAY_SIZE(clkset_sclk_hdmi_list),
-};
-
-static struct clksrc_clk clk_sclk_hdmi = {
-        .clk            = {
-                .name           = "sclk_hdmi",
-                .enable         = exynos4_clksrc_mask_tv_ctrl,
-                .ctrlbit        = (1 << 0),
-        },
-        .sources = &clkset_sclk_hdmi,
-        .reg_src = { .reg = S5P_CLKSRC_TV, .shift = 0, .size = 1 },
-};
-
-static struct clk *clkset_sclk_mixer_list[] = {
-        [0] = &clk_sclk_dac.clk,
-        [1] = &clk_sclk_hdmi.clk,
-};
-
-static struct clksrc_sources clkset_sclk_mixer = {
-        .sources        = clkset_sclk_mixer_list,
-        .nr_sources     = ARRAY_SIZE(clkset_sclk_mixer_list),
-};
-
-static struct clksrc_clk clk_sclk_mixer = {
-        .clk            = {
-                .name           = "sclk_mixer",
-                .enable         = exynos4_clksrc_mask_tv_ctrl,
-                .ctrlbit        = (1 << 4),
-        },
-        .sources = &clkset_sclk_mixer,
-        .reg_src = { .reg = S5P_CLKSRC_TV, .shift = 4, .size = 1 },
-};
-
-static struct clksrc_clk *sclk_tv[] = {
-        &clk_sclk_dac,
-        &clk_sclk_pixel,
-        &clk_sclk_hdmi,
-        &clk_sclk_mixer,
-};
-
-static struct clksrc_clk clk_dout_mmc0 = {
-        .clk            = {
-                .name           = "dout_mmc0",
-        },
-        .sources = &clkset_group,
-        .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 0, .size = 4 },
-        .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 0, .size = 4 },
-};
-
-static struct clksrc_clk clk_dout_mmc1 = {
-        .clk            = {
-                .name           = "dout_mmc1",
-        },
-        .sources = &clkset_group,
-        .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 4, .size = 4 },
-        .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 16, .size = 4 },
-};
-
-static struct clksrc_clk clk_dout_mmc2 = {
-        .clk            = {
-                .name           = "dout_mmc2",
-        },
-        .sources = &clkset_group,
-        .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 8, .size = 4 },
-        .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 0, .size = 4 },
-};
-
-static struct clksrc_clk clk_dout_mmc3 = {
-        .clk            = {
-                .name           = "dout_mmc3",
-        },
-        .sources = &clkset_group,
-        .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 12, .size = 4 },
-        .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 16, .size = 4 },
-};
-
-static struct clksrc_clk clk_dout_mmc4 = {
-        .clk            = {
-                .name           = "dout_mmc4",
-        },
-        .sources = &clkset_group,
-        .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 16, .size = 4 },
-        .reg_div = { .reg = S5P_CLKDIV_FSYS3, .shift = 0, .size = 4 },
-};
-
-static struct clksrc_clk clksrcs[] = {
-        {
-                .clk            = {
-                        .name           = "sclk_pwm",
-                        .enable         = exynos4_clksrc_mask_peril0_ctrl,
-                        .ctrlbit        = (1 << 24),
-                },
-                .sources = &clkset_group,
-                .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 24, .size = 4 },
-                .reg_div = { .reg = S5P_CLKDIV_PERIL3, .shift = 0, .size = 4 },
-        }, {
-                .clk            = {
-                        .name           = "sclk_csis",
-                        .devname        = "s5p-mipi-csis.0",
-                        .enable         = exynos4_clksrc_mask_cam_ctrl,
-                        .ctrlbit        = (1 << 24),
-                },
-                .sources = &clkset_group,
-                .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 24, .size = 4 },
-                .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 24, .size = 4 },
-        }, {
-                .clk            = {
-                        .name           = "sclk_csis",
-                        .devname        = "s5p-mipi-csis.1",
-                        .enable         = exynos4_clksrc_mask_cam_ctrl,
-                        .ctrlbit        = (1 << 28),
-                },
-                .sources = &clkset_group,
-                .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 28, .size = 4 },
-                .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 28, .size = 4 },
-        }, {
-                .clk            = {
-                        .name           = "sclk_cam0",
-                        .enable         = exynos4_clksrc_mask_cam_ctrl,
-                        .ctrlbit        = (1 << 16),
-                },
-                .sources = &clkset_group,
-                .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 16, .size = 4 },
-                .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 16, .size = 4 },
-        }, {
-                .clk            = {
-                        .name           = "sclk_cam1",
-                        .enable         = exynos4_clksrc_mask_cam_ctrl,
-                        .ctrlbit        = (1 << 20),
-                },
-                .sources = &clkset_group,
-                .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 20, .size = 4 },
-                .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 20, .size = 4 },
-        }, {
-                .clk            = {
-                        .name           = "sclk_fimc",
-                        .devname        = "exynos4-fimc.0",
-                        .enable         = exynos4_clksrc_mask_cam_ctrl,
-                        .ctrlbit        = (1 << 0),
-                },
-                .sources = &clkset_group,
-                .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 0, .size = 4 },
-                .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 0, .size = 4 },
-        }, {
-                .clk            = {
-                        .name           = "sclk_fimc",
-                        .devname        = "exynos4-fimc.1",
-                        .enable         = exynos4_clksrc_mask_cam_ctrl,
-                        .ctrlbit        = (1 << 4),
-                },
-                .sources = &clkset_group,
-                .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 4, .size = 4 },
-                .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 4, .size = 4 },
-        }, {
-                .clk            = {
-                        .name           = "sclk_fimc",
-                        .devname        = "exynos4-fimc.2",
-                        .enable         = exynos4_clksrc_mask_cam_ctrl,
-                        .ctrlbit        = (1 << 8),
-                },
-                .sources = &clkset_group,
-                .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 8, .size = 4 },
-                .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 8, .size = 4 },
-        }, {
-                .clk            = {
-                        .name           = "sclk_fimc",
-                        .devname        = "exynos4-fimc.3",
-                        .enable         = exynos4_clksrc_mask_cam_ctrl,
-                        .ctrlbit        = (1 << 12),
-                },
-                .sources = &clkset_group,
-                .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 12, .size = 4 },
-                .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 12, .size = 4 },
-        }, {
-                .clk            = {
-                        .name           = "sclk_fimd",
-                        .devname        = "exynos4-fb.0",
-                        .enable         = exynos4_clksrc_mask_lcd0_ctrl,
-                        .ctrlbit        = (1 << 0),
-                },
-                .sources = &clkset_group,
-                .reg_src = { .reg = S5P_CLKSRC_LCD0, .shift = 0, .size = 4 },
-                .reg_div = { .reg = S5P_CLKDIV_LCD0, .shift = 0, .size = 4 },
-        }, {
-                .clk            = {
-                        .name           = "sclk_fimg2d",
-                },
-                .sources = &clkset_mout_g2d,
-                .reg_src = { .reg = S5P_CLKSRC_IMAGE, .shift = 8, .size = 1 },
-                .reg_div = { .reg = S5P_CLKDIV_IMAGE, .shift = 0, .size = 4 },
-        }, {
-                .clk            = {
-                        .name           = "sclk_mfc",
-                        .devname        = "s5p-mfc",
-                },
-                .sources = &clkset_mout_mfc,
-                .reg_src = { .reg = S5P_CLKSRC_MFC, .shift = 8, .size = 1 },
-                .reg_div = { .reg = S5P_CLKDIV_MFC, .shift = 0, .size = 4 },
-        }, {
-                .clk            = {
-                        .name           = "sclk_dwmmc",
-                        .parent         = &clk_dout_mmc4.clk,
-                        .enable         = exynos4_clksrc_mask_fsys_ctrl,
-                        .ctrlbit        = (1 << 16),
-                },
-                .reg_div = { .reg = S5P_CLKDIV_FSYS3, .shift = 8, .size = 8 },
-        }
-};
-
-static struct clksrc_clk clk_sclk_uart0 = {
-        .clk    = {
-                .name           = "uclk1",
-                .devname        = "exynos4210-uart.0",
-                .enable         = exynos4_clksrc_mask_peril0_ctrl,
-                .ctrlbit        = (1 << 0),
-        },
-        .sources = &clkset_group,
-        .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 0, .size = 4 },
-        .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 0, .size = 4 },
-};
-
-static struct clksrc_clk clk_sclk_uart1 = {
-        .clk            = {
-                .name           = "uclk1",
-                .devname        = "exynos4210-uart.1",
-                .enable         = exynos4_clksrc_mask_peril0_ctrl,
-                .ctrlbit        = (1 << 4),
-        },
-        .sources = &clkset_group,
-        .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 4, .size = 4 },
-        .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 4, .size = 4 },
-};
-
-static struct clksrc_clk clk_sclk_uart2 = {
-        .clk            = {
-                .name           = "uclk1",
-                .devname        = "exynos4210-uart.2",
-                .enable         = exynos4_clksrc_mask_peril0_ctrl,
-                .ctrlbit        = (1 << 8),
-        },
-        .sources = &clkset_group,
-        .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 8, .size = 4 },
-        .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 8, .size = 4 },
-};
-
-static struct clksrc_clk clk_sclk_uart3 = {
-        .clk            = {
-                .name           = "uclk1",
-                .devname        = "exynos4210-uart.3",
-                .enable         = exynos4_clksrc_mask_peril0_ctrl,
-                .ctrlbit        = (1 << 12),
-        },
-        .sources = &clkset_group,
-        .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 12, .size = 4 },
-        .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 12, .size = 4 },
-};
-
-static struct clksrc_clk clk_sclk_mmc0 = {
-        .clk            = {
-                .name           = "sclk_mmc",
-                .devname        = "s3c-sdhci.0",
-                .parent         = &clk_dout_mmc0.clk,
-                .enable         = exynos4_clksrc_mask_fsys_ctrl,
-                .ctrlbit        = (1 << 0),
-        },
-        .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 8, .size = 8 },
-};
-
-static struct clksrc_clk clk_sclk_mmc1 = {
-        .clk            = {
-                .name           = "sclk_mmc",
-                .devname        = "s3c-sdhci.1",
-                .parent         = &clk_dout_mmc1.clk,
-                .enable         = exynos4_clksrc_mask_fsys_ctrl,
-                .ctrlbit        = (1 << 4),
-        },
-        .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 24, .size = 8 },
-};
-
-static struct clksrc_clk clk_sclk_mmc2 = {
-        .clk            = {
-                .name           = "sclk_mmc",
-                .devname        = "s3c-sdhci.2",
-                .parent         = &clk_dout_mmc2.clk,
-                .enable         = exynos4_clksrc_mask_fsys_ctrl,
-                .ctrlbit        = (1 << 8),
-        },
-        .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 8, .size = 8 },
-};
-
-static struct clksrc_clk clk_sclk_mmc3 = {
-        .clk            = {
-                .name           = "sclk_mmc",
-                .devname        = "s3c-sdhci.3",
-                .parent         = &clk_dout_mmc3.clk,
-                .enable         = exynos4_clksrc_mask_fsys_ctrl,
-                .ctrlbit        = (1 << 12),
-        },
-        .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 24, .size = 8 },
-};
-
-static struct clksrc_clk clk_sclk_spi0 = {
-        .clk            = {
-                .name           = "sclk_spi",
-                .devname                = "s3c64xx-spi.0",
-                .enable         = exynos4_clksrc_mask_peril1_ctrl,
-                .ctrlbit                = (1 << 16),
-        },
-        .sources = &clkset_group,
-        .reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 16, .size = 4 },
-        .reg_div = { .reg = S5P_CLKDIV_PERIL1, .shift = 0, .size = 4 },
-};
-
-static struct clksrc_clk clk_sclk_spi1 = {
-        .clk            = {
-                .name           = "sclk_spi",
-                .devname                = "s3c64xx-spi.1",
-                .enable         = exynos4_clksrc_mask_peril1_ctrl,
-                .ctrlbit                = (1 << 20),
-        },
-        .sources = &clkset_group,
-        .reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 20, .size = 4 },
-        .reg_div = { .reg = S5P_CLKDIV_PERIL1, .shift = 16, .size = 4 },
-};
-
-static struct clksrc_clk clk_sclk_spi2 = {
-        .clk            = {
-                .name           = "sclk_spi",
-                .devname                = "s3c64xx-spi.2",
-                .enable         = exynos4_clksrc_mask_peril1_ctrl,
-                .ctrlbit                = (1 << 24),
-        },
-        .sources = &clkset_group,
-        .reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 24, .size = 4 },
-        .reg_div = { .reg = S5P_CLKDIV_PERIL2, .shift = 0, .size = 4 },
-};
-
-/* Clock initialization code */
-static struct clksrc_clk *sysclks[] = {
-        &clk_mout_apll,
-        &clk_sclk_apll,
-        &clk_mout_epll,
-        &clk_mout_mpll,
-        &clk_moutcore,
-        &clk_coreclk,
-        &clk_armclk,
-        &clk_aclk_corem0,
-        &clk_aclk_cores,
-        &clk_aclk_corem1,
-        &clk_periphclk,
-        &clk_mout_corebus,
-        &clk_sclk_dmc,
-        &clk_aclk_cored,
-        &clk_aclk_corep,
-        &clk_aclk_acp,
-        &clk_pclk_acp,
-        &clk_vpllsrc,
-        &clk_sclk_vpll,
-        &clk_aclk_200,
-        &clk_aclk_100,
-        &clk_aclk_160,
-        &clk_aclk_133,
-        &clk_dout_mmc0,
-        &clk_dout_mmc1,
-        &clk_dout_mmc2,
-        &clk_dout_mmc3,
-        &clk_dout_mmc4,
-        &clk_mout_mfc0,
-        &clk_mout_mfc1,
-};
-
-static struct clk *clk_cdev[] = {
-        &clk_pdma0,
-        &clk_pdma1,
-};
-
-static struct clksrc_clk *clksrc_cdev[] = {
-        &clk_sclk_uart0,
-        &clk_sclk_uart1,
-        &clk_sclk_uart2,
-        &clk_sclk_uart3,
-        &clk_sclk_mmc0,
-        &clk_sclk_mmc1,
-        &clk_sclk_mmc2,
-        &clk_sclk_mmc3,
-        &clk_sclk_spi0,
-        &clk_sclk_spi1,
-        &clk_sclk_spi2,
-
-};
-
-static struct clk_lookup exynos4_clk_lookup[] = {
-        CLKDEV_INIT("exynos4210-uart.0", "clk_uart_baud0", &clk_sclk_uart0.clk),
-        CLKDEV_INIT("exynos4210-uart.1", "clk_uart_baud0", &clk_sclk_uart1.clk),
-        CLKDEV_INIT("exynos4210-uart.2", "clk_uart_baud0", &clk_sclk_uart2.clk),
-        CLKDEV_INIT("exynos4210-uart.3", "clk_uart_baud0", &clk_sclk_uart3.clk),
-        CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &clk_sclk_mmc0.clk),
-        CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk),
-        CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk),
-        CLKDEV_INIT("s3c-sdhci.3", "mmc_busclk.2", &clk_sclk_mmc3.clk),
-        CLKDEV_INIT("dma-pl330.0", "apb_pclk", &clk_pdma0),
-        CLKDEV_INIT("dma-pl330.1", "apb_pclk", &clk_pdma1),
-        CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk0", &clk_sclk_spi0.clk),
-        CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk0", &clk_sclk_spi1.clk),
-        CLKDEV_INIT("s3c64xx-spi.2", "spi_busclk0", &clk_sclk_spi2.clk),
-};
-
-static int xtal_rate;
-
-static unsigned long exynos4_fout_apll_get_rate(struct clk *clk)
-{
-        if (soc_is_exynos4210())
-                return s5p_get_pll45xx(xtal_rate, __raw_readl(S5P_APLL_CON0),
-                                        pll_4508);
-        else if (soc_is_exynos4212() || soc_is_exynos4412())
-                return s5p_get_pll35xx(xtal_rate, __raw_readl(S5P_APLL_CON0));
-        else
-                return 0;
-}
-
-static struct clk_ops exynos4_fout_apll_ops = {
-        .get_rate = exynos4_fout_apll_get_rate,
-};
-
-static u32 vpll_div[][8] = {
-        {  54000000, 3, 53, 3, 1024, 0, 17, 0 },
-        { 108000000, 3, 53, 2, 1024, 0, 17, 0 },
-};
-
-static unsigned long exynos4_vpll_get_rate(struct clk *clk)
-{
-        return clk->rate;
-}
-
-static int exynos4_vpll_set_rate(struct clk *clk, unsigned long rate)
-{
-        unsigned int vpll_con0, vpll_con1 = 0;
-        unsigned int i;
-
-        /* Return if nothing changed */
-        if (clk->rate == rate)
-                return 0;
-
-        vpll_con0 = __raw_readl(S5P_VPLL_CON0);
-        vpll_con0 &= ~(0x1 << 27 |                                      \
-                        PLL90XX_MDIV_MASK << PLL46XX_MDIV_SHIFT |       \
-                        PLL90XX_PDIV_MASK << PLL46XX_PDIV_SHIFT |       \
-                        PLL90XX_SDIV_MASK << PLL46XX_SDIV_SHIFT);
-
-        vpll_con1 = __raw_readl(S5P_VPLL_CON1);
-        vpll_con1 &= ~(PLL46XX_MRR_MASK << PLL46XX_MRR_SHIFT |  \
-                        PLL46XX_MFR_MASK << PLL46XX_MFR_SHIFT | \
-                        PLL4650C_KDIV_MASK << PLL46XX_KDIV_SHIFT);
-
-        for (i = 0; i < ARRAY_SIZE(vpll_div); i++) {
-                if (vpll_div[i][0] == rate) {
-                        vpll_con0 |= vpll_div[i][1] << PLL46XX_PDIV_SHIFT;
-                        vpll_con0 |= vpll_div[i][2] << PLL46XX_MDIV_SHIFT;
-                        vpll_con0 |= vpll_div[i][3] << PLL46XX_SDIV_SHIFT;
-                        vpll_con1 |= vpll_div[i][4] << PLL46XX_KDIV_SHIFT;
-                        vpll_con1 |= vpll_div[i][5] << PLL46XX_MFR_SHIFT;
-                        vpll_con1 |= vpll_div[i][6] << PLL46XX_MRR_SHIFT;
-                        vpll_con0 |= vpll_div[i][7] << 27;
-                        break;
-                }
-        }
-
-        if (i == ARRAY_SIZE(vpll_div)) {
-                printk(KERN_ERR "%s: Invalid Clock VPLL Frequency\n",
-                                __func__);
-                return -EINVAL;
-        }
-
-        __raw_writel(vpll_con0, S5P_VPLL_CON0);
-        __raw_writel(vpll_con1, S5P_VPLL_CON1);
-
-        /* Wait for VPLL lock */
-        while (!(__raw_readl(S5P_VPLL_CON0) & (1 << PLL46XX_LOCKED_SHIFT)))
-                continue;
-
-        clk->rate = rate;
-        return 0;
-}
-
-static struct clk_ops exynos4_vpll_ops = {
-        .get_rate = exynos4_vpll_get_rate,
-        .set_rate = exynos4_vpll_set_rate,
-};
-
-void __init_or_cpufreq exynos4_setup_clocks(void)
-{
-        struct clk *xtal_clk;
-        unsigned long apll = 0;
-        unsigned long mpll = 0;
-        unsigned long epll = 0;
-        unsigned long vpll = 0;
-        unsigned long vpllsrc;
-        unsigned long xtal;
-        unsigned long armclk;
-        unsigned long sclk_dmc;
-        unsigned long aclk_200;
-        unsigned long aclk_100;
-        unsigned long aclk_160;
-        unsigned long aclk_133;
-        unsigned int ptr;
-
-        printk(KERN_DEBUG "%s: registering clocks\n", __func__);
-
-        xtal_clk = clk_get(NULL, "xtal");
-        BUG_ON(IS_ERR(xtal_clk));
-
-        xtal = clk_get_rate(xtal_clk);
-
-        xtal_rate = xtal;
-
-        clk_put(xtal_clk);
-
-        printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
-
-        if (soc_is_exynos4210()) {
-                apll = s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON0),
-                                        pll_4508);
-                mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P_MPLL_CON0),
-                                        pll_4508);
-                epll = s5p_get_pll46xx(xtal, __raw_readl(S5P_EPLL_CON0),
-                                        __raw_readl(S5P_EPLL_CON1), pll_4600);
-
-                vpllsrc = clk_get_rate(&clk_vpllsrc.clk);
-                vpll = s5p_get_pll46xx(vpllsrc, __raw_readl(S5P_VPLL_CON0),
-                                        __raw_readl(S5P_VPLL_CON1), pll_4650c);
-        } else if (soc_is_exynos4212() || soc_is_exynos4412()) {
-                apll = s5p_get_pll35xx(xtal, __raw_readl(S5P_APLL_CON0));
-                mpll = s5p_get_pll35xx(xtal, __raw_readl(S5P_MPLL_CON0));
-                epll = s5p_get_pll36xx(xtal, __raw_readl(S5P_EPLL_CON0),
-                                        __raw_readl(S5P_EPLL_CON1));
-
-                vpllsrc = clk_get_rate(&clk_vpllsrc.clk);
-                vpll = s5p_get_pll36xx(vpllsrc, __raw_readl(S5P_VPLL_CON0),
-                                        __raw_readl(S5P_VPLL_CON1));
-        } else {
-                /* nothing */
-        }
-
-        clk_fout_apll.ops = &exynos4_fout_apll_ops;
-        clk_fout_mpll.rate = mpll;
-        clk_fout_epll.rate = epll;
-        clk_fout_vpll.ops = &exynos4_vpll_ops;
-        clk_fout_vpll.rate = vpll;
-
-        printk(KERN_INFO "EXYNOS4: PLL settings, A=%ld, M=%ld, E=%ld V=%ld",
-                        apll, mpll, epll, vpll);
-
-        armclk = clk_get_rate(&clk_armclk.clk);
-        sclk_dmc = clk_get_rate(&clk_sclk_dmc.clk);
-
-        aclk_200 = clk_get_rate(&clk_aclk_200.clk);
-        aclk_100 = clk_get_rate(&clk_aclk_100.clk);
-        aclk_160 = clk_get_rate(&clk_aclk_160.clk);
-        aclk_133 = clk_get_rate(&clk_aclk_133.clk);
-
-        printk(KERN_INFO "EXYNOS4: ARMCLK=%ld, DMC=%ld, ACLK200=%ld\n"
-                         "ACLK100=%ld, ACLK160=%ld, ACLK133=%ld\n",
-                        armclk, sclk_dmc, aclk_200,
-                        aclk_100, aclk_160, aclk_133);
-
-        clk_f.rate = armclk;
-        clk_h.rate = sclk_dmc;
-        clk_p.rate = aclk_100;
-
-        for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
-                s3c_set_clksrc(&clksrcs[ptr], true);
-}
-
-static struct clk *clks[] __initdata = {
-        &clk_sclk_hdmi27m,
-        &clk_sclk_hdmiphy,
-        &clk_sclk_usbphy0,
-        &clk_sclk_usbphy1,
-};
-
-#ifdef CONFIG_PM_SLEEP
-static int exynos4_clock_suspend(void)
-{
-        s3c_pm_do_save(exynos4_clock_save, ARRAY_SIZE(exynos4_clock_save));
-        return 0;
-}
-
-static void exynos4_clock_resume(void)
-{
-        s3c_pm_do_restore_core(exynos4_clock_save, ARRAY_SIZE(exynos4_clock_save));
-}
-
-#else
-#define exynos4_clock_suspend NULL
-#define exynos4_clock_resume NULL
-#endif
-
-struct syscore_ops exynos4_clock_syscore_ops = {
-        .suspend        = exynos4_clock_suspend,
-        .resume         = exynos4_clock_resume,
-};
-
-void __init exynos4_register_clocks(void)
-{
-        int ptr;
-
-        s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
-
-        for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
-                s3c_register_clksrc(sysclks[ptr], 1);
-
-        for (ptr = 0; ptr < ARRAY_SIZE(sclk_tv); ptr++)
-                s3c_register_clksrc(sclk_tv[ptr], 1);
-
-        for (ptr = 0; ptr < ARRAY_SIZE(clksrc_cdev); ptr++)
-                s3c_register_clksrc(clksrc_cdev[ptr], 1);
-
-        s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
-        s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
-
-        s3c24xx_register_clocks(clk_cdev, ARRAY_SIZE(clk_cdev));
-        for (ptr = 0; ptr < ARRAY_SIZE(clk_cdev); ptr++)
-                s3c_disable_clocks(clk_cdev[ptr], 1);
-
-        s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
-        s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
-        clkdev_add_table(exynos4_clk_lookup, ARRAY_SIZE(exynos4_clk_lookup));
-
-        register_syscore_ops(&exynos4_clock_syscore_ops);
-        s3c24xx_register_clock(&dummy_apb_pclk);
-
-        s3c_pwmclk_init();
-}
diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
index 6de298c5d2d..97ca2592ce8 100644
--- a/arch/arm/mach-exynos/common.c
+++ b/arch/arm/mach-exynos/common.c
@@ -26,10 +26,12 @@
 #include <asm/hardware/gic.h>
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
+#include <asm/cacheflush.h>
 
 #include <mach/regs-irq.h>
 #include <mach/regs-pmu.h>
 #include <mach/regs-gpio.h>
+#include <mach/pmu.h>
 
 #include <plat/cpu.h>
 #include <plat/clock.h>
@@ -45,6 +47,8 @@
 #include <plat/regs-serial.h>
 
 #include "common.h"
+#define L2_AUX_VAL 0x7C470001
+#define L2_AUX_MASK 0xC200ffff
 
 static const char name_exynos4210[] = "EXYNOS4210";
 static const char name_exynos4212[] = "EXYNOS4212";
@@ -173,7 +177,12 @@ static struct map_desc exynos4_iodesc[] __initdata = {
         }, {
                 .virtual        = (unsigned long)S5P_VA_DMC0,
                 .pfn            = __phys_to_pfn(EXYNOS4_PA_DMC0),
-                .length         = SZ_4K,
+                .length         = SZ_64K,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = (unsigned long)S5P_VA_DMC1,
+                .pfn            = __phys_to_pfn(EXYNOS4_PA_DMC1),
+                .length         = SZ_64K,
                 .type           = MT_DEVICE,
         }, {
                 .virtual        = (unsigned long)S3C_VA_USB_HSPHY,
@@ -201,14 +210,6 @@ static struct map_desc exynos4_iodesc1[] __initdata = {
         },
 };
 
-static void exynos_idle(void)
-{
-        if (!need_resched())
-                cpu_do_idle();
-
-        local_irq_enable();
-}
-
 void exynos4_restart(char mode, const char *cmd)
 {
         __raw_writel(0x1, S5P_SWRESET);
@@ -441,23 +442,48 @@ core_initcall(exynos4_core_init);
 #ifdef CONFIG_CACHE_L2X0
 static int __init exynos4_l2x0_cache_init(void)
 {
-        /* TAG, Data Latency Control: 2cycle */
-        __raw_writel(0x110, S5P_VA_L2CC + L2X0_TAG_LATENCY_CTRL);
+        int ret;
+        ret = l2x0_of_init(L2_AUX_VAL, L2_AUX_MASK);
+        if (!ret) {
+                l2x0_regs_phys = virt_to_phys(&l2x0_saved_regs);
+                clean_dcache_area(&l2x0_regs_phys, sizeof(unsigned long));
+                return 0;
+        }
 
-        if (soc_is_exynos4210())
-                __raw_writel(0x110, S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL);
-        else if (soc_is_exynos4212() || soc_is_exynos4412())
-                __raw_writel(0x120, S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL);
+        if (!(__raw_readl(S5P_VA_L2CC + L2X0_CTRL) & 0x1)) {
+                l2x0_saved_regs.phy_base = EXYNOS4_PA_L2CC;
+                /* TAG, Data Latency Control: 2 cycles */
+                l2x0_saved_regs.tag_latency = 0x110;
+
+                if (soc_is_exynos4212() || soc_is_exynos4412())
+                        l2x0_saved_regs.data_latency = 0x120;
+                else
+                        l2x0_saved_regs.data_latency = 0x110;
+
+                l2x0_saved_regs.prefetch_ctrl = 0x30000007;
+                l2x0_saved_regs.pwr_ctrl =
+                        (L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN);
+
+                l2x0_regs_phys = virt_to_phys(&l2x0_saved_regs);
 
-        /* L2X0 Prefetch Control */
-        __raw_writel(0x30000007, S5P_VA_L2CC + L2X0_PREFETCH_CTRL);
+                __raw_writel(l2x0_saved_regs.tag_latency,
+                                S5P_VA_L2CC + L2X0_TAG_LATENCY_CTRL);
+                __raw_writel(l2x0_saved_regs.data_latency,
+                                S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL);
 
-        /* L2X0 Power Control */
-        __raw_writel(L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN,
-                     S5P_VA_L2CC + L2X0_POWER_CTRL);
+                /* L2X0 Prefetch Control */
+                __raw_writel(l2x0_saved_regs.prefetch_ctrl,
+                                S5P_VA_L2CC + L2X0_PREFETCH_CTRL);
 
-        l2x0_init(S5P_VA_L2CC, 0x7C470001, 0xC200ffff);
+                /* L2X0 Power Control */
+                __raw_writel(l2x0_saved_regs.pwr_ctrl,
+                                S5P_VA_L2CC + L2X0_POWER_CTRL);
 
+                clean_dcache_area(&l2x0_regs_phys, sizeof(unsigned long));
+                clean_dcache_area(&l2x0_saved_regs, sizeof(struct l2x0_regs));
+        }
+
+        l2x0_init(S5P_VA_L2CC, L2_AUX_VAL, L2_AUX_MASK);
         return 0;
 }
 
@@ -467,10 +493,6 @@ early_initcall(exynos4_l2x0_cache_init);
 int __init exynos_init(void)
 {
         printk(KERN_INFO "EXYNOS: Initializing architecture\n");
-
-        /* set idle function */
-        pm_idle = exynos_idle;
-
         return device_register(&exynos4_dev);
 }
 
@@ -673,7 +695,7 @@ static void exynos4_irq_eint0_15(unsigned int irq, struct irq_desc *desc)
         chained_irq_exit(chip, desc);
 }
 
-int __init exynos4_init_irq_eint(void)
+static int __init exynos4_init_irq_eint(void)
 {
         int irq;
 
diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h
index 1ac49de0f39..8c1efe692c2 100644
--- a/arch/arm/mach-exynos/common.h
+++ b/arch/arm/mach-exynos/common.h
@@ -15,12 +15,21 @@
 void exynos_init_io(struct map_desc *mach_desc, int size);
 void exynos4_init_irq(void);
 
+#ifdef CONFIG_ARCH_EXYNOS4
 void exynos4_register_clocks(void);
 void exynos4_setup_clocks(void);
 
 void exynos4210_register_clocks(void);
 void exynos4212_register_clocks(void);
 
+#else
+#define exynos4_register_clocks()
+#define exynos4_setup_clocks()
+
+#define exynos4210_register_clocks()
+#define exynos4212_register_clocks()
+#endif
+
 void exynos4_restart(char mode, const char *cmd);
 
 extern struct sys_timer exynos4_timer;
diff --git a/arch/arm/mach-exynos/cpuidle.c b/arch/arm/mach-exynos/cpuidle.c
index 4ebb382c597..33ab4e7558a 100644
--- a/arch/arm/mach-exynos/cpuidle.c
+++ b/arch/arm/mach-exynos/cpuidle.c
@@ -11,25 +11,53 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/cpuidle.h>
+#include <linux/cpu_pm.h>
 #include <linux/io.h>
 #include <linux/export.h>
 #include <linux/time.h>
 
 #include <asm/proc-fns.h>
+#include <asm/smp_scu.h>
+#include <asm/suspend.h>
+#include <asm/unified.h>
+#include <mach/regs-pmu.h>
+#include <mach/pmu.h>
+
+#include <plat/cpu.h>
+
+#define REG_DIRECTGO_ADDR       (samsung_rev() == EXYNOS4210_REV_1_1 ? \
+                        S5P_INFORM7 : (samsung_rev() == EXYNOS4210_REV_1_0 ? \
+                        (S5P_VA_SYSRAM + 0x24) : S5P_INFORM0))
+#define REG_DIRECTGO_FLAG       (samsung_rev() == EXYNOS4210_REV_1_1 ? \
+                        S5P_INFORM6 : (samsung_rev() == EXYNOS4210_REV_1_0 ? \
+                        (S5P_VA_SYSRAM + 0x20) : S5P_INFORM1))
+
+#define S5P_CHECK_AFTR          0xFCBA0D10
 
 static int exynos4_enter_idle(struct cpuidle_device *dev,
                         struct cpuidle_driver *drv,
                               int index);
+static int exynos4_enter_lowpower(struct cpuidle_device *dev,
+                                struct cpuidle_driver *drv,
+                                int index);
 
-static struct cpuidle_state exynos4_cpuidle_set[] = {
+static struct cpuidle_state exynos4_cpuidle_set[] __initdata = {
         [0] = {
                 .enter                  = exynos4_enter_idle,
                 .exit_latency           = 1,
                 .target_residency       = 100000,
                 .flags                  = CPUIDLE_FLAG_TIME_VALID,
-                .name                   = "IDLE",
+                .name                   = "C0",
                 .desc                   = "ARM clock gating(WFI)",
         },
+        [1] = {
+                .enter                  = exynos4_enter_lowpower,
+                .exit_latency           = 300,
+                .target_residency       = 100000,
+                .flags                  = CPUIDLE_FLAG_TIME_VALID,
+                .name                   = "C1",
+                .desc                   = "ARM power down",
+        },
 };
 
 static DEFINE_PER_CPU(struct cpuidle_device, exynos4_cpuidle_device);
@@ -39,9 +67,102 @@ static struct cpuidle_driver exynos4_idle_driver = {
         .owner          = THIS_MODULE,
 };
 
+/* Ext-GIC nIRQ/nFIQ is the only wakeup source in AFTR */
+static void exynos4_set_wakeupmask(void)
+{
+        __raw_writel(0x0000ff3e, S5P_WAKEUP_MASK);
+}
+
+static unsigned int g_pwr_ctrl, g_diag_reg;
+
+static void save_cpu_arch_register(void)
+{
+        /*read power control register*/
+        asm("mrc p15, 0, %0, c15, c0, 0" : "=r"(g_pwr_ctrl) : : "cc");
+        /*read diagnostic register*/
+        asm("mrc p15, 0, %0, c15, c0, 1" : "=r"(g_diag_reg) : : "cc");
+        return;
+}
+
+static void restore_cpu_arch_register(void)
+{
+        /*write power control register*/
+        asm("mcr p15, 0, %0, c15, c0, 0" : : "r"(g_pwr_ctrl) : "cc");
+        /*write diagnostic register*/
+        asm("mcr p15, 0, %0, c15, c0, 1" : : "r"(g_diag_reg) : "cc");
+        return;
+}
+
+static int idle_finisher(unsigned long flags)
+{
+        cpu_do_idle();
+        return 1;
+}
+
+static int exynos4_enter_core0_aftr(struct cpuidle_device *dev,
+                                struct cpuidle_driver *drv,
+                                int index)
+{
+        struct timeval before, after;
+        int idle_time;
+        unsigned long tmp;
+
+        local_irq_disable();
+        do_gettimeofday(&before);
+
+        exynos4_set_wakeupmask();
+
+        /* Set value of power down register for aftr mode */
+        exynos4_sys_powerdown_conf(SYS_AFTR);
+
+        __raw_writel(virt_to_phys(s3c_cpu_resume), REG_DIRECTGO_ADDR);
+        __raw_writel(S5P_CHECK_AFTR, REG_DIRECTGO_FLAG);
+
+        save_cpu_arch_register();
+
+        /* Setting Central Sequence Register for power down mode */
+        tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
+        tmp &= ~S5P_CENTRAL_LOWPWR_CFG;
+        __raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
+
+        cpu_pm_enter();
+        cpu_suspend(0, idle_finisher);
+
+#ifdef CONFIG_SMP
+        scu_enable(S5P_VA_SCU);
+#endif
+        cpu_pm_exit();
+
+        restore_cpu_arch_register();
+
+        /*
+         * If PMU failed while entering sleep mode, WFI will be
+         * ignored by PMU and then exiting cpu_do_idle().
+         * S5P_CENTRAL_LOWPWR_CFG bit will not be set automatically
+         * in this situation.
+         */
+        tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
+        if (!(tmp & S5P_CENTRAL_LOWPWR_CFG)) {
+                tmp |= S5P_CENTRAL_LOWPWR_CFG;
+                __raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
+        }
+
+        /* Clear wakeup state register */
+        __raw_writel(0x0, S5P_WAKEUP_STAT);
+
+        do_gettimeofday(&after);
+
+        local_irq_enable();
+        idle_time = (after.tv_sec - before.tv_sec) * USEC_PER_SEC +
+                    (after.tv_usec - before.tv_usec);
+
+        dev->last_residency = idle_time;
+        return index;
+}
+
 static int exynos4_enter_idle(struct cpuidle_device *dev,
                                 struct cpuidle_driver *drv,
-                              int index)
+                                int index)
 {
         struct timeval before, after;
         int idle_time;
@@ -60,6 +181,22 @@ static int exynos4_enter_idle(struct cpuidle_device *dev,
         return index;
 }
 
+static int exynos4_enter_lowpower(struct cpuidle_device *dev,
+                                struct cpuidle_driver *drv,
+                                int index)
+{
+        int new_index = index;
+
+        /* This mode only can be entered when other core's are offline */
+        if (num_online_cpus() > 1)
+                new_index = drv->safe_state_index;
+
+        if (new_index == 0)
+                return exynos4_enter_idle(dev, drv, new_index);
+        else
+                return exynos4_enter_core0_aftr(dev, drv, new_index);
+}
+
 static int __init exynos4_init_cpuidle(void)
 {
         int i, max_cpuidle_state, cpu_id;
@@ -74,19 +211,25 @@ static int __init exynos4_init_cpuidle(void)
                 memcpy(&drv->states[i], &exynos4_cpuidle_set[i],
                                 sizeof(struct cpuidle_state));
         }
+        drv->safe_state_index = 0;
         cpuidle_register_driver(&exynos4_idle_driver);
 
         for_each_cpu(cpu_id, cpu_online_mask) {
                 device = &per_cpu(exynos4_cpuidle_device, cpu_id);
                 device->cpu = cpu_id;
 
-                device->state_count = drv->state_count;
+                if (cpu_id == 0)
+                        device->state_count = (sizeof(exynos4_cpuidle_set) /
+                                               sizeof(struct cpuidle_state));
+                else
+                        device->state_count = 1;        /* Support IDLE only */
 
                 if (cpuidle_register_device(device)) {
                         printk(KERN_ERR "CPUidle register device failed\n,");
                         return -EIO;
                 }
         }
+
         return 0;
 }
 device_initcall(exynos4_init_cpuidle);
diff --git a/arch/arm/mach-exynos/dma.c b/arch/arm/mach-exynos/dma.c
index b10fcd270f0..13607c4328b 100644
--- a/arch/arm/mach-exynos/dma.c
+++ b/arch/arm/mach-exynos/dma.c
@@ -29,6 +29,7 @@
 #include <asm/irq.h>
 #include <plat/devs.h>
 #include <plat/irqs.h>
+#include <plat/cpu.h>
 
 #include <mach/map.h>
 #include <mach/irqs.h>
@@ -36,7 +37,7 @@
 
 static u64 dma_dmamask = DMA_BIT_MASK(32);
 
-u8 pdma0_peri[] = {
+static u8 exynos4210_pdma0_peri[] = {
         DMACH_PCM0_RX,
         DMACH_PCM0_TX,
         DMACH_PCM2_RX,
@@ -69,28 +70,47 @@ u8 pdma0_peri[] = {
         DMACH_AC97_PCMOUT,
 };
 
-struct dma_pl330_platdata exynos4_pdma0_pdata = {
-        .nr_valid_peri = ARRAY_SIZE(pdma0_peri),
-        .peri_id = pdma0_peri,
+static u8 exynos4212_pdma0_peri[] = {
+        DMACH_PCM0_RX,
+        DMACH_PCM0_TX,
+        DMACH_PCM2_RX,
+        DMACH_PCM2_TX,
+        DMACH_MIPI_HSI0,
+        DMACH_MIPI_HSI1,
+        DMACH_SPI0_RX,
+        DMACH_SPI0_TX,
+        DMACH_SPI2_RX,
+        DMACH_SPI2_TX,
+        DMACH_I2S0S_TX,
+        DMACH_I2S0_RX,
+        DMACH_I2S0_TX,
+        DMACH_I2S2_RX,
+        DMACH_I2S2_TX,
+        DMACH_UART0_RX,
+        DMACH_UART0_TX,
+        DMACH_UART2_RX,
+        DMACH_UART2_TX,
+        DMACH_UART4_RX,
+        DMACH_UART4_TX,
+        DMACH_SLIMBUS0_RX,
+        DMACH_SLIMBUS0_TX,
+        DMACH_SLIMBUS2_RX,
+        DMACH_SLIMBUS2_TX,
+        DMACH_SLIMBUS4_RX,
+        DMACH_SLIMBUS4_TX,
+        DMACH_AC97_MICIN,
+        DMACH_AC97_PCMIN,
+        DMACH_AC97_PCMOUT,
+        DMACH_MIPI_HSI4,
+        DMACH_MIPI_HSI5,
 };
 
-struct amba_device exynos4_device_pdma0 = {
-        .dev = {
-                .init_name = "dma-pl330.0",
-                .dma_mask = &dma_dmamask,
-                .coherent_dma_mask = DMA_BIT_MASK(32),
-                .platform_data = &exynos4_pdma0_pdata,
-        },
-        .res = {
-                .start = EXYNOS4_PA_PDMA0,
-                .end = EXYNOS4_PA_PDMA0 + SZ_4K,
-                .flags = IORESOURCE_MEM,
-        },
-        .irq = {IRQ_PDMA0, NO_IRQ},
-        .periphid = 0x00041330,
-};
+struct dma_pl330_platdata exynos4_pdma0_pdata;
+
+static AMBA_AHB_DEVICE(exynos4_pdma0, "dma-pl330.0", 0x00041330,
+        EXYNOS4_PA_PDMA0, {IRQ_PDMA0}, &exynos4_pdma0_pdata);
 
-u8 pdma1_peri[] = {
+static u8 exynos4210_pdma1_peri[] = {
         DMACH_PCM0_RX,
         DMACH_PCM0_TX,
         DMACH_PCM1_RX,
@@ -118,39 +138,94 @@ u8 pdma1_peri[] = {
         DMACH_SLIMBUS5_TX,
 };
 
-struct dma_pl330_platdata exynos4_pdma1_pdata = {
-        .nr_valid_peri = ARRAY_SIZE(pdma1_peri),
-        .peri_id = pdma1_peri,
+static u8 exynos4212_pdma1_peri[] = {
+        DMACH_PCM0_RX,
+        DMACH_PCM0_TX,
+        DMACH_PCM1_RX,
+        DMACH_PCM1_TX,
+        DMACH_MIPI_HSI2,
+        DMACH_MIPI_HSI3,
+        DMACH_SPI1_RX,
+        DMACH_SPI1_TX,
+        DMACH_I2S0S_TX,
+        DMACH_I2S0_RX,
+        DMACH_I2S0_TX,
+        DMACH_I2S1_RX,
+        DMACH_I2S1_TX,
+        DMACH_UART0_RX,
+        DMACH_UART0_TX,
+        DMACH_UART1_RX,
+        DMACH_UART1_TX,
+        DMACH_UART3_RX,
+        DMACH_UART3_TX,
+        DMACH_SLIMBUS1_RX,
+        DMACH_SLIMBUS1_TX,
+        DMACH_SLIMBUS3_RX,
+        DMACH_SLIMBUS3_TX,
+        DMACH_SLIMBUS5_RX,
+        DMACH_SLIMBUS5_TX,
+        DMACH_SLIMBUS0AUX_RX,
+        DMACH_SLIMBUS0AUX_TX,
+        DMACH_SPDIF,
+        DMACH_MIPI_HSI6,
+        DMACH_MIPI_HSI7,
 };
 
-struct amba_device exynos4_device_pdma1 = {
-        .dev = {
-                .init_name = "dma-pl330.1",
-                .dma_mask = &dma_dmamask,
-                .coherent_dma_mask = DMA_BIT_MASK(32),
-                .platform_data = &exynos4_pdma1_pdata,
-        },
-        .res = {
-                .start = EXYNOS4_PA_PDMA1,
-                .end = EXYNOS4_PA_PDMA1 + SZ_4K,
-                .flags = IORESOURCE_MEM,
-        },
-        .irq = {IRQ_PDMA1, NO_IRQ},
-        .periphid = 0x00041330,
+static struct dma_pl330_platdata exynos4_pdma1_pdata;
+
+static AMBA_AHB_DEVICE(exynos4_pdma1,  "dma-pl330.1", 0x00041330,
+        EXYNOS4_PA_PDMA1, {IRQ_PDMA1}, &exynos4_pdma1_pdata);
+
+static u8 mdma_peri[] = {
+        DMACH_MTOM_0,
+        DMACH_MTOM_1,
+        DMACH_MTOM_2,
+        DMACH_MTOM_3,
+        DMACH_MTOM_4,
+        DMACH_MTOM_5,
+        DMACH_MTOM_6,
+        DMACH_MTOM_7,
+};
+
+static struct dma_pl330_platdata exynos4_mdma1_pdata = {
+        .nr_valid_peri = ARRAY_SIZE(mdma_peri),
+        .peri_id = mdma_peri,
 };
 
+static AMBA_AHB_DEVICE(exynos4_mdma1,  "dma-pl330.2", 0x00041330,
+        EXYNOS4_PA_MDMA1, {IRQ_MDMA1}, &exynos4_mdma1_pdata);
+
 static int __init exynos4_dma_init(void)
 {
         if (of_have_populated_dt())
                 return 0;
 
+        if (soc_is_exynos4210()) {
+                exynos4_pdma0_pdata.nr_valid_peri =
+                        ARRAY_SIZE(exynos4210_pdma0_peri);
+                exynos4_pdma0_pdata.peri_id = exynos4210_pdma0_peri;
+                exynos4_pdma1_pdata.nr_valid_peri =
+                        ARRAY_SIZE(exynos4210_pdma1_peri);
+                exynos4_pdma1_pdata.peri_id = exynos4210_pdma1_peri;
+        } else if (soc_is_exynos4212() || soc_is_exynos4412()) {
+                exynos4_pdma0_pdata.nr_valid_peri =
+                        ARRAY_SIZE(exynos4212_pdma0_peri);
+                exynos4_pdma0_pdata.peri_id = exynos4212_pdma0_peri;
+                exynos4_pdma1_pdata.nr_valid_peri =
+                        ARRAY_SIZE(exynos4212_pdma1_peri);
+                exynos4_pdma1_pdata.peri_id = exynos4212_pdma1_peri;
+        }
+
         dma_cap_set(DMA_SLAVE, exynos4_pdma0_pdata.cap_mask);
         dma_cap_set(DMA_CYCLIC, exynos4_pdma0_pdata.cap_mask);
-        amba_device_register(&exynos4_device_pdma0, &iomem_resource);
+        amba_device_register(&exynos4_pdma0_device, &iomem_resource);
 
         dma_cap_set(DMA_SLAVE, exynos4_pdma1_pdata.cap_mask);
         dma_cap_set(DMA_CYCLIC, exynos4_pdma1_pdata.cap_mask);
-        amba_device_register(&exynos4_device_pdma1, &iomem_resource);
+        amba_device_register(&exynos4_pdma1_device, &iomem_resource);
+
+        dma_cap_set(DMA_MEMCPY, exynos4_mdma1_pdata.cap_mask);
+        amba_device_register(&exynos4_mdma1_device, &iomem_resource);
 
         return 0;
 }
diff --git a/arch/arm/mach-exynos/include/mach/cpufreq.h b/arch/arm/mach-exynos/include/mach/cpufreq.h
index 3df27f2d503..7517c3f417a 100644
--- a/arch/arm/mach-exynos/include/mach/cpufreq.h
+++ b/arch/arm/mach-exynos/include/mach/cpufreq.h
@@ -32,3 +32,5 @@ struct exynos_dvfs_info {
 };
 
 extern int exynos4210_cpufreq_init(struct exynos_dvfs_info *);
+extern int exynos4x12_cpufreq_init(struct exynos_dvfs_info *);
+extern int exynos5250_cpufreq_init(struct exynos_dvfs_info *);
diff --git a/arch/arm/mach-exynos/include/mach/entry-macro.S b/arch/arm/mach-exynos/include/mach/entry-macro.S
deleted file mode 100644
index 3ba4f547534..00000000000
--- a/arch/arm/mach-exynos/include/mach/entry-macro.S
+++ /dev/null
@@ -1,16 +0,0 @@
-/* arch/arm/mach-exynos4/include/mach/entry-macro.S
- *
- * Cloned from arch/arm/mach-realview/include/mach/entry-macro.S
- *
- * Low-level IRQ helper macros for EXYNOS4 platforms
- *
- * This file is licensed under  the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
-*/
-
-                .macro  disable_fiq
-                .endm
-
-                .macro  arch_ret_to_user, tmp1, tmp2
-                .endm
diff --git a/arch/arm/mach-exynos/include/mach/exynos4-clock.h b/arch/arm/mach-exynos/include/mach/exynos4-clock.h
deleted file mode 100644
index a07fcbf5525..00000000000
--- a/arch/arm/mach-exynos/include/mach/exynos4-clock.h
+++ /dev/null
@@ -1,43 +0,0 @@
-/*
- * linux/arch/arm/mach-exynos4/include/mach/exynos4-clock.h
- *
- * Copyright (c) 2011 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com
- *
- * Header file for exynos4 clock support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __ASM_ARCH_CLOCK_H
-#define __ASM_ARCH_CLOCK_H __FILE__
-
-#include <linux/clk.h>
-
-extern struct clk clk_sclk_hdmi27m;
-extern struct clk clk_sclk_usbphy0;
-extern struct clk clk_sclk_usbphy1;
-extern struct clk clk_sclk_hdmiphy;
-
-extern struct clksrc_clk clk_sclk_apll;
-extern struct clksrc_clk clk_mout_mpll;
-extern struct clksrc_clk clk_aclk_133;
-extern struct clksrc_clk clk_mout_epll;
-extern struct clksrc_clk clk_sclk_vpll;
-
-extern struct clk *clkset_corebus_list[];
-extern struct clksrc_sources clkset_mout_corebus;
-
-extern struct clk *clkset_aclk_top_list[];
-extern struct clksrc_sources clkset_aclk;
-
-extern struct clk *clkset_group_list[];
-extern struct clksrc_sources clkset_group;
-
-extern int exynos4_clksrc_mask_fsys_ctrl(struct clk *clk, int enable);
-extern int exynos4_clk_ip_fsys_ctrl(struct clk *clk, int enable);
-extern int exynos4_clk_ip_lcd1_ctrl(struct clk *clk, int enable);
-
-#endif /* __ASM_ARCH_CLOCK_H */
diff --git a/arch/arm/mach-exynos/include/mach/irqs.h b/arch/arm/mach-exynos/include/mach/irqs.h
index f77bce04789..1d401c95783 100644
--- a/arch/arm/mach-exynos/include/mach/irqs.h
+++ b/arch/arm/mach-exynos/include/mach/irqs.h
@@ -43,6 +43,8 @@
 #define IRQ_EINT15              IRQ_SPI(31)
 #define IRQ_EINT16_31           IRQ_SPI(32)
 
+#define IRQ_MDMA0               IRQ_SPI(33)
+#define IRQ_MDMA1               IRQ_SPI(34)
 #define IRQ_PDMA0               IRQ_SPI(35)
 #define IRQ_PDMA1               IRQ_SPI(36)
 #define IRQ_TIMER0_VIC          IRQ_SPI(37)
diff --git a/arch/arm/mach-exynos/include/mach/map.h b/arch/arm/mach-exynos/include/mach/map.h
index c754a22a2bb..609127df9b0 100644
--- a/arch/arm/mach-exynos/include/mach/map.h
+++ b/arch/arm/mach-exynos/include/mach/map.h
@@ -31,6 +31,10 @@
 #define EXYNOS4_PA_FIMC2                0x11820000
 #define EXYNOS4_PA_FIMC3                0x11830000
 
+#define EXYNOS4_PA_JPEG                 0x11840000
+
+#define EXYNOS4_PA_G2D                  0x12800000
+
 #define EXYNOS4_PA_I2S0                 0x03830000
 #define EXYNOS4_PA_I2S1                 0xE3100000
 #define EXYNOS4_PA_I2S2                 0xE2A00000
@@ -57,6 +61,7 @@
 #define EXYNOS4_PA_KEYPAD               0x100A0000
 
 #define EXYNOS4_PA_DMC0                 0x10400000
+#define EXYNOS4_PA_DMC1                 0x10410000
 
 #define EXYNOS4_PA_COMBINER             0x10440000
 
@@ -67,7 +72,8 @@
 #define EXYNOS4_PA_TWD                  0x10500600
 #define EXYNOS4_PA_L2CC                 0x10502000
 
-#define EXYNOS4_PA_MDMA                 0x10810000
+#define EXYNOS4_PA_MDMA0                0x10810000
+#define EXYNOS4_PA_MDMA1                0x12840000
 #define EXYNOS4_PA_PDMA0                0x12680000
 #define EXYNOS4_PA_PDMA1                0x12690000
 
@@ -162,6 +168,8 @@
 #define S5P_PA_FIMC1                    EXYNOS4_PA_FIMC1
 #define S5P_PA_FIMC2                    EXYNOS4_PA_FIMC2
 #define S5P_PA_FIMC3                    EXYNOS4_PA_FIMC3
+#define S5P_PA_JPEG                     EXYNOS4_PA_JPEG
+#define S5P_PA_G2D                      EXYNOS4_PA_G2D
 #define S5P_PA_FIMD0                    EXYNOS4_PA_FIMD0
 #define S5P_PA_HDMI                     EXYNOS4_PA_HDMI
 #define S5P_PA_IIC_HDMIPHY              EXYNOS4_PA_IIC_HDMIPHY
diff --git a/arch/arm/mach-exynos/include/mach/pmu.h b/arch/arm/mach-exynos/include/mach/pmu.h
index 632dd563013..e76b7faba66 100644
--- a/arch/arm/mach-exynos/include/mach/pmu.h
+++ b/arch/arm/mach-exynos/include/mach/pmu.h
@@ -22,11 +22,13 @@ enum sys_powerdown {
         NUM_SYS_POWERDOWN,
 };
 
+extern unsigned long l2x0_regs_phys;
 struct exynos4_pmu_conf {
         void __iomem *reg;
         unsigned int val[NUM_SYS_POWERDOWN];
 };
 
 extern void exynos4_sys_powerdown_conf(enum sys_powerdown mode);
+extern void s3c_cpu_resume(void);
 
 #endif /* __ASM_ARCH_PMU_H */
diff --git a/arch/arm/mach-exynos/include/mach/regs-clock.h b/arch/arm/mach-exynos/include/mach/regs-clock.h
index 6c37ebe9482..1e4abd64a54 100644
--- a/arch/arm/mach-exynos/include/mach/regs-clock.h
+++ b/arch/arm/mach-exynos/include/mach/regs-clock.h
@@ -16,195 +16,247 @@
 #include <plat/cpu.h>
 #include <mach/map.h>
 
-#define S5P_CLKREG(x)                   (S5P_VA_CMU + (x))
-
-#define S5P_CLKDIV_LEFTBUS              S5P_CLKREG(0x04500)
-#define S5P_CLKDIV_STAT_LEFTBUS         S5P_CLKREG(0x04600)
-#define S5P_CLKGATE_IP_LEFTBUS          S5P_CLKREG(0x04800)
-
-#define S5P_CLKDIV_RIGHTBUS             S5P_CLKREG(0x08500)
-#define S5P_CLKDIV_STAT_RIGHTBUS        S5P_CLKREG(0x08600)
-#define S5P_CLKGATE_IP_RIGHTBUS         S5P_CLKREG(0x08800)
-
-#define S5P_EPLL_LOCK                   S5P_CLKREG(0x0C010)
-#define S5P_VPLL_LOCK                   S5P_CLKREG(0x0C020)
-
-#define S5P_EPLL_CON0                   S5P_CLKREG(0x0C110)
-#define S5P_EPLL_CON1                   S5P_CLKREG(0x0C114)
-#define S5P_VPLL_CON0                   S5P_CLKREG(0x0C120)
-#define S5P_VPLL_CON1                   S5P_CLKREG(0x0C124)
-
-#define S5P_CLKSRC_TOP0                 S5P_CLKREG(0x0C210)
-#define S5P_CLKSRC_TOP1                 S5P_CLKREG(0x0C214)
-#define S5P_CLKSRC_CAM                  S5P_CLKREG(0x0C220)
-#define S5P_CLKSRC_TV                   S5P_CLKREG(0x0C224)
-#define S5P_CLKSRC_MFC                  S5P_CLKREG(0x0C228)
-#define S5P_CLKSRC_G3D                  S5P_CLKREG(0x0C22C)
-#define S5P_CLKSRC_IMAGE                S5P_CLKREG(0x0C230)
-#define S5P_CLKSRC_LCD0                 S5P_CLKREG(0x0C234)
-#define S5P_CLKSRC_MAUDIO               S5P_CLKREG(0x0C23C)
-#define S5P_CLKSRC_FSYS                 S5P_CLKREG(0x0C240)
-#define S5P_CLKSRC_PERIL0               S5P_CLKREG(0x0C250)
-#define S5P_CLKSRC_PERIL1               S5P_CLKREG(0x0C254)
-
-#define S5P_CLKSRC_MASK_TOP             S5P_CLKREG(0x0C310)
-#define S5P_CLKSRC_MASK_CAM             S5P_CLKREG(0x0C320)
-#define S5P_CLKSRC_MASK_TV              S5P_CLKREG(0x0C324)
-#define S5P_CLKSRC_MASK_LCD0            S5P_CLKREG(0x0C334)
-#define S5P_CLKSRC_MASK_MAUDIO          S5P_CLKREG(0x0C33C)
-#define S5P_CLKSRC_MASK_FSYS            S5P_CLKREG(0x0C340)
-#define S5P_CLKSRC_MASK_PERIL0          S5P_CLKREG(0x0C350)
-#define S5P_CLKSRC_MASK_PERIL1          S5P_CLKREG(0x0C354)
-
-#define S5P_CLKDIV_TOP                  S5P_CLKREG(0x0C510)
-#define S5P_CLKDIV_CAM                  S5P_CLKREG(0x0C520)
-#define S5P_CLKDIV_TV                   S5P_CLKREG(0x0C524)
-#define S5P_CLKDIV_MFC                  S5P_CLKREG(0x0C528)
-#define S5P_CLKDIV_G3D                  S5P_CLKREG(0x0C52C)
-#define S5P_CLKDIV_IMAGE                S5P_CLKREG(0x0C530)
-#define S5P_CLKDIV_LCD0                 S5P_CLKREG(0x0C534)
-#define S5P_CLKDIV_MAUDIO               S5P_CLKREG(0x0C53C)
-#define S5P_CLKDIV_FSYS0                S5P_CLKREG(0x0C540)
-#define S5P_CLKDIV_FSYS1                S5P_CLKREG(0x0C544)
-#define S5P_CLKDIV_FSYS2                S5P_CLKREG(0x0C548)
-#define S5P_CLKDIV_FSYS3                S5P_CLKREG(0x0C54C)
-#define S5P_CLKDIV_PERIL0               S5P_CLKREG(0x0C550)
-#define S5P_CLKDIV_PERIL1               S5P_CLKREG(0x0C554)
-#define S5P_CLKDIV_PERIL2               S5P_CLKREG(0x0C558)
-#define S5P_CLKDIV_PERIL3               S5P_CLKREG(0x0C55C)
-#define S5P_CLKDIV_PERIL4               S5P_CLKREG(0x0C560)
-#define S5P_CLKDIV_PERIL5               S5P_CLKREG(0x0C564)
-#define S5P_CLKDIV2_RATIO               S5P_CLKREG(0x0C580)
-
-#define S5P_CLKDIV_STAT_TOP             S5P_CLKREG(0x0C610)
-
-#define S5P_CLKGATE_SCLKCAM             S5P_CLKREG(0x0C820)
-#define S5P_CLKGATE_IP_CAM              S5P_CLKREG(0x0C920)
-#define S5P_CLKGATE_IP_TV               S5P_CLKREG(0x0C924)
-#define S5P_CLKGATE_IP_MFC              S5P_CLKREG(0x0C928)
-#define S5P_CLKGATE_IP_G3D              S5P_CLKREG(0x0C92C)
-#define S5P_CLKGATE_IP_IMAGE            (soc_is_exynos4210() ? \
-                                        S5P_CLKREG(0x0C930) : \
-                                        S5P_CLKREG(0x04930))
-#define S5P_CLKGATE_IP_IMAGE_4210       S5P_CLKREG(0x0C930)
-#define S5P_CLKGATE_IP_IMAGE_4212       S5P_CLKREG(0x04930)
-#define S5P_CLKGATE_IP_LCD0             S5P_CLKREG(0x0C934)
-#define S5P_CLKGATE_IP_FSYS             S5P_CLKREG(0x0C940)
-#define S5P_CLKGATE_IP_GPS              S5P_CLKREG(0x0C94C)
-#define S5P_CLKGATE_IP_PERIL            S5P_CLKREG(0x0C950)
-#define S5P_CLKGATE_IP_PERIR            (soc_is_exynos4210() ? \
-                                        S5P_CLKREG(0x0C960) : \
-                                        S5P_CLKREG(0x08960))
-#define S5P_CLKGATE_IP_PERIR_4210       S5P_CLKREG(0x0C960)
-#define S5P_CLKGATE_IP_PERIR_4212       S5P_CLKREG(0x08960)
-#define S5P_CLKGATE_BLOCK               S5P_CLKREG(0x0C970)
-
-#define S5P_CLKSRC_MASK_DMC             S5P_CLKREG(0x10300)
-#define S5P_CLKSRC_DMC                  S5P_CLKREG(0x10200)
-#define S5P_CLKDIV_DMC0                 S5P_CLKREG(0x10500)
-#define S5P_CLKDIV_DMC1                 S5P_CLKREG(0x10504)
-#define S5P_CLKDIV_STAT_DMC0            S5P_CLKREG(0x10600)
-#define S5P_CLKGATE_IP_DMC              S5P_CLKREG(0x10900)
-
-#define S5P_APLL_LOCK                   S5P_CLKREG(0x14000)
-#define S5P_MPLL_LOCK                   (soc_is_exynos4210() ? \
-                                        S5P_CLKREG(0x14004) :  \
-                                        S5P_CLKREG(0x10008))
-#define S5P_APLL_CON0                   S5P_CLKREG(0x14100)
-#define S5P_APLL_CON1                   S5P_CLKREG(0x14104)
-#define S5P_MPLL_CON0                   (soc_is_exynos4210() ? \
-                                        S5P_CLKREG(0x14108) : \
-                                        S5P_CLKREG(0x10108))
-#define S5P_MPLL_CON1                   (soc_is_exynos4210() ? \
-                                        S5P_CLKREG(0x1410C) : \
-                                        S5P_CLKREG(0x1010C))
-
-#define S5P_CLKSRC_CPU                  S5P_CLKREG(0x14200)
-#define S5P_CLKMUX_STATCPU              S5P_CLKREG(0x14400)
-
-#define S5P_CLKDIV_CPU                  S5P_CLKREG(0x14500)
-#define S5P_CLKDIV_CPU1                 S5P_CLKREG(0x14504)
-#define S5P_CLKDIV_STATCPU              S5P_CLKREG(0x14600)
-#define S5P_CLKDIV_STATCPU1             S5P_CLKREG(0x14604)
-
-#define S5P_CLKGATE_SCLKCPU             S5P_CLKREG(0x14800)
-#define S5P_CLKGATE_IP_CPU              S5P_CLKREG(0x14900)
-
-#define S5P_APLL_LOCKTIME               (0x1C20)        /* 300us */
-
-#define S5P_APLLCON0_ENABLE_SHIFT       (31)
-#define S5P_APLLCON0_LOCKED_SHIFT       (29)
-#define S5P_APLL_VAL_1000               ((250 << 16) | (6 << 8) | 1)
-#define S5P_APLL_VAL_800                ((200 << 16) | (6 << 8) | 1)
-
-#define S5P_EPLLCON0_ENABLE_SHIFT       (31)
-#define S5P_EPLLCON0_LOCKED_SHIFT       (29)
-
-#define S5P_VPLLCON0_ENABLE_SHIFT       (31)
-#define S5P_VPLLCON0_LOCKED_SHIFT       (29)
-
-#define S5P_CLKSRC_CPU_MUXCORE_SHIFT    (16)
-#define S5P_CLKMUX_STATCPU_MUXCORE_MASK (0x7 << S5P_CLKSRC_CPU_MUXCORE_SHIFT)
-
-#define S5P_CLKDIV_CPU0_CORE_SHIFT      (0)
-#define S5P_CLKDIV_CPU0_CORE_MASK       (0x7 << S5P_CLKDIV_CPU0_CORE_SHIFT)
-#define S5P_CLKDIV_CPU0_COREM0_SHIFT    (4)
-#define S5P_CLKDIV_CPU0_COREM0_MASK     (0x7 << S5P_CLKDIV_CPU0_COREM0_SHIFT)
-#define S5P_CLKDIV_CPU0_COREM1_SHIFT    (8)
-#define S5P_CLKDIV_CPU0_COREM1_MASK     (0x7 << S5P_CLKDIV_CPU0_COREM1_SHIFT)
-#define S5P_CLKDIV_CPU0_PERIPH_SHIFT    (12)
-#define S5P_CLKDIV_CPU0_PERIPH_MASK     (0x7 << S5P_CLKDIV_CPU0_PERIPH_SHIFT)
-#define S5P_CLKDIV_CPU0_ATB_SHIFT       (16)
-#define S5P_CLKDIV_CPU0_ATB_MASK        (0x7 << S5P_CLKDIV_CPU0_ATB_SHIFT)
-#define S5P_CLKDIV_CPU0_PCLKDBG_SHIFT   (20)
-#define S5P_CLKDIV_CPU0_PCLKDBG_MASK    (0x7 << S5P_CLKDIV_CPU0_PCLKDBG_SHIFT)
-#define S5P_CLKDIV_CPU0_APLL_SHIFT      (24)
-#define S5P_CLKDIV_CPU0_APLL_MASK       (0x7 << S5P_CLKDIV_CPU0_APLL_SHIFT)
-
-#define S5P_CLKDIV_DMC0_ACP_SHIFT       (0)
-#define S5P_CLKDIV_DMC0_ACP_MASK        (0x7 << S5P_CLKDIV_DMC0_ACP_SHIFT)
-#define S5P_CLKDIV_DMC0_ACPPCLK_SHIFT   (4)
-#define S5P_CLKDIV_DMC0_ACPPCLK_MASK    (0x7 << S5P_CLKDIV_DMC0_ACPPCLK_SHIFT)
-#define S5P_CLKDIV_DMC0_DPHY_SHIFT      (8)
-#define S5P_CLKDIV_DMC0_DPHY_MASK       (0x7 << S5P_CLKDIV_DMC0_DPHY_SHIFT)
-#define S5P_CLKDIV_DMC0_DMC_SHIFT       (12)
-#define S5P_CLKDIV_DMC0_DMC_MASK        (0x7 << S5P_CLKDIV_DMC0_DMC_SHIFT)
-#define S5P_CLKDIV_DMC0_DMCD_SHIFT      (16)
-#define S5P_CLKDIV_DMC0_DMCD_MASK       (0x7 << S5P_CLKDIV_DMC0_DMCD_SHIFT)
-#define S5P_CLKDIV_DMC0_DMCP_SHIFT      (20)
-#define S5P_CLKDIV_DMC0_DMCP_MASK       (0x7 << S5P_CLKDIV_DMC0_DMCP_SHIFT)
-#define S5P_CLKDIV_DMC0_COPY2_SHIFT     (24)
-#define S5P_CLKDIV_DMC0_COPY2_MASK      (0x7 << S5P_CLKDIV_DMC0_COPY2_SHIFT)
-#define S5P_CLKDIV_DMC0_CORETI_SHIFT    (28)
-#define S5P_CLKDIV_DMC0_CORETI_MASK     (0x7 << S5P_CLKDIV_DMC0_CORETI_SHIFT)
-
-#define S5P_CLKDIV_TOP_ACLK200_SHIFT    (0)
-#define S5P_CLKDIV_TOP_ACLK200_MASK     (0x7 << S5P_CLKDIV_TOP_ACLK200_SHIFT)
-#define S5P_CLKDIV_TOP_ACLK100_SHIFT    (4)
-#define S5P_CLKDIV_TOP_ACLK100_MASK     (0xf << S5P_CLKDIV_TOP_ACLK100_SHIFT)
-#define S5P_CLKDIV_TOP_ACLK160_SHIFT    (8)
-#define S5P_CLKDIV_TOP_ACLK160_MASK     (0x7 << S5P_CLKDIV_TOP_ACLK160_SHIFT)
-#define S5P_CLKDIV_TOP_ACLK133_SHIFT    (12)
-#define S5P_CLKDIV_TOP_ACLK133_MASK     (0x7 << S5P_CLKDIV_TOP_ACLK133_SHIFT)
-#define S5P_CLKDIV_TOP_ONENAND_SHIFT    (16)
-#define S5P_CLKDIV_TOP_ONENAND_MASK     (0x7 << S5P_CLKDIV_TOP_ONENAND_SHIFT)
-
-#define S5P_CLKDIV_BUS_GDLR_SHIFT       (0)
-#define S5P_CLKDIV_BUS_GDLR_MASK        (0x7 << S5P_CLKDIV_BUS_GDLR_SHIFT)
-#define S5P_CLKDIV_BUS_GPLR_SHIFT       (4)
-#define S5P_CLKDIV_BUS_GPLR_MASK        (0x7 << S5P_CLKDIV_BUS_GPLR_SHIFT)
+#define EXYNOS_CLKREG(x)                        (S5P_VA_CMU + (x))
+
+#define EXYNOS4_CLKDIV_LEFTBUS                  EXYNOS_CLKREG(0x04500)
+#define EXYNOS4_CLKDIV_STAT_LEFTBUS             EXYNOS_CLKREG(0x04600)
+#define EXYNOS4_CLKGATE_IP_LEFTBUS              EXYNOS_CLKREG(0x04800)
+
+#define EXYNOS4_CLKDIV_RIGHTBUS                 EXYNOS_CLKREG(0x08500)
+#define EXYNOS4_CLKDIV_STAT_RIGHTBUS            EXYNOS_CLKREG(0x08600)
+#define EXYNOS4_CLKGATE_IP_RIGHTBUS             EXYNOS_CLKREG(0x08800)
+
+#define EXYNOS4_EPLL_LOCK                       EXYNOS_CLKREG(0x0C010)
+#define EXYNOS4_VPLL_LOCK                       EXYNOS_CLKREG(0x0C020)
+
+#define EXYNOS4_EPLL_CON0                       EXYNOS_CLKREG(0x0C110)
+#define EXYNOS4_EPLL_CON1                       EXYNOS_CLKREG(0x0C114)
+#define EXYNOS4_VPLL_CON0                       EXYNOS_CLKREG(0x0C120)
+#define EXYNOS4_VPLL_CON1                       EXYNOS_CLKREG(0x0C124)
+
+#define EXYNOS4_CLKSRC_TOP0                     EXYNOS_CLKREG(0x0C210)
+#define EXYNOS4_CLKSRC_TOP1                     EXYNOS_CLKREG(0x0C214)
+#define EXYNOS4_CLKSRC_CAM                      EXYNOS_CLKREG(0x0C220)
+#define EXYNOS4_CLKSRC_TV                       EXYNOS_CLKREG(0x0C224)
+#define EXYNOS4_CLKSRC_MFC                      EXYNOS_CLKREG(0x0C228)
+#define EXYNOS4_CLKSRC_G3D                      EXYNOS_CLKREG(0x0C22C)
+#define EXYNOS4_CLKSRC_IMAGE                    EXYNOS_CLKREG(0x0C230)
+#define EXYNOS4_CLKSRC_LCD0                     EXYNOS_CLKREG(0x0C234)
+#define EXYNOS4_CLKSRC_MAUDIO                   EXYNOS_CLKREG(0x0C23C)
+#define EXYNOS4_CLKSRC_FSYS                     EXYNOS_CLKREG(0x0C240)
+#define EXYNOS4_CLKSRC_PERIL0                   EXYNOS_CLKREG(0x0C250)
+#define EXYNOS4_CLKSRC_PERIL1                   EXYNOS_CLKREG(0x0C254)
+
+#define EXYNOS4_CLKSRC_MASK_TOP                 EXYNOS_CLKREG(0x0C310)
+#define EXYNOS4_CLKSRC_MASK_CAM                 EXYNOS_CLKREG(0x0C320)
+#define EXYNOS4_CLKSRC_MASK_TV                  EXYNOS_CLKREG(0x0C324)
+#define EXYNOS4_CLKSRC_MASK_LCD0                EXYNOS_CLKREG(0x0C334)
+#define EXYNOS4_CLKSRC_MASK_MAUDIO              EXYNOS_CLKREG(0x0C33C)
+#define EXYNOS4_CLKSRC_MASK_FSYS                EXYNOS_CLKREG(0x0C340)
+#define EXYNOS4_CLKSRC_MASK_PERIL0              EXYNOS_CLKREG(0x0C350)
+#define EXYNOS4_CLKSRC_MASK_PERIL1              EXYNOS_CLKREG(0x0C354)
+
+#define EXYNOS4_CLKDIV_TOP                      EXYNOS_CLKREG(0x0C510)
+#define EXYNOS4_CLKDIV_CAM                      EXYNOS_CLKREG(0x0C520)
+#define EXYNOS4_CLKDIV_TV                       EXYNOS_CLKREG(0x0C524)
+#define EXYNOS4_CLKDIV_MFC                      EXYNOS_CLKREG(0x0C528)
+#define EXYNOS4_CLKDIV_G3D                      EXYNOS_CLKREG(0x0C52C)
+#define EXYNOS4_CLKDIV_IMAGE                    EXYNOS_CLKREG(0x0C530)
+#define EXYNOS4_CLKDIV_LCD0                     EXYNOS_CLKREG(0x0C534)
+#define EXYNOS4_CLKDIV_MAUDIO                   EXYNOS_CLKREG(0x0C53C)
+#define EXYNOS4_CLKDIV_FSYS0                    EXYNOS_CLKREG(0x0C540)
+#define EXYNOS4_CLKDIV_FSYS1                    EXYNOS_CLKREG(0x0C544)
+#define EXYNOS4_CLKDIV_FSYS2                    EXYNOS_CLKREG(0x0C548)
+#define EXYNOS4_CLKDIV_FSYS3                    EXYNOS_CLKREG(0x0C54C)
+#define EXYNOS4_CLKDIV_PERIL0                   EXYNOS_CLKREG(0x0C550)
+#define EXYNOS4_CLKDIV_PERIL1                   EXYNOS_CLKREG(0x0C554)
+#define EXYNOS4_CLKDIV_PERIL2                   EXYNOS_CLKREG(0x0C558)
+#define EXYNOS4_CLKDIV_PERIL3                   EXYNOS_CLKREG(0x0C55C)
+#define EXYNOS4_CLKDIV_PERIL4                   EXYNOS_CLKREG(0x0C560)
+#define EXYNOS4_CLKDIV_PERIL5                   EXYNOS_CLKREG(0x0C564)
+#define EXYNOS4_CLKDIV2_RATIO                   EXYNOS_CLKREG(0x0C580)
+
+#define EXYNOS4_CLKDIV_STAT_TOP                 EXYNOS_CLKREG(0x0C610)
+#define EXYNOS4_CLKDIV_STAT_MFC                 EXYNOS_CLKREG(0x0C628)
+
+#define EXYNOS4_CLKGATE_SCLKCAM                 EXYNOS_CLKREG(0x0C820)
+#define EXYNOS4_CLKGATE_IP_CAM                  EXYNOS_CLKREG(0x0C920)
+#define EXYNOS4_CLKGATE_IP_TV                   EXYNOS_CLKREG(0x0C924)
+#define EXYNOS4_CLKGATE_IP_MFC                  EXYNOS_CLKREG(0x0C928)
+#define EXYNOS4_CLKGATE_IP_G3D                  EXYNOS_CLKREG(0x0C92C)
+#define EXYNOS4_CLKGATE_IP_IMAGE                (soc_is_exynos4210() ? \
+                                                EXYNOS_CLKREG(0x0C930) : \
+                                                EXYNOS_CLKREG(0x04930))
+#define EXYNOS4210_CLKGATE_IP_IMAGE             EXYNOS_CLKREG(0x0C930)
+#define EXYNOS4212_CLKGATE_IP_IMAGE             EXYNOS_CLKREG(0x04930)
+#define EXYNOS4_CLKGATE_IP_LCD0                 EXYNOS_CLKREG(0x0C934)
+#define EXYNOS4_CLKGATE_IP_FSYS                 EXYNOS_CLKREG(0x0C940)
+#define EXYNOS4_CLKGATE_IP_GPS                  EXYNOS_CLKREG(0x0C94C)
+#define EXYNOS4_CLKGATE_IP_PERIL                EXYNOS_CLKREG(0x0C950)
+#define EXYNOS4_CLKGATE_IP_PERIR                (soc_is_exynos4210() ? \
+                                                EXYNOS_CLKREG(0x0C960) : \
+                                                EXYNOS_CLKREG(0x08960))
+#define EXYNOS4210_CLKGATE_IP_PERIR             EXYNOS_CLKREG(0x0C960)
+#define EXYNOS4212_CLKGATE_IP_PERIR             EXYNOS_CLKREG(0x08960)
+#define EXYNOS4_CLKGATE_BLOCK                   EXYNOS_CLKREG(0x0C970)
+
+#define EXYNOS4_CLKSRC_MASK_DMC                 EXYNOS_CLKREG(0x10300)
+#define EXYNOS4_CLKSRC_DMC                      EXYNOS_CLKREG(0x10200)
+#define EXYNOS4_CLKDIV_DMC0                     EXYNOS_CLKREG(0x10500)
+#define EXYNOS4_CLKDIV_DMC1                     EXYNOS_CLKREG(0x10504)
+#define EXYNOS4_CLKDIV_STAT_DMC0                EXYNOS_CLKREG(0x10600)
+#define EXYNOS4_CLKDIV_STAT_DMC1                EXYNOS_CLKREG(0x10604)
+#define EXYNOS4_CLKGATE_IP_DMC                  EXYNOS_CLKREG(0x10900)
+
+#define EXYNOS4_DMC_PAUSE_CTRL                  EXYNOS_CLKREG(0x11094)
+#define EXYNOS4_DMC_PAUSE_ENABLE                (1 << 0)
+
+#define EXYNOS4_APLL_LOCK                       EXYNOS_CLKREG(0x14000)
+#define EXYNOS4_MPLL_LOCK                       (soc_is_exynos4210() ? \
+                                                EXYNOS_CLKREG(0x14004) :  \
+                                                EXYNOS_CLKREG(0x10008))
+#define EXYNOS4_APLL_CON0                       EXYNOS_CLKREG(0x14100)
+#define EXYNOS4_APLL_CON1                       EXYNOS_CLKREG(0x14104)
+#define EXYNOS4_MPLL_CON0                       (soc_is_exynos4210() ? \
+                                                EXYNOS_CLKREG(0x14108) : \
+                                                EXYNOS_CLKREG(0x10108))
+#define EXYNOS4_MPLL_CON1                       (soc_is_exynos4210() ? \
+                                                EXYNOS_CLKREG(0x1410C) : \
+                                                EXYNOS_CLKREG(0x1010C))
+
+#define EXYNOS4_CLKSRC_CPU                      EXYNOS_CLKREG(0x14200)
+#define EXYNOS4_CLKMUX_STATCPU                  EXYNOS_CLKREG(0x14400)
+
+#define EXYNOS4_CLKDIV_CPU                      EXYNOS_CLKREG(0x14500)
+#define EXYNOS4_CLKDIV_CPU1                     EXYNOS_CLKREG(0x14504)
+#define EXYNOS4_CLKDIV_STATCPU                  EXYNOS_CLKREG(0x14600)
+#define EXYNOS4_CLKDIV_STATCPU1                 EXYNOS_CLKREG(0x14604)
+
+#define EXYNOS4_CLKGATE_SCLKCPU                 EXYNOS_CLKREG(0x14800)
+#define EXYNOS4_CLKGATE_IP_CPU                  EXYNOS_CLKREG(0x14900)
+
+#define EXYNOS4_APLL_LOCKTIME                   (0x1C20)        /* 300us */
+
+#define EXYNOS4_APLLCON0_ENABLE_SHIFT           (31)
+#define EXYNOS4_APLLCON0_LOCKED_SHIFT           (29)
+#define EXYNOS4_APLL_VAL_1000                   ((250 << 16) | (6 << 8) | 1)
+#define EXYNOS4_APLL_VAL_800                    ((200 << 16) | (6 << 8) | 1)
+
+#define EXYNOS4_EPLLCON0_ENABLE_SHIFT           (31)
+#define EXYNOS4_EPLLCON0_LOCKED_SHIFT           (29)
+
+#define EXYNOS4_VPLLCON0_ENABLE_SHIFT           (31)
+#define EXYNOS4_VPLLCON0_LOCKED_SHIFT           (29)
+
+#define EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT        (16)
+#define EXYNOS4_CLKMUX_STATCPU_MUXCORE_MASK     (0x7 << EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT)
+
+#define EXYNOS4_CLKDIV_CPU0_CORE_SHIFT          (0)
+#define EXYNOS4_CLKDIV_CPU0_CORE_MASK           (0x7 << EXYNOS4_CLKDIV_CPU0_CORE_SHIFT)
+#define EXYNOS4_CLKDIV_CPU0_COREM0_SHIFT        (4)
+#define EXYNOS4_CLKDIV_CPU0_COREM0_MASK         (0x7 << EXYNOS4_CLKDIV_CPU0_COREM0_SHIFT)
+#define EXYNOS4_CLKDIV_CPU0_COREM1_SHIFT        (8)
+#define EXYNOS4_CLKDIV_CPU0_COREM1_MASK         (0x7 << EXYNOS4_CLKDIV_CPU0_COREM1_SHIFT)
+#define EXYNOS4_CLKDIV_CPU0_PERIPH_SHIFT        (12)
+#define EXYNOS4_CLKDIV_CPU0_PERIPH_MASK         (0x7 << EXYNOS4_CLKDIV_CPU0_PERIPH_SHIFT)
+#define EXYNOS4_CLKDIV_CPU0_ATB_SHIFT           (16)
+#define EXYNOS4_CLKDIV_CPU0_ATB_MASK            (0x7 << EXYNOS4_CLKDIV_CPU0_ATB_SHIFT)
+#define EXYNOS4_CLKDIV_CPU0_PCLKDBG_SHIFT       (20)
+#define EXYNOS4_CLKDIV_CPU0_PCLKDBG_MASK        (0x7 << EXYNOS4_CLKDIV_CPU0_PCLKDBG_SHIFT)
+#define EXYNOS4_CLKDIV_CPU0_APLL_SHIFT          (24)
+#define EXYNOS4_CLKDIV_CPU0_APLL_MASK           (0x7 << EXYNOS4_CLKDIV_CPU0_APLL_SHIFT)
+#define EXYNOS4_CLKDIV_CPU0_CORE2_SHIFT         28
+#define EXYNOS4_CLKDIV_CPU0_CORE2_MASK          (0x7 << EXYNOS4_CLKDIV_CPU0_CORE2_SHIFT)
+
+#define EXYNOS4_CLKDIV_CPU1_COPY_SHIFT          0
+#define EXYNOS4_CLKDIV_CPU1_COPY_MASK           (0x7 << EXYNOS4_CLKDIV_CPU1_COPY_SHIFT)
+#define EXYNOS4_CLKDIV_CPU1_HPM_SHIFT           4
+#define EXYNOS4_CLKDIV_CPU1_HPM_MASK            (0x7 << EXYNOS4_CLKDIV_CPU1_HPM_SHIFT)
+#define EXYNOS4_CLKDIV_CPU1_CORES_SHIFT         8
+#define EXYNOS4_CLKDIV_CPU1_CORES_MASK          (0x7 << EXYNOS4_CLKDIV_CPU1_CORES_SHIFT)
+
+#define EXYNOS4_CLKDIV_DMC0_ACP_SHIFT           (0)
+#define EXYNOS4_CLKDIV_DMC0_ACP_MASK            (0x7 << EXYNOS4_CLKDIV_DMC0_ACP_SHIFT)
+#define EXYNOS4_CLKDIV_DMC0_ACPPCLK_SHIFT       (4)
+#define EXYNOS4_CLKDIV_DMC0_ACPPCLK_MASK        (0x7 << EXYNOS4_CLKDIV_DMC0_ACPPCLK_SHIFT)
+#define EXYNOS4_CLKDIV_DMC0_DPHY_SHIFT          (8)
+#define EXYNOS4_CLKDIV_DMC0_DPHY_MASK           (0x7 << EXYNOS4_CLKDIV_DMC0_DPHY_SHIFT)
+#define EXYNOS4_CLKDIV_DMC0_DMC_SHIFT           (12)
+#define EXYNOS4_CLKDIV_DMC0_DMC_MASK            (0x7 << EXYNOS4_CLKDIV_DMC0_DMC_SHIFT)
+#define EXYNOS4_CLKDIV_DMC0_DMCD_SHIFT          (16)
+#define EXYNOS4_CLKDIV_DMC0_DMCD_MASK           (0x7 << EXYNOS4_CLKDIV_DMC0_DMCD_SHIFT)
+#define EXYNOS4_CLKDIV_DMC0_DMCP_SHIFT          (20)
+#define EXYNOS4_CLKDIV_DMC0_DMCP_MASK           (0x7 << EXYNOS4_CLKDIV_DMC0_DMCP_SHIFT)
+#define EXYNOS4_CLKDIV_DMC0_COPY2_SHIFT         (24)
+#define EXYNOS4_CLKDIV_DMC0_COPY2_MASK          (0x7 << EXYNOS4_CLKDIV_DMC0_COPY2_SHIFT)
+#define EXYNOS4_CLKDIV_DMC0_CORETI_SHIFT        (28)
+#define EXYNOS4_CLKDIV_DMC0_CORETI_MASK         (0x7 << EXYNOS4_CLKDIV_DMC0_CORETI_SHIFT)
+
+#define EXYNOS4_CLKDIV_DMC1_G2D_ACP_SHIFT       (0)
+#define EXYNOS4_CLKDIV_DMC1_G2D_ACP_MASK        (0xf << EXYNOS4_CLKDIV_DMC1_G2D_ACP_SHIFT)
+#define EXYNOS4_CLKDIV_DMC1_C2C_SHIFT           (4)
+#define EXYNOS4_CLKDIV_DMC1_C2C_MASK            (0x7 << EXYNOS4_CLKDIV_DMC1_C2C_SHIFT)
+#define EXYNOS4_CLKDIV_DMC1_PWI_SHIFT           (8)
+#define EXYNOS4_CLKDIV_DMC1_PWI_MASK            (0xf << EXYNOS4_CLKDIV_DMC1_PWI_SHIFT)
+#define EXYNOS4_CLKDIV_DMC1_C2CACLK_SHIFT       (12)
+#define EXYNOS4_CLKDIV_DMC1_C2CACLK_MASK        (0x7 << EXYNOS4_CLKDIV_DMC1_C2CACLK_SHIFT)
+#define EXYNOS4_CLKDIV_DMC1_DVSEM_SHIFT         (16)
+#define EXYNOS4_CLKDIV_DMC1_DVSEM_MASK          (0x7f << EXYNOS4_CLKDIV_DMC1_DVSEM_SHIFT)
+#define EXYNOS4_CLKDIV_DMC1_DPM_SHIFT           (24)
+#define EXYNOS4_CLKDIV_DMC1_DPM_MASK            (0x7f << EXYNOS4_CLKDIV_DMC1_DPM_SHIFT)
+
+#define EXYNOS4_CLKDIV_MFC_SHIFT                (0)
+#define EXYNOS4_CLKDIV_MFC_MASK                 (0x7 << EXYNOS4_CLKDIV_MFC_SHIFT)
+
+#define EXYNOS4_CLKDIV_TOP_ACLK200_SHIFT        (0)
+#define EXYNOS4_CLKDIV_TOP_ACLK200_MASK         (0x7 << EXYNOS4_CLKDIV_TOP_ACLK200_SHIFT)
+#define EXYNOS4_CLKDIV_TOP_ACLK100_SHIFT        (4)
+#define EXYNOS4_CLKDIV_TOP_ACLK100_MASK         (0xF << EXYNOS4_CLKDIV_TOP_ACLK100_SHIFT)
+#define EXYNOS4_CLKDIV_TOP_ACLK160_SHIFT        (8)
+#define EXYNOS4_CLKDIV_TOP_ACLK160_MASK         (0x7 << EXYNOS4_CLKDIV_TOP_ACLK160_SHIFT)
+#define EXYNOS4_CLKDIV_TOP_ACLK133_SHIFT        (12)
+#define EXYNOS4_CLKDIV_TOP_ACLK133_MASK         (0x7 << EXYNOS4_CLKDIV_TOP_ACLK133_SHIFT)
+#define EXYNOS4_CLKDIV_TOP_ONENAND_SHIFT        (16)
+#define EXYNOS4_CLKDIV_TOP_ONENAND_MASK         (0x7 << EXYNOS4_CLKDIV_TOP_ONENAND_SHIFT)
+#define EXYNOS4_CLKDIV_TOP_ACLK266_GPS_SHIFT    (20)
+#define EXYNOS4_CLKDIV_TOP_ACLK266_GPS_MASK     (0x7 << EXYNOS4_CLKDIV_TOP_ACLK266_GPS_SHIFT)
+#define EXYNOS4_CLKDIV_TOP_ACLK400_MCUISP_SHIFT (24)
+#define EXYNOS4_CLKDIV_TOP_ACLK400_MCUISP_MASK  (0x7 << EXYNOS4_CLKDIV_TOP_ACLK400_MCUISP_SHIFT)
+
+#define EXYNOS4_CLKDIV_BUS_GDLR_SHIFT           (0)
+#define EXYNOS4_CLKDIV_BUS_GDLR_MASK            (0x7 << EXYNOS4_CLKDIV_BUS_GDLR_SHIFT)
+#define EXYNOS4_CLKDIV_BUS_GPLR_SHIFT           (4)
+#define EXYNOS4_CLKDIV_BUS_GPLR_MASK            (0x7 << EXYNOS4_CLKDIV_BUS_GPLR_SHIFT)
+
+#define EXYNOS4_CLKDIV_CAM_FIMC0_SHIFT          (0)
+#define EXYNOS4_CLKDIV_CAM_FIMC0_MASK           (0xf << EXYNOS4_CLKDIV_CAM_FIMC0_SHIFT)
+#define EXYNOS4_CLKDIV_CAM_FIMC1_SHIFT          (4)
+#define EXYNOS4_CLKDIV_CAM_FIMC1_MASK           (0xf << EXYNOS4_CLKDIV_CAM_FIMC1_SHIFT)
+#define EXYNOS4_CLKDIV_CAM_FIMC2_SHIFT          (8)
+#define EXYNOS4_CLKDIV_CAM_FIMC2_MASK           (0xf << EXYNOS4_CLKDIV_CAM_FIMC2_SHIFT)
+#define EXYNOS4_CLKDIV_CAM_FIMC3_SHIFT          (12)
+#define EXYNOS4_CLKDIV_CAM_FIMC3_MASK           (0xf << EXYNOS4_CLKDIV_CAM_FIMC3_SHIFT)
 
 /* Only for EXYNOS4210 */
 
-#define S5P_CLKSRC_LCD1                 S5P_CLKREG(0x0C238)
-#define S5P_CLKSRC_MASK_LCD1            S5P_CLKREG(0x0C338)
-#define S5P_CLKDIV_LCD1                 S5P_CLKREG(0x0C538)
-#define S5P_CLKGATE_IP_LCD1             S5P_CLKREG(0x0C938)
+#define EXYNOS4210_CLKSRC_LCD1                  EXYNOS_CLKREG(0x0C238)
+#define EXYNOS4210_CLKSRC_MASK_LCD1             EXYNOS_CLKREG(0x0C338)
+#define EXYNOS4210_CLKDIV_LCD1                  EXYNOS_CLKREG(0x0C538)
+#define EXYNOS4210_CLKGATE_IP_LCD1              EXYNOS_CLKREG(0x0C938)
+
+/* Only for EXYNOS4212 */
+
+#define EXYNOS4_CLKDIV_CAM1                     EXYNOS_CLKREG(0x0C568)
+
+#define EXYNOS4_CLKDIV_STAT_CAM1                EXYNOS_CLKREG(0x0C668)
+
+#define EXYNOS4_CLKDIV_CAM1_JPEG_SHIFT          (0)
+#define EXYNOS4_CLKDIV_CAM1_JPEG_MASK           (0xf << EXYNOS4_CLKDIV_CAM1_JPEG_SHIFT)
 
 /* Compatibility defines and inclusion */
 
 #include <mach/regs-pmu.h>
 
-#define S5P_EPLL_CON                    S5P_EPLL_CON0
+#define S5P_EPLL_CON                            EXYNOS4_EPLL_CON0
 
 #endif /* __ASM_ARCH_REGS_CLOCK_H */
diff --git a/arch/arm/mach-exynos/include/mach/system.h b/arch/arm/mach-exynos/include/mach/system.h
deleted file mode 100644
index 0063a6de3dc..00000000000
--- a/arch/arm/mach-exynos/include/mach/system.h
+++ /dev/null
@@ -1,20 +0,0 @@
-/* linux/arch/arm/mach-exynos4/include/mach/system.h
- *
- * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com
- *
- * EXYNOS4 - system support header
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __ASM_ARCH_SYSTEM_H
-#define __ASM_ARCH_SYSTEM_H __FILE__
-
-static void arch_idle(void)
-{
-        /* nothing here yet */
-}
-#endif /* __ASM_ARCH_SYSTEM_H */
diff --git a/arch/arm/mach-exynos/mach-nuri.c b/arch/arm/mach-exynos/mach-nuri.c
index aa37179d776..82ea6fccfb3 100644
--- a/arch/arm/mach-exynos/mach-nuri.c
+++ b/arch/arm/mach-exynos/mach-nuri.c
@@ -28,6 +28,7 @@
 
 #include <video/platform_lcd.h>
 #include <media/m5mols.h>
+#include <media/s5k6aa.h>
 #include <media/s5p_fimc.h>
 #include <media/v4l2-mediabus.h>
 
@@ -75,6 +76,7 @@ enum fixed_regulator_id {
         FIXED_REG_ID_MAX8903,
         FIXED_REG_ID_CAM_A28V,
         FIXED_REG_ID_CAM_12V,
+        FIXED_REG_ID_CAM_VT_15V,
 };
 
 static struct s3c2410_uartcfg nuri_uartcfgs[] __initdata = {
@@ -115,7 +117,7 @@ static struct s3c_sdhci_platdata nuri_hsmmc0_data __initdata = {
 };
 
 static struct regulator_consumer_supply emmc_supplies[] = {
-        REGULATOR_SUPPLY("vmmc", "s3c-sdhci.0"),
+        REGULATOR_SUPPLY("vmmc", "exynos4-sdhci.0"),
         REGULATOR_SUPPLY("vmmc", "dw_mmc"),
 };
 
@@ -399,6 +401,9 @@ static struct regulator_consumer_supply __initdata max8997_ldo4_[] = {
 static struct regulator_consumer_supply __initdata max8997_ldo5_[] = {
         REGULATOR_SUPPLY("vhsic", "modemctl"), /* MODEM */
 };
+static struct regulator_consumer_supply nuri_max8997_ldo6_consumer[] = {
+        REGULATOR_SUPPLY("vdd_reg", "6-003c"), /* S5K6AA camera */
+};
 static struct regulator_consumer_supply __initdata max8997_ldo7_[] = {
         REGULATOR_SUPPLY("dig_18", "0-001f"), /* HCD803 */
 };
@@ -413,7 +418,7 @@ static struct regulator_consumer_supply __initdata max8997_ldo12_[] = {
         REGULATOR_SUPPLY("vddio", "6-003c"), /* HDC802 */
 };
 static struct regulator_consumer_supply __initdata max8997_ldo13_[] = {
-        REGULATOR_SUPPLY("vmmc", "s3c-sdhci.2"), /* TFLASH */
+        REGULATOR_SUPPLY("vmmc", "exynos4-sdhci.2"), /* TFLASH */
 };
 static struct regulator_consumer_supply __initdata max8997_ldo14_[] = {
         REGULATOR_SUPPLY("inmotor", "max8997-haptic"),
@@ -431,7 +436,7 @@ static struct regulator_consumer_supply __initdata max8997_buck1_[] = {
         REGULATOR_SUPPLY("vdd_arm", NULL), /* CPUFREQ */
 };
 static struct regulator_consumer_supply __initdata max8997_buck2_[] = {
-        REGULATOR_SUPPLY("vdd_int", NULL), /* CPUFREQ */
+        REGULATOR_SUPPLY("vdd_int", "exynos4210-busfreq.0"), /* CPUFREQ */
 };
 static struct regulator_consumer_supply __initdata max8997_buck3_[] = {
         REGULATOR_SUPPLY("vdd", "mali_dev.0"), /* G3D of Exynos 4 */
@@ -546,6 +551,8 @@ static struct regulator_init_data __initdata max8997_ldo6_data = {
                         .enabled        = 1,
                 },
         },
+        .num_consumer_supplies  = ARRAY_SIZE(nuri_max8997_ldo6_consumer),
+        .consumer_supplies      = nuri_max8997_ldo6_consumer,
 };
 
 static struct regulator_init_data __initdata max8997_ldo7_data = {
@@ -742,7 +749,7 @@ static struct regulator_init_data __initdata max8997_buck2_data = {
         .constraints    = {
                 .name           = "VINT_1.1V_C210",
                 .min_uV         = 900000,
-                .max_uV         = 1100000,
+                .max_uV         = 1200000,
                 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
                 .always_on      = 1,
                 .state_mem      = {
@@ -957,7 +964,6 @@ static struct max8997_platform_data __initdata nuri_max8997_pdata = {
         .regulators             = nuri_max8997_regulators,
 
         .buck125_gpios = { EXYNOS4_GPX0(5), EXYNOS4_GPX0(6), EXYNOS4_GPL0(0) },
-        .buck2_gpiodvs = true,
 
         .buck1_voltage[0] = 1350000, /* 1.35V */
         .buck1_voltage[1] = 1300000, /* 1.3V */
@@ -1116,7 +1122,30 @@ static void __init nuri_ehci_init(void)
 }
 
 /* CAMERA */
+static struct regulator_consumer_supply cam_vt_cam15_supply =
+        REGULATOR_SUPPLY("vdd_core", "6-003c");
+
+static struct regulator_init_data cam_vt_cam15_reg_init_data = {
+        .constraints = { .valid_ops_mask = REGULATOR_CHANGE_STATUS },
+        .num_consumer_supplies = 1,
+        .consumer_supplies = &cam_vt_cam15_supply,
+};
+
+static struct fixed_voltage_config cam_vt_cam15_fixed_voltage_cfg = {
+        .supply_name    = "VT_CAM_1.5V",
+        .microvolts     = 1500000,
+        .gpio           = EXYNOS4_GPE2(2), /* VT_CAM_1.5V_EN */
+        .enable_high    = 1,
+        .init_data      = &cam_vt_cam15_reg_init_data,
+};
+
+static struct platform_device cam_vt_cam15_fixed_rdev = {
+        .name = "reg-fixed-voltage", .id = FIXED_REG_ID_CAM_VT_15V,
+        .dev = { .platform_data = &cam_vt_cam15_fixed_voltage_cfg },
+};
+
 static struct regulator_consumer_supply cam_vdda_supply[] = {
+        REGULATOR_SUPPLY("vdda", "6-003c"),
         REGULATOR_SUPPLY("a_sensor", "0-001f"),
 };
 
@@ -1173,6 +1202,21 @@ static struct s5p_platform_mipi_csis mipi_csis_platdata = {
 
 #define GPIO_CAM_MEGA_RST       EXYNOS4_GPY3(7) /* ISP_RESET */
 #define GPIO_CAM_8M_ISP_INT     EXYNOS4_GPL2(5)
+#define GPIO_CAM_VT_NSTBY       EXYNOS4_GPL2(0)
+#define GPIO_CAM_VT_NRST        EXYNOS4_GPL2(1)
+
+static struct s5k6aa_platform_data s5k6aa_pldata = {
+        .mclk_frequency = 24000000UL,
+        .gpio_reset     = { GPIO_CAM_VT_NRST, 0 },
+        .gpio_stby      = { GPIO_CAM_VT_NSTBY, 0 },
+        .bus_type       = V4L2_MBUS_PARALLEL,
+        .horiz_flip     = 1,
+};
+
+static struct i2c_board_info s5k6aa_board_info = {
+        I2C_BOARD_INFO("S5K6AA", 0x3c),
+        .platform_data = &s5k6aa_pldata,
+};
 
 static struct m5mols_platform_data m5mols_platdata = {
         .gpio_reset = GPIO_CAM_MEGA_RST,
@@ -1185,6 +1229,13 @@ static struct i2c_board_info m5mols_board_info = {
 
 static struct s5p_fimc_isp_info nuri_camera_sensors[] = {
         {
+                .flags          = V4L2_MBUS_PCLK_SAMPLE_RISING |
+                                  V4L2_MBUS_VSYNC_ACTIVE_LOW,
+                .bus_type       = FIMC_ITU_601,
+                .board_info     = &s5k6aa_board_info,
+                .clk_frequency  = 24000000UL,
+                .i2c_bus_num    = 6,
+        }, {
                 .flags          = V4L2_MBUS_PCLK_SAMPLE_FALLING |
                                   V4L2_MBUS_VSYNC_ACTIVE_LOW,
                 .bus_type       = FIMC_MIPI_CSI2,
@@ -1200,11 +1251,13 @@ static struct s5p_platform_fimc fimc_md_platdata = {
 };
 
 static struct gpio nuri_camera_gpios[] = {
+        { GPIO_CAM_VT_NSTBY,    GPIOF_OUT_INIT_LOW, "CAM_VGA_NSTBY" },
+        { GPIO_CAM_VT_NRST,     GPIOF_OUT_INIT_LOW, "CAM_VGA_NRST"  },
         { GPIO_CAM_8M_ISP_INT,  GPIOF_IN,           "8M_ISP_INT"  },
         { GPIO_CAM_MEGA_RST,    GPIOF_OUT_INIT_LOW, "CAM_8M_NRST" },
 };
 
-static void nuri_camera_init(void)
+static void __init nuri_camera_init(void)
 {
         s3c_set_platdata(&mipi_csis_platdata, sizeof(mipi_csis_platdata),
                          &s5p_device_mipi_csis0);
@@ -1224,6 +1277,8 @@ static void nuri_camera_init(void)
                 pr_err("%s: Failed to configure 8M_ISP_INT GPIO\n", __func__);
 
         /* Free GPIOs controlled directly by the sensor drivers. */
+        gpio_free(GPIO_CAM_VT_NRST);
+        gpio_free(GPIO_CAM_VT_NSTBY);
         gpio_free(GPIO_CAM_MEGA_RST);
 
         if (exynos4_fimc_setup_gpio(S5P_CAMPORT_A)) {
@@ -1234,15 +1289,27 @@ static void nuri_camera_init(void)
         s5p_gpio_set_drvstr(EXYNOS4_GPJ1(3), S5P_GPIO_DRVSTR_LV4);
 }
 
+static struct s3c2410_platform_i2c nuri_i2c6_platdata __initdata = {
+        .frequency      = 400000U,
+        .sda_delay      = 200,
+        .bus_num        = 6,
+};
+
 static struct s3c2410_platform_i2c nuri_i2c0_platdata __initdata = {
         .frequency      = 400000U,
         .sda_delay      = 200,
 };
 
+/* DEVFREQ controlling memory/bus */
+static struct platform_device exynos4_bus_devfreq = {
+        .name                   = "exynos4210-busfreq",
+};
+
 static struct platform_device *nuri_devices[] __initdata = {
         /* Samsung Platform Devices */
         &s3c_device_i2c5, /* PMIC should initialize first */
         &s3c_device_i2c0,
+        &s3c_device_i2c6,
         &emmc_fixed_voltage,
         &s5p_device_mipi_csis0,
         &s5p_device_fimc0,
@@ -1259,6 +1326,8 @@ static struct platform_device *nuri_devices[] __initdata = {
         &s3c_device_i2c3,
         &i2c9_gpio,
         &s3c_device_adc,
+        &s5p_device_g2d,
+        &s5p_device_jpeg,
         &s3c_device_rtc,
         &s5p_device_mfc,
         &s5p_device_mfc_l,
@@ -1271,8 +1340,10 @@ static struct platform_device *nuri_devices[] __initdata = {
         &nuri_backlight_device,
         &max8903_fixed_reg_dev,
         &nuri_max8903_device,
+        &cam_vt_cam15_fixed_rdev,
         &cam_vdda_fixed_rdev,
         &cam_8m_12v_fixed_rdev,
+        &exynos4_bus_devfreq,
 };
 
 static void __init nuri_map_io(void)
@@ -1302,6 +1373,7 @@ static void __init nuri_machine_init(void)
         i2c_register_board_info(5, i2c5_devs, ARRAY_SIZE(i2c5_devs));
         i2c9_devs[I2C9_MAX17042].irq = gpio_to_irq(EXYNOS4_GPX2(3));
         i2c_register_board_info(9, i2c9_devs, ARRAY_SIZE(i2c9_devs));
+        s3c_i2c6_set_platdata(&nuri_i2c6_platdata);
 
         s5p_fimd0_set_platdata(&nuri_fb_pdata);
 
diff --git a/arch/arm/mach-exynos/mach-origen.c b/arch/arm/mach-exynos/mach-origen.c
index fa5c4a59b0a..878d4c99142 100644
--- a/arch/arm/mach-exynos/mach-origen.c
+++ b/arch/arm/mach-exynos/mach-origen.c
@@ -20,6 +20,7 @@
 #include <linux/regulator/machine.h>
 #include <linux/mfd/max8997.h>
 #include <linux/lcd.h>
+#include <linux/rfkill-gpio.h>
 
 #include <asm/mach/arch.h>
 #include <asm/hardware/gic.h>
@@ -235,6 +236,7 @@ static struct regulator_init_data __initdata max8997_ldo9_data = {
                 .min_uV         = 2800000,
                 .max_uV         = 2800000,
                 .apply_uV       = 1,
+                .always_on      = 1,
                 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
                 .state_mem      = {
                         .disabled       = 1,
@@ -278,6 +280,7 @@ static struct regulator_init_data __initdata max8997_ldo14_data = {
                 .min_uV         = 1800000,
                 .max_uV         = 1800000,
                 .apply_uV       = 1,
+                .always_on      = 1,
                 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
                 .state_mem      = {
                         .disabled       = 1,
@@ -293,6 +296,7 @@ static struct regulator_init_data __initdata max8997_ldo17_data = {
                 .min_uV         = 3300000,
                 .max_uV         = 3300000,
                 .apply_uV       = 1,
+                .always_on      = 1,
                 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
                 .state_mem      = {
                         .disabled       = 1,
@@ -412,7 +416,7 @@ static struct max8997_regulator_data __initdata origen_max8997_regulators[] = {
         { MAX8997_BUCK7,        &max8997_buck7_data },
 };
 
-struct max8997_platform_data __initdata origen_max8997_pdata = {
+static struct max8997_platform_data __initdata origen_max8997_pdata = {
         .num_regulators = ARRAY_SIZE(origen_max8997_regulators),
         .regulators     = origen_max8997_regulators,
 
@@ -602,6 +606,23 @@ static struct s3c_fb_platdata origen_lcd_pdata __initdata = {
         .setup_gpio     = exynos4_fimd0_gpio_setup_24bpp,
 };
 
+/* Bluetooth rfkill gpio platform data */
+struct rfkill_gpio_platform_data origen_bt_pdata = {
+        .reset_gpio     = EXYNOS4_GPX2(2),
+        .shutdown_gpio  = -1,
+        .type           = RFKILL_TYPE_BLUETOOTH,
+        .name           = "origen-bt",
+};
+
+/* Bluetooth Platform device */
+static struct platform_device origen_device_bluetooth = {
+        .name           = "rfkill_gpio",
+        .id             = -1,
+        .dev            = {
+                .platform_data  = &origen_bt_pdata,
+        },
+};
+
 static struct platform_device *origen_devices[] __initdata = {
         &s3c_device_hsmmc2,
         &s3c_device_hsmmc0,
@@ -613,9 +634,12 @@ static struct platform_device *origen_devices[] __initdata = {
         &s5p_device_fimc1,
         &s5p_device_fimc2,
         &s5p_device_fimc3,
+        &s5p_device_fimc_md,
         &s5p_device_fimd0,
+        &s5p_device_g2d,
         &s5p_device_hdmi,
         &s5p_device_i2c_hdmiphy,
+        &s5p_device_jpeg,
         &s5p_device_mfc,
         &s5p_device_mfc_l,
         &s5p_device_mfc_r,
@@ -623,6 +647,7 @@ static struct platform_device *origen_devices[] __initdata = {
         &exynos4_device_ohci,
         &origen_device_gpiokeys,
         &origen_lcd_hv070wsa,
+        &origen_device_bluetooth,
 };
 
 /* LCD Backlight data */
@@ -636,6 +661,16 @@ static struct platform_pwm_backlight_data origen_bl_data = {
         .pwm_period_ns  = 1000,
 };
 
+static void __init origen_bt_setup(void)
+{
+        gpio_request(EXYNOS4_GPA0(0), "GPIO BT_UART");
+        /* 4 UART Pins configuration */
+        s3c_gpio_cfgrange_nopull(EXYNOS4_GPA0(0), 4, S3C_GPIO_SFN(2));
+        /* Setup BT Reset, this gpio will be requesed by rfkill-gpio */
+        s3c_gpio_cfgpin(EXYNOS4_GPX2(2), S3C_GPIO_OUTPUT);
+        s3c_gpio_setpull(EXYNOS4_GPX2(2), S3C_GPIO_PULL_NONE);
+}
+
 static void s5p_tv_setup(void)
 {
         /* Direct HPD to HDMI chip */
@@ -689,6 +724,8 @@ static void __init origen_machine_init(void)
         platform_add_devices(origen_devices, ARRAY_SIZE(origen_devices));
 
         samsung_bl_set(&origen_bl_gpio_info, &origen_bl_data);
+
+        origen_bt_setup();
 }
 
 MACHINE_START(ORIGEN, "ORIGEN")
diff --git a/arch/arm/mach-exynos/mach-smdkv310.c b/arch/arm/mach-exynos/mach-smdkv310.c
index 5258b856367..83b91fa777c 100644
--- a/arch/arm/mach-exynos/mach-smdkv310.c
+++ b/arch/arm/mach-exynos/mach-smdkv310.c
@@ -270,6 +270,9 @@ static struct platform_device *smdkv310_devices[] __initdata = {
         &s5p_device_fimc1,
         &s5p_device_fimc2,
         &s5p_device_fimc3,
+        &s5p_device_fimc_md,
+        &s5p_device_g2d,
+        &s5p_device_jpeg,
         &exynos4_device_ac97,
         &exynos4_device_i2s0,
         &exynos4_device_ohci,
diff --git a/arch/arm/mach-exynos/mach-universal_c210.c b/arch/arm/mach-exynos/mach-universal_c210.c
index b2d495b3109..28658da9f42 100644
--- a/arch/arm/mach-exynos/mach-universal_c210.c
+++ b/arch/arm/mach-exynos/mach-universal_c210.c
@@ -47,6 +47,7 @@
 #include <media/v4l2-mediabus.h>
 #include <media/s5p_fimc.h>
 #include <media/m5mols.h>
+#include <media/s5k6aa.h>
 
 #include "common.h"
 
@@ -123,8 +124,10 @@ static struct regulator_consumer_supply lp3974_buck1_consumer =
 static struct regulator_consumer_supply lp3974_buck2_consumer =
         REGULATOR_SUPPLY("vddg3d", NULL);
 
-static struct regulator_consumer_supply lp3974_buck3_consumer =
-        REGULATOR_SUPPLY("vdet", "s5p-sdo");
+static struct regulator_consumer_supply lp3974_buck3_consumer[] = {
+        REGULATOR_SUPPLY("vdet", "s5p-sdo"),
+        REGULATOR_SUPPLY("vdd_reg", "0-003c"),
+};
 
 static struct regulator_init_data lp3974_buck1_data = {
         .constraints    = {
@@ -169,8 +172,8 @@ static struct regulator_init_data lp3974_buck3_data = {
                         .enabled        = 1,
                 },
         },
-        .num_consumer_supplies = 1,
-        .consumer_supplies = &lp3974_buck3_consumer,
+        .num_consumer_supplies = ARRAY_SIZE(lp3974_buck3_consumer),
+        .consumer_supplies = lp3974_buck3_consumer,
 };
 
 static struct regulator_init_data lp3974_buck4_data = {
@@ -303,6 +306,9 @@ static struct regulator_init_data lp3974_ldo8_data = {
         .consumer_supplies = lp3974_ldo8_consumer,
 };
 
+static struct regulator_consumer_supply lp3974_ldo9_consumer =
+        REGULATOR_SUPPLY("vddio", "0-003c");
+
 static struct regulator_init_data lp3974_ldo9_data = {
         .constraints    = {
                 .name           = "VCC_2.8V",
@@ -314,6 +320,8 @@ static struct regulator_init_data lp3974_ldo9_data = {
                         .enabled        = 1,
                 },
         },
+        .num_consumer_supplies  = 1,
+        .consumer_supplies      = &lp3974_ldo9_consumer,
 };
 
 static struct regulator_init_data lp3974_ldo10_data = {
@@ -412,6 +420,7 @@ static struct regulator_init_data lp3974_ldo15_data = {
 };
 
 static struct regulator_consumer_supply lp3974_ldo16_consumer[] = {
+        REGULATOR_SUPPLY("vdda", "0-003c"),
         REGULATOR_SUPPLY("a_sensor", "0-001f"),
 };
 
@@ -743,7 +752,7 @@ static struct s3c_sdhci_platdata universal_hsmmc0_data __initdata = {
 };
 
 static struct regulator_consumer_supply mmc0_supplies[] = {
-        REGULATOR_SUPPLY("vmmc", "s3c-sdhci.0"),
+        REGULATOR_SUPPLY("vmmc", "exynos4-sdhci.0"),
 };
 
 static struct regulator_init_data mmc0_fixed_voltage_init_data = {
@@ -819,6 +828,8 @@ static struct s3c_fb_pd_win universal_fb_win0 = {
         },
         .max_bpp        = 32,
         .default_bpp    = 16,
+        .virtual_x      = 480,
+        .virtual_y      = 2 * 800,
 };
 
 static struct s3c_fb_platdata universal_lcd_pdata __initdata = {
@@ -830,6 +841,28 @@ static struct s3c_fb_platdata universal_lcd_pdata __initdata = {
         .setup_gpio     = exynos4_fimd0_gpio_setup_24bpp,
 };
 
+static struct regulator_consumer_supply cam_vt_dio_supply =
+        REGULATOR_SUPPLY("vdd_core", "0-003c");
+
+static struct regulator_init_data cam_vt_dio_reg_init_data = {
+        .constraints = { .valid_ops_mask = REGULATOR_CHANGE_STATUS },
+        .num_consumer_supplies = 1,
+        .consumer_supplies = &cam_vt_dio_supply,
+};
+
+static struct fixed_voltage_config cam_vt_dio_fixed_voltage_cfg = {
+        .supply_name    = "CAM_VT_D_IO",
+        .microvolts     = 2800000,
+        .gpio           = EXYNOS4_GPE2(1), /* CAM_PWR_EN2 */
+        .enable_high    = 1,
+        .init_data      = &cam_vt_dio_reg_init_data,
+};
+
+static struct platform_device cam_vt_dio_fixed_reg_dev = {
+        .name = "reg-fixed-voltage", .id = FIXED_REG_ID_CAM_VT_DIO,
+        .dev = { .platform_data = &cam_vt_dio_fixed_voltage_cfg },
+};
+
 static struct regulator_consumer_supply cam_i_core_supply =
         REGULATOR_SUPPLY("core", "0-001f");
 
@@ -885,6 +918,28 @@ static struct s5p_platform_mipi_csis mipi_csis_platdata = {
 #define GPIO_CAM_LEVEL_EN(n)    EXYNOS4_GPE4(n + 3)
 #define GPIO_CAM_8M_ISP_INT     EXYNOS4_GPX1(5) /* XEINT_13 */
 #define GPIO_CAM_MEGA_nRST      EXYNOS4_GPE2(5)
+#define GPIO_CAM_VGA_NRST       EXYNOS4_GPE4(7)
+#define GPIO_CAM_VGA_NSTBY      EXYNOS4_GPE4(6)
+
+static int s5k6aa_set_power(int on)
+{
+        gpio_set_value(GPIO_CAM_LEVEL_EN(2), !!on);
+        return 0;
+}
+
+static struct s5k6aa_platform_data s5k6aa_platdata = {
+        .mclk_frequency = 21600000UL,
+        .gpio_reset     = { GPIO_CAM_VGA_NRST, 0 },
+        .gpio_stby      = { GPIO_CAM_VGA_NSTBY, 0 },
+        .bus_type       = V4L2_MBUS_PARALLEL,
+        .horiz_flip     = 1,
+        .set_power      = s5k6aa_set_power,
+};
+
+static struct i2c_board_info s5k6aa_board_info = {
+        I2C_BOARD_INFO("S5K6AA", 0x3C),
+        .platform_data = &s5k6aa_platdata,
+};
 
 static int m5mols_set_power(struct device *dev, int on)
 {
@@ -909,6 +964,14 @@ static struct s5p_fimc_isp_info universal_camera_sensors[] = {
                 .mux_id         = 0,
                 .flags          = V4L2_MBUS_PCLK_SAMPLE_FALLING |
                                   V4L2_MBUS_VSYNC_ACTIVE_LOW,
+                .bus_type       = FIMC_ITU_601,
+                .board_info     = &s5k6aa_board_info,
+                .i2c_bus_num    = 0,
+                .clk_frequency  = 24000000UL,
+        }, {
+                .mux_id         = 0,
+                .flags          = V4L2_MBUS_PCLK_SAMPLE_FALLING |
+                                  V4L2_MBUS_VSYNC_ACTIVE_LOW,
                 .bus_type       = FIMC_MIPI_CSI2,
                 .board_info     = &m5mols_board_info,
                 .i2c_bus_num    = 0,
@@ -927,9 +990,11 @@ static struct gpio universal_camera_gpios[] = {
         { GPIO_CAM_LEVEL_EN(2), GPIOF_OUT_INIT_LOW,  "CAM_LVL_EN2" },
         { GPIO_CAM_8M_ISP_INT,  GPIOF_IN,            "8M_ISP_INT"  },
         { GPIO_CAM_MEGA_nRST,   GPIOF_OUT_INIT_LOW,  "CAM_8M_NRST" },
+        { GPIO_CAM_VGA_NRST,    GPIOF_OUT_INIT_LOW,  "CAM_VGA_NRST"  },
+        { GPIO_CAM_VGA_NSTBY,   GPIOF_OUT_INIT_LOW,  "CAM_VGA_NSTBY" },
 };
 
-static void universal_camera_init(void)
+static void __init universal_camera_init(void)
 {
         s3c_set_platdata(&mipi_csis_platdata, sizeof(mipi_csis_platdata),
                          &s5p_device_mipi_csis0);
@@ -950,6 +1015,8 @@ static void universal_camera_init(void)
         /* Free GPIOs controlled directly by the sensor drivers. */
         gpio_free(GPIO_CAM_MEGA_nRST);
         gpio_free(GPIO_CAM_8M_ISP_INT);
+        gpio_free(GPIO_CAM_VGA_NRST);
+        gpio_free(GPIO_CAM_VGA_NSTBY);
 
         if (exynos4_fimc_setup_gpio(S5P_CAMPORT_A))
                 pr_err("Camera port A setup failed\n");
@@ -962,6 +1029,7 @@ static struct platform_device *universal_devices[] __initdata = {
         &s5p_device_fimc1,
         &s5p_device_fimc2,
         &s5p_device_fimc3,
+        &s5p_device_g2d,
         &mmc0_fixed_voltage,
         &s3c_device_hsmmc0,
         &s3c_device_hsmmc2,
@@ -980,9 +1048,11 @@ static struct platform_device *universal_devices[] __initdata = {
         &universal_gpio_keys,
         &s5p_device_onenand,
         &s5p_device_fimd0,
+        &s5p_device_jpeg,
         &s5p_device_mfc,
         &s5p_device_mfc_l,
         &s5p_device_mfc_r,
+        &cam_vt_dio_fixed_reg_dev,
         &cam_i_core_fixed_reg_dev,
         &cam_s_if_fixed_reg_dev,
         &s5p_device_fimc_md,
@@ -995,7 +1065,7 @@ static void __init universal_map_io(void)
         s3c24xx_init_uarts(universal_uartcfgs, ARRAY_SIZE(universal_uartcfgs));
 }
 
-void s5p_tv_setup(void)
+static void s5p_tv_setup(void)
 {
         /* direct HPD to HDMI chip */
         gpio_request_one(EXYNOS4_GPX3(7), GPIOF_IN, "hpd-plug");
diff --git a/arch/arm/mach-exynos/mct.c b/arch/arm/mach-exynos/mct.c
index 85b5527d091..e8a1caaf190 100644
--- a/arch/arm/mach-exynos/mct.c
+++ b/arch/arm/mach-exynos/mct.c
@@ -21,6 +21,7 @@
 #include <linux/percpu.h>
 
 #include <asm/hardware/gic.h>
+#include <asm/localtimer.h>
 
 #include <plat/cpu.h>
 
@@ -29,12 +30,13 @@
 #include <mach/regs-mct.h>
 #include <asm/mach/time.h>
 
+#define TICK_BASE_CNT   1
+
 enum {
         MCT_INT_SPI,
         MCT_INT_PPI
 };
 
-static unsigned long clk_cnt_per_tick;
 static unsigned long clk_rate;
 static unsigned int mct_int_type;
 
@@ -205,11 +207,14 @@ static int exynos4_comp_set_next_event(unsigned long cycles,
 static void exynos4_comp_set_mode(enum clock_event_mode mode,
                                   struct clock_event_device *evt)
 {
+        unsigned long cycles_per_jiffy;
         exynos4_mct_comp0_stop();
 
         switch (mode) {
         case CLOCK_EVT_MODE_PERIODIC:
-                exynos4_mct_comp0_start(mode, clk_cnt_per_tick);
+                cycles_per_jiffy =
+                        (((unsigned long long) NSEC_PER_SEC / HZ * evt->mult) >> evt->shift);
+                exynos4_mct_comp0_start(mode, cycles_per_jiffy);
                 break;
 
         case CLOCK_EVT_MODE_ONESHOT:
@@ -248,9 +253,7 @@ static struct irqaction mct_comp_event_irq = {
 
 static void exynos4_clockevent_init(void)
 {
-        clk_cnt_per_tick = clk_rate / 2 / HZ;
-
-        clockevents_calc_mult_shift(&mct_comp_device, clk_rate / 2, 5);
+        clockevents_calc_mult_shift(&mct_comp_device, clk_rate, 5);
         mct_comp_device.max_delta_ns =
                 clockevent_delta2ns(0xffffffff, &mct_comp_device);
         mct_comp_device.min_delta_ns =
@@ -314,12 +317,15 @@ static inline void exynos4_tick_set_mode(enum clock_event_mode mode,
                                          struct clock_event_device *evt)
 {
         struct mct_clock_event_device *mevt = this_cpu_ptr(&percpu_mct_tick);
+        unsigned long cycles_per_jiffy;
 
         exynos4_mct_tick_stop(mevt);
 
         switch (mode) {
         case CLOCK_EVT_MODE_PERIODIC:
-                exynos4_mct_tick_start(clk_cnt_per_tick, mevt);
+                cycles_per_jiffy =
+                        (((unsigned long long) NSEC_PER_SEC / HZ * evt->mult) >> evt->shift);
+                exynos4_mct_tick_start(cycles_per_jiffy, mevt);
                 break;
 
         case CLOCK_EVT_MODE_ONESHOT:
@@ -375,7 +381,7 @@ static struct irqaction mct_tick1_event_irq = {
         .handler        = exynos4_mct_tick_isr,
 };
 
-static void exynos4_mct_tick_init(struct clock_event_device *evt)
+static int __cpuinit exynos4_local_timer_setup(struct clock_event_device *evt)
 {
         struct mct_clock_event_device *mevt;
         unsigned int cpu = smp_processor_id();
@@ -393,7 +399,7 @@ static void exynos4_mct_tick_init(struct clock_event_device *evt)
         evt->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;
         evt->rating = 450;
 
-        clockevents_calc_mult_shift(evt, clk_rate / 2, 5);
+        clockevents_calc_mult_shift(evt, clk_rate / (TICK_BASE_CNT + 1), 5);
         evt->max_delta_ns =
                 clockevent_delta2ns(0x7fffffff, evt);
         evt->min_delta_ns =
@@ -401,7 +407,7 @@ static void exynos4_mct_tick_init(struct clock_event_device *evt)
 
         clockevents_register_device(evt);
 
-        exynos4_mct_write(0x1, mevt->base + MCT_L_TCNTB_OFFSET);
+        exynos4_mct_write(TICK_BASE_CNT, mevt->base + MCT_L_TCNTB_OFFSET);
 
         if (mct_int_type == MCT_INT_SPI) {
                 if (cpu == 0) {
@@ -417,17 +423,11 @@ static void exynos4_mct_tick_init(struct clock_event_device *evt)
         } else {
                 enable_percpu_irq(IRQ_MCT_LOCALTIMER, 0);
         }
-}
-
-/* Setup the local clock events for a CPU */
-int __cpuinit local_timer_setup(struct clock_event_device *evt)
-{
-        exynos4_mct_tick_init(evt);
 
         return 0;
 }
 
-void local_timer_stop(struct clock_event_device *evt)
+static void exynos4_local_timer_stop(struct clock_event_device *evt)
 {
         unsigned int cpu = smp_processor_id();
         evt->set_mode(CLOCK_EVT_MODE_UNUSED, evt);
@@ -439,6 +439,11 @@ void local_timer_stop(struct clock_event_device *evt)
         else
                 disable_percpu_irq(IRQ_MCT_LOCALTIMER);
 }
+
+static struct local_timer_ops exynos4_mct_tick_ops __cpuinitdata = {
+        .setup  = exynos4_local_timer_setup,
+        .stop   = exynos4_local_timer_stop,
+};
 #endif /* CONFIG_LOCAL_TIMERS */
 
 static void __init exynos4_timer_resources(void)
@@ -458,6 +463,8 @@ static void __init exynos4_timer_resources(void)
                 WARN(err, "MCT: can't request IRQ %d (%d)\n",
                      IRQ_MCT_LOCALTIMER, err);
         }
+
+        local_timer_register(&exynos4_mct_tick_ops);
 #endif /* CONFIG_LOCAL_TIMERS */
 }
 
diff --git a/arch/arm/mach-exynos/pm.c b/arch/arm/mach-exynos/pm.c
index e1901305177..428cfeb5772 100644
--- a/arch/arm/mach-exynos/pm.c
+++ b/arch/arm/mach-exynos/pm.c
@@ -38,29 +38,29 @@
 #include <mach/pmu.h>
 
 static struct sleep_save exynos4_set_clksrc[] = {
-        { .reg = S5P_CLKSRC_MASK_TOP                    , .val = 0x00000001, },
-        { .reg = S5P_CLKSRC_MASK_CAM                    , .val = 0x11111111, },
-        { .reg = S5P_CLKSRC_MASK_TV                     , .val = 0x00000111, },
-        { .reg = S5P_CLKSRC_MASK_LCD0                   , .val = 0x00001111, },
-        { .reg = S5P_CLKSRC_MASK_MAUDIO                 , .val = 0x00000001, },
-        { .reg = S5P_CLKSRC_MASK_FSYS                   , .val = 0x01011111, },
-        { .reg = S5P_CLKSRC_MASK_PERIL0                 , .val = 0x01111111, },
-        { .reg = S5P_CLKSRC_MASK_PERIL1                 , .val = 0x01110111, },
-        { .reg = S5P_CLKSRC_MASK_DMC                    , .val = 0x00010000, },
+        { .reg = EXYNOS4_CLKSRC_MASK_TOP                , .val = 0x00000001, },
+        { .reg = EXYNOS4_CLKSRC_MASK_CAM                , .val = 0x11111111, },
+        { .reg = EXYNOS4_CLKSRC_MASK_TV                 , .val = 0x00000111, },
+        { .reg = EXYNOS4_CLKSRC_MASK_LCD0               , .val = 0x00001111, },
+        { .reg = EXYNOS4_CLKSRC_MASK_MAUDIO             , .val = 0x00000001, },
+        { .reg = EXYNOS4_CLKSRC_MASK_FSYS               , .val = 0x01011111, },
+        { .reg = EXYNOS4_CLKSRC_MASK_PERIL0             , .val = 0x01111111, },
+        { .reg = EXYNOS4_CLKSRC_MASK_PERIL1             , .val = 0x01110111, },
+        { .reg = EXYNOS4_CLKSRC_MASK_DMC                , .val = 0x00010000, },
 };
 
 static struct sleep_save exynos4210_set_clksrc[] = {
-        { .reg = S5P_CLKSRC_MASK_LCD1                   , .val = 0x00001111, },
+        { .reg = EXYNOS4210_CLKSRC_MASK_LCD1            , .val = 0x00001111, },
 };
 
 static struct sleep_save exynos4_epll_save[] = {
-        SAVE_ITEM(S5P_EPLL_CON0),
-        SAVE_ITEM(S5P_EPLL_CON1),
+        SAVE_ITEM(EXYNOS4_EPLL_CON0),
+        SAVE_ITEM(EXYNOS4_EPLL_CON1),
 };
 
 static struct sleep_save exynos4_vpll_save[] = {
-        SAVE_ITEM(S5P_VPLL_CON0),
-        SAVE_ITEM(S5P_VPLL_CON1),
+        SAVE_ITEM(EXYNOS4_VPLL_CON0),
+        SAVE_ITEM(EXYNOS4_VPLL_CON1),
 };
 
 static struct sleep_save exynos4_core_save[] = {
@@ -155,13 +155,6 @@ static struct sleep_save exynos4_core_save[] = {
         SAVE_ITEM(S5P_SROM_BC3),
 };
 
-static struct sleep_save exynos4_l2cc_save[] = {
-        SAVE_ITEM(S5P_VA_L2CC + L2X0_TAG_LATENCY_CTRL),
-        SAVE_ITEM(S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL),
-        SAVE_ITEM(S5P_VA_L2CC + L2X0_PREFETCH_CTRL),
-        SAVE_ITEM(S5P_VA_L2CC + L2X0_POWER_CTRL),
-        SAVE_ITEM(S5P_VA_L2CC + L2X0_AUX_CTRL),
-};
 
 /* For Cortex-A9 Diagnostic and Power control register */
 static unsigned int save_arm_register[2];
@@ -182,7 +175,6 @@ static void exynos4_pm_prepare(void)
         u32 tmp;
 
         s3c_pm_do_save(exynos4_core_save, ARRAY_SIZE(exynos4_core_save));
-        s3c_pm_do_save(exynos4_l2cc_save, ARRAY_SIZE(exynos4_l2cc_save));
         s3c_pm_do_save(exynos4_epll_save, ARRAY_SIZE(exynos4_epll_save));
         s3c_pm_do_save(exynos4_vpll_save, ARRAY_SIZE(exynos4_vpll_save));
 
@@ -239,7 +231,7 @@ static void exynos4_restore_pll(void)
                 locktime = (3000 / pll_in_rate) * p_div;
                 lockcnt = locktime * 10000 / (10000 / pll_in_rate);
 
-                __raw_writel(lockcnt, S5P_EPLL_LOCK);
+                __raw_writel(lockcnt, EXYNOS4_EPLL_LOCK);
 
                 s3c_pm_do_restore_core(exynos4_epll_save,
                                         ARRAY_SIZE(exynos4_epll_save));
@@ -257,7 +249,7 @@ static void exynos4_restore_pll(void)
                 locktime = 750;
                 lockcnt = locktime * 10000 / (10000 / pll_in_rate);
 
-                __raw_writel(lockcnt, S5P_VPLL_LOCK);
+                __raw_writel(lockcnt, EXYNOS4_VPLL_LOCK);
 
                 s3c_pm_do_restore_core(exynos4_vpll_save,
                                         ARRAY_SIZE(exynos4_vpll_save));
@@ -268,14 +260,14 @@ static void exynos4_restore_pll(void)
 
         do {
                 if (epll_wait) {
-                        pll_con = __raw_readl(S5P_EPLL_CON0);
-                        if (pll_con & (1 << S5P_EPLLCON0_LOCKED_SHIFT))
+                        pll_con = __raw_readl(EXYNOS4_EPLL_CON0);
+                        if (pll_con & (1 << EXYNOS4_EPLLCON0_LOCKED_SHIFT))
                                 epll_wait = 0;
                 }
 
                 if (vpll_wait) {
-                        pll_con = __raw_readl(S5P_VPLL_CON0);
-                        if (pll_con & (1 << S5P_VPLLCON0_LOCKED_SHIFT))
+                        pll_con = __raw_readl(EXYNOS4_VPLL_CON0);
+                        if (pll_con & (1 << EXYNOS4_VPLLCON0_LOCKED_SHIFT))
                                 vpll_wait = 0;
                 }
         } while (epll_wait || vpll_wait);
@@ -388,13 +380,6 @@ static void exynos4_pm_resume(void)
         scu_enable(S5P_VA_SCU);
 #endif
 
-#ifdef CONFIG_CACHE_L2X0
-        s3c_pm_do_restore_core(exynos4_l2cc_save, ARRAY_SIZE(exynos4_l2cc_save));
-        outer_inv_all();
-        /* enable L2X0*/
-        writel_relaxed(1, S5P_VA_L2CC + L2X0_CTRL);
-#endif
-
 early_wakeup:
         return;
 }
diff --git a/arch/arm/mach-footbridge/dc21285.c b/arch/arm/mach-footbridge/dc21285.c
index f685650c25d..3194d3f7350 100644
--- a/arch/arm/mach-footbridge/dc21285.c
+++ b/arch/arm/mach-footbridge/dc21285.c
@@ -275,11 +275,13 @@ int __init dc21285_setup(int nr, struct pci_sys_data *sys)
         allocate_resource(&iomem_resource, &res[0], 0x40000000,
                           0x80000000, 0xffffffff, 0x40000000, NULL, NULL);
 
-        pci_add_resource(&sys->resources, &ioport_resource);
-        pci_add_resource(&sys->resources, &res[0]);
-        pci_add_resource(&sys->resources, &res[1]);
         sys->mem_offset  = DC21285_PCI_MEM;
 
+        pci_add_resource_offset(&sys->resources,
+                                &ioport_resource, sys->io_offset);
+        pci_add_resource_offset(&sys->resources, &res[0], sys->mem_offset);
+        pci_add_resource_offset(&sys->resources, &res[1], sys->mem_offset);
+
         return 1;
 }
 
diff --git a/arch/arm/mach-footbridge/include/mach/entry-macro.S b/arch/arm/mach-footbridge/include/mach/entry-macro.S
index d3847be0c66..dabbd5c54a7 100644
--- a/arch/arm/mach-footbridge/include/mach/entry-macro.S
+++ b/arch/arm/mach-footbridge/include/mach/entry-macro.S
@@ -14,9 +14,6 @@
                 .equ    dc21285_high, ARMCSR_BASE & 0xff000000
                 .equ    dc21285_low, ARMCSR_BASE & 0x00ffffff
 
-                .macro  disable_fiq
-                .endm
-
                 .macro  get_irqnr_preamble, base, tmp
                 mov     \base, #dc21285_high
                 .if     dc21285_low
@@ -24,9 +21,6 @@
                 .endif
                 .endm
 
-                .macro  arch_ret_to_user, tmp1, tmp2
-                .endm
-
                 .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
                 ldr     \irqstat, [\base, #0x180]       @ get interrupts
 
diff --git a/arch/arm/mach-footbridge/include/mach/system.h b/arch/arm/mach-footbridge/include/mach/system.h
deleted file mode 100644
index a174a5841bc..00000000000
--- a/arch/arm/mach-footbridge/include/mach/system.h
+++ /dev/null
@@ -1,13 +0,0 @@
-/*
- *  arch/arm/mach-footbridge/include/mach/system.h
- *
- *  Copyright (C) 1996-1999 Russell King.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-static inline void arch_idle(void)
-{
-        cpu_do_idle();
-}
diff --git a/arch/arm/mach-gemini/Makefile b/arch/arm/mach-gemini/Makefile
index c5b24b95a76..7355c0bbcb5 100644
--- a/arch/arm/mach-gemini/Makefile
+++ b/arch/arm/mach-gemini/Makefile
@@ -4,7 +4,7 @@
 
 # Object file lists.
 
-obj-y                   := irq.o mm.o time.o devices.o gpio.o
+obj-y                   := irq.o mm.o time.o devices.o gpio.o idle.o
 
 # Board-specific support
 obj-$(CONFIG_MACH_NAS4220B)     += board-nas4220b.o
diff --git a/arch/arm/mach-gemini/idle.c b/arch/arm/mach-gemini/idle.c
new file mode 100644
index 00000000000..92bbd6bb600
--- /dev/null
+++ b/arch/arm/mach-gemini/idle.c
@@ -0,0 +1,29 @@
+/*
+ * arch/arm/mach-gemini/idle.c
+ */
+
+#include <linux/init.h>
+#include <asm/system.h>
+#include <asm/proc-fns.h>
+
+static void gemini_idle(void)
+{
+        /*
+         * Because of broken hardware we have to enable interrupts or the CPU
+         * will never wakeup... Acctualy it is not very good to enable
+         * interrupts first since scheduler can miss a tick, but there is
+         * no other way around this. Platforms that needs it for power saving
+         * should call enable_hlt() in init code, since by default it is
+         * disabled.
+         */
+        local_irq_enable();
+        cpu_do_idle();
+}
+
+static int __init gemini_idle_init(void)
+{
+        arm_pm_idle = gemini_idle;
+        return 0;
+}
+
+arch_initcall(gemini_idle_init);
diff --git a/arch/arm/mach-gemini/include/mach/entry-macro.S b/arch/arm/mach-gemini/include/mach/entry-macro.S
index 1624f91a2b8..f044e430bfa 100644
--- a/arch/arm/mach-gemini/include/mach/entry-macro.S
+++ b/arch/arm/mach-gemini/include/mach/entry-macro.S
@@ -12,15 +12,9 @@
 
 #define IRQ_STATUS      0x14
 
-        .macro  disable_fiq
-        .endm
-
         .macro  get_irqnr_preamble, base, tmp
         .endm
 
-        .macro  arch_ret_to_user, tmp1, tmp2
-        .endm
-
         .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
         ldr     \irqstat, =IO_ADDRESS(GEMINI_INTERRUPT_BASE + IRQ_STATUS)
         ldr     \irqnr, [\irqstat]
diff --git a/arch/arm/mach-gemini/include/mach/system.h b/arch/arm/mach-gemini/include/mach/system.h
index 4d9c1f87247..a33b5a1f8ab 100644
--- a/arch/arm/mach-gemini/include/mach/system.h
+++ b/arch/arm/mach-gemini/include/mach/system.h
@@ -14,20 +14,6 @@
 #include <mach/hardware.h>
 #include <mach/global_reg.h>
 
-static inline void arch_idle(void)
-{
-        /*
-         * Because of broken hardware we have to enable interrupts or the CPU
-         * will never wakeup... Acctualy it is not very good to enable
-         * interrupts here since scheduler can miss a tick, but there is
-         * no other way around this. Platforms that needs it for power saving
-         * should call enable_hlt() in init code, since by default it is
-         * disabled.
-         */
-        local_irq_enable();
-        cpu_do_idle();
-}
-
 static inline void arch_reset(char mode, const char *cmd)
 {
         __raw_writel(RESET_GLOBAL | RESET_CPU1,
diff --git a/arch/arm/mach-gemini/irq.c b/arch/arm/mach-gemini/irq.c
index 9485a8fdf85..ca70e5fcc7a 100644
--- a/arch/arm/mach-gemini/irq.c
+++ b/arch/arm/mach-gemini/irq.c
@@ -73,8 +73,8 @@ void __init gemini_init_irq(void)
         unsigned int i, mode = 0, level = 0;
 
         /*
-         * Disable arch_idle() by default since it is buggy
-         * For more info see arch/arm/mach-gemini/include/mach/system.h
+         * Disable the idle handler by default since it is buggy
+         * For more info see arch/arm/mach-gemini/idle.c
          */
         disable_hlt();
 
diff --git a/arch/arm/mach-h720x/common.c b/arch/arm/mach-h720x/common.c
index f8a2f6bb548..e756d1ac00c 100644
--- a/arch/arm/mach-h720x/common.c
+++ b/arch/arm/mach-h720x/common.c
@@ -247,3 +247,21 @@ void h720x_restart(char mode, const char *cmd)
 {
         CPU_REG (PMU_BASE, PMU_STAT) |= PMU_WARMRESET;
 }
+
+static void h720x__idle(void)
+{
+        CPU_REG (PMU_BASE, PMU_MODE) = PMU_MODE_IDLE;
+        nop();
+        nop();
+        CPU_REG (PMU_BASE, PMU_MODE) = PMU_MODE_RUN;
+        nop();
+        nop();
+}
+
+static int __init h720x_idle_init(void)
+{
+        arm_pm_idle = h720x__idle;
+        return 0;
+}
+
+arch_initcall(h720x_idle_init);
diff --git a/arch/arm/mach-h720x/include/mach/entry-macro.S b/arch/arm/mach-h720x/include/mach/entry-macro.S
index c3948e5ba4a..75267fad701 100644
--- a/arch/arm/mach-h720x/include/mach/entry-macro.S
+++ b/arch/arm/mach-h720x/include/mach/entry-macro.S
@@ -8,15 +8,9 @@
  * warranty of any kind, whether express or implied.
  */
 
-                .macro  disable_fiq
-                .endm
-
                 .macro  get_irqnr_preamble, base, tmp
                 .endm
 
-                .macro  arch_ret_to_user, tmp1, tmp2
-                .endm
-
                 .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
 #if defined (CONFIG_CPU_H7201) || defined (CONFIG_CPU_H7202)
                 @ we could use the id register on H7202, but this is not
diff --git a/arch/arm/mach-h720x/include/mach/system.h b/arch/arm/mach-h720x/include/mach/system.h
deleted file mode 100644
index 16ac46e239a..00000000000
--- a/arch/arm/mach-h720x/include/mach/system.h
+++ /dev/null
@@ -1,27 +0,0 @@
-/*
- * arch/arm/mach-h720x/include/mach/system.h
- *
- * Copyright (C) 2001-2002 Jungjun Kim, Hynix Semiconductor Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- * arch/arm/mach-h720x/include/mach/system.h
- *
- */
-
-#ifndef __ASM_ARCH_SYSTEM_H
-#define __ASM_ARCH_SYSTEM_H
-#include <mach/hardware.h>
-
-static void arch_idle(void)
-{
-        CPU_REG (PMU_BASE, PMU_MODE) = PMU_MODE_IDLE;
-        nop();
-        nop();
-        CPU_REG (PMU_BASE, PMU_MODE) = PMU_MODE_RUN;
-        nop();
-        nop();
-}
-
-#endif
diff --git a/arch/arm/mach-highbank/Makefile b/arch/arm/mach-highbank/Makefile
index 986958a5a72..f8437dd238c 100644
--- a/arch/arm/mach-highbank/Makefile
+++ b/arch/arm/mach-highbank/Makefile
@@ -1,6 +1,5 @@
 obj-y                                   := clock.o highbank.o system.o
 obj-$(CONFIG_DEBUG_HIGHBANK_UART)       += lluart.o
 obj-$(CONFIG_SMP)                       += platsmp.o
-obj-$(CONFIG_LOCAL_TIMERS)              += localtimer.o
 obj-$(CONFIG_HOTPLUG_CPU)               += hotplug.o
 obj-$(CONFIG_PM_SLEEP)                  += pm.o
diff --git a/arch/arm/mach-highbank/highbank.c b/arch/arm/mach-highbank/highbank.c
index 8394d512a40..808b055289b 100644
--- a/arch/arm/mach-highbank/highbank.c
+++ b/arch/arm/mach-highbank/highbank.c
@@ -27,6 +27,7 @@
 #include <asm/cacheflush.h>
 #include <asm/smp_plat.h>
 #include <asm/smp_scu.h>
+#include <asm/smp_twd.h>
 #include <asm/hardware/arm_timer.h>
 #include <asm/hardware/timer-sp.h>
 #include <asm/hardware/gic.h>
@@ -109,8 +110,10 @@ static void __init highbank_timer_init(void)
 
         highbank_clocks_init();
 
-        sp804_clocksource_init(timer_base + 0x20, "timer1");
+        sp804_clocksource_and_sched_clock_init(timer_base + 0x20, "timer1");
         sp804_clockevents_init(timer_base, irq, "timer0");
+
+        twd_local_timer_of_register();
 }
 
 static struct sys_timer highbank_timer = {
diff --git a/arch/arm/mach-highbank/include/mach/entry-macro.S b/arch/arm/mach-highbank/include/mach/entry-macro.S
deleted file mode 100644
index a14f9e62ca9..00000000000
--- a/arch/arm/mach-highbank/include/mach/entry-macro.S
+++ /dev/null
@@ -1,5 +0,0 @@
-        .macro  disable_fiq
-        .endm
-
-        .macro  arch_ret_to_user, tmp1, tmp2
-        .endm
diff --git a/arch/arm/mach-highbank/include/mach/memory.h b/arch/arm/mach-highbank/include/mach/memory.h
deleted file mode 100644
index 40a8c178f10..00000000000
--- a/arch/arm/mach-highbank/include/mach/memory.h
+++ /dev/null
@@ -1 +0,0 @@
-/* empty */
diff --git a/arch/arm/mach-highbank/localtimer.c b/arch/arm/mach-highbank/localtimer.c
deleted file mode 100644
index 5a00e7945fd..00000000000
--- a/arch/arm/mach-highbank/localtimer.c
+++ /dev/null
@@ -1,40 +0,0 @@
-/*
- * Copyright 2010-2011 Calxeda, Inc.
- * Based on localtimer.c, Copyright (C) 2002 ARM Ltd.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program.  If not, see <http://www.gnu.org/licenses/>.
- */
-#include <linux/init.h>
-#include <linux/clockchips.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-#include <linux/of_irq.h>
-
-#include <asm/smp_twd.h>
-
-/*
- * Setup the local clock events for a CPU.
- */
-int __cpuinit local_timer_setup(struct clock_event_device *evt)
-{
-        struct device_node *np;
-
-        np = of_find_compatible_node(NULL, NULL, "arm,smp-twd");
-        if (!twd_base) {
-                twd_base = of_iomap(np, 0);
-                WARN_ON(!twd_base);
-        }
-        evt->irq = irq_of_parse_and_map(np, 0);
-        twd_timer_setup(evt);
-        return 0;
-}
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index 4defb97bbfc..52359f80c42 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -46,7 +46,6 @@ config SOC_IMX21
         bool
         select MACH_MX21
         select CPU_ARM926T
-        select ARCH_MXC_AUDMUX_V1
         select IMX_HAVE_DMA_V1
         select IMX_HAVE_IOMUX_V1
         select MXC_AVIC
@@ -55,7 +54,6 @@ config SOC_IMX25
         bool
         select ARCH_MX25
         select CPU_ARM926T
-        select ARCH_MXC_AUDMUX_V2
         select ARCH_MXC_IOMUX_V3
         select MXC_AVIC
 
@@ -63,7 +61,6 @@ config SOC_IMX27
         bool
         select MACH_MX27
         select CPU_ARM926T
-        select ARCH_MXC_AUDMUX_V1
         select IMX_HAVE_DMA_V1
         select IMX_HAVE_IOMUX_V1
         select MXC_AVIC
@@ -72,7 +69,6 @@ config SOC_IMX31
         bool
         select CPU_V6
         select IMX_HAVE_PLATFORM_MXC_RNGA
-        select ARCH_MXC_AUDMUX_V2
         select MXC_AVIC
         select SMP_ON_UP if SMP
 
@@ -80,7 +76,6 @@ config SOC_IMX35
         bool
         select CPU_V6
         select ARCH_MXC_IOMUX_V3
-        select ARCH_MXC_AUDMUX_V2
         select HAVE_EPIT
         select MXC_AVIC
         select SMP_ON_UP if SMP
@@ -89,7 +84,6 @@ config SOC_IMX5
         select CPU_V7
         select MXC_TZIC
         select ARCH_MXC_IOMUX_V3
-        select ARCH_MXC_AUDMUX_V2
         select ARCH_HAS_CPUFREQ
         select ARCH_MX5
         bool
@@ -304,6 +298,7 @@ config MACH_MX27_3DS
         select IMX_HAVE_PLATFORM_IMX_I2C
         select IMX_HAVE_PLATFORM_IMX_KEYPAD
         select IMX_HAVE_PLATFORM_IMX_UART
+        select IMX_HAVE_PLATFORM_MX2_CAMERA
         select IMX_HAVE_PLATFORM_MXC_EHCI
         select IMX_HAVE_PLATFORM_MXC_MMC
         select IMX_HAVE_PLATFORM_SPI_IMX
@@ -320,8 +315,10 @@ config MACH_IMX27_VISSTRIM_M10
         select IMX_HAVE_PLATFORM_IMX_I2C
         select IMX_HAVE_PLATFORM_IMX_SSI
         select IMX_HAVE_PLATFORM_IMX_UART
-        select IMX_HAVE_PLATFORM_MXC_MMC
+        select IMX_HAVE_PLATFORM_MX2_CAMERA
         select IMX_HAVE_PLATFORM_MXC_EHCI
+        select IMX_HAVE_PLATFORM_MXC_MMC
+        select LEDS_GPIO_REGISTER
         help
           Include support for Visstrim_m10 platform and its different variants.
           This includes specific configurations for the board and its
@@ -376,6 +373,14 @@ config MACH_IMX27IPCAM
           Include support for IMX27 IPCAM platform. This includes specific
           configurations for the board and its peripherals.
 
+config MACH_IMX27_DT
+        bool "Support i.MX27 platforms from device tree"
+        select SOC_IMX27
+        select USE_OF
+        help
+          Include support for Freescale i.MX27 based platforms
+          using the device tree for discovery
+
 endif
 
 if ARCH_IMX_V6_V7
@@ -492,6 +497,7 @@ config MACH_MX31MOBOARD
         bool "Support mx31moboard platforms (EPFL Mobots group)"
         select SOC_IMX31
         select IMX_HAVE_PLATFORM_FSL_USB2_UDC
+        select IMX_HAVE_PLATFORM_IMX2_WDT
         select IMX_HAVE_PLATFORM_IMX_I2C
         select IMX_HAVE_PLATFORM_IMX_UART
         select IMX_HAVE_PLATFORM_IPU_CORE
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index 55db9c488f2..35fc450fa26 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -8,8 +8,8 @@ obj-$(CONFIG_SOC_IMX25) += clock-imx25.o mm-imx25.o ehci-imx25.o cpu-imx25.o
 obj-$(CONFIG_SOC_IMX27) += cpu-imx27.o pm-imx27.o
 obj-$(CONFIG_SOC_IMX27) += clock-imx27.o mm-imx27.o ehci-imx27.o
 
-obj-$(CONFIG_SOC_IMX31) += mm-imx3.o cpu-imx31.o clock-imx31.o iomux-imx31.o ehci-imx31.o
-obj-$(CONFIG_SOC_IMX35) += mm-imx3.o cpu-imx35.o clock-imx35.o ehci-imx35.o
+obj-$(CONFIG_SOC_IMX31) += mm-imx3.o cpu-imx31.o clock-imx31.o iomux-imx31.o ehci-imx31.o pm-imx3.o
+obj-$(CONFIG_SOC_IMX35) += mm-imx3.o cpu-imx35.o clock-imx35.o ehci-imx35.o pm-imx3.o
 
 obj-$(CONFIG_SOC_IMX5) += cpu-imx5.o mm-imx5.o clock-mx51-mx53.o ehci-imx5.o pm-imx5.o cpu_op-mx51.o
 
@@ -41,6 +41,7 @@ obj-$(CONFIG_MACH_EUKREA_MBIMX27_BASEBOARD) += eukrea_mbimx27-baseboard.o
 obj-$(CONFIG_MACH_PCA100) += mach-pca100.o
 obj-$(CONFIG_MACH_MXT_TD60) += mach-mxt_td60.o
 obj-$(CONFIG_MACH_IMX27IPCAM) += mach-imx27ipcam.o
+obj-$(CONFIG_MACH_IMX27_DT) += imx27-dt.o
 
 # i.MX31 based machines
 obj-$(CONFIG_MACH_MX31ADS) += mach-mx31ads.o
@@ -71,7 +72,6 @@ obj-$(CONFIG_CPU_V7) += head-v7.o
 AFLAGS_head-v7.o :=-Wa,-march=armv7-a
 obj-$(CONFIG_SMP) += platsmp.o
 obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
-obj-$(CONFIG_LOCAL_TIMERS) += localtimer.o
 obj-$(CONFIG_SOC_IMX6Q) += clock-imx6q.o mach-imx6q.o
 
 ifeq ($(CONFIG_PM),y)
diff --git a/arch/arm/mach-imx/Makefile.boot b/arch/arm/mach-imx/Makefile.boot
index 6dfdbcc83af..3851d8a2787 100644
--- a/arch/arm/mach-imx/Makefile.boot
+++ b/arch/arm/mach-imx/Makefile.boot
@@ -38,5 +38,8 @@ zreladdr-$(CONFIG_SOC_IMX6Q)	+= 0x10008000
 params_phys-$(CONFIG_SOC_IMX6Q) := 0x10000100
 initrd_phys-$(CONFIG_SOC_IMX6Q) := 0x10800000
 
+dtb-$(CONFIG_MACH_IMX51_DT) += imx51-babbage.dtb
+dtb-$(CONFIG_MACH_IMX53_DT) += imx53-ard.dtb imx53-evk.dtb \
+                               imx53-qsb.dtb imx53-smd.dtb
 dtb-$(CONFIG_SOC_IMX6Q) += imx6q-arm2.dtb \
                            imx6q-sabrelite.dtb
diff --git a/arch/arm/mach-imx/clock-imx27.c b/arch/arm/mach-imx/clock-imx27.c
index 88fe00a146e..b9a95ed7555 100644
--- a/arch/arm/mach-imx/clock-imx27.c
+++ b/arch/arm/mach-imx/clock-imx27.c
@@ -22,6 +22,7 @@
 #include <linux/io.h>
 #include <linux/module.h>
 #include <linux/clkdev.h>
+#include <linux/of.h>
 
 #include <asm/div64.h>
 
@@ -661,7 +662,7 @@ static struct clk_lookup lookups[] = {
         _REGISTER_CLOCK(NULL, "dma", dma_clk)
         _REGISTER_CLOCK(NULL, "rtic", rtic_clk)
         _REGISTER_CLOCK(NULL, "brom", brom_clk)
-        _REGISTER_CLOCK(NULL, "emma", emma_clk)
+        _REGISTER_CLOCK("m2m-emmaprp.0", NULL, emma_clk)
         _REGISTER_CLOCK(NULL, "slcdc", slcdc_clk)
         _REGISTER_CLOCK("imx27-fec.0", NULL, fec_clk)
         _REGISTER_CLOCK(NULL, "emi", emi_clk)
@@ -764,3 +765,20 @@ int __init mx27_clocks_init(unsigned long fref)
         return 0;
 }
 
+#ifdef CONFIG_OF
+int __init mx27_clocks_init_dt(void)
+{
+        struct device_node *np;
+        u32 fref = 26000000; /* default */
+
+        for_each_compatible_node(np, NULL, "fixed-clock") {
+                if (!of_device_is_compatible(np, "fsl,imx-osc26m"))
+                        continue;
+
+                if (!of_property_read_u32(np, "clock-frequency", &fref))
+                        break;
+        }
+
+        return mx27_clocks_init(fref);
+}
+#endif
diff --git a/arch/arm/mach-imx/clock-imx31.c b/arch/arm/mach-imx/clock-imx31.c
index 988a28178d4..3a943cd4159 100644
--- a/arch/arm/mach-imx/clock-imx31.c
+++ b/arch/arm/mach-imx/clock-imx31.c
@@ -32,7 +32,7 @@
 #include <mach/mx31.h>
 #include <mach/common.h>
 
-#include "crmregs-imx31.h"
+#include "crmregs-imx3.h"
 
 #define PRE_DIV_MIN_FREQ    10000000 /* Minimum Frequency after Predivider */
 
diff --git a/arch/arm/mach-imx/clock-imx35.c b/arch/arm/mach-imx/clock-imx35.c
index ac8238caecb..1e279af656a 100644
--- a/arch/arm/mach-imx/clock-imx35.c
+++ b/arch/arm/mach-imx/clock-imx35.c
@@ -27,23 +27,7 @@
 #include <mach/hardware.h>
 #include <mach/common.h>
 
-#define CCM_BASE        MX35_IO_ADDRESS(MX35_CCM_BASE_ADDR)
-
-#define CCM_CCMR        0x00
-#define CCM_PDR0        0x04
-#define CCM_PDR1        0x08
-#define CCM_PDR2        0x0C
-#define CCM_PDR3        0x10
-#define CCM_PDR4        0x14
-#define CCM_RCSR        0x18
-#define CCM_MPCTL       0x1C
-#define CCM_PPCTL       0x20
-#define CCM_ACMR        0x24
-#define CCM_COSR        0x28
-#define CCM_CGR0        0x2C
-#define CCM_CGR1        0x30
-#define CCM_CGR2        0x34
-#define CCM_CGR3        0x38
+#include "crmregs-imx3.h"
 
 #ifdef HAVE_SET_RATE_SUPPORT
 static void calc_dividers(u32 div, u32 *pre, u32 *post, u32 maxpost)
@@ -111,14 +95,14 @@ static void calc_dividers_3_3(u32 div, u32 *pre, u32 *post)
 
 static unsigned long get_rate_mpll(void)
 {
-        ulong mpctl = __raw_readl(CCM_BASE + CCM_MPCTL);
+        ulong mpctl = __raw_readl(MX35_CCM_MPCTL);
 
         return mxc_decode_pll(mpctl, 24000000);
 }
 
 static unsigned long get_rate_ppll(void)
 {
-        ulong ppctl = __raw_readl(CCM_BASE + CCM_PPCTL);
+        ulong ppctl = __raw_readl(MX35_CCM_PPCTL);
 
         return mxc_decode_pll(ppctl, 24000000);
 }
@@ -148,7 +132,7 @@ static struct arm_ahb_div clk_consumer[] = {
 
 static unsigned long get_rate_arm(void)
 {
-        unsigned long pdr0 = __raw_readl(CCM_BASE + CCM_PDR0);
+        unsigned long pdr0 = __raw_readl(MXC_CCM_PDR0);
         struct arm_ahb_div *aad;
         unsigned long fref = get_rate_mpll();
 
@@ -161,7 +145,7 @@ static unsigned long get_rate_arm(void)
 
 static unsigned long get_rate_ahb(struct clk *clk)
 {
-        unsigned long pdr0 = __raw_readl(CCM_BASE + CCM_PDR0);
+        unsigned long pdr0 = __raw_readl(MXC_CCM_PDR0);
         struct arm_ahb_div *aad;
         unsigned long fref = get_rate_arm();
 
@@ -177,8 +161,8 @@ static unsigned long get_rate_ipg(struct clk *clk)
 
 static unsigned long get_rate_uart(struct clk *clk)
 {
-        unsigned long pdr3 = __raw_readl(CCM_BASE + CCM_PDR3);
-        unsigned long pdr4 = __raw_readl(CCM_BASE + CCM_PDR4);
+        unsigned long pdr3 = __raw_readl(MX35_CCM_PDR3);
+        unsigned long pdr4 = __raw_readl(MX35_CCM_PDR4);
         unsigned long div = ((pdr4 >> 10) & 0x3f) + 1;
 
         if (pdr3 & (1 << 14))
@@ -189,7 +173,7 @@ static unsigned long get_rate_uart(struct clk *clk)
 
 static unsigned long get_rate_sdhc(struct clk *clk)
 {
-        unsigned long pdr3 = __raw_readl(CCM_BASE + CCM_PDR3);
+        unsigned long pdr3 = __raw_readl(MX35_CCM_PDR3);
         unsigned long div, rate;
 
         if (pdr3 & (1 << 6))
@@ -215,7 +199,7 @@ static unsigned long get_rate_sdhc(struct clk *clk)
 
 static unsigned long get_rate_mshc(struct clk *clk)
 {
-        unsigned long pdr1 = __raw_readl(CCM_BASE + CCM_PDR1);
+        unsigned long pdr1 = __raw_readl(MXC_CCM_PDR1);
         unsigned long div1, div2, rate;
 
         if (pdr1 & (1 << 7))
@@ -231,7 +215,7 @@ static unsigned long get_rate_mshc(struct clk *clk)
 
 static unsigned long get_rate_ssi(struct clk *clk)
 {
-        unsigned long pdr2 = __raw_readl(CCM_BASE + CCM_PDR2);
+        unsigned long pdr2 = __raw_readl(MX35_CCM_PDR2);
         unsigned long div1, div2, rate;
 
         if (pdr2 & (1 << 6))
@@ -256,7 +240,7 @@ static unsigned long get_rate_ssi(struct clk *clk)
 
 static unsigned long get_rate_csi(struct clk *clk)
 {
-        unsigned long pdr2 = __raw_readl(CCM_BASE + CCM_PDR2);
+        unsigned long pdr2 = __raw_readl(MX35_CCM_PDR2);
         unsigned long rate;
 
         if (pdr2 & (1 << 7))
@@ -269,7 +253,7 @@ static unsigned long get_rate_csi(struct clk *clk)
 
 static unsigned long get_rate_otg(struct clk *clk)
 {
-        unsigned long pdr4 = __raw_readl(CCM_BASE + CCM_PDR4);
+        unsigned long pdr4 = __raw_readl(MX35_CCM_PDR4);
         unsigned long rate;
 
         if (pdr4 & (1 << 9))
@@ -282,8 +266,8 @@ static unsigned long get_rate_otg(struct clk *clk)
 
 static unsigned long get_rate_ipg_per(struct clk *clk)
 {
-        unsigned long pdr0 = __raw_readl(CCM_BASE + CCM_PDR0);
-        unsigned long pdr4 = __raw_readl(CCM_BASE + CCM_PDR4);
+        unsigned long pdr0 = __raw_readl(MXC_CCM_PDR0);
+        unsigned long pdr4 = __raw_readl(MX35_CCM_PDR4);
         unsigned long div;
 
         if (pdr0 & (1 << 26)) {
@@ -297,7 +281,7 @@ static unsigned long get_rate_ipg_per(struct clk *clk)
 
 static unsigned long get_rate_hsp(struct clk *clk)
 {
-        unsigned long hsp_podf = (__raw_readl(CCM_BASE + CCM_PDR0) >> 20) & 0x03;
+        unsigned long hsp_podf = (__raw_readl(MXC_CCM_PDR0) >> 20) & 0x03;
         unsigned long fref = get_rate_mpll();
 
         if (fref > 400 * 1000 * 1000) {
@@ -345,7 +329,7 @@ static void clk_cgr_disable(struct clk *clk)
 #define DEFINE_CLOCK(name, i, er, es, gr, sr)           \
         static struct clk name = {                      \
                 .id             = i,                    \
-                .enable_reg     = CCM_BASE + er,        \
+                .enable_reg     = er,                   \
                 .enable_shift   = es,                   \
                 .get_rate       = gr,                   \
                 .set_rate       = sr,                   \
@@ -353,59 +337,59 @@ static void clk_cgr_disable(struct clk *clk)
                 .disable        = clk_cgr_disable,      \
         }
 
-DEFINE_CLOCK(asrc_clk,   0, CCM_CGR0,  0, NULL, NULL);
-DEFINE_CLOCK(pata_clk,    0, CCM_CGR0,  2, get_rate_ipg, NULL);
-/* DEFINE_CLOCK(audmux_clk, 0, CCM_CGR0,  4, NULL, NULL); */
-DEFINE_CLOCK(can1_clk,   0, CCM_CGR0,  6, get_rate_ipg, NULL);
-DEFINE_CLOCK(can2_clk,   1, CCM_CGR0,  8, get_rate_ipg, NULL);
-DEFINE_CLOCK(cspi1_clk,  0, CCM_CGR0, 10, get_rate_ipg, NULL);
-DEFINE_CLOCK(cspi2_clk,  1, CCM_CGR0, 12, get_rate_ipg, NULL);
-DEFINE_CLOCK(ect_clk,    0, CCM_CGR0, 14, get_rate_ipg, NULL);
-DEFINE_CLOCK(edio_clk,   0, CCM_CGR0, 16, NULL, NULL);
-DEFINE_CLOCK(emi_clk,    0, CCM_CGR0, 18, get_rate_ipg, NULL);
-DEFINE_CLOCK(epit1_clk,  0, CCM_CGR0, 20, get_rate_ipg, NULL);
-DEFINE_CLOCK(epit2_clk,  1, CCM_CGR0, 22, get_rate_ipg, NULL);
-DEFINE_CLOCK(esai_clk,   0, CCM_CGR0, 24, NULL, NULL);
-DEFINE_CLOCK(esdhc1_clk, 0, CCM_CGR0, 26, get_rate_sdhc, NULL);
-DEFINE_CLOCK(esdhc2_clk, 1, CCM_CGR0, 28, get_rate_sdhc, NULL);
-DEFINE_CLOCK(esdhc3_clk, 2, CCM_CGR0, 30, get_rate_sdhc, NULL);
-
-DEFINE_CLOCK(fec_clk,    0, CCM_CGR1,  0, get_rate_ipg, NULL);
-DEFINE_CLOCK(gpio1_clk,  0, CCM_CGR1,  2, NULL, NULL);
-DEFINE_CLOCK(gpio2_clk,  1, CCM_CGR1,  4, NULL, NULL);
-DEFINE_CLOCK(gpio3_clk,  2, CCM_CGR1,  6, NULL, NULL);
-DEFINE_CLOCK(gpt_clk,    0, CCM_CGR1,  8, get_rate_ipg, NULL);
-DEFINE_CLOCK(i2c1_clk,   0, CCM_CGR1, 10, get_rate_ipg_per, NULL);
-DEFINE_CLOCK(i2c2_clk,   1, CCM_CGR1, 12, get_rate_ipg_per, NULL);
-DEFINE_CLOCK(i2c3_clk,   2, CCM_CGR1, 14, get_rate_ipg_per, NULL);
-DEFINE_CLOCK(iomuxc_clk, 0, CCM_CGR1, 16, NULL, NULL);
-DEFINE_CLOCK(ipu_clk,    0, CCM_CGR1, 18, get_rate_hsp, NULL);
-DEFINE_CLOCK(kpp_clk,    0, CCM_CGR1, 20, get_rate_ipg, NULL);
-DEFINE_CLOCK(mlb_clk,    0, CCM_CGR1, 22, get_rate_ahb, NULL);
-DEFINE_CLOCK(mshc_clk,   0, CCM_CGR1, 24, get_rate_mshc, NULL);
-DEFINE_CLOCK(owire_clk,  0, CCM_CGR1, 26, get_rate_ipg_per, NULL);
-DEFINE_CLOCK(pwm_clk,    0, CCM_CGR1, 28, get_rate_ipg_per, NULL);
-DEFINE_CLOCK(rngc_clk,   0, CCM_CGR1, 30, get_rate_ipg, NULL);
-
-DEFINE_CLOCK(rtc_clk,    0, CCM_CGR2,  0, get_rate_ipg, NULL);
-DEFINE_CLOCK(rtic_clk,   0, CCM_CGR2,  2, get_rate_ahb, NULL);
-DEFINE_CLOCK(scc_clk,    0, CCM_CGR2,  4, get_rate_ipg, NULL);
-DEFINE_CLOCK(sdma_clk,   0, CCM_CGR2,  6, NULL, NULL);
-DEFINE_CLOCK(spba_clk,   0, CCM_CGR2,  8, get_rate_ipg, NULL);
-DEFINE_CLOCK(spdif_clk,  0, CCM_CGR2, 10, NULL, NULL);
-DEFINE_CLOCK(ssi1_clk,   0, CCM_CGR2, 12, get_rate_ssi, NULL);
-DEFINE_CLOCK(ssi2_clk,   1, CCM_CGR2, 14, get_rate_ssi, NULL);
-DEFINE_CLOCK(uart1_clk,  0, CCM_CGR2, 16, get_rate_uart, NULL);
-DEFINE_CLOCK(uart2_clk,  1, CCM_CGR2, 18, get_rate_uart, NULL);
-DEFINE_CLOCK(uart3_clk,  2, CCM_CGR2, 20, get_rate_uart, NULL);
-DEFINE_CLOCK(usbotg_clk, 0, CCM_CGR2, 22, get_rate_otg, NULL);
-DEFINE_CLOCK(wdog_clk,   0, CCM_CGR2, 24, NULL, NULL);
-DEFINE_CLOCK(max_clk,    0, CCM_CGR2, 26, NULL, NULL);
-DEFINE_CLOCK(audmux_clk, 0, CCM_CGR2, 30, NULL, NULL);
-
-DEFINE_CLOCK(csi_clk,    0, CCM_CGR3,  0, get_rate_csi, NULL);
-DEFINE_CLOCK(iim_clk,    0, CCM_CGR3,  2, NULL, NULL);
-DEFINE_CLOCK(gpu2d_clk,  0, CCM_CGR3,  4, NULL, NULL);
+DEFINE_CLOCK(asrc_clk,   0, MX35_CCM_CGR0,  0, NULL, NULL);
+DEFINE_CLOCK(pata_clk,    0, MX35_CCM_CGR0,  2, get_rate_ipg, NULL);
+/* DEFINE_CLOCK(audmux_clk, 0, MX35_CCM_CGR0,  4, NULL, NULL); */
+DEFINE_CLOCK(can1_clk,   0, MX35_CCM_CGR0,  6, get_rate_ipg, NULL);
+DEFINE_CLOCK(can2_clk,   1, MX35_CCM_CGR0,  8, get_rate_ipg, NULL);
+DEFINE_CLOCK(cspi1_clk,  0, MX35_CCM_CGR0, 10, get_rate_ipg, NULL);
+DEFINE_CLOCK(cspi2_clk,  1, MX35_CCM_CGR0, 12, get_rate_ipg, NULL);
+DEFINE_CLOCK(ect_clk,    0, MX35_CCM_CGR0, 14, get_rate_ipg, NULL);
+DEFINE_CLOCK(edio_clk,   0, MX35_CCM_CGR0, 16, NULL, NULL);
+DEFINE_CLOCK(emi_clk,    0, MX35_CCM_CGR0, 18, get_rate_ipg, NULL);
+DEFINE_CLOCK(epit1_clk,  0, MX35_CCM_CGR0, 20, get_rate_ipg, NULL);
+DEFINE_CLOCK(epit2_clk,  1, MX35_CCM_CGR0, 22, get_rate_ipg, NULL);
+DEFINE_CLOCK(esai_clk,   0, MX35_CCM_CGR0, 24, NULL, NULL);
+DEFINE_CLOCK(esdhc1_clk, 0, MX35_CCM_CGR0, 26, get_rate_sdhc, NULL);
+DEFINE_CLOCK(esdhc2_clk, 1, MX35_CCM_CGR0, 28, get_rate_sdhc, NULL);
+DEFINE_CLOCK(esdhc3_clk, 2, MX35_CCM_CGR0, 30, get_rate_sdhc, NULL);
+
+DEFINE_CLOCK(fec_clk,    0, MX35_CCM_CGR1,  0, get_rate_ipg, NULL);
+DEFINE_CLOCK(gpio1_clk,  0, MX35_CCM_CGR1,  2, NULL, NULL);
+DEFINE_CLOCK(gpio2_clk,  1, MX35_CCM_CGR1,  4, NULL, NULL);
+DEFINE_CLOCK(gpio3_clk,  2, MX35_CCM_CGR1,  6, NULL, NULL);
+DEFINE_CLOCK(gpt_clk,    0, MX35_CCM_CGR1,  8, get_rate_ipg, NULL);
+DEFINE_CLOCK(i2c1_clk,   0, MX35_CCM_CGR1, 10, get_rate_ipg_per, NULL);
+DEFINE_CLOCK(i2c2_clk,   1, MX35_CCM_CGR1, 12, get_rate_ipg_per, NULL);
+DEFINE_CLOCK(i2c3_clk,   2, MX35_CCM_CGR1, 14, get_rate_ipg_per, NULL);
+DEFINE_CLOCK(iomuxc_clk, 0, MX35_CCM_CGR1, 16, NULL, NULL);
+DEFINE_CLOCK(ipu_clk,    0, MX35_CCM_CGR1, 18, get_rate_hsp, NULL);
+DEFINE_CLOCK(kpp_clk,    0, MX35_CCM_CGR1, 20, get_rate_ipg, NULL);
+DEFINE_CLOCK(mlb_clk,    0, MX35_CCM_CGR1, 22, get_rate_ahb, NULL);
+DEFINE_CLOCK(mshc_clk,   0, MX35_CCM_CGR1, 24, get_rate_mshc, NULL);
+DEFINE_CLOCK(owire_clk,  0, MX35_CCM_CGR1, 26, get_rate_ipg_per, NULL);
+DEFINE_CLOCK(pwm_clk,    0, MX35_CCM_CGR1, 28, get_rate_ipg_per, NULL);
+DEFINE_CLOCK(rngc_clk,   0, MX35_CCM_CGR1, 30, get_rate_ipg, NULL);
+
+DEFINE_CLOCK(rtc_clk,    0, MX35_CCM_CGR2,  0, get_rate_ipg, NULL);
+DEFINE_CLOCK(rtic_clk,   0, MX35_CCM_CGR2,  2, get_rate_ahb, NULL);
+DEFINE_CLOCK(scc_clk,    0, MX35_CCM_CGR2,  4, get_rate_ipg, NULL);
+DEFINE_CLOCK(sdma_clk,   0, MX35_CCM_CGR2,  6, NULL, NULL);
+DEFINE_CLOCK(spba_clk,   0, MX35_CCM_CGR2,  8, get_rate_ipg, NULL);
+DEFINE_CLOCK(spdif_clk,  0, MX35_CCM_CGR2, 10, NULL, NULL);
+DEFINE_CLOCK(ssi1_clk,   0, MX35_CCM_CGR2, 12, get_rate_ssi, NULL);
+DEFINE_CLOCK(ssi2_clk,   1, MX35_CCM_CGR2, 14, get_rate_ssi, NULL);
+DEFINE_CLOCK(uart1_clk,  0, MX35_CCM_CGR2, 16, get_rate_uart, NULL);
+DEFINE_CLOCK(uart2_clk,  1, MX35_CCM_CGR2, 18, get_rate_uart, NULL);
+DEFINE_CLOCK(uart3_clk,  2, MX35_CCM_CGR2, 20, get_rate_uart, NULL);
+DEFINE_CLOCK(usbotg_clk, 0, MX35_CCM_CGR2, 22, get_rate_otg, NULL);
+DEFINE_CLOCK(wdog_clk,   0, MX35_CCM_CGR2, 24, NULL, NULL);
+DEFINE_CLOCK(max_clk,    0, MX35_CCM_CGR2, 26, NULL, NULL);
+DEFINE_CLOCK(audmux_clk, 0, MX35_CCM_CGR2, 30, NULL, NULL);
+
+DEFINE_CLOCK(csi_clk,    0, MX35_CCM_CGR3,  0, get_rate_csi, NULL);
+DEFINE_CLOCK(iim_clk,    0, MX35_CCM_CGR3,  2, NULL, NULL);
+DEFINE_CLOCK(gpu2d_clk,  0, MX35_CCM_CGR3,  4, NULL, NULL);
 
 DEFINE_CLOCK(usbahb_clk, 0, 0,         0, get_rate_ahb, NULL);
 
@@ -422,7 +406,7 @@ static unsigned long get_rate_nfc(struct clk *clk)
 {
         unsigned long div1;
 
-        div1 = (__raw_readl(CCM_BASE + CCM_PDR4) >> 28) + 1;
+        div1 = (__raw_readl(MX35_CCM_PDR4) >> 28) + 1;
 
         return get_rate_ahb(NULL) / div1;
 }
@@ -518,11 +502,11 @@ int __init mx35_clocks_init()
         /* Turn off all clocks except the ones we need to survive, namely:
          * EMI, GPIO1/2/3, GPT, IOMUX, MAX and eventually uart
          */
-        __raw_writel((3 << 18), CCM_BASE + CCM_CGR0);
+        __raw_writel((3 << 18), MX35_CCM_CGR0);
         __raw_writel((3 << 2) | (3 << 4) | (3 << 6) | (3 << 8) | (3 << 16),
-                        CCM_BASE + CCM_CGR1);
-        __raw_writel(cgr2, CCM_BASE + CCM_CGR2);
-        __raw_writel(0, CCM_BASE + CCM_CGR3);
+                        MX35_CCM_CGR1);
+        __raw_writel(cgr2, MX35_CCM_CGR2);
+        __raw_writel(0, MX35_CCM_CGR3);
 
         clk_enable(&iim_clk);
         imx_print_silicon_rev("i.MX35", mx35_revision());
@@ -533,7 +517,7 @@ int __init mx35_clocks_init()
          * extra clocks turned on, otherwise the MX35 boot ROM code will
          * hang after a watchdog reset.
          */
-        if (!(__raw_readl(CCM_BASE + CCM_RCSR) & (3 << 10))) {
+        if (!(__raw_readl(MX35_CCM_RCSR) & (3 << 10))) {
                 /* Additionally turn on UART1, SCC, and IIM clocks */
                 clk_enable(&iim_clk);
                 clk_enable(&uart1_clk);
diff --git a/arch/arm/mach-imx/clock-imx6q.c b/arch/arm/mach-imx/clock-imx6q.c
index 2d88f8b9a45..111c328f542 100644
--- a/arch/arm/mach-imx/clock-imx6q.c
+++ b/arch/arm/mach-imx/clock-imx6q.c
@@ -329,6 +329,12 @@
 #define BM_CLPCR_MASK_SCU_IDLE          (0x1 << 26)
 #define BM_CLPCR_MASK_L2CC_IDLE         (0x1 << 27)
 
+#define BP_CCOSR_CKO1_EN                7
+#define BP_CCOSR_CKO1_PODF              4
+#define BM_CCOSR_CKO1_PODF              (0x7 << 4)
+#define BP_CCOSR_CKO1_SEL               0
+#define BM_CCOSR_CKO1_SEL               (0xf << 0)
+
 #define FREQ_480M       480000000
 #define FREQ_528M       528000000
 #define FREQ_594M       594000000
@@ -393,6 +399,7 @@ static struct clk ipu1_di1_clk;
 static struct clk ipu2_di0_clk;
 static struct clk ipu2_di1_clk;
 static struct clk enfc_clk;
+static struct clk cko1_clk;
 static struct clk dummy_clk = {};
 
 static unsigned long external_high_reference;
@@ -938,6 +945,24 @@ static void _clk_disable(struct clk *clk)
         writel_relaxed(reg, clk->enable_reg);
 }
 
+static int _clk_enable_1b(struct clk *clk)
+{
+        u32 reg;
+        reg = readl_relaxed(clk->enable_reg);
+        reg |= 0x1 << clk->enable_shift;
+        writel_relaxed(reg, clk->enable_reg);
+
+        return 0;
+}
+
+static void _clk_disable_1b(struct clk *clk)
+{
+        u32 reg;
+        reg = readl_relaxed(clk->enable_reg);
+        reg &= ~(0x1 << clk->enable_shift);
+        writel_relaxed(reg, clk->enable_reg);
+}
+
 struct divider {
         struct clk *clk;
         void __iomem *reg;
@@ -983,6 +1008,7 @@ DEF_CLK_DIV1(ipu2_di0_pre_div,	&ipu2_di0_pre_clk,	CSCDR2,	IPU2_DI0_PRE);
 DEF_CLK_DIV1(ipu2_di1_pre_div,  &ipu2_di1_pre_clk,      CSCDR2, IPU2_DI1_PRE);
 DEF_CLK_DIV1(ipu1_div,          &ipu1_clk,              CSCDR3, IPU1_HSP);
 DEF_CLK_DIV1(ipu2_div,          &ipu2_clk,              CSCDR3, IPU2_HSP);
+DEF_CLK_DIV1(cko1_div,          &cko1_clk,              CCOSR, CKO1);
 
 #define DEF_CLK_DIV2(d, c, r, b)                                \
         static struct divider d = {                             \
@@ -1038,6 +1064,7 @@ static struct divider *dividers[] = {
         &enfc_div,
         &spdif_div,
         &asrc_serial_div,
+        &cko1_div,
 };
 
 static unsigned long ldb_di_clk_get_rate(struct clk *clk)
@@ -1625,6 +1652,32 @@ DEF_IPU_DI_MUX(CSCDR2, 2, 1);
 DEF_IPU_MUX(1);
 DEF_IPU_MUX(2);
 
+static struct multiplexer cko1_mux = {
+        .clk = &cko1_clk,
+        .reg = CCOSR,
+        .bp = BP_CCOSR_CKO1_SEL,
+        .bm = BM_CCOSR_CKO1_SEL,
+        .parents = {
+                &pll3_usb_otg,
+                &pll2_bus,
+                &pll1_sys,
+                &pll5_video,
+                &dummy_clk,
+                &axi_clk,
+                &enfc_clk,
+                &ipu1_di0_clk,
+                &ipu1_di1_clk,
+                &ipu2_di0_clk,
+                &ipu2_di1_clk,
+                &ahb_clk,
+                &ipg_clk,
+                &ipg_perclk,
+                &ckil_clk,
+                &pll4_audio,
+                NULL
+        },
+};
+
 static struct multiplexer *multiplexers[] = {
         &axi_mux,
         &periph_mux,
@@ -1667,6 +1720,7 @@ static struct multiplexer *multiplexers[] = {
         &ipu2_di1_mux,
         &ipu1_mux,
         &ipu2_mux,
+        &cko1_mux,
 };
 
 static int _clk_set_parent(struct clk *clk, struct clk *parent)
@@ -1690,7 +1744,7 @@ static int _clk_set_parent(struct clk *clk, struct clk *parent)
                         break;
                 i++;
         }
-        if (!m->parents[i])
+        if (!m->parents[i] || m->parents[i] == &dummy_clk)
                 return -EINVAL;
 
         val = readl_relaxed(m->reg);
@@ -1745,6 +1799,20 @@ DEF_NG_CLK(asrc_serial_clk,	&pll3_usb_otg);
                 .secondary      = s,                    \
         }
 
+#define DEF_CLK_1B(name, er, es, p, s)                  \
+        static struct clk name = {                      \
+                .enable_reg     = er,                   \
+                .enable_shift   = es,                   \
+                .enable         = _clk_enable_1b,       \
+                .disable        = _clk_disable_1b,      \
+                .get_rate       = _clk_get_rate,        \
+                .set_rate       = _clk_set_rate,        \
+                .round_rate     = _clk_round_rate,      \
+                .set_parent     = _clk_set_parent,      \
+                .parent         = p,                    \
+                .secondary      = s,                    \
+        }
+
 DEF_CLK(aips_tz1_clk,     CCGR0, CG0,  &ahb_clk,          NULL);
 DEF_CLK(aips_tz2_clk,     CCGR0, CG1,  &ahb_clk,          NULL);
 DEF_CLK(apbh_dma_clk,     CCGR0, CG2,  &ahb_clk,          NULL);
@@ -1811,6 +1879,7 @@ DEF_CLK(usdhc4_clk,	  CCGR6, CG4,  &pll2_pfd_400m,	  NULL);
 DEF_CLK(emi_slow_clk,     CCGR6, CG5,  &axi_clk,          NULL);
 DEF_CLK(vdo_axi_clk,      CCGR6, CG6,  &axi_clk,          NULL);
 DEF_CLK(vpu_clk,          CCGR6, CG7,  &axi_clk,          NULL);
+DEF_CLK_1B(cko1_clk,      CCOSR, BP_CCOSR_CKO1_EN, &pll2_bus, NULL);
 
 static int pcie_clk_enable(struct clk *clk)
 {
@@ -1922,6 +1991,7 @@ static struct clk_lookup lookups[] = {
         _REGISTER_CLOCK(NULL, "gpmi_io_clk", gpmi_io_clk),
         _REGISTER_CLOCK(NULL, "usboh3_clk", usboh3_clk),
         _REGISTER_CLOCK(NULL, "sata_clk", sata_clk),
+        _REGISTER_CLOCK(NULL, "cko1_clk", cko1_clk),
 };
 
 int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode)
@@ -2029,6 +2099,8 @@ int __init mx6q_clocks_init(void)
         clk_set_rate(&usdhc3_clk, 49500000);
         clk_set_rate(&usdhc4_clk, 49500000);
 
+        clk_set_parent(&cko1_clk, &ahb_clk);
+
         np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-gpt");
         base = of_iomap(np, 0);
         WARN_ON(!base);
diff --git a/arch/arm/mach-imx/cpu-imx5.c b/arch/arm/mach-imx/cpu-imx5.c
index 5e2e7a84386..aa15c517d06 100644
--- a/arch/arm/mach-imx/cpu-imx5.c
+++ b/arch/arm/mach-imx/cpu-imx5.c
@@ -149,39 +149,3 @@ int mx50_revision(void)
         return mx5_cpu_rev;
 }
 EXPORT_SYMBOL(mx50_revision);
-
-static int __init post_cpu_init(void)
-{
-        unsigned int reg;
-        void __iomem *base;
-
-        if (cpu_is_mx51() || cpu_is_mx53()) {
-                if (cpu_is_mx51())
-                        base = MX51_IO_ADDRESS(MX51_AIPS1_BASE_ADDR);
-                else
-                        base = MX53_IO_ADDRESS(MX53_AIPS1_BASE_ADDR);
-
-                __raw_writel(0x0, base + 0x40);
-                __raw_writel(0x0, base + 0x44);
-                __raw_writel(0x0, base + 0x48);
-                __raw_writel(0x0, base + 0x4C);
-                reg = __raw_readl(base + 0x50) & 0x00FFFFFF;
-                __raw_writel(reg, base + 0x50);
-
-                if (cpu_is_mx51())
-                        base = MX51_IO_ADDRESS(MX51_AIPS2_BASE_ADDR);
-                else
-                        base = MX53_IO_ADDRESS(MX53_AIPS2_BASE_ADDR);
-
-                __raw_writel(0x0, base + 0x40);
-                __raw_writel(0x0, base + 0x44);
-                __raw_writel(0x0, base + 0x48);
-                __raw_writel(0x0, base + 0x4C);
-                reg = __raw_readl(base + 0x50) & 0x00FFFFFF;
-                __raw_writel(reg, base + 0x50);
-        }
-
-        return 0;
-}
-
-postcore_initcall(post_cpu_init);
diff --git a/arch/arm/mach-imx/cpu_op-mx51.c b/arch/arm/mach-imx/cpu_op-mx51.c
index 9d34c3d4c02..7b92cd6da6d 100644
--- a/arch/arm/mach-imx/cpu_op-mx51.c
+++ b/arch/arm/mach-imx/cpu_op-mx51.c
@@ -11,6 +11,7 @@
  * http://www.gnu.org/copyleft/gpl.html
  */
 
+#include <linux/bug.h>
 #include <linux/types.h>
 #include <mach/hardware.h>
 #include <linux/kernel.h>
diff --git a/arch/arm/mach-imx/crmregs-imx31.h b/arch/arm/mach-imx/crmregs-imx3.h
index 37a8a07beda..53141273df4 100644
--- a/arch/arm/mach-imx/crmregs-imx31.h
+++ b/arch/arm/mach-imx/crmregs-imx3.h
@@ -24,23 +24,36 @@
 #define CKIH_CLK_FREQ_27MHZ     27000000
 #define CKIL_CLK_FREQ           32768
 
-#define MXC_CCM_BASE            MX31_IO_ADDRESS(MX31_CCM_BASE_ADDR)
+#define MXC_CCM_BASE            (cpu_is_mx31() ? \
+MX31_IO_ADDRESS(MX31_CCM_BASE_ADDR) : MX35_IO_ADDRESS(MX35_CCM_BASE_ADDR))
 
 /* Register addresses */
 #define MXC_CCM_CCMR            (MXC_CCM_BASE + 0x00)
 #define MXC_CCM_PDR0            (MXC_CCM_BASE + 0x04)
 #define MXC_CCM_PDR1            (MXC_CCM_BASE + 0x08)
+#define MX35_CCM_PDR2           (MXC_CCM_BASE + 0x0C)
 #define MXC_CCM_RCSR            (MXC_CCM_BASE + 0x0C)
+#define MX35_CCM_PDR3           (MXC_CCM_BASE + 0x10)
 #define MXC_CCM_MPCTL           (MXC_CCM_BASE + 0x10)
+#define MX35_CCM_PDR4           (MXC_CCM_BASE + 0x14)
 #define MXC_CCM_UPCTL           (MXC_CCM_BASE + 0x14)
+#define MX35_CCM_RCSR           (MXC_CCM_BASE + 0x18)
 #define MXC_CCM_SRPCTL          (MXC_CCM_BASE + 0x18)
+#define MX35_CCM_MPCTL          (MXC_CCM_BASE + 0x1C)
 #define MXC_CCM_COSR            (MXC_CCM_BASE + 0x1C)
+#define MX35_CCM_PPCTL          (MXC_CCM_BASE + 0x20)
 #define MXC_CCM_CGR0            (MXC_CCM_BASE + 0x20)
+#define MX35_CCM_ACMR           (MXC_CCM_BASE + 0x24)
 #define MXC_CCM_CGR1            (MXC_CCM_BASE + 0x24)
+#define MX35_CCM_COSR           (MXC_CCM_BASE + 0x28)
 #define MXC_CCM_CGR2            (MXC_CCM_BASE + 0x28)
+#define MX35_CCM_CGR0           (MXC_CCM_BASE + 0x2C)
 #define MXC_CCM_WIMR            (MXC_CCM_BASE + 0x2C)
+#define MX35_CCM_CGR1           (MXC_CCM_BASE + 0x30)
 #define MXC_CCM_LDC             (MXC_CCM_BASE + 0x30)
+#define MX35_CCM_CGR2           (MXC_CCM_BASE + 0x34)
 #define MXC_CCM_DCVR0           (MXC_CCM_BASE + 0x34)
+#define MX35_CCM_CGR3           (MXC_CCM_BASE + 0x38)
 #define MXC_CCM_DCVR1           (MXC_CCM_BASE + 0x38)
 #define MXC_CCM_DCVR2           (MXC_CCM_BASE + 0x3C)
 #define MXC_CCM_DCVR3           (MXC_CCM_BASE + 0x40)
@@ -64,6 +77,7 @@
 #define MXC_CCM_CCMR_SSI2S_MASK                 (0x3 << 21)
 #define MXC_CCM_CCMR_LPM_OFFSET                 14
 #define MXC_CCM_CCMR_LPM_MASK                   (0x3 << 14)
+#define MXC_CCM_CCMR_LPM_WAIT_MX35              (0x1 << 14)
 #define MXC_CCM_CCMR_FIRS_OFFSET                11
 #define MXC_CCM_CCMR_FIRS_MASK                  (0x3 << 11)
 #define MXC_CCM_CCMR_UPE                        (1 << 9)
diff --git a/arch/arm/mach-imx/devices-imx27.h b/arch/arm/mach-imx/devices-imx27.h
index 2f727d7c380..28537a5d904 100644
--- a/arch/arm/mach-imx/devices-imx27.h
+++ b/arch/arm/mach-imx/devices-imx27.h
@@ -50,6 +50,8 @@ extern const struct imx_imx_uart_1irq_data imx27_imx_uart_data[];
 extern const struct imx_mx2_camera_data imx27_mx2_camera_data;
 #define imx27_add_mx2_camera(pdata)     \
         imx_add_mx2_camera(&imx27_mx2_camera_data, pdata)
+#define imx27_add_mx2_emmaprp(pdata)    \
+        imx_add_mx2_emmaprp(&imx27_mx2_camera_data)
 
 extern const struct imx_mxc_ehci_data imx27_mxc_ehci_otg_data;
 #define imx27_add_mxc_ehci_otg(pdata)   \
diff --git a/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c b/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c
index 5db3e1463af..5f2f91d1798 100644
--- a/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c
+++ b/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c
@@ -32,7 +32,6 @@
 #include <mach/common.h>
 #include <mach/iomux-mx27.h>
 #include <mach/hardware.h>
-#include <mach/audmux.h>
 
 #include "devices-imx27.h"
 
@@ -306,25 +305,6 @@ void __init eukrea_mbimx27_baseboard_init(void)
         mxc_gpio_setup_multiple_pins(eukrea_mbimx27_pins,
                 ARRAY_SIZE(eukrea_mbimx27_pins), "MBIMX27");
 
-#if defined(CONFIG_SND_SOC_EUKREA_TLV320) \
-        || defined(CONFIG_SND_SOC_EUKREA_TLV320_MODULE)
-        /* SSI unit master I2S codec connected to SSI_PINS_4*/
-        mxc_audmux_v1_configure_port(MX27_AUDMUX_HPCR1_SSI0,
-                        MXC_AUDMUX_V1_PCR_SYN |
-                        MXC_AUDMUX_V1_PCR_TFSDIR |
-                        MXC_AUDMUX_V1_PCR_TCLKDIR |
-                        MXC_AUDMUX_V1_PCR_RFSDIR |
-                        MXC_AUDMUX_V1_PCR_RCLKDIR |
-                        MXC_AUDMUX_V1_PCR_TFCSEL(MX27_AUDMUX_HPCR3_SSI_PINS_4) |
-                        MXC_AUDMUX_V1_PCR_RFCSEL(MX27_AUDMUX_HPCR3_SSI_PINS_4) |
-                        MXC_AUDMUX_V1_PCR_RXDSEL(MX27_AUDMUX_HPCR3_SSI_PINS_4)
-        );
-        mxc_audmux_v1_configure_port(MX27_AUDMUX_HPCR3_SSI_PINS_4,
-                        MXC_AUDMUX_V1_PCR_SYN |
-                        MXC_AUDMUX_V1_PCR_RXDSEL(MX27_AUDMUX_HPCR1_SSI0)
-        );
-#endif
-
         imx27_add_imx_uart1(&uart_pdata);
         imx27_add_imx_uart2(&uart_pdata);
 #if !defined(MACH_EUKREA_CPUIMX27_USEUART4)
diff --git a/arch/arm/mach-imx/eukrea_mbimxsd-baseboard.c b/arch/arm/mach-imx/eukrea_mbimxsd-baseboard.c
index d817fc80b98..aaa592fdb9c 100644
--- a/arch/arm/mach-imx/eukrea_mbimxsd-baseboard.c
+++ b/arch/arm/mach-imx/eukrea_mbimxsd-baseboard.c
@@ -37,7 +37,6 @@
 #include <mach/hardware.h>
 #include <mach/common.h>
 #include <mach/iomux-mx51.h>
-#include <mach/audmux.h>
 
 #include "devices-imx51.h"
 
diff --git a/arch/arm/mach-imx/eukrea_mbimxsd25-baseboard.c b/arch/arm/mach-imx/eukrea_mbimxsd25-baseboard.c
index 66e8726253f..2cf603e11c4 100644
--- a/arch/arm/mach-imx/eukrea_mbimxsd25-baseboard.c
+++ b/arch/arm/mach-imx/eukrea_mbimxsd25-baseboard.c
@@ -31,7 +31,6 @@
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <mach/mx25.h>
-#include <mach/audmux.h>
 
 #include "devices-imx25.h"
 
@@ -241,22 +240,6 @@ void __init eukrea_mbimxsd25_baseboard_init(void)
                         ARRAY_SIZE(eukrea_mbimxsd_pads)))
                 printk(KERN_ERR "error setting mbimxsd pads !\n");
 
-#if defined(CONFIG_SND_SOC_EUKREA_TLV320)
-        /* SSI unit master I2S codec connected to SSI_AUD5*/
-        mxc_audmux_v2_configure_port(0,
-                        MXC_AUDMUX_V2_PTCR_SYN |
-                        MXC_AUDMUX_V2_PTCR_TFSDIR |
-                        MXC_AUDMUX_V2_PTCR_TFSEL(4) |
-                        MXC_AUDMUX_V2_PTCR_TCLKDIR |
-                        MXC_AUDMUX_V2_PTCR_TCSEL(4),
-                        MXC_AUDMUX_V2_PDCR_RXDSEL(4)
-        );
-        mxc_audmux_v2_configure_port(4,
-                        MXC_AUDMUX_V2_PTCR_SYN,
-                        MXC_AUDMUX_V2_PDCR_RXDSEL(0)
-        );
-#endif
-
         imx25_add_imx_uart1(&uart_pdata);
         imx25_add_imx_fb(&eukrea_mximxsd_fb_pdata);
         imx25_add_imx_ssi(0, &eukrea_mbimxsd_ssi_pdata);
diff --git a/arch/arm/mach-imx/eukrea_mbimxsd35-baseboard.c b/arch/arm/mach-imx/eukrea_mbimxsd35-baseboard.c
index 0f0af02b318..fd8bf8a425a 100644
--- a/arch/arm/mach-imx/eukrea_mbimxsd35-baseboard.c
+++ b/arch/arm/mach-imx/eukrea_mbimxsd35-baseboard.c
@@ -38,7 +38,6 @@
 #include <mach/hardware.h>
 #include <mach/common.h>
 #include <mach/iomux-mx35.h>
-#include <mach/audmux.h>
 
 #include "devices-imx35.h"
 
@@ -252,22 +251,6 @@ void __init eukrea_mbimxsd35_baseboard_init(void)
                         ARRAY_SIZE(eukrea_mbimxsd_pads)))
                 printk(KERN_ERR "error setting mbimxsd pads !\n");
 
-#if defined(CONFIG_SND_SOC_EUKREA_TLV320)
-        /* SSI unit master I2S codec connected to SSI_AUD4 */
-        mxc_audmux_v2_configure_port(0,
-                        MXC_AUDMUX_V2_PTCR_SYN |
-                        MXC_AUDMUX_V2_PTCR_TFSDIR |
-                        MXC_AUDMUX_V2_PTCR_TFSEL(3) |
-                        MXC_AUDMUX_V2_PTCR_TCLKDIR |
-                        MXC_AUDMUX_V2_PTCR_TCSEL(3),
-                        MXC_AUDMUX_V2_PDCR_RXDSEL(3)
-        );
-        mxc_audmux_v2_configure_port(3,
-                        MXC_AUDMUX_V2_PTCR_SYN,
-                        MXC_AUDMUX_V2_PDCR_RXDSEL(0)
-        );
-#endif
-
         imx35_add_imx_uart1(&uart_pdata);
         imx35_add_ipu_core(&mx3_ipu_data);
         imx35_add_mx3_sdc_fb(&mx3fb_pdata);
diff --git a/arch/arm/mach-imx/imx27-dt.c b/arch/arm/mach-imx/imx27-dt.c
new file mode 100644
index 00000000000..861ceb8232d
--- /dev/null
+++ b/arch/arm/mach-imx/imx27-dt.c
@@ -0,0 +1,89 @@
+/*
+ * Copyright 2012 Sascha Hauer, Pengutronix
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/irq.h>
+#include <linux/irqdomain.h>
+#include <linux/of_irq.h>
+#include <linux/of_platform.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/time.h>
+#include <mach/common.h>
+#include <mach/mx27.h>
+
+static const struct of_dev_auxdata imx27_auxdata_lookup[] __initconst = {
+        OF_DEV_AUXDATA("fsl,imx27-uart", MX27_UART1_BASE_ADDR, "imx21-uart.0", NULL),
+        OF_DEV_AUXDATA("fsl,imx27-uart", MX27_UART2_BASE_ADDR, "imx21-uart.1", NULL),
+        OF_DEV_AUXDATA("fsl,imx27-uart", MX27_UART3_BASE_ADDR, "imx21-uart.2", NULL),
+        OF_DEV_AUXDATA("fsl,imx27-fec", MX27_FEC_BASE_ADDR, "imx27-fec.0", NULL),
+        OF_DEV_AUXDATA("fsl,imx27-i2c", MX27_I2C1_BASE_ADDR, "imx-i2c.0", NULL),
+        OF_DEV_AUXDATA("fsl,imx27-i2c", MX27_I2C2_BASE_ADDR, "imx-i2c.1", NULL),
+        OF_DEV_AUXDATA("fsl,imx27-cspi", MX27_CSPI1_BASE_ADDR, "imx27-cspi.0", NULL),
+        OF_DEV_AUXDATA("fsl,imx27-cspi", MX27_CSPI2_BASE_ADDR, "imx27-cspi.1", NULL),
+        OF_DEV_AUXDATA("fsl,imx27-cspi", MX27_CSPI3_BASE_ADDR, "imx27-cspi.2", NULL),
+        OF_DEV_AUXDATA("fsl,imx27-wdt", MX27_WDOG_BASE_ADDR, "imx2-wdt.0", NULL),
+        { /* sentinel */ }
+};
+
+static int __init imx27_avic_add_irq_domain(struct device_node *np,
+                                struct device_node *interrupt_parent)
+{
+        irq_domain_add_simple(np, 0);
+        return 0;
+}
+
+static int __init imx27_gpio_add_irq_domain(struct device_node *np,
+                                struct device_node *interrupt_parent)
+{
+        static int gpio_irq_base = MXC_GPIO_IRQ_START + ARCH_NR_GPIOS;
+
+        irq_domain_add_simple(np, gpio_irq_base);
+
+        return 0;
+}
+
+static const struct of_device_id imx27_irq_match[] __initconst = {
+        { .compatible = "fsl,imx27-avic", .data = imx27_avic_add_irq_domain, },
+        { .compatible = "fsl,imx27-gpio", .data = imx27_gpio_add_irq_domain, },
+        { /* sentinel */ }
+};
+
+static void __init imx27_dt_init(void)
+{
+        of_irq_init(imx27_irq_match);
+
+        of_platform_populate(NULL, of_default_bus_match_table,
+                             imx27_auxdata_lookup, NULL);
+}
+
+static void __init imx27_timer_init(void)
+{
+        mx27_clocks_init_dt();
+}
+
+static struct sys_timer imx27_timer = {
+        .init = imx27_timer_init,
+};
+
+static const char *imx27_dt_board_compat[] __initdata = {
+        "fsl,imx27",
+        NULL
+};
+
+DT_MACHINE_START(IMX27_DT, "Freescale i.MX27 (Device Tree Support)")
+        .map_io         = mx27_map_io,
+        .init_early     = imx27_init_early,
+        .init_irq       = mx27_init_irq,
+        .handle_irq     = imx27_handle_irq,
+        .timer          = &imx27_timer,
+        .init_machine   = imx27_dt_init,
+        .dt_compat      = imx27_dt_board_compat,
+        .restart        = mxc_restart,
+MACHINE_END
diff --git a/arch/arm/mach-imx/imx51-dt.c b/arch/arm/mach-imx/imx51-dt.c
index 1e03ef42faa..5cca573964f 100644
--- a/arch/arm/mach-imx/imx51-dt.c
+++ b/arch/arm/mach-imx/imx51-dt.c
@@ -104,6 +104,7 @@ static struct sys_timer imx51_timer = {
 
 static const char *imx51_dt_board_compat[] __initdata = {
         "fsl,imx51-babbage",
+        "fsl,imx51",
         NULL
 };
 
diff --git a/arch/arm/mach-imx/imx53-dt.c b/arch/arm/mach-imx/imx53-dt.c
index fd5be0f20fb..4172279b390 100644
--- a/arch/arm/mach-imx/imx53-dt.c
+++ b/arch/arm/mach-imx/imx53-dt.c
@@ -114,6 +114,7 @@ static const char *imx53_dt_board_compat[] __initdata = {
         "fsl,imx53-evk",
         "fsl,imx53-qsb",
         "fsl,imx53-smd",
+        "fsl,imx53",
         NULL
 };
 
diff --git a/arch/arm/mach-imx/lluart.c b/arch/arm/mach-imx/lluart.c
index d4ab6f29a76..0213f8dcee8 100644
--- a/arch/arm/mach-imx/lluart.c
+++ b/arch/arm/mach-imx/lluart.c
@@ -17,7 +17,7 @@
 #include <mach/hardware.h>
 
 static struct map_desc imx_lluart_desc = {
-#ifdef CONFIG_DEBUG_IMX6Q_UART
+#ifdef CONFIG_DEBUG_IMX6Q_UART4
         .virtual        = MX6Q_IO_P2V(MX6Q_UART4_BASE_ADDR),
         .pfn            = __phys_to_pfn(MX6Q_UART4_BASE_ADDR),
         .length         = MX6Q_UART4_SIZE,
diff --git a/arch/arm/mach-imx/localtimer.c b/arch/arm/mach-imx/localtimer.c
deleted file mode 100644
index 3a163515d41..00000000000
--- a/arch/arm/mach-imx/localtimer.c
+++ /dev/null
@@ -1,35 +0,0 @@
-/*
- * Copyright 2011 Freescale Semiconductor, Inc.
- * Copyright 2011 Linaro Ltd.
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-
-#include <linux/init.h>
-#include <linux/clockchips.h>
-#include <linux/of_address.h>
-#include <linux/of_irq.h>
-#include <asm/smp_twd.h>
-
-/*
- * Setup the local clock events for a CPU.
- */
-int __cpuinit local_timer_setup(struct clock_event_device *evt)
-{
-        struct device_node *np;
-
-        np = of_find_compatible_node(NULL, NULL, "arm,smp-twd");
-        if (!twd_base) {
-                twd_base = of_iomap(np, 0);
-                WARN_ON(!twd_base);
-        }
-        evt->irq = irq_of_parse_and_map(np, 0);
-        twd_timer_setup(evt);
-
-        return 0;
-}
diff --git a/arch/arm/mach-imx/mach-armadillo5x0.c b/arch/arm/mach-imx/mach-armadillo5x0.c
index e4f426a0989..27bc27e6ea4 100644
--- a/arch/arm/mach-imx/mach-armadillo5x0.c
+++ b/arch/arm/mach-imx/mach-armadillo5x0.c
@@ -51,7 +51,7 @@
 #include <mach/ulpi.h>
 
 #include "devices-imx31.h"
-#include "crmregs-imx31.h"
+#include "crmregs-imx3.h"
 
 static int armadillo5x0_pins[] = {
         /* UART1 */
diff --git a/arch/arm/mach-imx/mach-imx27_visstrim_m10.c b/arch/arm/mach-imx/mach-imx27_visstrim_m10.c
index c2766ae02b4..f7b074f496f 100644
--- a/arch/arm/mach-imx/mach-imx27_visstrim_m10.c
+++ b/arch/arm/mach-imx/mach-imx27_visstrim_m10.c
@@ -30,6 +30,10 @@
 #include <linux/input.h>
 #include <linux/gpio.h>
 #include <linux/delay.h>
+#include <linux/dma-mapping.h>
+#include <linux/leds.h>
+#include <linux/memblock.h>
+#include <media/soc_camera.h>
 #include <sound/tlv320aic32x4.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -39,6 +43,8 @@
 
 #include "devices-imx27.h"
 
+#define TVP5150_RSTN (GPIO_PORTC + 18)
+#define TVP5150_PWDN (GPIO_PORTC + 19)
 #define OTG_PHY_CS_GPIO (GPIO_PORTF + 17)
 #define SDHC1_IRQ IRQ_GPIOB(25)
 
@@ -100,8 +106,99 @@ static const int visstrim_m10_pins[] __initconst = {
         PE1_PF_USBOTG_STP,
         PB23_PF_USB_PWR,
         PB24_PF_USB_OC,
+        /* CSI */
+        PB10_PF_CSI_D0,
+        PB11_PF_CSI_D1,
+        PB12_PF_CSI_D2,
+        PB13_PF_CSI_D3,
+        PB14_PF_CSI_D4,
+        PB15_PF_CSI_MCLK,
+        PB16_PF_CSI_PIXCLK,
+        PB17_PF_CSI_D5,
+        PB18_PF_CSI_D6,
+        PB19_PF_CSI_D7,
+        PB20_PF_CSI_VSYNC,
+        PB21_PF_CSI_HSYNC,
 };
 
+/* Camera */
+static int visstrim_camera_power(struct device *dev, int on)
+{
+        gpio_set_value(TVP5150_PWDN, on);
+
+        return 0;
+};
+
+static int visstrim_camera_reset(struct device *dev)
+{
+        gpio_set_value(TVP5150_RSTN, 0);
+        ndelay(500);
+        gpio_set_value(TVP5150_RSTN, 1);
+
+        return 0;
+};
+
+static struct i2c_board_info visstrim_i2c_camera =  {
+        I2C_BOARD_INFO("tvp5150", 0x5d),
+};
+
+static struct soc_camera_link iclink_tvp5150 = {
+        .bus_id         = 0,
+        .board_info     = &visstrim_i2c_camera,
+        .i2c_adapter_id = 0,
+        .power = visstrim_camera_power,
+        .reset = visstrim_camera_reset,
+};
+
+static struct mx2_camera_platform_data visstrim_camera = {
+        .flags = MX2_CAMERA_CCIR | MX2_CAMERA_CCIR_INTERLACE |
+                        MX2_CAMERA_SWAP16 | MX2_CAMERA_PCLK_SAMPLE_RISING,
+        .clk = 100000,
+};
+
+static phys_addr_t mx2_camera_base __initdata;
+#define MX2_CAMERA_BUF_SIZE SZ_8M
+
+static void __init visstrim_camera_init(void)
+{
+        struct platform_device *pdev;
+        int dma;
+
+        /* Initialize tvp5150 gpios */
+        mxc_gpio_mode(TVP5150_RSTN | GPIO_GPIO | GPIO_OUT);
+        mxc_gpio_mode(TVP5150_PWDN | GPIO_GPIO | GPIO_OUT);
+        gpio_set_value(TVP5150_RSTN, 1);
+        gpio_set_value(TVP5150_PWDN, 0);
+        ndelay(1);
+
+        gpio_set_value(TVP5150_PWDN, 1);
+        ndelay(1);
+        gpio_set_value(TVP5150_RSTN, 0);
+        ndelay(500);
+        gpio_set_value(TVP5150_RSTN, 1);
+        ndelay(200000);
+
+        pdev = imx27_add_mx2_camera(&visstrim_camera);
+        if (IS_ERR(pdev))
+                return;
+
+        dma = dma_declare_coherent_memory(&pdev->dev,
+                                mx2_camera_base, mx2_camera_base,
+                                MX2_CAMERA_BUF_SIZE,
+                                DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE);
+        if (!(dma & DMA_MEMORY_MAP))
+                return;
+}
+
+static void __init visstrim_reserve(void)
+{
+        /* reserve 4 MiB for mx2-camera */
+        mx2_camera_base = memblock_alloc(MX2_CAMERA_BUF_SIZE,
+                        MX2_CAMERA_BUF_SIZE);
+        memblock_free(mx2_camera_base, MX2_CAMERA_BUF_SIZE);
+        memblock_remove(mx2_camera_base, MX2_CAMERA_BUF_SIZE);
+}
+
 /* GPIOs used as events for applications */
 static struct gpio_keys_button visstrim_gpio_keys[] = {
         {
@@ -136,6 +233,35 @@ static const struct gpio_keys_platform_data
         .nbuttons       = ARRAY_SIZE(visstrim_gpio_keys),
 };
 
+/* led */
+static const struct gpio_led visstrim_m10_leds[] __initconst = {
+        {
+                .name = "visstrim:ld0",
+                .default_trigger = "nand-disk",
+                .gpio = (GPIO_PORTC + 29),
+        },
+        {
+                .name = "visstrim:ld1",
+                .default_trigger = "nand-disk",
+                .gpio = (GPIO_PORTC + 24),
+        },
+        {
+                .name = "visstrim:ld2",
+                .default_trigger = "nand-disk",
+                .gpio = (GPIO_PORTC + 28),
+        },
+        {
+                .name = "visstrim:ld3",
+                .default_trigger = "nand-disk",
+                .gpio = (GPIO_PORTC + 25),
+        },
+};
+
+static const struct gpio_led_platform_data visstrim_m10_led_data __initconst = {
+        .leds = visstrim_m10_leds,
+        .num_leds = ARRAY_SIZE(visstrim_m10_leds),
+};
+
 /* Visstrim_SM10 has a microSD slot connected to sdhc1 */
 static int visstrim_m10_sdhc1_init(struct device *dev,
                 irq_handler_t detect_irq, void *data)
@@ -216,6 +342,9 @@ static struct i2c_board_info visstrim_m10_i2c_devices[] = {
         {
                 I2C_BOARD_INFO("tlv320aic32x4", 0x18),
                 .platform_data = &visstrim_m10_aic32x4_pdata,
+        },
+        {
+                 I2C_BOARD_INFO("m41t00", 0x68),
         }
 };
 
@@ -254,15 +383,21 @@ static void __init visstrim_m10_board_init(void)
         imx27_add_imx_ssi(0, &visstrim_m10_ssi_pdata);
         imx27_add_imx_uart0(&uart_pdata);
 
-        i2c_register_board_info(0, visstrim_m10_i2c_devices,
-                                ARRAY_SIZE(visstrim_m10_i2c_devices));
         imx27_add_imx_i2c(0, &visstrim_m10_i2c_data);
         imx27_add_imx_i2c(1, &visstrim_m10_i2c_data);
+        i2c_register_board_info(0, visstrim_m10_i2c_devices,
+                                ARRAY_SIZE(visstrim_m10_i2c_devices));
+
         imx27_add_mxc_mmc(0, &visstrim_m10_sdhc_pdata);
         imx27_add_mxc_ehci_otg(&visstrim_m10_usbotg_pdata);
         imx27_add_fec(NULL);
         imx_add_gpio_keys(&visstrim_gpio_keys_platform_data);
         platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
+        imx_add_platform_device("mx27vis", 0, NULL, 0, NULL, 0);
+        platform_device_register_resndata(NULL, "soc-camera-pdrv", 0, NULL, 0,
+                                      &iclink_tvp5150, sizeof(iclink_tvp5150));
+        gpio_led_register_device(0, &visstrim_m10_led_data);
+        visstrim_camera_init();
 }
 
 static void __init visstrim_m10_timer_init(void)
@@ -276,6 +411,7 @@ static struct sys_timer visstrim_m10_timer = {
 
 MACHINE_START(IMX27_VISSTRIM_M10, "Vista Silicon Visstrim_M10")
         .atag_offset = 0x100,
+        .reserve = visstrim_reserve,
         .map_io = mx27_map_io,
         .init_early = imx27_init_early,
         .init_irq = mx27_init_irq,
diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c
index 6075d4d62dd..7696dfa2bdb 100644
--- a/arch/arm/mach-imx/mach-imx6q.c
+++ b/arch/arm/mach-imx/mach-imx6q.c
@@ -21,6 +21,7 @@
 #include <linux/of_platform.h>
 #include <linux/phy.h>
 #include <linux/micrel_phy.h>
+#include <asm/smp_twd.h>
 #include <asm/hardware/cache-l2x0.h>
 #include <asm/hardware/gic.h>
 #include <asm/mach/arch.h>
@@ -120,6 +121,7 @@ static void __init imx6q_init_irq(void)
 static void __init imx6q_timer_init(void)
 {
         mx6q_clocks_init();
+        twd_local_timer_of_register();
 }
 
 static struct sys_timer imx6q_timer = {
@@ -129,6 +131,7 @@ static struct sys_timer imx6q_timer = {
 static const char *imx6q_dt_compat[] __initdata = {
         "fsl,imx6q-arm2",
         "fsl,imx6q-sabrelite",
+        "fsl,imx6q",
         NULL,
 };
 
diff --git a/arch/arm/mach-imx/mach-mx21ads.c b/arch/arm/mach-imx/mach-mx21ads.c
index 8d9f95514b1..e432d4acee1 100644
--- a/arch/arm/mach-imx/mach-mx21ads.c
+++ b/arch/arm/mach-imx/mach-mx21ads.c
@@ -37,8 +37,8 @@
 #define MX21ADS_REG_ADDR(offset)    (void __force __iomem *) \
                 (MX21ADS_MMIO_BASE_ADDR + (offset))
 
+#define MX21ADS_CS8900A_MMIO_SIZE   0x200000
 #define MX21ADS_CS8900A_IRQ         IRQ_GPIOE(11)
-#define MX21ADS_CS8900A_IOBASE_REG  MX21ADS_REG_ADDR(0x000000)
 #define MX21ADS_ST16C255_IOBASE_REG MX21ADS_REG_ADDR(0x200000)
 #define MX21ADS_VERSION_REG         MX21ADS_REG_ADDR(0x400000)
 #define MX21ADS_IO_REG              MX21ADS_REG_ADDR(0x800000)
@@ -159,6 +159,18 @@ static struct platform_device mx21ads_nor_mtd_device = {
         .resource = &mx21ads_flash_resource,
 };
 
+static const struct resource mx21ads_cs8900_resources[] __initconst = {
+        DEFINE_RES_MEM(MX21_CS1_BASE_ADDR, MX21ADS_CS8900A_MMIO_SIZE),
+        DEFINE_RES_IRQ(MX21ADS_CS8900A_IRQ),
+};
+
+static const struct platform_device_info mx21ads_cs8900_devinfo __initconst = {
+        .name = "cs89x0",
+        .id = 0,
+        .res = mx21ads_cs8900_resources,
+        .num_res = ARRAY_SIZE(mx21ads_cs8900_resources),
+};
+
 static const struct imxuart_platform_data uart_pdata_rts __initconst = {
         .flags = IMXUART_HAVE_RTSCTS,
 };
@@ -292,6 +304,8 @@ static void __init mx21ads_board_init(void)
         imx21_add_mxc_nand(&mx21ads_nand_board_info);
 
         platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
+        platform_device_register_full(
+                        (struct platform_device_info *)&mx21ads_cs8900_devinfo);
 }
 
 static void __init mx21ads_timer_init(void)
diff --git a/arch/arm/mach-imx/mach-mx27_3ds.c b/arch/arm/mach-imx/mach-mx27_3ds.c
index 18f35816706..c6d385c5225 100644
--- a/arch/arm/mach-imx/mach-mx27_3ds.c
+++ b/arch/arm/mach-imx/mach-mx27_3ds.c
@@ -31,6 +31,8 @@
 #include <linux/regulator/machine.h>
 #include <linux/spi/l4f00242t03.h>
 
+#include <media/soc_camera.h>
+
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
@@ -52,6 +54,8 @@
 #define SD1_CD                  IMX_GPIO_NR(2, 26)
 #define LCD_RESET               IMX_GPIO_NR(1, 3)
 #define LCD_ENABLE              IMX_GPIO_NR(1, 31)
+#define CSI_PWRDWN              IMX_GPIO_NR(4, 19)
+#define CSI_RESET               IMX_GPIO_NR(3, 6)
 
 static const int mx27pdk_pins[] __initconst = {
         /* UART1 */
@@ -141,6 +145,26 @@ static const int mx27pdk_pins[] __initconst = {
         PA30_PF_CONTRAST,
         LCD_ENABLE | GPIO_GPIO | GPIO_OUT,
         LCD_RESET | GPIO_GPIO | GPIO_OUT,
+        /* CSI */
+        PB10_PF_CSI_D0,
+        PB11_PF_CSI_D1,
+        PB12_PF_CSI_D2,
+        PB13_PF_CSI_D3,
+        PB14_PF_CSI_D4,
+        PB15_PF_CSI_MCLK,
+        PB16_PF_CSI_PIXCLK,
+        PB17_PF_CSI_D5,
+        PB18_PF_CSI_D6,
+        PB19_PF_CSI_D7,
+        PB20_PF_CSI_VSYNC,
+        PB21_PF_CSI_HSYNC,
+        CSI_PWRDWN | GPIO_GPIO | GPIO_OUT,
+        CSI_RESET | GPIO_GPIO | GPIO_OUT,
+};
+
+static struct gpio mx27_3ds_camera_gpios[] = {
+        { CSI_PWRDWN, GPIOF_OUT_INIT_HIGH, "camera-power" },
+        { CSI_RESET, GPIOF_OUT_INIT_HIGH, "camera-reset" },
 };
 
 static const struct imxuart_platform_data uart_pdata __initconst = {
@@ -242,6 +266,7 @@ static struct regulator_init_data gpo_init = {
 
 static struct regulator_consumer_supply vmmc1_consumers[] = {
         REGULATOR_SUPPLY("vcore", "spi0.0"),
+        REGULATOR_SUPPLY("cmos_2v8", "soc-camera-pdrv.0"),
 };
 
 static struct regulator_init_data vmmc1_init = {
@@ -270,6 +295,22 @@ static struct regulator_init_data vgen_init = {
         .consumer_supplies = vgen_consumers,
 };
 
+static struct regulator_consumer_supply vvib_consumers[] = {
+        REGULATOR_SUPPLY("cmos_vcore", "soc-camera-pdrv.0"),
+};
+
+static struct regulator_init_data vvib_init = {
+        .constraints = {
+                .min_uV = 1300000,
+                .max_uV = 1300000,
+                .apply_uV = 1,
+                .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
+                                  REGULATOR_CHANGE_STATUS,
+        },
+        .num_consumer_supplies = ARRAY_SIZE(vvib_consumers),
+        .consumer_supplies = vvib_consumers,
+};
+
 static struct mc13xxx_regulator_init_data mx27_3ds_regulators[] = {
         {
                 .id = MC13783_REG_VMMC1,
@@ -283,6 +324,9 @@ static struct mc13xxx_regulator_init_data mx27_3ds_regulators[] = {
         }, {
                 .id = MC13783_REG_GPO3, /* Turn on 3.3V */
                 .init_data = &gpo_init,
+        }, {
+                .id = MC13783_REG_VVIB,  /* Power OV2640 */
+                .init_data = &vvib_init,
         },
 };
 
@@ -311,6 +355,51 @@ static const struct spi_imx_master spi2_pdata __initconst = {
         .num_chipselect = ARRAY_SIZE(spi2_chipselect),
 };
 
+static int mx27_3ds_camera_power(struct device *dev, int on)
+{
+        /* enable or disable the camera */
+        pr_debug("%s: %s the camera\n", __func__, on ? "ENABLE" : "DISABLE");
+        gpio_set_value(CSI_PWRDWN, on ? 0 : 1);
+
+        if (!on)
+                goto out;
+
+        /* If enabled, give a reset impulse */
+        gpio_set_value(CSI_RESET, 0);
+        msleep(20);
+        gpio_set_value(CSI_RESET, 1);
+        msleep(100);
+
+out:
+        return 0;
+}
+
+static struct i2c_board_info mx27_3ds_i2c_camera = {
+        I2C_BOARD_INFO("ov2640", 0x30),
+};
+
+static struct regulator_bulk_data mx27_3ds_camera_regs[] = {
+        { .supply = "cmos_vcore" },
+        { .supply = "cmos_2v8" },
+};
+
+static struct soc_camera_link iclink_ov2640 = {
+        .bus_id         = 0,
+        .board_info     = &mx27_3ds_i2c_camera,
+        .i2c_adapter_id = 0,
+        .power          = mx27_3ds_camera_power,
+        .regulators     = mx27_3ds_camera_regs,
+        .num_regulators = ARRAY_SIZE(mx27_3ds_camera_regs),
+};
+
+static struct platform_device mx27_3ds_ov2640 = {
+        .name   = "soc-camera-pdrv",
+        .id     = 0,
+        .dev    = {
+                .platform_data = &iclink_ov2640,
+        },
+};
+
 static struct imx_fb_videomode mx27_3ds_modes[] = {
         {       /* 480x640 @ 60 Hz */
                 .mode = {
@@ -367,12 +456,21 @@ static struct spi_board_info mx27_3ds_spi_devs[] __initdata = {
         },
 };
 
+static struct platform_device *devices[] __initdata = {
+        &mx27_3ds_ov2640,
+};
+
+static const struct mx2_camera_platform_data mx27_3ds_cam_pdata __initconst = {
+        .clk = 26000000,
+};
+
 static const struct imxi2c_platform_data mx27_3ds_i2c0_data __initconst = {
         .bitrate = 100000,
 };
 
 static void __init mx27pdk_init(void)
 {
+        int ret;
         imx27_soc_init();
 
         mxc_gpio_setup_multiple_pins(mx27pdk_pins, ARRAY_SIZE(mx27pdk_pins),
@@ -404,7 +502,17 @@ static void __init mx27pdk_init(void)
         if (mxc_expio_init(MX27_CS5_BASE_ADDR, EXPIO_PARENT_INT))
                 pr_warn("Init of the debugboard failed, all devices on the debugboard are unusable.\n");
         imx27_add_imx_i2c(0, &mx27_3ds_i2c0_data);
+        platform_add_devices(devices, ARRAY_SIZE(devices));
         imx27_add_imx_fb(&mx27_3ds_fb_data);
+
+        ret = gpio_request_array(mx27_3ds_camera_gpios,
+                                 ARRAY_SIZE(mx27_3ds_camera_gpios));
+        if (ret) {
+                pr_err("Failed to request camera gpios");
+                iclink_ov2640.power = NULL;
+        }
+
+        imx27_add_mx2_camera(&mx27_3ds_cam_pdata);
 }
 
 static void __init mx27pdk_timer_init(void)
diff --git a/arch/arm/mach-imx/mach-mx31ads.c b/arch/arm/mach-imx/mach-mx31ads.c
index 4917aab0e25..4518e544822 100644
--- a/arch/arm/mach-imx/mach-mx31ads.c
+++ b/arch/arm/mach-imx/mach-mx31ads.c
@@ -28,7 +28,6 @@
 #include <asm/memory.h>
 #include <asm/mach/map.h>
 #include <mach/common.h>
-#include <mach/board-mx31ads.h>
 #include <mach/iomux-mx3.h>
 
 #ifdef CONFIG_MACH_MX31ADS_WM1133_EV1
@@ -39,6 +38,9 @@
 
 #include "devices-imx31.h"
 
+/* Base address of PBC controller */
+#define PBC_BASE_ADDRESS        MX31_CS4_BASE_ADDR_VIRT
+
 /* PBC Board interrupt status register */
 #define PBC_INTSTATUS           0x000016
 
@@ -62,6 +64,7 @@
 #define PBC_INTMASK_CLEAR_REG   (PBC_INTMASK_CLEAR + PBC_BASE_ADDRESS)
 #define EXPIO_PARENT_INT        IOMUX_TO_IRQ(MX31_PIN_GPIO1_4)
 
+#define MXC_EXP_IO_BASE         MXC_BOARD_IRQ_START
 #define MXC_IRQ_TO_EXPIO(irq)   ((irq) - MXC_EXP_IO_BASE)
 
 #define EXPIO_INT_XUART_INTA    (MXC_EXP_IO_BASE + 10)
@@ -69,6 +72,10 @@
 
 #define MXC_MAX_EXP_IO_LINES    16
 
+/* CS8900 */
+#define EXPIO_INT_ENET_INT      (MXC_EXP_IO_BASE + 8)
+#define CS4_CS8900_MMIO_START   0x20000
+
 /*
  * The serial port definition structure.
  */
@@ -101,11 +108,29 @@ static struct platform_device serial_device = {
         },
 };
 
+static const struct resource mx31ads_cs8900_resources[] __initconst = {
+        DEFINE_RES_MEM(MX31_CS4_BASE_ADDR + CS4_CS8900_MMIO_START, SZ_64K),
+        DEFINE_RES_IRQ(EXPIO_INT_ENET_INT),
+};
+
+static const struct platform_device_info mx31ads_cs8900_devinfo __initconst = {
+        .name = "cs89x0",
+        .id = 0,
+        .res = mx31ads_cs8900_resources,
+        .num_res = ARRAY_SIZE(mx31ads_cs8900_resources),
+};
+
 static int __init mxc_init_extuart(void)
 {
         return platform_device_register(&serial_device);
 }
 
+static void __init mxc_init_ext_ethernet(void)
+{
+        platform_device_register_full(
+                (struct platform_device_info *)&mx31ads_cs8900_devinfo);
+}
+
 static const struct imxuart_platform_data uart_pdata __initconst = {
         .flags = IMXUART_HAVE_RTSCTS,
 };
@@ -492,12 +517,15 @@ static void __init mxc_init_audio(void)
         mxc_iomux_setup_multiple_pins(ssi_pins, ARRAY_SIZE(ssi_pins), "ssi");
 }
 
-/* static mappings */
+/*
+ * Static mappings, starting from the CS4 start address up to the start address
+ * of the CS8900.
+ */
 static struct map_desc mx31ads_io_desc[] __initdata = {
         {
                 .virtual        = MX31_CS4_BASE_ADDR_VIRT,
                 .pfn            = __phys_to_pfn(MX31_CS4_BASE_ADDR),
-                .length         = MX31_CS4_SIZE / 2,
+                .length         = CS4_CS8900_MMIO_START,
                 .type           = MT_DEVICE
         },
 };
@@ -522,6 +550,7 @@ static void __init mx31ads_init(void)
         mxc_init_imx_uart();
         mxc_init_i2c();
         mxc_init_audio();
+        mxc_init_ext_ethernet();
 }
 
 static void __init mx31ads_timer_init(void)
diff --git a/arch/arm/mach-imx/mach-mx31moboard.c b/arch/arm/mach-imx/mach-mx31moboard.c
index f225262b5c3..f17a15f2831 100644
--- a/arch/arm/mach-imx/mach-mx31moboard.c
+++ b/arch/arm/mach-imx/mach-mx31moboard.c
@@ -507,7 +507,7 @@ static void mx31moboard_poweroff(void)
         struct clk *clk = clk_get_sys("imx2-wdt.0", NULL);
 
         if (!IS_ERR(clk))
-                clk_enable(clk);
+                clk_prepare_enable(clk);
 
         mxc_iomux_mode(MX31_PIN_WATCHDOG_RST__WATCHDOG_RST);
 
@@ -530,6 +530,8 @@ static void __init mx31moboard_init(void)
         platform_add_devices(devices, ARRAY_SIZE(devices));
         gpio_led_register_device(-1, &mx31moboard_led_pdata);
 
+        imx31_add_imx2_wdt(NULL);
+
         imx31_add_imx_uart0(&uart0_pdata);
         imx31_add_imx_uart4(&uart4_pdata);
 
@@ -590,7 +592,7 @@ static void __init mx31moboard_reserve(void)
 }
 
 MACHINE_START(MX31MOBOARD, "EPFL Mobots mx31moboard")
-        /* Maintainer: Valentin Longchamp, EPFL Mobots group */
+        /* Maintainer: Philippe Retornaz, EPFL Mobots group */
         .atag_offset = 0x100,
         .reserve = mx31moboard_reserve,
         .map_io = mx31_map_io,
diff --git a/arch/arm/mach-imx/mach-mx35_3ds.c b/arch/arm/mach-imx/mach-mx35_3ds.c
index 0af6c9c5b3f..e14291d89e4 100644
--- a/arch/arm/mach-imx/mach-mx35_3ds.c
+++ b/arch/arm/mach-imx/mach-mx35_3ds.c
@@ -4,6 +4,11 @@
  *
  * Author: Fabio Estevam <fabio.estevam@freescale.com>
  *
+ * Copyright (C) 2011 Meprolight, Ltd.
+ * Alex Gershgorin <alexg@meprolight.com>
+ *
+ * Modified from i.MX31 3-Stack Development System
+ *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
  * the Free Software Foundation; either version 2 of the License, or
@@ -34,15 +39,102 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
 #include <asm/mach/map.h>
+#include <asm/memblock.h>
 
 #include <mach/hardware.h>
 #include <mach/common.h>
 #include <mach/iomux-mx35.h>
 #include <mach/irqs.h>
 #include <mach/3ds_debugboard.h>
+#include <video/platform_lcd.h>
+
+#include <media/soc_camera.h>
 
 #include "devices-imx35.h"
 
+#define GPIO_MC9S08DZ60_GPS_ENABLE 0
+#define GPIO_MC9S08DZ60_HDD_ENABLE 4
+#define GPIO_MC9S08DZ60_WIFI_ENABLE 5
+#define GPIO_MC9S08DZ60_LCD_ENABLE 6
+#define GPIO_MC9S08DZ60_SPEAKER_ENABLE 8
+
+static const struct fb_videomode fb_modedb[] = {
+        {
+                 /* 800x480 @ 55 Hz */
+                .name = "Ceramate-CLAA070VC01",
+                .refresh = 55,
+                .xres = 800,
+                .yres = 480,
+                .pixclock = 40000,
+                .left_margin = 40,
+                .right_margin = 40,
+                .upper_margin = 5,
+                .lower_margin = 5,
+                .hsync_len = 20,
+                .vsync_len = 10,
+                .sync = FB_SYNC_OE_ACT_HIGH,
+                .vmode = FB_VMODE_NONINTERLACED,
+                .flag = 0,
+         },
+};
+
+static const struct ipu_platform_data mx3_ipu_data __initconst = {
+        .irq_base = MXC_IPU_IRQ_START,
+};
+
+static struct mx3fb_platform_data mx3fb_pdata __initdata = {
+        .name = "Ceramate-CLAA070VC01",
+        .mode = fb_modedb,
+        .num_modes = ARRAY_SIZE(fb_modedb),
+};
+
+static struct i2c_board_info __initdata i2c_devices_3ds[] = {
+        {
+                I2C_BOARD_INFO("mc9s08dz60", 0x69),
+        },
+};
+
+static int lcd_power_gpio = -ENXIO;
+
+static int mc9s08dz60_gpiochip_match(struct gpio_chip *chip,
+                                                     void *data)
+{
+        return !strcmp(chip->label, data);
+}
+
+static void mx35_3ds_lcd_set_power(
+                                struct plat_lcd_data *pd, unsigned int power)
+{
+        struct gpio_chip *chip;
+
+        if (!gpio_is_valid(lcd_power_gpio)) {
+                chip = gpiochip_find(
+                                "mc9s08dz60", mc9s08dz60_gpiochip_match);
+                if (chip) {
+                        lcd_power_gpio =
+                                chip->base + GPIO_MC9S08DZ60_LCD_ENABLE;
+                        if (gpio_request(lcd_power_gpio, "lcd_power") < 0) {
+                                pr_err("error: gpio already requested!\n");
+                                lcd_power_gpio = -ENXIO;
+                        }
+                } else {
+                        pr_err("error: didn't find mc9s08dz60 gpio chip\n");
+                }
+        }
+
+        if (gpio_is_valid(lcd_power_gpio))
+                gpio_set_value_cansleep(lcd_power_gpio, power);
+}
+
+static struct plat_lcd_data mx35_3ds_lcd_data = {
+        .set_power = mx35_3ds_lcd_set_power,
+};
+
+static struct platform_device mx35_3ds_lcd = {
+        .name = "platform-lcd",
+        .dev.platform_data = &mx35_3ds_lcd_data,
+};
+
 #define EXPIO_PARENT_INT        gpio_to_irq(IMX_GPIO_NR(1, 1))
 
 static const struct imxuart_platform_data uart_pdata __initconst = {
@@ -120,6 +212,109 @@ static iomux_v3_cfg_t mx35pdk_pads[] = {
         /* I2C1 */
         MX35_PAD_I2C1_CLK__I2C1_SCL,
         MX35_PAD_I2C1_DAT__I2C1_SDA,
+        /* Display */
+        MX35_PAD_LD0__IPU_DISPB_DAT_0,
+        MX35_PAD_LD1__IPU_DISPB_DAT_1,
+        MX35_PAD_LD2__IPU_DISPB_DAT_2,
+        MX35_PAD_LD3__IPU_DISPB_DAT_3,
+        MX35_PAD_LD4__IPU_DISPB_DAT_4,
+        MX35_PAD_LD5__IPU_DISPB_DAT_5,
+        MX35_PAD_LD6__IPU_DISPB_DAT_6,
+        MX35_PAD_LD7__IPU_DISPB_DAT_7,
+        MX35_PAD_LD8__IPU_DISPB_DAT_8,
+        MX35_PAD_LD9__IPU_DISPB_DAT_9,
+        MX35_PAD_LD10__IPU_DISPB_DAT_10,
+        MX35_PAD_LD11__IPU_DISPB_DAT_11,
+        MX35_PAD_LD12__IPU_DISPB_DAT_12,
+        MX35_PAD_LD13__IPU_DISPB_DAT_13,
+        MX35_PAD_LD14__IPU_DISPB_DAT_14,
+        MX35_PAD_LD15__IPU_DISPB_DAT_15,
+        MX35_PAD_LD16__IPU_DISPB_DAT_16,
+        MX35_PAD_LD17__IPU_DISPB_DAT_17,
+        MX35_PAD_D3_HSYNC__IPU_DISPB_D3_HSYNC,
+        MX35_PAD_D3_FPSHIFT__IPU_DISPB_D3_CLK,
+        MX35_PAD_D3_DRDY__IPU_DISPB_D3_DRDY,
+        MX35_PAD_CONTRAST__IPU_DISPB_CONTR,
+        MX35_PAD_D3_VSYNC__IPU_DISPB_D3_VSYNC,
+        MX35_PAD_D3_REV__IPU_DISPB_D3_REV,
+        MX35_PAD_D3_CLS__IPU_DISPB_D3_CLS,
+        /* CSI */
+        MX35_PAD_TX1__IPU_CSI_D_6,
+        MX35_PAD_TX0__IPU_CSI_D_7,
+        MX35_PAD_CSI_D8__IPU_CSI_D_8,
+        MX35_PAD_CSI_D9__IPU_CSI_D_9,
+        MX35_PAD_CSI_D10__IPU_CSI_D_10,
+        MX35_PAD_CSI_D11__IPU_CSI_D_11,
+        MX35_PAD_CSI_D12__IPU_CSI_D_12,
+        MX35_PAD_CSI_D13__IPU_CSI_D_13,
+        MX35_PAD_CSI_D14__IPU_CSI_D_14,
+        MX35_PAD_CSI_D15__IPU_CSI_D_15,
+        MX35_PAD_CSI_HSYNC__IPU_CSI_HSYNC,
+        MX35_PAD_CSI_MCLK__IPU_CSI_MCLK,
+        MX35_PAD_CSI_PIXCLK__IPU_CSI_PIXCLK,
+        MX35_PAD_CSI_VSYNC__IPU_CSI_VSYNC,
+};
+
+/*
+ * Camera support
+*/
+static phys_addr_t mx3_camera_base __initdata;
+#define MX35_3DS_CAMERA_BUF_SIZE SZ_8M
+
+static const struct mx3_camera_pdata mx35_3ds_camera_pdata __initconst = {
+        .flags = MX3_CAMERA_DATAWIDTH_8,
+        .mclk_10khz = 2000,
+};
+
+static int __init imx35_3ds_init_camera(void)
+{
+        int dma, ret = -ENOMEM;
+        struct platform_device *pdev =
+                imx35_alloc_mx3_camera(&mx35_3ds_camera_pdata);
+
+        if (IS_ERR(pdev))
+                return PTR_ERR(pdev);
+
+        if (!mx3_camera_base)
+                goto err;
+
+        dma = dma_declare_coherent_memory(&pdev->dev,
+                                        mx3_camera_base, mx3_camera_base,
+                                        MX35_3DS_CAMERA_BUF_SIZE,
+                                        DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE);
+
+        if (!(dma & DMA_MEMORY_MAP))
+                goto err;
+
+        ret = platform_device_add(pdev);
+        if (ret)
+err:
+                platform_device_put(pdev);
+
+        return ret;
+}
+
+static const struct ipu_platform_data mx35_3ds_ipu_data __initconst = {
+        .irq_base = MXC_IPU_IRQ_START,
+};
+
+static struct i2c_board_info mx35_3ds_i2c_camera = {
+        I2C_BOARD_INFO("ov2640", 0x30),
+};
+
+static struct soc_camera_link iclink_ov2640 = {
+        .bus_id         = 0,
+        .board_info     = &mx35_3ds_i2c_camera,
+        .i2c_adapter_id = 0,
+        .power          = NULL,
+};
+
+static struct platform_device mx35_3ds_ov2640 = {
+        .name   = "soc-camera-pdrv",
+        .id     = 0,
+        .dev    = {
+                .platform_data = &iclink_ov2640,
+        },
 };
 
 static int mx35_3ds_otg_init(struct platform_device *pdev)
@@ -179,6 +374,8 @@ static const struct imxi2c_platform_data mx35_3ds_i2c0_data __initconst = {
  */
 static void __init mx35_3ds_init(void)
 {
+        struct platform_device *imx35_fb_pdev;
+
         imx35_soc_init();
 
         mxc_iomux_v3_setup_multiple_pads(mx35pdk_pads, ARRAY_SIZE(mx35pdk_pads));
@@ -204,6 +401,17 @@ static void __init mx35_3ds_init(void)
                 pr_warn("Init of the debugboard failed, all "
                                 "devices on the debugboard are unusable.\n");
         imx35_add_imx_i2c0(&mx35_3ds_i2c0_data);
+
+        i2c_register_board_info(
+                0, i2c_devices_3ds, ARRAY_SIZE(i2c_devices_3ds));
+
+        imx35_add_ipu_core(&mx35_3ds_ipu_data);
+        platform_device_register(&mx35_3ds_ov2640);
+        imx35_3ds_init_camera();
+
+        imx35_fb_pdev = imx35_add_mx3_sdc_fb(&mx3fb_pdata);
+        mx35_3ds_lcd.dev.parent = &imx35_fb_pdev->dev;
+        platform_device_register(&mx35_3ds_lcd);
 }
 
 static void __init mx35pdk_timer_init(void)
@@ -215,6 +423,13 @@ struct sys_timer mx35pdk_timer = {
         .init   = mx35pdk_timer_init,
 };
 
+static void __init mx35_3ds_reserve(void)
+{
+        /* reserve MX35_3DS_CAMERA_BUF_SIZE bytes for mx3-camera */
+        mx3_camera_base = arm_memblock_steal(MX35_3DS_CAMERA_BUF_SIZE,
+                                         MX35_3DS_CAMERA_BUF_SIZE);
+}
+
 MACHINE_START(MX35_3DS, "Freescale MX35PDK")
         /* Maintainer: Freescale Semiconductor, Inc */
         .atag_offset = 0x100,
@@ -224,5 +439,6 @@ MACHINE_START(MX35_3DS, "Freescale MX35PDK")
         .handle_irq = imx35_handle_irq,
         .timer = &mx35pdk_timer,
         .init_machine = mx35_3ds_init,
+        .reserve = mx35_3ds_reserve,
         .restart        = mxc_restart,
 MACHINE_END
diff --git a/arch/arm/mach-imx/mach-pca100.c b/arch/arm/mach-imx/mach-pca100.c
index d3b9c6b5edd..541152e450c 100644
--- a/arch/arm/mach-imx/mach-pca100.c
+++ b/arch/arm/mach-imx/mach-pca100.c
@@ -36,7 +36,6 @@
 #include <mach/hardware.h>
 #include <mach/iomux-mx27.h>
 #include <asm/mach/time.h>
-#include <mach/audmux.h>
 #include <mach/irqs.h>
 #include <mach/ulpi.h>
 
@@ -359,18 +358,6 @@ static void __init pca100_init(void)
 
         imx27_soc_init();
 
-        /* SSI unit */
-        mxc_audmux_v1_configure_port(MX27_AUDMUX_HPCR1_SSI0,
-                                  MXC_AUDMUX_V1_PCR_SYN | /* 4wire mode */
-                                  MXC_AUDMUX_V1_PCR_TFCSEL(3) |
-                                  MXC_AUDMUX_V1_PCR_TCLKDIR | /* clock is output */
-                                  MXC_AUDMUX_V1_PCR_RXDSEL(3));
-        mxc_audmux_v1_configure_port(3,
-                                  MXC_AUDMUX_V1_PCR_SYN | /* 4wire mode */
-                                  MXC_AUDMUX_V1_PCR_TFCSEL(0) |
-                                  MXC_AUDMUX_V1_PCR_TFSDIR |
-                                  MXC_AUDMUX_V1_PCR_RXDSEL(0));
-
         ret = mxc_gpio_setup_multiple_pins(pca100_pins,
                         ARRAY_SIZE(pca100_pins), "PCA100");
         if (ret)
diff --git a/arch/arm/mach-imx/mach-pcm038.c b/arch/arm/mach-imx/mach-pcm038.c
index 16f126da9f8..2f3debe2a11 100644
--- a/arch/arm/mach-imx/mach-pcm038.c
+++ b/arch/arm/mach-imx/mach-pcm038.c
@@ -233,7 +233,7 @@ static struct regulator_init_data sdhc1_data = {
 
 static struct regulator_consumer_supply cam_consumers[] = {
         {
-                .dev    = NULL,
+                .dev_name = NULL,
                 .supply = "imx_cam_vcc",
         },
 };
diff --git a/arch/arm/mach-imx/mach-pcm043.c b/arch/arm/mach-imx/mach-pcm043.c
index 06dc106519a..237474fcca2 100644
--- a/arch/arm/mach-imx/mach-pcm043.c
+++ b/arch/arm/mach-imx/mach-pcm043.c
@@ -37,7 +37,6 @@
 #include <mach/common.h>
 #include <mach/iomux-mx35.h>
 #include <mach/ulpi.h>
-#include <mach/audmux.h>
 
 #include "devices-imx35.h"
 
@@ -362,18 +361,6 @@ static void __init pcm043_init(void)
 
         mxc_iomux_v3_setup_multiple_pads(pcm043_pads, ARRAY_SIZE(pcm043_pads));
 
-        mxc_audmux_v2_configure_port(3,
-                        MXC_AUDMUX_V2_PTCR_SYN | /* 4wire mode */
-                        MXC_AUDMUX_V2_PTCR_TFSEL(0) |
-                        MXC_AUDMUX_V2_PTCR_TFSDIR,
-                        MXC_AUDMUX_V2_PDCR_RXDSEL(0));
-
-        mxc_audmux_v2_configure_port(0,
-                        MXC_AUDMUX_V2_PTCR_SYN | /* 4wire mode */
-                        MXC_AUDMUX_V2_PTCR_TCSEL(3) |
-                        MXC_AUDMUX_V2_PTCR_TCLKDIR, /* clock is output */
-                        MXC_AUDMUX_V2_PDCR_RXDSEL(3));
-
         imx35_add_fec(NULL);
         platform_add_devices(devices, ARRAY_SIZE(devices));
         imx35_add_imx2_wdt(NULL);
diff --git a/arch/arm/mach-imx/mm-imx21.c b/arch/arm/mach-imx/mm-imx21.c
index 3f05dfebacc..14d540edfd1 100644
--- a/arch/arm/mach-imx/mm-imx21.c
+++ b/arch/arm/mach-imx/mm-imx21.c
@@ -75,6 +75,10 @@ void __init mx21_init_irq(void)
         mxc_init_irq(MX21_IO_ADDRESS(MX21_AVIC_BASE_ADDR));
 }
 
+static const struct resource imx21_audmux_res[] __initconst = {
+        DEFINE_RES_MEM(MX21_AUDMUX_BASE_ADDR, SZ_4K),
+};
+
 void __init imx21_soc_init(void)
 {
         mxc_register_gpio("imx21-gpio", 0, MX21_GPIO1_BASE_ADDR, SZ_256, MX21_INT_GPIO, 0);
@@ -85,4 +89,6 @@ void __init imx21_soc_init(void)
         mxc_register_gpio("imx21-gpio", 5, MX21_GPIO6_BASE_ADDR, SZ_256, MX21_INT_GPIO, 0);
 
         imx_add_imx_dma();
+        platform_device_register_simple("imx21-audmux", 0, imx21_audmux_res,
+                                        ARRAY_SIZE(imx21_audmux_res));
 }
diff --git a/arch/arm/mach-imx/mm-imx25.c b/arch/arm/mach-imx/mm-imx25.c
index cc4d152bd9b..153b457acdc 100644
--- a/arch/arm/mach-imx/mm-imx25.c
+++ b/arch/arm/mach-imx/mm-imx25.c
@@ -83,6 +83,10 @@ static struct sdma_platform_data imx25_sdma_pdata __initdata = {
         .script_addrs = &imx25_sdma_script,
 };
 
+static const struct resource imx25_audmux_res[] __initconst = {
+        DEFINE_RES_MEM(MX25_AUDMUX_BASE_ADDR, SZ_16K),
+};
+
 void __init imx25_soc_init(void)
 {
         /* i.mx25 has the i.mx31 type gpio */
@@ -93,4 +97,7 @@ void __init imx25_soc_init(void)
 
         /* i.mx25 has the i.mx35 type sdma */
         imx_add_imx_sdma("imx35-sdma", MX25_SDMA_BASE_ADDR, MX25_INT_SDMA, &imx25_sdma_pdata);
+        /* i.mx25 has the i.mx31 type audmux */
+        platform_device_register_simple("imx31-audmux", 0, imx25_audmux_res,
+                                        ARRAY_SIZE(imx25_audmux_res));
 }
diff --git a/arch/arm/mach-imx/mm-imx27.c b/arch/arm/mach-imx/mm-imx27.c
index 96dd1f5ea7b..8cb3f5e3e56 100644
--- a/arch/arm/mach-imx/mm-imx27.c
+++ b/arch/arm/mach-imx/mm-imx27.c
@@ -75,6 +75,10 @@ void __init mx27_init_irq(void)
         mxc_init_irq(MX27_IO_ADDRESS(MX27_AVIC_BASE_ADDR));
 }
 
+static const struct resource imx27_audmux_res[] __initconst = {
+        DEFINE_RES_MEM(MX27_AUDMUX_BASE_ADDR, SZ_4K),
+};
+
 void __init imx27_soc_init(void)
 {
         /* i.mx27 has the i.mx21 type gpio */
@@ -86,4 +90,7 @@ void __init imx27_soc_init(void)
         mxc_register_gpio("imx21-gpio", 5, MX27_GPIO6_BASE_ADDR, SZ_256, MX27_INT_GPIO, 0);
 
         imx_add_imx_dma();
+        /* imx27 has the imx21 type audmux */
+        platform_device_register_simple("imx21-audmux", 0, imx27_audmux_res,
+                                        ARRAY_SIZE(imx27_audmux_res));
 }
diff --git a/arch/arm/mach-imx/mm-imx3.c b/arch/arm/mach-imx/mm-imx3.c
index 31807d2a8b7..f8ca96c354f 100644
--- a/arch/arm/mach-imx/mm-imx3.c
+++ b/arch/arm/mach-imx/mm-imx3.c
@@ -34,31 +34,31 @@ static void imx3_idle(void)
 {
         unsigned long reg = 0;
 
-        if (!need_resched())
-                __asm__ __volatile__(
-                        /* disable I and D cache */
-                        "mrc p15, 0, %0, c1, c0, 0\n"
-                        "bic %0, %0, #0x00001000\n"
-                        "bic %0, %0, #0x00000004\n"
-                        "mcr p15, 0, %0, c1, c0, 0\n"
-                        /* invalidate I cache */
-                        "mov %0, #0\n"
-                        "mcr p15, 0, %0, c7, c5, 0\n"
-                        /* clear and invalidate D cache */
-                        "mov %0, #0\n"
-                        "mcr p15, 0, %0, c7, c14, 0\n"
-                        /* WFI */
-                        "mov %0, #0\n"
-                        "mcr p15, 0, %0, c7, c0, 4\n"
-                        "nop\n" "nop\n" "nop\n" "nop\n"
-                        "nop\n" "nop\n" "nop\n"
-                        /* enable I and D cache */
-                        "mrc p15, 0, %0, c1, c0, 0\n"
-                        "orr %0, %0, #0x00001000\n"
-                        "orr %0, %0, #0x00000004\n"
-                        "mcr p15, 0, %0, c1, c0, 0\n"
-                        : "=r" (reg));
-        local_irq_enable();
+        mx3_cpu_lp_set(MX3_WAIT);
+
+        __asm__ __volatile__(
+                /* disable I and D cache */
+                "mrc p15, 0, %0, c1, c0, 0\n"
+                "bic %0, %0, #0x00001000\n"
+                "bic %0, %0, #0x00000004\n"
+                "mcr p15, 0, %0, c1, c0, 0\n"
+                /* invalidate I cache */
+                "mov %0, #0\n"
+                "mcr p15, 0, %0, c7, c5, 0\n"
+                /* clear and invalidate D cache */
+                "mov %0, #0\n"
+                "mcr p15, 0, %0, c7, c14, 0\n"
+                /* WFI */
+                "mov %0, #0\n"
+                "mcr p15, 0, %0, c7, c0, 4\n"
+                "nop\n" "nop\n" "nop\n" "nop\n"
+                "nop\n" "nop\n" "nop\n"
+                /* enable I and D cache */
+                "mrc p15, 0, %0, c1, c0, 0\n"
+                "orr %0, %0, #0x00001000\n"
+                "orr %0, %0, #0x00000004\n"
+                "mcr p15, 0, %0, c1, c0, 0\n"
+                : "=r" (reg));
 }
 
 static void __iomem *imx3_ioremap(unsigned long phys_addr, size_t size,
@@ -78,7 +78,7 @@ static void __iomem *imx3_ioremap(unsigned long phys_addr, size_t size,
         return __arm_ioremap(phys_addr, size, mtype);
 }
 
-void imx3_init_l2x0(void)
+void __init imx3_init_l2x0(void)
 {
         void __iomem *l2x0_base;
         void __iomem *clkctl_base;
@@ -134,8 +134,8 @@ void __init imx31_init_early(void)
 {
         mxc_set_cpu_type(MXC_CPU_MX31);
         mxc_arch_reset_init(MX31_IO_ADDRESS(MX31_WDOG_BASE_ADDR));
-        pm_idle = imx3_idle;
         imx_ioremap = imx3_ioremap;
+        arm_pm_idle = imx3_idle;
 }
 
 void __init mx31_init_irq(void)
@@ -158,6 +158,10 @@ static struct sdma_platform_data imx31_sdma_pdata __initdata = {
         .script_addrs = &imx31_to2_sdma_script,
 };
 
+static const struct resource imx31_audmux_res[] __initconst = {
+        DEFINE_RES_MEM(MX31_AUDMUX_BASE_ADDR, SZ_16K),
+};
+
 void __init imx31_soc_init(void)
 {
         int to_version = mx31_revision() >> 4;
@@ -175,6 +179,12 @@ void __init imx31_soc_init(void)
         }
 
         imx_add_imx_sdma("imx31-sdma", MX31_SDMA_BASE_ADDR, MX31_INT_SDMA, &imx31_sdma_pdata);
+
+        imx_set_aips(MX31_IO_ADDRESS(MX31_AIPS1_BASE_ADDR));
+        imx_set_aips(MX31_IO_ADDRESS(MX31_AIPS2_BASE_ADDR));
+
+        platform_device_register_simple("imx31-audmux", 0, imx31_audmux_res,
+                                        ARRAY_SIZE(imx31_audmux_res));
 }
 #endif /* ifdef CONFIG_SOC_IMX31 */
 
@@ -197,7 +207,7 @@ void __init imx35_init_early(void)
         mxc_set_cpu_type(MXC_CPU_MX35);
         mxc_iomux_v3_init(MX35_IO_ADDRESS(MX35_IOMUXC_BASE_ADDR));
         mxc_arch_reset_init(MX35_IO_ADDRESS(MX35_WDOG_BASE_ADDR));
-        pm_idle = imx3_idle;
+        arm_pm_idle = imx3_idle;
         imx_ioremap = imx3_ioremap;
 }
 
@@ -241,6 +251,10 @@ static struct sdma_platform_data imx35_sdma_pdata __initdata = {
         .script_addrs = &imx35_to2_sdma_script,
 };
 
+static const struct resource imx35_audmux_res[] __initconst = {
+        DEFINE_RES_MEM(MX35_AUDMUX_BASE_ADDR, SZ_16K),
+};
+
 void __init imx35_soc_init(void)
 {
         int to_version = mx35_revision() >> 4;
@@ -259,5 +273,13 @@ void __init imx35_soc_init(void)
         }
 
         imx_add_imx_sdma("imx35-sdma", MX35_SDMA_BASE_ADDR, MX35_INT_SDMA, &imx35_sdma_pdata);
+
+        /* Setup AIPS registers */
+        imx_set_aips(MX35_IO_ADDRESS(MX35_AIPS1_BASE_ADDR));
+        imx_set_aips(MX35_IO_ADDRESS(MX35_AIPS2_BASE_ADDR));
+
+        /* i.mx35 has the i.mx31 type audmux */
+        platform_device_register_simple("imx31-audmux", 0, imx35_audmux_res,
+                                        ARRAY_SIZE(imx35_audmux_res));
 }
 #endif /* ifdef CONFIG_SOC_IMX35 */
diff --git a/arch/arm/mach-imx/mm-imx5.c b/arch/arm/mach-imx/mm-imx5.c
index bc17dfea381..51af9fa5694 100644
--- a/arch/arm/mach-imx/mm-imx5.c
+++ b/arch/arm/mach-imx/mm-imx5.c
@@ -26,23 +26,17 @@ static struct clk *gpc_dvfs_clk;
 
 static void imx5_idle(void)
 {
-        if (!need_resched()) {
-                /* gpc clock is needed for SRPG */
-                if (gpc_dvfs_clk == NULL) {
-                        gpc_dvfs_clk = clk_get(NULL, "gpc_dvfs");
-                        if (IS_ERR(gpc_dvfs_clk))
-                                goto err0;
-                }
-                clk_enable(gpc_dvfs_clk);
-                mx5_cpu_lp_set(WAIT_UNCLOCKED_POWER_OFF);
-                if (tzic_enable_wake())
-                        goto err1;
-                cpu_do_idle();
-err1:
-                clk_disable(gpc_dvfs_clk);
+        /* gpc clock is needed for SRPG */
+        if (gpc_dvfs_clk == NULL) {
+                gpc_dvfs_clk = clk_get(NULL, "gpc_dvfs");
+                if (IS_ERR(gpc_dvfs_clk))
+                        return;
         }
-err0:
-        local_irq_enable();
+        clk_enable(gpc_dvfs_clk);
+        mx5_cpu_lp_set(WAIT_UNCLOCKED_POWER_OFF);
+        if (tzic_enable_wake() != 0)
+                cpu_do_idle();
+        clk_disable(gpc_dvfs_clk);
 }
 
 /*
@@ -108,7 +102,7 @@ void __init imx51_init_early(void)
         mxc_set_cpu_type(MXC_CPU_MX51);
         mxc_iomux_v3_init(MX51_IO_ADDRESS(MX51_IOMUXC_BASE_ADDR));
         mxc_arch_reset_init(MX51_IO_ADDRESS(MX51_WDOG1_BASE_ADDR));
-        pm_idle = imx5_idle;
+        arm_pm_idle = imx5_idle;
 }
 
 void __init imx53_init_early(void)
@@ -170,6 +164,18 @@ static struct sdma_platform_data imx53_sdma_pdata __initdata = {
         .script_addrs = &imx53_sdma_script,
 };
 
+static const struct resource imx50_audmux_res[] __initconst = {
+        DEFINE_RES_MEM(MX50_AUDMUX_BASE_ADDR, SZ_16K),
+};
+
+static const struct resource imx51_audmux_res[] __initconst = {
+        DEFINE_RES_MEM(MX51_AUDMUX_BASE_ADDR, SZ_16K),
+};
+
+static const struct resource imx53_audmux_res[] __initconst = {
+        DEFINE_RES_MEM(MX53_AUDMUX_BASE_ADDR, SZ_16K),
+};
+
 void __init imx50_soc_init(void)
 {
         /* i.mx50 has the i.mx31 type gpio */
@@ -179,6 +185,10 @@ void __init imx50_soc_init(void)
         mxc_register_gpio("imx31-gpio", 3, MX50_GPIO4_BASE_ADDR, SZ_16K, MX50_INT_GPIO4_LOW, MX50_INT_GPIO4_HIGH);
         mxc_register_gpio("imx31-gpio", 4, MX50_GPIO5_BASE_ADDR, SZ_16K, MX50_INT_GPIO5_LOW, MX50_INT_GPIO5_HIGH);
         mxc_register_gpio("imx31-gpio", 5, MX50_GPIO6_BASE_ADDR, SZ_16K, MX50_INT_GPIO6_LOW, MX50_INT_GPIO6_HIGH);
+
+        /* i.mx50 has the i.mx31 type audmux */
+        platform_device_register_simple("imx31-audmux", 0, imx50_audmux_res,
+                                        ARRAY_SIZE(imx50_audmux_res));
 }
 
 void __init imx51_soc_init(void)
@@ -191,6 +201,14 @@ void __init imx51_soc_init(void)
 
         /* i.mx51 has the i.mx35 type sdma */
         imx_add_imx_sdma("imx35-sdma", MX51_SDMA_BASE_ADDR, MX51_INT_SDMA, &imx51_sdma_pdata);
+
+        /* Setup AIPS registers */
+        imx_set_aips(MX51_IO_ADDRESS(MX51_AIPS1_BASE_ADDR));
+        imx_set_aips(MX51_IO_ADDRESS(MX51_AIPS2_BASE_ADDR));
+
+        /* i.mx51 has the i.mx31 type audmux */
+        platform_device_register_simple("imx31-audmux", 0, imx51_audmux_res,
+                                        ARRAY_SIZE(imx51_audmux_res));
 }
 
 void __init imx53_soc_init(void)
@@ -206,4 +224,12 @@ void __init imx53_soc_init(void)
 
         /* i.mx53 has the i.mx35 type sdma */
         imx_add_imx_sdma("imx35-sdma", MX53_SDMA_BASE_ADDR, MX53_INT_SDMA, &imx53_sdma_pdata);
+
+        /* Setup AIPS registers */
+        imx_set_aips(MX53_IO_ADDRESS(MX53_AIPS1_BASE_ADDR));
+        imx_set_aips(MX53_IO_ADDRESS(MX53_AIPS2_BASE_ADDR));
+
+        /* i.mx53 has the i.mx31 type audmux */
+        platform_device_register_simple("imx31-audmux", 0, imx53_audmux_res,
+                                        ARRAY_SIZE(imx53_audmux_res));
 }
diff --git a/arch/arm/mach-imx/pm-imx27.c b/arch/arm/mach-imx/pm-imx27.c
index e455d2f855b..6fcffa7db97 100644
--- a/arch/arm/mach-imx/pm-imx27.c
+++ b/arch/arm/mach-imx/pm-imx27.c
@@ -10,7 +10,6 @@
 #include <linux/kernel.h>
 #include <linux/suspend.h>
 #include <linux/io.h>
-#include <mach/system.h>
 #include <mach/hardware.h>
 
 static int mx27_suspend_enter(suspend_state_t state)
@@ -23,7 +22,7 @@ static int mx27_suspend_enter(suspend_state_t state)
                 cscr &= 0xFFFFFFFC;
                 __raw_writel(cscr, MX27_IO_ADDRESS(MX27_CCM_BASE_ADDR));
                 /* Executes WFI */
-                arch_idle();
+                cpu_do_idle();
                 break;
 
         default:
diff --git a/arch/arm/mach-imx/pm-imx3.c b/arch/arm/mach-imx/pm-imx3.c
new file mode 100644
index 00000000000..b3752439632
--- /dev/null
+++ b/arch/arm/mach-imx/pm-imx3.c
@@ -0,0 +1,37 @@
+/*
+ *  Copyright (C) 2012 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+#include <linux/io.h>
+#include <mach/common.h>
+#include <mach/hardware.h>
+#include <mach/devices-common.h>
+#include "crmregs-imx3.h"
+
+/*
+ * Set cpu low power mode before WFI instruction. This function is called
+ * mx3 because it can be used for mx31 and mx35.
+ * Currently only WAIT_MODE is supported.
+ */
+void mx3_cpu_lp_set(enum mx3_cpu_pwr_mode mode)
+{
+        int reg = __raw_readl(MXC_CCM_CCMR);
+        reg &= ~MXC_CCM_CCMR_LPM_MASK;
+
+        switch (mode) {
+        case MX3_WAIT:
+                if (cpu_is_mx35())
+                        reg |= MXC_CCM_CCMR_LPM_WAIT_MX35;
+                __raw_writel(reg, MXC_CCM_CCMR);
+                break;
+        default:
+                pr_err("Unknown cpu power mode: %d\n", mode);
+                return;
+        }
+}
diff --git a/arch/arm/mach-imx/pm-imx5.c b/arch/arm/mach-imx/pm-imx5.c
index 6dc09344805..e26a9cb05ed 100644
--- a/arch/arm/mach-imx/pm-imx5.c
+++ b/arch/arm/mach-imx/pm-imx5.c
@@ -89,7 +89,7 @@ void mx5_cpu_lp_set(enum mxc_cpu_pwr_mode mode)
 
 static int mx5_suspend_prepare(void)
 {
-        return clk_enable(gpc_dvfs_clk);
+        return clk_prepare_enable(gpc_dvfs_clk);
 }
 
 static int mx5_suspend_enter(suspend_state_t state)
@@ -119,7 +119,7 @@ static int mx5_suspend_enter(suspend_state_t state)
 
 static void mx5_suspend_finish(void)
 {
-        clk_disable(gpc_dvfs_clk);
+        clk_disable_unprepare(gpc_dvfs_clk);
 }
 
 static int mx5_pm_valid(suspend_state_t state)
diff --git a/arch/arm/mach-integrator/core.c b/arch/arm/mach-integrator/core.c
index 019f0ab08f6..15b87f26ac9 100644
--- a/arch/arm/mach-integrator/core.c
+++ b/arch/arm/mach-integrator/core.c
@@ -35,67 +35,23 @@
 
 static struct amba_pl010_data integrator_uart_data;
 
-static struct amba_device rtc_device = {
-        .dev            = {
-                .init_name = "mb:15",
-        },
-        .res            = {
-                .start  = INTEGRATOR_RTC_BASE,
-                .end    = INTEGRATOR_RTC_BASE + SZ_4K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        .irq            = { IRQ_RTCINT, NO_IRQ },
-};
+#define INTEGRATOR_RTC_IRQ      { IRQ_RTCINT }
+#define INTEGRATOR_UART0_IRQ    { IRQ_UARTINT0 }
+#define INTEGRATOR_UART1_IRQ    { IRQ_UARTINT1 }
+#define KMI0_IRQ                { IRQ_KMIINT0 }
+#define KMI1_IRQ                { IRQ_KMIINT1 }
 
-static struct amba_device uart0_device = {
-        .dev            = {
-                .init_name = "mb:16",
-                .platform_data = &integrator_uart_data,
-        },
-        .res            = {
-                .start  = INTEGRATOR_UART0_BASE,
-                .end    = INTEGRATOR_UART0_BASE + SZ_4K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        .irq            = { IRQ_UARTINT0, NO_IRQ },
-};
+static AMBA_APB_DEVICE(rtc, "mb:15", 0,
+        INTEGRATOR_RTC_BASE, INTEGRATOR_RTC_IRQ, NULL);
 
-static struct amba_device uart1_device = {
-        .dev            = {
-                .init_name = "mb:17",
-                .platform_data = &integrator_uart_data,
-        },
-        .res            = {
-                .start  = INTEGRATOR_UART1_BASE,
-                .end    = INTEGRATOR_UART1_BASE + SZ_4K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        .irq            = { IRQ_UARTINT1, NO_IRQ },
-};
+static AMBA_APB_DEVICE(uart0, "mb:16", 0,
+        INTEGRATOR_UART0_BASE, INTEGRATOR_UART0_IRQ, &integrator_uart_data);
 
-static struct amba_device kmi0_device = {
-        .dev            = {
-                .init_name = "mb:18",
-        },
-        .res            = {
-                .start  = KMI0_BASE,
-                .end    = KMI0_BASE + SZ_4K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        .irq            = { IRQ_KMIINT0, NO_IRQ },
-};
+static AMBA_APB_DEVICE(uart1, "mb:17", 0,
+        INTEGRATOR_UART1_BASE, INTEGRATOR_UART1_IRQ, &integrator_uart_data);
 
-static struct amba_device kmi1_device = {
-        .dev            = {
-                .init_name = "mb:19",
-        },
-        .res            = {
-                .start  = KMI1_BASE,
-                .end    = KMI1_BASE + SZ_4K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        .irq            = { IRQ_KMIINT1, NO_IRQ },
-};
+static AMBA_APB_DEVICE(kmi0, "mb:18", 0, KMI0_BASE, KMI0_IRQ, NULL);
+static AMBA_APB_DEVICE(kmi1, "mb:19", 0, KMI1_BASE, KMI1_IRQ, NULL);
 
 static struct amba_device *amba_devs[] __initdata = {
         &rtc_device,
diff --git a/arch/arm/mach-integrator/impd1.c b/arch/arm/mach-integrator/impd1.c
index 8cbb75a96bd..3e538da6cb1 100644
--- a/arch/arm/mach-integrator/impd1.c
+++ b/arch/arm/mach-integrator/impd1.c
@@ -401,24 +401,21 @@ static int impd1_probe(struct lm_device *dev)
 
                 pc_base = dev->resource.start + idev->offset;
 
-                d = kzalloc(sizeof(struct amba_device), GFP_KERNEL);
+                d = amba_device_alloc(NULL, pc_base, SZ_4K);
                 if (!d)
                         continue;
 
                 dev_set_name(&d->dev, "lm%x:%5.5lx", dev->id, idev->offset >> 12);
                 d->dev.parent   = &dev->dev;
-                d->res.start    = dev->resource.start + idev->offset;
-                d->res.end      = d->res.start + SZ_4K - 1;
-                d->res.flags    = IORESOURCE_MEM;
                 d->irq[0]       = dev->irq;
                 d->irq[1]       = dev->irq;
                 d->periphid     = idev->id;
                 d->dev.platform_data = idev->platform_data;
 
-                ret = amba_device_register(d, &dev->resource);
+                ret = amba_device_add(d, &dev->resource);
                 if (ret) {
                         dev_err(&d->dev, "unable to register device: %d\n", ret);
-                        kfree(d);
+                        amba_device_put(d);
                 }
         }
 
diff --git a/arch/arm/mach-integrator/include/mach/entry-macro.S b/arch/arm/mach-integrator/include/mach/entry-macro.S
index 3d029c9f3ef..5cc7b85ad9d 100644
--- a/arch/arm/mach-integrator/include/mach/entry-macro.S
+++ b/arch/arm/mach-integrator/include/mach/entry-macro.S
@@ -11,15 +11,9 @@
 #include <mach/platform.h>
 #include <mach/irqs.h>
 
-                .macro  disable_fiq
-                .endm
-
                 .macro  get_irqnr_preamble, base, tmp
                 .endm
 
-                .macro  arch_ret_to_user, tmp1, tmp2
-                .endm
-
                 .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
 /* FIXME: should not be using soo many LDRs here */
                 ldr     \base, =IO_ADDRESS(INTEGRATOR_IC_BASE)
diff --git a/arch/arm/mach-integrator/include/mach/system.h b/arch/arm/mach-integrator/include/mach/system.h
deleted file mode 100644
index 901514eba4a..00000000000
--- a/arch/arm/mach-integrator/include/mach/system.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/*
- *  arch/arm/mach-integrator/include/mach/system.h
- *
- *  Copyright (C) 1999 ARM Limited
- *  Copyright (C) 2000 Deep Blue Solutions Ltd
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#ifndef __ASM_ARCH_SYSTEM_H
-#define __ASM_ARCH_SYSTEM_H
-
-static inline void arch_idle(void)
-{
-        /*
-         * This should do all the clock switching
-         * and wait for interrupt tricks
-         */
-        cpu_do_idle();
-}
-
-#endif
diff --git a/arch/arm/mach-integrator/integrator_cp.c b/arch/arm/mach-integrator/integrator_cp.c
index a8b6aa6003f..be9ead4a3bc 100644
--- a/arch/arm/mach-integrator/integrator_cp.c
+++ b/arch/arm/mach-integrator/integrator_cp.c
@@ -347,32 +347,14 @@ static struct mmci_platform_data mmc_data = {
         .gpio_cd        = -1,
 };
 
-static struct amba_device mmc_device = {
-        .dev            = {
-                .init_name = "mb:1c",
-                .platform_data = &mmc_data,
-        },
-        .res            = {
-                .start  = INTEGRATOR_CP_MMC_BASE,
-                .end    = INTEGRATOR_CP_MMC_BASE + SZ_4K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        .irq            = { IRQ_CP_MMCIINT0, IRQ_CP_MMCIINT1 },
-        .periphid       = 0,
-};
+#define INTEGRATOR_CP_MMC_IRQS  { IRQ_CP_MMCIINT0, IRQ_CP_MMCIINT1 }
+#define INTEGRATOR_CP_AACI_IRQS { IRQ_CP_AACIINT }
 
-static struct amba_device aaci_device = {
-        .dev            = {
-                .init_name = "mb:1d",
-        },
-        .res            = {
-                .start  = INTEGRATOR_CP_AACI_BASE,
-                .end    = INTEGRATOR_CP_AACI_BASE + SZ_4K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        .irq            = { IRQ_CP_AACIINT, NO_IRQ },
-        .periphid       = 0,
-};
+static AMBA_APB_DEVICE(mmc, "mb:1c", 0, INTEGRATOR_CP_MMC_BASE,
+        INTEGRATOR_CP_MMC_IRQS, &mmc_data);
+
+static AMBA_APB_DEVICE(aaci, "mb:1d", 0, INTEGRATOR_CP_AACI_BASE,
+        INTEGRATOR_CP_AACI_IRQS, NULL);
 
 
 /*
@@ -425,21 +407,8 @@ static struct clcd_board clcd_data = {
         .remove         = versatile_clcd_remove_dma,
 };
 
-static struct amba_device clcd_device = {
-        .dev            = {
-                .init_name = "mb:c0",
-                .coherent_dma_mask = ~0,
-                .platform_data = &clcd_data,
-        },
-        .res            = {
-                .start  = INTCP_PA_CLCD_BASE,
-                .end    = INTCP_PA_CLCD_BASE + SZ_4K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        .dma_mask       = ~0,
-        .irq            = { IRQ_CP_CLCDCINT, NO_IRQ },
-        .periphid       = 0,
-};
+static AMBA_AHB_DEVICE(clcd, "mb:c0", 0, INTCP_PA_CLCD_BASE,
+        { IRQ_CP_CLCDCINT }, &clcd_data);
 
 static struct amba_device *amba_devs[] __initdata = {
         &mmc_device,
diff --git a/arch/arm/mach-integrator/pci_v3.c b/arch/arm/mach-integrator/pci_v3.c
index 3c82566acec..015be770c1d 100644
--- a/arch/arm/mach-integrator/pci_v3.c
+++ b/arch/arm/mach-integrator/pci_v3.c
@@ -378,9 +378,10 @@ static int __init pci_v3_setup_resources(struct pci_sys_data *sys)
          * the mem resource for this bus
          * the prefetch mem resource for this bus
          */
-        pci_add_resource(&sys->resources, &ioport_resource);
-        pci_add_resource(&sys->resources, &non_mem);
-        pci_add_resource(&sys->resources, &pre_mem);
+        pci_add_resource_offset(&sys->resources,
+                                &ioport_resource, sys->io_offset);
+        pci_add_resource_offset(&sys->resources, &non_mem, sys->mem_offset);
+        pci_add_resource_offset(&sys->resources, &pre_mem, sys->mem_offset);
 
         return 1;
 }
diff --git a/arch/arm/mach-iop13xx/include/mach/entry-macro.S b/arch/arm/mach-iop13xx/include/mach/entry-macro.S
index a624a7870c6..1a2d603488d 100644
--- a/arch/arm/mach-iop13xx/include/mach/entry-macro.S
+++ b/arch/arm/mach-iop13xx/include/mach/entry-macro.S
@@ -16,9 +16,6 @@
  * Place - Suite 330, Boston, MA 02111-1307 USA.
  *
  */
-        .macro  disable_fiq
-        .endm
-
         .macro get_irqnr_preamble, base, tmp
         mrc     p15, 0, \tmp, c15, c1, 0
         orr     \tmp, \tmp, #(1 << 6)
diff --git a/arch/arm/mach-iop13xx/include/mach/system.h b/arch/arm/mach-iop13xx/include/mach/system.h
deleted file mode 100644
index 1f31ed3f8ae..00000000000
--- a/arch/arm/mach-iop13xx/include/mach/system.h
+++ /dev/null
@@ -1,13 +0,0 @@
-/*
- * arch/arm/mach-iop13xx/include/mach/system.h
- *
- *  Copyright (C) 2004 Intel Corp.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-static inline void arch_idle(void)
-{
-        cpu_do_idle();
-}
diff --git a/arch/arm/mach-iop13xx/pci.c b/arch/arm/mach-iop13xx/pci.c
index b8f5a873651..861cb12ef43 100644
--- a/arch/arm/mach-iop13xx/pci.c
+++ b/arch/arm/mach-iop13xx/pci.c
@@ -1084,8 +1084,8 @@ int iop13xx_pci_setup(int nr, struct pci_sys_data *sys)
         request_resource(&ioport_resource, &res[0]);
         request_resource(&iomem_resource, &res[1]);
 
-        pci_add_resource(&sys->resources, &res[0]);
-        pci_add_resource(&sys->resources, &res[1]);
+        pci_add_resource_offset(&sys->resources, &res[0], sys->io_offset);
+        pci_add_resource_offset(&sys->resources, &res[1], sys->mem_offset);
 
         return 1;
 }
diff --git a/arch/arm/mach-iop32x/include/mach/entry-macro.S b/arch/arm/mach-iop32x/include/mach/entry-macro.S
index b02fb56bafc..ea13ae02d9b 100644
--- a/arch/arm/mach-iop32x/include/mach/entry-macro.S
+++ b/arch/arm/mach-iop32x/include/mach/entry-macro.S
@@ -9,9 +9,6 @@
  */
 #include <mach/iop32x.h>
 
-        .macro  disable_fiq
-        .endm
-
         .macro get_irqnr_preamble, base, tmp
         mrc     p15, 0, \tmp, c15, c1, 0
         orr     \tmp, \tmp, #(1 << 6)
diff --git a/arch/arm/mach-iop32x/include/mach/system.h b/arch/arm/mach-iop32x/include/mach/system.h
deleted file mode 100644
index 4a88727bca9..00000000000
--- a/arch/arm/mach-iop32x/include/mach/system.h
+++ /dev/null
@@ -1,13 +0,0 @@
-/*
- * arch/arm/mach-iop32x/include/mach/system.h
- *
- * Copyright (C) 2001 MontaVista Software, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-static inline void arch_idle(void)
-{
-        cpu_do_idle();
-}
diff --git a/arch/arm/mach-iop33x/include/mach/entry-macro.S b/arch/arm/mach-iop33x/include/mach/entry-macro.S
index 4e1f7282b35..0a398fe1fba 100644
--- a/arch/arm/mach-iop33x/include/mach/entry-macro.S
+++ b/arch/arm/mach-iop33x/include/mach/entry-macro.S
@@ -9,9 +9,6 @@
  */
 #include <mach/iop33x.h>
 
-        .macro  disable_fiq
-        .endm
-
         .macro get_irqnr_preamble, base, tmp
         mrc     p15, 0, \tmp, c15, c1, 0
         orr     \tmp, \tmp, #(1 << 6)
diff --git a/arch/arm/mach-iop33x/include/mach/system.h b/arch/arm/mach-iop33x/include/mach/system.h
deleted file mode 100644
index 4f98e765397..00000000000
--- a/arch/arm/mach-iop33x/include/mach/system.h
+++ /dev/null
@@ -1,13 +0,0 @@
-/*
- * arch/arm/mach-iop33x/include/mach/system.h
- *
- * Copyright (C) 2001 MontaVista Software, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-static inline void arch_idle(void)
-{
-        cpu_do_idle();
-}
diff --git a/arch/arm/mach-ixp2000/include/mach/entry-macro.S b/arch/arm/mach-ixp2000/include/mach/entry-macro.S
index 5850ffc8c75..c4444dff920 100644
--- a/arch/arm/mach-ixp2000/include/mach/entry-macro.S
+++ b/arch/arm/mach-ixp2000/include/mach/entry-macro.S
@@ -9,15 +9,9 @@
  */
 #include <mach/irqs.h>
 
-                .macro  disable_fiq
-                .endm
-
                 .macro  get_irqnr_preamble, base, tmp
                 .endm
 
-                .macro  arch_ret_to_user, tmp1, tmp2
-                .endm
-
                 .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
 
                 mov     \irqnr, #0x0              @clear out irqnr as default
diff --git a/arch/arm/mach-ixp2000/include/mach/system.h b/arch/arm/mach-ixp2000/include/mach/system.h
deleted file mode 100644
index a7fb08b2b8e..00000000000
--- a/arch/arm/mach-ixp2000/include/mach/system.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/*
- * arch/arm/mach-ixp2000/include/mach/system.h
- *
- * Copyright (C) 2002 Intel Corp.
- * Copyricht (C) 2003-2005 MontaVista Software, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-static inline void arch_idle(void)
-{
-        cpu_do_idle();
-}
diff --git a/arch/arm/mach-ixp2000/ixdp2400.c b/arch/arm/mach-ixp2000/ixdp2400.c
index f53e911ec94..d519944653a 100644
--- a/arch/arm/mach-ixp2000/ixdp2400.c
+++ b/arch/arm/mach-ixp2000/ixdp2400.c
@@ -134,11 +134,11 @@ static void ixdp2400_pci_postinit(void)
 
         if (ixdp2x00_master_npu()) {
                 dev = pci_get_bus_and_slot(1, IXDP2400_SLAVE_ENET_DEVFN);
-                pci_remove_bus_device(dev);
+                pci_stop_and_remove_bus_device(dev);
                 pci_dev_put(dev);
         } else {
                 dev = pci_get_bus_and_slot(1, IXDP2400_MASTER_ENET_DEVFN);
-                pci_remove_bus_device(dev);
+                pci_stop_and_remove_bus_device(dev);
                 pci_dev_put(dev);
 
                 ixdp2x00_slave_pci_postinit();
diff --git a/arch/arm/mach-ixp2000/ixdp2800.c b/arch/arm/mach-ixp2000/ixdp2800.c
index a2e7c393e74..b415febd202 100644
--- a/arch/arm/mach-ixp2000/ixdp2800.c
+++ b/arch/arm/mach-ixp2000/ixdp2800.c
@@ -262,14 +262,14 @@ int __init ixdp2800_pci_init(void)
                 pci_common_init(&ixdp2800_pci);
                 if (ixdp2x00_master_npu()) {
                         dev = pci_get_bus_and_slot(1, IXDP2800_SLAVE_ENET_DEVFN);
-                        pci_remove_bus_device(dev);
+                        pci_stop_and_remove_bus_device(dev);
                         pci_dev_put(dev);
 
                         ixdp2800_master_enable_slave();
                         ixdp2800_master_wait_for_slave_bus_scan();
                 } else {
                         dev = pci_get_bus_and_slot(1, IXDP2800_MASTER_ENET_DEVFN);
-                        pci_remove_bus_device(dev);
+                        pci_stop_and_remove_bus_device(dev);
                         pci_dev_put(dev);
                 }
         }
diff --git a/arch/arm/mach-ixp2000/ixdp2x00.c b/arch/arm/mach-ixp2000/ixdp2x00.c
index 634b6c852f6..dd983829906 100644
--- a/arch/arm/mach-ixp2000/ixdp2x00.c
+++ b/arch/arm/mach-ixp2000/ixdp2x00.c
@@ -239,12 +239,12 @@ void ixdp2x00_slave_pci_postinit(void)
          * Remove PMC device is there is one
          */
         if((dev = pci_get_bus_and_slot(1, IXDP2X00_PMC_DEVFN))) {
-                pci_remove_bus_device(dev);
+                pci_stop_and_remove_bus_device(dev);
                 pci_dev_put(dev);
         }
 
         dev = pci_get_bus_and_slot(0, IXDP2X00_21555_DEVFN);
-        pci_remove_bus_device(dev);
+        pci_stop_and_remove_bus_device(dev);
         pci_dev_put(dev);
 }
 
diff --git a/arch/arm/mach-ixp2000/pci.c b/arch/arm/mach-ixp2000/pci.c
index 626fda435aa..49c36f3cd60 100644
--- a/arch/arm/mach-ixp2000/pci.c
+++ b/arch/arm/mach-ixp2000/pci.c
@@ -243,8 +243,10 @@ int ixp2000_pci_setup(int nr, struct pci_sys_data *sys)
         if (nr >= 1)
                 return 0;
 
-        pci_add_resource(&sys->resources, &ixp2000_pci_io_space);
-        pci_add_resource(&sys->resources, &ixp2000_pci_mem_space);
+        pci_add_resource_offset(&sys->resources,
+                                &ixp2000_pci_io_space, sys->io_offset);
+        pci_add_resource_offset(&sys->resources,
+                                &ixp2000_pci_mem_space, sys->mem_offset);
 
         return 1;
 }
diff --git a/arch/arm/mach-ixp23xx/core.c b/arch/arm/mach-ixp23xx/core.c
index 0923bb905cc..7c1495e4fe7 100644
--- a/arch/arm/mach-ixp23xx/core.c
+++ b/arch/arm/mach-ixp23xx/core.c
@@ -441,6 +441,9 @@ static struct platform_device *ixp23xx_devices[] __initdata = {
 
 void __init ixp23xx_sys_init(void)
 {
+        /* by default, the idle code is disabled */
+        disable_hlt();
+
         *IXP23XX_EXP_UNIT_FUSE |= 0xf;
         platform_add_devices(ixp23xx_devices, ARRAY_SIZE(ixp23xx_devices));
 }
diff --git a/arch/arm/mach-ixp23xx/include/mach/entry-macro.S b/arch/arm/mach-ixp23xx/include/mach/entry-macro.S
index 3f5338a7bbd..3fd2cb984e4 100644
--- a/arch/arm/mach-ixp23xx/include/mach/entry-macro.S
+++ b/arch/arm/mach-ixp23xx/include/mach/entry-macro.S
@@ -2,15 +2,9 @@
  * arch/arm/mach-ixp23xx/include/mach/entry-macro.S
  */
 
-                .macro  disable_fiq
-                .endm
-
                 .macro  get_irqnr_preamble, base, tmp
                 .endm
 
-                .macro  arch_ret_to_user, tmp1, tmp2
-                .endm
-
                 .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
                 ldr     \irqnr, =(IXP23XX_INTC_VIRT + IXP23XX_INTR_IRQ_ENC_ST_OFFSET)
                 ldr     \irqnr, [\irqnr]        @ get interrupt number
diff --git a/arch/arm/mach-ixp23xx/include/mach/system.h b/arch/arm/mach-ixp23xx/include/mach/system.h
deleted file mode 100644
index 277dda7334b..00000000000
--- a/arch/arm/mach-ixp23xx/include/mach/system.h
+++ /dev/null
@@ -1,16 +0,0 @@
-/*
- * arch/arm/mach-ixp23xx/include/mach/system.h
- *
- * Copyright (C) 2003 Intel Corporation.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-static inline void arch_idle(void)
-{
-#if 0
-        if (!hlt_counter)
-                cpu_do_idle();
-#endif
-}
diff --git a/arch/arm/mach-ixp23xx/pci.c b/arch/arm/mach-ixp23xx/pci.c
index 25b5c462cea..3cbbd3208fa 100644
--- a/arch/arm/mach-ixp23xx/pci.c
+++ b/arch/arm/mach-ixp23xx/pci.c
@@ -281,8 +281,10 @@ int ixp23xx_pci_setup(int nr, struct pci_sys_data *sys)
         if (nr >= 1)
                 return 0;
 
-        pci_add_resource(&sys->resources, &ixp23xx_pci_io_space);
-        pci_add_resource(&sys->resources, &ixp23xx_pci_mem_space);
+        pci_add_resource_offset(&sys->resources,
+                                &ixp23xx_pci_io_space, sys->io_offset);
+        pci_add_resource_offset(&sys->resources,
+                                &ixp23xx_pci_mem_space, sys->mem_offset);
 
         return 1;
 }
diff --git a/arch/arm/mach-ixp4xx/common-pci.c b/arch/arm/mach-ixp4xx/common-pci.c
index 5eff15f24bc..8508882b13f 100644
--- a/arch/arm/mach-ixp4xx/common-pci.c
+++ b/arch/arm/mach-ixp4xx/common-pci.c
@@ -472,8 +472,8 @@ int ixp4xx_setup(int nr, struct pci_sys_data *sys)
         request_resource(&ioport_resource, &res[0]);
         request_resource(&iomem_resource, &res[1]);
 
-        pci_add_resource(&sys->resources, &res[0]);
-        pci_add_resource(&sys->resources, &res[1]);
+        pci_add_resource_offset(&sys->resources, &res[0], sys->io_offset);
+        pci_add_resource_offset(&sys->resources, &res[1], sys->mem_offset);
 
         platform_notify = ixp4xx_pci_platform_notify;
         platform_notify_remove = ixp4xx_pci_platform_notify_remove;
diff --git a/arch/arm/mach-ixp4xx/common.c b/arch/arm/mach-ixp4xx/common.c
index 3841ab4146b..a6329a0a8ec 100644
--- a/arch/arm/mach-ixp4xx/common.c
+++ b/arch/arm/mach-ixp4xx/common.c
@@ -236,6 +236,12 @@ void __init ixp4xx_init_irq(void)
 {
         int i = 0;
 
+        /*
+         * ixp4xx does not implement the XScale PWRMODE register
+         * so it must not call cpu_do_idle().
+         */
+        disable_hlt();
+
         /* Route all sources to IRQ instead of FIQ */
         *IXP4XX_ICLR = 0x0;
 
diff --git a/arch/arm/mach-ixp4xx/include/mach/entry-macro.S b/arch/arm/mach-ixp4xx/include/mach/entry-macro.S
index f2e14e94ed1..79adf83e2c3 100644
--- a/arch/arm/mach-ixp4xx/include/mach/entry-macro.S
+++ b/arch/arm/mach-ixp4xx/include/mach/entry-macro.S
@@ -9,15 +9,9 @@
  */
 #include <mach/hardware.h>
 
-                .macro  disable_fiq
-                .endm
-
                 .macro  get_irqnr_preamble, base, tmp
                 .endm
 
-                .macro  arch_ret_to_user, tmp1, tmp2
-                .endm
-
                 .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
                 ldr     \irqstat, =(IXP4XX_INTC_BASE_VIRT+IXP4XX_ICIP_OFFSET)
                 ldr     \irqstat, [\irqstat]            @ get interrupts
diff --git a/arch/arm/mach-ixp4xx/include/mach/system.h b/arch/arm/mach-ixp4xx/include/mach/system.h
deleted file mode 100644
index 140a9bef446..00000000000
--- a/arch/arm/mach-ixp4xx/include/mach/system.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/*
- * arch/arm/mach-ixp4xx/include/mach/system.h
- *
- * Copyright (C) 2002 Intel Corporation.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- */
-static inline void arch_idle(void)
-{
-        /* ixp4xx does not implement the XScale PWRMODE register,
-         * so it must not call cpu_do_idle() here.
-         */
-#if 0
-        cpu_do_idle();
-#endif
-}
diff --git a/arch/arm/mach-kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig
index 7fc603b4689..90ceab76192 100644
--- a/arch/arm/mach-kirkwood/Kconfig
+++ b/arch/arm/mach-kirkwood/Kconfig
@@ -44,6 +44,20 @@ config MACH_GURUPLUG
           Say 'Y' here if you want your kernel to support the
           Marvell GuruPlug Reference Board.
 
+config ARCH_KIRKWOOD_DT
+        bool "Marvell Kirkwood Flattened Device Tree"
+        select USE_OF
+        help
+          Say 'Y' here if you want your kernel to support the
+          Marvell Kirkwood using flattened device tree.
+
+config MACH_DREAMPLUG_DT
+        bool "Marvell DreamPlug (Flattened Device Tree)"
+        select ARCH_KIRKWOOD_DT
+        help
+          Say 'Y' here if you want your kernel to support the
+          Marvell DreamPlug (Flattened Device Tree).
+
 config MACH_TS219
         bool "QNAP TS-110, TS-119, TS-119P+, TS-210, TS-219, TS-219P and TS-219P+ Turbo NAS"
         help
diff --git a/arch/arm/mach-kirkwood/Makefile b/arch/arm/mach-kirkwood/Makefile
index 5dcaa81a2ec..acbc5e1db06 100644
--- a/arch/arm/mach-kirkwood/Makefile
+++ b/arch/arm/mach-kirkwood/Makefile
@@ -20,3 +20,4 @@ obj-$(CONFIG_MACH_NET5BIG_V2)		+= netxbig_v2-setup.o lacie_v2-common.o
 obj-$(CONFIG_MACH_T5325)                += t5325-setup.o
 
 obj-$(CONFIG_CPU_IDLE)                  += cpuidle.o
+obj-$(CONFIG_ARCH_KIRKWOOD_DT)          += board-dt.o
diff --git a/arch/arm/mach-kirkwood/Makefile.boot b/arch/arm/mach-kirkwood/Makefile.boot
index 760a0efe758..16f93852230 100644
--- a/arch/arm/mach-kirkwood/Makefile.boot
+++ b/arch/arm/mach-kirkwood/Makefile.boot
@@ -1,3 +1,5 @@
    zreladdr-y   += 0x00008000
 params_phys-y   := 0x00000100
 initrd_phys-y   := 0x00800000
+
+dtb-$(CONFIG_MACH_DREAMPLUG_DT) += kirkwood-dreamplug.dtb
diff --git a/arch/arm/mach-kirkwood/board-dt.c b/arch/arm/mach-kirkwood/board-dt.c
new file mode 100644
index 00000000000..fbe6405602e
--- /dev/null
+++ b/arch/arm/mach-kirkwood/board-dt.c
@@ -0,0 +1,180 @@
+/*
+ * Copyright 2012 (C), Jason Cooper <jason@lakedaemon.net>
+ *
+ * arch/arm/mach-kirkwood/board-dt.c
+ *
+ * Marvell DreamPlug Reference Board Setup
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/mtd/partitions.h>
+#include <linux/ata_platform.h>
+#include <linux/mv643xx_eth.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_fdt.h>
+#include <linux/of_irq.h>
+#include <linux/of_platform.h>
+#include <linux/gpio.h>
+#include <linux/leds.h>
+#include <linux/mtd/physmap.h>
+#include <linux/spi/flash.h>
+#include <linux/spi/spi.h>
+#include <linux/spi/orion_spi.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <mach/kirkwood.h>
+#include <plat/mvsdio.h>
+#include "common.h"
+#include "mpp.h"
+
+static struct of_device_id kirkwood_dt_match_table[] __initdata = {
+        { .compatible = "simple-bus", },
+        { }
+};
+
+struct mtd_partition dreamplug_partitions[] = {
+        {
+                .name   = "u-boot",
+                .size   = SZ_512K,
+                .offset = 0,
+        },
+        {
+                .name   = "u-boot env",
+                .size   = SZ_64K,
+                .offset = SZ_512K + SZ_512K,
+        },
+        {
+                .name   = "dtb",
+                .size   = SZ_64K,
+                .offset = SZ_512K + SZ_512K + SZ_512K,
+        },
+};
+
+static const struct flash_platform_data dreamplug_spi_slave_data = {
+        .type           = "mx25l1606e",
+        .name           = "spi_flash",
+        .parts          = dreamplug_partitions,
+        .nr_parts       = ARRAY_SIZE(dreamplug_partitions),
+};
+
+static struct spi_board_info __initdata dreamplug_spi_slave_info[] = {
+        {
+                .modalias       = "m25p80",
+                .platform_data  = &dreamplug_spi_slave_data,
+                .irq            = -1,
+                .max_speed_hz   = 50000000,
+                .bus_num        = 0,
+                .chip_select    = 0,
+        },
+};
+
+static struct mv643xx_eth_platform_data dreamplug_ge00_data = {
+        .phy_addr       = MV643XX_ETH_PHY_ADDR(0),
+};
+
+static struct mv643xx_eth_platform_data dreamplug_ge01_data = {
+        .phy_addr       = MV643XX_ETH_PHY_ADDR(1),
+};
+
+static struct mv_sata_platform_data dreamplug_sata_data = {
+        .n_ports        = 1,
+};
+
+static struct mvsdio_platform_data dreamplug_mvsdio_data = {
+        /* unfortunately the CD signal has not been connected */
+};
+
+static struct gpio_led dreamplug_led_pins[] = {
+        {
+                .name                   = "dreamplug:blue:bluetooth",
+                .gpio                   = 47,
+                .active_low             = 1,
+        },
+        {
+                .name                   = "dreamplug:green:wifi",
+                .gpio                   = 48,
+                .active_low             = 1,
+        },
+        {
+                .name                   = "dreamplug:green:wifi_ap",
+                .gpio                   = 49,
+                .active_low             = 1,
+        },
+};
+
+static struct gpio_led_platform_data dreamplug_led_data = {
+        .leds           = dreamplug_led_pins,
+        .num_leds       = ARRAY_SIZE(dreamplug_led_pins),
+};
+
+static struct platform_device dreamplug_leds = {
+        .name   = "leds-gpio",
+        .id     = -1,
+        .dev    = {
+                .platform_data  = &dreamplug_led_data,
+        }
+};
+
+static unsigned int dreamplug_mpp_config[] __initdata = {
+        MPP0_SPI_SCn,
+        MPP1_SPI_MOSI,
+        MPP2_SPI_SCK,
+        MPP3_SPI_MISO,
+        MPP47_GPIO,     /* Bluetooth LED */
+        MPP48_GPIO,     /* Wifi LED */
+        MPP49_GPIO,     /* Wifi AP LED */
+        0
+};
+
+static void __init dreamplug_init(void)
+{
+        /*
+         * Basic setup. Needs to be called early.
+         */
+        kirkwood_mpp_conf(dreamplug_mpp_config);
+
+        spi_register_board_info(dreamplug_spi_slave_info,
+                                ARRAY_SIZE(dreamplug_spi_slave_info));
+        kirkwood_spi_init();
+
+        kirkwood_ehci_init();
+        kirkwood_ge00_init(&dreamplug_ge00_data);
+        kirkwood_ge01_init(&dreamplug_ge01_data);
+        kirkwood_sata_init(&dreamplug_sata_data);
+        kirkwood_sdio_init(&dreamplug_mvsdio_data);
+
+        platform_device_register(&dreamplug_leds);
+}
+
+static void __init kirkwood_dt_init(void)
+{
+        kirkwood_init();
+
+        if (of_machine_is_compatible("globalscale,dreamplug"))
+                dreamplug_init();
+
+        of_platform_populate(NULL, kirkwood_dt_match_table, NULL, NULL);
+}
+
+static const char *kirkwood_dt_board_compat[] = {
+        "globalscale,dreamplug",
+        NULL
+};
+
+DT_MACHINE_START(KIRKWOOD_DT, "Marvell Kirkwood (Flattened Device Tree)")
+        /* Maintainer: Jason Cooper <jason@lakedaemon.net> */
+        .map_io         = kirkwood_map_io,
+        .init_early     = kirkwood_init_early,
+        .init_irq       = kirkwood_init_irq,
+        .timer          = &kirkwood_timer,
+        .init_machine   = kirkwood_dt_init,
+        .restart        = kirkwood_restart,
+        .dt_compat      = kirkwood_dt_board_compat,
+MACHINE_END
diff --git a/arch/arm/mach-kirkwood/include/mach/entry-macro.S b/arch/arm/mach-kirkwood/include/mach/entry-macro.S
index 8939d36f893..82db29f7af8 100644
--- a/arch/arm/mach-kirkwood/include/mach/entry-macro.S
+++ b/arch/arm/mach-kirkwood/include/mach/entry-macro.S
@@ -10,12 +10,6 @@
 
 #include <mach/bridge-regs.h>
 
-        .macro  disable_fiq
-        .endm
-
-        .macro  arch_ret_to_user, tmp1, tmp2
-        .endm
-
         .macro  get_irqnr_preamble, base, tmp
         ldr     \base, =IRQ_VIRT_BASE
         .endm
diff --git a/arch/arm/mach-kirkwood/include/mach/system.h b/arch/arm/mach-kirkwood/include/mach/system.h
deleted file mode 100644
index 5fddde002b5..00000000000
--- a/arch/arm/mach-kirkwood/include/mach/system.h
+++ /dev/null
@@ -1,17 +0,0 @@
-/*
- * arch/arm/mach-kirkwood/include/mach/system.h
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#ifndef __ASM_ARCH_SYSTEM_H
-#define __ASM_ARCH_SYSTEM_H
-
-static inline void arch_idle(void)
-{
-        cpu_do_idle();
-}
-
-#endif
diff --git a/arch/arm/mach-kirkwood/openrd-setup.c b/arch/arm/mach-kirkwood/openrd-setup.c
index 01f8c899288..7e99c3f340f 100644
--- a/arch/arm/mach-kirkwood/openrd-setup.c
+++ b/arch/arm/mach-kirkwood/openrd-setup.c
@@ -83,6 +83,11 @@ static struct i2c_board_info i2c_board_info[] __initdata = {
         },
 };
 
+static struct platform_device openrd_client_audio_device = {
+        .name           = "openrd-client-audio",
+        .id             = -1,
+};
+
 static int __initdata uart1;
 
 static int __init sd_uart_selection(char *str)
@@ -172,6 +177,7 @@ static void __init openrd_init(void)
         kirkwood_i2c_init();
 
         if (machine_is_openrd_client() || machine_is_openrd_ultimate()) {
+                platform_device_register(&openrd_client_audio_device);
                 i2c_register_board_info(0, i2c_board_info,
                         ARRAY_SIZE(i2c_board_info));
                 kirkwood_audio_init();
diff --git a/arch/arm/mach-kirkwood/pcie.c b/arch/arm/mach-kirkwood/pcie.c
index a066a6d8d9d..f56a0118c1b 100644
--- a/arch/arm/mach-kirkwood/pcie.c
+++ b/arch/arm/mach-kirkwood/pcie.c
@@ -198,9 +198,9 @@ static int __init kirkwood_pcie_setup(int nr, struct pci_sys_data *sys)
         if (request_resource(&iomem_resource, &pp->res[1]))
                 panic("Request PCIe%d Memory resource failed\n", index);
 
-        pci_add_resource(&sys->resources, &pp->res[0]);
-        pci_add_resource(&sys->resources, &pp->res[1]);
         sys->io_offset = 0;
+        pci_add_resource_offset(&sys->resources, &pp->res[0], sys->io_offset);
+        pci_add_resource_offset(&sys->resources, &pp->res[1], sys->mem_offset);
 
         /*
          * Generic PCIe unit setup.
diff --git a/arch/arm/mach-kirkwood/t5325-setup.c b/arch/arm/mach-kirkwood/t5325-setup.c
index 966b2b3bb81..f9d2a11b7f9 100644
--- a/arch/arm/mach-kirkwood/t5325-setup.c
+++ b/arch/arm/mach-kirkwood/t5325-setup.c
@@ -106,6 +106,11 @@ static struct platform_device hp_t5325_button_device = {
         }
 };
 
+static struct platform_device hp_t5325_audio_device = {
+        .name           = "t5325-audio",
+        .id             = -1,
+};
+
 static unsigned int hp_t5325_mpp_config[] __initdata = {
         MPP0_NF_IO2,
         MPP1_SPI_MOSI,
@@ -179,6 +184,7 @@ static void __init hp_t5325_init(void)
         kirkwood_sata_init(&hp_t5325_sata_data);
         kirkwood_ehci_init();
         platform_device_register(&hp_t5325_button_device);
+        platform_device_register(&hp_t5325_audio_device);
 
         i2c_register_board_info(0, i2c_board_info, ARRAY_SIZE(i2c_board_info));
         kirkwood_audio_init();
diff --git a/arch/arm/mach-ks8695/include/mach/entry-macro.S b/arch/arm/mach-ks8695/include/mach/entry-macro.S
index b4fe0c11c6c..8315b34f32f 100644
--- a/arch/arm/mach-ks8695/include/mach/entry-macro.S
+++ b/arch/arm/mach-ks8695/include/mach/entry-macro.S
@@ -14,16 +14,10 @@
 #include <mach/hardware.h>
 #include <mach/regs-irq.h>
 
-        .macro  disable_fiq
-        .endm
-
         .macro  get_irqnr_preamble, base, tmp
                 ldr     \base, =KS8695_IRQ_VA                   @ Base address of interrupt controller
         .endm
 
-        .macro  arch_ret_to_user, tmp1, tmp2
-        .endm
-
         .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
                 ldr     \irqstat, [\base, #KS8695_INTMS]        @ Mask Status register
 
diff --git a/arch/arm/mach-ks8695/include/mach/system.h b/arch/arm/mach-ks8695/include/mach/system.h
deleted file mode 100644
index 59fe992395b..00000000000
--- a/arch/arm/mach-ks8695/include/mach/system.h
+++ /dev/null
@@ -1,27 +0,0 @@
-/*
- * arch/arm/mach-s3c2410/include/mach/system.h
- *
- * Copyright (C) 2006 Simtec Electronics
- *      Ben Dooks <ben@simtec.co.uk>
- *
- * KS8695 - System function defines and includes
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef __ASM_ARCH_SYSTEM_H
-#define __ASM_ARCH_SYSTEM_H
-
-static void arch_idle(void)
-{
-        /*
-         * This should do all the clock switching
-         * and wait for interrupt tricks,
-         */
-        cpu_do_idle();
-
-}
-
-#endif
diff --git a/arch/arm/mach-ks8695/pci.c b/arch/arm/mach-ks8695/pci.c
index b26f992071d..acc70143581 100644
--- a/arch/arm/mach-ks8695/pci.c
+++ b/arch/arm/mach-ks8695/pci.c
@@ -169,8 +169,8 @@ static int __init ks8695_pci_setup(int nr, struct pci_sys_data *sys)
         request_resource(&iomem_resource, &pci_mem);
         request_resource(&ioport_resource, &pci_io);
 
-        pci_add_resource(&sys->resources, &pci_io);
-        pci_add_resource(&sys->resources, &pci_mem);
+        pci_add_resource_offset(&sys->resources, &pci_io, sys->io_offset);
+        pci_add_resource_offset(&sys->resources, &pci_mem, sys->mem_offset);
 
         /* Assign and enable processor bridge */
         ks8695_local_writeconfig(PCI_BASE_ADDRESS_0, KS8695_PCIMEM_PA);
diff --git a/arch/arm/mach-lpc32xx/clock.c b/arch/arm/mach-lpc32xx/clock.c
index 1e027514096..f55c772d181 100644
--- a/arch/arm/mach-lpc32xx/clock.c
+++ b/arch/arm/mach-lpc32xx/clock.c
@@ -82,6 +82,7 @@
  *   will also impact the individual peripheral rates.
  */
 
+#include <linux/export.h>
 #include <linux/kernel.h>
 #include <linux/list.h>
 #include <linux/errno.h>
@@ -97,9 +98,10 @@
 #include "clock.h"
 #include "common.h"
 
+static DEFINE_SPINLOCK(global_clkregs_lock);
+
 static struct clk clk_armpll;
 static struct clk clk_usbpll;
-static DEFINE_MUTEX(clkm_lock);
 
 /*
  * Post divider values for PLLs based on selected register value
@@ -127,7 +129,7 @@ static struct clk osc_32KHz = {
 static int local_pll397_enable(struct clk *clk, int enable)
 {
         u32 reg;
-        unsigned long timeout = 1 + msecs_to_jiffies(10);
+        unsigned long timeout = jiffies + msecs_to_jiffies(10);
 
         reg = __raw_readl(LPC32XX_CLKPWR_PLL397_CTRL);
 
@@ -142,7 +144,7 @@ static int local_pll397_enable(struct clk *clk, int enable)
                 /* Wait for PLL397 lock */
                 while (((__raw_readl(LPC32XX_CLKPWR_PLL397_CTRL) &
                         LPC32XX_CLKPWR_SYSCTRL_PLL397_STS) == 0) &&
-                        (timeout > jiffies))
+                        time_before(jiffies, timeout))
                         cpu_relax();
 
                 if ((__raw_readl(LPC32XX_CLKPWR_PLL397_CTRL) &
@@ -156,7 +158,7 @@ static int local_pll397_enable(struct clk *clk, int enable)
 static int local_oscmain_enable(struct clk *clk, int enable)
 {
         u32 reg;
-        unsigned long timeout = 1 + msecs_to_jiffies(10);
+        unsigned long timeout = jiffies + msecs_to_jiffies(10);
 
         reg = __raw_readl(LPC32XX_CLKPWR_MAIN_OSC_CTRL);
 
@@ -171,7 +173,7 @@ static int local_oscmain_enable(struct clk *clk, int enable)
                 /* Wait for main oscillator to start */
                 while (((__raw_readl(LPC32XX_CLKPWR_MAIN_OSC_CTRL) &
                         LPC32XX_CLKPWR_MOSC_DISABLE) != 0) &&
-                        (timeout > jiffies))
+                        time_before(jiffies, timeout))
                         cpu_relax();
 
                 if ((__raw_readl(LPC32XX_CLKPWR_MAIN_OSC_CTRL) &
@@ -383,7 +385,7 @@ static int local_usbpll_enable(struct clk *clk, int enable)
 {
         u32 reg;
         int ret = -ENODEV;
-        unsigned long timeout = 1 + msecs_to_jiffies(10);
+        unsigned long timeout = jiffies + msecs_to_jiffies(10);
 
         reg = __raw_readl(LPC32XX_CLKPWR_USB_CTRL);
 
@@ -396,7 +398,7 @@ static int local_usbpll_enable(struct clk *clk, int enable)
                 __raw_writel(reg, LPC32XX_CLKPWR_USB_CTRL);
 
                 /* Wait for PLL lock */
-                while ((timeout > jiffies) & (ret == -ENODEV)) {
+                while (time_before(jiffies, timeout) && (ret == -ENODEV)) {
                         reg = __raw_readl(LPC32XX_CLKPWR_USB_CTRL);
                         if (reg & LPC32XX_CLKPWR_USBCTRL_PLL_STS)
                                 ret = 0;
@@ -719,6 +721,41 @@ static struct clk clk_tsc = {
         .get_rate       = local_return_parent_rate,
 };
 
+static int adc_onoff_enable(struct clk *clk, int enable)
+{
+        u32 tmp;
+        u32 divider;
+
+        /* Use PERIPH_CLOCK */
+        tmp = __raw_readl(LPC32XX_CLKPWR_ADC_CLK_CTRL_1);
+        tmp |= LPC32XX_CLKPWR_ADCCTRL1_PCLK_SEL;
+        /*
+         * Set clock divider so that we have equal to or less than
+         * 4.5MHz clock at ADC
+         */
+        divider = clk->get_rate(clk) / 4500000 + 1;
+        tmp |= divider;
+        __raw_writel(tmp, LPC32XX_CLKPWR_ADC_CLK_CTRL_1);
+
+        /* synchronize rate of this clock w/ actual HW setting */
+        clk->rate = clk->get_rate(clk->parent) / divider;
+
+        if (enable == 0)
+                __raw_writel(0, clk->enable_reg);
+        else
+                __raw_writel(clk->enable_mask, clk->enable_reg);
+
+        return 0;
+}
+
+static struct clk clk_adc = {
+        .parent         = &clk_pclk,
+        .enable         = adc_onoff_enable,
+        .enable_reg     = LPC32XX_CLKPWR_ADC_CLK_CTRL,
+        .enable_mask    = LPC32XX_CLKPWR_ADC32CLKCTRL_CLK_EN,
+        .get_rate       = local_return_parent_rate,
+};
+
 static int mmc_onoff_enable(struct clk *clk, int enable)
 {
         u32 tmp;
@@ -891,20 +928,8 @@ static struct clk clk_lcd = {
         .enable_mask    = LPC32XX_CLKPWR_LCDCTRL_CLK_EN,
 };
 
-static inline void clk_lock(void)
-{
-        mutex_lock(&clkm_lock);
-}
-
-static inline void clk_unlock(void)
-{
-        mutex_unlock(&clkm_lock);
-}
-
 static void local_clk_disable(struct clk *clk)
 {
-        WARN_ON(clk->usecount == 0);
-
         /* Don't attempt to disable clock if it has no users */
         if (clk->usecount > 0) {
                 clk->usecount--;
@@ -947,10 +972,11 @@ static int local_clk_enable(struct clk *clk)
 int clk_enable(struct clk *clk)
 {
         int ret;
+        unsigned long flags;
 
-        clk_lock();
+        spin_lock_irqsave(&global_clkregs_lock, flags);
         ret = local_clk_enable(clk);
-        clk_unlock();
+        spin_unlock_irqrestore(&global_clkregs_lock, flags);
 
         return ret;
 }
@@ -961,9 +987,11 @@ EXPORT_SYMBOL(clk_enable);
  */
 void clk_disable(struct clk *clk)
 {
-        clk_lock();
+        unsigned long flags;
+
+        spin_lock_irqsave(&global_clkregs_lock, flags);
         local_clk_disable(clk);
-        clk_unlock();
+        spin_unlock_irqrestore(&global_clkregs_lock, flags);
 }
 EXPORT_SYMBOL(clk_disable);
 
@@ -972,13 +1000,7 @@ EXPORT_SYMBOL(clk_disable);
  */
 unsigned long clk_get_rate(struct clk *clk)
 {
-        unsigned long rate;
-
-        clk_lock();
-        rate = clk->get_rate(clk);
-        clk_unlock();
-
-        return rate;
+        return clk->get_rate(clk);
 }
 EXPORT_SYMBOL(clk_get_rate);
 
@@ -994,11 +1016,8 @@ int clk_set_rate(struct clk *clk, unsigned long rate)
          * the actual rate set as part of the peripheral dividers
          * instead of high level clock control
          */
-        if (clk->set_rate) {
-                clk_lock();
+        if (clk->set_rate)
                 ret = clk->set_rate(clk, rate);
-                clk_unlock();
-        }
 
         return ret;
 }
@@ -1009,15 +1028,11 @@ EXPORT_SYMBOL(clk_set_rate);
  */
 long clk_round_rate(struct clk *clk, unsigned long rate)
 {
-        clk_lock();
-
         if (clk->round_rate)
                 rate = clk->round_rate(clk, rate);
         else
                 rate = clk->get_rate(clk);
 
-        clk_unlock();
-
         return rate;
 }
 EXPORT_SYMBOL(clk_round_rate);
@@ -1075,10 +1090,11 @@ static struct clk_lookup lookups[] = {
         _REGISTER_CLOCK("dev:ssp1", NULL, clk_ssp1)
         _REGISTER_CLOCK("lpc32xx_keys.0", NULL, clk_kscan)
         _REGISTER_CLOCK("lpc32xx-nand.0", "nand_ck", clk_nand)
-        _REGISTER_CLOCK("tbd", "i2s0_ck", clk_i2s0)
-        _REGISTER_CLOCK("tbd", "i2s1_ck", clk_i2s1)
+        _REGISTER_CLOCK("lpc32xx-adc", NULL, clk_adc)
+        _REGISTER_CLOCK(NULL, "i2s0_ck", clk_i2s0)
+        _REGISTER_CLOCK(NULL, "i2s1_ck", clk_i2s1)
         _REGISTER_CLOCK("ts-lpc32xx", NULL, clk_tsc)
-        _REGISTER_CLOCK("dev:mmc0", "MCLK", clk_mmc)
+        _REGISTER_CLOCK("dev:mmc0", NULL, clk_mmc)
         _REGISTER_CLOCK("lpc-net.0", NULL, clk_net)
         _REGISTER_CLOCK("dev:clcd", NULL, clk_lcd)
         _REGISTER_CLOCK("lpc32xx_udc", "ck_usbd", clk_usbd)
diff --git a/arch/arm/mach-lpc32xx/common.c b/arch/arm/mach-lpc32xx/common.c
index 369b152896c..6c76bb36559 100644
--- a/arch/arm/mach-lpc32xx/common.c
+++ b/arch/arm/mach-lpc32xx/common.c
@@ -138,6 +138,28 @@ struct platform_device lpc32xx_rtc_device = {
 };
 
 /*
+ * ADC support
+ */
+static struct resource adc_resources[] = {
+        {
+                .start = LPC32XX_ADC_BASE,
+                .end = LPC32XX_ADC_BASE + SZ_4K - 1,
+                .flags = IORESOURCE_MEM,
+        }, {
+                .start = IRQ_LPC32XX_TS_IRQ,
+                .end = IRQ_LPC32XX_TS_IRQ,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+
+struct platform_device lpc32xx_adc_device = {
+        .name =  "lpc32xx-adc",
+        .id = -1,
+        .num_resources = ARRAY_SIZE(adc_resources),
+        .resource = adc_resources,
+};
+
+/*
  * Returns the unique ID for the device
  */
 void lpc32xx_get_uid(u32 devid[4])
diff --git a/arch/arm/mach-lpc32xx/common.h b/arch/arm/mach-lpc32xx/common.h
index 4b4e700343c..68f2e46d98a 100644
--- a/arch/arm/mach-lpc32xx/common.h
+++ b/arch/arm/mach-lpc32xx/common.h
@@ -29,6 +29,7 @@ extern struct platform_device lpc32xx_i2c0_device;
 extern struct platform_device lpc32xx_i2c1_device;
 extern struct platform_device lpc32xx_i2c2_device;
 extern struct platform_device lpc32xx_tsc_device;
+extern struct platform_device lpc32xx_adc_device;
 extern struct platform_device lpc32xx_rtc_device;
 
 /*
@@ -65,7 +66,6 @@ extern u32 clk_get_pclk_div(void);
  */
 extern void lpc32xx_get_uid(u32 devid[4]);
 
-extern void lpc32xx_watchdog_reset(void);
 extern u32 lpc32xx_return_iram_size(void);
 
 /*
diff --git a/arch/arm/mach-lpc32xx/include/mach/entry-macro.S b/arch/arm/mach-lpc32xx/include/mach/entry-macro.S
index b725f6c9397..24ca11b377c 100644
--- a/arch/arm/mach-lpc32xx/include/mach/entry-macro.S
+++ b/arch/arm/mach-lpc32xx/include/mach/entry-macro.S
@@ -21,16 +21,10 @@
 
 #define LPC32XX_INTC_MASKED_STATUS_OFS  0x8
 
-        .macro  disable_fiq
-        .endm
-
         .macro  get_irqnr_preamble, base, tmp
         ldr     \base, =IO_ADDRESS(LPC32XX_MIC_BASE)
         .endm
 
-        .macro  arch_ret_to_user, tmp1, tmp2
-        .endm
-
 /*
  * Return IRQ number in irqnr. Also return processor Z flag status in CPSR
  * as set if an interrupt is pending.
diff --git a/arch/arm/mach-lpc32xx/include/mach/platform.h b/arch/arm/mach-lpc32xx/include/mach/platform.h
index 14ea8d1aadb..c584f5bb164 100644
--- a/arch/arm/mach-lpc32xx/include/mach/platform.h
+++ b/arch/arm/mach-lpc32xx/include/mach/platform.h
@@ -591,42 +591,42 @@
 /*
  * Timer/counter register offsets
  */
-#define LCP32XX_TIMER_IR(x)                     io_p2v((x) + 0x00)
-#define LCP32XX_TIMER_TCR(x)                    io_p2v((x) + 0x04)
-#define LCP32XX_TIMER_TC(x)                     io_p2v((x) + 0x08)
-#define LCP32XX_TIMER_PR(x)                     io_p2v((x) + 0x0C)
-#define LCP32XX_TIMER_PC(x)                     io_p2v((x) + 0x10)
-#define LCP32XX_TIMER_MCR(x)                    io_p2v((x) + 0x14)
-#define LCP32XX_TIMER_MR0(x)                    io_p2v((x) + 0x18)
-#define LCP32XX_TIMER_MR1(x)                    io_p2v((x) + 0x1C)
-#define LCP32XX_TIMER_MR2(x)                    io_p2v((x) + 0x20)
-#define LCP32XX_TIMER_MR3(x)                    io_p2v((x) + 0x24)
-#define LCP32XX_TIMER_CCR(x)                    io_p2v((x) + 0x28)
-#define LCP32XX_TIMER_CR0(x)                    io_p2v((x) + 0x2C)
-#define LCP32XX_TIMER_CR1(x)                    io_p2v((x) + 0x30)
-#define LCP32XX_TIMER_CR2(x)                    io_p2v((x) + 0x34)
-#define LCP32XX_TIMER_CR3(x)                    io_p2v((x) + 0x38)
-#define LCP32XX_TIMER_EMR(x)                    io_p2v((x) + 0x3C)
-#define LCP32XX_TIMER_CTCR(x)                   io_p2v((x) + 0x70)
+#define LPC32XX_TIMER_IR(x)                     io_p2v((x) + 0x00)
+#define LPC32XX_TIMER_TCR(x)                    io_p2v((x) + 0x04)
+#define LPC32XX_TIMER_TC(x)                     io_p2v((x) + 0x08)
+#define LPC32XX_TIMER_PR(x)                     io_p2v((x) + 0x0C)
+#define LPC32XX_TIMER_PC(x)                     io_p2v((x) + 0x10)
+#define LPC32XX_TIMER_MCR(x)                    io_p2v((x) + 0x14)
+#define LPC32XX_TIMER_MR0(x)                    io_p2v((x) + 0x18)
+#define LPC32XX_TIMER_MR1(x)                    io_p2v((x) + 0x1C)
+#define LPC32XX_TIMER_MR2(x)                    io_p2v((x) + 0x20)
+#define LPC32XX_TIMER_MR3(x)                    io_p2v((x) + 0x24)
+#define LPC32XX_TIMER_CCR(x)                    io_p2v((x) + 0x28)
+#define LPC32XX_TIMER_CR0(x)                    io_p2v((x) + 0x2C)
+#define LPC32XX_TIMER_CR1(x)                    io_p2v((x) + 0x30)
+#define LPC32XX_TIMER_CR2(x)                    io_p2v((x) + 0x34)
+#define LPC32XX_TIMER_CR3(x)                    io_p2v((x) + 0x38)
+#define LPC32XX_TIMER_EMR(x)                    io_p2v((x) + 0x3C)
+#define LPC32XX_TIMER_CTCR(x)                   io_p2v((x) + 0x70)
 
 /*
  * ir register definitions
  */
-#define LCP32XX_TIMER_CNTR_MTCH_BIT(n)          (1 << ((n) & 0x3))
-#define LCP32XX_TIMER_CNTR_CAPT_BIT(n)          (1 << (4 + ((n) & 0x3)))
+#define LPC32XX_TIMER_CNTR_MTCH_BIT(n)          (1 << ((n) & 0x3))
+#define LPC32XX_TIMER_CNTR_CAPT_BIT(n)          (1 << (4 + ((n) & 0x3)))
 
 /*
  * tcr register definitions
  */
-#define LCP32XX_TIMER_CNTR_TCR_EN               0x1
-#define LCP32XX_TIMER_CNTR_TCR_RESET            0x2
+#define LPC32XX_TIMER_CNTR_TCR_EN               0x1
+#define LPC32XX_TIMER_CNTR_TCR_RESET            0x2
 
 /*
  * mcr register definitions
  */
-#define LCP32XX_TIMER_CNTR_MCR_MTCH(n)          (0x1 << ((n) * 3))
-#define LCP32XX_TIMER_CNTR_MCR_RESET(n)         (0x1 << (((n) * 3) + 1))
-#define LCP32XX_TIMER_CNTR_MCR_STOP(n)          (0x1 << (((n) * 3) + 2))
+#define LPC32XX_TIMER_CNTR_MCR_MTCH(n)          (0x1 << ((n) * 3))
+#define LPC32XX_TIMER_CNTR_MCR_RESET(n)         (0x1 << (((n) * 3) + 1))
+#define LPC32XX_TIMER_CNTR_MCR_STOP(n)          (0x1 << (((n) * 3) + 2))
 
 /*
  * Standard UART register offsets
@@ -690,5 +690,8 @@
 #define LPC32XX_GPIO_P1_MUX_SET                 _GPREG(0x130)
 #define LPC32XX_GPIO_P1_MUX_CLR                 _GPREG(0x134)
 #define LPC32XX_GPIO_P1_MUX_STATE               _GPREG(0x138)
+#define LPC32XX_GPIO_P2_MUX_SET                 _GPREG(0x028)
+#define LPC32XX_GPIO_P2_MUX_CLR                 _GPREG(0x02C)
+#define LPC32XX_GPIO_P2_MUX_STATE               _GPREG(0x030)
 
 #endif
diff --git a/arch/arm/mach-lpc32xx/include/mach/system.h b/arch/arm/mach-lpc32xx/include/mach/system.h
deleted file mode 100644
index bf176c99152..00000000000
--- a/arch/arm/mach-lpc32xx/include/mach/system.h
+++ /dev/null
@@ -1,27 +0,0 @@
-/*
- * arch/arm/mach-lpc32xx/include/mach/system.h
- *
- * Author: Kevin Wells <kevin.wells@nxp.com>
- *
- * Copyright (C) 2010 NXP Semiconductors
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#ifndef __ASM_ARCH_SYSTEM_H
-#define __ASM_ARCH_SYSTEM_H
-
-static void arch_idle(void)
-{
-        cpu_do_idle();
-}
-
-#endif
diff --git a/arch/arm/mach-lpc32xx/phy3250.c b/arch/arm/mach-lpc32xx/phy3250.c
index bfee5b45510..0d79a3f8a5e 100644
--- a/arch/arm/mach-lpc32xx/phy3250.c
+++ b/arch/arm/mach-lpc32xx/phy3250.c
@@ -149,20 +149,8 @@ static struct clcd_board lpc32xx_clcd_data = {
         .remove         = lpc32xx_clcd_remove,
 };
 
-static struct amba_device lpc32xx_clcd_device = {
-        .dev                            = {
-                .coherent_dma_mask      = ~0,
-                .init_name              = "dev:clcd",
-                .platform_data          = &lpc32xx_clcd_data,
-        },
-        .res                            = {
-                .start                  = LPC32XX_LCD_BASE,
-                .end                    = (LPC32XX_LCD_BASE + SZ_4K - 1),
-                .flags                  = IORESOURCE_MEM,
-        },
-        .dma_mask                       = ~0,
-        .irq                            = {IRQ_LPC32XX_LCD, NO_IRQ},
-};
+static AMBA_AHB_DEVICE(lpc32xx_clcd, "dev:clcd", 0,
+        LPC32XX_LCD_BASE, { IRQ_LPC32XX_LCD }, &lpc32xx_clcd_data);
 
 /*
  * AMBA SSP (SPI)
@@ -191,20 +179,8 @@ static struct pl022_ssp_controller lpc32xx_ssp0_data = {
         .enable_dma             = 0,
 };
 
-static struct amba_device lpc32xx_ssp0_device = {
-        .dev                            = {
-                .coherent_dma_mask      = ~0,
-                .init_name              = "dev:ssp0",
-                .platform_data          = &lpc32xx_ssp0_data,
-        },
-        .res                            = {
-                .start                  = LPC32XX_SSP0_BASE,
-                .end                    = (LPC32XX_SSP0_BASE + SZ_4K - 1),
-                .flags                  = IORESOURCE_MEM,
-        },
-        .dma_mask                       = ~0,
-        .irq                            = {IRQ_LPC32XX_SSP0, NO_IRQ},
-};
+static AMBA_APB_DEVICE(lpc32xx_ssp0, "dev:ssp0", 0,
+        LPC32XX_SSP0_BASE, { IRQ_LPC32XX_SSP0 }, &lpc32xx_ssp0_data);
 
 /* AT25 driver registration */
 static int __init phy3250_spi_board_register(void)
@@ -271,11 +247,14 @@ static struct platform_device lpc32xx_gpio_led_device = {
 };
 
 static struct platform_device *phy3250_devs[] __initdata = {
+        &lpc32xx_rtc_device,
+        &lpc32xx_tsc_device,
         &lpc32xx_i2c0_device,
         &lpc32xx_i2c1_device,
         &lpc32xx_i2c2_device,
         &lpc32xx_watchdog_device,
         &lpc32xx_gpio_led_device,
+        &lpc32xx_adc_device,
 };
 
 static struct amba_device *amba_devs[] __initdata = {
diff --git a/arch/arm/mach-lpc32xx/pm.c b/arch/arm/mach-lpc32xx/pm.c
index b9c80597b7b..207e81275ff 100644
--- a/arch/arm/mach-lpc32xx/pm.c
+++ b/arch/arm/mach-lpc32xx/pm.c
@@ -13,7 +13,7 @@
 /*
  * LPC32XX CPU and system power management
  *
- * The LCP32XX has three CPU modes for controlling system power: run,
+ * The LPC32XX has three CPU modes for controlling system power: run,
  * direct-run, and halt modes. When switching between halt and run modes,
  * the CPU transistions through direct-run mode. For Linux, direct-run
  * mode is not used in normal operation. Halt mode is used when the
diff --git a/arch/arm/mach-lpc32xx/timer.c b/arch/arm/mach-lpc32xx/timer.c
index b42c909bbee..c40667c3316 100644
--- a/arch/arm/mach-lpc32xx/timer.c
+++ b/arch/arm/mach-lpc32xx/timer.c
@@ -34,11 +34,11 @@
 static int lpc32xx_clkevt_next_event(unsigned long delta,
     struct clock_event_device *dev)
 {
-        __raw_writel(LCP32XX_TIMER_CNTR_TCR_RESET,
-                LCP32XX_TIMER_TCR(LPC32XX_TIMER0_BASE));
-        __raw_writel(delta, LCP32XX_TIMER_PR(LPC32XX_TIMER0_BASE));
-        __raw_writel(LCP32XX_TIMER_CNTR_TCR_EN,
-                LCP32XX_TIMER_TCR(LPC32XX_TIMER0_BASE));
+        __raw_writel(LPC32XX_TIMER_CNTR_TCR_RESET,
+                LPC32XX_TIMER_TCR(LPC32XX_TIMER0_BASE));
+        __raw_writel(delta, LPC32XX_TIMER_PR(LPC32XX_TIMER0_BASE));
+        __raw_writel(LPC32XX_TIMER_CNTR_TCR_EN,
+                LPC32XX_TIMER_TCR(LPC32XX_TIMER0_BASE));
 
         return 0;
 }
@@ -58,7 +58,7 @@ static void lpc32xx_clkevt_mode(enum clock_event_mode mode,
                  * disable the timer to wait for the first call to
                  * set_next_event().
                  */
-                __raw_writel(0, LCP32XX_TIMER_TCR(LPC32XX_TIMER0_BASE));
+                __raw_writel(0, LPC32XX_TIMER_TCR(LPC32XX_TIMER0_BASE));
                 break;
 
         case CLOCK_EVT_MODE_UNUSED:
@@ -81,8 +81,8 @@ static irqreturn_t lpc32xx_timer_interrupt(int irq, void *dev_id)
         struct clock_event_device *evt = &lpc32xx_clkevt;
 
         /* Clear match */
-        __raw_writel(LCP32XX_TIMER_CNTR_MTCH_BIT(0),
-                LCP32XX_TIMER_IR(LPC32XX_TIMER0_BASE));
+        __raw_writel(LPC32XX_TIMER_CNTR_MTCH_BIT(0),
+                LPC32XX_TIMER_IR(LPC32XX_TIMER0_BASE));
 
         evt->event_handler(evt);
 
@@ -128,14 +128,14 @@ static void __init lpc32xx_timer_init(void)
         clkrate = clkrate / clk_get_pclk_div();
 
         /* Initial timer setup */
-        __raw_writel(0, LCP32XX_TIMER_TCR(LPC32XX_TIMER0_BASE));
-        __raw_writel(LCP32XX_TIMER_CNTR_MTCH_BIT(0),
-                LCP32XX_TIMER_IR(LPC32XX_TIMER0_BASE));
-        __raw_writel(1, LCP32XX_TIMER_MR0(LPC32XX_TIMER0_BASE));
-        __raw_writel(LCP32XX_TIMER_CNTR_MCR_MTCH(0) |
-                LCP32XX_TIMER_CNTR_MCR_STOP(0) |
-                LCP32XX_TIMER_CNTR_MCR_RESET(0),
-                LCP32XX_TIMER_MCR(LPC32XX_TIMER0_BASE));
+        __raw_writel(0, LPC32XX_TIMER_TCR(LPC32XX_TIMER0_BASE));
+        __raw_writel(LPC32XX_TIMER_CNTR_MTCH_BIT(0),
+                LPC32XX_TIMER_IR(LPC32XX_TIMER0_BASE));
+        __raw_writel(1, LPC32XX_TIMER_MR0(LPC32XX_TIMER0_BASE));
+        __raw_writel(LPC32XX_TIMER_CNTR_MCR_MTCH(0) |
+                LPC32XX_TIMER_CNTR_MCR_STOP(0) |
+                LPC32XX_TIMER_CNTR_MCR_RESET(0),
+                LPC32XX_TIMER_MCR(LPC32XX_TIMER0_BASE));
 
         /* Setup tick interrupt */
         setup_irq(IRQ_LPC32XX_TIMER0, &lpc32xx_timer_irq);
@@ -151,14 +151,14 @@ static void __init lpc32xx_timer_init(void)
         clockevents_register_device(&lpc32xx_clkevt);
 
         /* Use timer1 as clock source. */
-        __raw_writel(LCP32XX_TIMER_CNTR_TCR_RESET,
-                LCP32XX_TIMER_TCR(LPC32XX_TIMER1_BASE));
-        __raw_writel(0, LCP32XX_TIMER_PR(LPC32XX_TIMER1_BASE));
-        __raw_writel(0, LCP32XX_TIMER_MCR(LPC32XX_TIMER1_BASE));
-        __raw_writel(LCP32XX_TIMER_CNTR_TCR_EN,
-                LCP32XX_TIMER_TCR(LPC32XX_TIMER1_BASE));
-
-        clocksource_mmio_init(LCP32XX_TIMER_TC(LPC32XX_TIMER1_BASE),
+        __raw_writel(LPC32XX_TIMER_CNTR_TCR_RESET,
+                LPC32XX_TIMER_TCR(LPC32XX_TIMER1_BASE));
+        __raw_writel(0, LPC32XX_TIMER_PR(LPC32XX_TIMER1_BASE));
+        __raw_writel(0, LPC32XX_TIMER_MCR(LPC32XX_TIMER1_BASE));
+        __raw_writel(LPC32XX_TIMER_CNTR_TCR_EN,
+                LPC32XX_TIMER_TCR(LPC32XX_TIMER1_BASE));
+
+        clocksource_mmio_init(LPC32XX_TIMER_TC(LPC32XX_TIMER1_BASE),
                 "lpc32xx_clksrc", clkrate, 300, 32, clocksource_mmio_readl_up);
 }
 
diff --git a/arch/arm/mach-mmp/Kconfig b/arch/arm/mach-mmp/Kconfig
index 323d4c9e9f4..5a90b9a3ab6 100644
--- a/arch/arm/mach-mmp/Kconfig
+++ b/arch/arm/mach-mmp/Kconfig
@@ -2,6 +2,16 @@ if ARCH_MMP
 
 menu "Marvell PXA168/910/MMP2 Implmentations"
 
+config MACH_MMP_DT
+        bool "Support MMP2 platforms from device tree"
+        select CPU_PXA168
+        select CPU_PXA910
+        select USE_OF
+        help
+          Include support for Marvell MMP2 based platforms using
+          the device tree. Needn't select any other machine while
+          MACH_MMP_DT is enabled.
+
 config MACH_ASPENITE
         bool "Marvell's PXA168 Aspenite Development Board"
         select CPU_PXA168
diff --git a/arch/arm/mach-mmp/Makefile b/arch/arm/mach-mmp/Makefile
index ba254a71691..4fc0ff5dc96 100644
--- a/arch/arm/mach-mmp/Makefile
+++ b/arch/arm/mach-mmp/Makefile
@@ -18,5 +18,6 @@ obj-$(CONFIG_MACH_TTC_DKB)	+= ttc_dkb.o
 obj-$(CONFIG_MACH_BROWNSTONE)   += brownstone.o
 obj-$(CONFIG_MACH_FLINT)        += flint.o
 obj-$(CONFIG_MACH_MARVELL_JASPER) += jasper.o
+obj-$(CONFIG_MACH_MMP_DT)       += mmp-dt.o
 obj-$(CONFIG_MACH_TETON_BGA)    += teton_bga.o
 obj-$(CONFIG_MACH_GPLUGD)       += gplugd.o
diff --git a/arch/arm/mach-mmp/include/mach/entry-macro.S b/arch/arm/mach-mmp/include/mach/entry-macro.S
index c42d9d4e892..9cff9e7a2b2 100644
--- a/arch/arm/mach-mmp/include/mach/entry-macro.S
+++ b/arch/arm/mach-mmp/include/mach/entry-macro.S
@@ -8,12 +8,6 @@
 
 #include <mach/regs-icu.h>
 
-        .macro  disable_fiq
-        .endm
-
-        .macro  arch_ret_to_user, tmp1, tmp2
-        .endm
-
         .macro  get_irqnr_preamble, base, tmp
         mrc     p15, 0, \tmp, c0, c0, 0         @ CPUID
         and     \tmp, \tmp, #0xff00
diff --git a/arch/arm/mach-mmp/include/mach/pxa910.h b/arch/arm/mach-mmp/include/mach/pxa910.h
index 4de13abef7b..e2e1f1e5e12 100644
--- a/arch/arm/mach-mmp/include/mach/pxa910.h
+++ b/arch/arm/mach-mmp/include/mach/pxa910.h
@@ -22,6 +22,7 @@ extern struct pxa_device_desc pxa910_device_pwm4;
 extern struct pxa_device_desc pxa910_device_nand;
 
 extern struct platform_device pxa910_device_gpio;
+extern struct platform_device pxa910_device_rtc;
 
 static inline int pxa910_add_uart(int id)
 {
diff --git a/arch/arm/mach-mmp/include/mach/regs-apbc.h b/arch/arm/mach-mmp/include/mach/regs-apbc.h
index 1a96585336b..8a37fb00365 100644
--- a/arch/arm/mach-mmp/include/mach/regs-apbc.h
+++ b/arch/arm/mach-mmp/include/mach/regs-apbc.h
@@ -57,6 +57,7 @@
 #define APBC_PXA910_SSP1        APBC_REG(0x01c)
 #define APBC_PXA910_SSP2        APBC_REG(0x020)
 #define APBC_PXA910_IPC         APBC_REG(0x024)
+#define APBC_PXA910_RTC         APBC_REG(0x028)
 #define APBC_PXA910_TWSI0       APBC_REG(0x02c)
 #define APBC_PXA910_KPC         APBC_REG(0x030)
 #define APBC_PXA910_TIMERS      APBC_REG(0x034)
diff --git a/arch/arm/mach-mmp/include/mach/regs-rtc.h b/arch/arm/mach-mmp/include/mach/regs-rtc.h
new file mode 100644
index 00000000000..5bff886a394
--- /dev/null
+++ b/arch/arm/mach-mmp/include/mach/regs-rtc.h
@@ -0,0 +1,23 @@
+#ifndef __ASM_MACH_REGS_RTC_H
+#define __ASM_MACH_REGS_RTC_H
+
+#include <mach/addr-map.h>
+
+#define RTC_VIRT_BASE   (APB_VIRT_BASE + 0x10000)
+#define RTC_REG(x)      (*((volatile u32 __iomem *)(RTC_VIRT_BASE + (x))))
+
+/*
+ * Real Time Clock
+ */
+
+#define RCNR            RTC_REG(0x00)   /* RTC Count Register */
+#define RTAR            RTC_REG(0x04)   /* RTC Alarm Register */
+#define RTSR            RTC_REG(0x08)   /* RTC Status Register */
+#define RTTR            RTC_REG(0x0C)   /* RTC Timer Trim Register */
+
+#define RTSR_HZE        (1 << 3)        /* HZ interrupt enable */
+#define RTSR_ALE        (1 << 2)        /* RTC alarm interrupt enable */
+#define RTSR_HZ         (1 << 1)        /* HZ rising-edge detected */
+#define RTSR_AL         (1 << 0)        /* RTC alarm detected */
+
+#endif /* __ASM_MACH_REGS_RTC_H */
diff --git a/arch/arm/mach-mmp/include/mach/system.h b/arch/arm/mach-mmp/include/mach/system.h
deleted file mode 100644
index 1d001eab81e..00000000000
--- a/arch/arm/mach-mmp/include/mach/system.h
+++ /dev/null
@@ -1,16 +0,0 @@
-/*
- * linux/arch/arm/mach-mmp/include/mach/system.h
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef __ASM_MACH_SYSTEM_H
-#define __ASM_MACH_SYSTEM_H
-
-static inline void arch_idle(void)
-{
-        cpu_do_idle();
-}
-#endif /* __ASM_MACH_SYSTEM_H */
diff --git a/arch/arm/mach-mmp/mmp-dt.c b/arch/arm/mach-mmp/mmp-dt.c
new file mode 100644
index 00000000000..67075395e40
--- /dev/null
+++ b/arch/arm/mach-mmp/mmp-dt.c
@@ -0,0 +1,75 @@
+/*
+ *  linux/arch/arm/mach-mmp/mmp-dt.c
+ *
+ *  Copyright (C) 2012 Marvell Technology Group Ltd.
+ *  Author: Haojian Zhuang <haojian.zhuang@marvell.com>
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  publishhed by the Free Software Foundation.
+ */
+
+#include <linux/irq.h>
+#include <linux/irqdomain.h>
+#include <linux/of_irq.h>
+#include <linux/of_platform.h>
+#include <asm/mach/arch.h>
+#include <mach/irqs.h>
+
+#include "common.h"
+
+extern struct sys_timer pxa168_timer;
+extern void __init icu_init_irq(void);
+
+static const struct of_dev_auxdata mmp_auxdata_lookup[] __initconst = {
+        OF_DEV_AUXDATA("mrvl,mmp-uart", 0xd4017000, "pxa2xx-uart.0", NULL),
+        OF_DEV_AUXDATA("mrvl,mmp-uart", 0xd4018000, "pxa2xx-uart.1", NULL),
+        OF_DEV_AUXDATA("mrvl,mmp-uart", 0xd4026000, "pxa2xx-uart.2", NULL),
+        OF_DEV_AUXDATA("mrvl,mmp-twsi", 0xd4011000, "pxa2xx-i2c.0", NULL),
+        OF_DEV_AUXDATA("mrvl,mmp-twsi", 0xd4025000, "pxa2xx-i2c.1", NULL),
+        OF_DEV_AUXDATA("mrvl,mmp-gpio", 0xd4019000, "pxa-gpio", NULL),
+        OF_DEV_AUXDATA("mrvl,mmp-rtc", 0xd4010000, "sa1100-rtc", NULL),
+        {}
+};
+
+static int __init mmp_intc_add_irq_domain(struct device_node *np,
+                                           struct device_node *parent)
+{
+        irq_domain_add_simple(np, 0);
+        return 0;
+}
+
+static int __init mmp_gpio_add_irq_domain(struct device_node *np,
+                                           struct device_node *parent)
+{
+        irq_domain_add_simple(np, IRQ_GPIO_START);
+        return 0;
+}
+
+static const struct of_device_id mmp_irq_match[] __initconst = {
+        { .compatible = "mrvl,mmp-intc", .data = mmp_intc_add_irq_domain, },
+        { .compatible = "mrvl,mmp-gpio", .data = mmp_gpio_add_irq_domain, },
+        {}
+};
+
+static void __init mmp_dt_init(void)
+{
+
+        of_irq_init(mmp_irq_match);
+
+        of_platform_populate(NULL, of_default_bus_match_table,
+                             mmp_auxdata_lookup, NULL);
+}
+
+static const char *pxa168_dt_board_compat[] __initdata = {
+        "mrvl,pxa168-aspenite",
+        NULL,
+};
+
+DT_MACHINE_START(PXA168_DT, "Marvell PXA168 (Device Tree Support)")
+        .map_io         = mmp_map_io,
+        .init_irq       = icu_init_irq,
+        .timer          = &pxa168_timer,
+        .init_machine   = mmp_dt_init,
+        .dt_compat      = pxa168_dt_board_compat,
+MACHINE_END
diff --git a/arch/arm/mach-mmp/mmp2.c b/arch/arm/mach-mmp/mmp2.c
index 617c60a170a..c709a24a9d2 100644
--- a/arch/arm/mach-mmp/mmp2.c
+++ b/arch/arm/mach-mmp/mmp2.c
@@ -223,6 +223,7 @@ struct resource mmp2_resource_gpio[] = {
         }, {
                 .start  = IRQ_MMP2_GPIO,
                 .end    = IRQ_MMP2_GPIO,
+                .name   = "gpio_mux",
                 .flags  = IORESOURCE_IRQ,
         },
 };
diff --git a/arch/arm/mach-mmp/pxa168.c b/arch/arm/mach-mmp/pxa168.c
index ada1213982b..f7d59c03fc6 100644
--- a/arch/arm/mach-mmp/pxa168.c
+++ b/arch/arm/mach-mmp/pxa168.c
@@ -64,6 +64,7 @@ static APBC_CLK(ssp4, PXA168_SSP4, 4, 0);
 static APBC_CLK(ssp5, PXA168_SSP5, 4, 0);
 static APBC_CLK(gpio, PXA168_GPIO, 0, 13000000);
 static APBC_CLK(keypad, PXA168_KPC, 0, 32000);
+static APBC_CLK(rtc, PXA168_RTC, 8, 32768);
 
 static APMU_CLK(nand, NAND, 0x19b, 156000000);
 static APMU_CLK(lcd, LCD, 0x7f, 312000000);
@@ -92,6 +93,7 @@ static struct clk_lookup pxa168_clkregs[] = {
         INIT_CLKREG(&clk_keypad, "pxa27x-keypad", NULL),
         INIT_CLKREG(&clk_eth, "pxa168-eth", "MFUCLK"),
         INIT_CLKREG(&clk_usb, "pxa168-ehci", "PXA168-USBCLK"),
+        INIT_CLKREG(&clk_rtc, "sa1100-rtc", NULL),
 };
 
 static int __init pxa168_init(void)
@@ -166,6 +168,7 @@ struct resource pxa168_resource_gpio[] = {
         }, {
                 .start  = IRQ_PXA168_GPIOX,
                 .end    = IRQ_PXA168_GPIOX,
+                .name   = "gpio_mux",
                 .flags  = IORESOURCE_IRQ,
         },
 };
diff --git a/arch/arm/mach-mmp/pxa910.c b/arch/arm/mach-mmp/pxa910.c
index 3241a25784d..43f8bcc29b6 100644
--- a/arch/arm/mach-mmp/pxa910.c
+++ b/arch/arm/mach-mmp/pxa910.c
@@ -92,6 +92,7 @@ static APBC_CLK(pwm2, PXA910_PWM2, 1, 13000000);
 static APBC_CLK(pwm3, PXA910_PWM3, 1, 13000000);
 static APBC_CLK(pwm4, PXA910_PWM4, 1, 13000000);
 static APBC_CLK(gpio, PXA910_GPIO, 0, 13000000);
+static APBC_CLK(rtc, PXA910_RTC, 8, 32768);
 
 static APMU_CLK(nand, NAND, 0x19b, 156000000);
 static APMU_CLK(u2o, USB, 0x1b, 480000000);
@@ -109,6 +110,7 @@ static struct clk_lookup pxa910_clkregs[] = {
         INIT_CLKREG(&clk_nand, "pxa3xx-nand", NULL),
         INIT_CLKREG(&clk_gpio, "pxa-gpio", NULL),
         INIT_CLKREG(&clk_u2o, "pxa-u2o", "U2OCLK"),
+        INIT_CLKREG(&clk_rtc, "sa1100-rtc", NULL),
 };
 
 static int __init pxa910_init(void)
@@ -173,6 +175,7 @@ struct resource pxa910_resource_gpio[] = {
         }, {
                 .start  = IRQ_PXA910_AP_GPIO,
                 .end    = IRQ_PXA910_AP_GPIO,
+                .name   = "gpio_mux",
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -183,3 +186,28 @@ struct platform_device pxa910_device_gpio = {
         .num_resources  = ARRAY_SIZE(pxa910_resource_gpio),
         .resource       = pxa910_resource_gpio,
 };
+
+static struct resource pxa910_resource_rtc[] = {
+        {
+                .start  = 0xd4010000,
+                .end    = 0xd401003f,
+                .flags  = IORESOURCE_MEM,
+        }, {
+                .start  = IRQ_PXA910_RTC_INT,
+                .end    = IRQ_PXA910_RTC_INT,
+                .name   = "rtc 1Hz",
+                .flags  = IORESOURCE_IRQ,
+        }, {
+                .start  = IRQ_PXA910_RTC_ALARM,
+                .end    = IRQ_PXA910_RTC_ALARM,
+                .name   = "rtc alarm",
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+struct platform_device pxa910_device_rtc = {
+        .name           = "sa1100-rtc",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(pxa910_resource_rtc),
+        .resource       = pxa910_resource_rtc,
+};
diff --git a/arch/arm/mach-mmp/ttc_dkb.c b/arch/arm/mach-mmp/ttc_dkb.c
index 5ac5d5832e4..e72c709da44 100644
--- a/arch/arm/mach-mmp/ttc_dkb.c
+++ b/arch/arm/mach-mmp/ttc_dkb.c
@@ -124,6 +124,7 @@ static struct platform_device ttc_dkb_device_onenand = {
 
 static struct platform_device *ttc_dkb_devices[] = {
         &pxa910_device_gpio,
+        &pxa910_device_rtc,
         &ttc_dkb_device_onenand,
 };
 
diff --git a/arch/arm/mach-msm/idle.S b/arch/arm/mach-msm/idle.S
deleted file mode 100644
index 6a94f052713..00000000000
--- a/arch/arm/mach-msm/idle.S
+++ /dev/null
@@ -1,36 +0,0 @@
-/* arch/arm/mach-msm/include/mach/idle.S
- *
- * Idle processing for MSM7K - work around bugs with SWFI.
- *
- * Copyright (c) 2007 QUALCOMM Incorporated.
- * Copyright (C) 2007 Google, Inc. 
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */ 
-                
-#include <linux/linkage.h>
-#include <asm/assembler.h>
-
-ENTRY(arch_idle)
-#ifdef CONFIG_MSM7X00A_IDLE
-        mrc     p15, 0, r1, c1, c0, 0    /* read current CR    */
-        bic     r0, r1, #(1 << 2)        /* clear dcache bit   */
-        bic     r0, r0, #(1 << 12)       /* clear icache bit   */
-        mcr     p15, 0, r0, c1, c0, 0    /* disable d/i cache  */
-
-        mov     r0, #0                   /* prepare wfi value  */
-        mcr     p15, 0, r0, c7, c10, 0   /* flush the cache    */
-        mcr     p15, 0, r0, c7, c10, 4   /* memory barrier     */
-        mcr     p15, 0, r0, c7, c0, 4    /* wait for interrupt */
-
-        mcr     p15, 0, r1, c1, c0, 0    /* restore d/i cache  */
-#endif
-        mov     pc, lr
diff --git a/arch/arm/mach-msm/idle.c b/arch/arm/mach-msm/idle.c
new file mode 100644
index 00000000000..0c9e13c6574
--- /dev/null
+++ b/arch/arm/mach-msm/idle.c
@@ -0,0 +1,49 @@
+/* arch/arm/mach-msm/idle.c
+ *
+ * Idle processing for MSM7K - work around bugs with SWFI.
+ *
+ * Copyright (c) 2007 QUALCOMM Incorporated.
+ * Copyright (C) 2007 Google, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <linux/init.h>
+#include <asm/system.h>
+
+static void msm_idle(void)
+{
+#ifdef CONFIG_MSM7X00A_IDLE
+        asm volatile (
+
+        "mrc     p15, 0, r1, c1, c0, 0    /* read current CR    */ \n\t"
+        "bic     r0, r1, #(1 << 2)        /* clear dcache bit   */ \n\t"
+        "bic     r0, r0, #(1 << 12)       /* clear icache bit   */ \n\t"
+        "mcr     p15, 0, r0, c1, c0, 0    /* disable d/i cache  */ \n\t"
+
+        "mov     r0, #0                   /* prepare wfi value  */ \n\t"
+        "mcr     p15, 0, r0, c7, c10, 0   /* flush the cache    */ \n\t"
+        "mcr     p15, 0, r0, c7, c10, 4   /* memory barrier     */ \n\t"
+        "mcr     p15, 0, r0, c7, c0, 4    /* wait for interrupt */ \n\t"
+
+        "mcr     p15, 0, r1, c1, c0, 0    /* restore d/i cache  */ \n\t"
+
+        : : : "r0","r1" );
+#endif
+}
+
+static int __init msm_idle_init(void)
+{
+        arm_pm_idle = msm_idle;
+        return 0;
+}
+
+arch_initcall(msm_idle_init);
diff --git a/arch/arm/mach-msm/include/mach/entry-macro.S b/arch/arm/mach-msm/include/mach/entry-macro.S
index 41f7003ef34..f2ae9087f65 100644
--- a/arch/arm/mach-msm/include/mach/entry-macro.S
+++ b/arch/arm/mach-msm/include/mach/entry-macro.S
@@ -16,12 +16,6 @@
  *
  */
 
-        .macro  disable_fiq
-        .endm
-
-        .macro  arch_ret_to_user, tmp1, tmp2
-        .endm
-
 #if !defined(CONFIG_ARM_GIC)
 #include <mach/msm_iomap.h>
 
diff --git a/arch/arm/mach-msm/include/mach/system.h b/arch/arm/mach-msm/include/mach/system.h
index 311db2b35da..f5fb2ec87ff 100644
--- a/arch/arm/mach-msm/include/mach/system.h
+++ b/arch/arm/mach-msm/include/mach/system.h
@@ -12,7 +12,6 @@
  * GNU General Public License for more details.
  *
  */
-void arch_idle(void);
 
 /* low level hardware reset hook -- for example, hitting the
  * PSHOLD line on the PMIC to hard reset the system
diff --git a/arch/arm/mach-msm/timer.c b/arch/arm/mach-msm/timer.c
index 11d0d8f2656..75f4be40b3e 100644
--- a/arch/arm/mach-msm/timer.c
+++ b/arch/arm/mach-msm/timer.c
@@ -127,6 +127,45 @@ static struct clocksource msm_clocksource = {
         .flags  = CLOCK_SOURCE_IS_CONTINUOUS,
 };
 
+#ifdef CONFIG_LOCAL_TIMERS
+static int __cpuinit msm_local_timer_setup(struct clock_event_device *evt)
+{
+        /* Use existing clock_event for cpu 0 */
+        if (!smp_processor_id())
+                return 0;
+
+        writel_relaxed(0, event_base + TIMER_ENABLE);
+        writel_relaxed(0, event_base + TIMER_CLEAR);
+        writel_relaxed(~0, event_base + TIMER_MATCH_VAL);
+        evt->irq = msm_clockevent.irq;
+        evt->name = "local_timer";
+        evt->features = msm_clockevent.features;
+        evt->rating = msm_clockevent.rating;
+        evt->set_mode = msm_timer_set_mode;
+        evt->set_next_event = msm_timer_set_next_event;
+        evt->shift = msm_clockevent.shift;
+        evt->mult = div_sc(GPT_HZ, NSEC_PER_SEC, evt->shift);
+        evt->max_delta_ns = clockevent_delta2ns(0xf0000000, evt);
+        evt->min_delta_ns = clockevent_delta2ns(4, evt);
+
+        *__this_cpu_ptr(msm_evt.percpu_evt) = evt;
+        clockevents_register_device(evt);
+        enable_percpu_irq(evt->irq, 0);
+        return 0;
+}
+
+static void msm_local_timer_stop(struct clock_event_device *evt)
+{
+        evt->set_mode(CLOCK_EVT_MODE_UNUSED, evt);
+        disable_percpu_irq(evt->irq);
+}
+
+static struct local_timer_ops msm_local_timer_ops __cpuinitdata = {
+        .setup  = msm_local_timer_setup,
+        .stop   = msm_local_timer_stop,
+};
+#endif /* CONFIG_LOCAL_TIMERS */
+
 static void __init msm_timer_init(void)
 {
         struct clock_event_device *ce = &msm_clockevent;
@@ -173,8 +212,12 @@ static void __init msm_timer_init(void)
                 *__this_cpu_ptr(msm_evt.percpu_evt) = ce;
                 res = request_percpu_irq(ce->irq, msm_timer_interrupt,
                                          ce->name, msm_evt.percpu_evt);
-                if (!res)
+                if (!res) {
                         enable_percpu_irq(ce->irq, 0);
+#ifdef CONFIG_LOCAL_TIMERS
+                        local_timer_register(&msm_local_timer_ops);
+#endif
+                }
         } else {
                 msm_evt.evt = ce;
                 res = request_irq(ce->irq, msm_timer_interrupt,
@@ -191,40 +234,6 @@ err:
                 pr_err("clocksource_register failed\n");
 }
 
-#ifdef CONFIG_LOCAL_TIMERS
-int __cpuinit local_timer_setup(struct clock_event_device *evt)
-{
-        /* Use existing clock_event for cpu 0 */
-        if (!smp_processor_id())
-                return 0;
-
-        writel_relaxed(0, event_base + TIMER_ENABLE);
-        writel_relaxed(0, event_base + TIMER_CLEAR);
-        writel_relaxed(~0, event_base + TIMER_MATCH_VAL);
-        evt->irq = msm_clockevent.irq;
-        evt->name = "local_timer";
-        evt->features = msm_clockevent.features;
-        evt->rating = msm_clockevent.rating;
-        evt->set_mode = msm_timer_set_mode;
-        evt->set_next_event = msm_timer_set_next_event;
-        evt->shift = msm_clockevent.shift;
-        evt->mult = div_sc(GPT_HZ, NSEC_PER_SEC, evt->shift);
-        evt->max_delta_ns = clockevent_delta2ns(0xf0000000, evt);
-        evt->min_delta_ns = clockevent_delta2ns(4, evt);
-
-        *__this_cpu_ptr(msm_evt.percpu_evt) = evt;
-        clockevents_register_device(evt);
-        enable_percpu_irq(evt->irq, 0);
-        return 0;
-}
-
-void local_timer_stop(struct clock_event_device *evt)
-{
-        evt->set_mode(CLOCK_EVT_MODE_UNUSED, evt);
-        disable_percpu_irq(evt->irq);
-}
-#endif /* CONFIG_LOCAL_TIMERS */
-
 struct sys_timer msm_timer = {
         .init = msm_timer_init
 };
diff --git a/arch/arm/mach-mv78xx0/include/mach/entry-macro.S b/arch/arm/mach-mv78xx0/include/mach/entry-macro.S
index 66ae2d29e77..6b1f088e059 100644
--- a/arch/arm/mach-mv78xx0/include/mach/entry-macro.S
+++ b/arch/arm/mach-mv78xx0/include/mach/entry-macro.S
@@ -10,12 +10,6 @@
 
 #include <mach/bridge-regs.h>
 
-        .macro  disable_fiq
-        .endm
-
-        .macro  arch_ret_to_user, tmp1, tmp2
-        .endm
-
         .macro  get_irqnr_preamble, base, tmp
         ldr     \base, =IRQ_VIRT_BASE
         .endm
diff --git a/arch/arm/mach-mv78xx0/include/mach/system.h b/arch/arm/mach-mv78xx0/include/mach/system.h
deleted file mode 100644
index 8c3a5387cec..00000000000
--- a/arch/arm/mach-mv78xx0/include/mach/system.h
+++ /dev/null
@@ -1,17 +0,0 @@
-/*
- * arch/arm/mach-mv78xx0/include/mach/system.h
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#ifndef __ASM_ARCH_SYSTEM_H
-#define __ASM_ARCH_SYSTEM_H
-
-static inline void arch_idle(void)
-{
-        cpu_do_idle();
-}
-
-#endif
diff --git a/arch/arm/mach-mv78xx0/pcie.c b/arch/arm/mach-mv78xx0/pcie.c
index 8459f6d7d8c..df3e38055a2 100644
--- a/arch/arm/mach-mv78xx0/pcie.c
+++ b/arch/arm/mach-mv78xx0/pcie.c
@@ -155,8 +155,8 @@ static int __init mv78xx0_pcie_setup(int nr, struct pci_sys_data *sys)
         orion_pcie_set_local_bus_nr(pp->base, sys->busnr);
         orion_pcie_setup(pp->base);
 
-        pci_add_resource(&sys->resources, &pp->res[0]);
-        pci_add_resource(&sys->resources, &pp->res[1]);
+        pci_add_resource_offset(&sys->resources, &pp->res[0], sys->io_offset);
+        pci_add_resource_offset(&sys->resources, &pp->res[1], sys->mem_offset);
 
         return 1;
 }
diff --git a/arch/arm/mach-mxs/Kconfig b/arch/arm/mach-mxs/Kconfig
index cf00b3e3be8..c57f9964a71 100644
--- a/arch/arm/mach-mxs/Kconfig
+++ b/arch/arm/mach-mxs/Kconfig
@@ -83,6 +83,18 @@ config MODULE_M28
         select MXS_HAVE_PLATFORM_MXSFB
         select MXS_OCOTP
 
+config MODULE_APX4
+        bool
+        select SOC_IMX28
+        select LEDS_GPIO_REGISTER
+        select MXS_HAVE_AMBA_DUART
+        select MXS_HAVE_PLATFORM_AUART
+        select MXS_HAVE_PLATFORM_FEC
+        select MXS_HAVE_PLATFORM_MXS_I2C
+        select MXS_HAVE_PLATFORM_MXS_MMC
+        select MXS_HAVE_PLATFORM_MXS_SAIF
+        select MXS_OCOTP
+
 config MACH_TX28
         bool "Ka-Ro TX28 module"
         select MODULE_TX28
@@ -91,4 +103,8 @@ config MACH_M28EVK
         bool "Support DENX M28EVK Platform"
         select MODULE_M28
 
+config MACH_APX4DEVKIT
+        bool "Support Bluegiga APX4 Development Kit"
+        select MODULE_APX4
+
 endif
diff --git a/arch/arm/mach-mxs/Makefile b/arch/arm/mach-mxs/Makefile
index 8c93b24896b..908bf9a567f 100644
--- a/arch/arm/mach-mxs/Makefile
+++ b/arch/arm/mach-mxs/Makefile
@@ -11,6 +11,7 @@ obj-$(CONFIG_MACH_STMP378X_DEVB) += mach-stmp378x_devb.o
 obj-$(CONFIG_MACH_MX23EVK) += mach-mx23evk.o
 obj-$(CONFIG_MACH_MX28EVK) += mach-mx28evk.o
 obj-$(CONFIG_MACH_M28EVK)    += mach-m28evk.o
+obj-$(CONFIG_MACH_APX4DEVKIT) += mach-apx4devkit.o
 obj-$(CONFIG_MODULE_TX28) += module-tx28.o
 obj-$(CONFIG_MACH_TX28)    += mach-tx28.o
 
diff --git a/arch/arm/mach-mxs/clock-mx23.c b/arch/arm/mach-mxs/clock-mx23.c
index e12e11231dc..e3ac52c3401 100644
--- a/arch/arm/mach-mxs/clock-mx23.c
+++ b/arch/arm/mach-mxs/clock-mx23.c
@@ -223,7 +223,6 @@ static int cpu_clk_set_rate(struct clk *clk, unsigned long rate)
 {
         u32 reg, bm_busy, div_max, d, f, div, frac;
         unsigned long diff, parent_rate, calc_rate;
-        int i;
 
         parent_rate = clk_get_rate(clk->parent);
 
@@ -275,14 +274,7 @@ static int cpu_clk_set_rate(struct clk *clk, unsigned long rate)
         reg |= div << BP_CLKCTRL_CPU_DIV_CPU;
         __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_CPU);
 
-        for (i = 10000; i; i--)
-                if (!(__raw_readl(CLKCTRL_BASE_ADDR +
-                                        HW_CLKCTRL_CPU) & bm_busy))
-                        break;
-        if (!i) {
-                pr_err("%s: divider writing timeout\n", __func__);
-                return -ETIMEDOUT;
-        }
+        mxs_clkctrl_timeout(HW_CLKCTRL_CPU, bm_busy);
 
         return 0;
 }
@@ -292,7 +284,6 @@ static int name##_set_rate(struct clk *clk, unsigned long rate)		\
 {                                                                       \
         u32 reg, div_max, div;                                          \
         unsigned long parent_rate;                                      \
-        int i;                                                          \
                                                                         \
         parent_rate = clk_get_rate(clk->parent);                        \
         div_max = BM_CLKCTRL_##dr##_DIV >> BP_CLKCTRL_##dr##_DIV;       \
@@ -310,15 +301,7 @@ static int name##_set_rate(struct clk *clk, unsigned long rate)		\
         }                                                               \
         __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_##dr);         \
                                                                         \
-        for (i = 10000; i; i--)                                         \
-                if (!(__raw_readl(CLKCTRL_BASE_ADDR +                   \
-                        HW_CLKCTRL_##dr) & BM_CLKCTRL_##dr##_BUSY))     \
-                        break;                                          \
-        if (!i) {                                                       \
-                pr_err("%s: divider writing timeout\n", __func__);      \
-                return -ETIMEDOUT;                                      \
-        }                                                               \
-                                                                        \
+        mxs_clkctrl_timeout(HW_CLKCTRL_##dr, BM_CLKCTRL_##dr##_BUSY);   \
         return 0;                                                       \
 }
 
@@ -456,12 +439,13 @@ static struct clk_lookup lookups[] = {
         _REGISTER_CLOCK("mxs-pwm.3", NULL, pwm_clk)
         _REGISTER_CLOCK("mxs-pwm.4", NULL, pwm_clk)
         _REGISTER_CLOCK("imx23-fb", NULL, lcdif_clk)
+        _REGISTER_CLOCK("imx23-gpmi-nand", NULL, gpmi_clk)
 };
 
 static int clk_misc_init(void)
 {
         u32 reg;
-        int i;
+        int ret;
 
         /* Fix up parent per register setting */
         reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_CLKSEQ);
@@ -510,14 +494,7 @@ static int clk_misc_init(void)
         reg |= 3 << BP_CLKCTRL_HBUS_DIV;
         __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_HBUS);
 
-        for (i = 10000; i; i--)
-                if (!(__raw_readl(CLKCTRL_BASE_ADDR +
-                        HW_CLKCTRL_HBUS) & BM_CLKCTRL_HBUS_BUSY))
-                        break;
-        if (!i) {
-                pr_err("%s: divider writing timeout\n", __func__);
-                return -ETIMEDOUT;
-        }
+        ret = mxs_clkctrl_timeout(HW_CLKCTRL_HBUS, BM_CLKCTRL_HBUS_BUSY);
 
         /* Gate off cpu clock in WFI for power saving */
         __raw_writel(BM_CLKCTRL_CPU_INTERRUPT_WAIT,
@@ -532,7 +509,7 @@ static int clk_misc_init(void)
         reg |= 30 << BP_CLKCTRL_FRAC_IOFRAC;
         __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC);
 
-        return 0;
+        return ret;
 }
 
 int __init mx23_clocks_init(void)
diff --git a/arch/arm/mach-mxs/clock-mx28.c b/arch/arm/mach-mxs/clock-mx28.c
index 5d68e415222..cea29c99e21 100644
--- a/arch/arm/mach-mxs/clock-mx28.c
+++ b/arch/arm/mach-mxs/clock-mx28.c
@@ -322,7 +322,6 @@ static int name##_set_rate(struct clk *clk, unsigned long rate)		\
 {                                                                       \
         u32 reg, bm_busy, div_max, d, f, div, frac;                     \
         unsigned long diff, parent_rate, calc_rate;                     \
-        int i;                                                          \
                                                                         \
         div_max = BM_CLKCTRL_##dr##_DIV >> BP_CLKCTRL_##dr##_DIV;       \
         bm_busy = BM_CLKCTRL_##dr##_BUSY;                               \
@@ -396,16 +395,7 @@ static int name##_set_rate(struct clk *clk, unsigned long rate)		\
         }                                                               \
         __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_##dr);         \
                                                                         \
-        for (i = 10000; i; i--)                                         \
-                if (!(__raw_readl(CLKCTRL_BASE_ADDR +                   \
-                        HW_CLKCTRL_##dr) & bm_busy))                    \
-                        break;                                          \
-        if (!i) {                                                       \
-                pr_err("%s: divider writing timeout\n", __func__);      \
-                return -ETIMEDOUT;                                      \
-        }                                                               \
-                                                                        \
-        return 0;                                                       \
+        return mxs_clkctrl_timeout(HW_CLKCTRL_##dr, bm_busy);           \
 }
 
 _CLK_SET_RATE(cpu_clk, CPU, FRAC0, CPU)
@@ -421,7 +411,6 @@ static int name##_set_rate(struct clk *clk, unsigned long rate)		\
 {                                                                       \
         u32 reg, div_max, div;                                          \
         unsigned long parent_rate;                                      \
-        int i;                                                          \
                                                                         \
         parent_rate = clk_get_rate(clk->parent);                        \
         div_max = BM_CLKCTRL_##dr##_DIV >> BP_CLKCTRL_##dr##_DIV;       \
@@ -439,16 +428,7 @@ static int name##_set_rate(struct clk *clk, unsigned long rate)		\
         }                                                               \
         __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_##dr);         \
                                                                         \
-        for (i = 10000; i; i--)                                         \
-                if (!(__raw_readl(CLKCTRL_BASE_ADDR +                   \
-                        HW_CLKCTRL_##dr) & BM_CLKCTRL_##dr##_BUSY))     \
-                        break;                                          \
-        if (!i) {                                                       \
-                pr_err("%s: divider writing timeout\n", __func__);      \
-                return -ETIMEDOUT;                                      \
-        }                                                               \
-                                                                        \
-        return 0;                                                       \
+        return mxs_clkctrl_timeout(HW_CLKCTRL_##dr, BM_CLKCTRL_##dr##_BUSY);\
 }
 
 _CLK_SET_RATE1(xbus_clk, XBUS)
@@ -461,7 +441,6 @@ static int name##_set_rate(struct clk *clk, unsigned long rate)		\
         u32 reg;                                                        \
         u64 lrate;                                                      \
         unsigned long parent_rate;                                      \
-        int i;                                                          \
                                                                         \
         parent_rate = clk_get_rate(clk->parent);                        \
         if (rate > parent_rate)                                         \
@@ -477,18 +456,13 @@ static int name##_set_rate(struct clk *clk, unsigned long rate)		\
         reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_##rs);         \
         reg &= ~BM_CLKCTRL_##rs##_DIV;                                  \
         reg |= div << BP_CLKCTRL_##rs##_DIV;                            \
-        __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_##rs);         \
-                                                                        \
-        for (i = 10000; i; i--)                                         \
-                if (!(__raw_readl(CLKCTRL_BASE_ADDR +                   \
-                        HW_CLKCTRL_##rs) & BM_CLKCTRL_##rs##_BUSY))     \
-                        break;                                          \
-        if (!i) {                                                       \
-                pr_err("%s: divider writing timeout\n", __func__);      \
-                return -ETIMEDOUT;                                      \
+        if (reg & (1 << clk->enable_shift)) {                           \
+                pr_err("%s: clock is gated\n", __func__);               \
+                return -EINVAL;                                         \
         }                                                               \
+        __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_##rs);         \
                                                                         \
-        return 0;                                                       \
+        return mxs_clkctrl_timeout(HW_CLKCTRL_##rs, BM_CLKCTRL_##rs##_BUSY);\
 }
 
 _CLK_SET_RATE_SAIF(saif0_clk, SAIF0)
@@ -643,6 +617,7 @@ static struct clk_lookup lookups[] = {
         _REGISTER_CLOCK("duart", NULL, uart_clk)
         _REGISTER_CLOCK("imx28-fec.0", NULL, fec_clk)
         _REGISTER_CLOCK("imx28-fec.1", NULL, fec_clk)
+        _REGISTER_CLOCK("imx28-gpmi-nand", NULL, gpmi_clk)
         _REGISTER_CLOCK("mxs-auart.0", NULL, uart_clk)
         _REGISTER_CLOCK("mxs-auart.1", NULL, uart_clk)
         _REGISTER_CLOCK("mxs-auart.2", NULL, uart_clk)
@@ -654,6 +629,8 @@ static struct clk_lookup lookups[] = {
         _REGISTER_CLOCK("mxs-dma-apbx", NULL, xbus_clk)
         _REGISTER_CLOCK("mxs-mmc.0", NULL, ssp0_clk)
         _REGISTER_CLOCK("mxs-mmc.1", NULL, ssp1_clk)
+        _REGISTER_CLOCK("mxs-mmc.2", NULL, ssp2_clk)
+        _REGISTER_CLOCK("mxs-mmc.3", NULL, ssp3_clk)
         _REGISTER_CLOCK("flexcan.0", NULL, can0_clk)
         _REGISTER_CLOCK("flexcan.1", NULL, can1_clk)
         _REGISTER_CLOCK(NULL, "usb0", usb0_clk)
@@ -676,7 +653,7 @@ static struct clk_lookup lookups[] = {
 static int clk_misc_init(void)
 {
         u32 reg;
-        int i;
+        int ret;
 
         /* Fix up parent per register setting */
         reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_CLKSEQ);
@@ -756,14 +733,7 @@ static int clk_misc_init(void)
         reg |= 3 << BP_CLKCTRL_HBUS_DIV;
         __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_HBUS);
 
-        for (i = 10000; i; i--)
-                if (!(__raw_readl(CLKCTRL_BASE_ADDR +
-                        HW_CLKCTRL_HBUS) & BM_CLKCTRL_HBUS_ASM_BUSY))
-                        break;
-        if (!i) {
-                pr_err("%s: divider writing timeout\n", __func__);
-                return -ETIMEDOUT;
-        }
+        ret = mxs_clkctrl_timeout(HW_CLKCTRL_HBUS, BM_CLKCTRL_HBUS_ASM_BUSY);
 
         /* Gate off cpu clock in WFI for power saving */
         __raw_writel(BM_CLKCTRL_CPU_INTERRUPT_WAIT,
@@ -790,7 +760,7 @@ static int clk_misc_init(void)
         reg |= 30 << BP_CLKCTRL_FRAC0_IO0FRAC;
         __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC0);
 
-        return 0;
+        return ret;
 }
 
 int __init mx28_clocks_init(void)
@@ -803,6 +773,8 @@ int __init mx28_clocks_init(void)
          */
         clk_set_parent(&ssp0_clk, &ref_io0_clk);
         clk_set_parent(&ssp1_clk, &ref_io0_clk);
+        clk_set_parent(&ssp2_clk, &ref_io1_clk);
+        clk_set_parent(&ssp3_clk, &ref_io1_clk);
 
         clk_prepare_enable(&cpu_clk);
         clk_prepare_enable(&hbus_clk);
diff --git a/arch/arm/mach-mxs/devices-mx23.h b/arch/arm/mach-mxs/devices-mx23.h
index 3fa651d2c99..4d1329d5928 100644
--- a/arch/arm/mach-mxs/devices-mx23.h
+++ b/arch/arm/mach-mxs/devices-mx23.h
@@ -21,6 +21,10 @@ extern const struct mxs_auart_data mx23_auart_data[] __initconst;
 #define mx23_add_auart0()               mx23_add_auart(0)
 #define mx23_add_auart1()               mx23_add_auart(1)
 
+extern const struct mxs_gpmi_nand_data mx23_gpmi_nand_data __initconst;
+#define mx23_add_gpmi_nand(pdata)       \
+        mxs_add_gpmi_nand(pdata, &mx23_gpmi_nand_data)
+
 extern const struct mxs_mxs_mmc_data mx23_mxs_mmc_data[] __initconst;
 #define mx23_add_mxs_mmc(id, pdata) \
         mxs_add_mxs_mmc(&mx23_mxs_mmc_data[id], pdata)
diff --git a/arch/arm/mach-mxs/devices-mx28.h b/arch/arm/mach-mxs/devices-mx28.h
index 4f50094e293..9dbeae13084 100644
--- a/arch/arm/mach-mxs/devices-mx28.h
+++ b/arch/arm/mach-mxs/devices-mx28.h
@@ -34,6 +34,10 @@ extern const struct mxs_flexcan_data mx28_flexcan_data[] __initconst;
 #define mx28_add_flexcan0(pdata)        mx28_add_flexcan(0, pdata)
 #define mx28_add_flexcan1(pdata)        mx28_add_flexcan(1, pdata)
 
+extern const struct mxs_gpmi_nand_data mx28_gpmi_nand_data __initconst;
+#define mx28_add_gpmi_nand(pdata)       \
+        mxs_add_gpmi_nand(pdata, &mx28_gpmi_nand_data)
+
 extern const struct mxs_mxs_i2c_data mx28_mxs_i2c_data[] __initconst;
 #define mx28_add_mxs_i2c(id)            mxs_add_mxs_i2c(&mx28_mxs_i2c_data[id])
 
diff --git a/arch/arm/mach-mxs/devices.c b/arch/arm/mach-mxs/devices.c
index fe3e847930c..01faffec306 100644
--- a/arch/arm/mach-mxs/devices.c
+++ b/arch/arm/mach-mxs/devices.c
@@ -77,16 +77,18 @@ err:
 
 int __init mxs_add_amba_device(const struct amba_device *dev)
 {
-        struct amba_device *adev = kmalloc(sizeof(*adev), GFP_KERNEL);
+        struct amba_device *adev = amba_device_alloc(dev->dev.init_name,
+                dev->res.start, resource_size(&dev->res));
 
         if (!adev) {
                 pr_err("%s: failed to allocate memory", __func__);
                 return -ENOMEM;
         }
 
-        *adev = *dev;
+        adev->irq[0] = dev->irq[0];
+        adev->irq[1] = dev->irq[1];
 
-        return amba_device_register(adev, &iomem_resource);
+        return amba_device_add(adev, &iomem_resource);
 }
 
 struct device mxs_apbh_bus = {
diff --git a/arch/arm/mach-mxs/devices/Kconfig b/arch/arm/mach-mxs/devices/Kconfig
index 18b6bf526a2..b8913df4cfa 100644
--- a/arch/arm/mach-mxs/devices/Kconfig
+++ b/arch/arm/mach-mxs/devices/Kconfig
@@ -12,6 +12,9 @@ config MXS_HAVE_PLATFORM_FLEXCAN
         select HAVE_CAN_FLEXCAN if CAN
         bool
 
+config MXS_HAVE_PLATFORM_GPMI_NAND
+        bool
+
 config MXS_HAVE_PLATFORM_MXS_I2C
         bool
 
diff --git a/arch/arm/mach-mxs/devices/Makefile b/arch/arm/mach-mxs/devices/Makefile
index f52e3e53bae..c8f5c9541a3 100644
--- a/arch/arm/mach-mxs/devices/Makefile
+++ b/arch/arm/mach-mxs/devices/Makefile
@@ -3,6 +3,7 @@ obj-$(CONFIG_MXS_HAVE_PLATFORM_AUART) += platform-auart.o
 obj-y += platform-dma.o
 obj-$(CONFIG_MXS_HAVE_PLATFORM_FEC) += platform-fec.o
 obj-$(CONFIG_MXS_HAVE_PLATFORM_FLEXCAN) += platform-flexcan.o
+obj-$(CONFIG_MXS_HAVE_PLATFORM_GPMI_NAND) += platform-gpmi-nand.o
 obj-$(CONFIG_MXS_HAVE_PLATFORM_MXS_I2C) += platform-mxs-i2c.o
 obj-$(CONFIG_MXS_HAVE_PLATFORM_MXS_MMC) += platform-mxs-mmc.o
 obj-$(CONFIG_MXS_HAVE_PLATFORM_MXS_PWM) += platform-mxs-pwm.o
diff --git a/arch/arm/mach-mxs/devices/amba-duart.c b/arch/arm/mach-mxs/devices/amba-duart.c
index a559db09b49..a5479f76604 100644
--- a/arch/arm/mach-mxs/devices/amba-duart.c
+++ b/arch/arm/mach-mxs/devices/amba-duart.c
@@ -23,7 +23,7 @@ const struct amba_device name##_device __initconst = {		\
                 .end = (soc ## _DUART_BASE_ADDR) + SZ_8K - 1,   \
                 .flags = IORESOURCE_MEM,                        \
         },                                                      \
-        .irq = {soc ## _INT_DUART, NO_IRQ},                     \
+        .irq = {soc ## _INT_DUART},                             \
 }
 
 #ifdef CONFIG_SOC_IMX23
diff --git a/arch/arm/mach-mxs/devices/platform-gpmi-nand.c b/arch/arm/mach-mxs/devices/platform-gpmi-nand.c
new file mode 100644
index 00000000000..3e22df5944a
--- /dev/null
+++ b/arch/arm/mach-mxs/devices/platform-gpmi-nand.c
@@ -0,0 +1,81 @@
+/*
+ * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+#include <asm/sizes.h>
+#include <mach/mx23.h>
+#include <mach/mx28.h>
+#include <mach/devices-common.h>
+#include <linux/dma-mapping.h>
+
+#ifdef CONFIG_SOC_IMX23
+const struct mxs_gpmi_nand_data mx23_gpmi_nand_data __initconst = {
+        .devid = "imx23-gpmi-nand",
+        .res = {
+                /* GPMI */
+                DEFINE_RES_MEM_NAMED(MX23_GPMI_BASE_ADDR, SZ_8K,
+                                        GPMI_NAND_GPMI_REGS_ADDR_RES_NAME),
+                DEFINE_RES_IRQ_NAMED(MX23_INT_GPMI_ATTENTION,
+                                        GPMI_NAND_GPMI_INTERRUPT_RES_NAME),
+                /* BCH */
+                DEFINE_RES_MEM_NAMED(MX23_BCH_BASE_ADDR, SZ_8K,
+                                        GPMI_NAND_BCH_REGS_ADDR_RES_NAME),
+                DEFINE_RES_IRQ_NAMED(MX23_INT_BCH,
+                                        GPMI_NAND_BCH_INTERRUPT_RES_NAME),
+                /* DMA */
+                DEFINE_RES_NAMED(MX23_DMA_GPMI0,
+                                        MX23_DMA_GPMI3 - MX23_DMA_GPMI0 + 1,
+                                        GPMI_NAND_DMA_CHANNELS_RES_NAME,
+                                        IORESOURCE_DMA),
+                DEFINE_RES_IRQ_NAMED(MX23_INT_GPMI_DMA,
+                                        GPMI_NAND_DMA_INTERRUPT_RES_NAME),
+        },
+};
+#endif
+
+#ifdef CONFIG_SOC_IMX28
+const struct mxs_gpmi_nand_data mx28_gpmi_nand_data __initconst = {
+        .devid = "imx28-gpmi-nand",
+        .res = {
+                /* GPMI */
+                DEFINE_RES_MEM_NAMED(MX28_GPMI_BASE_ADDR, SZ_8K,
+                                        GPMI_NAND_GPMI_REGS_ADDR_RES_NAME),
+                DEFINE_RES_IRQ_NAMED(MX28_INT_GPMI,
+                                        GPMI_NAND_GPMI_INTERRUPT_RES_NAME),
+                /* BCH */
+                DEFINE_RES_MEM_NAMED(MX28_BCH_BASE_ADDR, SZ_8K,
+                                        GPMI_NAND_BCH_REGS_ADDR_RES_NAME),
+                DEFINE_RES_IRQ_NAMED(MX28_INT_BCH,
+                                        GPMI_NAND_BCH_INTERRUPT_RES_NAME),
+                /* DMA */
+                DEFINE_RES_NAMED(MX28_DMA_GPMI0,
+                                        MX28_DMA_GPMI7 - MX28_DMA_GPMI0 + 1,
+                                        GPMI_NAND_DMA_CHANNELS_RES_NAME,
+                                        IORESOURCE_DMA),
+                DEFINE_RES_IRQ_NAMED(MX28_INT_GPMI_DMA,
+                                        GPMI_NAND_DMA_INTERRUPT_RES_NAME),
+        },
+};
+#endif
+
+struct platform_device *__init
+mxs_add_gpmi_nand(const struct gpmi_nand_platform_data *pdata,
+                const struct mxs_gpmi_nand_data *data)
+{
+        return mxs_add_platform_device_dmamask(data->devid, -1,
+                                data->res, GPMI_NAND_RES_SIZE,
+                                pdata, sizeof(*pdata), DMA_BIT_MASK(32));
+}
diff --git a/arch/arm/mach-mxs/devices/platform-mxs-mmc.c b/arch/arm/mach-mxs/devices/platform-mxs-mmc.c
index 382dacbeca2..bef9d923f54 100644
--- a/arch/arm/mach-mxs/devices/platform-mxs-mmc.c
+++ b/arch/arm/mach-mxs/devices/platform-mxs-mmc.c
@@ -41,6 +41,8 @@ const struct mxs_mxs_mmc_data mx23_mxs_mmc_data[] __initconst = {
 const struct mxs_mxs_mmc_data mx28_mxs_mmc_data[] __initconst = {
         mxs_mxs_mmc_data_entry(MX28, 0, 0),
         mxs_mxs_mmc_data_entry(MX28, 1, 1),
+        mxs_mxs_mmc_data_entry(MX28, 2, 2),
+        mxs_mxs_mmc_data_entry(MX28, 3, 3),
 };
 #endif
 
diff --git a/arch/arm/mach-mxs/include/mach/common.h b/arch/arm/mach-mxs/include/mach/common.h
index e1237ab2586..c50c3ea28a9 100644
--- a/arch/arm/mach-mxs/include/mach/common.h
+++ b/arch/arm/mach-mxs/include/mach/common.h
@@ -31,4 +31,6 @@ extern void mx28_init_irq(void);
 
 extern void icoll_init_irq(void);
 
+extern int mxs_clkctrl_timeout(unsigned int reg_offset, unsigned int mask);
+
 #endif /* __MACH_MXS_COMMON_H__ */
diff --git a/arch/arm/mach-mxs/include/mach/devices-common.h b/arch/arm/mach-mxs/include/mach/devices-common.h
index dc369c1239f..f2e383955d8 100644
--- a/arch/arm/mach-mxs/include/mach/devices-common.h
+++ b/arch/arm/mach-mxs/include/mach/devices-common.h
@@ -66,6 +66,16 @@ struct platform_device *__init mxs_add_flexcan(
                 const struct mxs_flexcan_data *data,
                 const struct flexcan_platform_data *pdata);
 
+/* gpmi-nand */
+#include <linux/mtd/gpmi-nand.h>
+struct mxs_gpmi_nand_data {
+        const char *devid;
+        const struct resource res[GPMI_NAND_RES_SIZE];
+};
+struct platform_device *__init
+mxs_add_gpmi_nand(const struct gpmi_nand_platform_data *pdata,
+                const struct mxs_gpmi_nand_data *data);
+
 /* i2c */
 struct mxs_mxs_i2c_data {
         int id;
diff --git a/arch/arm/mach-mxs/include/mach/digctl.h b/arch/arm/mach-mxs/include/mach/digctl.h
index 49a888c65d6..17964066303 100644
--- a/arch/arm/mach-mxs/include/mach/digctl.h
+++ b/arch/arm/mach-mxs/include/mach/digctl.h
@@ -18,4 +18,5 @@
 #define HW_DIGCTL_CTRL                  0x0
 #define  BP_DIGCTL_CTRL_SAIF_CLKMUX     10
 #define  BM_DIGCTL_CTRL_SAIF_CLKMUX     (0x3 << 10)
+#define HW_DIGCTL_CHIPID                0x310
 #endif
diff --git a/arch/arm/mach-mxs/include/mach/entry-macro.S b/arch/arm/mach-mxs/include/mach/entry-macro.S
index 9f0da12e657..0c14259705b 100644
--- a/arch/arm/mach-mxs/include/mach/entry-macro.S
+++ b/arch/arm/mach-mxs/include/mach/entry-macro.S
@@ -23,9 +23,6 @@
 #define MXS_ICOLL_VBASE         MXS_IO_ADDRESS(MXS_ICOLL_BASE_ADDR)
 #define HW_ICOLL_STAT_OFFSET    0x70
 
-        .macro  disable_fiq
-        .endm
-
         .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
         ldr     \irqnr, [\base, #HW_ICOLL_STAT_OFFSET]
         cmp     \irqnr, #0x7F
@@ -36,6 +33,3 @@
         .macro  get_irqnr_preamble, base, tmp
         ldr     \base, =MXS_ICOLL_VBASE
         .endm
-
-        .macro  arch_ret_to_user, tmp1, tmp2
-        .endm
diff --git a/arch/arm/mach-mxs/include/mach/mxs.h b/arch/arm/mach-mxs/include/mach/mxs.h
index bde5f663474..7d4fb6d0afd 100644
--- a/arch/arm/mach-mxs/include/mach/mxs.h
+++ b/arch/arm/mach-mxs/include/mach/mxs.h
@@ -23,22 +23,10 @@
 #include <linux/io.h>
 #endif
 #include <asm/mach-types.h>
+#include <mach/digctl.h>
 #include <mach/hardware.h>
 
 /*
- * MXS CPU types
- */
-#define cpu_is_mx23()           (                                       \
-                machine_is_mx23evk() ||                                 \
-                machine_is_stmp378x() ||                                \
-                0)
-#define cpu_is_mx28()           (                                       \
-                machine_is_mx28evk() ||                                 \
-                machine_is_m28evk() ||                                  \
-                machine_is_tx28() ||                                    \
-                0)
-
-/*
  * IO addresses common to MXS-based
  */
 #define MXS_IO_BASE_ADDR                0x80000000
@@ -109,6 +97,21 @@ static inline void __mxs_togl(u32 mask, void __iomem *reg)
 {
         __raw_writel(mask, reg + MXS_TOG_ADDR);
 }
+
+/*
+ * MXS CPU types
+ */
+#define MXS_CHIPID (MXS_IO_ADDRESS(MXS_DIGCTL_BASE_ADDR) + HW_DIGCTL_CHIPID)
+
+static inline int cpu_is_mx23(void)
+{
+        return ((__raw_readl(MXS_CHIPID) >> 16) == 0x3780);
+}
+
+static inline int cpu_is_mx28(void)
+{
+        return ((__raw_readl(MXS_CHIPID) >> 16) == 0x2800);
+}
 #endif
 
 #endif /* __MACH_MXS_H__ */
diff --git a/arch/arm/mach-mxs/include/mach/system.h b/arch/arm/mach-mxs/include/mach/system.h
deleted file mode 100644
index e7ad1bb2942..00000000000
--- a/arch/arm/mach-mxs/include/mach/system.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- *  Copyright (C) 1999 ARM Limited
- *  Copyright (C) 2000 Deep Blue Solutions Ltd
- *  Copyright 2004-2008 Freescale Semiconductor, Inc. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#ifndef __MACH_MXS_SYSTEM_H__
-#define __MACH_MXS_SYSTEM_H__
-
-static inline void arch_idle(void)
-{
-        cpu_do_idle();
-}
-
-#endif /* __MACH_MXS_SYSTEM_H__ */
diff --git a/arch/arm/mach-mxs/include/mach/uncompress.h b/arch/arm/mach-mxs/include/mach/uncompress.h
index 67776746f14..ef281149544 100644
--- a/arch/arm/mach-mxs/include/mach/uncompress.h
+++ b/arch/arm/mach-mxs/include/mach/uncompress.h
@@ -18,8 +18,6 @@
 #ifndef __MACH_MXS_UNCOMPRESS_H__
 #define __MACH_MXS_UNCOMPRESS_H__
 
-#include <asm/mach-types.h>
-
 unsigned long mxs_duart_base;
 
 #define MXS_DUART(x)    (*(volatile unsigned long *)(mxs_duart_base + (x)))
@@ -55,16 +53,17 @@ static inline void flush(void)
 
 #define MX23_DUART_BASE_ADDR    0x80070000
 #define MX28_DUART_BASE_ADDR    0x80074000
+#define MXS_DIGCTL_CHIPID       0x8001c310
 
 static inline void __arch_decomp_setup(unsigned long arch_id)
 {
-        switch (arch_id) {
-        case MACH_TYPE_MX23EVK:
+        u16 chipid = (*(volatile unsigned long *) MXS_DIGCTL_CHIPID) >> 16;
+
+        switch (chipid) {
+        case 0x3780:
                 mxs_duart_base = MX23_DUART_BASE_ADDR;
                 break;
-        case MACH_TYPE_MX28EVK:
-        case MACH_TYPE_M28EVK:
-        case MACH_TYPE_TX28:
+        case 0x2800:
                 mxs_duart_base = MX28_DUART_BASE_ADDR;
                 break;
         default:
diff --git a/arch/arm/mach-mxs/mach-apx4devkit.c b/arch/arm/mach-mxs/mach-apx4devkit.c
new file mode 100644
index 00000000000..48a7fab571a
--- /dev/null
+++ b/arch/arm/mach-mxs/mach-apx4devkit.c
@@ -0,0 +1,260 @@
+/*
+ * Copyright (C) 2011-2012
+ * Lauri Hintsala, Bluegiga, <lauri.hintsala@bluegiga.com>
+ * Veli-Pekka Peltola, Bluegiga, <veli-pekka.peltola@bluegiga.com>
+ *
+ * based on: mach-mx28evk.c
+ * Copyright 2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/delay.h>
+#include <linux/platform_device.h>
+#include <linux/gpio.h>
+#include <linux/leds.h>
+#include <linux/clk.h>
+#include <linux/i2c.h>
+#include <linux/regulator/machine.h>
+#include <linux/regulator/fixed.h>
+#include <linux/micrel_phy.h>
+
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/time.h>
+
+#include <mach/common.h>
+#include <mach/digctl.h>
+#include <mach/iomux-mx28.h>
+
+#include "devices-mx28.h"
+
+#define APX4DEVKIT_GPIO_USERLED MXS_GPIO_NR(3, 28)
+
+static const iomux_cfg_t apx4devkit_pads[] __initconst = {
+        /* duart */
+        MX28_PAD_PWM0__DUART_RX | MXS_PAD_CTRL,
+        MX28_PAD_PWM1__DUART_TX | MXS_PAD_CTRL,
+
+        /* auart0 */
+        MX28_PAD_AUART0_RX__AUART0_RX | MXS_PAD_CTRL,
+        MX28_PAD_AUART0_TX__AUART0_TX | MXS_PAD_CTRL,
+        MX28_PAD_AUART0_CTS__AUART0_CTS | MXS_PAD_CTRL,
+        MX28_PAD_AUART0_RTS__AUART0_RTS | MXS_PAD_CTRL,
+
+        /* auart1 */
+        MX28_PAD_AUART1_RX__AUART1_RX | MXS_PAD_CTRL,
+        MX28_PAD_AUART1_TX__AUART1_TX | MXS_PAD_CTRL,
+
+        /* auart2 */
+        MX28_PAD_SSP2_SCK__AUART2_RX | MXS_PAD_CTRL,
+        MX28_PAD_SSP2_MOSI__AUART2_TX | MXS_PAD_CTRL,
+
+        /* auart3 */
+        MX28_PAD_SSP2_MISO__AUART3_RX | MXS_PAD_CTRL,
+        MX28_PAD_SSP2_SS0__AUART3_TX | MXS_PAD_CTRL,
+
+#define MXS_PAD_FEC     (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP)
+        /* fec0 */
+        MX28_PAD_ENET0_MDC__ENET0_MDC | MXS_PAD_FEC,
+        MX28_PAD_ENET0_MDIO__ENET0_MDIO | MXS_PAD_FEC,
+        MX28_PAD_ENET0_RX_EN__ENET0_RX_EN | MXS_PAD_FEC,
+        MX28_PAD_ENET0_RXD0__ENET0_RXD0 | MXS_PAD_FEC,
+        MX28_PAD_ENET0_RXD1__ENET0_RXD1 | MXS_PAD_FEC,
+        MX28_PAD_ENET0_TX_EN__ENET0_TX_EN | MXS_PAD_FEC,
+        MX28_PAD_ENET0_TXD0__ENET0_TXD0 | MXS_PAD_FEC,
+        MX28_PAD_ENET0_TXD1__ENET0_TXD1 | MXS_PAD_FEC,
+        MX28_PAD_ENET_CLK__CLKCTRL_ENET | MXS_PAD_FEC,
+
+        /* i2c */
+        MX28_PAD_I2C0_SCL__I2C0_SCL,
+        MX28_PAD_I2C0_SDA__I2C0_SDA,
+
+        /* mmc0 */
+        MX28_PAD_SSP0_DATA0__SSP0_D0 |
+                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
+        MX28_PAD_SSP0_DATA1__SSP0_D1 |
+                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
+        MX28_PAD_SSP0_DATA2__SSP0_D2 |
+                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
+        MX28_PAD_SSP0_DATA3__SSP0_D3 |
+                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
+        MX28_PAD_SSP0_DATA4__SSP0_D4 |
+                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
+        MX28_PAD_SSP0_DATA5__SSP0_D5 |
+                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
+        MX28_PAD_SSP0_DATA6__SSP0_D6 |
+                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
+        MX28_PAD_SSP0_DATA7__SSP0_D7 |
+                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
+        MX28_PAD_SSP0_CMD__SSP0_CMD |
+                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
+        MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT |
+                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
+        MX28_PAD_SSP0_SCK__SSP0_SCK |
+                (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
+
+        /* led */
+        MX28_PAD_PWM3__GPIO_3_28 | MXS_PAD_CTRL,
+
+        /* saif0 & saif1 */
+        MX28_PAD_SAIF0_MCLK__SAIF0_MCLK |
+                (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
+        MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK |
+                (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
+        MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK |
+                (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
+        MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0 |
+                (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
+        MX28_PAD_SAIF1_SDATA0__SAIF1_SDATA0 |
+                (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
+};
+
+/* led */
+static const struct gpio_led apx4devkit_leds[] __initconst = {
+        {
+                .name = "user-led",
+                .default_trigger = "heartbeat",
+                .gpio = APX4DEVKIT_GPIO_USERLED,
+        },
+};
+
+static const struct gpio_led_platform_data apx4devkit_led_data __initconst = {
+        .leds = apx4devkit_leds,
+        .num_leds = ARRAY_SIZE(apx4devkit_leds),
+};
+
+static const struct fec_platform_data mx28_fec_pdata __initconst = {
+        .phy = PHY_INTERFACE_MODE_RMII,
+};
+
+static const struct mxs_mmc_platform_data apx4devkit_mmc_pdata __initconst = {
+        .wp_gpio = -EINVAL,
+        .flags = SLOTF_4_BIT_CAPABLE,
+};
+
+static const struct i2c_board_info apx4devkit_i2c_boardinfo[] __initconst = {
+        { I2C_BOARD_INFO("sgtl5000", 0x0a) }, /* ASoC */
+        { I2C_BOARD_INFO("pcf8563", 0x51) }, /* RTC */
+};
+
+#if defined(CONFIG_REGULATOR_FIXED_VOLTAGE) || \
+                defined(CONFIG_REGULATOR_FIXED_VOLTAGE_MODULE)
+static struct regulator_consumer_supply apx4devkit_audio_consumer_supplies[] = {
+        REGULATOR_SUPPLY("VDDA", "0-000a"),
+        REGULATOR_SUPPLY("VDDIO", "0-000a"),
+};
+
+static struct regulator_init_data apx4devkit_vdd_reg_init_data = {
+        .constraints    = {
+                .name   = "3V3",
+                .always_on = 1,
+        },
+        .consumer_supplies = apx4devkit_audio_consumer_supplies,
+        .num_consumer_supplies = ARRAY_SIZE(apx4devkit_audio_consumer_supplies),
+};
+
+static struct fixed_voltage_config apx4devkit_vdd_pdata = {
+        .supply_name    = "board-3V3",
+        .microvolts     = 3300000,
+        .gpio           = -EINVAL,
+        .enabled_at_boot = 1,
+        .init_data      = &apx4devkit_vdd_reg_init_data,
+};
+
+static struct platform_device apx4devkit_voltage_regulator = {
+        .name           = "reg-fixed-voltage",
+        .id             = -1,
+        .num_resources  = 0,
+        .dev            = {
+                .platform_data  = &apx4devkit_vdd_pdata,
+        },
+};
+
+static void __init apx4devkit_add_regulators(void)
+{
+        platform_device_register(&apx4devkit_voltage_regulator);
+}
+#else
+static void __init apx4devkit_add_regulators(void) {}
+#endif
+
+static const struct mxs_saif_platform_data
+                        apx4devkit_mxs_saif_pdata[] __initconst = {
+        /* working on EXTMSTR0 mode (saif0 master, saif1 slave) */
+        {
+                .master_mode = 1,
+                .master_id = 0,
+        }, {
+                .master_mode = 0,
+                .master_id = 0,
+        },
+};
+
+static int apx4devkit_phy_fixup(struct phy_device *phy)
+{
+        phy->dev_flags |= MICREL_PHY_50MHZ_CLK;
+        return 0;
+}
+
+static void __init apx4devkit_init(void)
+{
+        mxs_iomux_setup_multiple_pads(apx4devkit_pads,
+                        ARRAY_SIZE(apx4devkit_pads));
+
+        mx28_add_duart();
+        mx28_add_auart0();
+        mx28_add_auart1();
+        mx28_add_auart2();
+        mx28_add_auart3();
+
+        /*
+         * Register fixup for the Micrel KS8031 PHY clock
+         * (shares same ID with KS8051)
+         */
+        phy_register_fixup_for_uid(PHY_ID_KS8051, MICREL_PHY_ID_MASK,
+                        apx4devkit_phy_fixup);
+
+        mx28_add_fec(0, &mx28_fec_pdata);
+
+        mx28_add_mxs_mmc(0, &apx4devkit_mmc_pdata);
+
+        gpio_led_register_device(0, &apx4devkit_led_data);
+
+        mxs_saif_clkmux_select(MXS_DIGCTL_SAIF_CLKMUX_EXTMSTR0);
+        mx28_add_saif(0, &apx4devkit_mxs_saif_pdata[0]);
+        mx28_add_saif(1, &apx4devkit_mxs_saif_pdata[1]);
+
+        apx4devkit_add_regulators();
+
+        mx28_add_mxs_i2c(0);
+        i2c_register_board_info(0, apx4devkit_i2c_boardinfo,
+                        ARRAY_SIZE(apx4devkit_i2c_boardinfo));
+
+        mxs_add_platform_device("mxs-sgtl5000", 0, NULL, 0, NULL, 0);
+}
+
+static void __init apx4devkit_timer_init(void)
+{
+        mx28_clocks_init();
+}
+
+static struct sys_timer apx4devkit_timer = {
+        .init   = apx4devkit_timer_init,
+};
+
+MACHINE_START(APX4DEVKIT, "Bluegiga APX4 Development Kit")
+        .map_io         = mx28_map_io,
+        .init_irq       = mx28_init_irq,
+        .timer          = &apx4devkit_timer,
+        .init_machine   = apx4devkit_init,
+        .restart        = mxs_restart,
+MACHINE_END
diff --git a/arch/arm/mach-mxs/mach-m28evk.c b/arch/arm/mach-mxs/mach-m28evk.c
index 2f2758230ed..06d79963611 100644
--- a/arch/arm/mach-mxs/mach-m28evk.c
+++ b/arch/arm/mach-mxs/mach-m28evk.c
@@ -247,18 +247,15 @@ static int __init m28evk_fec_get_mac(void)
         u32 val;
         const u32 *ocotp = mxs_get_ocotp();
 
-        if (!ocotp) {
-                pr_err("%s: timeout when reading fec mac from OCOTP\n",
-                        __func__);
+        if (!ocotp)
                 return -ETIMEDOUT;
-        }
 
         /*
          * OCOTP only stores the last 4 octets for each mac address,
          * so hard-code DENX OUI (C0:E5:4E) here.
          */
         for (i = 0; i < 2; i++) {
-                val = ocotp[i * 4];
+                val = ocotp[i];
                 mx28_fec_pdata[i].mac[0] = 0xC0;
                 mx28_fec_pdata[i].mac[1] = 0xE5;
                 mx28_fec_pdata[i].mac[2] = 0x4E;
diff --git a/arch/arm/mach-mxs/mach-mx28evk.c b/arch/arm/mach-mxs/mach-mx28evk.c
index fdb0a5664dd..e386c142f93 100644
--- a/arch/arm/mach-mxs/mach-mx28evk.c
+++ b/arch/arm/mach-mxs/mach-mx28evk.c
@@ -223,7 +223,6 @@ static const struct gpio_led_platform_data mx28evk_led_data __initconst = {
 /* fec */
 static void __init mx28evk_fec_reset(void)
 {
-        int ret;
         struct clk *clk;
 
         /* Enable fec phy clock */
@@ -231,32 +230,7 @@ static void __init mx28evk_fec_reset(void)
         if (!IS_ERR(clk))
                 clk_prepare_enable(clk);
 
-        /* Power up fec phy */
-        ret = gpio_request(MX28EVK_FEC_PHY_POWER, "fec-phy-power");
-        if (ret) {
-                pr_err("Failed to request gpio fec-phy-%s: %d\n", "power", ret);
-                return;
-        }
-
-        ret = gpio_direction_output(MX28EVK_FEC_PHY_POWER, 0);
-        if (ret) {
-                pr_err("Failed to drive gpio fec-phy-%s: %d\n", "power", ret);
-                return;
-        }
-
-        /* Reset fec phy */
-        ret = gpio_request(MX28EVK_FEC_PHY_RESET, "fec-phy-reset");
-        if (ret) {
-                pr_err("Failed to request gpio fec-phy-%s: %d\n", "reset", ret);
-                return;
-        }
-
-        gpio_direction_output(MX28EVK_FEC_PHY_RESET, 0);
-        if (ret) {
-                pr_err("Failed to drive gpio fec-phy-%s: %d\n", "reset", ret);
-                return;
-        }
-
+        gpio_set_value(MX28EVK_FEC_PHY_RESET, 0);
         mdelay(1);
         gpio_set_value(MX28EVK_FEC_PHY_RESET, 1);
 }
@@ -278,14 +252,14 @@ static int __init mx28evk_fec_get_mac(void)
         const u32 *ocotp = mxs_get_ocotp();
 
         if (!ocotp)
-                goto error;
+                return -ETIMEDOUT;
 
         /*
          * OCOTP only stores the last 4 octets for each mac address,
          * so hard-code Freescale OUI (00:04:9f) here.
          */
         for (i = 0; i < 2; i++) {
-                val = ocotp[i * 4];
+                val = ocotp[i];
                 mx28_fec_pdata[i].mac[0] = 0x00;
                 mx28_fec_pdata[i].mac[1] = 0x04;
                 mx28_fec_pdata[i].mac[2] = 0x9f;
@@ -295,10 +269,6 @@ static int __init mx28evk_fec_get_mac(void)
         }
 
         return 0;
-
-error:
-        pr_err("%s: timeout when reading fec mac from OCOTP\n", __func__);
-        return -ETIMEDOUT;
 }
 
 /*
@@ -417,9 +387,14 @@ static void __init mx28evk_add_regulators(void)
 static void __init mx28evk_add_regulators(void) {}
 #endif
 
-static struct gpio mx28evk_lcd_gpios[] = {
+static const struct gpio mx28evk_gpios[] __initconst = {
         { MX28EVK_LCD_ENABLE, GPIOF_OUT_INIT_HIGH, "lcd-enable" },
         { MX28EVK_BL_ENABLE, GPIOF_OUT_INIT_HIGH, "bl-enable" },
+        { MX28EVK_FLEXCAN_SWITCH, GPIOF_DIR_OUT, "flexcan-switch" },
+        { MX28EVK_MMC0_SLOT_POWER, GPIOF_OUT_INIT_LOW, "mmc0-slot-power" },
+        { MX28EVK_MMC1_SLOT_POWER, GPIOF_OUT_INIT_LOW, "mmc1-slot-power" },
+        { MX28EVK_FEC_PHY_POWER, GPIOF_OUT_INIT_LOW, "fec-phy-power" },
+        { MX28EVK_FEC_PHY_RESET, GPIOF_DIR_OUT, "fec-phy-reset" },
 };
 
 static const struct mxs_saif_platform_data
@@ -447,25 +422,18 @@ static void __init mx28evk_init(void)
         if (mx28evk_fec_get_mac())
                 pr_warn("%s: failed on fec mac setup\n", __func__);
 
+        ret = gpio_request_array(mx28evk_gpios, ARRAY_SIZE(mx28evk_gpios));
+        if (ret)
+                pr_err("One or more GPIOs failed to be requested: %d\n", ret);
+
         mx28evk_fec_reset();
         mx28_add_fec(0, &mx28_fec_pdata[0]);
         mx28_add_fec(1, &mx28_fec_pdata[1]);
 
-        ret = gpio_request_one(MX28EVK_FLEXCAN_SWITCH, GPIOF_DIR_OUT,
-                                "flexcan-switch");
-        if (ret) {
-                pr_err("failed to request gpio flexcan-switch: %d\n", ret);
-        } else {
-                mx28_add_flexcan(0, &mx28evk_flexcan_pdata[0]);
-                mx28_add_flexcan(1, &mx28evk_flexcan_pdata[1]);
-        }
+        mx28_add_flexcan(0, &mx28evk_flexcan_pdata[0]);
+        mx28_add_flexcan(1, &mx28evk_flexcan_pdata[1]);
 
-        ret = gpio_request_array(mx28evk_lcd_gpios,
-                                 ARRAY_SIZE(mx28evk_lcd_gpios));
-        if (ret)
-                pr_warn("failed to request gpio pins for lcd: %d\n", ret);
-        else
-                mx28_add_mxsfb(&mx28evk_mxsfb_pdata);
+        mx28_add_mxsfb(&mx28evk_mxsfb_pdata);
 
         mxs_saif_clkmux_select(MXS_DIGCTL_SAIF_CLKMUX_EXTMSTR0);
         mx28_add_saif(0, &mx28evk_mxs_saif_pdata[0]);
@@ -480,20 +448,8 @@ static void __init mx28evk_init(void)
         mxs_add_platform_device("mxs-sgtl5000", 0, NULL, 0,
                         NULL, 0);
 
-        /* power on mmc slot by writing 0 to the gpio */
-        ret = gpio_request_one(MX28EVK_MMC0_SLOT_POWER, GPIOF_OUT_INIT_LOW,
-                               "mmc0-slot-power");
-        if (ret)
-                pr_warn("failed to request gpio mmc0-slot-power: %d\n", ret);
-        else
-                mx28_add_mxs_mmc(0, &mx28evk_mmc_pdata[0]);
-
-        ret = gpio_request_one(MX28EVK_MMC1_SLOT_POWER, GPIOF_OUT_INIT_LOW,
-                               "mmc1-slot-power");
-        if (ret)
-                pr_warn("failed to request gpio mmc1-slot-power: %d\n", ret);
-        else
-                mx28_add_mxs_mmc(1, &mx28evk_mmc_pdata[1]);
+        mx28_add_mxs_mmc(0, &mx28evk_mmc_pdata[0]);
+        mx28_add_mxs_mmc(1, &mx28evk_mmc_pdata[1]);
 
         mx28_add_rtc_stmp3xxx();
 
diff --git a/arch/arm/mach-mxs/pm.c b/arch/arm/mach-mxs/pm.c
index fb042da29bd..a9b4bbcdafb 100644
--- a/arch/arm/mach-mxs/pm.c
+++ b/arch/arm/mach-mxs/pm.c
@@ -15,13 +15,12 @@
 #include <linux/kernel.h>
 #include <linux/suspend.h>
 #include <linux/io.h>
-#include <mach/system.h>
 
 static int mxs_suspend_enter(suspend_state_t state)
 {
         switch (state) {
         case PM_SUSPEND_MEM:
-                arch_idle();
+                cpu_do_idle();
                 break;
 
         default:
diff --git a/arch/arm/mach-mxs/system.c b/arch/arm/mach-mxs/system.c
index 54f91ad1c96..7aa5ac5d78b 100644
--- a/arch/arm/mach-mxs/system.c
+++ b/arch/arm/mach-mxs/system.c
@@ -37,6 +37,8 @@
 #define MXS_MODULE_CLKGATE              (1 << 30)
 #define MXS_MODULE_SFTRST               (1 << 31)
 
+#define CLKCTRL_TIMEOUT         10      /* 10 ms */
+
 static void __iomem *mxs_clkctrl_reset_addr;
 
 /*
@@ -137,3 +139,17 @@ error:
         return -ETIMEDOUT;
 }
 EXPORT_SYMBOL(mxs_reset_block);
+
+int mxs_clkctrl_timeout(unsigned int reg_offset, unsigned int mask)
+{
+        unsigned long timeout = jiffies + msecs_to_jiffies(CLKCTRL_TIMEOUT);
+        while (readl_relaxed(MXS_IO_ADDRESS(MXS_CLKCTRL_BASE_ADDR)
+                                                + reg_offset) & mask) {
+                if (time_after(jiffies, timeout)) {
+                        pr_err("Timeout at CLKCTRL + 0x%x\n", reg_offset);
+                        return -ETIMEDOUT;
+                }
+        }
+
+        return 0;
+}
diff --git a/arch/arm/mach-netx/fb.c b/arch/arm/mach-netx/fb.c
index b9913234bbf..2cdf6ef69be 100644
--- a/arch/arm/mach-netx/fb.c
+++ b/arch/arm/mach-netx/fb.c
@@ -92,18 +92,7 @@ void clk_put(struct clk *clk)
 {
 }
 
-static struct amba_device fb_device = {
-        .dev            = {
-                .init_name = "fb",
-                .coherent_dma_mask = ~0,
-        },
-        .res            = {
-                .start  = 0x00104000,
-                .end    = 0x00104fff,
-                .flags  = IORESOURCE_MEM,
-        },
-        .irq            = { NETX_IRQ_LCD, NO_IRQ },
-};
+static AMBA_AHB_DEVICE(fb, "fb", 0, 0x00104000, { NETX_IRQ_LCD }, NULL);
 
 int netx_fb_init(struct clcd_board *board, struct clcd_panel *panel)
 {
diff --git a/arch/arm/mach-netx/include/mach/entry-macro.S b/arch/arm/mach-netx/include/mach/entry-macro.S
deleted file mode 100644
index 6e9f1cbe163..00000000000
--- a/arch/arm/mach-netx/include/mach/entry-macro.S
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * arch/arm/mach-netx/include/mach/entry-macro.S
- *
- * Low-level IRQ helper macros for Hilscher netX based platforms
- *
- * Copyright (C) 2005 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2
- * as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-
-                .macro  disable_fiq
-                .endm
-
-                .macro  arch_ret_to_user, tmp1, tmp2
-                .endm
diff --git a/arch/arm/mach-netx/include/mach/system.h b/arch/arm/mach-netx/include/mach/system.h
deleted file mode 100644
index b38fa36d58c..00000000000
--- a/arch/arm/mach-netx/include/mach/system.h
+++ /dev/null
@@ -1,28 +0,0 @@
-/*
- * arch/arm/mach-netx/include/mach/system.h
- *
- * Copyright (C) 2005 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2
- * as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#ifndef __ASM_ARCH_SYSTEM_H
-#define __ASM_ARCH_SYSTEM_H
-
-static inline void arch_idle(void)
-{
-        cpu_do_idle();
-}
-
-#endif
-
diff --git a/arch/arm/mach-nomadik/board-nhk8815.c b/arch/arm/mach-nomadik/board-nhk8815.c
index 7c878bf0034..58cacafcf66 100644
--- a/arch/arm/mach-nomadik/board-nhk8815.c
+++ b/arch/arm/mach-nomadik/board-nhk8815.c
@@ -27,11 +27,11 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/irq.h>
 #include <asm/mach/flash.h>
+#include <asm/mach/time.h>
 
 #include <plat/gpio-nomadik.h>
 #include <plat/mtu.h>
 
-#include <mach/setup.h>
 #include <mach/nand.h>
 #include <mach/fsmc.h>
 
@@ -185,20 +185,11 @@ static void __init nhk8815_onenand_init(void)
 #endif
 }
 
-#define __MEM_4K_RESOURCE(x) \
-        .res = {.start = (x), .end = (x) + SZ_4K - 1, .flags = IORESOURCE_MEM}
+static AMBA_APB_DEVICE(uart0, "uart0", 0, NOMADIK_UART0_BASE,
+        { IRQ_UART0 }, NULL);
 
-static struct amba_device uart0_device = {
-        .dev = { .init_name = "uart0" },
-        __MEM_4K_RESOURCE(NOMADIK_UART0_BASE),
-        .irq = {IRQ_UART0, NO_IRQ},
-};
-
-static struct amba_device uart1_device = {
-        .dev = { .init_name = "uart1" },
-        __MEM_4K_RESOURCE(NOMADIK_UART1_BASE),
-        .irq = {IRQ_UART1, NO_IRQ},
-};
+static AMBA_APB_DEVICE(uart1, "uart1", 0, NOMADIK_UART1_BASE,
+        { IRQ_UART1 }, NULL);
 
 static struct amba_device *amba_devs[] __initdata = {
         &uart0_device,
@@ -255,10 +246,7 @@ static void __init nomadik_timer_init(void)
         src_cr |= SRC_CR_INIT_VAL;
         writel(src_cr, io_p2v(NOMADIK_SRC_BASE));
 
-        /* Save global pointer to mtu, used by platform timer code */
-        mtu_base = io_p2v(NOMADIK_MTU0_BASE);
-
-        nmdk_timer_init();
+        nmdk_timer_init(io_p2v(NOMADIK_MTU0_BASE));
 }
 
 static struct sys_timer nomadik_timer = {
diff --git a/arch/arm/mach-nomadik/cpu-8815.c b/arch/arm/mach-nomadik/cpu-8815.c
index 65df7b4fdd3..27f43a46985 100644
--- a/arch/arm/mach-nomadik/cpu-8815.c
+++ b/arch/arm/mach-nomadik/cpu-8815.c
@@ -97,12 +97,7 @@ static struct platform_device cpu8815_platform_gpio[] = {
         GPIO_DEVICE(3),
 };
 
-static struct amba_device cpu8815_amba_rng = {
-        .dev = {
-                .init_name = "rng",
-        },
-        __MEM_4K_RESOURCE(NOMADIK_RNG_BASE),
-};
+static AMBA_APB_DEVICE(cpu8815_amba_rng, "rng", 0, NOMADIK_RNG_BASE, { }, NULL);
 
 static struct platform_device *platform_devs[] __initdata = {
         cpu8815_platform_gpio + 0,
@@ -112,7 +107,7 @@ static struct platform_device *platform_devs[] __initdata = {
 };
 
 static struct amba_device *amba_devs[] __initdata = {
-        &cpu8815_amba_rng
+        &cpu8815_amba_rng_device
 };
 
 static int __init cpu8815_init(void)
diff --git a/arch/arm/mach-nomadik/include/mach/entry-macro.S b/arch/arm/mach-nomadik/include/mach/entry-macro.S
deleted file mode 100644
index 98ea1c1fbba..00000000000
--- a/arch/arm/mach-nomadik/include/mach/entry-macro.S
+++ /dev/null
@@ -1,13 +0,0 @@
-/*
- * Low-level IRQ helper macros for Nomadik platforms
- *
- * This file is licensed under  the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-        .macro  disable_fiq
-        .endm
-
-        .macro  arch_ret_to_user, tmp1, tmp2
-        .endm
diff --git a/arch/arm/mach-nomadik/include/mach/setup.h b/arch/arm/mach-nomadik/include/mach/setup.h
deleted file mode 100644
index bcaeaf41c05..00000000000
--- a/arch/arm/mach-nomadik/include/mach/setup.h
+++ /dev/null
@@ -1,19 +0,0 @@
-
-/*
- * These symbols are needed for board-specific files to call their
- * own cpu-specific files
- */
-
-#ifndef __ASM_ARCH_SETUP_H
-#define __ASM_ARCH_SETUP_H
-
-#include <asm/mach/time.h>
-#include <linux/init.h>
-
-#ifdef CONFIG_NOMADIK_8815
-
-extern void nmdk_timer_init(void);
-
-#endif /* NOMADIK_8815 */
-
-#endif /*  __ASM_ARCH_SETUP_H */
diff --git a/arch/arm/mach-nomadik/include/mach/system.h b/arch/arm/mach-nomadik/include/mach/system.h
deleted file mode 100644
index 25e198b8976..00000000000
--- a/arch/arm/mach-nomadik/include/mach/system.h
+++ /dev/null
@@ -1,32 +0,0 @@
-/*
- *  mach-nomadik/include/mach/system.h
- *
- *  Copyright (C) 2008 STMicroelectronics
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#ifndef __ASM_ARCH_SYSTEM_H
-#define __ASM_ARCH_SYSTEM_H
-
-static inline void arch_idle(void)
-{
-        /*
-         * This should do all the clock switching
-         * and wait for interrupt tricks
-         */
-        cpu_do_idle();
-}
-
-#endif
diff --git a/arch/arm/mach-omap1/Kconfig b/arch/arm/mach-omap1/Kconfig
index 4f8d66f044e..dfab466ebd1 100644
--- a/arch/arm/mach-omap1/Kconfig
+++ b/arch/arm/mach-omap1/Kconfig
@@ -37,7 +37,6 @@ comment "OMAP Board Type"
 config MACH_OMAP_INNOVATOR
         bool "TI Innovator"
         depends on ARCH_OMAP1 && (ARCH_OMAP15XX || ARCH_OMAP16XX)
-        select OMAP_MCBSP
         help
           TI OMAP 1510 or 1610 Innovator board support. Say Y here if you
           have such a board.
@@ -45,7 +44,6 @@ config MACH_OMAP_INNOVATOR
 config MACH_OMAP_H2
         bool "TI H2 Support"
         depends on ARCH_OMAP1 && ARCH_OMAP16XX
-        select OMAP_MCBSP
         help
           TI OMAP 1610/1611B H2 board support. Say Y here if you have such
           a board.
@@ -72,7 +70,6 @@ config MACH_HERALD
 config MACH_OMAP_OSK
         bool "TI OSK Support"
         depends on ARCH_OMAP1 && ARCH_OMAP16XX
-        select OMAP_MCBSP
         help
           TI OMAP 5912 OSK (OMAP Starter Kit) board support. Say Y here
           if you have such a board.
@@ -155,6 +152,10 @@ config MACH_AMS_DELTA
         bool "Amstrad E3 (Delta)"
         depends on ARCH_OMAP1 && ARCH_OMAP15XX
         select FIQ
+        select GPIO_GENERIC_PLATFORM
+        select LEDS_GPIO_REGISTER
+        select REGULATOR
+        select REGULATOR_FIXED_VOLTAGE
         help
           Support for the Amstrad E3 (codename Delta) videophone. Say Y here
           if you have such a device.
diff --git a/arch/arm/mach-omap1/Makefile b/arch/arm/mach-omap1/Makefile
index 11c85cd2731..9923f92b545 100644
--- a/arch/arm/mach-omap1/Makefile
+++ b/arch/arm/mach-omap1/Makefile
@@ -6,7 +6,9 @@
 obj-y := io.o id.o sram.o time.o irq.o mux.o flash.o serial.o devices.o dma.o
 obj-y += clock.o clock_data.o opp_data.o reset.o pm_bus.o timer.o
 
-obj-$(CONFIG_OMAP_MCBSP) += mcbsp.o
+ifneq ($(CONFIG_SND_OMAP_SOC_MCBSP),)
+obj-y += mcbsp.o
+endif
 
 obj-$(CONFIG_OMAP_32K_TIMER)    += timer32k.o
 
diff --git a/arch/arm/mach-omap1/ams-delta-fiq-handler.S b/arch/arm/mach-omap1/ams-delta-fiq-handler.S
index c1c5fb6a5b4..399c4c49722 100644
--- a/arch/arm/mach-omap1/ams-delta-fiq-handler.S
+++ b/arch/arm/mach-omap1/ams-delta-fiq-handler.S
@@ -15,11 +15,12 @@
 
 #include <linux/linkage.h>
 
-#include <plat/io.h>
 #include <plat/board-ams-delta.h>
 
 #include <mach/ams-delta-fiq.h>
 
+#include "iomap.h"
+
 /*
  * GPIO related definitions, copied from arch/arm/plat-omap/gpio.c.
  * Unfortunately, those were not placed in a separate header file.
diff --git a/arch/arm/mach-omap1/ams-delta-fiq.c b/arch/arm/mach-omap1/ams-delta-fiq.c
index 152b32c15e2..fcce7ff3763 100644
--- a/arch/arm/mach-omap1/ams-delta-fiq.c
+++ b/arch/arm/mach-omap1/ams-delta-fiq.c
@@ -22,6 +22,7 @@
 #include <plat/board-ams-delta.h>
 
 #include <asm/fiq.h>
+
 #include <mach/ams-delta-fiq.h>
 
 static struct fiq_handler fh = {
diff --git a/arch/arm/mach-omap1/board-ams-delta.c b/arch/arm/mach-omap1/board-ams-delta.c
index 88909cc0b25..c1b681ef4cb 100644
--- a/arch/arm/mach-omap1/board-ams-delta.c
+++ b/arch/arm/mach-omap1/board-ams-delta.c
@@ -11,6 +11,7 @@
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
  */
+#include <linux/basic_mmio_gpio.h>
 #include <linux/gpio.h>
 #include <linux/kernel.h>
 #include <linux/init.h>
@@ -18,30 +19,33 @@
 #include <linux/interrupt.h>
 #include <linux/leds.h>
 #include <linux/platform_device.h>
+#include <linux/regulator/consumer.h>
+#include <linux/regulator/fixed.h>
+#include <linux/regulator/machine.h>
 #include <linux/serial_8250.h>
 #include <linux/export.h>
+#include <linux/omapfb.h>
+#include <linux/io.h>
 
 #include <media/soc_camera.h>
 
 #include <asm/serial.h>
-#include <mach/hardware.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 
-#include <plat/io.h>
 #include <plat/board-ams-delta.h>
 #include <plat/keypad.h>
 #include <plat/mux.h>
 #include <plat/usb.h>
 #include <plat/board.h>
-#include "common.h"
-#include <mach/camera.h>
 
+#include <mach/hardware.h>
 #include <mach/ams-delta-fiq.h>
+#include <mach/camera.h>
 
-static u8 ams_delta_latch1_reg;
-static u16 ams_delta_latch2_reg;
+#include "iomap.h"
+#include "common.h"
 
 static const unsigned int ams_delta_keymap[] = {
         KEY(0, 0, KEY_F1),              /* Advert    */
@@ -121,58 +125,188 @@ static const unsigned int ams_delta_keymap[] = {
         KEY(7, 3, KEY_LEFTCTRL),        /* Vol down  */
 };
 
-void ams_delta_latch1_write(u8 mask, u8 value)
-{
-        ams_delta_latch1_reg &= ~mask;
-        ams_delta_latch1_reg |= value;
-        *(volatile __u8 *) AMS_DELTA_LATCH1_VIRT = ams_delta_latch1_reg;
-}
-
-void ams_delta_latch2_write(u16 mask, u16 value)
-{
-        ams_delta_latch2_reg &= ~mask;
-        ams_delta_latch2_reg |= value;
-        *(volatile __u16 *) AMS_DELTA_LATCH2_VIRT = ams_delta_latch2_reg;
-}
+#define LATCH1_PHYS     0x01000000
+#define LATCH1_VIRT     0xEA000000
+#define MODEM_PHYS      0x04000000
+#define MODEM_VIRT      0xEB000000
+#define LATCH2_PHYS     0x08000000
+#define LATCH2_VIRT     0xEC000000
 
 static struct map_desc ams_delta_io_desc[] __initdata = {
         /* AMS_DELTA_LATCH1 */
         {
-                .virtual        = AMS_DELTA_LATCH1_VIRT,
-                .pfn            = __phys_to_pfn(AMS_DELTA_LATCH1_PHYS),
+                .virtual        = LATCH1_VIRT,
+                .pfn            = __phys_to_pfn(LATCH1_PHYS),
                 .length         = 0x01000000,
                 .type           = MT_DEVICE
         },
         /* AMS_DELTA_LATCH2 */
         {
-                .virtual        = AMS_DELTA_LATCH2_VIRT,
-                .pfn            = __phys_to_pfn(AMS_DELTA_LATCH2_PHYS),
+                .virtual        = LATCH2_VIRT,
+                .pfn            = __phys_to_pfn(LATCH2_PHYS),
                 .length         = 0x01000000,
                 .type           = MT_DEVICE
         },
         /* AMS_DELTA_MODEM */
         {
-                .virtual        = AMS_DELTA_MODEM_VIRT,
-                .pfn            = __phys_to_pfn(AMS_DELTA_MODEM_PHYS),
+                .virtual        = MODEM_VIRT,
+                .pfn            = __phys_to_pfn(MODEM_PHYS),
                 .length         = 0x01000000,
                 .type           = MT_DEVICE
         }
 };
 
-static struct omap_lcd_config ams_delta_lcd_config = {
+static struct omap_lcd_config ams_delta_lcd_config __initdata = {
         .ctrl_name      = "internal",
 };
 
-static struct omap_usb_config ams_delta_usb_config __initdata = {
+static struct omap_usb_config ams_delta_usb_config = {
         .register_host  = 1,
         .hmc_mode       = 16,
         .pins[0]        = 2,
 };
 
-static struct omap_board_config_kernel ams_delta_config[] __initdata = {
-        { OMAP_TAG_LCD,         &ams_delta_lcd_config },
+#define LATCH1_GPIO_BASE        232
+#define LATCH1_NGPIO            8
+
+static struct resource latch1_resources[] = {
+        [0] = {
+                .name   = "dat",
+                .start  = LATCH1_PHYS,
+                .end    = LATCH1_PHYS + (LATCH1_NGPIO - 1) / 8,
+                .flags  = IORESOURCE_MEM,
+        },
 };
 
+static struct bgpio_pdata latch1_pdata = {
+        .base   = LATCH1_GPIO_BASE,
+        .ngpio  = LATCH1_NGPIO,
+};
+
+static struct platform_device latch1_gpio_device = {
+        .name           = "basic-mmio-gpio",
+        .id             = 0,
+        .resource       = latch1_resources,
+        .num_resources  = ARRAY_SIZE(latch1_resources),
+        .dev            = {
+                .platform_data  = &latch1_pdata,
+        },
+};
+
+static struct resource latch2_resources[] = {
+        [0] = {
+                .name   = "dat",
+                .start  = LATCH2_PHYS,
+                .end    = LATCH2_PHYS + (AMS_DELTA_LATCH2_NGPIO - 1) / 8,
+                .flags  = IORESOURCE_MEM,
+        },
+};
+
+static struct bgpio_pdata latch2_pdata = {
+        .base   = AMS_DELTA_LATCH2_GPIO_BASE,
+        .ngpio  = AMS_DELTA_LATCH2_NGPIO,
+};
+
+static struct platform_device latch2_gpio_device = {
+        .name           = "basic-mmio-gpio",
+        .id             = 1,
+        .resource       = latch2_resources,
+        .num_resources  = ARRAY_SIZE(latch2_resources),
+        .dev            = {
+                .platform_data  = &latch2_pdata,
+        },
+};
+
+static const struct gpio latch_gpios[] __initconst = {
+        {
+                .gpio   = LATCH1_GPIO_BASE + 6,
+                .flags  = GPIOF_OUT_INIT_LOW,
+                .label  = "dockit1",
+        },
+        {
+                .gpio   = LATCH1_GPIO_BASE + 7,
+                .flags  = GPIOF_OUT_INIT_LOW,
+                .label  = "dockit2",
+        },
+        {
+                .gpio   = AMS_DELTA_GPIO_PIN_SCARD_RSTIN,
+                .flags  = GPIOF_OUT_INIT_LOW,
+                .label  = "scard_rstin",
+        },
+        {
+                .gpio   = AMS_DELTA_GPIO_PIN_SCARD_CMDVCC,
+                .flags  = GPIOF_OUT_INIT_LOW,
+                .label  = "scard_cmdvcc",
+        },
+        {
+                .gpio   = AMS_DELTA_GPIO_PIN_MODEM_CODEC,
+                .flags  = GPIOF_OUT_INIT_LOW,
+                .label  = "modem_codec",
+        },
+        {
+                .gpio   = AMS_DELTA_LATCH2_GPIO_BASE + 14,
+                .flags  = GPIOF_OUT_INIT_LOW,
+                .label  = "hookflash1",
+        },
+        {
+                .gpio   = AMS_DELTA_LATCH2_GPIO_BASE + 15,
+                .flags  = GPIOF_OUT_INIT_LOW,
+                .label  = "hookflash2",
+        },
+};
+
+static struct regulator_consumer_supply modem_nreset_consumers[] = {
+        REGULATOR_SUPPLY("RESET#", "serial8250.1"),
+        REGULATOR_SUPPLY("POR", "cx20442-codec"),
+};
+
+static struct regulator_init_data modem_nreset_data = {
+        .constraints            = {
+                .valid_ops_mask         = REGULATOR_CHANGE_STATUS,
+                .boot_on                = 1,
+        },
+        .num_consumer_supplies  = ARRAY_SIZE(modem_nreset_consumers),
+        .consumer_supplies      = modem_nreset_consumers,
+};
+
+static struct fixed_voltage_config modem_nreset_config = {
+        .supply_name            = "modem_nreset",
+        .microvolts             = 3300000,
+        .gpio                   = AMS_DELTA_GPIO_PIN_MODEM_NRESET,
+        .startup_delay          = 25000,
+        .enable_high            = 1,
+        .enabled_at_boot        = 1,
+        .init_data              = &modem_nreset_data,
+};
+
+static struct platform_device modem_nreset_device = {
+        .name   = "reg-fixed-voltage",
+        .id     = -1,
+        .dev    = {
+                .platform_data  = &modem_nreset_config,
+        },
+};
+
+struct modem_private_data {
+        struct regulator *regulator;
+};
+
+static struct modem_private_data modem_priv;
+
+void ams_delta_latch_write(int base, int ngpio, u16 mask, u16 value)
+{
+        int bit = 0;
+        u16 bitpos = 1 << bit;
+
+        for (; bit < ngpio; bit++, bitpos = bitpos << 1) {
+                if (!(mask & bitpos))
+                        continue;
+                else
+                        gpio_set_value(base + bit, (value & bitpos) != 0);
+        }
+}
+EXPORT_SYMBOL(ams_delta_latch_write);
+
 static struct resource ams_delta_nand_resources[] = {
         [0] = {
                 .start  = OMAP1_MPUIO_BASE,
@@ -202,7 +336,7 @@ static const struct matrix_keymap_data ams_delta_keymap_data = {
         .keymap_size    = ARRAY_SIZE(ams_delta_keymap),
 };
 
-static struct omap_kp_platform_data ams_delta_kp_data __initdata = {
+static struct omap_kp_platform_data ams_delta_kp_data = {
         .rows           = 8,
         .cols           = 8,
         .keymap_data    = &ams_delta_keymap_data,
@@ -224,9 +358,45 @@ static struct platform_device ams_delta_lcd_device = {
         .id     = -1,
 };
 
-static struct platform_device ams_delta_led_device = {
-        .name   = "ams-delta-led",
-        .id     = -1
+static const struct gpio_led gpio_leds[] __initconst = {
+        {
+                .name            = "camera",
+                .gpio            = LATCH1_GPIO_BASE + 0,
+                .default_state   = LEDS_GPIO_DEFSTATE_OFF,
+#ifdef CONFIG_LEDS_TRIGGERS
+                .default_trigger = "ams_delta_camera",
+#endif
+        },
+        {
+                .name            = "advert",
+                .gpio            = LATCH1_GPIO_BASE + 1,
+                .default_state   = LEDS_GPIO_DEFSTATE_OFF,
+        },
+        {
+                .name            = "email",
+                .gpio            = LATCH1_GPIO_BASE + 2,
+                .default_state   = LEDS_GPIO_DEFSTATE_OFF,
+        },
+        {
+                .name            = "handsfree",
+                .gpio            = LATCH1_GPIO_BASE + 3,
+                .default_state   = LEDS_GPIO_DEFSTATE_OFF,
+        },
+        {
+                .name            = "voicemail",
+                .gpio            = LATCH1_GPIO_BASE + 4,
+                .default_state   = LEDS_GPIO_DEFSTATE_OFF,
+        },
+        {
+                .name            = "voice",
+                .gpio            = LATCH1_GPIO_BASE + 5,
+                .default_state   = LEDS_GPIO_DEFSTATE_OFF,
+        },
+};
+
+static const struct gpio_led_platform_data leds_pdata __initconst = {
+        .leds           = gpio_leds,
+        .num_leds       = ARRAY_SIZE(gpio_leds),
 };
 
 static struct i2c_board_info ams_delta_camera_board_info[] = {
@@ -275,13 +445,17 @@ static struct omap1_cam_platform_data ams_delta_camera_platform_data = {
 };
 
 static struct platform_device *ams_delta_devices[] __initdata = {
-        &ams_delta_nand_device,
+        &latch1_gpio_device,
+        &latch2_gpio_device,
         &ams_delta_kp_device,
-        &ams_delta_lcd_device,
-        &ams_delta_led_device,
         &ams_delta_camera_device,
 };
 
+static struct platform_device *late_devices[] __initdata = {
+        &ams_delta_nand_device,
+        &ams_delta_lcd_device,
+};
+
 static void __init ams_delta_init(void)
 {
         /* mux pins for uarts */
@@ -302,37 +476,53 @@ static void __init ams_delta_init(void)
         omap_cfg_reg(J19_1610_CAM_D6);
         omap_cfg_reg(J18_1610_CAM_D7);
 
-        omap_board_config = ams_delta_config;
-        omap_board_config_size = ARRAY_SIZE(ams_delta_config);
         omap_serial_init();
         omap_register_i2c_bus(1, 100, NULL, 0);
 
-        /* Clear latch2 (NAND, LCD, modem enable) */
-        ams_delta_latch2_write(~0, 0);
-
         omap1_usb_init(&ams_delta_usb_config);
         omap1_set_camera_info(&ams_delta_camera_platform_data);
 #ifdef CONFIG_LEDS_TRIGGERS
         led_trigger_register_simple("ams_delta_camera",
                         &ams_delta_camera_led_trigger);
 #endif
+        gpio_led_register_device(-1, &leds_pdata);
         platform_add_devices(ams_delta_devices, ARRAY_SIZE(ams_delta_devices));
 
         ams_delta_init_fiq();
 
         omap_writew(omap_readw(ARM_RSTCT1) | 0x0004, ARM_RSTCT1);
+
+        omapfb_set_lcd_config(&ams_delta_lcd_config);
+}
+
+static void modem_pm(struct uart_port *port, unsigned int state, unsigned old)
+{
+        struct modem_private_data *priv = port->private_data;
+
+        if (IS_ERR(priv->regulator))
+                return;
+
+        if (state == old)
+                return;
+
+        if (state == 0)
+                regulator_enable(priv->regulator);
+        else if (old == 0)
+                regulator_disable(priv->regulator);
 }
 
 static struct plat_serial8250_port ams_delta_modem_ports[] = {
         {
-                .membase        = IOMEM(AMS_DELTA_MODEM_VIRT),
-                .mapbase        = AMS_DELTA_MODEM_PHYS,
+                .membase        = IOMEM(MODEM_VIRT),
+                .mapbase        = MODEM_PHYS,
                 .irq            = -EINVAL, /* changed later */
                 .flags          = UPF_BOOT_AUTOCONF,
                 .irqflags       = IRQF_TRIGGER_RISING,
                 .iotype         = UPIO_MEM,
                 .regshift       = 1,
                 .uartclk        = BASE_BAUD * 16,
+                .pm             = modem_pm,
+                .private_data   = &modem_priv,
         },
         { },
 };
@@ -345,13 +535,27 @@ static struct platform_device ams_delta_modem_device = {
         },
 };
 
-static int __init ams_delta_modem_init(void)
+static int __init late_init(void)
 {
         int err;
 
         if (!machine_is_ams_delta())
                 return -ENODEV;
 
+        err = gpio_request_array(latch_gpios, ARRAY_SIZE(latch_gpios));
+        if (err) {
+                pr_err("Couldn't take over latch1/latch2 GPIO pins\n");
+                return err;
+        }
+
+        platform_add_devices(late_devices, ARRAY_SIZE(late_devices));
+
+        err = platform_device_register(&modem_nreset_device);
+        if (err) {
+                pr_err("Couldn't register the modem regulator device\n");
+                return err;
+        }
+
         omap_cfg_reg(M14_1510_GPIO2);
         ams_delta_modem_ports[0].irq =
                         gpio_to_irq(AMS_DELTA_GPIO_PIN_MODEM_IRQ);
@@ -363,13 +567,35 @@ static int __init ams_delta_modem_init(void)
         }
         gpio_direction_input(AMS_DELTA_GPIO_PIN_MODEM_IRQ);
 
-        ams_delta_latch2_write(
-                AMS_DELTA_LATCH2_MODEM_NRESET | AMS_DELTA_LATCH2_MODEM_CODEC,
-                AMS_DELTA_LATCH2_MODEM_NRESET | AMS_DELTA_LATCH2_MODEM_CODEC);
+        /* Initialize the modem_nreset regulator consumer before use */
+        modem_priv.regulator = ERR_PTR(-ENODEV);
+
+        ams_delta_latch2_write(AMS_DELTA_LATCH2_MODEM_CODEC,
+                        AMS_DELTA_LATCH2_MODEM_CODEC);
 
-        return platform_device_register(&ams_delta_modem_device);
+        err = platform_device_register(&ams_delta_modem_device);
+        if (err)
+                goto gpio_free;
+
+        /*
+         * Once the modem device is registered, the modem_nreset
+         * regulator can be requested on behalf of that device.
+         */
+        modem_priv.regulator = regulator_get(&ams_delta_modem_device.dev,
+                        "RESET#");
+        if (IS_ERR(modem_priv.regulator)) {
+                err = PTR_ERR(modem_priv.regulator);
+                goto unregister;
+        }
+        return 0;
+
+unregister:
+        platform_device_unregister(&ams_delta_modem_device);
+gpio_free:
+        gpio_free(AMS_DELTA_GPIO_PIN_MODEM_IRQ);
+        return err;
 }
-arch_initcall(ams_delta_modem_init);
+late_initcall(late_init);
 
 static void __init ams_delta_map_io(void)
 {
@@ -388,6 +614,3 @@ MACHINE_START(AMS_DELTA, "Amstrad E3 (Delta)")
         .timer          = &omap1_timer,
         .restart        = omap1_restart,
 MACHINE_END
-
-EXPORT_SYMBOL(ams_delta_latch1_write);
-EXPORT_SYMBOL(ams_delta_latch2_write);
diff --git a/arch/arm/mach-omap1/board-fsample.c b/arch/arm/mach-omap1/board-fsample.c
index 0b9464b4121..80bd43c7f4e 100644
--- a/arch/arm/mach-omap1/board-fsample.c
+++ b/arch/arm/mach-omap1/board-fsample.c
@@ -21,8 +21,8 @@
 #include <linux/mtd/physmap.h>
 #include <linux/input.h>
 #include <linux/smc91x.h>
+#include <linux/omapfb.h>
 
-#include <mach/hardware.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
@@ -32,9 +32,13 @@
 #include <plat/flash.h>
 #include <plat/fpga.h>
 #include <plat/keypad.h>
-#include "common.h"
 #include <plat/board.h>
 
+#include <mach/hardware.h>
+
+#include "iomap.h"
+#include "common.h"
+
 /* fsample is pretty close to p2-sample */
 
 #define fsample_cpld_read(reg) __raw_readb(reg)
@@ -273,27 +277,17 @@ static struct platform_device kp_device = {
         .resource       = kp_resources,
 };
 
-static struct platform_device lcd_device = {
-        .name           = "lcd_p2",
-        .id             = -1,
-};
-
 static struct platform_device *devices[] __initdata = {
         &nor_device,
         &nand_device,
         &smc91x_device,
         &kp_device,
-        &lcd_device,
 };
 
 static struct omap_lcd_config fsample_lcd_config = {
         .ctrl_name      = "internal",
 };
 
-static struct omap_board_config_kernel fsample_config[] __initdata = {
-        { OMAP_TAG_LCD,         &fsample_lcd_config },
-};
-
 static void __init omap_fsample_init(void)
 {
         /* Early, board-dependent init */
@@ -352,10 +346,10 @@ static void __init omap_fsample_init(void)
 
         platform_add_devices(devices, ARRAY_SIZE(devices));
 
-        omap_board_config = fsample_config;
-        omap_board_config_size = ARRAY_SIZE(fsample_config);
         omap_serial_init();
         omap_register_i2c_bus(1, 100, NULL, 0);
+
+        omapfb_set_lcd_config(&fsample_lcd_config);
 }
 
 /* Only FPGA needs to be mapped here. All others are done with ioremap */
diff --git a/arch/arm/mach-omap1/board-h2.c b/arch/arm/mach-omap1/board-h2.c
index 00ad6b22d60..c3068622fdc 100644
--- a/arch/arm/mach-omap1/board-h2.c
+++ b/arch/arm/mach-omap1/board-h2.c
@@ -30,8 +30,7 @@
 #include <linux/input.h>
 #include <linux/i2c/tps65010.h>
 #include <linux/smc91x.h>
-
-#include <mach/hardware.h>
+#include <linux/omapfb.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -43,9 +42,11 @@
 #include <plat/irda.h>
 #include <plat/usb.h>
 #include <plat/keypad.h>
-#include "common.h"
 #include <plat/flash.h>
 
+#include <mach/hardware.h>
+
+#include "common.h"
 #include "board-h2.h"
 
 /* At OMAP1610 Innovator the Ethernet is directly connected to CS1 */
@@ -325,18 +326,12 @@ static struct platform_device h2_irda_device = {
         .resource       = h2_irda_resources,
 };
 
-static struct platform_device h2_lcd_device = {
-        .name           = "lcd_h2",
-        .id             = -1,
-};
-
 static struct platform_device *h2_devices[] __initdata = {
         &h2_nor_device,
         &h2_nand_device,
         &h2_smc91x_device,
         &h2_irda_device,
         &h2_kp_device,
-        &h2_lcd_device,
 };
 
 static void __init h2_init_smc91x(void)
@@ -391,10 +386,6 @@ static struct omap_lcd_config h2_lcd_config __initdata = {
         .ctrl_name      = "internal",
 };
 
-static struct omap_board_config_kernel h2_config[] __initdata = {
-        { OMAP_TAG_LCD,         &h2_lcd_config },
-};
-
 static void __init h2_init(void)
 {
         h2_init_smc91x();
@@ -438,13 +429,13 @@ static void __init h2_init(void)
         omap_cfg_reg(N19_1610_KBR5);
 
         platform_add_devices(h2_devices, ARRAY_SIZE(h2_devices));
-        omap_board_config = h2_config;
-        omap_board_config_size = ARRAY_SIZE(h2_config);
         omap_serial_init();
         omap_register_i2c_bus(1, 100, h2_i2c_board_info,
                               ARRAY_SIZE(h2_i2c_board_info));
         omap1_usb_init(&h2_usb_config);
         h2_mmc_init();
+
+        omapfb_set_lcd_config(&h2_lcd_config);
 }
 
 MACHINE_START(OMAP_H2, "TI-H2")
diff --git a/arch/arm/mach-omap1/board-h3.c b/arch/arm/mach-omap1/board-h3.c
index 4a7f2514970..64b8584f64c 100644
--- a/arch/arm/mach-omap1/board-h3.c
+++ b/arch/arm/mach-omap1/board-h3.c
@@ -30,24 +30,25 @@
 #include <linux/spi/spi.h>
 #include <linux/i2c/tps65010.h>
 #include <linux/smc91x.h>
+#include <linux/omapfb.h>
 
 #include <asm/setup.h>
 #include <asm/page.h>
-#include <mach/hardware.h>
-
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 
-#include <mach/irqs.h>
 #include <plat/mux.h>
 #include <plat/tc.h>
 #include <plat/usb.h>
 #include <plat/keypad.h>
 #include <plat/dma.h>
-#include "common.h"
 #include <plat/flash.h>
 
+#include <mach/hardware.h>
+#include <mach/irqs.h>
+
+#include "common.h"
 #include "board-h3.h"
 
 /* In OMAP1710 H3 the Ethernet is directly connected to CS1 */
@@ -370,10 +371,6 @@ static struct omap_lcd_config h3_lcd_config __initdata = {
         .ctrl_name      = "internal",
 };
 
-static struct omap_board_config_kernel h3_config[] __initdata = {
-        { OMAP_TAG_LCD,         &h3_lcd_config },
-};
-
 static struct i2c_board_info __initdata h3_i2c_board_info[] = {
        {
                 I2C_BOARD_INFO("tps65013", 0x48),
@@ -426,13 +423,13 @@ static void __init h3_init(void)
         platform_add_devices(devices, ARRAY_SIZE(devices));
         spi_register_board_info(h3_spi_board_info,
                                 ARRAY_SIZE(h3_spi_board_info));
-        omap_board_config = h3_config;
-        omap_board_config_size = ARRAY_SIZE(h3_config);
         omap_serial_init();
         omap_register_i2c_bus(1, 100, h3_i2c_board_info,
                               ARRAY_SIZE(h3_i2c_board_info));
         omap1_usb_init(&h3_usb_config);
         h3_mmc_init();
+
+        omapfb_set_lcd_config(&h3_lcd_config);
 }
 
 MACHINE_START(OMAP_H3, "TI OMAP1710 H3 board")
diff --git a/arch/arm/mach-omap1/board-htcherald.c b/arch/arm/mach-omap1/board-htcherald.c
index 731cc3db7ab..827d83a96af 100644
--- a/arch/arm/mach-omap1/board-htcherald.c
+++ b/arch/arm/mach-omap1/board-htcherald.c
@@ -27,7 +27,7 @@
 #include <linux/init.h>
 #include <linux/platform_device.h>
 #include <linux/input.h>
-#include <linux/io.h>
+#include <linux/delay.h>
 #include <linux/gpio.h>
 #include <linux/gpio_keys.h>
 #include <linux/i2c.h>
@@ -36,12 +36,12 @@
 #include <linux/leds.h>
 #include <linux/spi/spi.h>
 #include <linux/spi/ads7846.h>
+#include <linux/omapfb.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 
 #include <plat/omap7xx.h>
-#include "common.h"
 #include <plat/board.h>
 #include <plat/keypad.h>
 #include <plat/usb.h>
@@ -49,7 +49,7 @@
 
 #include <mach/irqs.h>
 
-#include <linux/delay.h>
+#include "common.h"
 
 /* LCD register definition */
 #define       OMAP_LCDC_CONTROL               (0xfffec000 + 0x00)
@@ -398,10 +398,6 @@ static struct omap_lcd_config htcherald_lcd_config __initdata = {
         .ctrl_name      = "internal",
 };
 
-static struct omap_board_config_kernel htcherald_config[] __initdata = {
-        { OMAP_TAG_LCD, &htcherald_lcd_config },
-};
-
 static struct platform_device lcd_device = {
         .name           = "lcd_htcherald",
         .id             = -1,
@@ -580,8 +576,6 @@ static void __init htcherald_init(void)
         printk(KERN_INFO "HTC Herald init.\n");
 
         /* Do board initialization before we register all the devices */
-        omap_board_config = htcherald_config;
-        omap_board_config_size = ARRAY_SIZE(htcherald_config);
         platform_add_devices(devices, ARRAY_SIZE(devices));
 
         htcherald_disable_watchdog();
@@ -598,6 +592,8 @@ static void __init htcherald_init(void)
         htc_mmc_data[0] = &htc_mmc1_data;
         omap1_init_mmc(htc_mmc_data, 1);
 #endif
+
+        omapfb_set_lcd_config(&htcherald_lcd_config);
 }
 
 MACHINE_START(HERALD, "HTC Herald")
diff --git a/arch/arm/mach-omap1/board-innovator.c b/arch/arm/mach-omap1/board-innovator.c
index be2002f42de..61219182d16 100644
--- a/arch/arm/mach-omap1/board-innovator.c
+++ b/arch/arm/mach-omap1/board-innovator.c
@@ -25,8 +25,8 @@
 #include <linux/mtd/physmap.h>
 #include <linux/input.h>
 #include <linux/smc91x.h>
+#include <linux/omapfb.h>
 
-#include <mach/hardware.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
@@ -37,9 +37,13 @@
 #include <plat/tc.h>
 #include <plat/usb.h>
 #include <plat/keypad.h>
-#include "common.h"
 #include <plat/mmc.h>
 
+#include <mach/hardware.h>
+
+#include "iomap.h"
+#include "common.h"
+
 /* At OMAP1610 Innovator the Ethernet is directly connected to CS1 */
 #define INNOVATOR1610_ETHR_START        0x04000300
 
@@ -370,10 +374,6 @@ static inline void innovator_mmc_init(void)
 }
 #endif
 
-static struct omap_board_config_kernel innovator_config[] = {
-        { OMAP_TAG_LCD,         NULL },
-};
-
 static void __init innovator_init(void)
 {
         if (cpu_is_omap1510())
@@ -416,17 +416,15 @@ static void __init innovator_init(void)
 #ifdef CONFIG_ARCH_OMAP15XX
         if (cpu_is_omap1510()) {
                 omap1_usb_init(&innovator1510_usb_config);
-                innovator_config[0].data = &innovator1510_lcd_config;
+                omapfb_set_lcd_config(&innovator1510_lcd_config);
         }
 #endif
 #ifdef CONFIG_ARCH_OMAP16XX
         if (cpu_is_omap1610()) {
                 omap1_usb_init(&h2_usb_config);
-                innovator_config[0].data = &innovator1610_lcd_config;
+                omapfb_set_lcd_config(&innovator1610_lcd_config);
         }
 #endif
-        omap_board_config = innovator_config;
-        omap_board_config_size = ARRAY_SIZE(innovator_config);
         omap_serial_init();
         omap_register_i2c_bus(1, 100, NULL, 0);
         innovator_mmc_init();
diff --git a/arch/arm/mach-omap1/board-nokia770.c b/arch/arm/mach-omap1/board-nokia770.c
index f9efc036ba9..fe95ec5f6f0 100644
--- a/arch/arm/mach-omap1/board-nokia770.c
+++ b/arch/arm/mach-omap1/board-nokia770.c
@@ -21,7 +21,6 @@
 #include <linux/workqueue.h>
 #include <linux/delay.h>
 
-#include <mach/hardware.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
@@ -30,12 +29,14 @@
 #include <plat/usb.h>
 #include <plat/board.h>
 #include <plat/keypad.h>
-#include "common.h"
-#include <plat/hwa742.h>
 #include <plat/lcd_mipid.h>
 #include <plat/mmc.h>
 #include <plat/clock.h>
 
+#include <mach/hardware.h>
+
+#include "common.h"
+
 #define ADS7846_PENDOWN_GPIO    15
 
 static const unsigned int nokia770_keymap[] = {
@@ -99,15 +100,16 @@ static struct mipid_platform_data nokia770_mipid_platform_data = {
         .shutdown = mipid_shutdown,
 };
 
+static struct omap_lcd_config nokia770_lcd_config __initdata = {
+        .ctrl_name      = "hwa742",
+};
+
 static void __init mipid_dev_init(void)
 {
-        const struct omap_lcd_config *conf;
+        nokia770_mipid_platform_data.nreset_gpio = 13;
+        nokia770_mipid_platform_data.data_lines = 16;
 
-        conf = omap_get_config(OMAP_TAG_LCD, struct omap_lcd_config);
-        if (conf != NULL) {
-                nokia770_mipid_platform_data.nreset_gpio = conf->nreset_gpio;
-                nokia770_mipid_platform_data.data_lines = conf->data_lines;
-        }
+        omapfb_set_lcd_config(&nokia770_lcd_config);
 }
 
 static void __init ads7846_dev_init(void)
@@ -150,14 +152,9 @@ static struct spi_board_info nokia770_spi_board_info[] __initdata = {
         },
 };
 
-static struct hwa742_platform_data nokia770_hwa742_platform_data = {
-        .te_connected           = 1,
-};
-
 static void __init hwa742_dev_init(void)
 {
         clk_add_alias("hwa_sys_ck", NULL, "bclk", NULL);
-        omapfb_set_ctrl_platform_data(&nokia770_hwa742_platform_data);
 }
 
 /* assume no Mini-AB port */
diff --git a/arch/arm/mach-omap1/board-osk.c b/arch/arm/mach-omap1/board-osk.c
index 675de06557a..1fe347396f4 100644
--- a/arch/arm/mach-omap1/board-osk.c
+++ b/arch/arm/mach-omap1/board-osk.c
@@ -34,15 +34,12 @@
 #include <linux/i2c.h>
 #include <linux/leds.h>
 #include <linux/smc91x.h>
-
+#include <linux/omapfb.h>
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/partitions.h>
 #include <linux/mtd/physmap.h>
-
 #include <linux/i2c/tps65010.h>
 
-#include <mach/hardware.h>
-
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
@@ -51,6 +48,9 @@
 #include <plat/usb.h>
 #include <plat/mux.h>
 #include <plat/tc.h>
+
+#include <mach/hardware.h>
+
 #include "common.h"
 
 /* At OMAP5912 OSK the Ethernet is directly connected to CS1 */
@@ -300,12 +300,6 @@ static struct omap_lcd_config osk_lcd_config __initdata = {
 };
 #endif
 
-static struct omap_board_config_kernel osk_config[] __initdata = {
-#ifdef  CONFIG_OMAP_OSK_MISTRAL
-        { OMAP_TAG_LCD,                 &osk_lcd_config },
-#endif
-};
-
 #ifdef  CONFIG_OMAP_OSK_MISTRAL
 
 #include <linux/input.h>
@@ -549,8 +543,6 @@ static void __init osk_init(void)
         osk_flash_resource.end = osk_flash_resource.start = omap_cs3_phys();
         osk_flash_resource.end += SZ_32M - 1;
         platform_add_devices(osk5912_devices, ARRAY_SIZE(osk5912_devices));
-        omap_board_config = osk_config;
-        omap_board_config_size = ARRAY_SIZE(osk_config);
 
         l = omap_readl(USB_TRANSCEIVER_CTRL);
         l |= (3 << 1);
@@ -567,6 +559,11 @@ static void __init osk_init(void)
         omap_register_i2c_bus(1, 400, osk_i2c_board_info,
                               ARRAY_SIZE(osk_i2c_board_info));
         osk_mistral_init();
+
+#ifdef  CONFIG_OMAP_OSK_MISTRAL
+        omapfb_set_lcd_config(&osk_lcd_config);
+#endif
+
 }
 
 MACHINE_START(OMAP_OSK, "TI-OSK")
diff --git a/arch/arm/mach-omap1/board-palmte.c b/arch/arm/mach-omap1/board-palmte.c
index 81fa27f8836..0863d8e2bdf 100644
--- a/arch/arm/mach-omap1/board-palmte.c
+++ b/arch/arm/mach-omap1/board-palmte.c
@@ -27,8 +27,8 @@
 #include <linux/spi/spi.h>
 #include <linux/interrupt.h>
 #include <linux/apm-emulation.h>
+#include <linux/omapfb.h>
 
-#include <mach/hardware.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
@@ -41,6 +41,9 @@
 #include <plat/board.h>
 #include <plat/irda.h>
 #include <plat/keypad.h>
+
+#include <mach/hardware.h>
+
 #include "common.h"
 
 #define PALMTE_USBDETECT_GPIO   0
@@ -209,10 +212,6 @@ static struct omap_lcd_config palmte_lcd_config __initdata = {
         .ctrl_name      = "internal",
 };
 
-static struct omap_board_config_kernel palmte_config[] __initdata = {
-        { OMAP_TAG_LCD,         &palmte_lcd_config },
-};
-
 static struct spi_board_info palmte_spi_info[] __initdata = {
         {
                 .modalias       = "tsc2102",
@@ -250,9 +249,6 @@ static void __init omap_palmte_init(void)
         omap_cfg_reg(UART3_TX);
         omap_cfg_reg(UART3_RX);
 
-        omap_board_config = palmte_config;
-        omap_board_config_size = ARRAY_SIZE(palmte_config);
-
         platform_add_devices(palmte_devices, ARRAY_SIZE(palmte_devices));
 
         spi_register_board_info(palmte_spi_info, ARRAY_SIZE(palmte_spi_info));
@@ -260,6 +256,8 @@ static void __init omap_palmte_init(void)
         omap_serial_init();
         omap1_usb_init(&palmte_usb_config);
         omap_register_i2c_bus(1, 100, NULL, 0);
+
+        omapfb_set_lcd_config(&palmte_lcd_config);
 }
 
 MACHINE_START(OMAP_PALMTE, "OMAP310 based Palm Tungsten E")
diff --git a/arch/arm/mach-omap1/board-palmtt.c b/arch/arm/mach-omap1/board-palmtt.c
index 81cb8217838..4ff699c509c 100644
--- a/arch/arm/mach-omap1/board-palmtt.c
+++ b/arch/arm/mach-omap1/board-palmtt.c
@@ -24,8 +24,10 @@
 #include <linux/mtd/partitions.h>
 #include <linux/mtd/physmap.h>
 #include <linux/leds.h>
+#include <linux/omapfb.h>
+#include <linux/spi/spi.h>
+#include <linux/spi/ads7846.h>
 
-#include <mach/hardware.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
@@ -39,10 +41,10 @@
 #include <plat/board.h>
 #include <plat/irda.h>
 #include <plat/keypad.h>
-#include "common.h"
 
-#include <linux/spi/spi.h>
-#include <linux/spi/ads7846.h>
+#include <mach/hardware.h>
+
+#include "common.h"
 
 #define PALMTT_USBDETECT_GPIO   0
 #define PALMTT_CABLE_GPIO       1
@@ -273,10 +275,6 @@ static struct omap_lcd_config palmtt_lcd_config __initdata = {
         .ctrl_name      = "internal",
 };
 
-static struct omap_board_config_kernel palmtt_config[] __initdata = {
-        { OMAP_TAG_LCD,         &palmtt_lcd_config      },
-};
-
 static void __init omap_mpu_wdt_mode(int mode) {
         if (mode)
                 omap_writew(0x8000, OMAP_WDT_TIMER_MODE);
@@ -298,15 +296,14 @@ static void __init omap_palmtt_init(void)
 
         omap_mpu_wdt_mode(0);
 
-        omap_board_config = palmtt_config;
-        omap_board_config_size = ARRAY_SIZE(palmtt_config);
-
         platform_add_devices(palmtt_devices, ARRAY_SIZE(palmtt_devices));
 
         spi_register_board_info(palmtt_boardinfo,ARRAY_SIZE(palmtt_boardinfo));
         omap_serial_init();
         omap1_usb_init(&palmtt_usb_config);
         omap_register_i2c_bus(1, 100, NULL, 0);
+
+        omapfb_set_lcd_config(&palmtt_lcd_config);
 }
 
 MACHINE_START(OMAP_PALMTT, "OMAP1510 based Palm Tungsten|T")
diff --git a/arch/arm/mach-omap1/board-palmz71.c b/arch/arm/mach-omap1/board-palmz71.c
index e881945ce8e..abcbbd339ae 100644
--- a/arch/arm/mach-omap1/board-palmz71.c
+++ b/arch/arm/mach-omap1/board-palmz71.c
@@ -27,8 +27,10 @@
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/partitions.h>
 #include <linux/mtd/physmap.h>
+#include <linux/omapfb.h>
+#include <linux/spi/spi.h>
+#include <linux/spi/ads7846.h>
 
-#include <mach/hardware.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
@@ -41,10 +43,10 @@
 #include <plat/board.h>
 #include <plat/irda.h>
 #include <plat/keypad.h>
-#include "common.h"
 
-#include <linux/spi/spi.h>
-#include <linux/spi/ads7846.h>
+#include <mach/hardware.h>
+
+#include "common.h"
 
 #define PALMZ71_USBDETECT_GPIO  0
 #define PALMZ71_PENIRQ_GPIO     6
@@ -239,10 +241,6 @@ static struct omap_lcd_config palmz71_lcd_config __initdata = {
         .ctrl_name = "internal",
 };
 
-static struct omap_board_config_kernel palmz71_config[] __initdata = {
-        {OMAP_TAG_LCD,  &palmz71_lcd_config},
-};
-
 static irqreturn_t
 palmz71_powercable(int irq, void *dev_id)
 {
@@ -313,9 +311,6 @@ omap_palmz71_init(void)
         palmz71_gpio_setup(1);
         omap_mpu_wdt_mode(0);
 
-        omap_board_config = palmz71_config;
-        omap_board_config_size = ARRAY_SIZE(palmz71_config);
-
         platform_add_devices(devices, ARRAY_SIZE(devices));
 
         spi_register_board_info(palmz71_boardinfo,
@@ -324,6 +319,8 @@ omap_palmz71_init(void)
         omap_serial_init();
         omap_register_i2c_bus(1, 100, NULL, 0);
         palmz71_gpio_setup(0);
+
+        omapfb_set_lcd_config(&palmz71_lcd_config);
 }
 
 MACHINE_START(OMAP_PALMZ71, "OMAP310 based Palm Zire71")
diff --git a/arch/arm/mach-omap1/board-perseus2.c b/arch/arm/mach-omap1/board-perseus2.c
index c000bed7627..76d4ee05a81 100644
--- a/arch/arm/mach-omap1/board-perseus2.c
+++ b/arch/arm/mach-omap1/board-perseus2.c
@@ -21,8 +21,8 @@
 #include <linux/mtd/physmap.h>
 #include <linux/input.h>
 #include <linux/smc91x.h>
+#include <linux/omapfb.h>
 
-#include <mach/hardware.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
@@ -32,9 +32,13 @@
 #include <plat/fpga.h>
 #include <plat/flash.h>
 #include <plat/keypad.h>
-#include "common.h"
 #include <plat/board.h>
 
+#include <mach/hardware.h>
+
+#include "iomap.h"
+#include "common.h"
+
 static const unsigned int p2_keymap[] = {
         KEY(0, 0, KEY_UP),
         KEY(1, 0, KEY_RIGHT),
@@ -232,27 +236,17 @@ static struct platform_device kp_device = {
         .resource       = kp_resources,
 };
 
-static struct platform_device lcd_device = {
-        .name           = "lcd_p2",
-        .id             = -1,
-};
-
 static struct platform_device *devices[] __initdata = {
         &nor_device,
         &nand_device,
         &smc91x_device,
         &kp_device,
-        &lcd_device,
 };
 
 static struct omap_lcd_config perseus2_lcd_config __initdata = {
         .ctrl_name      = "internal",
 };
 
-static struct omap_board_config_kernel perseus2_config[] __initdata = {
-        { OMAP_TAG_LCD,         &perseus2_lcd_config },
-};
-
 static void __init perseus2_init_smc91x(void)
 {
         fpga_write(1, H2P2_DBG_FPGA_LAN_RESET);
@@ -320,10 +314,10 @@ static void __init omap_perseus2_init(void)
 
         platform_add_devices(devices, ARRAY_SIZE(devices));
 
-        omap_board_config = perseus2_config;
-        omap_board_config_size = ARRAY_SIZE(perseus2_config);
         omap_serial_init();
         omap_register_i2c_bus(1, 100, NULL, 0);
+
+        omapfb_set_lcd_config(&perseus2_lcd_config);
 }
 
 /* Only FPGA needs to be mapped here. All others are done with ioremap */
diff --git a/arch/arm/mach-omap1/board-sx1.c b/arch/arm/mach-omap1/board-sx1.c
index 7bcd82ab0fd..f34cb74a9f4 100644
--- a/arch/arm/mach-omap1/board-sx1.c
+++ b/arch/arm/mach-omap1/board-sx1.c
@@ -27,8 +27,8 @@
 #include <linux/i2c.h>
 #include <linux/errno.h>
 #include <linux/export.h>
+#include <linux/omapfb.h>
 
-#include <mach/hardware.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
@@ -40,10 +40,13 @@
 #include <plat/usb.h>
 #include <plat/tc.h>
 #include <plat/board.h>
-#include "common.h"
 #include <plat/keypad.h>
 #include <plat/board-sx1.h>
 
+#include <mach/hardware.h>
+
+#include "common.h"
+
 /* Write to I2C device */
 int sx1_i2c_write_byte(u8 devaddr, u8 regoffset, u8 value)
 {
@@ -355,11 +358,6 @@ static struct omap_usb_config sx1_usb_config __initdata = {
 
 /*----------- LCD -------------------------*/
 
-static struct platform_device sx1_lcd_device = {
-        .name           = "lcd_sx1",
-        .id             = -1,
-};
-
 static struct omap_lcd_config sx1_lcd_config __initdata = {
         .ctrl_name      = "internal",
 };
@@ -368,14 +366,8 @@ static struct omap_lcd_config sx1_lcd_config __initdata = {
 static struct platform_device *sx1_devices[] __initdata = {
         &sx1_flash_device,
         &sx1_kp_device,
-        &sx1_lcd_device,
         &sx1_irda_device,
 };
-/*-----------------------------------------*/
-
-static struct omap_board_config_kernel sx1_config[] __initdata = {
-        { OMAP_TAG_LCD, &sx1_lcd_config },
-};
 
 /*-----------------------------------------*/
 
@@ -391,8 +383,6 @@ static void __init omap_sx1_init(void)
 
         platform_add_devices(sx1_devices, ARRAY_SIZE(sx1_devices));
 
-        omap_board_config = sx1_config;
-        omap_board_config_size = ARRAY_SIZE(sx1_config);
         omap_serial_init();
         omap_register_i2c_bus(1, 100, NULL, 0);
         omap1_usb_init(&sx1_usb_config);
@@ -406,6 +396,8 @@ static void __init omap_sx1_init(void)
         gpio_direction_output(1, 1);    /*A_IRDA_OFF = 1 */
         gpio_direction_output(11, 0);   /*A_SWITCH = 0 */
         gpio_direction_output(15, 0);   /*A_USB_ON = 0 */
+
+        omapfb_set_lcd_config(&sx1_lcd_config);
 }
 
 MACHINE_START(SX1, "OMAP310 based Siemens SX1")
diff --git a/arch/arm/mach-omap1/board-voiceblue.c b/arch/arm/mach-omap1/board-voiceblue.c
index f83a502dc93..659d0f75de2 100644
--- a/arch/arm/mach-omap1/board-voiceblue.c
+++ b/arch/arm/mach-omap1/board-voiceblue.c
@@ -27,18 +27,20 @@
 #include <linux/smc91x.h>
 #include <linux/export.h>
 
-#include <mach/hardware.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 
 #include <plat/board-voiceblue.h>
-#include "common.h"
 #include <plat/flash.h>
 #include <plat/mux.h>
 #include <plat/tc.h>
 #include <plat/usb.h>
 
+#include <mach/hardware.h>
+
+#include "common.h"
+
 static struct plat_serial8250_port voiceblue_ports[] = {
         {
                 .mapbase        = (unsigned long)(OMAP_CS1_PHYS + 0x40000),
diff --git a/arch/arm/mach-omap1/clock.c b/arch/arm/mach-omap1/clock.c
index 0c50df05d13..67382ddd8c8 100644
--- a/arch/arm/mach-omap1/clock.c
+++ b/arch/arm/mach-omap1/clock.c
@@ -15,8 +15,8 @@
 #include <linux/list.h>
 #include <linux/errno.h>
 #include <linux/err.h>
-#include <linux/clk.h>
 #include <linux/io.h>
+#include <linux/clk.h>
 #include <linux/clkdev.h>
 
 #include <asm/mach-types.h>
@@ -27,6 +27,9 @@
 #include <plat/sram.h>
 #include <plat/clkdev_omap.h>
 
+#include <mach/hardware.h>
+
+#include "iomap.h"
 #include "clock.h"
 #include "opp.h"
 
diff --git a/arch/arm/mach-omap1/clock_data.c b/arch/arm/mach-omap1/clock_data.c
index 94699a82a73..c6ce93f71d0 100644
--- a/arch/arm/mach-omap1/clock_data.c
+++ b/arch/arm/mach-omap1/clock_data.c
@@ -15,10 +15,10 @@
  */
 
 #include <linux/kernel.h>
+#include <linux/io.h>
 #include <linux/clk.h>
 #include <linux/cpufreq.h>
 #include <linux/delay.h>
-#include <linux/io.h>
 
 #include <asm/mach-types.h>  /* for machine_is_* */
 
@@ -28,6 +28,9 @@
 #include <plat/sram.h>  /* for omap_sram_reprogram_clock() */
 #include <plat/usb.h>   /* for OTG_BASE */
 
+#include <mach/hardware.h>
+
+#include "iomap.h"
 #include "clock.h"
 
 /* Some ARM_IDLECT1 bit shifts - used in struct arm_idlect1_clk */
diff --git a/arch/arm/mach-omap1/common.h b/arch/arm/mach-omap1/common.h
index a9a5146dd2d..af658ad338e 100644
--- a/arch/arm/mach-omap1/common.h
+++ b/arch/arm/mach-omap1/common.h
@@ -58,5 +58,6 @@ void omap1_restart(char, const char *);
 
 extern struct sys_timer omap1_timer;
 extern bool omap_32k_timer_init(void);
+extern void __init omap_init_consistent_dma_size(void);
 
 #endif /* __ARCH_ARM_MACH_OMAP1_COMMON_H */
diff --git a/arch/arm/mach-omap1/devices.c b/arch/arm/mach-omap1/devices.c
index 1d76a63c098..dcd8ddbec2b 100644
--- a/arch/arm/mach-omap1/devices.c
+++ b/arch/arm/mach-omap1/devices.c
@@ -15,21 +15,20 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/platform_device.h>
-#include <linux/io.h>
 #include <linux/spi/spi.h>
 
-#include <mach/camera.h>
-#include <mach/hardware.h>
 #include <asm/mach/map.h>
 
-#include "common.h"
 #include <plat/tc.h>
 #include <plat/board.h>
 #include <plat/mux.h>
 #include <plat/mmc.h>
 #include <plat/omap7xx.h>
-#include <plat/mcbsp.h>
 
+#include <mach/camera.h>
+#include <mach/hardware.h>
+
+#include "common.h"
 #include "clock.h"
 
 /*-------------------------------------------------------------------------*/
@@ -250,16 +249,8 @@ static struct platform_device omap_pcm = {
         .id     = -1,
 };
 
-OMAP_MCBSP_PLATFORM_DEVICE(1);
-OMAP_MCBSP_PLATFORM_DEVICE(2);
-OMAP_MCBSP_PLATFORM_DEVICE(3);
-
 static void omap_init_audio(void)
 {
-        platform_device_register(&omap_mcbsp1);
-        platform_device_register(&omap_mcbsp2);
-        if (!cpu_is_omap7xx())
-                platform_device_register(&omap_mcbsp3);
         platform_device_register(&omap_pcm);
 }
 
diff --git a/arch/arm/mach-omap1/dma.c b/arch/arm/mach-omap1/dma.c
index f5a52204b89..3ef7d52316b 100644
--- a/arch/arm/mach-omap1/dma.c
+++ b/arch/arm/mach-omap1/dma.c
@@ -19,11 +19,11 @@
  */
 
 #include <linux/err.h>
-#include <linux/io.h>
 #include <linux/slab.h>
 #include <linux/module.h>
 #include <linux/init.h>
 #include <linux/device.h>
+#include <linux/io.h>
 
 #include <plat/dma.h>
 #include <plat/tc.h>
diff --git a/arch/arm/mach-omap1/flash.c b/arch/arm/mach-omap1/flash.c
index 1749cb37dda..f9bf78d4fdf 100644
--- a/arch/arm/mach-omap1/flash.c
+++ b/arch/arm/mach-omap1/flash.c
@@ -6,13 +6,15 @@
  * published by the Free Software Foundation.
  */
 
+#include <linux/io.h>
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/map.h>
 
-#include <plat/io.h>
 #include <plat/tc.h>
 #include <plat/flash.h>
 
+#include <mach/hardware.h>
+
 void omap1_set_vpp(struct platform_device *pdev, int enable)
 {
         static int count;
diff --git a/arch/arm/mach-omap1/fpga.c b/arch/arm/mach-omap1/fpga.c
index 0a17a1a7e00..76c67b3f9f6 100644
--- a/arch/arm/mach-omap1/fpga.c
+++ b/arch/arm/mach-omap1/fpga.c
@@ -24,12 +24,15 @@
 #include <linux/errno.h>
 #include <linux/io.h>
 
-#include <mach/hardware.h>
 #include <asm/irq.h>
 #include <asm/mach/irq.h>
 
 #include <plat/fpga.h>
 
+#include <mach/hardware.h>
+
+#include "iomap.h"
+
 static void fpga_mask_irq(struct irq_data *d)
 {
         unsigned int irq = d->irq - OMAP_FPGA_IRQ_BASE;
diff --git a/arch/arm/mach-omap1/gpio15xx.c b/arch/arm/mach-omap1/gpio15xx.c
index 399da4ce017..634903ef829 100644
--- a/arch/arm/mach-omap1/gpio15xx.c
+++ b/arch/arm/mach-omap1/gpio15xx.c
@@ -42,11 +42,12 @@ static struct omap_gpio_reg_offs omap15xx_mpuio_regs = {
         .irqstatus      = OMAP_MPUIO_GPIO_INT,
         .irqenable      = OMAP_MPUIO_GPIO_MASKIT,
         .irqenable_inv  = true,
+        .irqctrl        = OMAP_MPUIO_GPIO_INT_EDGE,
 };
 
 static struct __initdata omap_gpio_platform_data omap15xx_mpu_gpio_config = {
         .virtual_irq_start      = IH_MPUIO_BASE,
-        .bank_type              = METHOD_MPUIO,
+        .is_mpuio               = true,
         .bank_width             = 16,
         .bank_stride            = 1,
         .regs                   = &omap15xx_mpuio_regs,
@@ -83,11 +84,12 @@ static struct omap_gpio_reg_offs omap15xx_gpio_regs = {
         .irqstatus      = OMAP1510_GPIO_INT_STATUS,
         .irqenable      = OMAP1510_GPIO_INT_MASK,
         .irqenable_inv  = true,
+        .irqctrl        = OMAP1510_GPIO_INT_CONTROL,
+        .pinctrl        = OMAP1510_GPIO_PIN_CONTROL,
 };
 
 static struct __initdata omap_gpio_platform_data omap15xx_gpio_config = {
         .virtual_irq_start      = IH_GPIO_BASE,
-        .bank_type              = METHOD_GPIO_1510,
         .bank_width             = 16,
         .regs                   = &omap15xx_gpio_regs,
 };
@@ -115,7 +117,6 @@ static int __init omap15xx_gpio_init(void)
         platform_device_register(&omap15xx_mpu_gpio);
         platform_device_register(&omap15xx_gpio);
 
-        gpio_bank_count = 2;
         return 0;
 }
 postcore_initcall(omap15xx_gpio_init);
diff --git a/arch/arm/mach-omap1/gpio16xx.c b/arch/arm/mach-omap1/gpio16xx.c
index 0f399bd0e70..1fb3b9ad496 100644
--- a/arch/arm/mach-omap1/gpio16xx.c
+++ b/arch/arm/mach-omap1/gpio16xx.c
@@ -24,6 +24,9 @@
 #define OMAP1610_GPIO4_BASE             0xfffbbc00
 #define OMAP1_MPUIO_VBASE               OMAP1_MPUIO_BASE
 
+/* smart idle, enable wakeup */
+#define SYSCONFIG_WORD                  0x14
+
 /* mpu gpio */
 static struct __initdata resource omap16xx_mpu_gpio_resources[] = {
         {
@@ -45,11 +48,12 @@ static struct omap_gpio_reg_offs omap16xx_mpuio_regs = {
         .irqstatus      = OMAP_MPUIO_GPIO_INT,
         .irqenable      = OMAP_MPUIO_GPIO_MASKIT,
         .irqenable_inv  = true,
+        .irqctrl        = OMAP_MPUIO_GPIO_INT_EDGE,
 };
 
 static struct __initdata omap_gpio_platform_data omap16xx_mpu_gpio_config = {
         .virtual_irq_start      = IH_MPUIO_BASE,
-        .bank_type              = METHOD_MPUIO,
+        .is_mpuio               = true,
         .bank_width             = 16,
         .bank_stride            = 1,
         .regs                   = &omap16xx_mpuio_regs,
@@ -89,11 +93,13 @@ static struct omap_gpio_reg_offs omap16xx_gpio_regs = {
         .irqenable      = OMAP1610_GPIO_IRQENABLE1,
         .set_irqenable  = OMAP1610_GPIO_SET_IRQENABLE1,
         .clr_irqenable  = OMAP1610_GPIO_CLEAR_IRQENABLE1,
+        .wkup_en        = OMAP1610_GPIO_WAKEUPENABLE,
+        .edgectrl1      = OMAP1610_GPIO_EDGE_CTRL1,
+        .edgectrl2      = OMAP1610_GPIO_EDGE_CTRL2,
 };
 
 static struct __initdata omap_gpio_platform_data omap16xx_gpio1_config = {
         .virtual_irq_start      = IH_GPIO_BASE,
-        .bank_type              = METHOD_GPIO_1610,
         .bank_width             = 16,
         .regs                   = &omap16xx_gpio_regs,
 };
@@ -123,7 +129,6 @@ static struct __initdata resource omap16xx_gpio2_resources[] = {
 
 static struct __initdata omap_gpio_platform_data omap16xx_gpio2_config = {
         .virtual_irq_start      = IH_GPIO_BASE + 16,
-        .bank_type              = METHOD_GPIO_1610,
         .bank_width             = 16,
         .regs                   = &omap16xx_gpio_regs,
 };
@@ -153,7 +158,6 @@ static struct __initdata resource omap16xx_gpio3_resources[] = {
 
 static struct __initdata omap_gpio_platform_data omap16xx_gpio3_config = {
         .virtual_irq_start      = IH_GPIO_BASE + 32,
-        .bank_type              = METHOD_GPIO_1610,
         .bank_width             = 16,
         .regs                   = &omap16xx_gpio_regs,
 };
@@ -183,7 +187,6 @@ static struct __initdata resource omap16xx_gpio4_resources[] = {
 
 static struct __initdata omap_gpio_platform_data omap16xx_gpio4_config = {
         .virtual_irq_start      = IH_GPIO_BASE + 48,
-        .bank_type              = METHOD_GPIO_1610,
         .bank_width             = 16,
         .regs                   = &omap16xx_gpio_regs,
 };
@@ -214,14 +217,42 @@ static struct __initdata platform_device * omap16xx_gpio_dev[] = {
 static int __init omap16xx_gpio_init(void)
 {
         int i;
+        void __iomem *base;
+        struct resource *res;
+        struct platform_device *pdev;
+        struct omap_gpio_platform_data *pdata;
 
         if (!cpu_is_omap16xx())
                 return -EINVAL;
 
-        for (i = 0; i < ARRAY_SIZE(omap16xx_gpio_dev); i++)
-                platform_device_register(omap16xx_gpio_dev[i]);
+        /*
+         * Enable system clock for GPIO module.
+         * The CAM_CLK_CTRL *is* really the right place.
+         */
+        omap_writel(omap_readl(ULPD_CAM_CLK_CTRL) | 0x04,
+                                        ULPD_CAM_CLK_CTRL);
+
+        for (i = 0; i < ARRAY_SIZE(omap16xx_gpio_dev); i++) {
+                pdev = omap16xx_gpio_dev[i];
+                pdata = pdev->dev.platform_data;
+
+                res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+                if (unlikely(!res)) {
+                        dev_err(&pdev->dev, "Invalid mem resource.\n");
+                        return -ENODEV;
+                }
 
-        gpio_bank_count = ARRAY_SIZE(omap16xx_gpio_dev);
+                base = ioremap(res->start, resource_size(res));
+                if (unlikely(!base)) {
+                        dev_err(&pdev->dev, "ioremap failed.\n");
+                        return -ENOMEM;
+                }
+
+                __raw_writel(SYSCONFIG_WORD, base + OMAP1610_GPIO_SYSCONFIG);
+                iounmap(base);
+
+                platform_device_register(omap16xx_gpio_dev[i]);
+        }
 
         return 0;
 }
diff --git a/arch/arm/mach-omap1/gpio7xx.c b/arch/arm/mach-omap1/gpio7xx.c
index 5ab63eab0ff..4771d6b68b9 100644
--- a/arch/arm/mach-omap1/gpio7xx.c
+++ b/arch/arm/mach-omap1/gpio7xx.c
@@ -47,12 +47,13 @@ static struct omap_gpio_reg_offs omap7xx_mpuio_regs = {
         .irqstatus      = OMAP_MPUIO_GPIO_INT / 2,
         .irqenable      = OMAP_MPUIO_GPIO_MASKIT / 2,
         .irqenable_inv  = true,
+        .irqctrl        = OMAP_MPUIO_GPIO_INT_EDGE >> 1,
 };
 
 static struct __initdata omap_gpio_platform_data omap7xx_mpu_gpio_config = {
         .virtual_irq_start      = IH_MPUIO_BASE,
-        .bank_type              = METHOD_MPUIO,
-        .bank_width             = 32,
+        .is_mpuio               = true,
+        .bank_width             = 16,
         .bank_stride            = 2,
         .regs                   = &omap7xx_mpuio_regs,
 };
@@ -88,11 +89,11 @@ static struct omap_gpio_reg_offs omap7xx_gpio_regs = {
         .irqstatus      = OMAP7XX_GPIO_INT_STATUS,
         .irqenable      = OMAP7XX_GPIO_INT_MASK,
         .irqenable_inv  = true,
+        .irqctrl        = OMAP7XX_GPIO_INT_CONTROL,
 };
 
 static struct __initdata omap_gpio_platform_data omap7xx_gpio1_config = {
         .virtual_irq_start      = IH_GPIO_BASE,
-        .bank_type              = METHOD_GPIO_7XX,
         .bank_width             = 32,
         .regs                   = &omap7xx_gpio_regs,
 };
@@ -122,7 +123,6 @@ static struct __initdata resource omap7xx_gpio2_resources[] = {
 
 static struct __initdata omap_gpio_platform_data omap7xx_gpio2_config = {
         .virtual_irq_start      = IH_GPIO_BASE + 32,
-        .bank_type              = METHOD_GPIO_7XX,
         .bank_width             = 32,
         .regs                   = &omap7xx_gpio_regs,
 };
@@ -152,7 +152,6 @@ static struct __initdata resource omap7xx_gpio3_resources[] = {
 
 static struct __initdata omap_gpio_platform_data omap7xx_gpio3_config = {
         .virtual_irq_start      = IH_GPIO_BASE + 64,
-        .bank_type              = METHOD_GPIO_7XX,
         .bank_width             = 32,
         .regs                   = &omap7xx_gpio_regs,
 };
@@ -182,7 +181,6 @@ static struct __initdata resource omap7xx_gpio4_resources[] = {
 
 static struct __initdata omap_gpio_platform_data omap7xx_gpio4_config = {
         .virtual_irq_start      = IH_GPIO_BASE + 96,
-        .bank_type              = METHOD_GPIO_7XX,
         .bank_width             = 32,
         .regs                   = &omap7xx_gpio_regs,
 };
@@ -212,7 +210,6 @@ static struct __initdata resource omap7xx_gpio5_resources[] = {
 
 static struct __initdata omap_gpio_platform_data omap7xx_gpio5_config = {
         .virtual_irq_start      = IH_GPIO_BASE + 128,
-        .bank_type              = METHOD_GPIO_7XX,
         .bank_width             = 32,
         .regs                   = &omap7xx_gpio_regs,
 };
@@ -242,7 +239,6 @@ static struct __initdata resource omap7xx_gpio6_resources[] = {
 
 static struct __initdata omap_gpio_platform_data omap7xx_gpio6_config = {
         .virtual_irq_start      = IH_GPIO_BASE + 160,
-        .bank_type              = METHOD_GPIO_7XX,
         .bank_width             = 32,
         .regs                   = &omap7xx_gpio_regs,
 };
@@ -282,8 +278,6 @@ static int __init omap7xx_gpio_init(void)
         for (i = 0; i < ARRAY_SIZE(omap7xx_gpio_dev); i++)
                 platform_device_register(omap7xx_gpio_dev[i]);
 
-        gpio_bank_count = ARRAY_SIZE(omap7xx_gpio_dev);
-
         return 0;
 }
 postcore_initcall(omap7xx_gpio_init);
diff --git a/arch/arm/mach-omap1/id.c b/arch/arm/mach-omap1/id.c
index a0e3560b39d..f24c1e2c504 100644
--- a/arch/arm/mach-omap1/id.c
+++ b/arch/arm/mach-omap1/id.c
@@ -15,8 +15,11 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/io.h>
+
 #include <plat/cpu.h>
 
+#include <mach/hardware.h>
+
 #define OMAP_DIE_ID_0           0xfffe1800
 #define OMAP_DIE_ID_1           0xfffe1804
 #define OMAP_PRODUCTION_ID_0    0xfffe2000
diff --git a/arch/arm/mach-omap1/include/mach/entry-macro.S b/arch/arm/mach-omap1/include/mach/entry-macro.S
index bfb4fb1d738..fa0f32a686a 100644
--- a/arch/arm/mach-omap1/include/mach/entry-macro.S
+++ b/arch/arm/mach-omap1/include/mach/entry-macro.S
@@ -9,20 +9,16 @@
  * License version 2. This program is licensed "as is" without any
  * warranty of any kind, whether express or implied.
  */
+
 #include <mach/hardware.h>
 #include <mach/io.h>
 #include <mach/irqs.h>
-#include <asm/hardware/gic.h>
 
-                .macro  disable_fiq
-                .endm
+#include "../../iomap.h"
 
                 .macro  get_irqnr_preamble, base, tmp
                 .endm
 
-                .macro  arch_ret_to_user, tmp1, tmp2
-                .endm
-
                 .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
                 ldr     \base, =OMAP1_IO_ADDRESS(OMAP_IH1_BASE)
                 ldr     \irqnr, [\base, #IRQ_ITR_REG_OFFSET]
diff --git a/arch/arm/mach-omap1/include/mach/hardware.h b/arch/arm/mach-omap1/include/mach/hardware.h
index a3f6287b200..01e35fa106b 100644
--- a/arch/arm/mach-omap1/include/mach/hardware.h
+++ b/arch/arm/mach-omap1/include/mach/hardware.h
@@ -2,4 +2,40 @@
  * arch/arm/mach-omap1/include/mach/hardware.h
  */
 
+#ifndef __MACH_HARDWARE_H
+#define __MACH_HARDWARE_H
+
+#ifndef __ASSEMBLER__
+/*
+ * NOTE: Please use ioremap + __raw_read/write where possible instead of these
+ */
+extern u8 omap_readb(u32 pa);
+extern u16 omap_readw(u32 pa);
+extern u32 omap_readl(u32 pa);
+extern void omap_writeb(u8 v, u32 pa);
+extern void omap_writew(u16 v, u32 pa);
+extern void omap_writel(u32 v, u32 pa);
+
+#include <plat/tc.h>
+
+/* Almost all documentation for chip and board memory maps assumes
+ * BM is clear.  Most devel boards have a switch to control booting
+ * from NOR flash (using external chipselect 3) rather than mask ROM,
+ * which uses BM to interchange the physical CS0 and CS3 addresses.
+ */
+static inline u32 omap_cs0m_phys(void)
+{
+        return (omap_readl(EMIFS_CONFIG) & OMAP_EMIFS_CONFIG_BM)
+                        ?  OMAP_CS3_PHYS : 0;
+}
+
+static inline u32 omap_cs3_phys(void)
+{
+        return (omap_readl(EMIFS_CONFIG) & OMAP_EMIFS_CONFIG_BM)
+                        ? 0 : OMAP_CS3_PHYS;
+}
+
+#endif
+#endif
+
 #include <plat/hardware.h>
diff --git a/arch/arm/mach-omap1/include/mach/io.h b/arch/arm/mach-omap1/include/mach/io.h
index 57bdf74a3e6..37b12e1fd02 100644
--- a/arch/arm/mach-omap1/include/mach/io.h
+++ b/arch/arm/mach-omap1/include/mach/io.h
@@ -1,5 +1,46 @@
 /*
  * arch/arm/mach-omap1/include/mach/io.h
+ *
+ * IO definitions for TI OMAP processors and boards
+ *
+ * Copied from arch/arm/mach-sa1100/include/mach/io.h
+ * Copyright (C) 1997-1999 Russell King
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ * Modifications:
+ *  06-12-1997  RMK     Created.
+ *  07-04-1999  RMK     Major cleanup
  */
 
-#include <plat/io.h>
+#ifndef __ASM_ARM_ARCH_IO_H
+#define __ASM_ARM_ARCH_IO_H
+
+#define IO_SPACE_LIMIT 0xffffffff
+
+/*
+ * We don't actually have real ISA nor PCI buses, but there is so many
+ * drivers out there that might just work if we fake them...
+ */
+#define __io(a)         __typesafe_io(a)
+#define __mem_pci(a)    (a)
+
+#endif
diff --git a/arch/arm/mach-omap1/include/mach/memory.h b/arch/arm/mach-omap1/include/mach/memory.h
index c6337645ba8..901082def9b 100644
--- a/arch/arm/mach-omap1/include/mach/memory.h
+++ b/arch/arm/mach-omap1/include/mach/memory.h
@@ -18,7 +18,8 @@
  * Note that the is_lbus_device() test is not very efficient on 1510
  * because of the strncmp().
  */
-#ifdef CONFIG_ARCH_OMAP15XX
+#if defined(CONFIG_ARCH_OMAP15XX) && !defined(__ASSEMBLER__)
+#include <plat/cpu.h>
 
 /*
  * OMAP-1510 Local Bus address offset
diff --git a/arch/arm/mach-omap1/include/mach/system.h b/arch/arm/mach-omap1/include/mach/system.h
deleted file mode 100644
index a6c1b3a16df..00000000000
--- a/arch/arm/mach-omap1/include/mach/system.h
+++ /dev/null
@@ -1,5 +0,0 @@
-/*
- * arch/arm/mach-omap1/include/mach/system.h
- */
-
-#include <plat/system.h>
diff --git a/arch/arm/mach-omap1/io.c b/arch/arm/mach-omap1/io.c
index 8e55b6fb347..d969a7203d1 100644
--- a/arch/arm/mach-omap1/io.c
+++ b/arch/arm/mach-omap1/io.c
@@ -15,9 +15,12 @@
 
 #include <asm/tlb.h>
 #include <asm/mach/map.h>
+
 #include <plat/mux.h>
 #include <plat/tc.h>
 
+#include "iomap.h"
+#include "common.h"
 #include "clock.h"
 
 extern void omap_check_revision(void);
@@ -118,7 +121,7 @@ void __init omap16xx_map_io(void)
 /*
  * Common low-level hardware init for omap1.
  */
-void omap1_init_early(void)
+void __init omap1_init_early(void)
 {
         omap_check_revision();
 
diff --git a/arch/arm/mach-omap1/iomap.h b/arch/arm/mach-omap1/iomap.h
new file mode 100644
index 00000000000..d68175761c3
--- /dev/null
+++ b/arch/arm/mach-omap1/iomap.h
@@ -0,0 +1,42 @@
+/*
+ * IO mappings for OMAP1
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * You should have received a copy of the  GNU General Public License along
+ * with this program; if not, write  to the Free Software Foundation, Inc.,
+ * 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifdef __ASSEMBLER__
+#define IOMEM(x)                (x)
+#else
+#define IOMEM(x)                ((void __force __iomem *)(x))
+#endif
+
+#define OMAP1_IO_OFFSET         0x01000000      /* Virtual IO = 0xfefb0000 */
+#define OMAP1_IO_ADDRESS(pa)    IOMEM((pa) - OMAP1_IO_OFFSET)
+
+/*
+ * ----------------------------------------------------------------------------
+ * Omap1 specific IO mapping
+ * ----------------------------------------------------------------------------
+ */
+
+#define OMAP1_IO_PHYS           0xFFFB0000
+#define OMAP1_IO_SIZE           0x40000
+#define OMAP1_IO_VIRT           (OMAP1_IO_PHYS - OMAP1_IO_OFFSET)
diff --git a/arch/arm/mach-omap1/irq.c b/arch/arm/mach-omap1/irq.c
index e5b104b7fce..4448114fab7 100644
--- a/arch/arm/mach-omap1/irq.c
+++ b/arch/arm/mach-omap1/irq.c
@@ -42,11 +42,13 @@
 #include <linux/interrupt.h>
 #include <linux/io.h>
 
-#include <mach/hardware.h>
 #include <asm/irq.h>
 #include <asm/mach/irq.h>
+
 #include <plat/cpu.h>
 
+#include <mach/hardware.h>
+
 #define IRQ_BANK(irq) ((irq) >> 5)
 #define IRQ_BIT(irq)  ((irq) & 0x1f)
 
diff --git a/arch/arm/mach-omap1/lcd_dma.c b/arch/arm/mach-omap1/lcd_dma.c
index 4c5ce7d829c..86ace9aaa66 100644
--- a/arch/arm/mach-omap1/lcd_dma.c
+++ b/arch/arm/mach-omap1/lcd_dma.c
@@ -27,9 +27,10 @@
 #include <linux/interrupt.h>
 #include <linux/io.h>
 
+#include <plat/dma.h>
+
 #include <mach/hardware.h>
 #include <mach/lcdc.h>
-#include <plat/dma.h>
 
 int omap_lcd_dma_running(void)
 {
diff --git a/arch/arm/mach-omap1/mcbsp.c b/arch/arm/mach-omap1/mcbsp.c
index 91f9abbd325..adf00975b9b 100644
--- a/arch/arm/mach-omap1/mcbsp.c
+++ b/arch/arm/mach-omap1/mcbsp.c
@@ -19,12 +19,15 @@
 #include <linux/platform_device.h>
 #include <linux/slab.h>
 
-#include <mach/irqs.h>
 #include <plat/dma.h>
 #include <plat/mux.h>
 #include <plat/cpu.h>
 #include <plat/mcbsp.h>
 
+#include <mach/irqs.h>
+
+#include "iomap.h"
+
 #define DPS_RSTCT2_PER_EN       (1 << 0)
 #define DSP_RSTCT2_WD_PER_EN    (1 << 1)
 
@@ -420,18 +423,6 @@ static int __init omap1_mcbsp_init(void)
                 return -ENODEV;
 
         if (cpu_is_omap7xx())
-                omap_mcbsp_count = OMAP7XX_MCBSP_COUNT;
-        else if (cpu_is_omap15xx())
-                omap_mcbsp_count = OMAP15XX_MCBSP_COUNT;
-        else if (cpu_is_omap16xx())
-                omap_mcbsp_count = OMAP16XX_MCBSP_COUNT;
-
-        mcbsp_ptr = kzalloc(omap_mcbsp_count * sizeof(struct omap_mcbsp *),
-                                                                GFP_KERNEL);
-        if (!mcbsp_ptr)
-                return -ENOMEM;
-
-        if (cpu_is_omap7xx())
                 omap_mcbsp_register_board_cfg(omap7xx_mcbsp_res_0,
                                         OMAP7XX_MCBSP_RES_SZ,
                                         omap7xx_mcbsp_pdata,
@@ -449,7 +440,7 @@ static int __init omap1_mcbsp_init(void)
                                         omap16xx_mcbsp_pdata,
                                         OMAP16XX_MCBSP_COUNT);
 
-        return omap_mcbsp_init();
+        return 0;
 }
 
 arch_initcall(omap1_mcbsp_init);
diff --git a/arch/arm/mach-omap1/pm.c b/arch/arm/mach-omap1/pm.c
index 89ea20ca0cc..306beaca14c 100644
--- a/arch/arm/mach-omap1/pm.c
+++ b/arch/arm/mach-omap1/pm.c
@@ -42,14 +42,13 @@
 #include <linux/sysfs.h>
 #include <linux/module.h>
 #include <linux/io.h>
+#include <linux/atomic.h>
 
 #include <asm/irq.h>
-#include <linux/atomic.h>
 #include <asm/mach/time.h>
 #include <asm/mach/irq.h>
 
 #include <plat/cpu.h>
-#include <mach/irqs.h>
 #include <plat/clock.h>
 #include <plat/sram.h>
 #include <plat/tc.h>
@@ -57,6 +56,9 @@
 #include <plat/dma.h>
 #include <plat/dmtimer.h>
 
+#include <mach/irqs.h>
+
+#include "iomap.h"
 #include "pm.h"
 
 static unsigned int arm_sleep_save[ARM_SLEEP_SAVE_SIZE];
@@ -108,13 +110,7 @@ void omap1_pm_idle(void)
         __u32 use_idlect1 = arm_idlect1_mask;
         int do_sleep = 0;
 
-        local_irq_disable();
         local_fiq_disable();
-        if (need_resched()) {
-                local_fiq_enable();
-                local_irq_enable();
-                return;
-        }
 
 #if defined(CONFIG_OMAP_MPU_TIMER) && !defined(CONFIG_OMAP_DM_TIMER)
 #warning Enable 32kHz OS timer in order to allow sleep states in idle
@@ -157,14 +153,12 @@ void omap1_pm_idle(void)
                 omap_writel(saved_idlect1, ARM_IDLECT1);
 
                 local_fiq_enable();
-                local_irq_enable();
                 return;
         }
         omap_sram_suspend(omap_readl(ARM_IDLECT1),
                           omap_readl(ARM_IDLECT2));
 
         local_fiq_enable();
-        local_irq_enable();
 }
 
 /*
@@ -583,8 +577,6 @@ static void omap_pm_init_proc(void)
 
 #endif /* DEBUG && CONFIG_PROC_FS */
 
-static void (*saved_idle)(void) = NULL;
-
 /*
  *      omap_pm_prepare - Do preliminary suspend work.
  *
@@ -592,8 +584,7 @@ static void (*saved_idle)(void) = NULL;
 static int omap_pm_prepare(void)
 {
         /* We cannot sleep in idle until we have resumed */
-        saved_idle = pm_idle;
-        pm_idle = NULL;
+        disable_hlt();
 
         return 0;
 }
@@ -630,7 +621,7 @@ static int omap_pm_enter(suspend_state_t state)
 
 static void omap_pm_finish(void)
 {
-        pm_idle = saved_idle;
+        enable_hlt();
 }
 
 
@@ -687,7 +678,7 @@ static int __init omap_pm_init(void)
                 return -ENODEV;
         }
 
-        pm_idle = omap1_pm_idle;
+        arm_pm_idle = omap1_pm_idle;
 
         if (cpu_is_omap7xx())
                 setup_irq(INT_7XX_WAKE_UP_REQ, &omap_wakeup_irq);
diff --git a/arch/arm/mach-omap1/reset.c b/arch/arm/mach-omap1/reset.c
index 91d199b6497..f255b153b86 100644
--- a/arch/arm/mach-omap1/reset.c
+++ b/arch/arm/mach-omap1/reset.c
@@ -4,9 +4,10 @@
 #include <linux/kernel.h>
 #include <linux/io.h>
 
-#include <mach/hardware.h>
 #include <plat/prcm.h>
 
+#include <mach/hardware.h>
+
 void omap1_restart(char mode, const char *cmd)
 {
         /*
diff --git a/arch/arm/mach-omap1/sleep.S b/arch/arm/mach-omap1/sleep.S
index c875bdc902c..0779db150da 100644
--- a/arch/arm/mach-omap1/sleep.S
+++ b/arch/arm/mach-omap1/sleep.S
@@ -33,8 +33,12 @@
  */
 
 #include <linux/linkage.h>
+
 #include <asm/assembler.h>
+
 #include <mach/io.h>
+
+#include "iomap.h"
 #include "pm.h"
 
                 .text
diff --git a/arch/arm/mach-omap1/sram.S b/arch/arm/mach-omap1/sram.S
index 692587d07ea..2ce0b9ab20e 100644
--- a/arch/arm/mach-omap1/sram.S
+++ b/arch/arm/mach-omap1/sram.S
@@ -9,10 +9,14 @@
  */
 
 #include <linux/linkage.h>
+
 #include <asm/assembler.h>
+
 #include <mach/io.h>
 #include <mach/hardware.h>
 
+#include "iomap.h"
+
         .text
 
 /*
diff --git a/arch/arm/mach-omap1/time.c b/arch/arm/mach-omap1/time.c
index b8faffa44f9..2fae6a2740f 100644
--- a/arch/arm/mach-omap1/time.c
+++ b/arch/arm/mach-omap1/time.c
@@ -45,14 +45,15 @@
 #include <linux/io.h>
 
 #include <asm/system.h>
-#include <mach/hardware.h>
 #include <asm/leds.h>
 #include <asm/irq.h>
 #include <asm/sched_clock.h>
 
+#include <mach/hardware.h>
 #include <asm/mach/irq.h>
 #include <asm/mach/time.h>
 
+#include "iomap.h"
 #include "common.h"
 
 #ifdef CONFIG_OMAP_MPU_TIMER
diff --git a/arch/arm/mach-omap1/timer32k.c b/arch/arm/mach-omap1/timer32k.c
index 9a54ef4dcf5..a2e6d0709df 100644
--- a/arch/arm/mach-omap1/timer32k.c
+++ b/arch/arm/mach-omap1/timer32k.c
@@ -47,14 +47,17 @@
 #include <linux/io.h>
 
 #include <asm/system.h>
-#include <mach/hardware.h>
 #include <asm/leds.h>
 #include <asm/irq.h>
 #include <asm/mach/irq.h>
 #include <asm/mach/time.h>
-#include "common.h"
+
 #include <plat/dmtimer.h>
 
+#include <mach/hardware.h>
+
+#include "common.h"
+
 /*
  * ---------------------------------------------------------------------------
  * 32KHz OS timer
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index e20c8ab80b0..8141b76283a 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -32,7 +32,7 @@ config ARCH_OMAP3
         depends on ARCH_OMAP2PLUS
         default y
         select CPU_V7
-        select USB_ARCH_HAS_EHCI
+        select USB_ARCH_HAS_EHCI if USB_SUPPORT
         select ARCH_HAS_OPP
         select PM_OPP if PM
         select ARM_CPU_SUSPEND if PM
@@ -52,7 +52,7 @@ config ARCH_OMAP4
         select ARM_ERRATA_720789
         select ARCH_HAS_OPP
         select PM_OPP if PM
-        select USB_ARCH_HAS_EHCI
+        select USB_ARCH_HAS_EHCI if USB_SUPPORT
         select ARM_CPU_SUSPEND if PM
 
 comment "OMAP Core Type"
@@ -117,7 +117,6 @@ comment "OMAP Board Type"
 config MACH_OMAP_GENERIC
         bool "Generic OMAP2+ board"
         depends on ARCH_OMAP2PLUS
-        select USE_OF
         default y
         help
           Support for generic TI OMAP2+ boards using Flattened Device Tree.
@@ -245,10 +244,11 @@ config MACH_NOKIA_N8X0
         select MACH_NOKIA_N810_WIMAX
 
 config MACH_NOKIA_RM680
-        bool "Nokia RM-680 board"
+        bool "Nokia RM-680/696 board"
         depends on ARCH_OMAP3
         default y
         select OMAP_PACKAGE_CBB
+        select MACH_NOKIA_RM696
 
 config MACH_NOKIA_RX51
         bool "Nokia RX-51 board"
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index bd76394ccaf..49f92bc1c31 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -4,7 +4,7 @@
 
 # Common support
 obj-y := id.o io.o control.o mux.o devices.o serial.o gpmc.o timer.o pm.o \
-         common.o gpio.o dma.o wd_timer.o display.o
+         common.o gpio.o dma.o wd_timer.o display.o i2c.o
 
 omap-2-3-common                         = irq.o sdrc.o
 hwmod-common                            = omap_hwmod.o \
@@ -17,13 +17,14 @@ obj-$(CONFIG_ARCH_OMAP2) += $(omap-2-3-common) $(hwmod-common)
 obj-$(CONFIG_ARCH_OMAP3) += $(omap-2-3-common) $(hwmod-common) $(secure-common)
 obj-$(CONFIG_ARCH_OMAP4) += prm44xx.o $(hwmod-common) $(secure-common)
 
-obj-$(CONFIG_OMAP_MCBSP) += mcbsp.o
+ifneq ($(CONFIG_SND_OMAP_SOC_MCBSP),)
+obj-y += mcbsp.o
+endif
 
 obj-$(CONFIG_TWL4030_CORE) += omap_twl.o
 
 # SMP support ONLY available for OMAP4
 obj-$(CONFIG_SMP)                       += omap-smp.o omap-headsmp.o
-obj-$(CONFIG_LOCAL_TIMERS)              += timer-mpu.o
 obj-$(CONFIG_HOTPLUG_CPU)               += omap-hotplug.o
 obj-$(CONFIG_ARCH_OMAP4)                += omap4-common.o omap-wakeupgen.o \
                                            sleep44xx.o
@@ -182,9 +183,6 @@ obj-$(CONFIG_OMAP_IOMMU)		+= iommu2.o
 iommu-$(CONFIG_OMAP_IOMMU)              := omap-iommu.o
 obj-y                                   += $(iommu-m) $(iommu-y)
 
-i2c-omap-$(CONFIG_I2C_OMAP)             := i2c.o
-obj-y                                   += $(i2c-omap-m) $(i2c-omap-y)
-
 ifneq ($(CONFIG_TIDSPBRIDGE),)
 obj-y                                   += dsp.o
 endif
@@ -268,6 +266,11 @@ obj-y					+= $(smc91x-m) $(smc91x-y)
 
 smsc911x-$(CONFIG_SMSC911X)             := gpmc-smsc911x.o
 obj-y                                   += $(smsc911x-m) $(smsc911x-y)
-obj-$(CONFIG_ARCH_OMAP4)                += hwspinlock.o
+ifneq ($(CONFIG_HWSPINLOCK_OMAP),)
+obj-y                                   += hwspinlock.o
+endif
+
+emac-$(CONFIG_TI_DAVINCI_EMAC)          := am35xx-emac.o
+obj-y                                   += $(emac-m) $(emac-y)
 
 obj-y                                   += common-board-devices.o twl-common.o
diff --git a/arch/arm/mach-omap2/am35xx-emac.c b/arch/arm/mach-omap2/am35xx-emac.c
new file mode 100644
index 00000000000..1f97e747520
--- /dev/null
+++ b/arch/arm/mach-omap2/am35xx-emac.c
@@ -0,0 +1,117 @@
+/*
+ * Copyright (C) 2011 Ilya Yanok, Emcraft Systems
+ *
+ * Based on mach-omap2/board-am3517evm.c
+ * Copyright (C) 2009 Texas Instruments Incorporated
+ * Author: Ranjith Lohithakshan <ranjithl@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any kind,
+ * whether express or implied; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ */
+
+#include <linux/clk.h>
+#include <linux/davinci_emac.h>
+#include <linux/platform_device.h>
+#include <plat/irqs.h>
+#include <mach/am35xx.h>
+
+#include "control.h"
+
+static struct mdio_platform_data am35xx_emac_mdio_pdata;
+
+static struct resource am35xx_emac_mdio_resources[] = {
+        DEFINE_RES_MEM(AM35XX_IPSS_EMAC_BASE + AM35XX_EMAC_MDIO_OFFSET, SZ_4K),
+};
+
+static struct platform_device am35xx_emac_mdio_device = {
+        .name           = "davinci_mdio",
+        .id             = 0,
+        .num_resources  = ARRAY_SIZE(am35xx_emac_mdio_resources),
+        .resource       = am35xx_emac_mdio_resources,
+        .dev.platform_data = &am35xx_emac_mdio_pdata,
+};
+
+static void am35xx_enable_emac_int(void)
+{
+        u32 regval;
+
+        regval = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR);
+        regval = (regval | AM35XX_CPGMAC_C0_RX_PULSE_CLR |
+                  AM35XX_CPGMAC_C0_TX_PULSE_CLR |
+                  AM35XX_CPGMAC_C0_MISC_PULSE_CLR |
+                  AM35XX_CPGMAC_C0_RX_THRESH_CLR);
+        omap_ctrl_writel(regval, AM35XX_CONTROL_LVL_INTR_CLEAR);
+        regval = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR);
+}
+
+static void am35xx_disable_emac_int(void)
+{
+        u32 regval;
+
+        regval = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR);
+        regval = (regval | AM35XX_CPGMAC_C0_RX_PULSE_CLR |
+                  AM35XX_CPGMAC_C0_TX_PULSE_CLR);
+        omap_ctrl_writel(regval, AM35XX_CONTROL_LVL_INTR_CLEAR);
+        regval = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR);
+}
+
+static struct emac_platform_data am35xx_emac_pdata = {
+        .ctrl_reg_offset        = AM35XX_EMAC_CNTRL_OFFSET,
+        .ctrl_mod_reg_offset    = AM35XX_EMAC_CNTRL_MOD_OFFSET,
+        .ctrl_ram_offset        = AM35XX_EMAC_CNTRL_RAM_OFFSET,
+        .ctrl_ram_size          = AM35XX_EMAC_CNTRL_RAM_SIZE,
+        .hw_ram_addr            = AM35XX_EMAC_HW_RAM_ADDR,
+        .version                = EMAC_VERSION_2,
+        .interrupt_enable       = am35xx_enable_emac_int,
+        .interrupt_disable      = am35xx_disable_emac_int,
+};
+
+static struct resource am35xx_emac_resources[] = {
+        DEFINE_RES_MEM(AM35XX_IPSS_EMAC_BASE, 0x30000),
+        DEFINE_RES_IRQ(INT_35XX_EMAC_C0_RXTHRESH_IRQ),
+        DEFINE_RES_IRQ(INT_35XX_EMAC_C0_RX_PULSE_IRQ),
+        DEFINE_RES_IRQ(INT_35XX_EMAC_C0_TX_PULSE_IRQ),
+        DEFINE_RES_IRQ(INT_35XX_EMAC_C0_MISC_PULSE_IRQ),
+};
+
+static struct platform_device am35xx_emac_device = {
+        .name           = "davinci_emac",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(am35xx_emac_resources),
+        .resource       = am35xx_emac_resources,
+        .dev            = {
+                .platform_data  = &am35xx_emac_pdata,
+        },
+};
+
+void __init am35xx_emac_init(unsigned long mdio_bus_freq, u8 rmii_en)
+{
+        unsigned int regval;
+        int err;
+
+        am35xx_emac_pdata.rmii_en = rmii_en;
+        am35xx_emac_mdio_pdata.bus_freq = mdio_bus_freq;
+        err = platform_device_register(&am35xx_emac_device);
+        if (err) {
+                pr_err("AM35x: failed registering EMAC device: %d\n", err);
+                return;
+        }
+
+        err = platform_device_register(&am35xx_emac_mdio_device);
+        if (err) {
+                pr_err("AM35x: failed registering EMAC MDIO device: %d\n", err);
+                platform_device_unregister(&am35xx_emac_device);
+                return;
+        }
+
+        regval = omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET);
+        regval = regval & (~(AM35XX_CPGMACSS_SW_RST));
+        omap_ctrl_writel(regval, AM35XX_CONTROL_IP_SW_RESET);
+        regval = omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET);
+}
diff --git a/arch/arm/mach-omap2/am35xx-emac.h b/arch/arm/mach-omap2/am35xx-emac.h
new file mode 100644
index 00000000000..15c6f9ce59a
--- /dev/null
+++ b/arch/arm/mach-omap2/am35xx-emac.h
@@ -0,0 +1,15 @@
+/*
+ * Copyright (C) 2011 Ilya Yanok, Emcraft Systems
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#define AM35XX_DEFAULT_MDIO_FREQUENCY   1000000
+
+#if defined(CONFIG_TI_DAVINCI_EMAC) || defined(CONFIG_TI_DAVINCI_EMAC_MODULE)
+void am35xx_emac_init(unsigned long mdio_bus_freq, u8 rmii_en);
+#else
+static inline void am35xx_emac_init(unsigned long mdio_bus_freq, u8 rmii_en) {}
+#endif
diff --git a/arch/arm/mach-omap2/board-2430sdp.c b/arch/arm/mach-omap2/board-2430sdp.c
index 7370983f809..c8bda62900d 100644
--- a/arch/arm/mach-omap2/board-2430sdp.c
+++ b/arch/arm/mach-omap2/board-2430sdp.c
@@ -279,7 +279,7 @@ static void __init omap_2430sdp_init(void)
         platform_add_devices(sdp2430_devices, ARRAY_SIZE(sdp2430_devices));
         omap_serial_init();
         omap_sdrc_init(NULL, NULL);
-        omap2_hsmmc_init(mmc);
+        omap_hsmmc_init(mmc);
         omap2_usbfs_init(&sdp2430_usb_config);
 
         omap_mux_init_signal("usb0hs_stp", OMAP_PULL_ENA | OMAP_PULL_UP);
diff --git a/arch/arm/mach-omap2/board-3430sdp.c b/arch/arm/mach-omap2/board-3430sdp.c
index 383717ba63b..da75f239873 100644
--- a/arch/arm/mach-omap2/board-3430sdp.c
+++ b/arch/arm/mach-omap2/board-3430sdp.c
@@ -232,11 +232,13 @@ static struct omap2_hsmmc_info mmc[] = {
                  */
                 .caps           = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA,
                 .gpio_wp        = 4,
+                .deferred       = true,
         },
         {
                 .mmc            = 2,
                 .caps           = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA,
                 .gpio_wp        = 7,
+                .deferred       = true,
         },
         {}      /* Terminator */
 };
@@ -249,7 +251,7 @@ static int sdp3430_twl_gpio_setup(struct device *dev,
          */
         mmc[0].gpio_cd = gpio + 0;
         mmc[1].gpio_cd = gpio + 1;
-        omap2_hsmmc_init(mmc);
+        omap_hsmmc_late_init(mmc);
 
         /* gpio + 7 is "sub_lcd_en_bkl" (output/PWM1) */
         gpio_request_one(gpio + 7, GPIOF_OUT_INIT_LOW, "sub_lcd_en_bkl");
@@ -606,6 +608,7 @@ static void __init omap_3430sdp_init(void)
         omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
         omap_board_config = sdp3430_config;
         omap_board_config_size = ARRAY_SIZE(sdp3430_config);
+        omap_hsmmc_init(mmc);
         omap3430_i2c_init();
         omap_display_init(&sdp3430_dss_data);
         if (omap_rev() > OMAP3430_REV_ES1_0)
diff --git a/arch/arm/mach-omap2/board-4430sdp.c b/arch/arm/mach-omap2/board-4430sdp.c
index 4e9071589bf..30768c2f53f 100644
--- a/arch/arm/mach-omap2/board-4430sdp.c
+++ b/arch/arm/mach-omap2/board-4430sdp.c
@@ -25,6 +25,7 @@
 #include <linux/regulator/fixed.h>
 #include <linux/leds.h>
 #include <linux/leds_pwm.h>
+#include <linux/platform_data/omap4-keypad.h>
 
 #include <mach/hardware.h>
 #include <asm/hardware/gic.h>
@@ -41,6 +42,7 @@
 #include <video/omap-panel-nokia-dsi.h>
 #include <video/omap-panel-picodlp.h>
 #include <linux/wl12xx.h>
+#include <linux/platform_data/omap-abe-twl6040.h>
 
 #include "mux.h"
 #include "hsmmc.h"
@@ -322,7 +324,10 @@ static struct spi_board_info sdp4430_spi_board_info[] __initdata = {
                 .bus_num                = 1,
                 .chip_select            = 0,
                 .max_speed_hz           = 24000000,
-                .irq                    = ETH_KS8851_IRQ,
+                /*
+                 * .irq is set to gpio_to_irq(ETH_KS8851_IRQ)
+                 * in omap_4430sdp_init
+                 */
         },
 };
 
@@ -378,12 +383,40 @@ static struct platform_device sdp4430_dmic_codec = {
         .id     = -1,
 };
 
+static struct omap_abe_twl6040_data sdp4430_abe_audio_data = {
+        .card_name = "SDP4430",
+        .has_hs         = ABE_TWL6040_LEFT | ABE_TWL6040_RIGHT,
+        .has_hf         = ABE_TWL6040_LEFT | ABE_TWL6040_RIGHT,
+        .has_ep         = 1,
+        .has_aux        = ABE_TWL6040_LEFT | ABE_TWL6040_RIGHT,
+        .has_vibra      = ABE_TWL6040_LEFT | ABE_TWL6040_RIGHT,
+
+        .has_dmic       = 1,
+        .has_hsmic      = 1,
+        .has_mainmic    = 1,
+        .has_submic     = 1,
+        .has_afm        = ABE_TWL6040_LEFT | ABE_TWL6040_RIGHT,
+
+        .jack_detection = 1,
+        /* MCLK input is 38.4MHz */
+        .mclk_freq      = 38400000,
+};
+
+static struct platform_device sdp4430_abe_audio = {
+        .name           = "omap-abe-twl6040",
+        .id             = -1,
+        .dev = {
+                .platform_data = &sdp4430_abe_audio_data,
+        },
+};
+
 static struct platform_device *sdp4430_devices[] __initdata = {
         &sdp4430_gpio_keys_device,
         &sdp4430_leds_gpio,
         &sdp4430_leds_pwm,
         &sdp4430_vbat,
         &sdp4430_dmic_codec,
+        &sdp4430_abe_audio,
 };
 
 static struct omap_musb_board_data musb_board_data = {
@@ -491,9 +524,9 @@ static int __init omap4_twl6030_hsmmc_init(struct omap2_hsmmc_info *controllers)
 {
         struct omap2_hsmmc_info *c;
 
-        omap2_hsmmc_init(controllers);
+        omap_hsmmc_init(controllers);
         for (c = controllers; c->mmc; c++)
-                omap4_twl6030_hsmmc_set_late_init(c->dev);
+                omap4_twl6030_hsmmc_set_late_init(&c->pdev->dev);
 
         return 0;
 }
diff --git a/arch/arm/mach-omap2/board-am3517evm.c b/arch/arm/mach-omap2/board-am3517evm.c
index 4b1cfe32e6b..3645285a3e2 100644
--- a/arch/arm/mach-omap2/board-am3517evm.c
+++ b/arch/arm/mach-omap2/board-am3517evm.c
@@ -39,124 +39,11 @@
 #include <video/omap-panel-generic-dpi.h>
 #include <video/omap-panel-dvi.h>
 
+#include "am35xx-emac.h"
 #include "mux.h"
 #include "control.h"
 #include "hsmmc.h"
 
-#define AM35XX_EVM_MDIO_FREQUENCY       (1000000)
-
-static struct mdio_platform_data am3517_evm_mdio_pdata = {
-        .bus_freq       = AM35XX_EVM_MDIO_FREQUENCY,
-};
-
-static struct resource am3517_mdio_resources[] = {
-        {
-                .start  = AM35XX_IPSS_EMAC_BASE + AM35XX_EMAC_MDIO_OFFSET,
-                .end    = AM35XX_IPSS_EMAC_BASE + AM35XX_EMAC_MDIO_OFFSET +
-                          SZ_4K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-};
-
-static struct platform_device am3517_mdio_device = {
-        .name           = "davinci_mdio",
-        .id             = 0,
-        .num_resources  = ARRAY_SIZE(am3517_mdio_resources),
-        .resource       = am3517_mdio_resources,
-        .dev.platform_data = &am3517_evm_mdio_pdata,
-};
-
-static struct emac_platform_data am3517_evm_emac_pdata = {
-        .rmii_en        = 1,
-};
-
-static struct resource am3517_emac_resources[] = {
-        {
-                .start  = AM35XX_IPSS_EMAC_BASE,
-                .end    = AM35XX_IPSS_EMAC_BASE + 0x2FFFF,
-                .flags  = IORESOURCE_MEM,
-        },
-        {
-                .start  = INT_35XX_EMAC_C0_RXTHRESH_IRQ,
-                .end    = INT_35XX_EMAC_C0_RXTHRESH_IRQ,
-                .flags  = IORESOURCE_IRQ,
-        },
-        {
-                .start  = INT_35XX_EMAC_C0_RX_PULSE_IRQ,
-                .end    = INT_35XX_EMAC_C0_RX_PULSE_IRQ,
-                .flags  = IORESOURCE_IRQ,
-        },
-        {
-                .start  = INT_35XX_EMAC_C0_TX_PULSE_IRQ,
-                .end    = INT_35XX_EMAC_C0_TX_PULSE_IRQ,
-                .flags  = IORESOURCE_IRQ,
-        },
-        {
-                .start  = INT_35XX_EMAC_C0_MISC_PULSE_IRQ,
-                .end    = INT_35XX_EMAC_C0_MISC_PULSE_IRQ,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device am3517_emac_device = {
-        .name           = "davinci_emac",
-        .id             = -1,
-        .num_resources  = ARRAY_SIZE(am3517_emac_resources),
-        .resource       = am3517_emac_resources,
-};
-
-static void am3517_enable_ethernet_int(void)
-{
-        u32 regval;
-
-        regval = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR);
-        regval = (regval | AM35XX_CPGMAC_C0_RX_PULSE_CLR |
-                AM35XX_CPGMAC_C0_TX_PULSE_CLR |
-                AM35XX_CPGMAC_C0_MISC_PULSE_CLR |
-                AM35XX_CPGMAC_C0_RX_THRESH_CLR);
-        omap_ctrl_writel(regval, AM35XX_CONTROL_LVL_INTR_CLEAR);
-        regval = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR);
-}
-
-static void am3517_disable_ethernet_int(void)
-{
-        u32 regval;
-
-        regval = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR);
-        regval = (regval | AM35XX_CPGMAC_C0_RX_PULSE_CLR |
-                AM35XX_CPGMAC_C0_TX_PULSE_CLR);
-        omap_ctrl_writel(regval, AM35XX_CONTROL_LVL_INTR_CLEAR);
-        regval = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR);
-}
-
-static void am3517_evm_ethernet_init(struct emac_platform_data *pdata)
-{
-        unsigned int regval;
-
-        pdata->ctrl_reg_offset          = AM35XX_EMAC_CNTRL_OFFSET;
-        pdata->ctrl_mod_reg_offset      = AM35XX_EMAC_CNTRL_MOD_OFFSET;
-        pdata->ctrl_ram_offset          = AM35XX_EMAC_CNTRL_RAM_OFFSET;
-        pdata->ctrl_ram_size            = AM35XX_EMAC_CNTRL_RAM_SIZE;
-        pdata->version                  = EMAC_VERSION_2;
-        pdata->hw_ram_addr              = AM35XX_EMAC_HW_RAM_ADDR;
-        pdata->interrupt_enable         = am3517_enable_ethernet_int;
-        pdata->interrupt_disable        = am3517_disable_ethernet_int;
-        am3517_emac_device.dev.platform_data    = pdata;
-        platform_device_register(&am3517_emac_device);
-        platform_device_register(&am3517_mdio_device);
-        clk_add_alias(NULL, dev_name(&am3517_mdio_device.dev),
-                      NULL, &am3517_emac_device.dev);
-
-        regval = omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET);
-        regval = regval & (~(AM35XX_CPGMACSS_SW_RST));
-        omap_ctrl_writel(regval, AM35XX_CONTROL_IP_SW_RESET);
-        regval = omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET);
-
-        return ;
-}
-
-
-
 #define LCD_PANEL_PWR           176
 #define LCD_PANEL_BKLIGHT_PWR   182
 #define LCD_PANEL_PWM           181
@@ -498,13 +385,13 @@ static void __init am3517_evm_init(void)
         i2c_register_board_info(1, am3517evm_i2c1_boardinfo,
                                 ARRAY_SIZE(am3517evm_i2c1_boardinfo));
         /*Ethernet*/
-        am3517_evm_ethernet_init(&am3517_evm_emac_pdata);
+        am35xx_emac_init(AM35XX_DEFAULT_MDIO_FREQUENCY, 1);
 
         /* MUSB */
         am3517_evm_musb_init();
 
         /* MMC init function */
-        omap2_hsmmc_init(mmc);
+        omap_hsmmc_init(mmc);
 }
 
 MACHINE_START(OMAP3517EVM, "OMAP3517/AM3517 EVM")
diff --git a/arch/arm/mach-omap2/board-cm-t35.c b/arch/arm/mach-omap2/board-cm-t35.c
index d73316ed420..41b0a2fe0b0 100644
--- a/arch/arm/mach-omap2/board-cm-t35.c
+++ b/arch/arm/mach-omap2/board-cm-t35.c
@@ -280,7 +280,6 @@ static struct omap_dss_board_info cm_t35_dss_data = {
 
 static struct omap2_mcspi_device_config tdo24m_mcspi_config = {
         .turbo_mode     = 0,
-        .single_channel = 1,    /* 0: slave, 1: master */
 };
 
 static struct tdo24m_platform_data tdo24m_config = {
@@ -413,7 +412,7 @@ static struct omap2_hsmmc_info mmc[] = {
                 .caps           = MMC_CAP_4_BIT_DATA,
                 .gpio_cd        = -EINVAL,
                 .gpio_wp        = -EINVAL,
-
+                .deferred       = true,
         },
         {
                 .mmc            = 2,
@@ -471,7 +470,7 @@ static int cm_t35_twl_gpio_setup(struct device *dev, unsigned gpio,
 
         /* gpio + 0 is "mmc0_cd" (input/IRQ) */
         mmc[0].gpio_cd = gpio + 0;
-        omap2_hsmmc_init(mmc);
+        omap_hsmmc_late_init(mmc);
 
         return 0;
 }
@@ -639,6 +638,7 @@ static void __init cm_t3x_common_init(void)
         omap_serial_init();
         omap_sdrc_init(mt46h32m32lf6_sdrc_params,
                              mt46h32m32lf6_sdrc_params);
+        omap_hsmmc_init(mmc);
         cm_t35_init_i2c();
         omap_ads7846_init(1, CM_T35_GPIO_PENDOWN, 0, NULL);
         cm_t35_init_ethernet();
diff --git a/arch/arm/mach-omap2/board-cm-t3517.c b/arch/arm/mach-omap2/board-cm-t3517.c
index f36d694d215..9e66e167e4f 100644
--- a/arch/arm/mach-omap2/board-cm-t3517.c
+++ b/arch/arm/mach-omap2/board-cm-t3517.c
@@ -49,6 +49,7 @@
 #include "mux.h"
 #include "control.h"
 #include "common-board-devices.h"
+#include "am35xx-emac.h"
 
 #if defined(CONFIG_LEDS_GPIO) || defined(CONFIG_LEDS_GPIO_MODULE)
 static struct gpio_led cm_t3517_leds[] = {
@@ -291,6 +292,7 @@ static void __init cm_t3517_init(void)
         cm_t3517_init_rtc();
         cm_t3517_init_usbh();
         cm_t3517_init_hecc();
+        am35xx_emac_init(AM35XX_DEFAULT_MDIO_FREQUENCY, 1);
 }
 
 MACHINE_START(CM_T3517, "Compulab CM-T3517")
diff --git a/arch/arm/mach-omap2/board-devkit8000.c b/arch/arm/mach-omap2/board-devkit8000.c
index e873063f4fd..11cd2a80609 100644
--- a/arch/arm/mach-omap2/board-devkit8000.c
+++ b/arch/arm/mach-omap2/board-devkit8000.c
@@ -100,6 +100,7 @@ static struct omap2_hsmmc_info mmc[] = {
                 .mmc            = 1,
                 .caps           = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA,
                 .gpio_wp        = 29,
+                .deferred       = true,
         },
         {}      /* Terminator */
 };
@@ -228,7 +229,7 @@ static int devkit8000_twl_gpio_setup(struct device *dev,
 
         /* gpio + 0 is "mmc0_cd" (input/IRQ) */
         mmc[0].gpio_cd = gpio + 0;
-        omap2_hsmmc_init(mmc);
+        omap_hsmmc_late_init(mmc);
 
         /* TWL4030_GPIO_MAX + 1 == ledB, PMU_STAT (out, active low LED) */
         gpio_leds[2].gpio = gpio + TWL4030_GPIO_MAX + 1;
@@ -636,6 +637,7 @@ static void __init devkit8000_init(void)
 
         omap_dm9000_init();
 
+        omap_hsmmc_init(mmc);
         devkit8000_i2c_init();
         platform_add_devices(devkit8000_devices,
                         ARRAY_SIZE(devkit8000_devices));
diff --git a/arch/arm/mach-omap2/board-flash.c b/arch/arm/mach-omap2/board-flash.c
index 30a6f527510..0349fd2b68d 100644
--- a/arch/arm/mach-omap2/board-flash.c
+++ b/arch/arm/mach-omap2/board-flash.c
@@ -189,7 +189,7 @@ unmap:
  *
  * @return - void.
  */
-void board_flash_init(struct flash_partitions partition_info[],
+void __init board_flash_init(struct flash_partitions partition_info[],
                         char chip_sel_board[][GPMC_CS_NUM], int nand_type)
 {
         u8              cs = 0;
diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c
index 45fdfe2bd9d..74e1687b517 100644
--- a/arch/arm/mach-omap2/board-generic.c
+++ b/arch/arm/mach-omap2/board-generic.c
@@ -12,6 +12,7 @@
  * published by the Free Software Foundation.
  */
 #include <linux/io.h>
+#include <linux/of_irq.h>
 #include <linux/of_platform.h>
 #include <linux/irqdomain.h>
 #include <linux/i2c/twl.h>
@@ -24,33 +25,23 @@
 #include "common.h"
 #include "common-board-devices.h"
 
-/*
- * XXX: Still needed to boot until the i2c & twl driver is adapted to
- * device-tree
- */
-#ifdef CONFIG_ARCH_OMAP4
-static struct twl4030_platform_data sdp4430_twldata = {
-        .irq_base       = TWL6030_IRQ_BASE,
-        .irq_end        = TWL6030_IRQ_END,
-};
-
-static void __init omap4_i2c_init(void)
-{
-        omap4_pmic_init("twl6030", &sdp4430_twldata);
-}
+#if !(defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3))
+#define omap_intc_of_init       NULL
+#endif
+#ifndef CONFIG_ARCH_OMAP4
+#define gic_of_init             NULL
 #endif
 
-#ifdef CONFIG_ARCH_OMAP3
-static struct twl4030_platform_data beagle_twldata = {
-        .irq_base       = TWL4030_IRQ_BASE,
-        .irq_end        = TWL4030_IRQ_END,
+static struct of_device_id irq_match[] __initdata = {
+        { .compatible = "ti,omap2-intc", .data = omap_intc_of_init, },
+        { .compatible = "arm,cortex-a9-gic", .data = gic_of_init, },
+        { }
 };
 
-static void __init omap3_i2c_init(void)
+static void __init omap_init_irq(void)
 {
-        omap3_pmic_init("twl4030", &beagle_twldata);
+        of_irq_init(irq_match);
 }
-#endif
 
 static struct of_device_id omap_dt_match_table[] __initdata = {
         { .compatible = "simple-bus", },
@@ -58,51 +49,24 @@ static struct of_device_id omap_dt_match_table[] __initdata = {
         { }
 };
 
-static struct of_device_id intc_match[] __initdata = {
-        { .compatible = "ti,omap3-intc", },
-        { .compatible = "arm,cortex-a9-gic", },
-        { }
-};
-
 static void __init omap_generic_init(void)
 {
-        struct device_node *node = of_find_matching_node(NULL, intc_match);
-        if (node)
-                irq_domain_add_legacy(node, 32, 0, 0, &irq_domain_simple_ops, NULL);
-
         omap_sdrc_init(NULL, NULL);
 
         of_platform_populate(NULL, omap_dt_match_table, NULL, NULL);
 }
 
-#ifdef CONFIG_ARCH_OMAP4
-static void __init omap4_init(void)
-{
-        omap4_i2c_init();
-        omap_generic_init();
-}
-#endif
-
-#ifdef CONFIG_ARCH_OMAP3
-static void __init omap3_init(void)
-{
-        omap3_i2c_init();
-        omap_generic_init();
-}
-#endif
-
-#if defined(CONFIG_SOC_OMAP2420)
+#ifdef CONFIG_SOC_OMAP2420
 static const char *omap242x_boards_compat[] __initdata = {
         "ti,omap2420",
         NULL,
 };
 
 DT_MACHINE_START(OMAP242X_DT, "Generic OMAP2420 (Flattened Device Tree)")
-        .atag_offset    = 0x100,
         .reserve        = omap_reserve,
         .map_io         = omap242x_map_io,
         .init_early     = omap2420_init_early,
-        .init_irq       = omap2_init_irq,
+        .init_irq       = omap_init_irq,
         .handle_irq     = omap2_intc_handle_irq,
         .init_machine   = omap_generic_init,
         .timer          = &omap2_timer,
@@ -111,18 +75,17 @@ DT_MACHINE_START(OMAP242X_DT, "Generic OMAP2420 (Flattened Device Tree)")
 MACHINE_END
 #endif
 
-#if defined(CONFIG_SOC_OMAP2430)
+#ifdef CONFIG_SOC_OMAP2430
 static const char *omap243x_boards_compat[] __initdata = {
         "ti,omap2430",
         NULL,
 };
 
 DT_MACHINE_START(OMAP243X_DT, "Generic OMAP2430 (Flattened Device Tree)")
-        .atag_offset    = 0x100,
         .reserve        = omap_reserve,
         .map_io         = omap243x_map_io,
         .init_early     = omap2430_init_early,
-        .init_irq       = omap2_init_irq,
+        .init_irq       = omap_init_irq,
         .handle_irq     = omap2_intc_handle_irq,
         .init_machine   = omap_generic_init,
         .timer          = &omap2_timer,
@@ -131,18 +94,33 @@ DT_MACHINE_START(OMAP243X_DT, "Generic OMAP2430 (Flattened Device Tree)")
 MACHINE_END
 #endif
 
-#if defined(CONFIG_ARCH_OMAP3)
+#ifdef CONFIG_ARCH_OMAP3
+static struct twl4030_platform_data beagle_twldata = {
+        .irq_base       = TWL4030_IRQ_BASE,
+        .irq_end        = TWL4030_IRQ_END,
+};
+
+static void __init omap3_i2c_init(void)
+{
+        omap3_pmic_init("twl4030", &beagle_twldata);
+}
+
+static void __init omap3_init(void)
+{
+        omap3_i2c_init();
+        omap_generic_init();
+}
+
 static const char *omap3_boards_compat[] __initdata = {
         "ti,omap3",
         NULL,
 };
 
 DT_MACHINE_START(OMAP3_DT, "Generic OMAP3 (Flattened Device Tree)")
-        .atag_offset    = 0x100,
         .reserve        = omap_reserve,
         .map_io         = omap3_map_io,
         .init_early     = omap3430_init_early,
-        .init_irq       = omap3_init_irq,
+        .init_irq       = omap_init_irq,
         .handle_irq     = omap3_intc_handle_irq,
         .init_machine   = omap3_init,
         .timer          = &omap3_timer,
@@ -151,18 +129,33 @@ DT_MACHINE_START(OMAP3_DT, "Generic OMAP3 (Flattened Device Tree)")
 MACHINE_END
 #endif
 
-#if defined(CONFIG_ARCH_OMAP4)
+#ifdef CONFIG_ARCH_OMAP4
+static struct twl4030_platform_data sdp4430_twldata = {
+        .irq_base       = TWL6030_IRQ_BASE,
+        .irq_end        = TWL6030_IRQ_END,
+};
+
+static void __init omap4_i2c_init(void)
+{
+        omap4_pmic_init("twl6030", &sdp4430_twldata);
+}
+
+static void __init omap4_init(void)
+{
+        omap4_i2c_init();
+        omap_generic_init();
+}
+
 static const char *omap4_boards_compat[] __initdata = {
         "ti,omap4",
         NULL,
 };
 
 DT_MACHINE_START(OMAP4_DT, "Generic OMAP4 (Flattened Device Tree)")
-        .atag_offset    = 0x100,
         .reserve        = omap_reserve,
         .map_io         = omap4_map_io,
         .init_early     = omap4430_init_early,
-        .init_irq       = gic_init_irq,
+        .init_irq       = omap_init_irq,
         .handle_irq     = gic_handle_irq,
         .init_machine   = omap4_init,
         .timer          = &omap4_timer,
diff --git a/arch/arm/mach-omap2/board-igep0020.c b/arch/arm/mach-omap2/board-igep0020.c
index a59ace0ed56..e558800adfd 100644
--- a/arch/arm/mach-omap2/board-igep0020.c
+++ b/arch/arm/mach-omap2/board-igep0020.c
@@ -295,6 +295,7 @@ static struct omap2_hsmmc_info mmc[] = {
                 .caps           = MMC_CAP_4_BIT_DATA,
                 .gpio_cd        = -EINVAL,
                 .gpio_wp        = -EINVAL,
+                .deferred       = true,
         },
 #if defined(CONFIG_LIBERTAS_SDIO) || defined(CONFIG_LIBERTAS_SDIO_MODULE)
         {
@@ -402,7 +403,7 @@ static int igep_twl_gpio_setup(struct device *dev,
 
         /* gpio + 0 is "mmc0_cd" (input/IRQ) */
         mmc[0].gpio_cd = gpio + 0;
-        omap2_hsmmc_init(mmc);
+        omap_hsmmc_late_init(mmc);
 
         /* TWL4030_GPIO_MAX + 1 == ledB (out, active low LED) */
 #if !defined(CONFIG_LEDS_GPIO) && !defined(CONFIG_LEDS_GPIO_MODULE)
@@ -639,6 +640,9 @@ static void __init igep_init(void)
 
         /* Get IGEP2 hardware revision */
         igep2_get_revision();
+
+        omap_hsmmc_init(mmc);
+
         /* Register I2C busses and drivers */
         igep_i2c_init();
         platform_add_devices(igep_devices, ARRAY_SIZE(igep_devices));
diff --git a/arch/arm/mach-omap2/board-ldp.c b/arch/arm/mach-omap2/board-ldp.c
index 2d2a61f7dcb..d50a562adfa 100644
--- a/arch/arm/mach-omap2/board-ldp.c
+++ b/arch/arm/mach-omap2/board-ldp.c
@@ -27,7 +27,6 @@
 #include <linux/io.h>
 #include <linux/smsc911x.h>
 #include <linux/mmc/host.h>
-#include <linux/gpio.h>
 
 #include <mach/hardware.h>
 #include <asm/mach-types.h>
@@ -424,7 +423,7 @@ static void __init omap_ldp_init(void)
         board_nand_init(ldp_nand_partitions,
                 ARRAY_SIZE(ldp_nand_partitions), ZOOM_NAND_CS, 0);
 
-        omap2_hsmmc_init(mmc);
+        omap_hsmmc_init(mmc);
         ldp_display_init();
 }
 
diff --git a/arch/arm/mach-omap2/board-n8x0.c b/arch/arm/mach-omap2/board-n8x0.c
index 67226271760..518091c5f77 100644
--- a/arch/arm/mach-omap2/board-n8x0.c
+++ b/arch/arm/mach-omap2/board-n8x0.c
@@ -36,10 +36,6 @@
 
 #include "mux.h"
 
-static int slot1_cover_open;
-static int slot2_cover_open;
-static struct device *mmc_device;
-
 #define TUSB6010_ASYNC_CS       1
 #define TUSB6010_SYNC_CS        4
 #define TUSB6010_GPIO_INT       58
@@ -137,7 +133,6 @@ static void __init n8x0_usb_init(void) {}
 
 static struct omap2_mcspi_device_config p54spi_mcspi_config = {
         .turbo_mode     = 0,
-        .single_channel = 1,
 };
 
 static struct spi_board_info n800_spi_board_info[] __initdata = {
@@ -211,6 +206,10 @@ static struct omap_onenand_platform_data board_onenand_data[] = {
 #define N810_EMMC_VSD_GPIO      23
 #define N810_EMMC_VIO_GPIO      9
 
+static int slot1_cover_open;
+static int slot2_cover_open;
+static struct device *mmc_device;
+
 static int n8x0_mmc_switch_slot(struct device *dev, int slot)
 {
 #ifdef CONFIG_MMC_DEBUG
diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c
index 7ffcd2839e7..7be8d659d91 100644
--- a/arch/arm/mach-omap2/board-omap3beagle.c
+++ b/arch/arm/mach-omap2/board-omap3beagle.c
@@ -253,6 +253,7 @@ static struct omap2_hsmmc_info mmc[] = {
                 .mmc            = 1,
                 .caps           = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA,
                 .gpio_wp        = -EINVAL,
+                .deferred       = true,
         },
         {}      /* Terminator */
 };
@@ -272,12 +273,10 @@ static int beagle_twl_gpio_setup(struct device *dev,
 {
         int r;
 
-        if (beagle_config.mmc1_gpio_wp != -EINVAL)
-                omap_mux_init_gpio(beagle_config.mmc1_gpio_wp, OMAP_PIN_INPUT);
         mmc[0].gpio_wp = beagle_config.mmc1_gpio_wp;
         /* gpio + 0 is "mmc0_cd" (input/IRQ) */
         mmc[0].gpio_cd = gpio + 0;
-        omap2_hsmmc_init(mmc);
+        omap_hsmmc_late_init(mmc);
 
         /*
          * TWL4030_GPIO_MAX + 0 == ledA, EHCI nEN_USB_PWR (out, XM active
@@ -521,6 +520,11 @@ static void __init omap3_beagle_init(void)
 {
         omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
         omap3_beagle_init_rev();
+
+        if (beagle_config.mmc1_gpio_wp != -EINVAL)
+                omap_mux_init_gpio(beagle_config.mmc1_gpio_wp, OMAP_PIN_INPUT);
+        omap_hsmmc_init(mmc);
+
         omap3_beagle_i2c_init();
 
         gpio_buttons[0].gpio = beagle_config.usr_button_gpio;
diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c
index c877236a844..a659e198892 100644
--- a/arch/arm/mach-omap2/board-omap3evm.c
+++ b/arch/arm/mach-omap2/board-omap3evm.c
@@ -317,6 +317,7 @@ static struct omap2_hsmmc_info mmc[] = {
                 .caps           = MMC_CAP_4_BIT_DATA,
                 .gpio_cd        = -EINVAL,
                 .gpio_wp        = 63,
+                .deferred       = true,
         },
 #ifdef CONFIG_WL12XX_PLATFORM_DATA
         {
@@ -361,9 +362,8 @@ static int omap3evm_twl_gpio_setup(struct device *dev,
         int r, lcd_bl_en;
 
         /* gpio + 0 is "mmc0_cd" (input/IRQ) */
-        omap_mux_init_gpio(63, OMAP_PIN_INPUT);
         mmc[0].gpio_cd = gpio + 0;
-        omap2_hsmmc_init(mmc);
+        omap_hsmmc_late_init(mmc);
 
         /*
          * Most GPIOs are for USB OTG.  Some are mostly sent to
@@ -644,6 +644,9 @@ static void __init omap3_evm_init(void)
         omap_board_config = omap3_evm_config;
         omap_board_config_size = ARRAY_SIZE(omap3_evm_config);
 
+        omap_mux_init_gpio(63, OMAP_PIN_INPUT);
+        omap_hsmmc_init(mmc);
+
         omap3_evm_i2c_init();
 
         omap_display_init(&omap3_evm_dss_data);
diff --git a/arch/arm/mach-omap2/board-omap3logic.c b/arch/arm/mach-omap2/board-omap3logic.c
index 4198dd017d8..4a7d8c8a75d 100644
--- a/arch/arm/mach-omap2/board-omap3logic.c
+++ b/arch/arm/mach-omap2/board-omap3logic.c
@@ -128,7 +128,7 @@ static void __init board_mmc_init(void)
                 return;
         }
 
-        omap2_hsmmc_init(board_mmc_info);
+        omap_hsmmc_init(board_mmc_info);
 }
 
 static struct omap_smsc911x_platform_data __initdata board_smsc911x_data = {
@@ -205,6 +205,7 @@ static void __init omap3logic_init(void)
 
 MACHINE_START(OMAP3_TORPEDO, "Logic OMAP3 Torpedo board")
         .atag_offset    = 0x100,
+        .reserve        = omap_reserve,
         .map_io         = omap3_map_io,
         .init_early     = omap35xx_init_early,
         .init_irq       = omap3_init_irq,
@@ -216,6 +217,7 @@ MACHINE_END
 
 MACHINE_START(OMAP3530_LV_SOM, "OMAP Logic 3530 LV SOM board")
         .atag_offset    = 0x100,
+        .reserve        = omap_reserve,
         .map_io         = omap3_map_io,
         .init_early     = omap35xx_init_early,
         .init_irq       = omap3_init_irq,
diff --git a/arch/arm/mach-omap2/board-omap3pandora.c b/arch/arm/mach-omap2/board-omap3pandora.c
index 1644b73017f..33d995d0f07 100644
--- a/arch/arm/mach-omap2/board-omap3pandora.c
+++ b/arch/arm/mach-omap2/board-omap3pandora.c
@@ -121,6 +121,11 @@ static struct platform_device pandora_leds_gpio = {
         },
 };
 
+static struct platform_device pandora_backlight = {
+        .name   = "pandora-backlight",
+        .id     = -1,
+};
+
 #define GPIO_BUTTON(gpio_num, ev_type, ev_code, act_low, descr) \
 {                                                               \
         .gpio           = gpio_num,                             \
@@ -273,6 +278,7 @@ static struct omap2_hsmmc_info omap3pandora_mmc[] = {
                 .gpio_cd        = -EINVAL,
                 .gpio_wp        = 126,
                 .ext_clock      = 0,
+                .deferred       = true,
         },
         {
                 .mmc            = 2,
@@ -281,6 +287,7 @@ static struct omap2_hsmmc_info omap3pandora_mmc[] = {
                 .gpio_wp        = 127,
                 .ext_clock      = 1,
                 .transceiver    = true,
+                .deferred       = true,
         },
         {
                 .mmc            = 3,
@@ -300,7 +307,7 @@ static int omap3pandora_twl_gpio_setup(struct device *dev,
         /* gpio + {0,1} is "mmc{0,1}_cd" (input/IRQ) */
         omap3pandora_mmc[0].gpio_cd = gpio + 0;
         omap3pandora_mmc[1].gpio_cd = gpio + 1;
-        omap2_hsmmc_init(omap3pandora_mmc);
+        omap_hsmmc_late_init(omap3pandora_mmc);
 
         /* gpio + 13 drives 32kHz buffer for wifi module */
         gpio_32khz = gpio + 13;
@@ -343,7 +350,7 @@ static struct regulator_consumer_supply pandora_vcc_lcd_supply[] = {
 };
 
 static struct regulator_consumer_supply pandora_usb_phy_supply[] = {
-        REGULATOR_SUPPLY("hsusb0", "ehci-omap.0"),
+        REGULATOR_SUPPLY("hsusb1", "ehci-omap.0"),
 };
 
 /* ads7846 on SPI and 2 nub controllers on I2C */
@@ -476,6 +483,10 @@ static struct platform_device pandora_vwlan_device = {
 
 static struct twl4030_bci_platform_data pandora_bci_data;
 
+static struct twl4030_power_data pandora_power_data = {
+        .use_poweroff   = true,
+};
+
 static struct twl4030_platform_data omap3pandora_twldata = {
         .gpio           = &omap3pandora_gpio_data,
         .vmmc1          = &pandora_vmmc1,
@@ -486,6 +497,7 @@ static struct twl4030_platform_data omap3pandora_twldata = {
         .vsim           = &pandora_vsim,
         .keypad         = &pandora_kp_data,
         .bci            = &pandora_bci_data,
+        .power          = &pandora_power_data,
 };
 
 static struct i2c_board_info __initdata omap3pandora_i2c3_boardinfo[] = {
@@ -557,17 +569,18 @@ static struct platform_device *omap3pandora_devices[] __initdata = {
         &pandora_leds_gpio,
         &pandora_keys_gpio,
         &pandora_vwlan_device,
+        &pandora_backlight,
 };
 
 static const struct usbhs_omap_board_data usbhs_bdata __initconst = {
 
-        .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
-        .port_mode[1] = OMAP_USBHS_PORT_MODE_UNUSED,
+        .port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED,
+        .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
         .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
 
         .phy_reset  = true,
-        .reset_gpio_port[0]  = 16,
-        .reset_gpio_port[1]  = -EINVAL,
+        .reset_gpio_port[0]  = -EINVAL,
+        .reset_gpio_port[1]  = 16,
         .reset_gpio_port[2]  = -EINVAL
 };
 
@@ -580,6 +593,7 @@ static struct omap_board_mux board_mux[] __initdata = {
 static void __init omap3pandora_init(void)
 {
         omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
+        omap_hsmmc_init(omap3pandora_mmc);
         omap3pandora_i2c_init();
         pandora_wl1251_init();
         platform_add_devices(omap3pandora_devices,
diff --git a/arch/arm/mach-omap2/board-omap3stalker.c b/arch/arm/mach-omap2/board-omap3stalker.c
index cb089a46f62..64100438079 100644
--- a/arch/arm/mach-omap2/board-omap3stalker.c
+++ b/arch/arm/mach-omap2/board-omap3stalker.c
@@ -209,10 +209,11 @@ static struct regulator_init_data omap3stalker_vsim = {
 
 static struct omap2_hsmmc_info mmc[] = {
         {
-         .mmc           = 1,
-         .caps          = MMC_CAP_4_BIT_DATA,
-         .gpio_cd       = -EINVAL,
-         .gpio_wp       = 23,
+                .mmc            = 1,
+                .caps           = MMC_CAP_4_BIT_DATA,
+                .gpio_cd        = -EINVAL,
+                .gpio_wp        = 23,
+                .deferred       = true,
          },
         {}                      /* Terminator */
 };
@@ -282,9 +283,8 @@ omap3stalker_twl_gpio_setup(struct device *dev,
                             unsigned gpio, unsigned ngpio)
 {
         /* gpio + 0 is "mmc0_cd" (input/IRQ) */
-        omap_mux_init_gpio(23, OMAP_PIN_INPUT);
         mmc[0].gpio_cd = gpio + 0;
-        omap2_hsmmc_init(mmc);
+        omap_hsmmc_late_init(mmc);
 
         /*
          * Most GPIOs are for USB OTG.  Some are mostly sent to
@@ -425,6 +425,9 @@ static void __init omap3_stalker_init(void)
         omap_board_config = omap3_stalker_config;
         omap_board_config_size = ARRAY_SIZE(omap3_stalker_config);
 
+        omap_mux_init_gpio(23, OMAP_PIN_INPUT);
+        omap_hsmmc_init(mmc);
+
         omap3_stalker_i2c_init();
 
         platform_add_devices(omap3_stalker_devices,
diff --git a/arch/arm/mach-omap2/board-omap3touchbook.c b/arch/arm/mach-omap2/board-omap3touchbook.c
index a0b851aafcc..8842e04aef0 100644
--- a/arch/arm/mach-omap2/board-omap3touchbook.c
+++ b/arch/arm/mach-omap2/board-omap3touchbook.c
@@ -100,6 +100,7 @@ static struct omap2_hsmmc_info mmc[] = {
                 .mmc            = 1,
                 .caps           = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA,
                 .gpio_wp        = 29,
+                .deferred       = true,
         },
         {}      /* Terminator */
 };
@@ -117,15 +118,9 @@ static struct gpio_led gpio_leds[];
 static int touchbook_twl_gpio_setup(struct device *dev,
                 unsigned gpio, unsigned ngpio)
 {
-        if (system_rev >= 0x20 && system_rev <= 0x34301000) {
-                omap_mux_init_gpio(23, OMAP_PIN_INPUT);
-                mmc[0].gpio_wp = 23;
-        } else {
-                omap_mux_init_gpio(29, OMAP_PIN_INPUT);
-        }
         /* gpio + 0 is "mmc0_cd" (input/IRQ) */
         mmc[0].gpio_cd = gpio + 0;
-        omap2_hsmmc_init(mmc);
+        omap_hsmmc_late_init(mmc);
 
         /* REVISIT: need ehci-omap hooks for external VBUS
          * power switch and overcurrent detect
@@ -351,6 +346,14 @@ static void __init omap3_touchbook_init(void)
 
         pm_power_off = omap3_touchbook_poweroff;
 
+        if (system_rev >= 0x20 && system_rev <= 0x34301000) {
+                omap_mux_init_gpio(23, OMAP_PIN_INPUT);
+                mmc[0].gpio_wp = 23;
+        } else {
+                omap_mux_init_gpio(29, OMAP_PIN_INPUT);
+        }
+        omap_hsmmc_init(mmc);
+
         omap3_touchbook_i2c_init();
         platform_add_devices(omap3_touchbook_devices,
                         ARRAY_SIZE(omap3_touchbook_devices));
diff --git a/arch/arm/mach-omap2/board-omap4panda.c b/arch/arm/mach-omap2/board-omap4panda.c
index 28fc271f703..e9071a57c37 100644
--- a/arch/arm/mach-omap2/board-omap4panda.c
+++ b/arch/arm/mach-omap2/board-omap4panda.c
@@ -28,6 +28,7 @@
 #include <linux/regulator/machine.h>
 #include <linux/regulator/fixed.h>
 #include <linux/wl12xx.h>
+#include <linux/platform_data/omap-abe-twl6040.h>
 
 #include <mach/hardware.h>
 #include <asm/hardware/gic.h>
@@ -91,9 +92,40 @@ static struct platform_device leds_gpio = {
         },
 };
 
+static struct omap_abe_twl6040_data panda_abe_audio_data = {
+        /* Audio out */
+        .has_hs         = ABE_TWL6040_LEFT | ABE_TWL6040_RIGHT,
+        /* HandsFree through expasion connector */
+        .has_hf         = ABE_TWL6040_LEFT | ABE_TWL6040_RIGHT,
+        /* PandaBoard: FM TX, PandaBoardES: can be connected to audio out */
+        .has_aux        = ABE_TWL6040_LEFT | ABE_TWL6040_RIGHT,
+        /* PandaBoard: FM RX, PandaBoardES: audio in */
+        .has_afm        = ABE_TWL6040_LEFT | ABE_TWL6040_RIGHT,
+        /* No jack detection. */
+        .jack_detection = 0,
+        /* MCLK input is 38.4MHz */
+        .mclk_freq      = 38400000,
+
+};
+
+static struct platform_device panda_abe_audio = {
+        .name           = "omap-abe-twl6040",
+        .id             = -1,
+        .dev = {
+                .platform_data = &panda_abe_audio_data,
+        },
+};
+
+static struct platform_device btwilink_device = {
+        .name   = "btwilink",
+        .id     = -1,
+};
+
 static struct platform_device *panda_devices[] __initdata = {
         &leds_gpio,
         &wl1271_device,
+        &panda_abe_audio,
+        &btwilink_device,
 };
 
 static const struct usbhs_omap_board_data usbhs_bdata __initconst = {
@@ -245,15 +277,32 @@ static int __init omap4_twl6030_hsmmc_init(struct omap2_hsmmc_info *controllers)
 {
         struct omap2_hsmmc_info *c;
 
-        omap2_hsmmc_init(controllers);
+        omap_hsmmc_init(controllers);
         for (c = controllers; c->mmc; c++)
-                omap4_twl6030_hsmmc_set_late_init(c->dev);
+                omap4_twl6030_hsmmc_set_late_init(&c->pdev->dev);
 
         return 0;
 }
 
+static struct twl4030_codec_data twl6040_codec = {
+        /* single-step ramp for headset and handsfree */
+        .hs_left_step   = 0x0f,
+        .hs_right_step  = 0x0f,
+        .hf_left_step   = 0x1d,
+        .hf_right_step  = 0x1d,
+};
+
+static struct twl4030_audio_data twl6040_audio = {
+        .codec          = &twl6040_codec,
+        .audpwron_gpio  = 127,
+        .naudint_irq    = OMAP44XX_IRQ_SYS_2N,
+        .irq_base       = TWL6040_CODEC_IRQ_BASE,
+};
+
 /* Panda board uses the common PMIC configuration */
-static struct twl4030_platform_data omap4_panda_twldata;
+static struct twl4030_platform_data omap4_panda_twldata = {
+        .audio          = &twl6040_audio,
+};
 
 /*
  * Display monitor features are burnt in their EEPROM as EDID data. The EEPROM
@@ -461,7 +510,7 @@ static struct omap_dss_board_info omap4_panda_dss_data = {
         .default_device = &omap4_panda_dvi_device,
 };
 
-void omap4_panda_display_init(void)
+void __init omap4_panda_display_init(void)
 {
         int r;
 
@@ -485,6 +534,20 @@ void omap4_panda_display_init(void)
         omap_mux_init_gpio(HDMI_GPIO_HPD, OMAP_PIN_INPUT_PULLDOWN);
 }
 
+static void omap4_panda_init_rev(void)
+{
+        if (cpu_is_omap443x()) {
+                /* PandaBoard 4430 */
+                /* ASoC audio configuration */
+                panda_abe_audio_data.card_name = "PandaBoard";
+                panda_abe_audio_data.has_hsmic = 1;
+        } else {
+                /* PandaBoard ES */
+                /* ASoC audio configuration */
+                panda_abe_audio_data.card_name = "PandaBoardES";
+        }
+}
+
 static void __init omap4_panda_init(void)
 {
         int package = OMAP_PACKAGE_CBS;
@@ -498,6 +561,7 @@ static void __init omap4_panda_init(void)
         if (ret)
                 pr_err("error setting wl12xx data: %d\n", ret);
 
+        omap4_panda_init_rev();
         omap4_panda_i2c_init();
         platform_add_devices(panda_devices, ARRAY_SIZE(panda_devices));
         platform_device_register(&omap_vwlan_device);
diff --git a/arch/arm/mach-omap2/board-overo.c b/arch/arm/mach-omap2/board-overo.c
index 52c0cef7716..668533e2a37 100644
--- a/arch/arm/mach-omap2/board-overo.c
+++ b/arch/arm/mach-omap2/board-overo.c
@@ -407,8 +407,6 @@ static inline void __init overo_init_keys(void) { return; }
 static int overo_twl_gpio_setup(struct device *dev,
                 unsigned gpio, unsigned ngpio)
 {
-        omap2_hsmmc_init(mmc);
-
 #if defined(CONFIG_LEDS_GPIO) || defined(CONFIG_LEDS_GPIO_MODULE)
         /* TWL4030_GPIO_MAX + 1 == ledB, PMU_STAT (out, active low LED) */
         gpio_leds[2].gpio = gpio + TWL4030_GPIO_MAX + 1;
@@ -505,6 +503,7 @@ static void __init overo_init(void)
         int ret;
 
         omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
+        omap_hsmmc_init(mmc);
         overo_i2c_init();
         omap_display_init(&overo_dss_data);
         omap_serial_init();
diff --git a/arch/arm/mach-omap2/board-rm680.c b/arch/arm/mach-omap2/board-rm680.c
index 8678b386c6a..ae53d71f0ce 100644
--- a/arch/arm/mach-omap2/board-rm680.c
+++ b/arch/arm/mach-omap2/board-rm680.c
@@ -1,5 +1,5 @@
 /*
- * Board support file for Nokia RM-680.
+ * Board support file for Nokia RM-680/696.
  *
  * Copyright (C) 2010 Nokia
  *
@@ -120,7 +120,7 @@ static void __init rm680_peripherals_init(void)
                                 ARRAY_SIZE(rm680_peripherals_devices));
         rm680_i2c_init();
         gpmc_onenand_init(board_onenand_data);
-        omap2_hsmmc_init(mmc);
+        omap_hsmmc_init(mmc);
 }
 
 #ifdef CONFIG_OMAP_MUX
@@ -154,3 +154,15 @@ MACHINE_START(NOKIA_RM680, "Nokia RM-680 board")
         .timer          = &omap3_timer,
         .restart        = omap_prcm_restart,
 MACHINE_END
+
+MACHINE_START(NOKIA_RM696, "Nokia RM-696 board")
+        .atag_offset    = 0x100,
+        .reserve        = omap_reserve,
+        .map_io         = omap3_map_io,
+        .init_early     = omap3630_init_early,
+        .init_irq       = omap3_init_irq,
+        .handle_irq     = omap3_intc_handle_irq,
+        .init_machine   = rm680_init,
+        .timer          = &omap3_timer,
+        .restart        = omap_prcm_restart,
+MACHINE_END
diff --git a/arch/arm/mach-omap2/board-rx51-peripherals.c b/arch/arm/mach-omap2/board-rx51-peripherals.c
index acb4e77b39e..16aebfb8a7e 100644
--- a/arch/arm/mach-omap2/board-rx51-peripherals.c
+++ b/arch/arm/mach-omap2/board-rx51-peripherals.c
@@ -138,17 +138,14 @@ static struct lp5523_platform_data rx51_lp5523_platform_data = {
 
 static struct omap2_mcspi_device_config wl1251_mcspi_config = {
         .turbo_mode     = 0,
-        .single_channel = 1,
 };
 
 static struct omap2_mcspi_device_config mipid_mcspi_config = {
         .turbo_mode     = 0,
-        .single_channel = 1,
 };
 
 static struct omap2_mcspi_device_config tsc2005_mcspi_config = {
         .turbo_mode     = 0,
-        .single_channel = 1,
 };
 
 static struct spi_board_info rx51_peripherals_spi_board_info[] __initdata = {
@@ -1105,6 +1102,11 @@ static struct tsc2005_platform_data tsc2005_pdata = {
         .esd_timeout_ms         = 8000,
 };
 
+static struct gpio rx51_tsc2005_gpios[] __initdata = {
+        { RX51_TSC2005_IRQ_GPIO,   GPIOF_IN,            "tsc2005 IRQ"   },
+        { RX51_TSC2005_RESET_GPIO, GPIOF_OUT_INIT_HIGH, "tsc2005 reset" },
+};
+
 static void rx51_tsc2005_set_reset(bool enable)
 {
         gpio_set_value(RX51_TSC2005_RESET_GPIO, enable);
@@ -1114,20 +1116,18 @@ static void __init rx51_init_tsc2005(void)
 {
         int r;
 
-        r = gpio_request_one(RX51_TSC2005_IRQ_GPIO, GPIOF_IN, "tsc2005 IRQ");
-        if (r < 0) {
-                printk(KERN_ERR "unable to get %s GPIO\n", "tsc2005 IRQ");
-                rx51_peripherals_spi_board_info[RX51_SPI_TSC2005].irq = 0;
-        }
+        omap_mux_init_gpio(RX51_TSC2005_RESET_GPIO, OMAP_PIN_OUTPUT);
+        omap_mux_init_gpio(RX51_TSC2005_IRQ_GPIO, OMAP_PIN_INPUT_PULLUP);
 
-        r = gpio_request_one(RX51_TSC2005_RESET_GPIO, GPIOF_OUT_INIT_HIGH,
-                "tsc2005 reset");
-        if (r >= 0) {
-                tsc2005_pdata.set_reset = rx51_tsc2005_set_reset;
-        } else {
-                printk(KERN_ERR "unable to get %s GPIO\n", "tsc2005 reset");
+        r = gpio_request_array(rx51_tsc2005_gpios,
+                               ARRAY_SIZE(rx51_tsc2005_gpios));
+        if (r < 0) {
+                printk(KERN_ERR "tsc2005 board initialization failed\n");
                 tsc2005_pdata.esd_timeout_ms = 0;
+                return;
         }
+
+        tsc2005_pdata.set_reset = rx51_tsc2005_set_reset;
 }
 
 void __init rx51_peripherals_init(void)
@@ -1145,7 +1145,7 @@ void __init rx51_peripherals_init(void)
 
         partition = omap_mux_get("core");
         if (partition)
-                omap2_hsmmc_init(mmc);
+                omap_hsmmc_init(mmc);
 
         rx51_charger_init();
 }
diff --git a/arch/arm/mach-omap2/board-zoom-display.c b/arch/arm/mach-omap2/board-zoom-display.c
index d4683ba5f72..a43a765dd09 100644
--- a/arch/arm/mach-omap2/board-zoom-display.c
+++ b/arch/arm/mach-omap2/board-zoom-display.c
@@ -55,6 +55,7 @@ static void zoom_panel_disable_lcd(struct omap_dss_device *dssdev)
 
 static int zoom_set_bl_intensity(struct omap_dss_device *dssdev, int level)
 {
+#ifdef CONFIG_TWL4030_CORE
         unsigned char c;
         u8 mux_pwm, enb_pwm;
 
@@ -90,6 +91,9 @@ static int zoom_set_bl_intensity(struct omap_dss_device *dssdev, int level)
         c = ((50 * (100 - level)) / 100) + 1;
         twl_i2c_write_u8(TWL4030_MODULE_PWM1, 0x7F, TWL_LED_PWMOFF);
         twl_i2c_write_u8(TWL4030_MODULE_PWM1, c, TWL_LED_PWMON);
+#else
+        pr_warn("Backlight not enabled\n");
+#endif
 
         return 0;
 }
@@ -117,7 +121,6 @@ static struct omap_dss_board_info zoom_dss_data = {
 
 static struct omap2_mcspi_device_config dss_lcd_mcspi_config = {
         .turbo_mode             = 1,
-        .single_channel = 1,  /* 0: slave, 1: master */
 };
 
 static struct spi_board_info nec_8048_spi_board_info[] __initdata = {
diff --git a/arch/arm/mach-omap2/board-zoom-peripherals.c b/arch/arm/mach-omap2/board-zoom-peripherals.c
index c126461836a..3d39cdb2e25 100644
--- a/arch/arm/mach-omap2/board-zoom-peripherals.c
+++ b/arch/arm/mach-omap2/board-zoom-peripherals.c
@@ -205,6 +205,7 @@ static struct omap2_hsmmc_info mmc[] = {
                 .caps           = MMC_CAP_4_BIT_DATA,
                 .gpio_wp        = -EINVAL,
                 .power_saving   = true,
+                .deferred       = true,
         },
         {
                 .name           = "internal",
@@ -233,7 +234,7 @@ static int zoom_twl_gpio_setup(struct device *dev,
 
         /* gpio + 0 is "mmc0_cd" (input/IRQ) */
         mmc[0].gpio_cd = gpio + 0;
-        omap2_hsmmc_init(mmc);
+        omap_hsmmc_late_init(mmc);
 
         ret = gpio_request_one(LCD_PANEL_ENABLE_GPIO, GPIOF_OUT_INIT_LOW,
                                "lcd enable");
@@ -301,6 +302,7 @@ void __init zoom_peripherals_init(void)
         if (ret)
                 pr_err("error setting wl12xx data: %d\n", ret);
 
+        omap_hsmmc_init(mmc);
         omap_i2c_init();
         platform_device_register(&omap_vwlan_device);
         usb_musb_init(NULL);
diff --git a/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c b/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c
index 39f9d5a58d0..7072e0d651b 100644
--- a/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c
+++ b/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c
@@ -33,6 +33,7 @@
 #include <linux/cpufreq.h>
 #include <linux/slab.h>
 
+#include <plat/cpu.h>
 #include <plat/clock.h>
 #include <plat/sram.h>
 #include <plat/sdrc.h>
diff --git a/arch/arm/mach-omap2/clkt_clksel.c b/arch/arm/mach-omap2/clkt_clksel.c
index e25364de028..04d551b1f7f 100644
--- a/arch/arm/mach-omap2/clkt_clksel.c
+++ b/arch/arm/mach-omap2/clkt_clksel.c
@@ -43,6 +43,7 @@
 #include <linux/errno.h>
 #include <linux/clk.h>
 #include <linux/io.h>
+#include <linux/bug.h>
 
 #include <plat/clock.h>
 
diff --git a/arch/arm/mach-omap2/clkt_dpll.c b/arch/arm/mach-omap2/clkt_dpll.c
index e069a9be93d..cd7fd0f9114 100644
--- a/arch/arm/mach-omap2/clkt_dpll.c
+++ b/arch/arm/mach-omap2/clkt_dpll.c
@@ -22,6 +22,7 @@
 #include <asm/div64.h>
 
 #include <plat/clock.h>
+#include <plat/cpu.h>
 
 #include "clock.h"
 #include "cm-regbits-24xx.h"
diff --git a/arch/arm/mach-omap2/clock2420_data.c b/arch/arm/mach-omap2/clock2420_data.c
index 61ad3855f10..bace9308a4d 100644
--- a/arch/arm/mach-omap2/clock2420_data.c
+++ b/arch/arm/mach-omap2/clock2420_data.c
@@ -14,11 +14,14 @@
  */
 
 #include <linux/kernel.h>
+#include <linux/io.h>
 #include <linux/clk.h>
 #include <linux/list.h>
 
+#include <plat/hardware.h>
 #include <plat/clkdev_omap.h>
 
+#include "iomap.h"
 #include "clock.h"
 #include "clock2xxx.h"
 #include "opp2xxx.h"
diff --git a/arch/arm/mach-omap2/clock2430.c b/arch/arm/mach-omap2/clock2430.c
index d87bc9cb2a3..dfda9a3f2cb 100644
--- a/arch/arm/mach-omap2/clock2430.c
+++ b/arch/arm/mach-omap2/clock2430.c
@@ -21,8 +21,10 @@
 #include <linux/clk.h>
 #include <linux/io.h>
 
+#include <plat/hardware.h>
 #include <plat/clock.h>
 
+#include "iomap.h"
 #include "clock.h"
 #include "clock2xxx.h"
 #include "cm2xxx_3xxx.h"
diff --git a/arch/arm/mach-omap2/clock2430_data.c b/arch/arm/mach-omap2/clock2430_data.c
index 0cc12879e7b..3b4d09a5039 100644
--- a/arch/arm/mach-omap2/clock2430_data.c
+++ b/arch/arm/mach-omap2/clock2430_data.c
@@ -17,8 +17,10 @@
 #include <linux/clk.h>
 #include <linux/list.h>
 
+#include <plat/hardware.h>
 #include <plat/clkdev_omap.h>
 
+#include "iomap.h"
 #include "clock.h"
 #include "clock2xxx.h"
 #include "opp2xxx.h"
diff --git a/arch/arm/mach-omap2/clock2xxx.c b/arch/arm/mach-omap2/clock2xxx.c
index 80bb0f0e92e..12500097378 100644
--- a/arch/arm/mach-omap2/clock2xxx.c
+++ b/arch/arm/mach-omap2/clock2xxx.c
@@ -22,6 +22,7 @@
 #include <linux/clk.h>
 #include <linux/io.h>
 
+#include <plat/cpu.h>
 #include <plat/clock.h>
 
 #include "clock.h"
diff --git a/arch/arm/mach-omap2/clock3xxx.c b/arch/arm/mach-omap2/clock3xxx.c
index 952c3e01c9e..794d82702c8 100644
--- a/arch/arm/mach-omap2/clock3xxx.c
+++ b/arch/arm/mach-omap2/clock3xxx.c
@@ -21,6 +21,7 @@
 #include <linux/clk.h>
 #include <linux/io.h>
 
+#include <plat/hardware.h>
 #include <plat/clock.h>
 
 #include "clock.h"
diff --git a/arch/arm/mach-omap2/clock3xxx_data.c b/arch/arm/mach-omap2/clock3xxx_data.c
index d75e5f6b8a0..981b9f9111a 100644
--- a/arch/arm/mach-omap2/clock3xxx_data.c
+++ b/arch/arm/mach-omap2/clock3xxx_data.c
@@ -20,14 +20,15 @@
 #include <linux/clk.h>
 #include <linux/list.h>
 
+#include <plat/hardware.h>
 #include <plat/clkdev_omap.h>
 
+#include "iomap.h"
 #include "clock.h"
 #include "clock3xxx.h"
 #include "clock34xx.h"
 #include "clock36xx.h"
 #include "clock3517.h"
-
 #include "cm2xxx_3xxx.h"
 #include "cm-regbits-34xx.h"
 #include "prm2xxx_3xxx.h"
diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c
index 08e86d793a1..79b98f22f20 100644
--- a/arch/arm/mach-omap2/clock44xx_data.c
+++ b/arch/arm/mach-omap2/clock44xx_data.c
@@ -26,8 +26,11 @@
 #include <linux/kernel.h>
 #include <linux/list.h>
 #include <linux/clk.h>
+
+#include <plat/hardware.h>
 #include <plat/clkdev_omap.h>
 
+#include "iomap.h"
 #include "clock.h"
 #include "clock44xx.h"
 #include "cm1_44xx.h"
diff --git a/arch/arm/mach-omap2/cm2xxx_3xxx.c b/arch/arm/mach-omap2/cm2xxx_3xxx.c
index 04d39cdd211..389f9f8b570 100644
--- a/arch/arm/mach-omap2/cm2xxx_3xxx.c
+++ b/arch/arm/mach-omap2/cm2xxx_3xxx.c
@@ -18,8 +18,10 @@
 #include <linux/err.h>
 #include <linux/io.h>
 
-#include "common.h"
+#include <plat/hardware.h>
 
+#include "iomap.h"
+#include "common.h"
 #include "cm.h"
 #include "cm2xxx_3xxx.h"
 #include "cm-regbits-24xx.h"
diff --git a/arch/arm/mach-omap2/cm44xx.c b/arch/arm/mach-omap2/cm44xx.c
index 6a836303252..535d66e2822 100644
--- a/arch/arm/mach-omap2/cm44xx.c
+++ b/arch/arm/mach-omap2/cm44xx.c
@@ -18,8 +18,8 @@
 #include <linux/err.h>
 #include <linux/io.h>
 
+#include "iomap.h"
 #include "common.h"
-
 #include "cm.h"
 #include "cm1_44xx.h"
 #include "cm2_44xx.h"
diff --git a/arch/arm/mach-omap2/cminst44xx.c b/arch/arm/mach-omap2/cminst44xx.c
index 6204deaf85b..bd8810c3753 100644
--- a/arch/arm/mach-omap2/cminst44xx.c
+++ b/arch/arm/mach-omap2/cminst44xx.c
@@ -20,8 +20,8 @@
 #include <linux/err.h>
 #include <linux/io.h>
 
+#include "iomap.h"
 #include "common.h"
-
 #include "cm.h"
 #include "cm1_44xx.h"
 #include "cm2_44xx.h"
diff --git a/arch/arm/mach-omap2/common-board-devices.c b/arch/arm/mach-omap2/common-board-devices.c
index bcb0c581716..9498b0f5fbd 100644
--- a/arch/arm/mach-omap2/common-board-devices.c
+++ b/arch/arm/mach-omap2/common-board-devices.c
@@ -33,7 +33,6 @@
         defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE)
 static struct omap2_mcspi_device_config ads7846_mcspi_config = {
         .turbo_mode     = 0,
-        .single_channel = 1,    /* 0: slave, 1: master */
 };
 
 static struct ads7846_platform_data ads7846_config = {
@@ -76,13 +75,15 @@ void __init omap_ads7846_init(int bus_num, int gpio_pendown, int gpio_debounce,
                         gpio_set_debounce(gpio_pendown, gpio_debounce);
         }
 
-        ads7846_config.gpio_pendown = gpio_pendown;
-
         spi_bi->bus_num = bus_num;
         spi_bi->irq     = OMAP_GPIO_IRQ(gpio_pendown);
 
-        if (board_pdata)
+        if (board_pdata) {
+                board_pdata->gpio_pendown = gpio_pendown;
                 spi_bi->platform_data = board_pdata;
+        } else {
+                ads7846_config.gpio_pendown = gpio_pendown;
+        }
 
         spi_register_board_info(&ads7846_spi_board_info, 1);
 }
diff --git a/arch/arm/mach-omap2/common.c b/arch/arm/mach-omap2/common.c
index aaf421178c9..1549c11000d 100644
--- a/arch/arm/mach-omap2/common.c
+++ b/arch/arm/mach-omap2/common.c
@@ -17,12 +17,13 @@
 #include <linux/clk.h>
 #include <linux/io.h>
 
-#include "common.h"
+#include <plat/hardware.h>
 #include <plat/board.h>
 #include <plat/mux.h>
-
 #include <plat/clock.h>
 
+#include "iomap.h"
+#include "common.h"
 #include "sdrc.h"
 #include "control.h"
 
diff --git a/arch/arm/mach-omap2/common.h b/arch/arm/mach-omap2/common.h
index 7e9338e8d68..57da7f406e2 100644
--- a/arch/arm/mach-omap2/common.h
+++ b/arch/arm/mach-omap2/common.h
@@ -134,6 +134,8 @@ void omap4_map_io(void);
 void ti81xx_map_io(void);
 void omap_barriers_init(void);
 
+extern void __init omap_init_consistent_dma_size(void);
+
 /**
  * omap_test_timeout - busy-loop, testing a condition
  * @cond: condition to test until it evaluates to true
@@ -175,6 +177,18 @@ void omap3_intc_handle_irq(struct pt_regs *regs);
 extern void __iomem *omap4_get_l2cache_base(void);
 #endif
 
+struct device_node;
+#ifdef CONFIG_OF
+int __init omap_intc_of_init(struct device_node *node,
+                             struct device_node *parent);
+#else
+int __init omap_intc_of_init(struct device_node *node,
+                             struct device_node *parent)
+{
+        return 0;
+}
+#endif
+
 #ifdef CONFIG_SMP
 extern void __iomem *omap4_get_scu_base(void);
 #else
@@ -236,5 +250,10 @@ static inline u32 omap4_mpuss_read_prev_context_state(void)
         return 0;
 }
 #endif
+
+struct omap_sdrc_params;
+extern void omap_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
+                                      struct omap_sdrc_params *sdrc_cs1);
+
 #endif /* __ASSEMBLER__ */
 #endif /* __ARCH_ARM_MACH_OMAP2PLUS_COMMON_H */
diff --git a/arch/arm/mach-omap2/control.c b/arch/arm/mach-omap2/control.c
index 114c037e433..08e674bb041 100644
--- a/arch/arm/mach-omap2/control.c
+++ b/arch/arm/mach-omap2/control.c
@@ -15,9 +15,11 @@
 #include <linux/kernel.h>
 #include <linux/io.h>
 
-#include "common.h"
+#include <plat/hardware.h>
 #include <plat/sdrc.h>
 
+#include "iomap.h"
+#include "common.h"
 #include "cm-regbits-34xx.h"
 #include "prm-regbits-34xx.h"
 #include "prm2xxx_3xxx.h"
diff --git a/arch/arm/mach-omap2/control.h b/arch/arm/mach-omap2/control.h
index 0ba68d3764b..a406fd045ce 100644
--- a/arch/arm/mach-omap2/control.h
+++ b/arch/arm/mach-omap2/control.h
@@ -16,7 +16,6 @@
 #ifndef __ARCH_ARM_MACH_OMAP2_CONTROL_H
 #define __ARCH_ARM_MACH_OMAP2_CONTROL_H
 
-#include <mach/io.h>
 #include <mach/ctrl_module_core_44xx.h>
 #include <mach/ctrl_module_wkup_44xx.h>
 #include <mach/ctrl_module_pad_core_44xx.h>
@@ -339,6 +338,11 @@
 #define AM35XX_VPFE_PCLK_SW_RST         BIT(4)
 
 /*
+ * CONTROL AM33XX STATUS register
+ */
+#define AM33XX_CONTROL_STATUS           0x040
+
+/*
  * CONTROL OMAP STATUS register to identify OMAP3 features
  */
 #define OMAP3_CONTROL_OMAP_STATUS       0x044c
diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c
index 283d11eae69..e4336035c0e 100644
--- a/arch/arm/mach-omap2/devices.c
+++ b/arch/arm/mach-omap2/devices.c
@@ -17,6 +17,7 @@
 #include <linux/err.h>
 #include <linux/slab.h>
 #include <linux/of.h>
+#include <linux/platform_data/omap4-keypad.h>
 
 #include <mach/hardware.h>
 #include <mach/irqs.h>
@@ -24,9 +25,8 @@
 #include <asm/mach/map.h>
 #include <asm/pmu.h>
 
-#include <plat/tc.h>
+#include "iomap.h"
 #include <plat/board.h>
-#include <plat/mcbsp.h>
 #include <plat/mmc.h>
 #include <plat/dma.h>
 #include <plat/omap_hwmod.h>
@@ -276,7 +276,7 @@ int __init omap4_keyboard_init(struct omap4_keypad_platform_data
 }
 
 #if defined(CONFIG_OMAP_MBOX_FWK) || defined(CONFIG_OMAP_MBOX_FWK_MODULE)
-static inline void omap_init_mbox(void)
+static inline void __init omap_init_mbox(void)
 {
         struct omap_hwmod *oh;
         struct platform_device *pdev;
@@ -304,29 +304,8 @@ static struct platform_device omap_pcm = {
         .id     = -1,
 };
 
-/*
- * OMAP2420 has 2 McBSP ports
- * OMAP2430 has 5 McBSP ports
- * OMAP3 has 5 McBSP ports
- * OMAP4 has 4 McBSP ports
- */
-OMAP_MCBSP_PLATFORM_DEVICE(1);
-OMAP_MCBSP_PLATFORM_DEVICE(2);
-OMAP_MCBSP_PLATFORM_DEVICE(3);
-OMAP_MCBSP_PLATFORM_DEVICE(4);
-OMAP_MCBSP_PLATFORM_DEVICE(5);
-
 static void omap_init_audio(void)
 {
-        platform_device_register(&omap_mcbsp1);
-        platform_device_register(&omap_mcbsp2);
-        if (cpu_is_omap243x() || cpu_is_omap34xx() || cpu_is_omap44xx()) {
-                platform_device_register(&omap_mcbsp3);
-                platform_device_register(&omap_mcbsp4);
-        }
-        if (cpu_is_omap243x() || cpu_is_omap34xx())
-                platform_device_register(&omap_mcbsp5);
-
         platform_device_register(&omap_pcm);
 }
 
@@ -337,7 +316,7 @@ static inline void omap_init_audio(void) {}
 #if defined(CONFIG_SND_OMAP_SOC_MCPDM) || \
                 defined(CONFIG_SND_OMAP_SOC_MCPDM_MODULE)
 
-static void omap_init_mcpdm(void)
+static void __init omap_init_mcpdm(void)
 {
         struct omap_hwmod *oh;
         struct platform_device *pdev;
@@ -358,7 +337,7 @@ static inline void omap_init_mcpdm(void) {}
 #if defined(CONFIG_SND_OMAP_SOC_DMIC) || \
                 defined(CONFIG_SND_OMAP_SOC_DMIC_MODULE)
 
-static void omap_init_dmic(void)
+static void __init omap_init_dmic(void)
 {
         struct omap_hwmod *oh;
         struct platform_device *pdev;
@@ -380,7 +359,7 @@ static inline void omap_init_dmic(void) {}
 
 #include <plat/mcspi.h>
 
-static int omap_mcspi_init(struct omap_hwmod *oh, void *unused)
+static int __init omap_mcspi_init(struct omap_hwmod *oh, void *unused)
 {
         struct platform_device *pdev;
         char *name = "omap2_mcspi";
@@ -654,9 +633,7 @@ void __init omap242x_init_mmc(struct omap_mmc_platform_data **mmc_data)
 /*-------------------------------------------------------------------------*/
 
 #if defined(CONFIG_HDQ_MASTER_OMAP) || defined(CONFIG_HDQ_MASTER_OMAP_MODULE)
-#if defined(CONFIG_SOC_OMAP2430) || defined(CONFIG_SOC_OMAP3430)
 #define OMAP_HDQ_BASE   0x480B2000
-#endif
 static struct resource omap_hdq_resources[] = {
         {
                 .start          = OMAP_HDQ_BASE,
@@ -679,7 +656,10 @@ static struct platform_device omap_hdq_dev = {
 };
 static inline void omap_hdq_init(void)
 {
-        (void) platform_device_register(&omap_hdq_dev);
+        if (cpu_is_omap2420())
+                return;
+
+        platform_device_register(&omap_hdq_dev);
 }
 #else
 static inline void omap_hdq_init(void) {}
diff --git a/arch/arm/mach-omap2/display.c b/arch/arm/mach-omap2/display.c
index 3677b1f58b8..9706c648bc1 100644
--- a/arch/arm/mach-omap2/display.c
+++ b/arch/arm/mach-omap2/display.c
@@ -30,6 +30,7 @@
 #include <plat/omap-pm.h>
 #include "common.h"
 
+#include "iomap.h"
 #include "mux.h"
 #include "control.h"
 #include "display.h"
@@ -124,7 +125,7 @@ static void omap4_hdmi_mux_pads(enum omap_hdmi_flags flags)
         }
 }
 
-static int omap4_dsi_mux_pads(int dsi_id, unsigned lanes)
+static int __init omap4_dsi_mux_pads(int dsi_id, unsigned lanes)
 {
         u32 enable_mask, enable_shift;
         u32 pipd_mask, pipd_shift;
@@ -157,7 +158,7 @@ static int omap4_dsi_mux_pads(int dsi_id, unsigned lanes)
         return 0;
 }
 
-int omap_hdmi_init(enum omap_hdmi_flags flags)
+int __init omap_hdmi_init(enum omap_hdmi_flags flags)
 {
         if (cpu_is_omap44xx())
                 omap4_hdmi_mux_pads(flags);
@@ -165,7 +166,7 @@ int omap_hdmi_init(enum omap_hdmi_flags flags)
         return 0;
 }
 
-static int omap_dsi_enable_pads(int dsi_id, unsigned lane_mask)
+static int __init omap_dsi_enable_pads(int dsi_id, unsigned lane_mask)
 {
         if (cpu_is_omap44xx())
                 return omap4_dsi_mux_pads(dsi_id, lane_mask);
@@ -173,7 +174,7 @@ static int omap_dsi_enable_pads(int dsi_id, unsigned lane_mask)
         return 0;
 }
 
-static void omap_dsi_disable_pads(int dsi_id, unsigned lane_mask)
+static void __init omap_dsi_disable_pads(int dsi_id, unsigned lane_mask)
 {
         if (cpu_is_omap44xx())
                 omap4_dsi_mux_pads(dsi_id, 0);
diff --git a/arch/arm/mach-omap2/dma.c b/arch/arm/mach-omap2/dma.c
index a59a45a0096..b19d8496c16 100644
--- a/arch/arm/mach-omap2/dma.c
+++ b/arch/arm/mach-omap2/dma.c
@@ -227,7 +227,7 @@ static int __init omap2_system_dma_init_dev(struct omap_hwmod *oh, void *unused)
 
         dma_stride              = OMAP2_DMA_STRIDE;
         dma_common_ch_start     = CSDP;
-        if (cpu_is_omap3630() || cpu_is_omap4430())
+        if (cpu_is_omap3630() || cpu_is_omap44xx())
                 dma_common_ch_end = CCDN;
         else
                 dma_common_ch_end = CCFN;
diff --git a/arch/arm/mach-omap2/emu.c b/arch/arm/mach-omap2/emu.c
index 9c442e290cc..e28e761b7ab 100644
--- a/arch/arm/mach-omap2/emu.c
+++ b/arch/arm/mach-omap2/emu.c
@@ -21,6 +21,10 @@
 #include <linux/clk.h>
 #include <linux/err.h>
 
+#include <mach/hardware.h>
+
+#include "iomap.h"
+
 MODULE_LICENSE("GPL");
 MODULE_AUTHOR("Alexander Shishkin");
 
@@ -30,29 +34,8 @@ MODULE_AUTHOR("Alexander Shishkin");
 #define ETB_BASE        (L4_EMU_34XX_PHYS + 0x1b000)
 #define DAPCTL          (L4_EMU_34XX_PHYS + 0x1d000)
 
-static struct amba_device omap3_etb_device = {
-        .dev            = {
-                .init_name = "etb",
-        },
-        .res            = {
-                .start  = ETB_BASE,
-                .end    = ETB_BASE + SZ_4K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        .periphid       = 0x000bb907,
-};
-
-static struct amba_device omap3_etm_device = {
-        .dev            = {
-                .init_name = "etm",
-        },
-        .res            = {
-                .start  = ETM_BASE,
-                .end    = ETM_BASE + SZ_4K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        .periphid       = 0x102bb921,
-};
+static AMBA_APB_DEVICE(omap3_etb, "etb", 0x000bb907, ETB_BASE, { }, NULL);
+static AMBA_APB_DEVICE(omap3_etm, "etm", 0x102bb921, ETM_BASE, { }, NULL);
 
 static int __init emu_init(void)
 {
@@ -66,4 +49,3 @@ static int __init emu_init(void)
 }
 
 subsys_initcall(emu_init);
-
diff --git a/arch/arm/mach-omap2/gpio.c b/arch/arm/mach-omap2/gpio.c
index 8cbfbc2918c..2f994e5194e 100644
--- a/arch/arm/mach-omap2/gpio.c
+++ b/arch/arm/mach-omap2/gpio.c
@@ -23,14 +23,18 @@
 
 #include <plat/omap_hwmod.h>
 #include <plat/omap_device.h>
+#include <plat/omap-pm.h>
 
-static int omap2_gpio_dev_init(struct omap_hwmod *oh, void *unused)
+#include "powerdomain.h"
+
+static int __init omap2_gpio_dev_init(struct omap_hwmod *oh, void *unused)
 {
         struct platform_device *pdev;
         struct omap_gpio_platform_data *pdata;
         struct omap_gpio_dev_attr *dev_attr;
         char *name = "omap_gpio";
         int id;
+        struct powerdomain *pwrdm;
 
         /*
          * extract the device id from name field available in the
@@ -52,7 +56,7 @@ static int omap2_gpio_dev_init(struct omap_hwmod *oh, void *unused)
         pdata->bank_width = dev_attr->bank_width;
         pdata->dbck_flag = dev_attr->dbck_flag;
         pdata->virtual_irq_start = IH_GPIO_BASE + 32 * (id - 1);
-
+        pdata->get_context_loss_count = omap_pm_get_dev_context_loss_count;
         pdata->regs = kzalloc(sizeof(struct omap_gpio_reg_offs), GFP_KERNEL);
         if (!pdata) {
                 pr_err("gpio%d: Memory allocation failed\n", id);
@@ -61,8 +65,15 @@ static int omap2_gpio_dev_init(struct omap_hwmod *oh, void *unused)
 
         switch (oh->class->rev) {
         case 0:
+                if (id == 1)
+                        /* non-wakeup GPIO pins for OMAP2 Bank1 */
+                        pdata->non_wakeup_gpios = 0xe203ffc0;
+                else if (id == 2)
+                        /* non-wakeup GPIO pins for OMAP2 Bank2 */
+                        pdata->non_wakeup_gpios = 0x08700040;
+                /* fall through */
+
         case 1:
-                pdata->bank_type = METHOD_GPIO_24XX;
                 pdata->regs->revision = OMAP24XX_GPIO_REVISION;
                 pdata->regs->direction = OMAP24XX_GPIO_OE;
                 pdata->regs->datain = OMAP24XX_GPIO_DATAIN;
@@ -72,13 +83,19 @@ static int omap2_gpio_dev_init(struct omap_hwmod *oh, void *unused)
                 pdata->regs->irqstatus = OMAP24XX_GPIO_IRQSTATUS1;
                 pdata->regs->irqstatus2 = OMAP24XX_GPIO_IRQSTATUS2;
                 pdata->regs->irqenable = OMAP24XX_GPIO_IRQENABLE1;
+                pdata->regs->irqenable2 = OMAP24XX_GPIO_IRQENABLE2;
                 pdata->regs->set_irqenable = OMAP24XX_GPIO_SETIRQENABLE1;
                 pdata->regs->clr_irqenable = OMAP24XX_GPIO_CLEARIRQENABLE1;
                 pdata->regs->debounce = OMAP24XX_GPIO_DEBOUNCE_VAL;
                 pdata->regs->debounce_en = OMAP24XX_GPIO_DEBOUNCE_EN;
+                pdata->regs->ctrl = OMAP24XX_GPIO_CTRL;
+                pdata->regs->wkup_en = OMAP24XX_GPIO_WAKE_EN;
+                pdata->regs->leveldetect0 = OMAP24XX_GPIO_LEVELDETECT0;
+                pdata->regs->leveldetect1 = OMAP24XX_GPIO_LEVELDETECT1;
+                pdata->regs->risingdetect = OMAP24XX_GPIO_RISINGDETECT;
+                pdata->regs->fallingdetect = OMAP24XX_GPIO_FALLINGDETECT;
                 break;
         case 2:
-                pdata->bank_type = METHOD_GPIO_44XX;
                 pdata->regs->revision = OMAP4_GPIO_REVISION;
                 pdata->regs->direction = OMAP4_GPIO_OE;
                 pdata->regs->datain = OMAP4_GPIO_DATAIN;
@@ -88,10 +105,17 @@ static int omap2_gpio_dev_init(struct omap_hwmod *oh, void *unused)
                 pdata->regs->irqstatus = OMAP4_GPIO_IRQSTATUS0;
                 pdata->regs->irqstatus2 = OMAP4_GPIO_IRQSTATUS1;
                 pdata->regs->irqenable = OMAP4_GPIO_IRQSTATUSSET0;
+                pdata->regs->irqenable2 = OMAP4_GPIO_IRQSTATUSSET1;
                 pdata->regs->set_irqenable = OMAP4_GPIO_IRQSTATUSSET0;
                 pdata->regs->clr_irqenable = OMAP4_GPIO_IRQSTATUSCLR0;
                 pdata->regs->debounce = OMAP4_GPIO_DEBOUNCINGTIME;
                 pdata->regs->debounce_en = OMAP4_GPIO_DEBOUNCENABLE;
+                pdata->regs->ctrl = OMAP4_GPIO_CTRL;
+                pdata->regs->wkup_en = OMAP4_GPIO_IRQWAKEN0;
+                pdata->regs->leveldetect0 = OMAP4_GPIO_LEVELDETECT0;
+                pdata->regs->leveldetect1 = OMAP4_GPIO_LEVELDETECT1;
+                pdata->regs->risingdetect = OMAP4_GPIO_RISINGDETECT;
+                pdata->regs->fallingdetect = OMAP4_GPIO_FALLINGDETECT;
                 break;
         default:
                 WARN(1, "Invalid gpio bank_type\n");
@@ -99,6 +123,9 @@ static int omap2_gpio_dev_init(struct omap_hwmod *oh, void *unused)
                 return -EINVAL;
         }
 
+        pwrdm = omap_hwmod_get_pwrdm(oh);
+        pdata->loses_context = pwrdm_can_ever_lose_context(pwrdm);
+
         pdev = omap_device_build(name, id - 1, oh, pdata,
                                 sizeof(*pdata), NULL, 0, false);
         kfree(pdata);
@@ -109,9 +136,6 @@ static int omap2_gpio_dev_init(struct omap_hwmod *oh, void *unused)
                 return PTR_ERR(pdev);
         }
 
-        omap_device_disable_idle_on_suspend(pdev);
-
-        gpio_bank_count++;
         return 0;
 }
 
diff --git a/arch/arm/mach-omap2/gpmc-nand.c b/arch/arm/mach-omap2/gpmc-nand.c
index 8ad210bda9a..386dec8d235 100644
--- a/arch/arm/mach-omap2/gpmc-nand.c
+++ b/arch/arm/mach-omap2/gpmc-nand.c
@@ -16,6 +16,7 @@
 
 #include <asm/mach/flash.h>
 
+#include <plat/cpu.h>
 #include <plat/nand.h>
 #include <plat/board.h>
 #include <plat/gpmc.h>
diff --git a/arch/arm/mach-omap2/gpmc-onenand.c b/arch/arm/mach-omap2/gpmc-onenand.c
index 5cdce10d618..385b3e02c4a 100644
--- a/arch/arm/mach-omap2/gpmc-onenand.c
+++ b/arch/arm/mach-omap2/gpmc-onenand.c
@@ -18,6 +18,7 @@
 
 #include <asm/mach/flash.h>
 
+#include <plat/cpu.h>
 #include <plat/onenand.h>
 #include <plat/board.h>
 #include <plat/gpmc.h>
diff --git a/arch/arm/mach-omap2/gpmc-smsc911x.c b/arch/arm/mach-omap2/gpmc-smsc911x.c
index bbb870c04a5..5e5880d6d09 100644
--- a/arch/arm/mach-omap2/gpmc-smsc911x.c
+++ b/arch/arm/mach-omap2/gpmc-smsc911x.c
@@ -101,10 +101,13 @@ void __init gpmc_smsc911x_init(struct omap_smsc911x_platform_data *board_data)
 
         gpmc_cfg = board_data;
 
-        ret = platform_device_register(&gpmc_smsc911x_regulator);
-        if (ret < 0) {
-                pr_err("Unable to register smsc911x regulators: %d\n", ret);
-                return;
+        if (!gpmc_cfg->id) {
+                ret = platform_device_register(&gpmc_smsc911x_regulator);
+                if (ret < 0) {
+                        pr_err("Unable to register smsc911x regulators: %d\n",
+                               ret);
+                        return;
+                }
         }
 
         if (gpmc_cs_request(gpmc_cfg->cs, SZ_16M, &cs_mem_base) < 0) {
diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c
index dfffbbf4c00..00d510858e2 100644
--- a/arch/arm/mach-omap2/gpmc.c
+++ b/arch/arm/mach-omap2/gpmc.c
@@ -888,6 +888,7 @@ int gpmc_enable_hwecc(int cs, int mode, int dev_width, int ecc_size)
         gpmc_write_reg(GPMC_ECC_CONFIG, val);
         return 0;
 }
+EXPORT_SYMBOL_GPL(gpmc_enable_hwecc);
 
 /**
  * gpmc_calculate_ecc - generate non-inverted ecc bytes
@@ -918,3 +919,4 @@ int gpmc_calculate_ecc(int cs, const u_char *dat, u_char *ecc_code)
         gpmc_ecc_used = -EINVAL;
         return 0;
 }
+EXPORT_SYMBOL_GPL(gpmc_calculate_ecc);
diff --git a/arch/arm/mach-omap2/hsmmc.c b/arch/arm/mach-omap2/hsmmc.c
index 19dd1657245..8121720e942 100644
--- a/arch/arm/mach-omap2/hsmmc.c
+++ b/arch/arm/mach-omap2/hsmmc.c
@@ -293,8 +293,8 @@ static inline void omap_hsmmc_mux(struct omap_mmc_platform_data *mmc_controller,
         }
 }
 
-static int omap_hsmmc_pdata_init(struct omap2_hsmmc_info *c,
-                                 struct omap_mmc_platform_data *mmc)
+static int __init omap_hsmmc_pdata_init(struct omap2_hsmmc_info *c,
+                                        struct omap_mmc_platform_data *mmc)
 {
         char *hc_name;
 
@@ -429,66 +429,131 @@ static int omap_hsmmc_pdata_init(struct omap2_hsmmc_info *c,
 }
 
 static int omap_hsmmc_done;
+
+void omap_hsmmc_late_init(struct omap2_hsmmc_info *c)
+{
+        struct platform_device *pdev;
+        struct omap_mmc_platform_data *mmc_pdata;
+        int res;
+
+        if (omap_hsmmc_done != 1)
+                return;
+
+        omap_hsmmc_done++;
+
+        for (; c->mmc; c++) {
+                if (!c->deferred)
+                        continue;
+
+                pdev = c->pdev;
+                if (!pdev)
+                        continue;
+
+                mmc_pdata = pdev->dev.platform_data;
+                if (!mmc_pdata)
+                        continue;
+
+                mmc_pdata->slots[0].switch_pin = c->gpio_cd;
+                mmc_pdata->slots[0].gpio_wp = c->gpio_wp;
+
+                res = omap_device_register(pdev);
+                if (res)
+                        pr_err("Could not late init MMC %s\n",
+                               c->name);
+        }
+}
+
 #define MAX_OMAP_MMC_HWMOD_NAME_LEN             16
 
-void omap_init_hsmmc(struct omap2_hsmmc_info *hsmmcinfo, int ctrl_nr)
+static void __init omap_hsmmc_init_one(struct omap2_hsmmc_info *hsmmcinfo,
+                                        int ctrl_nr)
 {
         struct omap_hwmod *oh;
+        struct omap_hwmod *ohs[1];
+        struct omap_device *od;
         struct platform_device *pdev;
         char oh_name[MAX_OMAP_MMC_HWMOD_NAME_LEN];
         struct omap_mmc_platform_data *mmc_data;
         struct omap_mmc_dev_attr *mmc_dev_attr;
         char *name;
-        int l;
+        int res;
 
         mmc_data = kzalloc(sizeof(struct omap_mmc_platform_data), GFP_KERNEL);
         if (!mmc_data) {
                 pr_err("Cannot allocate memory for mmc device!\n");
-                goto done;
+                return;
         }
 
-        if (omap_hsmmc_pdata_init(hsmmcinfo, mmc_data) < 0) {
-                pr_err("%s fails!\n", __func__);
-                goto done;
-        }
+        res = omap_hsmmc_pdata_init(hsmmcinfo, mmc_data);
+        if (res < 0)
+                goto free_mmc;
+
         omap_hsmmc_mux(mmc_data, (ctrl_nr - 1));
 
         name = "omap_hsmmc";
-
-        l = snprintf(oh_name, MAX_OMAP_MMC_HWMOD_NAME_LEN,
+        res = snprintf(oh_name, MAX_OMAP_MMC_HWMOD_NAME_LEN,
                      "mmc%d", ctrl_nr);
-        WARN(l >= MAX_OMAP_MMC_HWMOD_NAME_LEN,
+        WARN(res >= MAX_OMAP_MMC_HWMOD_NAME_LEN,
              "String buffer overflow in MMC%d device setup\n", ctrl_nr);
+
         oh = omap_hwmod_lookup(oh_name);
         if (!oh) {
                 pr_err("Could not look up %s\n", oh_name);
-                kfree(mmc_data->slots[0].name);
-                goto done;
+                goto free_name;
         }
-
+        ohs[0] = oh;
         if (oh->dev_attr != NULL) {
                 mmc_dev_attr = oh->dev_attr;
                 mmc_data->controller_flags = mmc_dev_attr->flags;
         }
 
-        pdev = omap_device_build(name, ctrl_nr - 1, oh, mmc_data,
-                sizeof(struct omap_mmc_platform_data), NULL, 0, false);
-        if (IS_ERR(pdev)) {
-                WARN(1, "Can't build omap_device for %s:%s.\n", name, oh->name);
-                kfree(mmc_data->slots[0].name);
-                goto done;
+        pdev = platform_device_alloc(name, ctrl_nr - 1);
+        if (!pdev) {
+                pr_err("Could not allocate pdev for %s\n", name);
+                goto free_name;
         }
-        /*
-         * return device handle to board setup code
-         * required to populate for regulator framework structure
-         */
-        hsmmcinfo->dev = &pdev->dev;
+        dev_set_name(&pdev->dev, "%s.%d", pdev->name, pdev->id);
+
+        od = omap_device_alloc(pdev, ohs, 1, NULL, 0);
+        if (!od) {
+                pr_err("Could not allocate od for %s\n", name);
+                goto put_pdev;
+        }
+
+        res = platform_device_add_data(pdev, mmc_data,
+                              sizeof(struct omap_mmc_platform_data));
+        if (res) {
+                pr_err("Could not add pdata for %s\n", name);
+                goto put_pdev;
+        }
+
+        hsmmcinfo->pdev = pdev;
+
+        if (hsmmcinfo->deferred)
+                goto free_mmc;
+
+        res = omap_device_register(pdev);
+        if (res) {
+                pr_err("Could not register od for %s\n", name);
+                goto free_od;
+        }
+
+        goto free_mmc;
+
+free_od:
+        omap_device_delete(od);
+
+put_pdev:
+        platform_device_put(pdev);
+
+free_name:
+        kfree(mmc_data->slots[0].name);
 
-done:
+free_mmc:
         kfree(mmc_data);
 }
 
-void omap2_hsmmc_init(struct omap2_hsmmc_info *controllers)
+void __init omap_hsmmc_init(struct omap2_hsmmc_info *controllers)
 {
         u32 reg;
 
@@ -521,7 +586,7 @@ void omap2_hsmmc_init(struct omap2_hsmmc_info *controllers)
         }
 
         for (; controllers->mmc; controllers++)
-                omap_init_hsmmc(controllers, controllers->mmc);
+                omap_hsmmc_init_one(controllers, controllers->mmc);
 
 }
 
diff --git a/arch/arm/mach-omap2/hsmmc.h b/arch/arm/mach-omap2/hsmmc.h
index c4409730c4b..07831cc3c17 100644
--- a/arch/arm/mach-omap2/hsmmc.h
+++ b/arch/arm/mach-omap2/hsmmc.h
@@ -21,10 +21,11 @@ struct omap2_hsmmc_info {
         bool    no_off;         /* power_saving and power is not to go off */
         bool    no_off_init;    /* no power off when not in MMC sleep state */
         bool    vcc_aux_disable_is_sleep; /* Regulator off remapped to sleep */
+        bool    deferred;       /* mmc needs a deferred probe */
         int     gpio_cd;        /* or -EINVAL */
         int     gpio_wp;        /* or -EINVAL */
         char    *name;          /* or NULL for default */
-        struct device *dev;     /* returned: pointer to mmc adapter */
+        struct platform_device *pdev;   /* mmc controller instance */
         int     ocr_mask;       /* temporary HACK */
         /* Remux (pad configuration) when powering on/off */
         void (*remux)(struct device *dev, int slot, int power_on);
@@ -34,11 +35,16 @@ struct omap2_hsmmc_info {
 
 #if defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE)
 
-void omap2_hsmmc_init(struct omap2_hsmmc_info *);
+void omap_hsmmc_init(struct omap2_hsmmc_info *);
+void omap_hsmmc_late_init(struct omap2_hsmmc_info *);
 
 #else
 
-static inline void omap2_hsmmc_init(struct omap2_hsmmc_info *info)
+static inline void omap_hsmmc_init(struct omap2_hsmmc_info *info)
+{
+}
+
+static inline void omap_hsmmc_late_init(struct omap2_hsmmc_info *info)
 {
 }
 
diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c
index 719ee423abe..0e79b7bc6aa 100644
--- a/arch/arm/mach-omap2/id.c
+++ b/arch/arm/mach-omap2/id.c
@@ -29,7 +29,7 @@
 #include "control.h"
 
 static unsigned int omap_revision;
-
+static const char *cpu_rev;
 u32 omap_features;
 
 unsigned int omap_rev(void)
@@ -44,6 +44,8 @@ int omap_type(void)
 
         if (cpu_is_omap24xx()) {
                 val = omap_ctrl_readl(OMAP24XX_CONTROL_STATUS);
+        } else if (cpu_is_am33xx()) {
+                val = omap_ctrl_readl(AM33XX_CONTROL_STATUS);
         } else if (cpu_is_omap34xx()) {
                 val = omap_ctrl_readl(OMAP343X_CONTROL_STATUS);
         } else if (cpu_is_omap44xx()) {
@@ -112,7 +114,7 @@ void omap_get_die_id(struct omap_die_id *odi)
         odi->id_3 = read_tap_reg(OMAP_TAP_DIE_ID_3);
 }
 
-static void __init omap24xx_check_revision(void)
+void __init omap2xxx_check_revision(void)
 {
         int i, j;
         u32 idcode, prod_id;
@@ -166,13 +168,63 @@ static void __init omap24xx_check_revision(void)
         pr_info("\n");
 }
 
+#define OMAP3_SHOW_FEATURE(feat)                \
+        if (omap3_has_ ##feat())                \
+                printk(#feat" ");
+
+static void __init omap3_cpuinfo(void)
+{
+        const char *cpu_name;
+
+        /*
+         * OMAP3430 and OMAP3530 are assumed to be same.
+         *
+         * OMAP3525, OMAP3515 and OMAP3503 can be detected only based
+         * on available features. Upon detection, update the CPU id
+         * and CPU class bits.
+         */
+        if (cpu_is_omap3630()) {
+                cpu_name = "OMAP3630";
+        } else if (cpu_is_omap3517()) {
+                /* AM35xx devices */
+                cpu_name = (omap3_has_sgx()) ? "AM3517" : "AM3505";
+        } else if (cpu_is_ti816x()) {
+                cpu_name = "TI816X";
+        } else if (cpu_is_am335x()) {
+                cpu_name =  "AM335X";
+        } else if (cpu_is_ti814x()) {
+                cpu_name = "TI814X";
+        } else if (omap3_has_iva() && omap3_has_sgx()) {
+                /* OMAP3430, OMAP3525, OMAP3515, OMAP3503 devices */
+                cpu_name = "OMAP3430/3530";
+        } else if (omap3_has_iva()) {
+                cpu_name = "OMAP3525";
+        } else if (omap3_has_sgx()) {
+                cpu_name = "OMAP3515";
+        } else {
+                cpu_name = "OMAP3503";
+        }
+
+        /* Print verbose information */
+        pr_info("%s ES%s (", cpu_name, cpu_rev);
+
+        OMAP3_SHOW_FEATURE(l2cache);
+        OMAP3_SHOW_FEATURE(iva);
+        OMAP3_SHOW_FEATURE(sgx);
+        OMAP3_SHOW_FEATURE(neon);
+        OMAP3_SHOW_FEATURE(isp);
+        OMAP3_SHOW_FEATURE(192mhz_clk);
+
+        printk(")\n");
+}
+
 #define OMAP3_CHECK_FEATURE(status,feat)                                \
         if (((status & OMAP3_ ##feat## _MASK)                           \
                 >> OMAP3_ ##feat## _SHIFT) != FEAT_ ##feat## _NONE) {   \
                 omap_features |= OMAP3_HAS_ ##feat;                     \
         }
 
-static void __init omap3_check_features(void)
+void __init omap3xxx_check_features(void)
 {
         u32 status;
 
@@ -199,9 +251,11 @@ static void __init omap3_check_features(void)
          * TODO: Get additional info (where applicable)
          *       e.g. Size of L2 cache.
          */
+
+        omap3_cpuinfo();
 }
 
-static void __init omap4_check_features(void)
+void __init omap4xxx_check_features(void)
 {
         u32 si_type;
 
@@ -226,12 +280,13 @@ static void __init omap4_check_features(void)
         }
 }
 
-static void __init ti81xx_check_features(void)
+void __init ti81xx_check_features(void)
 {
         omap_features = OMAP3_HAS_NEON;
+        omap3_cpuinfo();
 }
 
-static void __init omap3_check_revision(const char **cpu_rev)
+void __init omap3xxx_check_revision(void)
 {
         u32 cpuid, idcode;
         u16 hawkeye;
@@ -245,7 +300,7 @@ static void __init omap3_check_revision(const char **cpu_rev)
         cpuid = read_cpuid(CPUID_ID);
         if ((((cpuid >> 4) & 0xfff) == 0xc08) && ((cpuid & 0xf) == 0x0)) {
                 omap_revision = OMAP3430_REV_ES1_0;
-                *cpu_rev = "1.0";
+                cpu_rev = "1.0";
                 return;
         }
 
@@ -266,26 +321,26 @@ static void __init omap3_check_revision(const char **cpu_rev)
                 case 0: /* Take care of early samples */
                 case 1:
                         omap_revision = OMAP3430_REV_ES2_0;
-                        *cpu_rev = "2.0";
+                        cpu_rev = "2.0";
                         break;
                 case 2:
                         omap_revision = OMAP3430_REV_ES2_1;
-                        *cpu_rev = "2.1";
+                        cpu_rev = "2.1";
                         break;
                 case 3:
                         omap_revision = OMAP3430_REV_ES3_0;
-                        *cpu_rev = "3.0";
+                        cpu_rev = "3.0";
                         break;
                 case 4:
                         omap_revision = OMAP3430_REV_ES3_1;
-                        *cpu_rev = "3.1";
+                        cpu_rev = "3.1";
                         break;
                 case 7:
                 /* FALLTHROUGH */
                 default:
                         /* Use the latest known revision as default */
                         omap_revision = OMAP3430_REV_ES3_1_2;
-                        *cpu_rev = "3.1.2";
+                        cpu_rev = "3.1.2";
                 }
                 break;
         case 0xb868:
@@ -298,13 +353,13 @@ static void __init omap3_check_revision(const char **cpu_rev)
                 switch (rev) {
                 case 0:
                         omap_revision = OMAP3517_REV_ES1_0;
-                        *cpu_rev = "1.0";
+                        cpu_rev = "1.0";
                         break;
                 case 1:
                 /* FALLTHROUGH */
                 default:
                         omap_revision = OMAP3517_REV_ES1_1;
-                        *cpu_rev = "1.1";
+                        cpu_rev = "1.1";
                 }
                 break;
         case 0xb891:
@@ -313,36 +368,36 @@ static void __init omap3_check_revision(const char **cpu_rev)
                 switch(rev) {
                 case 0: /* Take care of early samples */
                         omap_revision = OMAP3630_REV_ES1_0;
-                        *cpu_rev = "1.0";
+                        cpu_rev = "1.0";
                         break;
                 case 1:
                         omap_revision = OMAP3630_REV_ES1_1;
-                        *cpu_rev = "1.1";
+                        cpu_rev = "1.1";
                         break;
                 case 2:
                 /* FALLTHROUGH */
                 default:
                         omap_revision = OMAP3630_REV_ES1_2;
-                        *cpu_rev = "1.2";
+                        cpu_rev = "1.2";
                 }
                 break;
         case 0xb81e:
                 switch (rev) {
                 case 0:
                         omap_revision = TI8168_REV_ES1_0;
-                        *cpu_rev = "1.0";
+                        cpu_rev = "1.0";
                         break;
                 case 1:
                 /* FALLTHROUGH */
                 default:
                         omap_revision = TI8168_REV_ES1_1;
-                        *cpu_rev = "1.1";
+                        cpu_rev = "1.1";
                         break;
                 }
                 break;
         case 0xb944:
                 omap_revision = AM335X_REV_ES1_0;
-                *cpu_rev = "1.0";
+                cpu_rev = "1.0";
                 break;
         case 0xb8f2:
                 switch (rev) {
@@ -350,29 +405,29 @@ static void __init omap3_check_revision(const char **cpu_rev)
                 /* FALLTHROUGH */
                 case 1:
                         omap_revision = TI8148_REV_ES1_0;
-                        *cpu_rev = "1.0";
+                        cpu_rev = "1.0";
                         break;
                 case 2:
                         omap_revision = TI8148_REV_ES2_0;
-                        *cpu_rev = "2.0";
+                        cpu_rev = "2.0";
                         break;
                 case 3:
                 /* FALLTHROUGH */
                 default:
                         omap_revision = TI8148_REV_ES2_1;
-                        *cpu_rev = "2.1";
+                        cpu_rev = "2.1";
                         break;
                 }
                 break;
         default:
                 /* Unknown default to latest silicon rev as default */
                 omap_revision = OMAP3630_REV_ES1_2;
-                *cpu_rev = "1.2";
+                cpu_rev = "1.2";
                 pr_warn("Warning: unknown chip type; assuming OMAP3630ES1.2\n");
         }
 }
 
-static void __init omap4_check_revision(void)
+void __init omap4xxx_check_revision(void)
 {
         u32 idcode;
         u16 hawkeye;
@@ -445,89 +500,6 @@ static void __init omap4_check_revision(void)
                 ((omap_rev() >> 12) & 0xf), ((omap_rev() >> 8) & 0xf));
 }
 
-#define OMAP3_SHOW_FEATURE(feat)                \
-        if (omap3_has_ ##feat())                \
-                printk(#feat" ");
-
-static void __init omap3_cpuinfo(const char *cpu_rev)
-{
-        const char *cpu_name;
-
-        /*
-         * OMAP3430 and OMAP3530 are assumed to be same.
-         *
-         * OMAP3525, OMAP3515 and OMAP3503 can be detected only based
-         * on available features. Upon detection, update the CPU id
-         * and CPU class bits.
-         */
-        if (cpu_is_omap3630()) {
-                cpu_name = "OMAP3630";
-        } else if (cpu_is_omap3517()) {
-                /* AM35xx devices */
-                cpu_name = (omap3_has_sgx()) ? "AM3517" : "AM3505";
-        } else if (cpu_is_ti816x()) {
-                cpu_name = "TI816X";
-        } else if (cpu_is_am335x()) {
-                cpu_name =  "AM335X";
-        } else if (cpu_is_ti814x()) {
-                cpu_name = "TI814X";
-        } else if (omap3_has_iva() && omap3_has_sgx()) {
-                /* OMAP3430, OMAP3525, OMAP3515, OMAP3503 devices */
-                cpu_name = "OMAP3430/3530";
-        } else if (omap3_has_iva()) {
-                cpu_name = "OMAP3525";
-        } else if (omap3_has_sgx()) {
-                cpu_name = "OMAP3515";
-        } else {
-                cpu_name = "OMAP3503";
-        }
-
-        /* Print verbose information */
-        pr_info("%s ES%s (", cpu_name, cpu_rev);
-
-        OMAP3_SHOW_FEATURE(l2cache);
-        OMAP3_SHOW_FEATURE(iva);
-        OMAP3_SHOW_FEATURE(sgx);
-        OMAP3_SHOW_FEATURE(neon);
-        OMAP3_SHOW_FEATURE(isp);
-        OMAP3_SHOW_FEATURE(192mhz_clk);
-
-        printk(")\n");
-}
-
-/*
- * Try to detect the exact revision of the omap we're running on
- */
-void __init omap2_check_revision(void)
-{
-        const char *cpu_rev;
-
-        /*
-         * At this point we have an idea about the processor revision set
-         * earlier with omap2_set_globals_tap().
-         */
-        if (cpu_is_omap24xx()) {
-                omap24xx_check_revision();
-        } else if (cpu_is_omap34xx()) {
-                omap3_check_revision(&cpu_rev);
-
-                /* TI81XX doesn't have feature register */
-                if (!cpu_is_ti81xx())
-                        omap3_check_features();
-                else
-                        ti81xx_check_features();
-
-                omap3_cpuinfo(cpu_rev);
-                return;
-        } else if (cpu_is_omap44xx()) {
-                omap4_check_revision();
-                omap4_check_features();
-                return;
-        } else {
-                pr_err("OMAP revision unknown, please fix!\n");
-        }
-}
-
 /*
  * Set up things for map_io and processor detection later on. Gets called
  * pretty much first thing from board init. For multi-omap, this gets
diff --git a/arch/arm/mach-omap2/include/mach/entry-macro.S b/arch/arm/mach-omap2/include/mach/entry-macro.S
deleted file mode 100644
index 56964a0c4c7..00000000000
--- a/arch/arm/mach-omap2/include/mach/entry-macro.S
+++ /dev/null
@@ -1,18 +0,0 @@
-/*
- * arch/arm/plat-omap/include/mach/entry-macro.S
- *
- * Low-level IRQ helper macros for OMAP-based platforms
- *
- * Copyright (C) 2009 Texas Instruments
- * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
- *
- * This file is licensed under  the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-                .macro  disable_fiq
-                .endm
-
-                .macro  arch_ret_to_user, tmp1, tmp2
-                .endm
diff --git a/arch/arm/mach-omap2/include/mach/io.h b/arch/arm/mach-omap2/include/mach/io.h
index fd78f31aa1a..b8758c8a939 100644
--- a/arch/arm/mach-omap2/include/mach/io.h
+++ b/arch/arm/mach-omap2/include/mach/io.h
@@ -1,5 +1,49 @@
 /*
  * arch/arm/mach-omap2/include/mach/io.h
+ *
+ * IO definitions for TI OMAP processors and boards
+ *
+ * Copied from arch/arm/mach-sa1100/include/mach/io.h
+ * Copyright (C) 1997-1999 Russell King
+ *
+ * Copyright (C) 2009 Texas Instruments
+ * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ * Modifications:
+ *  06-12-1997  RMK     Created.
+ *  07-04-1999  RMK     Major cleanup
  */
 
-#include <plat/io.h>
+#ifndef __ASM_ARM_ARCH_IO_H
+#define __ASM_ARM_ARCH_IO_H
+
+#define IO_SPACE_LIMIT 0xffffffff
+
+/*
+ * We don't actually have real ISA nor PCI buses, but there is so many
+ * drivers out there that might just work if we fake them...
+ */
+#define __io(a)         __typesafe_io(a)
+#define __mem_pci(a)    (a)
+
+#endif
diff --git a/arch/arm/mach-omap2/include/mach/system.h b/arch/arm/mach-omap2/include/mach/system.h
deleted file mode 100644
index d488721ab90..00000000000
--- a/arch/arm/mach-omap2/include/mach/system.h
+++ /dev/null
@@ -1,5 +0,0 @@
-/*
- * arch/arm/mach-omap2/include/mach/system.h
- */
-
-#include <plat/system.h>
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index fb11b44fbde..065bd768987 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -21,36 +21,32 @@
 #include <linux/init.h>
 #include <linux/io.h>
 #include <linux/clk.h>
-#include <linux/omapfb.h>
 
 #include <asm/tlb.h>
-
 #include <asm/mach/map.h>
 
 #include <plat/sram.h>
 #include <plat/sdrc.h>
 #include <plat/serial.h>
-
-#include "clock2xxx.h"
-#include "clock3xxx.h"
-#include "clock44xx.h"
-
-#include "common.h"
 #include <plat/omap-pm.h>
+#include <plat/omap_hwmod.h>
+#include <plat/multi.h>
+
+#include "iomap.h"
 #include "voltage.h"
 #include "powerdomain.h"
-
 #include "clockdomain.h"
-#include <plat/omap_hwmod.h>
-#include <plat/multi.h>
 #include "common.h"
+#include "clock2xxx.h"
+#include "clock3xxx.h"
+#include "clock44xx.h"
 
 /*
  * The machine specific code may provide the extra mapping besides the
  * default mapping provided here.
  */
 
-#ifdef CONFIG_ARCH_OMAP2
+#if defined(CONFIG_SOC_OMAP2420) || defined(CONFIG_SOC_OMAP2430)
 static struct map_desc omap24xx_io_desc[] __initdata = {
         {
                 .virtual        = L3_24XX_VIRT,
@@ -352,7 +348,6 @@ static int _set_hwmod_postsetup_state(struct omap_hwmod *oh, void *data)
 
 static void __init omap_common_init_early(void)
 {
-        omap2_check_revision();
         omap_init_consistent_dma_size();
 }
 
@@ -393,6 +388,7 @@ static void __init omap_hwmod_init_postsetup(void)
 void __init omap2420_init_early(void)
 {
         omap2_set_globals_242x();
+        omap2xxx_check_revision();
         omap_common_init_early();
         omap2xxx_voltagedomains_init();
         omap242x_powerdomains_init();
@@ -407,6 +403,7 @@ void __init omap2420_init_early(void)
 void __init omap2430_init_early(void)
 {
         omap2_set_globals_243x();
+        omap2xxx_check_revision();
         omap_common_init_early();
         omap2xxx_voltagedomains_init();
         omap243x_powerdomains_init();
@@ -425,6 +422,8 @@ void __init omap2430_init_early(void)
 void __init omap3_init_early(void)
 {
         omap2_set_globals_3xxx();
+        omap3xxx_check_revision();
+        omap3xxx_check_features();
         omap_common_init_early();
         omap3xxx_voltagedomains_init();
         omap3xxx_powerdomains_init();
@@ -457,6 +456,8 @@ void __init am35xx_init_early(void)
 void __init ti81xx_init_early(void)
 {
         omap2_set_globals_ti81xx();
+        omap3xxx_check_revision();
+        ti81xx_check_features();
         omap_common_init_early();
         omap3xxx_voltagedomains_init();
         omap3xxx_powerdomains_init();
@@ -471,6 +472,8 @@ void __init ti81xx_init_early(void)
 void __init omap4430_init_early(void)
 {
         omap2_set_globals_443x();
+        omap4xxx_check_revision();
+        omap4xxx_check_features();
         omap_common_init_early();
         omap44xx_voltagedomains_init();
         omap44xx_powerdomains_init();
@@ -491,43 +494,3 @@ void __init omap_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
                 _omap2_init_reprogram_sdrc();
         }
 }
-
-/*
- * NOTE: Please use ioremap + __raw_read/write where possible instead of these
- */
-
-u8 omap_readb(u32 pa)
-{
-        return __raw_readb(OMAP2_L4_IO_ADDRESS(pa));
-}
-EXPORT_SYMBOL(omap_readb);
-
-u16 omap_readw(u32 pa)
-{
-        return __raw_readw(OMAP2_L4_IO_ADDRESS(pa));
-}
-EXPORT_SYMBOL(omap_readw);
-
-u32 omap_readl(u32 pa)
-{
-        return __raw_readl(OMAP2_L4_IO_ADDRESS(pa));
-}
-EXPORT_SYMBOL(omap_readl);
-
-void omap_writeb(u8 v, u32 pa)
-{
-        __raw_writeb(v, OMAP2_L4_IO_ADDRESS(pa));
-}
-EXPORT_SYMBOL(omap_writeb);
-
-void omap_writew(u16 v, u32 pa)
-{
-        __raw_writew(v, OMAP2_L4_IO_ADDRESS(pa));
-}
-EXPORT_SYMBOL(omap_writew);
-
-void omap_writel(u32 v, u32 pa)
-{
-        __raw_writel(v, OMAP2_L4_IO_ADDRESS(pa));
-}
-EXPORT_SYMBOL(omap_writel);
diff --git a/arch/arm/plat-omap/include/plat/io.h b/arch/arm/mach-omap2/iomap.h
index 0696bae1818..e6f95816529 100644
--- a/arch/arm/plat-omap/include/plat/io.h
+++ b/arch/arm/mach-omap2/iomap.h
@@ -1,13 +1,5 @@
 /*
- * arch/arm/plat-omap/include/mach/io.h
- *
- * IO definitions for TI OMAP processors and boards
- *
- * Copied from arch/arm/mach-sa1100/include/mach/io.h
- * Copyright (C) 1997-1999 Russell King
- *
- * Copyright (C) 2009 Texas Instruments
- * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
+ * IO mappings for OMAP2+
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms of the GNU General Public License as published by the
@@ -25,33 +17,9 @@
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
+ * You should have received a copy of the  GNU General Public License along
+ * with this program; if not, write  to the Free Software Foundation, Inc.,
  * 675 Mass Ave, Cambridge, MA 02139, USA.
- *
- * Modifications:
- *  06-12-1997  RMK     Created.
- *  07-04-1999  RMK     Major cleanup
- */
-
-#ifndef __ASM_ARM_ARCH_IO_H
-#define __ASM_ARM_ARCH_IO_H
-
-#include <mach/hardware.h>
-
-#define IO_SPACE_LIMIT 0xffffffff
-
-/*
- * We don't actually have real ISA nor PCI buses, but there is so many
- * drivers out there that might just work if we fake them...
- */
-#define __io(a)         __typesafe_io(a)
-#define __mem_pci(a)    (a)
-
-/*
- * ----------------------------------------------------------------------------
- * I/O mapping
- * ----------------------------------------------------------------------------
  */
 
 #ifdef __ASSEMBLER__
@@ -60,13 +28,9 @@
 #define IOMEM(x)                ((void __force __iomem *)(x))
 #endif
 
-#define OMAP1_IO_OFFSET         0x01000000      /* Virtual IO = 0xfefb0000 */
-#define OMAP1_IO_ADDRESS(pa)    IOMEM((pa) - OMAP1_IO_OFFSET)
-
 #define OMAP2_L3_IO_OFFSET      0x90000000
 #define OMAP2_L3_IO_ADDRESS(pa) IOMEM((pa) + OMAP2_L3_IO_OFFSET) /* L3 */
 
-
 #define OMAP2_L4_IO_OFFSET      0xb2000000
 #define OMAP2_L4_IO_ADDRESS(pa) IOMEM((pa) + OMAP2_L4_IO_OFFSET) /* L4 */
 
@@ -87,16 +51,6 @@
 
 /*
  * ----------------------------------------------------------------------------
- * Omap1 specific IO mapping
- * ----------------------------------------------------------------------------
- */
-
-#define OMAP1_IO_PHYS           0xFFFB0000
-#define OMAP1_IO_SIZE           0x40000
-#define OMAP1_IO_VIRT           (OMAP1_IO_PHYS - OMAP1_IO_OFFSET)
-
-/*
- * ----------------------------------------------------------------------------
  * Omap2 specific IO mapping
  * ----------------------------------------------------------------------------
  */
@@ -247,31 +201,3 @@
                                                 /* 0x4e000000 --> 0xfd300000 */
 #define OMAP44XX_DMM_SIZE       SZ_1M
 #define OMAP44XX_DMM_VIRT       (OMAP44XX_EMIF2_VIRT + OMAP44XX_EMIF2_SIZE)
-/*
- * ----------------------------------------------------------------------------
- * Omap specific register access
- * ----------------------------------------------------------------------------
- */
-
-#ifndef __ASSEMBLER__
-
-/*
- * NOTE: Please use ioremap + __raw_read/write where possible instead of these
- */
-
-extern u8 omap_readb(u32 pa);
-extern u16 omap_readw(u32 pa);
-extern u32 omap_readl(u32 pa);
-extern void omap_writeb(u8 v, u32 pa);
-extern void omap_writew(u16 v, u32 pa);
-extern void omap_writel(u32 v, u32 pa);
-
-struct omap_sdrc_params;
-extern void omap_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
-                                      struct omap_sdrc_params *sdrc_cs1);
-
-extern void __init omap_init_consistent_dma_size(void);
-
-#endif
-
-#endif
diff --git a/arch/arm/mach-omap2/irq.c b/arch/arm/mach-omap2/irq.c
index 1fef061f792..65f0d2571c9 100644
--- a/arch/arm/mach-omap2/irq.c
+++ b/arch/arm/mach-omap2/irq.c
@@ -11,13 +11,20 @@
  * for more details.
  */
 #include <linux/kernel.h>
+#include <linux/module.h>
 #include <linux/init.h>
 #include <linux/interrupt.h>
 #include <linux/io.h>
-#include <mach/hardware.h>
+
 #include <asm/exception.h>
 #include <asm/mach/irq.h>
+#include <linux/irqdomain.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
 
+#include <mach/hardware.h>
+
+#include "iomap.h"
 
 /* selected INTC register offsets */
 
@@ -57,6 +64,8 @@ static struct omap_irq_bank {
         },
 };
 
+static struct irq_domain *domain;
+
 /* Structure to save interrupt controller context */
 struct omap3_intc_regs {
         u32 sysconfig;
@@ -147,17 +156,27 @@ omap_alloc_gc(void __iomem *base, unsigned int irq_start, unsigned int num)
                                 IRQ_NOREQUEST | IRQ_NOPROBE, 0);
 }
 
-static void __init omap_init_irq(u32 base, int nr_irqs)
+static void __init omap_init_irq(u32 base, int nr_irqs,
+                                 struct device_node *node)
 {
         void __iomem *omap_irq_base;
         unsigned long nr_of_irqs = 0;
         unsigned int nr_banks = 0;
-        int i, j;
+        int i, j, irq_base;
 
         omap_irq_base = ioremap(base, SZ_4K);
         if (WARN_ON(!omap_irq_base))
                 return;
 
+        irq_base = irq_alloc_descs(-1, 0, nr_irqs, 0);
+        if (irq_base < 0) {
+                pr_warn("Couldn't allocate IRQ numbers\n");
+                irq_base = 0;
+        }
+
+        domain = irq_domain_add_legacy(node, nr_irqs, irq_base, 0,
+                                       &irq_domain_simple_ops, NULL);
+
         for (i = 0; i < ARRAY_SIZE(irq_banks); i++) {
                 struct omap_irq_bank *bank = irq_banks + i;
 
@@ -166,36 +185,36 @@ static void __init omap_init_irq(u32 base, int nr_irqs)
                 /* Static mapping, never released */
                 bank->base_reg = ioremap(base, SZ_4K);
                 if (!bank->base_reg) {
-                        printk(KERN_ERR "Could not ioremap irq bank%i\n", i);
+                        pr_err("Could not ioremap irq bank%i\n", i);
                         continue;
                 }
 
                 omap_irq_bank_init_one(bank);
 
                 for (j = 0; j < bank->nr_irqs; j += 32)
-                        omap_alloc_gc(bank->base_reg + j, j, 32);
+                        omap_alloc_gc(bank->base_reg + j, j + irq_base, 32);
 
                 nr_of_irqs += bank->nr_irqs;
                 nr_banks++;
         }
 
-        printk(KERN_INFO "Total of %ld interrupts on %d active controller%s\n",
-               nr_of_irqs, nr_banks, nr_banks > 1 ? "s" : "");
+        pr_info("Total of %ld interrupts on %d active controller%s\n",
+                nr_of_irqs, nr_banks, nr_banks > 1 ? "s" : "");
 }
 
 void __init omap2_init_irq(void)
 {
-        omap_init_irq(OMAP24XX_IC_BASE, 96);
+        omap_init_irq(OMAP24XX_IC_BASE, 96, NULL);
 }
 
 void __init omap3_init_irq(void)
 {
-        omap_init_irq(OMAP34XX_IC_BASE, 96);
+        omap_init_irq(OMAP34XX_IC_BASE, 96, NULL);
 }
 
 void __init ti81xx_init_irq(void)
 {
-        omap_init_irq(OMAP34XX_IC_BASE, 128);
+        omap_init_irq(OMAP34XX_IC_BASE, 128, NULL);
 }
 
 static inline void omap_intc_handle_irq(void __iomem *base_addr, struct pt_regs *regs)
@@ -225,8 +244,10 @@ out:
                 irqnr = readl_relaxed(base_addr + INTCPS_SIR_IRQ_OFFSET);
                 irqnr &= ACTIVEIRQ_MASK;
 
-                if (irqnr)
+                if (irqnr) {
+                        irqnr = irq_find_mapping(domain, irqnr);
                         handle_IRQ(irqnr, regs);
+                }
         } while (irqnr);
 }
 
@@ -236,6 +257,28 @@ asmlinkage void __exception_irq_entry omap2_intc_handle_irq(struct pt_regs *regs
         omap_intc_handle_irq(base_addr, regs);
 }
 
+int __init omap_intc_of_init(struct device_node *node,
+                             struct device_node *parent)
+{
+        struct resource res;
+        u32 nr_irqs = 96;
+
+        if (WARN_ON(!node))
+                return -ENODEV;
+
+        if (of_address_to_resource(node, 0, &res)) {
+                WARN(1, "unable to get intc registers\n");
+                return -EINVAL;
+        }
+
+        if (of_property_read_u32(node, "ti,intc-size", &nr_irqs))
+                pr_warn("unable to get intc-size, default to %d\n", nr_irqs);
+
+        omap_init_irq(res.start, nr_irqs, of_node_get(node));
+
+        return 0;
+}
+
 #ifdef CONFIG_ARCH_OMAP3
 static struct omap3_intc_regs intc_context[ARRAY_SIZE(irq_banks)];
 
diff --git a/arch/arm/mach-omap2/mcbsp.c b/arch/arm/mach-omap2/mcbsp.c
index fb4bcf81a18..577cb77db26 100644
--- a/arch/arm/mach-omap2/mcbsp.c
+++ b/arch/arm/mach-omap2/mcbsp.c
@@ -34,7 +34,7 @@
 #include "cm2xxx_3xxx.h"
 #include "cm-regbits-34xx.h"
 
-/* McBSP internal signal muxing function */
+/* McBSP1 internal signal muxing function for OMAP2/3 */
 static int omap2_mcbsp1_mux_rx_clk(struct device *dev, const char *signal,
                                    const char *src)
 {
@@ -65,6 +65,42 @@ static int omap2_mcbsp1_mux_rx_clk(struct device *dev, const char *signal,
         return 0;
 }
 
+/* McBSP4 internal signal muxing function for OMAP4 */
+#define OMAP4_CONTROL_MCBSPLP_ALBCTRLRX_FSX     (1 << 31)
+#define OMAP4_CONTROL_MCBSPLP_ALBCTRLRX_CLKX    (1 << 30)
+static int omap4_mcbsp4_mux_rx_clk(struct device *dev, const char *signal,
+                                   const char *src)
+{
+        u32 v;
+
+        /*
+         * In CONTROL_MCBSPLP register only bit 30 (CLKR mux), and bit 31 (FSR
+         * mux) is used */
+        v = omap4_ctrl_pad_readl(OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MCBSPLP);
+
+        if (!strcmp(signal, "clkr")) {
+                if (!strcmp(src, "clkr"))
+                        v &= ~OMAP4_CONTROL_MCBSPLP_ALBCTRLRX_CLKX;
+                else if (!strcmp(src, "clkx"))
+                        v |= OMAP4_CONTROL_MCBSPLP_ALBCTRLRX_CLKX;
+                else
+                        return -EINVAL;
+        } else if (!strcmp(signal, "fsr")) {
+                if (!strcmp(src, "fsr"))
+                        v &= ~OMAP4_CONTROL_MCBSPLP_ALBCTRLRX_FSX;
+                else if (!strcmp(src, "fsx"))
+                        v |= OMAP4_CONTROL_MCBSPLP_ALBCTRLRX_FSX;
+                else
+                        return -EINVAL;
+        } else {
+                return -EINVAL;
+        }
+
+        omap4_ctrl_pad_writel(v, OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MCBSPLP);
+
+        return 0;
+}
+
 /* McBSP CLKS source switching function */
 static int omap2_mcbsp_set_clk_src(struct device *dev, struct clk *clk,
                                    const char *src)
@@ -122,7 +158,7 @@ static int omap3_enable_st_clock(unsigned int id, bool enable)
         return 0;
 }
 
-static int omap_init_mcbsp(struct omap_hwmod *oh, void *unused)
+static int __init omap_init_mcbsp(struct omap_hwmod *oh, void *unused)
 {
         int id, count = 1;
         char *name = "omap-mcbsp";
@@ -146,9 +182,15 @@ static int omap_init_mcbsp(struct omap_hwmod *oh, void *unused)
                 pdata->has_ccr = true;
         }
         pdata->set_clk_src = omap2_mcbsp_set_clk_src;
-        if (id == 1)
+
+        /* On OMAP2/3 the McBSP1 port has 6 pin configuration */
+        if (id == 1 && oh->class->rev < MCBSP_CONFIG_TYPE4)
                 pdata->mux_signal = omap2_mcbsp1_mux_rx_clk;
 
+        /* On OMAP4 the McBSP4 port has 6 pin configuration */
+        if (id == 4 && oh->class->rev == MCBSP_CONFIG_TYPE4)
+                pdata->mux_signal = omap4_mcbsp4_mux_rx_clk;
+
         if (oh->class->rev == MCBSP_CONFIG_TYPE3) {
                 if (id == 2)
                         /* The FIFO has 1024 + 256 locations */
@@ -180,7 +222,6 @@ static int omap_init_mcbsp(struct omap_hwmod *oh, void *unused)
                                         name, oh->name);
                 return PTR_ERR(pdev);
         }
-        omap_mcbsp_count++;
         return 0;
 }
 
@@ -188,11 +229,6 @@ static int __init omap2_mcbsp_init(void)
 {
         omap_hwmod_for_each_by_class("mcbsp", omap_init_mcbsp, NULL);
 
-        mcbsp_ptr = kzalloc(omap_mcbsp_count * sizeof(struct omap_mcbsp *),
-                                                                GFP_KERNEL);
-        if (!mcbsp_ptr)
-                return -ENOMEM;
-
-        return omap_mcbsp_init();
+        return 0;
 }
 arch_initcall(omap2_mcbsp_init);
diff --git a/arch/arm/mach-omap2/mux.c b/arch/arm/mach-omap2/mux.c
index 611a0e3d54c..f26b2faa169 100644
--- a/arch/arm/mach-omap2/mux.c
+++ b/arch/arm/mach-omap2/mux.c
@@ -100,8 +100,8 @@ void omap_mux_write_array(struct omap_mux_partition *partition,
 
 static char *omap_mux_options;
 
-static int _omap_mux_init_gpio(struct omap_mux_partition *partition,
-                               int gpio, int val)
+static int __init _omap_mux_init_gpio(struct omap_mux_partition *partition,
+                                      int gpio, int val)
 {
         struct omap_mux_entry *e;
         struct omap_mux *gpio_mux = NULL;
@@ -145,7 +145,7 @@ static int _omap_mux_init_gpio(struct omap_mux_partition *partition,
         return 0;
 }
 
-int omap_mux_init_gpio(int gpio, int val)
+int __init omap_mux_init_gpio(int gpio, int val)
 {
         struct omap_mux_partition *partition;
         int ret;
@@ -159,9 +159,9 @@ int omap_mux_init_gpio(int gpio, int val)
         return -ENODEV;
 }
 
-static int _omap_mux_get_by_name(struct omap_mux_partition *partition,
-                                 const char *muxname,
-                                 struct omap_mux **found_mux)
+static int __init _omap_mux_get_by_name(struct omap_mux_partition *partition,
+                                        const char *muxname,
+                                        struct omap_mux **found_mux)
 {
         struct omap_mux *mux = NULL;
         struct omap_mux_entry *e;
@@ -218,7 +218,7 @@ static int _omap_mux_get_by_name(struct omap_mux_partition *partition,
         return -ENODEV;
 }
 
-static int
+static int __init
 omap_mux_get_by_name(const char *muxname,
                         struct omap_mux_partition **found_partition,
                         struct omap_mux **found_mux)
@@ -240,7 +240,7 @@ omap_mux_get_by_name(const char *muxname,
         return -ENODEV;
 }
 
-int omap_mux_init_signal(const char *muxname, int val)
+int __init omap_mux_init_signal(const char *muxname, int val)
 {
         struct omap_mux_partition *partition = NULL;
         struct omap_mux *mux = NULL;
diff --git a/arch/arm/mach-omap2/mux.h b/arch/arm/mach-omap2/mux.h
index 2132308ad1e..69fe060a0b7 100644
--- a/arch/arm/mach-omap2/mux.h
+++ b/arch/arm/mach-omap2/mux.h
@@ -246,7 +246,7 @@ static inline void omap_hwmod_mux(struct omap_hwmod_mux_info *hmux, u8 state)
 {
 }
 
-static struct omap_board_mux *board_mux __initdata __maybe_unused;
+static struct omap_board_mux *board_mux __maybe_unused;
 
 #endif
 
diff --git a/arch/arm/mach-omap2/omap-hotplug.c b/arch/arm/mach-omap2/omap-hotplug.c
index adbe4d8c7ca..56c345b8b93 100644
--- a/arch/arm/mach-omap2/omap-hotplug.c
+++ b/arch/arm/mach-omap2/omap-hotplug.c
@@ -33,7 +33,7 @@ int platform_cpu_kill(unsigned int cpu)
  * platform-specific code to shutdown a CPU
  * Called with IRQs disabled
  */
-void platform_cpu_die(unsigned int cpu)
+void __ref platform_cpu_die(unsigned int cpu)
 {
         unsigned int this_cpu;
 
diff --git a/arch/arm/mach-omap2/omap-mpuss-lowpower.c b/arch/arm/mach-omap2/omap-mpuss-lowpower.c
index 1d5d0105655..63ab686834c 100644
--- a/arch/arm/mach-omap2/omap-mpuss-lowpower.c
+++ b/arch/arm/mach-omap2/omap-mpuss-lowpower.c
@@ -263,12 +263,10 @@ int omap4_enter_lowpower(unsigned int cpu, unsigned int power_state)
          * In MPUSS OSWR or device OFF, interrupt controller  contest is lost.
          */
         mpuss_clear_prev_logic_pwrst();
-        pwrdm_clear_all_prev_pwrst(mpuss_pd);
         if ((pwrdm_read_next_pwrst(mpuss_pd) == PWRDM_POWER_RET) &&
                 (pwrdm_read_logic_retst(mpuss_pd) == PWRDM_POWER_OFF))
                 save_state = 2;
 
-        clear_cpu_prev_pwrst(cpu);
         cpu_clear_prev_logic_pwrst(cpu);
         set_cpu_next_pwrst(cpu, power_state);
         set_cpu_wakeup_addr(cpu, virt_to_phys(omap4_cpu_resume));
@@ -300,7 +298,7 @@ int omap4_enter_lowpower(unsigned int cpu, unsigned int power_state)
  * @cpu : CPU ID
  * @power_state: CPU low power state.
  */
-int omap4_hotplug_cpu(unsigned int cpu, unsigned int power_state)
+int __cpuinit omap4_hotplug_cpu(unsigned int cpu, unsigned int power_state)
 {
         unsigned int cpu_state = 0;
 
diff --git a/arch/arm/mach-omap2/omap-smp.c b/arch/arm/mach-omap2/omap-smp.c
index c1bf3ef0ba0..deffbf1c962 100644
--- a/arch/arm/mach-omap2/omap-smp.c
+++ b/arch/arm/mach-omap2/omap-smp.c
@@ -23,11 +23,12 @@
 #include <asm/cacheflush.h>
 #include <asm/hardware/gic.h>
 #include <asm/smp_scu.h>
+
 #include <mach/hardware.h>
 #include <mach/omap-secure.h>
 
+#include "iomap.h"
 #include "common.h"
-
 #include "clockdomain.h"
 
 /* SCU base address */
diff --git a/arch/arm/mach-omap2/omap-wakeupgen.c b/arch/arm/mach-omap2/omap-wakeupgen.c
index d3d8971d7f3..42cd7fb5241 100644
--- a/arch/arm/mach-omap2/omap-wakeupgen.c
+++ b/arch/arm/mach-omap2/omap-wakeupgen.c
@@ -43,7 +43,6 @@
 
 static void __iomem *wakeupgen_base;
 static void __iomem *sar_base;
-static DEFINE_PER_CPU(u32 [NR_REG_BANKS], irqmasks);
 static DEFINE_SPINLOCK(wakeupgen_lock);
 static unsigned int irq_target_cpu[NR_IRQS];
 
@@ -67,14 +66,6 @@ static inline void sar_writel(u32 val, u32 offset, u8 idx)
         __raw_writel(val, sar_base + offset + (idx * 4));
 }
 
-static void _wakeupgen_set_all(unsigned int cpu, unsigned int reg)
-{
-        u8 i;
-
-        for (i = 0; i < NR_REG_BANKS; i++)
-                wakeupgen_writel(reg, i, cpu);
-}
-
 static inline int _wakeupgen_get_irq_info(u32 irq, u32 *bit_posn, u8 *reg_index)
 {
         unsigned int spi_irq;
@@ -130,22 +121,6 @@ static void _wakeupgen_set(unsigned int irq, unsigned int cpu)
         wakeupgen_writel(val, i, cpu);
 }
 
-static void _wakeupgen_save_masks(unsigned int cpu)
-{
-        u8 i;
-
-        for (i = 0; i < NR_REG_BANKS; i++)
-                per_cpu(irqmasks, cpu)[i] = wakeupgen_readl(i, cpu);
-}
-
-static void _wakeupgen_restore_masks(unsigned int cpu)
-{
-        u8 i;
-
-        for (i = 0; i < NR_REG_BANKS; i++)
-                wakeupgen_writel(per_cpu(irqmasks, cpu)[i], i, cpu);
-}
-
 /*
  * Architecture specific Mask extension
  */
@@ -170,6 +145,33 @@ static void wakeupgen_unmask(struct irq_data *d)
         spin_unlock_irqrestore(&wakeupgen_lock, flags);
 }
 
+#ifdef CONFIG_HOTPLUG_CPU
+static DEFINE_PER_CPU(u32 [NR_REG_BANKS], irqmasks);
+
+static void _wakeupgen_save_masks(unsigned int cpu)
+{
+        u8 i;
+
+        for (i = 0; i < NR_REG_BANKS; i++)
+                per_cpu(irqmasks, cpu)[i] = wakeupgen_readl(i, cpu);
+}
+
+static void _wakeupgen_restore_masks(unsigned int cpu)
+{
+        u8 i;
+
+        for (i = 0; i < NR_REG_BANKS; i++)
+                wakeupgen_writel(per_cpu(irqmasks, cpu)[i], i, cpu);
+}
+
+static void _wakeupgen_set_all(unsigned int cpu, unsigned int reg)
+{
+        u8 i;
+
+        for (i = 0; i < NR_REG_BANKS; i++)
+                wakeupgen_writel(reg, i, cpu);
+}
+
 /*
  * Mask or unmask all interrupts on given CPU.
  *      0 = Mask all interrupts on the 'cpu'
@@ -191,6 +193,7 @@ static void wakeupgen_irqmask_all(unsigned int cpu, unsigned int set)
         }
         spin_unlock_irqrestore(&wakeupgen_lock, flags);
 }
+#endif
 
 #ifdef CONFIG_CPU_PM
 /*
diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
index 3c8dd928628..34b9766d1d2 100644
--- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
@@ -29,6 +29,7 @@
 
 #include "omap_hwmod_common_data.h"
 
+#include "smartreflex.h"
 #include "prm-regbits-34xx.h"
 #include "cm-regbits-34xx.h"
 #include "wd_timer.h"
@@ -376,6 +377,16 @@ static struct omap_hwmod_ocp_if omap3_l4_core__i2c3 = {
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
+static struct omap_hwmod_irq_info omap3_smartreflex_mpu_irqs[] = {
+        { .irq = 18},
+        { .irq = -1 }
+};
+
+static struct omap_hwmod_irq_info omap3_smartreflex_core_irqs[] = {
+        { .irq = 19},
+        { .irq = -1 }
+};
+
 /* L4 CORE -> SR1 interface */
 static struct omap_hwmod_addr_space omap3_sr1_addr_space[] = {
         {
@@ -2664,6 +2675,10 @@ static struct omap_hwmod_class omap36xx_smartreflex_hwmod_class = {
 };
 
 /* SR1 */
+static struct omap_smartreflex_dev_attr sr1_dev_attr = {
+        .sensor_voltdm_name   = "mpu_iva",
+};
+
 static struct omap_hwmod_ocp_if *omap3_sr1_slaves[] = {
         &omap3_l4_core__sr1,
 };
@@ -2672,7 +2687,6 @@ static struct omap_hwmod omap34xx_sr1_hwmod = {
         .name           = "sr1_hwmod",
         .class          = &omap34xx_smartreflex_hwmod_class,
         .main_clk       = "sr1_fck",
-        .vdd_name       = "mpu_iva",
         .prcm           = {
                 .omap2 = {
                         .prcm_reg_id = 1,
@@ -2684,6 +2698,8 @@ static struct omap_hwmod omap34xx_sr1_hwmod = {
         },
         .slaves         = omap3_sr1_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap3_sr1_slaves),
+        .dev_attr       = &sr1_dev_attr,
+        .mpu_irqs       = omap3_smartreflex_mpu_irqs,
         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 };
 
@@ -2691,7 +2707,6 @@ static struct omap_hwmod omap36xx_sr1_hwmod = {
         .name           = "sr1_hwmod",
         .class          = &omap36xx_smartreflex_hwmod_class,
         .main_clk       = "sr1_fck",
-        .vdd_name       = "mpu_iva",
         .prcm           = {
                 .omap2 = {
                         .prcm_reg_id = 1,
@@ -2703,9 +2718,15 @@ static struct omap_hwmod omap36xx_sr1_hwmod = {
         },
         .slaves         = omap3_sr1_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap3_sr1_slaves),
+        .dev_attr       = &sr1_dev_attr,
+        .mpu_irqs       = omap3_smartreflex_mpu_irqs,
 };
 
 /* SR2 */
+static struct omap_smartreflex_dev_attr sr2_dev_attr = {
+        .sensor_voltdm_name     = "core",
+};
+
 static struct omap_hwmod_ocp_if *omap3_sr2_slaves[] = {
         &omap3_l4_core__sr2,
 };
@@ -2714,7 +2735,6 @@ static struct omap_hwmod omap34xx_sr2_hwmod = {
         .name           = "sr2_hwmod",
         .class          = &omap34xx_smartreflex_hwmod_class,
         .main_clk       = "sr2_fck",
-        .vdd_name       = "core",
         .prcm           = {
                 .omap2 = {
                         .prcm_reg_id = 1,
@@ -2726,6 +2746,8 @@ static struct omap_hwmod omap34xx_sr2_hwmod = {
         },
         .slaves         = omap3_sr2_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap3_sr2_slaves),
+        .dev_attr       = &sr2_dev_attr,
+        .mpu_irqs       = omap3_smartreflex_core_irqs,
         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 };
 
@@ -2733,7 +2755,6 @@ static struct omap_hwmod omap36xx_sr2_hwmod = {
         .name           = "sr2_hwmod",
         .class          = &omap36xx_smartreflex_hwmod_class,
         .main_clk       = "sr2_fck",
-        .vdd_name       = "core",
         .prcm           = {
                 .omap2 = {
                         .prcm_reg_id = 1,
@@ -2745,6 +2766,8 @@ static struct omap_hwmod omap36xx_sr2_hwmod = {
         },
         .slaves         = omap3_sr2_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap3_sr2_slaves),
+        .dev_attr       = &sr2_dev_attr,
+        .mpu_irqs       = omap3_smartreflex_core_irqs,
 };
 
 /*
diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
index ef0524c10a8..08daa5e0eb5 100644
--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
@@ -28,12 +28,12 @@
 #include <plat/mcspi.h>
 #include <plat/mcbsp.h>
 #include <plat/mmc.h>
-#include <plat/i2c.h>
 #include <plat/dmtimer.h>
 #include <plat/common.h>
 
 #include "omap_hwmod_common_data.h"
 
+#include "smartreflex.h"
 #include "cm1_44xx.h"
 #include "cm2_44xx.h"
 #include "prm44xx.h"
@@ -3963,6 +3963,10 @@ static struct omap_hwmod_class omap44xx_smartreflex_hwmod_class = {
 };
 
 /* smartreflex_core */
+static struct omap_smartreflex_dev_attr smartreflex_core_dev_attr = {
+        .sensor_voltdm_name   = "core",
+};
+
 static struct omap_hwmod omap44xx_smartreflex_core_hwmod;
 static struct omap_hwmod_irq_info omap44xx_smartreflex_core_irqs[] = {
         { .irq = 19 + OMAP44XX_IRQ_GIC_START },
@@ -3999,7 +4003,6 @@ static struct omap_hwmod omap44xx_smartreflex_core_hwmod = {
         .mpu_irqs       = omap44xx_smartreflex_core_irqs,
 
         .main_clk       = "smartreflex_core_fck",
-        .vdd_name       = "core",
         .prcm = {
                 .omap4 = {
                         .clkctrl_offs = OMAP4_CM_ALWON_SR_CORE_CLKCTRL_OFFSET,
@@ -4009,9 +4012,14 @@ static struct omap_hwmod omap44xx_smartreflex_core_hwmod = {
         },
         .slaves         = omap44xx_smartreflex_core_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap44xx_smartreflex_core_slaves),
+        .dev_attr       = &smartreflex_core_dev_attr,
 };
 
 /* smartreflex_iva */
+static struct omap_smartreflex_dev_attr smartreflex_iva_dev_attr = {
+        .sensor_voltdm_name     = "iva",
+};
+
 static struct omap_hwmod omap44xx_smartreflex_iva_hwmod;
 static struct omap_hwmod_irq_info omap44xx_smartreflex_iva_irqs[] = {
         { .irq = 102 + OMAP44XX_IRQ_GIC_START },
@@ -4047,7 +4055,6 @@ static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = {
         .clkdm_name     = "l4_ao_clkdm",
         .mpu_irqs       = omap44xx_smartreflex_iva_irqs,
         .main_clk       = "smartreflex_iva_fck",
-        .vdd_name       = "iva",
         .prcm = {
                 .omap4 = {
                         .clkctrl_offs = OMAP4_CM_ALWON_SR_IVA_CLKCTRL_OFFSET,
@@ -4057,9 +4064,14 @@ static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = {
         },
         .slaves         = omap44xx_smartreflex_iva_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap44xx_smartreflex_iva_slaves),
+        .dev_attr       = &smartreflex_iva_dev_attr,
 };
 
 /* smartreflex_mpu */
+static struct omap_smartreflex_dev_attr smartreflex_mpu_dev_attr = {
+        .sensor_voltdm_name     = "mpu",
+};
+
 static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod;
 static struct omap_hwmod_irq_info omap44xx_smartreflex_mpu_irqs[] = {
         { .irq = 18 + OMAP44XX_IRQ_GIC_START },
@@ -4095,7 +4107,6 @@ static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = {
         .clkdm_name     = "l4_ao_clkdm",
         .mpu_irqs       = omap44xx_smartreflex_mpu_irqs,
         .main_clk       = "smartreflex_mpu_fck",
-        .vdd_name       = "mpu",
         .prcm = {
                 .omap4 = {
                         .clkctrl_offs = OMAP4_CM_ALWON_SR_MPU_CLKCTRL_OFFSET,
@@ -4105,6 +4116,7 @@ static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = {
         },
         .slaves         = omap44xx_smartreflex_mpu_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap44xx_smartreflex_mpu_slaves),
+        .dev_attr       = &smartreflex_mpu_dev_attr,
 };
 
 /*
diff --git a/arch/arm/mach-omap2/opp2420_data.c b/arch/arm/mach-omap2/opp2420_data.c
index e6dda694fd5..5037e76e4e2 100644
--- a/arch/arm/mach-omap2/opp2420_data.c
+++ b/arch/arm/mach-omap2/opp2420_data.c
@@ -28,6 +28,8 @@
  *     http://repository.maemo.org/pool/diablo/free/k/kernel-source-diablo/
  */
 
+#include <plat/hardware.h>
+
 #include "opp2xxx.h"
 #include "sdrc.h"
 #include "clock.h"
diff --git a/arch/arm/mach-omap2/opp2430_data.c b/arch/arm/mach-omap2/opp2430_data.c
index 1b9596ae201..750805c528d 100644
--- a/arch/arm/mach-omap2/opp2430_data.c
+++ b/arch/arm/mach-omap2/opp2430_data.c
@@ -26,6 +26,8 @@
  * This is technically part of the OMAP2xxx clock code.
  */
 
+#include <plat/hardware.h>
+
 #include "opp2xxx.h"
 #include "sdrc.h"
 #include "clock.h"
diff --git a/arch/arm/mach-omap2/pm-debug.c b/arch/arm/mach-omap2/pm-debug.c
index 4411163e012..814bcd90159 100644
--- a/arch/arm/mach-omap2/pm-debug.c
+++ b/arch/arm/mach-omap2/pm-debug.c
@@ -220,8 +220,8 @@ static int __init pwrdms_setup(struct powerdomain *pwrdm, void *dir)
                 return 0;
 
         d = debugfs_create_dir(pwrdm->name, (struct dentry *)dir);
-
-        (void) debugfs_create_file("suspend", S_IRUGO|S_IWUSR, d,
+        if (!(IS_ERR_OR_NULL(d)))
+                (void) debugfs_create_file("suspend", S_IRUGO|S_IWUSR, d,
                         (void *)pwrdm, &pwrdm_suspend_fops);
 
         return 0;
@@ -264,7 +264,7 @@ static int __init pm_dbg_init(void)
                 return 0;
 
         d = debugfs_create_dir("pm_debug", NULL);
-        if (IS_ERR(d))
+        if (IS_ERR_OR_NULL(d))
                 return PTR_ERR(d);
 
         (void) debugfs_create_file("count", S_IRUGO,
diff --git a/arch/arm/mach-omap2/pm.c b/arch/arm/mach-omap2/pm.c
index 5a65dd04aa3..a7bdec69a2b 100644
--- a/arch/arm/mach-omap2/pm.c
+++ b/arch/arm/mach-omap2/pm.c
@@ -15,11 +15,13 @@
 #include <linux/err.h>
 #include <linux/opp.h>
 #include <linux/export.h>
+#include <linux/suspend.h>
 
 #include <plat/omap-pm.h>
 #include <plat/omap_device.h>
 #include "common.h"
 
+#include "prcm-common.h"
 #include "voltage.h"
 #include "powerdomain.h"
 #include "clockdomain.h"
@@ -28,7 +30,13 @@
 
 static struct omap_device_pm_latency *pm_lats;
 
-static int _init_omap_device(char *name)
+/*
+ * omap_pm_suspend: points to a function that does the SoC-specific
+ * suspend work
+ */
+int (*omap_pm_suspend)(void);
+
+static int __init _init_omap_device(char *name)
 {
         struct omap_hwmod *oh;
         struct platform_device *pdev;
@@ -49,7 +57,7 @@ static int _init_omap_device(char *name)
 /*
  * Build omap_devices for processors and bus.
  */
-static void omap2_init_processor_devices(void)
+static void __init omap2_init_processor_devices(void)
 {
         _init_omap_device("mpu");
         if (omap3_has_iva())
@@ -68,32 +76,41 @@ static void omap2_init_processor_devices(void)
 #define FORCEWAKEUP_SWITCH      0
 #define LOWPOWERSTATE_SWITCH    1
 
+int __init omap_pm_clkdms_setup(struct clockdomain *clkdm, void *unused)
+{
+        if (clkdm->flags & CLKDM_CAN_ENABLE_AUTO)
+                clkdm_allow_idle(clkdm);
+        else if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP &&
+                 atomic_read(&clkdm->usecount) == 0)
+                clkdm_sleep(clkdm);
+        return 0;
+}
+
 /*
  * This sets pwrdm state (other than mpu & core. Currently only ON &
  * RET are supported.
  */
-int omap_set_pwrdm_state(struct powerdomain *pwrdm, u32 state)
+int omap_set_pwrdm_state(struct powerdomain *pwrdm, u32 pwrst)
 {
-        u32 cur_state;
-        int sleep_switch = -1;
-        int ret = 0;
-        int hwsup = 0;
+        u8 curr_pwrst, next_pwrst;
+        int sleep_switch = -1, ret = 0, hwsup = 0;
 
-        if (pwrdm == NULL || IS_ERR(pwrdm))
+        if (!pwrdm || IS_ERR(pwrdm))
                 return -EINVAL;
 
-        while (!(pwrdm->pwrsts & (1 << state))) {
-                if (state == PWRDM_POWER_OFF)
+        while (!(pwrdm->pwrsts & (1 << pwrst))) {
+                if (pwrst == PWRDM_POWER_OFF)
                         return ret;
-                state--;
+                pwrst--;
         }
 
-        cur_state = pwrdm_read_next_pwrst(pwrdm);
-        if (cur_state == state)
+        next_pwrst = pwrdm_read_next_pwrst(pwrdm);
+        if (next_pwrst == pwrst)
                 return ret;
 
-        if (pwrdm_read_pwrst(pwrdm) < PWRDM_POWER_ON) {
-                if ((pwrdm_read_pwrst(pwrdm) > state) &&
+        curr_pwrst = pwrdm_read_pwrst(pwrdm);
+        if (curr_pwrst < PWRDM_POWER_ON) {
+                if ((curr_pwrst > pwrst) &&
                         (pwrdm->flags & PWRDM_HAS_LOWPOWERSTATECHANGE)) {
                         sleep_switch = LOWPOWERSTATE_SWITCH;
                 } else {
@@ -103,12 +120,10 @@ int omap_set_pwrdm_state(struct powerdomain *pwrdm, u32 state)
                 }
         }
 
-        ret = pwrdm_set_next_pwrst(pwrdm, state);
-        if (ret) {
-                pr_err("%s: unable to set state of powerdomain: %s\n",
+        ret = pwrdm_set_next_pwrst(pwrdm, pwrst);
+        if (ret)
+                pr_err("%s: unable to set power state of powerdomain: %s\n",
                        __func__, pwrdm->name);
-                goto err;
-        }
 
         switch (sleep_switch) {
         case FORCEWAKEUP_SWITCH:
@@ -119,16 +134,16 @@ int omap_set_pwrdm_state(struct powerdomain *pwrdm, u32 state)
                 break;
         case LOWPOWERSTATE_SWITCH:
                 pwrdm_set_lowpwrstchange(pwrdm);
+                pwrdm_wait_transition(pwrdm);
+                pwrdm_state_switch(pwrdm);
                 break;
-        default:
-                return ret;
         }
 
-        pwrdm_state_switch(pwrdm);
-err:
         return ret;
 }
 
+
+
 /*
  * This API is to be called during init to set the various voltage
  * domains to the voltage as per the opp table. Typically we boot up
@@ -199,6 +214,56 @@ exit:
         return -EINVAL;
 }
 
+#ifdef CONFIG_SUSPEND
+static int omap_pm_enter(suspend_state_t suspend_state)
+{
+        int ret = 0;
+
+        if (!omap_pm_suspend)
+                return -ENOENT; /* XXX doublecheck */
+
+        switch (suspend_state) {
+        case PM_SUSPEND_STANDBY:
+        case PM_SUSPEND_MEM:
+                ret = omap_pm_suspend();
+                break;
+        default:
+                ret = -EINVAL;
+        }
+
+        return ret;
+}
+
+static int omap_pm_begin(suspend_state_t state)
+{
+        disable_hlt();
+        if (cpu_is_omap34xx())
+                omap_prcm_irq_prepare();
+        return 0;
+}
+
+static void omap_pm_end(void)
+{
+        enable_hlt();
+        return;
+}
+
+static void omap_pm_finish(void)
+{
+        if (cpu_is_omap34xx())
+                omap_prcm_irq_complete();
+}
+
+static const struct platform_suspend_ops omap_pm_ops = {
+        .begin          = omap_pm_begin,
+        .end            = omap_pm_end,
+        .enter          = omap_pm_enter,
+        .finish         = omap_pm_finish,
+        .valid          = suspend_valid_only_mem,
+};
+
+#endif /* CONFIG_SUSPEND */
+
 static void __init omap3_init_voltages(void)
 {
         if (!cpu_is_omap34xx())
@@ -230,6 +295,14 @@ postcore_initcall(omap2_common_pm_init);
 
 static int __init omap2_common_pm_late_init(void)
 {
+        /*
+         * In the case of DT, the PMIC and SR initialization will be done using
+         * a completely different mechanism.
+         * Disable this part if a DT blob is available.
+         */
+        if (of_have_populated_dt())
+                return 0;
+
         /* Init the voltage layer */
         omap_pmic_late_init();
         omap_voltage_late_init();
@@ -241,6 +314,10 @@ static int __init omap2_common_pm_late_init(void)
         /* Smartreflex device init */
         omap_devinit_smartreflex();
 
+#ifdef CONFIG_SUSPEND
+        suspend_set_ops(&omap_pm_ops);
+#endif
+
         return 0;
 }
 late_initcall(omap2_common_pm_late_init);
diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h
index b737b11e449..36fa90b6ece 100644
--- a/arch/arm/mach-omap2/pm.h
+++ b/arch/arm/mach-omap2/pm.h
@@ -18,10 +18,11 @@
 extern void *omap3_secure_ram_storage;
 extern void omap3_pm_off_mode_enable(int);
 extern void omap_sram_idle(void);
-extern int omap3_can_sleep(void);
 extern int omap_set_pwrdm_state(struct powerdomain *pwrdm, u32 state);
 extern int omap3_idle_init(void);
 extern int omap4_idle_init(void);
+extern int omap_pm_clkdms_setup(struct clockdomain *clkdm, void *unused);
+extern int (*omap_pm_suspend)(void);
 
 #if defined(CONFIG_PM_OPP)
 extern int omap3_opp_init(void);
diff --git a/arch/arm/mach-omap2/pm24xx.c b/arch/arm/mach-omap2/pm24xx.c
index 23de98d0384..5ca45ca7694 100644
--- a/arch/arm/mach-omap2/pm24xx.c
+++ b/arch/arm/mach-omap2/pm24xx.c
@@ -26,7 +26,6 @@
 #include <linux/module.h>
 #include <linux/delay.h>
 #include <linux/clk.h>
-#include <linux/io.h>
 #include <linux/irq.h>
 #include <linux/time.h>
 #include <linux/gpio.h>
@@ -35,12 +34,13 @@
 #include <asm/mach/irq.h>
 #include <asm/mach-types.h>
 
-#include <mach/irqs.h>
 #include <plat/clock.h>
 #include <plat/sram.h>
 #include <plat/dma.h>
 #include <plat/board.h>
 
+#include <mach/irqs.h>
+
 #include "common.h"
 #include "prm2xxx_3xxx.h"
 #include "prm-regbits-24xx.h"
@@ -49,23 +49,9 @@
 #include "sdrc.h"
 #include "pm.h"
 #include "control.h"
-
 #include "powerdomain.h"
 #include "clockdomain.h"
 
-#ifdef CONFIG_SUSPEND
-static suspend_state_t suspend_state = PM_SUSPEND_ON;
-static inline bool is_suspending(void)
-{
-        return (suspend_state != PM_SUSPEND_ON);
-}
-#else
-static inline bool is_suspending(void)
-{
-        return false;
-}
-#endif
-
 static void (*omap2_sram_idle)(void);
 static void (*omap2_sram_suspend)(u32 dllctrl, void __iomem *sdrc_dlla_ctrl,
                                   void __iomem *sdrc_power);
@@ -85,7 +71,7 @@ static int omap2_fclks_active(void)
         return (f1 | f2) ? 1 : 0;
 }
 
-static void omap2_enter_full_retention(void)
+static int omap2_enter_full_retention(void)
 {
         u32 l;
 
@@ -148,6 +134,8 @@ no_sleep:
 
         /* Mask future PRCM-to-MPU interrupts */
         omap2_prm_write_mod_reg(0x0, OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
+
+        return 0;
 }
 
 static int omap2_i2c_active(void)
@@ -226,7 +214,6 @@ static int omap2_can_sleep(void)
 
 static void omap2_pm_idle(void)
 {
-        local_irq_disable();
         local_fiq_disable();
 
         if (!omap2_can_sleep()) {
@@ -243,78 +230,6 @@ static void omap2_pm_idle(void)
 
 out:
         local_fiq_enable();
-        local_irq_enable();
-}
-
-#ifdef CONFIG_SUSPEND
-static int omap2_pm_begin(suspend_state_t state)
-{
-        disable_hlt();
-        suspend_state = state;
-        return 0;
-}
-
-static int omap2_pm_suspend(void)
-{
-        u32 wken_wkup, mir1;
-
-        wken_wkup = omap2_prm_read_mod_reg(WKUP_MOD, PM_WKEN);
-        wken_wkup &= ~OMAP24XX_EN_GPT1_MASK;
-        omap2_prm_write_mod_reg(wken_wkup, WKUP_MOD, PM_WKEN);
-
-        /* Mask GPT1 */
-        mir1 = omap_readl(0x480fe0a4);
-        omap_writel(1 << 5, 0x480fe0ac);
-
-        omap2_enter_full_retention();
-
-        omap_writel(mir1, 0x480fe0a4);
-        omap2_prm_write_mod_reg(wken_wkup, WKUP_MOD, PM_WKEN);
-
-        return 0;
-}
-
-static int omap2_pm_enter(suspend_state_t state)
-{
-        int ret = 0;
-
-        switch (state) {
-        case PM_SUSPEND_STANDBY:
-        case PM_SUSPEND_MEM:
-                ret = omap2_pm_suspend();
-                break;
-        default:
-                ret = -EINVAL;
-        }
-
-        return ret;
-}
-
-static void omap2_pm_end(void)
-{
-        suspend_state = PM_SUSPEND_ON;
-        enable_hlt();
-}
-
-static const struct platform_suspend_ops omap_pm_ops = {
-        .begin          = omap2_pm_begin,
-        .enter          = omap2_pm_enter,
-        .end            = omap2_pm_end,
-        .valid          = suspend_valid_only_mem,
-};
-#else
-static const struct platform_suspend_ops __initdata omap_pm_ops;
-#endif /* CONFIG_SUSPEND */
-
-/* XXX This function should be shareable between OMAP2xxx and OMAP3 */
-static int __init clkdms_setup(struct clockdomain *clkdm, void *unused)
-{
-        if (clkdm->flags & CLKDM_CAN_ENABLE_AUTO)
-                clkdm_allow_idle(clkdm);
-        else if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP &&
-                 atomic_read(&clkdm->usecount) == 0)
-                clkdm_sleep(clkdm);
-        return 0;
 }
 
 static void __init prcm_setup_regs(void)
@@ -358,9 +273,13 @@ static void __init prcm_setup_regs(void)
         clkdm_sleep(gfx_clkdm);
 
         /* Enable hardware-supervised idle for all clkdms */
-        clkdm_for_each(clkdms_setup, NULL);
+        clkdm_for_each(omap_pm_clkdms_setup, NULL);
         clkdm_add_wkdep(mpu_clkdm, wkup_clkdm);
 
+#ifdef CONFIG_SUSPEND
+        omap_pm_suspend = omap2_enter_full_retention;
+#endif
+
         /* REVISIT: Configure number of 32 kHz clock cycles for sys_clk
          * stabilisation */
         omap2_prm_write_mod_reg(15 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_GR_MOD,
@@ -461,8 +380,7 @@ static int __init omap2_pm_init(void)
                                                     omap24xx_cpu_suspend_sz);
         }
 
-        suspend_set_ops(&omap_pm_ops);
-        pm_idle = omap2_pm_idle;
+        arm_pm_idle = omap2_pm_idle;
 
         return 0;
 }
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index fc698757892..027a537d72b 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -50,10 +50,6 @@
 #include "sdrc.h"
 #include "control.h"
 
-#ifdef CONFIG_SUSPEND
-static suspend_state_t suspend_state = PM_SUSPEND_ON;
-#endif
-
 /* pm34xx errata defined in pm.h */
 u16 pm34xx_errata;
 
@@ -75,16 +71,6 @@ static struct powerdomain *mpu_pwrdm, *neon_pwrdm;
 static struct powerdomain *core_pwrdm, *per_pwrdm;
 static struct powerdomain *cam_pwrdm;
 
-static inline void omap3_per_save_context(void)
-{
-        omap_gpio_save_context();
-}
-
-static inline void omap3_per_restore_context(void)
-{
-        omap_gpio_restore_context();
-}
-
 static void omap3_enable_io_chain(void)
 {
         int timeout = 0;
@@ -290,11 +276,6 @@ void omap_sram_idle(void)
         int core_prev_state, per_prev_state;
         u32 sdrc_pwr = 0;
 
-        pwrdm_clear_all_prev_pwrst(mpu_pwrdm);
-        pwrdm_clear_all_prev_pwrst(neon_pwrdm);
-        pwrdm_clear_all_prev_pwrst(core_pwrdm);
-        pwrdm_clear_all_prev_pwrst(per_pwrdm);
-
         mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm);
         switch (mpu_next_state) {
         case PWRDM_POWER_ON:
@@ -332,8 +313,6 @@ void omap_sram_idle(void)
         if (per_next_state < PWRDM_POWER_ON) {
                 per_going_off = (per_next_state == PWRDM_POWER_OFF) ? 1 : 0;
                 omap2_gpio_prepare_for_idle(per_going_off);
-                if (per_next_state == PWRDM_POWER_OFF)
-                                omap3_per_save_context();
         }
 
         /* CORE */
@@ -399,8 +378,6 @@ void omap_sram_idle(void)
         if (per_next_state < PWRDM_POWER_ON) {
                 per_prev_state = pwrdm_read_prev_pwrst(per_pwrdm);
                 omap2_gpio_resume_after_idle();
-                if (per_prev_state == PWRDM_POWER_OFF)
-                        omap3_per_restore_context();
         }
 
         /* Disable IO-PAD and IO-CHAIN wakeup */
@@ -418,10 +395,9 @@ void omap_sram_idle(void)
 
 static void omap3_pm_idle(void)
 {
-        local_irq_disable();
         local_fiq_disable();
 
-        if (omap_irq_pending() || need_resched())
+        if (omap_irq_pending())
                 goto out;
 
         trace_power_start(POWER_CSTATE, 1, smp_processor_id());
@@ -434,7 +410,6 @@ static void omap3_pm_idle(void)
 
 out:
         local_fiq_enable();
-        local_irq_enable();
 }
 
 #ifdef CONFIG_SUSPEND
@@ -479,50 +454,6 @@ restore:
         return ret;
 }
 
-static int omap3_pm_enter(suspend_state_t unused)
-{
-        int ret = 0;
-
-        switch (suspend_state) {
-        case PM_SUSPEND_STANDBY:
-        case PM_SUSPEND_MEM:
-                ret = omap3_pm_suspend();
-                break;
-        default:
-                ret = -EINVAL;
-        }
-
-        return ret;
-}
-
-/* Hooks to enable / disable UART interrupts during suspend */
-static int omap3_pm_begin(suspend_state_t state)
-{
-        disable_hlt();
-        suspend_state = state;
-        omap_prcm_irq_prepare();
-        return 0;
-}
-
-static void omap3_pm_end(void)
-{
-        suspend_state = PM_SUSPEND_ON;
-        enable_hlt();
-        return;
-}
-
-static void omap3_pm_finish(void)
-{
-        omap_prcm_irq_complete();
-}
-
-static const struct platform_suspend_ops omap_pm_ops = {
-        .begin          = omap3_pm_begin,
-        .end            = omap3_pm_end,
-        .enter          = omap3_pm_enter,
-        .finish         = omap3_pm_finish,
-        .valid          = suspend_valid_only_mem,
-};
 #endif /* CONFIG_SUSPEND */
 
 
@@ -743,21 +674,6 @@ static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused)
 }
 
 /*
- * Enable hw supervised mode for all clockdomains if it's
- * supported. Initiate sleep transition for other clockdomains, if
- * they are not used
- */
-static int __init clkdms_setup(struct clockdomain *clkdm, void *unused)
-{
-        if (clkdm->flags & CLKDM_CAN_ENABLE_AUTO)
-                clkdm_allow_idle(clkdm);
-        else if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP &&
-                 atomic_read(&clkdm->usecount) == 0)
-                clkdm_sleep(clkdm);
-        return 0;
-}
-
-/*
  * Push functions to SRAM
  *
  * The minimum set of functions is pushed to SRAM for execution:
@@ -826,7 +742,7 @@ static int __init omap3_pm_init(void)
                 goto err2;
         }
 
-        (void) clkdm_for_each(clkdms_setup, NULL);
+        (void) clkdm_for_each(omap_pm_clkdms_setup, NULL);
 
         mpu_pwrdm = pwrdm_lookup("mpu_pwrdm");
         if (mpu_pwrdm == NULL) {
@@ -845,10 +761,10 @@ static int __init omap3_pm_init(void)
         core_clkdm = clkdm_lookup("core_clkdm");
 
 #ifdef CONFIG_SUSPEND
-        suspend_set_ops(&omap_pm_ops);
-#endif /* CONFIG_SUSPEND */
+        omap_pm_suspend = omap3_pm_suspend;
+#endif
 
-        pm_idle = omap3_pm_idle;
+        arm_pm_idle = omap3_pm_idle;
         omap3_idle_init();
 
         /*
diff --git a/arch/arm/mach-omap2/pm44xx.c b/arch/arm/mach-omap2/pm44xx.c
index c264ef7219c..91e0b1c9b76 100644
--- a/arch/arm/mach-omap2/pm44xx.c
+++ b/arch/arm/mach-omap2/pm44xx.c
@@ -83,59 +83,8 @@ static int omap4_pm_suspend(void)
 
         return 0;
 }
-
-static int omap4_pm_enter(suspend_state_t suspend_state)
-{
-        int ret = 0;
-
-        switch (suspend_state) {
-        case PM_SUSPEND_STANDBY:
-        case PM_SUSPEND_MEM:
-                ret = omap4_pm_suspend();
-                break;
-        default:
-                ret = -EINVAL;
-        }
-
-        return ret;
-}
-
-static int omap4_pm_begin(suspend_state_t state)
-{
-        disable_hlt();
-        return 0;
-}
-
-static void omap4_pm_end(void)
-{
-        enable_hlt();
-        return;
-}
-
-static const struct platform_suspend_ops omap_pm_ops = {
-        .begin          = omap4_pm_begin,
-        .end            = omap4_pm_end,
-        .enter          = omap4_pm_enter,
-        .valid          = suspend_valid_only_mem,
-};
 #endif /* CONFIG_SUSPEND */
 
-/*
- * Enable hardware supervised mode for all clockdomains if it's
- * supported. Initiate sleep transition for other clockdomains, if
- * they are not used
- */
-static int __init clkdms_setup(struct clockdomain *clkdm, void *unused)
-{
-        if (clkdm->flags & CLKDM_CAN_ENABLE_AUTO)
-                clkdm_allow_idle(clkdm);
-        else if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP &&
-                        atomic_read(&clkdm->usecount) == 0)
-                clkdm_sleep(clkdm);
-        return 0;
-}
-
-
 static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused)
 {
         struct power_state *pwrst;
@@ -173,18 +122,16 @@ static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused)
  * omap_default_idle - OMAP4 default ilde routine.'
  *
  * Implements OMAP4 memory, IO ordering requirements which can't be addressed
- * with default arch_idle() hook. Used by all CPUs with !CONFIG_CPUIDLE and
+ * with default cpu_do_idle() hook. Used by all CPUs with !CONFIG_CPUIDLE and
  * by secondary CPU with CONFIG_CPUIDLE.
  */
 static void omap_default_idle(void)
 {
-        local_irq_disable();
         local_fiq_disable();
 
         omap_do_wfi();
 
         local_fiq_enable();
-        local_irq_enable();
 }
 
 /**
@@ -249,14 +196,14 @@ static int __init omap4_pm_init(void)
                 goto err2;
         }
 
-        (void) clkdm_for_each(clkdms_setup, NULL);
+        (void) clkdm_for_each(omap_pm_clkdms_setup, NULL);
 
 #ifdef CONFIG_SUSPEND
-        suspend_set_ops(&omap_pm_ops);
-#endif /* CONFIG_SUSPEND */
+        omap_pm_suspend = omap4_pm_suspend;
+#endif
 
-        /* Overwrite the default arch_idle() */
-        pm_idle = omap_default_idle;
+        /* Overwrite the default cpu_do_idle() */
+        arm_pm_idle = omap_default_idle;
 
         omap4_idle_init();
 
diff --git a/arch/arm/mach-omap2/powerdomain-common.c b/arch/arm/mach-omap2/powerdomain-common.c
index f97afff68d6..c0aeabfcf00 100644
--- a/arch/arm/mach-omap2/powerdomain-common.c
+++ b/arch/arm/mach-omap2/powerdomain-common.c
@@ -13,6 +13,7 @@
 
 #include <linux/errno.h>
 #include <linux/kernel.h>
+#include <linux/bug.h>
 #include "pm.h"
 #include "cm.h"
 #include "cm-regbits-34xx.h"
diff --git a/arch/arm/mach-omap2/powerdomain2xxx_3xxx.c b/arch/arm/mach-omap2/powerdomain2xxx_3xxx.c
index 6a17e4ca1d7..0f0a9f1592f 100644
--- a/arch/arm/mach-omap2/powerdomain2xxx_3xxx.c
+++ b/arch/arm/mach-omap2/powerdomain2xxx_3xxx.c
@@ -15,6 +15,7 @@
 #include <linux/io.h>
 #include <linux/errno.h>
 #include <linux/delay.h>
+#include <linux/bug.h>
 
 #include <plat/prcm.h>
 
diff --git a/arch/arm/mach-omap2/powerdomain44xx.c b/arch/arm/mach-omap2/powerdomain44xx.c
index a7880af4b3d..601325b852a 100644
--- a/arch/arm/mach-omap2/powerdomain44xx.c
+++ b/arch/arm/mach-omap2/powerdomain44xx.c
@@ -15,6 +15,7 @@
 #include <linux/io.h>
 #include <linux/errno.h>
 #include <linux/delay.h>
+#include <linux/bug.h>
 
 #include "powerdomain.h"
 #include <plat/prcm.h>
diff --git a/arch/arm/mach-omap2/powerdomains3xxx_data.c b/arch/arm/mach-omap2/powerdomains3xxx_data.c
index 8ef26daeed6..b7ea468eea3 100644
--- a/arch/arm/mach-omap2/powerdomains3xxx_data.c
+++ b/arch/arm/mach-omap2/powerdomains3xxx_data.c
@@ -13,6 +13,7 @@
 
 #include <linux/kernel.h>
 #include <linux/init.h>
+#include <linux/bug.h>
 
 #include <plat/cpu.h>
 
diff --git a/arch/arm/mach-omap2/prcm_mpu44xx.c b/arch/arm/mach-omap2/prcm_mpu44xx.c
index ca669b50f39..928dbd4f20e 100644
--- a/arch/arm/mach-omap2/prcm_mpu44xx.c
+++ b/arch/arm/mach-omap2/prcm_mpu44xx.c
@@ -15,8 +15,8 @@
 #include <linux/err.h>
 #include <linux/io.h>
 
+#include "iomap.h"
 #include "common.h"
-
 #include "prcm_mpu44xx.h"
 #include "cm-regbits-44xx.h"
 
diff --git a/arch/arm/mach-omap2/prm44xx.c b/arch/arm/mach-omap2/prm44xx.c
index a1d6154dc12..eac623c7c3d 100644
--- a/arch/arm/mach-omap2/prm44xx.c
+++ b/arch/arm/mach-omap2/prm44xx.c
@@ -17,11 +17,12 @@
 #include <linux/err.h>
 #include <linux/io.h>
 
-#include "common.h"
 #include <plat/cpu.h>
 #include <plat/irqs.h>
 #include <plat/prcm.h>
 
+#include "iomap.h"
+#include "common.h"
 #include "vp.h"
 #include "prm44xx.h"
 #include "prm-regbits-44xx.h"
diff --git a/arch/arm/mach-omap2/prm_common.c b/arch/arm/mach-omap2/prm_common.c
index 860118ab43e..873b51d494e 100644
--- a/arch/arm/mach-omap2/prm_common.c
+++ b/arch/arm/mach-omap2/prm_common.c
@@ -24,7 +24,6 @@
 #include <linux/interrupt.h>
 #include <linux/slab.h>
 
-#include <mach/system.h>
 #include <plat/common.h>
 #include <plat/prcm.h>
 #include <plat/irqs.h>
diff --git a/arch/arm/mach-omap2/prminst44xx.c b/arch/arm/mach-omap2/prminst44xx.c
index f6de5bc6b12..9b3898a3ac9 100644
--- a/arch/arm/mach-omap2/prminst44xx.c
+++ b/arch/arm/mach-omap2/prminst44xx.c
@@ -16,8 +16,8 @@
 #include <linux/err.h>
 #include <linux/io.h>
 
+#include "iomap.h"
 #include "common.h"
-
 #include "prm44xx.h"
 #include "prminst44xx.h"
 #include "prm-regbits-44xx.h"
diff --git a/arch/arm/mach-omap2/sdram-nokia.c b/arch/arm/mach-omap2/sdram-nokia.c
index 7479d7ea137..845c4fd2b12 100644
--- a/arch/arm/mach-omap2/sdram-nokia.c
+++ b/arch/arm/mach-omap2/sdram-nokia.c
@@ -17,7 +17,6 @@
 #include <linux/err.h>
 #include <linux/io.h>
 
-#include <plat/io.h>
 #include "common.h"
 #include <plat/clock.h>
 #include <plat/sdrc.h>
diff --git a/arch/arm/mach-omap2/sdrc2xxx.c b/arch/arm/mach-omap2/sdrc2xxx.c
index 791a63cdceb..1133bb2f632 100644
--- a/arch/arm/mach-omap2/sdrc2xxx.c
+++ b/arch/arm/mach-omap2/sdrc2xxx.c
@@ -24,13 +24,15 @@
 #include <linux/clk.h>
 #include <linux/io.h>
 
-#include "common.h"
+#include <plat/hardware.h>
 #include <plat/clock.h>
 #include <plat/sram.h>
+#include <plat/sdrc.h>
 
+#include "iomap.h"
+#include "common.h"
 #include "prm2xxx_3xxx.h"
 #include "clock.h"
-#include <plat/sdrc.h>
 #include "sdrc.h"
 
 /* Memory timing, DLL mode flags */
diff --git a/arch/arm/mach-omap2/serial.c b/arch/arm/mach-omap2/serial.c
index f590afc1f67..0cdd359a128 100644
--- a/arch/arm/mach-omap2/serial.c
+++ b/arch/arm/mach-omap2/serial.c
@@ -54,11 +54,9 @@
 
 struct omap_uart_state {
         int num;
-        int can_sleep;
 
         struct list_head node;
         struct omap_hwmod *oh;
-        struct platform_device *pdev;
 };
 
 static LIST_HEAD(uart_list);
@@ -381,8 +379,6 @@ void __init omap_serial_init_port(struct omap_board_data *bdata,
 
         oh->mux = omap_hwmod_mux_init(bdata->pads, bdata->pads_cnt);
 
-        uart->pdev = pdev;
-
         oh->dev_attr = uart;
 
         if (((cpu_is_omap34xx() || cpu_is_omap44xx()) && bdata->pads)
diff --git a/arch/arm/mach-omap2/sleep24xx.S b/arch/arm/mach-omap2/sleep24xx.S
index b5071a47ec3..d4bf904d84a 100644
--- a/arch/arm/mach-omap2/sleep24xx.S
+++ b/arch/arm/mach-omap2/sleep24xx.S
@@ -27,7 +27,6 @@
 
 #include <linux/linkage.h>
 #include <asm/assembler.h>
-#include <mach/io.h>
 
 #include <plat/omap24xx.h>
 
diff --git a/arch/arm/mach-omap2/sleep34xx.S b/arch/arm/mach-omap2/sleep34xx.S
index f2ea1bd1c69..1f62f23673f 100644
--- a/arch/arm/mach-omap2/sleep34xx.S
+++ b/arch/arm/mach-omap2/sleep34xx.S
@@ -23,10 +23,13 @@
  * MA 02111-1307 USA
  */
 #include <linux/linkage.h>
+
 #include <asm/assembler.h>
+
+#include <plat/hardware.h>
 #include <plat/sram.h>
-#include <mach/io.h>
 
+#include "iomap.h"
 #include "cm2xxx_3xxx.h"
 #include "prm2xxx_3xxx.h"
 #include "sdrc.h"
diff --git a/arch/arm/mach-omap2/smartreflex-class3.c b/arch/arm/mach-omap2/smartreflex-class3.c
index 53d9d0a5b39..955566eefac 100644
--- a/arch/arm/mach-omap2/smartreflex-class3.c
+++ b/arch/arm/mach-omap2/smartreflex-class3.c
@@ -29,6 +29,7 @@ static int sr_class3_enable(struct voltagedomain *voltdm)
 
 static int sr_class3_disable(struct voltagedomain *voltdm, int is_volt_reset)
 {
+        sr_disable_errgen(voltdm);
         omap_vp_disable(voltdm);
         sr_disable(voltdm);
         if (is_volt_reset)
diff --git a/arch/arm/mach-omap2/smartreflex.c b/arch/arm/mach-omap2/smartreflex.c
index 7e755bb0ffc..008fbd7b935 100644
--- a/arch/arm/mach-omap2/smartreflex.c
+++ b/arch/arm/mach-omap2/smartreflex.c
@@ -36,6 +36,12 @@
 #define SR_DISABLE_TIMEOUT      200
 
 struct omap_sr {
+        struct list_head                node;
+        struct platform_device          *pdev;
+        struct omap_sr_nvalue_table     *nvalue_table;
+        struct voltagedomain            *voltdm;
+        struct dentry                   *dbg_dir;
+        unsigned int                    irq;
         int                             srid;
         int                             ip_type;
         int                             nvalue_count;
@@ -49,13 +55,7 @@ struct omap_sr {
         u32                             senp_avgweight;
         u32                             senp_mod;
         u32                             senn_mod;
-        unsigned int                    irq;
         void __iomem                    *base;
-        struct platform_device          *pdev;
-        struct list_head                node;
-        struct omap_sr_nvalue_table     *nvalue_table;
-        struct voltagedomain            *voltdm;
-        struct dentry                   *dbg_dir;
 };
 
 /* sr_list contains all the instances of smartreflex module */
@@ -74,10 +74,6 @@ static inline void sr_modify_reg(struct omap_sr *sr, unsigned offset, u32 mask,
                                         u32 value)
 {
         u32 reg_val;
-        u32 errconfig_offs = 0, errconfig_mask = 0;
-
-        reg_val = __raw_readl(sr->base + offset);
-        reg_val &= ~mask;
 
         /*
          * Smartreflex error config register is special as it contains
@@ -88,16 +84,15 @@ static inline void sr_modify_reg(struct omap_sr *sr, unsigned offset, u32 mask,
          * if they are currently set, but does allow the caller to write
          * those bits.
          */
-        if (sr->ip_type == SR_TYPE_V1) {
-                errconfig_offs = ERRCONFIG_V1;
-                errconfig_mask = ERRCONFIG_STATUS_V1_MASK;
-        } else if (sr->ip_type == SR_TYPE_V2) {
-                errconfig_offs = ERRCONFIG_V2;
-                errconfig_mask = ERRCONFIG_VPBOUNDINTST_V2;
-        }
+        if (sr->ip_type == SR_TYPE_V1 && offset == ERRCONFIG_V1)
+                mask |= ERRCONFIG_STATUS_V1_MASK;
+        else if (sr->ip_type == SR_TYPE_V2 && offset == ERRCONFIG_V2)
+                mask |= ERRCONFIG_VPBOUNDINTST_V2;
+
+        reg_val = __raw_readl(sr->base + offset);
+        reg_val &= ~mask;
 
-        if (offset == errconfig_offs)
-                reg_val &= ~errconfig_mask;
+        value &= mask;
 
         reg_val |= value;
 
@@ -128,21 +123,28 @@ static struct omap_sr *_sr_lookup(struct voltagedomain *voltdm)
 
 static irqreturn_t sr_interrupt(int irq, void *data)
 {
-        struct omap_sr *sr_info = (struct omap_sr *)data;
+        struct omap_sr *sr_info = data;
         u32 status = 0;
 
-        if (sr_info->ip_type == SR_TYPE_V1) {
+        switch (sr_info->ip_type) {
+        case SR_TYPE_V1:
                 /* Read the status bits */
                 status = sr_read_reg(sr_info, ERRCONFIG_V1);
 
                 /* Clear them by writing back */
                 sr_write_reg(sr_info, ERRCONFIG_V1, status);
-        } else if (sr_info->ip_type == SR_TYPE_V2) {
+                break;
+        case SR_TYPE_V2:
                 /* Read the status bits */
                 status = sr_read_reg(sr_info, IRQSTATUS);
 
                 /* Clear them by writing back */
                 sr_write_reg(sr_info, IRQSTATUS, status);
+                break;
+        default:
+                dev_err(&sr_info->pdev->dev, "UNKNOWN IP type %d\n",
+                        sr_info->ip_type);
+                return IRQ_NONE;
         }
 
         if (sr_class->notify)
@@ -166,6 +168,7 @@ static void sr_set_clk_length(struct omap_sr *sr)
                         __func__);
                 return;
         }
+
         sys_clk_speed = clk_get_rate(sys_ck);
         clk_put(sys_ck);
 
@@ -267,7 +270,7 @@ static int sr_late_init(struct omap_sr *sr_info)
                         goto error;
                 }
                 ret = request_irq(sr_info->irq, sr_interrupt,
-                                0, name, (void *)sr_info);
+                                0, name, sr_info);
                 if (ret)
                         goto error;
                 disable_irq(sr_info->irq);
@@ -288,12 +291,15 @@ error:
                 "not function as desired\n", __func__);
         kfree(name);
         kfree(sr_info);
+
         return ret;
 }
 
 static void sr_v1_disable(struct omap_sr *sr)
 {
         int timeout = 0;
+        int errconf_val = ERRCONFIG_MCUACCUMINTST | ERRCONFIG_MCUVALIDINTST |
+                        ERRCONFIG_MCUBOUNDINTST;
 
         /* Enable MCUDisableAcknowledge interrupt */
         sr_modify_reg(sr, ERRCONFIG_V1,
@@ -302,13 +308,13 @@ static void sr_v1_disable(struct omap_sr *sr)
         /* SRCONFIG - disable SR */
         sr_modify_reg(sr, SRCONFIG, SRCONFIG_SRENABLE, 0x0);
 
-        /* Disable all other SR interrupts and clear the status */
+        /* Disable all other SR interrupts and clear the status as needed */
+        if (sr_read_reg(sr, ERRCONFIG_V1) & ERRCONFIG_VPBOUNDINTST_V1)
+                errconf_val |= ERRCONFIG_VPBOUNDINTST_V1;
         sr_modify_reg(sr, ERRCONFIG_V1,
                         (ERRCONFIG_MCUACCUMINTEN | ERRCONFIG_MCUVALIDINTEN |
                         ERRCONFIG_MCUBOUNDINTEN | ERRCONFIG_VPBOUNDINTEN_V1),
-                        (ERRCONFIG_MCUACCUMINTST | ERRCONFIG_MCUVALIDINTST |
-                        ERRCONFIG_MCUBOUNDINTST |
-                        ERRCONFIG_VPBOUNDINTST_V1));
+                        errconf_val);
 
         /*
          * Wait for SR to be disabled.
@@ -337,9 +343,17 @@ static void sr_v2_disable(struct omap_sr *sr)
         /* SRCONFIG - disable SR */
         sr_modify_reg(sr, SRCONFIG, SRCONFIG_SRENABLE, 0x0);
 
-        /* Disable all other SR interrupts and clear the status */
-        sr_modify_reg(sr, ERRCONFIG_V2, ERRCONFIG_VPBOUNDINTEN_V2,
+        /*
+         * Disable all other SR interrupts and clear the status
+         * write to status register ONLY on need basis - only if status
+         * is set.
+         */
+        if (sr_read_reg(sr, ERRCONFIG_V2) & ERRCONFIG_VPBOUNDINTST_V2)
+                sr_modify_reg(sr, ERRCONFIG_V2, ERRCONFIG_VPBOUNDINTEN_V2,
                         ERRCONFIG_VPBOUNDINTST_V2);
+        else
+                sr_modify_reg(sr, ERRCONFIG_V2, ERRCONFIG_VPBOUNDINTEN_V2,
+                                0x0);
         sr_write_reg(sr, IRQENABLE_CLR, (IRQENABLE_MCUACCUMINT |
                         IRQENABLE_MCUVALIDINT |
                         IRQENABLE_MCUBOUNDSINT));
@@ -398,15 +412,16 @@ static u32 sr_retrieve_nvalue(struct omap_sr *sr, u32 efuse_offs)
  */
 int sr_configure_errgen(struct voltagedomain *voltdm)
 {
-        u32 sr_config, sr_errconfig, errconfig_offs, vpboundint_en;
-        u32 vpboundint_st, senp_en = 0, senn_en = 0;
+        u32 sr_config, sr_errconfig, errconfig_offs;
+        u32 vpboundint_en, vpboundint_st;
+        u32 senp_en = 0, senn_en = 0;
         u8 senp_shift, senn_shift;
         struct omap_sr *sr = _sr_lookup(voltdm);
 
         if (IS_ERR(sr)) {
                 pr_warning("%s: omap_sr struct for sr_%s not found\n",
                         __func__, voltdm->name);
-                return -EINVAL;
+                return PTR_ERR(sr);
         }
 
         if (!sr->clk_length)
@@ -418,20 +433,23 @@ int sr_configure_errgen(struct voltagedomain *voltdm)
         sr_config = (sr->clk_length << SRCONFIG_SRCLKLENGTH_SHIFT) |
                 SRCONFIG_SENENABLE | SRCONFIG_ERRGEN_EN;
 
-        if (sr->ip_type == SR_TYPE_V1) {
+        switch (sr->ip_type) {
+        case SR_TYPE_V1:
                 sr_config |= SRCONFIG_DELAYCTRL;
                 senn_shift = SRCONFIG_SENNENABLE_V1_SHIFT;
                 senp_shift = SRCONFIG_SENPENABLE_V1_SHIFT;
                 errconfig_offs = ERRCONFIG_V1;
                 vpboundint_en = ERRCONFIG_VPBOUNDINTEN_V1;
                 vpboundint_st = ERRCONFIG_VPBOUNDINTST_V1;
-        } else if (sr->ip_type == SR_TYPE_V2) {
+                break;
+        case SR_TYPE_V2:
                 senn_shift = SRCONFIG_SENNENABLE_V2_SHIFT;
                 senp_shift = SRCONFIG_SENPENABLE_V2_SHIFT;
                 errconfig_offs = ERRCONFIG_V2;
                 vpboundint_en = ERRCONFIG_VPBOUNDINTEN_V2;
                 vpboundint_st = ERRCONFIG_VPBOUNDINTST_V2;
-        } else {
+                break;
+        default:
                 dev_err(&sr->pdev->dev, "%s: Trying to Configure smartreflex"
                         "module without specifying the ip\n", __func__);
                 return -EINVAL;
@@ -447,8 +465,55 @@ int sr_configure_errgen(struct voltagedomain *voltdm)
                 sr_errconfig);
 
         /* Enabling the interrupts if the ERROR module is used */
-        sr_modify_reg(sr, errconfig_offs,
-                vpboundint_en, (vpboundint_en | vpboundint_st));
+        sr_modify_reg(sr, errconfig_offs, (vpboundint_en | vpboundint_st),
+                      vpboundint_en);
+
+        return 0;
+}
+
+/**
+ * sr_disable_errgen() - Disables SmartReflex AVS module's errgen component
+ * @voltdm:     VDD pointer to which the SR module to be configured belongs to.
+ *
+ * This API is to be called from the smartreflex class driver to
+ * disable the error generator module inside the smartreflex module.
+ *
+ * Returns 0 on success and error value in case of failure.
+ */
+int sr_disable_errgen(struct voltagedomain *voltdm)
+{
+        u32 errconfig_offs;
+        u32 vpboundint_en, vpboundint_st;
+        struct omap_sr *sr = _sr_lookup(voltdm);
+
+        if (IS_ERR(sr)) {
+                pr_warning("%s: omap_sr struct for sr_%s not found\n",
+                        __func__, voltdm->name);
+                return PTR_ERR(sr);
+        }
+
+        switch (sr->ip_type) {
+        case SR_TYPE_V1:
+                errconfig_offs = ERRCONFIG_V1;
+                vpboundint_en = ERRCONFIG_VPBOUNDINTEN_V1;
+                vpboundint_st = ERRCONFIG_VPBOUNDINTST_V1;
+                break;
+        case SR_TYPE_V2:
+                errconfig_offs = ERRCONFIG_V2;
+                vpboundint_en = ERRCONFIG_VPBOUNDINTEN_V2;
+                vpboundint_st = ERRCONFIG_VPBOUNDINTST_V2;
+                break;
+        default:
+                dev_err(&sr->pdev->dev, "%s: Trying to Configure smartreflex"
+                        "module without specifying the ip\n", __func__);
+                return -EINVAL;
+        }
+
+        /* Disable the interrupts of ERROR module */
+        sr_modify_reg(sr, errconfig_offs, vpboundint_en | vpboundint_st, 0);
+
+        /* Disable the Sensor and errorgen */
+        sr_modify_reg(sr, SRCONFIG, SRCONFIG_SENENABLE | SRCONFIG_ERRGEN_EN, 0);
 
         return 0;
 }
@@ -475,7 +540,7 @@ int sr_configure_minmax(struct voltagedomain *voltdm)
         if (IS_ERR(sr)) {
                 pr_warning("%s: omap_sr struct for sr_%s not found\n",
                         __func__, voltdm->name);
-                return -EINVAL;
+                return PTR_ERR(sr);
         }
 
         if (!sr->clk_length)
@@ -488,14 +553,17 @@ int sr_configure_minmax(struct voltagedomain *voltdm)
                 SRCONFIG_SENENABLE |
                 (sr->accum_data << SRCONFIG_ACCUMDATA_SHIFT);
 
-        if (sr->ip_type == SR_TYPE_V1) {
+        switch (sr->ip_type) {
+        case SR_TYPE_V1:
                 sr_config |= SRCONFIG_DELAYCTRL;
                 senn_shift = SRCONFIG_SENNENABLE_V1_SHIFT;
                 senp_shift = SRCONFIG_SENPENABLE_V1_SHIFT;
-        } else if (sr->ip_type == SR_TYPE_V2) {
+                break;
+        case SR_TYPE_V2:
                 senn_shift = SRCONFIG_SENNENABLE_V2_SHIFT;
                 senp_shift = SRCONFIG_SENPENABLE_V2_SHIFT;
-        } else {
+                break;
+        default:
                 dev_err(&sr->pdev->dev, "%s: Trying to Configure smartreflex"
                         "module without specifying the ip\n", __func__);
                 return -EINVAL;
@@ -511,20 +579,27 @@ int sr_configure_minmax(struct voltagedomain *voltdm)
          * Enabling the interrupts if MINMAXAVG module is used.
          * TODO: check if all the interrupts are mandatory
          */
-        if (sr->ip_type == SR_TYPE_V1) {
+        switch (sr->ip_type) {
+        case SR_TYPE_V1:
                 sr_modify_reg(sr, ERRCONFIG_V1,
                         (ERRCONFIG_MCUACCUMINTEN | ERRCONFIG_MCUVALIDINTEN |
                         ERRCONFIG_MCUBOUNDINTEN),
                         (ERRCONFIG_MCUACCUMINTEN | ERRCONFIG_MCUACCUMINTST |
                          ERRCONFIG_MCUVALIDINTEN | ERRCONFIG_MCUVALIDINTST |
                          ERRCONFIG_MCUBOUNDINTEN | ERRCONFIG_MCUBOUNDINTST));
-        } else if (sr->ip_type == SR_TYPE_V2) {
+                break;
+        case SR_TYPE_V2:
                 sr_write_reg(sr, IRQSTATUS,
                         IRQSTATUS_MCUACCUMINT | IRQSTATUS_MCVALIDINT |
                         IRQSTATUS_MCBOUNDSINT | IRQSTATUS_MCUDISABLEACKINT);
                 sr_write_reg(sr, IRQENABLE_SET,
                         IRQENABLE_MCUACCUMINT | IRQENABLE_MCUVALIDINT |
                         IRQENABLE_MCUBOUNDSINT | IRQENABLE_MCUDISABLEACKINT);
+                break;
+        default:
+                dev_err(&sr->pdev->dev, "%s: Trying to Configure smartreflex"
+                        "module without specifying the ip\n", __func__);
+                return -EINVAL;
         }
 
         return 0;
@@ -543,15 +618,15 @@ int sr_configure_minmax(struct voltagedomain *voltdm)
  */
 int sr_enable(struct voltagedomain *voltdm, unsigned long volt)
 {
-        u32 nvalue_reciprocal;
         struct omap_volt_data *volt_data;
         struct omap_sr *sr = _sr_lookup(voltdm);
+        u32 nvalue_reciprocal;
         int ret;
 
         if (IS_ERR(sr)) {
                 pr_warning("%s: omap_sr struct for sr_%s not found\n",
                         __func__, voltdm->name);
-                return -EINVAL;
+                return PTR_ERR(sr);
         }
 
         volt_data = omap_voltage_get_voltdata(sr->voltdm, volt);
@@ -559,7 +634,7 @@ int sr_enable(struct voltagedomain *voltdm, unsigned long volt)
         if (IS_ERR(volt_data)) {
                 dev_warn(&sr->pdev->dev, "%s: Unable to get voltage table"
                         "for nominal voltage %ld\n", __func__, volt);
-                return -ENODATA;
+                return PTR_ERR(volt_data);
         }
 
         nvalue_reciprocal = sr_retrieve_nvalue(sr, volt_data->sr_efuse_offs);
@@ -617,10 +692,17 @@ void sr_disable(struct voltagedomain *voltdm)
          * disable the clocks.
          */
         if (sr_read_reg(sr, SRCONFIG) & SRCONFIG_SRENABLE) {
-                if (sr->ip_type == SR_TYPE_V1)
+                switch (sr->ip_type) {
+                case SR_TYPE_V1:
                         sr_v1_disable(sr);
-                else if (sr->ip_type == SR_TYPE_V2)
+                        break;
+                case SR_TYPE_V2:
                         sr_v2_disable(sr);
+                        break;
+                default:
+                        dev_err(&sr->pdev->dev, "UNKNOWN IP type %d\n",
+                                sr->ip_type);
+                }
         }
 
         pm_runtime_put_sync_suspend(&sr->pdev->dev);
@@ -779,10 +861,10 @@ void omap_sr_register_pmic(struct omap_sr_pmic_data *pmic_data)
         sr_pmic_data = pmic_data;
 }
 
-/* PM Debug Fs enteries to enable disable smartreflex. */
+/* PM Debug FS entries to enable and disable smartreflex. */
 static int omap_sr_autocomp_show(void *data, u64 *val)
 {
-        struct omap_sr *sr_info = (struct omap_sr *) data;
+        struct omap_sr *sr_info = data;
 
         if (!sr_info) {
                 pr_warning("%s: omap_sr struct not found\n", __func__);
@@ -796,7 +878,7 @@ static int omap_sr_autocomp_show(void *data, u64 *val)
 
 static int omap_sr_autocomp_store(void *data, u64 val)
 {
-        struct omap_sr *sr_info = (struct omap_sr *) data;
+        struct omap_sr *sr_info = data;
 
         if (!sr_info) {
                 pr_warning("%s: omap_sr struct not found\n", __func__);
@@ -804,7 +886,7 @@ static int omap_sr_autocomp_store(void *data, u64 val)
         }
 
         /* Sanity check */
-        if (val && (val != 1)) {
+        if (val > 1) {
                 pr_warning("%s: Invalid argument %lld\n", __func__, val);
                 return -EINVAL;
         }
@@ -821,11 +903,11 @@ static int omap_sr_autocomp_store(void *data, u64 val)
 }
 
 DEFINE_SIMPLE_ATTRIBUTE(pm_sr_fops, omap_sr_autocomp_show,
-                omap_sr_autocomp_store, "%llu\n");
+                        omap_sr_autocomp_store, "%llu\n");
 
 static int __init omap_sr_probe(struct platform_device *pdev)
 {
-        struct omap_sr *sr_info = kzalloc(sizeof(struct omap_sr), GFP_KERNEL);
+        struct omap_sr *sr_info;
         struct omap_sr_data *pdata = pdev->dev.platform_data;
         struct resource *mem, *irq;
         struct dentry *nvalue_dir;
@@ -833,12 +915,15 @@ static int __init omap_sr_probe(struct platform_device *pdev)
         int i, ret = 0;
         char *name;
 
+        sr_info = kzalloc(sizeof(struct omap_sr), GFP_KERNEL);
         if (!sr_info) {
                 dev_err(&pdev->dev, "%s: unable to allocate sr_info\n",
                         __func__);
                 return -ENOMEM;
         }
 
+        platform_set_drvdata(pdev, sr_info);
+
         if (!pdata) {
                 dev_err(&pdev->dev, "%s: platform data missing\n", __func__);
                 ret = -EINVAL;
@@ -904,7 +989,7 @@ static int __init omap_sr_probe(struct platform_device *pdev)
         dev_info(&pdev->dev, "%s: SmartReflex driver initialized\n", __func__);
         if (!sr_dbg_dir) {
                 sr_dbg_dir = debugfs_create_dir("smartreflex", NULL);
-                if (!sr_dbg_dir) {
+                if (IS_ERR_OR_NULL(sr_dbg_dir)) {
                         ret = PTR_ERR(sr_dbg_dir);
                         pr_err("%s:sr debugfs dir creation failed(%d)\n",
                                 __func__, ret);
@@ -921,7 +1006,7 @@ static int __init omap_sr_probe(struct platform_device *pdev)
         }
         sr_info->dbg_dir = debugfs_create_dir(name, sr_dbg_dir);
         kfree(name);
-        if (IS_ERR(sr_info->dbg_dir)) {
+        if (IS_ERR_OR_NULL(sr_info->dbg_dir)) {
                 dev_err(&pdev->dev, "%s: Unable to create debugfs directory\n",
                         __func__);
                 ret = PTR_ERR(sr_info->dbg_dir);
@@ -938,7 +1023,7 @@ static int __init omap_sr_probe(struct platform_device *pdev)
                         &sr_info->err_minlimit);
 
         nvalue_dir = debugfs_create_dir("nvalue", sr_info->dbg_dir);
-        if (IS_ERR(nvalue_dir)) {
+        if (IS_ERR_OR_NULL(nvalue_dir)) {
                 dev_err(&pdev->dev, "%s: Unable to create debugfs directory"
                         "for n-values\n", __func__);
                 ret = PTR_ERR(nvalue_dir);
@@ -994,7 +1079,7 @@ static int __devexit omap_sr_remove(struct platform_device *pdev)
         if (IS_ERR(sr_info)) {
                 dev_warn(&pdev->dev, "%s: omap_sr struct not found\n",
                         __func__);
-                return -EINVAL;
+                return PTR_ERR(sr_info);
         }
 
         if (sr_info->autocomp_active)
@@ -1011,8 +1096,32 @@ static int __devexit omap_sr_remove(struct platform_device *pdev)
         return 0;
 }
 
+static void __devexit omap_sr_shutdown(struct platform_device *pdev)
+{
+        struct omap_sr_data *pdata = pdev->dev.platform_data;
+        struct omap_sr *sr_info;
+
+        if (!pdata) {
+                dev_err(&pdev->dev, "%s: platform data missing\n", __func__);
+                return;
+        }
+
+        sr_info = _sr_lookup(pdata->voltdm);
+        if (IS_ERR(sr_info)) {
+                dev_warn(&pdev->dev, "%s: omap_sr struct not found\n",
+                        __func__);
+                return;
+        }
+
+        if (sr_info->autocomp_active)
+                sr_stop_vddautocomp(sr_info);
+
+        return;
+}
+
 static struct platform_driver smartreflex_driver = {
-        .remove         = omap_sr_remove,
+        .remove         = __devexit_p(omap_sr_remove),
+        .shutdown       = __devexit_p(omap_sr_shutdown),
         .driver         = {
                 .name   = "smartreflex",
         },
@@ -1042,12 +1151,12 @@ static int __init sr_init(void)
 
         return 0;
 }
+late_initcall(sr_init);
 
 static void __exit sr_exit(void)
 {
         platform_driver_unregister(&smartreflex_driver);
 }
-late_initcall(sr_init);
 module_exit(sr_exit);
 
 MODULE_DESCRIPTION("OMAP Smartreflex Driver");
diff --git a/arch/arm/mach-omap2/smartreflex.h b/arch/arm/mach-omap2/smartreflex.h
index 5f35b9e2555..5809141171f 100644
--- a/arch/arm/mach-omap2/smartreflex.h
+++ b/arch/arm/mach-omap2/smartreflex.h
@@ -152,6 +152,15 @@ struct omap_sr_pmic_data {
         void (*sr_pmic_init) (void);
 };
 
+/**
+ * struct omap_smartreflex_dev_attr - Smartreflex Device attribute.
+ *
+ * @sensor_voltdm_name:       Name of voltdomain of SR instance
+ */
+struct omap_smartreflex_dev_attr {
+        const char      *sensor_voltdm_name;
+};
+
 #ifdef CONFIG_OMAP_SMARTREFLEX
 /*
  * The smart reflex driver supports CLASS1 CLASS2 and CLASS3 SR.
@@ -231,6 +240,7 @@ void omap_sr_register_pmic(struct omap_sr_pmic_data *pmic_data);
 int sr_enable(struct voltagedomain *voltdm, unsigned long volt);
 void sr_disable(struct voltagedomain *voltdm);
 int sr_configure_errgen(struct voltagedomain *voltdm);
+int sr_disable_errgen(struct voltagedomain *voltdm);
 int sr_configure_minmax(struct voltagedomain *voltdm);
 
 /* API to register the smartreflex class driver with the smartreflex driver */
diff --git a/arch/arm/mach-omap2/sr_device.c b/arch/arm/mach-omap2/sr_device.c
index 9f43fcc05d3..a503e1e8358 100644
--- a/arch/arm/mach-omap2/sr_device.c
+++ b/arch/arm/mach-omap2/sr_device.c
@@ -69,11 +69,12 @@ static void __init sr_set_nvalues(struct omap_volt_data *volt_data,
         sr_data->nvalue_count = count;
 }
 
-static int sr_dev_init(struct omap_hwmod *oh, void *user)
+static int __init sr_dev_init(struct omap_hwmod *oh, void *user)
 {
         struct omap_sr_data *sr_data;
         struct platform_device *pdev;
         struct omap_volt_data *volt_data;
+        struct omap_smartreflex_dev_attr *sr_dev_attr;
         char *name = "smartreflex";
         static int i;
 
@@ -84,9 +85,11 @@ static int sr_dev_init(struct omap_hwmod *oh, void *user)
                 return -ENOMEM;
         }
 
-        if (!oh->vdd_name) {
+        sr_dev_attr = (struct omap_smartreflex_dev_attr *)oh->dev_attr;
+        if (!sr_dev_attr || !sr_dev_attr->sensor_voltdm_name) {
                 pr_err("%s: No voltage domain specified for %s."
-                        "Cannot initialize\n", __func__, oh->name);
+                                "Cannot initialize\n", __func__,
+                                        oh->name);
                 goto exit;
         }
 
@@ -94,10 +97,10 @@ static int sr_dev_init(struct omap_hwmod *oh, void *user)
         sr_data->senn_mod = 0x1;
         sr_data->senp_mod = 0x1;
 
-        sr_data->voltdm = voltdm_lookup(oh->vdd_name);
+        sr_data->voltdm = voltdm_lookup(sr_dev_attr->sensor_voltdm_name);
         if (IS_ERR(sr_data->voltdm)) {
                 pr_err("%s: Unable to get voltage domain pointer for VDD %s\n",
-                        __func__, oh->vdd_name);
+                        __func__, sr_dev_attr->sensor_voltdm_name);
                 goto exit;
         }
 
diff --git a/arch/arm/mach-omap2/sram242x.S b/arch/arm/mach-omap2/sram242x.S
index ff9b9dbcb30..ee0bfcc1410 100644
--- a/arch/arm/mach-omap2/sram242x.S
+++ b/arch/arm/mach-omap2/sram242x.S
@@ -29,10 +29,12 @@
  * These crashes may be intermittent.
  */
 #include <linux/linkage.h>
+
 #include <asm/assembler.h>
-#include <mach/io.h>
+
 #include <mach/hardware.h>
 
+#include "iomap.h"
 #include "prm2xxx_3xxx.h"
 #include "cm2xxx_3xxx.h"
 #include "sdrc.h"
diff --git a/arch/arm/mach-omap2/sram243x.S b/arch/arm/mach-omap2/sram243x.S
index 76730209fa0..d4d39ef0476 100644
--- a/arch/arm/mach-omap2/sram243x.S
+++ b/arch/arm/mach-omap2/sram243x.S
@@ -29,10 +29,12 @@
  * These crashes may be intermittent.
  */
 #include <linux/linkage.h>
+
 #include <asm/assembler.h>
-#include <mach/io.h>
+
 #include <mach/hardware.h>
 
+#include "iomap.h"
 #include "prm2xxx_3xxx.h"
 #include "cm2xxx_3xxx.h"
 #include "sdrc.h"
diff --git a/arch/arm/mach-omap2/sram34xx.S b/arch/arm/mach-omap2/sram34xx.S
index 6f5849aaa7c..df5a21322b0 100644
--- a/arch/arm/mach-omap2/sram34xx.S
+++ b/arch/arm/mach-omap2/sram34xx.S
@@ -26,11 +26,12 @@
  * MA 02111-1307 USA
  */
 #include <linux/linkage.h>
+
 #include <asm/assembler.h>
-#include <mach/hardware.h>
 
-#include <mach/io.h>
+#include <mach/hardware.h>
 
+#include "iomap.h"
 #include "sdrc.h"
 #include "cm2xxx_3xxx.h"
 
diff --git a/arch/arm/mach-omap2/timer-mpu.c b/arch/arm/mach-omap2/timer-mpu.c
deleted file mode 100644
index 31c0ac4cd66..00000000000
--- a/arch/arm/mach-omap2/timer-mpu.c
+++ /dev/null
@@ -1,39 +0,0 @@
-/*
- * The MPU local timer source file. In OMAP4, both cortex-a9 cores have
- * own timer in it's MPU domain. These timers will be driving the
- * linux kernel SMP tick framework when active. These timers are not
- * part of the wake up domain.
- *
- * Copyright (C) 2009 Texas Instruments, Inc.
- *
- * Author:
- *      Santosh Shilimkar <santosh.shilimkar@ti.com>
- *
- * This file is based on arm realview smp platform file.
- * Copyright (C) 2002 ARM Ltd.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#include <linux/init.h>
-#include <linux/smp.h>
-#include <linux/clockchips.h>
-#include <asm/irq.h>
-#include <asm/smp_twd.h>
-#include <asm/localtimer.h>
-
-/*
- * Setup the local clock events for a CPU.
- */
-int __cpuinit local_timer_setup(struct clock_event_device *evt)
-{
-        /* Local timers are not supprted on OMAP4430 ES1.0 */
-        if (omap_rev() == OMAP4430_REV_ES1_0)
-                return -ENXIO;
-
-        evt->irq = OMAP44XX_IRQ_LOCALTIMER;
-        twd_timer_setup(evt);
-        return 0;
-}
-
diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
index 5c9acea9576..c512bac69ec 100644
--- a/arch/arm/mach-omap2/timer.c
+++ b/arch/arm/mach-omap2/timer.c
@@ -39,7 +39,7 @@
 
 #include <asm/mach/time.h>
 #include <plat/dmtimer.h>
-#include <asm/localtimer.h>
+#include <asm/smp_twd.h>
 #include <asm/sched_clock.h>
 #include "common.h"
 #include <plat/omap_hwmod.h>
@@ -324,14 +324,26 @@ OMAP_SYS_TIMER(3_secure)
 #endif
 
 #ifdef CONFIG_ARCH_OMAP4
-static void __init omap4_timer_init(void)
-{
 #ifdef CONFIG_LOCAL_TIMERS
-        twd_base = ioremap(OMAP44XX_LOCAL_TWD_BASE, SZ_256);
-        BUG_ON(!twd_base);
+static DEFINE_TWD_LOCAL_TIMER(twd_local_timer,
+                              OMAP44XX_LOCAL_TWD_BASE,
+                              OMAP44XX_IRQ_LOCALTIMER);
 #endif
+
+static void __init omap4_timer_init(void)
+{
         omap2_gp_clockevent_init(1, OMAP4_CLKEV_SOURCE);
         omap2_gp_clocksource_init(2, OMAP4_MPU_SOURCE);
+#ifdef CONFIG_LOCAL_TIMERS
+        /* Local timers are not supprted on OMAP4430 ES1.0 */
+        if (omap_rev() != OMAP4430_REV_ES1_0) {
+                int err;
+
+                err = twd_local_timer_register(&twd_local_timer);
+                if (err)
+                        pr_err("twd_local_timer_register failed %d\n", err);
+        }
+#endif
 }
 OMAP_SYS_TIMER(4)
 #endif
diff --git a/arch/arm/mach-omap2/vc.c b/arch/arm/mach-omap2/vc.c
index 175b7d86d86..84da34f9a7c 100644
--- a/arch/arm/mach-omap2/vc.c
+++ b/arch/arm/mach-omap2/vc.c
@@ -10,6 +10,7 @@
 #include <linux/kernel.h>
 #include <linux/delay.h>
 #include <linux/init.h>
+#include <linux/bug.h>
 
 #include <plat/cpu.h>
 
diff --git a/arch/arm/mach-omap2/vp.c b/arch/arm/mach-omap2/vp.c
index 0df88820978..f95c1bad9dc 100644
--- a/arch/arm/mach-omap2/vp.c
+++ b/arch/arm/mach-omap2/vp.c
@@ -61,8 +61,8 @@ void __init omap_vp_init(struct voltagedomain *voltdm)
         vddmin = voltdm->pmic->vp_vddmin;
         vddmax = voltdm->pmic->vp_vddmax;
 
-        waittime = ((voltdm->pmic->step_size / voltdm->pmic->slew_rate) *
-                    sys_clk_rate) / 1000;
+        waittime = DIV_ROUND_UP(voltdm->pmic->step_size * sys_clk_rate,
+                                1000 * voltdm->pmic->slew_rate);
         vstepmin = voltdm->pmic->vp_vstepmin;
         vstepmax = voltdm->pmic->vp_vstepmax;
 
diff --git a/arch/arm/mach-orion5x/include/mach/entry-macro.S b/arch/arm/mach-orion5x/include/mach/entry-macro.S
index d658992e540..79eb502a1e6 100644
--- a/arch/arm/mach-orion5x/include/mach/entry-macro.S
+++ b/arch/arm/mach-orion5x/include/mach/entry-macro.S
@@ -10,12 +10,6 @@
 
 #include <mach/bridge-regs.h>
 
-        .macro  disable_fiq
-        .endm
-
-        .macro  arch_ret_to_user, tmp1, tmp2
-        .endm
-
         .macro  get_irqnr_preamble, base, tmp
         ldr     \base, =MAIN_IRQ_CAUSE
         .endm
diff --git a/arch/arm/mach-orion5x/include/mach/system.h b/arch/arm/mach-orion5x/include/mach/system.h
deleted file mode 100644
index 825a2650cef..00000000000
--- a/arch/arm/mach-orion5x/include/mach/system.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/*
- * arch/arm/mach-orion5x/include/mach/system.h
- *
- * Tzachi Perelstein <tzachi@marvell.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#ifndef __ASM_ARCH_SYSTEM_H
-#define __ASM_ARCH_SYSTEM_H
-
-static inline void arch_idle(void)
-{
-        cpu_do_idle();
-}
-
-#endif
diff --git a/arch/arm/mach-orion5x/pci.c b/arch/arm/mach-orion5x/pci.c
index 09a045f0c40..d6a91948e4d 100644
--- a/arch/arm/mach-orion5x/pci.c
+++ b/arch/arm/mach-orion5x/pci.c
@@ -171,13 +171,14 @@ static int __init pcie_setup(struct pci_sys_data *sys)
         /*
          * IORESOURCE_IO
          */
+        sys->io_offset = 0;
         res[0].name = "PCIe I/O Space";
         res[0].flags = IORESOURCE_IO;
         res[0].start = ORION5X_PCIE_IO_BUS_BASE;
         res[0].end = res[0].start + ORION5X_PCIE_IO_SIZE - 1;
         if (request_resource(&ioport_resource, &res[0]))
                 panic("Request PCIe IO resource failed\n");
-        pci_add_resource(&sys->resources, &res[0]);
+        pci_add_resource_offset(&sys->resources, &res[0], sys->io_offset);
 
         /*
          * IORESOURCE_MEM
@@ -188,9 +189,7 @@ static int __init pcie_setup(struct pci_sys_data *sys)
         res[1].end = res[1].start + ORION5X_PCIE_MEM_SIZE - 1;
         if (request_resource(&iomem_resource, &res[1]))
                 panic("Request PCIe Memory resource failed\n");
-        pci_add_resource(&sys->resources, &res[1]);
-
-        sys->io_offset = 0;
+        pci_add_resource_offset(&sys->resources, &res[1], sys->mem_offset);
 
         return 1;
 }
@@ -499,13 +498,14 @@ static int __init pci_setup(struct pci_sys_data *sys)
         /*
          * IORESOURCE_IO
          */
+        sys->io_offset = 0;
         res[0].name = "PCI I/O Space";
         res[0].flags = IORESOURCE_IO;
         res[0].start = ORION5X_PCI_IO_BUS_BASE;
         res[0].end = res[0].start + ORION5X_PCI_IO_SIZE - 1;
         if (request_resource(&ioport_resource, &res[0]))
                 panic("Request PCI IO resource failed\n");
-        pci_add_resource(&sys->resources, &res[0]);
+        pci_add_resource_offset(&sys->resources, &res[0], sys->io_offset);
 
         /*
          * IORESOURCE_MEM
@@ -516,9 +516,7 @@ static int __init pci_setup(struct pci_sys_data *sys)
         res[1].end = res[1].start + ORION5X_PCI_MEM_SIZE - 1;
         if (request_resource(&iomem_resource, &res[1]))
                 panic("Request PCI Memory resource failed\n");
-        pci_add_resource(&sys->resources, &res[1]);
-
-        sys->io_offset = 0;
+        pci_add_resource_offset(&sys->resources, &res[1], sys->mem_offset);
 
         return 1;
 }
diff --git a/arch/arm/mach-picoxcell/include/mach/entry-macro.S b/arch/arm/mach-picoxcell/include/mach/entry-macro.S
deleted file mode 100644
index 9b505ac00be..00000000000
--- a/arch/arm/mach-picoxcell/include/mach/entry-macro.S
+++ /dev/null
@@ -1,16 +0,0 @@
-/*
- * entry-macro.S
- *
- * Copyright (c) 2011 Picochip Ltd., Jamie Iles
- *
- * Low-level IRQ helper macros for picoXcell platforms
- *
- * This file is licensed under  the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-        .macro  disable_fiq
-        .endm
-
-        .macro  arch_ret_to_user, tmp1, tmp2
-        .endm
diff --git a/arch/arm/mach-picoxcell/include/mach/system.h b/arch/arm/mach-picoxcell/include/mach/system.h
deleted file mode 100644
index 1a5d8cb57df..00000000000
--- a/arch/arm/mach-picoxcell/include/mach/system.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * Copyright (c) 2011 Picochip Ltd., Jamie Iles
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-#ifndef __ASM_ARCH_SYSTEM_H
-#define __ASM_ARCH_SYSTEM_H
-
-static inline void arch_idle(void)
-{
-        /*
-         * This should do all the clock switching and wait for interrupt
-         * tricks.
-         */
-        cpu_do_idle();
-}
-
-#endif /* __ASM_ARCH_SYSTEM_H */
diff --git a/arch/arm/mach-pnx4008/include/mach/entry-macro.S b/arch/arm/mach-pnx4008/include/mach/entry-macro.S
index db7eeebf30d..77a55584671 100644
--- a/arch/arm/mach-pnx4008/include/mach/entry-macro.S
+++ b/arch/arm/mach-pnx4008/include/mach/entry-macro.S
@@ -25,15 +25,9 @@
 #define SIC1_BASE_INT   32
 #define SIC2_BASE_INT   64
 
-                .macro  disable_fiq
-                .endm
-
                 .macro  get_irqnr_preamble, base, tmp
                 .endm
 
-                .macro  arch_ret_to_user, tmp1, tmp2
-                .endm
-
                 .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
 /* decode the MIC interrupt numbers */
                 ldr     \base, =IO_ADDRESS(PNX4008_INTCTRLMIC_BASE)
diff --git a/arch/arm/mach-pnx4008/include/mach/system.h b/arch/arm/mach-pnx4008/include/mach/system.h
deleted file mode 100644
index 60cfe718809..00000000000
--- a/arch/arm/mach-pnx4008/include/mach/system.h
+++ /dev/null
@@ -1,29 +0,0 @@
-/*
- * arch/arm/mach-pnx4008/include/mach/system.h
- *
- * Copyright (C) 2003 Philips Semiconductors
- * Copyright (C) 2005 MontaVista Software, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#ifndef __ASM_ARCH_SYSTEM_H
-#define __ASM_ARCH_SYSTEM_H
-
-static void arch_idle(void)
-{
-        cpu_do_idle();
-}
-
-#endif
diff --git a/arch/arm/mach-prima2/include/mach/entry-macro.S b/arch/arm/mach-prima2/include/mach/entry-macro.S
index 1c8a50f102a..86434e7a5be 100644
--- a/arch/arm/mach-prima2/include/mach/entry-macro.S
+++ b/arch/arm/mach-prima2/include/mach/entry-macro.S
@@ -20,10 +20,3 @@
         cmp \irqnr, #0x40                       @ the irq num can't be larger than 0x3f
         movges \irqnr, #0
         .endm
-
-        .macro  disable_fiq
-        .endm
-
-        .macro  arch_ret_to_user, tmp1, tmp2
-        .endm
-
diff --git a/arch/arm/mach-prima2/include/mach/system.h b/arch/arm/mach-prima2/include/mach/system.h
deleted file mode 100644
index 2c7d2a9d0c9..00000000000
--- a/arch/arm/mach-prima2/include/mach/system.h
+++ /dev/null
@@ -1,17 +0,0 @@
-/*
- * arch/arm/mach-prima2/include/mach/system.h
- *
- * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
- *
- * Licensed under GPLv2 or later.
- */
-
-#ifndef __MACH_SYSTEM_H__
-#define __MACH_SYSTEM_H__
-
-static inline void arch_idle(void)
-{
-        cpu_do_idle();
-}
-
-#endif
diff --git a/arch/arm/mach-pxa/devices.c b/arch/arm/mach-pxa/devices.c
index 5bc13121eac..84f2d7015cf 100644
--- a/arch/arm/mach-pxa/devices.c
+++ b/arch/arm/mach-pxa/devices.c
@@ -406,20 +406,17 @@ static struct resource pxa_rtc_resources[] = {
         [1] = {
                 .start  = IRQ_RTC1Hz,
                 .end    = IRQ_RTC1Hz,
+                .name   = "rtc 1Hz",
                 .flags  = IORESOURCE_IRQ,
         },
         [2] = {
                 .start  = IRQ_RTCAlrm,
                 .end    = IRQ_RTCAlrm,
+                .name   = "rtc alarm",
                 .flags  = IORESOURCE_IRQ,
         },
 };
 
-struct platform_device sa1100_device_rtc = {
-        .name           = "sa1100-rtc",
-        .id             = -1,
-};
-
 struct platform_device pxa_device_rtc = {
         .name           = "pxa-rtc",
         .id             = -1,
@@ -427,6 +424,27 @@ struct platform_device pxa_device_rtc = {
         .resource       = pxa_rtc_resources,
 };
 
+static struct resource sa1100_rtc_resources[] = {
+        {
+                .start  = IRQ_RTC1Hz,
+                .end    = IRQ_RTC1Hz,
+                .name   = "rtc 1Hz",
+                .flags  = IORESOURCE_IRQ,
+        }, {
+                .start  = IRQ_RTCAlrm,
+                .end    = IRQ_RTCAlrm,
+                .name   = "rtc alarm",
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+struct platform_device sa1100_device_rtc = {
+        .name           = "sa1100-rtc",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(sa1100_rtc_resources),
+        .resource       = sa1100_rtc_resources,
+};
+
 static struct resource pxa_ac97_resources[] = {
         [0] = {
                 .start  = 0x40500000,
diff --git a/arch/arm/mach-pxa/hx4700.c b/arch/arm/mach-pxa/hx4700.c
index 208eef1c048..3fa929d4a4f 100644
--- a/arch/arm/mach-pxa/hx4700.c
+++ b/arch/arm/mach-pxa/hx4700.c
@@ -28,7 +28,8 @@
 #include <linux/mtd/physmap.h>
 #include <linux/pda_power.h>
 #include <linux/pwm_backlight.h>
-#include <linux/regulator/bq24022.h>
+#include <linux/regulator/driver.h>
+#include <linux/regulator/gpio-regulator.h>
 #include <linux/regulator/machine.h>
 #include <linux/regulator/max1586.h>
 #include <linux/spi/ads7846.h>
@@ -97,9 +98,9 @@ static unsigned long hx4700_pin_config[] __initdata = {
 
         /* BTUART */
         GPIO42_BTUART_RXD,
-        GPIO43_BTUART_TXD,
+        GPIO43_BTUART_TXD_LPM_LOW,
         GPIO44_BTUART_CTS,
-        GPIO45_BTUART_RTS,
+        GPIO45_BTUART_RTS_LPM_LOW,
 
         /* PWM 1 (Backlight) */
         GPIO17_PWM1_OUT,
@@ -245,6 +246,21 @@ static u16 asic3_gpio_config[] = {
         ASIC3_GPIOD15_nPIOW,
 };
 
+static struct asic3_led asic3_leds[ASIC3_NUM_LEDS] = {
+        [0] = {
+                .name = "hx4700:amber",
+                .default_trigger = "ds2760-battery.0-charging-blink-full-solid",
+        },
+        [1] = {
+                .name = "hx4700:green",
+                .default_trigger = "unused",
+        },
+        [2] = {
+                .name = "hx4700:blue",
+                .default_trigger = "hx4700-radio",
+        },
+};
+
 static struct resource asic3_resources[] = {
         /* GPIO part */
         [0] = {
@@ -275,6 +291,7 @@ static struct asic3_platform_data asic3_platform_data = {
         .gpio_config_num = ARRAY_SIZE(asic3_gpio_config),
         .irq_base        = IRQ_BOARD_START,
         .gpio_base       = HX4700_ASIC3_GPIO_BASE,
+        .leds            = asic3_leds,
 };
 
 static struct platform_device asic3 = {
@@ -682,14 +699,34 @@ static struct regulator_init_data bq24022_init_data = {
         .consumer_supplies      = bq24022_consumers,
 };
 
-static struct bq24022_mach_info bq24022_info = {
-        .gpio_nce   = GPIO72_HX4700_BQ24022_nCHARGE_EN,
-        .gpio_iset2 = GPIO96_HX4700_BQ24022_ISET2,
-        .init_data  = &bq24022_init_data,
+static struct gpio bq24022_gpios[] = {
+        { GPIO96_HX4700_BQ24022_ISET2, GPIOF_OUT_INIT_LOW, "bq24022_iset2" },
+};
+
+static struct gpio_regulator_state bq24022_states[] = {
+        { .value = 100000, .gpios = (0 << 0) },
+        { .value = 500000, .gpios = (1 << 0) },
+};
+
+static struct gpio_regulator_config bq24022_info = {
+        .supply_name = "bq24022",
+
+        .enable_gpio = GPIO72_HX4700_BQ24022_nCHARGE_EN,
+        .enable_high = 0,
+        .enabled_at_boot = 0,
+
+        .gpios = bq24022_gpios,
+        .nr_gpios = ARRAY_SIZE(bq24022_gpios),
+
+        .states = bq24022_states,
+        .nr_states = ARRAY_SIZE(bq24022_states),
+
+        .type = REGULATOR_CURRENT,
+        .init_data = &bq24022_init_data,
 };
 
 static struct platform_device bq24022 = {
-        .name = "bq24022",
+        .name = "gpio-regulator",
         .id   = -1,
         .dev  = {
                 .platform_data = &bq24022_info,
@@ -705,10 +742,9 @@ static void hx4700_set_vpp(struct platform_device *pdev, int vpp)
         gpio_set_value(GPIO91_HX4700_FLASH_VPEN, vpp);
 }
 
-static struct resource strataflash_resource = {
-        .start = PXA_CS0_PHYS,
-        .end   = PXA_CS0_PHYS + SZ_128M - 1,
-        .flags = IORESOURCE_MEM,
+static struct resource strataflash_resource[] = {
+        [0] = DEFINE_RES_MEM(PXA_CS0_PHYS, SZ_64M),
+        [1] = DEFINE_RES_MEM(PXA_CS0_PHYS + SZ_64M, SZ_64M),
 };
 
 static struct physmap_flash_data strataflash_data = {
@@ -719,8 +755,8 @@ static struct physmap_flash_data strataflash_data = {
 static struct platform_device strataflash = {
         .name          = "physmap-flash",
         .id            = -1,
-        .resource      = &strataflash_resource,
-        .num_resources = 1,
+        .resource      = strataflash_resource,
+        .num_resources = ARRAY_SIZE(strataflash_resource),
         .dev = {
                 .platform_data = &strataflash_data,
         },
@@ -788,17 +824,6 @@ static struct platform_device audio = {
 
 
 /*
- * PCMCIA
- */
-
-static struct platform_device pcmcia = {
-        .name = "hx4700-pcmcia",
-        .dev  = {
-                .parent = &asic3.dev,
-        },
-};
-
-/*
  * Platform devices
  */
 
@@ -814,7 +839,6 @@ static struct platform_device *devices[] __initdata = {
         &power_supply,
         &strataflash,
         &audio,
-        &pcmcia,
 };
 
 static struct gpio global_gpios[] = {
@@ -830,7 +854,6 @@ static struct gpio global_gpios[] = {
         { GPIO32_HX4700_RS232_ON,         GPIOF_OUT_INIT_HIGH, "RS232_ON" },
         { GPIO71_HX4700_ASIC3_nRESET,     GPIOF_OUT_INIT_HIGH, "ASIC3_nRESET" },
         { GPIO82_HX4700_EUART_RESET,      GPIOF_OUT_INIT_HIGH, "EUART_RESET" },
-        { GPIO105_HX4700_nIR_ON,          GPIOF_OUT_INIT_HIGH, "nIR_EN" },
 };
 
 static void __init hx4700_init(void)
diff --git a/arch/arm/mach-pxa/include/mach/balloon3.h b/arch/arm/mach-pxa/include/mach/balloon3.h
index f02fa1e6ba8..954641e6c8b 100644
--- a/arch/arm/mach-pxa/include/mach/balloon3.h
+++ b/arch/arm/mach-pxa/include/mach/balloon3.h
@@ -174,7 +174,6 @@ enum balloon3_features {
 
 #define BALLOON3_AUX_NIRQ       PXA_GPIO_TO_IRQ(BALLOON3_GPIO_AUX_NIRQ)
 #define BALLOON3_CODEC_IRQ      PXA_GPIO_TO_IRQ(BALLOON3_GPIO_CODEC_IRQ)
-#define BALLOON3_S0_CD_IRQ      PXA_GPIO_TO_IRQ(BALLOON3_GPIO_S0_CD)
 
 #define BALLOON3_NR_IRQS        (IRQ_BOARD_START + 16)
 
diff --git a/arch/arm/mach-pxa/include/mach/entry-macro.S b/arch/arm/mach-pxa/include/mach/entry-macro.S
deleted file mode 100644
index 260c0c17692..00000000000
--- a/arch/arm/mach-pxa/include/mach/entry-macro.S
+++ /dev/null
@@ -1,15 +0,0 @@
-/*
- * arch/arm/mach-pxa/include/mach/entry-macro.S
- *
- * Low-level IRQ helper macros for PXA-based platforms
- *
- * This file is licensed under  the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-                .macro  disable_fiq
-                .endm
-
-                .macro  arch_ret_to_user, tmp1, tmp2
-                .endm
diff --git a/arch/arm/mach-pxa/include/mach/mfp-pxa27x.h b/arch/arm/mach-pxa/include/mach/mfp-pxa27x.h
index ec0f0b0b674..a65867209aa 100644
--- a/arch/arm/mach-pxa/include/mach/mfp-pxa27x.h
+++ b/arch/arm/mach-pxa/include/mach/mfp-pxa27x.h
@@ -158,7 +158,9 @@
 #define GPIO44_BTUART_CTS       MFP_CFG_IN(GPIO44, AF1)
 #define GPIO42_BTUART_RXD       MFP_CFG_IN(GPIO42, AF1)
 #define GPIO45_BTUART_RTS       MFP_CFG_OUT(GPIO45, AF2, DRIVE_HIGH)
+#define GPIO45_BTUART_RTS_LPM_LOW       MFP_CFG_OUT(GPIO45, AF2, DRIVE_LOW)
 #define GPIO43_BTUART_TXD       MFP_CFG_OUT(GPIO43, AF2, DRIVE_HIGH)
+#define GPIO43_BTUART_TXD_LPM_LOW       MFP_CFG_OUT(GPIO43, AF2, DRIVE_LOW)
 
 /* STUART */
 #define GPIO46_STUART_RXD       MFP_CFG_IN(GPIO46, AF2)
diff --git a/arch/arm/mach-pxa/include/mach/system.h b/arch/arm/mach-pxa/include/mach/system.h
deleted file mode 100644
index c5afacd3cc0..00000000000
--- a/arch/arm/mach-pxa/include/mach/system.h
+++ /dev/null
@@ -1,15 +0,0 @@
-/*
- * arch/arm/mach-pxa/include/mach/system.h
- *
- * Author:      Nicolas Pitre
- * Created:     Jun 15, 2001
- * Copyright:   MontaVista Software Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-static inline void arch_idle(void)
-{
-        cpu_do_idle();
-}
diff --git a/arch/arm/mach-pxa/magician.c b/arch/arm/mach-pxa/magician.c
index 3d6baf91396..5e26f3e93fd 100644
--- a/arch/arm/mach-pxa/magician.c
+++ b/arch/arm/mach-pxa/magician.c
@@ -25,7 +25,8 @@
 #include <linux/mtd/physmap.h>
 #include <linux/pda_power.h>
 #include <linux/pwm_backlight.h>
-#include <linux/regulator/bq24022.h>
+#include <linux/regulator/driver.h>
+#include <linux/regulator/gpio-regulator.h>
 #include <linux/regulator/machine.h>
 #include <linux/usb/gpio_vbus.h>
 #include <linux/i2c/pxa-i2c.h>
@@ -596,14 +597,34 @@ static struct regulator_init_data bq24022_init_data = {
         .consumer_supplies      = bq24022_consumers,
 };
 
-static struct bq24022_mach_info bq24022_info = {
-        .gpio_nce   = GPIO30_MAGICIAN_BQ24022_nCHARGE_EN,
-        .gpio_iset2 = EGPIO_MAGICIAN_BQ24022_ISET2,
-        .init_data  = &bq24022_init_data,
+static struct gpio bq24022_gpios[] = {
+        { EGPIO_MAGICIAN_BQ24022_ISET2, GPIOF_OUT_INIT_LOW, "bq24022_iset2" },
+};
+
+static struct gpio_regulator_state bq24022_states[] = {
+        { .value = 100000, .gpios = (0 << 0) },
+        { .value = 500000, .gpios = (1 << 0) },
+};
+
+static struct gpio_regulator_config bq24022_info = {
+        .supply_name = "bq24022",
+
+        .enable_gpio = GPIO30_MAGICIAN_BQ24022_nCHARGE_EN,
+        .enable_high = 0,
+        .enabled_at_boot = 0,
+
+        .gpios = bq24022_gpios,
+        .nr_gpios = ARRAY_SIZE(bq24022_gpios),
+
+        .states = bq24022_states,
+        .nr_states = ARRAY_SIZE(bq24022_states),
+
+        .type = REGULATOR_CURRENT,
+        .init_data = &bq24022_init_data,
 };
 
 static struct platform_device bq24022 = {
-        .name = "bq24022",
+        .name = "gpio-regulator",
         .id   = -1,
         .dev  = {
                 .platform_data = &bq24022_info,
diff --git a/arch/arm/mach-pxa/pxa3xx.c b/arch/arm/mach-pxa/pxa3xx.c
index 3918a672238..1570d457fea 100644
--- a/arch/arm/mach-pxa/pxa3xx.c
+++ b/arch/arm/mach-pxa/pxa3xx.c
@@ -89,6 +89,7 @@ static struct clk_lookup pxa3xx_clkregs[] = {
         INIT_CLKREG(&clk_pxa3xx_mmc2, "pxa2xx-mci.1", NULL),
         INIT_CLKREG(&clk_pxa3xx_smemc, "pxa2xx-pcmcia", NULL),
         INIT_CLKREG(&clk_pxa3xx_gpio, "pxa-gpio", NULL),
+        INIT_CLKREG(&clk_dummy, "sa1100-rtc", NULL),
 };
 
 #ifdef CONFIG_PM
diff --git a/arch/arm/mach-pxa/pxa95x.c b/arch/arm/mach-pxa/pxa95x.c
index 5ce434b95e8..47601f80e6e 100644
--- a/arch/arm/mach-pxa/pxa95x.c
+++ b/arch/arm/mach-pxa/pxa95x.c
@@ -231,6 +231,7 @@ static struct clk_lookup pxa95x_clkregs[] = {
         INIT_CLKREG(&clk_pxa95x_pwm0, "pxa27x-pwm.0", NULL),
         INIT_CLKREG(&clk_pxa95x_pwm1, "pxa27x-pwm.1", NULL),
         INIT_CLKREG(&clk_pxa95x_gpio, "pxa-gpio", NULL),
+        INIT_CLKREG(&clk_dummy, "sa1100-rtc", NULL),
 };
 
 void __init pxa95x_init_irq(void)
diff --git a/arch/arm/mach-realview/core.h b/arch/arm/mach-realview/core.h
index 735b57aaf2d..f8f2c0ac4c0 100644
--- a/arch/arm/mach-realview/core.h
+++ b/arch/arm/mach-realview/core.h
@@ -28,21 +28,11 @@
 #include <asm/setup.h>
 #include <asm/leds.h>
 
-#define AMBA_DEVICE(name,busid,base,plat)                       \
-static struct amba_device name##_device = {                     \
-        .dev            = {                                     \
-                .coherent_dma_mask = ~0,                        \
-                .init_name = busid,                             \
-                .platform_data = plat,                          \
-        },                                                      \
-        .res            = {                                     \
-                .start  = REALVIEW_##base##_BASE,               \
-                .end    = (REALVIEW_##base##_BASE) + SZ_4K - 1, \
-                .flags  = IORESOURCE_MEM,                       \
-        },                                                      \
-        .dma_mask       = ~0,                                   \
-        .irq            = base##_IRQ,                           \
-}
+#define APB_DEVICE(name, busid, base, plat)                     \
+static AMBA_APB_DEVICE(name, busid, 0, REALVIEW_##base##_BASE, base##_IRQ, plat)
+
+#define AHB_DEVICE(name, busid, base, plat)                     \
+static AMBA_AHB_DEVICE(name, busid, 0, REALVIEW_##base##_BASE, base##_IRQ, plat)
 
 struct machine_desc;
 
diff --git a/arch/arm/mach-realview/include/mach/entry-macro.S b/arch/arm/mach-realview/include/mach/entry-macro.S
deleted file mode 100644
index e8a5179c265..00000000000
--- a/arch/arm/mach-realview/include/mach/entry-macro.S
+++ /dev/null
@@ -1,16 +0,0 @@
-/*
- * arch/arm/mach-realview/include/mach/entry-macro.S
- *
- * Low-level IRQ helper macros for RealView platforms
- *
- * This file is licensed under  the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-                .macro  disable_fiq
-                .endm
-
-                .macro  arch_ret_to_user, tmp1, tmp2
-                .endm
-
diff --git a/arch/arm/mach-realview/include/mach/irqs-eb.h b/arch/arm/mach-realview/include/mach/irqs-eb.h
index 204d5378f30..d6b5073692d 100644
--- a/arch/arm/mach-realview/include/mach/irqs-eb.h
+++ b/arch/arm/mach-realview/include/mach/irqs-eb.h
@@ -96,16 +96,19 @@
 #define IRQ_EB11MP_L220_SLAVE   (IRQ_EB_GIC_START + 30)
 #define IRQ_EB11MP_L220_DECODE  (IRQ_EB_GIC_START + 31)
 
-#define IRQ_EB11MP_UART2        -1
-#define IRQ_EB11MP_UART3        -1
-#define IRQ_EB11MP_CLCD         -1
-#define IRQ_EB11MP_DMA          -1
-#define IRQ_EB11MP_WDOG         -1
-#define IRQ_EB11MP_GPIO0        -1
-#define IRQ_EB11MP_GPIO1        -1
-#define IRQ_EB11MP_GPIO2        -1
-#define IRQ_EB11MP_SCI          -1
-#define IRQ_EB11MP_SSP          -1
+/*
+ * The 11MPcore tile leaves the following unconnected.
+ */
+#define IRQ_EB11MP_UART2        0
+#define IRQ_EB11MP_UART3        0
+#define IRQ_EB11MP_CLCD         0
+#define IRQ_EB11MP_DMA          0
+#define IRQ_EB11MP_WDOG         0
+#define IRQ_EB11MP_GPIO0        0
+#define IRQ_EB11MP_GPIO1        0
+#define IRQ_EB11MP_GPIO2        0
+#define IRQ_EB11MP_SCI          0
+#define IRQ_EB11MP_SSP          0
 
 #define NR_GIC_EB11MP           2
 
diff --git a/arch/arm/mach-realview/include/mach/irqs-pb1176.h b/arch/arm/mach-realview/include/mach/irqs-pb1176.h
index 5c3c625e3e0..708f84156f2 100644
--- a/arch/arm/mach-realview/include/mach/irqs-pb1176.h
+++ b/arch/arm/mach-realview/include/mach/irqs-pb1176.h
@@ -40,6 +40,7 @@
 #define IRQ_DC1176_L2CC         (IRQ_DC1176_GIC_START + 13)
 #define IRQ_DC1176_RTC          (IRQ_DC1176_GIC_START + 14)
 #define IRQ_DC1176_CLCD         (IRQ_DC1176_GIC_START + 15)     /* CLCD controller */
+#define IRQ_DC1176_GPIO0        (IRQ_DC1176_GIC_START + 16)
 #define IRQ_DC1176_SSP          (IRQ_DC1176_GIC_START + 17)     /* SSP port */
 #define IRQ_DC1176_UART0        (IRQ_DC1176_GIC_START + 18)     /* UART 0 on development chip */
 #define IRQ_DC1176_UART1        (IRQ_DC1176_GIC_START + 19)     /* UART 1 on development chip */
@@ -73,7 +74,6 @@
 #define IRQ_PB1176_DMAC         (IRQ_PB1176_GIC_START + 24)     /* DMA controller */
 #define IRQ_PB1176_RTC          (IRQ_PB1176_GIC_START + 25)     /* Real Time Clock */
 
-#define IRQ_PB1176_GPIO0        -1
 #define IRQ_PB1176_SCTL         -1
 
 #define NR_GIC_PB1176           2
diff --git a/arch/arm/mach-realview/include/mach/system.h b/arch/arm/mach-realview/include/mach/system.h
deleted file mode 100644
index 471b671159c..00000000000
--- a/arch/arm/mach-realview/include/mach/system.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/*
- *  arch/arm/mach-realview/include/mach/system.h
- *
- *  Copyright (C) 2003 ARM Limited
- *  Copyright (C) 2000 Deep Blue Solutions Ltd
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#ifndef __ASM_ARCH_SYSTEM_H
-#define __ASM_ARCH_SYSTEM_H
-
-static inline void arch_idle(void)
-{
-        /*
-         * This should do all the clock switching
-         * and wait for interrupt tricks
-         */
-        cpu_do_idle();
-}
-
-#endif
diff --git a/arch/arm/mach-realview/realview_eb.c b/arch/arm/mach-realview/realview_eb.c
index 9578145f2df..baf382c5e77 100644
--- a/arch/arm/mach-realview/realview_eb.c
+++ b/arch/arm/mach-realview/realview_eb.c
@@ -36,7 +36,7 @@
 #include <asm/pgtable.h>
 #include <asm/hardware/gic.h>
 #include <asm/hardware/cache-l2x0.h>
-#include <asm/localtimer.h>
+#include <asm/smp_twd.h>
 
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
@@ -135,63 +135,63 @@ static struct pl022_ssp_controller ssp0_plat_data = {
 /*
  * These devices are connected via the core APB bridge
  */
-#define GPIO2_IRQ       { IRQ_EB_GPIO2, NO_IRQ }
-#define GPIO3_IRQ       { IRQ_EB_GPIO3, NO_IRQ }
+#define GPIO2_IRQ       { IRQ_EB_GPIO2 }
+#define GPIO3_IRQ       { IRQ_EB_GPIO3 }
 
-#define AACI_IRQ        { IRQ_EB_AACI, NO_IRQ }
+#define AACI_IRQ        { IRQ_EB_AACI }
 #define MMCI0_IRQ       { IRQ_EB_MMCI0A, IRQ_EB_MMCI0B }
-#define KMI0_IRQ        { IRQ_EB_KMI0, NO_IRQ }
-#define KMI1_IRQ        { IRQ_EB_KMI1, NO_IRQ }
+#define KMI0_IRQ        { IRQ_EB_KMI0 }
+#define KMI1_IRQ        { IRQ_EB_KMI1 }
 
 /*
  * These devices are connected directly to the multi-layer AHB switch
  */
-#define EB_SMC_IRQ      { NO_IRQ, NO_IRQ }
-#define MPMC_IRQ        { NO_IRQ, NO_IRQ }
-#define EB_CLCD_IRQ     { IRQ_EB_CLCD, NO_IRQ }
-#define DMAC_IRQ        { IRQ_EB_DMA, NO_IRQ }
+#define EB_SMC_IRQ      { }
+#define MPMC_IRQ        { }
+#define EB_CLCD_IRQ     { IRQ_EB_CLCD }
+#define DMAC_IRQ        { IRQ_EB_DMA }
 
 /*
  * These devices are connected via the core APB bridge
  */
-#define SCTL_IRQ        { NO_IRQ, NO_IRQ }
-#define EB_WATCHDOG_IRQ { IRQ_EB_WDOG, NO_IRQ }
-#define EB_GPIO0_IRQ    { IRQ_EB_GPIO0, NO_IRQ }
-#define GPIO1_IRQ       { IRQ_EB_GPIO1, NO_IRQ }
-#define EB_RTC_IRQ      { IRQ_EB_RTC, NO_IRQ }
+#define SCTL_IRQ        { }
+#define EB_WATCHDOG_IRQ { IRQ_EB_WDOG }
+#define EB_GPIO0_IRQ    { IRQ_EB_GPIO0 }
+#define GPIO1_IRQ       { IRQ_EB_GPIO1 }
+#define EB_RTC_IRQ      { IRQ_EB_RTC }
 
 /*
  * These devices are connected via the DMA APB bridge
  */
-#define SCI_IRQ         { IRQ_EB_SCI, NO_IRQ }
-#define EB_UART0_IRQ    { IRQ_EB_UART0, NO_IRQ }
-#define EB_UART1_IRQ    { IRQ_EB_UART1, NO_IRQ }
-#define EB_UART2_IRQ    { IRQ_EB_UART2, NO_IRQ }
-#define EB_UART3_IRQ    { IRQ_EB_UART3, NO_IRQ }
-#define EB_SSP_IRQ      { IRQ_EB_SSP, NO_IRQ }
+#define SCI_IRQ         { IRQ_EB_SCI }
+#define EB_UART0_IRQ    { IRQ_EB_UART0 }
+#define EB_UART1_IRQ    { IRQ_EB_UART1 }
+#define EB_UART2_IRQ    { IRQ_EB_UART2 }
+#define EB_UART3_IRQ    { IRQ_EB_UART3 }
+#define EB_SSP_IRQ      { IRQ_EB_SSP }
 
 /* FPGA Primecells */
-AMBA_DEVICE(aaci,  "fpga:aaci",  AACI,     NULL);
-AMBA_DEVICE(mmc0,  "fpga:mmc0",  MMCI0,    &realview_mmc0_plat_data);
-AMBA_DEVICE(kmi0,  "fpga:kmi0",  KMI0,     NULL);
-AMBA_DEVICE(kmi1,  "fpga:kmi1",  KMI1,     NULL);
-AMBA_DEVICE(uart3, "fpga:uart3", EB_UART3, NULL);
+APB_DEVICE(aaci,  "fpga:aaci",  AACI,     NULL);
+APB_DEVICE(mmc0,  "fpga:mmc0",  MMCI0,    &realview_mmc0_plat_data);
+APB_DEVICE(kmi0,  "fpga:kmi0",  KMI0,     NULL);
+APB_DEVICE(kmi1,  "fpga:kmi1",  KMI1,     NULL);
+APB_DEVICE(uart3, "fpga:uart3", EB_UART3, NULL);
 
 /* DevChip Primecells */
-AMBA_DEVICE(smc,   "dev:smc",   EB_SMC,   NULL);
-AMBA_DEVICE(clcd,  "dev:clcd",  EB_CLCD,  &clcd_plat_data);
-AMBA_DEVICE(dmac,  "dev:dmac",  DMAC,     NULL);
-AMBA_DEVICE(sctl,  "dev:sctl",  SCTL,     NULL);
-AMBA_DEVICE(wdog,  "dev:wdog",  EB_WATCHDOG, NULL);
-AMBA_DEVICE(gpio0, "dev:gpio0", EB_GPIO0, &gpio0_plat_data);
-AMBA_DEVICE(gpio1, "dev:gpio1", GPIO1,    &gpio1_plat_data);
-AMBA_DEVICE(gpio2, "dev:gpio2", GPIO2,    &gpio2_plat_data);
-AMBA_DEVICE(rtc,   "dev:rtc",   EB_RTC,   NULL);
-AMBA_DEVICE(sci0,  "dev:sci0",  SCI,      NULL);
-AMBA_DEVICE(uart0, "dev:uart0", EB_UART0, NULL);
-AMBA_DEVICE(uart1, "dev:uart1", EB_UART1, NULL);
-AMBA_DEVICE(uart2, "dev:uart2", EB_UART2, NULL);
-AMBA_DEVICE(ssp0,  "dev:ssp0",  EB_SSP,   &ssp0_plat_data);
+AHB_DEVICE(smc,   "dev:smc",   EB_SMC,   NULL);
+AHB_DEVICE(clcd,  "dev:clcd",  EB_CLCD,  &clcd_plat_data);
+AHB_DEVICE(dmac,  "dev:dmac",  DMAC,     NULL);
+AHB_DEVICE(sctl,  "dev:sctl",  SCTL,     NULL);
+APB_DEVICE(wdog,  "dev:wdog",  EB_WATCHDOG, NULL);
+APB_DEVICE(gpio0, "dev:gpio0", EB_GPIO0, &gpio0_plat_data);
+APB_DEVICE(gpio1, "dev:gpio1", GPIO1,    &gpio1_plat_data);
+APB_DEVICE(gpio2, "dev:gpio2", GPIO2,    &gpio2_plat_data);
+APB_DEVICE(rtc,   "dev:rtc",   EB_RTC,   NULL);
+APB_DEVICE(sci0,  "dev:sci0",  SCI,      NULL);
+APB_DEVICE(uart0, "dev:uart0", EB_UART0, NULL);
+APB_DEVICE(uart1, "dev:uart1", EB_UART1, NULL);
+APB_DEVICE(uart2, "dev:uart2", EB_UART2, NULL);
+APB_DEVICE(ssp0,  "dev:ssp0",  EB_SSP,   &ssp0_plat_data);
 
 static struct amba_device *amba_devs[] __initdata = {
         &dmac_device,
@@ -383,6 +383,23 @@ static void realview_eb11mp_fixup(void)
         realview_eb_isp1761_resources[1].end    = IRQ_EB11MP_USB;
 }
 
+#ifdef CONFIG_HAVE_ARM_TWD
+static DEFINE_TWD_LOCAL_TIMER(twd_local_timer,
+                              REALVIEW_EB11MP_TWD_BASE,
+                              IRQ_LOCALTIMER);
+
+static void __init realview_eb_twd_init(void)
+{
+        if (core_tile_eb11mp() || core_tile_a9mp()) {
+                int err = twd_local_timer_register(&twd_local_timer);
+                if (err)
+                        pr_err("twd_local_timer_register failed %d\n", err);
+        }
+}
+#else
+#define realview_eb_twd_init()  do { } while(0)
+#endif
+
 static void __init realview_eb_timer_init(void)
 {
         unsigned int timer_irq;
@@ -392,15 +409,13 @@ static void __init realview_eb_timer_init(void)
         timer2_va_base = __io_address(REALVIEW_EB_TIMER2_3_BASE);
         timer3_va_base = __io_address(REALVIEW_EB_TIMER2_3_BASE) + 0x20;
 
-        if (core_tile_eb11mp() || core_tile_a9mp()) {
-#ifdef CONFIG_LOCAL_TIMERS
-                twd_base = __io_address(REALVIEW_EB11MP_TWD_BASE);
-#endif
+        if (core_tile_eb11mp() || core_tile_a9mp())
                 timer_irq = IRQ_EB11MP_TIMER0_1;
-        } else
+        else
                 timer_irq = IRQ_EB_TIMER0_1;
 
         realview_timer_init(timer_irq);
+        realview_eb_twd_init();
 }
 
 static struct sys_timer realview_eb_timer = {
diff --git a/arch/arm/mach-realview/realview_pb1176.c b/arch/arm/mach-realview/realview_pb1176.c
index e4abe94fb11..b1d7cafa1a6 100644
--- a/arch/arm/mach-realview/realview_pb1176.c
+++ b/arch/arm/mach-realview/realview_pb1176.c
@@ -132,50 +132,50 @@ static struct pl022_ssp_controller ssp0_plat_data = {
 /*
  * RealView PB1176 AMBA devices
  */
-#define GPIO2_IRQ       { IRQ_PB1176_GPIO2, NO_IRQ }
-#define GPIO3_IRQ       { IRQ_PB1176_GPIO3, NO_IRQ }
-#define AACI_IRQ        { IRQ_PB1176_AACI, NO_IRQ }
+#define GPIO2_IRQ       { IRQ_PB1176_GPIO2 }
+#define GPIO3_IRQ       { IRQ_PB1176_GPIO3 }
+#define AACI_IRQ        { IRQ_PB1176_AACI }
 #define MMCI0_IRQ       { IRQ_PB1176_MMCI0A, IRQ_PB1176_MMCI0B }
-#define KMI0_IRQ        { IRQ_PB1176_KMI0, NO_IRQ }
-#define KMI1_IRQ        { IRQ_PB1176_KMI1, NO_IRQ }
-#define PB1176_SMC_IRQ  { NO_IRQ, NO_IRQ }
-#define MPMC_IRQ        { NO_IRQ, NO_IRQ }
-#define PB1176_CLCD_IRQ { IRQ_DC1176_CLCD, NO_IRQ }
-#define SCTL_IRQ        { NO_IRQ, NO_IRQ }
-#define PB1176_WATCHDOG_IRQ     { IRQ_DC1176_WATCHDOG, NO_IRQ }
-#define PB1176_GPIO0_IRQ        { IRQ_PB1176_GPIO0, NO_IRQ }
-#define GPIO1_IRQ       { IRQ_PB1176_GPIO1, NO_IRQ }
-#define PB1176_RTC_IRQ  { IRQ_DC1176_RTC, NO_IRQ }
-#define SCI_IRQ         { IRQ_PB1176_SCI, NO_IRQ }
-#define PB1176_UART0_IRQ        { IRQ_DC1176_UART0, NO_IRQ }
-#define PB1176_UART1_IRQ        { IRQ_DC1176_UART1, NO_IRQ }
-#define PB1176_UART2_IRQ        { IRQ_DC1176_UART2, NO_IRQ }
-#define PB1176_UART3_IRQ        { IRQ_DC1176_UART3, NO_IRQ }
-#define PB1176_UART4_IRQ        { IRQ_PB1176_UART4, NO_IRQ }
-#define PB1176_SSP_IRQ          { IRQ_DC1176_SSP, NO_IRQ }
+#define KMI0_IRQ        { IRQ_PB1176_KMI0 }
+#define KMI1_IRQ        { IRQ_PB1176_KMI1 }
+#define PB1176_SMC_IRQ  { }
+#define MPMC_IRQ        { }
+#define PB1176_CLCD_IRQ { IRQ_DC1176_CLCD }
+#define SCTL_IRQ        { }
+#define PB1176_WATCHDOG_IRQ     { IRQ_DC1176_WATCHDOG }
+#define PB1176_GPIO0_IRQ        { IRQ_DC1176_GPIO0 }
+#define GPIO1_IRQ       { IRQ_PB1176_GPIO1 }
+#define PB1176_RTC_IRQ  { IRQ_DC1176_RTC }
+#define SCI_IRQ         { IRQ_PB1176_SCI }
+#define PB1176_UART0_IRQ        { IRQ_DC1176_UART0 }
+#define PB1176_UART1_IRQ        { IRQ_DC1176_UART1 }
+#define PB1176_UART2_IRQ        { IRQ_DC1176_UART2 }
+#define PB1176_UART3_IRQ        { IRQ_DC1176_UART3 }
+#define PB1176_UART4_IRQ        { IRQ_PB1176_UART4 }
+#define PB1176_SSP_IRQ          { IRQ_DC1176_SSP }
 
 /* FPGA Primecells */
-AMBA_DEVICE(aaci,       "fpga:aaci",    AACI,           NULL);
-AMBA_DEVICE(mmc0,       "fpga:mmc0",    MMCI0,          &realview_mmc0_plat_data);
-AMBA_DEVICE(kmi0,       "fpga:kmi0",    KMI0,           NULL);
-AMBA_DEVICE(kmi1,       "fpga:kmi1",    KMI1,           NULL);
-AMBA_DEVICE(uart4,      "fpga:uart4",   PB1176_UART4,   NULL);
+APB_DEVICE(aaci,        "fpga:aaci",    AACI,           NULL);
+APB_DEVICE(mmc0,        "fpga:mmc0",    MMCI0,          &realview_mmc0_plat_data);
+APB_DEVICE(kmi0,        "fpga:kmi0",    KMI0,           NULL);
+APB_DEVICE(kmi1,        "fpga:kmi1",    KMI1,           NULL);
+APB_DEVICE(uart4,       "fpga:uart4",   PB1176_UART4,   NULL);
 
 /* DevChip Primecells */
-AMBA_DEVICE(smc,        "dev:smc",      PB1176_SMC,     NULL);
-AMBA_DEVICE(sctl,       "dev:sctl",     SCTL,           NULL);
-AMBA_DEVICE(wdog,       "dev:wdog",     PB1176_WATCHDOG,        NULL);
-AMBA_DEVICE(gpio0,      "dev:gpio0",    PB1176_GPIO0,   &gpio0_plat_data);
-AMBA_DEVICE(gpio1,      "dev:gpio1",    GPIO1,          &gpio1_plat_data);
-AMBA_DEVICE(gpio2,      "dev:gpio2",    GPIO2,          &gpio2_plat_data);
-AMBA_DEVICE(rtc,        "dev:rtc",      PB1176_RTC,     NULL);
-AMBA_DEVICE(sci0,       "dev:sci0",     SCI,            NULL);
-AMBA_DEVICE(uart0,      "dev:uart0",    PB1176_UART0,   NULL);
-AMBA_DEVICE(uart1,      "dev:uart1",    PB1176_UART1,   NULL);
-AMBA_DEVICE(uart2,      "dev:uart2",    PB1176_UART2,   NULL);
-AMBA_DEVICE(uart3,      "dev:uart3",    PB1176_UART3,   NULL);
-AMBA_DEVICE(ssp0,       "dev:ssp0",     PB1176_SSP,     &ssp0_plat_data);
-AMBA_DEVICE(clcd,       "dev:clcd",     PB1176_CLCD,    &clcd_plat_data);
+AHB_DEVICE(smc,         "dev:smc",      PB1176_SMC,     NULL);
+AHB_DEVICE(sctl,        "dev:sctl",     SCTL,           NULL);
+APB_DEVICE(wdog,        "dev:wdog",     PB1176_WATCHDOG,        NULL);
+APB_DEVICE(gpio0,       "dev:gpio0",    PB1176_GPIO0,   &gpio0_plat_data);
+APB_DEVICE(gpio1,       "dev:gpio1",    GPIO1,          &gpio1_plat_data);
+APB_DEVICE(gpio2,       "dev:gpio2",    GPIO2,          &gpio2_plat_data);
+APB_DEVICE(rtc,         "dev:rtc",      PB1176_RTC,     NULL);
+APB_DEVICE(sci0,        "dev:sci0",     SCI,            NULL);
+APB_DEVICE(uart0,       "dev:uart0",    PB1176_UART0,   NULL);
+APB_DEVICE(uart1,       "dev:uart1",    PB1176_UART1,   NULL);
+APB_DEVICE(uart2,       "dev:uart2",    PB1176_UART2,   NULL);
+APB_DEVICE(uart3,       "dev:uart3",    PB1176_UART3,   NULL);
+APB_DEVICE(ssp0,        "dev:ssp0",     PB1176_SSP,     &ssp0_plat_data);
+AHB_DEVICE(clcd,        "dev:clcd",     PB1176_CLCD,    &clcd_plat_data);
 
 static struct amba_device *amba_devs[] __initdata = {
         &uart0_device,
diff --git a/arch/arm/mach-realview/realview_pb11mp.c b/arch/arm/mach-realview/realview_pb11mp.c
index 2147335f66f..a98c536e332 100644
--- a/arch/arm/mach-realview/realview_pb11mp.c
+++ b/arch/arm/mach-realview/realview_pb11mp.c
@@ -36,7 +36,7 @@
 #include <asm/pgtable.h>
 #include <asm/hardware/gic.h>
 #include <asm/hardware/cache-l2x0.h>
-#include <asm/localtimer.h>
+#include <asm/smp_twd.h>
 
 #include <asm/mach/arch.h>
 #include <asm/mach/flash.h>
@@ -127,52 +127,52 @@ static struct pl022_ssp_controller ssp0_plat_data = {
  * RealView PB11MPCore AMBA devices
  */
 
-#define GPIO2_IRQ               { IRQ_PB11MP_GPIO2, NO_IRQ }
-#define GPIO3_IRQ               { IRQ_PB11MP_GPIO3, NO_IRQ }
-#define AACI_IRQ                { IRQ_TC11MP_AACI, NO_IRQ }
+#define GPIO2_IRQ               { IRQ_PB11MP_GPIO2 }
+#define GPIO3_IRQ               { IRQ_PB11MP_GPIO3 }
+#define AACI_IRQ                { IRQ_TC11MP_AACI }
 #define MMCI0_IRQ               { IRQ_TC11MP_MMCI0A, IRQ_TC11MP_MMCI0B }
-#define KMI0_IRQ                { IRQ_TC11MP_KMI0, NO_IRQ }
-#define KMI1_IRQ                { IRQ_TC11MP_KMI1, NO_IRQ }
-#define PB11MP_SMC_IRQ          { NO_IRQ, NO_IRQ }
-#define MPMC_IRQ                { NO_IRQ, NO_IRQ }
-#define PB11MP_CLCD_IRQ         { IRQ_PB11MP_CLCD, NO_IRQ }
-#define DMAC_IRQ                { IRQ_PB11MP_DMAC, NO_IRQ }
-#define SCTL_IRQ                { NO_IRQ, NO_IRQ }
-#define PB11MP_WATCHDOG_IRQ     { IRQ_PB11MP_WATCHDOG, NO_IRQ }
-#define PB11MP_GPIO0_IRQ        { IRQ_PB11MP_GPIO0, NO_IRQ }
-#define GPIO1_IRQ               { IRQ_PB11MP_GPIO1, NO_IRQ }
-#define PB11MP_RTC_IRQ          { IRQ_TC11MP_RTC, NO_IRQ }
-#define SCI_IRQ                 { IRQ_PB11MP_SCI, NO_IRQ }
-#define PB11MP_UART0_IRQ        { IRQ_TC11MP_UART0, NO_IRQ }
-#define PB11MP_UART1_IRQ        { IRQ_TC11MP_UART1, NO_IRQ }
-#define PB11MP_UART2_IRQ        { IRQ_PB11MP_UART2, NO_IRQ }
-#define PB11MP_UART3_IRQ        { IRQ_PB11MP_UART3, NO_IRQ }
-#define PB11MP_SSP_IRQ          { IRQ_PB11MP_SSP, NO_IRQ }
+#define KMI0_IRQ                { IRQ_TC11MP_KMI0 }
+#define KMI1_IRQ                { IRQ_TC11MP_KMI1 }
+#define PB11MP_SMC_IRQ          { }
+#define MPMC_IRQ                { }
+#define PB11MP_CLCD_IRQ         { IRQ_PB11MP_CLCD }
+#define DMAC_IRQ                { IRQ_PB11MP_DMAC }
+#define SCTL_IRQ                { }
+#define PB11MP_WATCHDOG_IRQ     { IRQ_PB11MP_WATCHDOG }
+#define PB11MP_GPIO0_IRQ        { IRQ_PB11MP_GPIO0 }
+#define GPIO1_IRQ               { IRQ_PB11MP_GPIO1 }
+#define PB11MP_RTC_IRQ          { IRQ_TC11MP_RTC }
+#define SCI_IRQ                 { IRQ_PB11MP_SCI }
+#define PB11MP_UART0_IRQ        { IRQ_TC11MP_UART0 }
+#define PB11MP_UART1_IRQ        { IRQ_TC11MP_UART1 }
+#define PB11MP_UART2_IRQ        { IRQ_PB11MP_UART2 }
+#define PB11MP_UART3_IRQ        { IRQ_PB11MP_UART3 }
+#define PB11MP_SSP_IRQ          { IRQ_PB11MP_SSP }
 
 /* FPGA Primecells */
-AMBA_DEVICE(aaci,       "fpga:aaci",    AACI,           NULL);
-AMBA_DEVICE(mmc0,       "fpga:mmc0",    MMCI0,          &realview_mmc0_plat_data);
-AMBA_DEVICE(kmi0,       "fpga:kmi0",    KMI0,           NULL);
-AMBA_DEVICE(kmi1,       "fpga:kmi1",    KMI1,           NULL);
-AMBA_DEVICE(uart3,      "fpga:uart3",   PB11MP_UART3,   NULL);
+APB_DEVICE(aaci,        "fpga:aaci",    AACI,           NULL);
+APB_DEVICE(mmc0,        "fpga:mmc0",    MMCI0,          &realview_mmc0_plat_data);
+APB_DEVICE(kmi0,        "fpga:kmi0",    KMI0,           NULL);
+APB_DEVICE(kmi1,        "fpga:kmi1",    KMI1,           NULL);
+APB_DEVICE(uart3,       "fpga:uart3",   PB11MP_UART3,   NULL);
 
 /* DevChip Primecells */
-AMBA_DEVICE(smc,        "dev:smc",      PB11MP_SMC,     NULL);
-AMBA_DEVICE(sctl,       "dev:sctl",     SCTL,           NULL);
-AMBA_DEVICE(wdog,       "dev:wdog",     PB11MP_WATCHDOG, NULL);
-AMBA_DEVICE(gpio0,      "dev:gpio0",    PB11MP_GPIO0,   &gpio0_plat_data);
-AMBA_DEVICE(gpio1,      "dev:gpio1",    GPIO1,          &gpio1_plat_data);
-AMBA_DEVICE(gpio2,      "dev:gpio2",    GPIO2,          &gpio2_plat_data);
-AMBA_DEVICE(rtc,        "dev:rtc",      PB11MP_RTC,     NULL);
-AMBA_DEVICE(sci0,       "dev:sci0",     SCI,            NULL);
-AMBA_DEVICE(uart0,      "dev:uart0",    PB11MP_UART0,   NULL);
-AMBA_DEVICE(uart1,      "dev:uart1",    PB11MP_UART1,   NULL);
-AMBA_DEVICE(uart2,      "dev:uart2",    PB11MP_UART2,   NULL);
-AMBA_DEVICE(ssp0,       "dev:ssp0",     PB11MP_SSP,     &ssp0_plat_data);
+AHB_DEVICE(smc,         "dev:smc",      PB11MP_SMC,     NULL);
+AHB_DEVICE(sctl,        "dev:sctl",     SCTL,           NULL);
+APB_DEVICE(wdog,        "dev:wdog",     PB11MP_WATCHDOG, NULL);
+APB_DEVICE(gpio0,       "dev:gpio0",    PB11MP_GPIO0,   &gpio0_plat_data);
+APB_DEVICE(gpio1,       "dev:gpio1",    GPIO1,          &gpio1_plat_data);
+APB_DEVICE(gpio2,       "dev:gpio2",    GPIO2,          &gpio2_plat_data);
+APB_DEVICE(rtc,         "dev:rtc",      PB11MP_RTC,     NULL);
+APB_DEVICE(sci0,        "dev:sci0",     SCI,            NULL);
+APB_DEVICE(uart0,       "dev:uart0",    PB11MP_UART0,   NULL);
+APB_DEVICE(uart1,       "dev:uart1",    PB11MP_UART1,   NULL);
+APB_DEVICE(uart2,       "dev:uart2",    PB11MP_UART2,   NULL);
+APB_DEVICE(ssp0,        "dev:ssp0",     PB11MP_SSP,     &ssp0_plat_data);
 
 /* Primecells on the NEC ISSP chip */
-AMBA_DEVICE(clcd,       "issp:clcd",    PB11MP_CLCD,    &clcd_plat_data);
-AMBA_DEVICE(dmac,       "issp:dmac",    DMAC,           NULL);
+AHB_DEVICE(clcd,        "issp:clcd",    PB11MP_CLCD,    &clcd_plat_data);
+AHB_DEVICE(dmac,        "issp:dmac",    DMAC,           NULL);
 
 static struct amba_device *amba_devs[] __initdata = {
         &dmac_device,
@@ -290,6 +290,21 @@ static void __init gic_init_irq(void)
         gic_cascade_irq(1, IRQ_TC11MP_PB_IRQ1);
 }
 
+#ifdef CONFIG_HAVE_ARM_TWD
+static DEFINE_TWD_LOCAL_TIMER(twd_local_timer,
+                              REALVIEW_TC11MP_TWD_BASE,
+                              IRQ_LOCALTIMER);
+
+static void __init realview_pb11mp_twd_init(void)
+{
+        int err = twd_local_timer_register(&twd_local_timer);
+        if (err)
+                pr_err("twd_local_timer_register failed %d\n", err);
+}
+#else
+#define realview_pb11mp_twd_init()      do {} while(0)
+#endif
+
 static void __init realview_pb11mp_timer_init(void)
 {
         timer0_va_base = __io_address(REALVIEW_PB11MP_TIMER0_1_BASE);
@@ -297,10 +312,8 @@ static void __init realview_pb11mp_timer_init(void)
         timer2_va_base = __io_address(REALVIEW_PB11MP_TIMER2_3_BASE);
         timer3_va_base = __io_address(REALVIEW_PB11MP_TIMER2_3_BASE) + 0x20;
 
-#ifdef CONFIG_LOCAL_TIMERS
-        twd_base = __io_address(REALVIEW_TC11MP_TWD_BASE);
-#endif
         realview_timer_init(IRQ_TC11MP_TIMER0_1);
+        realview_pb11mp_twd_init();
 }
 
 static struct sys_timer realview_pb11mp_timer = {
diff --git a/arch/arm/mach-realview/realview_pba8.c b/arch/arm/mach-realview/realview_pba8.c
index 25b2e59296f..59650174e6e 100644
--- a/arch/arm/mach-realview/realview_pba8.c
+++ b/arch/arm/mach-realview/realview_pba8.c
@@ -122,52 +122,52 @@ static struct pl022_ssp_controller ssp0_plat_data = {
  * RealView PBA8Core AMBA devices
  */
 
-#define GPIO2_IRQ               { IRQ_PBA8_GPIO2, NO_IRQ }
-#define GPIO3_IRQ               { IRQ_PBA8_GPIO3, NO_IRQ }
-#define AACI_IRQ                { IRQ_PBA8_AACI, NO_IRQ }
+#define GPIO2_IRQ               { IRQ_PBA8_GPIO2 }
+#define GPIO3_IRQ               { IRQ_PBA8_GPIO3 }
+#define AACI_IRQ                { IRQ_PBA8_AACI }
 #define MMCI0_IRQ               { IRQ_PBA8_MMCI0A, IRQ_PBA8_MMCI0B }
-#define KMI0_IRQ                { IRQ_PBA8_KMI0, NO_IRQ }
-#define KMI1_IRQ                { IRQ_PBA8_KMI1, NO_IRQ }
-#define PBA8_SMC_IRQ            { NO_IRQ, NO_IRQ }
-#define MPMC_IRQ                { NO_IRQ, NO_IRQ }
-#define PBA8_CLCD_IRQ           { IRQ_PBA8_CLCD, NO_IRQ }
-#define DMAC_IRQ                { IRQ_PBA8_DMAC, NO_IRQ }
-#define SCTL_IRQ                { NO_IRQ, NO_IRQ }
-#define PBA8_WATCHDOG_IRQ       { IRQ_PBA8_WATCHDOG, NO_IRQ }
-#define PBA8_GPIO0_IRQ          { IRQ_PBA8_GPIO0, NO_IRQ }
-#define GPIO1_IRQ               { IRQ_PBA8_GPIO1, NO_IRQ }
-#define PBA8_RTC_IRQ            { IRQ_PBA8_RTC, NO_IRQ }
-#define SCI_IRQ                 { IRQ_PBA8_SCI, NO_IRQ }
-#define PBA8_UART0_IRQ          { IRQ_PBA8_UART0, NO_IRQ }
-#define PBA8_UART1_IRQ          { IRQ_PBA8_UART1, NO_IRQ }
-#define PBA8_UART2_IRQ          { IRQ_PBA8_UART2, NO_IRQ }
-#define PBA8_UART3_IRQ          { IRQ_PBA8_UART3, NO_IRQ }
-#define PBA8_SSP_IRQ            { IRQ_PBA8_SSP, NO_IRQ }
+#define KMI0_IRQ                { IRQ_PBA8_KMI0 }
+#define KMI1_IRQ                { IRQ_PBA8_KMI1 }
+#define PBA8_SMC_IRQ            { }
+#define MPMC_IRQ                { }
+#define PBA8_CLCD_IRQ           { IRQ_PBA8_CLCD }
+#define DMAC_IRQ                { IRQ_PBA8_DMAC }
+#define SCTL_IRQ                { }
+#define PBA8_WATCHDOG_IRQ       { IRQ_PBA8_WATCHDOG }
+#define PBA8_GPIO0_IRQ          { IRQ_PBA8_GPIO0 }
+#define GPIO1_IRQ               { IRQ_PBA8_GPIO1 }
+#define PBA8_RTC_IRQ            { IRQ_PBA8_RTC }
+#define SCI_IRQ                 { IRQ_PBA8_SCI }
+#define PBA8_UART0_IRQ          { IRQ_PBA8_UART0 }
+#define PBA8_UART1_IRQ          { IRQ_PBA8_UART1 }
+#define PBA8_UART2_IRQ          { IRQ_PBA8_UART2 }
+#define PBA8_UART3_IRQ          { IRQ_PBA8_UART3 }
+#define PBA8_SSP_IRQ            { IRQ_PBA8_SSP }
 
 /* FPGA Primecells */
-AMBA_DEVICE(aaci,       "fpga:aaci",    AACI,           NULL);
-AMBA_DEVICE(mmc0,       "fpga:mmc0",    MMCI0,          &realview_mmc0_plat_data);
-AMBA_DEVICE(kmi0,       "fpga:kmi0",    KMI0,           NULL);
-AMBA_DEVICE(kmi1,       "fpga:kmi1",    KMI1,           NULL);
-AMBA_DEVICE(uart3,      "fpga:uart3",   PBA8_UART3,     NULL);
+APB_DEVICE(aaci,        "fpga:aaci",    AACI,           NULL);
+APB_DEVICE(mmc0,        "fpga:mmc0",    MMCI0,          &realview_mmc0_plat_data);
+APB_DEVICE(kmi0,        "fpga:kmi0",    KMI0,           NULL);
+APB_DEVICE(kmi1,        "fpga:kmi1",    KMI1,           NULL);
+APB_DEVICE(uart3,       "fpga:uart3",   PBA8_UART3,     NULL);
 
 /* DevChip Primecells */
-AMBA_DEVICE(smc,        "dev:smc",      PBA8_SMC,       NULL);
-AMBA_DEVICE(sctl,       "dev:sctl",     SCTL,           NULL);
-AMBA_DEVICE(wdog,       "dev:wdog",     PBA8_WATCHDOG, NULL);
-AMBA_DEVICE(gpio0,      "dev:gpio0",    PBA8_GPIO0,     &gpio0_plat_data);
-AMBA_DEVICE(gpio1,      "dev:gpio1",    GPIO1,          &gpio1_plat_data);
-AMBA_DEVICE(gpio2,      "dev:gpio2",    GPIO2,          &gpio2_plat_data);
-AMBA_DEVICE(rtc,        "dev:rtc",      PBA8_RTC,       NULL);
-AMBA_DEVICE(sci0,       "dev:sci0",     SCI,            NULL);
-AMBA_DEVICE(uart0,      "dev:uart0",    PBA8_UART0,     NULL);
-AMBA_DEVICE(uart1,      "dev:uart1",    PBA8_UART1,     NULL);
-AMBA_DEVICE(uart2,      "dev:uart2",    PBA8_UART2,     NULL);
-AMBA_DEVICE(ssp0,       "dev:ssp0",     PBA8_SSP,       &ssp0_plat_data);
+AHB_DEVICE(smc,         "dev:smc",      PBA8_SMC,       NULL);
+AHB_DEVICE(sctl,        "dev:sctl",     SCTL,           NULL);
+APB_DEVICE(wdog,        "dev:wdog",     PBA8_WATCHDOG, NULL);
+APB_DEVICE(gpio0,       "dev:gpio0",    PBA8_GPIO0,     &gpio0_plat_data);
+APB_DEVICE(gpio1,       "dev:gpio1",    GPIO1,          &gpio1_plat_data);
+APB_DEVICE(gpio2,       "dev:gpio2",    GPIO2,          &gpio2_plat_data);
+APB_DEVICE(rtc,         "dev:rtc",      PBA8_RTC,       NULL);
+APB_DEVICE(sci0,        "dev:sci0",     SCI,            NULL);
+APB_DEVICE(uart0,       "dev:uart0",    PBA8_UART0,     NULL);
+APB_DEVICE(uart1,       "dev:uart1",    PBA8_UART1,     NULL);
+APB_DEVICE(uart2,       "dev:uart2",    PBA8_UART2,     NULL);
+APB_DEVICE(ssp0,        "dev:ssp0",     PBA8_SSP,       &ssp0_plat_data);
 
 /* Primecells on the NEC ISSP chip */
-AMBA_DEVICE(clcd,       "issp:clcd",    PBA8_CLCD,      &clcd_plat_data);
-AMBA_DEVICE(dmac,       "issp:dmac",    DMAC,           NULL);
+AHB_DEVICE(clcd,        "issp:clcd",    PBA8_CLCD,      &clcd_plat_data);
+AHB_DEVICE(dmac,        "issp:dmac",    DMAC,           NULL);
 
 static struct amba_device *amba_devs[] __initdata = {
         &dmac_device,
diff --git a/arch/arm/mach-realview/realview_pbx.c b/arch/arm/mach-realview/realview_pbx.c
index ac715645b86..3f2f605624e 100644
--- a/arch/arm/mach-realview/realview_pbx.c
+++ b/arch/arm/mach-realview/realview_pbx.c
@@ -144,52 +144,52 @@ static struct pl022_ssp_controller ssp0_plat_data = {
  * RealView PBXCore AMBA devices
  */
 
-#define GPIO2_IRQ               { IRQ_PBX_GPIO2, NO_IRQ }
-#define GPIO3_IRQ               { IRQ_PBX_GPIO3, NO_IRQ }
-#define AACI_IRQ                { IRQ_PBX_AACI, NO_IRQ }
+#define GPIO2_IRQ               { IRQ_PBX_GPIO2 }
+#define GPIO3_IRQ               { IRQ_PBX_GPIO3 }
+#define AACI_IRQ                { IRQ_PBX_AACI }
 #define MMCI0_IRQ               { IRQ_PBX_MMCI0A, IRQ_PBX_MMCI0B }
-#define KMI0_IRQ                { IRQ_PBX_KMI0, NO_IRQ }
-#define KMI1_IRQ                { IRQ_PBX_KMI1, NO_IRQ }
-#define PBX_SMC_IRQ             { NO_IRQ, NO_IRQ }
-#define MPMC_IRQ                { NO_IRQ, NO_IRQ }
-#define PBX_CLCD_IRQ            { IRQ_PBX_CLCD, NO_IRQ }
-#define DMAC_IRQ                { IRQ_PBX_DMAC, NO_IRQ }
-#define SCTL_IRQ                { NO_IRQ, NO_IRQ }
-#define PBX_WATCHDOG_IRQ        { IRQ_PBX_WATCHDOG, NO_IRQ }
-#define PBX_GPIO0_IRQ           { IRQ_PBX_GPIO0, NO_IRQ }
-#define GPIO1_IRQ               { IRQ_PBX_GPIO1, NO_IRQ }
-#define PBX_RTC_IRQ             { IRQ_PBX_RTC, NO_IRQ }
-#define SCI_IRQ                 { IRQ_PBX_SCI, NO_IRQ }
-#define PBX_UART0_IRQ           { IRQ_PBX_UART0, NO_IRQ }
-#define PBX_UART1_IRQ           { IRQ_PBX_UART1, NO_IRQ }
-#define PBX_UART2_IRQ           { IRQ_PBX_UART2, NO_IRQ }
-#define PBX_UART3_IRQ           { IRQ_PBX_UART3, NO_IRQ }
-#define PBX_SSP_IRQ             { IRQ_PBX_SSP, NO_IRQ }
+#define KMI0_IRQ                { IRQ_PBX_KMI0 }
+#define KMI1_IRQ                { IRQ_PBX_KMI1 }
+#define PBX_SMC_IRQ             { }
+#define MPMC_IRQ                { }
+#define PBX_CLCD_IRQ            { IRQ_PBX_CLCD }
+#define DMAC_IRQ                { IRQ_PBX_DMAC }
+#define SCTL_IRQ                { }
+#define PBX_WATCHDOG_IRQ        { IRQ_PBX_WATCHDOG }
+#define PBX_GPIO0_IRQ           { IRQ_PBX_GPIO0 }
+#define GPIO1_IRQ               { IRQ_PBX_GPIO1 }
+#define PBX_RTC_IRQ             { IRQ_PBX_RTC }
+#define SCI_IRQ                 { IRQ_PBX_SCI }
+#define PBX_UART0_IRQ           { IRQ_PBX_UART0 }
+#define PBX_UART1_IRQ           { IRQ_PBX_UART1 }
+#define PBX_UART2_IRQ           { IRQ_PBX_UART2 }
+#define PBX_UART3_IRQ           { IRQ_PBX_UART3 }
+#define PBX_SSP_IRQ             { IRQ_PBX_SSP }
 
 /* FPGA Primecells */
-AMBA_DEVICE(aaci,       "fpga:aaci",    AACI,           NULL);
-AMBA_DEVICE(mmc0,       "fpga:mmc0",    MMCI0,          &realview_mmc0_plat_data);
-AMBA_DEVICE(kmi0,       "fpga:kmi0",    KMI0,           NULL);
-AMBA_DEVICE(kmi1,       "fpga:kmi1",    KMI1,           NULL);
-AMBA_DEVICE(uart3,      "fpga:uart3",   PBX_UART3,      NULL);
+APB_DEVICE(aaci,        "fpga:aaci",    AACI,           NULL);
+APB_DEVICE(mmc0,        "fpga:mmc0",    MMCI0,          &realview_mmc0_plat_data);
+APB_DEVICE(kmi0,        "fpga:kmi0",    KMI0,           NULL);
+APB_DEVICE(kmi1,        "fpga:kmi1",    KMI1,           NULL);
+APB_DEVICE(uart3,       "fpga:uart3",   PBX_UART3,      NULL);
 
 /* DevChip Primecells */
-AMBA_DEVICE(smc,        "dev:smc",      PBX_SMC,        NULL);
-AMBA_DEVICE(sctl,       "dev:sctl",     SCTL,           NULL);
-AMBA_DEVICE(wdog,       "dev:wdog",     PBX_WATCHDOG,   NULL);
-AMBA_DEVICE(gpio0,      "dev:gpio0",    PBX_GPIO0,      &gpio0_plat_data);
-AMBA_DEVICE(gpio1,      "dev:gpio1",    GPIO1,          &gpio1_plat_data);
-AMBA_DEVICE(gpio2,      "dev:gpio2",    GPIO2,          &gpio2_plat_data);
-AMBA_DEVICE(rtc,        "dev:rtc",      PBX_RTC,        NULL);
-AMBA_DEVICE(sci0,       "dev:sci0",     SCI,            NULL);
-AMBA_DEVICE(uart0,      "dev:uart0",    PBX_UART0,      NULL);
-AMBA_DEVICE(uart1,      "dev:uart1",    PBX_UART1,      NULL);
-AMBA_DEVICE(uart2,      "dev:uart2",    PBX_UART2,      NULL);
-AMBA_DEVICE(ssp0,       "dev:ssp0",     PBX_SSP,        &ssp0_plat_data);
+AHB_DEVICE(smc, "dev:smc",      PBX_SMC,        NULL);
+AHB_DEVICE(sctl,        "dev:sctl",     SCTL,           NULL);
+APB_DEVICE(wdog,        "dev:wdog",     PBX_WATCHDOG,   NULL);
+APB_DEVICE(gpio0,       "dev:gpio0",    PBX_GPIO0,      &gpio0_plat_data);
+APB_DEVICE(gpio1,       "dev:gpio1",    GPIO1,          &gpio1_plat_data);
+APB_DEVICE(gpio2,       "dev:gpio2",    GPIO2,          &gpio2_plat_data);
+APB_DEVICE(rtc,         "dev:rtc",      PBX_RTC,        NULL);
+APB_DEVICE(sci0,        "dev:sci0",     SCI,            NULL);
+APB_DEVICE(uart0,       "dev:uart0",    PBX_UART0,      NULL);
+APB_DEVICE(uart1,       "dev:uart1",    PBX_UART1,      NULL);
+APB_DEVICE(uart2,       "dev:uart2",    PBX_UART2,      NULL);
+APB_DEVICE(ssp0,        "dev:ssp0",     PBX_SSP,        &ssp0_plat_data);
 
 /* Primecells on the NEC ISSP chip */
-AMBA_DEVICE(clcd,       "issp:clcd",    PBX_CLCD,       &clcd_plat_data);
-AMBA_DEVICE(dmac,       "issp:dmac",    DMAC,           NULL);
+AHB_DEVICE(clcd,        "issp:clcd",    PBX_CLCD,       &clcd_plat_data);
+AHB_DEVICE(dmac,        "issp:dmac",    DMAC,           NULL);
 
 static struct amba_device *amba_devs[] __initdata = {
         &dmac_device,
@@ -298,6 +298,21 @@ static void __init gic_init_irq(void)
         }
 }
 
+#ifdef CONFIG_HAVE_ARM_TWD
+static DEFINE_TWD_LOCAL_TIMER(twd_local_timer,
+                              REALVIEW_PBX_TILE_TWD_BASE,
+                              IRQ_LOCALTIMER);
+
+static void __init realview_pbx_twd_init(void)
+{
+        int err = twd_local_timer_register(&twd_local_timer);
+        if (err)
+                pr_err("twd_local_timer_register failed %d\n", err);
+}
+#else
+#define realview_pbx_twd_init() do { } while(0)
+#endif
+
 static void __init realview_pbx_timer_init(void)
 {
         timer0_va_base = __io_address(REALVIEW_PBX_TIMER0_1_BASE);
@@ -305,11 +320,8 @@ static void __init realview_pbx_timer_init(void)
         timer2_va_base = __io_address(REALVIEW_PBX_TIMER2_3_BASE);
         timer3_va_base = __io_address(REALVIEW_PBX_TIMER2_3_BASE) + 0x20;
 
-#ifdef CONFIG_LOCAL_TIMERS
-        if (core_tile_pbx11mp() || core_tile_pbxa9mp())
-                twd_base = __io_address(REALVIEW_PBX_TILE_TWD_BASE);
-#endif
         realview_timer_init(IRQ_PBX_TIMER0_1);
+        realview_pbx_twd_init();
 }
 
 static struct sys_timer realview_pbx_timer = {
diff --git a/arch/arm/mach-rpc/Makefile b/arch/arm/mach-rpc/Makefile
index aa77bc9efbb..dfa405c0cfd 100644
--- a/arch/arm/mach-rpc/Makefile
+++ b/arch/arm/mach-rpc/Makefile
@@ -4,7 +4,7 @@
 
 # Object file lists.
 
-obj-y                   := dma.o irq.o riscpc.o
+obj-y                   := dma.o fiq.o irq.o riscpc.o
 obj-m                   :=
 obj-n                   :=
 obj-                    :=
diff --git a/arch/arm/mach-rpc/fiq.S b/arch/arm/mach-rpc/fiq.S
new file mode 100644
index 00000000000..48ddd57db16
--- /dev/null
+++ b/arch/arm/mach-rpc/fiq.S
@@ -0,0 +1,16 @@
+#include <linux/linkage.h>
+#include <asm/assembler.h>
+#include <mach/hardware.h>
+#include <mach/entry-macro.S>
+
+        .text
+
+        .global rpc_default_fiq_end
+ENTRY(rpc_default_fiq_start)
+        mov     r12, #ioc_base_high
+        .if     ioc_base_low
+        orr     r12, r12, #ioc_base_low
+        .endif
+        strb    r12, [r12, #0x38]       @ Disable FIQ register
+        subs    pc, lr, #4
+rpc_default_fiq_end:
diff --git a/arch/arm/mach-rpc/include/mach/entry-macro.S b/arch/arm/mach-rpc/include/mach/entry-macro.S
index 4e7e5414409..7178368d706 100644
--- a/arch/arm/mach-rpc/include/mach/entry-macro.S
+++ b/arch/arm/mach-rpc/include/mach/entry-macro.S
@@ -10,7 +10,3 @@
         orr     \base, \base, #ioc_base_low
         .endif
         .endm
-
-        .macro  arch_ret_to_user, tmp1, tmp2
-        .endm
-
diff --git a/arch/arm/mach-rpc/include/mach/system.h b/arch/arm/mach-rpc/include/mach/system.h
deleted file mode 100644
index 359bab94b6a..00000000000
--- a/arch/arm/mach-rpc/include/mach/system.h
+++ /dev/null
@@ -1,13 +0,0 @@
-/*
- *  arch/arm/mach-rpc/include/mach/system.h
- *
- *  Copyright (C) 1996-1999 Russell King.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-static inline void arch_idle(void)
-{
-        cpu_do_idle();
-}
diff --git a/arch/arm/mach-rpc/irq.c b/arch/arm/mach-rpc/irq.c
index 2e1b5309fba..cf0e669eaf1 100644
--- a/arch/arm/mach-rpc/irq.c
+++ b/arch/arm/mach-rpc/irq.c
@@ -5,6 +5,7 @@
 #include <asm/mach/irq.h>
 #include <asm/hardware/iomd.h>
 #include <asm/irq.h>
+#include <asm/fiq.h>
 
 static void iomd_ack_irq_a(struct irq_data *d)
 {
@@ -112,6 +113,8 @@ static struct irq_chip iomd_fiq_chip = {
         .irq_unmask     = iomd_unmask_irq_fiq,
 };
 
+extern unsigned char rpc_default_fiq_start, rpc_default_fiq_end;
+
 void __init rpc_init_irq(void)
 {
         unsigned int irq, flags;
@@ -121,6 +124,9 @@ void __init rpc_init_irq(void)
         iomd_writeb(0, IOMD_FIQMASK);
         iomd_writeb(0, IOMD_DMAMASK);
 
+        set_fiq_handler(&rpc_default_fiq_start,
+                &rpc_default_fiq_end - &rpc_default_fiq_start);
+
         for (irq = 0; irq < NR_IRQS; irq++) {
                 flags = IRQF_VALID;
 
diff --git a/arch/arm/mach-s3c2410/Kconfig b/arch/arm/mach-s3c2410/Kconfig
index 5261a7ed099..68d89cb96af 100644
--- a/arch/arm/mach-s3c2410/Kconfig
+++ b/arch/arm/mach-s3c2410/Kconfig
@@ -2,42 +2,6 @@
 #
 # Licensed under GPLv2
 
-config CPU_S3C2410
-        bool
-        depends on ARCH_S3C2410
-        select CPU_ARM920T
-        select S3C2410_CLOCK
-        select CPU_LLSERIAL_S3C2410
-        select S3C2410_PM if PM
-        select S3C2410_CPUFREQ if CPU_FREQ_S3C24XX
-        help
-          Support for S3C2410 and S3C2410A family from the S3C24XX line
-          of Samsung Mobile CPUs.
-
-config CPU_S3C2410_DMA
-        bool
-        depends on S3C2410_DMA && (CPU_S3C2410 || CPU_S3C2442)
-        default y if CPU_S3C2410 || CPU_S3C2442
-        help
-          DMA device selection for S3C2410 and compatible CPUs
-
-config S3C2410_PM
-        bool
-        help
-          Power Management code common to S3C2410 and better
-
-config SIMTEC_NOR
-        bool
-        help
-          Internal node to specify machine has simtec NOR mapping
-
-config MACH_BAST_IDE
-        bool
-        select HAVE_PATA_PLATFORM
-        help
-          Internal node for machines with an BAST style IDE
-          interface
-
 # cpu frequency scaling support
 
 config S3C2410_CPUFREQ
@@ -54,121 +18,3 @@ config S3C2410_PLLTABLE
         help
           Select the PLL table for the S3C2410
 
-menu "S3C2410 Machines"
-
-config ARCH_SMDK2410
-        bool "SMDK2410/A9M2410"
-        select CPU_S3C2410
-        select MACH_SMDK
-        help
-           Say Y here if you are using the SMDK2410 or the derived module A9M2410
-           <http://www.fsforth.de>
-
-config ARCH_H1940
-        bool "IPAQ H1940"
-        select CPU_S3C2410
-        select PM_H1940 if PM
-        select S3C_DEV_USB_HOST
-        select S3C_DEV_NAND
-        select S3C2410_SETUP_TS
-        help
-          Say Y here if you are using the HP IPAQ H1940
-
-config H1940BT
-        tristate "Control the state of H1940 bluetooth chip"
-        depends on ARCH_H1940
-        select RFKILL
-        help
-          This is a simple driver that is able to control
-          the state of built in bluetooth chip on h1940.
-
-config PM_H1940
-        bool
-        help
-          Internal node for H1940 and related PM
-
-config MACH_N30
-        bool "Acer N30 family"
-        select CPU_S3C2410
-        select MACH_N35
-        select S3C_DEV_USB_HOST
-        select S3C_DEV_NAND
-        help
-          Say Y here if you want suppt for the Acer N30, Acer N35,
-          Navman PiN570, Yakumo AlphaX or Airis NC05 PDAs.
-
-config MACH_N35
-        bool
-        help
-          Internal node in order to enable support for Acer N35 if Acer N30 is
-          selected.
-
-config ARCH_BAST
-        bool "Simtec Electronics BAST (EB2410ITX)"
-        select CPU_S3C2410
-        select S3C2410_IOTIMING if S3C2410_CPUFREQ
-        select PM_SIMTEC if PM
-        select SIMTEC_NOR
-        select MACH_BAST_IDE
-        select S3C24XX_DCLK
-        select ISA
-        select S3C_DEV_HWMON
-        select S3C_DEV_USB_HOST
-        select S3C_DEV_NAND
-        help
-          Say Y here if you are using the Simtec Electronics EB2410ITX
-          development board (also known as BAST)
-
-config MACH_OTOM
-        bool "NexVision OTOM Board"
-        select CPU_S3C2410
-        select S3C_DEV_USB_HOST
-        select S3C_DEV_NAND
-        help
-          Say Y here if you are using the Nex Vision OTOM board
-
-config MACH_AML_M5900
-        bool "AML M5900 Series"
-        select CPU_S3C2410
-        select PM_SIMTEC if PM
-        select S3C_DEV_USB_HOST
-        help
-           Say Y here if you are using the American Microsystems M5900 Series
-           <http://www.amltd.com>
-
-config BAST_PC104_IRQ
-        bool "BAST PC104 IRQ support"
-        depends on ARCH_BAST
-        default y
-        help
-          Say Y here to enable the PC104 IRQ routing on the
-          Simtec BAST (EB2410ITX)
-
-config MACH_TCT_HAMMER
-        bool "TCT Hammer Board"
-        select CPU_S3C2410
-        select S3C_DEV_USB_HOST
-        help
-           Say Y here if you are using the TinCanTools Hammer Board
-           <http://www.tincantools.com>
-
-config MACH_VR1000
-        bool "Thorcom VR1000"
-        select PM_SIMTEC if PM
-        select S3C24XX_DCLK
-        select SIMTEC_NOR
-        select MACH_BAST_IDE
-        select CPU_S3C2410
-        select S3C_DEV_USB_HOST
-        help
-          Say Y here if you are using the Thorcom VR1000 board.
-
-config MACH_QT2410
-        bool "QT2410"
-        select CPU_S3C2410
-        select S3C_DEV_USB_HOST
-        select S3C_DEV_NAND
-        help
-           Say Y here if you are using the Armzone QT2410
-
-endmenu
diff --git a/arch/arm/mach-s3c2410/Makefile b/arch/arm/mach-s3c2410/Makefile
index 782fd81144e..6b9a316e004 100644
--- a/arch/arm/mach-s3c2410/Makefile
+++ b/arch/arm/mach-s3c2410/Makefile
@@ -9,32 +9,6 @@ obj-m				:=
 obj-n                           :=
 obj-                            :=
 
-obj-$(CONFIG_CPU_S3C2410)       += s3c2410.o
-obj-$(CONFIG_CPU_S3C2410_DMA)   += dma.o
-obj-$(CONFIG_CPU_S3C2410_DMA)   += dma.o
-obj-$(CONFIG_S3C2410_PM)        += pm.o sleep.o
 obj-$(CONFIG_S3C2410_CPUFREQ)   += cpu-freq.o
 obj-$(CONFIG_S3C2410_PLLTABLE)  += pll.o
 
-# Machine support
-
-obj-$(CONFIG_ARCH_SMDK2410)     += mach-smdk2410.o
-obj-$(CONFIG_ARCH_H1940)        += mach-h1940.o
-obj-$(CONFIG_H1940BT)           += h1940-bluetooth.o
-obj-$(CONFIG_PM_H1940)          += pm-h1940.o
-obj-$(CONFIG_MACH_N30)          += mach-n30.o
-obj-$(CONFIG_ARCH_BAST)         += mach-bast.o usb-simtec.o
-obj-$(CONFIG_MACH_OTOM)         += mach-otom.o
-obj-$(CONFIG_MACH_AML_M5900)    += mach-amlm5900.o
-obj-$(CONFIG_BAST_PC104_IRQ)    += bast-irq.o
-obj-$(CONFIG_MACH_TCT_HAMMER)   += mach-tct_hammer.o
-obj-$(CONFIG_MACH_VR1000)       += mach-vr1000.o usb-simtec.o
-obj-$(CONFIG_MACH_QT2410)       += mach-qt2410.o
-
-# Common bits of machine support
-
-obj-$(CONFIG_SIMTEC_NOR)        += nor-simtec.o
-
-# machine additions
-
-obj-$(CONFIG_MACH_BAST_IDE)     += bast-ide.o
diff --git a/arch/arm/mach-s3c2410/common.h b/arch/arm/mach-s3c2410/common.h
deleted file mode 100644
index f65dc806296..00000000000
--- a/arch/arm/mach-s3c2410/common.h
+++ /dev/null
@@ -1,17 +0,0 @@
-/*
- * Copyright (c) 2011 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com
- *
- * Common Header for S3C2410 machines
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef __ARCH_ARM_MACH_S3C2410_COMMON_H
-#define __ARCH_ARM_MACH_S3C2410_COMMON_H
-
-void s3c2410_restart(char mode, const char *cmd);
-
-#endif /* __ARCH_ARM_MACH_S3C2410_COMMON_H */
diff --git a/arch/arm/mach-s3c2410/include/mach/spi.h b/arch/arm/mach-s3c2410/include/mach/spi.h
deleted file mode 100644
index 4d9588373aa..00000000000
--- a/arch/arm/mach-s3c2410/include/mach/spi.h
+++ /dev/null
@@ -1,38 +0,0 @@
-/* arch/arm/mach-s3c2410/include/mach/spi.h
- *
- * Copyright (c) 2006 Simtec Electronics
- *      Ben Dooks <ben@simtec.co.uk>
- *
- * S3C2410 - SPI Controller platform_device info
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __ASM_ARCH_SPI_H
-#define __ASM_ARCH_SPI_H __FILE__
-
-struct s3c2410_spi_info {
-        int                      pin_cs;        /* simple gpio cs */
-        unsigned int             num_cs;        /* total chipselects */
-        int                      bus_num;       /* bus number to use. */
-
-        unsigned int             use_fiq:1;     /* use fiq */
-
-        void (*gpio_setup)(struct s3c2410_spi_info *spi, int enable);
-        void (*set_cs)(struct s3c2410_spi_info *spi, int cs, int pol);
-};
-
-/* Standard setup / suspend routines for SPI GPIO pins. */
-
-extern void s3c24xx_spi_gpiocfg_bus0_gpe11_12_13(struct s3c2410_spi_info *spi,
-                                                 int enable);
-
-extern void s3c24xx_spi_gpiocfg_bus1_gpg5_6_7(struct s3c2410_spi_info *spi,
-                                              int enable);
-
-extern void s3c24xx_spi_gpiocfg_bus1_gpd8_9_10(struct s3c2410_spi_info *spi,
-                                               int enable);
-
-#endif /* __ASM_ARCH_SPI_H */
diff --git a/arch/arm/mach-s3c2410/include/mach/system.h b/arch/arm/mach-s3c2410/include/mach/system.h
deleted file mode 100644
index 5e215c1a5c8..00000000000
--- a/arch/arm/mach-s3c2410/include/mach/system.h
+++ /dev/null
@@ -1,54 +0,0 @@
-/* arch/arm/mach-s3c2410/include/mach/system.h
- *
- * Copyright (c) 2003 Simtec Electronics
- *      Ben Dooks <ben@simtec.co.uk>
- *
- * S3C2410 - System function defines and includes
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#include <linux/io.h>
-#include <mach/hardware.h>
-
-#include <mach/map.h>
-#include <mach/idle.h>
-
-#include <mach/regs-clock.h>
-
-void (*s3c24xx_idle)(void);
-
-void s3c24xx_default_idle(void)
-{
-        unsigned long tmp;
-        int i;
-
-        /* idle the system by using the idle mode which will wait for an
-         * interrupt to happen before restarting the system.
-         */
-
-        /* Warning: going into idle state upsets jtag scanning */
-
-        __raw_writel(__raw_readl(S3C2410_CLKCON) | S3C2410_CLKCON_IDLE,
-                     S3C2410_CLKCON);
-
-        /* the samsung port seems to do a loop and then unset idle.. */
-        for (i = 0; i < 50; i++) {
-                tmp += __raw_readl(S3C2410_CLKCON); /* ensure loop not optimised out */
-        }
-
-        /* this bit is not cleared on re-start... */
-
-        __raw_writel(__raw_readl(S3C2410_CLKCON) & ~S3C2410_CLKCON_IDLE,
-                     S3C2410_CLKCON);
-}
-
-static void arch_idle(void)
-{
-        if (s3c24xx_idle != NULL)
-                (s3c24xx_idle)();
-        else
-                s3c24xx_default_idle();
-}
diff --git a/arch/arm/mach-s3c2410/usb-simtec.h b/arch/arm/mach-s3c2410/usb-simtec.h
deleted file mode 100644
index 03842ede9e7..00000000000
--- a/arch/arm/mach-s3c2410/usb-simtec.h
+++ /dev/null
@@ -1,16 +0,0 @@
-/* linux/arch/arm/mach-s3c2410/usb-simtec.h
- *
- * Copyright (c) 2004 Simtec Electronics
- *   Ben Dooks <ben@simtec.co.uk>
- *
- * http://www.simtec.co.uk/products/EB2410ITX/
- *
- * Simtec BAST and Thorcom VR1000 USB port support functions
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-extern int usb_simtec_init(void);
-
diff --git a/arch/arm/mach-s3c2412/Kconfig b/arch/arm/mach-s3c2412/Kconfig
index b8b9029e9f2..c5256f4e90b 100644
--- a/arch/arm/mach-s3c2412/Kconfig
+++ b/arch/arm/mach-s3c2412/Kconfig
@@ -2,41 +2,6 @@
 #
 # Licensed under GPLv2
 
-config CPU_S3C2412
-        bool
-        depends on ARCH_S3C2410
-        select CPU_ARM926T
-        select CPU_LLSERIAL_S3C2440
-        select S3C2412_PM if PM
-        select S3C2412_DMA if S3C2410_DMA
-        help
-          Support for the S3C2412 and S3C2413 SoCs from the S3C24XX line
-
-config CPU_S3C2412_ONLY
-        bool
-        depends on ARCH_S3C2410 && !CPU_S3C2410 && \
-                   !CPU_S3C2416 && !CPU_S3C2440 && !CPU_S3C2442 && \
-                   !CPU_S3C2443 && CPU_S3C2412
-        default y if CPU_S3C2412
-
-config S3C2412_DMA
-        bool
-        depends on CPU_S3C2412
-        help
-          Internal config node for S3C2412 DMA support
-
-config S3C2412_PM
-        bool
-        select S3C2412_PM_SLEEP
-        help
-          Internal config node to apply S3C2412 power management
-
-config S3C2412_PM_SLEEP
-        bool
-        help
-          Internal config node to apply sleep for S3C2412 power management.
-          Can be selected by another SoCs with similar sleep procedure.
-
 # Note, the S3C2412 IOtiming support is in plat-s3c24xx
 
 config S3C2412_CPUFREQ
@@ -46,53 +11,3 @@ config S3C2412_CPUFREQ
         default y
         help
           CPU Frequency scaling support for S3C2412 and S3C2413 SoC CPUs.
-
-menu "S3C2412 Machines"
-
-config MACH_JIVE
-        bool "Logitech Jive"
-        select CPU_S3C2412
-        select S3C_DEV_USB_HOST
-        select S3C_DEV_NAND
-        help
-          Say Y here if you are using the Logitech Jive.
-
-config MACH_JIVE_SHOW_BOOTLOADER
-        bool "Allow access to bootloader partitions in MTD (EXPERIMENTAL)"
-        depends on MACH_JIVE && EXPERIMENTAL
-
-config MACH_SMDK2413
-        bool "SMDK2413"
-        select CPU_S3C2412
-        select MACH_S3C2413
-        select MACH_SMDK
-        select S3C_DEV_USB_HOST
-        select S3C_DEV_NAND
-        help
-          Say Y here if you are using an SMDK2413
-
-config MACH_S3C2413
-        bool
-        help
-          Internal node for S3C2413 version of SMDK2413, so that
-          machine_is_s3c2413() will work when MACH_SMDK2413 is
-          selected
-
-config MACH_SMDK2412
-        bool "SMDK2412"
-        select MACH_SMDK2413
-        help
-          Say Y here if you are using an SMDK2412
-
-          Note, this shares support with SMDK2413, so will automatically
-          select MACH_SMDK2413.
-
-config MACH_VSTMS
-        bool "VMSTMS"
-        select CPU_S3C2412
-        select S3C_DEV_USB_HOST
-        select S3C_DEV_NAND
-        help
-          Say Y here if you are using an VSTMS board
-
-endmenu
diff --git a/arch/arm/mach-s3c2412/Makefile b/arch/arm/mach-s3c2412/Makefile
index 7e4d95fa8a9..41a6c279fb2 100644
--- a/arch/arm/mach-s3c2412/Makefile
+++ b/arch/arm/mach-s3c2412/Makefile
@@ -9,16 +9,4 @@ obj-m				:=
 obj-n                           :=
 obj-                            :=
 
-obj-$(CONFIG_CPU_S3C2412)       += s3c2412.o
-obj-$(CONFIG_CPU_S3C2412)       += irq.o
-obj-$(CONFIG_CPU_S3C2412)       += clock.o
-obj-$(CONFIG_S3C2412_DMA)       += dma.o
-obj-$(CONFIG_S3C2412_PM)        += pm.o
-obj-$(CONFIG_S3C2412_PM_SLEEP)  += sleep.o
 obj-$(CONFIG_S3C2412_CPUFREQ)   += cpu-freq.o
-
-# Machine support
-
-obj-$(CONFIG_MACH_JIVE)         += mach-jive.o
-obj-$(CONFIG_MACH_SMDK2413)     += mach-smdk2413.o
-obj-$(CONFIG_MACH_VSTMS)        += mach-vstms.o
diff --git a/arch/arm/mach-s3c2416/Kconfig b/arch/arm/mach-s3c2416/Kconfig
deleted file mode 100644
index 84c7b03e5a3..00000000000
--- a/arch/arm/mach-s3c2416/Kconfig
+++ /dev/null
@@ -1,60 +0,0 @@
-# arch/arm/mach-s3c2416/Kconfig
-#
-# Copyright 2009 Yauhen Kharuzhy <jekhor@gmail.com>
-#
-# Licensed under GPLv2
-
-# note, this also supports the S3C2450 which is so similar it has the same
-# ID code as the S3C2416.
-
-config CPU_S3C2416
-        bool
-        depends on ARCH_S3C2410
-        select CPU_ARM926T
-        select S3C2416_DMA if S3C2410_DMA
-        select CPU_LLSERIAL_S3C2440
-        select SAMSUNG_CLKSRC
-        select S3C2443_CLOCK
-        help
-          Support for the S3C2416 SoC from the S3C24XX line
-
-config S3C2416_DMA
-        bool
-        depends on CPU_S3C2416
-        help
-          Internal config node for S3C2416 DMA support
-
-config S3C2416_PM
-        bool
-        select S3C2412_PM_SLEEP
-        help
-          Internal config node to apply S3C2416 power management
-
-config S3C2416_SETUP_SDHCI
-        bool
-        select S3C2416_SETUP_SDHCI_GPIO
-        help
-          Internal helper functions for S3C2416 based SDHCI systems
-
-config S3C2416_SETUP_SDHCI_GPIO
-        bool
-        help
-          Common setup code for SDHCI gpio.
-
-menu "S3C2416 Machines"
-
-config MACH_SMDK2416
-        bool "SMDK2416"
-        select CPU_S3C2416
-        select MACH_SMDK
-        select S3C_DEV_FB
-        select S3C_DEV_HSMMC
-        select S3C_DEV_HSMMC1
-        select S3C_DEV_NAND
-        select S3C_DEV_USB_HOST
-        select S3C2416_SETUP_SDHCI
-        select S3C2416_PM if PM
-        help
-          Say Y here if you are using an SMDK2416
-
-endmenu
diff --git a/arch/arm/mach-s3c2416/Makefile b/arch/arm/mach-s3c2416/Makefile
deleted file mode 100644
index ca0cd227f87..00000000000
--- a/arch/arm/mach-s3c2416/Makefile
+++ /dev/null
@@ -1,22 +0,0 @@
-# arch/arm/mach-s3c2416/Makefile
-#
-# Copyright 2009 Yauhen Kharuzhy <jekhor@gmail.com>
-#
-# Licensed under GPLv2
-
-obj-y                           :=
-obj-m                           :=
-obj-n                           :=
-obj-                            :=
-
-obj-$(CONFIG_CPU_S3C2416)       += s3c2416.o clock.o
-obj-$(CONFIG_CPU_S3C2416)       += irq.o
-obj-$(CONFIG_S3C2416_PM)        += pm.o
-#obj-$(CONFIG_S3C2416_DMA)      += dma.o
-
-# Device setup
-obj-$(CONFIG_S3C2416_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o
-
-# Machine support
-
-obj-$(CONFIG_MACH_SMDK2416)     += mach-smdk2416.o
diff --git a/arch/arm/mach-s3c2440/Kconfig b/arch/arm/mach-s3c2440/Kconfig
index 914e620f125..ece7a10fe3c 100644
--- a/arch/arm/mach-s3c2440/Kconfig
+++ b/arch/arm/mach-s3c2440/Kconfig
@@ -2,35 +2,6 @@
 #
 # Licensed under GPLv2
 
-config CPU_S3C2440
-        bool
-        select CPU_ARM920T
-        select S3C2410_CLOCK
-        select S3C2410_PM if PM
-        select S3C2440_DMA if S3C2410_DMA
-        select CPU_S3C244X
-        select CPU_LLSERIAL_S3C2440
-        help
-          Support for S3C2440 Samsung Mobile CPU based systems.
-
-config CPU_S3C2442
-        bool
-        select CPU_ARM920T
-        select S3C2410_CLOCK
-        select S3C2410_PM if PM
-        select CPU_S3C244X
-        select CPU_LLSERIAL_S3C2440
-        help
-          Support for S3C2442 Samsung Mobile CPU based systems.
-
-config CPU_S3C244X
-        bool
-        depends on CPU_S3C2440 || CPU_S3C2442
-        help
-          Support for S3C2440 and S3C2442 Samsung Mobile CPU based systems.
-
-
-
 config S3C2440_CPUFREQ
         bool "S3C2440/S3C2442 CPU Frequency scaling support"
         depends on CPU_FREQ_S3C24XX && (CPU_S3C2440 || CPU_S3C2442)
@@ -64,139 +35,3 @@ config S3C2440_PLL_16934400
         default y if CPU_FREQ_S3C24XX_PLL
         help
           PLL tables for S3C2440 or S3C2442 CPUs with 16.934MHz crystals.
-
-config S3C2440_DMA
-        bool
-        depends on CPU_S3C2440
-        help
-          Support for S3C2440 specific DMA code5A
-
-menu "S3C2440 and S3C2442 Machines"
-
-config MACH_ANUBIS
-        bool "Simtec Electronics ANUBIS"
-        select CPU_S3C2440
-        select S3C24XX_DCLK
-        select PM_SIMTEC if PM
-        select HAVE_PATA_PLATFORM
-        select S3C24XX_GPIO_EXTRA64
-        select S3C2440_XTAL_12000000
-        select S3C_DEV_USB_HOST
-        help
-          Say Y here if you are using the Simtec Electronics ANUBIS
-          development system
-
-config MACH_NEO1973_GTA02
-        bool "Openmoko GTA02 / Freerunner phone"
-        select CPU_S3C2442
-        select MFD_PCF50633
-        select PCF50633_GPIO
-        select I2C
-        select POWER_SUPPLY
-        select MACH_NEO1973
-        select S3C2410_PWM
-        select S3C_DEV_USB_HOST
-        help
-           Say Y here if you are using the Openmoko GTA02 / Freerunner GSM Phone
-
-config MACH_OSIRIS
-        bool "Simtec IM2440D20 (OSIRIS) module"
-        select CPU_S3C2440
-        select S3C24XX_DCLK
-        select PM_SIMTEC if PM
-        select S3C24XX_GPIO_EXTRA128
-        select S3C2440_XTAL_12000000
-        select S3C2410_IOTIMING if S3C2440_CPUFREQ
-        select S3C_DEV_USB_HOST
-        select S3C_DEV_NAND
-        help
-          Say Y here if you are using the Simtec IM2440D20 module, also
-          known as the Osiris.
-
-config MACH_OSIRIS_DVS
-        tristate "Simtec IM2440D20 (OSIRIS) Dynamic Voltage Scaling driver"
-        depends on MACH_OSIRIS
-        select TPS65010
-        help
-          Say Y/M here if you want to have dynamic voltage scaling support
-          on the Simtec IM2440D20 (OSIRIS) module via the TPS65011.
-
-          The DVS driver alters the voltage supplied to the ARM core
-          depending on the frequency it is running at. The driver itself
-          does not do any of the frequency alteration, which is left up
-          to the cpufreq driver.
-
-config MACH_RX3715
-        bool "HP iPAQ rx3715"
-        select CPU_S3C2440
-        select S3C2440_XTAL_16934400
-        select PM_H1940 if PM
-        select S3C_DEV_NAND
-        help
-          Say Y here if you are using the HP iPAQ rx3715.
-
-config ARCH_S3C2440
-        bool "SMDK2440"
-        select CPU_S3C2440
-        select S3C2440_XTAL_16934400
-        select MACH_SMDK
-        select S3C_DEV_USB_HOST
-        select S3C_DEV_NAND
-        help
-          Say Y here if you are using the SMDK2440.
-
-config MACH_NEXCODER_2440
-        bool "NexVision NEXCODER 2440 Light Board"
-        select CPU_S3C2440
-        select S3C2440_XTAL_12000000
-        select S3C_DEV_USB_HOST
-        select S3C_DEV_NAND
-        help
-          Say Y here if you are using the Nex Vision NEXCODER 2440 Light Board
-
-config SMDK2440_CPU2440
-        bool "SMDK2440 with S3C2440 CPU module"
-        default y if ARCH_S3C2440
-        select S3C2440_XTAL_16934400
-        select CPU_S3C2440
-
-config SMDK2440_CPU2442
-        bool "SMDM2440 with S3C2442 CPU module"
-        select CPU_S3C2442
-
-config MACH_AT2440EVB
-        bool "Avantech AT2440EVB development board"
-        select CPU_S3C2440
-        select S3C_DEV_USB_HOST
-        select S3C_DEV_NAND
-        help
-          Say Y here if you are using the AT2440EVB development board
-
-config MACH_MINI2440
-        bool "MINI2440 development board"
-        select CPU_S3C2440
-        select EEPROM_AT24
-        select NEW_LEDS
-        select LEDS_CLASS
-        select LEDS_TRIGGER
-        select LEDS_TRIGGER_BACKLIGHT
-        select S3C_DEV_NAND
-        select S3C_DEV_USB_HOST
-        help
-          Say Y here to select support for the MINI2440. Is a 10cm x 10cm board
-          available via various sources. It can come with a 3.5" or 7" touch LCD.
-
-config MACH_RX1950
-        bool "HP iPAQ rx1950"
-        select CPU_S3C2442
-        select S3C24XX_DCLK
-        select PM_H1940 if PM
-        select I2C
-        select S3C2410_PWM
-        select S3C_DEV_NAND
-        select S3C2410_IOTIMING if S3C2440_CPUFREQ
-        select S3C2440_XTAL_16934400
-        help
-           Say Y here if you're using HP iPAQ rx1950
-
-endmenu
diff --git a/arch/arm/mach-s3c2440/Makefile b/arch/arm/mach-s3c2440/Makefile
index d5440fa34b0..c4609243981 100644
--- a/arch/arm/mach-s3c2440/Makefile
+++ b/arch/arm/mach-s3c2440/Makefile
@@ -9,33 +9,9 @@ obj-m				:=
 obj-n                           :=
 obj-                            :=
 
-obj-$(CONFIG_CPU_S3C2440)       += s3c2440.o dsc.o
-obj-$(CONFIG_CPU_S3C2442)       += s3c2442.o
+obj-$(CONFIG_CPU_S3C2440)       += dsc.o
 
-obj-$(CONFIG_CPU_S3C2440)       += irq.o
-obj-$(CONFIG_CPU_S3C2440)       += clock.o
-obj-$(CONFIG_S3C2440_DMA)       += dma.o
-
-obj-$(CONFIG_CPU_S3C244X)       += s3c244x.o
-obj-$(CONFIG_CPU_S3C244X)       += s3c244x-irq.o
-obj-$(CONFIG_CPU_S3C244X)       += s3c244x-clock.o
 obj-$(CONFIG_S3C2440_CPUFREQ)   += s3c2440-cpufreq.o
 
 obj-$(CONFIG_S3C2440_PLL_12000000) += s3c2440-pll-12000000.o
 obj-$(CONFIG_S3C2440_PLL_16934400) += s3c2440-pll-16934400.o
-
-# Machine support
-
-obj-$(CONFIG_MACH_ANUBIS)       += mach-anubis.o
-obj-$(CONFIG_MACH_OSIRIS)       += mach-osiris.o
-obj-$(CONFIG_MACH_RX3715)       += mach-rx3715.o
-obj-$(CONFIG_ARCH_S3C2440)      += mach-smdk2440.o
-obj-$(CONFIG_MACH_NEXCODER_2440) += mach-nexcoder.o
-obj-$(CONFIG_MACH_AT2440EVB) += mach-at2440evb.o
-obj-$(CONFIG_MACH_MINI2440) += mach-mini2440.o
-obj-$(CONFIG_MACH_NEO1973_GTA02) += mach-gta02.o
-obj-$(CONFIG_MACH_RX1950) += mach-rx1950.o
-
-# extra machine support
-
-obj-$(CONFIG_MACH_OSIRIS_DVS)   += mach-osiris-dvs.o
diff --git a/arch/arm/mach-s3c2440/common.h b/arch/arm/mach-s3c2440/common.h
deleted file mode 100644
index 0c1eb1dfc53..00000000000
--- a/arch/arm/mach-s3c2440/common.h
+++ /dev/null
@@ -1,17 +0,0 @@
-/*
- * Copyright (c) 2011 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com
- *
- * Common Header for S3C2440 machines
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef __ARCH_ARM_MACH_S3C2440_COMMON_H
-#define __ARCH_ARM_MACH_S3C2440_COMMON_H
-
-void s3c244x_restart(char mode, const char *cmd);
-
-#endif /* __ARCH_ARM_MACH_S3C2440_COMMON_H */
diff --git a/arch/arm/mach-s3c2443/Kconfig b/arch/arm/mach-s3c2443/Kconfig
deleted file mode 100644
index 8814031516c..00000000000
--- a/arch/arm/mach-s3c2443/Kconfig
+++ /dev/null
@@ -1,32 +0,0 @@
-# Copyright 2007 Simtec Electronics
-#
-# Licensed under GPLv2
-
-config CPU_S3C2443
-        bool
-        depends on ARCH_S3C2410
-        select CPU_ARM920T
-        select S3C2443_DMA if S3C2410_DMA
-        select CPU_LLSERIAL_S3C2440
-        select SAMSUNG_CLKSRC
-        select S3C2443_CLOCK
-        help
-          Support for the S3C2443 SoC from the S3C24XX line
-
-config S3C2443_DMA
-        bool
-        depends on CPU_S3C2443
-        help
-          Internal config node for S3C2443 DMA support
-
-menu "S3C2443 Machines"
-
-config MACH_SMDK2443
-        bool "SMDK2443"
-        select CPU_S3C2443
-        select MACH_SMDK
-        select S3C_DEV_HSMMC1
-        help
-          Say Y here if you are using an SMDK2443
-
-endmenu
diff --git a/arch/arm/mach-s3c2443/Makefile b/arch/arm/mach-s3c2443/Makefile
deleted file mode 100644
index d1843c9eb8b..00000000000
--- a/arch/arm/mach-s3c2443/Makefile
+++ /dev/null
@@ -1,20 +0,0 @@
-# arch/arm/mach-s3c2443/Makefile
-#
-# Copyright 2007 Simtec Electronics
-#
-# Licensed under GPLv2
-
-obj-y                           :=
-obj-m                           :=
-obj-n                           :=
-obj-                            :=
-
-obj-$(CONFIG_CPU_S3C2443)       += s3c2443.o
-obj-$(CONFIG_CPU_S3C2443)       += irq.o
-obj-$(CONFIG_CPU_S3C2443)       += clock.o
-
-obj-$(CONFIG_S3C2443_DMA)       += dma.o
-
-# Machine support
-
-obj-$(CONFIG_MACH_SMDK2443)     += mach-smdk2443.o
diff --git a/arch/arm/mach-s3c24xx/Kconfig b/arch/arm/mach-s3c24xx/Kconfig
new file mode 100644
index 00000000000..0f3a327ebca
--- /dev/null
+++ b/arch/arm/mach-s3c24xx/Kconfig
@@ -0,0 +1,538 @@
+# arch/arm/mach-s3c24xx/Kconfig
+#
+# Copyright (c) 2012 Samsung Electronics Co., Ltd.
+#               http://www.samsung.com/
+#
+# Copyright 2007 Simtec Electronics
+#
+# Licensed under GPLv2
+
+if ARCH_S3C24XX
+
+menu "SAMSUNG S3C24XX SoCs Support"
+
+comment "S3C24XX SoCs"
+
+config CPU_S3C2410
+        bool "SAMSUNG S3C2410"
+        default y
+        select CPU_ARM920T
+        select S3C2410_CLOCK
+        select CPU_LLSERIAL_S3C2410
+        select S3C2410_PM if PM
+        select S3C2410_CPUFREQ if CPU_FREQ_S3C24XX
+        help
+          Support for S3C2410 and S3C2410A family from the S3C24XX line
+          of Samsung Mobile CPUs.
+
+config CPU_S3C2412
+        bool "SAMSUNG S3C2412"
+        depends on ARCH_S3C24XX
+        select CPU_ARM926T
+        select CPU_LLSERIAL_S3C2440
+        select S3C2412_PM if PM
+        select S3C2412_DMA if S3C24XX_DMA
+        help
+          Support for the S3C2412 and S3C2413 SoCs from the S3C24XX line
+
+config CPU_S3C2416
+        bool "SAMSUNG S3C2416/S3C2450"
+        depends on ARCH_S3C24XX
+        select CPU_ARM926T
+        select CPU_LLSERIAL_S3C2440
+        select SAMSUNG_CLKSRC
+        select S3C2443_COMMON
+        select S3C2443_DMA if S3C24XX_DMA
+        select S3C2416_PM if PM
+        help
+          Support for the S3C2416 SoC from the S3C24XX line
+
+config CPU_S3C2440
+        bool "SAMSUNG S3C2440"
+        select CPU_ARM920T
+        select CPU_LLSERIAL_S3C2440
+        select S3C2410_CLOCK
+        select S3C2410_PM if PM
+        select S3C2440_DMA if S3C24XX_DMA
+        help
+          Support for S3C2440 Samsung Mobile CPU based systems.
+
+config CPU_S3C2442
+        bool "SAMSUNG S3C2442"
+        select CPU_ARM920T
+        select CPU_LLSERIAL_S3C2440
+        select S3C2410_CLOCK
+        select S3C2410_PM if PM
+        help
+          Support for S3C2442 Samsung Mobile CPU based systems.
+
+config CPU_S3C244X
+        def_bool y
+        depends on CPU_S3C2440 || CPU_S3C2442
+
+config CPU_S3C2443
+        bool "SAMSUNG S3C2443"
+        depends on ARCH_S3C24XX
+        select CPU_ARM920T
+        select CPU_LLSERIAL_S3C2440
+        select SAMSUNG_CLKSRC
+        select S3C2443_COMMON
+        select S3C2443_DMA if S3C24XX_DMA
+        help
+          Support for the S3C2443 SoC from the S3C24XX line
+
+# common code
+
+config S3C24XX_SMDK
+        bool
+        help
+          Common machine code for SMDK2410 and SMDK2440
+
+config S3C24XX_SIMTEC_AUDIO
+        bool
+        depends on (ARCH_BAST || MACH_VR1000 || MACH_OSIRIS || MACH_ANUBIS)
+        default y
+        help
+          Add audio devices for common Simtec S3C24XX boards
+
+config S3C24XX_SIMTEC_PM
+        bool
+        help
+          Common power management code for systems that are
+          compatible with the Simtec style of power management
+
+config S3C24XX_SIMTEC_USB
+        bool
+        help
+          USB management code for common Simtec S3C24XX boards
+
+config S3C24XX_SETUP_TS
+        bool
+        help
+          Compile in platform device definition for Samsung TouchScreen.
+
+# cpu-specific sections
+
+if CPU_S3C2410
+
+config S3C2410_DMA
+        bool
+        depends on S3C24XX_DMA && (CPU_S3C2410 || CPU_S3C2442)
+        default y if CPU_S3C2410 || CPU_S3C2442
+        help
+          DMA device selection for S3C2410 and compatible CPUs
+
+config S3C2410_PM
+        bool
+        help
+          Power Management code common to S3C2410 and better
+
+config S3C24XX_SIMTEC_NOR
+        bool
+        help
+          Internal node to specify machine has simtec NOR mapping
+
+config MACH_BAST_IDE
+        bool
+        select HAVE_PATA_PLATFORM
+        help
+          Internal node for machines with an BAST style IDE
+          interface
+
+comment "S3C2410 Boards"
+
+#
+# The "S3C2410 Boards" list is ordered alphabetically by option text.
+# (without ARCH_ or MACH_)
+#
+
+config MACH_AML_M5900
+        bool "AML M5900 Series"
+        select S3C24XX_SIMTEC_PM if PM
+        select S3C_DEV_USB_HOST
+        help
+          Say Y here if you are using the American Microsystems M5900 Series
+          <http://www.amltd.com>
+
+config ARCH_BAST
+        bool "Simtec Electronics BAST (EB2410ITX)"
+        select S3C2410_IOTIMING if S3C2410_CPUFREQ
+        select S3C24XX_SIMTEC_PM if PM
+        select S3C24XX_SIMTEC_NOR
+        select S3C24XX_SIMTEC_USB
+        select MACH_BAST_IDE
+        select S3C24XX_DCLK
+        select ISA
+        select S3C_DEV_HWMON
+        select S3C_DEV_USB_HOST
+        select S3C_DEV_NAND
+        help
+          Say Y here if you are using the Simtec Electronics EB2410ITX
+          development board (also known as BAST)
+
+config BAST_PC104_IRQ
+        bool "BAST PC104 IRQ support"
+        depends on ARCH_BAST
+        default y
+        help
+          Say Y here to enable the PC104 IRQ routing on the
+          Simtec BAST (EB2410ITX)
+
+config ARCH_H1940
+        bool "IPAQ H1940"
+        select PM_H1940 if PM
+        select S3C_DEV_USB_HOST
+        select S3C_DEV_NAND
+        select S3C24XX_SETUP_TS
+        help
+          Say Y here if you are using the HP IPAQ H1940
+
+config H1940BT
+        tristate "Control the state of H1940 bluetooth chip"
+        depends on ARCH_H1940
+        select RFKILL
+        help
+          This is a simple driver that is able to control
+          the state of built in bluetooth chip on h1940.
+
+config PM_H1940
+        bool
+        help
+          Internal node for H1940 and related PM
+
+config MACH_N30
+        bool "Acer N30 family"
+        select MACH_N35
+        select S3C_DEV_USB_HOST
+        select S3C_DEV_NAND
+        help
+          Say Y here if you want suppt for the Acer N30, Acer N35,
+          Navman PiN570, Yakumo AlphaX or Airis NC05 PDAs.
+
+config MACH_OTOM
+        bool "NexVision OTOM Board"
+        select S3C_DEV_USB_HOST
+        select S3C_DEV_NAND
+        help
+          Say Y here if you are using the Nex Vision OTOM board
+
+config MACH_QT2410
+        bool "QT2410"
+        select S3C_DEV_USB_HOST
+        select S3C_DEV_NAND
+        help
+          Say Y here if you are using the Armzone QT2410
+
+config ARCH_SMDK2410
+        bool "SMDK2410/A9M2410"
+        select S3C24XX_SMDK
+        help
+          Say Y here if you are using the SMDK2410 or the derived module A9M2410
+          <http://www.fsforth.de>
+
+config MACH_TCT_HAMMER
+        bool "TCT Hammer Board"
+        select S3C_DEV_USB_HOST
+        help
+          Say Y here if you are using the TinCanTools Hammer Board
+          <http://www.tincantools.com>
+
+config MACH_VR1000
+        bool "Thorcom VR1000"
+        select S3C24XX_SIMTEC_PM if PM
+        select S3C24XX_DCLK
+        select S3C24XX_SIMTEC_NOR
+        select MACH_BAST_IDE
+        select S3C_DEV_USB_HOST
+        select S3C24XX_SIMTEC_USB
+        help
+          Say Y here if you are using the Thorcom VR1000 board.
+
+endif   # CPU_S3C2410
+
+config S3C2412_PM_SLEEP
+        bool
+        help
+          Internal config node to apply sleep for S3C2412 power management.
+          Can be selected by another SoCs such as S3C2416 with similar
+          sleep procedure.
+
+if CPU_S3C2412
+
+config CPU_S3C2412_ONLY
+        bool
+        depends on ARCH_S3C24XX && !CPU_S3C2410 && \
+                   !CPU_S3C2416 && !CPU_S3C2440 && !CPU_S3C2442 && \
+                   !CPU_S3C2443 && CPU_S3C2412
+        default y
+
+config S3C2412_DMA
+        bool
+        help
+          Internal config node for S3C2412 DMA support
+
+config S3C2412_PM
+        bool
+        help
+          Internal config node to apply S3C2412 power management
+
+comment "S3C2412 Boards"
+
+#
+# The "S3C2412 Boards" list is ordered alphabetically by option text.
+# (without ARCH_ or MACH_)
+#
+
+config MACH_JIVE
+        bool "Logitech Jive"
+        select S3C_DEV_USB_HOST
+        select S3C_DEV_NAND
+        help
+          Say Y here if you are using the Logitech Jive.
+
+config MACH_JIVE_SHOW_BOOTLOADER
+        bool "Allow access to bootloader partitions in MTD (EXPERIMENTAL)"
+        depends on MACH_JIVE && EXPERIMENTAL
+
+config MACH_S3C2413
+        bool
+        help
+          Internal node for S3C2413 version of SMDK2413, so that
+          machine_is_s3c2413() will work when MACH_SMDK2413 is
+          selected
+
+config MACH_SMDK2412
+        bool "SMDK2412"
+        select MACH_SMDK2413
+        help
+          Say Y here if you are using an SMDK2412
+
+          Note, this shares support with SMDK2413, so will automatically
+          select MACH_SMDK2413.
+
+config MACH_SMDK2413
+        bool "SMDK2413"
+        select MACH_S3C2413
+        select S3C24XX_SMDK
+        select S3C_DEV_USB_HOST
+        select S3C_DEV_NAND
+        help
+          Say Y here if you are using an SMDK2413
+
+config MACH_VSTMS
+        bool "VMSTMS"
+        select S3C_DEV_USB_HOST
+        select S3C_DEV_NAND
+        help
+          Say Y here if you are using an VSTMS board
+
+endif   # CPU_S3C2412
+
+if CPU_S3C2416
+
+config S3C2416_PM
+        bool
+        select S3C2412_PM_SLEEP
+        help
+          Internal config node to apply S3C2416 power management
+
+config S3C2416_SETUP_SDHCI
+        bool
+        select S3C2416_SETUP_SDHCI_GPIO
+        help
+          Internal helper functions for S3C2416 based SDHCI systems
+
+config S3C2416_SETUP_SDHCI_GPIO
+        bool
+        help
+          Common setup code for SDHCI gpio.
+
+comment "S3C2416 Boards"
+
+config MACH_SMDK2416
+        bool "SMDK2416"
+        select S3C24XX_SMDK
+        select S3C_DEV_FB
+        select S3C_DEV_HSMMC
+        select S3C_DEV_HSMMC1
+        select S3C_DEV_NAND
+        select S3C_DEV_USB_HOST
+        select S3C2416_SETUP_SDHCI
+        help
+          Say Y here if you are using an SMDK2416
+
+endif   # CPU_S3C2416
+
+if CPU_S3C2440
+
+config S3C2440_DMA
+        bool
+        help
+          Support for S3C2440 specific DMA code5A
+
+comment "S3C2440 Boards"
+
+#
+# The "S3C2440 Boards" list is ordered alphabetically by option text.
+# (without ARCH_ or MACH_)
+#
+
+config MACH_ANUBIS
+        bool "Simtec Electronics ANUBIS"
+        select S3C24XX_DCLK
+        select S3C24XX_SIMTEC_PM if PM
+        select HAVE_PATA_PLATFORM
+        select S3C24XX_GPIO_EXTRA64
+        select S3C2440_XTAL_12000000
+        select S3C_DEV_USB_HOST
+        help
+          Say Y here if you are using the Simtec Electronics ANUBIS
+          development system
+
+config MACH_AT2440EVB
+        bool "Avantech AT2440EVB development board"
+        select S3C_DEV_USB_HOST
+        select S3C_DEV_NAND
+        help
+          Say Y here if you are using the AT2440EVB development board
+
+config MACH_MINI2440
+        bool "MINI2440 development board"
+        select EEPROM_AT24
+        select NEW_LEDS
+        select LEDS_CLASS
+        select LEDS_TRIGGER
+        select LEDS_TRIGGER_BACKLIGHT
+        select S3C_DEV_NAND
+        select S3C_DEV_USB_HOST
+        help
+          Say Y here to select support for the MINI2440. Is a 10cm x 10cm board
+          available via various sources. It can come with a 3.5" or 7" touch LCD.
+
+config MACH_NEXCODER_2440
+        bool "NexVision NEXCODER 2440 Light Board"
+        select S3C2440_XTAL_12000000
+        select S3C_DEV_USB_HOST
+        select S3C_DEV_NAND
+        help
+          Say Y here if you are using the Nex Vision NEXCODER 2440 Light Board
+
+config MACH_OSIRIS
+        bool "Simtec IM2440D20 (OSIRIS) module"
+        select S3C24XX_DCLK
+        select S3C24XX_SIMTEC_PM if PM
+        select S3C24XX_GPIO_EXTRA128
+        select S3C2440_XTAL_12000000
+        select S3C2410_IOTIMING if S3C2440_CPUFREQ
+        select S3C_DEV_USB_HOST
+        select S3C_DEV_NAND
+        help
+          Say Y here if you are using the Simtec IM2440D20 module, also
+          known as the Osiris.
+
+config MACH_OSIRIS_DVS
+        tristate "Simtec IM2440D20 (OSIRIS) Dynamic Voltage Scaling driver"
+        depends on MACH_OSIRIS
+        select TPS65010
+        help
+          Say Y/M here if you want to have dynamic voltage scaling support
+          on the Simtec IM2440D20 (OSIRIS) module via the TPS65011.
+
+          The DVS driver alters the voltage supplied to the ARM core
+          depending on the frequency it is running at. The driver itself
+          does not do any of the frequency alteration, which is left up
+          to the cpufreq driver.
+
+config MACH_RX3715
+        bool "HP iPAQ rx3715"
+        select S3C2440_XTAL_16934400
+        select PM_H1940 if PM
+        select S3C_DEV_NAND
+        help
+          Say Y here if you are using the HP iPAQ rx3715.
+
+config ARCH_S3C2440
+        bool "SMDK2440"
+        select S3C2440_XTAL_16934400
+        select S3C24XX_SMDK
+        select S3C_DEV_USB_HOST
+        select S3C_DEV_NAND
+        help
+          Say Y here if you are using the SMDK2440.
+
+config SMDK2440_CPU2440
+        bool "SMDK2440 with S3C2440 CPU module"
+        default y if ARCH_S3C2440
+        select S3C2440_XTAL_16934400
+
+endif   # CPU_S3C2440
+
+if CPU_S3C2442
+
+comment "S3C2442 Boards"
+
+#
+# The "S3C2442 Boards" list is ordered alphabetically by option text.
+# (without ARCH_ or MACH_)
+#
+
+config MACH_NEO1973_GTA02
+        bool "Openmoko GTA02 / Freerunner phone"
+        select MFD_PCF50633
+        select PCF50633_GPIO
+        select I2C
+        select POWER_SUPPLY
+        select MACH_NEO1973
+        select S3C2410_PWM
+        select S3C_DEV_USB_HOST
+        help
+           Say Y here if you are using the Openmoko GTA02 / Freerunner GSM Phone
+
+config MACH_RX1950
+        bool "HP iPAQ rx1950"
+        select S3C24XX_DCLK
+        select PM_H1940 if PM
+        select I2C
+        select S3C2410_PWM
+        select S3C_DEV_NAND
+        select S3C2410_IOTIMING if S3C2440_CPUFREQ
+        select S3C2440_XTAL_16934400
+        help
+           Say Y here if you're using HP iPAQ rx1950
+
+config SMDK2440_CPU2442
+        bool "SMDM2440 with S3C2442 CPU module"
+
+endif   # CPU_S3C2440
+
+if CPU_S3C2443 || CPU_S3C2416
+
+config S3C2443_COMMON
+        bool
+        help
+          Common code for the S3C2443 and similar processors, which includes
+          the S3C2416 and S3C2450.
+
+config S3C2443_DMA
+        bool
+        help
+          Internal config node for S3C2443 DMA support
+
+endif   # CPU_S3C2443 || CPU_S3C2416
+
+if CPU_S3C2443
+
+comment "S3C2443 Boards"
+
+config MACH_SMDK2443
+        bool "SMDK2443"
+        select S3C24XX_SMDK
+        select S3C_DEV_HSMMC1
+        help
+          Say Y here if you are using an SMDK2443
+
+endif   # CPU_S3C2443
+
+endmenu # SAMSUNG S3C24XX SoCs Support
+
+endif   # ARCH_S3C24XX
diff --git a/arch/arm/mach-s3c24xx/Makefile b/arch/arm/mach-s3c24xx/Makefile
new file mode 100644
index 00000000000..3518fe812d5
--- /dev/null
+++ b/arch/arm/mach-s3c24xx/Makefile
@@ -0,0 +1,95 @@
+# arch/arm/mach-s3c24xx/Makefile
+#
+# Copyright (c) 2012 Samsung Electronics Co., Ltd.
+#               http://www.samsung.com/
+#
+# Copyright 2007 Simtec Electronics
+#
+# Licensed under GPLv2
+
+obj-y                           :=
+obj-m                           :=
+obj-n                           :=
+obj-                            :=
+
+# core
+
+obj-$(CONFIG_CPU_S3C2410)       += s3c2410.o
+obj-$(CONFIG_S3C2410_DMA)       += dma-s3c2410.o
+obj-$(CONFIG_S3C2410_PM)        += pm-s3c2410.o sleep-s3c2410.o
+
+obj-$(CONFIG_CPU_S3C2412)       += s3c2412.o irq-s3c2412.o clock-s3c2412.o
+obj-$(CONFIG_S3C2412_DMA)       += dma-s3c2412.o
+obj-$(CONFIG_S3C2412_PM)        += pm-s3c2412.o
+obj-$(CONFIG_S3C2412_PM_SLEEP)  += sleep-s3c2412.o
+
+obj-$(CONFIG_CPU_S3C2416)       += s3c2416.o irq-s3c2416.o clock-s3c2416.o
+obj-$(CONFIG_S3C2416_PM)        += pm-s3c2416.o
+
+obj-$(CONFIG_CPU_S3C2440)       += s3c2440.o irq-s3c2440.o clock-s3c2440.o
+obj-$(CONFIG_CPU_S3C2442)       += s3c2442.o
+obj-$(CONFIG_CPU_S3C244X)       += s3c244x.o irq-s3c244x.o clock-s3c244x.o
+obj-$(CONFIG_S3C2440_DMA)       += dma-s3c2440.o
+
+obj-$(CONFIG_CPU_S3C2443)       += s3c2443.o irq-s3c2443.o clock-s3c2443.o
+
+# common code
+
+obj-$(CONFIG_S3C2443_COMMON)    += common-s3c2443.o
+obj-$(CONFIG_S3C2443_DMA)       += dma-s3c2443.o
+
+#
+# machine support
+# following is ordered alphabetically by option text.
+#
+
+obj-$(CONFIG_MACH_AML_M5900)            += mach-amlm5900.o
+obj-$(CONFIG_ARCH_BAST)                 += mach-bast.o
+obj-$(CONFIG_BAST_PC104_IRQ)            += bast-irq.o
+obj-$(CONFIG_ARCH_H1940)                += mach-h1940.o
+obj-$(CONFIG_H1940BT)                   += h1940-bluetooth.o
+obj-$(CONFIG_PM_H1940)                  += pm-h1940.o
+obj-$(CONFIG_MACH_N30)                  += mach-n30.o
+obj-$(CONFIG_MACH_OTOM)                 += mach-otom.o
+obj-$(CONFIG_MACH_QT2410)               += mach-qt2410.o
+obj-$(CONFIG_ARCH_SMDK2410)             += mach-smdk2410.o
+obj-$(CONFIG_MACH_TCT_HAMMER)           += mach-tct_hammer.o
+obj-$(CONFIG_MACH_VR1000)               += mach-vr1000.o
+
+obj-$(CONFIG_MACH_JIVE)                 += mach-jive.o
+obj-$(CONFIG_MACH_SMDK2413)             += mach-smdk2413.o
+obj-$(CONFIG_MACH_VSTMS)                += mach-vstms.o
+
+obj-$(CONFIG_MACH_SMDK2416)             += mach-smdk2416.o
+
+obj-$(CONFIG_MACH_ANUBIS)               += mach-anubis.o
+obj-$(CONFIG_MACH_AT2440EVB)            += mach-at2440evb.o
+obj-$(CONFIG_MACH_MINI2440)             += mach-mini2440.o
+obj-$(CONFIG_MACH_NEXCODER_2440)        += mach-nexcoder.o
+obj-$(CONFIG_MACH_OSIRIS)               += mach-osiris.o
+obj-$(CONFIG_MACH_RX3715)               += mach-rx3715.o
+obj-$(CONFIG_ARCH_S3C2440)              += mach-smdk2440.o
+
+obj-$(CONFIG_MACH_NEO1973_GTA02)        += mach-gta02.o
+obj-$(CONFIG_MACH_RX1950)               += mach-rx1950.o
+
+obj-$(CONFIG_MACH_SMDK2443)             += mach-smdk2443.o
+
+# common bits of machine support
+
+obj-$(CONFIG_S3C24XX_SMDK)              += common-smdk.o
+obj-$(CONFIG_S3C24XX_SIMTEC_AUDIO)      += simtec-audio.o
+obj-$(CONFIG_S3C24XX_SIMTEC_NOR)        += simtec-nor.o
+obj-$(CONFIG_S3C24XX_SIMTEC_PM)         += simtec-pm.o
+obj-$(CONFIG_S3C24XX_SIMTEC_USB)        += simtec-usb.o
+
+# machine additions
+
+obj-$(CONFIG_MACH_BAST_IDE)             += bast-ide.o
+obj-$(CONFIG_MACH_OSIRIS_DVS)           += mach-osiris-dvs.o
+
+# device setup
+
+obj-$(CONFIG_S3C2416_SETUP_SDHCI_GPIO)  += setup-sdhci-gpio.o
+obj-$(CONFIG_ARCH_S3C24XX)              += setup-i2c.o
+obj-$(CONFIG_S3C24XX_SETUP_TS)          += setup-ts.o
diff --git a/arch/arm/mach-s3c2410/Makefile.boot b/arch/arm/mach-s3c24xx/Makefile.boot
index 4457605ba04..4457605ba04 100644
--- a/arch/arm/mach-s3c2410/Makefile.boot
+++ b/arch/arm/mach-s3c24xx/Makefile.boot
diff --git a/arch/arm/mach-s3c2410/bast-ide.c b/arch/arm/mach-s3c24xx/bast-ide.c
index 298ececfa36..298ececfa36 100644
--- a/arch/arm/mach-s3c2410/bast-ide.c
+++ b/arch/arm/mach-s3c24xx/bast-ide.c
diff --git a/arch/arm/mach-s3c2410/bast-irq.c b/arch/arm/mach-s3c24xx/bast-irq.c
index ac7b2ad5c40..ac7b2ad5c40 100644
--- a/arch/arm/mach-s3c2410/bast-irq.c
+++ b/arch/arm/mach-s3c24xx/bast-irq.c
diff --git a/arch/arm/mach-s3c2412/clock.c b/arch/arm/mach-s3c24xx/clock-s3c2412.c
index d10b695a906..d10b695a906 100644
--- a/arch/arm/mach-s3c2412/clock.c
+++ b/arch/arm/mach-s3c24xx/clock-s3c2412.c
diff --git a/arch/arm/mach-s3c2416/clock.c b/arch/arm/mach-s3c24xx/clock-s3c2416.c
index 59f54d1d7f8..dbc9ab4aaca 100644
--- a/arch/arm/mach-s3c2416/clock.c
+++ b/arch/arm/mach-s3c24xx/clock-s3c2416.c
@@ -15,7 +15,6 @@
 #include <linux/clk.h>
 
 #include <plat/s3c2416.h>
-#include <plat/s3c2443.h>
 #include <plat/clock.h>
 #include <plat/clock-clksrc.h>
 #include <plat/cpu.h>
@@ -132,12 +131,6 @@ static struct clk hsmmc0_clk = {
         .ctrlbit        = S3C2416_HCLKCON_HSMMC0,
 };
 
-void __init_or_cpufreq s3c2416_setup_clocks(void)
-{
-        s3c2443_common_setup_clocks(s3c2416_get_pll);
-}
-
-
 static struct clksrc_clk *clksrcs[] __initdata = {
         &hsspi_eplldiv,
         &hsspi_mux,
diff --git a/arch/arm/mach-s3c2440/clock.c b/arch/arm/mach-s3c24xx/clock-s3c2440.c
index 414364eb426..414364eb426 100644
--- a/arch/arm/mach-s3c2440/clock.c
+++ b/arch/arm/mach-s3c24xx/clock-s3c2440.c
diff --git a/arch/arm/mach-s3c2443/clock.c b/arch/arm/mach-s3c24xx/clock-s3c2443.c
index 6dde2696f8f..efb3ac35956 100644
--- a/arch/arm/mach-s3c2443/clock.c
+++ b/arch/arm/mach-s3c24xx/clock-s3c2443.c
@@ -179,11 +179,6 @@ static struct clk *clks[] __initdata = {
         &clk_hsmmc,
 };
 
-void __init_or_cpufreq s3c2443_setup_clocks(void)
-{
-        s3c2443_common_setup_clocks(s3c2443_get_mpll);
-}
-
 void __init s3c2443_init_clocks(int xtal)
 {
         unsigned long epllcon = __raw_readl(S3C2443_EPLLCON);
@@ -196,8 +191,6 @@ void __init s3c2443_init_clocks(int xtal)
                                    armdiv, ARRAY_SIZE(armdiv),
                                    S3C2443_CLKDIV0_ARMDIV_MASK);
 
-        s3c2443_setup_clocks();
-
         s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
 
         for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
diff --git a/arch/arm/mach-s3c2440/s3c244x-clock.c b/arch/arm/mach-s3c24xx/clock-s3c244x.c
index 6d9b688c442..6d9b688c442 100644
--- a/arch/arm/mach-s3c2440/s3c244x-clock.c
+++ b/arch/arm/mach-s3c24xx/clock-s3c244x.c
diff --git a/arch/arm/plat-s3c24xx/s3c2443-clock.c b/arch/arm/mach-s3c24xx/common-s3c2443.c
index 95e68190d59..460431589f3 100644
--- a/arch/arm/plat-s3c24xx/s3c2443-clock.c
+++ b/arch/arm/mach-s3c24xx/common-s3c2443.c
@@ -1,9 +1,18 @@
-/* linux/arch/arm/plat-s3c24xx/s3c2443-clock.c
+/*
+ * Common code for SoCs starting with the S3C2443
  *
  * Copyright (c) 2007, 2010 Simtec Electronics
  *      Ben Dooks <ben@simtec.co.uk>
  *
- * S3C2443 Clock control suport - common code
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
  */
 
 #include <linux/init.h>
@@ -12,7 +21,6 @@
 
 #include <mach/regs-s3c2443-clock.h>
 
-#include <plat/s3c2443.h>
 #include <plat/clock.h>
 #include <plat/clock-clksrc.h>
 #include <plat/cpu.h>
@@ -53,7 +61,7 @@ int s3c2443_clkcon_enable_s(struct clk *clk, int enable)
  * elided as the EPLL can be either sourced by the XTAL or EXTCLK and as
  * such directly equating the two source clocks is impossible.
  */
-struct clk clk_mpllref = {
+static struct clk clk_mpllref = {
         .name           = "mpllref",
         .parent         = &clk_xtal,
 };
@@ -160,6 +168,44 @@ static struct clk clk_prediv = {
         },
 };
 
+/* hclk divider
+ *
+ * divides the prediv and provides the hclk.
+ */
+
+static unsigned long s3c2443_hclkdiv_getrate(struct clk *clk)
+{
+        unsigned long rate = clk_get_rate(clk->parent);
+        unsigned long clkdiv0 = __raw_readl(S3C2443_CLKDIV0);
+
+        clkdiv0 &= S3C2443_CLKDIV0_HCLKDIV_MASK;
+
+        return rate / (clkdiv0 + 1);
+}
+
+static struct clk_ops clk_h_ops = {
+        .get_rate       = s3c2443_hclkdiv_getrate,
+};
+
+/* pclk divider
+ *
+ * divides the hclk and provides the pclk.
+ */
+
+static unsigned long s3c2443_pclkdiv_getrate(struct clk *clk)
+{
+        unsigned long rate = clk_get_rate(clk->parent);
+        unsigned long clkdiv0 = __raw_readl(S3C2443_CLKDIV0);
+
+        clkdiv0 = ((clkdiv0 & S3C2443_CLKDIV0_HALF_PCLK) ? 1 : 0);
+
+        return rate / (clkdiv0 + 1);
+}
+
+static struct clk_ops clk_p_ops = {
+        .get_rate       = s3c2443_pclkdiv_getrate,
+};
+
 /* armdiv
  *
  * this clock is sourced from msysclk and can have a number of
@@ -516,26 +562,15 @@ static struct clk hsmmc1_clk = {
         .ctrlbit        = S3C2443_HCLKCON_HSMMC,
 };
 
-static inline unsigned long s3c2443_get_hdiv(unsigned long clkcon0)
-{
-        clkcon0 &= S3C2443_CLKDIV0_HCLKDIV_MASK;
-
-        return clkcon0 + 1;
-}
-
 /* EPLLCON compatible enough to get on/off information */
 
 void __init_or_cpufreq s3c2443_common_setup_clocks(pll_fn get_mpll)
 {
         unsigned long epllcon = __raw_readl(S3C2443_EPLLCON);
         unsigned long mpllcon = __raw_readl(S3C2443_MPLLCON);
-        unsigned long clkdiv0 = __raw_readl(S3C2443_CLKDIV0);
         struct clk *xtal_clk;
         unsigned long xtal;
         unsigned long pll;
-        unsigned long fclk;
-        unsigned long hclk;
-        unsigned long pclk;
         int ptr;
 
         xtal_clk = clk_get(NULL, "xtal");
@@ -544,18 +579,13 @@ void __init_or_cpufreq s3c2443_common_setup_clocks(pll_fn get_mpll)
 
         pll = get_mpll(mpllcon, xtal);
         clk_msysclk.clk.rate = pll;
-
-        fclk = clk_get_rate(&clk_armdiv);
-        hclk = s3c2443_prediv_getrate(&clk_prediv);
-        hclk /= s3c2443_get_hdiv(clkdiv0);
-        pclk = hclk / ((clkdiv0 & S3C2443_CLKDIV0_HALF_PCLK) ? 2 : 1);
-
-        s3c24xx_setup_clocks(fclk, hclk, pclk);
+        clk_mpll.rate = pll;
 
         printk("CPU: MPLL %s %ld.%03ld MHz, cpu %ld.%03ld MHz, mem %ld.%03ld MHz, pclk %ld.%03ld MHz\n",
-               (mpllcon & S3C2443_PLLCON_OFF) ? "off":"on",
-               print_mhz(pll), print_mhz(fclk),
-               print_mhz(hclk), print_mhz(pclk));
+               (mpllcon & S3C2443_PLLCON_OFF) ? "off" : "on",
+               print_mhz(pll), print_mhz(clk_get_rate(&clk_armdiv)),
+               print_mhz(clk_get_rate(&clk_h)),
+               print_mhz(clk_get_rate(&clk_p)));
 
         for (ptr = 0; ptr < ARRAY_SIZE(clksrc_clks); ptr++)
                 s3c_set_clksrc(&clksrc_clks[ptr], true);
@@ -568,7 +598,7 @@ void __init_or_cpufreq s3c2443_common_setup_clocks(pll_fn get_mpll)
         }
 
         printk("CPU: EPLL %s %ld.%03ld MHz, usb-bus %ld.%03ld MHz\n",
-               (epllcon & S3C2443_PLLCON_OFF) ? "off":"on",
+               (epllcon & S3C2443_PLLCON_OFF) ? "off" : "on",
                print_mhz(clk_get_rate(&clk_epll)),
                print_mhz(clk_get_rate(&clk_usb_bus)));
 }
@@ -611,9 +641,13 @@ void __init s3c2443_common_init_clocks(int xtal, pll_fn get_mpll,
         nr_armdiv = nr_divs;
         armdivmask = divmask;
 
-        /* s3c2443 parents h and p clocks from prediv */
+        /* s3c2443 parents h clock from prediv */
         clk_h.parent = &clk_prediv;
-        clk_p.parent = &clk_prediv;
+        clk_h.ops = &clk_h_ops;
+
+        /* and p clock from h clock */
+        clk_p.parent = &clk_h;
+        clk_p.ops = &clk_p_ops;
 
         clk_usb_bus.parent = &clk_usb_bus_host.clk;
         clk_epll.parent = &clk_epllref.clk;
diff --git a/arch/arm/plat-s3c24xx/common-smdk.c b/arch/arm/mach-s3c24xx/common-smdk.c
index 084604be6ad..084604be6ad 100644
--- a/arch/arm/plat-s3c24xx/common-smdk.c
+++ b/arch/arm/mach-s3c24xx/common-smdk.c
diff --git a/arch/arm/mach-s3c2410/dma.c b/arch/arm/mach-s3c24xx/dma-s3c2410.c
index 4803338cf56..4803338cf56 100644
--- a/arch/arm/mach-s3c2410/dma.c
+++ b/arch/arm/mach-s3c24xx/dma-s3c2410.c
diff --git a/arch/arm/mach-s3c2412/dma.c b/arch/arm/mach-s3c24xx/dma-s3c2412.c
index 38472ac920f..38472ac920f 100644
--- a/arch/arm/mach-s3c2412/dma.c
+++ b/arch/arm/mach-s3c24xx/dma-s3c2412.c
diff --git a/arch/arm/mach-s3c2440/dma.c b/arch/arm/mach-s3c24xx/dma-s3c2440.c
index 5f0a0c8ef84..5f0a0c8ef84 100644
--- a/arch/arm/mach-s3c2440/dma.c
+++ b/arch/arm/mach-s3c24xx/dma-s3c2440.c
diff --git a/arch/arm/mach-s3c2443/dma.c b/arch/arm/mach-s3c24xx/dma-s3c2443.c
index 14224517e62..e227c472a40 100644
--- a/arch/arm/mach-s3c2443/dma.c
+++ b/arch/arm/mach-s3c24xx/dma-s3c2443.c
@@ -51,7 +51,7 @@ static struct s3c24xx_dma_map __initdata s3c2443_dma_mappings[] = {
                 .name           = "xdreq1",
                 .channels       = MAP(S3C2443_DMAREQSEL_XDREQ1),
         },
-        [DMACH_SDI] = {
+        [DMACH_SDI] = { /* only on S3C2443 */
                 .name           = "sdi",
                 .channels       = MAP(S3C2443_DMAREQSEL_SDI),
         },
@@ -59,7 +59,7 @@ static struct s3c24xx_dma_map __initdata s3c2443_dma_mappings[] = {
                 .name           = "spi0",
                 .channels       = MAP(S3C2443_DMAREQSEL_SPI0TX),
         },
-        [DMACH_SPI1] = {
+        [DMACH_SPI1] = { /* only on S3C2443/S3C2450 */
                 .name           = "spi1",
                 .channels       = MAP(S3C2443_DMAREQSEL_SPI1TX),
         },
@@ -71,11 +71,11 @@ static struct s3c24xx_dma_map __initdata s3c2443_dma_mappings[] = {
                 .name           = "uart1",
                 .channels       = MAP(S3C2443_DMAREQSEL_UART1_0),
         },
-        [DMACH_UART2] = {
+        [DMACH_UART2] = {
                 .name           = "uart2",
                 .channels       = MAP(S3C2443_DMAREQSEL_UART2_0),
         },
-        [DMACH_UART3] = {
+        [DMACH_UART3] = {
                 .name           = "uart3",
                 .channels       = MAP(S3C2443_DMAREQSEL_UART3_0),
         },
@@ -87,11 +87,11 @@ static struct s3c24xx_dma_map __initdata s3c2443_dma_mappings[] = {
                 .name           = "uart1",
                 .channels       = MAP(S3C2443_DMAREQSEL_UART1_1),
         },
-        [DMACH_UART2_SRC2] = {
+        [DMACH_UART2_SRC2] = {
                 .name           = "uart2",
                 .channels       = MAP(S3C2443_DMAREQSEL_UART2_1),
         },
-        [DMACH_UART3_SRC2] = {
+        [DMACH_UART3_SRC2] = {
                 .name           = "uart3",
                 .channels       = MAP(S3C2443_DMAREQSEL_UART3_1),
         },
@@ -142,6 +142,23 @@ static int __init s3c2443_dma_add(struct device *dev,
         return s3c24xx_dma_init_map(&s3c2443_dma_sel);
 }
 
+#ifdef CONFIG_CPU_S3C2416
+/* S3C2416 DMA contains the same selection table as the S3C2443 */
+static struct subsys_interface s3c2416_dma_interface = {
+        .name           = "s3c2416_dma",
+        .subsys         = &s3c2416_subsys,
+        .add_dev        = s3c2443_dma_add,
+};
+
+static int __init s3c2416_dma_init(void)
+{
+        return subsys_interface_register(&s3c2416_dma_interface);
+}
+
+arch_initcall(s3c2416_dma_init);
+#endif
+
+#ifdef CONFIG_CPU_S3C2443
 static struct subsys_interface s3c2443_dma_interface = {
         .name           = "s3c2443_dma",
         .subsys         = &s3c2443_subsys,
@@ -154,3 +171,4 @@ static int __init s3c2443_dma_init(void)
 }
 
 arch_initcall(s3c2443_dma_init);
+#endif
diff --git a/arch/arm/mach-s3c2410/h1940-bluetooth.c b/arch/arm/mach-s3c24xx/h1940-bluetooth.c
index a5eeb62ce1c..a5eeb62ce1c 100644
--- a/arch/arm/mach-s3c2410/h1940-bluetooth.c
+++ b/arch/arm/mach-s3c24xx/h1940-bluetooth.c
diff --git a/arch/arm/mach-s3c2410/include/mach/anubis-cpld.h b/arch/arm/mach-s3c24xx/include/mach/anubis-cpld.h
index 1b614d5a81f..1b614d5a81f 100644
--- a/arch/arm/mach-s3c2410/include/mach/anubis-cpld.h
+++ b/arch/arm/mach-s3c24xx/include/mach/anubis-cpld.h
diff --git a/arch/arm/mach-s3c2410/include/mach/anubis-irq.h b/arch/arm/mach-s3c24xx/include/mach/anubis-irq.h
index a2a328134e3..a2a328134e3 100644
--- a/arch/arm/mach-s3c2410/include/mach/anubis-irq.h
+++ b/arch/arm/mach-s3c24xx/include/mach/anubis-irq.h
diff --git a/arch/arm/mach-s3c2410/include/mach/anubis-map.h b/arch/arm/mach-s3c24xx/include/mach/anubis-map.h
index c9deb3a5b2c..c9deb3a5b2c 100644
--- a/arch/arm/mach-s3c2410/include/mach/anubis-map.h
+++ b/arch/arm/mach-s3c24xx/include/mach/anubis-map.h
diff --git a/arch/arm/mach-s3c2410/include/mach/bast-cpld.h b/arch/arm/mach-s3c24xx/include/mach/bast-cpld.h
index bee2a7a932a..bee2a7a932a 100644
--- a/arch/arm/mach-s3c2410/include/mach/bast-cpld.h
+++ b/arch/arm/mach-s3c24xx/include/mach/bast-cpld.h
diff --git a/arch/arm/mach-s3c2410/include/mach/bast-irq.h b/arch/arm/mach-s3c24xx/include/mach/bast-irq.h
index cac428c42e7..cac428c42e7 100644
--- a/arch/arm/mach-s3c2410/include/mach/bast-irq.h
+++ b/arch/arm/mach-s3c24xx/include/mach/bast-irq.h
diff --git a/arch/arm/mach-s3c2410/include/mach/bast-map.h b/arch/arm/mach-s3c24xx/include/mach/bast-map.h
index 6e7dc9d0cf0..6e7dc9d0cf0 100644
--- a/arch/arm/mach-s3c2410/include/mach/bast-map.h
+++ b/arch/arm/mach-s3c24xx/include/mach/bast-map.h
diff --git a/arch/arm/mach-s3c2410/include/mach/bast-pmu.h b/arch/arm/mach-s3c24xx/include/mach/bast-pmu.h
index 4c38b39b741..4c38b39b741 100644
--- a/arch/arm/mach-s3c2410/include/mach/bast-pmu.h
+++ b/arch/arm/mach-s3c24xx/include/mach/bast-pmu.h
diff --git a/arch/arm/mach-s3c2410/include/mach/debug-macro.S b/arch/arm/mach-s3c24xx/include/mach/debug-macro.S
index 4135de87d1f..4135de87d1f 100644
--- a/arch/arm/mach-s3c2410/include/mach/debug-macro.S
+++ b/arch/arm/mach-s3c24xx/include/mach/debug-macro.S
diff --git a/arch/arm/mach-s3c2410/include/mach/dma.h b/arch/arm/mach-s3c24xx/include/mach/dma.h
index acbdfecd418..acbdfecd418 100644
--- a/arch/arm/mach-s3c2410/include/mach/dma.h
+++ b/arch/arm/mach-s3c24xx/include/mach/dma.h
diff --git a/arch/arm/mach-s3c2410/include/mach/entry-macro.S b/arch/arm/mach-s3c24xx/include/mach/entry-macro.S
index 473b3cd37d9..7615a14773f 100644
--- a/arch/arm/mach-s3c2410/include/mach/entry-macro.S
+++ b/arch/arm/mach-s3c24xx/include/mach/entry-macro.S
@@ -25,9 +25,6 @@
         .macro  get_irqnr_preamble, base, tmp
         .endm
 
-        .macro  arch_ret_to_user, tmp1, tmp2
-        .endm
-
         .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
 
                 mov     \base, #S3C24XX_VA_IRQ
@@ -71,8 +68,3 @@
                 @@ exit here, Z flag unset if IRQ
 
         .endm
-
-                /* currently don't need an disable_fiq macro */
-
-                .macro  disable_fiq
-                .endm
diff --git a/arch/arm/mach-s3c2410/include/mach/fb.h b/arch/arm/mach-s3c24xx/include/mach/fb.h
index a957bc8ed44..a957bc8ed44 100644
--- a/arch/arm/mach-s3c2410/include/mach/fb.h
+++ b/arch/arm/mach-s3c24xx/include/mach/fb.h
diff --git a/arch/arm/mach-s3c2410/include/mach/gpio-fns.h b/arch/arm/mach-s3c24xx/include/mach/gpio-fns.h
index c53ad34c657..c53ad34c657 100644
--- a/arch/arm/mach-s3c2410/include/mach/gpio-fns.h
+++ b/arch/arm/mach-s3c24xx/include/mach/gpio-fns.h
diff --git a/arch/arm/mach-s3c2410/include/mach/gpio-nrs.h b/arch/arm/mach-s3c24xx/include/mach/gpio-nrs.h
index 019ea86057f..019ea86057f 100644
--- a/arch/arm/mach-s3c2410/include/mach/gpio-nrs.h
+++ b/arch/arm/mach-s3c24xx/include/mach/gpio-nrs.h
diff --git a/arch/arm/mach-s3c2410/include/mach/gpio-track.h b/arch/arm/mach-s3c24xx/include/mach/gpio-track.h
index c410a078622..c410a078622 100644
--- a/arch/arm/mach-s3c2410/include/mach/gpio-track.h
+++ b/arch/arm/mach-s3c24xx/include/mach/gpio-track.h
diff --git a/arch/arm/mach-s3c2410/include/mach/gpio.h b/arch/arm/mach-s3c24xx/include/mach/gpio.h
index 6fac70f3484..6fac70f3484 100644
--- a/arch/arm/mach-s3c2410/include/mach/gpio.h
+++ b/arch/arm/mach-s3c24xx/include/mach/gpio.h
diff --git a/arch/arm/mach-s3c2440/include/mach/gta02.h b/arch/arm/mach-s3c24xx/include/mach/gta02.h
index 3a56a229cac..3a56a229cac 100644
--- a/arch/arm/mach-s3c2440/include/mach/gta02.h
+++ b/arch/arm/mach-s3c24xx/include/mach/gta02.h
diff --git a/arch/arm/mach-s3c2410/include/mach/h1940-latch.h b/arch/arm/mach-s3c24xx/include/mach/h1940-latch.h
index fc897d3a056..fc897d3a056 100644
--- a/arch/arm/mach-s3c2410/include/mach/h1940-latch.h
+++ b/arch/arm/mach-s3c24xx/include/mach/h1940-latch.h
diff --git a/arch/arm/mach-s3c2410/include/mach/h1940.h b/arch/arm/mach-s3c24xx/include/mach/h1940.h
index 2aa683c8d3d..2aa683c8d3d 100644
--- a/arch/arm/mach-s3c2410/include/mach/h1940.h
+++ b/arch/arm/mach-s3c24xx/include/mach/h1940.h
diff --git a/arch/arm/mach-s3c2410/include/mach/hardware.h b/arch/arm/mach-s3c24xx/include/mach/hardware.h
index aef5631eac5..aef5631eac5 100644
--- a/arch/arm/mach-s3c2410/include/mach/hardware.h
+++ b/arch/arm/mach-s3c24xx/include/mach/hardware.h
diff --git a/arch/arm/mach-s3c2410/include/mach/idle.h b/arch/arm/mach-s3c24xx/include/mach/idle.h
index e9ddd706b16..e9ddd706b16 100644
--- a/arch/arm/mach-s3c2410/include/mach/idle.h
+++ b/arch/arm/mach-s3c24xx/include/mach/idle.h
diff --git a/arch/arm/mach-s3c2410/include/mach/io.h b/arch/arm/mach-s3c24xx/include/mach/io.h
index 118749f37c4..118749f37c4 100644
--- a/arch/arm/mach-s3c2410/include/mach/io.h
+++ b/arch/arm/mach-s3c24xx/include/mach/io.h
diff --git a/arch/arm/mach-s3c2410/include/mach/irqs.h b/arch/arm/mach-s3c24xx/include/mach/irqs.h
index e53b2177319..e53b2177319 100644
--- a/arch/arm/mach-s3c2410/include/mach/irqs.h
+++ b/arch/arm/mach-s3c24xx/include/mach/irqs.h
diff --git a/arch/arm/mach-s3c2410/include/mach/leds-gpio.h b/arch/arm/mach-s3c24xx/include/mach/leds-gpio.h
index d8a7672519b..d8a7672519b 100644
--- a/arch/arm/mach-s3c2410/include/mach/leds-gpio.h
+++ b/arch/arm/mach-s3c24xx/include/mach/leds-gpio.h
diff --git a/arch/arm/mach-s3c2410/include/mach/map.h b/arch/arm/mach-s3c24xx/include/mach/map.h
index 78ae807f128..78ae807f128 100644
--- a/arch/arm/mach-s3c2410/include/mach/map.h
+++ b/arch/arm/mach-s3c24xx/include/mach/map.h
diff --git a/arch/arm/mach-s3c2410/include/mach/osiris-cpld.h b/arch/arm/mach-s3c24xx/include/mach/osiris-cpld.h
index e9e36b0abba..e9e36b0abba 100644
--- a/arch/arm/mach-s3c2410/include/mach/osiris-cpld.h
+++ b/arch/arm/mach-s3c24xx/include/mach/osiris-cpld.h
diff --git a/arch/arm/mach-s3c2410/include/mach/osiris-map.h b/arch/arm/mach-s3c24xx/include/mach/osiris-map.h
index 17380f84842..17380f84842 100644
--- a/arch/arm/mach-s3c2410/include/mach/osiris-map.h
+++ b/arch/arm/mach-s3c24xx/include/mach/osiris-map.h
diff --git a/arch/arm/mach-s3c2410/include/mach/otom-map.h b/arch/arm/mach-s3c24xx/include/mach/otom-map.h
index f9277a52c14..f9277a52c14 100644
--- a/arch/arm/mach-s3c2410/include/mach/otom-map.h
+++ b/arch/arm/mach-s3c24xx/include/mach/otom-map.h
diff --git a/arch/arm/mach-s3c2410/include/mach/pm-core.h b/arch/arm/mach-s3c24xx/include/mach/pm-core.h
index 2eef7e6f767..2eef7e6f767 100644
--- a/arch/arm/mach-s3c2410/include/mach/pm-core.h
+++ b/arch/arm/mach-s3c24xx/include/mach/pm-core.h
diff --git a/arch/arm/mach-s3c2410/include/mach/regs-clock.h b/arch/arm/mach-s3c24xx/include/mach/regs-clock.h
index 3415b60082d..3415b60082d 100644
--- a/arch/arm/mach-s3c2410/include/mach/regs-clock.h
+++ b/arch/arm/mach-s3c24xx/include/mach/regs-clock.h
diff --git a/arch/arm/mach-s3c2410/include/mach/regs-dsc.h b/arch/arm/mach-s3c24xx/include/mach/regs-dsc.h
index 98fd4a05587..98fd4a05587 100644
--- a/arch/arm/mach-s3c2410/include/mach/regs-dsc.h
+++ b/arch/arm/mach-s3c24xx/include/mach/regs-dsc.h
diff --git a/arch/arm/mach-s3c2410/include/mach/regs-gpio.h b/arch/arm/mach-s3c24xx/include/mach/regs-gpio.h
index cac1ad6b582..cac1ad6b582 100644
--- a/arch/arm/mach-s3c2410/include/mach/regs-gpio.h
+++ b/arch/arm/mach-s3c24xx/include/mach/regs-gpio.h
diff --git a/arch/arm/mach-s3c2410/include/mach/regs-gpioj.h b/arch/arm/mach-s3c24xx/include/mach/regs-gpioj.h
index 19575e06111..19575e06111 100644
--- a/arch/arm/mach-s3c2410/include/mach/regs-gpioj.h
+++ b/arch/arm/mach-s3c24xx/include/mach/regs-gpioj.h
diff --git a/arch/arm/mach-s3c2410/include/mach/regs-irq.h b/arch/arm/mach-s3c24xx/include/mach/regs-irq.h
index 0f07ba30b1f..0f07ba30b1f 100644
--- a/arch/arm/mach-s3c2410/include/mach/regs-irq.h
+++ b/arch/arm/mach-s3c24xx/include/mach/regs-irq.h
diff --git a/arch/arm/mach-s3c2410/include/mach/regs-lcd.h b/arch/arm/mach-s3c24xx/include/mach/regs-lcd.h
index ee8f040aff5..ee8f040aff5 100644
--- a/arch/arm/mach-s3c2410/include/mach/regs-lcd.h
+++ b/arch/arm/mach-s3c24xx/include/mach/regs-lcd.h
diff --git a/arch/arm/mach-s3c2410/include/mach/regs-mem.h b/arch/arm/mach-s3c24xx/include/mach/regs-mem.h
index e0c67b0163d..e0c67b0163d 100644
--- a/arch/arm/mach-s3c2410/include/mach/regs-mem.h
+++ b/arch/arm/mach-s3c24xx/include/mach/regs-mem.h
diff --git a/arch/arm/mach-s3c2410/include/mach/regs-power.h b/arch/arm/mach-s3c24xx/include/mach/regs-power.h
index 4932b87bdf3..4932b87bdf3 100644
--- a/arch/arm/mach-s3c2410/include/mach/regs-power.h
+++ b/arch/arm/mach-s3c24xx/include/mach/regs-power.h
diff --git a/arch/arm/mach-s3c2410/include/mach/regs-s3c2412-mem.h b/arch/arm/mach-s3c24xx/include/mach/regs-s3c2412-mem.h
index fb635251509..fb635251509 100644
--- a/arch/arm/mach-s3c2410/include/mach/regs-s3c2412-mem.h
+++ b/arch/arm/mach-s3c24xx/include/mach/regs-s3c2412-mem.h
diff --git a/arch/arm/mach-s3c2410/include/mach/regs-s3c2412.h b/arch/arm/mach-s3c24xx/include/mach/regs-s3c2412.h
index aa69dc79bc3..aa69dc79bc3 100644
--- a/arch/arm/mach-s3c2410/include/mach/regs-s3c2412.h
+++ b/arch/arm/mach-s3c24xx/include/mach/regs-s3c2412.h
diff --git a/arch/arm/mach-s3c2410/include/mach/regs-s3c2416-mem.h b/arch/arm/mach-s3c24xx/include/mach/regs-s3c2416-mem.h
index 2f31b74974a..2f31b74974a 100644
--- a/arch/arm/mach-s3c2410/include/mach/regs-s3c2416-mem.h
+++ b/arch/arm/mach-s3c24xx/include/mach/regs-s3c2416-mem.h
diff --git a/arch/arm/mach-s3c2410/include/mach/regs-s3c2416.h b/arch/arm/mach-s3c24xx/include/mach/regs-s3c2416.h
index e443167efb8..e443167efb8 100644
--- a/arch/arm/mach-s3c2410/include/mach/regs-s3c2416.h
+++ b/arch/arm/mach-s3c24xx/include/mach/regs-s3c2416.h
diff --git a/arch/arm/mach-s3c2410/include/mach/regs-s3c2443-clock.h b/arch/arm/mach-s3c24xx/include/mach/regs-s3c2443-clock.h
index c3feff3c048..c3feff3c048 100644
--- a/arch/arm/mach-s3c2410/include/mach/regs-s3c2443-clock.h
+++ b/arch/arm/mach-s3c24xx/include/mach/regs-s3c2443-clock.h
diff --git a/arch/arm/mach-s3c2410/include/mach/regs-sdi.h b/arch/arm/mach-s3c24xx/include/mach/regs-sdi.h
index cbf2d8884e3..cbf2d8884e3 100644
--- a/arch/arm/mach-s3c2410/include/mach/regs-sdi.h
+++ b/arch/arm/mach-s3c24xx/include/mach/regs-sdi.h
diff --git a/arch/arm/mach-s3c2410/include/mach/tick.h b/arch/arm/mach-s3c24xx/include/mach/tick.h
index 544da41979d..544da41979d 100644
--- a/arch/arm/mach-s3c2410/include/mach/tick.h
+++ b/arch/arm/mach-s3c24xx/include/mach/tick.h
diff --git a/arch/arm/mach-s3c2410/include/mach/timex.h b/arch/arm/mach-s3c24xx/include/mach/timex.h
index fe9ca1ffd51..fe9ca1ffd51 100644
--- a/arch/arm/mach-s3c2410/include/mach/timex.h
+++ b/arch/arm/mach-s3c24xx/include/mach/timex.h
diff --git a/arch/arm/mach-s3c2410/include/mach/uncompress.h b/arch/arm/mach-s3c24xx/include/mach/uncompress.h
index 8b283f847da..8b283f847da 100644
--- a/arch/arm/mach-s3c2410/include/mach/uncompress.h
+++ b/arch/arm/mach-s3c24xx/include/mach/uncompress.h
diff --git a/arch/arm/mach-s3c2410/include/mach/vr1000-cpld.h b/arch/arm/mach-s3c24xx/include/mach/vr1000-cpld.h
index e4119913d7c..e4119913d7c 100644
--- a/arch/arm/mach-s3c2410/include/mach/vr1000-cpld.h
+++ b/arch/arm/mach-s3c24xx/include/mach/vr1000-cpld.h
diff --git a/arch/arm/mach-s3c2410/include/mach/vr1000-irq.h b/arch/arm/mach-s3c24xx/include/mach/vr1000-irq.h
index 47add133b8e..47add133b8e 100644
--- a/arch/arm/mach-s3c2410/include/mach/vr1000-irq.h
+++ b/arch/arm/mach-s3c24xx/include/mach/vr1000-irq.h
diff --git a/arch/arm/mach-s3c2410/include/mach/vr1000-map.h b/arch/arm/mach-s3c24xx/include/mach/vr1000-map.h
index 99612fcc4eb..99612fcc4eb 100644
--- a/arch/arm/mach-s3c2410/include/mach/vr1000-map.h
+++ b/arch/arm/mach-s3c24xx/include/mach/vr1000-map.h
diff --git a/arch/arm/mach-s3c2412/irq.c b/arch/arm/mach-s3c24xx/irq-s3c2412.c
index e65619ddbcc..e65619ddbcc 100644
--- a/arch/arm/mach-s3c2412/irq.c
+++ b/arch/arm/mach-s3c24xx/irq-s3c2412.c
diff --git a/arch/arm/mach-s3c2416/irq.c b/arch/arm/mach-s3c24xx/irq-s3c2416.c
index fd49f35e448..fd49f35e448 100644
--- a/arch/arm/mach-s3c2416/irq.c
+++ b/arch/arm/mach-s3c24xx/irq-s3c2416.c
diff --git a/arch/arm/mach-s3c2440/irq.c b/arch/arm/mach-s3c24xx/irq-s3c2440.c
index 4a18cde439c..4a18cde439c 100644
--- a/arch/arm/mach-s3c2440/irq.c
+++ b/arch/arm/mach-s3c24xx/irq-s3c2440.c
diff --git a/arch/arm/mach-s3c2443/irq.c b/arch/arm/mach-s3c24xx/irq-s3c2443.c
index ac2829f56d1..ac2829f56d1 100644
--- a/arch/arm/mach-s3c2443/irq.c
+++ b/arch/arm/mach-s3c24xx/irq-s3c2443.c
diff --git a/arch/arm/mach-s3c2440/s3c244x-irq.c b/arch/arm/mach-s3c24xx/irq-s3c244x.c
index 5fe8e58d3af..5fe8e58d3af 100644
--- a/arch/arm/mach-s3c2440/s3c244x-irq.c
+++ b/arch/arm/mach-s3c24xx/irq-s3c244x.c
diff --git a/arch/arm/mach-s3c2410/mach-amlm5900.c b/arch/arm/mach-s3c24xx/mach-amlm5900.c
index 4220cc60de3..4220cc60de3 100644
--- a/arch/arm/mach-s3c2410/mach-amlm5900.c
+++ b/arch/arm/mach-s3c24xx/mach-amlm5900.c
diff --git a/arch/arm/mach-s3c2440/mach-anubis.c b/arch/arm/mach-s3c24xx/mach-anubis.c
index 19b577bc09b..60c72c54c21 100644
--- a/arch/arm/mach-s3c2440/mach-anubis.c
+++ b/arch/arm/mach-s3c24xx/mach-anubis.c
@@ -55,6 +55,7 @@
 #include <plat/cpu.h>
 #include <plat/audio-simtec.h>
 
+#include "simtec.h"
 #include "common.h"
 
 #define COPYRIGHT ", Copyright 2005-2009 Simtec Electronics"
diff --git a/arch/arm/mach-s3c2440/mach-at2440evb.c b/arch/arm/mach-s3c24xx/mach-at2440evb.c
index d7ae49c9011..d7ae49c9011 100644
--- a/arch/arm/mach-s3c2440/mach-at2440evb.c
+++ b/arch/arm/mach-s3c24xx/mach-at2440evb.c
diff --git a/arch/arm/mach-s3c2410/mach-bast.c b/arch/arm/mach-s3c24xx/mach-bast.c
index feeaf73933d..53219c02eca 100644
--- a/arch/arm/mach-s3c2410/mach-bast.c
+++ b/arch/arm/mach-s3c24xx/mach-bast.c
@@ -64,8 +64,7 @@
 #include <plat/gpio-cfg.h>
 #include <plat/audio-simtec.h>
 
-#include "usb-simtec.h"
-#include "nor-simtec.h"
+#include "simtec.h"
 #include "common.h"
 
 #define COPYRIGHT ", Copyright 2004-2008 Simtec Electronics"
diff --git a/arch/arm/mach-s3c2440/mach-gta02.c b/arch/arm/mach-s3c24xx/mach-gta02.c
index 9a4a5bc008e..ba5d8539410 100644
--- a/arch/arm/mach-s3c2440/mach-gta02.c
+++ b/arch/arm/mach-s3c24xx/mach-gta02.c
@@ -38,6 +38,7 @@
 #include <linux/platform_device.h>
 #include <linux/serial_core.h>
 #include <linux/spi/spi.h>
+#include <linux/spi/s3c24xx.h>
 
 #include <linux/mmc/host.h>
 
@@ -73,7 +74,6 @@
 #include <mach/regs-gpioj.h>
 #include <mach/fb.h>
 
-#include <mach/spi.h>
 #include <plat/usb-control.h>
 #include <mach/regs-mem.h>
 #include <mach/hardware.h>
@@ -258,7 +258,7 @@ static struct pcf50633_bl_platform_data gta02_backlight_data = {
         .ramp_time = 5,
 };
 
-struct pcf50633_platform_data gta02_pcf_pdata = {
+static struct pcf50633_platform_data gta02_pcf_pdata = {
         .resumers = {
                 [0] =   PCF50633_INT1_USBINS |
                         PCF50633_INT1_USBREM |
@@ -404,7 +404,7 @@ static struct platform_device gta02_nor_flash = {
 };
 
 
-struct platform_device s3c24xx_pwm_device = {
+static struct platform_device s3c24xx_pwm_device = {
         .name           = "s3c24xx_pwm",
         .num_resources  = 0,
 };
diff --git a/arch/arm/mach-s3c2410/mach-h1940.c b/arch/arm/mach-s3c24xx/mach-h1940.c
index 41245a60398..6b21ba107ea 100644
--- a/arch/arm/mach-s3c2410/mach-h1940.c
+++ b/arch/arm/mach-s3c24xx/mach-h1940.c
@@ -162,7 +162,7 @@ static int h1940_gpiolib_latch_get(struct gpio_chip *chip,
         return (latch_state >> (offset + 16)) & 1;
 }
 
-struct gpio_chip h1940_latch_gpiochip = {
+static struct gpio_chip h1940_latch_gpiochip = {
         .base                   = H1940_LATCH_GPIO(0),
         .owner                  = THIS_MODULE,
         .label                  = "H1940_LATCH",
@@ -304,7 +304,7 @@ static const struct s3c_adc_bat_thresh bat_lut_acin[] = {
         { .volt = 3841, .cur = 0, .level = 0},
 };
 
-int h1940_bat_init(void)
+static int h1940_bat_init(void)
 {
         int ret;
 
@@ -317,17 +317,17 @@ int h1940_bat_init(void)
 
 }
 
-void h1940_bat_exit(void)
+static void h1940_bat_exit(void)
 {
         gpio_free(H1940_LATCH_SM803_ENABLE);
 }
 
-void h1940_enable_charger(void)
+static void h1940_enable_charger(void)
 {
         gpio_set_value(H1940_LATCH_SM803_ENABLE, 1);
 }
 
-void h1940_disable_charger(void)
+static void h1940_disable_charger(void)
 {
         gpio_set_value(H1940_LATCH_SM803_ENABLE, 0);
 }
@@ -364,7 +364,7 @@ static struct platform_device h1940_battery = {
         },
 };
 
-DEFINE_SPINLOCK(h1940_blink_spin);
+static DEFINE_SPINLOCK(h1940_blink_spin);
 
 int h1940_led_blink_set(unsigned gpio, int state,
         unsigned long *delay_on, unsigned long *delay_off)
diff --git a/arch/arm/mach-s3c2412/mach-jive.c b/arch/arm/mach-s3c24xx/mach-jive.c
index ae73ba34ecc..ae73ba34ecc 100644
--- a/arch/arm/mach-s3c2412/mach-jive.c
+++ b/arch/arm/mach-s3c24xx/mach-jive.c
diff --git a/arch/arm/mach-s3c2440/mach-mini2440.c b/arch/arm/mach-s3c24xx/mach-mini2440.c
index 5d66fb218a4..5d66fb218a4 100644
--- a/arch/arm/mach-s3c2440/mach-mini2440.c
+++ b/arch/arm/mach-s3c24xx/mach-mini2440.c
diff --git a/arch/arm/mach-s3c2410/mach-n30.c b/arch/arm/mach-s3c24xx/mach-n30.c
index 383d00ca8f6..383d00ca8f6 100644
--- a/arch/arm/mach-s3c2410/mach-n30.c
+++ b/arch/arm/mach-s3c24xx/mach-n30.c
diff --git a/arch/arm/mach-s3c2440/mach-nexcoder.c b/arch/arm/mach-s3c24xx/mach-nexcoder.c
index 5198e3e1c5b..5198e3e1c5b 100644
--- a/arch/arm/mach-s3c2440/mach-nexcoder.c
+++ b/arch/arm/mach-s3c24xx/mach-nexcoder.c
diff --git a/arch/arm/mach-s3c2440/mach-osiris-dvs.c b/arch/arm/mach-s3c24xx/mach-osiris-dvs.c
index ad2792dfbee..ad2792dfbee 100644
--- a/arch/arm/mach-s3c2440/mach-osiris-dvs.c
+++ b/arch/arm/mach-s3c24xx/mach-osiris-dvs.c
diff --git a/arch/arm/mach-s3c2440/mach-osiris.c b/arch/arm/mach-s3c24xx/mach-osiris.c
index c5daeb612a8..c5daeb612a8 100644
--- a/arch/arm/mach-s3c2440/mach-osiris.c
+++ b/arch/arm/mach-s3c24xx/mach-osiris.c
diff --git a/arch/arm/mach-s3c2410/mach-otom.c b/arch/arm/mach-s3c24xx/mach-otom.c
index 5f1e0eeb38a..5f1e0eeb38a 100644
--- a/arch/arm/mach-s3c2410/mach-otom.c
+++ b/arch/arm/mach-s3c24xx/mach-otom.c
diff --git a/arch/arm/mach-s3c2410/mach-qt2410.c b/arch/arm/mach-s3c24xx/mach-qt2410.c
index 91c16d9d245..91c16d9d245 100644
--- a/arch/arm/mach-s3c2410/mach-qt2410.c
+++ b/arch/arm/mach-s3c24xx/mach-qt2410.c
diff --git a/arch/arm/mach-s3c2440/mach-rx1950.c b/arch/arm/mach-s3c24xx/mach-rx1950.c
index 6f68abf44fa..200debb4c72 100644
--- a/arch/arm/mach-s3c2440/mach-rx1950.c
+++ b/arch/arm/mach-s3c24xx/mach-rx1950.c
@@ -217,7 +217,7 @@ static const struct s3c_adc_bat_thresh bat_lut_acin[] = {
         { .volt = 3820, .cur = 0, .level = 0},
 };
 
-int rx1950_bat_init(void)
+static int rx1950_bat_init(void)
 {
         int ret;
 
@@ -236,25 +236,25 @@ err_gpio1:
         return ret;
 }
 
-void rx1950_bat_exit(void)
+static void rx1950_bat_exit(void)
 {
         gpio_free(S3C2410_GPJ(2));
         gpio_free(S3C2410_GPJ(3));
 }
 
-void rx1950_enable_charger(void)
+static void rx1950_enable_charger(void)
 {
         gpio_direction_output(S3C2410_GPJ(2), 1);
         gpio_direction_output(S3C2410_GPJ(3), 1);
 }
 
-void rx1950_disable_charger(void)
+static void rx1950_disable_charger(void)
 {
         gpio_direction_output(S3C2410_GPJ(2), 0);
         gpio_direction_output(S3C2410_GPJ(3), 0);
 }
 
-DEFINE_SPINLOCK(rx1950_blink_spin);
+static DEFINE_SPINLOCK(rx1950_blink_spin);
 
 static int rx1950_led_blink_set(unsigned gpio, int state,
         unsigned long *delay_on, unsigned long *delay_off)
@@ -382,7 +382,7 @@ static struct s3c2410fb_mach_info rx1950_lcd_cfg = {
 
 static struct pwm_device *lcd_pwm;
 
-void rx1950_lcd_power(int enable)
+static void rx1950_lcd_power(int enable)
 {
         int i;
         static int enabled;
diff --git a/arch/arm/mach-s3c2440/mach-rx3715.c b/arch/arm/mach-s3c24xx/mach-rx3715.c
index 56af3544759..56af3544759 100644
--- a/arch/arm/mach-s3c2440/mach-rx3715.c
+++ b/arch/arm/mach-s3c24xx/mach-rx3715.c
diff --git a/arch/arm/mach-s3c2410/mach-smdk2410.c b/arch/arm/mach-s3c24xx/mach-smdk2410.c
index bdc27e77287..bdc27e77287 100644
--- a/arch/arm/mach-s3c2410/mach-smdk2410.c
+++ b/arch/arm/mach-s3c24xx/mach-smdk2410.c
diff --git a/arch/arm/mach-s3c2412/mach-smdk2413.c b/arch/arm/mach-s3c24xx/mach-smdk2413.c
index b11451b853d..b11451b853d 100644
--- a/arch/arm/mach-s3c2412/mach-smdk2413.c
+++ b/arch/arm/mach-s3c24xx/mach-smdk2413.c
diff --git a/arch/arm/mach-s3c2416/mach-smdk2416.c b/arch/arm/mach-s3c24xx/mach-smdk2416.c
index eebe1e72b93..30a44f806e0 100644
--- a/arch/arm/mach-s3c2416/mach-smdk2416.c
+++ b/arch/arm/mach-s3c24xx/mach-smdk2416.c
@@ -125,7 +125,7 @@ static struct s3c2410_uartcfg smdk2416_uartcfgs[] __initdata = {
         }
 };
 
-void smdk2416_hsudc_gpio_init(void)
+static void smdk2416_hsudc_gpio_init(void)
 {
         s3c_gpio_setpull(S3C2410_GPH(14), S3C_GPIO_PULL_UP);
         s3c_gpio_setpull(S3C2410_GPF(2), S3C_GPIO_PULL_NONE);
@@ -133,20 +133,20 @@ void smdk2416_hsudc_gpio_init(void)
         s3c2410_modify_misccr(S3C2416_MISCCR_SEL_SUSPND, 0);
 }
 
-void smdk2416_hsudc_gpio_uninit(void)
+static void smdk2416_hsudc_gpio_uninit(void)
 {
         s3c2410_modify_misccr(S3C2416_MISCCR_SEL_SUSPND, 1);
         s3c_gpio_setpull(S3C2410_GPH(14), S3C_GPIO_PULL_NONE);
         s3c_gpio_cfgpin(S3C2410_GPH(14), S3C_GPIO_SFN(0));
 }
 
-struct s3c24xx_hsudc_platdata smdk2416_hsudc_platdata = {
+static struct s3c24xx_hsudc_platdata smdk2416_hsudc_platdata = {
         .epnum = 9,
         .gpio_init = smdk2416_hsudc_gpio_init,
         .gpio_uninit = smdk2416_hsudc_gpio_uninit,
 };
 
-struct s3c_fb_pd_win smdk2416_fb_win[] = {
+static struct s3c_fb_pd_win smdk2416_fb_win[] = {
         [0] = {
                 /* think this is the same as the smdk6410 */
                 .win_mode       = {
diff --git a/arch/arm/mach-s3c2440/mach-smdk2440.c b/arch/arm/mach-s3c24xx/mach-smdk2440.c
index 83a1036d7dc..83a1036d7dc 100644
--- a/arch/arm/mach-s3c2440/mach-smdk2440.c
+++ b/arch/arm/mach-s3c24xx/mach-smdk2440.c
diff --git a/arch/arm/mach-s3c2443/mach-smdk2443.c b/arch/arm/mach-s3c24xx/mach-smdk2443.c
index 20923695622..20923695622 100644
--- a/arch/arm/mach-s3c2443/mach-smdk2443.c
+++ b/arch/arm/mach-s3c24xx/mach-smdk2443.c
diff --git a/arch/arm/mach-s3c2410/mach-tct_hammer.c b/arch/arm/mach-s3c24xx/mach-tct_hammer.c
index 1114666f0ef..1114666f0ef 100644
--- a/arch/arm/mach-s3c2410/mach-tct_hammer.c
+++ b/arch/arm/mach-s3c24xx/mach-tct_hammer.c
diff --git a/arch/arm/mach-s3c2410/mach-vr1000.c b/arch/arm/mach-s3c24xx/mach-vr1000.c
index dbe668a803e..87608d45dac 100644
--- a/arch/arm/mach-s3c2410/mach-vr1000.c
+++ b/arch/arm/mach-s3c24xx/mach-vr1000.c
@@ -51,8 +51,7 @@
 #include <plat/iic.h>
 #include <plat/audio-simtec.h>
 
-#include "usb-simtec.h"
-#include "nor-simtec.h"
+#include "simtec.h"
 #include "common.h"
 
 /* macros for virtual address mods for the io space entries */
diff --git a/arch/arm/mach-s3c2412/mach-vstms.c b/arch/arm/mach-s3c24xx/mach-vstms.c
index 94bfaa1fb14..94bfaa1fb14 100644
--- a/arch/arm/mach-s3c2412/mach-vstms.c
+++ b/arch/arm/mach-s3c24xx/mach-vstms.c
diff --git a/arch/arm/mach-s3c2410/pm-h1940.S b/arch/arm/mach-s3c24xx/pm-h1940.S
index c93bf2db9f4..c93bf2db9f4 100644
--- a/arch/arm/mach-s3c2410/pm-h1940.S
+++ b/arch/arm/mach-s3c24xx/pm-h1940.S
diff --git a/arch/arm/mach-s3c2410/pm.c b/arch/arm/mach-s3c24xx/pm-s3c2410.c
index 03f706dd600..03f706dd600 100644
--- a/arch/arm/mach-s3c2410/pm.c
+++ b/arch/arm/mach-s3c24xx/pm-s3c2410.c
diff --git a/arch/arm/mach-s3c2412/pm.c b/arch/arm/mach-s3c24xx/pm-s3c2412.c
index d04588506ec..d04588506ec 100644
--- a/arch/arm/mach-s3c2412/pm.c
+++ b/arch/arm/mach-s3c24xx/pm-s3c2412.c
diff --git a/arch/arm/mach-s3c2416/pm.c b/arch/arm/mach-s3c24xx/pm-s3c2416.c
index 1bd4817b8eb..1bd4817b8eb 100644
--- a/arch/arm/mach-s3c2416/pm.c
+++ b/arch/arm/mach-s3c24xx/pm-s3c2416.c
diff --git a/arch/arm/mach-s3c2410/s3c2410.c b/arch/arm/mach-s3c24xx/s3c2410.c
index 061b6bb1a55..061b6bb1a55 100644
--- a/arch/arm/mach-s3c2410/s3c2410.c
+++ b/arch/arm/mach-s3c24xx/s3c2410.c
diff --git a/arch/arm/mach-s3c2412/s3c2412.c b/arch/arm/mach-s3c24xx/s3c2412.c
index aff6e85a97c..c6eac987109 100644
--- a/arch/arm/mach-s3c2412/s3c2412.c
+++ b/arch/arm/mach-s3c24xx/s3c2412.c
@@ -32,8 +32,6 @@
 #include <asm/proc-fns.h>
 #include <asm/irq.h>
 
-#include <mach/idle.h>
-
 #include <plat/cpu-freq.h>
 
 #include <mach/regs-clock.h>
@@ -164,7 +162,7 @@ void __init s3c2412_map_io(void)
 
         /* set our idle function */
 
-        s3c24xx_idle = s3c2412_idle;
+        arm_pm_idle = s3c2412_idle;
 
         /* register our io-tables */
 
diff --git a/arch/arm/mach-s3c2416/s3c2416.c b/arch/arm/mach-s3c24xx/s3c2416.c
index 5287d2808d3..0e9a71c90ed 100644
--- a/arch/arm/mach-s3c2416/s3c2416.c
+++ b/arch/arm/mach-s3c24xx/s3c2416.c
@@ -44,7 +44,6 @@
 #include <asm/proc-fns.h>
 #include <asm/irq.h>
 
-#include <mach/idle.h>
 #include <mach/regs-s3c2443-clock.h>
 
 #include <plat/gpio-core.h>
@@ -60,6 +59,7 @@
 #include <plat/fb-core.h>
 #include <plat/nand-core.h>
 #include <plat/adc-core.h>
+#include <plat/rtc-core.h>
 
 static struct map_desc s3c2416_iodesc[] __initdata = {
         IODESC_ENT(WATCHDOG),
@@ -88,8 +88,6 @@ int __init s3c2416_init(void)
 {
         printk(KERN_INFO "S3C2416: Initializing architecture\n");
 
-        /* s3c24xx_idle = s3c2416_idle; */
-
         /* change WDT IRQ number */
         s3c_device_wdt.resource[1].start = IRQ_S3C2443_WDT;
         s3c_device_wdt.resource[1].end   = IRQ_S3C2443_WDT;
@@ -101,6 +99,7 @@ int __init s3c2416_init(void)
         s3c_fb_setname("s3c2443-fb");
 
         s3c_adc_setname("s3c2416-adc");
+        s3c_rtc_setname("s3c2416-rtc");
 
 #ifdef CONFIG_PM
         register_syscore_ops(&s3c2416_pm_syscore_ops);
diff --git a/arch/arm/mach-s3c2440/s3c2440.c b/arch/arm/mach-s3c24xx/s3c2440.c
index 2b3dddb49af..2b3dddb49af 100644
--- a/arch/arm/mach-s3c2440/s3c2440.c
+++ b/arch/arm/mach-s3c24xx/s3c2440.c
diff --git a/arch/arm/mach-s3c2440/s3c2442.c b/arch/arm/mach-s3c24xx/s3c2442.c
index 22cb7c94a8c..22cb7c94a8c 100644
--- a/arch/arm/mach-s3c2440/s3c2442.c
+++ b/arch/arm/mach-s3c24xx/s3c2442.c
diff --git a/arch/arm/mach-s3c2443/s3c2443.c b/arch/arm/mach-s3c24xx/s3c2443.c
index b9deaeb0dff..b7778a9dafa 100644
--- a/arch/arm/mach-s3c2443/s3c2443.c
+++ b/arch/arm/mach-s3c24xx/s3c2443.c
@@ -41,6 +41,7 @@
 #include <plat/fb-core.h>
 #include <plat/nand-core.h>
 #include <plat/adc-core.h>
+#include <plat/rtc-core.h>
 
 static struct map_desc s3c2443_iodesc[] __initdata = {
         IODESC_ENT(WATCHDOG),
@@ -73,6 +74,7 @@ int __init s3c2443_init(void)
         s3c_fb_setname("s3c2443-fb");
 
         s3c_adc_setname("s3c2443-adc");
+        s3c_rtc_setname("s3c2443-rtc");
 
         /* change WDT IRQ number */
         s3c_device_wdt.resource[1].start = IRQ_S3C2443_WDT;
diff --git a/arch/arm/mach-s3c2440/s3c244x.c b/arch/arm/mach-s3c24xx/s3c244x.c
index d15852f642b..d15852f642b 100644
--- a/arch/arm/mach-s3c2440/s3c244x.c
+++ b/arch/arm/mach-s3c24xx/s3c244x.c
diff --git a/arch/arm/plat-s3c24xx/setup-i2c.c b/arch/arm/mach-s3c24xx/setup-i2c.c
index 9e90a7cbd1d..9e90a7cbd1d 100644
--- a/arch/arm/plat-s3c24xx/setup-i2c.c
+++ b/arch/arm/mach-s3c24xx/setup-i2c.c
diff --git a/arch/arm/mach-s3c2416/setup-sdhci-gpio.c b/arch/arm/mach-s3c24xx/setup-sdhci-gpio.c
index f65cb3ef16c..f65cb3ef16c 100644
--- a/arch/arm/mach-s3c2416/setup-sdhci-gpio.c
+++ b/arch/arm/mach-s3c24xx/setup-sdhci-gpio.c
diff --git a/arch/arm/plat-s3c24xx/setup-ts.c b/arch/arm/mach-s3c24xx/setup-ts.c
index ed263866367..ed263866367 100644
--- a/arch/arm/plat-s3c24xx/setup-ts.c
+++ b/arch/arm/mach-s3c24xx/setup-ts.c
diff --git a/arch/arm/plat-s3c24xx/simtec-audio.c b/arch/arm/mach-s3c24xx/simtec-audio.c
index 6bc832e0d8e..11881c9a38c 100644
--- a/arch/arm/plat-s3c24xx/simtec-audio.c
+++ b/arch/arm/mach-s3c24xx/simtec-audio.c
@@ -27,6 +27,8 @@
 #include <plat/audio-simtec.h>
 #include <plat/devs.h>
 
+#include "simtec.h"
+
 /* platform ops for audio */
 
 static void simtec_audio_startup_lrroute(void)
diff --git a/arch/arm/mach-s3c2410/nor-simtec.c b/arch/arm/mach-s3c24xx/simtec-nor.c
index ad9f750f1e5..2119ca6a73b 100644
--- a/arch/arm/mach-s3c2410/nor-simtec.c
+++ b/arch/arm/mach-s3c24xx/simtec-nor.c
@@ -30,7 +30,7 @@
 #include <mach/bast-map.h>
 #include <mach/bast-cpld.h>
 
-#include "nor-simtec.h"
+#include "simtec.h"
 
 static void simtec_nor_vpp(struct platform_device *pdev, int vpp)
 {
diff --git a/arch/arm/plat-s3c24xx/pm-simtec.c b/arch/arm/mach-s3c24xx/simtec-pm.c
index 699f9317129..699f9317129 100644
--- a/arch/arm/plat-s3c24xx/pm-simtec.c
+++ b/arch/arm/mach-s3c24xx/simtec-pm.c
diff --git a/arch/arm/mach-s3c2410/usb-simtec.c b/arch/arm/mach-s3c24xx/simtec-usb.c
index 29bd3d987be..d91c1a72513 100644
--- a/arch/arm/mach-s3c2410/usb-simtec.c
+++ b/arch/arm/mach-s3c24xx/simtec-usb.c
@@ -37,7 +37,7 @@
 #include <plat/usb-control.h>
 #include <plat/devs.h>
 
-#include "usb-simtec.h"
+#include "simtec.h"
 
 /* control power and monitor over-current events on various Simtec
  * designed boards.
diff --git a/arch/arm/mach-s3c2410/nor-simtec.h b/arch/arm/mach-s3c24xx/simtec.h
index f619c1e0d0c..ae8f4f9ad2e 100644
--- a/arch/arm/mach-s3c2410/nor-simtec.h
+++ b/arch/arm/mach-s3c24xx/simtec.h
@@ -4,11 +4,18 @@
  *      http://armlinux.simtec.co.uk/
  *      Ben Dooks <ben@simtec.co.uk>
  *
- * Simtec NOR mapping
+ * Simtec common functions
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
 */
 
+struct s3c24xx_audio_simtec_pdata;
+
 extern void nor_simtec_init(void);
+
+extern int usb_simtec_init(void);
+
+extern int simtec_audio_add(const char *codec_name, bool has_lr_routing,
+                            struct s3c24xx_audio_simtec_pdata *pdata);
diff --git a/arch/arm/mach-s3c2410/sleep.S b/arch/arm/mach-s3c24xx/sleep-s3c2410.S
index dd5b6388a5a..dd5b6388a5a 100644
--- a/arch/arm/mach-s3c2410/sleep.S
+++ b/arch/arm/mach-s3c24xx/sleep-s3c2410.S
diff --git a/arch/arm/mach-s3c2412/sleep.S b/arch/arm/mach-s3c24xx/sleep-s3c2412.S
index c82418ed714..c82418ed714 100644
--- a/arch/arm/mach-s3c2412/sleep.S
+++ b/arch/arm/mach-s3c24xx/sleep-s3c2412.S
diff --git a/arch/arm/mach-s3c64xx/Kconfig b/arch/arm/mach-s3c64xx/Kconfig
index dd20c66cd70..82c0915729e 100644
--- a/arch/arm/mach-s3c64xx/Kconfig
+++ b/arch/arm/mach-s3c64xx/Kconfig
@@ -83,6 +83,11 @@ config S3C64XX_SETUP_SPI
         help
          Common setup code for SPI GPIO configurations
 
+config S3C64XX_SETUP_USB_PHY
+        bool
+        help
+          Common setup code for USB PHY controller
+
 # S36400 Macchine support
 
 config MACH_SMDK6400
@@ -157,6 +162,7 @@ config MACH_SMDK6410
         select S3C64XX_SETUP_IDE
         select S3C64XX_SETUP_FB_24BPP
         select S3C64XX_SETUP_KEYPAD
+        select S3C64XX_SETUP_USB_PHY
         help
           Machine support for the Samsung SMDK6410
 
@@ -256,6 +262,7 @@ config MACH_SMARTQ
         select S3C_DEV_USB_HOST
         select S3C64XX_SETUP_SDHCI
         select S3C64XX_SETUP_FB_24BPP
+        select S3C64XX_SETUP_USB_PHY
         select SAMSUNG_DEV_ADC
         select SAMSUNG_DEV_PWM
         select SAMSUNG_DEV_TS
@@ -283,6 +290,7 @@ config MACH_WLF_CRAGG_6410
         select S3C64XX_SETUP_FB_24BPP
         select S3C64XX_SETUP_KEYPAD
         select S3C64XX_SETUP_SPI
+        select S3C64XX_SETUP_USB_PHY
         select SAMSUNG_DEV_ADC
         select SAMSUNG_DEV_KEYPAD
         select S3C_DEV_USB_HOST
@@ -296,5 +304,6 @@ config MACH_WLF_CRAGG_6410
         select S3C64XX_DEV_SPI0
         select SAMSUNG_GPIO_EXTRA128
         select I2C
+        select LEDS_GPIO_REGISTER
         help
           Machine support for the Wolfson Cragganmore S3C6410 variant.
diff --git a/arch/arm/mach-s3c64xx/Makefile b/arch/arm/mach-s3c64xx/Makefile
index 1822ac2eba3..f9ce1dc28ce 100644
--- a/arch/arm/mach-s3c64xx/Makefile
+++ b/arch/arm/mach-s3c64xx/Makefile
@@ -22,6 +22,7 @@ obj-$(CONFIG_CPU_S3C6410)	+= s3c6410.o
 # PM
 
 obj-$(CONFIG_PM)                += pm.o irq-pm.o sleep.o
+obj-$(CONFIG_CPU_IDLE)          += cpuidle.o
 
 # DMA support
 
@@ -42,6 +43,7 @@ obj-$(CONFIG_S3C64XX_SETUP_IDE)		+= setup-ide.o
 obj-$(CONFIG_S3C64XX_SETUP_KEYPAD)      += setup-keypad.o
 obj-$(CONFIG_S3C64XX_SETUP_SDHCI_GPIO)  += setup-sdhci-gpio.o
 obj-$(CONFIG_S3C64XX_SETUP_SPI)         += setup-spi.o
+obj-$(CONFIG_S3C64XX_SETUP_USB_PHY) += setup-usb-phy.o
 
 # Machine support
 
diff --git a/arch/arm/mach-s3c64xx/clock.c b/arch/arm/mach-s3c64xx/clock.c
index aebbcc291b4..52f079a691c 100644
--- a/arch/arm/mach-s3c64xx/clock.c
+++ b/arch/arm/mach-s3c64xx/clock.c
@@ -207,6 +207,15 @@ static struct clk init_clocks_off[] = {
                 .enable         = s3c64xx_sclk_ctrl,
                 .ctrlbit        = S3C_CLKCON_SCLK_MMC2_48,
         }, {
+                .name           = "ac97",
+                .parent         = &clk_p,
+                .ctrlbit        = S3C_CLKCON_PCLK_AC97,
+        }, {
+                .name           = "cfcon",
+                .parent         = &clk_h,
+                .enable         = s3c64xx_hclk_ctrl,
+                .ctrlbit        = S3C_CLKCON_HCLK_IHOST,
+        }, {
                 .name           = "dma0",
                 .parent         = &clk_h,
                 .enable         = s3c64xx_hclk_ctrl,
@@ -216,6 +225,107 @@ static struct clk init_clocks_off[] = {
                 .parent         = &clk_h,
                 .enable         = s3c64xx_hclk_ctrl,
                 .ctrlbit        = S3C_CLKCON_HCLK_DMA1,
+        }, {
+                .name           = "3dse",
+                .parent         = &clk_h,
+                .enable         = s3c64xx_hclk_ctrl,
+                .ctrlbit        = S3C_CLKCON_HCLK_3DSE,
+        }, {
+                .name           = "hclk_secur",
+                .parent         = &clk_h,
+                .enable         = s3c64xx_hclk_ctrl,
+                .ctrlbit        = S3C_CLKCON_HCLK_SECUR,
+        }, {
+                .name           = "sdma1",
+                .parent         = &clk_h,
+                .enable         = s3c64xx_hclk_ctrl,
+                .ctrlbit        = S3C_CLKCON_HCLK_SDMA1,
+        }, {
+                .name           = "sdma0",
+                .parent         = &clk_h,
+                .enable         = s3c64xx_hclk_ctrl,
+                .ctrlbit        = S3C_CLKCON_HCLK_SDMA0,
+        }, {
+                .name           = "hclk_jpeg",
+                .parent         = &clk_h,
+                .enable         = s3c64xx_hclk_ctrl,
+                .ctrlbit        = S3C_CLKCON_HCLK_JPEG,
+        }, {
+                .name           = "camif",
+                .parent         = &clk_h,
+                .enable         = s3c64xx_hclk_ctrl,
+                .ctrlbit        = S3C_CLKCON_HCLK_CAMIF,
+        }, {
+                .name           = "hclk_scaler",
+                .parent         = &clk_h,
+                .enable         = s3c64xx_hclk_ctrl,
+                .ctrlbit        = S3C_CLKCON_HCLK_SCALER,
+        }, {
+                .name           = "2d",
+                .parent         = &clk_h,
+                .enable         = s3c64xx_hclk_ctrl,
+                .ctrlbit        = S3C_CLKCON_HCLK_2D,
+        }, {
+                .name           = "tv",
+                .parent         = &clk_h,
+                .enable         = s3c64xx_hclk_ctrl,
+                .ctrlbit        = S3C_CLKCON_HCLK_TV,
+        }, {
+                .name           = "post0",
+                .parent         = &clk_h,
+                .enable         = s3c64xx_hclk_ctrl,
+                .ctrlbit        = S3C_CLKCON_HCLK_POST0,
+        }, {
+                .name           = "rot",
+                .parent         = &clk_h,
+                .enable         = s3c64xx_hclk_ctrl,
+                .ctrlbit        = S3C_CLKCON_HCLK_ROT,
+        }, {
+                .name           = "hclk_mfc",
+                .parent         = &clk_h,
+                .enable         = s3c64xx_hclk_ctrl,
+                .ctrlbit        = S3C_CLKCON_HCLK_MFC,
+        }, {
+                .name           = "pclk_mfc",
+                .parent         = &clk_p,
+                .enable         = s3c64xx_pclk_ctrl,
+                .ctrlbit        = S3C_CLKCON_PCLK_MFC,
+        }, {
+                .name           = "dac27",
+                .enable         = s3c64xx_sclk_ctrl,
+                .ctrlbit        = S3C_CLKCON_SCLK_DAC27,
+        }, {
+                .name           = "tv27",
+                .enable         = s3c64xx_sclk_ctrl,
+                .ctrlbit        = S3C_CLKCON_SCLK_TV27,
+        }, {
+                .name           = "scaler27",
+                .enable         = s3c64xx_sclk_ctrl,
+                .ctrlbit        = S3C_CLKCON_SCLK_SCALER27,
+        }, {
+                .name           = "sclk_scaler",
+                .enable         = s3c64xx_sclk_ctrl,
+                .ctrlbit        = S3C_CLKCON_SCLK_SCALER,
+        }, {
+                .name           = "post0_27",
+                .enable         = s3c64xx_sclk_ctrl,
+                .ctrlbit        = S3C_CLKCON_SCLK_POST0_27,
+        }, {
+                .name           = "secur",
+                .enable         = s3c64xx_sclk_ctrl,
+                .ctrlbit        = S3C_CLKCON_SCLK_SECUR,
+        }, {
+                .name           = "sclk_mfc",
+                .enable         = s3c64xx_sclk_ctrl,
+                .ctrlbit        = S3C_CLKCON_SCLK_MFC,
+        }, {
+                .name           = "cam",
+                .enable         = s3c64xx_sclk_ctrl,
+                .ctrlbit        = S3C_CLKCON_SCLK_CAM,
+        }, {
+                .name           = "sclk_jpeg",
+                .enable         = s3c64xx_sclk_ctrl,
+                .ctrlbit        = S3C_CLKCON_SCLK_JPEG,
         },
 };
 
@@ -289,16 +399,7 @@ static struct clk init_clocks[] = {
                 .name           = "watchdog",
                 .parent         = &clk_p,
                 .ctrlbit        = S3C_CLKCON_PCLK_WDT,
-        }, {
-                .name           = "ac97",
-                .parent         = &clk_p,
-                .ctrlbit        = S3C_CLKCON_PCLK_AC97,
-        }, {
-                .name           = "cfcon",
-                .parent         = &clk_h,
-                .enable         = s3c64xx_hclk_ctrl,
-                .ctrlbit        = S3C_CLKCON_HCLK_IHOST,
-        }
+        },
 };
 
 static struct clk clk_hsmmc0 = {
diff --git a/arch/arm/mach-s3c64xx/common.h b/arch/arm/mach-s3c64xx/common.h
index 5eb9c9a7d73..7a10be629ab 100644
--- a/arch/arm/mach-s3c64xx/common.h
+++ b/arch/arm/mach-s3c64xx/common.h
@@ -25,8 +25,6 @@ void s3c64xx_setup_clocks(void);
 
 void s3c64xx_restart(char mode, const char *cmd);
 
-extern struct syscore_ops s3c64xx_irq_syscore_ops;
-
 #ifdef CONFIG_CPU_S3C6400
 
 extern  int s3c6400_init(void);
diff --git a/arch/arm/mach-s3c64xx/cpuidle.c b/arch/arm/mach-s3c64xx/cpuidle.c
new file mode 100644
index 00000000000..179460f38db
--- /dev/null
+++ b/arch/arm/mach-s3c64xx/cpuidle.c
@@ -0,0 +1,91 @@
+/* linux/arch/arm/mach-s3c64xx/cpuidle.c
+ *
+ * Copyright (c) 2011 Wolfson Microelectronics, plc
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/cpuidle.h>
+#include <linux/io.h>
+#include <linux/export.h>
+#include <linux/time.h>
+
+#include <asm/proc-fns.h>
+
+#include <mach/map.h>
+
+#include <mach/regs-sys.h>
+#include <mach/regs-syscon-power.h>
+
+static int s3c64xx_enter_idle(struct cpuidle_device *dev,
+                              struct cpuidle_driver *drv,
+                              int index)
+{
+        struct timeval before, after;
+        unsigned long tmp;
+        int idle_time;
+
+        local_irq_disable();
+        do_gettimeofday(&before);
+
+        /* Setup PWRCFG to enter idle mode */
+        tmp = __raw_readl(S3C64XX_PWR_CFG);
+        tmp &= ~S3C64XX_PWRCFG_CFG_WFI_MASK;
+        tmp |= S3C64XX_PWRCFG_CFG_WFI_IDLE;
+        __raw_writel(tmp, S3C64XX_PWR_CFG);
+
+        cpu_do_idle();
+
+        do_gettimeofday(&after);
+        local_irq_enable();
+        idle_time = (after.tv_sec - before.tv_sec) * USEC_PER_SEC +
+                    (after.tv_usec - before.tv_usec);
+
+        dev->last_residency = idle_time;
+        return index;
+}
+
+static struct cpuidle_state s3c64xx_cpuidle_set[] = {
+        [0] = {
+                .enter                  = s3c64xx_enter_idle,
+                .exit_latency           = 1,
+                .target_residency       = 1,
+                .flags                  = CPUIDLE_FLAG_TIME_VALID,
+                .name                   = "IDLE",
+                .desc                   = "System active, ARM gated",
+        },
+};
+
+static struct cpuidle_driver s3c64xx_cpuidle_driver = {
+        .name           = "s3c64xx_cpuidle",
+        .owner          = THIS_MODULE,
+        .state_count    = ARRAY_SIZE(s3c64xx_cpuidle_set),
+};
+
+static struct cpuidle_device s3c64xx_cpuidle_device = {
+        .state_count    = ARRAY_SIZE(s3c64xx_cpuidle_set),
+};
+
+static int __init s3c64xx_init_cpuidle(void)
+{
+        int ret;
+
+        memcpy(s3c64xx_cpuidle_driver.states, s3c64xx_cpuidle_set,
+               sizeof(s3c64xx_cpuidle_set));
+        cpuidle_register_driver(&s3c64xx_cpuidle_driver);
+
+        ret = cpuidle_register_device(&s3c64xx_cpuidle_device);
+        if (ret) {
+                pr_err("Failed to register cpuidle device: %d\n", ret);
+                return ret;
+        }
+
+        return 0;
+}
+device_initcall(s3c64xx_init_cpuidle);
diff --git a/arch/arm/mach-s3c64xx/include/mach/entry-macro.S b/arch/arm/mach-s3c64xx/include/mach/entry-macro.S
deleted file mode 100644
index dc2bc15142c..00000000000
--- a/arch/arm/mach-s3c64xx/include/mach/entry-macro.S
+++ /dev/null
@@ -1,19 +0,0 @@
-/* arch/arm/mach-s3c6400/include/mach/entry-macro.S
- *
- * Copyright 2008 Openmoko, Inc.
- * Copyright 2008 Simtec Electronics
- *      http://armlinux.simtec.co.uk/
- *      Ben Dooks <ben@simtec.co.uk>
- *
- * Low-level IRQ helper macros for the Samsung S3C64XX series
- *
- * This file is licensed under  the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
-*/
-
-                .macro  disable_fiq
-                .endm
-
-                .macro  arch_ret_to_user, tmp1, tmp2
-                .endm
diff --git a/arch/arm/mach-s3c64xx/include/mach/system.h b/arch/arm/mach-s3c64xx/include/mach/system.h
deleted file mode 100644
index 353ed4389ae..00000000000
--- a/arch/arm/mach-s3c64xx/include/mach/system.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/* linux/arch/arm/mach-s3c6400/include/mach/system.h
- *
- * Copyright 2008 Openmoko, Inc.
- * Copyright 2008 Simtec Electronics
- *      Ben Dooks <ben@simtec.co.uk>
- *      http://armlinux.simtec.co.uk/
- *
- * S3C6400 - system implementation
- */
-
-#ifndef __ASM_ARCH_SYSTEM_H
-#define __ASM_ARCH_SYSTEM_H __FILE__
-
-static void arch_idle(void)
-{
-        /* nothing here yet */
-}
-
-#endif /* __ASM_ARCH_IRQ_H */
diff --git a/arch/arm/mach-s3c64xx/irq-pm.c b/arch/arm/mach-s3c64xx/irq-pm.c
index 8bec61e242c..0c7e1d960ca 100644
--- a/arch/arm/mach-s3c64xx/irq-pm.c
+++ b/arch/arm/mach-s3c64xx/irq-pm.c
@@ -96,7 +96,7 @@ static void s3c64xx_irq_pm_resume(void)
         S3C_PMDBG("%s: IRQ configuration restored\n", __func__);
 }
 
-struct syscore_ops s3c64xx_irq_syscore_ops = {
+static struct syscore_ops s3c64xx_irq_syscore_ops = {
         .suspend = s3c64xx_irq_pm_suspend,
         .resume  = s3c64xx_irq_pm_resume,
 };
diff --git a/arch/arm/mach-s3c64xx/mach-crag6410-module.c b/arch/arm/mach-s3c64xx/mach-crag6410-module.c
index cd3c97e2ee7..b6a67728cc8 100644
--- a/arch/arm/mach-s3c64xx/mach-crag6410-module.c
+++ b/arch/arm/mach-s3c64xx/mach-crag6410-module.c
@@ -11,6 +11,7 @@
 #include <linux/export.h>
 #include <linux/interrupt.h>
 #include <linux/i2c.h>
+#include <linux/spi/spi.h>
 
 #include <linux/mfd/wm831x/irq.h>
 #include <linux/mfd/wm831x/gpio.h>
@@ -21,8 +22,25 @@
 #include <sound/wm8962.h>
 #include <sound/wm9081.h>
 
+#include <plat/s3c64xx-spi.h>
+
 #include <mach/crag6410.h>
 
+static struct s3c64xx_spi_csinfo wm0010_spi_csinfo = {
+        .set_level = gpio_set_value,
+        .line = S3C64XX_GPC(3),
+};
+
+static struct spi_board_info wm1253_devs[] = {
+        [0] = {
+                .modalias       = "wm0010",
+                .bus_num        = 0,
+                .chip_select    = 0,
+                .mode           = SPI_MODE_0,
+                .controller_data = &wm0010_spi_csinfo,
+        },
+};
+
 static struct wm5100_pdata wm5100_pdata = {
         .ldo_ena = S3C64XX_GPN(7),
         .irq_flags = IRQF_TRIGGER_HIGH,
@@ -102,6 +120,7 @@ static struct wm8962_pdata wm8962_pdata __initdata = {
                 0x8000 | WM8962_GPIO_FN_DMICDAT,
                 WM8962_GPIO_FN_IRQ,    /* Open drain mode */
         },
+        .in4_dc_measure = true,
 };
 
 static struct wm9081_pdata wm9081_pdata __initdata = {
@@ -158,14 +177,21 @@ static __devinitdata const struct {
         const char *name;
         const struct i2c_board_info *i2c_devs;
         int num_i2c_devs;
+        const struct spi_board_info *spi_devs;
+        int num_spi_devs;
 } gf_mods[] = {
         { .id = 0x01, .name = "1250-EV1 Springbank" },
         { .id = 0x02, .name = "1251-EV1 Jura" },
         { .id = 0x03, .name = "1252-EV1 Glenlivet" },
         { .id = 0x11, .name = "6249-EV2 Glenfarclas", },
+        { .id = 0x14, .name = "6271-EV1 Lochnagar" },
+        { .id = 0x15, .name = "XXXX-EV1 Bells" },
         { .id = 0x21, .name = "1275-EV1 Mortlach" },
         { .id = 0x25, .name = "1274-EV1 Glencadam" },
-        { .id = 0x31, .name = "1253-EV1 Tomatin", },
+        { .id = 0x31, .name = "1253-EV1 Tomatin",
+          .spi_devs = wm1253_devs, .num_spi_devs = ARRAY_SIZE(wm1253_devs) },
+        { .id = 0x32, .name = "XXXX-EV1 Caol Illa" },
+        { .id = 0x33, .name = "XXXX-EV1 Oban" },
         { .id = 0x39, .name = "1254-EV1 Dallas Dhu",
           .i2c_devs = wm1254_devs, .num_i2c_devs = ARRAY_SIZE(wm1254_devs) },
         { .id = 0x3a, .name = "1259-EV1 Tobermory",
@@ -197,12 +223,16 @@ static __devinit int wlf_gf_module_probe(struct i2c_client *i2c,
         if (i < ARRAY_SIZE(gf_mods)) {
                 dev_info(&i2c->dev, "%s revision %d\n",
                          gf_mods[i].name, rev + 1);
+
                 for (j = 0; j < gf_mods[i].num_i2c_devs; j++) {
                         if (!i2c_new_device(i2c->adapter,
                                             &(gf_mods[i].i2c_devs[j])))
                                 dev_err(&i2c->dev,
                                         "Failed to register dev: %d\n", ret);
                 }
+
+                spi_register_board_info(gf_mods[i].spi_devs,
+                                        gf_mods[i].num_spi_devs);
         } else {
                 dev_warn(&i2c->dev, "Unknown module ID 0x%x revision %d\n",
                          id, rev + 1);
diff --git a/arch/arm/mach-s3c64xx/mach-crag6410.c b/arch/arm/mach-s3c64xx/mach-crag6410.c
index 8077f650eb0..e20bf583536 100644
--- a/arch/arm/mach-s3c64xx/mach-crag6410.c
+++ b/arch/arm/mach-s3c64xx/mach-crag6410.c
@@ -19,7 +19,9 @@
 #include <linux/io.h>
 #include <linux/init.h>
 #include <linux/gpio.h>
+#include <linux/leds.h>
 #include <linux/delay.h>
+#include <linux/mmc/host.h>
 #include <linux/regulator/machine.h>
 #include <linux/regulator/fixed.h>
 #include <linux/pwm_backlight.h>
@@ -59,6 +61,7 @@
 #include <plat/sdhci.h>
 #include <plat/gpio-cfg.h>
 #include <plat/s3c64xx-spi.h>
+#include <plat/udc-hs.h>
 
 #include <plat/keypad.h>
 #include <plat/clock.h>
@@ -298,6 +301,7 @@ static struct platform_device littlemill_device = {
 };
 
 static struct regulator_consumer_supply wallvdd_consumers[] = {
+        REGULATOR_SUPPLY("SPKVDD", "1-001a"),
         REGULATOR_SUPPLY("SPKVDD1", "1-001a"),
         REGULATOR_SUPPLY("SPKVDD2", "1-001a"),
         REGULATOR_SUPPLY("SPKVDDL", "1-001a"),
@@ -574,11 +578,19 @@ static struct s3c2410_platform_i2c i2c0_pdata = {
         .frequency = 400000,
 };
 
+static struct regulator_consumer_supply pvdd_1v2_consumers[] __initdata = {
+        REGULATOR_SUPPLY("DCVDD", "spi0.0"),
+        REGULATOR_SUPPLY("AVDD", "spi0.0"),
+};
+
 static struct regulator_init_data pvdd_1v2 __initdata = {
         .constraints = {
                 .name = "PVDD_1V2",
-                .always_on = 1,
+                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
         },
+
+        .consumer_supplies = pvdd_1v2_consumers,
+        .num_consumer_supplies = ARRAY_SIZE(pvdd_1v2_consumers),
 };
 
 static struct regulator_consumer_supply pvdd_1v8_consumers[] __initdata = {
@@ -592,6 +604,7 @@ static struct regulator_consumer_supply pvdd_1v8_consumers[] __initdata = {
         REGULATOR_SUPPLY("AVDD2", "1-001a"),
         REGULATOR_SUPPLY("DCVDD", "1-001a"),
         REGULATOR_SUPPLY("AVDD", "1-001a"),
+        REGULATOR_SUPPLY("DBVDD", "spi0.0"),
 };
 
 static struct regulator_init_data pvdd_1v8 __initdata = {
@@ -681,6 +694,7 @@ static void __init crag6410_map_io(void)
 static struct s3c_sdhci_platdata crag6410_hsmmc2_pdata = {
         .max_width              = 4,
         .cd_type                = S3C_SDHCI_CD_PERMANENT,
+        .host_caps              = MMC_CAP_POWER_OFF_CARD,
 };
 
 static void crag6410_cfg_sdhci0(struct platform_device *dev, int width)
@@ -696,8 +710,59 @@ static struct s3c_sdhci_platdata crag6410_hsmmc0_pdata = {
         .max_width              = 4,
         .cd_type                = S3C_SDHCI_CD_INTERNAL,
         .cfg_gpio               = crag6410_cfg_sdhci0,
+        .host_caps              = MMC_CAP_POWER_OFF_CARD,
+};
+
+static const struct gpio_led gpio_leds[] = {
+        {
+                .name = "d13:green:",
+                .gpio = MMGPIO_GPIO_BASE + 0,
+                .default_state = LEDS_GPIO_DEFSTATE_ON,
+        },
+        {
+                .name = "d14:green:",
+                .gpio = MMGPIO_GPIO_BASE + 1,
+                .default_state = LEDS_GPIO_DEFSTATE_ON,
+        },
+        {
+                .name = "d15:green:",
+                .gpio = MMGPIO_GPIO_BASE + 2,
+                .default_state = LEDS_GPIO_DEFSTATE_ON,
+        },
+        {
+                .name = "d16:green:",
+                .gpio = MMGPIO_GPIO_BASE + 3,
+                .default_state = LEDS_GPIO_DEFSTATE_ON,
+        },
+        {
+                .name = "d17:green:",
+                .gpio = MMGPIO_GPIO_BASE + 4,
+                .default_state = LEDS_GPIO_DEFSTATE_ON,
+        },
+        {
+                .name = "d18:green:",
+                .gpio = MMGPIO_GPIO_BASE + 5,
+                .default_state = LEDS_GPIO_DEFSTATE_ON,
+        },
+        {
+                .name = "d19:green:",
+                .gpio = MMGPIO_GPIO_BASE + 6,
+                .default_state = LEDS_GPIO_DEFSTATE_ON,
+        },
+        {
+                .name = "d20:green:",
+                .gpio = MMGPIO_GPIO_BASE + 7,
+                .default_state = LEDS_GPIO_DEFSTATE_ON,
+        },
 };
 
+static const struct gpio_led_platform_data gpio_leds_pdata = {
+        .leds = gpio_leds,
+        .num_leds = ARRAY_SIZE(gpio_leds),
+};
+
+static struct s3c_hsotg_plat crag6410_hsotg_pdata;
+
 static void __init crag6410_machine_init(void)
 {
         /* Open drain IRQs need pullups */
@@ -722,14 +787,18 @@ static void __init crag6410_machine_init(void)
         s3c_i2c0_set_platdata(&i2c0_pdata);
         s3c_i2c1_set_platdata(&i2c1_pdata);
         s3c_fb_set_platdata(&crag6410_lcd_pdata);
+        s3c_hsotg_set_platdata(&crag6410_hsotg_pdata);
 
         i2c_register_board_info(0, i2c_devs0, ARRAY_SIZE(i2c_devs0));
         i2c_register_board_info(1, i2c_devs1, ARRAY_SIZE(i2c_devs1));
 
         samsung_keypad_set_platdata(&crag6410_keypad_data);
+        s3c64xx_spi0_set_platdata(&s3c64xx_spi0_pdata, 0, 1);
 
         platform_add_devices(crag6410_devices, ARRAY_SIZE(crag6410_devices));
 
+        gpio_led_register_device(-1, &gpio_leds_pdata);
+
         regulator_has_full_constraints();
 
         s3c64xx_pm_init();
diff --git a/arch/arm/mach-s3c64xx/mach-smartq.c b/arch/arm/mach-s3c64xx/mach-smartq.c
index ce31db13623..ce745e19aa2 100644
--- a/arch/arm/mach-s3c64xx/mach-smartq.c
+++ b/arch/arm/mach-s3c64xx/mach-smartq.c
@@ -187,6 +187,8 @@ static struct s3c_hwmon_pdata smartq_hwmon_pdata __initdata = {
         },
 };
 
+static struct s3c_hsotg_plat smartq_hsotg_pdata;
+
 static int __init smartq_lcd_setup_gpio(void)
 {
         int ret;
@@ -383,6 +385,7 @@ void __init smartq_map_io(void)
 void __init smartq_machine_init(void)
 {
         s3c_i2c0_set_platdata(NULL);
+        s3c_hsotg_set_platdata(&smartq_hsotg_pdata);
         s3c_hwmon_set_platdata(&smartq_hwmon_pdata);
         s3c_sdhci1_set_platdata(&smartq_internal_hsmmc_pdata);
         s3c_sdhci2_set_platdata(&smartq_internal_hsmmc_pdata);
diff --git a/arch/arm/mach-s3c64xx/mach-smdk6410.c b/arch/arm/mach-s3c64xx/mach-smdk6410.c
index ca6fc204f0e..d55bc96d958 100644
--- a/arch/arm/mach-s3c64xx/mach-smdk6410.c
+++ b/arch/arm/mach-s3c64xx/mach-smdk6410.c
@@ -72,6 +72,7 @@
 #include <plat/keypad.h>
 #include <plat/backlight.h>
 #include <plat/regs-fb-v4.h>
+#include <plat/udc-hs.h>
 
 #include "common.h"
 
@@ -631,6 +632,8 @@ static struct platform_pwm_backlight_data smdk6410_bl_data = {
         .pwm_id = 1,
 };
 
+static struct s3c_hsotg_plat smdk6410_hsotg_pdata;
+
 static void __init smdk6410_map_io(void)
 {
         u32 tmp;
@@ -659,6 +662,7 @@ static void __init smdk6410_machine_init(void)
         s3c_i2c0_set_platdata(NULL);
         s3c_i2c1_set_platdata(NULL);
         s3c_fb_set_platdata(&smdk6410_lcd_pdata);
+        s3c_hsotg_set_platdata(&smdk6410_hsotg_pdata);
 
         samsung_keypad_set_platdata(&smdk6410_keypad_data);
 
diff --git a/arch/arm/mach-s3c64xx/setup-usb-phy.c b/arch/arm/mach-s3c64xx/setup-usb-phy.c
new file mode 100644
index 00000000000..f6757e02d7d
--- /dev/null
+++ b/arch/arm/mach-s3c64xx/setup-usb-phy.c
@@ -0,0 +1,90 @@
+/*
+ * Copyright (C) 2011 Samsung Electronics Co.Ltd
+ * Author: Joonyoung Shim <jy0922.shim@samsung.com>
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ */
+
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/platform_device.h>
+#include <mach/map.h>
+#include <mach/regs-sys.h>
+#include <plat/cpu.h>
+#include <plat/regs-usb-hsotg-phy.h>
+#include <plat/usb-phy.h>
+
+static int s3c_usb_otgphy_init(struct platform_device *pdev)
+{
+        struct clk *xusbxti;
+        u32 phyclk;
+
+        writel(readl(S3C64XX_OTHERS) | S3C64XX_OTHERS_USBMASK, S3C64XX_OTHERS);
+
+        /* set clock frequency for PLL */
+        phyclk = readl(S3C_PHYCLK) & ~S3C_PHYCLK_CLKSEL_MASK;
+
+        xusbxti = clk_get(&pdev->dev, "xusbxti");
+        if (xusbxti && !IS_ERR(xusbxti)) {
+                switch (clk_get_rate(xusbxti)) {
+                case 12 * MHZ:
+                        phyclk |= S3C_PHYCLK_CLKSEL_12M;
+                        break;
+                case 24 * MHZ:
+                        phyclk |= S3C_PHYCLK_CLKSEL_24M;
+                        break;
+                default:
+                case 48 * MHZ:
+                        /* default reference clock */
+                        break;
+                }
+                clk_put(xusbxti);
+        }
+
+        /* TODO: select external clock/oscillator */
+        writel(phyclk | S3C_PHYCLK_CLK_FORCE, S3C_PHYCLK);
+
+        /* set to normal OTG PHY */
+        writel((readl(S3C_PHYPWR) & ~S3C_PHYPWR_NORMAL_MASK), S3C_PHYPWR);
+        mdelay(1);
+
+        /* reset OTG PHY and Link */
+        writel(S3C_RSTCON_PHY | S3C_RSTCON_HCLK | S3C_RSTCON_PHYCLK,
+                        S3C_RSTCON);
+        udelay(20);     /* at-least 10uS */
+        writel(0, S3C_RSTCON);
+
+        return 0;
+}
+
+static int s3c_usb_otgphy_exit(struct platform_device *pdev)
+{
+        writel((readl(S3C_PHYPWR) | S3C_PHYPWR_ANALOG_POWERDOWN |
+                                S3C_PHYPWR_OTG_DISABLE), S3C_PHYPWR);
+
+        writel(readl(S3C64XX_OTHERS) & ~S3C64XX_OTHERS_USBMASK, S3C64XX_OTHERS);
+
+        return 0;
+}
+
+int s5p_usb_phy_init(struct platform_device *pdev, int type)
+{
+        if (type == S5P_USB_PHY_DEVICE)
+                return s3c_usb_otgphy_init(pdev);
+
+        return -EINVAL;
+}
+
+int s5p_usb_phy_exit(struct platform_device *pdev, int type)
+{
+        if (type == S5P_USB_PHY_DEVICE)
+                return s3c_usb_otgphy_exit(pdev);
+
+        return -EINVAL;
+}
diff --git a/arch/arm/mach-s5p64x0/clock.c b/arch/arm/mach-s5p64x0/clock.c
index 241d0e645c8..57e718957ef 100644
--- a/arch/arm/mach-s5p64x0/clock.c
+++ b/arch/arm/mach-s5p64x0/clock.c
@@ -73,7 +73,7 @@ static const u32 clock_table[][3] = {
         {L2 * 1000, (3 << ARM_DIV_RATIO_SHIFT), (0 << S5P64X0_CLKDIV0_HCLK_SHIFT)},
 };
 
-unsigned long s5p64x0_armclk_get_rate(struct clk *clk)
+static unsigned long s5p64x0_armclk_get_rate(struct clk *clk)
 {
         unsigned long rate = clk_get_rate(clk->parent);
         u32 clkdiv;
@@ -84,7 +84,8 @@ unsigned long s5p64x0_armclk_get_rate(struct clk *clk)
         return rate / (clkdiv + 1);
 }
 
-unsigned long s5p64x0_armclk_round_rate(struct clk *clk, unsigned long rate)
+static unsigned long s5p64x0_armclk_round_rate(struct clk *clk,
+                                               unsigned long rate)
 {
         u32 iter;
 
@@ -96,7 +97,7 @@ unsigned long s5p64x0_armclk_round_rate(struct clk *clk, unsigned long rate)
         return clock_table[ARRAY_SIZE(clock_table) - 1][0];
 }
 
-int s5p64x0_armclk_set_rate(struct clk *clk, unsigned long rate)
+static int s5p64x0_armclk_set_rate(struct clk *clk, unsigned long rate)
 {
         u32 round_tmp;
         u32 iter;
@@ -148,7 +149,7 @@ int s5p64x0_armclk_set_rate(struct clk *clk, unsigned long rate)
         return 0;
 }
 
-struct clk_ops s5p64x0_clkarm_ops = {
+static struct clk_ops s5p64x0_clkarm_ops = {
         .get_rate       = s5p64x0_armclk_get_rate,
         .set_rate       = s5p64x0_armclk_set_rate,
         .round_rate     = s5p64x0_armclk_round_rate,
@@ -173,7 +174,7 @@ struct clksrc_clk clk_dout_mpll = {
         .reg_div        = { .reg = S5P64X0_CLK_DIV0, .shift = 4, .size = 1 },
 };
 
-struct clk *clkset_hclk_low_list[] = {
+static struct clk *clkset_hclk_low_list[] = {
         &clk_mout_apll.clk,
         &clk_mout_mpll.clk,
 };
diff --git a/arch/arm/mach-s5p64x0/common.c b/arch/arm/mach-s5p64x0/common.c
index 52b89a37644..9143f8b1996 100644
--- a/arch/arm/mach-s5p64x0/common.c
+++ b/arch/arm/mach-s5p64x0/common.c
@@ -146,15 +146,12 @@ static void s5p64x0_idle(void)
 {
         unsigned long val;
 
-        if (!need_resched()) {
-                val = __raw_readl(S5P64X0_PWR_CFG);
-                val &= ~(0x3 << 5);
-                val |= (0x1 << 5);
-                __raw_writel(val, S5P64X0_PWR_CFG);
+        val = __raw_readl(S5P64X0_PWR_CFG);
+        val &= ~(0x3 << 5);
+        val |= (0x1 << 5);
+        __raw_writel(val, S5P64X0_PWR_CFG);
 
-                cpu_do_idle();
-        }
-        local_irq_enable();
+        cpu_do_idle();
 }
 
 /*
@@ -286,7 +283,7 @@ int __init s5p64x0_init(void)
         printk(KERN_INFO "S5P64X0(S5P6440/S5P6450): Initializing architecture\n");
 
         /* set idle function */
-        pm_idle = s5p64x0_idle;
+        arm_pm_idle = s5p64x0_idle;
 
         return device_register(&s5p64x0_dev);
 }
diff --git a/arch/arm/mach-s5p64x0/dma.c b/arch/arm/mach-s5p64x0/dma.c
index f820c074440..2ee5dc069b3 100644
--- a/arch/arm/mach-s5p64x0/dma.c
+++ b/arch/arm/mach-s5p64x0/dma.c
@@ -38,7 +38,7 @@
 
 static u64 dma_dmamask = DMA_BIT_MASK(32);
 
-u8 s5p6440_pdma_peri[] = {
+static u8 s5p6440_pdma_peri[] = {
         DMACH_UART0_RX,
         DMACH_UART0_TX,
         DMACH_UART1_RX,
@@ -63,12 +63,12 @@ u8 s5p6440_pdma_peri[] = {
         DMACH_SPI1_RX,
 };
 
-struct dma_pl330_platdata s5p6440_pdma_pdata = {
+static struct dma_pl330_platdata s5p6440_pdma_pdata = {
         .nr_valid_peri = ARRAY_SIZE(s5p6440_pdma_peri),
         .peri_id = s5p6440_pdma_peri,
 };
 
-u8 s5p6450_pdma_peri[] = {
+static u8 s5p6450_pdma_peri[] = {
         DMACH_UART0_RX,
         DMACH_UART0_TX,
         DMACH_UART1_RX,
@@ -103,39 +103,27 @@ u8 s5p6450_pdma_peri[] = {
         DMACH_UART5_TX,
 };
 
-struct dma_pl330_platdata s5p6450_pdma_pdata = {
+static struct dma_pl330_platdata s5p6450_pdma_pdata = {
         .nr_valid_peri = ARRAY_SIZE(s5p6450_pdma_peri),
         .peri_id = s5p6450_pdma_peri,
 };
 
-struct amba_device s5p64x0_device_pdma = {
-        .dev = {
-                .init_name = "dma-pl330",
-                .dma_mask = &dma_dmamask,
-                .coherent_dma_mask = DMA_BIT_MASK(32),
-        },
-        .res = {
-                .start = S5P64X0_PA_PDMA,
-                .end = S5P64X0_PA_PDMA + SZ_4K,
-                .flags = IORESOURCE_MEM,
-        },
-        .irq = {IRQ_DMA0, NO_IRQ},
-        .periphid = 0x00041330,
-};
+static AMBA_AHB_DEVICE(s5p64x0_pdma, "dma-pl330", 0x00041330,
+        S5P64X0_PA_PDMA, {IRQ_DMA0}, NULL);
 
 static int __init s5p64x0_dma_init(void)
 {
         if (soc_is_s5p6450()) {
                 dma_cap_set(DMA_SLAVE, s5p6450_pdma_pdata.cap_mask);
                 dma_cap_set(DMA_CYCLIC, s5p6450_pdma_pdata.cap_mask);
-                s5p64x0_device_pdma.dev.platform_data = &s5p6450_pdma_pdata;
+                s5p64x0_pdma_device.dev.platform_data = &s5p6450_pdma_pdata;
         } else {
                 dma_cap_set(DMA_SLAVE, s5p6440_pdma_pdata.cap_mask);
                 dma_cap_set(DMA_CYCLIC, s5p6440_pdma_pdata.cap_mask);
-                s5p64x0_device_pdma.dev.platform_data = &s5p6440_pdma_pdata;
+                s5p64x0_pdma_device.dev.platform_data = &s5p6440_pdma_pdata;
         }
 
-        amba_device_register(&s5p64x0_device_pdma, &iomem_resource);
+        amba_device_register(&s5p64x0_pdma_device, &iomem_resource);
 
         return 0;
 }
diff --git a/arch/arm/mach-s5p64x0/include/mach/entry-macro.S b/arch/arm/mach-s5p64x0/include/mach/entry-macro.S
deleted file mode 100644
index fbb246d0a3d..00000000000
--- a/arch/arm/mach-s5p64x0/include/mach/entry-macro.S
+++ /dev/null
@@ -1,17 +0,0 @@
-/* linux/arch/arm/mach-s5p64x0/include/mach/entry-macro.S
- *
- * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com
- *
- * Low-level IRQ helper macros for the Samsung S5P64X0
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-                .macro  disable_fiq
-                .endm
-
-                .macro  arch_ret_to_user, tmp1, tmp2
-                .endm
diff --git a/arch/arm/mach-s5p64x0/include/mach/s5p64x0-clock.h b/arch/arm/mach-s5p64x0/include/mach/s5p64x0-clock.h
index ff85b4b6e8d..0ef47d1b767 100644
--- a/arch/arm/mach-s5p64x0/include/mach/s5p64x0-clock.h
+++ b/arch/arm/mach-s5p64x0/include/mach/s5p64x0-clock.h
@@ -22,16 +22,9 @@ extern struct clksrc_clk clk_mout_epll;
 extern int s5p64x0_epll_enable(struct clk *clk, int enable);
 extern unsigned long s5p64x0_epll_get_rate(struct clk *clk);
 
-extern unsigned long s5p64x0_armclk_get_rate(struct clk *clk);
-extern unsigned long s5p64x0_armclk_round_rate(struct clk *clk, unsigned long rate);
-extern int s5p64x0_armclk_set_rate(struct clk *clk, unsigned long rate);
-
-extern struct clk_ops s5p64x0_clkarm_ops;
-
 extern struct clksrc_clk clk_armclk;
 extern struct clksrc_clk clk_dout_mpll;
 
-extern struct clk *clkset_hclk_low_list[];
 extern struct clksrc_sources clkset_hclk_low;
 
 extern int s5p64x0_pclk_ctrl(struct clk *clk, int enable);
diff --git a/arch/arm/mach-s5p64x0/include/mach/system.h b/arch/arm/mach-s5p64x0/include/mach/system.h
deleted file mode 100644
index cf26e0954a2..00000000000
--- a/arch/arm/mach-s5p64x0/include/mach/system.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/* linux/arch/arm/mach-s5p64x0/include/mach/system.h
- *
- * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com
- *
- * S5P64X0 - system support header
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __ASM_ARCH_SYSTEM_H
-#define __ASM_ARCH_SYSTEM_H __FILE__
-
-static void arch_idle(void)
-{
-        /* nothing here yet */
-}
-
-#endif /* __ASM_ARCH_SYSTEM_H */
diff --git a/arch/arm/mach-s5pc100/clock.c b/arch/arm/mach-s5pc100/clock.c
index 247194dd366..16eca4ea201 100644
--- a/arch/arm/mach-s5pc100/clock.c
+++ b/arch/arm/mach-s5pc100/clock.c
@@ -170,7 +170,7 @@ static struct clk *clk_src_mout_am_list[] = {
         [1] = &clk_div_apll2.clk,
 };
 
-struct clksrc_sources clk_src_mout_am = {
+static struct clksrc_sources clk_src_mout_am = {
         .sources        = clk_src_mout_am_list,
         .nr_sources     = ARRAY_SIZE(clk_src_mout_am_list),
 };
@@ -212,7 +212,7 @@ static struct clk *clk_src_mout_onenand_list[] = {
         [1] = &clk_div_d1_bus.clk,
 };
 
-struct clksrc_sources clk_src_mout_onenand = {
+static struct clksrc_sources clk_src_mout_onenand = {
         .sources        = clk_src_mout_onenand_list,
         .nr_sources     = ARRAY_SIZE(clk_src_mout_onenand_list),
 };
@@ -756,7 +756,7 @@ static struct clk *clk_src_group1_list[] = {
         [3] = &clk_mout_hpll.clk,
 };
 
-struct clksrc_sources clk_src_group1 = {
+static struct clksrc_sources clk_src_group1 = {
         .sources        = clk_src_group1_list,
         .nr_sources     = ARRAY_SIZE(clk_src_group1_list),
 };
@@ -766,7 +766,7 @@ static struct clk *clk_src_group2_list[] = {
         [1] = &clk_div_mpll.clk,
 };
 
-struct clksrc_sources clk_src_group2 = {
+static struct clksrc_sources clk_src_group2 = {
         .sources        = clk_src_group2_list,
         .nr_sources     = ARRAY_SIZE(clk_src_group2_list),
 };
@@ -780,7 +780,7 @@ static struct clk *clk_src_group3_list[] = {
         [5] = &clk_mout_hpll.clk,
 };
 
-struct clksrc_sources clk_src_group3 = {
+static struct clksrc_sources clk_src_group3 = {
         .sources        = clk_src_group3_list,
         .nr_sources     = ARRAY_SIZE(clk_src_group3_list),
 };
@@ -806,7 +806,7 @@ static struct clk *clk_src_group4_list[] = {
         [5] = &clk_mout_hpll.clk,
 };
 
-struct clksrc_sources clk_src_group4 = {
+static struct clksrc_sources clk_src_group4 = {
         .sources        = clk_src_group4_list,
         .nr_sources     = ARRAY_SIZE(clk_src_group4_list),
 };
@@ -831,7 +831,7 @@ static struct clk *clk_src_group5_list[] = {
         [4] = &clk_mout_hpll.clk,
 };
 
-struct clksrc_sources clk_src_group5 = {
+static struct clksrc_sources clk_src_group5 = {
         .sources        = clk_src_group5_list,
         .nr_sources     = ARRAY_SIZE(clk_src_group5_list),
 };
@@ -854,7 +854,7 @@ static struct clk *clk_src_group6_list[] = {
         [2] = &clk_div_hdmi.clk,
 };
 
-struct clksrc_sources clk_src_group6 = {
+static struct clksrc_sources clk_src_group6 = {
         .sources        = clk_src_group6_list,
         .nr_sources     = ARRAY_SIZE(clk_src_group6_list),
 };
@@ -866,7 +866,7 @@ static struct clk *clk_src_group7_list[] = {
         [3] = &clk_vclk54m,
 };
 
-struct clksrc_sources clk_src_group7 = {
+static struct clksrc_sources clk_src_group7 = {
         .sources        = clk_src_group7_list,
         .nr_sources     = ARRAY_SIZE(clk_src_group7_list),
 };
@@ -877,7 +877,7 @@ static struct clk *clk_src_mmc0_list[] = {
         [2] = &clk_fin_epll,
 };
 
-struct clksrc_sources clk_src_mmc0 = {
+static struct clksrc_sources clk_src_mmc0 = {
         .sources        = clk_src_mmc0_list,
         .nr_sources     = ARRAY_SIZE(clk_src_mmc0_list),
 };
@@ -889,7 +889,7 @@ static struct clk *clk_src_mmc12_list[] = {
         [3] = &clk_mout_hpll.clk,
 };
 
-struct clksrc_sources clk_src_mmc12 = {
+static struct clksrc_sources clk_src_mmc12 = {
         .sources        = clk_src_mmc12_list,
         .nr_sources     = ARRAY_SIZE(clk_src_mmc12_list),
 };
@@ -901,7 +901,7 @@ static struct clk *clk_src_irda_usb_list[] = {
         [3] = &clk_mout_hpll.clk,
 };
 
-struct clksrc_sources clk_src_irda_usb = {
+static struct clksrc_sources clk_src_irda_usb = {
         .sources        = clk_src_irda_usb_list,
         .nr_sources     = ARRAY_SIZE(clk_src_irda_usb_list),
 };
@@ -912,7 +912,7 @@ static struct clk *clk_src_pwi_list[] = {
         [2] = &clk_div_mpll.clk,
 };
 
-struct clksrc_sources clk_src_pwi = {
+static struct clksrc_sources clk_src_pwi = {
         .sources        = clk_src_pwi_list,
         .nr_sources     = ARRAY_SIZE(clk_src_pwi_list),
 };
@@ -923,7 +923,7 @@ static struct clk *clk_sclk_spdif_list[] = {
         [2] = &clk_sclk_audio2.clk,
 };
 
-struct clksrc_sources clk_src_sclk_spdif = {
+static struct clksrc_sources clk_src_sclk_spdif = {
         .sources        = clk_sclk_spdif_list,
         .nr_sources     = ARRAY_SIZE(clk_sclk_spdif_list),
 };
diff --git a/arch/arm/mach-s5pc100/common.c b/arch/arm/mach-s5pc100/common.c
index c9095730a7f..ff71e2d467c 100644
--- a/arch/arm/mach-s5pc100/common.c
+++ b/arch/arm/mach-s5pc100/common.c
@@ -129,14 +129,6 @@ static struct map_desc s5pc100_iodesc[] __initdata = {
         }
 };
 
-static void s5pc100_idle(void)
-{
-        if (!need_resched())
-                cpu_do_idle();
-
-        local_irq_enable();
-}
-
 /*
  * s5pc100_map_io
  *
@@ -210,10 +202,6 @@ core_initcall(s5pc100_core_init);
 int __init s5pc100_init(void)
 {
         printk(KERN_INFO "S5PC100: Initializing architecture\n");
-
-        /* set idle function */
-        pm_idle = s5pc100_idle;
-
         return device_register(&s5pc100_dev);
 }
 
diff --git a/arch/arm/mach-s5pc100/dma.c b/arch/arm/mach-s5pc100/dma.c
index c841f4d313f..afd8db2d599 100644
--- a/arch/arm/mach-s5pc100/dma.c
+++ b/arch/arm/mach-s5pc100/dma.c
@@ -35,7 +35,7 @@
 
 static u64 dma_dmamask = DMA_BIT_MASK(32);
 
-u8 pdma0_peri[] = {
+static u8 pdma0_peri[] = {
         DMACH_UART0_RX,
         DMACH_UART0_TX,
         DMACH_UART1_RX,
@@ -68,28 +68,15 @@ u8 pdma0_peri[] = {
         DMACH_HSI_TX,
 };
 
-struct dma_pl330_platdata s5pc100_pdma0_pdata = {
+static struct dma_pl330_platdata s5pc100_pdma0_pdata = {
         .nr_valid_peri = ARRAY_SIZE(pdma0_peri),
         .peri_id = pdma0_peri,
 };
 
-struct amba_device s5pc100_device_pdma0 = {
-        .dev = {
-                .init_name = "dma-pl330.0",
-                .dma_mask = &dma_dmamask,
-                .coherent_dma_mask = DMA_BIT_MASK(32),
-                .platform_data = &s5pc100_pdma0_pdata,
-        },
-        .res = {
-                .start = S5PC100_PA_PDMA0,
-                .end = S5PC100_PA_PDMA0 + SZ_4K,
-                .flags = IORESOURCE_MEM,
-        },
-        .irq = {IRQ_PDMA0, NO_IRQ},
-        .periphid = 0x00041330,
-};
+static AMBA_AHB_DEVICE(s5pc100_pdma0,  "dma-pl330.0", 0x00041330,
+        S5PC100_PA_PDMA0, {IRQ_PDMA0}, &s5pc100_pdma0_pdata);
 
-u8 pdma1_peri[] = {
+static u8 pdma1_peri[] = {
         DMACH_UART0_RX,
         DMACH_UART0_TX,
         DMACH_UART1_RX,
@@ -122,36 +109,23 @@ u8 pdma1_peri[] = {
         DMACH_MSM_REQ3,
 };
 
-struct dma_pl330_platdata s5pc100_pdma1_pdata = {
+static struct dma_pl330_platdata s5pc100_pdma1_pdata = {
         .nr_valid_peri = ARRAY_SIZE(pdma1_peri),
         .peri_id = pdma1_peri,
 };
 
-struct amba_device s5pc100_device_pdma1 = {
-        .dev = {
-                .init_name = "dma-pl330.1",
-                .dma_mask = &dma_dmamask,
-                .coherent_dma_mask = DMA_BIT_MASK(32),
-                .platform_data = &s5pc100_pdma1_pdata,
-        },
-        .res = {
-                .start = S5PC100_PA_PDMA1,
-                .end = S5PC100_PA_PDMA1 + SZ_4K,
-                .flags = IORESOURCE_MEM,
-        },
-        .irq = {IRQ_PDMA1, NO_IRQ},
-        .periphid = 0x00041330,
-};
+static AMBA_AHB_DEVICE(s5pc100_pdma1, "dma-pl330.1", 0x00041330,
+        S5PC100_PA_PDMA1, {IRQ_PDMA1}, &s5pc100_pdma1_pdata);
 
 static int __init s5pc100_dma_init(void)
 {
         dma_cap_set(DMA_SLAVE, s5pc100_pdma0_pdata.cap_mask);
         dma_cap_set(DMA_CYCLIC, s5pc100_pdma0_pdata.cap_mask);
-        amba_device_register(&s5pc100_device_pdma0, &iomem_resource);
+        amba_device_register(&s5pc100_pdma0_device, &iomem_resource);
 
         dma_cap_set(DMA_SLAVE, s5pc100_pdma1_pdata.cap_mask);
         dma_cap_set(DMA_CYCLIC, s5pc100_pdma1_pdata.cap_mask);
-        amba_device_register(&s5pc100_device_pdma1, &iomem_resource);
+        amba_device_register(&s5pc100_pdma1_device, &iomem_resource);
 
         return 0;
 }
diff --git a/arch/arm/mach-s5pc100/include/mach/entry-macro.S b/arch/arm/mach-s5pc100/include/mach/entry-macro.S
index b8c242edfa2..bad0700457d 100644
--- a/arch/arm/mach-s5pc100/include/mach/entry-macro.S
+++ b/arch/arm/mach-s5pc100/include/mach/entry-macro.S
@@ -12,14 +12,8 @@
  * warranty of any kind, whether express or implied.
 */
 
-        .macro  disable_fiq
-        .endm
-
         .macro  get_irqnr_preamble, base, tmp
         .endm
 
-        .macro  arch_ret_to_user, tmp1, tmp2
-        .endm
-
         .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
         .endm
diff --git a/arch/arm/mach-s5pc100/include/mach/system.h b/arch/arm/mach-s5pc100/include/mach/system.h
deleted file mode 100644
index afc96c29851..00000000000
--- a/arch/arm/mach-s5pc100/include/mach/system.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/* linux/arch/arm/mach-s5pc100/include/mach/system.h
- *
- * Copyright 2009 Samsung Electronics Co.
- *      Byungho Min <bhmin@samsung.com>
- *
- * S5PC100 - system implementation
- *
- * Based on mach-s3c6400/include/mach/system.h
- */
-
-#ifndef __ASM_ARCH_SYSTEM_H
-#define __ASM_ARCH_SYSTEM_H __FILE__
-
-static void arch_idle(void)
-{
-        /* nothing here yet */
-}
-
-#endif /* __ASM_ARCH_IRQ_H */
diff --git a/arch/arm/mach-s5pv210/Kconfig b/arch/arm/mach-s5pv210/Kconfig
index 2cdc42e838b..29594fc4fdf 100644
--- a/arch/arm/mach-s5pv210/Kconfig
+++ b/arch/arm/mach-s5pv210/Kconfig
@@ -65,6 +65,11 @@ config S5PV210_SETUP_SPI
         help
           Common setup code for SPI GPIO configurations.
 
+config S5PV210_SETUP_USB_PHY
+        bool
+        help
+          Common setup code for USB PHY controller
+
 menu "S5PC110 Machines"
 
 config MACH_AQUILA
@@ -107,6 +112,7 @@ config MACH_GONI
         select S5PV210_SETUP_KEYPAD
         select S5PV210_SETUP_SDHCI
         select S5PV210_SETUP_FIMC
+        select S5PV210_SETUP_USB_PHY
         help
           Machine support for Samsung GONI board
           S5PC110(MCP) is one of package option of S5PV210
@@ -118,6 +124,10 @@ config MACH_SMDKC110
         select S3C_DEV_I2C2
         select S3C_DEV_RTC
         select S3C_DEV_WDT
+        select S5P_DEV_FIMC0
+        select S5P_DEV_FIMC1
+        select S5P_DEV_FIMC2
+        select S5P_DEV_MFC
         select SAMSUNG_DEV_IDE
         select S5PV210_SETUP_I2C1
         select S5PV210_SETUP_I2C2
@@ -142,6 +152,11 @@ config MACH_SMDKV210
         select S3C_DEV_I2C2
         select S3C_DEV_RTC
         select S3C_DEV_WDT
+        select S5P_DEV_FIMC0
+        select S5P_DEV_FIMC1
+        select S5P_DEV_FIMC2
+        select S5P_DEV_JPEG
+        select S5P_DEV_MFC
         select SAMSUNG_DEV_ADC
         select SAMSUNG_DEV_BACKLIGHT
         select SAMSUNG_DEV_IDE
diff --git a/arch/arm/mach-s5pv210/Makefile b/arch/arm/mach-s5pv210/Makefile
index 76a121dd52b..1c4e41998a1 100644
--- a/arch/arm/mach-s5pv210/Makefile
+++ b/arch/arm/mach-s5pv210/Makefile
@@ -39,3 +39,4 @@ obj-$(CONFIG_S5PV210_SETUP_IDE)		+= setup-ide.o
 obj-$(CONFIG_S5PV210_SETUP_KEYPAD)      += setup-keypad.o
 obj-$(CONFIG_S5PV210_SETUP_SDHCI_GPIO)  += setup-sdhci-gpio.o
 obj-$(CONFIG_S5PV210_SETUP_SPI)         += setup-spi.o
+obj-$(CONFIG_S5PV210_SETUP_USB_PHY) += setup-usb-phy.o
diff --git a/arch/arm/mach-s5pv210/clock.c b/arch/arm/mach-s5pv210/clock.c
index b9ec0c35379..09609d50961 100644
--- a/arch/arm/mach-s5pv210/clock.c
+++ b/arch/arm/mach-s5pv210/clock.c
@@ -340,6 +340,11 @@ static struct clk init_clocks_off[] = {
                 .enable         = s5pv210_clk_ip0_ctrl,
                 .ctrlbit        = (1 << 26),
         }, {
+                .name           = "jpeg",
+                .parent         = &clk_hclk_dsys.clk,
+                .enable         = s5pv210_clk_ip0_ctrl,
+                .ctrlbit        = (1 << 28),
+        }, {
                 .name           = "mfc",
                 .devname        = "s5p-mfc",
                 .parent         = &clk_pclk_psys.clk,
diff --git a/arch/arm/mach-s5pv210/common.c b/arch/arm/mach-s5pv210/common.c
index 9c1bcdcc12c..4c9e9027df9 100644
--- a/arch/arm/mach-s5pv210/common.c
+++ b/arch/arm/mach-s5pv210/common.c
@@ -142,14 +142,6 @@ static struct map_desc s5pv210_iodesc[] __initdata = {
         }
 };
 
-static void s5pv210_idle(void)
-{
-        if (!need_resched())
-                cpu_do_idle();
-
-        local_irq_enable();
-}
-
 void s5pv210_restart(char mode, const char *cmd)
 {
         __raw_writel(0x1, S5P_SWRESET);
@@ -247,10 +239,6 @@ core_initcall(s5pv210_core_init);
 int __init s5pv210_init(void)
 {
         printk(KERN_INFO "S5PV210: Initializing architecture\n");
-
-        /* set idle function */
-        pm_idle = s5pv210_idle;
-
         return device_register(&s5pv210_dev);
 }
 
diff --git a/arch/arm/mach-s5pv210/dma.c b/arch/arm/mach-s5pv210/dma.c
index a6113e0267f..86ce62f6619 100644
--- a/arch/arm/mach-s5pv210/dma.c
+++ b/arch/arm/mach-s5pv210/dma.c
@@ -35,7 +35,7 @@
 
 static u64 dma_dmamask = DMA_BIT_MASK(32);
 
-u8 pdma0_peri[] = {
+static u8 pdma0_peri[] = {
         DMACH_UART0_RX,
         DMACH_UART0_TX,
         DMACH_UART1_RX,
@@ -66,28 +66,15 @@ u8 pdma0_peri[] = {
         DMACH_SPDIF,
 };
 
-struct dma_pl330_platdata s5pv210_pdma0_pdata = {
+static struct dma_pl330_platdata s5pv210_pdma0_pdata = {
         .nr_valid_peri = ARRAY_SIZE(pdma0_peri),
         .peri_id = pdma0_peri,
 };
 
-struct amba_device s5pv210_device_pdma0 = {
-        .dev = {
-                .init_name = "dma-pl330.0",
-                .dma_mask = &dma_dmamask,
-                .coherent_dma_mask = DMA_BIT_MASK(32),
-                .platform_data = &s5pv210_pdma0_pdata,
-        },
-        .res = {
-                .start = S5PV210_PA_PDMA0,
-                .end = S5PV210_PA_PDMA0 + SZ_4K,
-                .flags = IORESOURCE_MEM,
-        },
-        .irq = {IRQ_PDMA0, NO_IRQ},
-        .periphid = 0x00041330,
-};
+static AMBA_AHB_DEVICE(s5pv210_pdma0, "dma-pl330.0", 0x00041330,
+        S5PV210_PA_PDMA0, {IRQ_PDMA0}, &s5pv210_pdma0_pdata);
 
-u8 pdma1_peri[] = {
+static u8 pdma1_peri[] = {
         DMACH_UART0_RX,
         DMACH_UART0_TX,
         DMACH_UART1_RX,
@@ -122,36 +109,23 @@ u8 pdma1_peri[] = {
         DMACH_PCM2_TX,
 };
 
-struct dma_pl330_platdata s5pv210_pdma1_pdata = {
+static struct dma_pl330_platdata s5pv210_pdma1_pdata = {
         .nr_valid_peri = ARRAY_SIZE(pdma1_peri),
         .peri_id = pdma1_peri,
 };
 
-struct amba_device s5pv210_device_pdma1 = {
-        .dev = {
-                .init_name = "dma-pl330.1",
-                .dma_mask = &dma_dmamask,
-                .coherent_dma_mask = DMA_BIT_MASK(32),
-                .platform_data = &s5pv210_pdma1_pdata,
-        },
-        .res = {
-                .start = S5PV210_PA_PDMA1,
-                .end = S5PV210_PA_PDMA1 + SZ_4K,
-                .flags = IORESOURCE_MEM,
-        },
-        .irq = {IRQ_PDMA1, NO_IRQ},
-        .periphid = 0x00041330,
-};
+static AMBA_AHB_DEVICE(s5pv210_pdma1, "dma-pl330.1", 0x00041330,
+        S5PV210_PA_PDMA1, {IRQ_PDMA1}, &s5pv210_pdma1_pdata);
 
 static int __init s5pv210_dma_init(void)
 {
         dma_cap_set(DMA_SLAVE, s5pv210_pdma0_pdata.cap_mask);
         dma_cap_set(DMA_CYCLIC, s5pv210_pdma0_pdata.cap_mask);
-        amba_device_register(&s5pv210_device_pdma0, &iomem_resource);
+        amba_device_register(&s5pv210_pdma0_device, &iomem_resource);
 
         dma_cap_set(DMA_SLAVE, s5pv210_pdma1_pdata.cap_mask);
         dma_cap_set(DMA_CYCLIC, s5pv210_pdma1_pdata.cap_mask);
-        amba_device_register(&s5pv210_device_pdma1, &iomem_resource);
+        amba_device_register(&s5pv210_pdma1_device, &iomem_resource);
 
         return 0;
 }
diff --git a/arch/arm/mach-s5pv210/include/mach/entry-macro.S b/arch/arm/mach-s5pv210/include/mach/entry-macro.S
deleted file mode 100644
index bebca1b5d0b..00000000000
--- a/arch/arm/mach-s5pv210/include/mach/entry-macro.S
+++ /dev/null
@@ -1,17 +0,0 @@
-/* linux/arch/arm/mach-s5pv210/include/mach/entry-macro.S
- *
- * Copyright (c) 2010 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com/
- *
- * Low-level IRQ helper macros for the Samsung S5PV210
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-        .macro  disable_fiq
-        .endm
-
-        .macro  arch_ret_to_user, tmp1, tmp2
-        .endm
diff --git a/arch/arm/mach-s5pv210/include/mach/map.h b/arch/arm/mach-s5pv210/include/mach/map.h
index 89c34b8f73b..b7c8a1917ff 100644
--- a/arch/arm/mach-s5pv210/include/mach/map.h
+++ b/arch/arm/mach-s5pv210/include/mach/map.h
@@ -90,6 +90,8 @@
 #define S5PV210_PA_FIMC1                0xFB300000
 #define S5PV210_PA_FIMC2                0xFB400000
 
+#define S5PV210_PA_JPEG                 0xFB600000
+
 #define S5PV210_PA_SDO                  0xF9000000
 #define S5PV210_PA_VP                   0xF9100000
 #define S5PV210_PA_MIXER                0xF9200000
@@ -132,6 +134,8 @@
 #define S5P_PA_SYSCON                   S5PV210_PA_SYSCON
 #define S5P_PA_TIMER                    S5PV210_PA_TIMER
 
+#define S5P_PA_JPEG                     S5PV210_PA_JPEG
+
 #define SAMSUNG_PA_ADC                  S5PV210_PA_ADC
 #define SAMSUNG_PA_CFCON                S5PV210_PA_CFCON
 #define SAMSUNG_PA_KEYPAD               S5PV210_PA_KEYPAD
diff --git a/arch/arm/mach-s5pv210/include/mach/regs-sys.h b/arch/arm/mach-s5pv210/include/mach/regs-sys.h
index 26691d39d0f..cccb1eddaa3 100644
--- a/arch/arm/mach-s5pv210/include/mach/regs-sys.h
+++ b/arch/arm/mach-s5pv210/include/mach/regs-sys.h
@@ -13,7 +13,3 @@
 #define S5PV210_USB_PHY_CON     (S3C_VA_SYS + 0xE80C)
 #define S5PV210_USB_PHY0_EN     (1 << 0)
 #define S5PV210_USB_PHY1_EN     (1 << 1)
-
-/* compatibility defines for s3c-hsotg driver */
-#define S3C64XX_OTHERS          S5PV210_USB_PHY_CON
-#define S3C64XX_OTHERS_USBMASK  S5PV210_USB_PHY0_EN
diff --git a/arch/arm/mach-s5pv210/include/mach/system.h b/arch/arm/mach-s5pv210/include/mach/system.h
deleted file mode 100644
index bf288ced860..00000000000
--- a/arch/arm/mach-s5pv210/include/mach/system.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/* linux/arch/arm/mach-s5pv210/include/mach/system.h
- *
- * Copyright (c) 2010 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com/
- *
- * S5PV210 - system support header
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __ASM_ARCH_SYSTEM_H
-#define __ASM_ARCH_SYSTEM_H __FILE__
-
-static void arch_idle(void)
-{
-        /* nothing here yet */
-}
-
-#endif /* __ASM_ARCH_SYSTEM_H */
diff --git a/arch/arm/mach-s5pv210/mach-aquila.c b/arch/arm/mach-s5pv210/mach-aquila.c
index 5e734d025a6..a9ea64e0da0 100644
--- a/arch/arm/mach-s5pv210/mach-aquila.c
+++ b/arch/arm/mach-s5pv210/mach-aquila.c
@@ -616,6 +616,7 @@ static struct platform_device *aquila_devices[] __initdata = {
         &s5p_device_fimc0,
         &s5p_device_fimc1,
         &s5p_device_fimc2,
+        &s5p_device_fimc_md,
         &s5pv210_device_iis0,
         &wm8994_fixed_voltage0,
         &wm8994_fixed_voltage1,
diff --git a/arch/arm/mach-s5pv210/mach-goni.c b/arch/arm/mach-s5pv210/mach-goni.c
index ff915261043..2cf5ed75f39 100644
--- a/arch/arm/mach-s5pv210/mach-goni.c
+++ b/arch/arm/mach-s5pv210/mach-goni.c
@@ -844,7 +844,7 @@ static struct s5p_fimc_isp_info goni_camera_sensors[] = {
         },
 };
 
-struct s5p_platform_fimc goni_fimc_md_platdata __initdata = {
+static struct s5p_platform_fimc goni_fimc_md_platdata __initdata = {
         .isp_info       = goni_camera_sensors,
         .num_clients    = ARRAY_SIZE(goni_camera_sensors),
 };
diff --git a/arch/arm/mach-s5pv210/mach-smdkc110.c b/arch/arm/mach-s5pv210/mach-smdkc110.c
index b323983b2c5..dfc29236321 100644
--- a/arch/arm/mach-s5pv210/mach-smdkc110.c
+++ b/arch/arm/mach-s5pv210/mach-smdkc110.c
@@ -31,6 +31,7 @@
 #include <plat/iic.h>
 #include <plat/pm.h>
 #include <plat/s5p-time.h>
+#include <plat/mfc.h>
 
 #include "common.h"
 
@@ -94,6 +95,13 @@ static struct platform_device *smdkc110_devices[] __initdata = {
         &s3c_device_i2c2,
         &s3c_device_rtc,
         &s3c_device_wdt,
+        &s5p_device_fimc0,
+        &s5p_device_fimc1,
+        &s5p_device_fimc2,
+        &s5p_device_fimc_md,
+        &s5p_device_mfc,
+        &s5p_device_mfc_l,
+        &s5p_device_mfc_r,
 };
 
 static struct i2c_board_info smdkc110_i2c_devs0[] __initdata = {
@@ -117,6 +125,11 @@ static void __init smdkc110_map_io(void)
         s5p_set_timer_source(S5P_PWM3, S5P_PWM4);
 }
 
+static void __init smdkc110_reserve(void)
+{
+        s5p_mfc_reserve_mem(0x43000000, 8 << 20, 0x51000000, 8 << 20);
+}
+
 static void __init smdkc110_machine_init(void)
 {
         s3c_pm_init();
@@ -145,4 +158,5 @@ MACHINE_START(SMDKC110, "SMDKC110")
         .init_machine   = smdkc110_machine_init,
         .timer          = &s5p_timer,
         .restart        = s5pv210_restart,
+        .reserve        = &smdkc110_reserve,
 MACHINE_END
diff --git a/arch/arm/mach-s5pv210/mach-smdkv210.c b/arch/arm/mach-s5pv210/mach-smdkv210.c
index dff9ea7b5bb..91d4ad8bcc7 100644
--- a/arch/arm/mach-s5pv210/mach-smdkv210.c
+++ b/arch/arm/mach-s5pv210/mach-smdkv210.c
@@ -46,6 +46,7 @@
 #include <plat/s5p-time.h>
 #include <plat/backlight.h>
 #include <plat/regs-fb-v4.h>
+#include <plat/mfc.h>
 
 #include "common.h"
 
@@ -140,7 +141,7 @@ static struct dm9000_plat_data smdkv210_dm9000_platdata = {
         .dev_addr       = { 0x00, 0x09, 0xc0, 0xff, 0xec, 0x48 },
 };
 
-struct platform_device smdkv210_dm9000 = {
+static struct platform_device smdkv210_dm9000 = {
         .name           = "dm9000",
         .id             = -1,
         .num_resources  = ARRAY_SIZE(smdkv210_dm9000_resources),
@@ -223,6 +224,14 @@ static struct platform_device *smdkv210_devices[] __initdata = {
         &s3c_device_rtc,
         &s3c_device_ts,
         &s3c_device_wdt,
+        &s5p_device_fimc0,
+        &s5p_device_fimc1,
+        &s5p_device_fimc2,
+        &s5p_device_fimc_md,
+        &s5p_device_jpeg,
+        &s5p_device_mfc,
+        &s5p_device_mfc_l,
+        &s5p_device_mfc_r,
         &s5pv210_device_ac97,
         &s5pv210_device_iis0,
         &s5pv210_device_spdif,
@@ -282,6 +291,11 @@ static void __init smdkv210_map_io(void)
         s5p_set_timer_source(S5P_PWM2, S5P_PWM4);
 }
 
+static void __init smdkv210_reserve(void)
+{
+        s5p_mfc_reserve_mem(0x43000000, 8 << 20, 0x51000000, 8 << 20);
+}
+
 static void __init smdkv210_machine_init(void)
 {
         s3c_pm_init();
@@ -319,4 +333,5 @@ MACHINE_START(SMDKV210, "SMDKV210")
         .init_machine   = smdkv210_machine_init,
         .timer          = &s5p_timer,
         .restart        = s5pv210_restart,
+        .reserve        = &smdkv210_reserve,
 MACHINE_END
diff --git a/arch/arm/mach-s5pv210/setup-usb-phy.c b/arch/arm/mach-s5pv210/setup-usb-phy.c
new file mode 100644
index 00000000000..be39cf4aa91
--- /dev/null
+++ b/arch/arm/mach-s5pv210/setup-usb-phy.c
@@ -0,0 +1,90 @@
+/*
+ * Copyright (C) 2012 Samsung Electronics Co.Ltd
+ * Author: Joonyoung Shim <jy0922.shim@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundationr
+ */
+
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/platform_device.h>
+#include <mach/map.h>
+#include <mach/regs-sys.h>
+#include <plat/cpu.h>
+#include <plat/regs-usb-hsotg-phy.h>
+#include <plat/usb-phy.h>
+
+static int s5pv210_usb_otgphy_init(struct platform_device *pdev)
+{
+        struct clk *xusbxti;
+        u32 phyclk;
+
+        writel(readl(S5PV210_USB_PHY_CON) | S5PV210_USB_PHY0_EN,
+                        S5PV210_USB_PHY_CON);
+
+        /* set clock frequency for PLL */
+        phyclk = readl(S3C_PHYCLK) & ~S3C_PHYCLK_CLKSEL_MASK;
+
+        xusbxti = clk_get(&pdev->dev, "xusbxti");
+        if (xusbxti && !IS_ERR(xusbxti)) {
+                switch (clk_get_rate(xusbxti)) {
+                case 12 * MHZ:
+                        phyclk |= S3C_PHYCLK_CLKSEL_12M;
+                        break;
+                case 24 * MHZ:
+                        phyclk |= S3C_PHYCLK_CLKSEL_24M;
+                        break;
+                default:
+                case 48 * MHZ:
+                        /* default reference clock */
+                        break;
+                }
+                clk_put(xusbxti);
+        }
+
+        /* TODO: select external clock/oscillator */
+        writel(phyclk | S3C_PHYCLK_CLK_FORCE, S3C_PHYCLK);
+
+        /* set to normal OTG PHY */
+        writel((readl(S3C_PHYPWR) & ~S3C_PHYPWR_NORMAL_MASK), S3C_PHYPWR);
+        mdelay(1);
+
+        /* reset OTG PHY and Link */
+        writel(S3C_RSTCON_PHY | S3C_RSTCON_HCLK | S3C_RSTCON_PHYCLK,
+                        S3C_RSTCON);
+        udelay(20);     /* at-least 10uS */
+        writel(0, S3C_RSTCON);
+
+        return 0;
+}
+
+static int s5pv210_usb_otgphy_exit(struct platform_device *pdev)
+{
+        writel((readl(S3C_PHYPWR) | S3C_PHYPWR_ANALOG_POWERDOWN |
+                                S3C_PHYPWR_OTG_DISABLE), S3C_PHYPWR);
+
+        writel(readl(S5PV210_USB_PHY_CON) & ~S5PV210_USB_PHY0_EN,
+                        S5PV210_USB_PHY_CON);
+
+        return 0;
+}
+
+int s5p_usb_phy_init(struct platform_device *pdev, int type)
+{
+        if (type == S5P_USB_PHY_DEVICE)
+                return s5pv210_usb_otgphy_init(pdev);
+
+        return -EINVAL;
+}
+
+int s5p_usb_phy_exit(struct platform_device *pdev, int type)
+{
+        if (type == S5P_USB_PHY_DEVICE)
+                return s5pv210_usb_otgphy_exit(pdev);
+
+        return -EINVAL;
+}
diff --git a/arch/arm/mach-sa1100/clock.c b/arch/arm/mach-sa1100/clock.c
index dab3c6347a8..172ebd0ee0a 100644
--- a/arch/arm/mach-sa1100/clock.c
+++ b/arch/arm/mach-sa1100/clock.c
@@ -11,17 +11,29 @@
 #include <linux/clk.h>
 #include <linux/spinlock.h>
 #include <linux/mutex.h>
+#include <linux/io.h>
+#include <linux/clkdev.h>
 
 #include <mach/hardware.h>
 
-/*
- * Very simple clock implementation - we only have one clock to deal with.
- */
+struct clkops {
+        void                    (*enable)(struct clk *);
+        void                    (*disable)(struct clk *);
+};
+
 struct clk {
+        const struct clkops     *ops;
         unsigned int            enabled;
 };
 
-static void clk_gpio27_enable(void)
+#define DEFINE_CLK(_name, _ops)                         \
+struct clk clk_##_name = {                              \
+                .ops    = _ops,                         \
+        }
+
+static DEFINE_SPINLOCK(clocks_lock);
+
+static void clk_gpio27_enable(struct clk *clk)
 {
         /*
          * First, set up the 3.6864MHz clock on GPIO 27 for the SA-1111:
@@ -32,38 +44,24 @@ static void clk_gpio27_enable(void)
         TUCR = TUCR_3_6864MHz;
 }
 
-static void clk_gpio27_disable(void)
+static void clk_gpio27_disable(struct clk *clk)
 {
         TUCR = 0;
         GPDR &= ~GPIO_32_768kHz;
         GAFR &= ~GPIO_32_768kHz;
 }
 
-static struct clk clk_gpio27;
-
-static DEFINE_SPINLOCK(clocks_lock);
-
-struct clk *clk_get(struct device *dev, const char *id)
-{
-        const char *devname = dev_name(dev);
-
-        return strcmp(devname, "sa1111.0") ? ERR_PTR(-ENOENT) : &clk_gpio27;
-}
-EXPORT_SYMBOL(clk_get);
-
-void clk_put(struct clk *clk)
-{
-}
-EXPORT_SYMBOL(clk_put);
-
 int clk_enable(struct clk *clk)
 {
         unsigned long flags;
 
-        spin_lock_irqsave(&clocks_lock, flags);
-        if (clk->enabled++ == 0)
-                clk_gpio27_enable();
-        spin_unlock_irqrestore(&clocks_lock, flags);
+        if (clk) {
+                spin_lock_irqsave(&clocks_lock, flags);
+                if (clk->enabled++ == 0)
+                        clk->ops->enable(clk);
+                spin_unlock_irqrestore(&clocks_lock, flags);
+        }
+
         return 0;
 }
 EXPORT_SYMBOL(clk_enable);
@@ -72,17 +70,31 @@ void clk_disable(struct clk *clk)
 {
         unsigned long flags;
 
-        WARN_ON(clk->enabled == 0);
-
-        spin_lock_irqsave(&clocks_lock, flags);
-        if (--clk->enabled == 0)
-                clk_gpio27_disable();
-        spin_unlock_irqrestore(&clocks_lock, flags);
+        if (clk) {
+                WARN_ON(clk->enabled == 0);
+                spin_lock_irqsave(&clocks_lock, flags);
+                if (--clk->enabled == 0)
+                        clk->ops->disable(clk);
+                spin_unlock_irqrestore(&clocks_lock, flags);
+        }
 }
 EXPORT_SYMBOL(clk_disable);
 
-unsigned long clk_get_rate(struct clk *clk)
+const struct clkops clk_gpio27_ops = {
+        .enable         = clk_gpio27_enable,
+        .disable        = clk_gpio27_disable,
+};
+
+static DEFINE_CLK(gpio27, &clk_gpio27_ops);
+
+static struct clk_lookup sa11xx_clkregs[] = {
+        CLKDEV_INIT("sa1111.0", NULL, &clk_gpio27),
+        CLKDEV_INIT("sa1100-rtc", NULL, NULL),
+};
+
+static int __init sa11xx_clk_init(void)
 {
-        return 3686400;
+        clkdev_add_table(sa11xx_clkregs, ARRAY_SIZE(sa11xx_clkregs));
+        return 0;
 }
-EXPORT_SYMBOL(clk_get_rate);
+core_initcall(sa11xx_clk_init);
diff --git a/arch/arm/mach-sa1100/generic.c b/arch/arm/mach-sa1100/generic.c
index bb10ee2cb89..7c1ebf4a792 100644
--- a/arch/arm/mach-sa1100/generic.c
+++ b/arch/arm/mach-sa1100/generic.c
@@ -345,9 +345,17 @@ void sa11x0_register_irda(struct irda_platform_data *irda)
         sa11x0_register_device(&sa11x0ir_device, irda);
 }
 
+static struct resource sa1100_rtc_resources[] = {
+        DEFINE_RES_MEM(0x90010000, 0x9001003f),
+        DEFINE_RES_IRQ_NAMED(IRQ_RTC1Hz, "rtc 1Hz"),
+        DEFINE_RES_IRQ_NAMED(IRQ_RTCAlrm, "rtc alarm"),
+};
+
 static struct platform_device sa11x0rtc_device = {
         .name           = "sa1100-rtc",
         .id             = -1,
+        .num_resources  = ARRAY_SIZE(sa1100_rtc_resources),
+        .resource       = sa1100_rtc_resources,
 };
 
 static struct platform_device *sa11x0_devices[] __initdata = {
diff --git a/arch/arm/mach-sa1100/include/mach/assabet.h b/arch/arm/mach-sa1100/include/mach/assabet.h
index 28c2cf50c25..307391488c2 100644
--- a/arch/arm/mach-sa1100/include/mach/assabet.h
+++ b/arch/arm/mach-sa1100/include/mach/assabet.h
@@ -85,21 +85,18 @@ extern void ASSABET_BCR_frob(unsigned int mask, unsigned int set);
 #define ASSABET_BSR_RAD_RI      (1 << 31)
 
 
-/* GPIOs for which the generic definition doesn't say much */
+/* GPIOs (bitmasks) for which the generic definition doesn't say much */
 #define ASSABET_GPIO_RADIO_IRQ          GPIO_GPIO (14)  /* Radio interrupt request  */
 #define ASSABET_GPIO_PS_MODE_SYNC       GPIO_GPIO (16)  /* Power supply mode/sync   */
 #define ASSABET_GPIO_STEREO_64FS_CLK    GPIO_GPIO (19)  /* SSP UDA1341 clock input  */
-#define ASSABET_GPIO_CF_IRQ             GPIO_GPIO (21)  /* CF IRQ   */
-#define ASSABET_GPIO_CF_CD              GPIO_GPIO (22)  /* CF CD */
-#define ASSABET_GPIO_CF_BVD2            GPIO_GPIO (24)  /* CF BVD */
 #define ASSABET_GPIO_GFX_IRQ            GPIO_GPIO (24)  /* Graphics IRQ */
-#define ASSABET_GPIO_CF_BVD1            GPIO_GPIO (25)  /* CF BVD */
 #define ASSABET_GPIO_BATT_LOW           GPIO_GPIO (26)  /* Low battery */
 #define ASSABET_GPIO_RCLK               GPIO_GPIO (26)  /* CCLK/2  */
 
-#define ASSABET_IRQ_GPIO_CF_IRQ         IRQ_GPIO21
-#define ASSABET_IRQ_GPIO_CF_CD          IRQ_GPIO22
-#define ASSABET_IRQ_GPIO_CF_BVD2        IRQ_GPIO24
-#define ASSABET_IRQ_GPIO_CF_BVD1        IRQ_GPIO25
+/* These are gpiolib GPIO numbers, not bitmasks */
+#define ASSABET_GPIO_CF_IRQ             21      /* CF IRQ */
+#define ASSABET_GPIO_CF_CD              22      /* CF CD  */
+#define ASSABET_GPIO_CF_BVD2            24      /* CF BVD / IOSPKR */
+#define ASSABET_GPIO_CF_BVD1            25      /* CF BVD / IOSTSCHG */
 
 #endif
diff --git a/arch/arm/mach-sa1100/include/mach/cerf.h b/arch/arm/mach-sa1100/include/mach/cerf.h
index c3ac3d0f946..88fd9c006ce 100644
--- a/arch/arm/mach-sa1100/include/mach/cerf.h
+++ b/arch/arm/mach-sa1100/include/mach/cerf.h
@@ -14,15 +14,10 @@
 #define CERF_ETH_IO                     0xf0000000
 #define CERF_ETH_IRQ IRQ_GPIO26
 
-#define CERF_GPIO_CF_BVD2               GPIO_GPIO (19)
-#define CERF_GPIO_CF_BVD1               GPIO_GPIO (20)
-#define CERF_GPIO_CF_RESET              GPIO_GPIO (21)
-#define CERF_GPIO_CF_IRQ                GPIO_GPIO (22)
-#define CERF_GPIO_CF_CD                 GPIO_GPIO (23)
-
-#define CERF_IRQ_GPIO_CF_BVD2           IRQ_GPIO19
-#define CERF_IRQ_GPIO_CF_BVD1           IRQ_GPIO20
-#define CERF_IRQ_GPIO_CF_IRQ            IRQ_GPIO22
-#define CERF_IRQ_GPIO_CF_CD             IRQ_GPIO23
+#define CERF_GPIO_CF_BVD2               19
+#define CERF_GPIO_CF_BVD1               20
+#define CERF_GPIO_CF_RESET              21
+#define CERF_GPIO_CF_IRQ                22
+#define CERF_GPIO_CF_CD                 23
 
 #endif // _INCLUDE_CERF_H_
diff --git a/arch/arm/mach-sa1100/include/mach/entry-macro.S b/arch/arm/mach-sa1100/include/mach/entry-macro.S
index 6aa13c46c5d..8cf7630bf02 100644
--- a/arch/arm/mach-sa1100/include/mach/entry-macro.S
+++ b/arch/arm/mach-sa1100/include/mach/entry-macro.S
@@ -8,17 +8,11 @@
  * warranty of any kind, whether express or implied.
  */
 
-                .macro  disable_fiq
-                .endm
-
                 .macro  get_irqnr_preamble, base, tmp
                 mov     \base, #0xfa000000              @ ICIP = 0xfa050000
                 add     \base, \base, #0x00050000
                 .endm
 
-                .macro  arch_ret_to_user, tmp1, tmp2
-                .endm
-
                 .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
                 ldr     \irqstat, [\base]               @ get irqs
                 ldr     \irqnr, [\base, #4]             @ ICMR = 0xfa050004
diff --git a/arch/arm/mach-sa1100/include/mach/nanoengine.h b/arch/arm/mach-sa1100/include/mach/nanoengine.h
index 14f8382d066..5ebd469a31f 100644
--- a/arch/arm/mach-sa1100/include/mach/nanoengine.h
+++ b/arch/arm/mach-sa1100/include/mach/nanoengine.h
@@ -16,12 +16,12 @@
 
 #include <mach/irqs.h>
 
-#define GPIO_PC_READY0  GPIO_GPIO(11) /* ready for socket 0 (active high)*/
-#define GPIO_PC_READY1  GPIO_GPIO(12) /* ready for socket 1 (active high) */
-#define GPIO_PC_CD0     GPIO_GPIO(13) /* detect for socket 0 (active low) */
-#define GPIO_PC_CD1     GPIO_GPIO(14) /* detect for socket 1 (active low) */
-#define GPIO_PC_RESET0  GPIO_GPIO(15) /* reset socket 0 */
-#define GPIO_PC_RESET1  GPIO_GPIO(16) /* reset socket 1 */
+#define GPIO_PC_READY0  11 /* ready for socket 0 (active high)*/
+#define GPIO_PC_READY1  12 /* ready for socket 1 (active high) */
+#define GPIO_PC_CD0     13 /* detect for socket 0 (active low) */
+#define GPIO_PC_CD1     14 /* detect for socket 1 (active low) */
+#define GPIO_PC_RESET0  15 /* reset socket 0 */
+#define GPIO_PC_RESET1  16 /* reset socket 1 */
 
 #define NANOENGINE_IRQ_GPIO_PCI         IRQ_GPIO0
 #define NANOENGINE_IRQ_GPIO_PC_READY0   IRQ_GPIO11
diff --git a/arch/arm/mach-sa1100/include/mach/shannon.h b/arch/arm/mach-sa1100/include/mach/shannon.h
index ec27d6e1214..019f857a793 100644
--- a/arch/arm/mach-sa1100/include/mach/shannon.h
+++ b/arch/arm/mach-sa1100/include/mach/shannon.h
@@ -23,14 +23,10 @@
 #define SHANNON_GPIO_SENSE_12V          GPIO_GPIO (21)  /* Input, 12v flash unprotect detected */
 #define SHANNON_GPIO_DISP_EN            GPIO_GPIO (22)  /* out */
 /* XXX GPIO 23 unaccounted for */
-#define SHANNON_GPIO_EJECT_0            GPIO_GPIO (24)  /* in */
-#define SHANNON_IRQ_GPIO_EJECT_0        IRQ_GPIO24
-#define SHANNON_GPIO_EJECT_1            GPIO_GPIO (25)  /* in */
-#define SHANNON_IRQ_GPIO_EJECT_1        IRQ_GPIO25
-#define SHANNON_GPIO_RDY_0              GPIO_GPIO (26)  /* in */
-#define SHANNON_IRQ_GPIO_RDY_0          IRQ_GPIO26
-#define SHANNON_GPIO_RDY_1              GPIO_GPIO (27)  /* in */
-#define SHANNON_IRQ_GPIO_RDY_1          IRQ_GPIO27
+#define SHANNON_GPIO_EJECT_0            24              /* in */
+#define SHANNON_GPIO_EJECT_1            25              /* in */
+#define SHANNON_GPIO_RDY_0              26              /* in */
+#define SHANNON_GPIO_RDY_1              27              /* in */
 
 /* MCP UCB codec GPIO pins... */
 
diff --git a/arch/arm/mach-sa1100/include/mach/simpad.h b/arch/arm/mach-sa1100/include/mach/simpad.h
index db28118103e..cdea671e893 100644
--- a/arch/arm/mach-sa1100/include/mach/simpad.h
+++ b/arch/arm/mach-sa1100/include/mach/simpad.h
@@ -39,10 +39,8 @@
 
 
 /*---  PCMCIA  ---*/
-#define GPIO_CF_CD              GPIO_GPIO24
-#define GPIO_CF_IRQ             GPIO_GPIO1
-#define IRQ_GPIO_CF_IRQ         IRQ_GPIO1
-#define IRQ_GPIO_CF_CD          IRQ_GPIO24
+#define GPIO_CF_CD              24
+#define GPIO_CF_IRQ             1
 
 /*--- SmartCard ---*/
 #define GPIO_SMART_CARD         GPIO_GPIO10
diff --git a/arch/arm/mach-sa1100/include/mach/system.h b/arch/arm/mach-sa1100/include/mach/system.h
deleted file mode 100644
index e17b208f76d..00000000000
--- a/arch/arm/mach-sa1100/include/mach/system.h
+++ /dev/null
@@ -1,9 +0,0 @@
-/*
- * arch/arm/mach-sa1100/include/mach/system.h
- *
- * Copyright (c) 1999 Nicolas Pitre <nico@fluxnic.net>
- */
-static inline void arch_idle(void)
-{
-        cpu_do_idle();
-}
diff --git a/arch/arm/mach-sa1100/pci-nanoengine.c b/arch/arm/mach-sa1100/pci-nanoengine.c
index 0d01ca78892..b466bca9c65 100644
--- a/arch/arm/mach-sa1100/pci-nanoengine.c
+++ b/arch/arm/mach-sa1100/pci-nanoengine.c
@@ -244,9 +244,11 @@ static int __init pci_nanoengine_setup_resources(struct pci_sys_data *sys)
                 printk(KERN_ERR "PCI: unable to allocate prefetchable\n");
                 return -EBUSY;
         }
-        pci_add_resource(&sys->resources, &pci_io_ports);
-        pci_add_resource(&sys->resources, &pci_non_prefetchable_memory);
-        pci_add_resource(&sys->resources, &pci_prefetchable_memory);
+        pci_add_resource_offset(&sys->resources, &pci_io_ports, sys->io_offset);
+        pci_add_resource_offset(&sys->resources,
+                                &pci_non_prefetchable_memory, sys->mem_offset);
+        pci_add_resource_offset(&sys->resources,
+                                &pci_prefetchable_memory, sys->mem_offset);
 
         return 1;
 }
diff --git a/arch/arm/mach-shark/core.c b/arch/arm/mach-shark/core.c
index a851c254ad6..6a2a7f2c255 100644
--- a/arch/arm/mach-shark/core.c
+++ b/arch/arm/mach-shark/core.c
@@ -149,10 +149,16 @@ static struct sys_timer shark_timer = {
         .init           = shark_timer_init,
 };
 
+static void shark_init_early(void)
+{
+        disable_hlt();
+}
+
 MACHINE_START(SHARK, "Shark")
         /* Maintainer: Alexander Schulz */
         .atag_offset    = 0x3000,
         .map_io         = shark_map_io,
+        .init_early     = shark_init_early,
         .init_irq       = shark_init_irq,
         .timer          = &shark_timer,
         .dma_zone_size  = SZ_4M,
diff --git a/arch/arm/mach-shark/include/mach/entry-macro.S b/arch/arm/mach-shark/include/mach/entry-macro.S
index 0bb6cc626eb..5901b09fc96 100644
--- a/arch/arm/mach-shark/include/mach/entry-macro.S
+++ b/arch/arm/mach-shark/include/mach/entry-macro.S
@@ -7,16 +7,10 @@
  * License version 2. This program is licensed "as is" without any
  * warranty of any kind, whether express or implied.
  */
-                .macro  disable_fiq
-                .endm
-
                 .macro  get_irqnr_preamble, base, tmp
                 mov     \base, #0xe0000000
                 .endm
 
-                .macro  arch_ret_to_user, tmp1, tmp2
-                .endm
-
                 .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
 
                 mov     \irqstat, #0x0C
diff --git a/arch/arm/mach-shark/include/mach/system.h b/arch/arm/mach-shark/include/mach/system.h
deleted file mode 100644
index 1b2f2c5050a..00000000000
--- a/arch/arm/mach-shark/include/mach/system.h
+++ /dev/null
@@ -1,13 +0,0 @@
-/*
- * arch/arm/mach-shark/include/mach/system.h
- *
- * by Alexander Schulz
- */
-#ifndef __ASM_ARCH_SYSTEM_H
-#define __ASM_ARCH_SYSTEM_H
-
-static inline void arch_idle(void)
-{
-}
-
-#endif
diff --git a/arch/arm/mach-shmobile/Makefile b/arch/arm/mach-shmobile/Makefile
index 7ad6954c46c..e7c2590b75d 100644
--- a/arch/arm/mach-shmobile/Makefile
+++ b/arch/arm/mach-shmobile/Makefile
@@ -16,7 +16,6 @@ obj-$(CONFIG_ARCH_R8A7779)	+= setup-r8a7779.o clock-r8a7779.o intc-r8a7779.o
 # SMP objects
 smp-y                           := platsmp.o headsmp.o
 smp-$(CONFIG_HOTPLUG_CPU)       += hotplug.o
-smp-$(CONFIG_LOCAL_TIMERS)      += localtimer.o
 smp-$(CONFIG_ARCH_SH73A0)       += smp-sh73a0.o
 smp-$(CONFIG_ARCH_R8A7779)      += smp-r8a7779.o
 
diff --git a/arch/arm/mach-shmobile/board-ag5evm.c b/arch/arm/mach-shmobile/board-ag5evm.c
index 8aea3a2dd88..f50d7c8b122 100644
--- a/arch/arm/mach-shmobile/board-ag5evm.c
+++ b/arch/arm/mach-shmobile/board-ag5evm.c
@@ -47,8 +47,6 @@
 #include <mach/common.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/mach/time.h>
 #include <asm/hardware/gic.h>
 #include <asm/hardware/cache-l2x0.h>
 #include <asm/traps.h>
@@ -230,16 +228,6 @@ static void lcd_backlight_reset(void)
         gpio_set_value(GPIO_PORT235, 1);
 }
 
-static void lcd_on(void *board_data, struct fb_info *info)
-{
-        lcd_backlight_on();
-}
-
-static void lcd_off(void *board_data)
-{
-        lcd_backlight_reset();
-}
-
 /* LCDC0 */
 static const struct fb_videomode lcdc0_modes[] = {
         {
@@ -263,14 +251,14 @@ static struct sh_mobile_lcdc_info lcdc0_info = {
                 .interface_type = RGB24,
                 .clock_divider = 1,
                 .flags = LCDC_FLAGS_DWPOL,
-                .lcd_size_cfg.width = 44,
-                .lcd_size_cfg.height = 79,
                 .fourcc = V4L2_PIX_FMT_RGB565,
-                .lcd_cfg = lcdc0_modes,
-                .num_cfg = ARRAY_SIZE(lcdc0_modes),
-                .board_cfg = {
-                        .display_on = lcd_on,
-                        .display_off = lcd_off,
+                .lcd_modes = lcdc0_modes,
+                .num_modes = ARRAY_SIZE(lcdc0_modes),
+                .panel_cfg = {
+                        .width = 44,
+                        .height = 79,
+                        .display_on = lcd_backlight_on,
+                        .display_off = lcd_backlight_reset,
                 },
         }
 };
@@ -487,27 +475,6 @@ static struct platform_device *ag5evm_devices[] __initdata = {
         &sdhi1_device,
 };
 
-static struct map_desc ag5evm_io_desc[] __initdata = {
-        /* create a 1:1 entity map for 0xe6xxxxxx
-         * used by CPGA, INTC and PFC.
-         */
-        {
-                .virtual        = 0xe6000000,
-                .pfn            = __phys_to_pfn(0xe6000000),
-                .length         = 256 << 20,
-                .type           = MT_DEVICE_NONSHARED
-        },
-};
-
-static void __init ag5evm_map_io(void)
-{
-        iotable_init(ag5evm_io_desc, ARRAY_SIZE(ag5evm_io_desc));
-
-        /* setup early devices and console here as well */
-        sh73a0_add_early_devices();
-        shmobile_setup_console();
-}
-
 static void __init ag5evm_init(void)
 {
         sh73a0_pinmux_init();
@@ -623,22 +590,12 @@ static void __init ag5evm_init(void)
         platform_add_devices(ag5evm_devices, ARRAY_SIZE(ag5evm_devices));
 }
 
-static void __init ag5evm_timer_init(void)
-{
-        sh73a0_clock_init();
-        shmobile_timer.init();
-        return;
-}
-
-struct sys_timer ag5evm_timer = {
-        .init   = ag5evm_timer_init,
-};
-
 MACHINE_START(AG5EVM, "ag5evm")
-        .map_io         = ag5evm_map_io,
+        .map_io         = sh73a0_map_io,
+        .init_early     = sh73a0_add_early_devices,
         .nr_irqs        = NR_IRQS_LEGACY,
         .init_irq       = sh73a0_init_irq,
         .handle_irq     = gic_handle_irq,
         .init_machine   = ag5evm_init,
-        .timer          = &ag5evm_timer,
+        .timer          = &shmobile_timer,
 MACHINE_END
diff --git a/arch/arm/mach-shmobile/board-ap4evb.c b/arch/arm/mach-shmobile/board-ap4evb.c
index b4718b00e82..262f8def557 100644
--- a/arch/arm/mach-shmobile/board-ap4evb.c
+++ b/arch/arm/mach-shmobile/board-ap4evb.c
@@ -61,8 +61,6 @@
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/mach/time.h>
 #include <asm/setup.h>
 
 /*
@@ -258,10 +256,16 @@ static struct sh_mobile_meram_info meram_info = {
 
 static struct resource meram_resources[] = {
         [0] = {
-                .name   = "MERAM",
-                .start  = 0xe8000000,
-                .end    = 0xe81fffff,
-                .flags  = IORESOURCE_MEM,
+                .name   = "regs",
+                .start  = 0xe8000000,
+                .end    = 0xe807ffff,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .name   = "meram",
+                .start  = 0xe8080000,
+                .end    = 0xe81fffff,
+                .flags  = IORESOURCE_MEM,
         },
 };
 
@@ -437,82 +441,6 @@ static struct platform_device usb1_host_device = {
         .resource       = usb1_host_resources,
 };
 
-static const struct fb_videomode ap4evb_lcdc_modes[] = {
-        {
-#ifdef CONFIG_AP4EVB_QHD
-                .name           = "R63302(QHD)",
-                .xres           = 544,
-                .yres           = 961,
-                .left_margin    = 72,
-                .right_margin   = 600,
-                .hsync_len      = 16,
-                .upper_margin   = 8,
-                .lower_margin   = 8,
-                .vsync_len      = 2,
-                .sync           = FB_SYNC_VERT_HIGH_ACT | FB_SYNC_HOR_HIGH_ACT,
-#else
-                .name           = "WVGA Panel",
-                .xres           = 800,
-                .yres           = 480,
-                .left_margin    = 220,
-                .right_margin   = 110,
-                .hsync_len      = 70,
-                .upper_margin   = 20,
-                .lower_margin   = 5,
-                .vsync_len      = 5,
-                .sync           = 0,
-#endif
-        },
-};
-static struct sh_mobile_meram_cfg lcd_meram_cfg = {
-        .icb[0] = {
-                .marker_icb     = 28,
-                .cache_icb      = 24,
-                .meram_offset   = 0x0,
-                .meram_size     = 0x40,
-        },
-        .icb[1] = {
-                .marker_icb     = 29,
-                .cache_icb      = 25,
-                .meram_offset   = 0x40,
-                .meram_size     = 0x40,
-        },
-};
-
-static struct sh_mobile_lcdc_info lcdc_info = {
-        .meram_dev = &meram_info,
-        .ch[0] = {
-                .chan = LCDC_CHAN_MAINLCD,
-                .fourcc = V4L2_PIX_FMT_RGB565,
-                .lcd_cfg = ap4evb_lcdc_modes,
-                .num_cfg = ARRAY_SIZE(ap4evb_lcdc_modes),
-                .meram_cfg = &lcd_meram_cfg,
-        }
-};
-
-static struct resource lcdc_resources[] = {
-        [0] = {
-                .name   = "LCDC",
-                .start  = 0xfe940000, /* P4-only space */
-                .end    = 0xfe943fff,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = intcs_evt2irq(0x580),
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device lcdc_device = {
-        .name           = "sh_mobile_lcdc_fb",
-        .num_resources  = ARRAY_SIZE(lcdc_resources),
-        .resource       = lcdc_resources,
-        .dev    = {
-                .platform_data  = &lcdc_info,
-                .coherent_dma_mask = ~0,
-        },
-};
-
 /*
  * QHD display
  */
@@ -556,20 +484,25 @@ static struct platform_device keysc_device = {
 };
 
 /* MIPI-DSI */
-#define PHYCTRL         0x0070
 static int sh_mipi_set_dot_clock(struct platform_device *pdev,
                                  void __iomem *base,
                                  int enable)
 {
         struct clk *pck = clk_get(&pdev->dev, "dsip_clk");
-        void __iomem *phy =  base + PHYCTRL;
 
         if (IS_ERR(pck))
                 return PTR_ERR(pck);
 
         if (enable) {
+                /*
+                 * DSIPCLK      = 24MHz
+                 * D-PHY        = DSIPCLK * ((0x6*2)+1) = 312MHz (see .phyctrl)
+                 * HsByteCLK    = D-PHY/8 = 39MHz
+                 *
+                 *  X * Y * FPS =
+                 * (544+72+600+16) * (961+8+8+2) * 30 = 36.1MHz
+                 */
                 clk_set_rate(pck, clk_round_rate(pck, 24000000));
-                iowrite32(ioread32(phy) | (0xb << 8), phy);
                 clk_enable(pck);
         } else {
                 clk_disable(pck);
@@ -593,11 +526,14 @@ static struct resource mipidsi0_resources[] = {
         },
 };
 
+static struct sh_mobile_lcdc_info lcdc_info;
+
 static struct sh_mipi_dsi_info mipidsi0_info = {
         .data_format    = MIPI_RGB888,
         .lcd_chan       = &lcdc_info.ch[0],
         .lane           = 2,
         .vsynw_offset   = 17,
+        .phyctrl        = 0x6 << 8,
         .flags          = SH_MIPI_DSI_SYNC_PULSES_MODE |
                           SH_MIPI_DSI_HSbyteCLK,
         .set_dot_clock  = sh_mipi_set_dot_clock,
@@ -619,6 +555,81 @@ static struct platform_device *qhd_devices[] __initdata = {
 };
 #endif /* CONFIG_AP4EVB_QHD */
 
+/* LCDC0 */
+static const struct fb_videomode ap4evb_lcdc_modes[] = {
+        {
+#ifdef CONFIG_AP4EVB_QHD
+                .name           = "R63302(QHD)",
+                .xres           = 544,
+                .yres           = 961,
+                .left_margin    = 72,
+                .right_margin   = 600,
+                .hsync_len      = 16,
+                .upper_margin   = 8,
+                .lower_margin   = 8,
+                .vsync_len      = 2,
+                .sync           = FB_SYNC_VERT_HIGH_ACT | FB_SYNC_HOR_HIGH_ACT,
+#else
+                .name           = "WVGA Panel",
+                .xres           = 800,
+                .yres           = 480,
+                .left_margin    = 220,
+                .right_margin   = 110,
+                .hsync_len      = 70,
+                .upper_margin   = 20,
+                .lower_margin   = 5,
+                .vsync_len      = 5,
+                .sync           = 0,
+#endif
+        },
+};
+
+static const struct sh_mobile_meram_cfg lcd_meram_cfg = {
+        .icb[0] = {
+                .meram_size     = 0x40,
+        },
+        .icb[1] = {
+                .meram_size     = 0x40,
+        },
+};
+
+static struct sh_mobile_lcdc_info lcdc_info = {
+        .meram_dev = &meram_info,
+        .ch[0] = {
+                .chan = LCDC_CHAN_MAINLCD,
+                .fourcc = V4L2_PIX_FMT_RGB565,
+                .lcd_modes = ap4evb_lcdc_modes,
+                .num_modes = ARRAY_SIZE(ap4evb_lcdc_modes),
+                .meram_cfg = &lcd_meram_cfg,
+#ifdef CONFIG_AP4EVB_QHD
+                .tx_dev = &mipidsi0_device,
+#endif
+        }
+};
+
+static struct resource lcdc_resources[] = {
+        [0] = {
+                .name   = "LCDC",
+                .start  = 0xfe940000, /* P4-only space */
+                .end    = 0xfe943fff,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = intcs_evt2irq(0x580),
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device lcdc_device = {
+        .name           = "sh_mobile_lcdc_fb",
+        .num_resources  = ARRAY_SIZE(lcdc_resources),
+        .resource       = lcdc_resources,
+        .dev    = {
+                .platform_data  = &lcdc_info,
+                .coherent_dma_mask = ~0,
+        },
+};
+
 /* FSI */
 #define IRQ_FSI         evt2irq(0x1840)
 static int __fsi_set_rate(struct clk *clk, long rate, int enable)
@@ -737,26 +748,18 @@ fsi_set_rate_end:
         return ret;
 }
 
-static int fsi_set_rate(struct device *dev, int is_porta, int rate, int enable)
-{
-        int ret;
-
-        if (is_porta)
-                ret = fsi_ak4642_set_rate(dev, rate, enable);
-        else
-                ret = fsi_hdmi_set_rate(dev, rate, enable);
-
-        return ret;
-}
-
 static struct sh_fsi_platform_info fsi_info = {
-        .porta_flags = SH_FSI_BRS_INV,
-
-        .portb_flags = SH_FSI_BRS_INV |
-                       SH_FSI_BRM_INV |
-                       SH_FSI_LRS_INV |
-                       SH_FSI_FMT_SPDIF,
-        .set_rate = fsi_set_rate,
+        .port_a = {
+                .flags          = SH_FSI_BRS_INV,
+                .set_rate       = fsi_ak4642_set_rate,
+        },
+        .port_b = {
+                .flags          = SH_FSI_BRS_INV |
+                                  SH_FSI_BRM_INV |
+                                  SH_FSI_LRS_INV |
+                                  SH_FSI_FMT_SPDIF,
+                .set_rate       = fsi_hdmi_set_rate,
+        },
 };
 
 static struct resource fsi_resources[] = {
@@ -798,65 +801,11 @@ static struct platform_device fsi_ak4643_device = {
         },
 };
 
-static struct sh_mobile_meram_cfg hdmi_meram_cfg = {
-        .icb[0] = {
-                .marker_icb     = 30,
-                .cache_icb      = 26,
-                .meram_offset   = 0x80,
-                .meram_size     = 0x100,
-        },
-        .icb[1] = {
-                .marker_icb     = 31,
-                .cache_icb      = 27,
-                .meram_offset   = 0x180,
-                .meram_size     = 0x100,
-        },
-};
-
-static struct sh_mobile_lcdc_info sh_mobile_lcdc1_info = {
-        .clock_source = LCDC_CLK_EXTERNAL,
-        .meram_dev = &meram_info,
-        .ch[0] = {
-                .chan = LCDC_CHAN_MAINLCD,
-                .fourcc = V4L2_PIX_FMT_RGB565,
-                .interface_type = RGB24,
-                .clock_divider = 1,
-                .flags = LCDC_FLAGS_DWPOL,
-                .meram_cfg = &hdmi_meram_cfg,
-        }
-};
-
-static struct resource lcdc1_resources[] = {
-        [0] = {
-                .name   = "LCDC1",
-                .start  = 0xfe944000,
-                .end    = 0xfe947fff,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = intcs_evt2irq(0x1780),
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device lcdc1_device = {
-        .name           = "sh_mobile_lcdc_fb",
-        .num_resources  = ARRAY_SIZE(lcdc1_resources),
-        .resource       = lcdc1_resources,
-        .id             = 1,
-        .dev    = {
-                .platform_data  = &sh_mobile_lcdc1_info,
-                .coherent_dma_mask = ~0,
-        },
-};
-
+/* LCDC1 */
 static long ap4evb_clk_optimize(unsigned long target, unsigned long *best_freq,
                                 unsigned long *parent_freq);
 
-
 static struct sh_mobile_hdmi_info hdmi_info = {
-        .lcd_chan = &sh_mobile_lcdc1_info.ch[0],
-        .lcd_dev = &lcdc1_device.dev,
         .flags = HDMI_SND_SRC_SPDIF,
         .clk_optimize_parent = ap4evb_clk_optimize,
 };
@@ -885,10 +834,6 @@ static struct platform_device hdmi_device = {
         },
 };
 
-static struct platform_device fsi_hdmi_device = {
-        .name           = "sh_fsi2_b_hdmi",
-};
-
 static long ap4evb_clk_optimize(unsigned long target, unsigned long *best_freq,
                                 unsigned long *parent_freq)
 {
@@ -908,6 +853,57 @@ static long ap4evb_clk_optimize(unsigned long target, unsigned long *best_freq,
         return error;
 }
 
+static const struct sh_mobile_meram_cfg hdmi_meram_cfg = {
+        .icb[0] = {
+                .meram_size     = 0x100,
+        },
+        .icb[1] = {
+                .meram_size     = 0x100,
+        },
+};
+
+static struct sh_mobile_lcdc_info sh_mobile_lcdc1_info = {
+        .clock_source = LCDC_CLK_EXTERNAL,
+        .meram_dev = &meram_info,
+        .ch[0] = {
+                .chan = LCDC_CHAN_MAINLCD,
+                .fourcc = V4L2_PIX_FMT_RGB565,
+                .interface_type = RGB24,
+                .clock_divider = 1,
+                .flags = LCDC_FLAGS_DWPOL,
+                .meram_cfg = &hdmi_meram_cfg,
+                .tx_dev = &hdmi_device,
+        }
+};
+
+static struct resource lcdc1_resources[] = {
+        [0] = {
+                .name   = "LCDC1",
+                .start  = 0xfe944000,
+                .end    = 0xfe947fff,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = intcs_evt2irq(0x1780),
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device lcdc1_device = {
+        .name           = "sh_mobile_lcdc_fb",
+        .num_resources  = ARRAY_SIZE(lcdc1_resources),
+        .resource       = lcdc1_resources,
+        .id             = 1,
+        .dev    = {
+                .platform_data  = &sh_mobile_lcdc1_info,
+                .coherent_dma_mask = ~0,
+        },
+};
+
+static struct platform_device fsi_hdmi_device = {
+        .name           = "sh_fsi2_b_hdmi",
+};
+
 static struct gpio_led ap4evb_leds[] = {
         {
                 .name                   = "led4",
@@ -1042,9 +1038,9 @@ static struct platform_device *ap4evb_devices[] __initdata = {
         &fsi_ak4643_device,
         &fsi_hdmi_device,
         &sh_mmcif_device,
-        &lcdc1_device,
-        &lcdc_device,
         &hdmi_device,
+        &lcdc_device,
+        &lcdc1_device,
         &ceu_device,
         &ap4evb_camera,
         &meram_device,
@@ -1190,27 +1186,6 @@ static struct i2c_board_info i2c1_devices[] = {
         },
 };
 
-static struct map_desc ap4evb_io_desc[] __initdata = {
-        /* create a 1:1 entity map for 0xe6xxxxxx
-         * used by CPGA, INTC and PFC.
-         */
-        {
-                .virtual        = 0xe6000000,
-                .pfn            = __phys_to_pfn(0xe6000000),
-                .length         = 256 << 20,
-                .type           = MT_DEVICE_NONSHARED
-        },
-};
-
-static void __init ap4evb_map_io(void)
-{
-        iotable_init(ap4evb_io_desc, ARRAY_SIZE(ap4evb_io_desc));
-
-        /* setup early devices and console here as well */
-        sh7372_add_early_devices();
-        shmobile_setup_console();
-}
-
 #define GPIO_PORT9CR    0xE6051009
 #define GPIO_PORT10CR   0xE605100A
 #define USCCR1          0xE6058144
@@ -1219,6 +1194,9 @@ static void __init ap4evb_init(void)
         u32 srcr4;
         struct clk *clk;
 
+        /* External clock source */
+        clk_set_rate(&sh7372_dv_clki_clk, 27000000);
+
         sh7372_pinmux_init();
 
         /* enable SCIFA0 */
@@ -1355,8 +1333,8 @@ static void __init ap4evb_init(void)
         lcdc_info.ch[0].interface_type          = RGB24;
         lcdc_info.ch[0].clock_divider           = 1;
         lcdc_info.ch[0].flags                   = LCDC_FLAGS_DWPOL;
-        lcdc_info.ch[0].lcd_size_cfg.width      = 44;
-        lcdc_info.ch[0].lcd_size_cfg.height     = 79;
+        lcdc_info.ch[0].panel_cfg.width         = 44;
+        lcdc_info.ch[0].panel_cfg.height        = 79;
 
         platform_add_devices(qhd_devices, ARRAY_SIZE(qhd_devices));
 
@@ -1397,8 +1375,8 @@ static void __init ap4evb_init(void)
         lcdc_info.ch[0].interface_type          = RGB18;
         lcdc_info.ch[0].clock_divider           = 3;
         lcdc_info.ch[0].flags                   = 0;
-        lcdc_info.ch[0].lcd_size_cfg.width      = 152;
-        lcdc_info.ch[0].lcd_size_cfg.height     = 91;
+        lcdc_info.ch[0].panel_cfg.width         = 152;
+        lcdc_info.ch[0].panel_cfg.height        = 91;
 
         /* enable TouchScreen */
         irq_set_irq_type(IRQ7, IRQ_TYPE_LEVEL_LOW);
@@ -1455,23 +1433,11 @@ static void __init ap4evb_init(void)
         pm_clk_add(&lcdc1_device.dev, "hdmi");
 }
 
-static void __init ap4evb_timer_init(void)
-{
-        sh7372_clock_init();
-        shmobile_timer.init();
-
-        /* External clock source */
-        clk_set_rate(&sh7372_dv_clki_clk, 27000000);
-}
-
-static struct sys_timer ap4evb_timer = {
-        .init           = ap4evb_timer_init,
-};
-
 MACHINE_START(AP4EVB, "ap4evb")
-        .map_io         = ap4evb_map_io,
+        .map_io         = sh7372_map_io,
+        .init_early     = sh7372_add_early_devices,
         .init_irq       = sh7372_init_irq,
         .handle_irq     = shmobile_handle_irq_intc,
         .init_machine   = ap4evb_init,
-        .timer          = &ap4evb_timer,
+        .timer          = &shmobile_timer,
 MACHINE_END
diff --git a/arch/arm/mach-shmobile/board-bonito.c b/arch/arm/mach-shmobile/board-bonito.c
index 4bd1162ce0d..8b2124da245 100644
--- a/arch/arm/mach-shmobile/board-bonito.c
+++ b/arch/arm/mach-shmobile/board-bonito.c
@@ -246,9 +246,9 @@ static struct sh_mobile_lcdc_info lcdc0_info = {
                 .interface_type         = RGB24,
                 .clock_divider          = 5,
                 .flags                  = 0,
-                .lcd_cfg                = &lcdc0_mode,
-                .num_cfg                = 1,
-                .lcd_size_cfg = {
+                .lcd_modes              = &lcdc0_mode,
+                .num_modes              = 1,
+                .panel_cfg = {
                         .width  = 152,
                         .height = 91,
                 },
@@ -328,28 +328,6 @@ static struct platform_device *bonito_base_devices[] __initdata = {
  * map I/O
  */
 static struct map_desc bonito_io_desc[] __initdata = {
-         /*
-          * for CPGA/INTC/PFC
-          * 0xe6000000-0xefffffff -> 0xe6000000-0xefffffff
-          */
-        {
-                .virtual        = 0xe6000000,
-                .pfn            = __phys_to_pfn(0xe6000000),
-                .length         = 160 << 20,
-                .type           = MT_DEVICE_NONSHARED
-        },
-#ifdef CONFIG_CACHE_L2X0
-        /*
-         * for l2x0_init()
-         * 0xf0100000-0xf0101000 -> 0xf0002000-0xf0003000
-         */
-        {
-                .virtual        = 0xf0002000,
-                .pfn            = __phys_to_pfn(0xf0100000),
-                .length         = PAGE_SIZE,
-                .type           = MT_DEVICE_NONSHARED
-        },
-#endif
         /*
          * for FPGA (0x1800000-0x19ffffff)
          * 0x18000000-0x18002000 -> 0xf0003000-0xf0005000
@@ -364,11 +342,8 @@ static struct map_desc bonito_io_desc[] __initdata = {
 
 static void __init bonito_map_io(void)
 {
+        r8a7740_map_io();
         iotable_init(bonito_io_desc, ARRAY_SIZE(bonito_io_desc));
-
-        /* setup early devices and console here as well */
-        r8a7740_add_early_devices();
-        shmobile_setup_console();
 }
 
 /*
@@ -492,7 +467,7 @@ static void __init bonito_init(void)
         }
 }
 
-static void __init bonito_timer_init(void)
+static void __init bonito_earlytimer_init(void)
 {
         u16 val;
         u8 md_ck = 0;
@@ -507,17 +482,22 @@ static void __init bonito_timer_init(void)
                 md_ck |= MD_CK0;
 
         r8a7740_clock_init(md_ck);
-        shmobile_timer.init();
+        shmobile_earlytimer_init();
 }
 
-struct sys_timer bonito_timer = {
-        .init   = bonito_timer_init,
-};
+void __init bonito_add_early_devices(void)
+{
+        r8a7740_add_early_devices();
+
+        /* override timer setup with board-specific code */
+        shmobile_timer.init = bonito_earlytimer_init;
+}
 
 MACHINE_START(BONITO, "bonito")
         .map_io         = bonito_map_io,
+        .init_early     = bonito_add_early_devices,
         .init_irq       = r8a7740_init_irq,
         .handle_irq     = shmobile_handle_irq_intc,
         .init_machine   = bonito_init,
-        .timer          = &bonito_timer,
+        .timer          = &shmobile_timer,
 MACHINE_END
diff --git a/arch/arm/mach-shmobile/board-g3evm.c b/arch/arm/mach-shmobile/board-g3evm.c
index 72d557281b1..b627e89037f 100644
--- a/arch/arm/mach-shmobile/board-g3evm.c
+++ b/arch/arm/mach-shmobile/board-g3evm.c
@@ -37,8 +37,6 @@
 #include <mach/common.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/mach/time.h>
 
 /*
  * IrDA
@@ -246,27 +244,6 @@ static struct platform_device *g3evm_devices[] __initdata = {
         &irda_device,
 };
 
-static struct map_desc g3evm_io_desc[] __initdata = {
-        /* create a 1:1 entity map for 0xe6xxxxxx
-         * used by CPGA, INTC and PFC.
-         */
-        {
-                .virtual        = 0xe6000000,
-                .pfn            = __phys_to_pfn(0xe6000000),
-                .length         = 256 << 20,
-                .type           = MT_DEVICE_NONSHARED
-        },
-};
-
-static void __init g3evm_map_io(void)
-{
-        iotable_init(g3evm_io_desc, ARRAY_SIZE(g3evm_io_desc));
-
-        /* setup early devices and console here as well */
-        sh7367_add_early_devices();
-        shmobile_setup_console();
-}
-
 static void __init g3evm_init(void)
 {
         sh7367_pinmux_init();
@@ -354,20 +331,11 @@ static void __init g3evm_init(void)
         platform_add_devices(g3evm_devices, ARRAY_SIZE(g3evm_devices));
 }
 
-static void __init g3evm_timer_init(void)
-{
-        sh7367_clock_init();
-        shmobile_timer.init();
-}
-
-static struct sys_timer g3evm_timer = {
-        .init           = g3evm_timer_init,
-};
-
 MACHINE_START(G3EVM, "g3evm")
-        .map_io         = g3evm_map_io,
+        .map_io         = sh7367_map_io,
+        .init_early     = sh7367_add_early_devices,
         .init_irq       = sh7367_init_irq,
         .handle_irq     = shmobile_handle_irq_intc,
         .init_machine   = g3evm_init,
-        .timer          = &g3evm_timer,
+        .timer          = &shmobile_timer,
 MACHINE_END
diff --git a/arch/arm/mach-shmobile/board-g4evm.c b/arch/arm/mach-shmobile/board-g4evm.c
index 2220b885cff..46d757d2759 100644
--- a/arch/arm/mach-shmobile/board-g4evm.c
+++ b/arch/arm/mach-shmobile/board-g4evm.c
@@ -38,8 +38,6 @@
 #include <mach/common.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/mach/time.h>
 
 /*
  * SDHI
@@ -260,27 +258,6 @@ static struct platform_device *g4evm_devices[] __initdata = {
         &sdhi1_device,
 };
 
-static struct map_desc g4evm_io_desc[] __initdata = {
-        /* create a 1:1 entity map for 0xe6xxxxxx
-         * used by CPGA, INTC and PFC.
-         */
-        {
-                .virtual        = 0xe6000000,
-                .pfn            = __phys_to_pfn(0xe6000000),
-                .length         = 256 << 20,
-                .type           = MT_DEVICE_NONSHARED
-        },
-};
-
-static void __init g4evm_map_io(void)
-{
-        iotable_init(g4evm_io_desc, ARRAY_SIZE(g4evm_io_desc));
-
-        /* setup early devices and console here as well */
-        sh7377_add_early_devices();
-        shmobile_setup_console();
-}
-
 #define GPIO_SDHID0_D0  0xe60520fc
 #define GPIO_SDHID0_D1  0xe60520fd
 #define GPIO_SDHID0_D2  0xe60520fe
@@ -397,20 +374,11 @@ static void __init g4evm_init(void)
         platform_add_devices(g4evm_devices, ARRAY_SIZE(g4evm_devices));
 }
 
-static void __init g4evm_timer_init(void)
-{
-        sh7377_clock_init();
-        shmobile_timer.init();
-}
-
-static struct sys_timer g4evm_timer = {
-        .init           = g4evm_timer_init,
-};
-
 MACHINE_START(G4EVM, "g4evm")
-        .map_io         = g4evm_map_io,
+        .map_io         = sh7377_map_io,
+        .init_early     = sh7377_add_early_devices,
         .init_irq       = sh7377_init_irq,
         .handle_irq     = shmobile_handle_irq_intc,
         .init_machine   = g4evm_init,
-        .timer          = &g4evm_timer,
+        .timer          = &shmobile_timer,
 MACHINE_END
diff --git a/arch/arm/mach-shmobile/board-kota2.c b/arch/arm/mach-shmobile/board-kota2.c
index c8e7ca23fc0..61c06729466 100644
--- a/arch/arm/mach-shmobile/board-kota2.c
+++ b/arch/arm/mach-shmobile/board-kota2.c
@@ -43,7 +43,6 @@
 #include <mach/common.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
-#include <asm/mach/map.h>
 #include <asm/mach/time.h>
 #include <asm/hardware/gic.h>
 #include <asm/hardware/cache-l2x0.h>
@@ -409,27 +408,6 @@ static struct platform_device *kota2_devices[] __initdata = {
         &sdhi1_device,
 };
 
-static struct map_desc kota2_io_desc[] __initdata = {
-        /* create a 1:1 entity map for 0xe6xxxxxx
-         * used by CPGA, INTC and PFC.
-         */
-        {
-                .virtual        = 0xe6000000,
-                .pfn            = __phys_to_pfn(0xe6000000),
-                .length         = 256 << 20,
-                .type           = MT_DEVICE_NONSHARED
-        },
-};
-
-static void __init kota2_map_io(void)
-{
-        iotable_init(kota2_io_desc, ARRAY_SIZE(kota2_io_desc));
-
-        /* setup early devices and console here as well */
-        sh73a0_add_early_devices();
-        shmobile_setup_console();
-}
-
 static void __init kota2_init(void)
 {
         sh73a0_pinmux_init();
@@ -535,22 +513,12 @@ static void __init kota2_init(void)
         platform_add_devices(kota2_devices, ARRAY_SIZE(kota2_devices));
 }
 
-static void __init kota2_timer_init(void)
-{
-        sh73a0_clock_init();
-        shmobile_timer.init();
-        return;
-}
-
-struct sys_timer kota2_timer = {
-        .init   = kota2_timer_init,
-};
-
 MACHINE_START(KOTA2, "kota2")
-        .map_io         = kota2_map_io,
+        .map_io         = sh73a0_map_io,
+        .init_early     = sh73a0_add_early_devices,
         .nr_irqs        = NR_IRQS_LEGACY,
         .init_irq       = sh73a0_init_irq,
         .handle_irq     = gic_handle_irq,
         .init_machine   = kota2_init,
-        .timer          = &kota2_timer,
+        .timer          = &shmobile_timer,
 MACHINE_END
diff --git a/arch/arm/mach-shmobile/board-mackerel.c b/arch/arm/mach-shmobile/board-mackerel.c
index 7b53cda4185..bd4253ba05b 100644
--- a/arch/arm/mach-shmobile/board-mackerel.c
+++ b/arch/arm/mach-shmobile/board-mackerel.c
@@ -57,8 +57,6 @@
 #include <mach/sh7372.h>
 
 #include <asm/mach/arch.h>
-#include <asm/mach/time.h>
-#include <asm/mach/map.h>
 #include <asm/mach-types.h>
 
 /*
@@ -318,8 +316,14 @@ static struct sh_mobile_meram_info mackerel_meram_info = {
 
 static struct resource meram_resources[] = {
         [0] = {
-                .name   = "MERAM",
+                .name   = "regs",
                 .start  = 0xe8000000,
+                .end    = 0xe807ffff,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .name   = "meram",
+                .start  = 0xe8080000,
                 .end    = 0xe81fffff,
                 .flags  = IORESOURCE_MEM,
         },
@@ -351,29 +355,23 @@ static struct fb_videomode mackerel_lcdc_modes[] = {
         },
 };
 
-static int mackerel_set_brightness(void *board_data, int brightness)
+static int mackerel_set_brightness(int brightness)
 {
         gpio_set_value(GPIO_PORT31, brightness);
 
         return 0;
 }
 
-static int mackerel_get_brightness(void *board_data)
+static int mackerel_get_brightness(void)
 {
         return gpio_get_value(GPIO_PORT31);
 }
 
-static struct sh_mobile_meram_cfg lcd_meram_cfg = {
+static const struct sh_mobile_meram_cfg lcd_meram_cfg = {
         .icb[0] = {
-                .marker_icb     = 28,
-                .cache_icb      = 24,
-                .meram_offset   = 0x0,
                 .meram_size     = 0x40,
         },
         .icb[1] = {
-                .marker_icb     = 29,
-                .cache_icb      = 25,
-                .meram_offset   = 0x40,
                 .meram_size     = 0x40,
         },
 };
@@ -384,20 +382,20 @@ static struct sh_mobile_lcdc_info lcdc_info = {
         .ch[0] = {
                 .chan = LCDC_CHAN_MAINLCD,
                 .fourcc = V4L2_PIX_FMT_RGB565,
-                .lcd_cfg = mackerel_lcdc_modes,
-                .num_cfg = ARRAY_SIZE(mackerel_lcdc_modes),
+                .lcd_modes = mackerel_lcdc_modes,
+                .num_modes = ARRAY_SIZE(mackerel_lcdc_modes),
                 .interface_type         = RGB24,
                 .clock_divider          = 3,
                 .flags                  = 0,
-                .lcd_size_cfg.width     = 152,
-                .lcd_size_cfg.height    = 91,
-                .board_cfg = {
-                        .set_brightness = mackerel_set_brightness,
-                        .get_brightness = mackerel_get_brightness,
+                .panel_cfg = {
+                        .width          = 152,
+                        .height         = 91,
                 },
                 .bl_info = {
                         .name = "sh_mobile_lcdc_bl",
                         .max_brightness = 1,
+                        .set_brightness = mackerel_set_brightness,
+                        .get_brightness = mackerel_get_brightness,
                 },
                 .meram_cfg = &lcd_meram_cfg,
         }
@@ -426,21 +424,44 @@ static struct platform_device lcdc_device = {
         },
 };
 
-static struct sh_mobile_meram_cfg hdmi_meram_cfg = {
+/* HDMI */
+static struct sh_mobile_hdmi_info hdmi_info = {
+        .flags          = HDMI_SND_SRC_SPDIF,
+};
+
+static struct resource hdmi_resources[] = {
+        [0] = {
+                .name   = "HDMI",
+                .start  = 0xe6be0000,
+                .end    = 0xe6be00ff,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                /* There's also an HDMI interrupt on INTCS @ 0x18e0 */
+                .start  = evt2irq(0x17e0),
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device hdmi_device = {
+        .name           = "sh-mobile-hdmi",
+        .num_resources  = ARRAY_SIZE(hdmi_resources),
+        .resource       = hdmi_resources,
+        .id             = -1,
+        .dev    = {
+                .platform_data  = &hdmi_info,
+        },
+};
+
+static const struct sh_mobile_meram_cfg hdmi_meram_cfg = {
         .icb[0] = {
-                .marker_icb     = 30,
-                .cache_icb      = 26,
-                .meram_offset   = 0x80,
                 .meram_size     = 0x100,
         },
         .icb[1] = {
-                .marker_icb     = 31,
-                .cache_icb      = 27,
-                .meram_offset   = 0x180,
                 .meram_size     = 0x100,
         },
 };
-/* HDMI */
+
 static struct sh_mobile_lcdc_info hdmi_lcdc_info = {
         .meram_dev = &mackerel_meram_info,
         .clock_source = LCDC_CLK_EXTERNAL,
@@ -451,6 +472,7 @@ static struct sh_mobile_lcdc_info hdmi_lcdc_info = {
                 .clock_divider = 1,
                 .flags = LCDC_FLAGS_DWPOL,
                 .meram_cfg = &hdmi_meram_cfg,
+                .tx_dev = &hdmi_device,
         }
 };
 
@@ -478,36 +500,6 @@ static struct platform_device hdmi_lcdc_device = {
         },
 };
 
-static struct sh_mobile_hdmi_info hdmi_info = {
-        .lcd_chan       = &hdmi_lcdc_info.ch[0],
-        .lcd_dev        = &hdmi_lcdc_device.dev,
-        .flags          = HDMI_SND_SRC_SPDIF,
-};
-
-static struct resource hdmi_resources[] = {
-        [0] = {
-                .name   = "HDMI",
-                .start  = 0xe6be0000,
-                .end    = 0xe6be00ff,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                /* There's also an HDMI interrupt on INTCS @ 0x18e0 */
-                .start  = evt2irq(0x17e0),
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device hdmi_device = {
-        .name           = "sh-mobile-hdmi",
-        .num_resources  = ARRAY_SIZE(hdmi_resources),
-        .resource       = hdmi_resources,
-        .id             = -1,
-        .dev    = {
-                .platform_data  = &hdmi_info,
-        },
-};
-
 static struct platform_device fsi_hdmi_device = {
         .name           = "sh_fsi2_b_hdmi",
 };
@@ -860,7 +852,7 @@ static int __fsi_set_round_rate(struct clk *clk, long rate, int enable)
         return clk_enable(clk);
 }
 
-static int fsi_set_rate(struct device *dev, int is_porta, int rate, int enable)
+static int fsi_b_set_rate(struct device *dev, int rate, int enable)
 {
         struct clk *fsib_clk;
         struct clk *fdiv_clk = &sh7372_fsidivb_clk;
@@ -869,10 +861,6 @@ static int fsi_set_rate(struct device *dev, int is_porta, int rate, int enable)
         int ackmd_bpfmd;
         int ret;
 
-        /* FSIA is slave mode. nothing to do here */
-        if (is_porta)
-                return 0;
-
         /* clock start */
         switch (rate) {
         case 44100:
@@ -916,14 +904,16 @@ fsi_set_rate_end:
 }
 
 static struct sh_fsi_platform_info fsi_info = {
-        .porta_flags =  SH_FSI_BRS_INV,
-
-        .portb_flags =  SH_FSI_BRS_INV  |
+        .port_a = {
+                .flags = SH_FSI_BRS_INV,
+        },
+        .port_b = {
+                .flags = SH_FSI_BRS_INV |
                         SH_FSI_BRM_INV  |
                         SH_FSI_LRS_INV  |
                         SH_FSI_FMT_SPDIF,
-
-        .set_rate = fsi_set_rate,
+                .set_rate = fsi_b_set_rate,
+        }
 };
 
 static struct resource fsi_resources[] = {
@@ -1276,8 +1266,8 @@ static struct platform_device *mackerel_devices[] __initdata = {
         &sh_mmcif_device,
         &ceu_device,
         &mackerel_camera,
-        &hdmi_lcdc_device,
         &hdmi_device,
+        &hdmi_lcdc_device,
         &meram_device,
 };
 
@@ -1337,29 +1327,13 @@ static struct i2c_board_info i2c1_devices[] = {
         },
 };
 
-static struct map_desc mackerel_io_desc[] __initdata = {
-        /* create a 1:1 entity map for 0xe6xxxxxx
-         * used by CPGA, INTC and PFC.
-         */
-        {
-                .virtual        = 0xe6000000,
-                .pfn            = __phys_to_pfn(0xe6000000),
-                .length         = 256 << 20,
-                .type           = MT_DEVICE_NONSHARED
-        },
-};
-
 static void __init mackerel_map_io(void)
 {
-        iotable_init(mackerel_io_desc, ARRAY_SIZE(mackerel_io_desc));
+        sh7372_map_io();
         /* DMA memory at 0xff200000 - 0xffdfffff. The default 2MB size isn't
          * enough to allocate the frame buffer memory.
          */
         init_consistent_dma_size(12 << 20);
-
-        /* setup early devices and console here as well */
-        sh7372_add_early_devices();
-        shmobile_setup_console();
 }
 
 #define GPIO_PORT9CR    0xE6051009
@@ -1374,6 +1348,9 @@ static void __init mackerel_init(void)
         struct clk *clk;
         int ret;
 
+        /* External clock source */
+        clk_set_rate(&sh7372_dv_clki_clk, 27000000);
+
         sh7372_pinmux_init();
 
         /* enable SCIFA0 */
@@ -1577,23 +1554,11 @@ static void __init mackerel_init(void)
         pm_clk_add(&hdmi_lcdc_device.dev, "hdmi");
 }
 
-static void __init mackerel_timer_init(void)
-{
-        sh7372_clock_init();
-        shmobile_timer.init();
-
-        /* External clock source */
-        clk_set_rate(&sh7372_dv_clki_clk, 27000000);
-}
-
-static struct sys_timer mackerel_timer = {
-        .init           = mackerel_timer_init,
-};
-
 MACHINE_START(MACKEREL, "mackerel")
         .map_io         = mackerel_map_io,
+        .init_early     = sh7372_add_early_devices,
         .init_irq       = sh7372_init_irq,
         .handle_irq     = shmobile_handle_irq_intc,
         .init_machine   = mackerel_init,
-        .timer          = &mackerel_timer,
+        .timer          = &shmobile_timer,
 MACHINE_END
diff --git a/arch/arm/mach-shmobile/board-marzen.c b/arch/arm/mach-shmobile/board-marzen.c
index f0e02c0ce99..cbd5e4cd06d 100644
--- a/arch/arm/mach-shmobile/board-marzen.c
+++ b/arch/arm/mach-shmobile/board-marzen.c
@@ -33,8 +33,6 @@
 #include <mach/common.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/mach/time.h>
 #include <asm/hardware/gic.h>
 #include <asm/traps.h>
 
@@ -72,49 +70,6 @@ static struct platform_device *marzen_devices[] __initdata = {
         &eth_device,
 };
 
-static struct map_desc marzen_io_desc[] __initdata = {
-        /* 2M entity map for 0xf0000000 (MPCORE) */
-        {
-                .virtual        = 0xf0000000,
-                .pfn            = __phys_to_pfn(0xf0000000),
-                .length         = SZ_2M,
-                .type           = MT_DEVICE_NONSHARED
-        },
-        /* 16M entity map for 0xfexxxxxx (DMAC-S/HPBREG/INTC2/LRAM/DBSC) */
-        {
-                .virtual        = 0xfe000000,
-                .pfn            = __phys_to_pfn(0xfe000000),
-                .length         = SZ_16M,
-                .type           = MT_DEVICE_NONSHARED
-        },
-};
-
-static void __init marzen_map_io(void)
-{
-        iotable_init(marzen_io_desc, ARRAY_SIZE(marzen_io_desc));
-}
-
-static void __init marzen_init_early(void)
-{
-        r8a7779_add_early_devices();
-
-        /* Early serial console setup is not included here due to
-         * memory map collisions. The SCIF serial ports in r8a7779
-         * are difficult to entity map 1:1 due to collision with the
-         * virtual memory range used by the coherent DMA code on ARM.
-         *
-         * Anyone wanting to debug early can remove UPF_IOREMAP from
-         * the sh-sci serial console platform data, adjust mapbase
-         * to a static M:N virt:phys mapping that needs to be added to
-         * the mappings passed with iotable_init() above.
-         *
-         * Then add a call to shmobile_setup_console() from this function.
-         *
-         * As a final step pass earlyprint=sh-sci.2,115200 on the kernel
-         * command line.
-         */
-}
-
 static void __init marzen_init(void)
 {
         r8a7779_pinmux_init();
@@ -135,23 +90,12 @@ static void __init marzen_init(void)
         platform_add_devices(marzen_devices, ARRAY_SIZE(marzen_devices));
 }
 
-static void __init marzen_timer_init(void)
-{
-        r8a7779_clock_init();
-        shmobile_timer.init();
-        return;
-}
-
-struct sys_timer marzen_timer = {
-        .init   = marzen_timer_init,
-};
-
 MACHINE_START(MARZEN, "marzen")
-        .map_io         = marzen_map_io,
-        .init_early     = marzen_init_early,
+        .map_io         = r8a7779_map_io,
+        .init_early     = r8a7779_add_early_devices,
         .nr_irqs        = NR_IRQS_LEGACY,
         .init_irq       = r8a7779_init_irq,
         .handle_irq     = gic_handle_irq,
         .init_machine   = marzen_init,
-        .timer          = &marzen_timer,
+        .timer          = &shmobile_timer,
 MACHINE_END
diff --git a/arch/arm/mach-shmobile/clock-r8a7740.c b/arch/arm/mach-shmobile/clock-r8a7740.c
index 3b35b9afc00..99c4d743a99 100644
--- a/arch/arm/mach-shmobile/clock-r8a7740.c
+++ b/arch/arm/mach-shmobile/clock-r8a7740.c
@@ -93,7 +93,7 @@ static unsigned long div_recalc(struct clk *clk)
         return clk->parent->rate / (int)(clk->priv);
 }
 
-static struct clk_ops div_clk_ops = {
+static struct sh_clk_ops div_clk_ops = {
         .recalc = div_recalc,
 };
 
@@ -125,7 +125,7 @@ static struct clk extal2_div2_clk = {
         .parent = &extal2_clk,
 };
 
-static struct clk_ops followparent_clk_ops = {
+static struct sh_clk_ops followparent_clk_ops = {
         .recalc = followparent_recalc,
 };
 
@@ -156,7 +156,7 @@ static unsigned long pllc01_recalc(struct clk *clk)
         return clk->parent->rate * mult;
 }
 
-static struct clk_ops pllc01_clk_ops = {
+static struct sh_clk_ops pllc01_clk_ops = {
         .recalc         = pllc01_recalc,
 };
 
@@ -376,7 +376,7 @@ void __init r8a7740_clock_init(u8 md_ck)
         clkdev_add_table(lookups, ARRAY_SIZE(lookups));
 
         if (!ret)
-                clk_init();
+                shmobile_clk_init();
         else
                 panic("failed to setup r8a7740 clocks\n");
 }
diff --git a/arch/arm/mach-shmobile/clock-r8a7779.c b/arch/arm/mach-shmobile/clock-r8a7779.c
index b4b0e8cd096..7d6e9fe47b5 100644
--- a/arch/arm/mach-shmobile/clock-r8a7779.c
+++ b/arch/arm/mach-shmobile/clock-r8a7779.c
@@ -107,7 +107,7 @@ static unsigned long mul4_recalc(struct clk *clk)
         return clk->parent->rate * 4;
 }
 
-static struct clk_ops mul4_clk_ops = {
+static struct sh_clk_ops mul4_clk_ops = {
         .recalc         = mul4_recalc,
 };
 
@@ -170,7 +170,7 @@ void __init r8a7779_clock_init(void)
         clkdev_add_table(lookups, ARRAY_SIZE(lookups));
 
         if (!ret)
-                clk_init();
+                shmobile_clk_init();
         else
                 panic("failed to setup r8a7779 clocks\n");
 }
diff --git a/arch/arm/mach-shmobile/clock-sh7367.c b/arch/arm/mach-shmobile/clock-sh7367.c
index 5218c34a9cc..006e7b5d304 100644
--- a/arch/arm/mach-shmobile/clock-sh7367.c
+++ b/arch/arm/mach-shmobile/clock-sh7367.c
@@ -74,7 +74,7 @@ static unsigned long div2_recalc(struct clk *clk)
         return clk->parent->rate / 2;
 }
 
-static struct clk_ops div2_clk_ops = {
+static struct sh_clk_ops div2_clk_ops = {
         .recalc         = div2_recalc,
 };
 
@@ -101,7 +101,7 @@ static unsigned long pllc1_recalc(struct clk *clk)
         return clk->parent->rate * mult;
 }
 
-static struct clk_ops pllc1_clk_ops = {
+static struct sh_clk_ops pllc1_clk_ops = {
         .recalc         = pllc1_recalc,
 };
 
@@ -128,7 +128,7 @@ static unsigned long pllc2_recalc(struct clk *clk)
         return clk->parent->rate * mult;
 }
 
-static struct clk_ops pllc2_clk_ops = {
+static struct sh_clk_ops pllc2_clk_ops = {
         .recalc         = pllc2_recalc,
 };
 
@@ -349,7 +349,7 @@ void __init sh7367_clock_init(void)
         clkdev_add_table(lookups, ARRAY_SIZE(lookups));
 
         if (!ret)
-                clk_init();
+                shmobile_clk_init();
         else
                 panic("failed to setup sh7367 clocks\n");
 }
diff --git a/arch/arm/mach-shmobile/clock-sh7372.c b/arch/arm/mach-shmobile/clock-sh7372.c
index 293456d8dcf..de243e3c839 100644
--- a/arch/arm/mach-shmobile/clock-sh7372.c
+++ b/arch/arm/mach-shmobile/clock-sh7372.c
@@ -89,7 +89,7 @@ static unsigned long div2_recalc(struct clk *clk)
         return clk->parent->rate / 2;
 }
 
-static struct clk_ops div2_clk_ops = {
+static struct sh_clk_ops div2_clk_ops = {
         .recalc         = div2_recalc,
 };
 
@@ -128,7 +128,7 @@ static unsigned long pllc01_recalc(struct clk *clk)
         return clk->parent->rate * mult;
 }
 
-static struct clk_ops pllc01_clk_ops = {
+static struct sh_clk_ops pllc01_clk_ops = {
         .recalc         = pllc01_recalc,
 };
 
@@ -276,7 +276,7 @@ static int pllc2_set_parent(struct clk *clk, struct clk *parent)
         return 0;
 }
 
-static struct clk_ops pllc2_clk_ops = {
+static struct sh_clk_ops pllc2_clk_ops = {
         .recalc         = pllc2_recalc,
         .round_rate     = pllc2_round_rate,
         .set_rate       = pllc2_set_rate,
@@ -468,7 +468,7 @@ static int fsidiv_set_rate(struct clk *clk, unsigned long rate)
         return 0;
 }
 
-static struct clk_ops fsidiv_clk_ops = {
+static struct sh_clk_ops fsidiv_clk_ops = {
         .recalc         = fsidiv_recalc,
         .round_rate     = fsidiv_round_rate,
         .set_rate       = fsidiv_set_rate,
@@ -710,7 +710,7 @@ void __init sh7372_clock_init(void)
         clkdev_add_table(lookups, ARRAY_SIZE(lookups));
 
         if (!ret)
-                clk_init();
+                shmobile_clk_init();
         else
                 panic("failed to setup sh7372 clocks\n");
 
diff --git a/arch/arm/mach-shmobile/clock-sh7377.c b/arch/arm/mach-shmobile/clock-sh7377.c
index 8cee7b151ae..0798a15936c 100644
--- a/arch/arm/mach-shmobile/clock-sh7377.c
+++ b/arch/arm/mach-shmobile/clock-sh7377.c
@@ -77,7 +77,7 @@ static unsigned long div2_recalc(struct clk *clk)
         return clk->parent->rate / 2;
 }
 
-static struct clk_ops div2_clk_ops = {
+static struct sh_clk_ops div2_clk_ops = {
         .recalc         = div2_recalc,
 };
 
@@ -110,7 +110,7 @@ static unsigned long pllc1_recalc(struct clk *clk)
         return clk->parent->rate * mult;
 }
 
-static struct clk_ops pllc1_clk_ops = {
+static struct sh_clk_ops pllc1_clk_ops = {
         .recalc         = pllc1_recalc,
 };
 
@@ -137,7 +137,7 @@ static unsigned long pllc2_recalc(struct clk *clk)
         return clk->parent->rate * mult;
 }
 
-static struct clk_ops pllc2_clk_ops = {
+static struct sh_clk_ops pllc2_clk_ops = {
         .recalc         = pllc2_recalc,
 };
 
@@ -360,7 +360,7 @@ void __init sh7377_clock_init(void)
         clkdev_add_table(lookups, ARRAY_SIZE(lookups));
 
         if (!ret)
-                clk_init();
+                shmobile_clk_init();
         else
                 panic("failed to setup sh7377 clocks\n");
 }
diff --git a/arch/arm/mach-shmobile/clock-sh73a0.c b/arch/arm/mach-shmobile/clock-sh73a0.c
index 7727cca6136..472d1f5361e 100644
--- a/arch/arm/mach-shmobile/clock-sh73a0.c
+++ b/arch/arm/mach-shmobile/clock-sh73a0.c
@@ -88,7 +88,7 @@ static unsigned long div2_recalc(struct clk *clk)
         return clk->parent->rate / 2;
 }
 
-static struct clk_ops div2_clk_ops = {
+static struct sh_clk_ops div2_clk_ops = {
         .recalc         = div2_recalc,
 };
 
@@ -97,7 +97,7 @@ static unsigned long div7_recalc(struct clk *clk)
         return clk->parent->rate / 7;
 }
 
-static struct clk_ops div7_clk_ops = {
+static struct sh_clk_ops div7_clk_ops = {
         .recalc         = div7_recalc,
 };
 
@@ -106,7 +106,7 @@ static unsigned long div13_recalc(struct clk *clk)
         return clk->parent->rate / 13;
 }
 
-static struct clk_ops div13_clk_ops = {
+static struct sh_clk_ops div13_clk_ops = {
         .recalc         = div13_recalc,
 };
 
@@ -122,7 +122,7 @@ static struct clk extal2_div2_clk = {
         .parent         = &sh73a0_extal2_clk,
 };
 
-static struct clk_ops main_clk_ops = {
+static struct sh_clk_ops main_clk_ops = {
         .recalc         = followparent_recalc,
 };
 
@@ -156,7 +156,7 @@ static unsigned long pll_recalc(struct clk *clk)
         return clk->parent->rate * mult;
 }
 
-static struct clk_ops pll_clk_ops = {
+static struct sh_clk_ops pll_clk_ops = {
         .recalc         = pll_recalc,
 };
 
@@ -438,7 +438,7 @@ static int dsiphy_set_rate(struct clk *clk, unsigned long rate)
         return 0;
 }
 
-static struct clk_ops dsiphy_clk_ops = {
+static struct sh_clk_ops dsiphy_clk_ops = {
         .recalc         = dsiphy_recalc,
         .round_rate     = dsiphy_round_rate,
         .set_rate       = dsiphy_set_rate,
@@ -620,7 +620,7 @@ void __init sh73a0_clock_init(void)
         clkdev_add_table(lookups, ARRAY_SIZE(lookups));
 
         if (!ret)
-                clk_init();
+                shmobile_clk_init();
         else
                 panic("failed to setup sh73a0 clocks\n");
 }
diff --git a/arch/arm/mach-shmobile/clock.c b/arch/arm/mach-shmobile/clock.c
index 31654d78b96..e816ca9bd21 100644
--- a/arch/arm/mach-shmobile/clock.c
+++ b/arch/arm/mach-shmobile/clock.c
@@ -24,7 +24,7 @@
 #include <linux/sh_clk.h>
 #include <linux/export.h>
 
-int __init clk_init(void)
+int __init shmobile_clk_init(void)
 {
         /* Kick the child clocks.. */
         recalculate_root_clocks();
diff --git a/arch/arm/mach-shmobile/include/mach/common.h b/arch/arm/mach-shmobile/include/mach/common.h
index e4b945e271e..83ad3fe0a75 100644
--- a/arch/arm/mach-shmobile/include/mach/common.h
+++ b/arch/arm/mach-shmobile/include/mach/common.h
@@ -1,12 +1,15 @@
 #ifndef __ARCH_MACH_COMMON_H
 #define __ARCH_MACH_COMMON_H
 
+extern void shmobile_earlytimer_init(void);
 extern struct sys_timer shmobile_timer;
+struct twd_local_timer;
+void shmobile_twd_init(struct twd_local_timer *twd_local_timer);
 extern void shmobile_setup_console(void);
 extern void shmobile_secondary_vector(void);
 extern int shmobile_platform_cpu_kill(unsigned int cpu);
 struct clk;
-extern int clk_init(void);
+extern int shmobile_clk_init(void);
 extern void shmobile_handle_irq_intc(struct pt_regs *);
 extern struct platform_suspend_ops shmobile_suspend_ops;
 struct cpuidle_driver;
@@ -14,6 +17,7 @@ extern void (*shmobile_cpuidle_modes[])(void);
 extern void (*shmobile_cpuidle_setup)(struct cpuidle_driver *drv);
 
 extern void sh7367_init_irq(void);
+extern void sh7367_map_io(void);
 extern void sh7367_add_early_devices(void);
 extern void sh7367_add_standard_devices(void);
 extern void sh7367_clock_init(void);
@@ -22,6 +26,7 @@ extern struct clk sh7367_extalb1_clk;
 extern struct clk sh7367_extal2_clk;
 
 extern void sh7377_init_irq(void);
+extern void sh7377_map_io(void);
 extern void sh7377_add_early_devices(void);
 extern void sh7377_add_standard_devices(void);
 extern void sh7377_clock_init(void);
@@ -30,6 +35,7 @@ extern struct clk sh7377_extalc1_clk;
 extern struct clk sh7377_extal2_clk;
 
 extern void sh7372_init_irq(void);
+extern void sh7372_map_io(void);
 extern void sh7372_add_early_devices(void);
 extern void sh7372_add_standard_devices(void);
 extern void sh7372_clock_init(void);
@@ -41,6 +47,7 @@ extern struct clk sh7372_extal1_clk;
 extern struct clk sh7372_extal2_clk;
 
 extern void sh73a0_init_irq(void);
+extern void sh73a0_map_io(void);
 extern void sh73a0_add_early_devices(void);
 extern void sh73a0_add_standard_devices(void);
 extern void sh73a0_clock_init(void);
@@ -56,12 +63,14 @@ extern int sh73a0_boot_secondary(unsigned int cpu);
 extern void sh73a0_smp_prepare_cpus(void);
 
 extern void r8a7740_init_irq(void);
+extern void r8a7740_map_io(void);
 extern void r8a7740_add_early_devices(void);
 extern void r8a7740_add_standard_devices(void);
 extern void r8a7740_clock_init(u8 md_ck);
 extern void r8a7740_pinmux_init(void);
 
 extern void r8a7779_init_irq(void);
+extern void r8a7779_map_io(void);
 extern void r8a7779_add_early_devices(void);
 extern void r8a7779_add_standard_devices(void);
 extern void r8a7779_clock_init(void);
diff --git a/arch/arm/mach-shmobile/include/mach/entry-macro.S b/arch/arm/mach-shmobile/include/mach/entry-macro.S
deleted file mode 100644
index 2a57b2964ee..00000000000
--- a/arch/arm/mach-shmobile/include/mach/entry-macro.S
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * Copyright (C) 2010  Paul Mundt
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
- */
-
-        .macro  disable_fiq
-        .endm
-
-        .macro  arch_ret_to_user, tmp1, tmp2
-        .endm
diff --git a/arch/arm/mach-shmobile/include/mach/system.h b/arch/arm/mach-shmobile/include/mach/system.h
index 956ac18ddbf..3bbcb3fa077 100644
--- a/arch/arm/mach-shmobile/include/mach/system.h
+++ b/arch/arm/mach-shmobile/include/mach/system.h
@@ -1,11 +1,6 @@
 #ifndef __ASM_ARCH_SYSTEM_H
 #define __ASM_ARCH_SYSTEM_H
 
-static inline void arch_idle(void)
-{
-        cpu_do_idle();
-}
-
 static inline void arch_reset(char mode, const char *cmd)
 {
         soft_restart(0);
diff --git a/arch/arm/mach-shmobile/localtimer.c b/arch/arm/mach-shmobile/localtimer.c
deleted file mode 100644
index ad9ccc9900c..00000000000
--- a/arch/arm/mach-shmobile/localtimer.c
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * SMP support for R-Mobile / SH-Mobile - local timer portion
- *
- * Copyright (C) 2010  Magnus Damm
- *
- * Based on vexpress, Copyright (C) 2002 ARM Ltd, All Rights Reserved
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#include <linux/init.h>
-#include <linux/smp.h>
-#include <linux/clockchips.h>
-#include <asm/smp_twd.h>
-#include <asm/localtimer.h>
-
-/*
- * Setup the local clock events for a CPU.
- */
-int __cpuinit local_timer_setup(struct clock_event_device *evt)
-{
-        evt->irq = 29;
-        twd_timer_setup(evt);
-        return 0;
-}
diff --git a/arch/arm/mach-shmobile/platsmp.c b/arch/arm/mach-shmobile/platsmp.c
index 993381257f6..45fa3924c6a 100644
--- a/arch/arm/mach-shmobile/platsmp.c
+++ b/arch/arm/mach-shmobile/platsmp.c
@@ -17,7 +17,6 @@
 #include <linux/smp.h>
 #include <linux/io.h>
 #include <asm/hardware/gic.h>
-#include <asm/localtimer.h>
 #include <asm/mach-types.h>
 #include <mach/common.h>
 
diff --git a/arch/arm/mach-shmobile/setup-r8a7740.c b/arch/arm/mach-shmobile/setup-r8a7740.c
index 986dca6b3fa..74e52341dd1 100644
--- a/arch/arm/mach-shmobile/setup-r8a7740.c
+++ b/arch/arm/mach-shmobile/setup-r8a7740.c
@@ -25,8 +25,41 @@
 #include <linux/serial_sci.h>
 #include <linux/sh_timer.h>
 #include <mach/r8a7740.h>
+#include <mach/common.h>
 #include <asm/mach-types.h>
+#include <asm/mach/map.h>
 #include <asm/mach/arch.h>
+#include <asm/mach/time.h>
+
+static struct map_desc r8a7740_io_desc[] __initdata = {
+         /*
+          * for CPGA/INTC/PFC
+          * 0xe6000000-0xefffffff -> 0xe6000000-0xefffffff
+          */
+        {
+                .virtual        = 0xe6000000,
+                .pfn            = __phys_to_pfn(0xe6000000),
+                .length         = 160 << 20,
+                .type           = MT_DEVICE_NONSHARED
+        },
+#ifdef CONFIG_CACHE_L2X0
+        /*
+         * for l2x0_init()
+         * 0xf0100000-0xf0101000 -> 0xf0002000-0xf0003000
+         */
+        {
+                .virtual        = 0xf0002000,
+                .pfn            = __phys_to_pfn(0xf0100000),
+                .length         = PAGE_SIZE,
+                .type           = MT_DEVICE_NONSHARED
+        },
+#endif
+};
+
+void __init r8a7740_map_io(void)
+{
+        iotable_init(r8a7740_io_desc, ARRAY_SIZE(r8a7740_io_desc));
+}
 
 /* SCIFA0 */
 static struct plat_sci_port scif0_platform_data = {
@@ -345,8 +378,20 @@ void __init r8a7740_add_standard_devices(void)
                              ARRAY_SIZE(r8a7740_late_devices));
 }
 
+static void __init r8a7740_earlytimer_init(void)
+{
+        r8a7740_clock_init(0);
+        shmobile_earlytimer_init();
+}
+
 void __init r8a7740_add_early_devices(void)
 {
         early_platform_add_devices(r8a7740_early_devices,
                                    ARRAY_SIZE(r8a7740_early_devices));
+
+        /* setup early console here as well */
+        shmobile_setup_console();
+
+        /* override timer setup with soc-specific code */
+        shmobile_timer.init = r8a7740_earlytimer_init;
 }
diff --git a/arch/arm/mach-shmobile/setup-r8a7779.c b/arch/arm/mach-shmobile/setup-r8a7779.c
index 4725663bd03..6820d785493 100644
--- a/arch/arm/mach-shmobile/setup-r8a7779.c
+++ b/arch/arm/mach-shmobile/setup-r8a7779.c
@@ -33,6 +33,31 @@
 #include <mach/common.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
+#include <asm/mach/time.h>
+#include <asm/mach/map.h>
+#include <asm/hardware/cache-l2x0.h>
+
+static struct map_desc r8a7779_io_desc[] __initdata = {
+        /* 2M entity map for 0xf0000000 (MPCORE) */
+        {
+                .virtual        = 0xf0000000,
+                .pfn            = __phys_to_pfn(0xf0000000),
+                .length         = SZ_2M,
+                .type           = MT_DEVICE_NONSHARED
+        },
+        /* 16M entity map for 0xfexxxxxx (DMAC-S/HPBREG/INTC2/LRAM/DBSC) */
+        {
+                .virtual        = 0xfe000000,
+                .pfn            = __phys_to_pfn(0xfe000000),
+                .length         = SZ_16M,
+                .type           = MT_DEVICE_NONSHARED
+        },
+};
+
+void __init r8a7779_map_io(void)
+{
+        iotable_init(r8a7779_io_desc, ARRAY_SIZE(r8a7779_io_desc));
+}
 
 static struct plat_sci_port scif0_platform_data = {
         .mapbase        = 0xffe40000,
@@ -219,6 +244,10 @@ static struct platform_device *r8a7779_late_devices[] __initdata = {
 
 void __init r8a7779_add_standard_devices(void)
 {
+#ifdef CONFIG_CACHE_L2X0
+        /* Early BRESP enable, Shared attribute override enable, 64K*16way */
+        l2x0_init((void __iomem __force *)(0xf0100000), 0x40470000, 0x82000fff);
+#endif
         r8a7779_pm_init();
 
         r8a7779_init_pm_domain(&r8a7779_sh4a);
@@ -232,8 +261,33 @@ void __init r8a7779_add_standard_devices(void)
                             ARRAY_SIZE(r8a7779_late_devices));
 }
 
+static void __init r8a7779_earlytimer_init(void)
+{
+        r8a7779_clock_init();
+        shmobile_earlytimer_init();
+}
+
 void __init r8a7779_add_early_devices(void)
 {
         early_platform_add_devices(r8a7779_early_devices,
                                    ARRAY_SIZE(r8a7779_early_devices));
+
+        /* Early serial console setup is not included here due to
+         * memory map collisions. The SCIF serial ports in r8a7779
+         * are difficult to entity map 1:1 due to collision with the
+         * virtual memory range used by the coherent DMA code on ARM.
+         *
+         * Anyone wanting to debug early can remove UPF_IOREMAP from
+         * the sh-sci serial console platform data, adjust mapbase
+         * to a static M:N virt:phys mapping that needs to be added to
+         * the mappings passed with iotable_init() above.
+         *
+         * Then add a call to shmobile_setup_console() from this function.
+         *
+         * As a final step pass earlyprint=sh-sci.2,115200 on the kernel
+         * command line in case of the marzen board.
+         */
+
+        /* override timer setup with soc-specific code */
+        shmobile_timer.init = r8a7779_earlytimer_init;
 }
diff --git a/arch/arm/mach-shmobile/setup-sh7367.c b/arch/arm/mach-shmobile/setup-sh7367.c
index e546017f15d..a51e1a1e699 100644
--- a/arch/arm/mach-shmobile/setup-sh7367.c
+++ b/arch/arm/mach-shmobile/setup-sh7367.c
@@ -29,8 +29,28 @@
 #include <linux/serial_sci.h>
 #include <linux/sh_timer.h>
 #include <mach/hardware.h>
+#include <mach/common.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/mach/time.h>
+
+static struct map_desc sh7367_io_desc[] __initdata = {
+        /* create a 1:1 entity map for 0xe6xxxxxx
+         * used by CPGA, INTC and PFC.
+         */
+        {
+                .virtual        = 0xe6000000,
+                .pfn            = __phys_to_pfn(0xe6000000),
+                .length         = 256 << 20,
+                .type           = MT_DEVICE_NONSHARED
+        },
+};
+
+void __init sh7367_map_io(void)
+{
+        iotable_init(sh7367_io_desc, ARRAY_SIZE(sh7367_io_desc));
+}
 
 /* SCIFA0 */
 static struct plat_sci_port scif0_platform_data = {
@@ -435,6 +455,12 @@ void __init sh7367_add_standard_devices(void)
                             ARRAY_SIZE(sh7367_devices));
 }
 
+static void __init sh7367_earlytimer_init(void)
+{
+        sh7367_clock_init();
+        shmobile_earlytimer_init();
+}
+
 #define SYMSTPCR2 0xe6158048
 #define SYMSTPCR2_CMT1 (1 << 29)
 
@@ -445,4 +471,10 @@ void __init sh7367_add_early_devices(void)
 
         early_platform_add_devices(sh7367_early_devices,
                                    ARRAY_SIZE(sh7367_early_devices));
+
+        /* setup early console here as well */
+        shmobile_setup_console();
+
+        /* override timer setup with soc-specific code */
+        shmobile_timer.init = sh7367_earlytimer_init;
 }
diff --git a/arch/arm/mach-shmobile/setup-sh7372.c b/arch/arm/mach-shmobile/setup-sh7372.c
index cccf91b8fae..5375325d7ca 100644
--- a/arch/arm/mach-shmobile/setup-sh7372.c
+++ b/arch/arm/mach-shmobile/setup-sh7372.c
@@ -33,8 +33,28 @@
 #include <linux/pm_domain.h>
 #include <mach/hardware.h>
 #include <mach/sh7372.h>
+#include <mach/common.h>
+#include <asm/mach/map.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
+#include <asm/mach/time.h>
+
+static struct map_desc sh7372_io_desc[] __initdata = {
+        /* create a 1:1 entity map for 0xe6xxxxxx
+         * used by CPGA, INTC and PFC.
+         */
+        {
+                .virtual        = 0xe6000000,
+                .pfn            = __phys_to_pfn(0xe6000000),
+                .length         = 256 << 20,
+                .type           = MT_DEVICE_NONSHARED
+        },
+};
+
+void __init sh7372_map_io(void)
+{
+        iotable_init(sh7372_io_desc, ARRAY_SIZE(sh7372_io_desc));
+}
 
 /* SCIFA0 */
 static struct plat_sci_port scif0_platform_data = {
@@ -1047,8 +1067,20 @@ void __init sh7372_add_standard_devices(void)
         sh7372_add_device_to_domain(&sh7372_a4r, &tmu01_device);
 }
 
+static void __init sh7372_earlytimer_init(void)
+{
+        sh7372_clock_init();
+        shmobile_earlytimer_init();
+}
+
 void __init sh7372_add_early_devices(void)
 {
         early_platform_add_devices(sh7372_early_devices,
                                    ARRAY_SIZE(sh7372_early_devices));
+
+        /* setup early console here as well */
+        shmobile_setup_console();
+
+        /* override timer setup with soc-specific code */
+        shmobile_timer.init = sh7372_earlytimer_init;
 }
diff --git a/arch/arm/mach-shmobile/setup-sh7377.c b/arch/arm/mach-shmobile/setup-sh7377.c
index bb405b8e459..9f146095098 100644
--- a/arch/arm/mach-shmobile/setup-sh7377.c
+++ b/arch/arm/mach-shmobile/setup-sh7377.c
@@ -30,8 +30,28 @@
 #include <linux/sh_intc.h>
 #include <linux/sh_timer.h>
 #include <mach/hardware.h>
+#include <mach/common.h>
+#include <asm/mach/map.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
+#include <asm/mach/time.h>
+
+static struct map_desc sh7377_io_desc[] __initdata = {
+        /* create a 1:1 entity map for 0xe6xxxxxx
+         * used by CPGA, INTC and PFC.
+         */
+        {
+                .virtual        = 0xe6000000,
+                .pfn            = __phys_to_pfn(0xe6000000),
+                .length         = 256 << 20,
+                .type           = MT_DEVICE_NONSHARED
+        },
+};
+
+void __init sh7377_map_io(void)
+{
+        iotable_init(sh7377_io_desc, ARRAY_SIZE(sh7377_io_desc));
+}
 
 /* SCIFA0 */
 static struct plat_sci_port scif0_platform_data = {
@@ -456,6 +476,12 @@ void __init sh7377_add_standard_devices(void)
                             ARRAY_SIZE(sh7377_devices));
 }
 
+static void __init sh7377_earlytimer_init(void)
+{
+        sh7377_clock_init();
+        shmobile_earlytimer_init();
+}
+
 #define SMSTPCR3 0xe615013c
 #define SMSTPCR3_CMT1 (1 << 29)
 
@@ -466,4 +492,10 @@ void __init sh7377_add_early_devices(void)
 
         early_platform_add_devices(sh7377_early_devices,
                                    ARRAY_SIZE(sh7377_early_devices));
+
+        /* setup early console here as well */
+        shmobile_setup_console();
+
+        /* override timer setup with soc-specific code */
+        shmobile_timer.init = sh7377_earlytimer_init;
 }
diff --git a/arch/arm/mach-shmobile/setup-sh73a0.c b/arch/arm/mach-shmobile/setup-sh73a0.c
index 20e71e5cace..b6a0734a738 100644
--- a/arch/arm/mach-shmobile/setup-sh73a0.c
+++ b/arch/arm/mach-shmobile/setup-sh73a0.c
@@ -32,8 +32,28 @@
 #include <linux/sh_timer.h>
 #include <mach/hardware.h>
 #include <mach/sh73a0.h>
+#include <mach/common.h>
 #include <asm/mach-types.h>
+#include <asm/mach/map.h>
 #include <asm/mach/arch.h>
+#include <asm/mach/time.h>
+
+static struct map_desc sh73a0_io_desc[] __initdata = {
+        /* create a 1:1 entity map for 0xe6xxxxxx
+         * used by CPGA, INTC and PFC.
+         */
+        {
+                .virtual        = 0xe6000000,
+                .pfn            = __phys_to_pfn(0xe6000000),
+                .length         = 256 << 20,
+                .type           = MT_DEVICE_NONSHARED
+        },
+};
+
+void __init sh73a0_map_io(void)
+{
+        iotable_init(sh73a0_io_desc, ARRAY_SIZE(sh73a0_io_desc));
+}
 
 static struct plat_sci_port scif0_platform_data = {
         .mapbase        = 0xe6c40000,
@@ -667,8 +687,20 @@ void __init sh73a0_add_standard_devices(void)
                             ARRAY_SIZE(sh73a0_late_devices));
 }
 
+static void __init sh73a0_earlytimer_init(void)
+{
+        sh73a0_clock_init();
+        shmobile_earlytimer_init();
+}
+
 void __init sh73a0_add_early_devices(void)
 {
         early_platform_add_devices(sh73a0_early_devices,
                                    ARRAY_SIZE(sh73a0_early_devices));
+
+        /* setup early console here as well */
+        shmobile_setup_console();
+
+        /* override timer setup with soc-specific code */
+        shmobile_timer.init = sh73a0_earlytimer_init;
 }
diff --git a/arch/arm/mach-shmobile/smp-r8a7779.c b/arch/arm/mach-shmobile/smp-r8a7779.c
index 4fe2e9eaf50..9bb7b8575a1 100644
--- a/arch/arm/mach-shmobile/smp-r8a7779.c
+++ b/arch/arm/mach-shmobile/smp-r8a7779.c
@@ -64,6 +64,8 @@ static void __iomem *scu_base_addr(void)
 static DEFINE_SPINLOCK(scu_lock);
 static unsigned long tmp;
 
+static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, 0xf0000600, 29);
+
 static void modify_scu_cpu_psr(unsigned long set, unsigned long clr)
 {
         void __iomem *scu_base = scu_base_addr();
@@ -82,11 +84,7 @@ unsigned int __init r8a7779_get_core_count(void)
 {
         void __iomem *scu_base = scu_base_addr();
 
-#ifdef CONFIG_HAVE_ARM_TWD
-        /* twd_base needs to be initialized before percpu_timer_setup() */
-        twd_base = (void __iomem *)0xf0000600;
-#endif
-
+        shmobile_twd_init(&twd_local_timer);
         return scu_get_core_count(scu_base);
 }
 
diff --git a/arch/arm/mach-shmobile/smp-sh73a0.c b/arch/arm/mach-shmobile/smp-sh73a0.c
index 2d0d4212be4..c0a9093ba3a 100644
--- a/arch/arm/mach-shmobile/smp-sh73a0.c
+++ b/arch/arm/mach-shmobile/smp-sh73a0.c
@@ -42,6 +42,8 @@ static void __iomem *scu_base_addr(void)
 static DEFINE_SPINLOCK(scu_lock);
 static unsigned long tmp;
 
+static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, 0xf0000600, 29);
+
 static void modify_scu_cpu_psr(unsigned long set, unsigned long clr)
 {
         void __iomem *scu_base = scu_base_addr();
@@ -60,11 +62,7 @@ unsigned int __init sh73a0_get_core_count(void)
 {
         void __iomem *scu_base = scu_base_addr();
 
-#ifdef CONFIG_HAVE_ARM_TWD
-        /* twd_base needs to be initialized before percpu_timer_setup() */
-        twd_base = (void __iomem *)0xf0000600;
-#endif
-
+        shmobile_twd_init(&twd_local_timer);
         return scu_get_core_count(scu_base);
 }
 
diff --git a/arch/arm/mach-shmobile/timer.c b/arch/arm/mach-shmobile/timer.c
index 895794b543c..2fba5f3d1c8 100644
--- a/arch/arm/mach-shmobile/timer.c
+++ b/arch/arm/mach-shmobile/timer.c
@@ -20,6 +20,7 @@
  */
 #include <linux/platform_device.h>
 #include <asm/mach/time.h>
+#include <asm/smp_twd.h>
 
 static void __init shmobile_late_time_init(void)
 {
@@ -36,11 +37,24 @@ static void __init shmobile_late_time_init(void)
         early_platform_driver_probe("earlytimer", 2, 0);
 }
 
-static void __init shmobile_timer_init(void)
+void __init shmobile_earlytimer_init(void)
 {
         late_time_init = shmobile_late_time_init;
 }
 
+static void __init shmobile_timer_init(void)
+{
+}
+
+void __init shmobile_twd_init(struct twd_local_timer *twd_local_timer)
+{
+#ifdef CONFIG_HAVE_ARM_TWD
+        int err = twd_local_timer_register(twd_local_timer);
+        if (err)
+                pr_err("twd_local_timer_register failed %d\n", err);
+#endif
+}
+
 struct sys_timer shmobile_timer = {
         .init           = shmobile_timer_init,
 };
diff --git a/arch/arm/mach-spear3xx/include/mach/entry-macro.S b/arch/arm/mach-spear3xx/include/mach/entry-macro.S
deleted file mode 100644
index de3bb41c8e9..00000000000
--- a/arch/arm/mach-spear3xx/include/mach/entry-macro.S
+++ /dev/null
@@ -1,18 +0,0 @@
-/*
- * arch/arm/mach-spear3xx/include/mach/entry-macro.S
- *
- * Low-level IRQ helper macros for SPEAr3xx machine family
- *
- * Copyright (C) 2009 ST Microelectronics
- * Viresh Kumar<viresh.kumar@st.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-                .macro  disable_fiq
-                .endm
-
-                .macro  arch_ret_to_user, tmp1, tmp2
-                .endm
diff --git a/arch/arm/mach-spear3xx/include/mach/system.h b/arch/arm/mach-spear3xx/include/mach/system.h
deleted file mode 100644
index 92cee6335c9..00000000000
--- a/arch/arm/mach-spear3xx/include/mach/system.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/*
- * arch/arm/mach-spear3xx/include/mach/system.h
- *
- * SPEAr3xx Machine family specific architecture functions
- *
- * Copyright (C) 2009 ST Microelectronics
- * Viresh Kumar<viresh.kumar@st.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#ifndef __MACH_SYSTEM_H
-#define __MACH_SYSTEM_H
-
-#include <plat/system.h>
-
-#endif /* __MACH_SYSTEM_H */
diff --git a/arch/arm/mach-spear3xx/spear300.c b/arch/arm/mach-spear3xx/spear300.c
index 4f7f5182dd4..f7db66812ab 100644
--- a/arch/arm/mach-spear3xx/spear300.c
+++ b/arch/arm/mach-spear3xx/spear300.c
@@ -430,18 +430,8 @@ static struct pl061_platform_data gpio1_plat_data = {
         .irq_base       = SPEAR300_GPIO1_INT_BASE,
 };
 
-struct amba_device spear300_gpio1_device = {
-        .dev = {
-                .init_name = "gpio1",
-                .platform_data = &gpio1_plat_data,
-        },
-        .res = {
-                .start = SPEAR300_GPIO_BASE,
-                .end = SPEAR300_GPIO_BASE + SZ_4K - 1,
-                .flags = IORESOURCE_MEM,
-        },
-        .irq = {SPEAR300_VIRQ_GPIO1, NO_IRQ},
-};
+AMBA_APB_DEVICE(spear300_gpio1, "gpio1", 0, SPEAR300_GPIO_BASE,
+        {SPEAR300_VIRQ_GPIO1}, &gpio1_plat_data);
 
 /* spear300 routines */
 void __init spear300_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
diff --git a/arch/arm/mach-spear3xx/spear3xx.c b/arch/arm/mach-spear3xx/spear3xx.c
index 10af45da86a..b1733c37f20 100644
--- a/arch/arm/mach-spear3xx/spear3xx.c
+++ b/arch/arm/mach-spear3xx/spear3xx.c
@@ -28,31 +28,12 @@ static struct pl061_platform_data gpio_plat_data = {
         .irq_base       = SPEAR3XX_GPIO_INT_BASE,
 };
 
-struct amba_device spear3xx_gpio_device = {
-        .dev = {
-                .init_name = "gpio",
-                .platform_data = &gpio_plat_data,
-        },
-        .res = {
-                .start = SPEAR3XX_ICM3_GPIO_BASE,
-                .end = SPEAR3XX_ICM3_GPIO_BASE + SZ_4K - 1,
-                .flags = IORESOURCE_MEM,
-        },
-        .irq = {SPEAR3XX_IRQ_BASIC_GPIO, NO_IRQ},
-};
+AMBA_APB_DEVICE(spear3xx_gpio, "gpio", 0, SPEAR3XX_ICM3_GPIO_BASE,
+        {SPEAR3XX_IRQ_BASIC_GPIO}, &gpio_plat_data);
 
 /* uart device registration */
-struct amba_device spear3xx_uart_device = {
-        .dev = {
-                .init_name = "uart",
-        },
-        .res = {
-                .start = SPEAR3XX_ICM1_UART_BASE,
-                .end = SPEAR3XX_ICM1_UART_BASE + SZ_4K - 1,
-                .flags = IORESOURCE_MEM,
-        },
-        .irq = {SPEAR3XX_IRQ_UART, NO_IRQ},
-};
+AMBA_APB_DEVICE(spear3xx_uart, "uart", 0, SPEAR3XX_ICM1_UART_BASE,
+        {SPEAR3XX_IRQ_UART}, NULL);
 
 /* Do spear3xx familiy common initialization part here */
 void __init spear3xx_init(void)
diff --git a/arch/arm/mach-spear6xx/include/mach/entry-macro.S b/arch/arm/mach-spear6xx/include/mach/entry-macro.S
deleted file mode 100644
index d490a910d92..00000000000
--- a/arch/arm/mach-spear6xx/include/mach/entry-macro.S
+++ /dev/null
@@ -1,18 +0,0 @@
-/*
- * arch/arm/mach-spear6xx/include/mach/entry-macro.S
- *
- * Low-level IRQ helper macros for SPEAr6xx machine family
- *
- * Copyright (C) 2009 ST Microelectronics
- * Rajeev Kumar<rajeev-dlh.kumar@st.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-                .macro  disable_fiq
-                .endm
-
-                .macro  arch_ret_to_user, tmp1, tmp2
-                .endm
diff --git a/arch/arm/mach-spear6xx/include/mach/system.h b/arch/arm/mach-spear6xx/include/mach/system.h
deleted file mode 100644
index 0b1d2be81cf..00000000000
--- a/arch/arm/mach-spear6xx/include/mach/system.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/*
- * arch/arm/mach-spear6xx/include/mach/system.h
- *
- * SPEAr6xx Machine family specific architecture functions
- *
- * Copyright (C) 2009 ST Microelectronics
- * Rajeev Kumar<rajeev-dlh.kumar@st.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#ifndef __MACH_SYSTEM_H
-#define __MACH_SYSTEM_H
-
-#include <plat/system.h>
-
-#endif  /* __MACH_SYSTEM_H */
diff --git a/arch/arm/mach-spear6xx/spear6xx.c b/arch/arm/mach-spear6xx/spear6xx.c
index e0f6628c8b2..b997b1b10ba 100644
--- a/arch/arm/mach-spear6xx/spear6xx.c
+++ b/arch/arm/mach-spear6xx/spear6xx.c
@@ -34,7 +34,7 @@ struct amba_device uart_device[] = {
                         .end = SPEAR6XX_ICM1_UART0_BASE + SZ_4K - 1,
                         .flags = IORESOURCE_MEM,
                 },
-                .irq = {IRQ_UART_0, NO_IRQ},
+                .irq = {IRQ_UART_0},
         }, {
                 .dev = {
                         .init_name = "uart1",
@@ -44,7 +44,7 @@ struct amba_device uart_device[] = {
                         .end = SPEAR6XX_ICM1_UART1_BASE + SZ_4K - 1,
                         .flags = IORESOURCE_MEM,
                 },
-                .irq = {IRQ_UART_1, NO_IRQ},
+                .irq = {IRQ_UART_1},
         }
 };
 
@@ -73,7 +73,7 @@ struct amba_device gpio_device[] = {
                         .end = SPEAR6XX_CPU_GPIO_BASE + SZ_4K - 1,
                         .flags = IORESOURCE_MEM,
                 },
-                .irq = {IRQ_LOCAL_GPIO, NO_IRQ},
+                .irq = {IRQ_LOCAL_GPIO},
         }, {
                 .dev = {
                         .init_name = "gpio1",
@@ -84,7 +84,7 @@ struct amba_device gpio_device[] = {
                         .end = SPEAR6XX_ICM3_GPIO_BASE + SZ_4K - 1,
                         .flags = IORESOURCE_MEM,
                 },
-                .irq = {IRQ_BASIC_GPIO, NO_IRQ},
+                .irq = {IRQ_BASIC_GPIO},
         }, {
                 .dev = {
                         .init_name = "gpio2",
@@ -95,7 +95,7 @@ struct amba_device gpio_device[] = {
                         .end = SPEAR6XX_ICM2_GPIO_BASE + SZ_4K - 1,
                         .flags = IORESOURCE_MEM,
                 },
-                .irq = {IRQ_APPL_GPIO, NO_IRQ},
+                .irq = {IRQ_APPL_GPIO},
         }
 };
 
diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig
index 373652d76b9..d0f2546706c 100644
--- a/arch/arm/mach-tegra/Kconfig
+++ b/arch/arm/mach-tegra/Kconfig
@@ -7,9 +7,19 @@ config ARCH_TEGRA_2x_SOC
         select CPU_V7
         select ARM_GIC
         select ARCH_REQUIRE_GPIOLIB
+        select PINCTRL
+        select PINCTRL_TEGRA20
         select USB_ARCH_HAS_EHCI if USB_SUPPORT
-        select USB_ULPI if USB_SUPPORT
+        select USB_ULPI if USB
         select USB_ULPI_VIEWPORT if USB_SUPPORT
+        select ARM_ERRATA_720789
+        select ARM_ERRATA_742230
+        select ARM_ERRATA_751472
+        select ARM_ERRATA_754327
+        select ARM_ERRATA_764369
+        select PL310_ERRATA_727915 if CACHE_L2X0
+        select PL310_ERRATA_769419 if CACHE_L2X0
+        select CPU_FREQ_TABLE if CPU_FREQ
         help
           Support for NVIDIA Tegra AP20 and T20 processors, based on the
           ARM CortexA9MP CPU and the ARM PL310 L2 cache controller
@@ -19,10 +29,18 @@ config ARCH_TEGRA_3x_SOC
         select CPU_V7
         select ARM_GIC
         select ARCH_REQUIRE_GPIOLIB
+        select PINCTRL
+        select PINCTRL_TEGRA30
         select USB_ARCH_HAS_EHCI if USB_SUPPORT
-        select USB_ULPI if USB_SUPPORT
+        select USB_ULPI if USB
         select USB_ULPI_VIEWPORT if USB_SUPPORT
         select USE_OF
+        select ARM_ERRATA_743622
+        select ARM_ERRATA_751472
+        select ARM_ERRATA_754322
+        select ARM_ERRATA_764369
+        select PL310_ERRATA_769419 if CACHE_L2X0
+        select CPU_FREQ_TABLE if CPU_FREQ
         help
           Support for NVIDIA Tegra T30 processor family, based on the
           ARM CortexA9MP CPU and the ARM PL310 L2 cache controller
diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile
index e120ff54f66..1dd2726986c 100644
--- a/arch/arm/mach-tegra/Makefile
+++ b/arch/arm/mach-tegra/Makefile
@@ -7,15 +7,19 @@ obj-y                                   += clock.o
 obj-y                                   += timer.o
 obj-y                                   += pinmux.o
 obj-y                                   += fuse.o
+obj-y                                   += pmc.o
+obj-$(CONFIG_CPU_IDLE)                  += cpuidle.o
+obj-$(CONFIG_CPU_IDLE)                  += sleep.o
 obj-$(CONFIG_ARCH_TEGRA_2x_SOC)         += powergate.o
 obj-$(CONFIG_ARCH_TEGRA_2x_SOC)         += tegra2_clocks.o
 obj-$(CONFIG_ARCH_TEGRA_2x_SOC)         += tegra2_emc.o
 obj-$(CONFIG_ARCH_TEGRA_2x_SOC)         += pinmux-tegra20-tables.o
 obj-$(CONFIG_ARCH_TEGRA_3x_SOC)         += pinmux-tegra30-tables.o
 obj-$(CONFIG_ARCH_TEGRA_3x_SOC)         += board-dt-tegra30.o
-obj-$(CONFIG_SMP)                       += platsmp.o localtimer.o headsmp.o
+obj-$(CONFIG_ARCH_TEGRA_3x_SOC)         += tegra30_clocks.o
+obj-$(CONFIG_SMP)                       += platsmp.o headsmp.o
 obj-$(CONFIG_HOTPLUG_CPU)               += hotplug.o
-obj-$(CONFIG_TEGRA_SYSTEM_DMA)          += dma.o
+obj-$(CONFIG_TEGRA_SYSTEM_DMA)          += dma.o apbio.o
 obj-$(CONFIG_CPU_FREQ)                  += cpu-tegra.o
 obj-$(CONFIG_TEGRA_PCI)                 += pcie.o
 obj-$(CONFIG_USB_SUPPORT)               += usb_phy.o
diff --git a/arch/arm/mach-tegra/apbio.c b/arch/arm/mach-tegra/apbio.c
new file mode 100644
index 00000000000..e75451e517b
--- /dev/null
+++ b/arch/arm/mach-tegra/apbio.c
@@ -0,0 +1,145 @@
+/*
+ * Copyright (C) 2010 NVIDIA Corporation.
+ * Copyright (C) 2010 Google, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/io.h>
+#include <linux/dma-mapping.h>
+#include <linux/spinlock.h>
+#include <linux/completion.h>
+#include <linux/sched.h>
+#include <linux/mutex.h>
+
+#include <mach/dma.h>
+#include <mach/iomap.h>
+
+#include "apbio.h"
+
+static DEFINE_MUTEX(tegra_apb_dma_lock);
+
+static struct tegra_dma_channel *tegra_apb_dma;
+static u32 *tegra_apb_bb;
+static dma_addr_t tegra_apb_bb_phys;
+static DECLARE_COMPLETION(tegra_apb_wait);
+
+bool tegra_apb_init(void)
+{
+        struct tegra_dma_channel *ch;
+
+        mutex_lock(&tegra_apb_dma_lock);
+
+        /* Check to see if we raced to setup */
+        if (tegra_apb_dma)
+                goto out;
+
+        ch = tegra_dma_allocate_channel(TEGRA_DMA_MODE_ONESHOT |
+                TEGRA_DMA_SHARED);
+
+        if (!ch)
+                goto out_fail;
+
+        tegra_apb_bb = dma_alloc_coherent(NULL, sizeof(u32),
+                &tegra_apb_bb_phys, GFP_KERNEL);
+        if (!tegra_apb_bb) {
+                pr_err("%s: can not allocate bounce buffer\n", __func__);
+                tegra_dma_free_channel(ch);
+                goto out_fail;
+        }
+
+        tegra_apb_dma = ch;
+out:
+        mutex_unlock(&tegra_apb_dma_lock);
+        return true;
+
+out_fail:
+        mutex_unlock(&tegra_apb_dma_lock);
+        return false;
+}
+
+static void apb_dma_complete(struct tegra_dma_req *req)
+{
+        complete(&tegra_apb_wait);
+}
+
+u32 tegra_apb_readl(unsigned long offset)
+{
+        struct tegra_dma_req req;
+        int ret;
+
+        if (!tegra_apb_dma && !tegra_apb_init())
+                return readl(IO_TO_VIRT(offset));
+
+        mutex_lock(&tegra_apb_dma_lock);
+        req.complete = apb_dma_complete;
+        req.to_memory = 1;
+        req.dest_addr = tegra_apb_bb_phys;
+        req.dest_bus_width = 32;
+        req.dest_wrap = 1;
+        req.source_addr = offset;
+        req.source_bus_width = 32;
+        req.source_wrap = 4;
+        req.req_sel = TEGRA_DMA_REQ_SEL_CNTR;
+        req.size = 4;
+
+        INIT_COMPLETION(tegra_apb_wait);
+
+        tegra_dma_enqueue_req(tegra_apb_dma, &req);
+
+        ret = wait_for_completion_timeout(&tegra_apb_wait,
+                msecs_to_jiffies(50));
+
+        if (WARN(ret == 0, "apb read dma timed out")) {
+                tegra_dma_dequeue_req(tegra_apb_dma, &req);
+                *(u32 *)tegra_apb_bb = 0;
+        }
+
+        mutex_unlock(&tegra_apb_dma_lock);
+        return *((u32 *)tegra_apb_bb);
+}
+
+void tegra_apb_writel(u32 value, unsigned long offset)
+{
+        struct tegra_dma_req req;
+        int ret;
+
+        if (!tegra_apb_dma && !tegra_apb_init()) {
+                writel(value, IO_TO_VIRT(offset));
+                return;
+        }
+
+        mutex_lock(&tegra_apb_dma_lock);
+        *((u32 *)tegra_apb_bb) = value;
+        req.complete = apb_dma_complete;
+        req.to_memory = 0;
+        req.dest_addr = offset;
+        req.dest_wrap = 4;
+        req.dest_bus_width = 32;
+        req.source_addr = tegra_apb_bb_phys;
+        req.source_bus_width = 32;
+        req.source_wrap = 1;
+        req.req_sel = TEGRA_DMA_REQ_SEL_CNTR;
+        req.size = 4;
+
+        INIT_COMPLETION(tegra_apb_wait);
+
+        tegra_dma_enqueue_req(tegra_apb_dma, &req);
+
+        ret = wait_for_completion_timeout(&tegra_apb_wait,
+                msecs_to_jiffies(50));
+
+        if (WARN(ret == 0, "apb write dma timed out"))
+                tegra_dma_dequeue_req(tegra_apb_dma, &req);
+
+        mutex_unlock(&tegra_apb_dma_lock);
+}
diff --git a/arch/arm/mach-tegra/include/mach/system.h b/arch/arm/mach-tegra/apbio.h
index a312988bf6f..8b49e8c89a6 100644
--- a/arch/arm/mach-tegra/include/mach/system.h
+++ b/arch/arm/mach-tegra/apbio.h
@@ -1,12 +1,7 @@
 /*
- * arch/arm/mach-tegra/include/mach/system.h
- *
+ * Copyright (C) 2010 NVIDIA Corporation.
  * Copyright (C) 2010 Google, Inc.
  *
- * Author:
- *      Colin Cross <ccross@google.com>
- *      Erik Gilling <konkers@google.com>
- *
  * This software is licensed under the terms of the GNU General Public
  * License version 2, as published by the Free Software Foundation, and
  * may be copied, distributed, and modified under those terms.
@@ -18,11 +13,27 @@
  *
  */
 
-#ifndef __MACH_TEGRA_SYSTEM_H
-#define __MACH_TEGRA_SYSTEM_H
+#ifndef __MACH_TEGRA_APBIO_H
+#define __MACH_TEGRA_APBIO_H
+
+#ifdef CONFIG_TEGRA_SYSTEM_DMA
+
+u32 tegra_apb_readl(unsigned long offset);
+void tegra_apb_writel(u32 value, unsigned long offset);
+
+#else
+#include <asm/io.h>
+#include <mach/io.h>
 
-static inline void arch_idle(void)
+static inline u32 tegra_apb_readl(unsigned long offset)
 {
+        return readl(IO_TO_VIRT(offset));
 }
 
+static inline void tegra_apb_writel(u32 value, unsigned long offset)
+{
+        writel(value, IO_TO_VIRT(offset));
+}
+#endif
+
 #endif
diff --git a/arch/arm/mach-tegra/board-dt-tegra20.c b/arch/arm/mach-tegra/board-dt-tegra20.c
index 7a95e0bc4ab..e20b419d598 100644
--- a/arch/arm/mach-tegra/board-dt-tegra20.c
+++ b/arch/arm/mach-tegra/board-dt-tegra20.c
@@ -131,11 +131,7 @@ static void __init tegra_dt_init(void)
 }
 
 static const char *tegra20_dt_board_compat[] = {
-        "compulab,trimslice",
-        "nvidia,harmony",
-        "compal,paz00",
-        "nvidia,seaboard",
-        "nvidia,ventana",
+        "nvidia,tegra20",
         NULL
 };
 
diff --git a/arch/arm/mach-tegra/board-dt-tegra30.c b/arch/arm/mach-tegra/board-dt-tegra30.c
index 3c197e2440b..96f6c0d030b 100644
--- a/arch/arm/mach-tegra/board-dt-tegra30.c
+++ b/arch/arm/mach-tegra/board-dt-tegra30.c
@@ -34,20 +34,42 @@
 #include <asm/hardware/gic.h>
 
 #include "board.h"
+#include "clock.h"
 
 static struct of_device_id tegra_dt_match_table[] __initdata = {
         { .compatible = "simple-bus", },
         {}
 };
 
+struct of_dev_auxdata tegra30_auxdata_lookup[] __initdata = {
+        OF_DEV_AUXDATA("nvidia,tegra20-sdhci", 0x78000000, "sdhci-tegra.0", NULL),
+        OF_DEV_AUXDATA("nvidia,tegra20-sdhci", 0x78000200, "sdhci-tegra.1", NULL),
+        OF_DEV_AUXDATA("nvidia,tegra20-sdhci", 0x78000400, "sdhci-tegra.2", NULL),
+        OF_DEV_AUXDATA("nvidia,tegra20-sdhci", 0x78000600, "sdhci-tegra.3", NULL),
+        OF_DEV_AUXDATA("nvidia,tegra20-i2c", 0x7000C000, "tegra-i2c.0", NULL),
+        OF_DEV_AUXDATA("nvidia,tegra20-i2c", 0x7000C400, "tegra-i2c.1", NULL),
+        OF_DEV_AUXDATA("nvidia,tegra20-i2c", 0x7000C500, "tegra-i2c.2", NULL),
+        OF_DEV_AUXDATA("nvidia,tegra20-i2c", 0x7000C700, "tegra-i2c.3", NULL),
+        OF_DEV_AUXDATA("nvidia,tegra20-i2c", 0x7000D000, "tegra-i2c.4", NULL),
+        {}
+};
+
+static __initdata struct tegra_clk_init_table tegra_dt_clk_init_table[] = {
+        /* name         parent          rate            enabled */
+        { "uartd",      "pll_p",        408000000,      true },
+        { NULL,         NULL,           0,              0},
+};
+
 static void __init tegra30_dt_init(void)
 {
+        tegra_clk_init_from_table(tegra_dt_clk_init_table);
+
         of_platform_populate(NULL, tegra_dt_match_table,
-                                NULL, NULL);
+                                tegra30_auxdata_lookup, NULL);
 }
 
 static const char *tegra30_dt_board_compat[] = {
-        "nvidia,cardhu",
+        "nvidia,tegra30",
         NULL
 };
 
diff --git a/arch/arm/mach-tegra/board-harmony-pinmux.c b/arch/arm/mach-tegra/board-harmony-pinmux.c
index 465808c8ac0..1af85bccc0f 100644
--- a/arch/arm/mach-tegra/board-harmony-pinmux.c
+++ b/arch/arm/mach-tegra/board-harmony-pinmux.c
@@ -53,7 +53,7 @@ static struct tegra_pingroup_config harmony_pinmux[] = {
         {TEGRA_PINGROUP_GME,   TEGRA_MUX_SDIO4,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
         {TEGRA_PINGROUP_GPU,   TEGRA_MUX_GMI,           TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
         {TEGRA_PINGROUP_GPU7,  TEGRA_MUX_RTCK,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_GPV,   TEGRA_MUX_PCIE,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
+        {TEGRA_PINGROUP_GPV,   TEGRA_MUX_PCIE,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
         {TEGRA_PINGROUP_HDINT, TEGRA_MUX_HDMI,          TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
         {TEGRA_PINGROUP_I2CP,  TEGRA_MUX_I2C,           TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
         {TEGRA_PINGROUP_IRRX,  TEGRA_MUX_UARTA,         TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
@@ -112,10 +112,10 @@ static struct tegra_pingroup_config harmony_pinmux[] = {
         {TEGRA_PINGROUP_SDC,   TEGRA_MUX_PWM,           TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
         {TEGRA_PINGROUP_SDD,   TEGRA_MUX_PWM,           TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
         {TEGRA_PINGROUP_SDIO1, TEGRA_MUX_SDIO1,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_SLXA,  TEGRA_MUX_PCIE,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
+        {TEGRA_PINGROUP_SLXA,  TEGRA_MUX_PCIE,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
         {TEGRA_PINGROUP_SLXC,  TEGRA_MUX_SPDIF,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
         {TEGRA_PINGROUP_SLXD,  TEGRA_MUX_SPDIF,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_SLXK,  TEGRA_MUX_PCIE,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
+        {TEGRA_PINGROUP_SLXK,  TEGRA_MUX_PCIE,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
         {TEGRA_PINGROUP_SPDI,  TEGRA_MUX_RSVD2,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
         {TEGRA_PINGROUP_SPDO,  TEGRA_MUX_RSVD2,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
         {TEGRA_PINGROUP_SPIA,  TEGRA_MUX_GMI,           TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
diff --git a/arch/arm/mach-tegra/board-harmony-power.c b/arch/arm/mach-tegra/board-harmony-power.c
index 21d1285731b..82f32300796 100644
--- a/arch/arm/mach-tegra/board-harmony-power.c
+++ b/arch/arm/mach-tegra/board-harmony-power.c
@@ -18,31 +18,27 @@
 #include <linux/i2c.h>
 #include <linux/platform_device.h>
 #include <linux/gpio.h>
-#include <linux/io.h>
 #include <linux/regulator/machine.h>
 #include <linux/mfd/tps6586x.h>
 
-#include <mach/iomap.h>
 #include <mach/irqs.h>
 
 #include "board-harmony.h"
 
-#define PMC_CTRL                0x0
-#define PMC_CTRL_INTR_LOW       (1 << 17)
-
 static struct regulator_consumer_supply tps658621_ldo0_supply[] = {
         REGULATOR_SUPPLY("pex_clk", NULL),
 };
 
 static struct regulator_init_data ldo0_data = {
         .constraints = {
-                .min_uV = 1250 * 1000,
+                .min_uV = 3300 * 1000,
                 .max_uV = 3300 * 1000,
                 .valid_modes_mask = (REGULATOR_MODE_NORMAL |
                                      REGULATOR_MODE_STANDBY),
                 .valid_ops_mask = (REGULATOR_CHANGE_MODE |
                                    REGULATOR_CHANGE_STATUS |
                                    REGULATOR_CHANGE_VOLTAGE),
+                .apply_uV = 1,
         },
         .num_consumer_supplies = ARRAY_SIZE(tps658621_ldo0_supply),
         .consumer_supplies = tps658621_ldo0_supply,
@@ -114,16 +110,6 @@ static struct i2c_board_info __initdata harmony_regulators[] = {
 
 int __init harmony_regulator_init(void)
 {
-        void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE);
-        u32 pmc_ctrl;
-
-        /*
-         * Configure the power management controller to trigger PMU
-         * interrupts when low
-         */
-        pmc_ctrl = readl(pmc + PMC_CTRL);
-        writel(pmc_ctrl | PMC_CTRL_INTR_LOW, pmc + PMC_CTRL);
-
         i2c_register_board_info(3, harmony_regulators, 1);
 
         return 0;
diff --git a/arch/arm/mach-tegra/board-harmony.c b/arch/arm/mach-tegra/board-harmony.c
index 789bdc9e8f9..c00aadb01e0 100644
--- a/arch/arm/mach-tegra/board-harmony.c
+++ b/arch/arm/mach-tegra/board-harmony.c
@@ -101,7 +101,6 @@ static struct wm8903_platform_data harmony_wm8903_pdata = {
 static struct i2c_board_info __initdata wm8903_board_info = {
         I2C_BOARD_INFO("wm8903", 0x1a),
         .platform_data = &harmony_wm8903_pdata,
-        .irq = TEGRA_GPIO_TO_IRQ(TEGRA_GPIO_CDC_IRQ),
 };
 
 static void __init harmony_i2c_init(void)
@@ -111,6 +110,7 @@ static void __init harmony_i2c_init(void)
         platform_device_register(&tegra_i2c_device3);
         platform_device_register(&tegra_i2c_device4);
 
+        wm8903_board_info.irq = gpio_to_irq(TEGRA_GPIO_CDC_IRQ);
         i2c_register_board_info(0, &wm8903_board_info, 1);
 }
 
diff --git a/arch/arm/mach-tegra/board-seaboard.c b/arch/arm/mach-tegra/board-seaboard.c
index ebac65f5251..d669847f048 100644
--- a/arch/arm/mach-tegra/board-seaboard.c
+++ b/arch/arm/mach-tegra/board-seaboard.c
@@ -159,7 +159,6 @@ static struct platform_device *seaboard_devices[] __initdata = {
 
 static struct i2c_board_info __initdata isl29018_device = {
         I2C_BOARD_INFO("isl29018", 0x44),
-        .irq = TEGRA_GPIO_TO_IRQ(TEGRA_GPIO_ISL29018_IRQ),
 };
 
 static struct i2c_board_info __initdata adt7461_device = {
@@ -183,7 +182,6 @@ static struct wm8903_platform_data wm8903_pdata = {
 static struct i2c_board_info __initdata wm8903_device = {
         I2C_BOARD_INFO("wm8903", 0x1a),
         .platform_data = &wm8903_pdata,
-        .irq = TEGRA_GPIO_TO_IRQ(TEGRA_GPIO_CDC_IRQ),
 };
 
 static int seaboard_ehci_init(void)
@@ -214,7 +212,10 @@ static void __init seaboard_i2c_init(void)
         gpio_request(TEGRA_GPIO_ISL29018_IRQ, "isl29018");
         gpio_direction_input(TEGRA_GPIO_ISL29018_IRQ);
 
+        isl29018_device.irq = gpio_to_irq(TEGRA_GPIO_ISL29018_IRQ);
         i2c_register_board_info(0, &isl29018_device, 1);
+
+        wm8903_device.irq = gpio_to_irq(TEGRA_GPIO_CDC_IRQ);
         i2c_register_board_info(0, &wm8903_device, 1);
 
         i2c_register_board_info(3, &adt7461_device, 1);
diff --git a/arch/arm/mach-tegra/clock.c b/arch/arm/mach-tegra/clock.c
index 8337068a4ab..8dad8d18cb4 100644
--- a/arch/arm/mach-tegra/clock.c
+++ b/arch/arm/mach-tegra/clock.c
@@ -399,6 +399,28 @@ void tegra_periph_reset_assert(struct clk *c)
 }
 EXPORT_SYMBOL(tegra_periph_reset_assert);
 
+/* Several extended clock configuration bits (e.g., clock routing, clock
+ * phase control) are included in PLL and peripheral clock source
+ * registers. */
+int tegra_clk_cfg_ex(struct clk *c, enum tegra_clk_ex_param p, u32 setting)
+{
+        int ret = 0;
+        unsigned long flags;
+
+        spin_lock_irqsave(&c->spinlock, flags);
+
+        if (!c->ops || !c->ops->clk_cfg_ex) {
+                ret = -ENOSYS;
+                goto out;
+        }
+        ret = c->ops->clk_cfg_ex(c, p, setting);
+
+out:
+        spin_unlock_irqrestore(&c->spinlock, flags);
+
+        return ret;
+}
+
 #ifdef CONFIG_DEBUG_FS
 
 static int __clk_lock_all_spinlocks(void)
diff --git a/arch/arm/mach-tegra/clock.h b/arch/arm/mach-tegra/clock.h
index 5c44106616c..bc300657deb 100644
--- a/arch/arm/mach-tegra/clock.h
+++ b/arch/arm/mach-tegra/clock.h
@@ -24,6 +24,8 @@
 #include <linux/list.h>
 #include <linux/spinlock.h>
 
+#include <mach/clk.h>
+
 #define DIV_BUS                 (1 << 0)
 #define DIV_U71                 (1 << 1)
 #define DIV_U71_FIXED           (1 << 2)
@@ -39,7 +41,16 @@
 #define PERIPH_MANUAL_RESET     (1 << 12)
 #define PLL_ALT_MISC_REG        (1 << 13)
 #define PLLU                    (1 << 14)
+#define PLLX                    (1 << 15)
+#define MUX_PWM                 (1 << 16)
+#define MUX8                    (1 << 17)
+#define DIV_U71_UART            (1 << 18)
+#define MUX_CLK_OUT             (1 << 19)
+#define PLLM                    (1 << 20)
+#define DIV_U71_INT             (1 << 21)
+#define DIV_U71_IDLE            (1 << 22)
 #define ENABLE_ON_INIT          (1 << 28)
+#define PERIPH_ON_APB           (1 << 29)
 
 struct clk;
 
@@ -65,6 +76,8 @@ struct clk_ops {
         int             (*set_rate)(struct clk *, unsigned long);
         long            (*round_rate)(struct clk *, unsigned long);
         void            (*reset)(struct clk *, bool);
+        int             (*clk_cfg_ex)(struct clk *,
+                                enum tegra_clk_ex_param, u32);
 };
 
 enum clk_state {
@@ -114,6 +127,7 @@ struct clk {
                         unsigned long                   vco_max;
                         const struct clk_pll_freq_table *freq_table;
                         int                             lock_delay;
+                        unsigned long                   fixed_rate;
                 } pll;
                 struct {
                         u32                             sel;
@@ -146,6 +160,7 @@ struct tegra_clk_init_table {
 };
 
 void tegra2_init_clocks(void);
+void tegra30_init_clocks(void);
 void clk_init(struct clk *clk);
 struct clk *tegra_get_clock_by_name(const char *name);
 int clk_reparent(struct clk *c, struct clk *parent);
diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c
index a2eb90169ae..2f86fcca64a 100644
--- a/arch/arm/mach-tegra/common.c
+++ b/arch/arm/mach-tegra/common.c
@@ -27,11 +27,28 @@
 #include <asm/hardware/gic.h>
 
 #include <mach/iomap.h>
-#include <mach/system.h>
 
 #include "board.h"
 #include "clock.h"
 #include "fuse.h"
+#include "pmc.h"
+
+/*
+ * Storage for debug-macro.S's state.
+ *
+ * This must be in .data not .bss so that it gets initialized each time the
+ * kernel is loaded. The data is declared here rather than debug-macro.S so
+ * that multiple inclusions of debug-macro.S point at the same data.
+ */
+#define TEGRA_DEBUG_UART_OFFSET (TEGRA_DEBUG_UART_BASE & 0xFFFF)
+u32 tegra_uart_config[3] = {
+        /* Debug UART initialization required */
+        1,
+        /* Debug UART physical address */
+        (u32)(IO_APB_PHYS + TEGRA_DEBUG_UART_OFFSET),
+        /* Debug UART virtual address */
+        (u32)(IO_APB_VIRT + TEGRA_DEBUG_UART_OFFSET),
+};
 
 #ifdef CONFIG_OF
 static const struct of_device_id tegra_dt_irq_match[] __initconst = {
@@ -100,11 +117,14 @@ void __init tegra20_init_early(void)
         tegra2_init_clocks();
         tegra_clk_init_from_table(tegra20_clk_init_table);
         tegra_init_cache(0x331, 0x441);
+        tegra_pmc_init();
 }
 #endif
 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
 void __init tegra30_init_early(void)
 {
+        tegra30_init_clocks();
         tegra_init_cache(0x441, 0x551);
+        tegra_pmc_init();
 }
 #endif
diff --git a/arch/arm/mach-tegra/cpuidle.c b/arch/arm/mach-tegra/cpuidle.c
new file mode 100644
index 00000000000..d83a8c0296f
--- /dev/null
+++ b/arch/arm/mach-tegra/cpuidle.c
@@ -0,0 +1,107 @@
+/*
+ * arch/arm/mach-tegra/cpuidle.c
+ *
+ * CPU idle driver for Tegra CPUs
+ *
+ * Copyright (c) 2010-2012, NVIDIA Corporation.
+ * Copyright (c) 2011 Google, Inc.
+ * Author: Colin Cross <ccross@android.com>
+ *         Gary King <gking@nvidia.com>
+ *
+ * Rework for 3.3 by Peter De Schrijver <pdeschrijver@nvidia.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/cpu.h>
+#include <linux/cpuidle.h>
+#include <linux/hrtimer.h>
+
+#include <mach/iomap.h>
+
+extern void tegra_cpu_wfi(void);
+
+static int tegra_idle_enter_lp3(struct cpuidle_device *dev,
+                                struct cpuidle_driver *drv, int index);
+
+struct cpuidle_driver tegra_idle_driver = {
+        .name = "tegra_idle",
+        .owner = THIS_MODULE,
+        .state_count = 1,
+        .states = {
+                [0] = {
+                        .enter                  = tegra_idle_enter_lp3,
+                        .exit_latency           = 10,
+                        .target_residency       = 10,
+                        .power_usage            = 600,
+                        .flags                  = CPUIDLE_FLAG_TIME_VALID,
+                        .name                   = "LP3",
+                        .desc                   = "CPU flow-controlled",
+                },
+        },
+};
+
+static DEFINE_PER_CPU(struct cpuidle_device, tegra_idle_device);
+
+static int tegra_idle_enter_lp3(struct cpuidle_device *dev,
+        struct cpuidle_driver *drv, int index)
+{
+        ktime_t enter, exit;
+        s64 us;
+
+        local_irq_disable();
+        local_fiq_disable();
+
+        enter = ktime_get();
+
+        tegra_cpu_wfi();
+
+        exit = ktime_sub(ktime_get(), enter);
+        us = ktime_to_us(exit);
+
+        local_fiq_enable();
+        local_irq_enable();
+
+        dev->last_residency = us;
+
+        return index;
+}
+
+static int __init tegra_cpuidle_init(void)
+{
+        int ret;
+        unsigned int cpu;
+        struct cpuidle_device *dev;
+        struct cpuidle_driver *drv = &tegra_idle_driver;
+
+        ret = cpuidle_register_driver(&tegra_idle_driver);
+        if (ret) {
+                pr_err("CPUidle driver registration failed\n");
+                return ret;
+        }
+
+        for_each_possible_cpu(cpu) {
+                dev = &per_cpu(tegra_idle_device, cpu);
+                dev->cpu = cpu;
+
+                dev->state_count = drv->state_count;
+                ret = cpuidle_register_device(dev);
+                if (ret) {
+                        pr_err("CPU%u: CPUidle device registration failed\n",
+                                cpu);
+                        return ret;
+                }
+        }
+        return 0;
+}
+device_initcall(tegra_cpuidle_init);
diff --git a/arch/arm/mach-tegra/dma.c b/arch/arm/mach-tegra/dma.c
index c0cf967e47d..abea4f6e2dd 100644
--- a/arch/arm/mach-tegra/dma.c
+++ b/arch/arm/mach-tegra/dma.c
@@ -33,6 +33,8 @@
 #include <mach/iomap.h>
 #include <mach/suspend.h>
 
+#include "apbio.h"
+
 #define APB_DMA_GEN                             0x000
 #define GEN_ENABLE                              (1<<31)
 
@@ -50,8 +52,6 @@
 #define CSR_ONCE                                (1<<27)
 #define CSR_FLOW                                (1<<21)
 #define CSR_REQ_SEL_SHIFT                       16
-#define CSR_REQ_SEL_MASK                        (0x1F<<CSR_REQ_SEL_SHIFT)
-#define CSR_REQ_SEL_INVALID                     (31<<CSR_REQ_SEL_SHIFT)
 #define CSR_WCOUNT_SHIFT                        2
 #define CSR_WCOUNT_MASK                         0xFFFC
 
@@ -133,6 +133,7 @@ struct tegra_dma_channel {
 
 static bool tegra_dma_initialized;
 static DEFINE_MUTEX(tegra_dma_lock);
+static DEFINE_SPINLOCK(enable_lock);
 
 static DECLARE_BITMAP(channel_usage, NV_DMA_MAX_CHANNELS);
 static struct tegra_dma_channel dma_channels[NV_DMA_MAX_CHANNELS];
@@ -180,36 +181,94 @@ static void tegra_dma_stop(struct tegra_dma_channel *ch)
 
 static int tegra_dma_cancel(struct tegra_dma_channel *ch)
 {
-        u32 csr;
         unsigned long irq_flags;
 
         spin_lock_irqsave(&ch->lock, irq_flags);
         while (!list_empty(&ch->list))
                 list_del(ch->list.next);
 
-        csr = readl(ch->addr + APB_DMA_CHAN_CSR);
-        csr &= ~CSR_REQ_SEL_MASK;
-        csr |= CSR_REQ_SEL_INVALID;
-        writel(csr, ch->addr + APB_DMA_CHAN_CSR);
-
         tegra_dma_stop(ch);
 
         spin_unlock_irqrestore(&ch->lock, irq_flags);
         return 0;
 }
 
+static unsigned int get_channel_status(struct tegra_dma_channel *ch,
+                        struct tegra_dma_req *req, bool is_stop_dma)
+{
+        void __iomem *addr = IO_ADDRESS(TEGRA_APB_DMA_BASE);
+        unsigned int status;
+
+        if (is_stop_dma) {
+                /*
+                 * STOP the DMA and get the transfer count.
+                 * Getting the transfer count is tricky.
+                 *  - Globally disable DMA on all channels
+                 *  - Read the channel's status register to know the number
+                 *    of pending bytes to be transfered.
+                 *  - Stop the dma channel
+                 *  - Globally re-enable DMA to resume other transfers
+                 */
+                spin_lock(&enable_lock);
+                writel(0, addr + APB_DMA_GEN);
+                udelay(20);
+                status = readl(ch->addr + APB_DMA_CHAN_STA);
+                tegra_dma_stop(ch);
+                writel(GEN_ENABLE, addr + APB_DMA_GEN);
+                spin_unlock(&enable_lock);
+                if (status & STA_ISE_EOC) {
+                        pr_err("Got Dma Int here clearing");
+                        writel(status, ch->addr + APB_DMA_CHAN_STA);
+                }
+                req->status = TEGRA_DMA_REQ_ERROR_ABORTED;
+        } else {
+                status = readl(ch->addr + APB_DMA_CHAN_STA);
+        }
+        return status;
+}
+
+/* should be called with the channel lock held */
+static unsigned int dma_active_count(struct tegra_dma_channel *ch,
+        struct tegra_dma_req *req, unsigned int status)
+{
+        unsigned int to_transfer;
+        unsigned int req_transfer_count;
+        unsigned int bytes_transferred;
+
+        to_transfer = ((status & STA_COUNT_MASK) >> STA_COUNT_SHIFT) + 1;
+        req_transfer_count = ch->req_transfer_count + 1;
+        bytes_transferred = req_transfer_count;
+        if (status & STA_BUSY)
+                bytes_transferred -= to_transfer;
+        /*
+         * In continuous transfer mode, DMA only tracks the count of the
+         * half DMA buffer. So, if the DMA already finished half the DMA
+         * then add the half buffer to the completed count.
+         */
+        if (ch->mode & TEGRA_DMA_MODE_CONTINOUS) {
+                if (req->buffer_status == TEGRA_DMA_REQ_BUF_STATUS_HALF_FULL)
+                        bytes_transferred += req_transfer_count;
+                if (status & STA_ISE_EOC)
+                        bytes_transferred += req_transfer_count;
+        }
+        bytes_transferred *= 4;
+        return bytes_transferred;
+}
+
 int tegra_dma_dequeue_req(struct tegra_dma_channel *ch,
         struct tegra_dma_req *_req)
 {
-        unsigned int csr;
         unsigned int status;
         struct tegra_dma_req *req = NULL;
         int found = 0;
         unsigned long irq_flags;
-        int to_transfer;
-        int req_transfer_count;
+        int stop = 0;
 
         spin_lock_irqsave(&ch->lock, irq_flags);
+
+        if (list_entry(ch->list.next, struct tegra_dma_req, node) == _req)
+                stop = 1;
+
         list_for_each_entry(req, &ch->list, node) {
                 if (req == _req) {
                         list_del(&req->node);
@@ -222,47 +281,12 @@ int tegra_dma_dequeue_req(struct tegra_dma_channel *ch,
                 return 0;
         }
 
-        /* STOP the DMA and get the transfer count.
-         * Getting the transfer count is tricky.
-         *  - Change the source selector to invalid to stop the DMA from
-         *    FIFO to memory.
-         *  - Read the status register to know the number of pending
-         *    bytes to be transferred.
-         *  - Finally stop or program the DMA to the next buffer in the
-         *    list.
-         */
-        csr = readl(ch->addr + APB_DMA_CHAN_CSR);
-        csr &= ~CSR_REQ_SEL_MASK;
-        csr |= CSR_REQ_SEL_INVALID;
-        writel(csr, ch->addr + APB_DMA_CHAN_CSR);
-
-        /* Get the transfer count */
-        status = readl(ch->addr + APB_DMA_CHAN_STA);
-        to_transfer = (status & STA_COUNT_MASK) >> STA_COUNT_SHIFT;
-        req_transfer_count = ch->req_transfer_count;
-        req_transfer_count += 1;
-        to_transfer += 1;
-
-        req->bytes_transferred = req_transfer_count;
-
-        if (status & STA_BUSY)
-                req->bytes_transferred -= to_transfer;
-
-        /* In continuous transfer mode, DMA only tracks the count of the
-         * half DMA buffer. So, if the DMA already finished half the DMA
-         * then add the half buffer to the completed count.
-         *
-         *      FIXME: There can be a race here. What if the req to
-         *      dequue happens at the same time as the DMA just moved to
-         *      the new buffer and SW didn't yet received the interrupt?
-         */
-        if (ch->mode & TEGRA_DMA_MODE_CONTINOUS)
-                if (req->buffer_status == TEGRA_DMA_REQ_BUF_STATUS_HALF_FULL)
-                        req->bytes_transferred += req_transfer_count;
+        if (!stop)
+                goto skip_stop_dma;
 
-        req->bytes_transferred *= 4;
+        status = get_channel_status(ch, req, true);
+        req->bytes_transferred = dma_active_count(ch, req, status);
 
-        tegra_dma_stop(ch);
         if (!list_empty(&ch->list)) {
                 /* if the list is not empty, queue the next request */
                 struct tegra_dma_req *next_req;
@@ -270,6 +294,8 @@ int tegra_dma_dequeue_req(struct tegra_dma_channel *ch,
                         typeof(*next_req), node);
                 tegra_dma_update_hw(ch, next_req);
         }
+
+skip_stop_dma:
         req->status = -TEGRA_DMA_REQ_ERROR_ABORTED;
 
         spin_unlock_irqrestore(&ch->lock, irq_flags);
@@ -357,7 +383,7 @@ struct tegra_dma_channel *tegra_dma_allocate_channel(int mode)
         int channel;
         struct tegra_dma_channel *ch = NULL;
 
-        if (WARN_ON(!tegra_dma_initialized))
+        if (!tegra_dma_initialized)
                 return NULL;
 
         mutex_lock(&tegra_dma_lock);
diff --git a/arch/arm/mach-tegra/flowctrl.h b/arch/arm/mach-tegra/flowctrl.h
new file mode 100644
index 00000000000..74c6efbe52f
--- /dev/null
+++ b/arch/arm/mach-tegra/flowctrl.h
@@ -0,0 +1,37 @@
+/*
+ * arch/arm/mach-tegra/flowctrl.h
+ *
+ * functions and macros to control the flowcontroller
+ *
+ * Copyright (c) 2010-2012, NVIDIA Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef __MACH_TEGRA_FLOWCTRL_H
+#define __MACH_TEGRA_FLOWCTRL_H
+
+#define FLOW_CTRL_HALT_CPU0_EVENTS      0x0
+#define FLOW_CTRL_WAITEVENT             (2 << 29)
+#define FLOW_CTRL_WAIT_FOR_INTERRUPT    (4 << 29)
+#define FLOW_CTRL_JTAG_RESUME           (1 << 28)
+#define FLOW_CTRL_HALT_CPU_IRQ          (1 << 10)
+#define FLOW_CTRL_HALT_CPU_FIQ          (1 << 8)
+#define FLOW_CTRL_CPU0_CSR              0x8
+#define FLOW_CTRL_CSR_INTR_FLAG         (1 << 15)
+#define FLOW_CTRL_CSR_EVENT_FLAG        (1 << 14)
+#define FLOW_CTRL_CSR_ENABLE            (1 << 0)
+#define FLOW_CTRL_HALT_CPU1_EVENTS      0x14
+#define FLOW_CTRL_CPU1_CSR              0x18
+
+#endif
diff --git a/arch/arm/mach-tegra/fuse.c b/arch/arm/mach-tegra/fuse.c
index ea49bd93c6b..c1afb273876 100644
--- a/arch/arm/mach-tegra/fuse.c
+++ b/arch/arm/mach-tegra/fuse.c
@@ -19,25 +19,75 @@
 
 #include <linux/kernel.h>
 #include <linux/io.h>
-#include <linux/module.h>
+#include <linux/export.h>
 
 #include <mach/iomap.h>
 
 #include "fuse.h"
+#include "apbio.h"
 
 #define FUSE_UID_LOW            0x108
 #define FUSE_UID_HIGH           0x10c
 #define FUSE_SKU_INFO           0x110
 #define FUSE_SPARE_BIT          0x200
 
-static inline u32 fuse_readl(unsigned long offset)
+int tegra_sku_id;
+int tegra_cpu_process_id;
+int tegra_core_process_id;
+enum tegra_revision tegra_revision;
+
+/* The BCT to use at boot is specified by board straps that can be read
+ * through a APB misc register and decoded. 2 bits, i.e. 4 possible BCTs.
+ */
+int tegra_bct_strapping;
+
+#define STRAP_OPT 0x008
+#define GMI_AD0 (1 << 4)
+#define GMI_AD1 (1 << 5)
+#define RAM_ID_MASK (GMI_AD0 | GMI_AD1)
+#define RAM_CODE_SHIFT 4
+
+static const char *tegra_revision_name[TEGRA_REVISION_MAX] = {
+        [TEGRA_REVISION_UNKNOWN] = "unknown",
+        [TEGRA_REVISION_A01]     = "A01",
+        [TEGRA_REVISION_A02]     = "A02",
+        [TEGRA_REVISION_A03]     = "A03",
+        [TEGRA_REVISION_A03p]    = "A03 prime",
+        [TEGRA_REVISION_A04]     = "A04",
+};
+
+static inline u32 tegra_fuse_readl(unsigned long offset)
+{
+        return tegra_apb_readl(TEGRA_FUSE_BASE + offset);
+}
+
+static inline bool get_spare_fuse(int bit)
 {
-        return readl(IO_TO_VIRT(TEGRA_FUSE_BASE + offset));
+        return tegra_fuse_readl(FUSE_SPARE_BIT + bit * 4);
 }
 
-static inline void fuse_writel(u32 value, unsigned long offset)
+static enum tegra_revision tegra_get_revision(void)
 {
-        writel(value, IO_TO_VIRT(TEGRA_FUSE_BASE + offset));
+        void __iomem *chip_id = IO_ADDRESS(TEGRA_APB_MISC_BASE) + 0x804;
+        u32 id = readl(chip_id);
+        u32 minor_rev = (id >> 16) & 0xf;
+        u32 chipid = (id >> 8) & 0xff;
+
+        switch (minor_rev) {
+        case 1:
+                return TEGRA_REVISION_A01;
+        case 2:
+                return TEGRA_REVISION_A02;
+        case 3:
+                if (chipid == 0x20 && (get_spare_fuse(18) || get_spare_fuse(19)))
+                        return TEGRA_REVISION_A03p;
+                else
+                        return TEGRA_REVISION_A03;
+        case 4:
+                return TEGRA_REVISION_A04;
+        default:
+                return TEGRA_REVISION_UNKNOWN;
+        }
 }
 
 void tegra_init_fuse(void)
@@ -46,41 +96,32 @@ void tegra_init_fuse(void)
         reg |= 1 << 28;
         writel(reg, IO_TO_VIRT(TEGRA_CLK_RESET_BASE + 0x48));
 
-        pr_info("Tegra SKU: %d CPU Process: %d Core Process: %d\n",
-                tegra_sku_id(), tegra_cpu_process_id(),
-                tegra_core_process_id());
+        reg = tegra_fuse_readl(FUSE_SKU_INFO);
+        tegra_sku_id = reg & 0xFF;
+
+        reg = tegra_fuse_readl(FUSE_SPARE_BIT);
+        tegra_cpu_process_id = (reg >> 6) & 3;
+
+        reg = tegra_fuse_readl(FUSE_SPARE_BIT);
+        tegra_core_process_id = (reg >> 12) & 3;
+
+        reg = tegra_apb_readl(TEGRA_APB_MISC_BASE + STRAP_OPT);
+        tegra_bct_strapping = (reg & RAM_ID_MASK) >> RAM_CODE_SHIFT;
+
+        tegra_revision = tegra_get_revision();
+
+        pr_info("Tegra Revision: %s SKU: %d CPU Process: %d Core Process: %d\n",
+                tegra_revision_name[tegra_get_revision()],
+                tegra_sku_id, tegra_cpu_process_id,
+                tegra_core_process_id);
 }
 
 unsigned long long tegra_chip_uid(void)
 {
         unsigned long long lo, hi;
 
-        lo = fuse_readl(FUSE_UID_LOW);
-        hi = fuse_readl(FUSE_UID_HIGH);
+        lo = tegra_fuse_readl(FUSE_UID_LOW);
+        hi = tegra_fuse_readl(FUSE_UID_HIGH);
         return (hi << 32ull) | lo;
 }
 EXPORT_SYMBOL(tegra_chip_uid);
-
-int tegra_sku_id(void)
-{
-        int sku_id;
-        u32 reg = fuse_readl(FUSE_SKU_INFO);
-        sku_id = reg & 0xFF;
-        return sku_id;
-}
-
-int tegra_cpu_process_id(void)
-{
-        int cpu_process_id;
-        u32 reg = fuse_readl(FUSE_SPARE_BIT);
-        cpu_process_id = (reg >> 6) & 3;
-        return cpu_process_id;
-}
-
-int tegra_core_process_id(void)
-{
-        int core_process_id;
-        u32 reg = fuse_readl(FUSE_SPARE_BIT);
-        core_process_id = (reg >> 12) & 3;
-        return core_process_id;
-}
diff --git a/arch/arm/mach-tegra/fuse.h b/arch/arm/mach-tegra/fuse.h
index 584b2e27dbd..d65d2abf803 100644
--- a/arch/arm/mach-tegra/fuse.h
+++ b/arch/arm/mach-tegra/fuse.h
@@ -1,6 +1,4 @@
 /*
- * arch/arm/mach-tegra/fuse.c
- *
  * Copyright (C) 2010 Google, Inc.
  *
  * Author:
@@ -17,8 +15,34 @@
  *
  */
 
+#ifndef __MACH_TEGRA_FUSE_H
+#define __MACH_TEGRA_FUSE_H
+
+enum tegra_revision {
+        TEGRA_REVISION_UNKNOWN = 0,
+        TEGRA_REVISION_A01,
+        TEGRA_REVISION_A02,
+        TEGRA_REVISION_A03,
+        TEGRA_REVISION_A03p,
+        TEGRA_REVISION_A04,
+        TEGRA_REVISION_MAX,
+};
+
+#define SKU_ID_T20      8
+#define SKU_ID_T25SE    20
+#define SKU_ID_AP25     23
+#define SKU_ID_T25      24
+#define SKU_ID_AP25E    27
+#define SKU_ID_T25E     28
+
+extern int tegra_sku_id;
+extern int tegra_cpu_process_id;
+extern int tegra_core_process_id;
+extern enum tegra_revision tegra_revision;
+
+extern int tegra_bct_strapping;
+
 unsigned long long tegra_chip_uid(void);
-int tegra_sku_id(void);
-int tegra_cpu_process_id(void);
-int tegra_core_process_id(void);
 void tegra_init_fuse(void);
+
+#endif
diff --git a/arch/arm/mach-tegra/include/mach/clk.h b/arch/arm/mach-tegra/include/mach/clk.h
index fc3ecb66de0..d97e403303a 100644
--- a/arch/arm/mach-tegra/include/mach/clk.h
+++ b/arch/arm/mach-tegra/include/mach/clk.h
@@ -22,10 +22,20 @@
 
 struct clk;
 
+enum tegra_clk_ex_param {
+        TEGRA_CLK_VI_INP_SEL,
+        TEGRA_CLK_DTV_INVERT,
+        TEGRA_CLK_NAND_PAD_DIV2_ENB,
+        TEGRA_CLK_PLLD_CSI_OUT_ENB,
+        TEGRA_CLK_PLLD_DSI_OUT_ENB,
+        TEGRA_CLK_PLLD_MIPI_MUX_SEL,
+};
+
 void tegra_periph_reset_deassert(struct clk *c);
 void tegra_periph_reset_assert(struct clk *c);
 
 unsigned long clk_get_rate_all_locked(struct clk *c);
 void tegra2_sdmmc_tap_delay(struct clk *c, int delay);
+int tegra_clk_cfg_ex(struct clk *c, enum tegra_clk_ex_param p, u32 setting);
 
 #endif
diff --git a/arch/arm/mach-tegra/include/mach/debug-macro.S b/arch/arm/mach-tegra/include/mach/debug-macro.S
index 619abc63aee..90069abd37b 100644
--- a/arch/arm/mach-tegra/include/mach/debug-macro.S
+++ b/arch/arm/mach-tegra/include/mach/debug-macro.S
@@ -1,11 +1,17 @@
 /*
  * arch/arm/mach-tegra/include/mach/debug-macro.S
  *
- * Copyright (C) 2010 Google, Inc.
+ * Copyright (C) 2010,2011 Google, Inc.
+ * Copyright (C) 2011-2012 NVIDIA CORPORATION. All Rights Reserved.
  *
  * Author:
  *      Colin Cross <ccross@google.com>
  *      Erik Gilling <konkers@google.com>
+ *      Doug Anderson <dianders@chromium.org>
+ *      Stephen Warren <swarren@nvidia.com>
+ *
+ * Portions based on mach-omap2's debug-macro.S
+ * Copyright (C) 1994-1999 Russell King
  *
  * This software is licensed under the terms of the GNU General Public
  * License version 2, as published by the Free Software Foundation, and
@@ -18,18 +24,78 @@
  *
  */
 
+#include <linux/serial_reg.h>
+
 #include <mach/io.h>
 #include <mach/iomap.h>
+#include <mach/irammap.h>
+
+                .macro  addruart, rp, rv, tmp
+                adr     \rp, 99f                @ actual addr of 99f
+                ldr     \rv, [\rp]              @ linked addr is stored there
+                sub     \rv, \rv, \rp           @ offset between the two
+                ldr     \rp, [\rp, #4]          @ linked tegra_uart_config
+                sub     \tmp, \rp, \rv          @ actual tegra_uart_config
+                ldr     \rp, [\tmp]             @ Load tegra_uart_config
+                cmp     \rp, #1                 @ needs intitialization?
+                bne     100f                    @ no; go load the addresses
+                mov     \rv, #0                 @ yes; record init is done
+                str     \rv, [\tmp]
+                mov     \rp, #TEGRA_IRAM_BASE   @ See if cookie is in IRAM
+                ldr     \rv, [\rp, #TEGRA_IRAM_DEBUG_UART_OFFSET]
+                movw    \rp, #TEGRA_IRAM_DEBUG_UART_COOKIE & 0xffff
+                movt    \rp, #TEGRA_IRAM_DEBUG_UART_COOKIE >> 16
+                cmp     \rv, \rp                @ Cookie present?
+                bne     100f                    @ No, use default UART
+                mov     \rp, #TEGRA_IRAM_BASE   @ Load UART address from IRAM
+                ldr     \rv, [\rp, #TEGRA_IRAM_DEBUG_UART_OFFSET + 4]
+                str     \rv, [\tmp, #4]         @ Store in tegra_uart_phys
+                sub     \rv, \rv, #IO_APB_PHYS  @ Calculate virt address
+                add     \rv, \rv, #IO_APB_VIRT
+                str     \rv, [\tmp, #8]         @ Store in tegra_uart_virt
+                b       100f
+
+                .align
+99:             .word   .
+                .word   tegra_uart_config
+                .ltorg
+
+100:            ldr     \rp, [\tmp, #4]         @ Load tegra_uart_phys
+                ldr     \rv, [\tmp, #8]         @ Load tegra_uart_virt
+                .endm
+
+#define UART_SHIFT 2
+
+/*
+ * Code below is swiped from <asm/hardware/debug-8250.S>, but add an extra
+ * check to make sure that we aren't in the CONFIG_TEGRA_DEBUG_UART_NONE case.
+ * We use the fact that all 5 valid UART addresses all have something in the
+ * 2nd-to-lowest byte.
+ */
 
-        .macro  addruart, rp, rv, tmp
-        ldr     \rp, =IO_APB_PHYS       @ physical
-        ldr     \rv, =IO_APB_VIRT        @ virtual
-        orr     \rp, \rp, #(TEGRA_DEBUG_UART_BASE & 0xFF)
-        orr     \rp, \rp, #(TEGRA_DEBUG_UART_BASE & 0xFF00)
-        orr     \rv, \rv, #(TEGRA_DEBUG_UART_BASE & 0xFF)
-        orr     \rv, \rv, #(TEGRA_DEBUG_UART_BASE & 0xFF00)
-        .endm
+                .macro  senduart, rd, rx
+                tst     \rx, #0x0000ff00
+                strneb  \rd, [\rx, #UART_TX << UART_SHIFT]
+1001:
+                .endm
 
-#define UART_SHIFT      2
-#include <asm/hardware/debug-8250.S>
+                .macro  busyuart, rd, rx
+                tst     \rx, #0x0000ff00
+                beq     1002f
+1001:           ldrb    \rd, [\rx, #UART_LSR << UART_SHIFT]
+                and     \rd, \rd, #UART_LSR_TEMT | UART_LSR_THRE
+                teq     \rd, #UART_LSR_TEMT | UART_LSR_THRE
+                bne     1001b
+1002:
+                .endm
 
+                .macro  waituart, rd, rx
+#ifdef FLOW_CONTROL
+                tst     \rx, #0x0000ff00
+                beq     1002f
+1001:           ldrb    \rd, [\rx, #UART_MSR << UART_SHIFT]
+                tst     \rd, #UART_MSR_CTS
+                beq     1001b
+1002:
+#endif
+                .endm
diff --git a/arch/arm/mach-tegra/include/mach/entry-macro.S b/arch/arm/mach-tegra/include/mach/entry-macro.S
deleted file mode 100644
index e577cfe27e7..00000000000
--- a/arch/arm/mach-tegra/include/mach/entry-macro.S
+++ /dev/null
@@ -1,20 +0,0 @@
-/* arch/arm/mach-tegra/include/mach/entry-macro.S
- *
- * Copyright (C) 2009 Palm, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-        .macro  disable_fiq
-        .endm
-
-        .macro  arch_ret_to_user, tmp1, tmp2
-        .endm
diff --git a/arch/arm/mach-tegra/include/mach/gpio-tegra.h b/arch/arm/mach-tegra/include/mach/gpio-tegra.h
index 87d37fdf508..6140820555e 100644
--- a/arch/arm/mach-tegra/include/mach/gpio-tegra.h
+++ b/arch/arm/mach-tegra/include/mach/gpio-tegra.h
@@ -25,8 +25,6 @@
 
 #define TEGRA_NR_GPIOS          INT_GPIO_NR
 
-#define TEGRA_GPIO_TO_IRQ(gpio) (INT_GPIO_BASE + (gpio))
-
 struct tegra_gpio_table {
         int     gpio;   /* GPIO number */
         bool    enable; /* Enable for GPIO at init? */
diff --git a/arch/arm/mach-tegra/include/mach/iomap.h b/arch/arm/mach-tegra/include/mach/iomap.h
index 19dec3ac085..67644c905d8 100644
--- a/arch/arm/mach-tegra/include/mach/iomap.h
+++ b/arch/arm/mach-tegra/include/mach/iomap.h
@@ -74,6 +74,9 @@
 #define TEGRA_QUATERNARY_ICTLR_BASE     0x60004300
 #define TEGRA_QUATERNARY_ICTLR_SIZE     SZ_64
 
+#define TEGRA_QUINARY_ICTLR_BASE        0x60004400
+#define TEGRA_QUINARY_ICTLR_SIZE        SZ_64
+
 #define TEGRA_TMR1_BASE                 0x60005000
 #define TEGRA_TMR1_SIZE                 SZ_8
 
diff --git a/arch/arm/mach-tegra/include/mach/irammap.h b/arch/arm/mach-tegra/include/mach/irammap.h
new file mode 100644
index 00000000000..0cbe6326185
--- /dev/null
+++ b/arch/arm/mach-tegra/include/mach/irammap.h
@@ -0,0 +1,35 @@
+/*
+ * Copyright (c) 2012, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef __MACH_TEGRA_IRAMMAP_H
+#define __MACH_TEGRA_IRAMMAP_H
+
+#include <asm/sizes.h>
+
+/* The first 1K of IRAM is permanently reserved for the CPU reset handler */
+#define TEGRA_IRAM_RESET_HANDLER_OFFSET 0
+#define TEGRA_IRAM_RESET_HANDLER_SIZE   SZ_1K
+
+/*
+ * These locations are written to by uncompress.h, and read by debug-macro.S.
+ * The first word holds the cookie value if the data is valid. The second
+ * word holds the UART physical address.
+ */
+#define TEGRA_IRAM_DEBUG_UART_OFFSET    SZ_1K
+#define TEGRA_IRAM_DEBUG_UART_SIZE      8
+#define TEGRA_IRAM_DEBUG_UART_COOKIE    0x55415254
+
+#endif
diff --git a/arch/arm/mach-tegra/include/mach/irqs.h b/arch/arm/mach-tegra/include/mach/irqs.h
index a2146cd6867..aad1a2c1d71 100644
--- a/arch/arm/mach-tegra/include/mach/irqs.h
+++ b/arch/arm/mach-tegra/include/mach/irqs.h
@@ -165,11 +165,12 @@
 #define INT_QUAD_RES_30                 (INT_QUAD_BASE + 30)
 #define INT_QUAD_RES_31                 (INT_QUAD_BASE + 31)
 
-#define INT_MAIN_NR                     (INT_QUAD_BASE + 32 - INT_PRI_BASE)
-
+/* Tegra30 has 5 banks of 32 IRQs */
+#define INT_MAIN_NR                     (32 * 5)
 #define INT_GPIO_BASE                   (INT_PRI_BASE + INT_MAIN_NR)
 
-#define INT_GPIO_NR                     (28 * 8)
+/* Tegra30 has 8 banks of 32 GPIOs */
+#define INT_GPIO_NR                     (32 * 8)
 
 #define TEGRA_NR_IRQS                   (INT_GPIO_BASE + INT_GPIO_NR)
 
diff --git a/arch/arm/mach-tegra/include/mach/kbc.h b/arch/arm/mach-tegra/include/mach/kbc.h
index 20bb0545f99..a1302561293 100644
--- a/arch/arm/mach-tegra/include/mach/kbc.h
+++ b/arch/arm/mach-tegra/include/mach/kbc.h
@@ -24,20 +24,21 @@
 #include <linux/types.h>
 #include <linux/input/matrix_keypad.h>
 
-#ifdef CONFIG_ARCH_TEGRA_2x_SOC
 #define KBC_MAX_GPIO    24
 #define KBC_MAX_KPENT   8
-#else
-#define KBC_MAX_GPIO    20
-#define KBC_MAX_KPENT   7
-#endif
 
 #define KBC_MAX_ROW     16
 #define KBC_MAX_COL     8
 #define KBC_MAX_KEY     (KBC_MAX_ROW * KBC_MAX_COL)
 
+enum tegra_pin_type {
+        PIN_CFG_IGNORE,
+        PIN_CFG_COL,
+        PIN_CFG_ROW,
+};
+
 struct tegra_kbc_pin_cfg {
-        bool is_row;
+        enum tegra_pin_type type;
         unsigned char num;
 };
 
diff --git a/arch/arm/mach-tegra/include/mach/pinconf-tegra.h b/arch/arm/mach-tegra/include/mach/pinconf-tegra.h
new file mode 100644
index 00000000000..1f24d304921
--- /dev/null
+++ b/arch/arm/mach-tegra/include/mach/pinconf-tegra.h
@@ -0,0 +1,63 @@
+/*
+ * pinctrl configuration definitions for the NVIDIA Tegra pinmux
+ *
+ * Copyright (c) 2011, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ */
+
+#ifndef __PINCONF_TEGRA_H__
+#define __PINCONF_TEGRA_H__
+
+enum tegra_pinconf_param {
+        /* argument: tegra_pinconf_pull */
+        TEGRA_PINCONF_PARAM_PULL,
+        /* argument: tegra_pinconf_tristate */
+        TEGRA_PINCONF_PARAM_TRISTATE,
+        /* argument: Boolean */
+        TEGRA_PINCONF_PARAM_ENABLE_INPUT,
+        /* argument: Boolean */
+        TEGRA_PINCONF_PARAM_OPEN_DRAIN,
+        /* argument: Boolean */
+        TEGRA_PINCONF_PARAM_LOCK,
+        /* argument: Boolean */
+        TEGRA_PINCONF_PARAM_IORESET,
+        /* argument: Boolean */
+        TEGRA_PINCONF_PARAM_HIGH_SPEED_MODE,
+        /* argument: Boolean */
+        TEGRA_PINCONF_PARAM_SCHMITT,
+        /* argument: Boolean */
+        TEGRA_PINCONF_PARAM_LOW_POWER_MODE,
+        /* argument: Integer, range is HW-dependant */
+        TEGRA_PINCONF_PARAM_DRIVE_DOWN_STRENGTH,
+        /* argument: Integer, range is HW-dependant */
+        TEGRA_PINCONF_PARAM_DRIVE_UP_STRENGTH,
+        /* argument: Integer, range is HW-dependant */
+        TEGRA_PINCONF_PARAM_SLEW_RATE_FALLING,
+        /* argument: Integer, range is HW-dependant */
+        TEGRA_PINCONF_PARAM_SLEW_RATE_RISING,
+};
+
+enum tegra_pinconf_pull {
+        TEGRA_PINCONFIG_PULL_NONE,
+        TEGRA_PINCONFIG_PULL_DOWN,
+        TEGRA_PINCONFIG_PULL_UP,
+};
+
+enum tegra_pinconf_tristate {
+        TEGRA_PINCONFIG_DRIVEN,
+        TEGRA_PINCONFIG_TRISTATE,
+};
+
+#define TEGRA_PINCONF_PACK(_param_, _arg_) ((_param_) << 16 | (_arg_))
+#define TEGRA_PINCONF_UNPACK_PARAM(_conf_) ((_conf_) >> 16)
+#define TEGRA_PINCONF_UNPACK_ARG(_conf_) ((_conf_) & 0xffff)
+
+#endif
diff --git a/arch/arm/mach-tegra/include/mach/smmu.h b/arch/arm/mach-tegra/include/mach/smmu.h
new file mode 100644
index 00000000000..dad403a9cf0
--- /dev/null
+++ b/arch/arm/mach-tegra/include/mach/smmu.h
@@ -0,0 +1,63 @@
+/*
+ * IOMMU API for SMMU in Tegra30
+ *
+ * Copyright (c) 2012, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#ifndef MACH_SMMU_H
+#define MACH_SMMU_H
+
+enum smmu_hwgrp {
+        HWGRP_AFI,
+        HWGRP_AVPC,
+        HWGRP_DC,
+        HWGRP_DCB,
+        HWGRP_EPP,
+        HWGRP_G2,
+        HWGRP_HC,
+        HWGRP_HDA,
+        HWGRP_ISP,
+        HWGRP_MPE,
+        HWGRP_NV,
+        HWGRP_NV2,
+        HWGRP_PPCS,
+        HWGRP_SATA,
+        HWGRP_VDE,
+        HWGRP_VI,
+
+        HWGRP_COUNT,
+
+        HWGRP_END = ~0,
+};
+
+#define HWG_AFI         (1 << HWGRP_AFI)
+#define HWG_AVPC        (1 << HWGRP_AVPC)
+#define HWG_DC          (1 << HWGRP_DC)
+#define HWG_DCB         (1 << HWGRP_DCB)
+#define HWG_EPP         (1 << HWGRP_EPP)
+#define HWG_G2          (1 << HWGRP_G2)
+#define HWG_HC          (1 << HWGRP_HC)
+#define HWG_HDA         (1 << HWGRP_HDA)
+#define HWG_ISP         (1 << HWGRP_ISP)
+#define HWG_MPE         (1 << HWGRP_MPE)
+#define HWG_NV          (1 << HWGRP_NV)
+#define HWG_NV2         (1 << HWGRP_NV2)
+#define HWG_PPCS        (1 << HWGRP_PPCS)
+#define HWG_SATA        (1 << HWGRP_SATA)
+#define HWG_VDE         (1 << HWGRP_VDE)
+#define HWG_VI          (1 << HWGRP_VI)
+
+#endif  /* MACH_SMMU_H */
diff --git a/arch/arm/mach-tegra/include/mach/uncompress.h b/arch/arm/mach-tegra/include/mach/uncompress.h
index 4e8323770c7..5a440f315e5 100644
--- a/arch/arm/mach-tegra/include/mach/uncompress.h
+++ b/arch/arm/mach-tegra/include/mach/uncompress.h
@@ -2,10 +2,14 @@
  * arch/arm/mach-tegra/include/mach/uncompress.h
  *
  * Copyright (C) 2010 Google, Inc.
+ * Copyright (C) 2011 Google, Inc.
+ * Copyright (C) 2011-2012 NVIDIA CORPORATION. All Rights Reserved.
  *
  * Author:
  *      Colin Cross <ccross@google.com>
  *      Erik Gilling <konkers@google.com>
+ *      Doug Anderson <dianders@chromium.org>
+ *      Stephen Warren <swarren@nvidia.com>
  *
  * This software is licensed under the terms of the GNU General Public
  * License version 2, as published by the Free Software Foundation, and
@@ -25,36 +29,130 @@
 #include <linux/serial_reg.h>
 
 #include <mach/iomap.h>
+#include <mach/irammap.h>
+
+#define BIT(x) (1 << (x))
+#define ARRAY_SIZE(arr) (sizeof(arr) / sizeof((arr)[0]))
+
+#define DEBUG_UART_SHIFT 2
+
+volatile u8 *uart;
 
 static void putc(int c)
 {
-        volatile u8 *uart = (volatile u8 *)TEGRA_DEBUG_UART_BASE;
-        int shift = 2;
-
         if (uart == NULL)
                 return;
 
-        while (!(uart[UART_LSR << shift] & UART_LSR_THRE))
+        while (!(uart[UART_LSR << DEBUG_UART_SHIFT] & UART_LSR_THRE))
                 barrier();
-        uart[UART_TX << shift] = c;
+        uart[UART_TX << DEBUG_UART_SHIFT] = c;
 }
 
 static inline void flush(void)
 {
 }
 
+static inline void save_uart_address(void)
+{
+        u32 *buf = (u32 *)(TEGRA_IRAM_BASE + TEGRA_IRAM_DEBUG_UART_OFFSET);
+
+        if (uart) {
+                buf[0] = TEGRA_IRAM_DEBUG_UART_COOKIE;
+                buf[1] = (u32)uart;
+        } else
+                buf[0] = 0;
+}
+
+/*
+ * Setup before decompression.  This is where we do UART selection for
+ * earlyprintk and init the uart_base register.
+ */
 static inline void arch_decomp_setup(void)
 {
-        volatile u8 *uart = (volatile u8 *)TEGRA_DEBUG_UART_BASE;
-        int shift = 2;
+        static const struct {
+                u32 base;
+                u32 reset_reg;
+                u32 clock_reg;
+                u32 bit;
+        } uarts[] = {
+                {
+                        TEGRA_UARTA_BASE,
+                        TEGRA_CLK_RESET_BASE + 0x04,
+                        TEGRA_CLK_RESET_BASE + 0x10,
+                        6,
+                },
+                {
+                        TEGRA_UARTB_BASE,
+                        TEGRA_CLK_RESET_BASE + 0x04,
+                        TEGRA_CLK_RESET_BASE + 0x10,
+                        7,
+                },
+                {
+                        TEGRA_UARTC_BASE,
+                        TEGRA_CLK_RESET_BASE + 0x08,
+                        TEGRA_CLK_RESET_BASE + 0x14,
+                        23,
+                },
+                {
+                        TEGRA_UARTD_BASE,
+                        TEGRA_CLK_RESET_BASE + 0x0c,
+                        TEGRA_CLK_RESET_BASE + 0x18,
+                        1,
+                },
+                {
+                        TEGRA_UARTE_BASE,
+                        TEGRA_CLK_RESET_BASE + 0x0c,
+                        TEGRA_CLK_RESET_BASE + 0x18,
+                        2,
+                },
+        };
+        int i;
+        volatile u32 *apb_misc = (volatile u32 *)TEGRA_APB_MISC_BASE;
+        u32 chip, div;
+
+        /*
+         * Look for the first UART that:
+         * a) Is not in reset.
+         * b) Is clocked.
+         * c) Has a 'D' in the scratchpad register.
+         *
+         * Note that on Tegra30, the first two conditions are required, since
+         * if not true, accesses to the UART scratch register will hang.
+         * Tegra20 doesn't have this issue.
+         *
+         * The intent is that the bootloader will tell the kernel which UART
+         * to use by setting up those conditions. If nothing found, we'll fall
+         * back to what's specified in TEGRA_DEBUG_UART_BASE.
+         */
+        for (i = 0; i < ARRAY_SIZE(uarts); i++) {
+                if (*(u8 *)uarts[i].reset_reg & BIT(uarts[i].bit))
+                        continue;
 
+                if (!(*(u8 *)uarts[i].clock_reg & BIT(uarts[i].bit)))
+                        continue;
+
+                uart = (volatile u8 *)uarts[i].base;
+                if (uart[UART_SCR << DEBUG_UART_SHIFT] != 'D')
+                        continue;
+
+                break;
+        }
+        if (i == ARRAY_SIZE(uarts))
+                uart = (volatile u8 *)TEGRA_DEBUG_UART_BASE;
+        save_uart_address();
         if (uart == NULL)
                 return;
 
-        uart[UART_LCR << shift] |= UART_LCR_DLAB;
-        uart[UART_DLL << shift] = 0x75;
-        uart[UART_DLM << shift] = 0x0;
-        uart[UART_LCR << shift] = 3;
+        chip = (apb_misc[0x804 / 4] >> 8) & 0xff;
+        if (chip == 0x20)
+                div = 0x0075;
+        else
+                div = 0x00dd;
+
+        uart[UART_LCR << DEBUG_UART_SHIFT] |= UART_LCR_DLAB;
+        uart[UART_DLL << DEBUG_UART_SHIFT] = div & 0xff;
+        uart[UART_DLM << DEBUG_UART_SHIFT] = div >> 8;
+        uart[UART_LCR << DEBUG_UART_SHIFT] = 3;
 }
 
 static inline void arch_decomp_wdog(void)
diff --git a/arch/arm/mach-tegra/irq.c b/arch/arm/mach-tegra/irq.c
index 4e1afcd54fa..2f5bd2db8e1 100644
--- a/arch/arm/mach-tegra/irq.c
+++ b/arch/arm/mach-tegra/irq.c
@@ -44,14 +44,16 @@
 #define ICTLR_COP_IER_CLR       0x38
 #define ICTLR_COP_IEP_CLASS     0x3c
 
-#define NUM_ICTLRS 4
 #define FIRST_LEGACY_IRQ 32
 
+static int num_ictlrs;
+
 static void __iomem *ictlr_reg_base[] = {
         IO_ADDRESS(TEGRA_PRIMARY_ICTLR_BASE),
         IO_ADDRESS(TEGRA_SECONDARY_ICTLR_BASE),
         IO_ADDRESS(TEGRA_TERTIARY_ICTLR_BASE),
         IO_ADDRESS(TEGRA_QUATERNARY_ICTLR_BASE),
+        IO_ADDRESS(TEGRA_QUINARY_ICTLR_BASE),
 };
 
 static inline void tegra_irq_write_mask(unsigned int irq, unsigned long reg)
@@ -60,7 +62,7 @@ static inline void tegra_irq_write_mask(unsigned int irq, unsigned long reg)
         u32 mask;
 
         BUG_ON(irq < FIRST_LEGACY_IRQ ||
-                irq >= FIRST_LEGACY_IRQ + NUM_ICTLRS * 32);
+                irq >= FIRST_LEGACY_IRQ + num_ictlrs * 32);
 
         base = ictlr_reg_base[(irq - FIRST_LEGACY_IRQ) / 32];
         mask = BIT((irq - FIRST_LEGACY_IRQ) % 32);
@@ -113,8 +115,18 @@ static int tegra_retrigger(struct irq_data *d)
 void __init tegra_init_irq(void)
 {
         int i;
+        void __iomem *distbase;
+
+        distbase = IO_ADDRESS(TEGRA_ARM_INT_DIST_BASE);
+        num_ictlrs = readl_relaxed(distbase + GIC_DIST_CTR) & 0x1f;
+
+        if (num_ictlrs > ARRAY_SIZE(ictlr_reg_base)) {
+                WARN(1, "Too many (%d) interrupt controllers found. Maximum is %d.",
+                        num_ictlrs, ARRAY_SIZE(ictlr_reg_base));
+                num_ictlrs = ARRAY_SIZE(ictlr_reg_base);
+        }
 
-        for (i = 0; i < NUM_ICTLRS; i++) {
+        for (i = 0; i < num_ictlrs; i++) {
                 void __iomem *ictlr = ictlr_reg_base[i];
                 writel(~0, ictlr + ICTLR_CPU_IER_CLR);
                 writel(0, ictlr + ICTLR_CPU_IEP_CLASS);
@@ -131,6 +143,6 @@ void __init tegra_init_irq(void)
          * initialized elsewhere under DT.
          */
         if (!of_have_populated_dt())
-                gic_init(0, 29, IO_ADDRESS(TEGRA_ARM_INT_DIST_BASE),
+                gic_init(0, 29, distbase,
                         IO_ADDRESS(TEGRA_ARM_PERIF_BASE + 0x100));
 }
diff --git a/arch/arm/mach-tegra/localtimer.c b/arch/arm/mach-tegra/localtimer.c
deleted file mode 100644
index e91d681d45a..00000000000
--- a/arch/arm/mach-tegra/localtimer.c
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- *  arch/arm/mach-tegra/localtimer.c
- *
- *  Copyright (C) 2002 ARM Ltd.
- *  All Rights Reserved
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#include <linux/init.h>
-#include <linux/smp.h>
-#include <linux/clockchips.h>
-#include <asm/irq.h>
-#include <asm/smp_twd.h>
-#include <asm/localtimer.h>
-
-/*
- * Setup the local clock events for a CPU.
- */
-int __cpuinit local_timer_setup(struct clock_event_device *evt)
-{
-        evt->irq = IRQ_LOCALTIMER;
-        twd_timer_setup(evt);
-        return 0;
-}
diff --git a/arch/arm/mach-tegra/pcie.c b/arch/arm/mach-tegra/pcie.c
index af8b6343572..54a816ff384 100644
--- a/arch/arm/mach-tegra/pcie.c
+++ b/arch/arm/mach-tegra/pcie.c
@@ -408,7 +408,7 @@ static int tegra_pcie_setup(int nr, struct pci_sys_data *sys)
         pp->res[0].flags = IORESOURCE_IO;
         if (request_resource(&ioport_resource, &pp->res[0]))
                 panic("Request PCIe IO resource failed\n");
-        pci_add_resource(&sys->resources, &pp->res[0]);
+        pci_add_resource_offset(&sys->resources, &pp->res[0], sys->io_offset);
 
         /*
          * IORESOURCE_MEM
@@ -427,7 +427,7 @@ static int tegra_pcie_setup(int nr, struct pci_sys_data *sys)
         pp->res[1].flags = IORESOURCE_MEM;
         if (request_resource(&iomem_resource, &pp->res[1]))
                 panic("Request PCIe Memory resource failed\n");
-        pci_add_resource(&sys->resources, &pp->res[1]);
+        pci_add_resource_offset(&sys->resources, &pp->res[1], sys->mem_offset);
 
         /*
          * IORESOURCE_MEM | IORESOURCE_PREFETCH
@@ -446,7 +446,7 @@ static int tegra_pcie_setup(int nr, struct pci_sys_data *sys)
         pp->res[2].flags = IORESOURCE_MEM | IORESOURCE_PREFETCH;
         if (request_resource(&iomem_resource, &pp->res[2]))
                 panic("Request PCIe Prefetch Memory resource failed\n");
-        pci_add_resource(&sys->resources, &pp->res[2]);
+        pci_add_resource_offset(&sys->resources, &pp->res[2], sys->mem_offset);
 
         return 1;
 }
@@ -585,10 +585,10 @@ static void tegra_pcie_setup_translations(void)
         afi_writel(0, AFI_MSI_BAR_SZ);
 }
 
-static void tegra_pcie_enable_controller(void)
+static int tegra_pcie_enable_controller(void)
 {
         u32 val, reg;
-        int i;
+        int i, timeout;
 
         /* Enable slot clock and pulse the reset signals */
         for (i = 0, reg = AFI_PEX0_CTRL; i < 2; i++, reg += 0x8) {
@@ -639,8 +639,14 @@ static void tegra_pcie_enable_controller(void)
         pads_writel(0xfa5cfa5c, 0xc8);
 
         /* Wait for the PLL to lock */
+        timeout = 300;
         do {
                 val = pads_readl(PADS_PLL_CTL);
+                usleep_range(1000, 1000);
+                if (--timeout == 0) {
+                        pr_err("Tegra PCIe error: timeout waiting for PLL\n");
+                        return -EBUSY;
+                }
         } while (!(val & PADS_PLL_CTL_LOCKDET));
 
         /* turn off IDDQ override */
@@ -671,7 +677,7 @@ static void tegra_pcie_enable_controller(void)
         /* Disable all execptions */
         afi_writel(0, AFI_FPCI_ERROR_MASKS);
 
-        return;
+        return 0;
 }
 
 static void tegra_pcie_xclk_clamp(bool clamp)
@@ -921,7 +927,9 @@ int __init tegra_pcie_init(bool init_port0, bool init_port1)
         if (err)
                 return err;
 
-        tegra_pcie_enable_controller();
+        err = tegra_pcie_enable_controller();
+        if (err)
+                return err;
 
         /* setup the AFI address translations */
         tegra_pcie_setup_translations();
diff --git a/arch/arm/mach-tegra/pmc.c b/arch/arm/mach-tegra/pmc.c
new file mode 100644
index 00000000000..7af6a54404b
--- /dev/null
+++ b/arch/arm/mach-tegra/pmc.c
@@ -0,0 +1,76 @@
+/*
+ * Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/io.h>
+#include <linux/of.h>
+
+#include <mach/iomap.h>
+
+#define PMC_CTRL                0x0
+#define PMC_CTRL_INTR_LOW       (1 << 17)
+
+static inline u32 tegra_pmc_readl(u32 reg)
+{
+        return readl(IO_ADDRESS(TEGRA_PMC_BASE + reg));
+}
+
+static inline void tegra_pmc_writel(u32 val, u32 reg)
+{
+        writel(val, IO_ADDRESS(TEGRA_PMC_BASE + reg));
+}
+
+#ifdef CONFIG_OF
+static const struct of_device_id matches[] __initconst = {
+        { .compatible = "nvidia,tegra20-pmc" },
+        { }
+};
+#endif
+
+void __init tegra_pmc_init(void)
+{
+        /*
+         * For now, Harmony is the only board that uses the PMC, and it wants
+         * the signal inverted. Seaboard would too if it used the PMC.
+         * Hopefully by the time other boards want to use the PMC, everything
+         * will be device-tree, or they also want it inverted.
+         */
+        bool invert_interrupt = true;
+        u32 val;
+
+#ifdef CONFIG_OF
+        if (of_have_populated_dt()) {
+                struct device_node *np;
+
+                invert_interrupt = false;
+
+                np = of_find_matching_node(NULL, matches);
+                if (np) {
+                        if (of_find_property(np, "nvidia,invert-interrupt",
+                                                NULL))
+                                invert_interrupt = true;
+                }
+        }
+#endif
+
+        val = tegra_pmc_readl(PMC_CTRL);
+        if (invert_interrupt)
+                val |= PMC_CTRL_INTR_LOW;
+        else
+                val &= ~PMC_CTRL_INTR_LOW;
+        tegra_pmc_writel(val, PMC_CTRL);
+}
diff --git a/arch/arm/mach-highbank/include/mach/system.h b/arch/arm/mach-tegra/pmc.h
index b1d8b5fbe37..8995ee4a876 100644
--- a/arch/arm/mach-highbank/include/mach/system.h
+++ b/arch/arm/mach-tegra/pmc.h
@@ -1,5 +1,5 @@
 /*
- * Copyright 2010-2011 Calxeda, Inc.
+ * Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -10,15 +10,14 @@
  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  * more details.
  *
- * You should have received a copy of the GNU General Public License along with
- * this program.  If not, see <http://www.gnu.org/licenses/>.
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ *
  */
-#ifndef __MACH_SYSTEM_H
-#define __MACH_SYSTEM_H
 
-static inline void arch_idle(void)
-{
-        cpu_do_idle();
-}
+#ifndef __MACH_TEGRA_PMC_H
+#define __MACH_TEGRA_PMC_H
+
+void tegra_pmc_init(void);
 
 #endif
diff --git a/arch/arm/mach-tegra/sleep.S b/arch/arm/mach-tegra/sleep.S
new file mode 100644
index 00000000000..8f9fde161c3
--- /dev/null
+++ b/arch/arm/mach-tegra/sleep.S
@@ -0,0 +1,91 @@
+/*
+ * arch/arm/mach-tegra/sleep.S
+ *
+ * Copyright (c) 2010-2011, NVIDIA Corporation.
+ * Copyright (c) 2011, Google, Inc.
+ *
+ * Author: Colin Cross <ccross@android.com>
+ *         Gary King <gking@nvidia.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+#include <linux/linkage.h>
+#include <mach/io.h>
+#include <mach/iomap.h>
+
+#include "flowctrl.h"
+
+#define TEGRA_FLOW_CTRL_VIRT (TEGRA_FLOW_CTRL_BASE - IO_PPSB_PHYS \
+                                        + IO_PPSB_VIRT)
+
+/* returns the offset of the flow controller halt register for a cpu */
+.macro cpu_to_halt_reg rd, rcpu
+        cmp     \rcpu, #0
+        subne   \rd, \rcpu, #1
+        movne   \rd, \rd, lsl #3
+        addne   \rd, \rd, #0x14
+        moveq   \rd, #0
+.endm
+
+/* returns the offset of the flow controller csr register for a cpu */
+.macro cpu_to_csr_reg rd, rcpu
+        cmp     \rcpu, #0
+        subne   \rd, \rcpu, #1
+        movne   \rd, \rd, lsl #3
+        addne   \rd, \rd, #0x18
+        moveq   \rd, #8
+.endm
+
+/* returns the ID of the current processor */
+.macro cpu_id, rd
+        mrc     p15, 0, \rd, c0, c0, 5
+        and     \rd, \rd, #0xF
+.endm
+
+/* loads a 32-bit value into a register without a data access */
+.macro mov32, reg, val
+        movw    \reg, #:lower16:\val
+        movt    \reg, #:upper16:\val
+.endm
+
+/*
+ * tegra_cpu_wfi
+ *
+ * puts current CPU in clock-gated wfi using the flow controller
+ *
+ * corrupts r0-r3
+ * must be called with MMU on
+ */
+
+ENTRY(tegra_cpu_wfi)
+        cpu_id  r0
+        cpu_to_halt_reg r1, r0
+        cpu_to_csr_reg r2, r0
+        mov32   r0, TEGRA_FLOW_CTRL_VIRT
+        mov     r3, #FLOW_CTRL_CSR_INTR_FLAG | FLOW_CTRL_CSR_EVENT_FLAG
+        str     r3, [r0, r2]    @ clear event & interrupt status
+        mov     r3, #FLOW_CTRL_WAIT_FOR_INTERRUPT | FLOW_CTRL_JTAG_RESUME
+        str     r3, [r0, r1]    @ put flow controller in wait irq mode
+        dsb
+        wfi
+        mov     r3, #0
+        str     r3, [r0, r1]    @ clear flow controller halt status
+        mov     r3, #FLOW_CTRL_CSR_INTR_FLAG | FLOW_CTRL_CSR_EVENT_FLAG
+        str     r3, [r0, r2]    @ clear event & interrupt status
+        dsb
+        mov     pc, lr
+ENDPROC(tegra_cpu_wfi)
+
diff --git a/arch/arm/mach-tegra/tegra2_clocks.c b/arch/arm/mach-tegra/tegra2_clocks.c
index ff9e6b6c046..592a4eeb532 100644
--- a/arch/arm/mach-tegra/tegra2_clocks.c
+++ b/arch/arm/mach-tegra/tegra2_clocks.c
@@ -720,7 +720,7 @@ static void tegra2_pllx_clk_init(struct clk *c)
 {
         tegra2_pll_clk_init(c);
 
-        if (tegra_sku_id() == 7)
+        if (tegra_sku_id == 7)
                 c->max_rate = 750000000;
 }
 
@@ -1143,15 +1143,35 @@ static void tegra2_emc_clk_init(struct clk *c)
 
 static long tegra2_emc_clk_round_rate(struct clk *c, unsigned long rate)
 {
-        long new_rate = rate;
+        long emc_rate;
+        long clk_rate;
 
-        new_rate = tegra_emc_round_rate(new_rate);
-        if (new_rate < 0)
+        /*
+         * The slowest entry in the EMC clock table that is at least as
+         * fast as rate.
+         */
+        emc_rate = tegra_emc_round_rate(rate);
+        if (emc_rate < 0)
                 return c->max_rate;
 
-        BUG_ON(new_rate != tegra2_periph_clk_round_rate(c, new_rate));
+        /*
+         * The fastest rate the PLL will generate that is at most the
+         * requested rate.
+         */
+        clk_rate = tegra2_periph_clk_round_rate(c, emc_rate);
+
+        /*
+         * If this fails, and emc_rate > clk_rate, it's because the maximum
+         * rate in the EMC tables is larger than the maximum rate of the EMC
+         * clock. The EMC clock's max rate is the rate it was running when the
+         * kernel booted. Such a mismatch is probably due to using the wrong
+         * BCT, i.e. using a Tegra20 BCT with an EMC table written for Tegra25.
+         */
+        WARN_ONCE(emc_rate != clk_rate,
+                "emc_rate %ld != clk_rate %ld",
+                emc_rate, clk_rate);
 
-        return new_rate;
+        return emc_rate;
 }
 
 static int tegra2_emc_clk_set_rate(struct clk *c, unsigned long rate)
diff --git a/arch/arm/mach-tegra/tegra2_emc.c b/arch/arm/mach-tegra/tegra2_emc.c
index 0f7ae6e90b5..5070d833bdd 100644
--- a/arch/arm/mach-tegra/tegra2_emc.c
+++ b/arch/arm/mach-tegra/tegra2_emc.c
@@ -16,14 +16,19 @@
  */
 
 #include <linux/kernel.h>
+#include <linux/device.h>
 #include <linux/clk.h>
 #include <linux/err.h>
 #include <linux/io.h>
 #include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/platform_data/tegra_emc.h>
 
 #include <mach/iomap.h>
 
 #include "tegra2_emc.h"
+#include "fuse.h"
 
 #ifdef CONFIG_TEGRA_EMC_SCALING_ENABLE
 static bool emc_enable = true;
@@ -32,18 +37,17 @@ static bool emc_enable;
 #endif
 module_param(emc_enable, bool, 0644);
 
-static void __iomem *emc = IO_ADDRESS(TEGRA_EMC_BASE);
-static const struct tegra_emc_table *tegra_emc_table;
-static int tegra_emc_table_size;
+static struct platform_device *emc_pdev;
+static void __iomem *emc_regbase;
 
 static inline void emc_writel(u32 val, unsigned long addr)
 {
-        writel(val, emc + addr);
+        writel(val, emc_regbase + addr);
 }
 
 static inline u32 emc_readl(unsigned long addr)
 {
-        return readl(emc + addr);
+        return readl(emc_regbase + addr);
 }
 
 static const unsigned long emc_reg_addr[TEGRA_EMC_NUM_REGS] = {
@@ -98,15 +102,15 @@ static const unsigned long emc_reg_addr[TEGRA_EMC_NUM_REGS] = {
 /* Select the closest EMC rate that is higher than the requested rate */
 long tegra_emc_round_rate(unsigned long rate)
 {
+        struct tegra_emc_pdata *pdata;
         int i;
         int best = -1;
         unsigned long distance = ULONG_MAX;
 
-        if (!tegra_emc_table)
+        if (!emc_pdev)
                 return -EINVAL;
 
-        if (!emc_enable)
-                return -EINVAL;
+        pdata = emc_pdev->dev.platform_data;
 
         pr_debug("%s: %lu\n", __func__, rate);
 
@@ -116,10 +120,10 @@ long tegra_emc_round_rate(unsigned long rate)
          */
         rate = rate / 2 / 1000;
 
-        for (i = 0; i < tegra_emc_table_size; i++) {
-                if (tegra_emc_table[i].rate >= rate &&
-                    (tegra_emc_table[i].rate - rate) < distance) {
-                        distance = tegra_emc_table[i].rate - rate;
+        for (i = 0; i < pdata->num_tables; i++) {
+                if (pdata->tables[i].rate >= rate &&
+                    (pdata->tables[i].rate - rate) < distance) {
+                        distance = pdata->tables[i].rate - rate;
                         best = i;
                 }
         }
@@ -127,9 +131,9 @@ long tegra_emc_round_rate(unsigned long rate)
         if (best < 0)
                 return -EINVAL;
 
-        pr_debug("%s: using %lu\n", __func__, tegra_emc_table[best].rate);
+        pr_debug("%s: using %lu\n", __func__, pdata->tables[best].rate);
 
-        return tegra_emc_table[best].rate * 2 * 1000;
+        return pdata->tables[best].rate * 2 * 1000;
 }
 
 /*
@@ -142,37 +146,211 @@ long tegra_emc_round_rate(unsigned long rate)
  */
 int tegra_emc_set_rate(unsigned long rate)
 {
+        struct tegra_emc_pdata *pdata;
         int i;
         int j;
 
-        if (!tegra_emc_table)
+        if (!emc_pdev)
                 return -EINVAL;
 
+        pdata = emc_pdev->dev.platform_data;
+
         /*
          * The EMC clock rate is twice the bus rate, and the bus rate is
          * measured in kHz
          */
         rate = rate / 2 / 1000;
 
-        for (i = 0; i < tegra_emc_table_size; i++)
-                if (tegra_emc_table[i].rate == rate)
+        for (i = 0; i < pdata->num_tables; i++)
+                if (pdata->tables[i].rate == rate)
                         break;
 
-        if (i >= tegra_emc_table_size)
+        if (i >= pdata->num_tables)
                 return -EINVAL;
 
         pr_debug("%s: setting to %lu\n", __func__, rate);
 
         for (j = 0; j < TEGRA_EMC_NUM_REGS; j++)
-                emc_writel(tegra_emc_table[i].regs[j], emc_reg_addr[j]);
+                emc_writel(pdata->tables[i].regs[j], emc_reg_addr[j]);
 
-        emc_readl(tegra_emc_table[i].regs[TEGRA_EMC_NUM_REGS - 1]);
+        emc_readl(pdata->tables[i].regs[TEGRA_EMC_NUM_REGS - 1]);
 
         return 0;
 }
 
-void tegra_init_emc(const struct tegra_emc_table *table, int table_size)
+#ifdef CONFIG_OF
+static struct device_node *tegra_emc_ramcode_devnode(struct device_node *np)
+{
+        struct device_node *iter;
+        u32 reg;
+
+        for_each_child_of_node(np, iter) {
+                if (of_property_read_u32(np, "nvidia,ram-code", &reg))
+                        continue;
+                if (reg == tegra_bct_strapping)
+                        return of_node_get(iter);
+        }
+
+        return NULL;
+}
+
+static struct tegra_emc_pdata *tegra_emc_dt_parse_pdata(
+                struct platform_device *pdev)
+{
+        struct device_node *np = pdev->dev.of_node;
+        struct device_node *tnp, *iter;
+        struct tegra_emc_pdata *pdata;
+        int ret, i, num_tables;
+
+        if (!np)
+                return NULL;
+
+        if (of_find_property(np, "nvidia,use-ram-code", NULL)) {
+                tnp = tegra_emc_ramcode_devnode(np);
+                if (!tnp)
+                        dev_warn(&pdev->dev,
+                                 "can't find emc table for ram-code 0x%02x\n",
+                                 tegra_bct_strapping);
+        } else
+                tnp = of_node_get(np);
+
+        if (!tnp)
+                return NULL;
+
+        num_tables = 0;
+        for_each_child_of_node(tnp, iter)
+                if (of_device_is_compatible(iter, "nvidia,tegra20-emc-table"))
+                        num_tables++;
+
+        if (!num_tables) {
+                pdata = NULL;
+                goto out;
+        }
+
+        pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
+        pdata->tables = devm_kzalloc(&pdev->dev,
+                                     sizeof(*pdata->tables) * num_tables,
+                                     GFP_KERNEL);
+
+        i = 0;
+        for_each_child_of_node(tnp, iter) {
+                u32 prop;
+
+                ret = of_property_read_u32(iter, "clock-frequency", &prop);
+                if (ret) {
+                        dev_err(&pdev->dev, "no clock-frequency in %s\n",
+                                iter->full_name);
+                        continue;
+                }
+                pdata->tables[i].rate = prop;
+
+                ret = of_property_read_u32_array(iter, "nvidia,emc-registers",
+                                                 pdata->tables[i].regs,
+                                                 TEGRA_EMC_NUM_REGS);
+                if (ret) {
+                        dev_err(&pdev->dev,
+                                "malformed emc-registers property in %s\n",
+                                iter->full_name);
+                        continue;
+                }
+
+                i++;
+        }
+        pdata->num_tables = i;
+
+out:
+        of_node_put(tnp);
+        return pdata;
+}
+#else
+static struct tegra_emc_pdata *tegra_emc_dt_parse_pdata(
+                struct platform_device *pdev)
+{
+        return NULL;
+}
+#endif
+
+static struct tegra_emc_pdata __devinit *tegra_emc_fill_pdata(struct platform_device *pdev)
+{
+        struct clk *c = clk_get_sys(NULL, "emc");
+        struct tegra_emc_pdata *pdata;
+        unsigned long khz;
+        int i;
+
+        WARN_ON(pdev->dev.platform_data);
+        BUG_ON(IS_ERR_OR_NULL(c));
+
+        pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
+        pdata->tables = devm_kzalloc(&pdev->dev, sizeof(*pdata->tables),
+                                     GFP_KERNEL);
+
+        pdata->tables[0].rate = clk_get_rate(c) / 2 / 1000;
+
+        for (i = 0; i < TEGRA_EMC_NUM_REGS; i++)
+                pdata->tables[0].regs[i] = emc_readl(emc_reg_addr[i]);
+
+        pdata->num_tables = 1;
+
+        khz = pdata->tables[0].rate;
+        dev_info(&pdev->dev, "no tables provided, using %ld kHz emc, "
+                 "%ld kHz mem\n", khz * 2, khz);
+
+        return pdata;
+}
+
+static int __devinit tegra_emc_probe(struct platform_device *pdev)
+{
+        struct tegra_emc_pdata *pdata;
+        struct resource *res;
+
+        if (!emc_enable) {
+                dev_err(&pdev->dev, "disabled per module parameter\n");
+                return -ENODEV;
+        }
+
+        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+        if (!res) {
+                dev_err(&pdev->dev, "missing register base\n");
+                return -ENOMEM;
+        }
+
+        emc_regbase = devm_request_and_ioremap(&pdev->dev, res);
+        if (!emc_regbase) {
+                dev_err(&pdev->dev, "failed to remap registers\n");
+                return -ENOMEM;
+        }
+
+        pdata = pdev->dev.platform_data;
+
+        if (!pdata)
+                pdata = tegra_emc_dt_parse_pdata(pdev);
+
+        if (!pdata)
+                pdata = tegra_emc_fill_pdata(pdev);
+
+        pdev->dev.platform_data = pdata;
+
+        emc_pdev = pdev;
+
+        return 0;
+}
+
+static struct of_device_id tegra_emc_of_match[] __devinitdata = {
+        { .compatible = "nvidia,tegra20-emc", },
+        { },
+};
+
+static struct platform_driver tegra_emc_driver = {
+        .driver         = {
+                .name   = "tegra-emc",
+                .owner  = THIS_MODULE,
+                .of_match_table = tegra_emc_of_match,
+        },
+        .probe          = tegra_emc_probe,
+};
+
+static int __init tegra_emc_init(void)
 {
-        tegra_emc_table = table;
-        tegra_emc_table_size = table_size;
+        return platform_driver_register(&tegra_emc_driver);
 }
+device_initcall(tegra_emc_init);
diff --git a/arch/arm/mach-tegra/tegra2_emc.h b/arch/arm/mach-tegra/tegra2_emc.h
index 19f08cb3160..f61409b54cb 100644
--- a/arch/arm/mach-tegra/tegra2_emc.h
+++ b/arch/arm/mach-tegra/tegra2_emc.h
@@ -15,13 +15,10 @@
  *
  */
 
-#define TEGRA_EMC_NUM_REGS 46
-
-struct tegra_emc_table {
-        unsigned long rate;
-        u32 regs[TEGRA_EMC_NUM_REGS];
-};
+#ifndef __MACH_TEGRA_TEGRA2_EMC_H_
+#define __MACH_TEGRA_TEGRA2_EMC_H
 
 int tegra_emc_set_rate(unsigned long rate);
 long tegra_emc_round_rate(unsigned long rate);
-void tegra_init_emc(const struct tegra_emc_table *table, int table_size);
+
+#endif
diff --git a/arch/arm/mach-tegra/tegra30_clocks.c b/arch/arm/mach-tegra/tegra30_clocks.c
new file mode 100644
index 00000000000..6d08b53f92d
--- /dev/null
+++ b/arch/arm/mach-tegra/tegra30_clocks.c
@@ -0,0 +1,3099 @@
+/*
+ * arch/arm/mach-tegra/tegra30_clocks.c
+ *
+ * Copyright (c) 2010-2011 NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/list.h>
+#include <linux/spinlock.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/clk.h>
+#include <linux/cpufreq.h>
+#include <linux/syscore_ops.h>
+
+#include <asm/clkdev.h>
+
+#include <mach/iomap.h>
+
+#include "clock.h"
+#include "fuse.h"
+
+#define USE_PLL_LOCK_BITS 0
+
+#define RST_DEVICES_L                   0x004
+#define RST_DEVICES_H                   0x008
+#define RST_DEVICES_U                   0x00C
+#define RST_DEVICES_V                   0x358
+#define RST_DEVICES_W                   0x35C
+#define RST_DEVICES_SET_L               0x300
+#define RST_DEVICES_CLR_L               0x304
+#define RST_DEVICES_SET_V               0x430
+#define RST_DEVICES_CLR_V               0x434
+#define RST_DEVICES_NUM                 5
+
+#define CLK_OUT_ENB_L                   0x010
+#define CLK_OUT_ENB_H                   0x014
+#define CLK_OUT_ENB_U                   0x018
+#define CLK_OUT_ENB_V                   0x360
+#define CLK_OUT_ENB_W                   0x364
+#define CLK_OUT_ENB_SET_L               0x320
+#define CLK_OUT_ENB_CLR_L               0x324
+#define CLK_OUT_ENB_SET_V               0x440
+#define CLK_OUT_ENB_CLR_V               0x444
+#define CLK_OUT_ENB_NUM                 5
+
+#define RST_DEVICES_V_SWR_CPULP_RST_DIS (0x1 << 1)
+#define CLK_OUT_ENB_V_CLK_ENB_CPULP_EN  (0x1 << 1)
+
+#define PERIPH_CLK_TO_BIT(c)            (1 << (c->u.periph.clk_num % 32))
+#define PERIPH_CLK_TO_RST_REG(c)        \
+        periph_clk_to_reg((c), RST_DEVICES_L, RST_DEVICES_V, 4)
+#define PERIPH_CLK_TO_RST_SET_REG(c)    \
+        periph_clk_to_reg((c), RST_DEVICES_SET_L, RST_DEVICES_SET_V, 8)
+#define PERIPH_CLK_TO_RST_CLR_REG(c)    \
+        periph_clk_to_reg((c), RST_DEVICES_CLR_L, RST_DEVICES_CLR_V, 8)
+
+#define PERIPH_CLK_TO_ENB_REG(c)        \
+        periph_clk_to_reg((c), CLK_OUT_ENB_L, CLK_OUT_ENB_V, 4)
+#define PERIPH_CLK_TO_ENB_SET_REG(c)    \
+        periph_clk_to_reg((c), CLK_OUT_ENB_SET_L, CLK_OUT_ENB_SET_V, 8)
+#define PERIPH_CLK_TO_ENB_CLR_REG(c)    \
+        periph_clk_to_reg((c), CLK_OUT_ENB_CLR_L, CLK_OUT_ENB_CLR_V, 8)
+
+#define CLK_MASK_ARM                    0x44
+#define MISC_CLK_ENB                    0x48
+
+#define OSC_CTRL                        0x50
+#define OSC_CTRL_OSC_FREQ_MASK          (0xF<<28)
+#define OSC_CTRL_OSC_FREQ_13MHZ         (0x0<<28)
+#define OSC_CTRL_OSC_FREQ_19_2MHZ       (0x4<<28)
+#define OSC_CTRL_OSC_FREQ_12MHZ         (0x8<<28)
+#define OSC_CTRL_OSC_FREQ_26MHZ         (0xC<<28)
+#define OSC_CTRL_OSC_FREQ_16_8MHZ       (0x1<<28)
+#define OSC_CTRL_OSC_FREQ_38_4MHZ       (0x5<<28)
+#define OSC_CTRL_OSC_FREQ_48MHZ         (0x9<<28)
+#define OSC_CTRL_MASK                   (0x3f2 | OSC_CTRL_OSC_FREQ_MASK)
+
+#define OSC_CTRL_PLL_REF_DIV_MASK       (3<<26)
+#define OSC_CTRL_PLL_REF_DIV_1          (0<<26)
+#define OSC_CTRL_PLL_REF_DIV_2          (1<<26)
+#define OSC_CTRL_PLL_REF_DIV_4          (2<<26)
+
+#define OSC_FREQ_DET                    0x58
+#define OSC_FREQ_DET_TRIG               (1<<31)
+
+#define OSC_FREQ_DET_STATUS             0x5C
+#define OSC_FREQ_DET_BUSY               (1<<31)
+#define OSC_FREQ_DET_CNT_MASK           0xFFFF
+
+#define PERIPH_CLK_SOURCE_I2S1          0x100
+#define PERIPH_CLK_SOURCE_EMC           0x19c
+#define PERIPH_CLK_SOURCE_OSC           0x1fc
+#define PERIPH_CLK_SOURCE_NUM1 \
+        ((PERIPH_CLK_SOURCE_OSC - PERIPH_CLK_SOURCE_I2S1) / 4)
+
+#define PERIPH_CLK_SOURCE_G3D2          0x3b0
+#define PERIPH_CLK_SOURCE_SE            0x42c
+#define PERIPH_CLK_SOURCE_NUM2 \
+        ((PERIPH_CLK_SOURCE_SE - PERIPH_CLK_SOURCE_G3D2) / 4 + 1)
+
+#define AUDIO_DLY_CLK                   0x49c
+#define AUDIO_SYNC_CLK_SPDIF            0x4b4
+#define PERIPH_CLK_SOURCE_NUM3 \
+        ((AUDIO_SYNC_CLK_SPDIF - AUDIO_DLY_CLK) / 4 + 1)
+
+#define PERIPH_CLK_SOURCE_NUM           (PERIPH_CLK_SOURCE_NUM1 + \
+                                         PERIPH_CLK_SOURCE_NUM2 + \
+                                         PERIPH_CLK_SOURCE_NUM3)
+
+#define CPU_SOFTRST_CTRL                0x380
+
+#define PERIPH_CLK_SOURCE_DIVU71_MASK   0xFF
+#define PERIPH_CLK_SOURCE_DIVU16_MASK   0xFFFF
+#define PERIPH_CLK_SOURCE_DIV_SHIFT     0
+#define PERIPH_CLK_SOURCE_DIVIDLE_SHIFT 8
+#define PERIPH_CLK_SOURCE_DIVIDLE_VAL   50
+#define PERIPH_CLK_UART_DIV_ENB         (1<<24)
+#define PERIPH_CLK_VI_SEL_EX_SHIFT      24
+#define PERIPH_CLK_VI_SEL_EX_MASK       (0x3<<PERIPH_CLK_VI_SEL_EX_SHIFT)
+#define PERIPH_CLK_NAND_DIV_EX_ENB      (1<<8)
+#define PERIPH_CLK_DTV_POLARITY_INV     (1<<25)
+
+#define AUDIO_SYNC_SOURCE_MASK          0x0F
+#define AUDIO_SYNC_DISABLE_BIT          0x10
+#define AUDIO_SYNC_TAP_NIBBLE_SHIFT(c)  ((c->reg_shift - 24) * 4)
+
+#define PLL_BASE                        0x0
+#define PLL_BASE_BYPASS                 (1<<31)
+#define PLL_BASE_ENABLE                 (1<<30)
+#define PLL_BASE_REF_ENABLE             (1<<29)
+#define PLL_BASE_OVERRIDE               (1<<28)
+#define PLL_BASE_LOCK                   (1<<27)
+#define PLL_BASE_DIVP_MASK              (0x7<<20)
+#define PLL_BASE_DIVP_SHIFT             20
+#define PLL_BASE_DIVN_MASK              (0x3FF<<8)
+#define PLL_BASE_DIVN_SHIFT             8
+#define PLL_BASE_DIVM_MASK              (0x1F)
+#define PLL_BASE_DIVM_SHIFT             0
+
+#define PLL_OUT_RATIO_MASK              (0xFF<<8)
+#define PLL_OUT_RATIO_SHIFT             8
+#define PLL_OUT_OVERRIDE                (1<<2)
+#define PLL_OUT_CLKEN                   (1<<1)
+#define PLL_OUT_RESET_DISABLE           (1<<0)
+
+#define PLL_MISC(c)                     \
+        (((c)->flags & PLL_ALT_MISC_REG) ? 0x4 : 0xc)
+#define PLL_MISC_LOCK_ENABLE(c) \
+        (((c)->flags & (PLLU | PLLD)) ? (1<<22) : (1<<18))
+
+#define PLL_MISC_DCCON_SHIFT            20
+#define PLL_MISC_CPCON_SHIFT            8
+#define PLL_MISC_CPCON_MASK             (0xF<<PLL_MISC_CPCON_SHIFT)
+#define PLL_MISC_LFCON_SHIFT            4
+#define PLL_MISC_LFCON_MASK             (0xF<<PLL_MISC_LFCON_SHIFT)
+#define PLL_MISC_VCOCON_SHIFT           0
+#define PLL_MISC_VCOCON_MASK            (0xF<<PLL_MISC_VCOCON_SHIFT)
+#define PLLD_MISC_CLKENABLE             (1<<30)
+
+#define PLLU_BASE_POST_DIV              (1<<20)
+
+#define PLLD_BASE_DSIB_MUX_SHIFT        25
+#define PLLD_BASE_DSIB_MUX_MASK         (1<<PLLD_BASE_DSIB_MUX_SHIFT)
+#define PLLD_BASE_CSI_CLKENABLE         (1<<26)
+#define PLLD_MISC_DSI_CLKENABLE         (1<<30)
+#define PLLD_MISC_DIV_RST               (1<<23)
+#define PLLD_MISC_DCCON_SHIFT           12
+
+#define PLLDU_LFCON_SET_DIVN            600
+
+/* FIXME: OUT_OF_TABLE_CPCON per pll */
+#define OUT_OF_TABLE_CPCON              0x8
+
+#define SUPER_CLK_MUX                   0x00
+#define SUPER_STATE_SHIFT               28
+#define SUPER_STATE_MASK                (0xF << SUPER_STATE_SHIFT)
+#define SUPER_STATE_STANDBY             (0x0 << SUPER_STATE_SHIFT)
+#define SUPER_STATE_IDLE                (0x1 << SUPER_STATE_SHIFT)
+#define SUPER_STATE_RUN                 (0x2 << SUPER_STATE_SHIFT)
+#define SUPER_STATE_IRQ                 (0x3 << SUPER_STATE_SHIFT)
+#define SUPER_STATE_FIQ                 (0x4 << SUPER_STATE_SHIFT)
+#define SUPER_LP_DIV2_BYPASS            (0x1 << 16)
+#define SUPER_SOURCE_MASK               0xF
+#define SUPER_FIQ_SOURCE_SHIFT          12
+#define SUPER_IRQ_SOURCE_SHIFT          8
+#define SUPER_RUN_SOURCE_SHIFT          4
+#define SUPER_IDLE_SOURCE_SHIFT         0
+
+#define SUPER_CLK_DIVIDER               0x04
+#define SUPER_CLOCK_DIV_U71_SHIFT       16
+#define SUPER_CLOCK_DIV_U71_MASK        (0xff << SUPER_CLOCK_DIV_U71_SHIFT)
+/* guarantees safe cpu backup */
+#define SUPER_CLOCK_DIV_U71_MIN         0x2
+
+#define BUS_CLK_DISABLE                 (1<<3)
+#define BUS_CLK_DIV_MASK                0x3
+
+#define PMC_CTRL                        0x0
+ #define PMC_CTRL_BLINK_ENB             (1 << 7)
+
+#define PMC_DPD_PADS_ORIDE              0x1c
+ #define PMC_DPD_PADS_ORIDE_BLINK_ENB   (1 << 20)
+
+#define PMC_BLINK_TIMER_DATA_ON_SHIFT   0
+#define PMC_BLINK_TIMER_DATA_ON_MASK    0x7fff
+#define PMC_BLINK_TIMER_ENB             (1 << 15)
+#define PMC_BLINK_TIMER_DATA_OFF_SHIFT  16
+#define PMC_BLINK_TIMER_DATA_OFF_MASK   0xffff
+
+#define PMC_PLLP_WB0_OVERRIDE                           0xf8
+#define PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE               (1 << 12)
+
+#define UTMIP_PLL_CFG2                                  0x488
+#define UTMIP_PLL_CFG2_STABLE_COUNT(x)                  (((x) & 0xfff) << 6)
+#define UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(x)              (((x) & 0x3f) << 18)
+#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN        (1 << 0)
+#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN        (1 << 2)
+#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN        (1 << 4)
+
+#define UTMIP_PLL_CFG1                                  0x484
+#define UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(x)              (((x) & 0x1f) << 27)
+#define UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(x)               (((x) & 0xfff) << 0)
+#define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN       (1 << 14)
+#define UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN       (1 << 12)
+#define UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN             (1 << 16)
+
+#define PLLE_BASE_CML_ENABLE            (1<<31)
+#define PLLE_BASE_ENABLE                (1<<30)
+#define PLLE_BASE_DIVCML_SHIFT          24
+#define PLLE_BASE_DIVCML_MASK           (0xf<<PLLE_BASE_DIVCML_SHIFT)
+#define PLLE_BASE_DIVP_SHIFT            16
+#define PLLE_BASE_DIVP_MASK             (0x3f<<PLLE_BASE_DIVP_SHIFT)
+#define PLLE_BASE_DIVN_SHIFT            8
+#define PLLE_BASE_DIVN_MASK             (0xFF<<PLLE_BASE_DIVN_SHIFT)
+#define PLLE_BASE_DIVM_SHIFT            0
+#define PLLE_BASE_DIVM_MASK             (0xFF<<PLLE_BASE_DIVM_SHIFT)
+#define PLLE_BASE_DIV_MASK              \
+        (PLLE_BASE_DIVCML_MASK | PLLE_BASE_DIVP_MASK | \
+         PLLE_BASE_DIVN_MASK | PLLE_BASE_DIVM_MASK)
+#define PLLE_BASE_DIV(m, n, p, cml)             \
+         (((cml)<<PLLE_BASE_DIVCML_SHIFT) | ((p)<<PLLE_BASE_DIVP_SHIFT) | \
+          ((n)<<PLLE_BASE_DIVN_SHIFT) | ((m)<<PLLE_BASE_DIVM_SHIFT))
+
+#define PLLE_MISC_SETUP_BASE_SHIFT      16
+#define PLLE_MISC_SETUP_BASE_MASK       (0xFFFF<<PLLE_MISC_SETUP_BASE_SHIFT)
+#define PLLE_MISC_READY                 (1<<15)
+#define PLLE_MISC_LOCK                  (1<<11)
+#define PLLE_MISC_LOCK_ENABLE           (1<<9)
+#define PLLE_MISC_SETUP_EX_SHIFT        2
+#define PLLE_MISC_SETUP_EX_MASK         (0x3<<PLLE_MISC_SETUP_EX_SHIFT)
+#define PLLE_MISC_SETUP_MASK            \
+          (PLLE_MISC_SETUP_BASE_MASK | PLLE_MISC_SETUP_EX_MASK)
+#define PLLE_MISC_SETUP_VALUE           \
+          ((0x7<<PLLE_MISC_SETUP_BASE_SHIFT) | (0x0<<PLLE_MISC_SETUP_EX_SHIFT))
+
+#define PLLE_SS_CTRL                    0x68
+#define PLLE_SS_INCINTRV_SHIFT          24
+#define PLLE_SS_INCINTRV_MASK           (0x3f<<PLLE_SS_INCINTRV_SHIFT)
+#define PLLE_SS_INC_SHIFT               16
+#define PLLE_SS_INC_MASK                (0xff<<PLLE_SS_INC_SHIFT)
+#define PLLE_SS_MAX_SHIFT               0
+#define PLLE_SS_MAX_MASK                (0x1ff<<PLLE_SS_MAX_SHIFT)
+#define PLLE_SS_COEFFICIENTS_MASK       \
+        (PLLE_SS_INCINTRV_MASK | PLLE_SS_INC_MASK | PLLE_SS_MAX_MASK)
+#define PLLE_SS_COEFFICIENTS_12MHZ      \
+        ((0x18<<PLLE_SS_INCINTRV_SHIFT) | (0x1<<PLLE_SS_INC_SHIFT) | \
+         (0x24<<PLLE_SS_MAX_SHIFT))
+#define PLLE_SS_DISABLE                 ((1<<12) | (1<<11) | (1<<10))
+
+#define PLLE_AUX                        0x48c
+#define PLLE_AUX_PLLP_SEL               (1<<2)
+#define PLLE_AUX_CML_SATA_ENABLE        (1<<1)
+#define PLLE_AUX_CML_PCIE_ENABLE        (1<<0)
+
+#define PMC_SATA_PWRGT                  0x1ac
+#define PMC_SATA_PWRGT_PLLE_IDDQ_VALUE  (1<<5)
+#define PMC_SATA_PWRGT_PLLE_IDDQ_SWCTL  (1<<4)
+
+#define ROUND_DIVIDER_UP        0
+#define ROUND_DIVIDER_DOWN      1
+
+/* FIXME: recommended safety delay after lock is detected */
+#define PLL_POST_LOCK_DELAY             100
+
+/**
+* Structure defining the fields for USB UTMI clocks Parameters.
+*/
+struct utmi_clk_param {
+        /* Oscillator Frequency in KHz */
+        u32 osc_frequency;
+        /* UTMIP PLL Enable Delay Count  */
+        u8 enable_delay_count;
+        /* UTMIP PLL Stable count */
+        u8 stable_count;
+        /*  UTMIP PLL Active delay count */
+        u8 active_delay_count;
+        /* UTMIP PLL Xtal frequency count */
+        u8 xtal_freq_count;
+};
+
+static const struct utmi_clk_param utmi_parameters[] = {
+        {
+                .osc_frequency = 13000000,
+                .enable_delay_count = 0x02,
+                .stable_count = 0x33,
+                .active_delay_count = 0x05,
+                .xtal_freq_count = 0x7F
+        },
+        {
+                .osc_frequency = 19200000,
+                .enable_delay_count = 0x03,
+                .stable_count = 0x4B,
+                .active_delay_count = 0x06,
+                .xtal_freq_count = 0xBB},
+        {
+                .osc_frequency = 12000000,
+                .enable_delay_count = 0x02,
+                .stable_count = 0x2F,
+                .active_delay_count = 0x04,
+                .xtal_freq_count = 0x76
+        },
+        {
+                .osc_frequency = 26000000,
+                .enable_delay_count = 0x04,
+                .stable_count = 0x66,
+                .active_delay_count = 0x09,
+                .xtal_freq_count = 0xFE
+        },
+        {
+                .osc_frequency = 16800000,
+                .enable_delay_count = 0x03,
+                .stable_count = 0x41,
+                .active_delay_count = 0x0A,
+                .xtal_freq_count = 0xA4
+        },
+};
+
+static void __iomem *reg_clk_base = IO_ADDRESS(TEGRA_CLK_RESET_BASE);
+static void __iomem *reg_pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
+static void __iomem *misc_gp_hidrev_base = IO_ADDRESS(TEGRA_APB_MISC_BASE);
+
+#define MISC_GP_HIDREV                  0x804
+
+/*
+ * Some peripheral clocks share an enable bit, so refcount the enable bits
+ * in registers CLK_ENABLE_L, ... CLK_ENABLE_W
+ */
+static int tegra_periph_clk_enable_refcount[CLK_OUT_ENB_NUM * 32];
+
+#define clk_writel(value, reg) \
+        __raw_writel(value, (u32)reg_clk_base + (reg))
+#define clk_readl(reg) \
+        __raw_readl((u32)reg_clk_base + (reg))
+#define pmc_writel(value, reg) \
+        __raw_writel(value, (u32)reg_pmc_base + (reg))
+#define pmc_readl(reg) \
+        __raw_readl((u32)reg_pmc_base + (reg))
+#define chipid_readl() \
+        __raw_readl((u32)misc_gp_hidrev_base + MISC_GP_HIDREV)
+
+#define clk_writel_delay(value, reg)                                    \
+        do {                                                            \
+                __raw_writel((value), (u32)reg_clk_base + (reg));       \
+                udelay(2);                                              \
+        } while (0)
+
+
+static inline int clk_set_div(struct clk *c, u32 n)
+{
+        return clk_set_rate(c, (clk_get_rate(c->parent) + n-1) / n);
+}
+
+static inline u32 periph_clk_to_reg(
+        struct clk *c, u32 reg_L, u32 reg_V, int offs)
+{
+        u32 reg = c->u.periph.clk_num / 32;
+        BUG_ON(reg >= RST_DEVICES_NUM);
+        if (reg < 3)
+                reg = reg_L + (reg * offs);
+        else
+                reg = reg_V + ((reg - 3) * offs);
+        return reg;
+}
+
+static unsigned long clk_measure_input_freq(void)
+{
+        u32 clock_autodetect;
+        clk_writel(OSC_FREQ_DET_TRIG | 1, OSC_FREQ_DET);
+        do {} while (clk_readl(OSC_FREQ_DET_STATUS) & OSC_FREQ_DET_BUSY);
+        clock_autodetect = clk_readl(OSC_FREQ_DET_STATUS);
+        if (clock_autodetect >= 732 - 3 && clock_autodetect <= 732 + 3) {
+                return 12000000;
+        } else if (clock_autodetect >= 794 - 3 && clock_autodetect <= 794 + 3) {
+                return 13000000;
+        } else if (clock_autodetect >= 1172 - 3 && clock_autodetect <= 1172 + 3) {
+                return 19200000;
+        } else if (clock_autodetect >= 1587 - 3 && clock_autodetect <= 1587 + 3) {
+                return 26000000;
+        } else if (clock_autodetect >= 1025 - 3 && clock_autodetect <= 1025 + 3) {
+                return 16800000;
+        } else if (clock_autodetect >= 2344 - 3 && clock_autodetect <= 2344 + 3) {
+                return 38400000;
+        } else if (clock_autodetect >= 2928 - 3 && clock_autodetect <= 2928 + 3) {
+                return 48000000;
+        } else {
+                pr_err("%s: Unexpected clock autodetect value %d", __func__,
+                        clock_autodetect);
+                BUG();
+                return 0;
+        }
+}
+
+static int clk_div71_get_divider(unsigned long parent_rate, unsigned long rate,
+                                 u32 flags, u32 round_mode)
+{
+        s64 divider_u71 = parent_rate;
+        if (!rate)
+                return -EINVAL;
+
+        if (!(flags & DIV_U71_INT))
+                divider_u71 *= 2;
+        if (round_mode == ROUND_DIVIDER_UP)
+                divider_u71 += rate - 1;
+        do_div(divider_u71, rate);
+        if (flags & DIV_U71_INT)
+                divider_u71 *= 2;
+
+        if (divider_u71 - 2 < 0)
+                return 0;
+
+        if (divider_u71 - 2 > 255)
+                return -EINVAL;
+
+        return divider_u71 - 2;
+}
+
+static int clk_div16_get_divider(unsigned long parent_rate, unsigned long rate)
+{
+        s64 divider_u16;
+
+        divider_u16 = parent_rate;
+        if (!rate)
+                return -EINVAL;
+        divider_u16 += rate - 1;
+        do_div(divider_u16, rate);
+
+        if (divider_u16 - 1 < 0)
+                return 0;
+
+        if (divider_u16 - 1 > 0xFFFF)
+                return -EINVAL;
+
+        return divider_u16 - 1;
+}
+
+/* clk_m functions */
+static unsigned long tegra30_clk_m_autodetect_rate(struct clk *c)
+{
+        u32 osc_ctrl = clk_readl(OSC_CTRL);
+        u32 auto_clock_control = osc_ctrl & ~OSC_CTRL_OSC_FREQ_MASK;
+        u32 pll_ref_div = osc_ctrl & OSC_CTRL_PLL_REF_DIV_MASK;
+
+        c->rate = clk_measure_input_freq();
+        switch (c->rate) {
+        case 12000000:
+                auto_clock_control |= OSC_CTRL_OSC_FREQ_12MHZ;
+                BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1);
+                break;
+        case 13000000:
+                auto_clock_control |= OSC_CTRL_OSC_FREQ_13MHZ;
+                BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1);
+                break;
+        case 19200000:
+                auto_clock_control |= OSC_CTRL_OSC_FREQ_19_2MHZ;
+                BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1);
+                break;
+        case 26000000:
+                auto_clock_control |= OSC_CTRL_OSC_FREQ_26MHZ;
+                BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1);
+                break;
+        case 16800000:
+                auto_clock_control |= OSC_CTRL_OSC_FREQ_16_8MHZ;
+                BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1);
+                break;
+        case 38400000:
+                auto_clock_control |= OSC_CTRL_OSC_FREQ_38_4MHZ;
+                BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_2);
+                break;
+        case 48000000:
+                auto_clock_control |= OSC_CTRL_OSC_FREQ_48MHZ;
+                BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_4);
+                break;
+        default:
+                pr_err("%s: Unexpected clock rate %ld", __func__, c->rate);
+                BUG();
+        }
+        clk_writel(auto_clock_control, OSC_CTRL);
+        return c->rate;
+}
+
+static void tegra30_clk_m_init(struct clk *c)
+{
+        pr_debug("%s on clock %s\n", __func__, c->name);
+        tegra30_clk_m_autodetect_rate(c);
+}
+
+static int tegra30_clk_m_enable(struct clk *c)
+{
+        pr_debug("%s on clock %s\n", __func__, c->name);
+        return 0;
+}
+
+static void tegra30_clk_m_disable(struct clk *c)
+{
+        pr_debug("%s on clock %s\n", __func__, c->name);
+        WARN(1, "Attempting to disable main SoC clock\n");
+}
+
+static struct clk_ops tegra_clk_m_ops = {
+        .init           = tegra30_clk_m_init,
+        .enable         = tegra30_clk_m_enable,
+        .disable        = tegra30_clk_m_disable,
+};
+
+static struct clk_ops tegra_clk_m_div_ops = {
+        .enable         = tegra30_clk_m_enable,
+};
+
+/* PLL reference divider functions */
+static void tegra30_pll_ref_init(struct clk *c)
+{
+        u32 pll_ref_div = clk_readl(OSC_CTRL) & OSC_CTRL_PLL_REF_DIV_MASK;
+        pr_debug("%s on clock %s\n", __func__, c->name);
+
+        switch (pll_ref_div) {
+        case OSC_CTRL_PLL_REF_DIV_1:
+                c->div = 1;
+                break;
+        case OSC_CTRL_PLL_REF_DIV_2:
+                c->div = 2;
+                break;
+        case OSC_CTRL_PLL_REF_DIV_4:
+                c->div = 4;
+                break;
+        default:
+                pr_err("%s: Invalid pll ref divider %d", __func__, pll_ref_div);
+                BUG();
+        }
+        c->mul = 1;
+        c->state = ON;
+}
+
+static struct clk_ops tegra_pll_ref_ops = {
+        .init           = tegra30_pll_ref_init,
+        .enable         = tegra30_clk_m_enable,
+        .disable        = tegra30_clk_m_disable,
+};
+
+/* super clock functions */
+/* "super clocks" on tegra30 have two-stage muxes, fractional 7.1 divider and
+ * clock skipping super divider.  We will ignore the clock skipping divider,
+ * since we can't lower the voltage when using the clock skip, but we can if
+ * we lower the PLL frequency. We will use 7.1 divider for CPU super-clock
+ * only when its parent is a fixed rate PLL, since we can't change PLL rate
+ * in this case.
+ */
+static void tegra30_super_clk_init(struct clk *c)
+{
+        u32 val;
+        int source;
+        int shift;
+        const struct clk_mux_sel *sel;
+        val = clk_readl(c->reg + SUPER_CLK_MUX);
+        c->state = ON;
+        BUG_ON(((val & SUPER_STATE_MASK) != SUPER_STATE_RUN) &&
+                ((val & SUPER_STATE_MASK) != SUPER_STATE_IDLE));
+        shift = ((val & SUPER_STATE_MASK) == SUPER_STATE_IDLE) ?
+                SUPER_IDLE_SOURCE_SHIFT : SUPER_RUN_SOURCE_SHIFT;
+        source = (val >> shift) & SUPER_SOURCE_MASK;
+        if (c->flags & DIV_2)
+                source |= val & SUPER_LP_DIV2_BYPASS;
+        for (sel = c->inputs; sel->input != NULL; sel++) {
+                if (sel->value == source)
+                        break;
+        }
+        BUG_ON(sel->input == NULL);
+        c->parent = sel->input;
+
+        if (c->flags & DIV_U71) {
+                /* Init safe 7.1 divider value (does not affect PLLX path) */
+                clk_writel(SUPER_CLOCK_DIV_U71_MIN << SUPER_CLOCK_DIV_U71_SHIFT,
+                           c->reg + SUPER_CLK_DIVIDER);
+                c->mul = 2;
+                c->div = 2;
+                if (!(c->parent->flags & PLLX))
+                        c->div += SUPER_CLOCK_DIV_U71_MIN;
+        } else
+                clk_writel(0, c->reg + SUPER_CLK_DIVIDER);
+}
+
+static int tegra30_super_clk_enable(struct clk *c)
+{
+        return 0;
+}
+
+static void tegra30_super_clk_disable(struct clk *c)
+{
+        /* since tegra 3 has 2 CPU super clocks - low power lp-mode clock and
+           geared up g-mode super clock - mode switch may request to disable
+           either of them; accept request with no affect on h/w */
+}
+
+static int tegra30_super_clk_set_parent(struct clk *c, struct clk *p)
+{
+        u32 val;
+        const struct clk_mux_sel *sel;
+        int shift;
+
+        val = clk_readl(c->reg + SUPER_CLK_MUX);
+        BUG_ON(((val & SUPER_STATE_MASK) != SUPER_STATE_RUN) &&
+                ((val & SUPER_STATE_MASK) != SUPER_STATE_IDLE));
+        shift = ((val & SUPER_STATE_MASK) == SUPER_STATE_IDLE) ?
+                SUPER_IDLE_SOURCE_SHIFT : SUPER_RUN_SOURCE_SHIFT;
+        for (sel = c->inputs; sel->input != NULL; sel++) {
+                if (sel->input == p) {
+                        /* For LP mode super-clock switch between PLLX direct
+                           and divided-by-2 outputs is allowed only when other
+                           than PLLX clock source is current parent */
+                        if ((c->flags & DIV_2) && (p->flags & PLLX) &&
+                            ((sel->value ^ val) & SUPER_LP_DIV2_BYPASS)) {
+                                if (c->parent->flags & PLLX)
+                                        return -EINVAL;
+                                val ^= SUPER_LP_DIV2_BYPASS;
+                                clk_writel_delay(val, c->reg);
+                        }
+                        val &= ~(SUPER_SOURCE_MASK << shift);
+                        val |= (sel->value & SUPER_SOURCE_MASK) << shift;
+
+                        /* 7.1 divider for CPU super-clock does not affect
+                           PLLX path */
+                        if (c->flags & DIV_U71) {
+                                u32 div = 0;
+                                if (!(p->flags & PLLX)) {
+                                        div = clk_readl(c->reg +
+                                                        SUPER_CLK_DIVIDER);
+                                        div &= SUPER_CLOCK_DIV_U71_MASK;
+                                        div >>= SUPER_CLOCK_DIV_U71_SHIFT;
+                                }
+                                c->div = div + 2;
+                                c->mul = 2;
+                        }
+
+                        if (c->refcnt)
+                                clk_enable(p);
+
+                        clk_writel_delay(val, c->reg);
+
+                        if (c->refcnt && c->parent)
+                                clk_disable(c->parent);
+
+                        clk_reparent(c, p);
+                        return 0;
+                }
+        }
+        return -EINVAL;
+}
+
+/*
+ * Do not use super clocks "skippers", since dividing using a clock skipper
+ * does not allow the voltage to be scaled down. Instead adjust the rate of
+ * the parent clock. This requires that the parent of a super clock have no
+ * other children, otherwise the rate will change underneath the other
+ * children. Special case: if fixed rate PLL is CPU super clock parent the
+ * rate of this PLL can't be changed, and it has many other children. In
+ * this case use 7.1 fractional divider to adjust the super clock rate.
+ */
+static int tegra30_super_clk_set_rate(struct clk *c, unsigned long rate)
+{
+        if ((c->flags & DIV_U71) && (c->parent->flags & PLL_FIXED)) {
+                int div = clk_div71_get_divider(c->parent->u.pll.fixed_rate,
+                                        rate, c->flags, ROUND_DIVIDER_DOWN);
+                div = max(div, SUPER_CLOCK_DIV_U71_MIN);
+
+                clk_writel(div << SUPER_CLOCK_DIV_U71_SHIFT,
+                           c->reg + SUPER_CLK_DIVIDER);
+                c->div = div + 2;
+                c->mul = 2;
+                return 0;
+        }
+        return clk_set_rate(c->parent, rate);
+}
+
+static struct clk_ops tegra_super_ops = {
+        .init                   = tegra30_super_clk_init,
+        .enable                 = tegra30_super_clk_enable,
+        .disable                = tegra30_super_clk_disable,
+        .set_parent             = tegra30_super_clk_set_parent,
+        .set_rate               = tegra30_super_clk_set_rate,
+};
+
+static int tegra30_twd_clk_set_rate(struct clk *c, unsigned long rate)
+{
+        /* The input value 'rate' is the clock rate of the CPU complex. */
+        c->rate = (rate * c->mul) / c->div;
+        return 0;
+}
+
+static struct clk_ops tegra30_twd_ops = {
+        .set_rate       = tegra30_twd_clk_set_rate,
+};
+
+/* Blink output functions */
+
+static void tegra30_blink_clk_init(struct clk *c)
+{
+        u32 val;
+
+        val = pmc_readl(PMC_CTRL);
+        c->state = (val & PMC_CTRL_BLINK_ENB) ? ON : OFF;
+        c->mul = 1;
+        val = pmc_readl(c->reg);
+
+        if (val & PMC_BLINK_TIMER_ENB) {
+                unsigned int on_off;
+
+                on_off = (val >> PMC_BLINK_TIMER_DATA_ON_SHIFT) &
+                        PMC_BLINK_TIMER_DATA_ON_MASK;
+                val >>= PMC_BLINK_TIMER_DATA_OFF_SHIFT;
+                val &= PMC_BLINK_TIMER_DATA_OFF_MASK;
+                on_off += val;
+                /* each tick in the blink timer is 4 32KHz clocks */
+                c->div = on_off * 4;
+        } else {
+                c->div = 1;
+        }
+}
+
+static int tegra30_blink_clk_enable(struct clk *c)
+{
+        u32 val;
+
+        val = pmc_readl(PMC_DPD_PADS_ORIDE);
+        pmc_writel(val | PMC_DPD_PADS_ORIDE_BLINK_ENB, PMC_DPD_PADS_ORIDE);
+
+        val = pmc_readl(PMC_CTRL);
+        pmc_writel(val | PMC_CTRL_BLINK_ENB, PMC_CTRL);
+
+        return 0;
+}
+
+static void tegra30_blink_clk_disable(struct clk *c)
+{
+        u32 val;
+
+        val = pmc_readl(PMC_CTRL);
+        pmc_writel(val & ~PMC_CTRL_BLINK_ENB, PMC_CTRL);
+
+        val = pmc_readl(PMC_DPD_PADS_ORIDE);
+        pmc_writel(val & ~PMC_DPD_PADS_ORIDE_BLINK_ENB, PMC_DPD_PADS_ORIDE);
+}
+
+static int tegra30_blink_clk_set_rate(struct clk *c, unsigned long rate)
+{
+        unsigned long parent_rate = clk_get_rate(c->parent);
+        if (rate >= parent_rate) {
+                c->div = 1;
+                pmc_writel(0, c->reg);
+        } else {
+                unsigned int on_off;
+                u32 val;
+
+                on_off = DIV_ROUND_UP(parent_rate / 8, rate);
+                c->div = on_off * 8;
+
+                val = (on_off & PMC_BLINK_TIMER_DATA_ON_MASK) <<
+                        PMC_BLINK_TIMER_DATA_ON_SHIFT;
+                on_off &= PMC_BLINK_TIMER_DATA_OFF_MASK;
+                on_off <<= PMC_BLINK_TIMER_DATA_OFF_SHIFT;
+                val |= on_off;
+                val |= PMC_BLINK_TIMER_ENB;
+                pmc_writel(val, c->reg);
+        }
+
+        return 0;
+}
+
+static struct clk_ops tegra_blink_clk_ops = {
+        .init                   = &tegra30_blink_clk_init,
+        .enable                 = &tegra30_blink_clk_enable,
+        .disable                = &tegra30_blink_clk_disable,
+        .set_rate               = &tegra30_blink_clk_set_rate,
+};
+
+/* PLL Functions */
+static int tegra30_pll_clk_wait_for_lock(struct clk *c, u32 lock_reg,
+                                         u32 lock_bit)
+{
+#if USE_PLL_LOCK_BITS
+        int i;
+        for (i = 0; i < c->u.pll.lock_delay; i++) {
+                if (clk_readl(lock_reg) & lock_bit) {
+                        udelay(PLL_POST_LOCK_DELAY);
+                        return 0;
+                }
+                udelay(2);              /* timeout = 2 * lock time */
+        }
+        pr_err("Timed out waiting for lock bit on pll %s", c->name);
+        return -1;
+#endif
+        udelay(c->u.pll.lock_delay);
+
+        return 0;
+}
+
+
+static void tegra30_utmi_param_configure(struct clk *c)
+{
+        u32 reg;
+        int i;
+        unsigned long main_rate =
+                clk_get_rate(c->parent->parent);
+
+        for (i = 0; i < ARRAY_SIZE(utmi_parameters); i++) {
+                if (main_rate == utmi_parameters[i].osc_frequency)
+                        break;
+        }
+
+        if (i >= ARRAY_SIZE(utmi_parameters)) {
+                pr_err("%s: Unexpected main rate %lu\n", __func__, main_rate);
+                return;
+        }
+
+        reg = clk_readl(UTMIP_PLL_CFG2);
+
+        /* Program UTMIP PLL stable and active counts */
+        /* [FIXME] arclk_rst.h says WRONG! This should be 1ms -> 0x50 Check! */
+        reg &= ~UTMIP_PLL_CFG2_STABLE_COUNT(~0);
+        reg |= UTMIP_PLL_CFG2_STABLE_COUNT(
+                        utmi_parameters[i].stable_count);
+
+        reg &= ~UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(~0);
+
+        reg |= UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(
+                        utmi_parameters[i].active_delay_count);
+
+        /* Remove power downs from UTMIP PLL control bits */
+        reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN;
+        reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN;
+        reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN;
+
+        clk_writel(reg, UTMIP_PLL_CFG2);
+
+        /* Program UTMIP PLL delay and oscillator frequency counts */
+        reg = clk_readl(UTMIP_PLL_CFG1);
+        reg &= ~UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(~0);
+
+        reg |= UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(
+                utmi_parameters[i].enable_delay_count);
+
+        reg &= ~UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(~0);
+        reg |= UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(
+                utmi_parameters[i].xtal_freq_count);
+
+        /* Remove power downs from UTMIP PLL control bits */
+        reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN;
+        reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN;
+        reg &= ~UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN;
+
+        clk_writel(reg, UTMIP_PLL_CFG1);
+}
+
+static void tegra30_pll_clk_init(struct clk *c)
+{
+        u32 val = clk_readl(c->reg + PLL_BASE);
+
+        c->state = (val & PLL_BASE_ENABLE) ? ON : OFF;
+
+        if (c->flags & PLL_FIXED && !(val & PLL_BASE_OVERRIDE)) {
+                const struct clk_pll_freq_table *sel;
+                unsigned long input_rate = clk_get_rate(c->parent);
+                for (sel = c->u.pll.freq_table; sel->input_rate != 0; sel++) {
+                        if (sel->input_rate == input_rate &&
+                                sel->output_rate == c->u.pll.fixed_rate) {
+                                c->mul = sel->n;
+                                c->div = sel->m * sel->p;
+                                return;
+                        }
+                }
+                pr_err("Clock %s has unknown fixed frequency\n", c->name);
+                BUG();
+        } else if (val & PLL_BASE_BYPASS) {
+                c->mul = 1;
+                c->div = 1;
+        } else {
+                c->mul = (val & PLL_BASE_DIVN_MASK) >> PLL_BASE_DIVN_SHIFT;
+                c->div = (val & PLL_BASE_DIVM_MASK) >> PLL_BASE_DIVM_SHIFT;
+                if (c->flags & PLLU)
+                        c->div *= (val & PLLU_BASE_POST_DIV) ? 1 : 2;
+                else
+                        c->div *= (0x1 << ((val & PLL_BASE_DIVP_MASK) >>
+                                        PLL_BASE_DIVP_SHIFT));
+                if (c->flags & PLL_FIXED) {
+                        unsigned long rate = clk_get_rate_locked(c);
+                        BUG_ON(rate != c->u.pll.fixed_rate);
+                }
+        }
+
+        if (c->flags & PLLU)
+                tegra30_utmi_param_configure(c);
+}
+
+static int tegra30_pll_clk_enable(struct clk *c)
+{
+        u32 val;
+        pr_debug("%s on clock %s\n", __func__, c->name);
+
+#if USE_PLL_LOCK_BITS
+        val = clk_readl(c->reg + PLL_MISC(c));
+        val |= PLL_MISC_LOCK_ENABLE(c);
+        clk_writel(val, c->reg + PLL_MISC(c));
+#endif
+        val = clk_readl(c->reg + PLL_BASE);
+        val &= ~PLL_BASE_BYPASS;
+        val |= PLL_BASE_ENABLE;
+        clk_writel(val, c->reg + PLL_BASE);
+
+        if (c->flags & PLLM) {
+                val = pmc_readl(PMC_PLLP_WB0_OVERRIDE);
+                val |= PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE;
+                pmc_writel(val, PMC_PLLP_WB0_OVERRIDE);
+        }
+
+        tegra30_pll_clk_wait_for_lock(c, c->reg + PLL_BASE, PLL_BASE_LOCK);
+
+        return 0;
+}
+
+static void tegra30_pll_clk_disable(struct clk *c)
+{
+        u32 val;
+        pr_debug("%s on clock %s\n", __func__, c->name);
+
+        val = clk_readl(c->reg);
+        val &= ~(PLL_BASE_BYPASS | PLL_BASE_ENABLE);
+        clk_writel(val, c->reg);
+
+        if (c->flags & PLLM) {
+                val = pmc_readl(PMC_PLLP_WB0_OVERRIDE);
+                val &= ~PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE;
+                pmc_writel(val, PMC_PLLP_WB0_OVERRIDE);
+        }
+}
+
+static int tegra30_pll_clk_set_rate(struct clk *c, unsigned long rate)
+{
+        u32 val, p_div, old_base;
+        unsigned long input_rate;
+        const struct clk_pll_freq_table *sel;
+        struct clk_pll_freq_table cfg;
+
+        pr_debug("%s: %s %lu\n", __func__, c->name, rate);
+
+        if (c->flags & PLL_FIXED) {
+                int ret = 0;
+                if (rate != c->u.pll.fixed_rate) {
+                        pr_err("%s: Can not change %s fixed rate %lu to %lu\n",
+                               __func__, c->name, c->u.pll.fixed_rate, rate);
+                        ret = -EINVAL;
+                }
+                return ret;
+        }
+
+        if (c->flags & PLLM) {
+                if (rate != clk_get_rate_locked(c)) {
+                        pr_err("%s: Can not change memory %s rate in flight\n",
+                               __func__, c->name);
+                        return -EINVAL;
+                }
+                return 0;
+        }
+
+        p_div = 0;
+        input_rate = clk_get_rate(c->parent);
+
+        /* Check if the target rate is tabulated */
+        for (sel = c->u.pll.freq_table; sel->input_rate != 0; sel++) {
+                if (sel->input_rate == input_rate && sel->output_rate == rate) {
+                        if (c->flags & PLLU) {
+                                BUG_ON(sel->p < 1 || sel->p > 2);
+                                if (sel->p == 1)
+                                        p_div = PLLU_BASE_POST_DIV;
+                        } else {
+                                BUG_ON(sel->p < 1);
+                                for (val = sel->p; val > 1; val >>= 1)
+                                        p_div++;
+                                p_div <<= PLL_BASE_DIVP_SHIFT;
+                        }
+                        break;
+                }
+        }
+
+        /* Configure out-of-table rate */
+        if (sel->input_rate == 0) {
+                unsigned long cfreq;
+                BUG_ON(c->flags & PLLU);
+                sel = &cfg;
+
+                switch (input_rate) {
+                case 12000000:
+                case 26000000:
+                        cfreq = (rate <= 1000000 * 1000) ? 1000000 : 2000000;
+                        break;
+                case 13000000:
+                        cfreq = (rate <= 1000000 * 1000) ? 1000000 : 2600000;
+                        break;
+                case 16800000:
+                case 19200000:
+                        cfreq = (rate <= 1200000 * 1000) ? 1200000 : 2400000;
+                        break;
+                default:
+                        pr_err("%s: Unexpected reference rate %lu\n",
+                               __func__, input_rate);
+                        BUG();
+                }
+
+                /* Raise VCO to guarantee 0.5% accuracy */
+                for (cfg.output_rate = rate; cfg.output_rate < 200 * cfreq;
+                      cfg.output_rate <<= 1)
+                        p_div++;
+
+                cfg.p = 0x1 << p_div;
+                cfg.m = input_rate / cfreq;
+                cfg.n = cfg.output_rate / cfreq;
+                cfg.cpcon = OUT_OF_TABLE_CPCON;
+
+                if ((cfg.m > (PLL_BASE_DIVM_MASK >> PLL_BASE_DIVM_SHIFT)) ||
+                    (cfg.n > (PLL_BASE_DIVN_MASK >> PLL_BASE_DIVN_SHIFT)) ||
+                    (p_div > (PLL_BASE_DIVP_MASK >> PLL_BASE_DIVP_SHIFT)) ||
+                    (cfg.output_rate > c->u.pll.vco_max)) {
+                        pr_err("%s: Failed to set %s out-of-table rate %lu\n",
+                               __func__, c->name, rate);
+                        return -EINVAL;
+                }
+                p_div <<= PLL_BASE_DIVP_SHIFT;
+        }
+
+        c->mul = sel->n;
+        c->div = sel->m * sel->p;
+
+        old_base = val = clk_readl(c->reg + PLL_BASE);
+        val &= ~(PLL_BASE_DIVM_MASK | PLL_BASE_DIVN_MASK |
+                 ((c->flags & PLLU) ? PLLU_BASE_POST_DIV : PLL_BASE_DIVP_MASK));
+        val |= (sel->m << PLL_BASE_DIVM_SHIFT) |
+                (sel->n << PLL_BASE_DIVN_SHIFT) | p_div;
+        if (val == old_base)
+                return 0;
+
+        if (c->state == ON) {
+                tegra30_pll_clk_disable(c);
+                val &= ~(PLL_BASE_BYPASS | PLL_BASE_ENABLE);
+        }
+        clk_writel(val, c->reg + PLL_BASE);
+
+        if (c->flags & PLL_HAS_CPCON) {
+                val = clk_readl(c->reg + PLL_MISC(c));
+                val &= ~PLL_MISC_CPCON_MASK;
+                val |= sel->cpcon << PLL_MISC_CPCON_SHIFT;
+                if (c->flags & (PLLU | PLLD)) {
+                        val &= ~PLL_MISC_LFCON_MASK;
+                        if (sel->n >= PLLDU_LFCON_SET_DIVN)
+                                val |= 0x1 << PLL_MISC_LFCON_SHIFT;
+                } else if (c->flags & (PLLX | PLLM)) {
+                        val &= ~(0x1 << PLL_MISC_DCCON_SHIFT);
+                        if (rate >= (c->u.pll.vco_max >> 1))
+                                val |= 0x1 << PLL_MISC_DCCON_SHIFT;
+                }
+                clk_writel(val, c->reg + PLL_MISC(c));
+        }
+
+        if (c->state == ON)
+                tegra30_pll_clk_enable(c);
+
+        return 0;
+}
+
+static struct clk_ops tegra_pll_ops = {
+        .init                   = tegra30_pll_clk_init,
+        .enable                 = tegra30_pll_clk_enable,
+        .disable                = tegra30_pll_clk_disable,
+        .set_rate               = tegra30_pll_clk_set_rate,
+};
+
+static int
+tegra30_plld_clk_cfg_ex(struct clk *c, enum tegra_clk_ex_param p, u32 setting)
+{
+        u32 val, mask, reg;
+
+        switch (p) {
+        case TEGRA_CLK_PLLD_CSI_OUT_ENB:
+                mask = PLLD_BASE_CSI_CLKENABLE;
+                reg = c->reg + PLL_BASE;
+                break;
+        case TEGRA_CLK_PLLD_DSI_OUT_ENB:
+                mask = PLLD_MISC_DSI_CLKENABLE;
+                reg = c->reg + PLL_MISC(c);
+                break;
+        case TEGRA_CLK_PLLD_MIPI_MUX_SEL:
+                if (!(c->flags & PLL_ALT_MISC_REG)) {
+                        mask = PLLD_BASE_DSIB_MUX_MASK;
+                        reg = c->reg + PLL_BASE;
+                        break;
+                }
+        /* fall through - error since PLLD2 does not have MUX_SEL control */
+        default:
+                return -EINVAL;
+        }
+
+        val = clk_readl(reg);
+        if (setting)
+                val |= mask;
+        else
+                val &= ~mask;
+        clk_writel(val, reg);
+        return 0;
+}
+
+static struct clk_ops tegra_plld_ops = {
+        .init                   = tegra30_pll_clk_init,
+        .enable                 = tegra30_pll_clk_enable,
+        .disable                = tegra30_pll_clk_disable,
+        .set_rate               = tegra30_pll_clk_set_rate,
+        .clk_cfg_ex             = tegra30_plld_clk_cfg_ex,
+};
+
+static void tegra30_plle_clk_init(struct clk *c)
+{
+        u32 val;
+
+        val = clk_readl(PLLE_AUX);
+        c->parent = (val & PLLE_AUX_PLLP_SEL) ?
+                tegra_get_clock_by_name("pll_p") :
+                tegra_get_clock_by_name("pll_ref");
+
+        val = clk_readl(c->reg + PLL_BASE);
+        c->state = (val & PLLE_BASE_ENABLE) ? ON : OFF;
+        c->mul = (val & PLLE_BASE_DIVN_MASK) >> PLLE_BASE_DIVN_SHIFT;
+        c->div = (val & PLLE_BASE_DIVM_MASK) >> PLLE_BASE_DIVM_SHIFT;
+        c->div *= (val & PLLE_BASE_DIVP_MASK) >> PLLE_BASE_DIVP_SHIFT;
+}
+
+static void tegra30_plle_clk_disable(struct clk *c)
+{
+        u32 val;
+        pr_debug("%s on clock %s\n", __func__, c->name);
+
+        val = clk_readl(c->reg + PLL_BASE);
+        val &= ~(PLLE_BASE_CML_ENABLE | PLLE_BASE_ENABLE);
+        clk_writel(val, c->reg + PLL_BASE);
+}
+
+static void tegra30_plle_training(struct clk *c)
+{
+        u32 val;
+
+        /* PLLE is already disabled, and setup cleared;
+         * create falling edge on PLLE IDDQ input */
+        val = pmc_readl(PMC_SATA_PWRGT);
+        val |= PMC_SATA_PWRGT_PLLE_IDDQ_VALUE;
+        pmc_writel(val, PMC_SATA_PWRGT);
+
+        val = pmc_readl(PMC_SATA_PWRGT);
+        val |= PMC_SATA_PWRGT_PLLE_IDDQ_SWCTL;
+        pmc_writel(val, PMC_SATA_PWRGT);
+
+        val = pmc_readl(PMC_SATA_PWRGT);
+        val &= ~PMC_SATA_PWRGT_PLLE_IDDQ_VALUE;
+        pmc_writel(val, PMC_SATA_PWRGT);
+
+        do {
+                val = clk_readl(c->reg + PLL_MISC(c));
+        } while (!(val & PLLE_MISC_READY));
+}
+
+static int tegra30_plle_configure(struct clk *c, bool force_training)
+{
+        u32 val;
+        const struct clk_pll_freq_table *sel;
+        unsigned long rate = c->u.pll.fixed_rate;
+        unsigned long input_rate = clk_get_rate(c->parent);
+
+        for (sel = c->u.pll.freq_table; sel->input_rate != 0; sel++) {
+                if (sel->input_rate == input_rate && sel->output_rate == rate)
+                        break;
+        }
+
+        if (sel->input_rate == 0)
+                return -ENOSYS;
+
+        /* disable PLLE, clear setup fiels */
+        tegra30_plle_clk_disable(c);
+
+        val = clk_readl(c->reg + PLL_MISC(c));
+        val &= ~(PLLE_MISC_LOCK_ENABLE | PLLE_MISC_SETUP_MASK);
+        clk_writel(val, c->reg + PLL_MISC(c));
+
+        /* training */
+        val = clk_readl(c->reg + PLL_MISC(c));
+        if (force_training || (!(val & PLLE_MISC_READY)))
+                tegra30_plle_training(c);
+
+        /* configure dividers, setup, disable SS */
+        val = clk_readl(c->reg + PLL_BASE);
+        val &= ~PLLE_BASE_DIV_MASK;
+        val |= PLLE_BASE_DIV(sel->m, sel->n, sel->p, sel->cpcon);
+        clk_writel(val, c->reg + PLL_BASE);
+        c->mul = sel->n;
+        c->div = sel->m * sel->p;
+
+        val = clk_readl(c->reg + PLL_MISC(c));
+        val |= PLLE_MISC_SETUP_VALUE;
+        val |= PLLE_MISC_LOCK_ENABLE;
+        clk_writel(val, c->reg + PLL_MISC(c));
+
+        val = clk_readl(PLLE_SS_CTRL);
+        val |= PLLE_SS_DISABLE;
+        clk_writel(val, PLLE_SS_CTRL);
+
+        /* enable and lock PLLE*/
+        val = clk_readl(c->reg + PLL_BASE);
+        val |= (PLLE_BASE_CML_ENABLE | PLLE_BASE_ENABLE);
+        clk_writel(val, c->reg + PLL_BASE);
+
+        tegra30_pll_clk_wait_for_lock(c, c->reg + PLL_MISC(c), PLLE_MISC_LOCK);
+
+        return 0;
+}
+
+static int tegra30_plle_clk_enable(struct clk *c)
+{
+        pr_debug("%s on clock %s\n", __func__, c->name);
+        return tegra30_plle_configure(c, !c->set);
+}
+
+static struct clk_ops tegra_plle_ops = {
+        .init                   = tegra30_plle_clk_init,
+        .enable                 = tegra30_plle_clk_enable,
+        .disable                = tegra30_plle_clk_disable,
+};
+
+/* Clock divider ops */
+static void tegra30_pll_div_clk_init(struct clk *c)
+{
+        if (c->flags & DIV_U71) {
+                u32 divu71;
+                u32 val = clk_readl(c->reg);
+                val >>= c->reg_shift;
+                c->state = (val & PLL_OUT_CLKEN) ? ON : OFF;
+                if (!(val & PLL_OUT_RESET_DISABLE))
+                        c->state = OFF;
+
+                divu71 = (val & PLL_OUT_RATIO_MASK) >> PLL_OUT_RATIO_SHIFT;
+                c->div = (divu71 + 2);
+                c->mul = 2;
+        } else if (c->flags & DIV_2) {
+                c->state = ON;
+                if (c->flags & (PLLD | PLLX)) {
+                        c->div = 2;
+                        c->mul = 1;
+                } else
+                        BUG();
+        } else {
+                c->state = ON;
+                c->div = 1;
+                c->mul = 1;
+        }
+}
+
+static int tegra30_pll_div_clk_enable(struct clk *c)
+{
+        u32 val;
+        u32 new_val;
+
+        pr_debug("%s: %s\n", __func__, c->name);
+        if (c->flags & DIV_U71) {
+                val = clk_readl(c->reg);
+                new_val = val >> c->reg_shift;
+                new_val &= 0xFFFF;
+
+                new_val |= PLL_OUT_CLKEN | PLL_OUT_RESET_DISABLE;
+
+                val &= ~(0xFFFF << c->reg_shift);
+                val |= new_val << c->reg_shift;
+                clk_writel_delay(val, c->reg);
+                return 0;
+        } else if (c->flags & DIV_2) {
+                return 0;
+        }
+        return -EINVAL;
+}
+
+static void tegra30_pll_div_clk_disable(struct clk *c)
+{
+        u32 val;
+        u32 new_val;
+
+        pr_debug("%s: %s\n", __func__, c->name);
+        if (c->flags & DIV_U71) {
+                val = clk_readl(c->reg);
+                new_val = val >> c->reg_shift;
+                new_val &= 0xFFFF;
+
+                new_val &= ~(PLL_OUT_CLKEN | PLL_OUT_RESET_DISABLE);
+
+                val &= ~(0xFFFF << c->reg_shift);
+                val |= new_val << c->reg_shift;
+                clk_writel_delay(val, c->reg);
+        }
+}
+
+static int tegra30_pll_div_clk_set_rate(struct clk *c, unsigned long rate)
+{
+        u32 val;
+        u32 new_val;
+        int divider_u71;
+        unsigned long parent_rate = clk_get_rate(c->parent);
+
+        pr_debug("%s: %s %lu\n", __func__, c->name, rate);
+        if (c->flags & DIV_U71) {
+                divider_u71 = clk_div71_get_divider(
+                        parent_rate, rate, c->flags, ROUND_DIVIDER_UP);
+                if (divider_u71 >= 0) {
+                        val = clk_readl(c->reg);
+                        new_val = val >> c->reg_shift;
+                        new_val &= 0xFFFF;
+                        if (c->flags & DIV_U71_FIXED)
+                                new_val |= PLL_OUT_OVERRIDE;
+                        new_val &= ~PLL_OUT_RATIO_MASK;
+                        new_val |= divider_u71 << PLL_OUT_RATIO_SHIFT;
+
+                        val &= ~(0xFFFF << c->reg_shift);
+                        val |= new_val << c->reg_shift;
+                        clk_writel_delay(val, c->reg);
+                        c->div = divider_u71 + 2;
+                        c->mul = 2;
+                        return 0;
+                }
+        } else if (c->flags & DIV_2)
+                return clk_set_rate(c->parent, rate * 2);
+
+        return -EINVAL;
+}
+
+static long tegra30_pll_div_clk_round_rate(struct clk *c, unsigned long rate)
+{
+        int divider;
+        unsigned long parent_rate = clk_get_rate(c->parent);
+        pr_debug("%s: %s %lu\n", __func__, c->name, rate);
+
+        if (c->flags & DIV_U71) {
+                divider = clk_div71_get_divider(
+                        parent_rate, rate, c->flags, ROUND_DIVIDER_UP);
+                if (divider < 0)
+                        return divider;
+                return DIV_ROUND_UP(parent_rate * 2, divider + 2);
+        } else if (c->flags & DIV_2)
+                /* no rounding - fixed DIV_2 dividers pass rate to parent PLL */
+                return rate;
+
+        return -EINVAL;
+}
+
+static struct clk_ops tegra_pll_div_ops = {
+        .init                   = tegra30_pll_div_clk_init,
+        .enable                 = tegra30_pll_div_clk_enable,
+        .disable                = tegra30_pll_div_clk_disable,
+        .set_rate               = tegra30_pll_div_clk_set_rate,
+        .round_rate             = tegra30_pll_div_clk_round_rate,
+};
+
+/* Periph clk ops */
+static inline u32 periph_clk_source_mask(struct clk *c)
+{
+        if (c->flags & MUX8)
+                return 7 << 29;
+        else if (c->flags & MUX_PWM)
+                return 3 << 28;
+        else if (c->flags & MUX_CLK_OUT)
+                return 3 << (c->u.periph.clk_num + 4);
+        else if (c->flags & PLLD)
+                return PLLD_BASE_DSIB_MUX_MASK;
+        else
+                return 3 << 30;
+}
+
+static inline u32 periph_clk_source_shift(struct clk *c)
+{
+        if (c->flags & MUX8)
+                return 29;
+        else if (c->flags & MUX_PWM)
+                return 28;
+        else if (c->flags & MUX_CLK_OUT)
+                return c->u.periph.clk_num + 4;
+        else if (c->flags & PLLD)
+                return PLLD_BASE_DSIB_MUX_SHIFT;
+        else
+                return 30;
+}
+
+static void tegra30_periph_clk_init(struct clk *c)
+{
+        u32 val = clk_readl(c->reg);
+        const struct clk_mux_sel *mux = 0;
+        const struct clk_mux_sel *sel;
+        if (c->flags & MUX) {
+                for (sel = c->inputs; sel->input != NULL; sel++) {
+                        if (((val & periph_clk_source_mask(c)) >>
+                            periph_clk_source_shift(c)) == sel->value)
+                                mux = sel;
+                }
+                BUG_ON(!mux);
+
+                c->parent = mux->input;
+        } else {
+                c->parent = c->inputs[0].input;
+        }
+
+        if (c->flags & DIV_U71) {
+                u32 divu71 = val & PERIPH_CLK_SOURCE_DIVU71_MASK;
+                if ((c->flags & DIV_U71_UART) &&
+                    (!(val & PERIPH_CLK_UART_DIV_ENB))) {
+                        divu71 = 0;
+                }
+                if (c->flags & DIV_U71_IDLE) {
+                        val &= ~(PERIPH_CLK_SOURCE_DIVU71_MASK <<
+                                PERIPH_CLK_SOURCE_DIVIDLE_SHIFT);
+                        val |= (PERIPH_CLK_SOURCE_DIVIDLE_VAL <<
+                                PERIPH_CLK_SOURCE_DIVIDLE_SHIFT);
+                        clk_writel(val, c->reg);
+                }
+                c->div = divu71 + 2;
+                c->mul = 2;
+        } else if (c->flags & DIV_U16) {
+                u32 divu16 = val & PERIPH_CLK_SOURCE_DIVU16_MASK;
+                c->div = divu16 + 1;
+                c->mul = 1;
+        } else {
+                c->div = 1;
+                c->mul = 1;
+        }
+
+        c->state = ON;
+        if (!(clk_readl(PERIPH_CLK_TO_ENB_REG(c)) & PERIPH_CLK_TO_BIT(c)))
+                c->state = OFF;
+        if (!(c->flags & PERIPH_NO_RESET))
+                if (clk_readl(PERIPH_CLK_TO_RST_REG(c)) & PERIPH_CLK_TO_BIT(c))
+                        c->state = OFF;
+}
+
+static int tegra30_periph_clk_enable(struct clk *c)
+{
+        pr_debug("%s on clock %s\n", __func__, c->name);
+
+        tegra_periph_clk_enable_refcount[c->u.periph.clk_num]++;
+        if (tegra_periph_clk_enable_refcount[c->u.periph.clk_num] > 1)
+                return 0;
+
+        clk_writel_delay(PERIPH_CLK_TO_BIT(c), PERIPH_CLK_TO_ENB_SET_REG(c));
+        if (!(c->flags & PERIPH_NO_RESET) &&
+                 !(c->flags & PERIPH_MANUAL_RESET)) {
+                if (clk_readl(PERIPH_CLK_TO_RST_REG(c)) &
+                         PERIPH_CLK_TO_BIT(c)) {
+                        udelay(5);      /* reset propagation delay */
+                        clk_writel(PERIPH_CLK_TO_BIT(c),
+                                 PERIPH_CLK_TO_RST_CLR_REG(c));
+                }
+        }
+        return 0;
+}
+
+static void tegra30_periph_clk_disable(struct clk *c)
+{
+        unsigned long val;
+        pr_debug("%s on clock %s\n", __func__, c->name);
+
+        if (c->refcnt)
+                tegra_periph_clk_enable_refcount[c->u.periph.clk_num]--;
+
+        if (tegra_periph_clk_enable_refcount[c->u.periph.clk_num] == 0) {
+                /* If peripheral is in the APB bus then read the APB bus to
+                 * flush the write operation in apb bus. This will avoid the
+                 * peripheral access after disabling clock*/
+                if (c->flags & PERIPH_ON_APB)
+                        val = chipid_readl();
+
+                clk_writel_delay(
+                        PERIPH_CLK_TO_BIT(c), PERIPH_CLK_TO_ENB_CLR_REG(c));
+        }
+}
+
+static void tegra30_periph_clk_reset(struct clk *c, bool assert)
+{
+        unsigned long val;
+        pr_debug("%s %s on clock %s\n", __func__,
+                 assert ? "assert" : "deassert", c->name);
+
+        if (!(c->flags & PERIPH_NO_RESET)) {
+                if (assert) {
+                        /* If peripheral is in the APB bus then read the APB
+                         * bus to flush the write operation in apb bus. This
+                         * will avoid the peripheral access after disabling
+                         * clock */
+                        if (c->flags & PERIPH_ON_APB)
+                                val = chipid_readl();
+
+                        clk_writel(PERIPH_CLK_TO_BIT(c),
+                                   PERIPH_CLK_TO_RST_SET_REG(c));
+                } else
+                        clk_writel(PERIPH_CLK_TO_BIT(c),
+                                   PERIPH_CLK_TO_RST_CLR_REG(c));
+        }
+}
+
+static int tegra30_periph_clk_set_parent(struct clk *c, struct clk *p)
+{
+        u32 val;
+        const struct clk_mux_sel *sel;
+        pr_debug("%s: %s %s\n", __func__, c->name, p->name);
+
+        if (!(c->flags & MUX))
+                return (p == c->parent) ? 0 : (-EINVAL);
+
+        for (sel = c->inputs; sel->input != NULL; sel++) {
+                if (sel->input == p) {
+                        val = clk_readl(c->reg);
+                        val &= ~periph_clk_source_mask(c);
+                        val |= (sel->value << periph_clk_source_shift(c));
+
+                        if (c->refcnt)
+                                clk_enable(p);
+
+                        clk_writel_delay(val, c->reg);
+
+                        if (c->refcnt && c->parent)
+                                clk_disable(c->parent);
+
+                        clk_reparent(c, p);
+                        return 0;
+                }
+        }
+
+        return -EINVAL;
+}
+
+static int tegra30_periph_clk_set_rate(struct clk *c, unsigned long rate)
+{
+        u32 val;
+        int divider;
+        unsigned long parent_rate = clk_get_rate(c->parent);
+
+        if (c->flags & DIV_U71) {
+                divider = clk_div71_get_divider(
+                        parent_rate, rate, c->flags, ROUND_DIVIDER_UP);
+                if (divider >= 0) {
+                        val = clk_readl(c->reg);
+                        val &= ~PERIPH_CLK_SOURCE_DIVU71_MASK;
+                        val |= divider;
+                        if (c->flags & DIV_U71_UART) {
+                                if (divider)
+                                        val |= PERIPH_CLK_UART_DIV_ENB;
+                                else
+                                        val &= ~PERIPH_CLK_UART_DIV_ENB;
+                        }
+                        clk_writel_delay(val, c->reg);
+                        c->div = divider + 2;
+                        c->mul = 2;
+                        return 0;
+                }
+        } else if (c->flags & DIV_U16) {
+                divider = clk_div16_get_divider(parent_rate, rate);
+                if (divider >= 0) {
+                        val = clk_readl(c->reg);
+                        val &= ~PERIPH_CLK_SOURCE_DIVU16_MASK;
+                        val |= divider;
+                        clk_writel_delay(val, c->reg);
+                        c->div = divider + 1;
+                        c->mul = 1;
+                        return 0;
+                }
+        } else if (parent_rate <= rate) {
+                c->div = 1;
+                c->mul = 1;
+                return 0;
+        }
+        return -EINVAL;
+}
+
+static long tegra30_periph_clk_round_rate(struct clk *c,
+        unsigned long rate)
+{
+        int divider;
+        unsigned long parent_rate = clk_get_rate(c->parent);
+        pr_debug("%s: %s %lu\n", __func__, c->name, rate);
+
+        if (c->flags & DIV_U71) {
+                divider = clk_div71_get_divider(
+                        parent_rate, rate, c->flags, ROUND_DIVIDER_UP);
+                if (divider < 0)
+                        return divider;
+
+                return DIV_ROUND_UP(parent_rate * 2, divider + 2);
+        } else if (c->flags & DIV_U16) {
+                divider = clk_div16_get_divider(parent_rate, rate);
+                if (divider < 0)
+                        return divider;
+                return DIV_ROUND_UP(parent_rate, divider + 1);
+        }
+        return -EINVAL;
+}
+
+static struct clk_ops tegra_periph_clk_ops = {
+        .init                   = &tegra30_periph_clk_init,
+        .enable                 = &tegra30_periph_clk_enable,
+        .disable                = &tegra30_periph_clk_disable,
+        .set_parent             = &tegra30_periph_clk_set_parent,
+        .set_rate               = &tegra30_periph_clk_set_rate,
+        .round_rate             = &tegra30_periph_clk_round_rate,
+        .reset                  = &tegra30_periph_clk_reset,
+};
+
+
+/* Periph extended clock configuration ops */
+static int
+tegra30_vi_clk_cfg_ex(struct clk *c, enum tegra_clk_ex_param p, u32 setting)
+{
+        if (p == TEGRA_CLK_VI_INP_SEL) {
+                u32 val = clk_readl(c->reg);
+                val &= ~PERIPH_CLK_VI_SEL_EX_MASK;
+                val |= (setting << PERIPH_CLK_VI_SEL_EX_SHIFT) &
+                        PERIPH_CLK_VI_SEL_EX_MASK;
+                clk_writel(val, c->reg);
+                return 0;
+        }
+        return -EINVAL;
+}
+
+static struct clk_ops tegra_vi_clk_ops = {
+        .init                   = &tegra30_periph_clk_init,
+        .enable                 = &tegra30_periph_clk_enable,
+        .disable                = &tegra30_periph_clk_disable,
+        .set_parent             = &tegra30_periph_clk_set_parent,
+        .set_rate               = &tegra30_periph_clk_set_rate,
+        .round_rate             = &tegra30_periph_clk_round_rate,
+        .clk_cfg_ex             = &tegra30_vi_clk_cfg_ex,
+        .reset                  = &tegra30_periph_clk_reset,
+};
+
+static int
+tegra30_nand_clk_cfg_ex(struct clk *c, enum tegra_clk_ex_param p, u32 setting)
+{
+        if (p == TEGRA_CLK_NAND_PAD_DIV2_ENB) {
+                u32 val = clk_readl(c->reg);
+                if (setting)
+                        val |= PERIPH_CLK_NAND_DIV_EX_ENB;
+                else
+                        val &= ~PERIPH_CLK_NAND_DIV_EX_ENB;
+                clk_writel(val, c->reg);
+                return 0;
+        }
+        return -EINVAL;
+}
+
+static struct clk_ops tegra_nand_clk_ops = {
+        .init                   = &tegra30_periph_clk_init,
+        .enable                 = &tegra30_periph_clk_enable,
+        .disable                = &tegra30_periph_clk_disable,
+        .set_parent             = &tegra30_periph_clk_set_parent,
+        .set_rate               = &tegra30_periph_clk_set_rate,
+        .round_rate             = &tegra30_periph_clk_round_rate,
+        .clk_cfg_ex             = &tegra30_nand_clk_cfg_ex,
+        .reset                  = &tegra30_periph_clk_reset,
+};
+
+
+static int
+tegra30_dtv_clk_cfg_ex(struct clk *c, enum tegra_clk_ex_param p, u32 setting)
+{
+        if (p == TEGRA_CLK_DTV_INVERT) {
+                u32 val = clk_readl(c->reg);
+                if (setting)
+                        val |= PERIPH_CLK_DTV_POLARITY_INV;
+                else
+                        val &= ~PERIPH_CLK_DTV_POLARITY_INV;
+                clk_writel(val, c->reg);
+                return 0;
+        }
+        return -EINVAL;
+}
+
+static struct clk_ops tegra_dtv_clk_ops = {
+        .init                   = &tegra30_periph_clk_init,
+        .enable                 = &tegra30_periph_clk_enable,
+        .disable                = &tegra30_periph_clk_disable,
+        .set_parent             = &tegra30_periph_clk_set_parent,
+        .set_rate               = &tegra30_periph_clk_set_rate,
+        .round_rate             = &tegra30_periph_clk_round_rate,
+        .clk_cfg_ex             = &tegra30_dtv_clk_cfg_ex,
+        .reset                  = &tegra30_periph_clk_reset,
+};
+
+static int tegra30_dsib_clk_set_parent(struct clk *c, struct clk *p)
+{
+        const struct clk_mux_sel *sel;
+        struct clk *d = tegra_get_clock_by_name("pll_d");
+
+        pr_debug("%s: %s %s\n", __func__, c->name, p->name);
+
+        for (sel = c->inputs; sel->input != NULL; sel++) {
+                if (sel->input == p) {
+                        if (c->refcnt)
+                                clk_enable(p);
+
+                        /* The DSIB parent selection bit is in PLLD base
+                           register - can not do direct r-m-w, must be
+                           protected by PLLD lock */
+                        tegra_clk_cfg_ex(
+                                d, TEGRA_CLK_PLLD_MIPI_MUX_SEL, sel->value);
+
+                        if (c->refcnt && c->parent)
+                                clk_disable(c->parent);
+
+                        clk_reparent(c, p);
+                        return 0;
+                }
+        }
+
+        return -EINVAL;
+}
+
+static struct clk_ops tegra_dsib_clk_ops = {
+        .init                   = &tegra30_periph_clk_init,
+        .enable                 = &tegra30_periph_clk_enable,
+        .disable                = &tegra30_periph_clk_disable,
+        .set_parent             = &tegra30_dsib_clk_set_parent,
+        .set_rate               = &tegra30_periph_clk_set_rate,
+        .round_rate             = &tegra30_periph_clk_round_rate,
+        .reset                  = &tegra30_periph_clk_reset,
+};
+
+/* pciex clock support only reset function */
+static struct clk_ops tegra_pciex_clk_ops = {
+        .reset    = tegra30_periph_clk_reset,
+};
+
+/* Output clock ops */
+
+static DEFINE_SPINLOCK(clk_out_lock);
+
+static void tegra30_clk_out_init(struct clk *c)
+{
+        const struct clk_mux_sel *mux = 0;
+        const struct clk_mux_sel *sel;
+        u32 val = pmc_readl(c->reg);
+
+        c->state = (val & (0x1 << c->u.periph.clk_num)) ? ON : OFF;
+        c->mul = 1;
+        c->div = 1;
+
+        for (sel = c->inputs; sel->input != NULL; sel++) {
+                if (((val & periph_clk_source_mask(c)) >>
+                     periph_clk_source_shift(c)) == sel->value)
+                        mux = sel;
+        }
+        BUG_ON(!mux);
+        c->parent = mux->input;
+}
+
+static int tegra30_clk_out_enable(struct clk *c)
+{
+        u32 val;
+        unsigned long flags;
+
+        pr_debug("%s on clock %s\n", __func__, c->name);
+
+        spin_lock_irqsave(&clk_out_lock, flags);
+        val = pmc_readl(c->reg);
+        val |= (0x1 << c->u.periph.clk_num);
+        pmc_writel(val, c->reg);
+        spin_unlock_irqrestore(&clk_out_lock, flags);
+
+        return 0;
+}
+
+static void tegra30_clk_out_disable(struct clk *c)
+{
+        u32 val;
+        unsigned long flags;
+
+        pr_debug("%s on clock %s\n", __func__, c->name);
+
+        spin_lock_irqsave(&clk_out_lock, flags);
+        val = pmc_readl(c->reg);
+        val &= ~(0x1 << c->u.periph.clk_num);
+        pmc_writel(val, c->reg);
+        spin_unlock_irqrestore(&clk_out_lock, flags);
+}
+
+static int tegra30_clk_out_set_parent(struct clk *c, struct clk *p)
+{
+        u32 val;
+        unsigned long flags;
+        const struct clk_mux_sel *sel;
+
+        pr_debug("%s: %s %s\n", __func__, c->name, p->name);
+
+        for (sel = c->inputs; sel->input != NULL; sel++) {
+                if (sel->input == p) {
+                        if (c->refcnt)
+                                clk_enable(p);
+
+                        spin_lock_irqsave(&clk_out_lock, flags);
+                        val = pmc_readl(c->reg);
+                        val &= ~periph_clk_source_mask(c);
+                        val |= (sel->value << periph_clk_source_shift(c));
+                        pmc_writel(val, c->reg);
+                        spin_unlock_irqrestore(&clk_out_lock, flags);
+
+                        if (c->refcnt && c->parent)
+                                clk_disable(c->parent);
+
+                        clk_reparent(c, p);
+                        return 0;
+                }
+        }
+        return -EINVAL;
+}
+
+static struct clk_ops tegra_clk_out_ops = {
+        .init                   = &tegra30_clk_out_init,
+        .enable                 = &tegra30_clk_out_enable,
+        .disable                = &tegra30_clk_out_disable,
+        .set_parent             = &tegra30_clk_out_set_parent,
+};
+
+
+/* Clock doubler ops */
+static void tegra30_clk_double_init(struct clk *c)
+{
+        u32 val = clk_readl(c->reg);
+        c->mul = val & (0x1 << c->reg_shift) ? 1 : 2;
+        c->div = 1;
+        c->state = ON;
+        if (!(clk_readl(PERIPH_CLK_TO_ENB_REG(c)) & PERIPH_CLK_TO_BIT(c)))
+                c->state = OFF;
+};
+
+static int tegra30_clk_double_set_rate(struct clk *c, unsigned long rate)
+{
+        u32 val;
+        unsigned long parent_rate = clk_get_rate(c->parent);
+        if (rate == parent_rate) {
+                val = clk_readl(c->reg) | (0x1 << c->reg_shift);
+                clk_writel(val, c->reg);
+                c->mul = 1;
+                c->div = 1;
+                return 0;
+        } else if (rate == 2 * parent_rate) {
+                val = clk_readl(c->reg) & (~(0x1 << c->reg_shift));
+                clk_writel(val, c->reg);
+                c->mul = 2;
+                c->div = 1;
+                return 0;
+        }
+        return -EINVAL;
+}
+
+static struct clk_ops tegra_clk_double_ops = {
+        .init                   = &tegra30_clk_double_init,
+        .enable                 = &tegra30_periph_clk_enable,
+        .disable                = &tegra30_periph_clk_disable,
+        .set_rate               = &tegra30_clk_double_set_rate,
+};
+
+/* Audio sync clock ops */
+static int tegra30_sync_source_set_rate(struct clk *c, unsigned long rate)
+{
+        c->rate = rate;
+        return 0;
+}
+
+static struct clk_ops tegra_sync_source_ops = {
+        .set_rate               = &tegra30_sync_source_set_rate,
+};
+
+static void tegra30_audio_sync_clk_init(struct clk *c)
+{
+        int source;
+        const struct clk_mux_sel *sel;
+        u32 val = clk_readl(c->reg);
+        c->state = (val & AUDIO_SYNC_DISABLE_BIT) ? OFF : ON;
+        source = val & AUDIO_SYNC_SOURCE_MASK;
+        for (sel = c->inputs; sel->input != NULL; sel++)
+                if (sel->value == source)
+                        break;
+        BUG_ON(sel->input == NULL);
+        c->parent = sel->input;
+}
+
+static int tegra30_audio_sync_clk_enable(struct clk *c)
+{
+        u32 val = clk_readl(c->reg);
+        clk_writel((val & (~AUDIO_SYNC_DISABLE_BIT)), c->reg);
+        return 0;
+}
+
+static void tegra30_audio_sync_clk_disable(struct clk *c)
+{
+        u32 val = clk_readl(c->reg);
+        clk_writel((val | AUDIO_SYNC_DISABLE_BIT), c->reg);
+}
+
+static int tegra30_audio_sync_clk_set_parent(struct clk *c, struct clk *p)
+{
+        u32 val;
+        const struct clk_mux_sel *sel;
+        for (sel = c->inputs; sel->input != NULL; sel++) {
+                if (sel->input == p) {
+                        val = clk_readl(c->reg);
+                        val &= ~AUDIO_SYNC_SOURCE_MASK;
+                        val |= sel->value;
+
+                        if (c->refcnt)
+                                clk_enable(p);
+
+                        clk_writel(val, c->reg);
+
+                        if (c->refcnt && c->parent)
+                                clk_disable(c->parent);
+
+                        clk_reparent(c, p);
+                        return 0;
+                }
+        }
+
+        return -EINVAL;
+}
+
+static struct clk_ops tegra_audio_sync_clk_ops = {
+        .init       = tegra30_audio_sync_clk_init,
+        .enable     = tegra30_audio_sync_clk_enable,
+        .disable    = tegra30_audio_sync_clk_disable,
+        .set_parent = tegra30_audio_sync_clk_set_parent,
+};
+
+/* cml0 (pcie), and cml1 (sata) clock ops */
+static void tegra30_cml_clk_init(struct clk *c)
+{
+        u32 val = clk_readl(c->reg);
+        c->state = val & (0x1 << c->u.periph.clk_num) ? ON : OFF;
+}
+
+static int tegra30_cml_clk_enable(struct clk *c)
+{
+        u32 val = clk_readl(c->reg);
+        val |= (0x1 << c->u.periph.clk_num);
+        clk_writel(val, c->reg);
+        return 0;
+}
+
+static void tegra30_cml_clk_disable(struct clk *c)
+{
+        u32 val = clk_readl(c->reg);
+        val &= ~(0x1 << c->u.periph.clk_num);
+        clk_writel(val, c->reg);
+}
+
+static struct clk_ops tegra_cml_clk_ops = {
+        .init                   = &tegra30_cml_clk_init,
+        .enable                 = &tegra30_cml_clk_enable,
+        .disable                = &tegra30_cml_clk_disable,
+};
+
+/* Clock definitions */
+static struct clk tegra_clk_32k = {
+        .name = "clk_32k",
+        .rate = 32768,
+        .ops  = NULL,
+        .max_rate = 32768,
+};
+
+static struct clk tegra_clk_m = {
+        .name      = "clk_m",
+        .flags     = ENABLE_ON_INIT,
+        .ops       = &tegra_clk_m_ops,
+        .reg       = 0x1fc,
+        .reg_shift = 28,
+        .max_rate  = 48000000,
+};
+
+static struct clk tegra_clk_m_div2 = {
+        .name      = "clk_m_div2",
+        .ops       = &tegra_clk_m_div_ops,
+        .parent    = &tegra_clk_m,
+        .mul       = 1,
+        .div       = 2,
+        .state     = ON,
+        .max_rate  = 24000000,
+};
+
+static struct clk tegra_clk_m_div4 = {
+        .name      = "clk_m_div4",
+        .ops       = &tegra_clk_m_div_ops,
+        .parent    = &tegra_clk_m,
+        .mul       = 1,
+        .div       = 4,
+        .state     = ON,
+        .max_rate  = 12000000,
+};
+
+static struct clk tegra_pll_ref = {
+        .name      = "pll_ref",
+        .flags     = ENABLE_ON_INIT,
+        .ops       = &tegra_pll_ref_ops,
+        .parent    = &tegra_clk_m,
+        .max_rate  = 26000000,
+};
+
+static struct clk_pll_freq_table tegra_pll_c_freq_table[] = {
+        { 12000000, 1040000000, 520,  6, 1, 8},
+        { 13000000, 1040000000, 480,  6, 1, 8},
+        { 16800000, 1040000000, 495,  8, 1, 8},         /* actual: 1039.5 MHz */
+        { 19200000, 1040000000, 325,  6, 1, 6},
+        { 26000000, 1040000000, 520, 13, 1, 8},
+
+        { 12000000, 832000000, 416,  6, 1, 8},
+        { 13000000, 832000000, 832, 13, 1, 8},
+        { 16800000, 832000000, 396,  8, 1, 8},          /* actual: 831.6 MHz */
+        { 19200000, 832000000, 260,  6, 1, 8},
+        { 26000000, 832000000, 416, 13, 1, 8},
+
+        { 12000000, 624000000, 624, 12, 1, 8},
+        { 13000000, 624000000, 624, 13, 1, 8},
+        { 16800000, 600000000, 520, 14, 1, 8},
+        { 19200000, 624000000, 520, 16, 1, 8},
+        { 26000000, 624000000, 624, 26, 1, 8},
+
+        { 12000000, 600000000, 600, 12, 1, 8},
+        { 13000000, 600000000, 600, 13, 1, 8},
+        { 16800000, 600000000, 500, 14, 1, 8},
+        { 19200000, 600000000, 375, 12, 1, 6},
+        { 26000000, 600000000, 600, 26, 1, 8},
+
+        { 12000000, 520000000, 520, 12, 1, 8},
+        { 13000000, 520000000, 520, 13, 1, 8},
+        { 16800000, 520000000, 495, 16, 1, 8},          /* actual: 519.75 MHz */
+        { 19200000, 520000000, 325, 12, 1, 6},
+        { 26000000, 520000000, 520, 26, 1, 8},
+
+        { 12000000, 416000000, 416, 12, 1, 8},
+        { 13000000, 416000000, 416, 13, 1, 8},
+        { 16800000, 416000000, 396, 16, 1, 8},          /* actual: 415.8 MHz */
+        { 19200000, 416000000, 260, 12, 1, 6},
+        { 26000000, 416000000, 416, 26, 1, 8},
+        { 0, 0, 0, 0, 0, 0 },
+};
+
+static struct clk tegra_pll_c = {
+        .name      = "pll_c",
+        .flags     = PLL_HAS_CPCON,
+        .ops       = &tegra_pll_ops,
+        .reg       = 0x80,
+        .parent    = &tegra_pll_ref,
+        .max_rate  = 1400000000,
+        .u.pll = {
+                .input_min = 2000000,
+                .input_max = 31000000,
+                .cf_min    = 1000000,
+                .cf_max    = 6000000,
+                .vco_min   = 20000000,
+                .vco_max   = 1400000000,
+                .freq_table = tegra_pll_c_freq_table,
+                .lock_delay = 300,
+        },
+};
+
+static struct clk tegra_pll_c_out1 = {
+        .name      = "pll_c_out1",
+        .ops       = &tegra_pll_div_ops,
+        .flags     = DIV_U71,
+        .parent    = &tegra_pll_c,
+        .reg       = 0x84,
+        .reg_shift = 0,
+        .max_rate  = 700000000,
+};
+
+static struct clk_pll_freq_table tegra_pll_m_freq_table[] = {
+        { 12000000, 666000000, 666, 12, 1, 8},
+        { 13000000, 666000000, 666, 13, 1, 8},
+        { 16800000, 666000000, 555, 14, 1, 8},
+        { 19200000, 666000000, 555, 16, 1, 8},
+        { 26000000, 666000000, 666, 26, 1, 8},
+        { 12000000, 600000000, 600, 12, 1, 8},
+        { 13000000, 600000000, 600, 13, 1, 8},
+        { 16800000, 600000000, 500, 14, 1, 8},
+        { 19200000, 600000000, 375, 12, 1, 6},
+        { 26000000, 600000000, 600, 26, 1, 8},
+        { 0, 0, 0, 0, 0, 0 },
+};
+
+static struct clk tegra_pll_m = {
+        .name      = "pll_m",
+        .flags     = PLL_HAS_CPCON | PLLM,
+        .ops       = &tegra_pll_ops,
+        .reg       = 0x90,
+        .parent    = &tegra_pll_ref,
+        .max_rate  = 800000000,
+        .u.pll = {
+                .input_min = 2000000,
+                .input_max = 31000000,
+                .cf_min    = 1000000,
+                .cf_max    = 6000000,
+                .vco_min   = 20000000,
+                .vco_max   = 1200000000,
+                .freq_table = tegra_pll_m_freq_table,
+                .lock_delay = 300,
+        },
+};
+
+static struct clk tegra_pll_m_out1 = {
+        .name      = "pll_m_out1",
+        .ops       = &tegra_pll_div_ops,
+        .flags     = DIV_U71,
+        .parent    = &tegra_pll_m,
+        .reg       = 0x94,
+        .reg_shift = 0,
+        .max_rate  = 600000000,
+};
+
+static struct clk_pll_freq_table tegra_pll_p_freq_table[] = {
+        { 12000000, 216000000, 432, 12, 2, 8},
+        { 13000000, 216000000, 432, 13, 2, 8},
+        { 16800000, 216000000, 360, 14, 2, 8},
+        { 19200000, 216000000, 360, 16, 2, 8},
+        { 26000000, 216000000, 432, 26, 2, 8},
+        { 0, 0, 0, 0, 0, 0 },
+};
+
+static struct clk tegra_pll_p = {
+        .name      = "pll_p",
+        .flags     = ENABLE_ON_INIT | PLL_FIXED | PLL_HAS_CPCON,
+        .ops       = &tegra_pll_ops,
+        .reg       = 0xa0,
+        .parent    = &tegra_pll_ref,
+        .max_rate  = 432000000,
+        .u.pll = {
+                .input_min = 2000000,
+                .input_max = 31000000,
+                .cf_min    = 1000000,
+                .cf_max    = 6000000,
+                .vco_min   = 20000000,
+                .vco_max   = 1400000000,
+                .freq_table = tegra_pll_p_freq_table,
+                .lock_delay = 300,
+                .fixed_rate = 408000000,
+        },
+};
+
+static struct clk tegra_pll_p_out1 = {
+        .name      = "pll_p_out1",
+        .ops       = &tegra_pll_div_ops,
+        .flags     = ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED,
+        .parent    = &tegra_pll_p,
+        .reg       = 0xa4,
+        .reg_shift = 0,
+        .max_rate  = 432000000,
+};
+
+static struct clk tegra_pll_p_out2 = {
+        .name      = "pll_p_out2",
+        .ops       = &tegra_pll_div_ops,
+        .flags     = ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED,
+        .parent    = &tegra_pll_p,
+        .reg       = 0xa4,
+        .reg_shift = 16,
+        .max_rate  = 432000000,
+};
+
+static struct clk tegra_pll_p_out3 = {
+        .name      = "pll_p_out3",
+        .ops       = &tegra_pll_div_ops,
+        .flags     = ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED,
+        .parent    = &tegra_pll_p,
+        .reg       = 0xa8,
+        .reg_shift = 0,
+        .max_rate  = 432000000,
+};
+
+static struct clk tegra_pll_p_out4 = {
+        .name      = "pll_p_out4",
+        .ops       = &tegra_pll_div_ops,
+        .flags     = ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED,
+        .parent    = &tegra_pll_p,
+        .reg       = 0xa8,
+        .reg_shift = 16,
+        .max_rate  = 432000000,
+};
+
+static struct clk_pll_freq_table tegra_pll_a_freq_table[] = {
+        { 9600000, 564480000, 294, 5, 1, 4},
+        { 9600000, 552960000, 288, 5, 1, 4},
+        { 9600000, 24000000,  5,   2, 1, 1},
+
+        { 28800000, 56448000, 49, 25, 1, 1},
+        { 28800000, 73728000, 64, 25, 1, 1},
+        { 28800000, 24000000,  5,  6, 1, 1},
+        { 0, 0, 0, 0, 0, 0 },
+};
+
+static struct clk tegra_pll_a = {
+        .name      = "pll_a",
+        .flags     = PLL_HAS_CPCON,
+        .ops       = &tegra_pll_ops,
+        .reg       = 0xb0,
+        .parent    = &tegra_pll_p_out1,
+        .max_rate  = 700000000,
+        .u.pll = {
+                .input_min = 2000000,
+                .input_max = 31000000,
+                .cf_min    = 1000000,
+                .cf_max    = 6000000,
+                .vco_min   = 20000000,
+                .vco_max   = 1400000000,
+                .freq_table = tegra_pll_a_freq_table,
+                .lock_delay = 300,
+        },
+};
+
+static struct clk tegra_pll_a_out0 = {
+        .name      = "pll_a_out0",
+        .ops       = &tegra_pll_div_ops,
+        .flags     = DIV_U71,
+        .parent    = &tegra_pll_a,
+        .reg       = 0xb4,
+        .reg_shift = 0,
+        .max_rate  = 100000000,
+};
+
+static struct clk_pll_freq_table tegra_pll_d_freq_table[] = {
+        { 12000000, 216000000, 216, 12, 1, 4},
+        { 13000000, 216000000, 216, 13, 1, 4},
+        { 16800000, 216000000, 180, 14, 1, 4},
+        { 19200000, 216000000, 180, 16, 1, 4},
+        { 26000000, 216000000, 216, 26, 1, 4},
+
+        { 12000000, 594000000, 594, 12, 1, 8},
+        { 13000000, 594000000, 594, 13, 1, 8},
+        { 16800000, 594000000, 495, 14, 1, 8},
+        { 19200000, 594000000, 495, 16, 1, 8},
+        { 26000000, 594000000, 594, 26, 1, 8},
+
+        { 12000000, 1000000000, 1000, 12, 1, 12},
+        { 13000000, 1000000000, 1000, 13, 1, 12},
+        { 19200000, 1000000000, 625,  12, 1, 8},
+        { 26000000, 1000000000, 1000, 26, 1, 12},
+
+        { 0, 0, 0, 0, 0, 0 },
+};
+
+static struct clk tegra_pll_d = {
+        .name      = "pll_d",
+        .flags     = PLL_HAS_CPCON | PLLD,
+        .ops       = &tegra_plld_ops,
+        .reg       = 0xd0,
+        .parent    = &tegra_pll_ref,
+        .max_rate  = 1000000000,
+        .u.pll = {
+                .input_min = 2000000,
+                .input_max = 40000000,
+                .cf_min    = 1000000,
+                .cf_max    = 6000000,
+                .vco_min   = 40000000,
+                .vco_max   = 1000000000,
+                .freq_table = tegra_pll_d_freq_table,
+                .lock_delay = 1000,
+        },
+};
+
+static struct clk tegra_pll_d_out0 = {
+        .name      = "pll_d_out0",
+        .ops       = &tegra_pll_div_ops,
+        .flags     = DIV_2 | PLLD,
+        .parent    = &tegra_pll_d,
+        .max_rate  = 500000000,
+};
+
+static struct clk tegra_pll_d2 = {
+        .name      = "pll_d2",
+        .flags     = PLL_HAS_CPCON | PLL_ALT_MISC_REG | PLLD,
+        .ops       = &tegra_plld_ops,
+        .reg       = 0x4b8,
+        .parent    = &tegra_pll_ref,
+        .max_rate  = 1000000000,
+        .u.pll = {
+                .input_min = 2000000,
+                .input_max = 40000000,
+                .cf_min    = 1000000,
+                .cf_max    = 6000000,
+                .vco_min   = 40000000,
+                .vco_max   = 1000000000,
+                .freq_table = tegra_pll_d_freq_table,
+                .lock_delay = 1000,
+        },
+};
+
+static struct clk tegra_pll_d2_out0 = {
+        .name      = "pll_d2_out0",
+        .ops       = &tegra_pll_div_ops,
+        .flags     = DIV_2 | PLLD,
+        .parent    = &tegra_pll_d2,
+        .max_rate  = 500000000,
+};
+
+static struct clk_pll_freq_table tegra_pll_u_freq_table[] = {
+        { 12000000, 480000000, 960, 12, 2, 12},
+        { 13000000, 480000000, 960, 13, 2, 12},
+        { 16800000, 480000000, 400, 7,  2, 5},
+        { 19200000, 480000000, 200, 4,  2, 3},
+        { 26000000, 480000000, 960, 26, 2, 12},
+        { 0, 0, 0, 0, 0, 0 },
+};
+
+static struct clk tegra_pll_u = {
+        .name      = "pll_u",
+        .flags     = PLL_HAS_CPCON | PLLU,
+        .ops       = &tegra_pll_ops,
+        .reg       = 0xc0,
+        .parent    = &tegra_pll_ref,
+        .max_rate  = 480000000,
+        .u.pll = {
+                .input_min = 2000000,
+                .input_max = 40000000,
+                .cf_min    = 1000000,
+                .cf_max    = 6000000,
+                .vco_min   = 480000000,
+                .vco_max   = 960000000,
+                .freq_table = tegra_pll_u_freq_table,
+                .lock_delay = 1000,
+        },
+};
+
+static struct clk_pll_freq_table tegra_pll_x_freq_table[] = {
+        /* 1.7 GHz */
+        { 12000000, 1700000000, 850,  6,  1, 8},
+        { 13000000, 1700000000, 915,  7,  1, 8},        /* actual: 1699.2 MHz */
+        { 16800000, 1700000000, 708,  7,  1, 8},        /* actual: 1699.2 MHz */
+        { 19200000, 1700000000, 885,  10, 1, 8},        /* actual: 1699.2 MHz */
+        { 26000000, 1700000000, 850,  13, 1, 8},
+
+        /* 1.6 GHz */
+        { 12000000, 1600000000, 800,  6,  1, 8},
+        { 13000000, 1600000000, 738,  6,  1, 8},        /* actual: 1599.0 MHz */
+        { 16800000, 1600000000, 857,  9,  1, 8},        /* actual: 1599.7 MHz */
+        { 19200000, 1600000000, 500,  6,  1, 8},
+        { 26000000, 1600000000, 800,  13, 1, 8},
+
+        /* 1.5 GHz */
+        { 12000000, 1500000000, 750,  6,  1, 8},
+        { 13000000, 1500000000, 923,  8,  1, 8},        /* actual: 1499.8 MHz */
+        { 16800000, 1500000000, 625,  7,  1, 8},
+        { 19200000, 1500000000, 625,  8,  1, 8},
+        { 26000000, 1500000000, 750,  13, 1, 8},
+
+        /* 1.4 GHz */
+        { 12000000, 1400000000, 700,  6,  1, 8},
+        { 13000000, 1400000000, 969,  9,  1, 8},        /* actual: 1399.7 MHz */
+        { 16800000, 1400000000, 1000, 12, 1, 8},
+        { 19200000, 1400000000, 875,  12, 1, 8},
+        { 26000000, 1400000000, 700,  13, 1, 8},
+
+        /* 1.3 GHz */
+        { 12000000, 1300000000, 975,  9,  1, 8},
+        { 13000000, 1300000000, 1000, 10, 1, 8},
+        { 16800000, 1300000000, 928,  12, 1, 8},        /* actual: 1299.2 MHz */
+        { 19200000, 1300000000, 812,  12, 1, 8},        /* actual: 1299.2 MHz */
+        { 26000000, 1300000000, 650,  13, 1, 8},
+
+        /* 1.2 GHz */
+        { 12000000, 1200000000, 1000, 10, 1, 8},
+        { 13000000, 1200000000, 923,  10, 1, 8},        /* actual: 1199.9 MHz */
+        { 16800000, 1200000000, 1000, 14, 1, 8},
+        { 19200000, 1200000000, 1000, 16, 1, 8},
+        { 26000000, 1200000000, 600,  13, 1, 8},
+
+        /* 1.1 GHz */
+        { 12000000, 1100000000, 825,  9,  1, 8},
+        { 13000000, 1100000000, 846,  10, 1, 8},        /* actual: 1099.8 MHz */
+        { 16800000, 1100000000, 982,  15, 1, 8},        /* actual: 1099.8 MHz */
+        { 19200000, 1100000000, 859,  15, 1, 8},        /* actual: 1099.5 MHz */
+        { 26000000, 1100000000, 550,  13, 1, 8},
+
+        /* 1 GHz */
+        { 12000000, 1000000000, 1000, 12, 1, 8},
+        { 13000000, 1000000000, 1000, 13, 1, 8},
+        { 16800000, 1000000000, 833,  14, 1, 8},        /* actual: 999.6 MHz */
+        { 19200000, 1000000000, 625,  12, 1, 8},
+        { 26000000, 1000000000, 1000, 26, 1, 8},
+
+        { 0, 0, 0, 0, 0, 0 },
+};
+
+static struct clk tegra_pll_x = {
+        .name      = "pll_x",
+        .flags     = PLL_HAS_CPCON | PLL_ALT_MISC_REG | PLLX,
+        .ops       = &tegra_pll_ops,
+        .reg       = 0xe0,
+        .parent    = &tegra_pll_ref,
+        .max_rate  = 1700000000,
+        .u.pll = {
+                .input_min = 2000000,
+                .input_max = 31000000,
+                .cf_min    = 1000000,
+                .cf_max    = 6000000,
+                .vco_min   = 20000000,
+                .vco_max   = 1700000000,
+                .freq_table = tegra_pll_x_freq_table,
+                .lock_delay = 300,
+        },
+};
+
+static struct clk tegra_pll_x_out0 = {
+        .name      = "pll_x_out0",
+        .ops       = &tegra_pll_div_ops,
+        .flags     = DIV_2 | PLLX,
+        .parent    = &tegra_pll_x,
+        .max_rate  = 850000000,
+};
+
+
+static struct clk_pll_freq_table tegra_pll_e_freq_table[] = {
+        /* PLLE special case: use cpcon field to store cml divider value */
+        { 12000000,  100000000, 150, 1,  18, 11},
+        { 216000000, 100000000, 200, 18, 24, 13},
+        { 0, 0, 0, 0, 0, 0 },
+};
+
+static struct clk tegra_pll_e = {
+        .name      = "pll_e",
+        .flags     = PLL_ALT_MISC_REG,
+        .ops       = &tegra_plle_ops,
+        .reg       = 0xe8,
+        .max_rate  = 100000000,
+        .u.pll = {
+                .input_min = 12000000,
+                .input_max = 216000000,
+                .cf_min    = 12000000,
+                .cf_max    = 12000000,
+                .vco_min   = 1200000000,
+                .vco_max   = 2400000000U,
+                .freq_table = tegra_pll_e_freq_table,
+                .lock_delay = 300,
+                .fixed_rate = 100000000,
+        },
+};
+
+static struct clk tegra_cml0_clk = {
+        .name      = "cml0",
+        .parent    = &tegra_pll_e,
+        .ops       = &tegra_cml_clk_ops,
+        .reg       = PLLE_AUX,
+        .max_rate  = 100000000,
+        .u.periph  = {
+                .clk_num = 0,
+        },
+};
+
+static struct clk tegra_cml1_clk = {
+        .name      = "cml1",
+        .parent    = &tegra_pll_e,
+        .ops       = &tegra_cml_clk_ops,
+        .reg       = PLLE_AUX,
+        .max_rate  = 100000000,
+        .u.periph  = {
+                .clk_num   = 1,
+        },
+};
+
+static struct clk tegra_pciex_clk = {
+        .name      = "pciex",
+        .parent    = &tegra_pll_e,
+        .ops       = &tegra_pciex_clk_ops,
+        .max_rate  = 100000000,
+        .u.periph  = {
+                .clk_num   = 74,
+        },
+};
+
+/* Audio sync clocks */
+#define SYNC_SOURCE(_id)                                \
+        {                                               \
+                .name      = #_id "_sync",              \
+                .rate      = 24000000,                  \
+                .max_rate  = 24000000,                  \
+                .ops       = &tegra_sync_source_ops     \
+        }
+static struct clk tegra_sync_source_list[] = {
+        SYNC_SOURCE(spdif_in),
+        SYNC_SOURCE(i2s0),
+        SYNC_SOURCE(i2s1),
+        SYNC_SOURCE(i2s2),
+        SYNC_SOURCE(i2s3),
+        SYNC_SOURCE(i2s4),
+        SYNC_SOURCE(vimclk),
+};
+
+static struct clk_mux_sel mux_audio_sync_clk[] = {
+        { .input = &tegra_sync_source_list[0],  .value = 0},
+        { .input = &tegra_sync_source_list[1],  .value = 1},
+        { .input = &tegra_sync_source_list[2],  .value = 2},
+        { .input = &tegra_sync_source_list[3],  .value = 3},
+        { .input = &tegra_sync_source_list[4],  .value = 4},
+        { .input = &tegra_sync_source_list[5],  .value = 5},
+        { .input = &tegra_pll_a_out0,           .value = 6},
+        { .input = &tegra_sync_source_list[6],  .value = 7},
+        { 0, 0 }
+};
+
+#define AUDIO_SYNC_CLK(_id, _index)                     \
+        {                                               \
+                .name      = #_id,                      \
+                .inputs    = mux_audio_sync_clk,        \
+                .reg       = 0x4A0 + (_index) * 4,      \
+                .max_rate  = 24000000,                  \
+                .ops       = &tegra_audio_sync_clk_ops  \
+        }
+static struct clk tegra_clk_audio_list[] = {
+        AUDIO_SYNC_CLK(audio0, 0),
+        AUDIO_SYNC_CLK(audio1, 1),
+        AUDIO_SYNC_CLK(audio2, 2),
+        AUDIO_SYNC_CLK(audio3, 3),
+        AUDIO_SYNC_CLK(audio4, 4),
+        AUDIO_SYNC_CLK(audio, 5),       /* SPDIF */
+};
+
+#define AUDIO_SYNC_2X_CLK(_id, _index)                          \
+        {                                                       \
+                .name      = #_id "_2x",                        \
+                .flags     = PERIPH_NO_RESET,                   \
+                .max_rate  = 48000000,                          \
+                .ops       = &tegra_clk_double_ops,             \
+                .reg       = 0x49C,                             \
+                .reg_shift = 24 + (_index),                     \
+                .parent    = &tegra_clk_audio_list[(_index)],   \
+                .u.periph = {                                   \
+                        .clk_num = 113 + (_index),              \
+                },                                              \
+        }
+static struct clk tegra_clk_audio_2x_list[] = {
+        AUDIO_SYNC_2X_CLK(audio0, 0),
+        AUDIO_SYNC_2X_CLK(audio1, 1),
+        AUDIO_SYNC_2X_CLK(audio2, 2),
+        AUDIO_SYNC_2X_CLK(audio3, 3),
+        AUDIO_SYNC_2X_CLK(audio4, 4),
+        AUDIO_SYNC_2X_CLK(audio, 5),    /* SPDIF */
+};
+
+#define MUX_I2S_SPDIF(_id, _index)                                      \
+static struct clk_mux_sel mux_pllaout0_##_id##_2x_pllp_clkm[] = {       \
+        {.input = &tegra_pll_a_out0, .value = 0},                       \
+        {.input = &tegra_clk_audio_2x_list[(_index)], .value = 1},      \
+        {.input = &tegra_pll_p, .value = 2},                            \
+        {.input = &tegra_clk_m, .value = 3},                            \
+        { 0, 0},                                                        \
+}
+MUX_I2S_SPDIF(audio0, 0);
+MUX_I2S_SPDIF(audio1, 1);
+MUX_I2S_SPDIF(audio2, 2);
+MUX_I2S_SPDIF(audio3, 3);
+MUX_I2S_SPDIF(audio4, 4);
+MUX_I2S_SPDIF(audio, 5);                /* SPDIF */
+
+/* External clock outputs (through PMC) */
+#define MUX_EXTERN_OUT(_id)                                             \
+static struct clk_mux_sel mux_clkm_clkm2_clkm4_extern##_id[] = {        \
+        {.input = &tegra_clk_m,         .value = 0},                    \
+        {.input = &tegra_clk_m_div2,    .value = 1},                    \
+        {.input = &tegra_clk_m_div4,    .value = 2},                    \
+        {.input = NULL,                 .value = 3}, /* placeholder */  \
+        { 0, 0},                                                        \
+}
+MUX_EXTERN_OUT(1);
+MUX_EXTERN_OUT(2);
+MUX_EXTERN_OUT(3);
+
+static struct clk_mux_sel *mux_extern_out_list[] = {
+        mux_clkm_clkm2_clkm4_extern1,
+        mux_clkm_clkm2_clkm4_extern2,
+        mux_clkm_clkm2_clkm4_extern3,
+};
+
+#define CLK_OUT_CLK(_id)                                        \
+        {                                                       \
+                .name      = "clk_out_" #_id,                   \
+                .lookup    = {                                  \
+                        .dev_id    = "clk_out_" #_id,           \
+                        .con_id    = "extern" #_id,             \
+                },                                              \
+                .ops       = &tegra_clk_out_ops,                \
+                .reg       = 0x1a8,                             \
+                .inputs    = mux_clkm_clkm2_clkm4_extern##_id,  \
+                .flags     = MUX_CLK_OUT,                       \
+                .max_rate  = 216000000,                         \
+                .u.periph = {                                   \
+                        .clk_num   = (_id - 1) * 8 + 2,         \
+                },                                              \
+        }
+static struct clk tegra_clk_out_list[] = {
+        CLK_OUT_CLK(1),
+        CLK_OUT_CLK(2),
+        CLK_OUT_CLK(3),
+};
+
+/* called after peripheral external clocks are initialized */
+static void init_clk_out_mux(void)
+{
+        int i;
+        struct clk *c;
+
+        /* output clock con_id is the name of peripheral
+           external clock connected to input 3 of the output mux */
+        for (i = 0; i < ARRAY_SIZE(tegra_clk_out_list); i++) {
+                c = tegra_get_clock_by_name(
+                        tegra_clk_out_list[i].lookup.con_id);
+                if (!c)
+                        pr_err("%s: could not find clk %s\n", __func__,
+                               tegra_clk_out_list[i].lookup.con_id);
+                mux_extern_out_list[i][3].input = c;
+        }
+}
+
+/* Peripheral muxes */
+static struct clk_mux_sel mux_sclk[] = {
+        { .input = &tegra_clk_m,        .value = 0},
+        { .input = &tegra_pll_c_out1,   .value = 1},
+        { .input = &tegra_pll_p_out4,   .value = 2},
+        { .input = &tegra_pll_p_out3,   .value = 3},
+        { .input = &tegra_pll_p_out2,   .value = 4},
+        /* { .input = &tegra_clk_d,     .value = 5}, - no use on tegra30 */
+        { .input = &tegra_clk_32k,      .value = 6},
+        { .input = &tegra_pll_m_out1,   .value = 7},
+        { 0, 0},
+};
+
+static struct clk tegra_clk_sclk = {
+        .name   = "sclk",
+        .inputs = mux_sclk,
+        .reg    = 0x28,
+        .ops    = &tegra_super_ops,
+        .max_rate = 334000000,
+        .min_rate = 40000000,
+};
+
+static struct clk tegra_clk_blink = {
+        .name           = "blink",
+        .parent         = &tegra_clk_32k,
+        .reg            = 0x40,
+        .ops            = &tegra_blink_clk_ops,
+        .max_rate       = 32768,
+};
+
+static struct clk_mux_sel mux_pllm_pllc_pllp_plla[] = {
+        { .input = &tegra_pll_m, .value = 0},
+        { .input = &tegra_pll_c, .value = 1},
+        { .input = &tegra_pll_p, .value = 2},
+        { .input = &tegra_pll_a_out0, .value = 3},
+        { 0, 0},
+};
+
+static struct clk_mux_sel mux_pllp_pllc_pllm_clkm[] = {
+        { .input = &tegra_pll_p, .value = 0},
+        { .input = &tegra_pll_c, .value = 1},
+        { .input = &tegra_pll_m, .value = 2},
+        { .input = &tegra_clk_m, .value = 3},
+        { 0, 0},
+};
+
+static struct clk_mux_sel mux_pllp_clkm[] = {
+        { .input = &tegra_pll_p, .value = 0},
+        { .input = &tegra_clk_m, .value = 3},
+        { 0, 0},
+};
+
+static struct clk_mux_sel mux_pllp_plld_pllc_clkm[] = {
+        {.input = &tegra_pll_p, .value = 0},
+        {.input = &tegra_pll_d_out0, .value = 1},
+        {.input = &tegra_pll_c, .value = 2},
+        {.input = &tegra_clk_m, .value = 3},
+        { 0, 0},
+};
+
+static struct clk_mux_sel mux_pllp_pllm_plld_plla_pllc_plld2_clkm[] = {
+        {.input = &tegra_pll_p, .value = 0},
+        {.input = &tegra_pll_m, .value = 1},
+        {.input = &tegra_pll_d_out0, .value = 2},
+        {.input = &tegra_pll_a_out0, .value = 3},
+        {.input = &tegra_pll_c, .value = 4},
+        {.input = &tegra_pll_d2_out0, .value = 5},
+        {.input = &tegra_clk_m, .value = 6},
+        { 0, 0},
+};
+
+static struct clk_mux_sel mux_plla_pllc_pllp_clkm[] = {
+        { .input = &tegra_pll_a_out0, .value = 0},
+        /* { .input = &tegra_pll_c, .value = 1}, no use on tegra30 */
+        { .input = &tegra_pll_p, .value = 2},
+        { .input = &tegra_clk_m, .value = 3},
+        { 0, 0},
+};
+
+static struct clk_mux_sel mux_pllp_pllc_clk32_clkm[] = {
+        {.input = &tegra_pll_p,     .value = 0},
+        {.input = &tegra_pll_c,     .value = 1},
+        {.input = &tegra_clk_32k,   .value = 2},
+        {.input = &tegra_clk_m,     .value = 3},
+        { 0, 0},
+};
+
+static struct clk_mux_sel mux_pllp_pllc_clkm_clk32[] = {
+        {.input = &tegra_pll_p,     .value = 0},
+        {.input = &tegra_pll_c,     .value = 1},
+        {.input = &tegra_clk_m,     .value = 2},
+        {.input = &tegra_clk_32k,   .value = 3},
+        { 0, 0},
+};
+
+static struct clk_mux_sel mux_pllp_pllc_pllm[] = {
+        {.input = &tegra_pll_p,     .value = 0},
+        {.input = &tegra_pll_c,     .value = 1},
+        {.input = &tegra_pll_m,     .value = 2},
+        { 0, 0},
+};
+
+static struct clk_mux_sel mux_clk_m[] = {
+        { .input = &tegra_clk_m, .value = 0},
+        { 0, 0},
+};
+
+static struct clk_mux_sel mux_pllp_out3[] = {
+        { .input = &tegra_pll_p_out3, .value = 0},
+        { 0, 0},
+};
+
+static struct clk_mux_sel mux_plld_out0[] = {
+        { .input = &tegra_pll_d_out0, .value = 0},
+        { 0, 0},
+};
+
+static struct clk_mux_sel mux_plld_out0_plld2_out0[] = {
+        { .input = &tegra_pll_d_out0,  .value = 0},
+        { .input = &tegra_pll_d2_out0, .value = 1},
+        { 0, 0},
+};
+
+static struct clk_mux_sel mux_clk_32k[] = {
+        { .input = &tegra_clk_32k, .value = 0},
+        { 0, 0},
+};
+
+static struct clk_mux_sel mux_plla_clk32_pllp_clkm_plle[] = {
+        { .input = &tegra_pll_a_out0, .value = 0},
+        { .input = &tegra_clk_32k,    .value = 1},
+        { .input = &tegra_pll_p,      .value = 2},
+        { .input = &tegra_clk_m,      .value = 3},
+        { .input = &tegra_pll_e,      .value = 4},
+        { 0, 0},
+};
+
+static struct clk_mux_sel mux_cclk_g[] = {
+        { .input = &tegra_clk_m,        .value = 0},
+        { .input = &tegra_pll_c,        .value = 1},
+        { .input = &tegra_clk_32k,      .value = 2},
+        { .input = &tegra_pll_m,        .value = 3},
+        { .input = &tegra_pll_p,        .value = 4},
+        { .input = &tegra_pll_p_out4,   .value = 5},
+        { .input = &tegra_pll_p_out3,   .value = 6},
+        { .input = &tegra_pll_x,        .value = 8},
+        { 0, 0},
+};
+
+static struct clk tegra_clk_cclk_g = {
+        .name   = "cclk_g",
+        .flags  = DIV_U71 | DIV_U71_INT,
+        .inputs = mux_cclk_g,
+        .reg    = 0x368,
+        .ops    = &tegra_super_ops,
+        .max_rate = 1700000000,
+};
+
+static struct clk tegra30_clk_twd = {
+        .parent   = &tegra_clk_cclk_g,
+        .name     = "twd",
+        .ops      = &tegra30_twd_ops,
+        .max_rate = 1400000000, /* Same as tegra_clk_cpu_cmplx.max_rate */
+        .mul      = 1,
+        .div      = 2,
+};
+
+#define PERIPH_CLK(_name, _dev, _con, _clk_num, _reg, _max, _inputs, _flags) \
+        {                                               \
+                .name      = _name,                     \
+                .lookup    = {                          \
+                        .dev_id    = _dev,              \
+                        .con_id    = _con,              \
+                },                                      \
+                .ops       = &tegra_periph_clk_ops,     \
+                .reg       = _reg,                      \
+                .inputs    = _inputs,                   \
+                .flags     = _flags,                    \
+                .max_rate  = _max,                      \
+                .u.periph = {                           \
+                        .clk_num   = _clk_num,          \
+                },                                      \
+        }
+
+#define PERIPH_CLK_EX(_name, _dev, _con, _clk_num, _reg, _max, _inputs, \
+                        _flags, _ops)                                   \
+        {                                               \
+                .name      = _name,                     \
+                .lookup    = {                          \
+                        .dev_id    = _dev,              \
+                        .con_id    = _con,              \
+                },                                      \
+                .ops       = _ops,                      \
+                .reg       = _reg,                      \
+                .inputs    = _inputs,                   \
+                .flags     = _flags,                    \
+                .max_rate  = _max,                      \
+                .u.periph = {                           \
+                        .clk_num   = _clk_num,          \
+                },                                      \
+        }
+
+#define SHARED_CLK(_name, _dev, _con, _parent, _id, _div, _mode)\
+        {                                               \
+                .name      = _name,                     \
+                .lookup    = {                          \
+                        .dev_id    = _dev,              \
+                        .con_id    = _con,              \
+                },                                      \
+                .ops       = &tegra_clk_shared_bus_ops, \
+                .parent = _parent,                      \
+                .u.shared_bus_user = {                  \
+                        .client_id = _id,               \
+                        .client_div = _div,             \
+                        .mode = _mode,                  \
+                },                                      \
+        }
+struct clk tegra_list_clks[] = {
+        PERIPH_CLK("apbdma",    "tegra-dma",            NULL,   34,     0,      26000000,  mux_clk_m,                   0),
+        PERIPH_CLK("rtc",       "rtc-tegra",            NULL,   4,      0,      32768,     mux_clk_32k,                 PERIPH_NO_RESET | PERIPH_ON_APB),
+        PERIPH_CLK("kbc",       "tegra-kbc",            NULL,   36,     0,      32768,     mux_clk_32k,                 PERIPH_NO_RESET | PERIPH_ON_APB),
+        PERIPH_CLK("timer",     "timer",                NULL,   5,      0,      26000000,  mux_clk_m,                   0),
+        PERIPH_CLK("kfuse",     "kfuse-tegra",          NULL,   40,     0,      26000000,  mux_clk_m,                   0),
+        PERIPH_CLK("fuse",      "fuse-tegra",           "fuse", 39,     0,      26000000,  mux_clk_m,                   PERIPH_ON_APB),
+        PERIPH_CLK("fuse_burn", "fuse-tegra",           "fuse_burn",    39,     0,      26000000,  mux_clk_m,           PERIPH_ON_APB),
+        PERIPH_CLK("apbif",     "tegra30-ahub",         "apbif", 107,   0,      26000000,  mux_clk_m,                   0),
+        PERIPH_CLK("i2s0",      "tegra30-i2s.0",        NULL,   30,     0x1d8,  26000000,  mux_pllaout0_audio0_2x_pllp_clkm,    MUX | DIV_U71 | PERIPH_ON_APB),
+        PERIPH_CLK("i2s1",      "tegra30-i2s.1",        NULL,   11,     0x100,  26000000,  mux_pllaout0_audio1_2x_pllp_clkm,    MUX | DIV_U71 | PERIPH_ON_APB),
+        PERIPH_CLK("i2s2",      "tegra30-i2s.2",        NULL,   18,     0x104,  26000000,  mux_pllaout0_audio2_2x_pllp_clkm,    MUX | DIV_U71 | PERIPH_ON_APB),
+        PERIPH_CLK("i2s3",      "tegra30-i2s.3",        NULL,   101,    0x3bc,  26000000,  mux_pllaout0_audio3_2x_pllp_clkm,    MUX | DIV_U71 | PERIPH_ON_APB),
+        PERIPH_CLK("i2s4",      "tegra30-i2s.4",        NULL,   102,    0x3c0,  26000000,  mux_pllaout0_audio4_2x_pllp_clkm,    MUX | DIV_U71 | PERIPH_ON_APB),
+        PERIPH_CLK("spdif_out", "tegra30-spdif",        "spdif_out",    10,     0x108,  100000000, mux_pllaout0_audio_2x_pllp_clkm,     MUX | DIV_U71 | PERIPH_ON_APB),
+        PERIPH_CLK("spdif_in",  "tegra30-spdif",        "spdif_in",     10,     0x10c,  100000000, mux_pllp_pllc_pllm,          MUX | DIV_U71 | PERIPH_ON_APB),
+        PERIPH_CLK("pwm",       "pwm",                  NULL,   17,     0x110,  432000000, mux_pllp_pllc_clk32_clkm,    MUX | MUX_PWM | DIV_U71 | PERIPH_ON_APB),
+        PERIPH_CLK("d_audio",   "tegra30-ahub",         "d_audio", 106, 0x3d0,  48000000,  mux_plla_pllc_pllp_clkm,     MUX | DIV_U71),
+        PERIPH_CLK("dam0",      "tegra30-dam.0",        NULL,   108,    0x3d8,  48000000,  mux_plla_pllc_pllp_clkm,     MUX | DIV_U71),
+        PERIPH_CLK("dam1",      "tegra30-dam.1",        NULL,   109,    0x3dc,  48000000,  mux_plla_pllc_pllp_clkm,     MUX | DIV_U71),
+        PERIPH_CLK("dam2",      "tegra30-dam.2",        NULL,   110,    0x3e0,  48000000,  mux_plla_pllc_pllp_clkm,     MUX | DIV_U71),
+        PERIPH_CLK("hda",       "tegra30-hda",          "hda",   125,   0x428,  108000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71),
+        PERIPH_CLK("hda2codec_2x",      "tegra30-hda",  "hda2codec",   111,     0x3e4,  48000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71),
+        PERIPH_CLK("hda2hdmi",  "tegra30-hda",          "hda2hdmi",     128,    0,      48000000,  mux_clk_m,                   0),
+        PERIPH_CLK("sbc1",      "spi_tegra.0",          NULL,   41,     0x134,  160000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | PERIPH_ON_APB),
+        PERIPH_CLK("sbc2",      "spi_tegra.1",          NULL,   44,     0x118,  160000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | PERIPH_ON_APB),
+        PERIPH_CLK("sbc3",      "spi_tegra.2",          NULL,   46,     0x11c,  160000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | PERIPH_ON_APB),
+        PERIPH_CLK("sbc4",      "spi_tegra.3",          NULL,   68,     0x1b4,  160000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | PERIPH_ON_APB),
+        PERIPH_CLK("sbc5",      "spi_tegra.4",          NULL,   104,    0x3c8,  160000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | PERIPH_ON_APB),
+        PERIPH_CLK("sbc6",      "spi_tegra.5",          NULL,   105,    0x3cc,  160000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | PERIPH_ON_APB),
+        PERIPH_CLK("sata_oob",  "tegra_sata_oob",       NULL,   123,    0x420,  216000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71),
+        PERIPH_CLK("sata",      "tegra_sata",           NULL,   124,    0x424,  216000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71),
+        PERIPH_CLK("sata_cold", "tegra_sata_cold",      NULL,   129,    0,      48000000,  mux_clk_m,                   0),
+        PERIPH_CLK_EX("ndflash", "tegra_nand",          NULL,   13,     0x160,  240000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71,  &tegra_nand_clk_ops),
+        PERIPH_CLK("ndspeed",   "tegra_nand_speed",     NULL,   80,     0x3f8,  240000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71),
+        PERIPH_CLK("vfir",      "vfir",                 NULL,   7,      0x168,  72000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | PERIPH_ON_APB),
+        PERIPH_CLK("sdmmc1",    "sdhci-tegra.0",        NULL,   14,     0x150,  208000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71), /* scales with voltage */
+        PERIPH_CLK("sdmmc2",    "sdhci-tegra.1",        NULL,   9,      0x154,  104000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71), /* scales with voltage */
+        PERIPH_CLK("sdmmc3",    "sdhci-tegra.2",        NULL,   69,     0x1bc,  208000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71), /* scales with voltage */
+        PERIPH_CLK("sdmmc4",    "sdhci-tegra.3",        NULL,   15,     0x164,  104000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71), /* scales with voltage */
+        PERIPH_CLK("vcp",       "tegra-avp",            "vcp",  29,     0,      250000000, mux_clk_m,                   0),
+        PERIPH_CLK("bsea",      "tegra-avp",            "bsea", 62,     0,      250000000, mux_clk_m,                   0),
+        PERIPH_CLK("bsev",      "tegra-aes",            "bsev", 63,     0,      250000000, mux_clk_m,                   0),
+        PERIPH_CLK("vde",       "vde",                  NULL,   61,     0x1c8,  520000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | DIV_U71_INT),
+        PERIPH_CLK("csite",     "csite",                NULL,   73,     0x1d4,  144000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71), /* max rate ??? */
+        PERIPH_CLK("la",        "la",                   NULL,   76,     0x1f8,  26000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71),
+        PERIPH_CLK("owr",       "tegra_w1",             NULL,   71,     0x1cc,  26000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | PERIPH_ON_APB),
+        PERIPH_CLK("nor",       "nor",                  NULL,   42,     0x1d0,  127000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71), /* requires min voltage */
+        PERIPH_CLK("mipi",      "mipi",                 NULL,   50,     0x174,  60000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | PERIPH_ON_APB), /* scales with voltage */
+        PERIPH_CLK("i2c1",      "tegra-i2c.0",          NULL,   12,     0x124,  26000000,  mux_pllp_clkm,               MUX | DIV_U16 | PERIPH_ON_APB),
+        PERIPH_CLK("i2c2",      "tegra-i2c.1",          NULL,   54,     0x198,  26000000,  mux_pllp_clkm,               MUX | DIV_U16 | PERIPH_ON_APB),
+        PERIPH_CLK("i2c3",      "tegra-i2c.2",          NULL,   67,     0x1b8,  26000000,  mux_pllp_clkm,               MUX | DIV_U16 | PERIPH_ON_APB),
+        PERIPH_CLK("i2c4",      "tegra-i2c.3",          NULL,   103,    0x3c4,  26000000,  mux_pllp_clkm,               MUX | DIV_U16 | PERIPH_ON_APB),
+        PERIPH_CLK("i2c5",      "tegra-i2c.4",          NULL,   47,     0x128,  26000000,  mux_pllp_clkm,               MUX | DIV_U16 | PERIPH_ON_APB),
+        PERIPH_CLK("uarta",     "tegra_uart.0",         NULL,   6,      0x178,  800000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB),
+        PERIPH_CLK("uartb",     "tegra_uart.1",         NULL,   7,      0x17c,  800000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB),
+        PERIPH_CLK("uartc",     "tegra_uart.2",         NULL,   55,     0x1a0,  800000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB),
+        PERIPH_CLK("uartd",     "tegra_uart.3",         NULL,   65,     0x1c0,  800000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB),
+        PERIPH_CLK("uarte",     "tegra_uart.4",         NULL,   66,     0x1c4,  800000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB),
+        PERIPH_CLK("uarta_dbg", "serial8250.0",         "uarta", 6,     0x178,  800000000, mux_pllp_clkm,               MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB),
+        PERIPH_CLK("uartb_dbg", "serial8250.0",         "uartb", 7,     0x17c,  800000000, mux_pllp_clkm,               MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB),
+        PERIPH_CLK("uartc_dbg", "serial8250.0",         "uartc", 55,    0x1a0,  800000000, mux_pllp_clkm,               MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB),
+        PERIPH_CLK("uartd_dbg", "serial8250.0",         "uartd", 65,    0x1c0,  800000000, mux_pllp_clkm,               MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB),
+        PERIPH_CLK("uarte_dbg", "serial8250.0",         "uarte", 66,    0x1c4,  800000000, mux_pllp_clkm,               MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB),
+        PERIPH_CLK_EX("vi",     "tegra_camera",         "vi",   20,     0x148,  425000000, mux_pllm_pllc_pllp_plla,     MUX | DIV_U71 | DIV_U71_INT,    &tegra_vi_clk_ops),
+        PERIPH_CLK("3d",        "3d",                   NULL,   24,     0x158,  520000000, mux_pllm_pllc_pllp_plla,     MUX | DIV_U71 | DIV_U71_INT | DIV_U71_IDLE | PERIPH_MANUAL_RESET),
+        PERIPH_CLK("3d2",       "3d2",                  NULL,   98,     0x3b0,  520000000, mux_pllm_pllc_pllp_plla,     MUX | DIV_U71 | DIV_U71_INT | DIV_U71_IDLE | PERIPH_MANUAL_RESET),
+        PERIPH_CLK("2d",        "2d",                   NULL,   21,     0x15c,  520000000, mux_pllm_pllc_pllp_plla,     MUX | DIV_U71 | DIV_U71_INT | DIV_U71_IDLE),
+        PERIPH_CLK("vi_sensor", "tegra_camera",         "vi_sensor",    20,     0x1a8,  150000000, mux_pllm_pllc_pllp_plla,     MUX | DIV_U71 | PERIPH_NO_RESET),
+        PERIPH_CLK("epp",       "epp",                  NULL,   19,     0x16c,  520000000, mux_pllm_pllc_pllp_plla,     MUX | DIV_U71 | DIV_U71_INT),
+        PERIPH_CLK("mpe",       "mpe",                  NULL,   60,     0x170,  520000000, mux_pllm_pllc_pllp_plla,     MUX | DIV_U71 | DIV_U71_INT),
+        PERIPH_CLK("host1x",    "host1x",               NULL,   28,     0x180,  260000000, mux_pllm_pllc_pllp_plla,     MUX | DIV_U71 | DIV_U71_INT),
+        PERIPH_CLK("cve",       "cve",                  NULL,   49,     0x140,  250000000, mux_pllp_plld_pllc_clkm,     MUX | DIV_U71), /* requires min voltage */
+        PERIPH_CLK("tvo",       "tvo",                  NULL,   49,     0x188,  250000000, mux_pllp_plld_pllc_clkm,     MUX | DIV_U71), /* requires min voltage */
+        PERIPH_CLK_EX("dtv",    "dtv",                  NULL,   79,     0x1dc,  250000000, mux_clk_m,                   0,              &tegra_dtv_clk_ops),
+        PERIPH_CLK("hdmi",      "hdmi",                 NULL,   51,     0x18c,  148500000, mux_pllp_pllm_plld_plla_pllc_plld2_clkm,     MUX | MUX8 | DIV_U71),
+        PERIPH_CLK("tvdac",     "tvdac",                NULL,   53,     0x194,  220000000, mux_pllp_plld_pllc_clkm,     MUX | DIV_U71), /* requires min voltage */
+        PERIPH_CLK("disp1",     "tegradc.0",            NULL,   27,     0x138,  600000000, mux_pllp_pllm_plld_plla_pllc_plld2_clkm,     MUX | MUX8),
+        PERIPH_CLK("disp2",     "tegradc.1",            NULL,   26,     0x13c,  600000000, mux_pllp_pllm_plld_plla_pllc_plld2_clkm,     MUX | MUX8),
+        PERIPH_CLK("usbd",      "fsl-tegra-udc",        NULL,   22,     0,      480000000, mux_clk_m,                   0), /* requires min voltage */
+        PERIPH_CLK("usb2",      "tegra-ehci.1",         NULL,   58,     0,      480000000, mux_clk_m,                   0), /* requires min voltage */
+        PERIPH_CLK("usb3",      "tegra-ehci.2",         NULL,   59,     0,      480000000, mux_clk_m,                   0), /* requires min voltage */
+        PERIPH_CLK("dsia",      "tegradc.0",            "dsia", 48,     0,      500000000, mux_plld_out0,               0),
+        PERIPH_CLK_EX("dsib",   "tegradc.1",            "dsib", 82,     0xd0,   500000000, mux_plld_out0_plld2_out0,    MUX | PLLD,     &tegra_dsib_clk_ops),
+        PERIPH_CLK("csi",       "tegra_camera",         "csi",  52,     0,      102000000, mux_pllp_out3,               0),
+        PERIPH_CLK("isp",       "tegra_camera",         "isp",  23,     0,      150000000, mux_clk_m,                   0), /* same frequency as VI */
+        PERIPH_CLK("csus",      "tegra_camera",         "csus", 92,     0,      150000000, mux_clk_m,                   PERIPH_NO_RESET),
+
+        PERIPH_CLK("tsensor",   "tegra-tsensor",        NULL,   100,    0x3b8,  216000000, mux_pllp_pllc_clkm_clk32,    MUX | DIV_U71),
+        PERIPH_CLK("actmon",    "actmon",               NULL,   119,    0x3e8,  216000000, mux_pllp_pllc_clk32_clkm,    MUX | DIV_U71),
+        PERIPH_CLK("extern1",   "extern1",              NULL,   120,    0x3ec,  216000000, mux_plla_clk32_pllp_clkm_plle,       MUX | MUX8 | DIV_U71),
+        PERIPH_CLK("extern2",   "extern2",              NULL,   121,    0x3f0,  216000000, mux_plla_clk32_pllp_clkm_plle,       MUX | MUX8 | DIV_U71),
+        PERIPH_CLK("extern3",   "extern3",              NULL,   122,    0x3f4,  216000000, mux_plla_clk32_pllp_clkm_plle,       MUX | MUX8 | DIV_U71),
+        PERIPH_CLK("i2cslow",   "i2cslow",              NULL,   81,     0x3fc,  26000000,  mux_pllp_pllc_clk32_clkm,    MUX | DIV_U71 | PERIPH_ON_APB),
+        PERIPH_CLK("pcie",      "tegra-pcie",           "pcie", 70,     0,      250000000, mux_clk_m,                   0),
+        PERIPH_CLK("afi",       "tegra-pcie",           "afi",  72,     0,      250000000, mux_clk_m,                   0),
+        PERIPH_CLK("se",        "se",                   NULL,   127,    0x42c,  520000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | DIV_U71_INT),
+};
+
+#define CLK_DUPLICATE(_name, _dev, _con)                \
+        {                                               \
+                .name   = _name,                        \
+                .lookup = {                             \
+                        .dev_id = _dev,                 \
+                        .con_id         = _con,         \
+                },                                      \
+        }
+
+/* Some clocks may be used by different drivers depending on the board
+ * configuration.  List those here to register them twice in the clock lookup
+ * table under two names.
+ */
+struct clk_duplicate tegra_clk_duplicates[] = {
+        CLK_DUPLICATE("usbd", "utmip-pad", NULL),
+        CLK_DUPLICATE("usbd", "tegra-ehci.0", NULL),
+        CLK_DUPLICATE("usbd", "tegra-otg", NULL),
+        CLK_DUPLICATE("hdmi", "tegradc.0", "hdmi"),
+        CLK_DUPLICATE("hdmi", "tegradc.1", "hdmi"),
+        CLK_DUPLICATE("dsib", "tegradc.0", "dsib"),
+        CLK_DUPLICATE("dsia", "tegradc.1", "dsia"),
+        CLK_DUPLICATE("pwm", "tegra_pwm.0", NULL),
+        CLK_DUPLICATE("pwm", "tegra_pwm.1", NULL),
+        CLK_DUPLICATE("pwm", "tegra_pwm.2", NULL),
+        CLK_DUPLICATE("pwm", "tegra_pwm.3", NULL),
+        CLK_DUPLICATE("bsev", "tegra-avp", "bsev"),
+        CLK_DUPLICATE("bsev", "nvavp", "bsev"),
+        CLK_DUPLICATE("vde", "tegra-aes", "vde"),
+        CLK_DUPLICATE("bsea", "tegra-aes", "bsea"),
+        CLK_DUPLICATE("bsea", "nvavp", "bsea"),
+        CLK_DUPLICATE("cml1", "tegra_sata_cml", NULL),
+        CLK_DUPLICATE("cml0", "tegra_pcie", "cml"),
+        CLK_DUPLICATE("pciex", "tegra_pcie", "pciex"),
+        CLK_DUPLICATE("i2c1", "tegra-i2c-slave.0", NULL),
+        CLK_DUPLICATE("i2c2", "tegra-i2c-slave.1", NULL),
+        CLK_DUPLICATE("i2c3", "tegra-i2c-slave.2", NULL),
+        CLK_DUPLICATE("i2c4", "tegra-i2c-slave.3", NULL),
+        CLK_DUPLICATE("i2c5", "tegra-i2c-slave.4", NULL),
+        CLK_DUPLICATE("sbc1", "spi_slave_tegra.0", NULL),
+        CLK_DUPLICATE("sbc2", "spi_slave_tegra.1", NULL),
+        CLK_DUPLICATE("sbc3", "spi_slave_tegra.2", NULL),
+        CLK_DUPLICATE("sbc4", "spi_slave_tegra.3", NULL),
+        CLK_DUPLICATE("sbc5", "spi_slave_tegra.4", NULL),
+        CLK_DUPLICATE("sbc6", "spi_slave_tegra.5", NULL),
+        CLK_DUPLICATE("twd", "smp_twd", NULL),
+        CLK_DUPLICATE("vcp", "nvavp", "vcp"),
+};
+
+struct clk *tegra_ptr_clks[] = {
+        &tegra_clk_32k,
+        &tegra_clk_m,
+        &tegra_clk_m_div2,
+        &tegra_clk_m_div4,
+        &tegra_pll_ref,
+        &tegra_pll_m,
+        &tegra_pll_m_out1,
+        &tegra_pll_c,
+        &tegra_pll_c_out1,
+        &tegra_pll_p,
+        &tegra_pll_p_out1,
+        &tegra_pll_p_out2,
+        &tegra_pll_p_out3,
+        &tegra_pll_p_out4,
+        &tegra_pll_a,
+        &tegra_pll_a_out0,
+        &tegra_pll_d,
+        &tegra_pll_d_out0,
+        &tegra_pll_d2,
+        &tegra_pll_d2_out0,
+        &tegra_pll_u,
+        &tegra_pll_x,
+        &tegra_pll_x_out0,
+        &tegra_pll_e,
+        &tegra_clk_cclk_g,
+        &tegra_cml0_clk,
+        &tegra_cml1_clk,
+        &tegra_pciex_clk,
+        &tegra_clk_sclk,
+        &tegra_clk_blink,
+        &tegra30_clk_twd,
+};
+
+
+static void tegra30_init_one_clock(struct clk *c)
+{
+        clk_init(c);
+        INIT_LIST_HEAD(&c->shared_bus_list);
+        if (!c->lookup.dev_id && !c->lookup.con_id)
+                c->lookup.con_id = c->name;
+        c->lookup.clk = c;
+        clkdev_add(&c->lookup);
+}
+
+void __init tegra30_init_clocks(void)
+{
+        int i;
+        struct clk *c;
+
+        for (i = 0; i < ARRAY_SIZE(tegra_ptr_clks); i++)
+                tegra30_init_one_clock(tegra_ptr_clks[i]);
+
+        for (i = 0; i < ARRAY_SIZE(tegra_list_clks); i++)
+                tegra30_init_one_clock(&tegra_list_clks[i]);
+
+        for (i = 0; i < ARRAY_SIZE(tegra_clk_duplicates); i++) {
+                c = tegra_get_clock_by_name(tegra_clk_duplicates[i].name);
+                if (!c) {
+                        pr_err("%s: Unknown duplicate clock %s\n", __func__,
+                                tegra_clk_duplicates[i].name);
+                        continue;
+                }
+
+                tegra_clk_duplicates[i].lookup.clk = c;
+                clkdev_add(&tegra_clk_duplicates[i].lookup);
+        }
+
+        for (i = 0; i < ARRAY_SIZE(tegra_sync_source_list); i++)
+                tegra30_init_one_clock(&tegra_sync_source_list[i]);
+        for (i = 0; i < ARRAY_SIZE(tegra_clk_audio_list); i++)
+                tegra30_init_one_clock(&tegra_clk_audio_list[i]);
+        for (i = 0; i < ARRAY_SIZE(tegra_clk_audio_2x_list); i++)
+                tegra30_init_one_clock(&tegra_clk_audio_2x_list[i]);
+
+        init_clk_out_mux();
+        for (i = 0; i < ARRAY_SIZE(tegra_clk_out_list); i++)
+                tegra30_init_one_clock(&tegra_clk_out_list[i]);
+
+}
diff --git a/arch/arm/mach-tegra/timer.c b/arch/arm/mach-tegra/timer.c
index 1d1acda4f3e..1eed8d4a80e 100644
--- a/arch/arm/mach-tegra/timer.c
+++ b/arch/arm/mach-tegra/timer.c
@@ -28,7 +28,7 @@
 #include <linux/io.h>
 
 #include <asm/mach/time.h>
-#include <asm/localtimer.h>
+#include <asm/smp_twd.h>
 #include <asm/sched_clock.h>
 
 #include <mach/iomap.h>
@@ -162,6 +162,21 @@ static struct irqaction tegra_timer_irq = {
         .irq            = INT_TMR3,
 };
 
+#ifdef CONFIG_HAVE_ARM_TWD
+static DEFINE_TWD_LOCAL_TIMER(twd_local_timer,
+                              TEGRA_ARM_PERIF_BASE + 0x600,
+                              IRQ_LOCALTIMER);
+
+static void __init tegra_twd_init(void)
+{
+        int err = twd_local_timer_register(&twd_local_timer);
+        if (err)
+                pr_err("twd_local_timer_register failed %d\n", err);
+}
+#else
+#define tegra_twd_init()        do {} while(0)
+#endif
+
 static void __init tegra_init_timer(void)
 {
         struct clk *clk;
@@ -188,10 +203,6 @@ static void __init tegra_init_timer(void)
         else
                 clk_enable(clk);
 
-#ifdef CONFIG_HAVE_ARM_TWD
-        twd_base = IO_ADDRESS(TEGRA_ARM_PERIF_BASE + 0x600);
-#endif
-
         switch (rate) {
         case 12000000:
                 timer_writel(0x000b, TIMERUS_USEC_CFG);
@@ -231,6 +242,7 @@ static void __init tegra_init_timer(void)
         tegra_clockevent.cpumask = cpu_all_mask;
         tegra_clockevent.irq = tegra_timer_irq.irq;
         clockevents_register_device(&tegra_clockevent);
+        tegra_twd_init();
 }
 
 struct sys_timer tegra_timer = {
diff --git a/arch/arm/mach-tegra/usb_phy.c b/arch/arm/mach-tegra/usb_phy.c
index ad321f9e2bb..c5b2ac04e2a 100644
--- a/arch/arm/mach-tegra/usb_phy.c
+++ b/arch/arm/mach-tegra/usb_phy.c
@@ -22,6 +22,7 @@
 #include <linux/delay.h>
 #include <linux/slab.h>
 #include <linux/err.h>
+#include <linux/export.h>
 #include <linux/platform_device.h>
 #include <linux/io.h>
 #include <linux/gpio.h>
@@ -730,6 +731,7 @@ err0:
         kfree(phy);
         return ERR_PTR(err);
 }
+EXPORT_SYMBOL_GPL(tegra_usb_phy_open);
 
 int tegra_usb_phy_power_on(struct tegra_usb_phy *phy)
 {
@@ -738,6 +740,7 @@ int tegra_usb_phy_power_on(struct tegra_usb_phy *phy)
         else
                 return utmi_phy_power_on(phy);
 }
+EXPORT_SYMBOL_GPL(tegra_usb_phy_power_on);
 
 void tegra_usb_phy_power_off(struct tegra_usb_phy *phy)
 {
@@ -746,18 +749,21 @@ void tegra_usb_phy_power_off(struct tegra_usb_phy *phy)
         else
                 utmi_phy_power_off(phy);
 }
+EXPORT_SYMBOL_GPL(tegra_usb_phy_power_off);
 
 void tegra_usb_phy_preresume(struct tegra_usb_phy *phy)
 {
         if (!phy_is_ulpi(phy))
                 utmi_phy_preresume(phy);
 }
+EXPORT_SYMBOL_GPL(tegra_usb_phy_preresume);
 
 void tegra_usb_phy_postresume(struct tegra_usb_phy *phy)
 {
         if (!phy_is_ulpi(phy))
                 utmi_phy_postresume(phy);
 }
+EXPORT_SYMBOL_GPL(tegra_usb_phy_postresume);
 
 void tegra_ehci_phy_restore_start(struct tegra_usb_phy *phy,
                                  enum tegra_usb_phy_port_speed port_speed)
@@ -765,24 +771,28 @@ void tegra_ehci_phy_restore_start(struct tegra_usb_phy *phy,
         if (!phy_is_ulpi(phy))
                 utmi_phy_restore_start(phy, port_speed);
 }
+EXPORT_SYMBOL_GPL(tegra_ehci_phy_restore_start);
 
 void tegra_ehci_phy_restore_end(struct tegra_usb_phy *phy)
 {
         if (!phy_is_ulpi(phy))
                 utmi_phy_restore_end(phy);
 }
+EXPORT_SYMBOL_GPL(tegra_ehci_phy_restore_end);
 
 void tegra_usb_phy_clk_disable(struct tegra_usb_phy *phy)
 {
         if (!phy_is_ulpi(phy))
                 utmi_phy_clk_disable(phy);
 }
+EXPORT_SYMBOL_GPL(tegra_usb_phy_clk_disable);
 
 void tegra_usb_phy_clk_enable(struct tegra_usb_phy *phy)
 {
         if (!phy_is_ulpi(phy))
                 utmi_phy_clk_enable(phy);
 }
+EXPORT_SYMBOL_GPL(tegra_usb_phy_clk_enable);
 
 void tegra_usb_phy_close(struct tegra_usb_phy *phy)
 {
@@ -794,3 +804,4 @@ void tegra_usb_phy_close(struct tegra_usb_phy *phy)
         clk_put(phy->pll_u);
         kfree(phy);
 }
+EXPORT_SYMBOL_GPL(tegra_usb_phy_close);
diff --git a/arch/arm/mach-u300/Makefile b/arch/arm/mach-u300/Makefile
index 285538124e5..fd3a5c382f4 100644
--- a/arch/arm/mach-u300/Makefile
+++ b/arch/arm/mach-u300/Makefile
@@ -8,7 +8,6 @@ obj-n		:=
 obj-            :=
 
 obj-$(CONFIG_ARCH_U300)           += u300.o
-obj-$(CONFIG_MMC)                 += mmc.o
 obj-$(CONFIG_SPI_PL022)           += spi.o
 obj-$(CONFIG_MACH_U300_SPIDUMMY)  += dummyspichip.o
 obj-$(CONFIG_I2C_STU300)          += i2c.o
diff --git a/arch/arm/mach-u300/core.c b/arch/arm/mach-u300/core.c
index b4c6926a700..8b90c44d237 100644
--- a/arch/arm/mach-u300/core.c
+++ b/arch/arm/mach-u300/core.c
@@ -18,6 +18,7 @@
 #include <linux/termios.h>
 #include <linux/dmaengine.h>
 #include <linux/amba/bus.h>
+#include <linux/amba/mmci.h>
 #include <linux/amba/serial.h>
 #include <linux/platform_device.h>
 #include <linux/gpio.h>
@@ -26,7 +27,8 @@
 #include <linux/mtd/nand.h>
 #include <linux/mtd/fsmc.h>
 #include <linux/pinctrl/machine.h>
-#include <linux/pinctrl/pinmux.h>
+#include <linux/pinctrl/consumer.h>
+#include <linux/pinctrl/pinconf-generic.h>
 #include <linux/dma-mapping.h>
 
 #include <asm/types.h>
@@ -43,9 +45,9 @@
 #include <mach/gpio-u300.h>
 
 #include "clock.h"
-#include "mmc.h"
 #include "spi.h"
 #include "i2c.h"
+#include "u300-gpio.h"
 
 /*
  * Static I/O mappings that are needed for booting the U300 platforms. The
@@ -94,19 +96,9 @@ static struct amba_pl011_data uart0_plat_data = {
 #endif
 };
 
-static struct amba_device uart0_device = {
-        .dev = {
-                .coherent_dma_mask = ~0,
-                .init_name = "uart0", /* Slow device at 0x3000 offset */
-                .platform_data = &uart0_plat_data,
-        },
-        .res = {
-                .start = U300_UART0_BASE,
-                .end   = U300_UART0_BASE + SZ_4K - 1,
-                .flags = IORESOURCE_MEM,
-        },
-        .irq = { IRQ_U300_UART0, NO_IRQ },
-};
+/* Slow device at 0x3000 offset */
+static AMBA_APB_DEVICE(uart0, "uart0", 0, U300_UART0_BASE,
+        { IRQ_U300_UART0 }, &uart0_plat_data);
 
 /* The U335 have an additional UART1 on the APP CPU */
 #ifdef CONFIG_MACH_U300_BS335
@@ -118,72 +110,42 @@ static struct amba_pl011_data uart1_plat_data = {
 #endif
 };
 
-static struct amba_device uart1_device = {
-        .dev = {
-                .coherent_dma_mask = ~0,
-                .init_name = "uart1", /* Fast device at 0x7000 offset */
-                .platform_data = &uart1_plat_data,
-        },
-        .res = {
-                .start = U300_UART1_BASE,
-                .end   = U300_UART1_BASE + SZ_4K - 1,
-                .flags = IORESOURCE_MEM,
-        },
-        .irq = { IRQ_U300_UART1, NO_IRQ },
-};
+/* Fast device at 0x7000 offset */
+static AMBA_APB_DEVICE(uart1, "uart1", 0, U300_UART1_BASE,
+        { IRQ_U300_UART1 }, &uart1_plat_data);
 #endif
 
-static struct amba_device pl172_device = {
-        .dev = {
-                .init_name = "pl172", /* AHB device at 0x4000 offset */
-                .platform_data = NULL,
-        },
-        .res = {
-                .start = U300_EMIF_CFG_BASE,
-                .end   = U300_EMIF_CFG_BASE + SZ_4K - 1,
-                .flags = IORESOURCE_MEM,
-        },
-};
+/* AHB device at 0x4000 offset */
+static AMBA_APB_DEVICE(pl172, "pl172", 0, U300_EMIF_CFG_BASE, { }, NULL);
 
+/* Fast device at 0x6000 offset */
+static AMBA_APB_DEVICE(pl022, "pl022", 0, U300_SPI_BASE,
+        { IRQ_U300_SPI }, NULL);
 
-/*
- * Everything within this next ifdef deals with external devices connected to
- * the APP SPI bus.
- */
-static struct amba_device pl022_device = {
-        .dev = {
-                .coherent_dma_mask = ~0,
-                .init_name = "pl022", /* Fast device at 0x6000 offset */
-        },
-        .res = {
-                .start = U300_SPI_BASE,
-                .end   = U300_SPI_BASE + SZ_4K - 1,
-                .flags = IORESOURCE_MEM,
-        },
-        .irq = {IRQ_U300_SPI, NO_IRQ },
-        /*
-         * This device has a DMA channel but the Linux driver does not use
-         * it currently.
-         */
-};
+/* Fast device at 0x1000 offset */
+#define U300_MMCSD_IRQS { IRQ_U300_MMCSD_MCIINTR0, IRQ_U300_MMCSD_MCIINTR1 }
 
-static struct amba_device mmcsd_device = {
-        .dev = {
-                .init_name = "mmci", /* Fast device at 0x1000 offset */
-                .platform_data = NULL, /* Added later */
-        },
-        .res = {
-                .start = U300_MMCSD_BASE,
-                .end   = U300_MMCSD_BASE + SZ_4K - 1,
-                .flags = IORESOURCE_MEM,
-        },
-        .irq = {IRQ_U300_MMCSD_MCIINTR0, IRQ_U300_MMCSD_MCIINTR1 },
+static struct mmci_platform_data mmcsd_platform_data = {
         /*
-         * This device has a DMA channel but the Linux driver does not use
-         * it currently.
+         * Do not set ocr_mask or voltage translation function,
+         * we have a regulator we can control instead.
          */
+        .f_max = 24000000,
+        .gpio_wp = -1,
+        .gpio_cd = U300_GPIO_PIN_MMC_CD,
+        .cd_invert = true,
+        .capabilities = MMC_CAP_MMC_HIGHSPEED |
+        MMC_CAP_SD_HIGHSPEED | MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA,
+#ifdef CONFIG_COH901318
+        .dma_filter = coh901318_filter_id,
+        .dma_rx_param = (void *) U300_DMA_MMCSD_RX_TX,
+        /* Don't specify a TX channel, this RX channel is bidirectional */
+#endif
 };
 
+static AMBA_APB_DEVICE(mmcsd, "mmci", 0, U300_MMCSD_BASE,
+        U300_MMCSD_IRQS, &mmcsd_platform_data);
+
 /*
  * The order of device declaration may be important, since some devices
  * have dependencies on other devices being initialized first.
@@ -1477,7 +1439,7 @@ static struct coh901318_platform coh901318_platform = {
         .max_channels = U300_DMA_CHANNELS,
 };
 
-static struct resource pinmux_resources[] = {
+static struct resource pinctrl_resources[] = {
         {
                 .start = U300_SYSCON_BASE,
                 .end   = U300_SYSCON_BASE + SZ_4K - 1,
@@ -1506,6 +1468,13 @@ static struct platform_device i2c1_device = {
         .resource = i2c1_resources,
 };
 
+static struct platform_device pinctrl_device = {
+        .name = "pinctrl-u300",
+        .id = -1,
+        .num_resources = ARRAY_SIZE(pinctrl_resources),
+        .resource = pinctrl_resources,
+};
+
 /*
  * The different variants have a few different versions of the
  * GPIO block, with different number of ports.
@@ -1525,6 +1494,7 @@ static struct u300_gpio_platform u300_gpio_plat = {
 #endif
         .gpio_base = 0,
         .gpio_irq_base = IRQ_U300_GPIO_BASE,
+        .pinctrl_device = &pinctrl_device,
 };
 
 static struct platform_device gpio_device = {
@@ -1597,71 +1567,67 @@ static struct platform_device dma_device = {
         },
 };
 
-static struct platform_device pinmux_device = {
-        .name = "pinmux-u300",
-        .id = -1,
-        .num_resources = ARRAY_SIZE(pinmux_resources),
-        .resource = pinmux_resources,
+static unsigned long pin_pullup_conf[] = {
+        PIN_CONF_PACKED(PIN_CONFIG_BIAS_PULL_UP, 1),
+};
+
+static unsigned long pin_highz_conf[] = {
+        PIN_CONF_PACKED(PIN_CONFIG_BIAS_HIGH_IMPEDANCE, 0),
 };
 
-/* Pinmux settings */
-static struct pinmux_map __initdata u300_pinmux_map[] = {
+/* Pin control settings */
+static struct pinctrl_map __initdata u300_pinmux_map[] = {
         /* anonymous maps for chip power and EMIFs */
-        PINMUX_MAP_SYS_HOG("POWER", "pinmux-u300", "power"),
-        PINMUX_MAP_SYS_HOG("EMIF0", "pinmux-u300", "emif0"),
-        PINMUX_MAP_SYS_HOG("EMIF1", "pinmux-u300", "emif1"),
+        PIN_MAP_MUX_GROUP_HOG_DEFAULT("pinctrl-u300", NULL, "power"),
+        PIN_MAP_MUX_GROUP_HOG_DEFAULT("pinctrl-u300", NULL, "emif0"),
+        PIN_MAP_MUX_GROUP_HOG_DEFAULT("pinctrl-u300", NULL, "emif1"),
         /* per-device maps for MMC/SD, SPI and UART */
-        PINMUX_MAP("MMCSD", "pinmux-u300", "mmc0", "mmci"),
-        PINMUX_MAP("SPI", "pinmux-u300", "spi0", "pl022"),
-        PINMUX_MAP("UART0", "pinmux-u300", "uart0", "uart0"),
+        PIN_MAP_MUX_GROUP_DEFAULT("mmci",  "pinctrl-u300", NULL, "mmc0"),
+        PIN_MAP_MUX_GROUP_DEFAULT("pl022", "pinctrl-u300", NULL, "spi0"),
+        PIN_MAP_MUX_GROUP_DEFAULT("uart0", "pinctrl-u300", NULL, "uart0"),
+        /* This pin is used for clock return rather than GPIO */
+        PIN_MAP_CONFIGS_PIN_DEFAULT("mmci", "pinctrl-u300", "PIO APP GPIO 11",
+                                    pin_pullup_conf),
+        /* This pin is used for card detect */
+        PIN_MAP_CONFIGS_PIN_DEFAULT("mmci", "pinctrl-u300", "PIO MS INS",
+                                    pin_highz_conf),
 };
 
 struct u300_mux_hog {
-        const char *name;
         struct device *dev;
-        struct pinmux *pmx;
+        struct pinctrl *p;
 };
 
 static struct u300_mux_hog u300_mux_hogs[] = {
         {
-                .name = "uart0",
                 .dev = &uart0_device.dev,
         },
         {
-                .name = "spi0",
                 .dev = &pl022_device.dev,
         },
         {
-                .name = "mmc0",
                 .dev = &mmcsd_device.dev,
         },
 };
 
-static int __init u300_pinmux_fetch(void)
+static int __init u300_pinctrl_fetch(void)
 {
         int i;
 
         for (i = 0; i < ARRAY_SIZE(u300_mux_hogs); i++) {
-                struct pinmux *pmx;
-                int ret;
+                struct pinctrl *p;
 
-                pmx = pinmux_get(u300_mux_hogs[i].dev, NULL);
-                if (IS_ERR(pmx)) {
-                        pr_err("u300: could not get pinmux hog %s\n",
-                               u300_mux_hogs[i].name);
-                        continue;
-                }
-                ret = pinmux_enable(pmx);
-                if (ret) {
-                        pr_err("u300: could enable pinmux hog %s\n",
-                               u300_mux_hogs[i].name);
+                p = pinctrl_get_select_default(u300_mux_hogs[i].dev);
+                if (IS_ERR(p)) {
+                        pr_err("u300: could not get pinmux hog for dev %s\n",
+                               dev_name(u300_mux_hogs[i].dev));
                         continue;
                 }
-                u300_mux_hogs[i].pmx = pmx;
+                u300_mux_hogs[i].p = p;
         }
         return 0;
 }
-subsys_initcall(u300_pinmux_fetch);
+subsys_initcall(u300_pinctrl_fetch);
 
 /*
  * Notice that AMBA devices are initialized before platform devices.
@@ -1676,7 +1642,6 @@ static struct platform_device *platform_devs[] __initdata = {
         &gpio_device,
         &nand_device,
         &wdog_device,
-        &pinmux_device,
 };
 
 /*
@@ -1861,8 +1826,8 @@ void __init u300_init_devices(void)
         u300_assign_physmem();
 
         /* Initialize pinmuxing */
-        pinmux_register_mappings(u300_pinmux_map,
-                                 ARRAY_SIZE(u300_pinmux_map));
+        pinctrl_register_mappings(u300_pinmux_map,
+                                  ARRAY_SIZE(u300_pinmux_map));
 
         /* Register subdevices on the I2C buses */
         u300_i2c_register_board_devices();
@@ -1879,16 +1844,6 @@ void __init u300_init_devices(void)
         writew(val, U300_SYSCON_VBASE + U300_SYSCON_SMCR);
 }
 
-static int core_module_init(void)
-{
-        /*
-         * This needs to be initialized later: it needs the input framework
-         * to be initialized first.
-         */
-        return mmc_init(&mmcsd_device);
-}
-module_init(core_module_init);
-
 /* Forward declare this function from the watchdog */
 void coh901327_watchdog_reset(void);
 
diff --git a/arch/arm/mach-u300/include/mach/entry-macro.S b/arch/arm/mach-u300/include/mach/entry-macro.S
deleted file mode 100644
index 7181d6ac665..00000000000
--- a/arch/arm/mach-u300/include/mach/entry-macro.S
+++ /dev/null
@@ -1,16 +0,0 @@
-/*
- *
- * arch-arm/mach-u300/include/mach/entry-macro.S
- *
- *
- * Copyright (C) 2006-2009 ST-Ericsson AB
- * License terms: GNU General Public License (GPL) version 2
- * Low-level IRQ helper macros for ST-Ericsson U300
- * Author: Linus Walleij <linus.walleij@stericsson.com>
- */
-
-        .macro  disable_fiq
-        .endm
-
-        .macro  arch_ret_to_user, tmp1, tmp2
-        .endm
diff --git a/arch/arm/mach-u300/include/mach/gpio-u300.h b/arch/arm/mach-u300/include/mach/gpio-u300.h
index bf4c7935aec..e81400c1753 100644
--- a/arch/arm/mach-u300/include/mach/gpio-u300.h
+++ b/arch/arm/mach-u300/include/mach/gpio-u300.h
@@ -24,12 +24,14 @@ enum u300_gpio_variant {
  * @ports: number of GPIO block ports
  * @gpio_base: first GPIO number for this block (use a free range)
  * @gpio_irq_base: first GPIO IRQ number for this block (use a free range)
+ * @pinctrl_device: pin control device to spawn as child
  */
 struct u300_gpio_platform {
         enum u300_gpio_variant variant;
         u8 ports;
         int gpio_base;
         int gpio_irq_base;
+        struct platform_device *pinctrl_device;
 };
 
 #endif /* __MACH_U300_GPIO_U300_H */
diff --git a/arch/arm/mach-u300/include/mach/system.h b/arch/arm/mach-u300/include/mach/system.h
deleted file mode 100644
index 574d46e3829..00000000000
--- a/arch/arm/mach-u300/include/mach/system.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/*
- *
- * arch/arm/mach-u300/include/mach/system.h
- *
- *
- * Copyright (C) 2007-2009 ST-Ericsson AB
- * License terms: GNU General Public License (GPL) version 2
- * System shutdown and reset functions.
- * Author: Linus Walleij <linus.walleij@stericsson.com>
- */
-static inline void arch_idle(void)
-{
-        cpu_do_idle();
-}
diff --git a/arch/arm/mach-u300/mmc.c b/arch/arm/mach-u300/mmc.c
deleted file mode 100644
index 05abd6ad9fa..00000000000
--- a/arch/arm/mach-u300/mmc.c
+++ /dev/null
@@ -1,52 +0,0 @@
-/*
- *
- * arch/arm/mach-u300/mmc.c
- *
- *
- * Copyright (C) 2009 ST-Ericsson SA
- * License terms: GNU General Public License (GPL) version 2
- *
- * Author: Linus Walleij <linus.walleij@stericsson.com>
- * Author: Johan Lundin
- * Author: Jonas Aaberg <jonas.aberg@stericsson.com>
- */
-#include <linux/device.h>
-#include <linux/amba/bus.h>
-#include <linux/mmc/host.h>
-#include <linux/dmaengine.h>
-#include <linux/amba/mmci.h>
-#include <linux/slab.h>
-#include <mach/coh901318.h>
-#include <mach/dma_channels.h>
-
-#include "u300-gpio.h"
-#include "mmc.h"
-
-static struct mmci_platform_data mmc0_plat_data = {
-        /*
-         * Do not set ocr_mask or voltage translation function,
-         * we have a regulator we can control instead.
-         */
-        /* Nominally 2.85V on our platform */
-        .f_max = 24000000,
-        .gpio_wp = -1,
-        .gpio_cd = U300_GPIO_PIN_MMC_CD,
-        .cd_invert = true,
-        .capabilities = MMC_CAP_MMC_HIGHSPEED |
-        MMC_CAP_SD_HIGHSPEED | MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA,
-#ifdef CONFIG_COH901318
-        .dma_filter = coh901318_filter_id,
-        .dma_rx_param = (void *) U300_DMA_MMCSD_RX_TX,
-        /* Don't specify a TX channel, this RX channel is bidirectional */
-#endif
-};
-
-int __devinit mmc_init(struct amba_device *adev)
-{
-        struct device *mmcsd_device = &adev->dev;
-        int ret = 0;
-
-        mmcsd_device->platform_data = &mmc0_plat_data;
-
-        return ret;
-}
diff --git a/arch/arm/mach-u300/mmc.h b/arch/arm/mach-u300/mmc.h
deleted file mode 100644
index 92b85125abb..00000000000
--- a/arch/arm/mach-u300/mmc.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/*
- *
- * arch/arm/mach-u300/mmc.h
- *
- *
- * Copyright (C) 2009 ST-Ericsson AB
- * License terms: GNU General Public License (GPL) version 2
- *
- * Author: Jonas Aaberg <jonas.aberg@stericsson.com>
- */
-#ifndef MMC_H
-#define MMC_H
-
-#include <linux/amba/bus.h>
-
-int __devinit mmc_init(struct amba_device *adev);
-
-#endif
diff --git a/arch/arm/mach-ux500/Kconfig b/arch/arm/mach-ux500/Kconfig
index c59e8b892d6..9ec63581234 100644
--- a/arch/arm/mach-ux500/Kconfig
+++ b/arch/arm/mach-ux500/Kconfig
@@ -8,47 +8,55 @@ config UX500_SOC_COMMON
         select PL310_ERRATA_753970
         select ARM_ERRATA_754322
         select ARM_ERRATA_764369
-
-menu "Ux500 SoC"
+        select CACHE_L2X0
 
 config UX500_SOC_DB5500
-        bool "DB5500"
+        bool
         select MFD_DB5500_PRCMU
 
 config UX500_SOC_DB8500
-        bool "DB8500"
+        bool
         select MFD_DB8500_PRCMU
         select REGULATOR_DB8500_PRCMU
-
-endmenu
+        select CPU_FREQ_TABLE if CPU_FREQ
 
 menu "Ux500 target platform (boards)"
 
-config MACH_U8500
-        bool "U8500 Development platform"
-        depends on UX500_SOC_DB8500
-        select TPS6105X
+config MACH_MOP500
+        bool "U8500 Development platform, MOP500 versions"
+        select UX500_SOC_DB8500
+        select I2C
+        select I2C_NOMADIK
         help
-          Include support for the mop500 development platform.
+          Include support for the MOP500 development platform.
 
 config MACH_HREFV60
-       bool "U85000 Development platform, HREFv60 version"
-       depends on UX500_SOC_DB8500
-       help
-         Include support for the HREFv60 new development platform.
+        bool "U8500 Development platform, HREFv60 version"
+        select MACH_MOP500
+        help
+          Include support for the HREFv60 new development platform.
+          Includes HREFv70, v71 etc.
 
 config MACH_SNOWBALL
         bool "U8500 Snowball platform"
-        depends on UX500_SOC_DB8500
-        select MACH_U8500
+        select MACH_MOP500
         help
           Include support for the snowball development platform.
 
 config MACH_U5500
         bool "U5500 Development platform"
-        depends on UX500_SOC_DB5500
+        select UX500_SOC_DB5500
         help
           Include support for the U5500 development platform.
+
+config UX500_AUTO_PLATFORM
+        def_bool y
+        depends on !MACH_U5500
+        select MACH_MOP500
+        help
+          At least one platform needs to be selected in order to build
+          a working kernel. If everything else is disabled, this
+          automatically enables MACH_MOP500.
 endmenu
 
 config UX500_DEBUG_UART
diff --git a/arch/arm/mach-ux500/Makefile b/arch/arm/mach-ux500/Makefile
index 6bd2f451c18..465b9ec9510 100644
--- a/arch/arm/mach-ux500/Makefile
+++ b/arch/arm/mach-ux500/Makefile
@@ -7,7 +7,7 @@ obj-y				:= clock.o cpu.o devices.o devices-common.o \
 obj-$(CONFIG_CACHE_L2X0)        += cache-l2x0.o
 obj-$(CONFIG_UX500_SOC_DB5500)  += cpu-db5500.o dma-db5500.o
 obj-$(CONFIG_UX500_SOC_DB8500)  += cpu-db8500.o devices-db8500.o
-obj-$(CONFIG_MACH_U8500)        += board-mop500.o board-mop500-sdi.o \
+obj-$(CONFIG_MACH_MOP500)       += board-mop500.o board-mop500-sdi.o \
                                 board-mop500-regulators.o \
                                 board-mop500-uib.o board-mop500-stuib.o \
                                 board-mop500-u8500uib.o \
@@ -15,7 +15,6 @@ obj-$(CONFIG_MACH_U8500)	+= board-mop500.o board-mop500-sdi.o \
 obj-$(CONFIG_MACH_U5500)        += board-u5500.o board-u5500-sdi.o
 obj-$(CONFIG_SMP)               += platsmp.o headsmp.o
 obj-$(CONFIG_HOTPLUG_CPU)       += hotplug.o
-obj-$(CONFIG_LOCAL_TIMERS)      += localtimer.o
 obj-$(CONFIG_U5500_MODEM_IRQ)   += modem-irq-db5500.o
 obj-$(CONFIG_U5500_MBOX)        += mbox-db5500.o
 
diff --git a/arch/arm/mach-ux500/board-mop500-pins.c b/arch/arm/mach-ux500/board-mop500-pins.c
index 74bfcff2bdf..f5413dca532 100644
--- a/arch/arm/mach-ux500/board-mop500-pins.c
+++ b/arch/arm/mach-ux500/board-mop500-pins.c
@@ -6,6 +6,7 @@
 
 #include <linux/kernel.h>
 #include <linux/init.h>
+#include <linux/bug.h>
 
 #include <asm/mach-types.h>
 #include <plat/pincfg.h>
diff --git a/arch/arm/mach-ux500/board-mop500-regulators.c b/arch/arm/mach-ux500/board-mop500-regulators.c
index 2735d03996c..52426a42578 100644
--- a/arch/arm/mach-ux500/board-mop500-regulators.c
+++ b/arch/arm/mach-ux500/board-mop500-regulators.c
@@ -74,6 +74,26 @@ static struct regulator_consumer_supply ab8500_vtvout_consumers[] = {
         REGULATOR_SUPPLY("vddadc", "ab8500-gpadc.0"),
 };
 
+static struct regulator_consumer_supply ab8500_vaud_consumers[] = {
+        /* AB8500 audio-codec main supply */
+        REGULATOR_SUPPLY("vaud", "ab8500-codec.0"),
+};
+
+static struct regulator_consumer_supply ab8500_vamic1_consumers[] = {
+        /* AB8500 audio-codec Mic1 supply */
+        REGULATOR_SUPPLY("vamic1", "ab8500-codec.0"),
+};
+
+static struct regulator_consumer_supply ab8500_vamic2_consumers[] = {
+        /* AB8500 audio-codec Mic2 supply */
+        REGULATOR_SUPPLY("vamic2", "ab8500-codec.0"),
+};
+
+static struct regulator_consumer_supply ab8500_vdmic_consumers[] = {
+        /* AB8500 audio-codec DMic supply */
+        REGULATOR_SUPPLY("vdmic", "ab8500-codec.0"),
+};
+
 static struct regulator_consumer_supply ab8500_vintcore_consumers[] = {
         /* SoC core supply, no device */
         REGULATOR_SUPPLY("v-intcore", NULL),
@@ -323,6 +343,8 @@ struct regulator_init_data ab8500_regulators[AB8500_NUM_REGULATORS] = {
                         .name = "V-AUD",
                         .valid_ops_mask = REGULATOR_CHANGE_STATUS,
                 },
+                .num_consumer_supplies = ARRAY_SIZE(ab8500_vaud_consumers),
+                .consumer_supplies = ab8500_vaud_consumers,
         },
         /* supply for v-anamic1 VAMic1-LDO */
         [AB8500_LDO_ANAMIC1] = {
@@ -330,6 +352,8 @@ struct regulator_init_data ab8500_regulators[AB8500_NUM_REGULATORS] = {
                         .name = "V-AMIC1",
                         .valid_ops_mask = REGULATOR_CHANGE_STATUS,
                 },
+                .num_consumer_supplies = ARRAY_SIZE(ab8500_vamic1_consumers),
+                .consumer_supplies = ab8500_vamic1_consumers,
         },
         /* supply for v-amic2, VAMIC2 LDO, reuse constants for AMIC1 */
         [AB8500_LDO_ANAMIC2] = {
@@ -337,6 +361,8 @@ struct regulator_init_data ab8500_regulators[AB8500_NUM_REGULATORS] = {
                         .name = "V-AMIC2",
                         .valid_ops_mask = REGULATOR_CHANGE_STATUS,
                 },
+                .num_consumer_supplies = ARRAY_SIZE(ab8500_vamic2_consumers),
+                .consumer_supplies = ab8500_vamic2_consumers,
         },
         /* supply for v-dmic, VDMIC LDO */
         [AB8500_LDO_DMIC] = {
@@ -344,6 +370,8 @@ struct regulator_init_data ab8500_regulators[AB8500_NUM_REGULATORS] = {
                         .name = "V-DMIC",
                         .valid_ops_mask = REGULATOR_CHANGE_STATUS,
                 },
+                .num_consumer_supplies = ARRAY_SIZE(ab8500_vdmic_consumers),
+                .consumer_supplies = ab8500_vdmic_consumers,
         },
         /* supply for v-intcore12, VINTCORE12 LDO */
         [AB8500_LDO_INTCORE] = {
diff --git a/arch/arm/mach-ux500/board-mop500-sdi.c b/arch/arm/mach-ux500/board-mop500-sdi.c
index 5dde4d4ebe8..1daead3e583 100644
--- a/arch/arm/mach-ux500/board-mop500-sdi.c
+++ b/arch/arm/mach-ux500/board-mop500-sdi.c
@@ -31,21 +31,13 @@
  * SDI 0 (MicroSD slot)
  */
 
-/* MMCIPOWER bits */
-#define MCI_DATA2DIREN          (1 << 2)
-#define MCI_CMDDIREN            (1 << 3)
-#define MCI_DATA0DIREN          (1 << 4)
-#define MCI_DATA31DIREN         (1 << 5)
-#define MCI_FBCLKEN             (1 << 7)
-
 /* GPIO pins used by the sdi0 level shifter */
 static int sdi0_en = -1;
 static int sdi0_vsel = -1;
 
-static u32 mop500_sdi0_vdd_handler(struct device *dev, unsigned int vdd,
-                                   unsigned char power_mode)
+static int mop500_sdi0_ios_handler(struct device *dev, struct mmc_ios *ios)
 {
-        switch (power_mode) {
+        switch (ios->power_mode) {
         case MMC_POWER_UP:
         case MMC_POWER_ON:
                 /*
@@ -65,8 +57,7 @@ static u32 mop500_sdi0_vdd_handler(struct device *dev, unsigned int vdd,
                 break;
         }
 
-        return MCI_FBCLKEN | MCI_CMDDIREN | MCI_DATA0DIREN |
-               MCI_DATA2DIREN | MCI_DATA31DIREN;
+        return 0;
 }
 
 #ifdef CONFIG_STE_DMA40
@@ -90,13 +81,17 @@ static struct stedma40_chan_cfg mop500_sdi0_dma_cfg_tx = {
 #endif
 
 static struct mmci_platform_data mop500_sdi0_data = {
-        .vdd_handler    = mop500_sdi0_vdd_handler,
+        .ios_handler    = mop500_sdi0_ios_handler,
         .ocr_mask       = MMC_VDD_29_30,
         .f_max          = 50000000,
         .capabilities   = MMC_CAP_4_BIT_DATA |
                                 MMC_CAP_SD_HIGHSPEED |
                                 MMC_CAP_MMC_HIGHSPEED,
         .gpio_wp        = -1,
+        .sigdir         = MCI_ST_FBCLKEN |
+                                MCI_ST_CMDDIREN |
+                                MCI_ST_DATA0DIREN |
+                                MCI_ST_DATA2DIREN,
 #ifdef CONFIG_STE_DMA40
         .dma_filter     = stedma40_filter,
         .dma_rx_param   = &mop500_sdi0_dma_cfg_rx,
diff --git a/arch/arm/mach-ux500/board-mop500-u8500uib.c b/arch/arm/mach-ux500/board-mop500-u8500uib.c
index feb5744d98b..ead91c968ff 100644
--- a/arch/arm/mach-ux500/board-mop500-u8500uib.c
+++ b/arch/arm/mach-ux500/board-mop500-u8500uib.c
@@ -8,7 +8,6 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/i2c.h>
-#include <linux/gpio.h>
 #include <linux/interrupt.h>
 #include <linux/mfd/tc3589x.h>
 #include <linux/input/matrix_keypad.h>
diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c
index 5c00712907d..6d672a556df 100644
--- a/arch/arm/mach-ux500/board-mop500.c
+++ b/arch/arm/mach-ux500/board-mop500.c
@@ -72,7 +72,7 @@ static struct platform_device snowball_led_dev = {
 };
 
 static struct ab8500_gpio_platform_data ab8500_gpio_pdata = {
-        .gpio_base              = MOP500_AB8500_GPIO(0),
+        .gpio_base              = MOP500_AB8500_PIN_GPIO(1),
         .irq_base               = MOP500_AB8500_VIR_GPIO_IRQ_BASE,
         /* config_reg is the initial configuration of ab8500 pins.
          * The pins can be configured as GPIO or alt functions based
diff --git a/arch/arm/mach-ux500/board-mop500.h b/arch/arm/mach-ux500/board-mop500.h
index f926d3db620..7ff6cbffc10 100644
--- a/arch/arm/mach-ux500/board-mop500.h
+++ b/arch/arm/mach-ux500/board-mop500.h
@@ -63,7 +63,7 @@
  * because the AB8500 GPIO pins are enumbered starting from 1, so the value in
  * parens matches the GPIO pin number in the data sheet.
  */
-#define MOP500_AB8500_GPIO(x)           (MOP500_EGPIO_END + (x) - 1)
+#define MOP500_AB8500_PIN_GPIO(x)       (MOP500_EGPIO_END + (x) - 1)
 /*Snowball AB8500 GPIO */
 #define SNOWBALL_VSMPS2_1V8_GPIO        MOP500_AB8500_PIN_GPIO(1)       /* SYSCLKREQ2/GPIO1 */
 #define SNOWBALL_PM_GPIO1_GPIO          MOP500_AB8500_PIN_GPIO(2)       /* SYSCLKREQ3/GPIO2 */
diff --git a/arch/arm/mach-ux500/clock.c b/arch/arm/mach-ux500/clock.c
index 73790753700..ec35f0aa566 100644
--- a/arch/arm/mach-ux500/clock.c
+++ b/arch/arm/mach-ux500/clock.c
@@ -223,6 +223,13 @@ int clk_set_rate(struct clk *clk, unsigned long rate)
 }
 EXPORT_SYMBOL(clk_set_rate);
 
+int clk_set_parent(struct clk *clk, struct clk *parent)
+{
+        /*TODO*/
+        return -ENOSYS;
+}
+EXPORT_SYMBOL(clk_set_parent);
+
 static void clk_prcmu_enable(struct clk *clk)
 {
         void __iomem *cg_set_reg = __io_address(U8500_PRCMU_BASE)
diff --git a/arch/arm/mach-ux500/clock.h b/arch/arm/mach-ux500/clock.h
index 07449070522..d776ada08db 100644
--- a/arch/arm/mach-ux500/clock.h
+++ b/arch/arm/mach-ux500/clock.h
@@ -21,6 +21,7 @@ struct clkops {
         void (*enable) (struct clk *);
         void (*disable) (struct clk *);
         unsigned long (*get_rate) (struct clk *);
+        int (*set_parent)(struct clk *, struct clk *);
 };
 
 /**
diff --git a/arch/arm/mach-ux500/cpu.c b/arch/arm/mach-ux500/cpu.c
index f4185749437..851308bf642 100644
--- a/arch/arm/mach-ux500/cpu.c
+++ b/arch/arm/mach-ux500/cpu.c
@@ -14,7 +14,6 @@
 
 #include <asm/hardware/gic.h>
 #include <asm/mach/map.h>
-#include <asm/localtimer.h>
 
 #include <mach/hardware.h>
 #include <mach/setup.h>
diff --git a/arch/arm/mach-ux500/devices-common.c b/arch/arm/mach-ux500/devices-common.c
index c563e5418d8..898a64517b0 100644
--- a/arch/arm/mach-ux500/devices-common.c
+++ b/arch/arm/mach-ux500/devices-common.c
@@ -26,29 +26,22 @@ dbx500_add_amba_device(const char *name, resource_size_t base,
         struct amba_device *dev;
         int ret;
 
-        dev = kzalloc(sizeof *dev, GFP_KERNEL);
+        dev = amba_device_alloc(name, base, SZ_4K);
         if (!dev)
                 return ERR_PTR(-ENOMEM);
 
-        dev->dev.init_name = name;
-
-        dev->res.start = base;
-        dev->res.end = base + SZ_4K - 1;
-        dev->res.flags = IORESOURCE_MEM;
-
         dev->dma_mask = DMA_BIT_MASK(32);
         dev->dev.coherent_dma_mask = DMA_BIT_MASK(32);
 
         dev->irq[0] = irq;
-        dev->irq[1] = NO_IRQ;
 
         dev->periphid = periphid;
 
         dev->dev.platform_data = pdata;
 
-        ret = amba_device_register(dev, &iomem_resource);
+        ret = amba_device_add(dev, &iomem_resource);
         if (ret) {
-                kfree(dev);
+                amba_device_put(dev);
                 return ERR_PTR(ret);
         }
 
diff --git a/arch/arm/mach-ux500/devices-db8500.c b/arch/arm/mach-ux500/devices-db8500.c
index a7c6cdc9b11..6e66d3777ed 100644
--- a/arch/arm/mach-ux500/devices-db8500.c
+++ b/arch/arm/mach-ux500/devices-db8500.c
@@ -101,6 +101,9 @@ static const dma_addr_t dma40_tx_map[DB8500_DMA_NR_DEV] = {
         [DB8500_DMA_DEV41_SD_MM3_TX] = -1,
         [DB8500_DMA_DEV42_SD_MM4_TX] = -1,
         [DB8500_DMA_DEV43_SD_MM5_TX] = -1,
+        [DB8500_DMA_DEV14_MSP2_TX] = U8500_MSP2_BASE + MSP_TX_RX_REG_OFFSET,
+        [DB8500_DMA_DEV30_MSP1_TX] = U8500_MSP1_BASE + MSP_TX_RX_REG_OFFSET,
+        [DB8500_DMA_DEV31_MSP0_TX_SLIM0_CH0_TX] = U8500_MSP0_BASE + MSP_TX_RX_REG_OFFSET,
 };
 
 /* Mapping between source event lines and physical device address */
@@ -133,6 +136,9 @@ static const dma_addr_t dma40_rx_map[DB8500_DMA_NR_DEV] = {
         [DB8500_DMA_DEV41_SD_MM3_RX] = -1,
         [DB8500_DMA_DEV42_SD_MM4_RX] = -1,
         [DB8500_DMA_DEV43_SD_MM5_RX] = -1,
+        [DB8500_DMA_DEV14_MSP2_RX] = U8500_MSP2_BASE + MSP_TX_RX_REG_OFFSET,
+        [DB8500_DMA_DEV30_MSP3_RX] = U8500_MSP3_BASE + MSP_TX_RX_REG_OFFSET,
+        [DB8500_DMA_DEV31_MSP0_RX_SLIM0_CH0_RX] = U8500_MSP0_BASE + MSP_TX_RX_REG_OFFSET,
 };
 
 /* Reserved event lines for memcpy only */
diff --git a/arch/arm/mach-ux500/include/mach/entry-macro.S b/arch/arm/mach-ux500/include/mach/entry-macro.S
deleted file mode 100644
index e16299e1020..00000000000
--- a/arch/arm/mach-ux500/include/mach/entry-macro.S
+++ /dev/null
@@ -1,18 +0,0 @@
-/*
- * Low-level IRQ helper macros for U8500 platforms
- *
- * Copyright (C) 2009 ST-Ericsson.
- *
- * This file is a copy of ARM Realview platform.
- *      -just satisfied checkpatch script.
- *
- * This file is licensed under  the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-                .macro  disable_fiq
-                .endm
-
-                .macro  arch_ret_to_user, tmp1, tmp2
-                .endm
diff --git a/arch/arm/mach-ux500/include/mach/hardware.h b/arch/arm/mach-ux500/include/mach/hardware.h
index b6ba26a1367..d93d6dbef25 100644
--- a/arch/arm/mach-ux500/include/mach/hardware.h
+++ b/arch/arm/mach-ux500/include/mach/hardware.h
@@ -30,6 +30,8 @@
 #include <mach/db8500-regs.h>
 #include <mach/db5500-regs.h>
 
+#define MSP_TX_RX_REG_OFFSET    0
+
 #ifndef __ASSEMBLY__
 
 #include <mach/id.h>
diff --git a/arch/arm/mach-ux500/include/mach/irqs.h b/arch/arm/mach-ux500/include/mach/irqs.h
index 9db68d264c5..c23a6b5f0c4 100644
--- a/arch/arm/mach-ux500/include/mach/irqs.h
+++ b/arch/arm/mach-ux500/include/mach/irqs.h
@@ -43,7 +43,7 @@
 /* This will be overridden by board-specific irq headers */
 #define IRQ_BOARD_END           IRQ_BOARD_START
 
-#ifdef CONFIG_MACH_U8500
+#ifdef CONFIG_MACH_MOP500
 #include <mach/irqs-board-mop500.h>
 #endif
 
diff --git a/arch/arm/mach-ux500/include/mach/setup.h b/arch/arm/mach-ux500/include/mach/setup.h
index a7d363fdb4c..93d403955ea 100644
--- a/arch/arm/mach-ux500/include/mach/setup.h
+++ b/arch/arm/mach-ux500/include/mach/setup.h
@@ -27,9 +27,6 @@ extern void __init u5500_sdi_init(void);
 
 extern void __init db5500_dma_init(void);
 
-/* We re-use nomadik_timer for this platform */
-extern void nmdk_timer_init(void);
-
 struct amba_device;
 extern void __init amba_add_devices(struct amba_device *devs[], int num);
 
diff --git a/arch/arm/mach-ux500/include/mach/system.h b/arch/arm/mach-ux500/include/mach/system.h
deleted file mode 100644
index 258e5c919c2..00000000000
--- a/arch/arm/mach-ux500/include/mach/system.h
+++ /dev/null
@@ -1,20 +0,0 @@
-/*
- * Copyright (C) 2009 ST-Ericsson.
- *
- * This file is licensed under  the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-#ifndef __ASM_ARCH_SYSTEM_H
-#define __ASM_ARCH_SYSTEM_H
-
-static inline void arch_idle(void)
-{
-        /*
-         * This should do all the clock switching
-         * and wait for interrupt tricks
-         */
-        cpu_do_idle();
-}
-
-#endif
diff --git a/arch/arm/mach-ux500/localtimer.c b/arch/arm/mach-ux500/localtimer.c
deleted file mode 100644
index 5ba113309a0..00000000000
--- a/arch/arm/mach-ux500/localtimer.c
+++ /dev/null
@@ -1,29 +0,0 @@
-/*
- * Copyright (C) 2008-2009 ST-Ericsson
- * Srinidhi Kasagar <srinidhi.kasagar@stericsson.com>
- *
- * This file is heavily based on relaview platform, almost a copy.
- *
- * Copyright (C) 2002 ARM Ltd.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#include <linux/init.h>
-#include <linux/smp.h>
-#include <linux/clockchips.h>
-
-#include <asm/irq.h>
-#include <asm/smp_twd.h>
-#include <asm/localtimer.h>
-
-/*
- * Setup the local clock events for a CPU.
- */
-int __cpuinit local_timer_setup(struct clock_event_device *evt)
-{
-        evt->irq = IRQ_LOCALTIMER;
-        twd_timer_setup(evt);
-        return 0;
-}
diff --git a/arch/arm/mach-ux500/timer.c b/arch/arm/mach-ux500/timer.c
index aea467d04ff..e9d580702fb 100644
--- a/arch/arm/mach-ux500/timer.c
+++ b/arch/arm/mach-ux500/timer.c
@@ -8,28 +8,46 @@
 #include <linux/errno.h>
 #include <linux/clksrc-dbx500-prcmu.h>
 
-#include <asm/localtimer.h>
+#include <asm/smp_twd.h>
 
 #include <plat/mtu.h>
 
 #include <mach/setup.h>
 #include <mach/hardware.h>
+#include <mach/irqs.h>
+
+#ifdef CONFIG_HAVE_ARM_TWD
+static DEFINE_TWD_LOCAL_TIMER(u5500_twd_local_timer,
+                              U5500_TWD_BASE, IRQ_LOCALTIMER);
+static DEFINE_TWD_LOCAL_TIMER(u8500_twd_local_timer,
+                              U8500_TWD_BASE, IRQ_LOCALTIMER);
+
+static void __init ux500_twd_init(void)
+{
+        struct twd_local_timer *twd_local_timer;
+        int err;
+
+        twd_local_timer = cpu_is_u5500() ? &u5500_twd_local_timer :
+                                           &u8500_twd_local_timer;
+
+        err = twd_local_timer_register(twd_local_timer);
+        if (err)
+                pr_err("twd_local_timer_register failed %d\n", err);
+}
+#else
+#define ux500_twd_init()        do { } while(0)
+#endif
 
 static void __init ux500_timer_init(void)
 {
+        void __iomem *mtu_timer_base;
         void __iomem *prcmu_timer_base;
 
         if (cpu_is_u5500()) {
-#ifdef CONFIG_LOCAL_TIMERS
-                twd_base = __io_address(U5500_TWD_BASE);
-#endif
-                mtu_base = __io_address(U5500_MTU0_BASE);
+                mtu_timer_base = __io_address(U5500_MTU0_BASE);
                 prcmu_timer_base = __io_address(U5500_PRCMU_TIMER_3_BASE);
         } else if (cpu_is_u8500()) {
-#ifdef CONFIG_LOCAL_TIMERS
-                twd_base = __io_address(U8500_TWD_BASE);
-#endif
-                mtu_base = __io_address(U8500_MTU0_BASE);
+                mtu_timer_base = __io_address(U8500_MTU0_BASE);
                 prcmu_timer_base = __io_address(U8500_PRCMU_TIMER_4_BASE);
         } else {
                 ux500_unknown_soc();
@@ -52,8 +70,9 @@ static void __init ux500_timer_init(void)
          *
          */
 
-        nmdk_timer_init();
+        nmdk_timer_init(mtu_timer_base);
         clksrc_dbx500_prcmu_init(prcmu_timer_base);
+        ux500_twd_init();
 }
 
 static void ux500_timer_reset(void)
diff --git a/arch/arm/mach-versatile/core.c b/arch/arm/mach-versatile/core.c
index 008ce22b9a0..0968772aedb 100644
--- a/arch/arm/mach-versatile/core.c
+++ b/arch/arm/mach-versatile/core.c
@@ -585,58 +585,58 @@ static struct pl022_ssp_controller ssp0_plat_data = {
         .num_chipselect = 1,
 };
 
-#define AACI_IRQ        { IRQ_AACI, NO_IRQ }
+#define AACI_IRQ        { IRQ_AACI }
 #define MMCI0_IRQ       { IRQ_MMCI0A,IRQ_SIC_MMCI0B }
-#define KMI0_IRQ        { IRQ_SIC_KMI0, NO_IRQ }
-#define KMI1_IRQ        { IRQ_SIC_KMI1, NO_IRQ }
+#define KMI0_IRQ        { IRQ_SIC_KMI0 }
+#define KMI1_IRQ        { IRQ_SIC_KMI1 }
 
 /*
  * These devices are connected directly to the multi-layer AHB switch
  */
-#define SMC_IRQ         { NO_IRQ, NO_IRQ }
-#define MPMC_IRQ        { NO_IRQ, NO_IRQ }
-#define CLCD_IRQ        { IRQ_CLCDINT, NO_IRQ }
-#define DMAC_IRQ        { IRQ_DMAINT, NO_IRQ }
+#define SMC_IRQ         { }
+#define MPMC_IRQ        { }
+#define CLCD_IRQ        { IRQ_CLCDINT }
+#define DMAC_IRQ        { IRQ_DMAINT }
 
 /*
  * These devices are connected via the core APB bridge
  */
-#define SCTL_IRQ        { NO_IRQ, NO_IRQ }
-#define WATCHDOG_IRQ    { IRQ_WDOGINT, NO_IRQ }
-#define GPIO0_IRQ       { IRQ_GPIOINT0, NO_IRQ }
-#define GPIO1_IRQ       { IRQ_GPIOINT1, NO_IRQ }
-#define RTC_IRQ         { IRQ_RTCINT, NO_IRQ }
+#define SCTL_IRQ        { }
+#define WATCHDOG_IRQ    { IRQ_WDOGINT }
+#define GPIO0_IRQ       { IRQ_GPIOINT0 }
+#define GPIO1_IRQ       { IRQ_GPIOINT1 }
+#define RTC_IRQ         { IRQ_RTCINT }
 
 /*
  * These devices are connected via the DMA APB bridge
  */
-#define SCI_IRQ         { IRQ_SCIINT, NO_IRQ }
-#define UART0_IRQ       { IRQ_UARTINT0, NO_IRQ }
-#define UART1_IRQ       { IRQ_UARTINT1, NO_IRQ }
-#define UART2_IRQ       { IRQ_UARTINT2, NO_IRQ }
-#define SSP_IRQ         { IRQ_SSPINT, NO_IRQ }
+#define SCI_IRQ         { IRQ_SCIINT }
+#define UART0_IRQ       { IRQ_UARTINT0 }
+#define UART1_IRQ       { IRQ_UARTINT1 }
+#define UART2_IRQ       { IRQ_UARTINT2 }
+#define SSP_IRQ         { IRQ_SSPINT }
 
 /* FPGA Primecells */
-AMBA_DEVICE(aaci,  "fpga:04", AACI,     NULL);
-AMBA_DEVICE(mmc0,  "fpga:05", MMCI0,    &mmc0_plat_data);
-AMBA_DEVICE(kmi0,  "fpga:06", KMI0,     NULL);
-AMBA_DEVICE(kmi1,  "fpga:07", KMI1,     NULL);
+APB_DEVICE(aaci,  "fpga:04", AACI,     NULL);
+APB_DEVICE(mmc0,  "fpga:05", MMCI0,    &mmc0_plat_data);
+APB_DEVICE(kmi0,  "fpga:06", KMI0,     NULL);
+APB_DEVICE(kmi1,  "fpga:07", KMI1,     NULL);
 
 /* DevChip Primecells */
-AMBA_DEVICE(smc,   "dev:00",  SMC,      NULL);
-AMBA_DEVICE(mpmc,  "dev:10",  MPMC,     NULL);
-AMBA_DEVICE(clcd,  "dev:20",  CLCD,     &clcd_plat_data);
-AMBA_DEVICE(dmac,  "dev:30",  DMAC,     NULL);
-AMBA_DEVICE(sctl,  "dev:e0",  SCTL,     NULL);
-AMBA_DEVICE(wdog,  "dev:e1",  WATCHDOG, NULL);
-AMBA_DEVICE(gpio0, "dev:e4",  GPIO0,    &gpio0_plat_data);
-AMBA_DEVICE(gpio1, "dev:e5",  GPIO1,    &gpio1_plat_data);
-AMBA_DEVICE(rtc,   "dev:e8",  RTC,      NULL);
-AMBA_DEVICE(sci0,  "dev:f0",  SCI,      NULL);
-AMBA_DEVICE(uart0, "dev:f1",  UART0,    NULL);
-AMBA_DEVICE(uart1, "dev:f2",  UART1,    NULL);
-AMBA_DEVICE(uart2, "dev:f3",  UART2,    NULL);
-AMBA_DEVICE(ssp0,  "dev:f4",  SSP,      &ssp0_plat_data);
+AHB_DEVICE(smc,   "dev:00",  SMC,      NULL);
+AHB_DEVICE(mpmc,  "dev:10",  MPMC,     NULL);
+AHB_DEVICE(clcd,  "dev:20",  CLCD,     &clcd_plat_data);
+AHB_DEVICE(dmac,  "dev:30",  DMAC,     NULL);
+APB_DEVICE(sctl,  "dev:e0",  SCTL,     NULL);
+APB_DEVICE(wdog,  "dev:e1",  WATCHDOG, NULL);
+APB_DEVICE(gpio0, "dev:e4",  GPIO0,    &gpio0_plat_data);
+APB_DEVICE(gpio1, "dev:e5",  GPIO1,    &gpio1_plat_data);
+APB_DEVICE(rtc,   "dev:e8",  RTC,      NULL);
+APB_DEVICE(sci0,  "dev:f0",  SCI,      NULL);
+APB_DEVICE(uart0, "dev:f1",  UART0,    NULL);
+APB_DEVICE(uart1, "dev:f2",  UART1,    NULL);
+APB_DEVICE(uart2, "dev:f3",  UART2,    NULL);
+APB_DEVICE(ssp0,  "dev:f4",  SSP,      &ssp0_plat_data);
 
 static struct amba_device *amba_devs[] __initdata = {
         &dmac_device,
diff --git a/arch/arm/mach-versatile/core.h b/arch/arm/mach-versatile/core.h
index 2ef2f555f31..683e60776a8 100644
--- a/arch/arm/mach-versatile/core.h
+++ b/arch/arm/mach-versatile/core.h
@@ -36,20 +36,10 @@ extern unsigned int mmc_status(struct device *dev);
 extern struct of_dev_auxdata versatile_auxdata_lookup[];
 #endif
 
-#define AMBA_DEVICE(name,busid,base,plat)                       \
-static struct amba_device name##_device = {                     \
-        .dev            = {                                     \
-                .coherent_dma_mask = ~0,                        \
-                .init_name = busid,                             \
-                .platform_data = plat,                          \
-        },                                                      \
-        .res            = {                                     \
-                .start  = VERSATILE_##base##_BASE,              \
-                .end    = (VERSATILE_##base##_BASE) + SZ_4K - 1,\
-                .flags  = IORESOURCE_MEM,                       \
-        },                                                      \
-        .dma_mask       = ~0,                                   \
-        .irq            = base##_IRQ,                           \
-}
+#define APB_DEVICE(name, busid, base, plat)     \
+static AMBA_APB_DEVICE(name, busid, 0, VERSATILE_##base##_BASE, base##_IRQ, plat)
+
+#define AHB_DEVICE(name, busid, base, plat)     \
+static AMBA_AHB_DEVICE(name, busid, 0, VERSATILE_##base##_BASE, base##_IRQ, plat)
 
 #endif
diff --git a/arch/arm/mach-versatile/include/mach/entry-macro.S b/arch/arm/mach-versatile/include/mach/entry-macro.S
deleted file mode 100644
index b6f0dbf122e..00000000000
--- a/arch/arm/mach-versatile/include/mach/entry-macro.S
+++ /dev/null
@@ -1,15 +0,0 @@
-/*
- * arch/arm/mach-versatile/include/mach/entry-macro.S
- *
- * Low-level IRQ helper macros for Versatile platforms
- *
- * This file is licensed under  the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-                .macro  disable_fiq
-                .endm
-
-                .macro  arch_ret_to_user, tmp1, tmp2
-                .endm
diff --git a/arch/arm/mach-versatile/include/mach/system.h b/arch/arm/mach-versatile/include/mach/system.h
deleted file mode 100644
index f3fa347895f..00000000000
--- a/arch/arm/mach-versatile/include/mach/system.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/*
- *  arch/arm/mach-versatile/include/mach/system.h
- *
- *  Copyright (C) 2003 ARM Limited
- *  Copyright (C) 2000 Deep Blue Solutions Ltd
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#ifndef __ASM_ARCH_SYSTEM_H
-#define __ASM_ARCH_SYSTEM_H
-
-static inline void arch_idle(void)
-{
-        /*
-         * This should do all the clock switching
-         * and wait for interrupt tricks
-         */
-        cpu_do_idle();
-}
-
-#endif
diff --git a/arch/arm/mach-versatile/pci.c b/arch/arm/mach-versatile/pci.c
index 90069bce23b..51733b022d0 100644
--- a/arch/arm/mach-versatile/pci.c
+++ b/arch/arm/mach-versatile/pci.c
@@ -219,9 +219,9 @@ static int __init pci_versatile_setup_resources(struct list_head *resources)
          * the mem resource for this bus
          * the prefetch mem resource for this bus
          */
-        pci_add_resource(resources, &io_mem);
-        pci_add_resource(resources, &non_mem);
-        pci_add_resource(resources, &pre_mem);
+        pci_add_resource_offset(resources, &io_mem, sys->io_offset);
+        pci_add_resource_offset(resources, &non_mem, sys->mem_offset);
+        pci_add_resource_offset(resources, &pre_mem, sys->mem_offset);
 
         goto out;
 
diff --git a/arch/arm/mach-versatile/versatile_pb.c b/arch/arm/mach-versatile/versatile_pb.c
index 9581c197500..19738331bd3 100644
--- a/arch/arm/mach-versatile/versatile_pb.c
+++ b/arch/arm/mach-versatile/versatile_pb.c
@@ -58,28 +58,28 @@ static struct pl061_platform_data gpio3_plat_data = {
         .irq_base       = IRQ_GPIO3_START,
 };
 
-#define UART3_IRQ       { IRQ_SIC_UART3, NO_IRQ }
-#define SCI1_IRQ        { IRQ_SIC_SCI3, NO_IRQ }
+#define UART3_IRQ       { IRQ_SIC_UART3 }
+#define SCI1_IRQ        { IRQ_SIC_SCI3 }
 #define MMCI1_IRQ       { IRQ_MMCI1A, IRQ_SIC_MMCI1B }
 
 /*
  * These devices are connected via the core APB bridge
  */
-#define GPIO2_IRQ       { IRQ_GPIOINT2, NO_IRQ }
-#define GPIO3_IRQ       { IRQ_GPIOINT3, NO_IRQ }
+#define GPIO2_IRQ       { IRQ_GPIOINT2 }
+#define GPIO3_IRQ       { IRQ_GPIOINT3 }
 
 /*
  * These devices are connected via the DMA APB bridge
  */
 
 /* FPGA Primecells */
-AMBA_DEVICE(uart3, "fpga:09", UART3,    NULL);
-AMBA_DEVICE(sci1,  "fpga:0a", SCI1,     NULL);
-AMBA_DEVICE(mmc1,  "fpga:0b", MMCI1,    &mmc1_plat_data);
+APB_DEVICE(uart3, "fpga:09", UART3,    NULL);
+APB_DEVICE(sci1,  "fpga:0a", SCI1,     NULL);
+APB_DEVICE(mmc1,  "fpga:0b", MMCI1,    &mmc1_plat_data);
 
 /* DevChip Primecells */
-AMBA_DEVICE(gpio2, "dev:e6",  GPIO2,    &gpio2_plat_data);
-AMBA_DEVICE(gpio3, "dev:e7",  GPIO3,    &gpio3_plat_data);
+APB_DEVICE(gpio2, "dev:e6",  GPIO2,    &gpio2_plat_data);
+APB_DEVICE(gpio3, "dev:e7",  GPIO3,    &gpio3_plat_data);
 
 static struct amba_device *amba_devs[] __initdata = {
         &uart3_device,
diff --git a/arch/arm/mach-vexpress/Kconfig b/arch/arm/mach-vexpress/Kconfig
index 88c3ba151e8..cf8730d35e7 100644
--- a/arch/arm/mach-vexpress/Kconfig
+++ b/arch/arm/mach-vexpress/Kconfig
@@ -1,14 +1,55 @@
 menu "Versatile Express platform type"
         depends on ARCH_VEXPRESS
 
+config ARCH_VEXPRESS_CORTEX_A5_A9_ERRATA
+        bool
+        select ARM_ERRATA_720789
+        select ARM_ERRATA_751472
+        select PL310_ERRATA_753970 if CACHE_PL310
+        help
+          Provides common dependencies for Versatile Express platforms
+          based on Cortex-A5 and Cortex-A9 processors. In order to
+          build a working kernel, you must also enable relevant core
+          tile support or Flattened Device Tree based support options.
+
 config ARCH_VEXPRESS_CA9X4
         bool "Versatile Express Cortex-A9x4 tile"
+        select ARCH_VEXPRESS_CORTEX_A5_A9_ERRATA
+        select ARM_GIC
         select CPU_V7
+        select HAVE_SMP
+        select MIGHT_HAVE_CACHE_L2X0
+
+config ARCH_VEXPRESS_DT
+        bool "Device Tree support for Versatile Express platforms"
+        select ARCH_VEXPRESS_CORTEX_A5_A9_ERRATA
         select ARM_GIC
-        select ARM_ERRATA_720789
-        select ARM_ERRATA_751472
-        select PL310_ERRATA_753970
+        select ARM_PATCH_PHYS_VIRT
+        select AUTO_ZRELADDR
+        select CPU_V7
         select HAVE_SMP
         select MIGHT_HAVE_CACHE_L2X0
+        select USE_OF
+        help
+          New Versatile Express platforms require Flattened Device Tree to
+          be passed to the kernel.
+
+          This option enables support for systems using Cortex processor based
+          ARM core and logic (FPGA) tiles on the Versatile Express motherboard,
+          for example:
+
+          - CoreTile Express A5x2 (V2P-CA5s)
+          - CoreTile Express A9x4 (V2P-CA9)
+          - CoreTile Express A15x2 (V2P-CA15)
+          - LogicTile Express 13MG (V2F-2XV6) with A5, A7, A9 or A15 SMMs
+            (Soft Macrocell Models)
+          - Versatile Express RTSMs (Models)
+
+          You must boot using a Flattened Device Tree in order to use these
+          platforms. The traditional (ATAGs) boot method is not usable on
+          these boards with this option.
+
+          If your bootloader supports Flattened Device Tree based booting,
+          say Y here.
 
 endmenu
diff --git a/arch/arm/mach-vexpress/Makefile.boot b/arch/arm/mach-vexpress/Makefile.boot
index 8630b3d10a4..909f85ebf5f 100644
--- a/arch/arm/mach-vexpress/Makefile.boot
+++ b/arch/arm/mach-vexpress/Makefile.boot
@@ -1,3 +1,9 @@
+# Those numbers are used only by the non-DT V2P-CA9 platform
+# The DT-enabled ones require CONFIG_AUTO_ZRELADDR=y
    zreladdr-y   += 0x60008000
 params_phys-y   := 0x60000100
 initrd_phys-y   := 0x60800000
+
+dtb-$(CONFIG_ARCH_VEXPRESS_DT)  += vexpress-v2p-ca5s.dtb \
+                                   vexpress-v2p-ca9.dtb \
+                                   vexpress-v2p-ca15-tc1.dtb
diff --git a/arch/arm/mach-vexpress/core.h b/arch/arm/mach-vexpress/core.h
index f4397159c17..a3a4980770b 100644
--- a/arch/arm/mach-vexpress/core.h
+++ b/arch/arm/mach-vexpress/core.h
@@ -1,19 +1,7 @@
-#define __MMIO_P2V(x)   (((x) & 0xfffff) | (((x) & 0x0f000000) >> 4) | 0xf8000000)
-#define MMIO_P2V(x)     ((void __iomem *)__MMIO_P2V(x))
+/* 2MB large area for motherboard's peripherals static mapping */
+#define V2M_PERIPH 0xf8000000
 
-#define AMBA_DEVICE(name,busid,base,plat)       \
-struct amba_device name##_device = {            \
-        .dev            = {                     \
-                .coherent_dma_mask = ~0UL,      \
-                .init_name = busid,             \
-                .platform_data = plat,          \
-        },                                      \
-        .res            = {                     \
-                .start  = base,                 \
-                .end    = base + SZ_4K - 1,     \
-                .flags  = IORESOURCE_MEM,       \
-        },                                      \
-        .dma_mask       = ~0UL,                 \
-        .irq            = IRQ_##base,           \
-        /* .dma         = DMA_##base,*/         \
-}
+/* Tile's peripherals static mappings should start here */
+#define V2T_PERIPH 0xf8200000
+
+void vexpress_dt_smp_map_io(void);
diff --git a/arch/arm/mach-vexpress/ct-ca9x4.c b/arch/arm/mach-vexpress/ct-ca9x4.c
index b1e87c184e5..c65cc3b462a 100644
--- a/arch/arm/mach-vexpress/ct-ca9x4.c
+++ b/arch/arm/mach-vexpress/ct-ca9x4.c
@@ -30,57 +30,40 @@
 
 #include <plat/clcd.h>
 
-#define V2M_PA_CS7      0x10000000
-
 static struct map_desc ct_ca9x4_io_desc[] __initdata = {
         {
-                .virtual        = __MMIO_P2V(CT_CA9X4_MPIC),
-                .pfn            = __phys_to_pfn(CT_CA9X4_MPIC),
-                .length         = SZ_16K,
-                .type           = MT_DEVICE,
-        }, {
-                .virtual        = __MMIO_P2V(CT_CA9X4_SP804_TIMER),
-                .pfn            = __phys_to_pfn(CT_CA9X4_SP804_TIMER),
-                .length         = SZ_4K,
-                .type           = MT_DEVICE,
-        }, {
-                .virtual        = __MMIO_P2V(CT_CA9X4_L2CC),
-                .pfn            = __phys_to_pfn(CT_CA9X4_L2CC),
-                .length         = SZ_4K,
-                .type           = MT_DEVICE,
+                .virtual        = V2T_PERIPH,
+                .pfn            = __phys_to_pfn(CT_CA9X4_MPIC),
+                .length         = SZ_8K,
+                .type           = MT_DEVICE,
         },
 };
 
 static void __init ct_ca9x4_map_io(void)
 {
-#ifdef CONFIG_LOCAL_TIMERS
-        twd_base = MMIO_P2V(A9_MPCORE_TWD);
-#endif
         iotable_init(ct_ca9x4_io_desc, ARRAY_SIZE(ct_ca9x4_io_desc));
 }
 
-static void __init ct_ca9x4_init_irq(void)
+#ifdef CONFIG_HAVE_ARM_TWD
+static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, A9_MPCORE_TWD, IRQ_LOCALTIMER);
+
+static void __init ca9x4_twd_init(void)
 {
-        gic_init(0, 29, MMIO_P2V(A9_MPCORE_GIC_DIST),
-                 MMIO_P2V(A9_MPCORE_GIC_CPU));
+        int err = twd_local_timer_register(&twd_local_timer);
+        if (err)
+                pr_err("twd_local_timer_register failed %d\n", err);
 }
+#else
+#define ca9x4_twd_init()        do {} while(0)
+#endif
 
-#if 0
-static void __init ct_ca9x4_timer_init(void)
+static void __init ct_ca9x4_init_irq(void)
 {
-        writel(0, MMIO_P2V(CT_CA9X4_TIMER0) + TIMER_CTRL);
-        writel(0, MMIO_P2V(CT_CA9X4_TIMER1) + TIMER_CTRL);
-
-        sp804_clocksource_init(MMIO_P2V(CT_CA9X4_TIMER1), "ct-timer1");
-        sp804_clockevents_init(MMIO_P2V(CT_CA9X4_TIMER0), IRQ_CT_CA9X4_TIMER0,
-                "ct-timer0");
+        gic_init(0, 29, ioremap(A9_MPCORE_GIC_DIST, SZ_4K),
+                 ioremap(A9_MPCORE_GIC_CPU, SZ_256));
+        ca9x4_twd_init();
 }
 
-static struct sys_timer ct_ca9x4_timer = {
-        .init   = ct_ca9x4_timer_init,
-};
-#endif
-
 static void ct_ca9x4_clcd_enable(struct clcd_fb *fb)
 {
         v2m_cfg_write(SYS_CFG_MUXFPGA | SYS_CFG_SITE_DB1, 0);
@@ -109,10 +92,10 @@ static struct clcd_board ct_ca9x4_clcd_data = {
         .remove         = versatile_clcd_remove_dma,
 };
 
-static AMBA_DEVICE(clcd, "ct:clcd", CT_CA9X4_CLCDC, &ct_ca9x4_clcd_data);
-static AMBA_DEVICE(dmc, "ct:dmc", CT_CA9X4_DMC, NULL);
-static AMBA_DEVICE(smc, "ct:smc", CT_CA9X4_SMC, NULL);
-static AMBA_DEVICE(gpio, "ct:gpio", CT_CA9X4_GPIO, NULL);
+static AMBA_AHB_DEVICE(clcd, "ct:clcd", 0, CT_CA9X4_CLCDC, IRQ_CT_CA9X4_CLCDC, &ct_ca9x4_clcd_data);
+static AMBA_APB_DEVICE(dmc, "ct:dmc", 0, CT_CA9X4_DMC, IRQ_CT_CA9X4_DMC, NULL);
+static AMBA_APB_DEVICE(smc, "ct:smc", 0, CT_CA9X4_SMC, IRQ_CT_CA9X4_SMC, NULL);
+static AMBA_APB_DEVICE(gpio, "ct:gpio", 0, CT_CA9X4_GPIO, IRQ_CT_CA9X4_GPIO, NULL);
 
 static struct amba_device *ct_ca9x4_amba_devs[] __initdata = {
         &clcd_device,
@@ -201,7 +184,7 @@ static void __init ct_ca9x4_init(void)
         int i;
 
 #ifdef CONFIG_CACHE_L2X0
-        void __iomem *l2x0_base = MMIO_P2V(CT_CA9X4_L2CC);
+        void __iomem *l2x0_base = ioremap(CT_CA9X4_L2CC, SZ_4K);
 
         /* set RAM latencies to 1 cycle for this core tile. */
         writel(0, l2x0_base + L2X0_TAG_LATENCY_CTRL);
@@ -217,9 +200,17 @@ static void __init ct_ca9x4_init(void)
 }
 
 #ifdef CONFIG_SMP
+static void *ct_ca9x4_scu_base __initdata;
+
 static void __init ct_ca9x4_init_cpu_map(void)
 {
-        int i, ncores = scu_get_core_count(MMIO_P2V(A9_MPCORE_SCU));
+        int i, ncores;
+
+        ct_ca9x4_scu_base = ioremap(A9_MPCORE_SCU, SZ_128);
+        if (WARN_ON(!ct_ca9x4_scu_base))
+                return;
+
+        ncores = scu_get_core_count(ct_ca9x4_scu_base);
 
         if (ncores > nr_cpu_ids) {
                 pr_warn("SMP: %u cores greater than maximum (%u), clipping\n",
@@ -235,7 +226,7 @@ static void __init ct_ca9x4_init_cpu_map(void)
 
 static void __init ct_ca9x4_smp_enable(unsigned int max_cpus)
 {
-        scu_enable(MMIO_P2V(A9_MPCORE_SCU));
+        scu_enable(ct_ca9x4_scu_base);
 }
 #endif
 
diff --git a/arch/arm/mach-vexpress/include/mach/ct-ca9x4.h b/arch/arm/mach-vexpress/include/mach/ct-ca9x4.h
index a34d3d4faae..84acf8439d4 100644
--- a/arch/arm/mach-vexpress/include/mach/ct-ca9x4.h
+++ b/arch/arm/mach-vexpress/include/mach/ct-ca9x4.h
@@ -22,9 +22,6 @@
 #define CT_CA9X4_SYSWDT         (0x1e007000)
 #define CT_CA9X4_L2CC           (0x1e00a000)
 
-#define CT_CA9X4_TIMER0         (CT_CA9X4_SP804_TIMER + 0x000)
-#define CT_CA9X4_TIMER1         (CT_CA9X4_SP804_TIMER + 0x020)
-
 #define A9_MPCORE_SCU           (CT_CA9X4_MPIC + 0x0000)
 #define A9_MPCORE_GIC_CPU       (CT_CA9X4_MPIC + 0x0100)
 #define A9_MPCORE_GIT           (CT_CA9X4_MPIC + 0x0200)
@@ -35,7 +32,7 @@
  * Interrupts.  Those in {} are for AMBA devices
  */
 #define IRQ_CT_CA9X4_CLCDC      { 76 }
-#define IRQ_CT_CA9X4_DMC        { -1 }
+#define IRQ_CT_CA9X4_DMC        { 0 }
 #define IRQ_CT_CA9X4_SMC        { 77, 78 }
 #define IRQ_CT_CA9X4_TIMER0     80
 #define IRQ_CT_CA9X4_TIMER1     81
diff --git a/arch/arm/mach-vexpress/include/mach/debug-macro.S b/arch/arm/mach-vexpress/include/mach/debug-macro.S
index fd9e6c7ea49..fa8224794e0 100644
--- a/arch/arm/mach-vexpress/include/mach/debug-macro.S
+++ b/arch/arm/mach-vexpress/include/mach/debug-macro.S
@@ -10,12 +10,34 @@
  * published by the Free Software Foundation.
  */
 
-#define DEBUG_LL_UART_OFFSET    0x00009000
+#define DEBUG_LL_PHYS_BASE              0x10000000
+#define DEBUG_LL_UART_OFFSET            0x00009000
+
+#define DEBUG_LL_PHYS_BASE_RS1          0x1c000000
+#define DEBUG_LL_UART_OFFSET_RS1        0x00090000
+
+#define DEBUG_LL_VIRT_BASE              0xf8000000
 
                 .macro  addruart,rp,rv,tmp
-                mov     \rp, #DEBUG_LL_UART_OFFSET
-                orr     \rv, \rp, #0xf8000000   @ virtual base
-                orr     \rp, \rp, #0x10000000   @ physical base
+
+                @ Make an educated guess regarding the memory map:
+                @ - the original A9 core tile, which has MPCore peripherals
+                @   located at 0x1e000000, should use UART at 0x10009000
+                @ - all other (RS1 complaint) tiles use UART mapped
+                @   at 0x1c090000
+                mrc     p15, 4, \tmp, c15, c0, 0
+                cmp     \tmp, #0x1e000000
+
+                @ Original memory map
+                moveq   \rp, #DEBUG_LL_UART_OFFSET
+                orreq   \rv, \rp, #DEBUG_LL_VIRT_BASE
+                orreq   \rp, \rp, #DEBUG_LL_PHYS_BASE
+
+                @ RS1 memory map
+                movne   \rp, #DEBUG_LL_UART_OFFSET_RS1
+                orrne   \rv, \rp, #DEBUG_LL_VIRT_BASE
+                orrne   \rp, \rp, #DEBUG_LL_PHYS_BASE_RS1
+
                 .endm
 
 #include <asm/hardware/debug-pl01x.S>
diff --git a/arch/arm/mach-vexpress/include/mach/entry-macro.S b/arch/arm/mach-vexpress/include/mach/entry-macro.S
deleted file mode 100644
index a14f9e62ca9..00000000000
--- a/arch/arm/mach-vexpress/include/mach/entry-macro.S
+++ /dev/null
@@ -1,5 +0,0 @@
-        .macro  disable_fiq
-        .endm
-
-        .macro  arch_ret_to_user, tmp1, tmp2
-        .endm
diff --git a/arch/arm/mach-vexpress/include/mach/irqs.h b/arch/arm/mach-vexpress/include/mach/irqs.h
index 7054cbfc9de..4b10ee7657a 100644
--- a/arch/arm/mach-vexpress/include/mach/irqs.h
+++ b/arch/arm/mach-vexpress/include/mach/irqs.h
@@ -1,4 +1,4 @@
 #define IRQ_LOCALTIMER          29
 #define IRQ_LOCALWDOG           30
 
-#define NR_IRQS 128
+#define NR_IRQS 256
diff --git a/arch/arm/mach-vexpress/include/mach/motherboard.h b/arch/arm/mach-vexpress/include/mach/motherboard.h
index 0a3a3751840..31a92890893 100644
--- a/arch/arm/mach-vexpress/include/mach/motherboard.h
+++ b/arch/arm/mach-vexpress/include/mach/motherboard.h
@@ -39,33 +39,30 @@
 #define V2M_CF                  (V2M_PA_CS7 + 0x0001a000)
 #define V2M_CLCD                (V2M_PA_CS7 + 0x0001f000)
 
-#define V2M_SYS_ID              (V2M_SYSREGS + 0x000)
-#define V2M_SYS_SW              (V2M_SYSREGS + 0x004)
-#define V2M_SYS_LED             (V2M_SYSREGS + 0x008)
-#define V2M_SYS_100HZ           (V2M_SYSREGS + 0x024)
-#define V2M_SYS_FLAGS           (V2M_SYSREGS + 0x030)
-#define V2M_SYS_FLAGSSET        (V2M_SYSREGS + 0x030)
-#define V2M_SYS_FLAGSCLR        (V2M_SYSREGS + 0x034)
-#define V2M_SYS_NVFLAGS         (V2M_SYSREGS + 0x038)
-#define V2M_SYS_NVFLAGSSET      (V2M_SYSREGS + 0x038)
-#define V2M_SYS_NVFLAGSCLR      (V2M_SYSREGS + 0x03c)
-#define V2M_SYS_MCI             (V2M_SYSREGS + 0x048)
-#define V2M_SYS_FLASH           (V2M_SYSREGS + 0x03c)
-#define V2M_SYS_CFGSW           (V2M_SYSREGS + 0x058)
-#define V2M_SYS_24MHZ           (V2M_SYSREGS + 0x05c)
-#define V2M_SYS_MISC            (V2M_SYSREGS + 0x060)
-#define V2M_SYS_DMA             (V2M_SYSREGS + 0x064)
-#define V2M_SYS_PROCID0         (V2M_SYSREGS + 0x084)
-#define V2M_SYS_PROCID1         (V2M_SYSREGS + 0x088)
-#define V2M_SYS_CFGDATA         (V2M_SYSREGS + 0x0a0)
-#define V2M_SYS_CFGCTRL         (V2M_SYSREGS + 0x0a4)
-#define V2M_SYS_CFGSTAT         (V2M_SYSREGS + 0x0a8)
-
-#define V2M_TIMER0              (V2M_TIMER01 + 0x000)
-#define V2M_TIMER1              (V2M_TIMER01 + 0x020)
-
-#define V2M_TIMER2              (V2M_TIMER23 + 0x000)
-#define V2M_TIMER3              (V2M_TIMER23 + 0x020)
+/*
+ * Offsets from SYSREGS base
+ */
+#define V2M_SYS_ID              0x000
+#define V2M_SYS_SW              0x004
+#define V2M_SYS_LED             0x008
+#define V2M_SYS_100HZ           0x024
+#define V2M_SYS_FLAGS           0x030
+#define V2M_SYS_FLAGSSET        0x030
+#define V2M_SYS_FLAGSCLR        0x034
+#define V2M_SYS_NVFLAGS         0x038
+#define V2M_SYS_NVFLAGSSET      0x038
+#define V2M_SYS_NVFLAGSCLR      0x03c
+#define V2M_SYS_MCI             0x048
+#define V2M_SYS_FLASH           0x03c
+#define V2M_SYS_CFGSW           0x058
+#define V2M_SYS_24MHZ           0x05c
+#define V2M_SYS_MISC            0x060
+#define V2M_SYS_DMA             0x064
+#define V2M_SYS_PROCID0         0x084
+#define V2M_SYS_PROCID1         0x088
+#define V2M_SYS_CFGDATA         0x0a0
+#define V2M_SYS_CFGCTRL         0x0a4
+#define V2M_SYS_CFGSTAT         0x0a8
 
 
 /*
@@ -117,6 +114,13 @@
 
 int v2m_cfg_write(u32 devfn, u32 data);
 int v2m_cfg_read(u32 devfn, u32 *data);
+void v2m_flags_set(u32 data);
+
+/*
+ * Miscellaneous
+ */
+#define SYS_MISC_MASTERSITE     (1 << 14)
+#define SYS_PROCIDx_HBI_MASK    0xfff
 
 /*
  * Core tile IDs
diff --git a/arch/arm/mach-vexpress/include/mach/system.h b/arch/arm/mach-vexpress/include/mach/system.h
deleted file mode 100644
index f653a8e265b..00000000000
--- a/arch/arm/mach-vexpress/include/mach/system.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/*
- *  arch/arm/mach-vexpress/include/mach/system.h
- *
- *  Copyright (C) 2003 ARM Limited
- *  Copyright (C) 2000 Deep Blue Solutions Ltd
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#ifndef __ASM_ARCH_SYSTEM_H
-#define __ASM_ARCH_SYSTEM_H
-
-static inline void arch_idle(void)
-{
-        /*
-         * This should do all the clock switching
-         * and wait for interrupt tricks
-         */
-        cpu_do_idle();
-}
-
-#endif
diff --git a/arch/arm/mach-vexpress/include/mach/uncompress.h b/arch/arm/mach-vexpress/include/mach/uncompress.h
index 7972c5748d0..7dab5596b86 100644
--- a/arch/arm/mach-vexpress/include/mach/uncompress.h
+++ b/arch/arm/mach-vexpress/include/mach/uncompress.h
@@ -22,7 +22,27 @@
 #define AMBA_UART_CR(base)      (*(volatile unsigned char *)((base) + 0x30))
 #define AMBA_UART_FR(base)      (*(volatile unsigned char *)((base) + 0x18))
 
-#define get_uart_base() (0x10000000 + 0x00009000)
+#define UART_BASE       0x10009000
+#define UART_BASE_RS1   0x1c090000
+
+static unsigned long get_uart_base(void)
+{
+        unsigned long mpcore_periph;
+
+        /*
+         * Make an educated guess regarding the memory map:
+         * - the original A9 core tile, which has MPCore peripherals
+         *   located at 0x1e000000, should use UART at 0x10009000
+         * - all other (RS1 complaint) tiles use UART mapped
+         *   at 0x1c090000
+         */
+        asm("mrc p15, 4, %0, c15, c0, 0" : "=r" (mpcore_periph));
+
+        if (mpcore_periph == 0x1e000000)
+                return UART_BASE;
+        else
+                return UART_BASE_RS1;
+}
 
 /*
  * This does not append a newline
diff --git a/arch/arm/mach-vexpress/platsmp.c b/arch/arm/mach-vexpress/platsmp.c
index 124ffb16909..14ba1128ae8 100644
--- a/arch/arm/mach-vexpress/platsmp.c
+++ b/arch/arm/mach-vexpress/platsmp.c
@@ -12,21 +12,168 @@
 #include <linux/errno.h>
 #include <linux/smp.h>
 #include <linux/io.h>
+#include <linux/of_fdt.h>
+
+#include <asm/smp_scu.h>
+#include <asm/hardware/gic.h>
+#include <asm/mach/map.h>
 
 #include <mach/motherboard.h>
-#define V2M_PA_CS7 0x10000000
 
 #include "core.h"
 
 extern void versatile_secondary_startup(void);
 
+#if defined(CONFIG_OF)
+
+static enum {
+        GENERIC_SCU,
+        CORTEX_A9_SCU,
+} vexpress_dt_scu __initdata = GENERIC_SCU;
+
+static struct map_desc vexpress_dt_cortex_a9_scu_map __initdata = {
+        .virtual        = V2T_PERIPH,
+        /* .pfn set in vexpress_dt_init_cortex_a9_scu() */
+        .length         = SZ_128,
+        .type           = MT_DEVICE,
+};
+
+static void *vexpress_dt_cortex_a9_scu_base __initdata;
+
+const static char *vexpress_dt_cortex_a9_match[] __initconst = {
+        "arm,cortex-a5-scu",
+        "arm,cortex-a9-scu",
+        NULL
+};
+
+static int __init vexpress_dt_find_scu(unsigned long node,
+                const char *uname, int depth, void *data)
+{
+        if (of_flat_dt_match(node, vexpress_dt_cortex_a9_match)) {
+                phys_addr_t phys_addr;
+                __be32 *reg = of_get_flat_dt_prop(node, "reg", NULL);
+
+                if (WARN_ON(!reg))
+                        return -EINVAL;
+
+                phys_addr = be32_to_cpup(reg);
+                vexpress_dt_scu = CORTEX_A9_SCU;
+
+                vexpress_dt_cortex_a9_scu_map.pfn = __phys_to_pfn(phys_addr);
+                iotable_init(&vexpress_dt_cortex_a9_scu_map, 1);
+                vexpress_dt_cortex_a9_scu_base = ioremap(phys_addr, SZ_256);
+                if (WARN_ON(!vexpress_dt_cortex_a9_scu_base))
+                        return -EFAULT;
+        }
+
+        return 0;
+}
+
+void __init vexpress_dt_smp_map_io(void)
+{
+        if (initial_boot_params)
+                WARN_ON(of_scan_flat_dt(vexpress_dt_find_scu, NULL));
+}
+
+static int __init vexpress_dt_cpus_num(unsigned long node, const char *uname,
+                int depth, void *data)
+{
+        static int prev_depth = -1;
+        static int nr_cpus = -1;
+
+        if (prev_depth > depth && nr_cpus > 0)
+                return nr_cpus;
+
+        if (nr_cpus < 0 && strcmp(uname, "cpus") == 0)
+                nr_cpus = 0;
+
+        if (nr_cpus >= 0) {
+                const char *device_type = of_get_flat_dt_prop(node,
+                                "device_type", NULL);
+
+                if (device_type && strcmp(device_type, "cpu") == 0)
+                        nr_cpus++;
+        }
+
+        prev_depth = depth;
+
+        return 0;
+}
+
+static void __init vexpress_dt_smp_init_cpus(void)
+{
+        int ncores = 0, i;
+
+        switch (vexpress_dt_scu) {
+        case GENERIC_SCU:
+                ncores = of_scan_flat_dt(vexpress_dt_cpus_num, NULL);
+                break;
+        case CORTEX_A9_SCU:
+                ncores = scu_get_core_count(vexpress_dt_cortex_a9_scu_base);
+                break;
+        default:
+                WARN_ON(1);
+                break;
+        }
+
+        if (ncores < 2)
+                return;
+
+        if (ncores > nr_cpu_ids) {
+                pr_warn("SMP: %u cores greater than maximum (%u), clipping\n",
+                                ncores, nr_cpu_ids);
+                ncores = nr_cpu_ids;
+        }
+
+        for (i = 0; i < ncores; ++i)
+                set_cpu_possible(i, true);
+
+        set_smp_cross_call(gic_raise_softirq);
+}
+
+static void __init vexpress_dt_smp_prepare_cpus(unsigned int max_cpus)
+{
+        int i;
+
+        switch (vexpress_dt_scu) {
+        case GENERIC_SCU:
+                for (i = 0; i < max_cpus; i++)
+                        set_cpu_present(i, true);
+                break;
+        case CORTEX_A9_SCU:
+                scu_enable(vexpress_dt_cortex_a9_scu_base);
+                break;
+        default:
+                WARN_ON(1);
+                break;
+        }
+}
+
+#else
+
+static void __init vexpress_dt_smp_init_cpus(void)
+{
+        WARN_ON(1);
+}
+
+void __init vexpress_dt_smp_prepare_cpus(unsigned int max_cpus)
+{
+        WARN_ON(1);
+}
+
+#endif
+
 /*
  * Initialise the CPU possible map early - this describes the CPUs
  * which may be present or become present in the system.
  */
 void __init smp_init_cpus(void)
 {
-        ct_desc->init_cpu_map();
+        if (ct_desc)
+                ct_desc->init_cpu_map();
+        else
+                vexpress_dt_smp_init_cpus();
+
 }
 
 void __init platform_smp_prepare_cpus(unsigned int max_cpus)
@@ -35,7 +182,10 @@ void __init platform_smp_prepare_cpus(unsigned int max_cpus)
          * Initialise the present map, which describes the set of CPUs
          * actually populated at the present time.
          */
-        ct_desc->smp_enable(max_cpus);
+        if (ct_desc)
+                ct_desc->smp_enable(max_cpus);
+        else
+                vexpress_dt_smp_prepare_cpus(max_cpus);
 
         /*
          * Write the address of secondary startup into the
@@ -43,7 +193,5 @@ void __init platform_smp_prepare_cpus(unsigned int max_cpus)
          * until it receives a soft interrupt, and then the
          * secondary CPU branches to this address.
          */
-        writel(~0, MMIO_P2V(V2M_SYS_FLAGSCLR));
-        writel(virt_to_phys(versatile_secondary_startup),
-                MMIO_P2V(V2M_SYS_FLAGSSET));
+        v2m_flags_set(virt_to_phys(versatile_secondary_startup));
 }
diff --git a/arch/arm/mach-vexpress/v2m.c b/arch/arm/mach-vexpress/v2m.c
index b4a28ca0e50..47cdcca5a7e 100644
--- a/arch/arm/mach-vexpress/v2m.c
+++ b/arch/arm/mach-vexpress/v2m.c
@@ -6,6 +6,10 @@
 #include <linux/amba/mmci.h>
 #include <linux/io.h>
 #include <linux/init.h>
+#include <linux/of_address.h>
+#include <linux/of_fdt.h>
+#include <linux/of_irq.h>
+#include <linux/of_platform.h>
 #include <linux/platform_device.h>
 #include <linux/ata_platform.h>
 #include <linux/smsc911x.h>
@@ -21,6 +25,8 @@
 #include <asm/mach/map.h>
 #include <asm/mach/time.h>
 #include <asm/hardware/arm_timer.h>
+#include <asm/hardware/cache-l2x0.h>
+#include <asm/hardware/gic.h>
 #include <asm/hardware/timer-sp.h>
 #include <asm/hardware/sp810.h>
 #include <asm/hardware/gic.h>
@@ -40,29 +46,45 @@
 
 static struct map_desc v2m_io_desc[] __initdata = {
         {
-                .virtual        = __MMIO_P2V(V2M_PA_CS7),
+                .virtual        = V2M_PERIPH,
                 .pfn            = __phys_to_pfn(V2M_PA_CS7),
                 .length         = SZ_128K,
                 .type           = MT_DEVICE,
         },
 };
 
-static void __init v2m_timer_init(void)
+static void __iomem *v2m_sysreg_base;
+
+static void __init v2m_sysctl_init(void __iomem *base)
 {
         u32 scctrl;
 
+        if (WARN_ON(!base))
+                return;
+
         /* Select 1MHz TIMCLK as the reference clock for SP804 timers */
-        scctrl = readl(MMIO_P2V(V2M_SYSCTL + SCCTRL));
+        scctrl = readl(base + SCCTRL);
         scctrl |= SCCTRL_TIMEREN0SEL_TIMCLK;
         scctrl |= SCCTRL_TIMEREN1SEL_TIMCLK;
-        writel(scctrl, MMIO_P2V(V2M_SYSCTL + SCCTRL));
+        writel(scctrl, base + SCCTRL);
+}
+
+static void __init v2m_sp804_init(void __iomem *base, unsigned int irq)
+{
+        if (WARN_ON(!base || irq == NO_IRQ))
+                return;
+
+        writel(0, base + TIMER_1_BASE + TIMER_CTRL);
+        writel(0, base + TIMER_2_BASE + TIMER_CTRL);
 
-        writel(0, MMIO_P2V(V2M_TIMER0) + TIMER_CTRL);
-        writel(0, MMIO_P2V(V2M_TIMER1) + TIMER_CTRL);
+        sp804_clocksource_init(base + TIMER_2_BASE, "v2m-timer1");
+        sp804_clockevents_init(base + TIMER_1_BASE, irq, "v2m-timer0");
+}
 
-        sp804_clocksource_init(MMIO_P2V(V2M_TIMER1), "v2m-timer1");
-        sp804_clockevents_init(MMIO_P2V(V2M_TIMER0), IRQ_V2M_TIMER0,
-                "v2m-timer0");
+static void __init v2m_timer_init(void)
+{
+        v2m_sysctl_init(ioremap(V2M_SYSCTL, SZ_4K));
+        v2m_sp804_init(ioremap(V2M_TIMER01, SZ_4K), IRQ_V2M_TIMER0);
 }
 
 static struct sys_timer v2m_timer = {
@@ -82,14 +104,14 @@ int v2m_cfg_write(u32 devfn, u32 data)
         devfn |= SYS_CFG_START | SYS_CFG_WRITE;
 
         spin_lock(&v2m_cfg_lock);
-        val = readl(MMIO_P2V(V2M_SYS_CFGSTAT));
-        writel(val & ~SYS_CFG_COMPLETE, MMIO_P2V(V2M_SYS_CFGSTAT));
+        val = readl(v2m_sysreg_base + V2M_SYS_CFGSTAT);
+        writel(val & ~SYS_CFG_COMPLETE, v2m_sysreg_base + V2M_SYS_CFGSTAT);
 
-        writel(data, MMIO_P2V(V2M_SYS_CFGDATA));
-        writel(devfn, MMIO_P2V(V2M_SYS_CFGCTRL));
+        writel(data, v2m_sysreg_base +  V2M_SYS_CFGDATA);
+        writel(devfn, v2m_sysreg_base + V2M_SYS_CFGCTRL);
 
         do {
-                val = readl(MMIO_P2V(V2M_SYS_CFGSTAT));
+                val = readl(v2m_sysreg_base + V2M_SYS_CFGSTAT);
         } while (val == 0);
         spin_unlock(&v2m_cfg_lock);
 
@@ -103,22 +125,28 @@ int v2m_cfg_read(u32 devfn, u32 *data)
         devfn |= SYS_CFG_START;
 
         spin_lock(&v2m_cfg_lock);
-        writel(0, MMIO_P2V(V2M_SYS_CFGSTAT));
-        writel(devfn, MMIO_P2V(V2M_SYS_CFGCTRL));
+        writel(0, v2m_sysreg_base + V2M_SYS_CFGSTAT);
+        writel(devfn, v2m_sysreg_base + V2M_SYS_CFGCTRL);
 
         mb();
 
         do {
                 cpu_relax();
-                val = readl(MMIO_P2V(V2M_SYS_CFGSTAT));
+                val = readl(v2m_sysreg_base + V2M_SYS_CFGSTAT);
         } while (val == 0);
 
-        *data = readl(MMIO_P2V(V2M_SYS_CFGDATA));
+        *data = readl(v2m_sysreg_base + V2M_SYS_CFGDATA);
         spin_unlock(&v2m_cfg_lock);
 
         return !!(val & SYS_CFG_ERR);
 }
 
+void __init v2m_flags_set(u32 data)
+{
+        writel(~0, v2m_sysreg_base + V2M_SYS_FLAGSCLR);
+        writel(data, v2m_sysreg_base + V2M_SYS_FLAGSSET);
+}
+
 
 static struct resource v2m_pcie_i2c_resource = {
         .start  = V2M_SERIAL_BUS_PCI,
@@ -204,7 +232,7 @@ static struct platform_device v2m_usb_device = {
 
 static void v2m_flash_set_vpp(struct platform_device *pdev, int on)
 {
-        writel(on != 0, MMIO_P2V(V2M_SYS_FLASH));
+        writel(on != 0, v2m_sysreg_base + V2M_SYS_FLASH);
 }
 
 static struct physmap_flash_data v2m_flash_data = {
@@ -258,7 +286,7 @@ static struct platform_device v2m_cf_device = {
 
 static unsigned int v2m_mmci_status(struct device *dev)
 {
-        return readl(MMIO_P2V(V2M_SYS_MCI)) & (1 << 0);
+        return readl(v2m_sysreg_base + V2M_SYS_MCI) & (1 << 0);
 }
 
 static struct mmci_platform_data v2m_mmci_data = {
@@ -266,16 +294,16 @@ static struct mmci_platform_data v2m_mmci_data = {
         .status         = v2m_mmci_status,
 };
 
-static AMBA_DEVICE(aaci,  "mb:aaci",  V2M_AACI, NULL);
-static AMBA_DEVICE(mmci,  "mb:mmci",  V2M_MMCI, &v2m_mmci_data);
-static AMBA_DEVICE(kmi0,  "mb:kmi0",  V2M_KMI0, NULL);
-static AMBA_DEVICE(kmi1,  "mb:kmi1",  V2M_KMI1, NULL);
-static AMBA_DEVICE(uart0, "mb:uart0", V2M_UART0, NULL);
-static AMBA_DEVICE(uart1, "mb:uart1", V2M_UART1, NULL);
-static AMBA_DEVICE(uart2, "mb:uart2", V2M_UART2, NULL);
-static AMBA_DEVICE(uart3, "mb:uart3", V2M_UART3, NULL);
-static AMBA_DEVICE(wdt,   "mb:wdt",   V2M_WDT, NULL);
-static AMBA_DEVICE(rtc,   "mb:rtc",   V2M_RTC, NULL);
+static AMBA_APB_DEVICE(aaci,  "mb:aaci",  0, V2M_AACI, IRQ_V2M_AACI, NULL);
+static AMBA_APB_DEVICE(mmci,  "mb:mmci",  0, V2M_MMCI, IRQ_V2M_MMCI, &v2m_mmci_data);
+static AMBA_APB_DEVICE(kmi0,  "mb:kmi0",  0, V2M_KMI0, IRQ_V2M_KMI0, NULL);
+static AMBA_APB_DEVICE(kmi1,  "mb:kmi1",  0, V2M_KMI1, IRQ_V2M_KMI1, NULL);
+static AMBA_APB_DEVICE(uart0, "mb:uart0", 0, V2M_UART0, IRQ_V2M_UART0, NULL);
+static AMBA_APB_DEVICE(uart1, "mb:uart1", 0, V2M_UART1, IRQ_V2M_UART1, NULL);
+static AMBA_APB_DEVICE(uart2, "mb:uart2", 0, V2M_UART2, IRQ_V2M_UART2, NULL);
+static AMBA_APB_DEVICE(uart3, "mb:uart3", 0, V2M_UART3, IRQ_V2M_UART3, NULL);
+static AMBA_APB_DEVICE(wdt,   "mb:wdt",   0, V2M_WDT, IRQ_V2M_WDT, NULL);
+static AMBA_APB_DEVICE(rtc,   "mb:rtc",   0, V2M_RTC, IRQ_V2M_RTC, NULL);
 
 static struct amba_device *v2m_amba_devs[] __initdata = {
         &aaci_device,
@@ -371,7 +399,7 @@ static void __init v2m_init_early(void)
 {
         ct_desc->init_early();
         clkdev_add_table(v2m_lookups, ARRAY_SIZE(v2m_lookups));
-        versatile_sched_clock_init(MMIO_P2V(V2M_SYS_24MHZ), 24000000);
+        versatile_sched_clock_init(v2m_sysreg_base + V2M_SYS_24MHZ, 24000000);
 }
 
 static void v2m_power_off(void)
@@ -400,20 +428,23 @@ static void __init v2m_populate_ct_desc(void)
         u32 current_tile_id;
 
         ct_desc = NULL;
-        current_tile_id = readl(MMIO_P2V(V2M_SYS_PROCID0)) & V2M_CT_ID_MASK;
+        current_tile_id = readl(v2m_sysreg_base + V2M_SYS_PROCID0)
+                                & V2M_CT_ID_MASK;
 
         for (i = 0; i < ARRAY_SIZE(ct_descs) && !ct_desc; ++i)
                 if (ct_descs[i]->id == current_tile_id)
                         ct_desc = ct_descs[i];
 
         if (!ct_desc)
-                panic("vexpress: failed to populate core tile description "
-                      "for tile ID 0x%8x\n", current_tile_id);
+                panic("vexpress: this kernel does not support core tile ID 0x%08x when booting via ATAGs.\n"
+                      "You may need a device tree blob or a different kernel to boot on this board.\n",
+                      current_tile_id);
 }
 
 static void __init v2m_map_io(void)
 {
         iotable_init(v2m_io_desc, ARRAY_SIZE(v2m_io_desc));
+        v2m_sysreg_base = ioremap(V2M_SYSREGS, SZ_4K);
         v2m_populate_ct_desc();
         ct_desc->map_io();
 }
@@ -452,3 +483,205 @@ MACHINE_START(VEXPRESS, "ARM-Versatile Express")
         .init_machine   = v2m_init,
         .restart        = v2m_restart,
 MACHINE_END
+
+#if defined(CONFIG_ARCH_VEXPRESS_DT)
+
+static struct map_desc v2m_rs1_io_desc __initdata = {
+        .virtual        = V2M_PERIPH,
+        .pfn            = __phys_to_pfn(0x1c000000),
+        .length         = SZ_2M,
+        .type           = MT_DEVICE,
+};
+
+static int __init v2m_dt_scan_memory_map(unsigned long node, const char *uname,
+                int depth, void *data)
+{
+        const char **map = data;
+
+        if (strcmp(uname, "motherboard") != 0)
+                return 0;
+
+        *map = of_get_flat_dt_prop(node, "arm,v2m-memory-map", NULL);
+
+        return 1;
+}
+
+void __init v2m_dt_map_io(void)
+{
+        const char *map = NULL;
+
+        of_scan_flat_dt(v2m_dt_scan_memory_map, &map);
+
+        if (map && strcmp(map, "rs1") == 0)
+                iotable_init(&v2m_rs1_io_desc, 1);
+        else
+                iotable_init(v2m_io_desc, ARRAY_SIZE(v2m_io_desc));
+
+#if defined(CONFIG_SMP)
+        vexpress_dt_smp_map_io();
+#endif
+}
+
+static struct clk_lookup v2m_dt_lookups[] = {
+        {       /* AMBA bus clock */
+                .con_id         = "apb_pclk",
+                .clk            = &dummy_apb_pclk,
+        }, {    /* SP804 timers */
+                .dev_id         = "sp804",
+                .con_id         = "v2m-timer0",
+                .clk            = &v2m_sp804_clk,
+        }, {    /* SP804 timers */
+                .dev_id         = "sp804",
+                .con_id         = "v2m-timer1",
+                .clk            = &v2m_sp804_clk,
+        }, {    /* PL180 MMCI */
+                .dev_id         = "mb:mmci", /* 10005000.mmci */
+                .clk            = &osc2_clk,
+        }, {    /* PL050 KMI0 */
+                .dev_id         = "10006000.kmi",
+                .clk            = &osc2_clk,
+        }, {    /* PL050 KMI1 */
+                .dev_id         = "10007000.kmi",
+                .clk            = &osc2_clk,
+        }, {    /* PL011 UART0 */
+                .dev_id         = "10009000.uart",
+                .clk            = &osc2_clk,
+        }, {    /* PL011 UART1 */
+                .dev_id         = "1000a000.uart",
+                .clk            = &osc2_clk,
+        }, {    /* PL011 UART2 */
+                .dev_id         = "1000b000.uart",
+                .clk            = &osc2_clk,
+        }, {    /* PL011 UART3 */
+                .dev_id         = "1000c000.uart",
+                .clk            = &osc2_clk,
+        }, {    /* SP805 WDT */
+                .dev_id         = "1000f000.wdt",
+                .clk            = &v2m_ref_clk,
+        }, {    /* PL111 CLCD */
+                .dev_id         = "1001f000.clcd",
+                .clk            = &osc1_clk,
+        },
+        /* RS1 memory map */
+        {       /* PL180 MMCI */
+                .dev_id         = "mb:mmci", /* 1c050000.mmci */
+                .clk            = &osc2_clk,
+        }, {    /* PL050 KMI0 */
+                .dev_id         = "1c060000.kmi",
+                .clk            = &osc2_clk,
+        }, {    /* PL050 KMI1 */
+                .dev_id         = "1c070000.kmi",
+                .clk            = &osc2_clk,
+        }, {    /* PL011 UART0 */
+                .dev_id         = "1c090000.uart",
+                .clk            = &osc2_clk,
+        }, {    /* PL011 UART1 */
+                .dev_id         = "1c0a0000.uart",
+                .clk            = &osc2_clk,
+        }, {    /* PL011 UART2 */
+                .dev_id         = "1c0b0000.uart",
+                .clk            = &osc2_clk,
+        }, {    /* PL011 UART3 */
+                .dev_id         = "1c0c0000.uart",
+                .clk            = &osc2_clk,
+        }, {    /* SP805 WDT */
+                .dev_id         = "1c0f0000.wdt",
+                .clk            = &v2m_ref_clk,
+        }, {    /* PL111 CLCD */
+                .dev_id         = "1c1f0000.clcd",
+                .clk            = &osc1_clk,
+        },
+};
+
+void __init v2m_dt_init_early(void)
+{
+        struct device_node *node;
+        u32 dt_hbi;
+
+        node = of_find_compatible_node(NULL, NULL, "arm,vexpress-sysreg");
+        v2m_sysreg_base = of_iomap(node, 0);
+        if (WARN_ON(!v2m_sysreg_base))
+                return;
+
+        /* Confirm board type against DT property, if available */
+        if (of_property_read_u32(allnodes, "arm,hbi", &dt_hbi) == 0) {
+                u32 misc = readl(v2m_sysreg_base + V2M_SYS_MISC);
+                u32 id = readl(v2m_sysreg_base + (misc & SYS_MISC_MASTERSITE ?
+                                V2M_SYS_PROCID1 : V2M_SYS_PROCID0));
+                u32 hbi = id & SYS_PROCIDx_HBI_MASK;
+
+                if (WARN_ON(dt_hbi != hbi))
+                        pr_warning("vexpress: DT HBI (%x) is not matching "
+                                        "hardware (%x)!\n", dt_hbi, hbi);
+        }
+
+        clkdev_add_table(v2m_dt_lookups, ARRAY_SIZE(v2m_dt_lookups));
+        versatile_sched_clock_init(v2m_sysreg_base + V2M_SYS_24MHZ, 24000000);
+}
+
+static  struct of_device_id vexpress_irq_match[] __initdata = {
+        { .compatible = "arm,cortex-a9-gic", .data = gic_of_init, },
+        {}
+};
+
+static void __init v2m_dt_init_irq(void)
+{
+        of_irq_init(vexpress_irq_match);
+}
+
+static void __init v2m_dt_timer_init(void)
+{
+        struct device_node *node;
+        const char *path;
+        int err;
+
+        node = of_find_compatible_node(NULL, NULL, "arm,sp810");
+        v2m_sysctl_init(of_iomap(node, 0));
+
+        err = of_property_read_string(of_aliases, "arm,v2m_timer", &path);
+        if (WARN_ON(err))
+                return;
+        node = of_find_node_by_path(path);
+        v2m_sp804_init(of_iomap(node, 0), irq_of_parse_and_map(node, 0));
+}
+
+static struct sys_timer v2m_dt_timer = {
+        .init = v2m_dt_timer_init,
+};
+
+static struct of_dev_auxdata v2m_dt_auxdata_lookup[] __initdata = {
+        OF_DEV_AUXDATA("arm,vexpress-flash", V2M_NOR0, "physmap-flash",
+                        &v2m_flash_data),
+        OF_DEV_AUXDATA("arm,primecell", V2M_MMCI, "mb:mmci", &v2m_mmci_data),
+        /* RS1 memory map */
+        OF_DEV_AUXDATA("arm,vexpress-flash", 0x08000000, "physmap-flash",
+                        &v2m_flash_data),
+        OF_DEV_AUXDATA("arm,primecell", 0x1c050000, "mb:mmci", &v2m_mmci_data),
+        {}
+};
+
+static void __init v2m_dt_init(void)
+{
+        l2x0_of_init(0x00400000, 0xfe0fffff);
+        of_platform_populate(NULL, of_default_bus_match_table,
+                        v2m_dt_auxdata_lookup, NULL);
+        pm_power_off = v2m_power_off;
+}
+
+const static char *v2m_dt_match[] __initconst = {
+        "arm,vexpress",
+        NULL,
+};
+
+DT_MACHINE_START(VEXPRESS_DT, "ARM-Versatile Express")
+        .dt_compat      = v2m_dt_match,
+        .map_io         = v2m_dt_map_io,
+        .init_early     = v2m_dt_init_early,
+        .init_irq       = v2m_dt_init_irq,
+        .timer          = &v2m_dt_timer,
+        .init_machine   = v2m_dt_init,
+        .handle_irq     = gic_handle_irq,
+        .restart        = v2m_restart,
+MACHINE_END
+
+#endif
diff --git a/arch/arm/mach-vt8500/include/mach/entry-macro.S b/arch/arm/mach-vt8500/include/mach/entry-macro.S
index 92684c7eaed..367d1b55fb9 100644
--- a/arch/arm/mach-vt8500/include/mach/entry-macro.S
+++ b/arch/arm/mach-vt8500/include/mach/entry-macro.S
@@ -8,18 +8,12 @@
  * warranty of any kind, whether express or implied.
  */
 
-        .macro  disable_fiq
-        .endm
-
         .macro  get_irqnr_preamble, base, tmp
         @ physical 0xd8140000 is virtual 0xf8140000
         mov     \base, #0xf8000000
         orr     \base, \base, #0x00140000
         .endm
 
-        .macro  arch_ret_to_user, tmp1, tmp2
-        .endm
-
         .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
         ldr     \irqnr, [\base]
         cmp     \irqnr, #63 @ may be false positive, check interrupt status
diff --git a/arch/arm/mach-vt8500/include/mach/system.h b/arch/arm/mach-vt8500/include/mach/system.h
index d6c757eaf26..58fa8010ee6 100644
--- a/arch/arm/mach-vt8500/include/mach/system.h
+++ b/arch/arm/mach-vt8500/include/mach/system.h
@@ -7,11 +7,6 @@
 /* PM Software Reset request register */
 #define VT8500_PMSR_VIRT        0xf8130060
 
-static inline void arch_idle(void)
-{
-        cpu_do_idle();
-}
-
 static inline void arch_reset(char mode, const char *cmd)
 {
         writel(1, VT8500_PMSR_VIRT);
diff --git a/arch/arm/mach-w90x900/dev.c b/arch/arm/mach-w90x900/dev.c
index 78110befb7a..db82568a998 100644
--- a/arch/arm/mach-w90x900/dev.c
+++ b/arch/arm/mach-w90x900/dev.c
@@ -530,6 +530,7 @@ static struct platform_device *nuc900_public_dev[] __initdata = {
 
 void __init nuc900_board_init(struct platform_device **device, int size)
 {
+        disable_hlt();
         platform_add_devices(device, size);
         platform_add_devices(nuc900_public_dev, ARRAY_SIZE(nuc900_public_dev));
         spi_register_board_info(nuc900_spi_board_info,
diff --git a/arch/arm/mach-w90x900/include/mach/entry-macro.S b/arch/arm/mach-w90x900/include/mach/entry-macro.S
index d39aca5be9e..e286daca682 100644
--- a/arch/arm/mach-w90x900/include/mach/entry-macro.S
+++ b/arch/arm/mach-w90x900/include/mach/entry-macro.S
@@ -15,9 +15,6 @@
         .macro  get_irqnr_preamble, base, tmp
         .endm
 
-        .macro  arch_ret_to_user, tmp1, tmp2
-        .endm
-
         .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
 
                 mov     \base, #AIC_BA
@@ -27,8 +24,3 @@
                 cmp     \irqnr, #0
 
         .endm
-
-        /* currently don't need an disable_fiq macro */
-
-        .macro  disable_fiq
-        .endm
diff --git a/arch/arm/mach-w90x900/include/mach/system.h b/arch/arm/mach-w90x900/include/mach/system.h
deleted file mode 100644
index 2aaeb931161..00000000000
--- a/arch/arm/mach-w90x900/include/mach/system.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/*
- * arch/arm/mach-w90x900/include/mach/system.h
- *
- * Copyright (c) 2008 Nuvoton technology corporation
- * All rights reserved.
- *
- * Wan ZongShun <mcuos.com@gmail.com>
- *
- * Based on arch/arm/mach-s3c2410/include/mach/system.h
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- */
-static void arch_idle(void)
-{
-}
diff --git a/arch/arm/mach-zynq/include/mach/entry-macro.S b/arch/arm/mach-zynq/include/mach/entry-macro.S
deleted file mode 100644
index d621fb73256..00000000000
--- a/arch/arm/mach-zynq/include/mach/entry-macro.S
+++ /dev/null
@@ -1,27 +0,0 @@
-/*
- * arch/arm/mach-zynq/include/mach/entry-macro.S
- *
- * Low-level IRQ helper macros
- *
- *  Copyright (C) 2011 Xilinx
- *
- * based on arch/plat-mxc/include/mach/entry-macro.S
- *
- *  Copyright (C) 2007 Lennert Buytenhek <buytenh@wantstofly.org>
- *  Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-                .macro  disable_fiq
-                .endm
-
-                .macro  arch_ret_to_user, tmp1, tmp2
-                .endm
diff --git a/arch/arm/mach-zynq/include/mach/system.h b/arch/arm/mach-zynq/include/mach/system.h
deleted file mode 100644
index 8e88e0b8d2b..00000000000
--- a/arch/arm/mach-zynq/include/mach/system.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/* arch/arm/mach-zynq/include/mach/system.h
- *
- *  Copyright (C) 2011 Xilinx
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#ifndef __MACH_SYSTEM_H__
-#define __MACH_SYSTEM_H__
-
-static inline void arch_idle(void)
-{
-        cpu_do_idle();
-}
-
-#endif
diff --git a/arch/arm/mm/iomap.c b/arch/arm/mm/iomap.c
index e62956e1203..4614208369f 100644
--- a/arch/arm/mm/iomap.c
+++ b/arch/arm/mm/iomap.c
@@ -32,9 +32,6 @@ EXPORT_SYMBOL(pcibios_min_io);
 unsigned long pcibios_min_mem = 0x01000000;
 EXPORT_SYMBOL(pcibios_min_mem);
 
-unsigned int pci_flags = PCI_REASSIGN_ALL_RSRC;
-EXPORT_SYMBOL(pci_flags);
-
 void pci_iounmap(struct pci_dev *dev, void __iomem *addr)
 {
         if ((unsigned long)addr >= VMALLOC_START &&
diff --git a/arch/arm/plat-iop/pci.c b/arch/arm/plat-iop/pci.c
index f4d40a27111..72768356447 100644
--- a/arch/arm/plat-iop/pci.c
+++ b/arch/arm/plat-iop/pci.c
@@ -215,8 +215,8 @@ int iop3xx_pci_setup(int nr, struct pci_sys_data *sys)
         sys->mem_offset = IOP3XX_PCI_LOWER_MEM_PA - *IOP3XX_OMWTVR0;
         sys->io_offset  = IOP3XX_PCI_LOWER_IO_PA - *IOP3XX_OIOWTVR;
 
-        pci_add_resource(&sys->resources, &res[0]);
-        pci_add_resource(&sys->resources, &res[1]);
+        pci_add_resource_offset(&sys->resources, &res[0], sys->io_offset);
+        pci_add_resource_offset(&sys->resources, &res[1], sys->mem_offset);
 
         return 1;
 }
diff --git a/arch/arm/plat-mxc/Kconfig b/arch/arm/plat-mxc/Kconfig
index dcebb1230f7..c722f9ce691 100644
--- a/arch/arm/plat-mxc/Kconfig
+++ b/arch/arm/plat-mxc/Kconfig
@@ -88,12 +88,6 @@ config IMX_HAVE_IOMUX_V1
 config ARCH_MXC_IOMUX_V3
         bool
 
-config ARCH_MXC_AUDMUX_V1
-        bool
-
-config ARCH_MXC_AUDMUX_V2
-        bool
-
 config IRAM_ALLOC
         bool
         select GENERIC_ALLOCATOR
diff --git a/arch/arm/plat-mxc/Makefile b/arch/arm/plat-mxc/Makefile
index 076db84f3e3..e81290c27c6 100644
--- a/arch/arm/plat-mxc/Makefile
+++ b/arch/arm/plat-mxc/Makefile
@@ -14,8 +14,6 @@ obj-$(CONFIG_IRAM_ALLOC) += iram_alloc.o
 obj-$(CONFIG_MXC_PWM)  += pwm.o
 obj-$(CONFIG_MXC_ULPI) += ulpi.o
 obj-$(CONFIG_MXC_USE_EPIT) += epit.o
-obj-$(CONFIG_ARCH_MXC_AUDMUX_V1) += audmux-v1.o
-obj-$(CONFIG_ARCH_MXC_AUDMUX_V2) += audmux-v2.o
 obj-$(CONFIG_MXC_DEBUG_BOARD) += 3ds_debugboard.o
 obj-$(CONFIG_CPU_FREQ_IMX)    += cpufreq.o
 ifdef CONFIG_SND_IMX_SOC
diff --git a/arch/arm/plat-mxc/audmux-v1.c b/arch/arm/plat-mxc/audmux-v1.c
deleted file mode 100644
index 1180bef7664..00000000000
--- a/arch/arm/plat-mxc/audmux-v1.c
+++ /dev/null
@@ -1,64 +0,0 @@
-/*
- * Copyright 2009 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
- *
- * Initial development of this code was funded by
- * Phytec Messtechnik GmbH, http://www.phytec.de
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <linux/module.h>
-#include <linux/err.h>
-#include <linux/io.h>
-#include <linux/clk.h>
-#include <mach/audmux.h>
-#include <mach/hardware.h>
-
-static void __iomem *audmux_base;
-
-static unsigned char port_mapping[] = {
-        0x0, 0x4, 0x8, 0x10, 0x14, 0x1c,
-};
-
-int mxc_audmux_v1_configure_port(unsigned int port, unsigned int pcr)
-{
-        if (!audmux_base) {
-                printk("%s: not configured\n", __func__);
-                return -ENOSYS;
-        }
-
-        if (port >= ARRAY_SIZE(port_mapping))
-                return -EINVAL;
-
-        writel(pcr, audmux_base + port_mapping[port]);
-
-        return 0;
-}
-EXPORT_SYMBOL_GPL(mxc_audmux_v1_configure_port);
-
-static int mxc_audmux_v1_init(void)
-{
-#ifdef CONFIG_MACH_MX21
-        if (cpu_is_mx21())
-                audmux_base = MX21_IO_ADDRESS(MX21_AUDMUX_BASE_ADDR);
-        else
-#endif
-#ifdef CONFIG_MACH_MX27
-        if (cpu_is_mx27())
-                audmux_base = MX27_IO_ADDRESS(MX27_AUDMUX_BASE_ADDR);
-        else
-#endif
-                (void)0;
-        
-        return 0;
-}
-
-postcore_initcall(mxc_audmux_v1_init);
diff --git a/arch/arm/plat-mxc/audmux-v2.c b/arch/arm/plat-mxc/audmux-v2.c
deleted file mode 100644
index 8cced35009b..00000000000
--- a/arch/arm/plat-mxc/audmux-v2.c
+++ /dev/null
@@ -1,219 +0,0 @@
-/*
- * Copyright 2009 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
- *
- * Initial development of this code was funded by
- * Phytec Messtechnik GmbH, http://www.phytec.de
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <linux/module.h>
-#include <linux/err.h>
-#include <linux/io.h>
-#include <linux/clk.h>
-#include <linux/debugfs.h>
-#include <linux/slab.h>
-#include <mach/audmux.h>
-#include <mach/hardware.h>
-
-static struct clk *audmux_clk;
-static void __iomem *audmux_base;
-
-#define MXC_AUDMUX_V2_PTCR(x)           ((x) * 8)
-#define MXC_AUDMUX_V2_PDCR(x)           ((x) * 8 + 4)
-
-#ifdef CONFIG_DEBUG_FS
-static struct dentry *audmux_debugfs_root;
-
-static int audmux_open_file(struct inode *inode, struct file *file)
-{
-        file->private_data = inode->i_private;
-        return 0;
-}
-
-/* There is an annoying discontinuity in the SSI numbering with regard
- * to the Linux number of the devices */
-static const char *audmux_port_string(int port)
-{
-        switch (port) {
-        case MX31_AUDMUX_PORT1_SSI0:
-                return "imx-ssi.0";
-        case MX31_AUDMUX_PORT2_SSI1:
-                return "imx-ssi.1";
-        case MX31_AUDMUX_PORT3_SSI_PINS_3:
-                return "SSI3";
-        case MX31_AUDMUX_PORT4_SSI_PINS_4:
-                return "SSI4";
-        case MX31_AUDMUX_PORT5_SSI_PINS_5:
-                return "SSI5";
-        case MX31_AUDMUX_PORT6_SSI_PINS_6:
-                return "SSI6";
-        default:
-                return "UNKNOWN";
-        }
-}
-
-static ssize_t audmux_read_file(struct file *file, char __user *user_buf,
-                                size_t count, loff_t *ppos)
-{
-        ssize_t ret;
-        char *buf = kmalloc(PAGE_SIZE, GFP_KERNEL);
-        int port = (int)file->private_data;
-        u32 pdcr, ptcr;
-
-        if (!buf)
-                return -ENOMEM;
-
-        if (audmux_clk)
-                clk_enable(audmux_clk);
-
-        ptcr = readl(audmux_base + MXC_AUDMUX_V2_PTCR(port));
-        pdcr = readl(audmux_base + MXC_AUDMUX_V2_PDCR(port));
-
-        if (audmux_clk)
-                clk_disable(audmux_clk);
-
-        ret = snprintf(buf, PAGE_SIZE, "PDCR: %08x\nPTCR: %08x\n",
-                       pdcr, ptcr);
-
-        if (ptcr & MXC_AUDMUX_V2_PTCR_TFSDIR)
-                ret += snprintf(buf + ret, PAGE_SIZE - ret,
-                                "TxFS output from %s, ",
-                                audmux_port_string((ptcr >> 27) & 0x7));
-        else
-                ret += snprintf(buf + ret, PAGE_SIZE - ret,
-                                "TxFS input, ");
-
-        if (ptcr & MXC_AUDMUX_V2_PTCR_TCLKDIR)
-                ret += snprintf(buf + ret, PAGE_SIZE - ret,
-                                "TxClk output from %s",
-                                audmux_port_string((ptcr >> 22) & 0x7));
-        else
-                ret += snprintf(buf + ret, PAGE_SIZE - ret,
-                                "TxClk input");
-
-        ret += snprintf(buf + ret, PAGE_SIZE - ret, "\n");
-
-        if (ptcr & MXC_AUDMUX_V2_PTCR_SYN) {
-                ret += snprintf(buf + ret, PAGE_SIZE - ret,
-                                "Port is symmetric");
-        } else {
-                if (ptcr & MXC_AUDMUX_V2_PTCR_RFSDIR)
-                        ret += snprintf(buf + ret, PAGE_SIZE - ret,
-                                        "RxFS output from %s, ",
-                                        audmux_port_string((ptcr >> 17) & 0x7));
-                else
-                        ret += snprintf(buf + ret, PAGE_SIZE - ret,
-                                        "RxFS input, ");
-
-                if (ptcr & MXC_AUDMUX_V2_PTCR_RCLKDIR)
-                        ret += snprintf(buf + ret, PAGE_SIZE - ret,
-                                        "RxClk output from %s",
-                                        audmux_port_string((ptcr >> 12) & 0x7));
-                else
-                        ret += snprintf(buf + ret, PAGE_SIZE - ret,
-                                        "RxClk input");
-        }
-
-        ret += snprintf(buf + ret, PAGE_SIZE - ret,
-                        "\nData received from %s\n",
-                        audmux_port_string((pdcr >> 13) & 0x7));
-
-        ret = simple_read_from_buffer(user_buf, count, ppos, buf, ret);
-
-        kfree(buf);
-
-        return ret;
-}
-
-static const struct file_operations audmux_debugfs_fops = {
-        .open = audmux_open_file,
-        .read = audmux_read_file,
-        .llseek = default_llseek,
-};
-
-static void audmux_debugfs_init(void)
-{
-        int i;
-        char buf[20];
-
-        audmux_debugfs_root = debugfs_create_dir("audmux", NULL);
-        if (!audmux_debugfs_root) {
-                pr_warning("Failed to create AUDMUX debugfs root\n");
-                return;
-        }
-
-        for (i = 1; i < 8; i++) {
-                snprintf(buf, sizeof(buf), "ssi%d", i);
-                if (!debugfs_create_file(buf, 0444, audmux_debugfs_root,
-                                         (void *)i, &audmux_debugfs_fops))
-                        pr_warning("Failed to create AUDMUX port %d debugfs file\n",
-                                   i);
-        }
-}
-#else
-static inline void audmux_debugfs_init(void)
-{
-}
-#endif
-
-int mxc_audmux_v2_configure_port(unsigned int port, unsigned int ptcr,
-                unsigned int pdcr)
-{
-        if (!audmux_base)
-                return -ENOSYS;
-
-        if (audmux_clk)
-                clk_enable(audmux_clk);
-
-        writel(ptcr, audmux_base + MXC_AUDMUX_V2_PTCR(port));
-        writel(pdcr, audmux_base + MXC_AUDMUX_V2_PDCR(port));
-
-        if (audmux_clk)
-                clk_disable(audmux_clk);
-
-        return 0;
-}
-EXPORT_SYMBOL_GPL(mxc_audmux_v2_configure_port);
-
-static int mxc_audmux_v2_init(void)
-{
-        int ret;
-        if (cpu_is_mx51()) {
-                audmux_base = MX51_IO_ADDRESS(MX51_AUDMUX_BASE_ADDR);
-        } else if (cpu_is_mx31()) {
-                audmux_base = MX31_IO_ADDRESS(MX31_AUDMUX_BASE_ADDR);
-        } else if (cpu_is_mx35()) {
-                audmux_clk = clk_get(NULL, "audmux");
-                if (IS_ERR(audmux_clk)) {
-                        ret = PTR_ERR(audmux_clk);
-                        printk(KERN_ERR "%s: cannot get clock: %d\n", __func__,
-                                        ret);
-                        return ret;
-                }
-                audmux_base = MX35_IO_ADDRESS(MX35_AUDMUX_BASE_ADDR);
-        } else if (cpu_is_mx25()) {
-                audmux_clk = clk_get(NULL, "audmux");
-                if (IS_ERR(audmux_clk)) {
-                        ret = PTR_ERR(audmux_clk);
-                        printk(KERN_ERR "%s: cannot get clock: %d\n", __func__,
-                                        ret);
-                        return ret;
-                }
-                audmux_base = MX25_IO_ADDRESS(MX25_AUDMUX_BASE_ADDR);
-        }
-
-        audmux_debugfs_init();
-
-        return 0;
-}
-
-postcore_initcall(mxc_audmux_v2_init);
diff --git a/arch/arm/plat-mxc/avic.c b/arch/arm/plat-mxc/avic.c
index 55f15699a38..689f81f9593 100644
--- a/arch/arm/plat-mxc/avic.c
+++ b/arch/arm/plat-mxc/avic.c
@@ -60,7 +60,7 @@ static int avic_irq_set_priority(unsigned char irq, unsigned char prio)
         unsigned int mask = 0x0F << irq % 8 * 4;
 
         if (irq >= AVIC_NUM_IRQS)
-                return -EINVAL;;
+                return -EINVAL;
 
         temp = __raw_readl(avic_base + AVIC_NIPRIORITY(irq / 8));
         temp &= ~mask;
diff --git a/arch/arm/plat-mxc/cpu.c b/arch/arm/plat-mxc/cpu.c
index f5b7e0fa237..220dd6f9312 100644
--- a/arch/arm/plat-mxc/cpu.c
+++ b/arch/arm/plat-mxc/cpu.c
@@ -1,5 +1,6 @@
 
 #include <linux/module.h>
+#include <linux/io.h>
 #include <mach/hardware.h>
 
 unsigned int __mxc_cpu_type;
@@ -18,3 +19,26 @@ void imx_print_silicon_rev(const char *cpu, int srev)
                 pr_info("CPU identified as %s, silicon rev %d.%d\n",
                                 cpu, (srev >> 4) & 0xf, srev & 0xf);
 }
+
+void __init imx_set_aips(void __iomem *base)
+{
+        unsigned int reg;
+/*
+ * Set all MPROTx to be non-bufferable, trusted for R/W,
+ * not forced to user-mode.
+ */
+        __raw_writel(0x77777777, base + 0x0);
+        __raw_writel(0x77777777, base + 0x4);
+
+/*
+ * Set all OPACRx to be non-bufferable, to not require
+ * supervisor privilege level for access, allow for
+ * write access and untrusted master access.
+ */
+        __raw_writel(0x0, base + 0x40);
+        __raw_writel(0x0, base + 0x44);
+        __raw_writel(0x0, base + 0x48);
+        __raw_writel(0x0, base + 0x4C);
+        reg = __raw_readl(base + 0x50) & 0x00FFFFFF;
+        __raw_writel(reg, base + 0x50);
+}
diff --git a/arch/arm/plat-mxc/devices/platform-ahci-imx.c b/arch/arm/plat-mxc/devices/platform-ahci-imx.c
index d8a56aee521..ade4a1c4e2a 100644
--- a/arch/arm/plat-mxc/devices/platform-ahci-imx.c
+++ b/arch/arm/plat-mxc/devices/platform-ahci-imx.c
@@ -60,9 +60,9 @@ static int imx_sata_init(struct device *dev, void __iomem *addr)
                 dev_err(dev, "no sata clock.\n");
                 return PTR_ERR(sata_clk);
         }
-        ret = clk_enable(sata_clk);
+        ret = clk_prepare_enable(sata_clk);
         if (ret) {
-                dev_err(dev, "can't enable sata clock.\n");
+                dev_err(dev, "can't prepare/enable sata clock.\n");
                 goto put_sata_clk;
         }
 
@@ -73,9 +73,9 @@ static int imx_sata_init(struct device *dev, void __iomem *addr)
                 ret = PTR_ERR(sata_ref_clk);
                 goto release_sata_clk;
         }
-        ret = clk_enable(sata_ref_clk);
+        ret = clk_prepare_enable(sata_ref_clk);
         if (ret) {
-                dev_err(dev, "can't enable sata ref clock.\n");
+                dev_err(dev, "can't prepare/enable sata ref clock.\n");
                 goto put_sata_ref_clk;
         }
 
@@ -104,11 +104,11 @@ static int imx_sata_init(struct device *dev, void __iomem *addr)
         return 0;
 
 release_sata_ref_clk:
-        clk_disable(sata_ref_clk);
+        clk_disable_unprepare(sata_ref_clk);
 put_sata_ref_clk:
         clk_put(sata_ref_clk);
 release_sata_clk:
-        clk_disable(sata_clk);
+        clk_disable_unprepare(sata_clk);
 put_sata_clk:
         clk_put(sata_clk);
 
@@ -117,10 +117,10 @@ put_sata_clk:
 
 static void imx_sata_exit(struct device *dev)
 {
-        clk_disable(sata_ref_clk);
+        clk_disable_unprepare(sata_ref_clk);
         clk_put(sata_ref_clk);
 
-        clk_disable(sata_clk);
+        clk_disable_unprepare(sata_clk);
         clk_put(sata_clk);
 
 }
diff --git a/arch/arm/plat-mxc/devices/platform-mx2-camera.c b/arch/arm/plat-mxc/devices/platform-mx2-camera.c
index b3f4828dc44..11eace953a0 100644
--- a/arch/arm/plat-mxc/devices/platform-mx2-camera.c
+++ b/arch/arm/plat-mxc/devices/platform-mx2-camera.c
@@ -62,3 +62,21 @@ struct platform_device *__init imx_add_mx2_camera(
                         res, data->iobaseemmaprp ? 4 : 2,
                         pdata, sizeof(*pdata), DMA_BIT_MASK(32));
 }
+
+struct platform_device *__init imx_add_mx2_emmaprp(
+                const struct imx_mx2_camera_data *data)
+{
+        struct resource res[] = {
+                {
+                        .start = data->iobaseemmaprp,
+                        .end = data->iobaseemmaprp + data->iosizeemmaprp - 1,
+                        .flags = IORESOURCE_MEM,
+                }, {
+                        .start = data->irqemmaprp,
+                        .end = data->irqemmaprp,
+                        .flags = IORESOURCE_IRQ,
+                },
+        };
+        return imx_add_platform_device_dmamask("m2m-emmaprp", 0,
+                        res, 2, NULL, 0, DMA_BIT_MASK(32));
+}
diff --git a/arch/arm/plat-mxc/epit.c b/arch/arm/plat-mxc/epit.c
index d3467f818c3..9129c9e7d53 100644
--- a/arch/arm/plat-mxc/epit.c
+++ b/arch/arm/plat-mxc/epit.c
@@ -203,7 +203,7 @@ static int __init epit_clockevent_init(struct clk *timer_clk)
 
 void __init epit_timer_init(struct clk *timer_clk, void __iomem *base, int irq)
 {
-        clk_enable(timer_clk);
+        clk_prepare_enable(timer_clk);
 
         timer_base = base;
 
diff --git a/arch/arm/plat-mxc/include/mach/audmux.h b/arch/arm/plat-mxc/include/mach/audmux.h
deleted file mode 100644
index 6fda788ed0e..00000000000
--- a/arch/arm/plat-mxc/include/mach/audmux.h
+++ /dev/null
@@ -1,60 +0,0 @@
-#ifndef __MACH_AUDMUX_H
-#define __MACH_AUDMUX_H
-
-#define MX27_AUDMUX_HPCR1_SSI0          0
-#define MX27_AUDMUX_HPCR2_SSI1          1
-#define MX27_AUDMUX_HPCR3_SSI_PINS_4    2
-#define MX27_AUDMUX_PPCR1_SSI_PINS_1    3
-#define MX27_AUDMUX_PPCR2_SSI_PINS_2    4
-#define MX27_AUDMUX_PPCR3_SSI_PINS_3    5
-
-#define MX31_AUDMUX_PORT1_SSI0          0
-#define MX31_AUDMUX_PORT2_SSI1          1
-#define MX31_AUDMUX_PORT3_SSI_PINS_3    2
-#define MX31_AUDMUX_PORT4_SSI_PINS_4    3
-#define MX31_AUDMUX_PORT5_SSI_PINS_5    4
-#define MX31_AUDMUX_PORT6_SSI_PINS_6    5
-
-#define MX51_AUDMUX_PORT1_SSI0          0
-#define MX51_AUDMUX_PORT2_SSI1          1
-#define MX51_AUDMUX_PORT3               2
-#define MX51_AUDMUX_PORT4               3
-#define MX51_AUDMUX_PORT5               4
-#define MX51_AUDMUX_PORT6               5
-#define MX51_AUDMUX_PORT7               6
-
-/* Register definitions for the i.MX21/27 Digital Audio Multiplexer */
-#define MXC_AUDMUX_V1_PCR_INMMASK(x)    ((x) & 0xff)
-#define MXC_AUDMUX_V1_PCR_INMEN         (1 << 8)
-#define MXC_AUDMUX_V1_PCR_TXRXEN        (1 << 10)
-#define MXC_AUDMUX_V1_PCR_SYN           (1 << 12)
-#define MXC_AUDMUX_V1_PCR_RXDSEL(x)     (((x) & 0x7) << 13)
-#define MXC_AUDMUX_V1_PCR_RFCSEL(x)     (((x) & 0xf) << 20)
-#define MXC_AUDMUX_V1_PCR_RCLKDIR       (1 << 24)
-#define MXC_AUDMUX_V1_PCR_RFSDIR        (1 << 25)
-#define MXC_AUDMUX_V1_PCR_TFCSEL(x)     (((x) & 0xf) << 26)
-#define MXC_AUDMUX_V1_PCR_TCLKDIR       (1 << 30)
-#define MXC_AUDMUX_V1_PCR_TFSDIR        (1 << 31)
-
-/* Register definitions for the i.MX25/31/35/51 Digital Audio Multiplexer */
-#define MXC_AUDMUX_V2_PTCR_TFSDIR       (1 << 31)
-#define MXC_AUDMUX_V2_PTCR_TFSEL(x)     (((x) & 0xf) << 27)
-#define MXC_AUDMUX_V2_PTCR_TCLKDIR      (1 << 26)
-#define MXC_AUDMUX_V2_PTCR_TCSEL(x)     (((x) & 0xf) << 22)
-#define MXC_AUDMUX_V2_PTCR_RFSDIR       (1 << 21)
-#define MXC_AUDMUX_V2_PTCR_RFSEL(x)     (((x) & 0xf) << 17)
-#define MXC_AUDMUX_V2_PTCR_RCLKDIR      (1 << 16)
-#define MXC_AUDMUX_V2_PTCR_RCSEL(x)     (((x) & 0xf) << 12)
-#define MXC_AUDMUX_V2_PTCR_SYN          (1 << 11)
-
-#define MXC_AUDMUX_V2_PDCR_RXDSEL(x)    (((x) & 0x7) << 13)
-#define MXC_AUDMUX_V2_PDCR_TXRXEN       (1 << 12)
-#define MXC_AUDMUX_V2_PDCR_MODE(x)      (((x) & 0x3) << 8)
-#define MXC_AUDMUX_V2_PDCR_INMMASK(x)   ((x) & 0xff)
-
-int mxc_audmux_v1_configure_port(unsigned int port, unsigned int pcr);
-
-int mxc_audmux_v2_configure_port(unsigned int port, unsigned int ptcr,
-                unsigned int pdcr);
-
-#endif /* __MACH_AUDMUX_H */
diff --git a/arch/arm/plat-mxc/include/mach/board-mx31ads.h b/arch/arm/plat-mxc/include/mach/board-mx31ads.h
deleted file mode 100644
index 94b60dd4713..00000000000
--- a/arch/arm/plat-mxc/include/mach/board-mx31ads.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/*
- * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
- */
-
-/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef __ASM_ARCH_MXC_BOARD_MX31ADS_H__
-#define __ASM_ARCH_MXC_BOARD_MX31ADS_H__
-
-#include <mach/hardware.h>
-
-/*
- * These symbols are used by drivers/net/cs89x0.c.
- * This is ugly as hell, but we have to provide them until
- * someone fixed the driver.
- */
-
-/* Base address of PBC controller */
-#define PBC_BASE_ADDRESS        MX31_CS4_BASE_ADDR_VIRT
-/* Offsets for the PBC Controller register */
-
-/* Ethernet Controller IO base address */
-#define PBC_CS8900A_IOBASE      0x020000
-
-#define MXC_EXP_IO_BASE         (MXC_BOARD_IRQ_START)
-
-#define EXPIO_INT_ENET_INT      (MXC_EXP_IO_BASE + 8)
-
-#endif /* __ASM_ARCH_MXC_BOARD_MX31ADS_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/common.h b/arch/arm/plat-mxc/include/mach/common.h
index 1bf0df81bdc..0319c4a0caf 100644
--- a/arch/arm/plat-mxc/include/mach/common.h
+++ b/arch/arm/plat-mxc/include/mach/common.h
@@ -65,6 +65,7 @@ extern int mx51_clocks_init(unsigned long ckil, unsigned long osc,
                         unsigned long ckih1, unsigned long ckih2);
 extern int mx53_clocks_init(unsigned long ckil, unsigned long osc,
                         unsigned long ckih1, unsigned long ckih2);
+extern int mx27_clocks_init_dt(void);
 extern int mx51_clocks_init_dt(void);
 extern int mx53_clocks_init_dt(void);
 extern int mx6q_clocks_init(void);
@@ -75,6 +76,7 @@ extern void mxc_restart(char, const char *);
 extern void mxc_arch_reset_init(void __iomem *);
 extern int mx53_revision(void);
 extern int mx53_display_revision(void);
+extern void imx_set_aips(void __iomem *);
 
 enum mxc_cpu_pwr_mode {
         WAIT_CLOCKED,           /* wfi only */
@@ -84,6 +86,14 @@ enum mxc_cpu_pwr_mode {
         STOP_POWER_OFF,         /* STOP + SRPG */
 };
 
+enum mx3_cpu_pwr_mode {
+        MX3_RUN,
+        MX3_WAIT,
+        MX3_DOZE,
+        MX3_SLEEP,
+};
+
+extern void mx3_cpu_lp_set(enum mx3_cpu_pwr_mode mode);
 extern void mx5_cpu_lp_set(enum mxc_cpu_pwr_mode mode);
 extern void imx_print_silicon_rev(const char *cpu, int srev);
 
diff --git a/arch/arm/plat-mxc/include/mach/debug-macro.S b/arch/arm/plat-mxc/include/mach/debug-macro.S
index 6e192c4a391..8ddda365f1a 100644
--- a/arch/arm/plat-mxc/include/mach/debug-macro.S
+++ b/arch/arm/plat-mxc/include/mach/debug-macro.S
@@ -24,7 +24,7 @@
 #define UART_PADDR      MX51_UART1_BASE_ADDR
 #elif defined (CONFIG_DEBUG_IMX50_IMX53_UART)
 #define UART_PADDR      MX53_UART1_BASE_ADDR
-#elif defined (CONFIG_DEBUG_IMX6Q_UART)
+#elif defined (CONFIG_DEBUG_IMX6Q_UART4)
 #define UART_PADDR      MX6Q_UART4_BASE_ADDR
 #endif
 
diff --git a/arch/arm/plat-mxc/include/mach/devices-common.h b/arch/arm/plat-mxc/include/mach/devices-common.h
index def9ba53e23..1b2258daa05 100644
--- a/arch/arm/plat-mxc/include/mach/devices-common.h
+++ b/arch/arm/plat-mxc/include/mach/devices-common.h
@@ -223,6 +223,8 @@ struct imx_mx2_camera_data {
 struct platform_device *__init imx_add_mx2_camera(
                 const struct imx_mx2_camera_data *data,
                 const struct mx2_camera_platform_data *pdata);
+struct platform_device *__init imx_add_mx2_emmaprp(
+                const struct imx_mx2_camera_data *data);
 
 #include <mach/mxc_ehci.h>
 struct imx_mxc_ehci_data {
diff --git a/arch/arm/plat-mxc/include/mach/dma.h b/arch/arm/plat-mxc/include/mach/dma.h
index 233d0a5e2d6..1b9080385b4 100644
--- a/arch/arm/plat-mxc/include/mach/dma.h
+++ b/arch/arm/plat-mxc/include/mach/dma.h
@@ -60,8 +60,7 @@ static inline int imx_dma_is_ipu(struct dma_chan *chan)
 
 static inline int imx_dma_is_general_purpose(struct dma_chan *chan)
 {
-        return !strcmp(dev_name(chan->device->dev), "imx31-sdma") ||
-                !strcmp(dev_name(chan->device->dev), "imx35-sdma") ||
+        return strstr(dev_name(chan->device->dev), "sdma") ||
                 !strcmp(dev_name(chan->device->dev), "imx-dma");
 }
 
diff --git a/arch/arm/plat-mxc/include/mach/entry-macro.S b/arch/arm/plat-mxc/include/mach/entry-macro.S
deleted file mode 100644
index def5d30cb67..00000000000
--- a/arch/arm/plat-mxc/include/mach/entry-macro.S
+++ /dev/null
@@ -1,16 +0,0 @@
-/*
- *  Copyright (C) 2007 Lennert Buytenhek <buytenh@wantstofly.org>
- *  Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved.
- */
-
-/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-        .macro  disable_fiq
-        .endm
-
-        .macro  arch_ret_to_user, tmp1, tmp2
-        .endm
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx25.h b/arch/arm/plat-mxc/include/mach/iomux-mx25.h
index f0726d48df2..c61ec0fc10d 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-mx25.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-mx25.h
@@ -139,15 +139,15 @@
 #define MX25_PAD_NFRB__GPIO_3_31        IOMUX_PAD(0x27c, 0x084, 0x15, 0, 0, NO_PAD_CTRL)
 
 #define MX25_PAD_D15__D15               IOMUX_PAD(0x280, 0x088, 0x00, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_D15__LD16              IOMUX_PAD(0x280, 0x088, 0x01, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_D15__LD16              IOMUX_PAD(0x280, 0x088, 0x01, 0, 0, PAD_CTL_SRE_FAST)
 #define MX25_PAD_D15__GPIO_4_5          IOMUX_PAD(0x280, 0x088, 0x05, 0, 0, NO_PAD_CTRL)
 
 #define MX25_PAD_D14__D14               IOMUX_PAD(0x284, 0x08c, 0x00, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_D14__LD17              IOMUX_PAD(0x284, 0x08c, 0x01, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_D14__LD17              IOMUX_PAD(0x284, 0x08c, 0x01, 0, 0, PAD_CTL_SRE_FAST)
 #define MX25_PAD_D14__GPIO_4_6          IOMUX_PAD(0x284, 0x08c, 0x05, 0, 0, NO_PAD_CTRL)
 
 #define MX25_PAD_D13__D13               IOMUX_PAD(0x288, 0x090, 0x00, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_D13__LD18              IOMUX_PAD(0x288, 0x090, 0x01, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_D13__LD18              IOMUX_PAD(0x288, 0x090, 0x01, 0, 0, PAD_CTL_SRE_FAST)
 #define MX25_PAD_D13__GPIO_4_7          IOMUX_PAD(0x288, 0x090, 0x05, 0, 0, NO_PAD_CTRL)
 
 #define MX25_PAD_D12__D12               IOMUX_PAD(0x28c, 0x094, 0x00, 0, 0, NO_PAD_CTRL)
@@ -192,54 +192,54 @@
 #define MX25_PAD_D0__D0                 IOMUX_PAD(0x2bc, 0x0c4, 0x00, 0, 0, NO_PAD_CTRL)
 #define MX25_PAD_D0__GPIO_4_20          IOMUX_PAD(0x2bc, 0x0c4, 0x05, 0, 0, NO_PAD_CTRL)
 
-#define MX25_PAD_LD0__LD0               IOMUX_PAD(0x2c0, 0x0c8, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_LD0__LD0               IOMUX_PAD(0x2c0, 0x0c8, 0x10, 0, 0, PAD_CTL_SRE_FAST)
 #define MX25_PAD_LD0__CSI_D0            IOMUX_PAD(0x2c0, 0x0c8, 0x12, 0x488, 0, NO_PAD_CTRL)
 #define MX25_PAD_LD0__GPIO_2_15         IOMUX_PAD(0x2c0, 0x0c8, 0x15, 0, 0, NO_PAD_CTRL)
 
-#define MX25_PAD_LD1__LD1               IOMUX_PAD(0x2c4, 0x0cc, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_LD1__LD1               IOMUX_PAD(0x2c4, 0x0cc, 0x10, 0, 0, PAD_CTL_SRE_FAST)
 #define MX25_PAD_LD1__CSI_D1            IOMUX_PAD(0x2c4, 0x0cc, 0x12, 0x48c, 0, NO_PAD_CTRL)
 #define MX25_PAD_LD1__GPIO_2_16         IOMUX_PAD(0x2c4, 0x0cc, 0x15, 0, 0, NO_PAD_CTRL)
 
-#define MX25_PAD_LD2__LD2               IOMUX_PAD(0x2c8, 0x0d0, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_LD2__LD2               IOMUX_PAD(0x2c8, 0x0d0, 0x10, 0, 0, PAD_CTL_SRE_FAST)
 #define MX25_PAD_LD2__GPIO_2_17         IOMUX_PAD(0x2c8, 0x0d0, 0x15, 0, 0, NO_PAD_CTRL)
 
-#define MX25_PAD_LD3__LD3               IOMUX_PAD(0x2cc, 0x0d4, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_LD3__LD3               IOMUX_PAD(0x2cc, 0x0d4, 0x10, 0, 0, PAD_CTL_SRE_FAST)
 #define MX25_PAD_LD3__GPIO_2_18         IOMUX_PAD(0x2cc, 0x0d4, 0x15, 0, 0, NO_PAD_CTRL)
 
-#define MX25_PAD_LD4__LD4               IOMUX_PAD(0x2d0, 0x0d8, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_LD4__LD4               IOMUX_PAD(0x2d0, 0x0d8, 0x10, 0, 0, PAD_CTL_SRE_FAST)
 #define MX25_PAD_LD4__GPIO_2_19         IOMUX_PAD(0x2d0, 0x0d8, 0x15, 0, 0, NO_PAD_CTRL)
 
-#define MX25_PAD_LD5__LD5               IOMUX_PAD(0x2d4, 0x0dc, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_LD5__LD5               IOMUX_PAD(0x2d4, 0x0dc, 0x10, 0, 0, PAD_CTL_SRE_FAST)
 #define MX25_PAD_LD5__GPIO_1_19         IOMUX_PAD(0x2d4, 0x0dc, 0x15, 0, 0, NO_PAD_CTRL)
 
-#define MX25_PAD_LD6__LD6               IOMUX_PAD(0x2d8, 0x0e0, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_LD6__LD6               IOMUX_PAD(0x2d8, 0x0e0, 0x10, 0, 0, PAD_CTL_SRE_FAST)
 #define MX25_PAD_LD6__GPIO_1_20         IOMUX_PAD(0x2d8, 0x0e0, 0x15, 0, 0, NO_PAD_CTRL)
 
-#define MX25_PAD_LD7__LD7               IOMUX_PAD(0x2dc, 0x0e4, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_LD7__LD7               IOMUX_PAD(0x2dc, 0x0e4, 0x10, 0, 0, PAD_CTL_SRE_FAST)
 #define MX25_PAD_LD7__GPIO_1_21         IOMUX_PAD(0x2dc, 0x0e4, 0x15, 0, 0, NO_PAD_CTRL)
 
-#define MX25_PAD_LD8__LD8               IOMUX_PAD(0x2e0, 0x0e8, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_LD8__LD8               IOMUX_PAD(0x2e0, 0x0e8, 0x10, 0, 0, PAD_CTL_SRE_FAST)
 #define MX25_PAD_LD8__FEC_TX_ERR        IOMUX_PAD(0x2e0, 0x0e8, 0x15, 0, 0, NO_PAD_CTRL)
 
-#define MX25_PAD_LD9__LD9               IOMUX_PAD(0x2e4, 0x0ec, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_LD9__LD9               IOMUX_PAD(0x2e4, 0x0ec, 0x10, 0, 0, PAD_CTL_SRE_FAST)
 #define MX25_PAD_LD9__FEC_COL           IOMUX_PAD(0x2e4, 0x0ec, 0x15, 0x504, 1, NO_PAD_CTRL)
 
-#define MX25_PAD_LD10__LD10             IOMUX_PAD(0x2e8, 0x0f0, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_LD10__LD10             IOMUX_PAD(0x2e8, 0x0f0, 0x10, 0, 0, PAD_CTL_SRE_FAST)
 #define MX25_PAD_LD10__FEC_RX_ER        IOMUX_PAD(0x2e8, 0x0f0, 0x15, 0x518, 1, NO_PAD_CTRL)
 
-#define MX25_PAD_LD11__LD11             IOMUX_PAD(0x2ec, 0x0f4, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_LD11__LD11             IOMUX_PAD(0x2ec, 0x0f4, 0x10, 0, 0, PAD_CTL_SRE_FAST)
 #define MX25_PAD_LD11__FEC_RDATA2       IOMUX_PAD(0x2ec, 0x0f4, 0x15, 0x50c, 1, NO_PAD_CTRL)
 
-#define MX25_PAD_LD12__LD12             IOMUX_PAD(0x2f0, 0x0f8, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_LD12__LD12             IOMUX_PAD(0x2f0, 0x0f8, 0x10, 0, 0, PAD_CTL_SRE_FAST)
 #define MX25_PAD_LD12__FEC_RDATA3       IOMUX_PAD(0x2f0, 0x0f8, 0x15, 0x510, 1, NO_PAD_CTRL)
 
-#define MX25_PAD_LD13__LD13             IOMUX_PAD(0x2f4, 0x0fc, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_LD13__LD13             IOMUX_PAD(0x2f4, 0x0fc, 0x10, 0, 0, PAD_CTL_SRE_FAST)
 #define MX25_PAD_LD13__FEC_TDATA2       IOMUX_PAD(0x2f4, 0x0fc, 0x15, 0, 0, NO_PAD_CTRL)
 
-#define MX25_PAD_LD14__LD14             IOMUX_PAD(0x2f8, 0x100, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_LD14__LD14             IOMUX_PAD(0x2f8, 0x100, 0x10, 0, 0, PAD_CTL_SRE_FAST)
 #define MX25_PAD_LD14__FEC_TDATA3       IOMUX_PAD(0x2f8, 0x100, 0x15, 0, 0, NO_PAD_CTRL)
 
-#define MX25_PAD_LD15__LD15             IOMUX_PAD(0x2fc, 0x104, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_LD15__LD15             IOMUX_PAD(0x2fc, 0x104, 0x10, 0, 0, PAD_CTL_SRE_FAST)
 #define MX25_PAD_LD15__FEC_RX_CLK       IOMUX_PAD(0x2fc, 0x104, 0x15, 0x514, 1, NO_PAD_CTRL)
 
 #define MX25_PAD_HSYNC__HSYNC           IOMUX_PAD(0x300, 0x108, 0x10, 0, 0, NO_PAD_CTRL)
@@ -468,11 +468,11 @@
 #define MX25_PAD_GPIO_C__CAN2_TX        IOMUX_PAD(0x3f8, 0x1fc, 0x16, 0, 0, PAD_CTL_PUS_22K_UP)
 
 #define MX25_PAD_GPIO_D__GPIO_D         IOMUX_PAD(0x3fc, 0x200, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_GPIO_E__LD16           IOMUX_PAD(0x400, 0x204, 0x02, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_GPIO_E__LD16           IOMUX_PAD(0x400, 0x204, 0x02, 0, 0, PAD_CTL_SRE_FAST)
 #define MX25_PAD_GPIO_D__CAN2_RX        IOMUX_PAD(0x3fc, 0x200, 0x16, 0x484, 1, PAD_CTL_PUS_22K_UP)
 
 #define MX25_PAD_GPIO_E__GPIO_E         IOMUX_PAD(0x400, 0x204, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_GPIO_F__LD17           IOMUX_PAD(0x404, 0x208, 0x02, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_GPIO_F__LD17           IOMUX_PAD(0x404, 0x208, 0x02, 0, 0, PAD_CTL_SRE_FAST)
 #define MX25_PAD_GPIO_E__AUD7_TXD       IOMUX_PAD(0x400, 0x204, 0x14, 0, 0, NO_PAD_CTRL)
 
 #define MX25_PAD_GPIO_F__GPIO_F         IOMUX_PAD(0x404, 0x208, 0x10, 0, 0, NO_PAD_CTRL)
diff --git a/arch/arm/plat-mxc/include/mach/system.h b/arch/arm/plat-mxc/include/mach/system.h
deleted file mode 100644
index 13ad0df2e86..00000000000
--- a/arch/arm/plat-mxc/include/mach/system.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- *  Copyright (C) 1999 ARM Limited
- *  Copyright (C) 2000 Deep Blue Solutions Ltd
- *  Copyright 2004-2008 Freescale Semiconductor, Inc. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#ifndef __ASM_ARCH_MXC_SYSTEM_H__
-#define __ASM_ARCH_MXC_SYSTEM_H__
-
-static inline void arch_idle(void)
-{
-        cpu_do_idle();
-}
-
-#endif /* __ASM_ARCH_MXC_SYSTEM_H__ */
diff --git a/arch/arm/plat-mxc/pwm.c b/arch/arm/plat-mxc/pwm.c
index e032717f7d0..c0cab2270dd 100644
--- a/arch/arm/plat-mxc/pwm.c
+++ b/arch/arm/plat-mxc/pwm.c
@@ -132,7 +132,7 @@ int pwm_enable(struct pwm_device *pwm)
         int rc = 0;
 
         if (!pwm->clk_enabled) {
-                rc = clk_enable(pwm->clk);
+                rc = clk_prepare_enable(pwm->clk);
                 if (!rc)
                         pwm->clk_enabled = 1;
         }
@@ -145,7 +145,7 @@ void pwm_disable(struct pwm_device *pwm)
         writel(0, pwm->mmio_base + MX3_PWMCR);
 
         if (pwm->clk_enabled) {
-                clk_disable(pwm->clk);
+                clk_disable_unprepare(pwm->clk);
                 pwm->clk_enabled = 0;
         }
 }
diff --git a/arch/arm/plat-mxc/system.c b/arch/arm/plat-mxc/system.c
index 3599bf2cfd4..f30dcacbbd0 100644
--- a/arch/arm/plat-mxc/system.c
+++ b/arch/arm/plat-mxc/system.c
@@ -48,7 +48,7 @@ void mxc_restart(char mode, const char *cmd)
 
                 clk = clk_get_sys("imx2-wdt.0", NULL);
                 if (!IS_ERR(clk))
-                        clk_enable(clk);
+                        clk_prepare_enable(clk);
                 wcr_enable = (1 << 2);
         }
 
diff --git a/arch/arm/plat-mxc/time.c b/arch/arm/plat-mxc/time.c
index 1c96cdb4c35..7daf7c9a413 100644
--- a/arch/arm/plat-mxc/time.c
+++ b/arch/arm/plat-mxc/time.c
@@ -283,7 +283,7 @@ void __init mxc_timer_init(struct clk *timer_clk, void __iomem *base, int irq)
 {
         uint32_t tctl_val;
 
-        clk_enable(timer_clk);
+        clk_prepare_enable(timer_clk);
 
         timer_base = base;
 
diff --git a/arch/arm/plat-nomadik/include/plat/mtu.h b/arch/arm/plat-nomadik/include/plat/mtu.h
index 6508e7694a4..582641f3dc0 100644
--- a/arch/arm/plat-nomadik/include/plat/mtu.h
+++ b/arch/arm/plat-nomadik/include/plat/mtu.h
@@ -1,9 +1,7 @@
 #ifndef __PLAT_MTU_H
 #define __PLAT_MTU_H
 
-/* should be set by the platform code */
-extern void __iomem *mtu_base;
-
+void nmdk_timer_init(void __iomem *base);
 void nmdk_clkevt_reset(void);
 void nmdk_clksrc_reset(void);
 
diff --git a/arch/arm/plat-nomadik/timer.c b/arch/arm/plat-nomadik/timer.c
index ad1b45b605a..9222e5522a4 100644
--- a/arch/arm/plat-nomadik/timer.c
+++ b/arch/arm/plat-nomadik/timer.c
@@ -21,12 +21,6 @@
 #include <asm/sched_clock.h>
 
 /*
- * Guaranteed runtime conversion range in seconds for
- * the clocksource and clockevent.
- */
-#define MTU_MIN_RANGE 4
-
-/*
  * The MTU device hosts four different counters, with 4 set of
  * registers. These are register names.
  */
@@ -66,12 +60,11 @@
 #define MTU_PCELL2      0xff8
 #define MTU_PCELL3      0xffC
 
+static void __iomem *mtu_base;
 static bool clkevt_periodic;
 static u32 clk_prescale;
 static u32 nmdk_cycle;          /* write-once */
 
-void __iomem *mtu_base; /* Assigned by machine code */
-
 #ifdef CONFIG_NOMADIK_MTU_SCHED_CLOCK
 /*
  * Override the global weak sched_clock symbol with this
@@ -103,7 +96,6 @@ static int nmdk_clkevt_next(unsigned long evt, struct clock_event_device *ev)
 void nmdk_clkevt_reset(void)
 {
         if (clkevt_periodic) {
-
                 /* Timer: configure load and background-load, and fire it up */
                 writel(nmdk_cycle, mtu_base + MTU_LR(1));
                 writel(nmdk_cycle, mtu_base + MTU_BGLR(1));
@@ -121,7 +113,6 @@ void nmdk_clkevt_reset(void)
 static void nmdk_clkevt_mode(enum clock_event_mode mode,
                              struct clock_event_device *dev)
 {
-
         switch (mode) {
         case CLOCK_EVT_MODE_PERIODIC:
                 clkevt_periodic = true;
@@ -183,15 +174,16 @@ void nmdk_clksrc_reset(void)
                mtu_base + MTU_CR(0));
 }
 
-void __init nmdk_timer_init(void)
+void __init nmdk_timer_init(void __iomem *base)
 {
         unsigned long rate;
         struct clk *clk0;
 
+        mtu_base = base;
         clk0 = clk_get_sys("mtu0", NULL);
         BUG_ON(IS_ERR(clk0));
-
-        clk_enable(clk0);
+        BUG_ON(clk_prepare(clk0) < 0);
+        BUG_ON(clk_enable(clk0) < 0);
 
         /*
          * Tick rate is 2.4MHz for Nomadik and 2.4Mhz, 100MHz or 133 MHz
@@ -224,17 +216,8 @@ void __init nmdk_timer_init(void)
         setup_sched_clock(nomadik_read_sched_clock, 32, rate);
 #endif
 
-        /* Timer 1 is used for events */
-
-        clockevents_calc_mult_shift(&nmdk_clkevt, rate, MTU_MIN_RANGE);
-
-        nmdk_clkevt.max_delta_ns =
-                clockevent_delta2ns(0xffffffff, &nmdk_clkevt);
-        nmdk_clkevt.min_delta_ns =
-                clockevent_delta2ns(0x00000002, &nmdk_clkevt);
-        nmdk_clkevt.cpumask     = cpumask_of(0);
-
-        /* Register irq and clockevents */
+        /* Timer 1 is used for events, register irq and clockevents */
         setup_irq(IRQ_MTU0, &nmdk_timer_irq);
-        clockevents_register_device(&nmdk_clkevt);
+        nmdk_clkevt.cpumask = cpumask_of(0);
+        clockevents_config_and_register(&nmdk_clkevt, rate, 2, 0xffffffffU);
 }
diff --git a/arch/arm/plat-omap/Kconfig b/arch/arm/plat-omap/Kconfig
index aa59f4247dc..ce1e9b96ba1 100644
--- a/arch/arm/plat-omap/Kconfig
+++ b/arch/arm/plat-omap/Kconfig
@@ -14,6 +14,7 @@ config ARCH_OMAP1
         select CLKDEV_LOOKUP
         select CLKSRC_MMIO
         select GENERIC_IRQ_CHIP
+        select IRQ_DOMAIN
         select HAVE_IDE
         select NEED_MACH_MEMORY_H
         help
@@ -24,6 +25,8 @@ config ARCH_OMAP2PLUS
         select CLKDEV_LOOKUP
         select GENERIC_IRQ_CHIP
         select OMAP_DM_TIMER
+        select USE_OF
+        select PROC_DEVICETREE if PROC_FS
         help
           "Systems based on OMAP2, OMAP3 or OMAP4"
 
@@ -110,14 +113,6 @@ config OMAP_MUX_WARNINGS
           to change the pin multiplexing setup.  When there are no warnings
           printed, it's safe to deselect OMAP_MUX for your product.
 
-config OMAP_MCBSP
-        bool "McBSP support"
-        depends on ARCH_OMAP
-        default y
-        help
-          Say Y here if you want support for the OMAP Multichannel
-          Buffered Serial Port.
-
 config OMAP_MBOX_FWK
         tristate "Mailbox framework support"
         depends on ARCH_OMAP
diff --git a/arch/arm/plat-omap/Makefile b/arch/arm/plat-omap/Makefile
index 9a584614e7e..c0fe2757b69 100644
--- a/arch/arm/plat-omap/Makefile
+++ b/arch/arm/plat-omap/Makefile
@@ -17,8 +17,6 @@ obj-$(CONFIG_ARCH_OMAP2) += omap_device.o
 obj-$(CONFIG_ARCH_OMAP3) += omap_device.o
 obj-$(CONFIG_ARCH_OMAP4) += omap_device.o
 
-obj-$(CONFIG_OMAP_MCBSP) += mcbsp.o
-
 obj-$(CONFIG_OMAP_DM_TIMER) += dmtimer.o
 obj-$(CONFIG_OMAP_DEBUG_DEVICES) += debug-devices.o
 obj-$(CONFIG_OMAP_DEBUG_LEDS) += debug-leds.o
diff --git a/arch/arm/plat-omap/clock.c b/arch/arm/plat-omap/clock.c
index 567e4b54f24..56b6f8b7053 100644
--- a/arch/arm/plat-omap/clock.c
+++ b/arch/arm/plat-omap/clock.c
@@ -20,7 +20,6 @@
 #include <linux/clk.h>
 #include <linux/mutex.h>
 #include <linux/cpufreq.h>
-#include <linux/debugfs.h>
 #include <linux/io.h>
 
 #include <plat/clock.h>
diff --git a/arch/arm/plat-omap/common.c b/arch/arm/plat-omap/common.c
index 4de7d1e79e7..f1e46ea6b81 100644
--- a/arch/arm/plat-omap/common.c
+++ b/arch/arm/plat-omap/common.c
@@ -15,7 +15,6 @@
 #include <linux/init.h>
 #include <linux/io.h>
 #include <linux/dma-mapping.h>
-#include <linux/omapfb.h>
 
 #include <plat/common.h>
 #include <plat/board.h>
@@ -65,7 +64,6 @@ const void *__init omap_get_var_config(u16 tag, size_t *len)
 
 void __init omap_reserve(void)
 {
-        omapfb_reserve_sdram_memblock();
         omap_vram_reserve_sdram_memblock();
         omap_dsp_reserve_sdram_memblock();
         omap_secure_ram_reserve_memblock();
diff --git a/arch/arm/plat-omap/counter_32k.c b/arch/arm/plat-omap/counter_32k.c
index 5f0f2292b7f..5068fe5a691 100644
--- a/arch/arm/plat-omap/counter_32k.c
+++ b/arch/arm/plat-omap/counter_32k.c
@@ -21,6 +21,7 @@
 
 #include <asm/sched_clock.h>
 
+#include <plat/hardware.h>
 #include <plat/common.h>
 #include <plat/board.h>
 
diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c
index 002fb4d96bb..74300ae29b7 100644
--- a/arch/arm/plat-omap/dma.c
+++ b/arch/arm/plat-omap/dma.c
@@ -164,6 +164,8 @@ static inline void set_gdma_dev(int req, int dev)
 }
 #else
 #define set_gdma_dev(req, dev)  do {} while (0)
+#define omap_readl(reg)         0
+#define omap_writel(val, reg)   do {} while (0)
 #endif
 
 void omap_set_dma_priority(int lch, int dst_port, int priority)
@@ -2125,7 +2127,7 @@ static int __devexit omap_system_dma_remove(struct platform_device *pdev)
 
 static struct platform_driver omap_system_dma_driver = {
         .probe          = omap_system_dma_probe,
-        .remove         = omap_system_dma_remove,
+        .remove         = __devexit_p(omap_system_dma_remove),
         .driver         = {
                 .name   = "omap_dma_system"
         },
diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c
index af3b92be845..652139c0339 100644
--- a/arch/arm/plat-omap/dmtimer.c
+++ b/arch/arm/plat-omap/dmtimer.c
@@ -43,6 +43,8 @@
 
 #include <plat/dmtimer.h>
 
+#include <mach/hardware.h>
+
 static LIST_HEAD(omap_timer_list);
 static DEFINE_SPINLOCK(dm_timer_lock);
 
@@ -80,9 +82,9 @@ static void omap_dm_timer_write_reg(struct omap_dm_timer *timer, u32 reg,
 
 static void omap_timer_restore_context(struct omap_dm_timer *timer)
 {
-        omap_dm_timer_write_reg(timer, OMAP_TIMER_OCP_CFG_OFFSET,
-                                timer->context.tiocp_cfg);
-        if (timer->revision > 1)
+        __raw_writel(timer->context.tiocp_cfg,
+                        timer->io_base + OMAP_TIMER_OCP_CFG_OFFSET);
+        if (timer->revision == 1)
                 __raw_writel(timer->context.tistat, timer->sys_stat);
 
         __raw_writel(timer->context.tisr, timer->irq_stat);
@@ -357,6 +359,19 @@ int omap_dm_timer_stop(struct omap_dm_timer *timer)
 
         __omap_dm_timer_stop(timer, timer->posted, rate);
 
+        if (timer->loses_context && timer->get_context_loss_count)
+                timer->ctx_loss_count =
+                        timer->get_context_loss_count(&timer->pdev->dev);
+
+        /*
+         * Since the register values are computed and written within
+         * __omap_dm_timer_stop, we need to use read to retrieve the
+         * context.
+         */
+        timer->context.tclr =
+                        omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
+        timer->context.tisr = __raw_readl(timer->irq_stat);
+        omap_dm_timer_disable(timer);
         return 0;
 }
 EXPORT_SYMBOL_GPL(omap_dm_timer_stop);
diff --git a/arch/arm/plat-omap/fb.c b/arch/arm/plat-omap/fb.c
index c9e5d7298c4..dd6f92c99e5 100644
--- a/arch/arm/plat-omap/fb.c
+++ b/arch/arm/plat-omap/fb.c
@@ -34,15 +34,11 @@
 #include <asm/mach/map.h>
 
 #include <plat/board.h>
-#include <plat/sram.h>
-
-#include "fb.h"
 
 #if defined(CONFIG_FB_OMAP) || defined(CONFIG_FB_OMAP_MODULE)
 
+static bool omapfb_lcd_configured;
 static struct omapfb_platform_data omapfb_config;
-static int config_invalid;
-static int configured_regions;
 
 static u64 omap_fb_dma_mask = ~(u32)0;
 
@@ -57,302 +53,21 @@ static struct platform_device omap_fb_device = {
         .num_resources = 0,
 };
 
-void omapfb_set_platform_data(struct omapfb_platform_data *data)
-{
-}
-
-static inline int ranges_overlap(unsigned long start1, unsigned long size1,
-                                 unsigned long start2, unsigned long size2)
-{
-        return (start1 >= start2 && start1 < start2 + size2) ||
-               (start2 >= start1 && start2 < start1 + size1);
-}
-
-static inline int range_included(unsigned long start1, unsigned long size1,
-                                 unsigned long start2, unsigned long size2)
-{
-        return start1 >= start2 && start1 + size1 <= start2 + size2;
-}
-
-
-/* Check if there is an overlapping region. */
-static int fbmem_region_reserved(unsigned long start, size_t size)
-{
-        struct omapfb_mem_region *rg;
-        int i;
-
-        rg = &omapfb_config.mem_desc.region[0];
-        for (i = 0; i < OMAPFB_PLANE_NUM; i++, rg++) {
-                if (!rg->paddr)
-                        /* Empty slot. */
-                        continue;
-                if (ranges_overlap(start, size, rg->paddr, rg->size))
-                        return 1;
-        }
-        return 0;
-}
-
-/*
- * Get the region_idx`th region from board config/ATAG and convert it to
- * our internal format.
- */
-static int __init get_fbmem_region(int region_idx, struct omapfb_mem_region *rg)
+void __init omapfb_set_lcd_config(const struct omap_lcd_config *config)
 {
-        const struct omap_fbmem_config  *conf;
-        u32                             paddr;
-
-        conf = omap_get_nr_config(OMAP_TAG_FBMEM,
-                                  struct omap_fbmem_config, region_idx);
-        if (conf == NULL)
-                return -ENOENT;
-
-        paddr = conf->start;
-        /*
-         * Low bits encode the page allocation mode, if high bits
-         * are zero. Otherwise we need a page aligned fixed
-         * address.
-         */
-        memset(rg, 0, sizeof(*rg));
-        rg->type = paddr & ~PAGE_MASK;
-        rg->paddr = paddr & PAGE_MASK;
-        rg->size = PAGE_ALIGN(conf->size);
-        return 0;
+        omapfb_config.lcd = *config;
+        omapfb_lcd_configured = true;
 }
 
-static int set_fbmem_region_type(struct omapfb_mem_region *rg, int mem_type,
-                                  unsigned long mem_start,
-                                  unsigned long mem_size)
-{
-        /*
-         * Check if the configuration specifies the type explicitly.
-         * type = 0 && paddr = 0, a default don't care case maps to
-         * the SDRAM type.
-         */
-        if (rg->type || !rg->paddr)
-                return 0;
-        if (ranges_overlap(rg->paddr, rg->size, mem_start, mem_size)) {
-                rg->type = mem_type;
-                return 0;
-        }
-        /* Can't determine it. */
-        return -1;
-}
-
-static int check_fbmem_region(int region_idx, struct omapfb_mem_region *rg,
-                              unsigned long start_avail, unsigned size_avail)
+static int __init omap_init_fb(void)
 {
-        unsigned long   paddr = rg->paddr;
-        size_t          size = rg->size;
-
-        if (rg->type > OMAPFB_MEMTYPE_MAX) {
-                printk(KERN_ERR
-                        "Invalid start address for FB region %d\n", region_idx);
-                return -EINVAL;
-        }
-
-        if (!rg->size) {
-                printk(KERN_ERR "Zero size for FB region %d\n", region_idx);
-                return -EINVAL;
-        }
-
-        if (!paddr)
-                /* Allocate this dynamically, leave paddr 0 for now. */
-                return 0;
-
         /*
-         * Fixed region for the given RAM range. Check if it's already
-         * reserved by the FB code or someone else.
+         * If the board file has not set the lcd config with
+         * omapfb_set_lcd_config(), don't bother registering the omapfb device
          */
-        if (fbmem_region_reserved(paddr, size) ||
-            !range_included(paddr, size, start_avail, size_avail)) {
-                printk(KERN_ERR "Trying to use reserved memory "
-                        "for FB region %d\n", region_idx);
-                return -EINVAL;
-        }
-
-        return 0;
-}
-
-static int valid_sdram(unsigned long addr, unsigned long size)
-{
-        return memblock_is_region_memory(addr, size);
-}
-
-static int reserve_sdram(unsigned long addr, unsigned long size)
-{
-        if (memblock_is_region_reserved(addr, size))
-                return -EBUSY;
-        if (memblock_reserve(addr, size))
-                return -ENOMEM;
-        return 0;
-}
-
-/*
- * Called from map_io. We need to call to this early enough so that we
- * can reserve the fixed SDRAM regions before VM could get hold of them.
- */
-void __init omapfb_reserve_sdram_memblock(void)
-{
-        unsigned long reserved = 0;
-        int i;
-
-        if (config_invalid)
-                return;
-
-        for (i = 0; ; i++) {
-                struct omapfb_mem_region rg;
-
-                if (get_fbmem_region(i, &rg) < 0)
-                        break;
-
-                if (i == OMAPFB_PLANE_NUM) {
-                        pr_err("Extraneous FB mem configuration entries\n");
-                        config_invalid = 1;
-                        return;
-                }
-
-                /* Check if it's our memory type. */
-                if (rg.type != OMAPFB_MEMTYPE_SDRAM)
-                        continue;
-
-                /* Check if the region falls within SDRAM */
-                if (rg.paddr && !valid_sdram(rg.paddr, rg.size))
-                        continue;
-
-                if (rg.size == 0) {
-                        pr_err("Zero size for FB region %d\n", i);
-                        config_invalid = 1;
-                        return;
-                }
-
-                if (rg.paddr) {
-                        if (reserve_sdram(rg.paddr, rg.size)) {
-                                pr_err("Trying to use reserved memory for FB region %d\n",
-                                        i);
-                                config_invalid = 1;
-                                return;
-                        }
-                        reserved += rg.size;
-                }
-
-                if (omapfb_config.mem_desc.region[i].size) {
-                        pr_err("FB region %d already set\n", i);
-                        config_invalid = 1;
-                        return;
-                }
-
-                omapfb_config.mem_desc.region[i] = rg;
-                configured_regions++;
-        }
-        omapfb_config.mem_desc.region_cnt = i;
-        if (reserved)
-                pr_info("Reserving %lu bytes SDRAM for frame buffer\n",
-                         reserved);
-}
-
-/*
- * Called at sram init time, before anything is pushed to the SRAM stack.
- * Because of the stack scheme, we will allocate everything from the
- * start of the lowest address region to the end of SRAM. This will also
- * include padding for page alignment and possible holes between regions.
- *
- * As opposed to the SDRAM case, we'll also do any dynamic allocations at
- * this point, since the driver built as a module would have problem with
- * freeing / reallocating the regions.
- */
-unsigned long __init omapfb_reserve_sram(unsigned long sram_pstart,
-                                  unsigned long sram_vstart,
-                                  unsigned long sram_size,
-                                  unsigned long pstart_avail,
-                                  unsigned long size_avail)
-{
-        struct omapfb_mem_region        rg;
-        unsigned long                   pend_avail;
-        unsigned long                   reserved;
-        int                             i;
-
-        if (config_invalid)
+        if (!omapfb_lcd_configured)
                 return 0;
 
-        reserved = 0;
-        pend_avail = pstart_avail + size_avail;
-        for (i = 0; ; i++) {
-                if (get_fbmem_region(i, &rg) < 0)
-                        break;
-                if (i == OMAPFB_PLANE_NUM) {
-                        printk(KERN_ERR
-                                "Extraneous FB mem configuration entries\n");
-                        config_invalid = 1;
-                        return 0;
-                }
-
-                /* Check if it's our memory type. */
-                if (set_fbmem_region_type(&rg, OMAPFB_MEMTYPE_SRAM,
-                                          sram_pstart, sram_size) < 0 ||
-                    (rg.type != OMAPFB_MEMTYPE_SRAM))
-                        continue;
-                BUG_ON(omapfb_config.mem_desc.region[i].size);
-
-                if (check_fbmem_region(i, &rg, pstart_avail, size_avail) < 0) {
-                        config_invalid = 1;
-                        return 0;
-                }
-
-                if (!rg.paddr) {
-                        /* Dynamic allocation */
-                        if ((size_avail & PAGE_MASK) < rg.size) {
-                                printk("Not enough SRAM for FB region %d\n",
-                                        i);
-                                config_invalid = 1;
-                                return 0;
-                        }
-                        size_avail = (size_avail - rg.size) & PAGE_MASK;
-                        rg.paddr = pstart_avail + size_avail;
-                }
-                /* Reserve everything above the start of the region. */
-                if (pend_avail - rg.paddr > reserved)
-                        reserved = pend_avail - rg.paddr;
-                size_avail = pend_avail - reserved - pstart_avail;
-
-                /*
-                 * We have a kernel mapping for this already, so the
-                 * driver won't have to make one.
-                 */
-                rg.vaddr = (void *)(sram_vstart + rg.paddr - sram_pstart);
-                omapfb_config.mem_desc.region[i] = rg;
-                configured_regions++;
-        }
-        omapfb_config.mem_desc.region_cnt = i;
-        if (reserved)
-                pr_info("Reserving %lu bytes SRAM for frame buffer\n",
-                         reserved);
-        return reserved;
-}
-
-void omapfb_set_ctrl_platform_data(void *data)
-{
-        omapfb_config.ctrl_platform_data = data;
-}
-
-static int __init omap_init_fb(void)
-{
-        const struct omap_lcd_config *conf;
-
-        if (config_invalid)
-                return 0;
-        if (configured_regions != omapfb_config.mem_desc.region_cnt) {
-                printk(KERN_ERR "Invalid FB mem configuration entries\n");
-                return 0;
-        }
-        conf = omap_get_config(OMAP_TAG_LCD, struct omap_lcd_config);
-        if (conf == NULL) {
-                if (configured_regions)
-                        /* FB mem config, but no LCD config? */
-                        printk(KERN_ERR "Missing LCD configuration\n");
-                return 0;
-        }
-        omapfb_config.lcd = *conf;
-
         return platform_device_register(&omap_fb_device);
 }
 
@@ -374,11 +89,6 @@ static struct platform_device omap_fb_device = {
         .num_resources = 0,
 };
 
-void omapfb_set_platform_data(struct omapfb_platform_data *data)
-{
-        omapfb_config = *data;
-}
-
 static int __init omap_init_fb(void)
 {
         return platform_device_register(&omap_fb_device);
@@ -386,36 +96,10 @@ static int __init omap_init_fb(void)
 
 arch_initcall(omap_init_fb);
 
-void omapfb_reserve_sdram_memblock(void)
-{
-}
-
-unsigned long __init omapfb_reserve_sram(unsigned long sram_pstart,
-                                  unsigned long sram_vstart,
-                                  unsigned long sram_size,
-                                  unsigned long start_avail,
-                                  unsigned long size_avail)
-{
-        return 0;
-}
-
 #else
 
-void omapfb_set_platform_data(struct omapfb_platform_data *data)
-{
-}
-
-void omapfb_reserve_sdram_memblock(void)
-{
-}
-
-unsigned long __init omapfb_reserve_sram(unsigned long sram_pstart,
-                                  unsigned long sram_vstart,
-                                  unsigned long sram_size,
-                                  unsigned long start_avail,
-                                  unsigned long size_avail)
+void __init omapfb_set_lcd_config(const struct omap_lcd_config *config)
 {
-        return 0;
 }
 
 #endif
diff --git a/arch/arm/plat-omap/fb.h b/arch/arm/plat-omap/fb.h
deleted file mode 100644
index d765d0bd852..00000000000
--- a/arch/arm/plat-omap/fb.h
+++ /dev/null
@@ -1,10 +0,0 @@
-#ifndef __PLAT_OMAP_FB_H__
-#define __PLAT_OMAP_FB_H__
-
-extern unsigned long omapfb_reserve_sram(unsigned long sram_pstart,
-                                         unsigned long sram_vstart,
-                                         unsigned long sram_size,
-                                         unsigned long pstart_avail,
-                                         unsigned long size_avail);
-
-#endif /* __PLAT_OMAP_FB_H__ */
diff --git a/arch/arm/plat-omap/include/plat/blizzard.h b/arch/arm/plat-omap/include/plat/blizzard.h
deleted file mode 100644
index 56e7f2e7d12..00000000000
--- a/arch/arm/plat-omap/include/plat/blizzard.h
+++ /dev/null
@@ -1,12 +0,0 @@
-#ifndef _BLIZZARD_H
-#define _BLIZZARD_H
-
-struct blizzard_platform_data {
-        void            (*power_up)(struct device *dev);
-        void            (*power_down)(struct device *dev);
-        unsigned long   (*get_clock_rate)(struct device *dev);
-
-        unsigned        te_connected:1;
-};
-
-#endif
diff --git a/arch/arm/plat-omap/include/plat/board-ams-delta.h b/arch/arm/plat-omap/include/plat/board-ams-delta.h
index 51b102dc906..ad6f865d1f1 100644
--- a/arch/arm/plat-omap/include/plat/board-ams-delta.h
+++ b/arch/arm/plat-omap/include/plat/board-ams-delta.h
@@ -28,33 +28,8 @@
 
 #if defined (CONFIG_MACH_AMS_DELTA)
 
-#define AMS_DELTA_LATCH1_PHYS           0x01000000
-#define AMS_DELTA_LATCH1_VIRT           0xEA000000
-#define AMS_DELTA_MODEM_PHYS            0x04000000
-#define AMS_DELTA_MODEM_VIRT            0xEB000000
-#define AMS_DELTA_LATCH2_PHYS           0x08000000
-#define AMS_DELTA_LATCH2_VIRT           0xEC000000
-
-#define AMS_DELTA_LATCH1_LED_CAMERA     0x01
-#define AMS_DELTA_LATCH1_LED_ADVERT     0x02
-#define AMS_DELTA_LATCH1_LED_EMAIL      0x04
-#define AMS_DELTA_LATCH1_LED_HANDSFREE  0x08
-#define AMS_DELTA_LATCH1_LED_VOICEMAIL  0x10
-#define AMS_DELTA_LATCH1_LED_VOICE      0x20
-
-#define AMS_DELTA_LATCH2_LCD_VBLEN      0x0001
-#define AMS_DELTA_LATCH2_LCD_NDISP      0x0002
-#define AMS_DELTA_LATCH2_NAND_NCE       0x0004
-#define AMS_DELTA_LATCH2_NAND_NRE       0x0008
-#define AMS_DELTA_LATCH2_NAND_NWP       0x0010
-#define AMS_DELTA_LATCH2_NAND_NWE       0x0020
-#define AMS_DELTA_LATCH2_NAND_ALE       0x0040
-#define AMS_DELTA_LATCH2_NAND_CLE       0x0080
-#define AMD_DELTA_LATCH2_KEYBRD_PWR     0x0100
-#define AMD_DELTA_LATCH2_KEYBRD_DATA    0x0200
 #define AMD_DELTA_LATCH2_SCARD_RSTIN    0x0400
 #define AMD_DELTA_LATCH2_SCARD_CMDVCC   0x0800
-#define AMS_DELTA_LATCH2_MODEM_NRESET   0x1000
 #define AMS_DELTA_LATCH2_MODEM_CODEC    0x2000
 
 #define AMS_DELTA_GPIO_PIN_KEYBRD_DATA  0
@@ -66,9 +41,29 @@
 #define AMS_DELTA_GPIO_PIN_CONFIG       11
 #define AMS_DELTA_GPIO_PIN_NAND_RB      12
 
+#define AMS_DELTA_GPIO_PIN_LCD_VBLEN            240
+#define AMS_DELTA_GPIO_PIN_LCD_NDISP            241
+#define AMS_DELTA_GPIO_PIN_NAND_NCE             242
+#define AMS_DELTA_GPIO_PIN_NAND_NRE             243
+#define AMS_DELTA_GPIO_PIN_NAND_NWP             244
+#define AMS_DELTA_GPIO_PIN_NAND_NWE             245
+#define AMS_DELTA_GPIO_PIN_NAND_ALE             246
+#define AMS_DELTA_GPIO_PIN_NAND_CLE             247
+#define AMS_DELTA_GPIO_PIN_KEYBRD_PWR           248
+#define AMS_DELTA_GPIO_PIN_KEYBRD_DATAOUT       249
+#define AMS_DELTA_GPIO_PIN_SCARD_RSTIN          250
+#define AMS_DELTA_GPIO_PIN_SCARD_CMDVCC         251
+#define AMS_DELTA_GPIO_PIN_MODEM_NRESET         252
+#define AMS_DELTA_GPIO_PIN_MODEM_CODEC          253
+
+#define AMS_DELTA_LATCH2_GPIO_BASE      AMS_DELTA_GPIO_PIN_LCD_VBLEN
+#define AMS_DELTA_LATCH2_NGPIO          16
+
 #ifndef __ASSEMBLY__
-void ams_delta_latch1_write(u8 mask, u8 value);
-void ams_delta_latch2_write(u16 mask, u16 value);
+void ams_delta_latch_write(int base, int ngpio, u16 mask, u16 value);
+#define ams_delta_latch2_write(mask, value) \
+        ams_delta_latch_write(AMS_DELTA_LATCH2_GPIO_BASE, \
+                        AMS_DELTA_LATCH2_NGPIO, (mask), (value))
 #endif
 
 #endif /* CONFIG_MACH_AMS_DELTA */
diff --git a/arch/arm/plat-omap/include/plat/board.h b/arch/arm/plat-omap/include/plat/board.h
index 97126dfd288..d5eb4c87db9 100644
--- a/arch/arm/plat-omap/include/plat/board.h
+++ b/arch/arm/plat-omap/include/plat/board.h
@@ -28,9 +28,7 @@ enum {
 
 /* Different peripheral ids */
 #define OMAP_TAG_CLOCK          0x4f01
-#define OMAP_TAG_LCD            0x4f05
 #define OMAP_TAG_GPIO_SWITCH    0x4f06
-#define OMAP_TAG_FBMEM          0x4f08
 #define OMAP_TAG_STI_CONSOLE    0x4f09
 #define OMAP_TAG_CAMERA_SENSOR  0x4f0a
 
diff --git a/arch/arm/plat-omap/include/plat/cpu.h b/arch/arm/plat-omap/include/plat/cpu.h
index 6b51086fce1..dc6a86bf217 100644
--- a/arch/arm/plat-omap/include/plat/cpu.h
+++ b/arch/arm/plat-omap/include/plat/cpu.h
@@ -250,7 +250,6 @@ IS_AM_SUBCLASS(335x, 0x335)
  * cpu_is_omap2423():   True for OMAP2423
  * cpu_is_omap2430():   True for OMAP2430
  * cpu_is_omap3430():   True for OMAP3430
- * cpu_is_omap4430():   True for OMAP4430
  * cpu_is_omap3505():   True for OMAP3505
  * cpu_is_omap3517():   True for OMAP3517
  */
@@ -299,7 +298,6 @@ IS_OMAP_TYPE(3517, 0x3517)
 #define cpu_is_omap3505()               0
 #define cpu_is_omap3517()               0
 #define cpu_is_omap3430()               0
-#define cpu_is_omap4430()               0
 #define cpu_is_omap3630()               0
 
 /*
@@ -451,7 +449,12 @@ IS_OMAP_TYPE(3517, 0x3517)
 #define OMAP447X_CLASS          0x44700044
 #define OMAP4470_REV_ES1_0      (OMAP447X_CLASS | (0x10 << 8))
 
-void omap2_check_revision(void);
+void omap2xxx_check_revision(void);
+void omap3xxx_check_revision(void);
+void omap4xxx_check_revision(void);
+void omap3xxx_check_features(void);
+void ti81xx_check_features(void);
+void omap4xxx_check_features(void);
 
 /*
  * Runtime detection of OMAP3 features
diff --git a/arch/arm/plat-omap/include/plat/gpio.h b/arch/arm/plat-omap/include/plat/gpio.h
index 9e86ee0aed0..cb75b657b04 100644
--- a/arch/arm/plat-omap/include/plat/gpio.h
+++ b/arch/arm/plat-omap/include/plat/gpio.h
@@ -162,13 +162,6 @@
                                  IH_MPUIO_BASE + ((nr) & 0x0f) : \
                                  IH_GPIO_BASE + (nr))
 
-#define METHOD_MPUIO            0
-#define METHOD_GPIO_1510        1
-#define METHOD_GPIO_1610        2
-#define METHOD_GPIO_7XX         3
-#define METHOD_GPIO_24XX        5
-#define METHOD_GPIO_44XX        6
-
 struct omap_gpio_dev_attr {
         int bank_width;         /* GPIO bank width */
         bool dbck_flag;         /* dbck required or not - True for OMAP3&4 */
@@ -184,10 +177,21 @@ struct omap_gpio_reg_offs {
         u16 irqstatus;
         u16 irqstatus2;
         u16 irqenable;
+        u16 irqenable2;
         u16 set_irqenable;
         u16 clr_irqenable;
         u16 debounce;
         u16 debounce_en;
+        u16 ctrl;
+        u16 wkup_en;
+        u16 leveldetect0;
+        u16 leveldetect1;
+        u16 risingdetect;
+        u16 fallingdetect;
+        u16 irqctrl;
+        u16 edgectrl1;
+        u16 edgectrl2;
+        u16 pinctrl;
 
         bool irqenable_inv;
 };
@@ -198,19 +202,20 @@ struct omap_gpio_platform_data {
         int bank_width;         /* GPIO bank width */
         int bank_stride;        /* Only needed for omap1 MPUIO */
         bool dbck_flag;         /* dbck required or not - True for OMAP3&4 */
+        bool loses_context;     /* whether the bank would ever lose context */
+        bool is_mpuio;          /* whether the bank is of type MPUIO */
+        u32 non_wakeup_gpios;
 
         struct omap_gpio_reg_offs *regs;
-};
 
-/* TODO: Analyze removing gpio_bank_count usage from driver code */
-extern int gpio_bank_count;
+        /* Return context loss count due to PM states changing */
+        int (*get_context_loss_count)(struct device *dev);
+};
 
 extern void omap2_gpio_prepare_for_idle(int off_mode);
 extern void omap2_gpio_resume_after_idle(void);
 extern void omap_set_gpio_debounce(int gpio, int enable);
 extern void omap_set_gpio_debounce_time(int gpio, int enable);
-extern void omap_gpio_save_context(void);
-extern void omap_gpio_restore_context(void);
 /*-------------------------------------------------------------------------*/
 
 /* Wrappers for "new style" GPIO calls, using the new infrastructure
diff --git a/arch/arm/plat-omap/include/plat/hardware.h b/arch/arm/plat-omap/include/plat/hardware.h
index e897978371c..537b05ae1f5 100644
--- a/arch/arm/plat-omap/include/plat/hardware.h
+++ b/arch/arm/plat-omap/include/plat/hardware.h
@@ -43,6 +43,12 @@
 #endif
 #include <plat/serial.h>
 
+#ifdef __ASSEMBLER__
+#define IOMEM(x)                (x)
+#else
+#define IOMEM(x)                ((void __force __iomem *)(x))
+#endif
+
 /*
  * ---------------------------------------------------------------------------
  * Common definitions for all OMAP processors
diff --git a/arch/arm/plat-omap/include/plat/hwa742.h b/arch/arm/plat-omap/include/plat/hwa742.h
deleted file mode 100644
index 886248d32b4..00000000000
--- a/arch/arm/plat-omap/include/plat/hwa742.h
+++ /dev/null
@@ -1,8 +0,0 @@
-#ifndef _HWA742_H
-#define _HWA742_H
-
-struct hwa742_platform_data {
-        unsigned        te_connected:1;
-};
-
-#endif
diff --git a/arch/arm/plat-omap/include/plat/keypad.h b/arch/arm/plat-omap/include/plat/keypad.h
index 793ce9d5329..a6b21eddb21 100644
--- a/arch/arm/plat-omap/include/plat/keypad.h
+++ b/arch/arm/plat-omap/include/plat/keypad.h
@@ -12,6 +12,8 @@
 
 #ifndef CONFIG_ARCH_OMAP1
 #warning Please update the board to use matrix-keypad driver
+#define omap_readw(reg)         0
+#define omap_writew(val, reg)   do {} while (0)
 #endif
 #include <linux/input/matrix_keypad.h>
 
diff --git a/arch/arm/plat-omap/include/plat/mcbsp.h b/arch/arm/plat-omap/include/plat/mcbsp.h
index 8fa74e2c9d6..18814127809 100644
--- a/arch/arm/plat-omap/include/plat/mcbsp.h
+++ b/arch/arm/plat-omap/include/plat/mcbsp.h
@@ -27,271 +27,10 @@
 #include <linux/spinlock.h>
 #include <linux/clk.h>
 
-/* macro for building platform_device for McBSP ports */
-#define OMAP_MCBSP_PLATFORM_DEVICE(port_nr)             \
-static struct platform_device omap_mcbsp##port_nr = {   \
-        .name   = "omap-mcbsp-dai",                     \
-        .id     = port_nr - 1,                  \
-}
-
 #define MCBSP_CONFIG_TYPE2      0x2
 #define MCBSP_CONFIG_TYPE3      0x3
 #define MCBSP_CONFIG_TYPE4      0x4
 
-/* McBSP register numbers. Register address offset = num * reg_step */
-enum {
-        /* Common registers */
-        OMAP_MCBSP_REG_SPCR2 = 4,
-        OMAP_MCBSP_REG_SPCR1,
-        OMAP_MCBSP_REG_RCR2,
-        OMAP_MCBSP_REG_RCR1,
-        OMAP_MCBSP_REG_XCR2,
-        OMAP_MCBSP_REG_XCR1,
-        OMAP_MCBSP_REG_SRGR2,
-        OMAP_MCBSP_REG_SRGR1,
-        OMAP_MCBSP_REG_MCR2,
-        OMAP_MCBSP_REG_MCR1,
-        OMAP_MCBSP_REG_RCERA,
-        OMAP_MCBSP_REG_RCERB,
-        OMAP_MCBSP_REG_XCERA,
-        OMAP_MCBSP_REG_XCERB,
-        OMAP_MCBSP_REG_PCR0,
-        OMAP_MCBSP_REG_RCERC,
-        OMAP_MCBSP_REG_RCERD,
-        OMAP_MCBSP_REG_XCERC,
-        OMAP_MCBSP_REG_XCERD,
-        OMAP_MCBSP_REG_RCERE,
-        OMAP_MCBSP_REG_RCERF,
-        OMAP_MCBSP_REG_XCERE,
-        OMAP_MCBSP_REG_XCERF,
-        OMAP_MCBSP_REG_RCERG,
-        OMAP_MCBSP_REG_RCERH,
-        OMAP_MCBSP_REG_XCERG,
-        OMAP_MCBSP_REG_XCERH,
-
-        /* OMAP1-OMAP2420 registers */
-        OMAP_MCBSP_REG_DRR2 = 0,
-        OMAP_MCBSP_REG_DRR1,
-        OMAP_MCBSP_REG_DXR2,
-        OMAP_MCBSP_REG_DXR1,
-
-        /* OMAP2430 and onwards */
-        OMAP_MCBSP_REG_DRR = 0,
-        OMAP_MCBSP_REG_DXR = 2,
-        OMAP_MCBSP_REG_SYSCON = 35,
-        OMAP_MCBSP_REG_THRSH2,
-        OMAP_MCBSP_REG_THRSH1,
-        OMAP_MCBSP_REG_IRQST = 40,
-        OMAP_MCBSP_REG_IRQEN,
-        OMAP_MCBSP_REG_WAKEUPEN,
-        OMAP_MCBSP_REG_XCCR,
-        OMAP_MCBSP_REG_RCCR,
-        OMAP_MCBSP_REG_XBUFFSTAT,
-        OMAP_MCBSP_REG_RBUFFSTAT,
-        OMAP_MCBSP_REG_SSELCR,
-};
-
-/* OMAP3 sidetone control registers */
-#define OMAP_ST_REG_REV         0x00
-#define OMAP_ST_REG_SYSCONFIG   0x10
-#define OMAP_ST_REG_IRQSTATUS   0x18
-#define OMAP_ST_REG_IRQENABLE   0x1C
-#define OMAP_ST_REG_SGAINCR     0x24
-#define OMAP_ST_REG_SFIRCR      0x28
-#define OMAP_ST_REG_SSELCR      0x2C
-
-/************************** McBSP SPCR1 bit definitions ***********************/
-#define RRST                    0x0001
-#define RRDY                    0x0002
-#define RFULL                   0x0004
-#define RSYNC_ERR               0x0008
-#define RINTM(value)            ((value)<<4)    /* bits 4:5 */
-#define ABIS                    0x0040
-#define DXENA                   0x0080
-#define CLKSTP(value)           ((value)<<11)   /* bits 11:12 */
-#define RJUST(value)            ((value)<<13)   /* bits 13:14 */
-#define ALB                     0x8000
-#define DLB                     0x8000
-
-/************************** McBSP SPCR2 bit definitions ***********************/
-#define XRST            0x0001
-#define XRDY            0x0002
-#define XEMPTY          0x0004
-#define XSYNC_ERR       0x0008
-#define XINTM(value)    ((value)<<4)            /* bits 4:5 */
-#define GRST            0x0040
-#define FRST            0x0080
-#define SOFT            0x0100
-#define FREE            0x0200
-
-/************************** McBSP PCR bit definitions *************************/
-#define CLKRP           0x0001
-#define CLKXP           0x0002
-#define FSRP            0x0004
-#define FSXP            0x0008
-#define DR_STAT         0x0010
-#define DX_STAT         0x0020
-#define CLKS_STAT       0x0040
-#define SCLKME          0x0080
-#define CLKRM           0x0100
-#define CLKXM           0x0200
-#define FSRM            0x0400
-#define FSXM            0x0800
-#define RIOEN           0x1000
-#define XIOEN           0x2000
-#define IDLE_EN         0x4000
-
-/************************** McBSP RCR1 bit definitions ************************/
-#define RWDLEN1(value)          ((value)<<5)    /* Bits 5:7 */
-#define RFRLEN1(value)          ((value)<<8)    /* Bits 8:14 */
-
-/************************** McBSP XCR1 bit definitions ************************/
-#define XWDLEN1(value)          ((value)<<5)    /* Bits 5:7 */
-#define XFRLEN1(value)          ((value)<<8)    /* Bits 8:14 */
-
-/*************************** McBSP RCR2 bit definitions ***********************/
-#define RDATDLY(value)          (value)         /* Bits 0:1 */
-#define RFIG                    0x0004
-#define RCOMPAND(value)         ((value)<<3)    /* Bits 3:4 */
-#define RWDLEN2(value)          ((value)<<5)    /* Bits 5:7 */
-#define RFRLEN2(value)          ((value)<<8)    /* Bits 8:14 */
-#define RPHASE                  0x8000
-
-/*************************** McBSP XCR2 bit definitions ***********************/
-#define XDATDLY(value)          (value)         /* Bits 0:1 */
-#define XFIG                    0x0004
-#define XCOMPAND(value)         ((value)<<3)    /* Bits 3:4 */
-#define XWDLEN2(value)          ((value)<<5)    /* Bits 5:7 */
-#define XFRLEN2(value)          ((value)<<8)    /* Bits 8:14 */
-#define XPHASE                  0x8000
-
-/************************* McBSP SRGR1 bit definitions ************************/
-#define CLKGDV(value)           (value)         /* Bits 0:7 */
-#define FWID(value)             ((value)<<8)    /* Bits 8:15 */
-
-/************************* McBSP SRGR2 bit definitions ************************/
-#define FPER(value)             (value)         /* Bits 0:11 */
-#define FSGM                    0x1000
-#define CLKSM                   0x2000
-#define CLKSP                   0x4000
-#define GSYNC                   0x8000
-
-/************************* McBSP MCR1 bit definitions *************************/
-#define RMCM                    0x0001
-#define RCBLK(value)            ((value)<<2)    /* Bits 2:4 */
-#define RPABLK(value)           ((value)<<5)    /* Bits 5:6 */
-#define RPBBLK(value)           ((value)<<7)    /* Bits 7:8 */
-
-/************************* McBSP MCR2 bit definitions *************************/
-#define XMCM(value)             (value)         /* Bits 0:1 */
-#define XCBLK(value)            ((value)<<2)    /* Bits 2:4 */
-#define XPABLK(value)           ((value)<<5)    /* Bits 5:6 */
-#define XPBBLK(value)           ((value)<<7)    /* Bits 7:8 */
-
-/*********************** McBSP XCCR bit definitions *************************/
-#define EXTCLKGATE              0x8000
-#define PPCONNECT               0x4000
-#define DXENDLY(value)          ((value)<<12)   /* Bits 12:13 */
-#define XFULL_CYCLE             0x0800
-#define DILB                    0x0020
-#define XDMAEN                  0x0008
-#define XDISABLE                0x0001
-
-/********************** McBSP RCCR bit definitions *************************/
-#define RFULL_CYCLE             0x0800
-#define RDMAEN                  0x0008
-#define RDISABLE                0x0001
-
-/********************** McBSP SYSCONFIG bit definitions ********************/
-#define CLOCKACTIVITY(value)    ((value)<<8)
-#define SIDLEMODE(value)        ((value)<<3)
-#define ENAWAKEUP               0x0004
-#define SOFTRST                 0x0002
-
-/********************** McBSP SSELCR bit definitions ***********************/
-#define SIDETONEEN              0x0400
-
-/********************** McBSP Sidetone SYSCONFIG bit definitions ***********/
-#define ST_AUTOIDLE             0x0001
-
-/********************** McBSP Sidetone SGAINCR bit definitions *************/
-#define ST_CH1GAIN(value)       ((value<<16))   /* Bits 16:31 */
-#define ST_CH0GAIN(value)       (value)         /* Bits 0:15 */
-
-/********************** McBSP Sidetone SFIRCR bit definitions **************/
-#define ST_FIRCOEFF(value)      (value)         /* Bits 0:15 */
-
-/********************** McBSP Sidetone SSELCR bit definitions **************/
-#define ST_COEFFWRDONE          0x0004
-#define ST_COEFFWREN            0x0002
-#define ST_SIDETONEEN           0x0001
-
-/********************** McBSP DMA operating modes **************************/
-#define MCBSP_DMA_MODE_ELEMENT          0
-#define MCBSP_DMA_MODE_THRESHOLD        1
-#define MCBSP_DMA_MODE_FRAME            2
-
-/********************** McBSP WAKEUPEN bit definitions *********************/
-#define XEMPTYEOFEN             0x4000
-#define XRDYEN                  0x0400
-#define XEOFEN                  0x0200
-#define XFSXEN                  0x0100
-#define XSYNCERREN              0x0080
-#define RRDYEN                  0x0008
-#define REOFEN                  0x0004
-#define RFSREN                  0x0002
-#define RSYNCERREN              0x0001
-
-/* CLKR signal muxing options */
-#define CLKR_SRC_CLKR           0
-#define CLKR_SRC_CLKX           1
-
-/* FSR signal muxing options */
-#define FSR_SRC_FSR             0
-#define FSR_SRC_FSX             1
-
-/* McBSP functional clock sources */
-#define MCBSP_CLKS_PRCM_SRC     0
-#define MCBSP_CLKS_PAD_SRC      1
-
-/* we don't do multichannel for now */
-struct omap_mcbsp_reg_cfg {
-        u16 spcr2;
-        u16 spcr1;
-        u16 rcr2;
-        u16 rcr1;
-        u16 xcr2;
-        u16 xcr1;
-        u16 srgr2;
-        u16 srgr1;
-        u16 mcr2;
-        u16 mcr1;
-        u16 pcr0;
-        u16 rcerc;
-        u16 rcerd;
-        u16 xcerc;
-        u16 xcerd;
-        u16 rcere;
-        u16 rcerf;
-        u16 xcere;
-        u16 xcerf;
-        u16 rcerg;
-        u16 rcerh;
-        u16 xcerg;
-        u16 xcerh;
-        u16 xccr;
-        u16 rccr;
-};
-
-typedef enum {
-        OMAP_MCBSP_WORD_8 = 0,
-        OMAP_MCBSP_WORD_12,
-        OMAP_MCBSP_WORD_16,
-        OMAP_MCBSP_WORD_20,
-        OMAP_MCBSP_WORD_24,
-        OMAP_MCBSP_WORD_32,
-} omap_mcbsp_word_length;
-
 /* Platform specific configuration */
 struct omap_mcbsp_ops {
         void (*request)(unsigned int);
@@ -312,43 +51,6 @@ struct omap_mcbsp_platform_data {
         int (*mux_signal)(struct device *dev, const char *signal, const char *src);
 };
 
-struct omap_mcbsp_st_data {
-        void __iomem *io_base_st;
-        bool running;
-        bool enabled;
-        s16 taps[128];  /* Sidetone filter coefficients */
-        int nr_taps;    /* Number of filter coefficients in use */
-        s16 ch0gain;
-        s16 ch1gain;
-};
-
-struct omap_mcbsp {
-        struct device *dev;
-        unsigned long phys_base;
-        unsigned long phys_dma_base;
-        void __iomem *io_base;
-        u8 id;
-        u8 free;
-
-        int rx_irq;
-        int tx_irq;
-
-        /* DMA stuff */
-        u8 dma_rx_sync;
-        u8 dma_tx_sync;
-
-        /* Protect the field .free, while checking if the mcbsp is in use */
-        spinlock_t lock;
-        struct omap_mcbsp_platform_data *pdata;
-        struct clk *fclk;
-        struct omap_mcbsp_st_data *st_data;
-        int dma_op_mode;
-        u16 max_tx_thres;
-        u16 max_rx_thres;
-        void *reg_cache;
-        int reg_cache_size;
-};
-
 /**
  * omap_mcbsp_dev_attr - OMAP McBSP device attributes for omap_hwmod
  * @sidetone: name of the sidetone device
@@ -357,39 +59,4 @@ struct omap_mcbsp_dev_attr {
         const char *sidetone;
 };
 
-extern struct omap_mcbsp **mcbsp_ptr;
-extern int omap_mcbsp_count;
-
-int omap_mcbsp_init(void);
-void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg * config);
-void omap_mcbsp_set_tx_threshold(unsigned int id, u16 threshold);
-void omap_mcbsp_set_rx_threshold(unsigned int id, u16 threshold);
-u16 omap_mcbsp_get_max_tx_threshold(unsigned int id);
-u16 omap_mcbsp_get_max_rx_threshold(unsigned int id);
-u16 omap_mcbsp_get_fifo_size(unsigned int id);
-u16 omap_mcbsp_get_tx_delay(unsigned int id);
-u16 omap_mcbsp_get_rx_delay(unsigned int id);
-int omap_mcbsp_get_dma_op_mode(unsigned int id);
-int omap_mcbsp_request(unsigned int id);
-void omap_mcbsp_free(unsigned int id);
-void omap_mcbsp_start(unsigned int id, int tx, int rx);
-void omap_mcbsp_stop(unsigned int id, int tx, int rx);
-
-/* McBSP functional clock source changing function */
-extern int omap2_mcbsp_set_clks_src(u8 id, u8 fck_src_id);
-
-/* McBSP signal muxing API */
-void omap2_mcbsp1_mux_clkr_src(u8 mux);
-void omap2_mcbsp1_mux_fsr_src(u8 mux);
-
-int omap_mcbsp_dma_ch_params(unsigned int id, unsigned int stream);
-int omap_mcbsp_dma_reg_params(unsigned int id, unsigned int stream);
-
-/* Sidetone specific API */
-int omap_st_set_chgain(unsigned int id, int channel, s16 chgain);
-int omap_st_get_chgain(unsigned int id, int channel, s16 *chgain);
-int omap_st_enable(unsigned int id);
-int omap_st_disable(unsigned int id);
-int omap_st_is_enabled(unsigned int id);
-
 #endif
diff --git a/arch/arm/plat-omap/include/plat/mcspi.h b/arch/arm/plat-omap/include/plat/mcspi.h
index 3d51b18131c..a357eb26bd2 100644
--- a/arch/arm/plat-omap/include/plat/mcspi.h
+++ b/arch/arm/plat-omap/include/plat/mcspi.h
@@ -18,9 +18,6 @@ struct omap2_mcspi_dev_attr {
 
 struct omap2_mcspi_device_config {
         unsigned turbo_mode:1;
-
-        /* Do we want one channel enabled at the same time? */
-        unsigned single_channel:1;
 };
 
 #endif
diff --git a/arch/arm/plat-omap/include/plat/omap4-keypad.h b/arch/arm/plat-omap/include/plat/omap4-keypad.h
index 9fe6c878323..8ad0a377a54 100644
--- a/arch/arm/plat-omap/include/plat/omap4-keypad.h
+++ b/arch/arm/plat-omap/include/plat/omap4-keypad.h
@@ -1,15 +1,6 @@
 #ifndef ARCH_ARM_PLAT_OMAP4_KEYPAD_H
 #define ARCH_ARM_PLAT_OMAP4_KEYPAD_H
 
-#include <linux/input/matrix_keypad.h>
-
-struct omap4_keypad_platform_data {
-        const struct matrix_keymap_data *keymap_data;
-
-        u8 rows;
-        u8 cols;
-};
-
 extern int omap4_keyboard_init(struct omap4_keypad_platform_data *,
                                 struct omap_board_data *);
 #endif
diff --git a/arch/arm/plat-omap/include/plat/omap_device.h b/arch/arm/plat-omap/include/plat/omap_device.h
index 51423d2727a..4327b2c90c3 100644
--- a/arch/arm/plat-omap/include/plat/omap_device.h
+++ b/arch/arm/plat-omap/include/plat/omap_device.h
@@ -36,7 +36,7 @@
 
 #include <plat/omap_hwmod.h>
 
-extern struct device omap_device_parent;
+extern struct dev_pm_domain omap_device_pm_domain;
 
 /* omap_device._state values */
 #define OMAP_DEVICE_STATE_UNKNOWN       0
@@ -100,6 +100,13 @@ struct platform_device *omap_device_build_ss(const char *pdev_name, int pdev_id,
                                          struct omap_device_pm_latency *pm_lats,
                                          int pm_lats_cnt, int is_early_device);
 
+struct omap_device *omap_device_alloc(struct platform_device *pdev,
+                                      struct omap_hwmod **ohs, int oh_cnt,
+                                      struct omap_device_pm_latency *pm_lats,
+                                      int pm_lats_cnt);
+void omap_device_delete(struct omap_device *od);
+int omap_device_register(struct platform_device *pdev);
+
 void __iomem *omap_device_get_rt_va(struct omap_device *od);
 struct device *omap_device_get_by_hwmod_name(const char *oh_name);
 
diff --git a/arch/arm/plat-omap/include/plat/omap_hwmod.h b/arch/arm/plat-omap/include/plat/omap_hwmod.h
index 647010109af..9e8e63d52aa 100644
--- a/arch/arm/plat-omap/include/plat/omap_hwmod.h
+++ b/arch/arm/plat-omap/include/plat/omap_hwmod.h
@@ -484,7 +484,6 @@ struct omap_hwmod_class {
  * @main_clk: main clock: OMAP clock name
  * @_clk: pointer to the main struct clk (filled in at runtime)
  * @opt_clks: other device clocks that drivers can request (0..*)
- * @vdd_name: voltage domain name
  * @voltdm: pointer to voltage domain (filled in at runtime)
  * @masters: ptr to array of OCP ifs that this hwmod can initiate on
  * @slaves: ptr to array of OCP ifs that this hwmod can respond on
@@ -528,7 +527,6 @@ struct omap_hwmod {
         struct omap_hwmod_opt_clk       *opt_clks;
         char                            *clkdm_name;
         struct clockdomain              *clkdm;
-        char                            *vdd_name;
         struct omap_hwmod_ocp_if        **masters; /* connect to *_IA */
         struct omap_hwmod_ocp_if        **slaves;  /* connect to *_TA */
         void                            *dev_attr;
diff --git a/arch/arm/plat-omap/include/plat/remoteproc.h b/arch/arm/plat-omap/include/plat/remoteproc.h
new file mode 100644
index 00000000000..b10eac89e2e
--- /dev/null
+++ b/arch/arm/plat-omap/include/plat/remoteproc.h
@@ -0,0 +1,57 @@
+/*
+ * Remote Processor - omap-specific bits
+ *
+ * Copyright (C) 2011 Texas Instruments, Inc.
+ * Copyright (C) 2011 Google, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _PLAT_REMOTEPROC_H
+#define _PLAT_REMOTEPROC_H
+
+struct rproc_ops;
+struct platform_device;
+
+/*
+ * struct omap_rproc_pdata - omap remoteproc's platform data
+ * @name: the remoteproc's name
+ * @oh_name: omap hwmod device
+ * @oh_name_opt: optional, secondary omap hwmod device
+ * @firmware: name of firmware file to load
+ * @mbox_name: name of omap mailbox device to use with this rproc
+ * @ops: start/stop rproc handlers
+ * @device_enable: omap-specific handler for enabling a device
+ * @device_shutdown: omap-specific handler for shutting down a device
+ */
+struct omap_rproc_pdata {
+        const char *name;
+        const char *oh_name;
+        const char *oh_name_opt;
+        const char *firmware;
+        const char *mbox_name;
+        const struct rproc_ops *ops;
+        int (*device_enable) (struct platform_device *pdev);
+        int (*device_shutdown) (struct platform_device *pdev);
+};
+
+#if defined(CONFIG_OMAP_REMOTEPROC) || defined(CONFIG_OMAP_REMOTEPROC_MODULE)
+
+void __init omap_rproc_reserve_cma(void);
+
+#else
+
+void __init omap_rproc_reserve_cma(void)
+{
+}
+
+#endif
+
+#endif /* _PLAT_REMOTEPROC_H */
diff --git a/arch/arm/plat-omap/include/plat/serial.h b/arch/arm/plat-omap/include/plat/serial.h
index 198d1e6a4a6..b073e5f2b19 100644
--- a/arch/arm/plat-omap/include/plat/serial.h
+++ b/arch/arm/plat-omap/include/plat/serial.h
@@ -110,7 +110,6 @@ struct omap_board_data;
 struct omap_uart_port_info;
 
 extern void omap_serial_init(void);
-extern int omap_uart_can_sleep(void);
 extern void omap_serial_board_init(struct omap_uart_port_info *platform_data);
 extern void omap_serial_init_port(struct omap_board_data *bdata,
                 struct omap_uart_port_info *platform_data);
diff --git a/arch/arm/plat-omap/include/plat/sram.h b/arch/arm/plat-omap/include/plat/sram.h
index 75aa1b2bef5..227ae265755 100644
--- a/arch/arm/plat-omap/include/plat/sram.h
+++ b/arch/arm/plat-omap/include/plat/sram.h
@@ -101,4 +101,5 @@ static inline void omap_push_sram_idle(void) {}
 #else
 #define OMAP4_SRAM_PA           0x40300000
 #endif
+#define AM33XX_SRAM_PA          0x40300000
 #endif
diff --git a/arch/arm/plat-omap/include/plat/system.h b/arch/arm/plat-omap/include/plat/system.h
deleted file mode 100644
index 8e5ebd74b12..00000000000
--- a/arch/arm/plat-omap/include/plat/system.h
+++ /dev/null
@@ -1,15 +0,0 @@
-/*
- * Copied from arch/arm/mach-sa1100/include/mach/system.h
- * Copyright (c) 1999 Nicolas Pitre <nico@fluxnic.net>
- */
-#ifndef __ASM_ARCH_SYSTEM_H
-#define __ASM_ARCH_SYSTEM_H
-
-#include <asm/proc-fns.h>
-
-static inline void arch_idle(void)
-{
-        cpu_do_idle();
-}
-
-#endif
diff --git a/arch/arm/plat-omap/include/plat/tc.h b/arch/arm/plat-omap/include/plat/tc.h
index d2fcd789bb9..1b4b2da8620 100644
--- a/arch/arm/plat-omap/include/plat/tc.h
+++ b/arch/arm/plat-omap/include/plat/tc.h
@@ -84,23 +84,6 @@
 #define EMIFS_CCS(n)            (EMIFS_CS0_CONFIG + (4 * (n)))
 #define EMIFS_ACS(n)            (EMIFS_ACS0 + (4 * (n)))
 
-/* Almost all documentation for chip and board memory maps assumes
- * BM is clear.  Most devel boards have a switch to control booting
- * from NOR flash (using external chipselect 3) rather than mask ROM,
- * which uses BM to interchange the physical CS0 and CS3 addresses.
- */
-static inline u32 omap_cs0_phys(void)
-{
-        return (omap_readl(EMIFS_CONFIG) & OMAP_EMIFS_CONFIG_BM)
-                        ?  OMAP_CS3_PHYS : 0;
-}
-
-static inline u32 omap_cs3_phys(void)
-{
-        return (omap_readl(EMIFS_CONFIG) & OMAP_EMIFS_CONFIG_BM)
-                        ? 0 : OMAP_CS3_PHYS;
-}
-
 #endif  /* __ASSEMBLER__ */
 
 #endif  /* __ASM_ARCH_TC_H */
diff --git a/arch/arm/plat-omap/include/plat/uncompress.h b/arch/arm/plat-omap/include/plat/uncompress.h
index 6ee90495ca4..cc3f11ba7a9 100644
--- a/arch/arm/plat-omap/include/plat/uncompress.h
+++ b/arch/arm/plat-omap/include/plat/uncompress.h
@@ -160,6 +160,7 @@ static inline void __arch_decomp_setup(unsigned long arch_id)
                 DEBUG_LL_OMAP3(3, igep0020);
                 DEBUG_LL_OMAP3(3, igep0030);
                 DEBUG_LL_OMAP3(3, nokia_rm680);
+                DEBUG_LL_OMAP3(3, nokia_rm696);
                 DEBUG_LL_OMAP3(3, nokia_rx51);
                 DEBUG_LL_OMAP3(3, omap3517evm);
                 DEBUG_LL_OMAP3(3, omap3_beagle);
diff --git a/arch/arm/plat-omap/include/plat/usb.h b/arch/arm/plat-omap/include/plat/usb.h
index dc864b580da..d0fc9f4dc15 100644
--- a/arch/arm/plat-omap/include/plat/usb.h
+++ b/arch/arm/plat-omap/include/plat/usb.h
@@ -3,6 +3,7 @@
 #ifndef __ASM_ARCH_OMAP_USB_H
 #define __ASM_ARCH_OMAP_USB_H
 
+#include <linux/io.h>
 #include <linux/usb/musb.h>
 #include <plat/board.h>
 
@@ -105,6 +106,46 @@ extern int omap4430_phy_set_clk(struct device *dev, int on);
 extern int omap4430_phy_init(struct device *dev);
 extern int omap4430_phy_exit(struct device *dev);
 extern int omap4430_phy_suspend(struct device *dev, int suspend);
+
+/*
+ * NOTE: Please update omap USB drivers to use ioremap + read/write
+ */
+
+#define OMAP2_L4_IO_OFFSET      0xb2000000
+#define IOMEM(x)                ((void __force __iomem *)(x))
+#define OMAP2_L4_IO_ADDRESS(pa) IOMEM((pa) + OMAP2_L4_IO_OFFSET)
+
+static inline u8 omap_readb(u32 pa)
+{
+        return __raw_readb(OMAP2_L4_IO_ADDRESS(pa));
+}
+
+static inline u16 omap_readw(u32 pa)
+{
+        return __raw_readw(OMAP2_L4_IO_ADDRESS(pa));
+}
+
+static inline u32 omap_readl(u32 pa)
+{
+        return __raw_readl(OMAP2_L4_IO_ADDRESS(pa));
+}
+
+static inline void omap_writeb(u8 v, u32 pa)
+{
+        __raw_writeb(v, OMAP2_L4_IO_ADDRESS(pa));
+}
+
+
+static inline void omap_writew(u16 v, u32 pa)
+{
+        __raw_writew(v, OMAP2_L4_IO_ADDRESS(pa));
+}
+
+static inline void omap_writel(u32 v, u32 pa)
+{
+        __raw_writel(v, OMAP2_L4_IO_ADDRESS(pa));
+}
+
 #endif
 
 extern void am35x_musb_reset(void);
diff --git a/arch/arm/plat-omap/include/plat/vram.h b/arch/arm/plat-omap/include/plat/vram.h
index 0aa4ecd12c7..4d65b7d06e6 100644
--- a/arch/arm/plat-omap/include/plat/vram.h
+++ b/arch/arm/plat-omap/include/plat/vram.h
@@ -23,40 +23,21 @@
 
 #include <linux/types.h>
 
-#define OMAP_VRAM_MEMTYPE_SDRAM         0
-#define OMAP_VRAM_MEMTYPE_SRAM          1
-#define OMAP_VRAM_MEMTYPE_MAX           1
-
 extern int omap_vram_add_region(unsigned long paddr, size_t size);
 extern int omap_vram_free(unsigned long paddr, size_t size);
-extern int omap_vram_alloc(int mtype, size_t size, unsigned long *paddr);
+extern int omap_vram_alloc(size_t size, unsigned long *paddr);
 extern int omap_vram_reserve(unsigned long paddr, size_t size);
 extern void omap_vram_get_info(unsigned long *vram, unsigned long *free_vram,
                 unsigned long *largest_free_block);
 
 #ifdef CONFIG_OMAP2_VRAM
 extern void omap_vram_set_sdram_vram(u32 size, u32 start);
-extern void omap_vram_set_sram_vram(u32 size, u32 start);
 
 extern void omap_vram_reserve_sdram_memblock(void);
-extern unsigned long omap_vram_reserve_sram(unsigned long sram_pstart,
-                                            unsigned long sram_vstart,
-                                            unsigned long sram_size,
-                                            unsigned long pstart_avail,
-                                            unsigned long size_avail);
 #else
 static inline void omap_vram_set_sdram_vram(u32 size, u32 start) { }
-static inline void omap_vram_set_sram_vram(u32 size, u32 start) { }
 
 static inline void omap_vram_reserve_sdram_memblock(void) { }
-static inline unsigned long omap_vram_reserve_sram(unsigned long sram_pstart,
-                                            unsigned long sram_vstart,
-                                            unsigned long sram_size,
-                                            unsigned long pstart_avail,
-                                            unsigned long size_avail)
-{
-        return 0;
-}
 #endif
 
 #endif
diff --git a/arch/arm/plat-omap/mailbox.c b/arch/arm/plat-omap/mailbox.c
index ad80112c227..ad32621aa52 100644
--- a/arch/arm/plat-omap/mailbox.c
+++ b/arch/arm/plat-omap/mailbox.c
@@ -307,7 +307,7 @@ static void omap_mbox_fini(struct omap_mbox *mbox)
         if (!--mbox->use_count) {
                 free_irq(mbox->irq, mbox);
                 tasklet_kill(&mbox->txq->tasklet);
-        flush_work_sync(&mbox->rxq->work);
+                flush_work_sync(&mbox->rxq->work);
                 mbox_queue_free(mbox->txq);
                 mbox_queue_free(mbox->rxq);
         }
diff --git a/arch/arm/plat-omap/mcbsp.c b/arch/arm/plat-omap/mcbsp.c
deleted file mode 100644
index 4b15cd7926d..00000000000
--- a/arch/arm/plat-omap/mcbsp.c
+++ /dev/null
@@ -1,1361 +0,0 @@
-/*
- * linux/arch/arm/plat-omap/mcbsp.c
- *
- * Copyright (C) 2004 Nokia Corporation
- * Author: Samuel Ortiz <samuel.ortiz@nokia.com>
- *
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * Multichannel mode not supported.
- */
-
-#include <linux/module.h>
-#include <linux/init.h>
-#include <linux/device.h>
-#include <linux/platform_device.h>
-#include <linux/interrupt.h>
-#include <linux/err.h>
-#include <linux/clk.h>
-#include <linux/delay.h>
-#include <linux/io.h>
-#include <linux/slab.h>
-
-#include <plat/mcbsp.h>
-#include <linux/pm_runtime.h>
-
-struct omap_mcbsp **mcbsp_ptr;
-int omap_mcbsp_count;
-
-#define omap_mcbsp_check_valid_id(id)   (id < omap_mcbsp_count)
-#define id_to_mcbsp_ptr(id)             mcbsp_ptr[id];
-
-static void omap_mcbsp_write(struct omap_mcbsp *mcbsp, u16 reg, u32 val)
-{
-        void __iomem *addr = mcbsp->io_base + reg * mcbsp->pdata->reg_step;
-
-        if (mcbsp->pdata->reg_size == 2) {
-                ((u16 *)mcbsp->reg_cache)[reg] = (u16)val;
-                __raw_writew((u16)val, addr);
-        } else {
-                ((u32 *)mcbsp->reg_cache)[reg] = val;
-                __raw_writel(val, addr);
-        }
-}
-
-static int omap_mcbsp_read(struct omap_mcbsp *mcbsp, u16 reg, bool from_cache)
-{
-        void __iomem *addr = mcbsp->io_base + reg * mcbsp->pdata->reg_step;
-
-        if (mcbsp->pdata->reg_size == 2) {
-                return !from_cache ? __raw_readw(addr) :
-                                     ((u16 *)mcbsp->reg_cache)[reg];
-        } else {
-                return !from_cache ? __raw_readl(addr) :
-                                     ((u32 *)mcbsp->reg_cache)[reg];
-        }
-}
-
-static void omap_mcbsp_st_write(struct omap_mcbsp *mcbsp, u16 reg, u32 val)
-{
-        __raw_writel(val, mcbsp->st_data->io_base_st + reg);
-}
-
-static int omap_mcbsp_st_read(struct omap_mcbsp *mcbsp, u16 reg)
-{
-        return __raw_readl(mcbsp->st_data->io_base_st + reg);
-}
-
-#define MCBSP_READ(mcbsp, reg) \
-                omap_mcbsp_read(mcbsp, OMAP_MCBSP_REG_##reg, 0)
-#define MCBSP_WRITE(mcbsp, reg, val) \
-                omap_mcbsp_write(mcbsp, OMAP_MCBSP_REG_##reg, val)
-#define MCBSP_READ_CACHE(mcbsp, reg) \
-                omap_mcbsp_read(mcbsp, OMAP_MCBSP_REG_##reg, 1)
-
-#define MCBSP_ST_READ(mcbsp, reg) \
-                        omap_mcbsp_st_read(mcbsp, OMAP_ST_REG_##reg)
-#define MCBSP_ST_WRITE(mcbsp, reg, val) \
-                        omap_mcbsp_st_write(mcbsp, OMAP_ST_REG_##reg, val)
-
-static void omap_mcbsp_dump_reg(u8 id)
-{
-        struct omap_mcbsp *mcbsp = id_to_mcbsp_ptr(id);
-
-        dev_dbg(mcbsp->dev, "**** McBSP%d regs ****\n", mcbsp->id);
-        dev_dbg(mcbsp->dev, "DRR2:  0x%04x\n",
-                        MCBSP_READ(mcbsp, DRR2));
-        dev_dbg(mcbsp->dev, "DRR1:  0x%04x\n",
-                        MCBSP_READ(mcbsp, DRR1));
-        dev_dbg(mcbsp->dev, "DXR2:  0x%04x\n",
-                        MCBSP_READ(mcbsp, DXR2));
-        dev_dbg(mcbsp->dev, "DXR1:  0x%04x\n",
-                        MCBSP_READ(mcbsp, DXR1));
-        dev_dbg(mcbsp->dev, "SPCR2: 0x%04x\n",
-                        MCBSP_READ(mcbsp, SPCR2));
-        dev_dbg(mcbsp->dev, "SPCR1: 0x%04x\n",
-                        MCBSP_READ(mcbsp, SPCR1));
-        dev_dbg(mcbsp->dev, "RCR2:  0x%04x\n",
-                        MCBSP_READ(mcbsp, RCR2));
-        dev_dbg(mcbsp->dev, "RCR1:  0x%04x\n",
-                        MCBSP_READ(mcbsp, RCR1));
-        dev_dbg(mcbsp->dev, "XCR2:  0x%04x\n",
-                        MCBSP_READ(mcbsp, XCR2));
-        dev_dbg(mcbsp->dev, "XCR1:  0x%04x\n",
-                        MCBSP_READ(mcbsp, XCR1));
-        dev_dbg(mcbsp->dev, "SRGR2: 0x%04x\n",
-                        MCBSP_READ(mcbsp, SRGR2));
-        dev_dbg(mcbsp->dev, "SRGR1: 0x%04x\n",
-                        MCBSP_READ(mcbsp, SRGR1));
-        dev_dbg(mcbsp->dev, "PCR0:  0x%04x\n",
-                        MCBSP_READ(mcbsp, PCR0));
-        dev_dbg(mcbsp->dev, "***********************\n");
-}
-
-static irqreturn_t omap_mcbsp_tx_irq_handler(int irq, void *dev_id)
-{
-        struct omap_mcbsp *mcbsp_tx = dev_id;
-        u16 irqst_spcr2;
-
-        irqst_spcr2 = MCBSP_READ(mcbsp_tx, SPCR2);
-        dev_dbg(mcbsp_tx->dev, "TX IRQ callback : 0x%x\n", irqst_spcr2);
-
-        if (irqst_spcr2 & XSYNC_ERR) {
-                dev_err(mcbsp_tx->dev, "TX Frame Sync Error! : 0x%x\n",
-                        irqst_spcr2);
-                /* Writing zero to XSYNC_ERR clears the IRQ */
-                MCBSP_WRITE(mcbsp_tx, SPCR2, MCBSP_READ_CACHE(mcbsp_tx, SPCR2));
-        }
-
-        return IRQ_HANDLED;
-}
-
-static irqreturn_t omap_mcbsp_rx_irq_handler(int irq, void *dev_id)
-{
-        struct omap_mcbsp *mcbsp_rx = dev_id;
-        u16 irqst_spcr1;
-
-        irqst_spcr1 = MCBSP_READ(mcbsp_rx, SPCR1);
-        dev_dbg(mcbsp_rx->dev, "RX IRQ callback : 0x%x\n", irqst_spcr1);
-
-        if (irqst_spcr1 & RSYNC_ERR) {
-                dev_err(mcbsp_rx->dev, "RX Frame Sync Error! : 0x%x\n",
-                        irqst_spcr1);
-                /* Writing zero to RSYNC_ERR clears the IRQ */
-                MCBSP_WRITE(mcbsp_rx, SPCR1, MCBSP_READ_CACHE(mcbsp_rx, SPCR1));
-        }
-
-        return IRQ_HANDLED;
-}
-
-/*
- * omap_mcbsp_config simply write a config to the
- * appropriate McBSP.
- * You either call this function or set the McBSP registers
- * by yourself before calling omap_mcbsp_start().
- */
-void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg *config)
-{
-        struct omap_mcbsp *mcbsp;
-
-        if (!omap_mcbsp_check_valid_id(id)) {
-                printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
-                return;
-        }
-        mcbsp = id_to_mcbsp_ptr(id);
-
-        dev_dbg(mcbsp->dev, "Configuring McBSP%d  phys_base: 0x%08lx\n",
-                        mcbsp->id, mcbsp->phys_base);
-
-        /* We write the given config */
-        MCBSP_WRITE(mcbsp, SPCR2, config->spcr2);
-        MCBSP_WRITE(mcbsp, SPCR1, config->spcr1);
-        MCBSP_WRITE(mcbsp, RCR2, config->rcr2);
-        MCBSP_WRITE(mcbsp, RCR1, config->rcr1);
-        MCBSP_WRITE(mcbsp, XCR2, config->xcr2);
-        MCBSP_WRITE(mcbsp, XCR1, config->xcr1);
-        MCBSP_WRITE(mcbsp, SRGR2, config->srgr2);
-        MCBSP_WRITE(mcbsp, SRGR1, config->srgr1);
-        MCBSP_WRITE(mcbsp, MCR2, config->mcr2);
-        MCBSP_WRITE(mcbsp, MCR1, config->mcr1);
-        MCBSP_WRITE(mcbsp, PCR0, config->pcr0);
-        if (mcbsp->pdata->has_ccr) {
-                MCBSP_WRITE(mcbsp, XCCR, config->xccr);
-                MCBSP_WRITE(mcbsp, RCCR, config->rccr);
-        }
-}
-EXPORT_SYMBOL(omap_mcbsp_config);
-
-/**
- * omap_mcbsp_dma_params - returns the dma channel number
- * @id - mcbsp id
- * @stream - indicates the direction of data flow (rx or tx)
- *
- * Returns the dma channel number for the rx channel or tx channel
- * based on the value of @stream for the requested mcbsp given by @id
- */
-int omap_mcbsp_dma_ch_params(unsigned int id, unsigned int stream)
-{
-        struct omap_mcbsp *mcbsp;
-
-        if (!omap_mcbsp_check_valid_id(id)) {
-                printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
-                return -ENODEV;
-        }
-        mcbsp = id_to_mcbsp_ptr(id);
-
-        if (stream)
-                return mcbsp->dma_rx_sync;
-        else
-                return mcbsp->dma_tx_sync;
-}
-EXPORT_SYMBOL(omap_mcbsp_dma_ch_params);
-
-/**
- * omap_mcbsp_dma_reg_params - returns the address of mcbsp data register
- * @id - mcbsp id
- * @stream - indicates the direction of data flow (rx or tx)
- *
- * Returns the address of mcbsp data transmit register or data receive register
- * to be used by DMA for transferring/receiving data based on the value of
- * @stream for the requested mcbsp given by @id
- */
-int omap_mcbsp_dma_reg_params(unsigned int id, unsigned int stream)
-{
-        struct omap_mcbsp *mcbsp;
-        int data_reg;
-
-        if (!omap_mcbsp_check_valid_id(id)) {
-                printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
-                return -ENODEV;
-        }
-        mcbsp = id_to_mcbsp_ptr(id);
-
-        if (mcbsp->pdata->reg_size == 2) {
-                if (stream)
-                        data_reg = OMAP_MCBSP_REG_DRR1;
-                else
-                        data_reg = OMAP_MCBSP_REG_DXR1;
-        } else {
-                if (stream)
-                        data_reg = OMAP_MCBSP_REG_DRR;
-                else
-                        data_reg = OMAP_MCBSP_REG_DXR;
-        }
-
-        return mcbsp->phys_dma_base + data_reg * mcbsp->pdata->reg_step;
-}
-EXPORT_SYMBOL(omap_mcbsp_dma_reg_params);
-
-static void omap_st_on(struct omap_mcbsp *mcbsp)
-{
-        unsigned int w;
-
-        if (mcbsp->pdata->enable_st_clock)
-                mcbsp->pdata->enable_st_clock(mcbsp->id, 1);
-
-        /* Enable McBSP Sidetone */
-        w = MCBSP_READ(mcbsp, SSELCR);
-        MCBSP_WRITE(mcbsp, SSELCR, w | SIDETONEEN);
-
-        /* Enable Sidetone from Sidetone Core */
-        w = MCBSP_ST_READ(mcbsp, SSELCR);
-        MCBSP_ST_WRITE(mcbsp, SSELCR, w | ST_SIDETONEEN);
-}
-
-static void omap_st_off(struct omap_mcbsp *mcbsp)
-{
-        unsigned int w;
-
-        w = MCBSP_ST_READ(mcbsp, SSELCR);
-        MCBSP_ST_WRITE(mcbsp, SSELCR, w & ~(ST_SIDETONEEN));
-
-        w = MCBSP_READ(mcbsp, SSELCR);
-        MCBSP_WRITE(mcbsp, SSELCR, w & ~(SIDETONEEN));
-
-        if (mcbsp->pdata->enable_st_clock)
-                mcbsp->pdata->enable_st_clock(mcbsp->id, 0);
-}
-
-static void omap_st_fir_write(struct omap_mcbsp *mcbsp, s16 *fir)
-{
-        u16 val, i;
-
-        val = MCBSP_ST_READ(mcbsp, SSELCR);
-
-        if (val & ST_COEFFWREN)
-                MCBSP_ST_WRITE(mcbsp, SSELCR, val & ~(ST_COEFFWREN));
-
-        MCBSP_ST_WRITE(mcbsp, SSELCR, val | ST_COEFFWREN);
-
-        for (i = 0; i < 128; i++)
-                MCBSP_ST_WRITE(mcbsp, SFIRCR, fir[i]);
-
-        i = 0;
-
-        val = MCBSP_ST_READ(mcbsp, SSELCR);
-        while (!(val & ST_COEFFWRDONE) && (++i < 1000))
-                val = MCBSP_ST_READ(mcbsp, SSELCR);
-
-        MCBSP_ST_WRITE(mcbsp, SSELCR, val & ~(ST_COEFFWREN));
-
-        if (i == 1000)
-                dev_err(mcbsp->dev, "McBSP FIR load error!\n");
-}
-
-static void omap_st_chgain(struct omap_mcbsp *mcbsp)
-{
-        u16 w;
-        struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
-
-        w = MCBSP_ST_READ(mcbsp, SSELCR);
-
-        MCBSP_ST_WRITE(mcbsp, SGAINCR, ST_CH0GAIN(st_data->ch0gain) | \
-                      ST_CH1GAIN(st_data->ch1gain));
-}
-
-int omap_st_set_chgain(unsigned int id, int channel, s16 chgain)
-{
-        struct omap_mcbsp *mcbsp;
-        struct omap_mcbsp_st_data *st_data;
-        int ret = 0;
-
-        if (!omap_mcbsp_check_valid_id(id)) {
-                printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
-                return -ENODEV;
-        }
-
-        mcbsp = id_to_mcbsp_ptr(id);
-        st_data = mcbsp->st_data;
-
-        if (!st_data)
-                return -ENOENT;
-
-        spin_lock_irq(&mcbsp->lock);
-        if (channel == 0)
-                st_data->ch0gain = chgain;
-        else if (channel == 1)
-                st_data->ch1gain = chgain;
-        else
-                ret = -EINVAL;
-
-        if (st_data->enabled)
-                omap_st_chgain(mcbsp);
-        spin_unlock_irq(&mcbsp->lock);
-
-        return ret;
-}
-EXPORT_SYMBOL(omap_st_set_chgain);
-
-int omap_st_get_chgain(unsigned int id, int channel, s16 *chgain)
-{
-        struct omap_mcbsp *mcbsp;
-        struct omap_mcbsp_st_data *st_data;
-        int ret = 0;
-
-        if (!omap_mcbsp_check_valid_id(id)) {
-                printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
-                return -ENODEV;
-        }
-
-        mcbsp = id_to_mcbsp_ptr(id);
-        st_data = mcbsp->st_data;
-
-        if (!st_data)
-                return -ENOENT;
-
-        spin_lock_irq(&mcbsp->lock);
-        if (channel == 0)
-                *chgain = st_data->ch0gain;
-        else if (channel == 1)
-                *chgain = st_data->ch1gain;
-        else
-                ret = -EINVAL;
-        spin_unlock_irq(&mcbsp->lock);
-
-        return ret;
-}
-EXPORT_SYMBOL(omap_st_get_chgain);
-
-static int omap_st_start(struct omap_mcbsp *mcbsp)
-{
-        struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
-
-        if (st_data && st_data->enabled && !st_data->running) {
-                omap_st_fir_write(mcbsp, st_data->taps);
-                omap_st_chgain(mcbsp);
-
-                if (!mcbsp->free) {
-                        omap_st_on(mcbsp);
-                        st_data->running = 1;
-                }
-        }
-
-        return 0;
-}
-
-int omap_st_enable(unsigned int id)
-{
-        struct omap_mcbsp *mcbsp;
-        struct omap_mcbsp_st_data *st_data;
-
-        if (!omap_mcbsp_check_valid_id(id)) {
-                printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
-                return -ENODEV;
-        }
-
-        mcbsp = id_to_mcbsp_ptr(id);
-        st_data = mcbsp->st_data;
-
-        if (!st_data)
-                return -ENODEV;
-
-        spin_lock_irq(&mcbsp->lock);
-        st_data->enabled = 1;
-        omap_st_start(mcbsp);
-        spin_unlock_irq(&mcbsp->lock);
-
-        return 0;
-}
-EXPORT_SYMBOL(omap_st_enable);
-
-static int omap_st_stop(struct omap_mcbsp *mcbsp)
-{
-        struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
-
-        if (st_data && st_data->running) {
-                if (!mcbsp->free) {
-                        omap_st_off(mcbsp);
-                        st_data->running = 0;
-                }
-        }
-
-        return 0;
-}
-
-int omap_st_disable(unsigned int id)
-{
-        struct omap_mcbsp *mcbsp;
-        struct omap_mcbsp_st_data *st_data;
-        int ret = 0;
-
-        if (!omap_mcbsp_check_valid_id(id)) {
-                printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
-                return -ENODEV;
-        }
-
-        mcbsp = id_to_mcbsp_ptr(id);
-        st_data = mcbsp->st_data;
-
-        if (!st_data)
-                return -ENODEV;
-
-        spin_lock_irq(&mcbsp->lock);
-        omap_st_stop(mcbsp);
-        st_data->enabled = 0;
-        spin_unlock_irq(&mcbsp->lock);
-
-        return ret;
-}
-EXPORT_SYMBOL(omap_st_disable);
-
-int omap_st_is_enabled(unsigned int id)
-{
-        struct omap_mcbsp *mcbsp;
-        struct omap_mcbsp_st_data *st_data;
-
-        if (!omap_mcbsp_check_valid_id(id)) {
-                printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
-                return -ENODEV;
-        }
-
-        mcbsp = id_to_mcbsp_ptr(id);
-        st_data = mcbsp->st_data;
-
-        if (!st_data)
-                return -ENODEV;
-
-
-        return st_data->enabled;
-}
-EXPORT_SYMBOL(omap_st_is_enabled);
-
-/*
- * omap_mcbsp_set_rx_threshold configures the transmit threshold in words.
- * The threshold parameter is 1 based, and it is converted (threshold - 1)
- * for the THRSH2 register.
- */
-void omap_mcbsp_set_tx_threshold(unsigned int id, u16 threshold)
-{
-        struct omap_mcbsp *mcbsp;
-
-        if (!omap_mcbsp_check_valid_id(id)) {
-                printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
-                return;
-        }
-        mcbsp = id_to_mcbsp_ptr(id);
-        if (mcbsp->pdata->buffer_size == 0)
-                return;
-
-        if (threshold && threshold <= mcbsp->max_tx_thres)
-                MCBSP_WRITE(mcbsp, THRSH2, threshold - 1);
-}
-EXPORT_SYMBOL(omap_mcbsp_set_tx_threshold);
-
-/*
- * omap_mcbsp_set_rx_threshold configures the receive threshold in words.
- * The threshold parameter is 1 based, and it is converted (threshold - 1)
- * for the THRSH1 register.
- */
-void omap_mcbsp_set_rx_threshold(unsigned int id, u16 threshold)
-{
-        struct omap_mcbsp *mcbsp;
-
-        if (!omap_mcbsp_check_valid_id(id)) {
-                printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
-                return;
-        }
-        mcbsp = id_to_mcbsp_ptr(id);
-        if (mcbsp->pdata->buffer_size == 0)
-                return;
-
-        if (threshold && threshold <= mcbsp->max_rx_thres)
-                MCBSP_WRITE(mcbsp, THRSH1, threshold - 1);
-}
-EXPORT_SYMBOL(omap_mcbsp_set_rx_threshold);
-
-/*
- * omap_mcbsp_get_max_tx_thres just return the current configured
- * maximum threshold for transmission
- */
-u16 omap_mcbsp_get_max_tx_threshold(unsigned int id)
-{
-        struct omap_mcbsp *mcbsp;
-
-        if (!omap_mcbsp_check_valid_id(id)) {
-                printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
-                return -ENODEV;
-        }
-        mcbsp = id_to_mcbsp_ptr(id);
-
-        return mcbsp->max_tx_thres;
-}
-EXPORT_SYMBOL(omap_mcbsp_get_max_tx_threshold);
-
-/*
- * omap_mcbsp_get_max_rx_thres just return the current configured
- * maximum threshold for reception
- */
-u16 omap_mcbsp_get_max_rx_threshold(unsigned int id)
-{
-        struct omap_mcbsp *mcbsp;
-
-        if (!omap_mcbsp_check_valid_id(id)) {
-                printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
-                return -ENODEV;
-        }
-        mcbsp = id_to_mcbsp_ptr(id);
-
-        return mcbsp->max_rx_thres;
-}
-EXPORT_SYMBOL(omap_mcbsp_get_max_rx_threshold);
-
-u16 omap_mcbsp_get_fifo_size(unsigned int id)
-{
-        struct omap_mcbsp *mcbsp;
-
-        if (!omap_mcbsp_check_valid_id(id)) {
-                printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
-                return -ENODEV;
-        }
-        mcbsp = id_to_mcbsp_ptr(id);
-
-        return mcbsp->pdata->buffer_size;
-}
-EXPORT_SYMBOL(omap_mcbsp_get_fifo_size);
-
-/*
- * omap_mcbsp_get_tx_delay returns the number of used slots in the McBSP FIFO
- */
-u16 omap_mcbsp_get_tx_delay(unsigned int id)
-{
-        struct omap_mcbsp *mcbsp;
-        u16 buffstat;
-
-        if (!omap_mcbsp_check_valid_id(id)) {
-                printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
-                return -ENODEV;
-        }
-        mcbsp = id_to_mcbsp_ptr(id);
-        if (mcbsp->pdata->buffer_size == 0)
-                return 0;
-
-        /* Returns the number of free locations in the buffer */
-        buffstat = MCBSP_READ(mcbsp, XBUFFSTAT);
-
-        /* Number of slots are different in McBSP ports */
-        return mcbsp->pdata->buffer_size - buffstat;
-}
-EXPORT_SYMBOL(omap_mcbsp_get_tx_delay);
-
-/*
- * omap_mcbsp_get_rx_delay returns the number of free slots in the McBSP FIFO
- * to reach the threshold value (when the DMA will be triggered to read it)
- */
-u16 omap_mcbsp_get_rx_delay(unsigned int id)
-{
-        struct omap_mcbsp *mcbsp;
-        u16 buffstat, threshold;
-
-        if (!omap_mcbsp_check_valid_id(id)) {
-                printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
-                return -ENODEV;
-        }
-        mcbsp = id_to_mcbsp_ptr(id);
-        if (mcbsp->pdata->buffer_size == 0)
-                return 0;
-
-        /* Returns the number of used locations in the buffer */
-        buffstat = MCBSP_READ(mcbsp, RBUFFSTAT);
-        /* RX threshold */
-        threshold = MCBSP_READ(mcbsp, THRSH1);
-
-        /* Return the number of location till we reach the threshold limit */
-        if (threshold <= buffstat)
-                return 0;
-        else
-                return threshold - buffstat;
-}
-EXPORT_SYMBOL(omap_mcbsp_get_rx_delay);
-
-/*
- * omap_mcbsp_get_dma_op_mode just return the current configured
- * operating mode for the mcbsp channel
- */
-int omap_mcbsp_get_dma_op_mode(unsigned int id)
-{
-        struct omap_mcbsp *mcbsp;
-        int dma_op_mode;
-
-        if (!omap_mcbsp_check_valid_id(id)) {
-                printk(KERN_ERR "%s: Invalid id (%u)\n", __func__, id + 1);
-                return -ENODEV;
-        }
-        mcbsp = id_to_mcbsp_ptr(id);
-
-        dma_op_mode = mcbsp->dma_op_mode;
-
-        return dma_op_mode;
-}
-EXPORT_SYMBOL(omap_mcbsp_get_dma_op_mode);
-
-int omap_mcbsp_request(unsigned int id)
-{
-        struct omap_mcbsp *mcbsp;
-        void *reg_cache;
-        int err;
-
-        if (!omap_mcbsp_check_valid_id(id)) {
-                printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
-                return -ENODEV;
-        }
-        mcbsp = id_to_mcbsp_ptr(id);
-
-        reg_cache = kzalloc(mcbsp->reg_cache_size, GFP_KERNEL);
-        if (!reg_cache) {
-                return -ENOMEM;
-        }
-
-        spin_lock(&mcbsp->lock);
-        if (!mcbsp->free) {
-                dev_err(mcbsp->dev, "McBSP%d is currently in use\n",
-                        mcbsp->id);
-                err = -EBUSY;
-                goto err_kfree;
-        }
-
-        mcbsp->free = false;
-        mcbsp->reg_cache = reg_cache;
-        spin_unlock(&mcbsp->lock);
-
-        if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->request)
-                mcbsp->pdata->ops->request(id);
-
-        pm_runtime_get_sync(mcbsp->dev);
-
-        /* Enable wakeup behavior */
-        if (mcbsp->pdata->has_wakeup)
-                MCBSP_WRITE(mcbsp, WAKEUPEN, XRDYEN | RRDYEN);
-
-        /*
-         * Make sure that transmitter, receiver and sample-rate generator are
-         * not running before activating IRQs.
-         */
-        MCBSP_WRITE(mcbsp, SPCR1, 0);
-        MCBSP_WRITE(mcbsp, SPCR2, 0);
-
-        err = request_irq(mcbsp->tx_irq, omap_mcbsp_tx_irq_handler,
-                                0, "McBSP", (void *)mcbsp);
-        if (err != 0) {
-                dev_err(mcbsp->dev, "Unable to request TX IRQ %d "
-                                "for McBSP%d\n", mcbsp->tx_irq,
-                                mcbsp->id);
-                goto err_clk_disable;
-        }
-
-        if (mcbsp->rx_irq) {
-                err = request_irq(mcbsp->rx_irq,
-                                omap_mcbsp_rx_irq_handler,
-                                0, "McBSP", (void *)mcbsp);
-                if (err != 0) {
-                        dev_err(mcbsp->dev, "Unable to request RX IRQ %d "
-                                        "for McBSP%d\n", mcbsp->rx_irq,
-                                        mcbsp->id);
-                        goto err_free_irq;
-                }
-        }
-
-        return 0;
-err_free_irq:
-        free_irq(mcbsp->tx_irq, (void *)mcbsp);
-err_clk_disable:
-        if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->free)
-                mcbsp->pdata->ops->free(id);
-
-        /* Disable wakeup behavior */
-        if (mcbsp->pdata->has_wakeup)
-                MCBSP_WRITE(mcbsp, WAKEUPEN, 0);
-
-        pm_runtime_put_sync(mcbsp->dev);
-
-        spin_lock(&mcbsp->lock);
-        mcbsp->free = true;
-        mcbsp->reg_cache = NULL;
-err_kfree:
-        spin_unlock(&mcbsp->lock);
-        kfree(reg_cache);
-
-        return err;
-}
-EXPORT_SYMBOL(omap_mcbsp_request);
-
-void omap_mcbsp_free(unsigned int id)
-{
-        struct omap_mcbsp *mcbsp;
-        void *reg_cache;
-
-        if (!omap_mcbsp_check_valid_id(id)) {
-                printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
-                return;
-        }
-        mcbsp = id_to_mcbsp_ptr(id);
-
-        if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->free)
-                mcbsp->pdata->ops->free(id);
-
-        /* Disable wakeup behavior */
-        if (mcbsp->pdata->has_wakeup)
-                MCBSP_WRITE(mcbsp, WAKEUPEN, 0);
-
-        pm_runtime_put_sync(mcbsp->dev);
-
-        if (mcbsp->rx_irq)
-                free_irq(mcbsp->rx_irq, (void *)mcbsp);
-        free_irq(mcbsp->tx_irq, (void *)mcbsp);
-
-        reg_cache = mcbsp->reg_cache;
-
-        spin_lock(&mcbsp->lock);
-        if (mcbsp->free)
-                dev_err(mcbsp->dev, "McBSP%d was not reserved\n", mcbsp->id);
-        else
-                mcbsp->free = true;
-        mcbsp->reg_cache = NULL;
-        spin_unlock(&mcbsp->lock);
-
-        if (reg_cache)
-                kfree(reg_cache);
-}
-EXPORT_SYMBOL(omap_mcbsp_free);
-
-/*
- * Here we start the McBSP, by enabling transmitter, receiver or both.
- * If no transmitter or receiver is active prior calling, then sample-rate
- * generator and frame sync are started.
- */
-void omap_mcbsp_start(unsigned int id, int tx, int rx)
-{
-        struct omap_mcbsp *mcbsp;
-        int enable_srg = 0;
-        u16 w;
-
-        if (!omap_mcbsp_check_valid_id(id)) {
-                printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
-                return;
-        }
-        mcbsp = id_to_mcbsp_ptr(id);
-
-        if (mcbsp->st_data)
-                omap_st_start(mcbsp);
-
-        /* Only enable SRG, if McBSP is master */
-        w = MCBSP_READ_CACHE(mcbsp, PCR0);
-        if (w & (FSXM | FSRM | CLKXM | CLKRM))
-                enable_srg = !((MCBSP_READ_CACHE(mcbsp, SPCR2) |
-                                MCBSP_READ_CACHE(mcbsp, SPCR1)) & 1);
-
-        if (enable_srg) {
-                /* Start the sample generator */
-                w = MCBSP_READ_CACHE(mcbsp, SPCR2);
-                MCBSP_WRITE(mcbsp, SPCR2, w | (1 << 6));
-        }
-
-        /* Enable transmitter and receiver */
-        tx &= 1;
-        w = MCBSP_READ_CACHE(mcbsp, SPCR2);
-        MCBSP_WRITE(mcbsp, SPCR2, w | tx);
-
-        rx &= 1;
-        w = MCBSP_READ_CACHE(mcbsp, SPCR1);
-        MCBSP_WRITE(mcbsp, SPCR1, w | rx);
-
-        /*
-         * Worst case: CLKSRG*2 = 8000khz: (1/8000) * 2 * 2 usec
-         * REVISIT: 100us may give enough time for two CLKSRG, however
-         * due to some unknown PM related, clock gating etc. reason it
-         * is now at 500us.
-         */
-        udelay(500);
-
-        if (enable_srg) {
-                /* Start frame sync */
-                w = MCBSP_READ_CACHE(mcbsp, SPCR2);
-                MCBSP_WRITE(mcbsp, SPCR2, w | (1 << 7));
-        }
-
-        if (mcbsp->pdata->has_ccr) {
-                /* Release the transmitter and receiver */
-                w = MCBSP_READ_CACHE(mcbsp, XCCR);
-                w &= ~(tx ? XDISABLE : 0);
-                MCBSP_WRITE(mcbsp, XCCR, w);
-                w = MCBSP_READ_CACHE(mcbsp, RCCR);
-                w &= ~(rx ? RDISABLE : 0);
-                MCBSP_WRITE(mcbsp, RCCR, w);
-        }
-
-        /* Dump McBSP Regs */
-        omap_mcbsp_dump_reg(id);
-}
-EXPORT_SYMBOL(omap_mcbsp_start);
-
-void omap_mcbsp_stop(unsigned int id, int tx, int rx)
-{
-        struct omap_mcbsp *mcbsp;
-        int idle;
-        u16 w;
-
-        if (!omap_mcbsp_check_valid_id(id)) {
-                printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
-                return;
-        }
-
-        mcbsp = id_to_mcbsp_ptr(id);
-
-        /* Reset transmitter */
-        tx &= 1;
-        if (mcbsp->pdata->has_ccr) {
-                w = MCBSP_READ_CACHE(mcbsp, XCCR);
-                w |= (tx ? XDISABLE : 0);
-                MCBSP_WRITE(mcbsp, XCCR, w);
-        }
-        w = MCBSP_READ_CACHE(mcbsp, SPCR2);
-        MCBSP_WRITE(mcbsp, SPCR2, w & ~tx);
-
-        /* Reset receiver */
-        rx &= 1;
-        if (mcbsp->pdata->has_ccr) {
-                w = MCBSP_READ_CACHE(mcbsp, RCCR);
-                w |= (rx ? RDISABLE : 0);
-                MCBSP_WRITE(mcbsp, RCCR, w);
-        }
-        w = MCBSP_READ_CACHE(mcbsp, SPCR1);
-        MCBSP_WRITE(mcbsp, SPCR1, w & ~rx);
-
-        idle = !((MCBSP_READ_CACHE(mcbsp, SPCR2) |
-                        MCBSP_READ_CACHE(mcbsp, SPCR1)) & 1);
-
-        if (idle) {
-                /* Reset the sample rate generator */
-                w = MCBSP_READ_CACHE(mcbsp, SPCR2);
-                MCBSP_WRITE(mcbsp, SPCR2, w & ~(1 << 6));
-        }
-
-        if (mcbsp->st_data)
-                omap_st_stop(mcbsp);
-}
-EXPORT_SYMBOL(omap_mcbsp_stop);
-
-int omap2_mcbsp_set_clks_src(u8 id, u8 fck_src_id)
-{
-        struct omap_mcbsp *mcbsp;
-        const char *src;
-
-        if (!omap_mcbsp_check_valid_id(id)) {
-                pr_err("%s: Invalid id (%d)\n", __func__, id + 1);
-                return -EINVAL;
-        }
-        mcbsp = id_to_mcbsp_ptr(id);
-
-        if (fck_src_id == MCBSP_CLKS_PAD_SRC)
-                src = "clks_ext";
-        else if (fck_src_id == MCBSP_CLKS_PRCM_SRC)
-                src = "clks_fclk";
-        else
-                return -EINVAL;
-
-        if (mcbsp->pdata->set_clk_src)
-                return mcbsp->pdata->set_clk_src(mcbsp->dev, mcbsp->fclk, src);
-        else
-                return -EINVAL;
-}
-EXPORT_SYMBOL(omap2_mcbsp_set_clks_src);
-
-void omap2_mcbsp1_mux_clkr_src(u8 mux)
-{
-        struct omap_mcbsp *mcbsp;
-        const char *src;
-
-        if (mux == CLKR_SRC_CLKR)
-                src = "clkr";
-        else if (mux == CLKR_SRC_CLKX)
-                src = "clkx";
-        else
-                return;
-
-        mcbsp = id_to_mcbsp_ptr(0);
-        if (mcbsp->pdata->mux_signal)
-                mcbsp->pdata->mux_signal(mcbsp->dev, "clkr", src);
-}
-EXPORT_SYMBOL(omap2_mcbsp1_mux_clkr_src);
-
-void omap2_mcbsp1_mux_fsr_src(u8 mux)
-{
-        struct omap_mcbsp *mcbsp;
-        const char *src;
-
-        if (mux == FSR_SRC_FSR)
-                src = "fsr";
-        else if (mux == FSR_SRC_FSX)
-                src = "fsx";
-        else
-                return;
-
-        mcbsp = id_to_mcbsp_ptr(0);
-        if (mcbsp->pdata->mux_signal)
-                mcbsp->pdata->mux_signal(mcbsp->dev, "fsr", src);
-}
-EXPORT_SYMBOL(omap2_mcbsp1_mux_fsr_src);
-
-#define max_thres(m)                    (mcbsp->pdata->buffer_size)
-#define valid_threshold(m, val)         ((val) <= max_thres(m))
-#define THRESHOLD_PROP_BUILDER(prop)                                    \
-static ssize_t prop##_show(struct device *dev,                          \
-                        struct device_attribute *attr, char *buf)       \
-{                                                                       \
-        struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);                \
-                                                                        \
-        return sprintf(buf, "%u\n", mcbsp->prop);                       \
-}                                                                       \
-                                                                        \
-static ssize_t prop##_store(struct device *dev,                         \
-                                struct device_attribute *attr,          \
-                                const char *buf, size_t size)           \
-{                                                                       \
-        struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);                \
-        unsigned long val;                                              \
-        int status;                                                     \
-                                                                        \
-        status = strict_strtoul(buf, 0, &val);                          \
-        if (status)                                                     \
-                return status;                                          \
-                                                                        \
-        if (!valid_threshold(mcbsp, val))                               \
-                return -EDOM;                                           \
-                                                                        \
-        mcbsp->prop = val;                                              \
-        return size;                                                    \
-}                                                                       \
-                                                                        \
-static DEVICE_ATTR(prop, 0644, prop##_show, prop##_store);
-
-THRESHOLD_PROP_BUILDER(max_tx_thres);
-THRESHOLD_PROP_BUILDER(max_rx_thres);
-
-static const char *dma_op_modes[] = {
-        "element", "threshold", "frame",
-};
-
-static ssize_t dma_op_mode_show(struct device *dev,
-                        struct device_attribute *attr, char *buf)
-{
-        struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
-        int dma_op_mode, i = 0;
-        ssize_t len = 0;
-        const char * const *s;
-
-        dma_op_mode = mcbsp->dma_op_mode;
-
-        for (s = &dma_op_modes[i]; i < ARRAY_SIZE(dma_op_modes); s++, i++) {
-                if (dma_op_mode == i)
-                        len += sprintf(buf + len, "[%s] ", *s);
-                else
-                        len += sprintf(buf + len, "%s ", *s);
-        }
-        len += sprintf(buf + len, "\n");
-
-        return len;
-}
-
-static ssize_t dma_op_mode_store(struct device *dev,
-                                struct device_attribute *attr,
-                                const char *buf, size_t size)
-{
-        struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
-        const char * const *s;
-        int i = 0;
-
-        for (s = &dma_op_modes[i]; i < ARRAY_SIZE(dma_op_modes); s++, i++)
-                if (sysfs_streq(buf, *s))
-                        break;
-
-        if (i == ARRAY_SIZE(dma_op_modes))
-                return -EINVAL;
-
-        spin_lock_irq(&mcbsp->lock);
-        if (!mcbsp->free) {
-                size = -EBUSY;
-                goto unlock;
-        }
-        mcbsp->dma_op_mode = i;
-
-unlock:
-        spin_unlock_irq(&mcbsp->lock);
-
-        return size;
-}
-
-static DEVICE_ATTR(dma_op_mode, 0644, dma_op_mode_show, dma_op_mode_store);
-
-static const struct attribute *additional_attrs[] = {
-        &dev_attr_max_tx_thres.attr,
-        &dev_attr_max_rx_thres.attr,
-        &dev_attr_dma_op_mode.attr,
-        NULL,
-};
-
-static const struct attribute_group additional_attr_group = {
-        .attrs = (struct attribute **)additional_attrs,
-};
-
-static ssize_t st_taps_show(struct device *dev,
-                            struct device_attribute *attr, char *buf)
-{
-        struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
-        struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
-        ssize_t status = 0;
-        int i;
-
-        spin_lock_irq(&mcbsp->lock);
-        for (i = 0; i < st_data->nr_taps; i++)
-                status += sprintf(&buf[status], (i ? ", %d" : "%d"),
-                                  st_data->taps[i]);
-        if (i)
-                status += sprintf(&buf[status], "\n");
-        spin_unlock_irq(&mcbsp->lock);
-
-        return status;
-}
-
-static ssize_t st_taps_store(struct device *dev,
-                             struct device_attribute *attr,
-                             const char *buf, size_t size)
-{
-        struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
-        struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
-        int val, tmp, status, i = 0;
-
-        spin_lock_irq(&mcbsp->lock);
-        memset(st_data->taps, 0, sizeof(st_data->taps));
-        st_data->nr_taps = 0;
-
-        do {
-                status = sscanf(buf, "%d%n", &val, &tmp);
-                if (status < 0 || status == 0) {
-                        size = -EINVAL;
-                        goto out;
-                }
-                if (val < -32768 || val > 32767) {
-                        size = -EINVAL;
-                        goto out;
-                }
-                st_data->taps[i++] = val;
-                buf += tmp;
-                if (*buf != ',')
-                        break;
-                buf++;
-        } while (1);
-
-        st_data->nr_taps = i;
-
-out:
-        spin_unlock_irq(&mcbsp->lock);
-
-        return size;
-}
-
-static DEVICE_ATTR(st_taps, 0644, st_taps_show, st_taps_store);
-
-static const struct attribute *sidetone_attrs[] = {
-        &dev_attr_st_taps.attr,
-        NULL,
-};
-
-static const struct attribute_group sidetone_attr_group = {
-        .attrs = (struct attribute **)sidetone_attrs,
-};
-
-static int __devinit omap_st_add(struct omap_mcbsp *mcbsp,
-                                 struct resource *res)
-{
-        struct omap_mcbsp_st_data *st_data;
-        int err;
-
-        st_data = kzalloc(sizeof(*mcbsp->st_data), GFP_KERNEL);
-        if (!st_data) {
-                err = -ENOMEM;
-                goto err1;
-        }
-
-        st_data->io_base_st = ioremap(res->start, resource_size(res));
-        if (!st_data->io_base_st) {
-                err = -ENOMEM;
-                goto err2;
-        }
-
-        err = sysfs_create_group(&mcbsp->dev->kobj, &sidetone_attr_group);
-        if (err)
-                goto err3;
-
-        mcbsp->st_data = st_data;
-        return 0;
-
-err3:
-        iounmap(st_data->io_base_st);
-err2:
-        kfree(st_data);
-err1:
-        return err;
-
-}
-
-static void __devexit omap_st_remove(struct omap_mcbsp *mcbsp)
-{
-        struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
-
-        sysfs_remove_group(&mcbsp->dev->kobj, &sidetone_attr_group);
-        iounmap(st_data->io_base_st);
-        kfree(st_data);
-}
-
-/*
- * McBSP1 and McBSP3 are directly mapped on 1610 and 1510.
- * 730 has only 2 McBSP, and both of them are MPU peripherals.
- */
-static int __devinit omap_mcbsp_probe(struct platform_device *pdev)
-{
-        struct omap_mcbsp_platform_data *pdata = pdev->dev.platform_data;
-        struct omap_mcbsp *mcbsp;
-        int id = pdev->id - 1;
-        struct resource *res;
-        int ret = 0;
-
-        if (!pdata) {
-                dev_err(&pdev->dev, "McBSP device initialized without"
-                                "platform data\n");
-                ret = -EINVAL;
-                goto exit;
-        }
-
-        dev_dbg(&pdev->dev, "Initializing OMAP McBSP (%d).\n", pdev->id);
-
-        if (id >= omap_mcbsp_count) {
-                dev_err(&pdev->dev, "Invalid McBSP device id (%d)\n", id);
-                ret = -EINVAL;
-                goto exit;
-        }
-
-        mcbsp = kzalloc(sizeof(struct omap_mcbsp), GFP_KERNEL);
-        if (!mcbsp) {
-                ret = -ENOMEM;
-                goto exit;
-        }
-
-        spin_lock_init(&mcbsp->lock);
-        mcbsp->id = id + 1;
-        mcbsp->free = true;
-
-        res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpu");
-        if (!res) {
-                res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-                if (!res) {
-                        dev_err(&pdev->dev, "%s:mcbsp%d has invalid memory"
-                                        "resource\n", __func__, pdev->id);
-                        ret = -ENOMEM;
-                        goto exit;
-                }
-        }
-        mcbsp->phys_base = res->start;
-        mcbsp->reg_cache_size = resource_size(res);
-        mcbsp->io_base = ioremap(res->start, resource_size(res));
-        if (!mcbsp->io_base) {
-                ret = -ENOMEM;
-                goto err_ioremap;
-        }
-
-        res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dma");
-        if (!res)
-                mcbsp->phys_dma_base = mcbsp->phys_base;
-        else
-                mcbsp->phys_dma_base = res->start;
-
-        mcbsp->tx_irq = platform_get_irq_byname(pdev, "tx");
-        mcbsp->rx_irq = platform_get_irq_byname(pdev, "rx");
-
-        /* From OMAP4 there will be a single irq line */
-        if (mcbsp->tx_irq == -ENXIO)
-                mcbsp->tx_irq = platform_get_irq(pdev, 0);
-
-        res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "rx");
-        if (!res) {
-                dev_err(&pdev->dev, "%s:mcbsp%d has invalid rx DMA channel\n",
-                                        __func__, pdev->id);
-                ret = -ENODEV;
-                goto err_res;
-        }
-        mcbsp->dma_rx_sync = res->start;
-
-        res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "tx");
-        if (!res) {
-                dev_err(&pdev->dev, "%s:mcbsp%d has invalid tx DMA channel\n",
-                                        __func__, pdev->id);
-                ret = -ENODEV;
-                goto err_res;
-        }
-        mcbsp->dma_tx_sync = res->start;
-
-        mcbsp->fclk = clk_get(&pdev->dev, "fck");
-        if (IS_ERR(mcbsp->fclk)) {
-                ret = PTR_ERR(mcbsp->fclk);
-                dev_err(&pdev->dev, "unable to get fck: %d\n", ret);
-                goto err_res;
-        }
-
-        mcbsp->pdata = pdata;
-        mcbsp->dev = &pdev->dev;
-        mcbsp_ptr[id] = mcbsp;
-        platform_set_drvdata(pdev, mcbsp);
-        pm_runtime_enable(mcbsp->dev);
-
-        mcbsp->dma_op_mode = MCBSP_DMA_MODE_ELEMENT;
-        if (mcbsp->pdata->buffer_size) {
-                /*
-                 * Initially configure the maximum thresholds to a safe value.
-                 * The McBSP FIFO usage with these values should not go under
-                 * 16 locations.
-                 * If the whole FIFO without safety buffer is used, than there
-                 * is a possibility that the DMA will be not able to push the
-                 * new data on time, causing channel shifts in runtime.
-                 */
-                mcbsp->max_tx_thres = max_thres(mcbsp) - 0x10;
-                mcbsp->max_rx_thres = max_thres(mcbsp) - 0x10;
-
-                ret = sysfs_create_group(&mcbsp->dev->kobj,
-                                         &additional_attr_group);
-                if (ret) {
-                        dev_err(mcbsp->dev,
-                                "Unable to create additional controls\n");
-                        goto err_thres;
-                }
-        } else {
-                mcbsp->max_tx_thres = -EINVAL;
-                mcbsp->max_rx_thres = -EINVAL;
-        }
-
-        res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "sidetone");
-        if (res) {
-                ret = omap_st_add(mcbsp, res);
-                if (ret) {
-                        dev_err(mcbsp->dev,
-                                "Unable to create sidetone controls\n");
-                        goto err_st;
-                }
-        }
-
-        return 0;
-
-err_st:
-        if (mcbsp->pdata->buffer_size)
-                sysfs_remove_group(&mcbsp->dev->kobj,
-                                   &additional_attr_group);
-err_thres:
-        clk_put(mcbsp->fclk);
-err_res:
-        iounmap(mcbsp->io_base);
-err_ioremap:
-        kfree(mcbsp);
-exit:
-        return ret;
-}
-
-static int __devexit omap_mcbsp_remove(struct platform_device *pdev)
-{
-        struct omap_mcbsp *mcbsp = platform_get_drvdata(pdev);
-
-        platform_set_drvdata(pdev, NULL);
-        if (mcbsp) {
-
-                if (mcbsp->pdata && mcbsp->pdata->ops &&
-                                mcbsp->pdata->ops->free)
-                        mcbsp->pdata->ops->free(mcbsp->id);
-
-                if (mcbsp->pdata->buffer_size)
-                        sysfs_remove_group(&mcbsp->dev->kobj,
-                                           &additional_attr_group);
-
-                if (mcbsp->st_data)
-                        omap_st_remove(mcbsp);
-
-                clk_put(mcbsp->fclk);
-
-                iounmap(mcbsp->io_base);
-                kfree(mcbsp);
-        }
-
-        return 0;
-}
-
-static struct platform_driver omap_mcbsp_driver = {
-        .probe          = omap_mcbsp_probe,
-        .remove         = __devexit_p(omap_mcbsp_remove),
-        .driver         = {
-                .name   = "omap-mcbsp",
-        },
-};
-
-int __init omap_mcbsp_init(void)
-{
-        /* Register the McBSP driver */
-        return platform_driver_register(&omap_mcbsp_driver);
-}
diff --git a/arch/arm/plat-omap/mux.c b/arch/arm/plat-omap/mux.c
index 0d4aa0d5876..cff8712122b 100644
--- a/arch/arm/plat-omap/mux.c
+++ b/arch/arm/plat-omap/mux.c
@@ -26,8 +26,11 @@
 #include <linux/init.h>
 #include <linux/kernel.h>
 #include <linux/io.h>
-#include <asm/system.h>
 #include <linux/spinlock.h>
+
+#include <asm/system.h>
+
+#include <plat/cpu.h>
 #include <plat/mux.h>
 
 #ifdef CONFIG_OMAP_MUX
diff --git a/arch/arm/plat-omap/omap-pm-noop.c b/arch/arm/plat-omap/omap-pm-noop.c
index 3dc3801aace..5a97b4d98d4 100644
--- a/arch/arm/plat-omap/omap-pm-noop.c
+++ b/arch/arm/plat-omap/omap-pm-noop.c
@@ -319,7 +319,7 @@ int omap_pm_get_dev_context_loss_count(struct device *dev)
         if (WARN_ON(!dev))
                 return -ENODEV;
 
-        if (dev->parent == &omap_device_parent) {
+        if (dev->pm_domain == &omap_device_pm_domain) {
                 count = omap_device_get_context_loss_count(pdev);
         } else {
                 WARN_ONCE(off_mode_enabled, "omap_pm: using dummy context loss counter; device %s should be converted to omap_device",
diff --git a/arch/arm/plat-omap/omap_device.c b/arch/arm/plat-omap/omap_device.c
index e8d98693d2d..d50cbc6385b 100644
--- a/arch/arm/plat-omap/omap_device.c
+++ b/arch/arm/plat-omap/omap_device.c
@@ -1,3 +1,4 @@
+
 /*
  * omap_device implementation
  *
@@ -97,14 +98,7 @@
 #define USE_WAKEUP_LAT                  0
 #define IGNORE_WAKEUP_LAT               1
 
-static int omap_device_register(struct platform_device *pdev);
 static int omap_early_device_register(struct platform_device *pdev);
-static struct omap_device *omap_device_alloc(struct platform_device *pdev,
-                                      struct omap_hwmod **ohs, int oh_cnt,
-                                      struct omap_device_pm_latency *pm_lats,
-                                      int pm_lats_cnt);
-static void omap_device_delete(struct omap_device *od);
-
 
 static struct omap_device_pm_latency omap_default_latency[] = {
         {
@@ -320,8 +314,6 @@ static void _add_hwmod_clocks_clkdev(struct omap_device *od,
 }
 
 
-static struct dev_pm_domain omap_device_pm_domain;
-
 /**
  * omap_device_build_from_dt - build an omap_device with multiple hwmods
  * @pdev_name: name of the platform_device driver to use
@@ -348,7 +340,7 @@ static int omap_device_build_from_dt(struct platform_device *pdev)
 
         oh_cnt = of_property_count_strings(node, "ti,hwmods");
         if (!oh_cnt || IS_ERR_VALUE(oh_cnt)) {
-                dev_warn(&pdev->dev, "No 'hwmods' to build omap_device\n");
+                dev_dbg(&pdev->dev, "No 'hwmods' to build omap_device\n");
                 return -ENODEV;
         }
 
@@ -509,7 +501,7 @@ static int omap_device_fill_resources(struct omap_device *od,
  *
  * Returns an struct omap_device pointer or ERR_PTR() on error;
  */
-static struct omap_device *omap_device_alloc(struct platform_device *pdev,
+struct omap_device *omap_device_alloc(struct platform_device *pdev,
                                         struct omap_hwmod **ohs, int oh_cnt,
                                         struct omap_device_pm_latency *pm_lats,
                                         int pm_lats_cnt)
@@ -591,7 +583,7 @@ oda_exit1:
         return ERR_PTR(ret);
 }
 
-static void omap_device_delete(struct omap_device *od)
+void omap_device_delete(struct omap_device *od)
 {
         if (!od)
                 return;
@@ -619,7 +611,7 @@ static void omap_device_delete(struct omap_device *od)
  * information.  Returns ERR_PTR(-EINVAL) if @oh is NULL; otherwise,
  * passes along the return value of omap_device_build_ss().
  */
-struct platform_device *omap_device_build(const char *pdev_name, int pdev_id,
+struct platform_device __init *omap_device_build(const char *pdev_name, int pdev_id,
                                       struct omap_hwmod *oh, void *pdata,
                                       int pdata_len,
                                       struct omap_device_pm_latency *pm_lats,
@@ -652,7 +644,7 @@ struct platform_device *omap_device_build(const char *pdev_name, int pdev_id,
  * platform_device record.  Returns an ERR_PTR() on error, or passes
  * along the return value of omap_device_register().
  */
-struct platform_device *omap_device_build_ss(const char *pdev_name, int pdev_id,
+struct platform_device __init *omap_device_build_ss(const char *pdev_name, int pdev_id,
                                          struct omap_hwmod **ohs, int oh_cnt,
                                          void *pdata, int pdata_len,
                                          struct omap_device_pm_latency *pm_lats,
@@ -717,7 +709,7 @@ odbs_exit:
  * platform_early_add_device() on the underlying platform_device.
  * Returns 0 by default.
  */
-static int omap_early_device_register(struct platform_device *pdev)
+static int __init omap_early_device_register(struct platform_device *pdev)
 {
         struct platform_device *devices[1];
 
@@ -762,14 +754,12 @@ static int _od_suspend_noirq(struct device *dev)
         struct omap_device *od = to_omap_device(pdev);
         int ret;
 
-        if (od->flags & OMAP_DEVICE_NO_IDLE_ON_SUSPEND)
-                return pm_generic_suspend_noirq(dev);
-
         ret = pm_generic_suspend_noirq(dev);
 
         if (!ret && !pm_runtime_status_suspended(dev)) {
                 if (pm_generic_runtime_suspend(dev) == 0) {
-                        omap_device_idle(pdev);
+                        if (!(od->flags & OMAP_DEVICE_NO_IDLE_ON_SUSPEND))
+                                omap_device_idle(pdev);
                         od->flags |= OMAP_DEVICE_SUSPENDED;
                 }
         }
@@ -782,13 +772,11 @@ static int _od_resume_noirq(struct device *dev)
         struct platform_device *pdev = to_platform_device(dev);
         struct omap_device *od = to_omap_device(pdev);
 
-        if (od->flags & OMAP_DEVICE_NO_IDLE_ON_SUSPEND)
-                return pm_generic_resume_noirq(dev);
-
         if ((od->flags & OMAP_DEVICE_SUSPENDED) &&
             !pm_runtime_status_suspended(dev)) {
                 od->flags &= ~OMAP_DEVICE_SUSPENDED;
-                omap_device_enable(pdev);
+                if (!(od->flags & OMAP_DEVICE_NO_IDLE_ON_SUSPEND))
+                        omap_device_enable(pdev);
                 pm_generic_runtime_resume(dev);
         }
 
@@ -799,7 +787,7 @@ static int _od_resume_noirq(struct device *dev)
 #define _od_resume_noirq NULL
 #endif
 
-static struct dev_pm_domain omap_device_pm_domain = {
+struct dev_pm_domain omap_device_pm_domain = {
         .ops = {
                 SET_RUNTIME_PM_OPS(_od_runtime_suspend, _od_runtime_resume,
                                    _od_runtime_idle)
@@ -817,11 +805,10 @@ static struct dev_pm_domain omap_device_pm_domain = {
  * platform_device_register() on the underlying platform_device.
  * Returns the return value of platform_device_register().
  */
-static int omap_device_register(struct platform_device *pdev)
+int omap_device_register(struct platform_device *pdev)
 {
         pr_debug("omap_device: %s: registering\n", pdev->name);
 
-        pdev->dev.parent = &omap_device_parent;
         pdev->dev.pm_domain = &omap_device_pm_domain;
         return platform_device_add(pdev);
 }
@@ -1130,11 +1117,6 @@ int omap_device_enable_clocks(struct omap_device *od)
         return 0;
 }
 
-struct device omap_device_parent = {
-        .init_name      = "omap",
-        .parent         = &platform_bus,
-};
-
 static struct notifier_block platform_nb = {
         .notifier_call = _omap_device_notifier_call,
 };
@@ -1142,6 +1124,6 @@ static struct notifier_block platform_nb = {
 static int __init omap_device_init(void)
 {
         bus_register_notifier(&platform_bus_type, &platform_nb);
-        return device_register(&omap_device_parent);
+        return 0;
 }
 core_initcall(omap_device_init);
diff --git a/arch/arm/plat-omap/sram.c b/arch/arm/plat-omap/sram.c
index 4243bdcc87b..eec98afa0f8 100644
--- a/arch/arm/plat-omap/sram.c
+++ b/arch/arm/plat-omap/sram.c
@@ -31,11 +31,10 @@
 
 #include "sram.h"
 
-/* XXX These "sideways" includes are a sign that something is wrong */
-#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
-# include "../mach-omap2/prm2xxx_3xxx.h"
-# include "../mach-omap2/sdrc.h"
-#endif
+/* XXX These "sideways" includes will disappear when sram.c becomes a driver */
+#include "../mach-omap2/iomap.h"
+#include "../mach-omap2/prm2xxx_3xxx.h"
+#include "../mach-omap2/sdrc.h"
 
 #define OMAP1_SRAM_PA           0x20000000
 #define OMAP2_SRAM_PUB_PA       (OMAP2_SRAM_PA + 0xf800)
@@ -86,7 +85,7 @@ static int is_sram_locked(void)
                         __raw_writel(0xCFDE, OMAP24XX_VA_READPERM0);  /* all i-read */
                         __raw_writel(0xCFDE, OMAP24XX_VA_WRITEPERM0); /* all i-write */
                 }
-                if (cpu_is_omap34xx()) {
+                if (cpu_is_omap34xx() && !cpu_is_am33xx()) {
                         __raw_writel(0xFFFF, OMAP34XX_VA_REQINFOPERM0); /* all q-vects */
                         __raw_writel(0xFFFF, OMAP34XX_VA_READPERM0);  /* all i-read */
                         __raw_writel(0xFFFF, OMAP34XX_VA_WRITEPERM0); /* all i-write */
@@ -124,7 +123,10 @@ static void __init omap_detect_sram(void)
                                 omap_sram_size = 0x800; /* 2K */
                         }
                 } else {
-                        if (cpu_is_omap34xx()) {
+                        if (cpu_is_am33xx()) {
+                                omap_sram_start = AM33XX_SRAM_PA;
+                                omap_sram_size = 0x10000; /* 64K */
+                        } else if (cpu_is_omap34xx()) {
                                 omap_sram_start = OMAP3_SRAM_PA;
                                 omap_sram_size = 0x10000; /* 64K */
                         } else if (cpu_is_omap44xx()) {
@@ -368,6 +370,11 @@ static inline int omap34xx_sram_init(void)
         return 0;
 }
 
+static inline int am33xx_sram_init(void)
+{
+        return 0;
+}
+
 int __init omap_sram_init(void)
 {
         omap_detect_sram();
@@ -379,6 +386,8 @@ int __init omap_sram_init(void)
                 omap242x_sram_init();
         else if (cpu_is_omap2430())
                 omap243x_sram_init();
+        else if (cpu_is_am33xx())
+                am33xx_sram_init();
         else if (cpu_is_omap34xx())
                 omap34xx_sram_init();
 
diff --git a/arch/arm/plat-omap/usb.c b/arch/arm/plat-omap/usb.c
index f3570884883..d2bbfd1cb0b 100644
--- a/arch/arm/plat-omap/usb.c
+++ b/arch/arm/plat-omap/usb.c
@@ -29,6 +29,10 @@
 #include <plat/usb.h>
 #include <plat/board.h>
 
+#include <mach/hardware.h>
+
+#include "../mach-omap2/common.h"
+
 #ifdef  CONFIG_ARCH_OMAP_OTG
 
 void __init
diff --git a/arch/arm/plat-s3c24xx/Kconfig b/arch/arm/plat-s3c24xx/Kconfig
index d8973ac46bc..21bf6adb919 100644
--- a/arch/arm/plat-s3c24xx/Kconfig
+++ b/arch/arm/plat-s3c24xx/Kconfig
@@ -4,7 +4,7 @@
 
 config PLAT_S3C24XX
         bool
-        depends on ARCH_S3C2410
+        depends on ARCH_S3C24XX
         default y
         select NO_IOPORT
         select ARCH_REQUIRE_GPIOLIB
@@ -44,12 +44,6 @@ config S3C2410_CLOCK
           Clock code for the S3C2410, and similar processors which
           is currently includes the S3C2410, S3C2440, S3C2442.
 
-config S3C2443_CLOCK
-        bool
-        help
-          Clock code for the S3C2443 and similar processors, which includes
-          the S3C2416 and S3C2450.
-
 config S3C24XX_DCLK
         bool
         help
@@ -76,15 +70,9 @@ config S3C24XX_GPIO_EXTRA128
           Add an extra 128 gpio numbers to the available GPIO pool. This is
           available for boards that need extra gpios for external devices.
 
-config PM_SIMTEC
-        bool
-        help
-          Common power management code for systems that are
-          compatible with the Simtec style of power management
-
-config S3C2410_DMA
+config S3C24XX_DMA
         bool "S3C2410 DMA support"
-        depends on ARCH_S3C2410
+        depends on ARCH_S3C24XX
         select S3C_DMA
         help
           S3C2410 DMA support. This is needed for drivers like sound which
@@ -93,31 +81,11 @@ config S3C2410_DMA
 
 config S3C2410_DMA_DEBUG
         bool "S3C2410 DMA support debug"
-        depends on ARCH_S3C2410 && S3C2410_DMA
+        depends on ARCH_S3C24XX && S3C2410_DMA
         help
           Enable debugging output for the DMA code. This option sends info
           to the kernel log, at priority KERN_DEBUG.
 
-# SPI default pin configuration code
-
-config S3C24XX_SPI_BUS0_GPE11_GPE12_GPE13
-        bool
-        help
-          SPI GPIO configuration code for BUS0 when connected to
-          GPE11, GPE12 and GPE13.
-
-config S3C24XX_SPI_BUS1_GPG5_GPG6_GPG7
-        bool
-        help
-          SPI GPIO configuration code for BUS 1 when connected to
-          GPG5, GPG6 and GPG7.
-
-config S3C24XX_SPI_BUS1_GPD8_GPD9_GPD10
-        bool
-        help
-          SPI GPIO configuration code for BUS 1 when connected to
-          GPD8, GPD9 and GPD10.
-
 # common code for s3c24xx based machines, such as the SMDKs.
 
 # cpu frequency items common between s3c2410 and s3c2440/s3c2442
@@ -145,21 +113,4 @@ config S3C2412_IOTIMING
           Intel node to select io timing code that is common to the s3c2412
           and the s3c2443.
 
-config MACH_SMDK
-        bool
-        help
-          Common machine code for SMDK2410 and SMDK2440
-
-config S3C24XX_SIMTEC_AUDIO
-        bool
-        depends on (ARCH_BAST || MACH_VR1000 || MACH_OSIRIS || MACH_ANUBIS)
-        default y
-        help
-          Add audio devices for common Simtec S3C24XX boards
-
-config S3C2410_SETUP_TS
-        bool
-        help
-          Compile in platform device definition for Samsung TouchScreen.
-
 endif
diff --git a/arch/arm/plat-s3c24xx/Makefile b/arch/arm/plat-s3c24xx/Makefile
index b2b01125de6..2467b800cc7 100644
--- a/arch/arm/plat-s3c24xx/Makefile
+++ b/arch/arm/plat-s3c24xx/Makefile
@@ -23,28 +23,11 @@ obj-$(CONFIG_CPU_FREQ_S3C24XX_DEBUGFS) += cpu-freq-debugfs.o
 
 # Architecture dependent builds
 
-obj-$(CONFIG_PM_SIMTEC)         += pm-simtec.o
 obj-$(CONFIG_PM)                += pm.o
 obj-$(CONFIG_PM)                += irq-pm.o
 obj-$(CONFIG_PM)                += sleep.o
 obj-$(CONFIG_S3C2410_CLOCK)     += s3c2410-clock.o
-obj-$(CONFIG_S3C2443_CLOCK)     += s3c2443-clock.o
-obj-$(CONFIG_S3C2410_DMA)       += dma.o
+obj-$(CONFIG_S3C24XX_DMA)       += dma.o
 obj-$(CONFIG_S3C2410_IOTIMING)  += s3c2410-iotiming.o
 obj-$(CONFIG_S3C2412_IOTIMING)  += s3c2412-iotiming.o
 obj-$(CONFIG_S3C2410_CPUFREQ_UTILS) += s3c2410-cpufreq-utils.o
-
-# device specific setup and/or initialisation
-obj-$(CONFIG_ARCH_S3C2410)      += setup-i2c.o
-obj-$(CONFIG_S3C2410_SETUP_TS)  += setup-ts.o
-
-# SPI gpio central GPIO functions
-
-obj-$(CONFIG_S3C24XX_SPI_BUS0_GPE11_GPE12_GPE13) += spi-bus0-gpe11_12_13.o
-obj-$(CONFIG_S3C24XX_SPI_BUS1_GPG5_GPG6_GPG7)    += spi-bus1-gpg5_6_7.o
-obj-$(CONFIG_S3C24XX_SPI_BUS1_GPD8_GPD9_GPD10)   += spi-bus1-gpd8_9_10.o
-
-# machine common support
-
-obj-$(CONFIG_MACH_SMDK)         += common-smdk.o
-obj-$(CONFIG_S3C24XX_SIMTEC_AUDIO)      += simtec-audio.o
diff --git a/arch/arm/plat-s3c24xx/cpu.c b/arch/arm/plat-s3c24xx/cpu.c
index 21f1fda8b66..32a09931350 100644
--- a/arch/arm/plat-s3c24xx/cpu.c
+++ b/arch/arm/plat-s3c24xx/cpu.c
@@ -32,6 +32,7 @@
 #include <linux/io.h>
 
 #include <mach/hardware.h>
+#include <mach/regs-clock.h>
 #include <asm/irq.h>
 #include <asm/cacheflush.h>
 
@@ -190,8 +191,34 @@ static unsigned long s3c24xx_read_idcode_v4(void)
         return __raw_readl(S3C2410_GSTATUS1);
 }
 
+static void s3c24xx_default_idle(void)
+{
+        unsigned long tmp;
+        int i;
+
+        /* idle the system by using the idle mode which will wait for an
+         * interrupt to happen before restarting the system.
+         */
+
+        /* Warning: going into idle state upsets jtag scanning */
+
+        __raw_writel(__raw_readl(S3C2410_CLKCON) | S3C2410_CLKCON_IDLE,
+                     S3C2410_CLKCON);
+
+        /* the samsung port seems to do a loop and then unset idle.. */
+        for (i = 0; i < 50; i++)
+                tmp += __raw_readl(S3C2410_CLKCON); /* ensure loop not optimised out */
+
+        /* this bit is not cleared on re-start... */
+
+        __raw_writel(__raw_readl(S3C2410_CLKCON) & ~S3C2410_CLKCON_IDLE,
+                     S3C2410_CLKCON);
+}
+
 void __init s3c24xx_init_io(struct map_desc *mach_desc, int size)
 {
+        arm_pm_idle = s3c24xx_default_idle;
+
         /* initialise the io descriptors we need for initialisation */
         iotable_init(mach_desc, size);
         iotable_init(s3c_iodesc, ARRAY_SIZE(s3c_iodesc));
diff --git a/arch/arm/plat-s3c24xx/spi-bus0-gpe11_12_13.c b/arch/arm/plat-s3c24xx/spi-bus0-gpe11_12_13.c
deleted file mode 100644
index 704175b0573..00000000000
--- a/arch/arm/plat-s3c24xx/spi-bus0-gpe11_12_13.c
+++ /dev/null
@@ -1,36 +0,0 @@
-/* linux/arch/arm/plat-s3c24xx/spi-bus0-gpe11_12_13.c
- *
- * Copyright (c) 2008 Simtec Electronics
- *      http://armlinux.simtec.co.uk/
- *      Ben Dooks <ben@simtec.co.uk>
- *
- * S3C24XX SPI - gpio configuration for bus 0 on gpe11,12,13
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License.
-*/
-
-#include <linux/kernel.h>
-#include <linux/gpio.h>
-
-#include <mach/spi.h>
-#include <mach/regs-gpio.h>
-
-void s3c24xx_spi_gpiocfg_bus0_gpe11_12_13(struct s3c2410_spi_info *spi,
-                                          int enable)
-{
-        if (enable) {
-                s3c_gpio_cfgpin(S3C2410_GPE(13), S3C2410_GPE13_SPICLK0);
-                s3c_gpio_cfgpin(S3C2410_GPE(12), S3C2410_GPE12_SPIMOSI0);
-                s3c_gpio_cfgpin(S3C2410_GPE(11), S3C2410_GPE11_SPIMISO0);
-                s3c2410_gpio_pullup(S3C2410_GPE(11), 0);
-                s3c2410_gpio_pullup(S3C2410_GPE(13), 0);
-        } else {
-                s3c_gpio_cfgpin(S3C2410_GPE(13), S3C2410_GPIO_INPUT);
-                s3c_gpio_cfgpin(S3C2410_GPE(11), S3C2410_GPIO_INPUT);
-                s3c_gpio_setpull(S3C2410_GPE(11), S3C_GPIO_PULL_NONE);
-                s3c_gpio_setpull(S3C2410_GPE(12), S3C_GPIO_PULL_NONE);
-                s3c_gpio_setpull(S3C2410_GPE(13), S3C_GPIO_PULL_NONE);
-        }
-}
diff --git a/arch/arm/plat-s3c24xx/spi-bus1-gpd8_9_10.c b/arch/arm/plat-s3c24xx/spi-bus1-gpd8_9_10.c
deleted file mode 100644
index 72457afd625..00000000000
--- a/arch/arm/plat-s3c24xx/spi-bus1-gpd8_9_10.c
+++ /dev/null
@@ -1,38 +0,0 @@
-/* linux/arch/arm/plat-s3c24xx/spi-bus0-gpd8_9_10.c
- *
- * Copyright (c) 2008 Simtec Electronics
- *      http://armlinux.simtec.co.uk/
- *      Ben Dooks <ben@simtec.co.uk>
- *
- * S3C24XX SPI - gpio configuration for bus 1 on gpd8,9,10
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License.
-*/
-
-#include <linux/kernel.h>
-#include <linux/gpio.h>
-
-#include <mach/spi.h>
-#include <mach/regs-gpio.h>
-
-void s3c24xx_spi_gpiocfg_bus1_gpd8_9_10(struct s3c2410_spi_info *spi,
-                                        int enable)
-{
-
-        printk(KERN_INFO "%s(%d)\n", __func__, enable);
-        if (enable) {
-                s3c_gpio_cfgpin(S3C2410_GPD(10), S3C2440_GPD10_SPICLK1);
-                s3c_gpio_cfgpin(S3C2410_GPD(9), S3C2440_GPD9_SPIMOSI1);
-                s3c_gpio_cfgpin(S3C2410_GPD(8), S3C2440_GPD8_SPIMISO1);
-                s3c2410_gpio_pullup(S3C2410_GPD(10), 0);
-                s3c2410_gpio_pullup(S3C2410_GPD(9), 0);
-        } else {
-                s3c_gpio_cfgpin(S3C2410_GPD(8), S3C2410_GPIO_INPUT);
-                s3c_gpio_cfgpin(S3C2410_GPD(9), S3C2410_GPIO_INPUT);
-                s3c_gpio_setpull(S3C2410_GPD(10), S3C_GPIO_PULL_NONE);
-                s3c_gpio_setpull(S3C2410_GPD(9), S3C_GPIO_PULL_NONE);
-                s3c_gpio_setpull(S3C2410_GPD(8), S3C_GPIO_PULL_NONE);
-        }
-}
diff --git a/arch/arm/plat-s3c24xx/spi-bus1-gpg5_6_7.c b/arch/arm/plat-s3c24xx/spi-bus1-gpg5_6_7.c
deleted file mode 100644
index c3972b645d1..00000000000
--- a/arch/arm/plat-s3c24xx/spi-bus1-gpg5_6_7.c
+++ /dev/null
@@ -1,36 +0,0 @@
-/* linux/arch/arm/plat-s3c24xx/spi-bus0-gpg5_6_7.c
- *
- * Copyright (c) 2008 Simtec Electronics
- *      http://armlinux.simtec.co.uk/
- *      Ben Dooks <ben@simtec.co.uk>
- *
- * S3C24XX SPI - gpio configuration for bus 1 on gpg5,6,7
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License.
-*/
-
-#include <linux/kernel.h>
-#include <linux/gpio.h>
-
-#include <mach/spi.h>
-#include <mach/regs-gpio.h>
-
-void s3c24xx_spi_gpiocfg_bus1_gpg5_6_7(struct s3c2410_spi_info *spi,
-                                       int enable)
-{
-        if (enable) {
-                s3c_gpio_cfgpin(S3C2410_GPG(7), S3C2410_GPG7_SPICLK1);
-                s3c_gpio_cfgpin(S3C2410_GPG(6), S3C2410_GPG6_SPIMOSI1);
-                s3c_gpio_cfgpin(S3C2410_GPG(5), S3C2410_GPG5_SPIMISO1);
-                s3c2410_gpio_pullup(S3C2410_GPG(5), 0);
-                s3c2410_gpio_pullup(S3C2410_GPG(6), 0);
-        } else {
-                s3c_gpio_cfgpin(S3C2410_GPG(7), S3C2410_GPIO_INPUT);
-                s3c_gpio_cfgpin(S3C2410_GPG(5), S3C2410_GPIO_INPUT);
-                s3c_gpio_setpull(S3C2410_GPG(5), S3C_GPIO_PULL_NONE);
-                s3c_gpio_setpull(S3C2410_GPG(6), S3C_GPIO_PULL_NONE);
-                s3c_gpio_setpull(S3C2410_GPG(7), S3C_GPIO_PULL_NONE);
-        }
-}
diff --git a/arch/arm/plat-s5p/Kconfig b/arch/arm/plat-s5p/Kconfig
index 8167ce66188..7a308699f81 100644
--- a/arch/arm/plat-s5p/Kconfig
+++ b/arch/arm/plat-s5p/Kconfig
@@ -80,6 +80,16 @@ config S5P_DEV_FIMC3
         help
           Compile in platform device definitions for FIMC controller 3
 
+config S5P_DEV_JPEG
+        bool
+        help
+          Compile in platform device definitions for JPEG codec
+
+config S5P_DEV_G2D
+        bool
+        help
+          Compile in platform device definitions for G2D device
+
 config S5P_DEV_FIMD0
         bool
         help
diff --git a/arch/arm/plat-s5p/irq-eint.c b/arch/arm/plat-s5p/irq-eint.c
index c496b359c37..139c050918c 100644
--- a/arch/arm/plat-s5p/irq-eint.c
+++ b/arch/arm/plat-s5p/irq-eint.c
@@ -200,7 +200,7 @@ static struct irq_chip s5p_irq_vic_eint = {
 #endif
 };
 
-int __init s5p_init_irq_eint(void)
+static int __init s5p_init_irq_eint(void)
 {
         int irq;
 
diff --git a/arch/arm/plat-s5p/irq-gpioint.c b/arch/arm/plat-s5p/irq-gpioint.c
index 1fdfaa4599c..82c7311017a 100644
--- a/arch/arm/plat-s5p/irq-gpioint.c
+++ b/arch/arm/plat-s5p/irq-gpioint.c
@@ -41,7 +41,7 @@ struct s5p_gpioint_bank {
         void                    (*handler)(unsigned int, struct irq_desc *);
 };
 
-LIST_HEAD(banks);
+static LIST_HEAD(banks);
 
 static int s5p_gpioint_set_type(struct irq_data *d, unsigned int type)
 {
diff --git a/arch/arm/plat-s5p/sleep.S b/arch/arm/plat-s5p/sleep.S
index 0fd591bfc9f..006bd01eda0 100644
--- a/arch/arm/plat-s5p/sleep.S
+++ b/arch/arm/plat-s5p/sleep.S
@@ -23,9 +23,18 @@
 */
 
 #include <linux/linkage.h>
-#include <asm/assembler.h>
+#include <asm/asm-offsets.h>
+#include <asm/hardware/cache-l2x0.h>
 
-        .text
+/*
+ *       The following code is located into the .data section. This is to
+ *       allow l2x0_regs_phys to be accessed with a relative load while we
+ *       can't rely on any MMU translation. We could have put l2x0_regs_phys
+ *       in the .text section as well, but some setups might insist on it to
+ *       be truly read-only. (Reference from: arch/arm/kernel/sleep.S)
+ */
+        .data
+        .align
 
         /*
          * sleep magic, to allow the bootloader to check for an valid
@@ -39,11 +48,34 @@
          * s3c_cpu_resume
          *
          * resume code entry for bootloader to call
-         *
-         * we must put this code here in the data segment as we have no
-         * other way of restoring the stack pointer after sleep, and we
-         * must not write to the code segment (code is read-only)
          */
 
 ENTRY(s3c_cpu_resume)
+#ifdef CONFIG_CACHE_L2X0
+        adr     r0, l2x0_regs_phys
+        ldr     r0, [r0]
+        ldr     r1, [r0, #L2X0_R_PHY_BASE]
+        ldr     r2, [r1, #L2X0_CTRL]
+        tst     r2, #0x1
+        bne     resume_l2on
+        ldr     r2, [r0, #L2X0_R_AUX_CTRL]
+        str     r2, [r1, #L2X0_AUX_CTRL]
+        ldr     r2, [r0, #L2X0_R_TAG_LATENCY]
+        str     r2, [r1, #L2X0_TAG_LATENCY_CTRL]
+        ldr     r2, [r0, #L2X0_R_DATA_LATENCY]
+        str     r2, [r1, #L2X0_DATA_LATENCY_CTRL]
+        ldr     r2, [r0, #L2X0_R_PREFETCH_CTRL]
+        str     r2, [r1, #L2X0_PREFETCH_CTRL]
+        ldr     r2, [r0, #L2X0_R_PWR_CTRL]
+        str     r2, [r1, #L2X0_POWER_CTRL]
+        mov     r2, #1
+        str     r2, [r1, #L2X0_CTRL]
+resume_l2on:
+#endif
         b       cpu_resume
+ENDPROC(s3c_cpu_resume)
+#ifdef CONFIG_CACHE_L2X0
+        .globl l2x0_regs_phys
+l2x0_regs_phys:
+        .long   0
+#endif
diff --git a/arch/arm/plat-samsung/Kconfig b/arch/arm/plat-samsung/Kconfig
index 6a2abe67c8b..71553f41001 100644
--- a/arch/arm/plat-samsung/Kconfig
+++ b/arch/arm/plat-samsung/Kconfig
@@ -205,7 +205,7 @@ config S3C_DEV_USB_HSOTG
 
 config S3C_DEV_WDT
         bool
-        default y if ARCH_S3C2410
+        default y if ARCH_S3C24XX
         help
           Complie in platform device definition for Watchdog Timer
 
@@ -264,7 +264,7 @@ config SAMSUNG_DEV_KEYPAD
 
 config SAMSUNG_DEV_PWM
         bool
-        default y if ARCH_S3C2410
+        default y if ARCH_S3C24XX
         help
           Compile in platform device definition for PWM Timer
 
diff --git a/arch/arm/plat-samsung/clock.c b/arch/arm/plat-samsung/clock.c
index 10f71179071..65c5eca475e 100644
--- a/arch/arm/plat-samsung/clock.c
+++ b/arch/arm/plat-samsung/clock.c
@@ -84,31 +84,35 @@ static int clk_null_enable(struct clk *clk, int enable)
 
 int clk_enable(struct clk *clk)
 {
+        unsigned long flags;
+
         if (IS_ERR(clk) || clk == NULL)
                 return -EINVAL;
 
         clk_enable(clk->parent);
 
-        spin_lock(&clocks_lock);
+        spin_lock_irqsave(&clocks_lock, flags);
 
         if ((clk->usage++) == 0)
                 (clk->enable)(clk, 1);
 
-        spin_unlock(&clocks_lock);
+        spin_unlock_irqrestore(&clocks_lock, flags);
         return 0;
 }
 
 void clk_disable(struct clk *clk)
 {
+        unsigned long flags;
+
         if (IS_ERR(clk) || clk == NULL)
                 return;
 
-        spin_lock(&clocks_lock);
+        spin_lock_irqsave(&clocks_lock, flags);
 
         if ((--clk->usage) == 0)
                 (clk->enable)(clk, 0);
 
-        spin_unlock(&clocks_lock);
+        spin_unlock_irqrestore(&clocks_lock, flags);
         clk_disable(clk->parent);
 }
 
diff --git a/arch/arm/plat-samsung/dev-backlight.c b/arch/arm/plat-samsung/dev-backlight.c
index a976c023b28..5f197dcaf10 100644
--- a/arch/arm/plat-samsung/dev-backlight.c
+++ b/arch/arm/plat-samsung/dev-backlight.c
@@ -77,7 +77,7 @@ static struct platform_device samsung_dfl_bl_device __initdata = {
  * @gpio_info:  structure containing GPIO info for PWM timer
  * @bl_data:    structure containing Backlight control data
  */
-void samsung_bl_set(struct samsung_bl_gpio_info *gpio_info,
+void __init samsung_bl_set(struct samsung_bl_gpio_info *gpio_info,
         struct platform_pwm_backlight_data *bl_data)
 {
         int ret = 0;
@@ -115,6 +115,8 @@ void samsung_bl_set(struct samsung_bl_gpio_info *gpio_info,
                 samsung_bl_data->init = bl_data->init;
         if (bl_data->notify)
                 samsung_bl_data->notify = bl_data->notify;
+        if (bl_data->notify_after)
+                samsung_bl_data->notify_after = bl_data->notify_after;
         if (bl_data->exit)
                 samsung_bl_data->exit = bl_data->exit;
         if (bl_data->check_fb)
diff --git a/arch/arm/plat-samsung/devs.c b/arch/arm/plat-samsung/devs.c
index d21d744e4d9..8b928f9bc1c 100644
--- a/arch/arm/plat-samsung/devs.c
+++ b/arch/arm/plat-samsung/devs.c
@@ -57,6 +57,7 @@
 #include <plat/sdhci.h>
 #include <plat/ts.h>
 #include <plat/udc.h>
+#include <plat/udc-hs.h>
 #include <plat/usb-control.h>
 #include <plat/usb-phy.h>
 #include <plat/regs-iic.h>
@@ -267,6 +268,52 @@ struct platform_device s5p_device_fimc3 = {
 };
 #endif /* CONFIG_S5P_DEV_FIMC3 */
 
+/* G2D */
+
+#ifdef CONFIG_S5P_DEV_G2D
+static struct resource s5p_g2d_resource[] = {
+        [0] = {
+                .start  = S5P_PA_G2D,
+                .end    = S5P_PA_G2D + SZ_4K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = IRQ_2D,
+                .end    = IRQ_2D,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+struct platform_device s5p_device_g2d = {
+        .name           = "s5p-g2d",
+        .id             = 0,
+        .num_resources  = ARRAY_SIZE(s5p_g2d_resource),
+        .resource       = s5p_g2d_resource,
+        .dev            = {
+                .dma_mask               = &samsung_device_dma_mask,
+                .coherent_dma_mask      = DMA_BIT_MASK(32),
+        },
+};
+#endif /* CONFIG_S5P_DEV_G2D */
+
+#ifdef CONFIG_S5P_DEV_JPEG
+static struct resource s5p_jpeg_resource[] = {
+        [0] = DEFINE_RES_MEM(S5P_PA_JPEG, SZ_4K),
+        [1] = DEFINE_RES_IRQ(IRQ_JPEG),
+};
+
+struct platform_device s5p_device_jpeg = {
+        .name           = "s5p-jpeg",
+        .id             = 0,
+        .num_resources  = ARRAY_SIZE(s5p_jpeg_resource),
+        .resource       = s5p_jpeg_resource,
+        .dev            = {
+                .dma_mask               = &samsung_device_dma_mask,
+                .coherent_dma_mask      = DMA_BIT_MASK(32),
+        },
+};
+#endif /*  CONFIG_S5P_DEV_JPEG */
+
 /* FIMD0 */
 
 #ifdef CONFIG_S5P_DEV_FIMD0
@@ -744,17 +791,6 @@ struct platform_device s3c_device_iis = {
 };
 #endif /* CONFIG_PLAT_S3C24XX */
 
-#ifdef CONFIG_CPU_S3C2440
-struct platform_device s3c2412_device_iis = {
-        .name           = "s3c2412-iis",
-        .id             = -1,
-        .dev            = {
-                .dma_mask               = &samsung_device_dma_mask,
-                .coherent_dma_mask      = DMA_BIT_MASK(32),
-        }
-};
-#endif /* CONFIG_CPU_S3C2440 */
-
 /* IDE CFCON */
 
 #ifdef CONFIG_SAMSUNG_DEV_IDE
@@ -769,7 +805,7 @@ struct platform_device s3c_device_cfcon = {
         .resource       = s3c_cfcon_resource,
 };
 
-void s3c_ide_set_platdata(struct s3c_ide_platdata *pdata)
+void __init s3c_ide_set_platdata(struct s3c_ide_platdata *pdata)
 {
         s3c_set_platdata(pdata, sizeof(struct s3c_ide_platdata),
                          &s3c_device_cfcon);
@@ -887,7 +923,7 @@ struct platform_device s5p_device_mfc_r = {
 
 #ifdef CONFIG_S5P_DEV_CSIS0
 static struct resource s5p_mipi_csis0_resource[] = {
-        [0] = DEFINE_RES_MEM(S5P_PA_MIPI_CSIS0, SZ_4K),
+        [0] = DEFINE_RES_MEM(S5P_PA_MIPI_CSIS0, SZ_16K),
         [1] = DEFINE_RES_IRQ(IRQ_MIPI_CSIS0),
 };
 
@@ -901,7 +937,7 @@ struct platform_device s5p_device_mipi_csis0 = {
 
 #ifdef CONFIG_S5P_DEV_CSIS1
 static struct resource s5p_mipi_csis1_resource[] = {
-        [0] = DEFINE_RES_MEM(S5P_PA_MIPI_CSIS1, SZ_4K),
+        [0] = DEFINE_RES_MEM(S5P_PA_MIPI_CSIS1, SZ_16K),
         [1] = DEFINE_RES_IRQ(IRQ_MIPI_CSIS1),
 };
 
@@ -1049,7 +1085,7 @@ struct platform_device s3c64xx_device_onenand1 = {
         .resource       = s3c64xx_onenand1_resources,
 };
 
-void s3c64xx_onenand1_set_platdata(struct onenand_platform_data *pdata)
+void __init s3c64xx_onenand1_set_platdata(struct onenand_platform_data *pdata)
 {
         s3c_set_platdata(pdata, sizeof(struct onenand_platform_data),
                          &s3c64xx_device_onenand1);
@@ -1078,7 +1114,7 @@ static struct resource s5p_pmu_resource[] = {
         DEFINE_RES_IRQ(IRQ_PMU)
 };
 
-struct platform_device s5p_device_pmu = {
+static struct platform_device s5p_device_pmu = {
         .name           = "arm-pmu",
         .id             = ARM_PMU_DEVICE_CPU,
         .num_resources  = ARRAY_SIZE(s5p_pmu_resource),
@@ -1423,6 +1459,19 @@ struct platform_device s3c_device_usb_hsotg = {
                 .coherent_dma_mask      = DMA_BIT_MASK(32),
         },
 };
+
+void __init s3c_hsotg_set_platdata(struct s3c_hsotg_plat *pd)
+{
+        struct s3c_hsotg_plat *npd;
+
+        npd = s3c_set_platdata(pd, sizeof(struct s3c_hsotg_plat),
+                        &s3c_device_usb_hsotg);
+
+        if (!npd->phy_init)
+                npd->phy_init = s5p_usb_phy_init;
+        if (!npd->phy_exit)
+                npd->phy_exit = s5p_usb_phy_exit;
+}
 #endif /* CONFIG_S3C_DEV_USB_HSOTG */
 
 /* USB High Spped 2.0 Device (Gadget) */
diff --git a/arch/arm/plat-samsung/dma-ops.c b/arch/arm/plat-samsung/dma-ops.c
index 0747c77a2fd..301d9c319d0 100644
--- a/arch/arm/plat-samsung/dma-ops.c
+++ b/arch/arm/plat-samsung/dma-ops.c
@@ -116,7 +116,7 @@ static inline int samsung_dmadev_flush(unsigned ch)
         return dmaengine_terminate_all((struct dma_chan *)ch);
 }
 
-struct samsung_dma_ops dmadev_ops = {
+static struct samsung_dma_ops dmadev_ops = {
         .request        = samsung_dmadev_request,
         .release        = samsung_dmadev_release,
         .prepare        = samsung_dmadev_prepare,
diff --git a/arch/arm/plat-samsung/include/plat/audio-simtec.h b/arch/arm/plat-samsung/include/plat/audio-simtec.h
index 5345364e742..376af5286a3 100644
--- a/arch/arm/plat-samsung/include/plat/audio-simtec.h
+++ b/arch/arm/plat-samsung/include/plat/audio-simtec.h
@@ -32,6 +32,3 @@ struct s3c24xx_audio_simtec_pdata {
 
         void    (*startup)(void);
 };
-
-extern int simtec_audio_add(const char *codec_name, bool has_lr_routing,
-                            struct s3c24xx_audio_simtec_pdata *pdata);
diff --git a/arch/arm/plat-samsung/include/plat/clock.h b/arch/arm/plat-samsung/include/plat/clock.h
index 73c66d4d10f..a62753dc15b 100644
--- a/arch/arm/plat-samsung/include/plat/clock.h
+++ b/arch/arm/plat-samsung/include/plat/clock.h
@@ -79,6 +79,10 @@ extern struct clk clk_epll;
 extern struct clk clk_xtal;
 extern struct clk clk_ext;
 
+/* S3C2443/S3C2416 specific clocks */
+extern struct clksrc_clk clk_epllref;
+extern struct clksrc_clk clk_esysclk;
+
 /* S3C64XX specific clocks */
 extern struct clk clk_h2;
 extern struct clk clk_27m;
@@ -114,7 +118,23 @@ extern void s3c24xx_setup_clocks(unsigned long fclk,
 extern void s3c2410_setup_clocks(void);
 extern void s3c2412_setup_clocks(void);
 extern void s3c244x_setup_clocks(void);
-extern void s3c2443_setup_clocks(void);
+
+/* S3C2410 specific clock functions */
+
+extern int s3c2410_baseclk_add(void);
+
+/* S3C2443/S3C2416 specific clock functions */
+
+typedef unsigned int (*pll_fn)(unsigned int reg, unsigned int base);
+
+extern void s3c2443_common_setup_clocks(pll_fn get_mpll);
+extern void s3c2443_common_init_clocks(int xtal, pll_fn get_mpll,
+                                       unsigned int *divs, int nr_divs,
+                                       int divmask);
+
+extern int s3c2443_clkcon_enable_h(struct clk *clk, int enable);
+extern int s3c2443_clkcon_enable_p(struct clk *clk, int enable);
+extern int s3c2443_clkcon_enable_s(struct clk *clk, int enable);
 
 /* S3C64XX specific functions and clocks */
 
diff --git a/arch/arm/plat-samsung/include/plat/devs.h b/arch/arm/plat-samsung/include/plat/devs.h
index 4214ea0ff8f..5e7972de3ed 100644
--- a/arch/arm/plat-samsung/include/plat/devs.h
+++ b/arch/arm/plat-samsung/include/plat/devs.h
@@ -79,6 +79,8 @@ extern struct platform_device s5p_device_fimc1;
 extern struct platform_device s5p_device_fimc2;
 extern struct platform_device s5p_device_fimc3;
 extern struct platform_device s5p_device_fimc_md;
+extern struct platform_device s5p_device_jpeg;
+extern struct platform_device s5p_device_g2d;
 extern struct platform_device s5p_device_fimd0;
 extern struct platform_device s5p_device_hdmi;
 extern struct platform_device s5p_device_i2c_hdmiphy;
diff --git a/arch/arm/plat-samsung/include/plat/dma-pl330.h b/arch/arm/plat-samsung/include/plat/dma-pl330.h
index c5eaad529de..0670f37aaae 100644
--- a/arch/arm/plat-samsung/include/plat/dma-pl330.h
+++ b/arch/arm/plat-samsung/include/plat/dma-pl330.h
@@ -82,6 +82,22 @@ enum dma_ch {
         DMACH_SLIMBUS4_TX,
         DMACH_SLIMBUS5_RX,
         DMACH_SLIMBUS5_TX,
+        DMACH_MIPI_HSI0,
+        DMACH_MIPI_HSI1,
+        DMACH_MIPI_HSI2,
+        DMACH_MIPI_HSI3,
+        DMACH_MIPI_HSI4,
+        DMACH_MIPI_HSI5,
+        DMACH_MIPI_HSI6,
+        DMACH_MIPI_HSI7,
+        DMACH_MTOM_0,
+        DMACH_MTOM_1,
+        DMACH_MTOM_2,
+        DMACH_MTOM_3,
+        DMACH_MTOM_4,
+        DMACH_MTOM_5,
+        DMACH_MTOM_6,
+        DMACH_MTOM_7,
         /* END Marker, also used to denote a reserved channel */
         DMACH_MAX,
 };
diff --git a/arch/arm/plat-samsung/include/plat/regs-dma.h b/arch/arm/plat-samsung/include/plat/regs-dma.h
index 178bccbe480..a7d622ef16a 100644
--- a/arch/arm/plat-samsung/include/plat/regs-dma.h
+++ b/arch/arm/plat-samsung/include/plat/regs-dma.h
@@ -119,7 +119,7 @@
 #define S3C2412_DMAREQSEL_UART2_1       S3C2412_DMAREQSEL_SRC(24)
 #endif /* CONFIG_CPU_S3C2412 */
 
-#ifdef CONFIG_CPU_S3C2443
+#if defined(CONFIG_CPU_S3C2416) || defined(CONFIG_CPU_S3C2443)
 
 #define S3C2443_DMAREQSEL_SRC(x)        ((x) << 1)
 
diff --git a/arch/arm/plat-samsung/include/plat/regs-fb.h b/arch/arm/plat-samsung/include/plat/regs-fb.h
index 8f39aa5b26e..9a78012d6f4 100644
--- a/arch/arm/plat-samsung/include/plat/regs-fb.h
+++ b/arch/arm/plat-samsung/include/plat/regs-fb.h
@@ -91,6 +91,9 @@
 #define VIDCON1_VSTATUS_BACKPORCH               (0x1 << 13)
 #define VIDCON1_VSTATUS_ACTIVE                  (0x2 << 13)
 #define VIDCON1_VSTATUS_FRONTPORCH              (0x0 << 13)
+#define VIDCON1_VCLK_MASK                       (0x3 << 9)
+#define VIDCON1_VCLK_HOLD                       (0x0 << 9)
+#define VIDCON1_VCLK_RUN                        (0x1 << 9)
 
 #define VIDCON1_INV_VCLK                        (1 << 7)
 #define VIDCON1_INV_HSYNC                       (1 << 6)
@@ -164,15 +167,17 @@
 #define VIDTCON1_HSPW(_x)                       ((_x) << 0)
 
 #define VIDTCON2                                (0x18)
+#define VIDTCON2_LINEVAL_E(_x)                  ((((_x) & 0x800) >> 11) << 23)
 #define VIDTCON2_LINEVAL_MASK                   (0x7ff << 11)
 #define VIDTCON2_LINEVAL_SHIFT                  (11)
 #define VIDTCON2_LINEVAL_LIMIT                  (0x7ff)
-#define VIDTCON2_LINEVAL(_x)                    ((_x) << 11)
+#define VIDTCON2_LINEVAL(_x)                    (((_x) & 0x7ff) << 11)
 
+#define VIDTCON2_HOZVAL_E(_x)                   ((((_x) & 0x800) >> 11) << 22)
 #define VIDTCON2_HOZVAL_MASK                    (0x7ff << 0)
 #define VIDTCON2_HOZVAL_SHIFT                   (0)
 #define VIDTCON2_HOZVAL_LIMIT                   (0x7ff)
-#define VIDTCON2_HOZVAL(_x)                     ((_x) << 0)
+#define VIDTCON2_HOZVAL(_x)                     (((_x) & 0x7ff) << 0)
 
 /* WINCONx */
 
@@ -228,25 +233,29 @@
 /* Local input channels (windows 0-2) */
 #define SHADOWCON_CHx_LOCAL_ENABLE(_win)        (1 << (5 + (_win)))
 
+#define VIDOSDxA_TOPLEFT_X_E(_x)                ((((_x) & 0x800) >> 11) << 23)
 #define VIDOSDxA_TOPLEFT_X_MASK                 (0x7ff << 11)
 #define VIDOSDxA_TOPLEFT_X_SHIFT                (11)
 #define VIDOSDxA_TOPLEFT_X_LIMIT                (0x7ff)
-#define VIDOSDxA_TOPLEFT_X(_x)                  ((_x) << 11)
+#define VIDOSDxA_TOPLEFT_X(_x)                  (((_x) & 0x7ff) << 11)
 
+#define VIDOSDxA_TOPLEFT_Y_E(_x)                ((((_x) & 0x800) >> 11) << 22)
 #define VIDOSDxA_TOPLEFT_Y_MASK                 (0x7ff << 0)
 #define VIDOSDxA_TOPLEFT_Y_SHIFT                (0)
 #define VIDOSDxA_TOPLEFT_Y_LIMIT                (0x7ff)
-#define VIDOSDxA_TOPLEFT_Y(_x)                  ((_x) << 0)
+#define VIDOSDxA_TOPLEFT_Y(_x)                  (((_x) & 0x7ff) << 0)
 
+#define VIDOSDxB_BOTRIGHT_X_E(_x)               ((((_x) & 0x800) >> 11) << 23)
 #define VIDOSDxB_BOTRIGHT_X_MASK                (0x7ff << 11)
 #define VIDOSDxB_BOTRIGHT_X_SHIFT               (11)
 #define VIDOSDxB_BOTRIGHT_X_LIMIT               (0x7ff)
-#define VIDOSDxB_BOTRIGHT_X(_x)                 ((_x) << 11)
+#define VIDOSDxB_BOTRIGHT_X(_x)                 (((_x) & 0x7ff) << 11)
 
+#define VIDOSDxB_BOTRIGHT_Y_E(_x)               ((((_x) & 0x800) >> 11) << 22)
 #define VIDOSDxB_BOTRIGHT_Y_MASK                (0x7ff << 0)
 #define VIDOSDxB_BOTRIGHT_Y_SHIFT               (0)
 #define VIDOSDxB_BOTRIGHT_Y_LIMIT               (0x7ff)
-#define VIDOSDxB_BOTRIGHT_Y(_x)                 ((_x) << 0)
+#define VIDOSDxB_BOTRIGHT_Y(_x)                 (((_x) & 0x7ff) << 0)
 
 /* For VIDOSD[1..4]C */
 #define VIDISD14C_ALPHA0_R(_x)                  ((_x) << 20)
@@ -278,15 +287,17 @@
 #define VIDW_BUF_END1(_buff)                    (0xD4 + ((_buff) * 8))
 #define VIDW_BUF_SIZE(_buff)                    (0x100 + ((_buff) * 4))
 
+#define VIDW_BUF_SIZE_OFFSET_E(_x)              ((((_x) & 0x2000) >> 13) << 27)
 #define VIDW_BUF_SIZE_OFFSET_MASK               (0x1fff << 13)
 #define VIDW_BUF_SIZE_OFFSET_SHIFT              (13)
 #define VIDW_BUF_SIZE_OFFSET_LIMIT              (0x1fff)
-#define VIDW_BUF_SIZE_OFFSET(_x)                ((_x) << 13)
+#define VIDW_BUF_SIZE_OFFSET(_x)                (((_x) & 0x1fff) << 13)
 
+#define VIDW_BUF_SIZE_PAGEWIDTH_E(_x)           ((((_x) & 0x2000) >> 13) << 26)
 #define VIDW_BUF_SIZE_PAGEWIDTH_MASK            (0x1fff << 0)
 #define VIDW_BUF_SIZE_PAGEWIDTH_SHIFT           (0)
 #define VIDW_BUF_SIZE_PAGEWIDTH_LIMIT           (0x1fff)
-#define VIDW_BUF_SIZE_PAGEWIDTH(_x)             ((_x) << 0)
+#define VIDW_BUF_SIZE_PAGEWIDTH(_x)             (((_x) & 0x1fff) << 0)
 
 /* Interrupt controls and status */
 
@@ -384,3 +395,9 @@
 #define WPALCON_W0PAL_16BPP_A555                (0x5 << 0)
 #define WPALCON_W0PAL_16BPP_565                 (0x6 << 0)
 
+/* Blending equation control */
+#define BLENDCON                                (0x260)
+#define BLENDCON_NEW_MASK                       (1 << 0)
+#define BLENDCON_NEW_8BIT_ALPHA_VALUE           (1 << 0)
+#define BLENDCON_NEW_4BIT_ALPHA_VALUE           (0 << 0)
+
diff --git a/arch/arm/plat-samsung/include/plat/regs-rtc.h b/arch/arm/plat-samsung/include/plat/regs-rtc.h
index 30b7cc14cef..0f8263e93ee 100644
--- a/arch/arm/plat-samsung/include/plat/regs-rtc.h
+++ b/arch/arm/plat-samsung/include/plat/regs-rtc.h
@@ -18,51 +18,54 @@
 #define S3C2410_INTP_ALM        (1 << 1)
 #define S3C2410_INTP_TIC        (1 << 0)
 
-#define S3C2410_RTCCON        S3C2410_RTCREG(0x40)
-#define S3C2410_RTCCON_RTCEN  (1<<0)
-#define S3C2410_RTCCON_CLKSEL (1<<1)
-#define S3C2410_RTCCON_CNTSEL (1<<2)
-#define S3C2410_RTCCON_CLKRST (1<<3)
-#define S3C64XX_RTCCON_TICEN  (1<<8)
+#define S3C2410_RTCCON          S3C2410_RTCREG(0x40)
+#define S3C2410_RTCCON_RTCEN    (1 << 0)
+#define S3C2410_RTCCON_CNTSEL   (1 << 2)
+#define S3C2410_RTCCON_CLKRST   (1 << 3)
+#define S3C2443_RTCCON_TICSEL   (1 << 4)
+#define S3C64XX_RTCCON_TICEN    (1 << 8)
 
-#define S3C64XX_RTCCON_TICMSK (0xF<<7)
-#define S3C64XX_RTCCON_TICSHT (7)
+#define S3C2410_TICNT           S3C2410_RTCREG(0x44)
+#define S3C2410_TICNT_ENABLE    (1 << 7)
 
-#define S3C2410_TICNT         S3C2410_RTCREG(0x44)
-#define S3C2410_TICNT_ENABLE  (1<<7)
+/* S3C2443: tick count is 15 bit wide
+ * TICNT[6:0] contains upper 7 bits
+ * TICNT1[7:0] contains lower 8 bits
+ */
+#define S3C2443_TICNT_PART(x)   ((x & 0x7f00) >> 8)
+#define S3C2443_TICNT1          S3C2410_RTCREG(0x4C)
+#define S3C2443_TICNT1_PART(x)  (x & 0xff)
 
-#define S3C2410_RTCALM        S3C2410_RTCREG(0x50)
-#define S3C2410_RTCALM_ALMEN  (1<<6)
-#define S3C2410_RTCALM_YEAREN (1<<5)
-#define S3C2410_RTCALM_MONEN  (1<<4)
-#define S3C2410_RTCALM_DAYEN  (1<<3)
-#define S3C2410_RTCALM_HOUREN (1<<2)
-#define S3C2410_RTCALM_MINEN  (1<<1)
-#define S3C2410_RTCALM_SECEN  (1<<0)
+/* S3C2416: tick count is 32 bit wide
+ * TICNT[6:0] contains bits [14:8]
+ * TICNT1[7:0] contains lower 8 bits
+ * TICNT2[16:0] contains upper 17 bits
+ */
+#define S3C2416_TICNT2          S3C2410_RTCREG(0x48)
+#define S3C2416_TICNT2_PART(x)  ((x & 0xffff8000) >> 15)
 
-#define S3C2410_RTCALM_ALL \
-  S3C2410_RTCALM_ALMEN | S3C2410_RTCALM_YEAREN | S3C2410_RTCALM_MONEN |\
-  S3C2410_RTCALM_DAYEN | S3C2410_RTCALM_HOUREN | S3C2410_RTCALM_MINEN |\
-  S3C2410_RTCALM_SECEN
+#define S3C2410_RTCALM          S3C2410_RTCREG(0x50)
+#define S3C2410_RTCALM_ALMEN    (1 << 6)
+#define S3C2410_RTCALM_YEAREN   (1 << 5)
+#define S3C2410_RTCALM_MONEN    (1 << 4)
+#define S3C2410_RTCALM_DAYEN    (1 << 3)
+#define S3C2410_RTCALM_HOUREN   (1 << 2)
+#define S3C2410_RTCALM_MINEN    (1 << 1)
+#define S3C2410_RTCALM_SECEN    (1 << 0)
 
+#define S3C2410_ALMSEC          S3C2410_RTCREG(0x54)
+#define S3C2410_ALMMIN          S3C2410_RTCREG(0x58)
+#define S3C2410_ALMHOUR         S3C2410_RTCREG(0x5c)
 
-#define S3C2410_ALMSEC        S3C2410_RTCREG(0x54)
-#define S3C2410_ALMMIN        S3C2410_RTCREG(0x58)
-#define S3C2410_ALMHOUR       S3C2410_RTCREG(0x5c)
-
-#define S3C2410_ALMDATE       S3C2410_RTCREG(0x60)
-#define S3C2410_ALMMON        S3C2410_RTCREG(0x64)
-#define S3C2410_ALMYEAR       S3C2410_RTCREG(0x68)
-
-#define S3C2410_RTCRST        S3C2410_RTCREG(0x6c)
-
-#define S3C2410_RTCSEC        S3C2410_RTCREG(0x70)
-#define S3C2410_RTCMIN        S3C2410_RTCREG(0x74)
-#define S3C2410_RTCHOUR       S3C2410_RTCREG(0x78)
-#define S3C2410_RTCDATE       S3C2410_RTCREG(0x7c)
-#define S3C2410_RTCDAY        S3C2410_RTCREG(0x80)
-#define S3C2410_RTCMON        S3C2410_RTCREG(0x84)
-#define S3C2410_RTCYEAR       S3C2410_RTCREG(0x88)
+#define S3C2410_ALMDATE         S3C2410_RTCREG(0x60)
+#define S3C2410_ALMMON          S3C2410_RTCREG(0x64)
+#define S3C2410_ALMYEAR         S3C2410_RTCREG(0x68)
 
+#define S3C2410_RTCSEC          S3C2410_RTCREG(0x70)
+#define S3C2410_RTCMIN          S3C2410_RTCREG(0x74)
+#define S3C2410_RTCHOUR         S3C2410_RTCREG(0x78)
+#define S3C2410_RTCDATE         S3C2410_RTCREG(0x7c)
+#define S3C2410_RTCMON          S3C2410_RTCREG(0x84)
+#define S3C2410_RTCYEAR         S3C2410_RTCREG(0x88)
 
 #endif /* __ASM_ARCH_REGS_RTC_H */
diff --git a/arch/arm/plat-samsung/include/plat/regs-usb-hsotg-phy.h b/arch/arm/plat-samsung/include/plat/regs-usb-hsotg-phy.h
index a111ad87183..fcf27966206 100644
--- a/arch/arm/plat-samsung/include/plat/regs-usb-hsotg-phy.h
+++ b/arch/arm/plat-samsung/include/plat/regs-usb-hsotg-phy.h
@@ -25,8 +25,9 @@
 #define S3C_HSOTG_PHYREG(x)     ((x) + S3C_VA_USB_HSPHY)
 
 #define S3C_PHYPWR                              S3C_HSOTG_PHYREG(0x00)
-#define SRC_PHYPWR_OTG_DISABLE                  (1 << 4)
-#define SRC_PHYPWR_ANALOG_POWERDOWN             (1 << 3)
+#define S3C_PHYPWR_NORMAL_MASK                  (0x19 << 0)
+#define S3C_PHYPWR_OTG_DISABLE                  (1 << 4)
+#define S3C_PHYPWR_ANALOG_POWERDOWN             (1 << 3)
 #define SRC_PHYPWR_FORCE_SUSPEND                (1 << 1)
 
 #define S3C_PHYCLK                              S3C_HSOTG_PHYREG(0x04)
@@ -42,7 +43,7 @@
 
 #define S3C_RSTCON                              S3C_HSOTG_PHYREG(0x08)
 #define S3C_RSTCON_PHYCLK                       (1 << 2)
-#define S3C_RSTCON_HCLK                         (1 << 2)
+#define S3C_RSTCON_HCLK                         (1 << 1)
 #define S3C_RSTCON_PHY                          (1 << 0)
 
 #define S3C_PHYTUNE                             S3C_HSOTG_PHYREG(0x20)
diff --git a/arch/arm/plat-samsung/include/plat/rtc-core.h b/arch/arm/plat-samsung/include/plat/rtc-core.h
new file mode 100644
index 00000000000..21d8594d37c
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/rtc-core.h
@@ -0,0 +1,27 @@
+/* linux/arch/arm/plat-samsung/include/plat/rtc-core.h
+ *
+ * Copyright (c) 2011 Heiko Stuebner <heiko@sntech.de>
+ *
+ * Samsung RTC Controller core functions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_PLAT_RTC_CORE_H
+#define __ASM_PLAT_RTC_CORE_H __FILE__
+
+/* These functions are only for use with the core support code, such as
+ * the cpu specific initialisation code
+ */
+
+/* re-define device name depending on support. */
+static inline void s3c_rtc_setname(char *name)
+{
+#if defined(CONFIG_SAMSUNG_DEV_RTC) || defined(CONFIG_PLAT_S3C24XX)
+        s3c_device_rtc.name = name;
+#endif
+}
+
+#endif /* __ASM_PLAT_RTC_CORE_H */
diff --git a/arch/arm/plat-samsung/include/plat/s3c2410.h b/arch/arm/plat-samsung/include/plat/s3c2410.h
index 3986497dd3f..55b0e5f51e9 100644
--- a/arch/arm/plat-samsung/include/plat/s3c2410.h
+++ b/arch/arm/plat-samsung/include/plat/s3c2410.h
@@ -29,5 +29,3 @@ extern void s3c2410_init_clocks(int xtal);
 #define s3c2410_init NULL
 #define s3c2410a_init NULL
 #endif
-
-extern int s3c2410_baseclk_add(void);
diff --git a/arch/arm/plat-samsung/include/plat/s3c2443.h b/arch/arm/plat-samsung/include/plat/s3c2443.h
index dce05b43d51..a5b794ff838 100644
--- a/arch/arm/plat-samsung/include/plat/s3c2443.h
+++ b/arch/arm/plat-samsung/include/plat/s3c2443.h
@@ -32,23 +32,3 @@ extern void s3c2443_restart(char mode, const char *cmd);
 #define s3c2443_init NULL
 #define s3c2443_restart NULL
 #endif
-
-/* common code used by s3c2443 and others.
- * note, not to be used outside of arch/arm/mach-s3c* */
-
-struct clk;     /* some files don't need clk.h otherwise */
-
-typedef unsigned int (*pll_fn)(unsigned int reg, unsigned int base);
-
-extern void s3c2443_common_setup_clocks(pll_fn get_mpll);
-extern void s3c2443_common_init_clocks(int xtal, pll_fn get_mpll,
-                                       unsigned int *divs, int nr_divs,
-                                       int divmask);
-
-extern int s3c2443_clkcon_enable_h(struct clk *clk, int enable);
-extern int s3c2443_clkcon_enable_p(struct clk *clk, int enable);
-extern int s3c2443_clkcon_enable_s(struct clk *clk, int enable);
-
-extern struct clksrc_clk clk_epllref;
-extern struct clksrc_clk clk_esysclk;
-extern struct clksrc_clk clk_msysclk;
diff --git a/arch/arm/plat-samsung/include/plat/sdhci.h b/arch/arm/plat-samsung/include/plat/sdhci.h
index f82f888b91a..317e246ffc5 100644
--- a/arch/arm/plat-samsung/include/plat/sdhci.h
+++ b/arch/arm/plat-samsung/include/plat/sdhci.h
@@ -40,6 +40,7 @@ enum clk_types {
  * struct s3c_sdhci_platdata() - Platform device data for Samsung SDHCI
  * @max_width: The maximum number of data bits supported.
  * @host_caps: Standard MMC host capabilities bit field.
+ * @host_caps2: The second standard MMC host capabilities bit field.
  * @cd_type: Type of Card Detection method (see cd_types enum above)
  * @clk_type: Type of clock divider method (see clk_types enum above)
  * @ext_cd_init: Initialize external card detect subsystem. Called on
@@ -63,6 +64,7 @@ enum clk_types {
 struct s3c_sdhci_platdata {
         unsigned int    max_width;
         unsigned int    host_caps;
+        unsigned int    host_caps2;
         unsigned int    pm_caps;
         enum cd_types   cd_type;
         enum clk_types  clk_type;
diff --git a/arch/arm/plat-samsung/include/plat/udc-hs.h b/arch/arm/plat-samsung/include/plat/udc-hs.h
index a22a4f2eea9..c9e3667cb2b 100644
--- a/arch/arm/plat-samsung/include/plat/udc-hs.h
+++ b/arch/arm/plat-samsung/include/plat/udc-hs.h
@@ -26,4 +26,9 @@ enum s3c_hsotg_dmamode {
 struct s3c_hsotg_plat {
         enum s3c_hsotg_dmamode  dma;
         unsigned int            is_osc : 1;
+
+        int (*phy_init)(struct platform_device *pdev, int type);
+        int (*phy_exit)(struct platform_device *pdev, int type);
 };
+
+extern void s3c_hsotg_set_platdata(struct s3c_hsotg_plat *pd);
diff --git a/arch/arm/plat-samsung/platformdata.c b/arch/arm/plat-samsung/platformdata.c
index 0f707184eae..fa78aa710ed 100644
--- a/arch/arm/plat-samsung/platformdata.c
+++ b/arch/arm/plat-samsung/platformdata.c
@@ -53,6 +53,8 @@ void s3c_sdhci_set_platdata(struct s3c_sdhci_platdata *pd,
                 set->cfg_gpio = pd->cfg_gpio;
         if (pd->host_caps)
                 set->host_caps |= pd->host_caps;
+        if (pd->host_caps2)
+                set->host_caps2 |= pd->host_caps2;
         if (pd->pm_caps)
                 set->pm_caps |= pd->pm_caps;
         if (pd->clk_type)
diff --git a/arch/arm/plat-spear/include/plat/keyboard.h b/arch/arm/plat-spear/include/plat/keyboard.h
index 68b5394fc58..c16cc31ecbe 100644
--- a/arch/arm/plat-spear/include/plat/keyboard.h
+++ b/arch/arm/plat-spear/include/plat/keyboard.h
@@ -15,7 +15,7 @@
 #include <linux/input/matrix_keypad.h>
 #include <linux/types.h>
 
-#define DECLARE_KEYMAP(_name) \
+#define DECLARE_9x9_KEYMAP(_name) \
 int _name[] = { \
         KEY(0, 0, KEY_ESC), \
         KEY(0, 1, KEY_1), \
@@ -62,24 +62,6 @@ int _name[] = { \
         KEY(4, 6, KEY_Z), \
         KEY(4, 7, KEY_X), \
         KEY(4, 8, KEY_C), \
-        KEY(4, 0, KEY_L), \
-        KEY(4, 1, KEY_SEMICOLON), \
-        KEY(4, 2, KEY_APOSTROPHE), \
-        KEY(4, 3, KEY_GRAVE), \
-        KEY(4, 4, KEY_LEFTSHIFT), \
-        KEY(4, 5, KEY_BACKSLASH), \
-        KEY(4, 6, KEY_Z), \
-        KEY(4, 7, KEY_X), \
-        KEY(4, 8, KEY_C), \
-        KEY(4, 0, KEY_L), \
-        KEY(4, 1, KEY_SEMICOLON), \
-        KEY(4, 2, KEY_APOSTROPHE), \
-        KEY(4, 3, KEY_GRAVE), \
-        KEY(4, 4, KEY_LEFTSHIFT), \
-        KEY(4, 5, KEY_BACKSLASH), \
-        KEY(4, 6, KEY_Z), \
-        KEY(4, 7, KEY_X), \
-        KEY(4, 8, KEY_C), \
         KEY(5, 0, KEY_V), \
         KEY(5, 1, KEY_B), \
         KEY(5, 2, KEY_N), \
@@ -118,10 +100,55 @@ int _name[] = { \
         KEY(8, 8, KEY_KP0), \
 }
 
+#define DECLARE_6x6_KEYMAP(_name) \
+int _name[] = { \
+        KEY(0, 0, KEY_RESERVED), \
+        KEY(0, 1, KEY_1), \
+        KEY(0, 2, KEY_2), \
+        KEY(0, 3, KEY_3), \
+        KEY(0, 4, KEY_4), \
+        KEY(0, 5, KEY_5), \
+        KEY(1, 0, KEY_Q), \
+        KEY(1, 1, KEY_W), \
+        KEY(1, 2, KEY_E), \
+        KEY(1, 3, KEY_R), \
+        KEY(1, 4, KEY_T), \
+        KEY(1, 5, KEY_Y), \
+        KEY(2, 0, KEY_D), \
+        KEY(2, 1, KEY_F), \
+        KEY(2, 2, KEY_G), \
+        KEY(2, 3, KEY_H), \
+        KEY(2, 4, KEY_J), \
+        KEY(2, 5, KEY_K), \
+        KEY(3, 0, KEY_B), \
+        KEY(3, 1, KEY_N), \
+        KEY(3, 2, KEY_M), \
+        KEY(3, 3, KEY_COMMA), \
+        KEY(3, 4, KEY_DOT), \
+        KEY(3, 5, KEY_SLASH), \
+        KEY(4, 0, KEY_F6), \
+        KEY(4, 1, KEY_F7), \
+        KEY(4, 2, KEY_F8), \
+        KEY(4, 3, KEY_F9), \
+        KEY(4, 4, KEY_F10), \
+        KEY(4, 5, KEY_NUMLOCK), \
+        KEY(5, 0, KEY_KP2), \
+        KEY(5, 1, KEY_KP3), \
+        KEY(5, 2, KEY_KP0), \
+        KEY(5, 3, KEY_KPDOT), \
+        KEY(5, 4, KEY_RO), \
+        KEY(5, 5, KEY_ZENKAKUHANKAKU), \
+}
+
+#define KEYPAD_9x9     0
+#define KEYPAD_6x6     1
+#define KEYPAD_2x2     2
+
 /**
  * struct kbd_platform_data - spear keyboard platform data
  * keymap: pointer to keymap data (table and size)
  * rep: enables key autorepeat
+ * mode: choose keyboard support(9x9, 6x6, 2x2)
  *
  * This structure is supposed to be used by platform code to supply
  * keymaps to drivers that implement keyboards.
@@ -129,6 +156,7 @@ int _name[] = { \
 struct kbd_platform_data {
         const struct matrix_keymap_data *keymap;
         bool rep;
+        unsigned int mode;
 };
 
 /* This function is used to set platform data field of pdev->dev */
diff --git a/arch/arm/plat-spear/include/plat/system.h b/arch/arm/plat-spear/include/plat/system.h
deleted file mode 100644
index 86c6f83b44c..00000000000
--- a/arch/arm/plat-spear/include/plat/system.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * arch/arm/plat-spear/include/plat/system.h
- *
- * SPEAr platform specific architecture functions
- *
- * Copyright (C) 2009 ST Microelectronics
- * Viresh Kumar<viresh.kumar@st.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#ifndef __PLAT_SYSTEM_H
-#define __PLAT_SYSTEM_H
-
-static inline void arch_idle(void)
-{
-        /*
-         * This should do all the clock switching
-         * and wait for interrupt tricks
-         */
-        cpu_do_idle();
-}
-
-#endif /* __PLAT_SYSTEM_H */
diff --git a/arch/arm/plat-versatile/Makefile b/arch/arm/plat-versatile/Makefile
index 69714db47c3..a5cb1945bdc 100644
--- a/arch/arm/plat-versatile/Makefile
+++ b/arch/arm/plat-versatile/Makefile
@@ -1,5 +1,4 @@
 obj-y   := clock.o
-obj-$(CONFIG_LOCAL_TIMERS) += localtimer.o
 obj-$(CONFIG_PLAT_VERSATILE_CLCD) += clcd.o
 obj-$(CONFIG_PLAT_VERSATILE_FPGA_IRQ) += fpga-irq.o
 obj-$(CONFIG_PLAT_VERSATILE_LEDS) += leds.o
diff --git a/arch/arm/plat-versatile/localtimer.c b/arch/arm/plat-versatile/localtimer.c
deleted file mode 100644
index 0fb3961999b..00000000000
--- a/arch/arm/plat-versatile/localtimer.c
+++ /dev/null
@@ -1,27 +0,0 @@
-/*
- *  linux/arch/arm/plat-versatile/localtimer.c
- *
- *  Copyright (C) 2002 ARM Ltd.
- *  All Rights Reserved
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#include <linux/init.h>
-#include <linux/smp.h>
-#include <linux/clockchips.h>
-
-#include <asm/smp_twd.h>
-#include <asm/localtimer.h>
-#include <mach/irqs.h>
-
-/*
- * Setup the local clock events for a CPU.
- */
-int __cpuinit local_timer_setup(struct clock_event_device *evt)
-{
-        evt->irq = IRQ_LOCALTIMER;
-        twd_timer_setup(evt);
-        return 0;
-}
diff --git a/arch/avr32/include/asm/io.h b/arch/avr32/include/asm/io.h
index 22c97ef9220..cf60d0a9f17 100644
--- a/arch/avr32/include/asm/io.h
+++ b/arch/avr32/include/asm/io.h
@@ -1,6 +1,7 @@
 #ifndef __ASM_AVR32_IO_H
 #define __ASM_AVR32_IO_H
 
+#include <linux/bug.h>
 #include <linux/kernel.h>
 #include <linux/string.h>
 #include <linux/types.h>
diff --git a/arch/avr32/mach-at32ap/at32ap700x.c b/arch/avr32/mach-at32ap/at32ap700x.c
index 402a7bb7266..889c544688c 100644
--- a/arch/avr32/mach-at32ap/at32ap700x.c
+++ b/arch/avr32/mach-at32ap/at32ap700x.c
@@ -1055,8 +1055,6 @@ struct platform_device *__init at32_add_device_usart(unsigned int id)
         return at32_usarts[id];
 }
 
-struct platform_device *atmel_default_console_device;
-
 void __init at32_setup_serial_console(unsigned int usart_id)
 {
         atmel_default_console_device = at32_usarts[usart_id];
diff --git a/arch/avr32/mach-at32ap/include/mach/cpu.h b/arch/avr32/mach-at32ap/include/mach/cpu.h
index 8181293115e..16a24b14146 100644
--- a/arch/avr32/mach-at32ap/include/mach/cpu.h
+++ b/arch/avr32/mach-at32ap/include/mach/cpu.h
@@ -30,9 +30,6 @@
 #define cpu_is_at91sam9261()    (0)
 #define cpu_is_at91sam9263()    (0)
 #define cpu_is_at91sam9rl()     (0)
-#define cpu_is_at91cap9()       (0)
-#define cpu_is_at91cap9_revB()  (0)
-#define cpu_is_at91cap9_revC()  (0)
 #define cpu_is_at91sam9g10()    (0)
 #define cpu_is_at91sam9g20()    (0)
 #define cpu_is_at91sam9g45()    (0)
diff --git a/arch/blackfin/Kconfig b/arch/blackfin/Kconfig
index abe5a9e8514..c1269a1085e 100644
--- a/arch/blackfin/Kconfig
+++ b/arch/blackfin/Kconfig
@@ -36,6 +36,7 @@ config BLACKFIN
         select GENERIC_ATOMIC64
         select GENERIC_IRQ_PROBE
         select IRQ_PER_CPU if SMP
+        select HAVE_NMI_WATCHDOG if NMI_WATCHDOG
 
 config GENERIC_CSUM
         def_bool y
diff --git a/arch/blackfin/configs/BF518F-EZBRD_defconfig b/arch/blackfin/configs/BF518F-EZBRD_defconfig
index 0b7039cf07f..383007877b2 100644
--- a/arch/blackfin/configs/BF518F-EZBRD_defconfig
+++ b/arch/blackfin/configs/BF518F-EZBRD_defconfig
@@ -4,9 +4,7 @@ CONFIG_IKCONFIG=y
 CONFIG_IKCONFIG_PROC=y
 CONFIG_LOG_BUF_SHIFT=14
 CONFIG_BLK_DEV_INITRD=y
-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
 CONFIG_EXPERT=y
-# CONFIG_SYSCTL_SYSCALL is not set
 # CONFIG_ELF_CORE is not set
 # CONFIG_FUTEX is not set
 # CONFIG_SIGNALFD is not set
@@ -35,7 +33,6 @@ CONFIG_C_CDPRIO=y
 CONFIG_BANK_3=0x99B2
 CONFIG_BINFMT_FLAT=y
 CONFIG_BINFMT_ZFLAT=y
-CONFIG_PM=y
 CONFIG_NET=y
 CONFIG_PACKET=y
 CONFIG_UNIX=y
@@ -51,7 +48,6 @@ CONFIG_IP_PNP=y
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 # CONFIG_FW_LOADER is not set
 CONFIG_MTD=y
-CONFIG_MTD_PARTITIONS=y
 CONFIG_MTD_CHAR=y
 CONFIG_MTD_BLOCK=y
 CONFIG_MTD_JEDECPROBE=m
@@ -60,20 +56,28 @@ CONFIG_MTD_ROM=m
 CONFIG_MTD_COMPLEX_MAPPINGS=y
 CONFIG_BLK_DEV_RAM=y
 CONFIG_NETDEVICES=y
-CONFIG_NET_ETHERNET=y
+CONFIG_NET_BFIN=y
 CONFIG_BFIN_MAC=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
+# CONFIG_NET_VENDOR_BROADCOM is not set
+# CONFIG_NET_VENDOR_CHELSIO is not set
+# CONFIG_NET_VENDOR_INTEL is not set
+# CONFIG_NET_VENDOR_MARVELL is not set
+# CONFIG_NET_VENDOR_MICREL is not set
+# CONFIG_NET_VENDOR_MICROCHIP is not set
+# CONFIG_NET_VENDOR_NATSEMI is not set
+# CONFIG_NET_VENDOR_SEEQ is not set
+# CONFIG_NET_VENDOR_SMSC is not set
+# CONFIG_NET_VENDOR_STMICRO is not set
 # CONFIG_WLAN is not set
 # CONFIG_INPUT is not set
 # CONFIG_SERIO is not set
 # CONFIG_VT is not set
-# CONFIG_DEVKMEM is not set
+# CONFIG_LEGACY_PTYS is not set
 CONFIG_BFIN_JTAG_COMM=m
+# CONFIG_DEVKMEM is not set
 CONFIG_SERIAL_BFIN=y
 CONFIG_SERIAL_BFIN_CONSOLE=y
 CONFIG_SERIAL_BFIN_UART0=y
-# CONFIG_LEGACY_PTYS is not set
 # CONFIG_HW_RANDOM is not set
 CONFIG_I2C=y
 CONFIG_I2C_CHARDEV=y
@@ -97,16 +101,13 @@ CONFIG_EXT2_FS=m
 CONFIG_VFAT_FS=m
 CONFIG_NFS_FS=m
 CONFIG_NFS_V3=y
-CONFIG_SMB_FS=m
 CONFIG_NLS_CODEPAGE_437=m
 CONFIG_NLS_CODEPAGE_936=m
 CONFIG_NLS_ISO8859_1=m
 CONFIG_NLS_UTF8=m
-CONFIG_DEBUG_KERNEL=y
 CONFIG_DEBUG_SHIRQ=y
 CONFIG_DETECT_HUNG_TASK=y
 CONFIG_DEBUG_INFO=y
-# CONFIG_RCU_CPU_STALL_DETECTOR is not set
 # CONFIG_FTRACE is not set
 CONFIG_DEBUG_MMRS=y
 CONFIG_DEBUG_HWERR=y
diff --git a/arch/blackfin/configs/BF526-EZBRD_defconfig b/arch/blackfin/configs/BF526-EZBRD_defconfig
index 5553205d7cb..2f2c6acf210 100644
--- a/arch/blackfin/configs/BF526-EZBRD_defconfig
+++ b/arch/blackfin/configs/BF526-EZBRD_defconfig
@@ -4,9 +4,7 @@ CONFIG_IKCONFIG=y
 CONFIG_IKCONFIG_PROC=y
 CONFIG_LOG_BUF_SHIFT=14
 CONFIG_BLK_DEV_INITRD=y
-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
 CONFIG_EXPERT=y
-# CONFIG_SYSCTL_SYSCALL is not set
 # CONFIG_ELF_CORE is not set
 # CONFIG_FUTEX is not set
 # CONFIG_SIGNALFD is not set
@@ -40,7 +38,6 @@ CONFIG_C_CDPRIO=y
 CONFIG_BANK_3=0x99B2
 CONFIG_BINFMT_FLAT=y
 CONFIG_BINFMT_ZFLAT=y
-CONFIG_PM=y
 CONFIG_NET=y
 CONFIG_PACKET=y
 CONFIG_UNIX=y
@@ -56,7 +53,6 @@ CONFIG_IP_PNP=y
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 # CONFIG_FW_LOADER is not set
 CONFIG_MTD=y
-CONFIG_MTD_PARTITIONS=y
 CONFIG_MTD_CHAR=y
 CONFIG_MTD_BLOCK=y
 CONFIG_MTD_CFI=y
@@ -74,10 +70,18 @@ CONFIG_BLK_DEV_SD=y
 CONFIG_BLK_DEV_SR=m
 # CONFIG_SCSI_LOWLEVEL is not set
 CONFIG_NETDEVICES=y
-CONFIG_NET_ETHERNET=y
+CONFIG_NET_BFIN=y
 CONFIG_BFIN_MAC=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
+# CONFIG_NET_VENDOR_BROADCOM is not set
+# CONFIG_NET_VENDOR_CHELSIO is not set
+# CONFIG_NET_VENDOR_INTEL is not set
+# CONFIG_NET_VENDOR_MARVELL is not set
+# CONFIG_NET_VENDOR_MICREL is not set
+# CONFIG_NET_VENDOR_MICROCHIP is not set
+# CONFIG_NET_VENDOR_NATSEMI is not set
+# CONFIG_NET_VENDOR_SEEQ is not set
+# CONFIG_NET_VENDOR_SMSC is not set
+# CONFIG_NET_VENDOR_STMICRO is not set
 # CONFIG_WLAN is not set
 CONFIG_INPUT_FF_MEMLESS=m
 # CONFIG_INPUT_MOUSEDEV is not set
@@ -85,12 +89,12 @@ CONFIG_INPUT_FF_MEMLESS=m
 # CONFIG_INPUT_MOUSE is not set
 CONFIG_INPUT_MISC=y
 # CONFIG_SERIO is not set
-# CONFIG_DEVKMEM is not set
+# CONFIG_LEGACY_PTYS is not set
 CONFIG_BFIN_JTAG_COMM=m
+# CONFIG_DEVKMEM is not set
 CONFIG_SERIAL_BFIN=y
 CONFIG_SERIAL_BFIN_CONSOLE=y
 CONFIG_SERIAL_BFIN_UART1=y
-# CONFIG_LEGACY_PTYS is not set
 # CONFIG_HW_RANDOM is not set
 CONFIG_I2C=y
 CONFIG_I2C_CHARDEV=m
@@ -123,7 +127,6 @@ CONFIG_USB_DEVICEFS=y
 # CONFIG_USB_DEVICE_CLASS is not set
 CONFIG_USB_OTG_BLACKLIST_HUB=y
 CONFIG_USB_MON=y
-CONFIG_USB_MUSB_HDRC=y
 CONFIG_USB_STORAGE=y
 CONFIG_RTC_CLASS=y
 CONFIG_RTC_DRV_BFIN=y
@@ -135,16 +138,13 @@ CONFIG_VFAT_FS=m
 CONFIG_JFFS2_FS=m
 CONFIG_NFS_FS=m
 CONFIG_NFS_V3=y
-CONFIG_SMB_FS=m
 CONFIG_NLS_CODEPAGE_437=m
 CONFIG_NLS_CODEPAGE_936=m
 CONFIG_NLS_ISO8859_1=m
 CONFIG_NLS_UTF8=m
-CONFIG_DEBUG_KERNEL=y
 CONFIG_DEBUG_SHIRQ=y
 CONFIG_DETECT_HUNG_TASK=y
 CONFIG_DEBUG_INFO=y
-# CONFIG_RCU_CPU_STALL_DETECTOR is not set
 # CONFIG_FTRACE is not set
 CONFIG_DEBUG_MMRS=y
 CONFIG_DEBUG_HWERR=y
diff --git a/arch/blackfin/configs/BF527-EZKIT-V2_defconfig b/arch/blackfin/configs/BF527-EZKIT-V2_defconfig
index 498f64a8705..91535c38e7f 100644
--- a/arch/blackfin/configs/BF527-EZKIT-V2_defconfig
+++ b/arch/blackfin/configs/BF527-EZKIT-V2_defconfig
@@ -4,9 +4,7 @@ CONFIG_IKCONFIG=y
 CONFIG_IKCONFIG_PROC=y
 CONFIG_LOG_BUF_SHIFT=14
 CONFIG_BLK_DEV_INITRD=y
-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
 CONFIG_EXPERT=y
-# CONFIG_SYSCTL_SYSCALL is not set
 # CONFIG_ELF_CORE is not set
 # CONFIG_FUTEX is not set
 # CONFIG_SIGNALFD is not set
@@ -39,7 +37,6 @@ CONFIG_C_CDPRIO=y
 CONFIG_BANK_3=0x99B2
 CONFIG_BINFMT_FLAT=y
 CONFIG_BINFMT_ZFLAT=y
-CONFIG_PM=y
 CONFIG_NET=y
 CONFIG_PACKET=y
 CONFIG_UNIX=y
@@ -61,7 +58,6 @@ CONFIG_BFIN_SIR0=y
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 # CONFIG_FW_LOADER is not set
 CONFIG_MTD=y
-CONFIG_MTD_PARTITIONS=y
 CONFIG_MTD_CHAR=m
 CONFIG_MTD_BLOCK=y
 CONFIG_MTD_JEDECPROBE=m
@@ -77,10 +73,18 @@ CONFIG_BLK_DEV_SD=y
 CONFIG_BLK_DEV_SR=m
 # CONFIG_SCSI_LOWLEVEL is not set
 CONFIG_NETDEVICES=y
-CONFIG_NET_ETHERNET=y
+CONFIG_NET_BFIN=y
 CONFIG_BFIN_MAC=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
+# CONFIG_NET_VENDOR_BROADCOM is not set
+# CONFIG_NET_VENDOR_CHELSIO is not set
+# CONFIG_NET_VENDOR_INTEL is not set
+# CONFIG_NET_VENDOR_MARVELL is not set
+# CONFIG_NET_VENDOR_MICREL is not set
+# CONFIG_NET_VENDOR_MICROCHIP is not set
+# CONFIG_NET_VENDOR_NATSEMI is not set
+# CONFIG_NET_VENDOR_SEEQ is not set
+# CONFIG_NET_VENDOR_SMSC is not set
+# CONFIG_NET_VENDOR_STMICRO is not set
 # CONFIG_WLAN is not set
 CONFIG_INPUT_FF_MEMLESS=m
 # CONFIG_INPUT_MOUSEDEV is not set
@@ -93,12 +97,12 @@ CONFIG_TOUCHSCREEN_AD7879=y
 CONFIG_TOUCHSCREEN_AD7879_I2C=y
 CONFIG_INPUT_MISC=y
 # CONFIG_SERIO is not set
-# CONFIG_DEVKMEM is not set
+# CONFIG_LEGACY_PTYS is not set
 CONFIG_BFIN_JTAG_COMM=m
+# CONFIG_DEVKMEM is not set
 CONFIG_SERIAL_BFIN=y
 CONFIG_SERIAL_BFIN_CONSOLE=y
 CONFIG_SERIAL_BFIN_UART1=y
-# CONFIG_LEGACY_PTYS is not set
 # CONFIG_HW_RANDOM is not set
 CONFIG_I2C=y
 CONFIG_I2C_CHARDEV=m
@@ -148,7 +152,9 @@ CONFIG_USB_DEVICEFS=y
 CONFIG_USB_OTG_BLACKLIST_HUB=y
 CONFIG_USB_MON=y
 CONFIG_USB_MUSB_HDRC=y
+CONFIG_USB_MUSB_BLACKFIN=y
 CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
 CONFIG_NEW_LEDS=y
 CONFIG_LEDS_CLASS=y
 CONFIG_LEDS_ADP5520=y
@@ -163,16 +169,13 @@ CONFIG_VFAT_FS=m
 CONFIG_JFFS2_FS=m
 CONFIG_NFS_FS=m
 CONFIG_NFS_V3=y
-CONFIG_SMB_FS=m
 CONFIG_NLS_CODEPAGE_437=m
 CONFIG_NLS_CODEPAGE_936=m
 CONFIG_NLS_ISO8859_1=m
 CONFIG_NLS_UTF8=m
-CONFIG_DEBUG_KERNEL=y
 CONFIG_DEBUG_SHIRQ=y
 CONFIG_DETECT_HUNG_TASK=y
 CONFIG_DEBUG_INFO=y
-# CONFIG_RCU_CPU_STALL_DETECTOR is not set
 # CONFIG_FTRACE is not set
 CONFIG_DEBUG_MMRS=y
 CONFIG_DEBUG_HWERR=y
diff --git a/arch/blackfin/configs/BF527-EZKIT_defconfig b/arch/blackfin/configs/BF527-EZKIT_defconfig
index 72e0317565e..9ccc18a6b4d 100644
--- a/arch/blackfin/configs/BF527-EZKIT_defconfig
+++ b/arch/blackfin/configs/BF527-EZKIT_defconfig
@@ -4,9 +4,7 @@ CONFIG_IKCONFIG=y
 CONFIG_IKCONFIG_PROC=y
 CONFIG_LOG_BUF_SHIFT=14
 CONFIG_BLK_DEV_INITRD=y
-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
 CONFIG_EXPERT=y
-# CONFIG_SYSCTL_SYSCALL is not set
 # CONFIG_ELF_CORE is not set
 # CONFIG_FUTEX is not set
 # CONFIG_SIGNALFD is not set
@@ -38,7 +36,6 @@ CONFIG_C_CDPRIO=y
 CONFIG_BANK_3=0x99B2
 CONFIG_BINFMT_FLAT=y
 CONFIG_BINFMT_ZFLAT=y
-CONFIG_PM=y
 CONFIG_NET=y
 CONFIG_PACKET=y
 CONFIG_UNIX=y
@@ -60,7 +57,6 @@ CONFIG_BFIN_SIR0=y
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 # CONFIG_FW_LOADER is not set
 CONFIG_MTD=y
-CONFIG_MTD_PARTITIONS=y
 CONFIG_MTD_CHAR=m
 CONFIG_MTD_BLOCK=y
 CONFIG_MTD_JEDECPROBE=m
@@ -76,10 +72,18 @@ CONFIG_BLK_DEV_SD=y
 CONFIG_BLK_DEV_SR=m
 # CONFIG_SCSI_LOWLEVEL is not set
 CONFIG_NETDEVICES=y
-CONFIG_NET_ETHERNET=y
+CONFIG_NET_BFIN=y
 CONFIG_BFIN_MAC=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
+# CONFIG_NET_VENDOR_BROADCOM is not set
+# CONFIG_NET_VENDOR_CHELSIO is not set
+# CONFIG_NET_VENDOR_INTEL is not set
+# CONFIG_NET_VENDOR_MARVELL is not set
+# CONFIG_NET_VENDOR_MICREL is not set
+# CONFIG_NET_VENDOR_MICROCHIP is not set
+# CONFIG_NET_VENDOR_NATSEMI is not set
+# CONFIG_NET_VENDOR_SEEQ is not set
+# CONFIG_NET_VENDOR_SMSC is not set
+# CONFIG_NET_VENDOR_STMICRO is not set
 # CONFIG_WLAN is not set
 CONFIG_INPUT_FF_MEMLESS=m
 # CONFIG_INPUT_MOUSEDEV is not set
@@ -87,12 +91,12 @@ CONFIG_INPUT_FF_MEMLESS=m
 # CONFIG_INPUT_MOUSE is not set
 CONFIG_INPUT_MISC=y
 # CONFIG_SERIO is not set
-# CONFIG_DEVKMEM is not set
+# CONFIG_LEGACY_PTYS is not set
 CONFIG_BFIN_JTAG_COMM=m
+# CONFIG_DEVKMEM is not set
 CONFIG_SERIAL_BFIN=y
 CONFIG_SERIAL_BFIN_CONSOLE=y
 CONFIG_SERIAL_BFIN_UART1=y
-# CONFIG_LEGACY_PTYS is not set
 # CONFIG_HW_RANDOM is not set
 CONFIG_I2C=y
 CONFIG_I2C_CHARDEV=m
@@ -142,8 +146,9 @@ CONFIG_USB_DEVICEFS=y
 CONFIG_USB_OTG_BLACKLIST_HUB=y
 CONFIG_USB_MON=y
 CONFIG_USB_MUSB_HDRC=y
-CONFIG_MUSB_PIO_ONLY=y
+CONFIG_USB_MUSB_BLACKFIN=y
 CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
 CONFIG_RTC_CLASS=y
 CONFIG_RTC_DRV_BFIN=y
 CONFIG_EXT2_FS=m
@@ -155,16 +160,13 @@ CONFIG_VFAT_FS=m
 CONFIG_JFFS2_FS=m
 CONFIG_NFS_FS=m
 CONFIG_NFS_V3=y
-CONFIG_SMB_FS=m
 CONFIG_NLS_CODEPAGE_437=m
 CONFIG_NLS_CODEPAGE_936=m
 CONFIG_NLS_ISO8859_1=m
 CONFIG_NLS_UTF8=m
-CONFIG_DEBUG_KERNEL=y
 CONFIG_DEBUG_SHIRQ=y
 CONFIG_DETECT_HUNG_TASK=y
 CONFIG_DEBUG_INFO=y
-# CONFIG_RCU_CPU_STALL_DETECTOR is not set
 # CONFIG_FTRACE is not set
 CONFIG_DEBUG_MMRS=y
 CONFIG_DEBUG_HWERR=y
diff --git a/arch/blackfin/configs/BF533-EZKIT_defconfig b/arch/blackfin/configs/BF533-EZKIT_defconfig
index 2f075e0b262..127f20df75a 100644
--- a/arch/blackfin/configs/BF533-EZKIT_defconfig
+++ b/arch/blackfin/configs/BF533-EZKIT_defconfig
@@ -4,9 +4,7 @@ CONFIG_IKCONFIG=y
 CONFIG_IKCONFIG_PROC=y
 CONFIG_LOG_BUF_SHIFT=14
 CONFIG_BLK_DEV_INITRD=y
-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
 CONFIG_EXPERT=y
-# CONFIG_SYSCTL_SYSCALL is not set
 # CONFIG_ELF_CORE is not set
 # CONFIG_FUTEX is not set
 # CONFIG_SIGNALFD is not set
@@ -32,7 +30,6 @@ CONFIG_C_CDPRIO=y
 CONFIG_BANK_3=0xAAC2
 CONFIG_BINFMT_FLAT=y
 CONFIG_BINFMT_ZFLAT=y
-CONFIG_PM=y
 CONFIG_NET=y
 CONFIG_PACKET=y
 CONFIG_UNIX=y
@@ -53,7 +50,6 @@ CONFIG_IRTTY_SIR=m
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 # CONFIG_FW_LOADER is not set
 CONFIG_MTD=y
-CONFIG_MTD_PARTITIONS=y
 CONFIG_MTD_CHAR=m
 CONFIG_MTD_BLOCK=y
 CONFIG_MTD_JEDECPROBE=m
@@ -62,10 +58,16 @@ CONFIG_MTD_ROM=m
 CONFIG_MTD_COMPLEX_MAPPINGS=y
 CONFIG_BLK_DEV_RAM=y
 CONFIG_NETDEVICES=y
-CONFIG_NET_ETHERNET=y
+# CONFIG_NET_VENDOR_BROADCOM is not set
+# CONFIG_NET_VENDOR_CHELSIO is not set
+# CONFIG_NET_VENDOR_INTEL is not set
+# CONFIG_NET_VENDOR_MARVELL is not set
+# CONFIG_NET_VENDOR_MICREL is not set
+# CONFIG_NET_VENDOR_MICROCHIP is not set
+# CONFIG_NET_VENDOR_NATSEMI is not set
+# CONFIG_NET_VENDOR_SEEQ is not set
 CONFIG_SMC91X=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
+# CONFIG_NET_VENDOR_STMICRO is not set
 # CONFIG_WLAN is not set
 CONFIG_INPUT=m
 # CONFIG_INPUT_MOUSEDEV is not set
@@ -74,11 +76,11 @@ CONFIG_INPUT_EVDEV=m
 # CONFIG_INPUT_MOUSE is not set
 # CONFIG_SERIO is not set
 # CONFIG_VT is not set
-# CONFIG_DEVKMEM is not set
+# CONFIG_LEGACY_PTYS is not set
 CONFIG_BFIN_JTAG_COMM=m
+# CONFIG_DEVKMEM is not set
 CONFIG_SERIAL_BFIN=y
 CONFIG_SERIAL_BFIN_CONSOLE=y
-# CONFIG_LEGACY_PTYS is not set
 # CONFIG_HW_RANDOM is not set
 CONFIG_SPI=y
 CONFIG_SPI_BFIN5XX=y
@@ -94,12 +96,9 @@ CONFIG_RTC_DRV_BFIN=y
 CONFIG_JFFS2_FS=m
 CONFIG_NFS_FS=m
 CONFIG_NFS_V3=y
-CONFIG_SMB_FS=m
-CONFIG_DEBUG_KERNEL=y
 CONFIG_DEBUG_SHIRQ=y
 CONFIG_DETECT_HUNG_TASK=y
 CONFIG_DEBUG_INFO=y
-# CONFIG_RCU_CPU_STALL_DETECTOR is not set
 # CONFIG_FTRACE is not set
 CONFIG_DEBUG_MMRS=y
 CONFIG_DEBUG_HWERR=y
diff --git a/arch/blackfin/configs/BF533-STAMP_defconfig b/arch/blackfin/configs/BF533-STAMP_defconfig
index ab38a82597b..0df2f921f7e 100644
--- a/arch/blackfin/configs/BF533-STAMP_defconfig
+++ b/arch/blackfin/configs/BF533-STAMP_defconfig
@@ -4,9 +4,7 @@ CONFIG_IKCONFIG=y
 CONFIG_IKCONFIG_PROC=y
 CONFIG_LOG_BUF_SHIFT=14
 CONFIG_BLK_DEV_INITRD=y
-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
 CONFIG_EXPERT=y
-# CONFIG_SYSCTL_SYSCALL is not set
 # CONFIG_ELF_CORE is not set
 # CONFIG_FUTEX is not set
 # CONFIG_SIGNALFD is not set
@@ -30,7 +28,6 @@ CONFIG_C_CDPRIO=y
 CONFIG_BANK_3=0xAAC2
 CONFIG_BINFMT_FLAT=y
 CONFIG_BINFMT_ZFLAT=y
-CONFIG_PM=y
 CONFIG_NET=y
 CONFIG_PACKET=y
 CONFIG_UNIX=y
@@ -62,10 +59,16 @@ CONFIG_MTD_ROM=m
 CONFIG_MTD_COMPLEX_MAPPINGS=y
 CONFIG_BLK_DEV_RAM=y
 CONFIG_NETDEVICES=y
-CONFIG_NET_ETHERNET=y
+# CONFIG_NET_VENDOR_BROADCOM is not set
+# CONFIG_NET_VENDOR_CHELSIO is not set
+# CONFIG_NET_VENDOR_INTEL is not set
+# CONFIG_NET_VENDOR_MARVELL is not set
+# CONFIG_NET_VENDOR_MICREL is not set
+# CONFIG_NET_VENDOR_MICROCHIP is not set
+# CONFIG_NET_VENDOR_NATSEMI is not set
+# CONFIG_NET_VENDOR_SEEQ is not set
 CONFIG_SMC91X=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
+# CONFIG_NET_VENDOR_STMICRO is not set
 # CONFIG_WLAN is not set
 # CONFIG_INPUT_MOUSEDEV is not set
 CONFIG_INPUT_EVDEV=m
@@ -74,11 +77,11 @@ CONFIG_INPUT_EVDEV=m
 CONFIG_INPUT_MISC=y
 # CONFIG_SERIO is not set
 # CONFIG_VT is not set
-# CONFIG_DEVKMEM is not set
+# CONFIG_LEGACY_PTYS is not set
 CONFIG_BFIN_JTAG_COMM=m
+# CONFIG_DEVKMEM is not set
 CONFIG_SERIAL_BFIN=y
 CONFIG_SERIAL_BFIN_CONSOLE=y
-# CONFIG_LEGACY_PTYS is not set
 # CONFIG_HW_RANDOM is not set
 CONFIG_I2C=m
 CONFIG_I2C_CHARDEV=m
@@ -106,12 +109,9 @@ CONFIG_RTC_DRV_BFIN=y
 CONFIG_JFFS2_FS=m
 CONFIG_NFS_FS=m
 CONFIG_NFS_V3=y
-CONFIG_SMB_FS=m
-CONFIG_DEBUG_KERNEL=y
 CONFIG_DEBUG_SHIRQ=y
 CONFIG_DETECT_HUNG_TASK=y
 CONFIG_DEBUG_INFO=y
-# CONFIG_RCU_CPU_STALL_DETECTOR is not set
 # CONFIG_FTRACE is not set
 CONFIG_DEBUG_MMRS=y
 CONFIG_DEBUG_HWERR=y
diff --git a/arch/blackfin/configs/BF537-STAMP_defconfig b/arch/blackfin/configs/BF537-STAMP_defconfig
index 5c802d6bbbc..91d3eda4274 100644
--- a/arch/blackfin/configs/BF537-STAMP_defconfig
+++ b/arch/blackfin/configs/BF537-STAMP_defconfig
@@ -4,9 +4,7 @@ CONFIG_IKCONFIG=y
 CONFIG_IKCONFIG_PROC=y
 CONFIG_LOG_BUF_SHIFT=14
 CONFIG_BLK_DEV_INITRD=y
-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
 CONFIG_EXPERT=y
-# CONFIG_SYSCTL_SYSCALL is not set
 # CONFIG_ELF_CORE is not set
 # CONFIG_FUTEX is not set
 # CONFIG_SIGNALFD is not set
@@ -30,7 +28,6 @@ CONFIG_C_CDPRIO=y
 CONFIG_BANK_3=0x99B2
 CONFIG_BINFMT_FLAT=y
 CONFIG_BINFMT_ZFLAT=y
-CONFIG_PM=y
 CONFIG_NET=y
 CONFIG_PACKET=y
 CONFIG_UNIX=y
@@ -45,7 +42,6 @@ CONFIG_IP_PNP=y
 CONFIG_CAN=m
 CONFIG_CAN_RAW=m
 CONFIG_CAN_BCM=m
-CONFIG_CAN_DEV=m
 CONFIG_CAN_BFIN=m
 CONFIG_IRDA=m
 CONFIG_IRLAN=m
@@ -58,7 +54,6 @@ CONFIG_BFIN_SIR1=y
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 # CONFIG_FW_LOADER is not set
 CONFIG_MTD=y
-CONFIG_MTD_PARTITIONS=y
 CONFIG_MTD_CMDLINE_PARTS=y
 CONFIG_MTD_CHAR=m
 CONFIG_MTD_BLOCK=y
@@ -69,11 +64,18 @@ CONFIG_MTD_ROM=m
 CONFIG_MTD_PHYSMAP=m
 CONFIG_BLK_DEV_RAM=y
 CONFIG_NETDEVICES=y
-CONFIG_SMSC_PHY=y
-CONFIG_NET_ETHERNET=y
+CONFIG_NET_BFIN=y
 CONFIG_BFIN_MAC=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
+# CONFIG_NET_VENDOR_BROADCOM is not set
+# CONFIG_NET_VENDOR_CHELSIO is not set
+# CONFIG_NET_VENDOR_INTEL is not set
+# CONFIG_NET_VENDOR_MARVELL is not set
+# CONFIG_NET_VENDOR_MICREL is not set
+# CONFIG_NET_VENDOR_MICROCHIP is not set
+# CONFIG_NET_VENDOR_NATSEMI is not set
+# CONFIG_NET_VENDOR_SEEQ is not set
+# CONFIG_NET_VENDOR_SMSC is not set
+# CONFIG_NET_VENDOR_STMICRO is not set
 # CONFIG_WLAN is not set
 # CONFIG_INPUT_MOUSEDEV is not set
 CONFIG_INPUT_EVDEV=m
@@ -82,12 +84,12 @@ CONFIG_INPUT_EVDEV=m
 CONFIG_INPUT_MISC=y
 # CONFIG_SERIO is not set
 # CONFIG_VT is not set
-# CONFIG_DEVKMEM is not set
+# CONFIG_LEGACY_PTYS is not set
 CONFIG_BFIN_JTAG_COMM=m
+# CONFIG_DEVKMEM is not set
 CONFIG_SERIAL_BFIN=y
 CONFIG_SERIAL_BFIN_CONSOLE=y
 CONFIG_SERIAL_BFIN_UART0=y
-# CONFIG_LEGACY_PTYS is not set
 # CONFIG_HW_RANDOM is not set
 CONFIG_I2C=m
 CONFIG_I2C_CHARDEV=m
@@ -117,12 +119,9 @@ CONFIG_RTC_DRV_BFIN=y
 CONFIG_JFFS2_FS=m
 CONFIG_NFS_FS=m
 CONFIG_NFS_V3=y
-CONFIG_SMB_FS=m
-CONFIG_DEBUG_KERNEL=y
 CONFIG_DEBUG_SHIRQ=y
 CONFIG_DETECT_HUNG_TASK=y
 CONFIG_DEBUG_INFO=y
-# CONFIG_RCU_CPU_STALL_DETECTOR is not set
 # CONFIG_FTRACE is not set
 CONFIG_DEBUG_MMRS=y
 CONFIG_DEBUG_HWERR=y
diff --git a/arch/blackfin/configs/BF548-EZKIT_defconfig b/arch/blackfin/configs/BF548-EZKIT_defconfig
index 7a1e3bf2b04..e716fdfd2cf 100644
--- a/arch/blackfin/configs/BF548-EZKIT_defconfig
+++ b/arch/blackfin/configs/BF548-EZKIT_defconfig
@@ -5,7 +5,6 @@ CONFIG_IKCONFIG_PROC=y
 CONFIG_LOG_BUF_SHIFT=14
 CONFIG_BLK_DEV_INITRD=y
 CONFIG_EXPERT=y
-# CONFIG_SYSCTL_SYSCALL is not set
 # CONFIG_ELF_CORE is not set
 # CONFIG_FUTEX is not set
 # CONFIG_SIGNALFD is not set
@@ -85,10 +84,16 @@ CONFIG_ATA=y
 # CONFIG_SATA_PMP is not set
 CONFIG_PATA_BF54X=y
 CONFIG_NETDEVICES=y
-CONFIG_NET_ETHERNET=y
+# CONFIG_NET_VENDOR_BROADCOM is not set
+# CONFIG_NET_VENDOR_CHELSIO is not set
+# CONFIG_NET_VENDOR_INTEL is not set
+# CONFIG_NET_VENDOR_MARVELL is not set
+# CONFIG_NET_VENDOR_MICREL is not set
+# CONFIG_NET_VENDOR_MICROCHIP is not set
+# CONFIG_NET_VENDOR_NATSEMI is not set
+# CONFIG_NET_VENDOR_SEEQ is not set
 CONFIG_SMSC911X=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
+# CONFIG_NET_VENDOR_STMICRO is not set
 # CONFIG_WLAN is not set
 CONFIG_INPUT_FF_MEMLESS=m
 # CONFIG_INPUT_MOUSEDEV is not set
@@ -161,6 +166,7 @@ CONFIG_USB_MON=y
 CONFIG_USB_MUSB_HDRC=y
 CONFIG_USB_MUSB_BLACKFIN=y
 CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
 CONFIG_MMC=y
 CONFIG_MMC_BLOCK=m
 CONFIG_SDH_BFIN=y
@@ -187,7 +193,6 @@ CONFIG_NLS_CODEPAGE_437=m
 CONFIG_NLS_CODEPAGE_936=m
 CONFIG_NLS_ISO8859_1=m
 CONFIG_NLS_UTF8=m
-CONFIG_DEBUG_KERNEL=y
 CONFIG_DEBUG_SHIRQ=y
 CONFIG_DETECT_HUNG_TASK=y
 CONFIG_DEBUG_INFO=y
diff --git a/arch/blackfin/configs/BF561-EZKIT-SMP_defconfig b/arch/blackfin/configs/BF561-EZKIT-SMP_defconfig
index 78adbbf3982..680730eeaf2 100644
--- a/arch/blackfin/configs/BF561-EZKIT-SMP_defconfig
+++ b/arch/blackfin/configs/BF561-EZKIT-SMP_defconfig
@@ -4,9 +4,7 @@ CONFIG_IKCONFIG=y
 CONFIG_IKCONFIG_PROC=y
 CONFIG_LOG_BUF_SHIFT=14
 CONFIG_BLK_DEV_INITRD=y
-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
 CONFIG_EXPERT=y
-# CONFIG_SYSCTL_SYSCALL is not set
 # CONFIG_ELF_CORE is not set
 # CONFIG_FUTEX is not set
 # CONFIG_SIGNALFD is not set
@@ -23,17 +21,18 @@ CONFIG_MODULE_UNLOAD=y
 # CONFIG_IOSCHED_CFQ is not set
 CONFIG_PREEMPT_VOLUNTARY=y
 CONFIG_BF561=y
-CONFIG_SMP=y
 CONFIG_IRQ_TIMER0=10
 CONFIG_CLKIN_HZ=30000000
 CONFIG_HIGH_RES_TIMERS=y
 CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0
 CONFIG_BFIN_GPTIMERS=m
+CONFIG_BFIN_EXTMEM_WRITETHROUGH=y
+CONFIG_BFIN_L2_DCACHEABLE=y
+CONFIG_BFIN_L2_WRITETHROUGH=y
 CONFIG_C_CDPRIO=y
 CONFIG_BANK_3=0xAAC2
 CONFIG_BINFMT_FLAT=y
 CONFIG_BINFMT_ZFLAT=y
-CONFIG_PM=y
 CONFIG_NET=y
 CONFIG_PACKET=y
 CONFIG_UNIX=y
@@ -54,21 +53,26 @@ CONFIG_IRTTY_SIR=m
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 # CONFIG_FW_LOADER is not set
 CONFIG_MTD=y
-CONFIG_MTD_PARTITIONS=y
 CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_CHAR=m
+CONFIG_MTD_CHAR=y
 CONFIG_MTD_BLOCK=y
-CONFIG_MTD_CFI=m
-CONFIG_MTD_CFI_AMDSTD=m
+CONFIG_MTD_CFI=y
+CONFIG_MTD_CFI_AMDSTD=y
 CONFIG_MTD_RAM=y
 CONFIG_MTD_ROM=m
-CONFIG_MTD_PHYSMAP=m
+CONFIG_MTD_PHYSMAP=y
 CONFIG_BLK_DEV_RAM=y
 CONFIG_NETDEVICES=y
-CONFIG_NET_ETHERNET=y
+# CONFIG_NET_VENDOR_BROADCOM is not set
+# CONFIG_NET_VENDOR_CHELSIO is not set
+# CONFIG_NET_VENDOR_INTEL is not set
+# CONFIG_NET_VENDOR_MARVELL is not set
+# CONFIG_NET_VENDOR_MICREL is not set
+# CONFIG_NET_VENDOR_MICROCHIP is not set
+# CONFIG_NET_VENDOR_NATSEMI is not set
+# CONFIG_NET_VENDOR_SEEQ is not set
 CONFIG_SMC91X=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
+# CONFIG_NET_VENDOR_STMICRO is not set
 # CONFIG_WLAN is not set
 CONFIG_INPUT=m
 # CONFIG_INPUT_MOUSEDEV is not set
@@ -77,11 +81,11 @@ CONFIG_INPUT_EVDEV=m
 # CONFIG_INPUT_MOUSE is not set
 # CONFIG_SERIO is not set
 # CONFIG_VT is not set
-# CONFIG_DEVKMEM is not set
+# CONFIG_LEGACY_PTYS is not set
 CONFIG_BFIN_JTAG_COMM=m
+# CONFIG_DEVKMEM is not set
 CONFIG_SERIAL_BFIN=y
 CONFIG_SERIAL_BFIN_CONSOLE=y
-# CONFIG_LEGACY_PTYS is not set
 # CONFIG_HW_RANDOM is not set
 CONFIG_SPI=y
 CONFIG_SPI_BFIN5XX=y
@@ -95,12 +99,9 @@ CONFIG_BFIN_WDT=y
 CONFIG_JFFS2_FS=m
 CONFIG_NFS_FS=m
 CONFIG_NFS_V3=y
-CONFIG_SMB_FS=m
-CONFIG_DEBUG_KERNEL=y
 CONFIG_DEBUG_SHIRQ=y
 CONFIG_DETECT_HUNG_TASK=y
 CONFIG_DEBUG_INFO=y
-# CONFIG_RCU_CPU_STALL_DETECTOR is not set
 # CONFIG_FTRACE is not set
 CONFIG_DEBUG_MMRS=y
 CONFIG_DEBUG_HWERR=y
diff --git a/arch/blackfin/configs/BF561-EZKIT_defconfig b/arch/blackfin/configs/BF561-EZKIT_defconfig
index d3cd0f561c8..680730eeaf2 100644
--- a/arch/blackfin/configs/BF561-EZKIT_defconfig
+++ b/arch/blackfin/configs/BF561-EZKIT_defconfig
@@ -4,9 +4,7 @@ CONFIG_IKCONFIG=y
 CONFIG_IKCONFIG_PROC=y
 CONFIG_LOG_BUF_SHIFT=14
 CONFIG_BLK_DEV_INITRD=y
-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
 CONFIG_EXPERT=y
-# CONFIG_SYSCTL_SYSCALL is not set
 # CONFIG_ELF_CORE is not set
 # CONFIG_FUTEX is not set
 # CONFIG_SIGNALFD is not set
@@ -35,7 +33,6 @@ CONFIG_C_CDPRIO=y
 CONFIG_BANK_3=0xAAC2
 CONFIG_BINFMT_FLAT=y
 CONFIG_BINFMT_ZFLAT=y
-CONFIG_PM=y
 CONFIG_NET=y
 CONFIG_PACKET=y
 CONFIG_UNIX=y
@@ -56,7 +53,6 @@ CONFIG_IRTTY_SIR=m
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 # CONFIG_FW_LOADER is not set
 CONFIG_MTD=y
-CONFIG_MTD_PARTITIONS=y
 CONFIG_MTD_CMDLINE_PARTS=y
 CONFIG_MTD_CHAR=y
 CONFIG_MTD_BLOCK=y
@@ -67,10 +63,16 @@ CONFIG_MTD_ROM=m
 CONFIG_MTD_PHYSMAP=y
 CONFIG_BLK_DEV_RAM=y
 CONFIG_NETDEVICES=y
-CONFIG_NET_ETHERNET=y
+# CONFIG_NET_VENDOR_BROADCOM is not set
+# CONFIG_NET_VENDOR_CHELSIO is not set
+# CONFIG_NET_VENDOR_INTEL is not set
+# CONFIG_NET_VENDOR_MARVELL is not set
+# CONFIG_NET_VENDOR_MICREL is not set
+# CONFIG_NET_VENDOR_MICROCHIP is not set
+# CONFIG_NET_VENDOR_NATSEMI is not set
+# CONFIG_NET_VENDOR_SEEQ is not set
 CONFIG_SMC91X=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
+# CONFIG_NET_VENDOR_STMICRO is not set
 # CONFIG_WLAN is not set
 CONFIG_INPUT=m
 # CONFIG_INPUT_MOUSEDEV is not set
@@ -79,11 +81,11 @@ CONFIG_INPUT_EVDEV=m
 # CONFIG_INPUT_MOUSE is not set
 # CONFIG_SERIO is not set
 # CONFIG_VT is not set
-# CONFIG_DEVKMEM is not set
+# CONFIG_LEGACY_PTYS is not set
 CONFIG_BFIN_JTAG_COMM=m
+# CONFIG_DEVKMEM is not set
 CONFIG_SERIAL_BFIN=y
 CONFIG_SERIAL_BFIN_CONSOLE=y
-# CONFIG_LEGACY_PTYS is not set
 # CONFIG_HW_RANDOM is not set
 CONFIG_SPI=y
 CONFIG_SPI_BFIN5XX=y
@@ -97,12 +99,9 @@ CONFIG_BFIN_WDT=y
 CONFIG_JFFS2_FS=m
 CONFIG_NFS_FS=m
 CONFIG_NFS_V3=y
-CONFIG_SMB_FS=m
-CONFIG_DEBUG_KERNEL=y
 CONFIG_DEBUG_SHIRQ=y
 CONFIG_DETECT_HUNG_TASK=y
 CONFIG_DEBUG_INFO=y
-# CONFIG_RCU_CPU_STALL_DETECTOR is not set
 # CONFIG_FTRACE is not set
 CONFIG_DEBUG_MMRS=y
 CONFIG_DEBUG_HWERR=y
diff --git a/arch/blackfin/include/asm/atomic.h b/arch/blackfin/include/asm/atomic.h
index 54c6e2887e9..c8db653c72d 100644
--- a/arch/blackfin/include/asm/atomic.h
+++ b/arch/blackfin/include/asm/atomic.h
@@ -7,6 +7,8 @@
 #ifndef __ARCH_BLACKFIN_ATOMIC__
 #define __ARCH_BLACKFIN_ATOMIC__
 
+#include <asm/cmpxchg.h>
+
 #ifdef CONFIG_SMP
 
 #include <linux/linkage.h>
diff --git a/arch/blackfin/include/asm/barrier.h b/arch/blackfin/include/asm/barrier.h
new file mode 100644
index 00000000000..ebb189507dd
--- /dev/null
+++ b/arch/blackfin/include/asm/barrier.h
@@ -0,0 +1,48 @@
+/*
+ * Copyright 2004-2009 Analog Devices Inc.
+ *               Tony Kou (tonyko@lineo.ca)
+ *
+ * Licensed under the GPL-2 or later
+ */
+
+#ifndef _BLACKFIN_BARRIER_H
+#define _BLACKFIN_BARRIER_H
+
+#include <asm/cache.h>
+
+#define nop()  __asm__ __volatile__ ("nop;\n\t" : : )
+
+/*
+ * Force strict CPU ordering.
+ */
+#ifdef CONFIG_SMP
+
+#ifdef __ARCH_SYNC_CORE_DCACHE
+/* Force Core data cache coherence */
+# define mb()   do { barrier(); smp_check_barrier(); smp_mark_barrier(); } while (0)
+# define rmb()  do { barrier(); smp_check_barrier(); } while (0)
+# define wmb()  do { barrier(); smp_mark_barrier(); } while (0)
+# define read_barrier_depends() do { barrier(); smp_check_barrier(); } while (0)
+#else
+# define mb()   barrier()
+# define rmb()  barrier()
+# define wmb()  barrier()
+# define read_barrier_depends() do { } while (0)
+#endif
+
+#else /* !CONFIG_SMP */
+
+#define mb()    barrier()
+#define rmb()   barrier()
+#define wmb()   barrier()
+#define read_barrier_depends()  do { } while (0)
+
+#endif /* !CONFIG_SMP */
+
+#define smp_mb()  mb()
+#define smp_rmb() rmb()
+#define smp_wmb() wmb()
+#define set_mb(var, value) do { var = value; mb(); } while (0)
+#define smp_read_barrier_depends()      read_barrier_depends()
+
+#endif /* _BLACKFIN_BARRIER_H */
diff --git a/arch/blackfin/include/asm/bfin5xx_spi.h b/arch/blackfin/include/asm/bfin5xx_spi.h
index 5392583d025..fb95c853bb1 100644
--- a/arch/blackfin/include/asm/bfin5xx_spi.h
+++ b/arch/blackfin/include/asm/bfin5xx_spi.h
@@ -77,7 +77,6 @@ struct bfin5xx_spi_master {
 struct bfin5xx_spi_chip {
         u16 ctl_reg;
         u8 enable_dma;
-        u8 bits_per_word;
         u16 cs_chg_udelay; /* Some devices require 16-bit delays */
         /* Value to send if no TX value is supplied, usually 0x0 or 0xFFFF */
         u16 idle_tx_val;
diff --git a/arch/blackfin/include/asm/bfin_simple_timer.h b/arch/blackfin/include/asm/bfin_simple_timer.h
index 5248c133bc6..aadfb1ad1fa 100644
--- a/arch/blackfin/include/asm/bfin_simple_timer.h
+++ b/arch/blackfin/include/asm/bfin_simple_timer.h
@@ -11,9 +11,11 @@
 
 #define BFIN_SIMPLE_TIMER_IOCTL_MAGIC 't'
 
-#define BFIN_SIMPLE_TIMER_SET_PERIOD _IO (BFIN_SIMPLE_TIMER_IOCTL_MAGIC,  2)
-#define BFIN_SIMPLE_TIMER_START      _IO (BFIN_SIMPLE_TIMER_IOCTL_MAGIC,  6)
-#define BFIN_SIMPLE_TIMER_STOP       _IO (BFIN_SIMPLE_TIMER_IOCTL_MAGIC,  8)
-#define BFIN_SIMPLE_TIMER_READ       _IO (BFIN_SIMPLE_TIMER_IOCTL_MAGIC, 10)
+#define BFIN_SIMPLE_TIMER_SET_PERIOD _IO(BFIN_SIMPLE_TIMER_IOCTL_MAGIC,  2)
+#define BFIN_SIMPLE_TIMER_SET_WIDTH _IO(BFIN_SIMPLE_TIMER_IOCTL_MAGIC,  3)
+#define BFIN_SIMPLE_TIMER_SET_MODE _IO(BFIN_SIMPLE_TIMER_IOCTL_MAGIC,  4)
+#define BFIN_SIMPLE_TIMER_START      _IO(BFIN_SIMPLE_TIMER_IOCTL_MAGIC,  6)
+#define BFIN_SIMPLE_TIMER_STOP       _IO(BFIN_SIMPLE_TIMER_IOCTL_MAGIC,  8)
+#define BFIN_SIMPLE_TIMER_READ       _IO(BFIN_SIMPLE_TIMER_IOCTL_MAGIC, 10)
 
 #endif
diff --git a/arch/blackfin/include/asm/bfin_sport.h b/arch/blackfin/include/asm/bfin_sport.h
index f8568a31d0a..0afcfbd54a8 100644
--- a/arch/blackfin/include/asm/bfin_sport.h
+++ b/arch/blackfin/include/asm/bfin_sport.h
@@ -13,6 +13,7 @@
 #define NORM_MODE       0x0
 #define TDM_MODE        0x1
 #define I2S_MODE        0x2
+#define NDSO_MODE       0x3
 
 /* Data format, normal, a-law or u-law */
 #define NORM_FORMAT     0x0
@@ -56,6 +57,8 @@ struct sport_config {
 /* Userspace interface */
 #define SPORT_IOC_MAGIC         'P'
 #define SPORT_IOC_CONFIG        _IOWR('P', 0x01, struct sport_config)
+#define SPORT_IOC_GET_SYSTEMCLOCK         _IOR('P', 0x02, unsigned long)
+#define SPORT_IOC_SET_BAUDRATE            _IOW('P', 0x03, unsigned long)
 
 #ifdef __KERNEL__
 
diff --git a/arch/blackfin/include/asm/blackfin.h b/arch/blackfin/include/asm/blackfin.h
index 0928700b6bc..7be5368c051 100644
--- a/arch/blackfin/include/asm/blackfin.h
+++ b/arch/blackfin/include/asm/blackfin.h
@@ -17,22 +17,16 @@
 static inline void SSYNC(void)
 {
         int _tmp;
-        if (ANOMALY_05000312)
+        if (ANOMALY_05000312 || ANOMALY_05000244)
                 __asm__ __volatile__(
                         "cli %0;"
                         "nop;"
                         "nop;"
+                        "nop;"
                         "ssync;"
                         "sti %0;"
                         : "=d" (_tmp)
                 );
-        else if (ANOMALY_05000244)
-                __asm__ __volatile__(
-                        "nop;"
-                        "nop;"
-                        "nop;"
-                        "ssync;"
-                );
         else
                 __asm__ __volatile__("ssync;");
 }
@@ -41,22 +35,16 @@ static inline void SSYNC(void)
 static inline void CSYNC(void)
 {
         int _tmp;
-        if (ANOMALY_05000312)
+        if (ANOMALY_05000312 || ANOMALY_05000244)
                 __asm__ __volatile__(
                         "cli %0;"
                         "nop;"
                         "nop;"
+                        "nop;"
                         "csync;"
                         "sti %0;"
                         : "=d" (_tmp)
                 );
-        else if (ANOMALY_05000244)
-                __asm__ __volatile__(
-                        "nop;"
-                        "nop;"
-                        "nop;"
-                        "csync;"
-                );
         else
                 __asm__ __volatile__("csync;");
 }
@@ -73,18 +61,26 @@ static inline void CSYNC(void)
 #define ssync(x) SSYNC(x)
 #define csync(x) CSYNC(x)
 
-#if ANOMALY_05000312
-#define SSYNC(scratch) cli scratch; nop; nop; SSYNC; sti scratch;
-#define CSYNC(scratch) cli scratch; nop; nop; CSYNC; sti scratch;
-
-#elif ANOMALY_05000244
-#define SSYNC(scratch) nop; nop; nop; SSYNC;
-#define CSYNC(scratch) nop; nop; nop; CSYNC;
+#if ANOMALY_05000312 || ANOMALY_05000244
+#define SSYNC(scratch)  \
+do {                    \
+        cli scratch;    \
+        nop; nop; nop;  \
+        SSYNC;          \
+        sti scratch;    \
+} while (0)
+
+#define CSYNC(scratch)  \
+do {                    \
+        cli scratch;    \
+        nop; nop; nop;  \
+        CSYNC;          \
+        sti scratch;    \
+} while (0)
 
 #else
 #define SSYNC(scratch) SSYNC;
 #define CSYNC(scratch) CSYNC;
-
 #endif /* ANOMALY_05000312 & ANOMALY_05000244 handling */
 
 #endif /* __ASSEMBLY__ */
diff --git a/arch/blackfin/include/asm/cmpxchg.h b/arch/blackfin/include/asm/cmpxchg.h
new file mode 100644
index 00000000000..ba2484f4cb2
--- /dev/null
+++ b/arch/blackfin/include/asm/cmpxchg.h
@@ -0,0 +1,132 @@
+/*
+ * Copyright 2004-2011 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#ifndef __ARCH_BLACKFIN_CMPXCHG__
+#define __ARCH_BLACKFIN_CMPXCHG__
+
+#ifdef CONFIG_SMP
+
+#include <linux/linkage.h>
+
+asmlinkage unsigned long __raw_xchg_1_asm(volatile void *ptr, unsigned long value);
+asmlinkage unsigned long __raw_xchg_2_asm(volatile void *ptr, unsigned long value);
+asmlinkage unsigned long __raw_xchg_4_asm(volatile void *ptr, unsigned long value);
+asmlinkage unsigned long __raw_cmpxchg_1_asm(volatile void *ptr,
+                                        unsigned long new, unsigned long old);
+asmlinkage unsigned long __raw_cmpxchg_2_asm(volatile void *ptr,
+                                        unsigned long new, unsigned long old);
+asmlinkage unsigned long __raw_cmpxchg_4_asm(volatile void *ptr,
+                                        unsigned long new, unsigned long old);
+
+static inline unsigned long __xchg(unsigned long x, volatile void *ptr,
+                                   int size)
+{
+        unsigned long tmp;
+
+        switch (size) {
+        case 1:
+                tmp = __raw_xchg_1_asm(ptr, x);
+                break;
+        case 2:
+                tmp = __raw_xchg_2_asm(ptr, x);
+                break;
+        case 4:
+                tmp = __raw_xchg_4_asm(ptr, x);
+                break;
+        }
+
+        return tmp;
+}
+
+/*
+ * Atomic compare and exchange.  Compare OLD with MEM, if identical,
+ * store NEW in MEM.  Return the initial value in MEM.  Success is
+ * indicated by comparing RETURN with OLD.
+ */
+static inline unsigned long __cmpxchg(volatile void *ptr, unsigned long old,
+                                      unsigned long new, int size)
+{
+        unsigned long tmp;
+
+        switch (size) {
+        case 1:
+                tmp = __raw_cmpxchg_1_asm(ptr, new, old);
+                break;
+        case 2:
+                tmp = __raw_cmpxchg_2_asm(ptr, new, old);
+                break;
+        case 4:
+                tmp = __raw_cmpxchg_4_asm(ptr, new, old);
+                break;
+        }
+
+        return tmp;
+}
+#define cmpxchg(ptr, o, n) \
+        ((__typeof__(*(ptr)))__cmpxchg((ptr), (unsigned long)(o), \
+                (unsigned long)(n), sizeof(*(ptr))))
+
+#else /* !CONFIG_SMP */
+
+#include <mach/blackfin.h>
+#include <asm/irqflags.h>
+
+struct __xchg_dummy {
+        unsigned long a[100];
+};
+#define __xg(x) ((volatile struct __xchg_dummy *)(x))
+
+static inline unsigned long __xchg(unsigned long x, volatile void *ptr,
+                                   int size)
+{
+        unsigned long tmp = 0;
+        unsigned long flags;
+
+        flags = hard_local_irq_save();
+
+        switch (size) {
+        case 1:
+                __asm__ __volatile__
+                        ("%0 = b%2 (z);\n\t"
+                         "b%2 = %1;\n\t"
+                         : "=&d" (tmp) : "d" (x), "m" (*__xg(ptr)) : "memory");
+                break;
+        case 2:
+                __asm__ __volatile__
+                        ("%0 = w%2 (z);\n\t"
+                         "w%2 = %1;\n\t"
+                         : "=&d" (tmp) : "d" (x), "m" (*__xg(ptr)) : "memory");
+                break;
+        case 4:
+                __asm__ __volatile__
+                        ("%0 = %2;\n\t"
+                         "%2 = %1;\n\t"
+                         : "=&d" (tmp) : "d" (x), "m" (*__xg(ptr)) : "memory");
+                break;
+        }
+        hard_local_irq_restore(flags);
+        return tmp;
+}
+
+#include <asm-generic/cmpxchg-local.h>
+
+/*
+ * cmpxchg_local and cmpxchg64_local are atomic wrt current CPU. Always make
+ * them available.
+ */
+#define cmpxchg_local(ptr, o, n)                                               \
+        ((__typeof__(*(ptr)))__cmpxchg_local_generic((ptr), (unsigned long)(o),\
+                        (unsigned long)(n), sizeof(*(ptr))))
+#define cmpxchg64_local(ptr, o, n) __cmpxchg64_local_generic((ptr), (o), (n))
+
+#include <asm-generic/cmpxchg.h>
+
+#endif /* !CONFIG_SMP */
+
+#define xchg(ptr, x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x), (ptr), sizeof(*(ptr))))
+#define tas(ptr) ((void)xchg((ptr), 1))
+
+#endif /* __ARCH_BLACKFIN_CMPXCHG__ */
diff --git a/arch/blackfin/include/asm/exec.h b/arch/blackfin/include/asm/exec.h
new file mode 100644
index 00000000000..54c2e1db274
--- /dev/null
+++ b/arch/blackfin/include/asm/exec.h
@@ -0,0 +1 @@
+/* define arch_align_stack() here */
diff --git a/arch/blackfin/include/asm/irq.h b/arch/blackfin/include/asm/irq.h
index 12f4060a31b..89de539ed01 100644
--- a/arch/blackfin/include/asm/irq.h
+++ b/arch/blackfin/include/asm/irq.h
@@ -38,8 +38,4 @@
 
 #include <asm-generic/irq.h>
 
-#ifdef CONFIG_NMI_WATCHDOG
-# define ARCH_HAS_NMI_WATCHDOG
-#endif
-
 #endif                          /* _BFIN_IRQ_H_ */
diff --git a/arch/blackfin/include/asm/irq_handler.h b/arch/blackfin/include/asm/irq_handler.h
index ee73f79aef1..4fbf83575db 100644
--- a/arch/blackfin/include/asm/irq_handler.h
+++ b/arch/blackfin/include/asm/irq_handler.h
@@ -9,6 +9,7 @@
 
 #include <linux/types.h>
 #include <linux/linkage.h>
+#include <mach/irq.h>
 
 /* init functions only */
 extern int __init init_arch_irq(void);
diff --git a/arch/blackfin/include/asm/kgdb.h b/arch/blackfin/include/asm/kgdb.h
index aaf884591b0..2703ddeeb5d 100644
--- a/arch/blackfin/include/asm/kgdb.h
+++ b/arch/blackfin/include/asm/kgdb.h
@@ -109,6 +109,7 @@ static inline void arch_kgdb_breakpoint(void)
 # define CACHE_FLUSH_IS_SAFE    1
 #endif
 #define GDB_ADJUSTS_BREAK_OFFSET
+#define GDB_SKIP_HW_WATCH_TEST
 #define HW_INST_WATCHPOINT_NUM  6
 #define HW_WATCHPOINT_NUM       8
 #define TYPE_INST_WATCHPOINT    0
diff --git a/arch/blackfin/include/asm/mmu_context.h b/arch/blackfin/include/asm/mmu_context.h
index 3828c70e7a2..15b16d3e8de 100644
--- a/arch/blackfin/include/asm/mmu_context.h
+++ b/arch/blackfin/include/asm/mmu_context.h
@@ -30,8 +30,11 @@ extern void *l1sram_alloc_max(void*);
 static inline void free_l1stack(void)
 {
         nr_l1stack_tasks--;
-        if (nr_l1stack_tasks == 0)
+        if (nr_l1stack_tasks == 0) {
                 l1sram_free(l1_stack_base);
+                l1_stack_base = NULL;
+                l1_stack_len = 0;
+        }
 }
 
 static inline unsigned long
diff --git a/arch/blackfin/include/asm/switch_to.h b/arch/blackfin/include/asm/switch_to.h
new file mode 100644
index 00000000000..aaf671be924
--- /dev/null
+++ b/arch/blackfin/include/asm/switch_to.h
@@ -0,0 +1,39 @@
+/*
+ * Copyright 2004-2009 Analog Devices Inc.
+ *               Tony Kou (tonyko@lineo.ca)
+ *
+ * Licensed under the GPL-2 or later
+ */
+
+#ifndef _BLACKFIN_SWITCH_TO_H
+#define _BLACKFIN_SWITCH_TO_H
+
+#define prepare_to_switch()     do { } while(0)
+
+/*
+ * switch_to(n) should switch tasks to task ptr, first checking that
+ * ptr isn't the current task, in which case it does nothing.
+ */
+
+#include <asm/l1layout.h>
+#include <asm/mem_map.h>
+
+asmlinkage struct task_struct *resume(struct task_struct *prev, struct task_struct *next);
+
+#ifndef CONFIG_SMP
+#define switch_to(prev,next,last) \
+do {    \
+        memcpy (&task_thread_info(prev)->l1_task_info, L1_SCRATCH_TASK_INFO, \
+                sizeof *L1_SCRATCH_TASK_INFO); \
+        memcpy (L1_SCRATCH_TASK_INFO, &task_thread_info(next)->l1_task_info, \
+                sizeof *L1_SCRATCH_TASK_INFO); \
+        (last) = resume (prev, next);   \
+} while (0)
+#else
+#define switch_to(prev, next, last) \
+do {    \
+        (last) = resume(prev, next);   \
+} while (0)
+#endif
+
+#endif /* _BLACKFIN_SWITCH_TO_H */
diff --git a/arch/blackfin/include/asm/system.h b/arch/blackfin/include/asm/system.h
index 44bd0cced72..a7f40578587 100644
--- a/arch/blackfin/include/asm/system.h
+++ b/arch/blackfin/include/asm/system.h
@@ -1,192 +1,5 @@
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- *               Tony Kou (tonyko@lineo.ca)
- *
- * Licensed under the GPL-2 or later
- */
-
-#ifndef _BLACKFIN_SYSTEM_H
-#define _BLACKFIN_SYSTEM_H
-
-#include <linux/linkage.h>
-#include <linux/irqflags.h>
-#include <mach/anomaly.h>
-#include <asm/cache.h>
-#include <asm/pda.h>
-#include <asm/irq.h>
-
-/*
- * Force strict CPU ordering.
- */
-#define nop()  __asm__ __volatile__ ("nop;\n\t" : : )
-#define smp_mb()  mb()
-#define smp_rmb() rmb()
-#define smp_wmb() wmb()
-#define set_mb(var, value) do { var = value; mb(); } while (0)
-#define smp_read_barrier_depends()      read_barrier_depends()
-
-#ifdef CONFIG_SMP
-asmlinkage unsigned long __raw_xchg_1_asm(volatile void *ptr, unsigned long value);
-asmlinkage unsigned long __raw_xchg_2_asm(volatile void *ptr, unsigned long value);
-asmlinkage unsigned long __raw_xchg_4_asm(volatile void *ptr, unsigned long value);
-asmlinkage unsigned long __raw_cmpxchg_1_asm(volatile void *ptr,
-                                        unsigned long new, unsigned long old);
-asmlinkage unsigned long __raw_cmpxchg_2_asm(volatile void *ptr,
-                                        unsigned long new, unsigned long old);
-asmlinkage unsigned long __raw_cmpxchg_4_asm(volatile void *ptr,
-                                        unsigned long new, unsigned long old);
-
-#ifdef __ARCH_SYNC_CORE_DCACHE
-/* Force Core data cache coherence */
-# define mb()   do { barrier(); smp_check_barrier(); smp_mark_barrier(); } while (0)
-# define rmb()  do { barrier(); smp_check_barrier(); } while (0)
-# define wmb()  do { barrier(); smp_mark_barrier(); } while (0)
-# define read_barrier_depends() do { barrier(); smp_check_barrier(); } while (0)
-#else
-# define mb()   barrier()
-# define rmb()  barrier()
-# define wmb()  barrier()
-# define read_barrier_depends() do { } while (0)
-#endif
-
-static inline unsigned long __xchg(unsigned long x, volatile void *ptr,
-                                   int size)
-{
-        unsigned long tmp;
-
-        switch (size) {
-        case 1:
-                tmp = __raw_xchg_1_asm(ptr, x);
-                break;
-        case 2:
-                tmp = __raw_xchg_2_asm(ptr, x);
-                break;
-        case 4:
-                tmp = __raw_xchg_4_asm(ptr, x);
-                break;
-        }
-
-        return tmp;
-}
-
-/*
- * Atomic compare and exchange.  Compare OLD with MEM, if identical,
- * store NEW in MEM.  Return the initial value in MEM.  Success is
- * indicated by comparing RETURN with OLD.
- */
-static inline unsigned long __cmpxchg(volatile void *ptr, unsigned long old,
-                                      unsigned long new, int size)
-{
-        unsigned long tmp;
-
-        switch (size) {
-        case 1:
-                tmp = __raw_cmpxchg_1_asm(ptr, new, old);
-                break;
-        case 2:
-                tmp = __raw_cmpxchg_2_asm(ptr, new, old);
-                break;
-        case 4:
-                tmp = __raw_cmpxchg_4_asm(ptr, new, old);
-                break;
-        }
-
-        return tmp;
-}
-#define cmpxchg(ptr, o, n) \
-        ((__typeof__(*(ptr)))__cmpxchg((ptr), (unsigned long)(o), \
-                (unsigned long)(n), sizeof(*(ptr))))
-
-#else /* !CONFIG_SMP */
-
-#define mb()    barrier()
-#define rmb()   barrier()
-#define wmb()   barrier()
-#define read_barrier_depends()  do { } while (0)
-
-struct __xchg_dummy {
-        unsigned long a[100];
-};
-#define __xg(x) ((volatile struct __xchg_dummy *)(x))
-
-#include <mach/blackfin.h>
-
-static inline unsigned long __xchg(unsigned long x, volatile void *ptr,
-                                   int size)
-{
-        unsigned long tmp = 0;
-        unsigned long flags;
-
-        flags = hard_local_irq_save();
-
-        switch (size) {
-        case 1:
-                __asm__ __volatile__
-                        ("%0 = b%2 (z);\n\t"
-                         "b%2 = %1;\n\t"
-                         : "=&d" (tmp) : "d" (x), "m" (*__xg(ptr)) : "memory");
-                break;
-        case 2:
-                __asm__ __volatile__
-                        ("%0 = w%2 (z);\n\t"
-                         "w%2 = %1;\n\t"
-                         : "=&d" (tmp) : "d" (x), "m" (*__xg(ptr)) : "memory");
-                break;
-        case 4:
-                __asm__ __volatile__
-                        ("%0 = %2;\n\t"
-                         "%2 = %1;\n\t"
-                         : "=&d" (tmp) : "d" (x), "m" (*__xg(ptr)) : "memory");
-                break;
-        }
-        hard_local_irq_restore(flags);
-        return tmp;
-}
-
-#include <asm-generic/cmpxchg-local.h>
-
-/*
- * cmpxchg_local and cmpxchg64_local are atomic wrt current CPU. Always make
- * them available.
- */
-#define cmpxchg_local(ptr, o, n)                                               \
-        ((__typeof__(*(ptr)))__cmpxchg_local_generic((ptr), (unsigned long)(o),\
-                        (unsigned long)(n), sizeof(*(ptr))))
-#define cmpxchg64_local(ptr, o, n) __cmpxchg64_local_generic((ptr), (o), (n))
-
-#include <asm-generic/cmpxchg.h>
-
-#endif /* !CONFIG_SMP */
-
-#define xchg(ptr, x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x), (ptr), sizeof(*(ptr))))
-#define tas(ptr) ((void)xchg((ptr), 1))
-
-#define prepare_to_switch()     do { } while(0)
-
-/*
- * switch_to(n) should switch tasks to task ptr, first checking that
- * ptr isn't the current task, in which case it does nothing.
- */
-
-#include <asm/l1layout.h>
-#include <asm/mem_map.h>
-
-asmlinkage struct task_struct *resume(struct task_struct *prev, struct task_struct *next);
-
-#ifndef CONFIG_SMP
-#define switch_to(prev,next,last) \
-do {    \
-        memcpy (&task_thread_info(prev)->l1_task_info, L1_SCRATCH_TASK_INFO, \
-                sizeof *L1_SCRATCH_TASK_INFO); \
-        memcpy (L1_SCRATCH_TASK_INFO, &task_thread_info(next)->l1_task_info, \
-                sizeof *L1_SCRATCH_TASK_INFO); \
-        (last) = resume (prev, next);   \
-} while (0)
-#else
-#define switch_to(prev, next, last) \
-do {    \
-        (last) = resume(prev, next);   \
-} while (0)
-#endif
-
-#endif  /* _BLACKFIN_SYSTEM_H */
+/* FILE TO BE DELETED. DO NOT ADD STUFF HERE! */
+#include <asm/barrier.h>
+#include <asm/cmpxchg.h>
+#include <asm/exec.h>
+#include <asm/switch_to.h>
diff --git a/arch/blackfin/include/asm/thread_info.h b/arch/blackfin/include/asm/thread_info.h
index 53ad10005ae..02560fd8a12 100644
--- a/arch/blackfin/include/asm/thread_info.h
+++ b/arch/blackfin/include/asm/thread_info.h
@@ -100,6 +100,7 @@ static inline struct thread_info *current_thread_info(void)
                                            TIF_NEED_RESCHED */
 #define TIF_MEMDIE              4       /* is terminating due to OOM killer */
 #define TIF_RESTORE_SIGMASK     5       /* restore signal mask in do_signal() */
+#define TIF_FREEZE              6       /* is freezing for suspend */
 #define TIF_IRQ_SYNC            7       /* sync pipeline stage */
 #define TIF_NOTIFY_RESUME       8       /* callback before returning to user */
 #define TIF_SINGLESTEP          9
@@ -110,6 +111,7 @@ static inline struct thread_info *current_thread_info(void)
 #define _TIF_NEED_RESCHED       (1<<TIF_NEED_RESCHED)
 #define _TIF_POLLING_NRFLAG     (1<<TIF_POLLING_NRFLAG)
 #define _TIF_RESTORE_SIGMASK    (1<<TIF_RESTORE_SIGMASK)
+#define _TIF_FREEZE             (1<<TIF_FREEZE)
 #define _TIF_IRQ_SYNC           (1<<TIF_IRQ_SYNC)
 #define _TIF_NOTIFY_RESUME      (1<<TIF_NOTIFY_RESUME)
 #define _TIF_SINGLESTEP         (1<<TIF_SINGLESTEP)
diff --git a/arch/blackfin/include/asm/unistd.h b/arch/blackfin/include/asm/unistd.h
index 0ccba60b9cc..75ec9df5318 100644
--- a/arch/blackfin/include/asm/unistd.h
+++ b/arch/blackfin/include/asm/unistd.h
@@ -399,8 +399,10 @@
 #define __NR_syncfs             378
 #define __NR_setns              379
 #define __NR_sendmmsg           380
+#define __NR_process_vm_readv   381
+#define __NR_process_vm_writev  382
 
-#define __NR_syscall            381
+#define __NR_syscall            383
 #define NR_syscalls             __NR_syscall
 
 /* Old optional stuff no one actually uses */
diff --git a/arch/blackfin/kernel/Makefile b/arch/blackfin/kernel/Makefile
index 1f88edd4572..9a0d6d70644 100644
--- a/arch/blackfin/kernel/Makefile
+++ b/arch/blackfin/kernel/Makefile
@@ -7,7 +7,7 @@ extra-y := init_task.o vmlinux.lds
 obj-y := \
         entry.o process.o bfin_ksyms.o ptrace.o setup.o signal.o \
         sys_bfin.o traps.o irqchip.o dma-mapping.o flat.o \
-        fixed_code.o reboot.o bfin_gpio.o bfin_dma_5xx.o \
+        fixed_code.o reboot.o bfin_gpio.o bfin_dma.o \
         exception.o dumpstack.o
 
 ifeq ($(CONFIG_GENERIC_CLOCKEVENTS),y)
diff --git a/arch/blackfin/kernel/asm-offsets.c b/arch/blackfin/kernel/asm-offsets.c
index 17e35465a41..37fcae95021 100644
--- a/arch/blackfin/kernel/asm-offsets.c
+++ b/arch/blackfin/kernel/asm-offsets.c
@@ -14,6 +14,7 @@
 #include <linux/irq.h>
 #include <linux/thread_info.h>
 #include <linux/kbuild.h>
+#include <asm/pda.h>
 
 int main(void)
 {
diff --git a/arch/blackfin/kernel/bfin_dma_5xx.c b/arch/blackfin/kernel/bfin_dma.c
index 71dbaa4a48a..40c2ed61258 100644
--- a/arch/blackfin/kernel/bfin_dma_5xx.c
+++ b/arch/blackfin/kernel/bfin_dma.c
@@ -1,5 +1,5 @@
 /*
- * bfin_dma_5xx.c - Blackfin DMA implementation
+ * bfin_dma.c - Blackfin DMA implementation
  *
  * Copyright 2004-2008 Analog Devices Inc.
  *
@@ -218,6 +218,9 @@ int blackfin_dma_suspend(void)
                         dma_ch[i].saved_peripheral_map = dma_ch[i].regs->peripheral_map;
         }
 
+#if ANOMALY_05000480
+        bfin_write_DMAC_TC_PER(0x0);
+#endif
         return 0;
 }
 
@@ -231,6 +234,9 @@ void blackfin_dma_resume(void)
                 if (i < MAX_DMA_SUSPEND_CHANNELS)
                         dma_ch[i].regs->peripheral_map = dma_ch[i].saved_peripheral_map;
         }
+#if ANOMALY_05000480
+        bfin_write_DMAC_TC_PER(0x0111);
+#endif
 }
 #endif
 
diff --git a/arch/blackfin/kernel/cplb-mpu/cplbmgr.c b/arch/blackfin/kernel/cplb-mpu/cplbmgr.c
index 8de92299b3e..b56bd8514b7 100644
--- a/arch/blackfin/kernel/cplb-mpu/cplbmgr.c
+++ b/arch/blackfin/kernel/cplb-mpu/cplbmgr.c
@@ -120,6 +120,7 @@ MGR_ATTR static noinline int dcplb_miss(unsigned int cpu)
                 d_data = L2_DMEMORY;
         } else if (addr >= physical_mem_end) {
                 if (addr >= ASYNC_BANK0_BASE && addr < ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE) {
+#if defined(CONFIG_ROMFS_ON_MTD) && defined(CONFIG_MTD_ROM)
                         mask = current_rwx_mask[cpu];
                         if (mask) {
                                 int page = (addr - (ASYNC_BANK0_BASE - _ramend)) >> PAGE_SHIFT;
@@ -129,6 +130,7 @@ MGR_ATTR static noinline int dcplb_miss(unsigned int cpu)
                                 if (mask[idx] & bit)
                                         d_data |= CPLB_USER_RD;
                         }
+#endif
                 } else if (addr >= BOOT_ROM_START && addr < BOOT_ROM_START + BOOT_ROM_LENGTH
                     && (status & (FAULT_RW | FAULT_USERSUPV)) == FAULT_USERSUPV) {
                         addr &= ~(1 * 1024 * 1024 - 1);
diff --git a/arch/blackfin/kernel/ipipe.c b/arch/blackfin/kernel/ipipe.c
index dbe11220cc5..f657b38163e 100644
--- a/arch/blackfin/kernel/ipipe.c
+++ b/arch/blackfin/kernel/ipipe.c
@@ -31,7 +31,6 @@
 #include <linux/kthread.h>
 #include <linux/unistd.h>
 #include <linux/io.h>
-#include <asm/system.h>
 #include <linux/atomic.h>
 #include <asm/irq_handler.h>
 
diff --git a/arch/blackfin/kernel/kgdb_test.c b/arch/blackfin/kernel/kgdb_test.c
index 4a7dcfea98a..18ab004aea1 100644
--- a/arch/blackfin/kernel/kgdb_test.c
+++ b/arch/blackfin/kernel/kgdb_test.c
@@ -13,7 +13,6 @@
 
 #include <asm/current.h>
 #include <asm/uaccess.h>
-#include <asm/system.h>
 
 #include <asm/blackfin.h>
 
diff --git a/arch/blackfin/kernel/process.c b/arch/blackfin/kernel/process.c
index a80a643f369..c0f4fe287eb 100644
--- a/arch/blackfin/kernel/process.c
+++ b/arch/blackfin/kernel/process.c
@@ -19,6 +19,7 @@
 #include <asm/blackfin.h>
 #include <asm/fixed_code.h>
 #include <asm/mem_map.h>
+#include <asm/irq.h>
 
 asmlinkage void ret_from_fork(void);
 
diff --git a/arch/blackfin/kernel/ptrace.c b/arch/blackfin/kernel/ptrace.c
index 75089f80855..e1f88e028cf 100644
--- a/arch/blackfin/kernel/ptrace.c
+++ b/arch/blackfin/kernel/ptrace.c
@@ -20,7 +20,6 @@
 
 #include <asm/page.h>
 #include <asm/pgtable.h>
-#include <asm/system.h>
 #include <asm/processor.h>
 #include <asm/asm-offsets.h>
 #include <asm/dma.h>
diff --git a/arch/blackfin/kernel/reboot.c b/arch/blackfin/kernel/reboot.c
index c4c0081b199..b0434f89e8d 100644
--- a/arch/blackfin/kernel/reboot.c
+++ b/arch/blackfin/kernel/reboot.c
@@ -9,7 +9,6 @@
 #include <linux/interrupt.h>
 #include <asm/bfin-global.h>
 #include <asm/reboot.h>
-#include <asm/system.h>
 #include <asm/bfrom.h>
 
 /* A system soft reset makes external memory unusable so force
diff --git a/arch/blackfin/kernel/setup.c b/arch/blackfin/kernel/setup.c
index d6102c86d03..2aa01936850 100644
--- a/arch/blackfin/kernel/setup.c
+++ b/arch/blackfin/kernel/setup.c
@@ -30,6 +30,7 @@
 #include <asm/fixed_code.h>
 #include <asm/early_printk.h>
 #include <asm/irq_handler.h>
+#include <asm/pda.h>
 
 u16 _bfin_swrst;
 EXPORT_SYMBOL(_bfin_swrst);
diff --git a/arch/blackfin/kernel/trace.c b/arch/blackfin/kernel/trace.c
index 050db44fe91..44bbf2f564c 100644
--- a/arch/blackfin/kernel/trace.c
+++ b/arch/blackfin/kernel/trace.c
@@ -21,6 +21,7 @@
 #include <asm/fixed_code.h>
 #include <asm/traps.h>
 #include <asm/irq_handler.h>
+#include <asm/pda.h>
 
 void decode_address(char *buf, unsigned long address)
 {
diff --git a/arch/blackfin/kernel/traps.c b/arch/blackfin/kernel/traps.c
index 655f25d139a..de5c2c3ebd9 100644
--- a/arch/blackfin/kernel/traps.c
+++ b/arch/blackfin/kernel/traps.c
@@ -17,6 +17,7 @@
 #include <asm/trace.h>
 #include <asm/fixed_code.h>
 #include <asm/pseudo_instructions.h>
+#include <asm/pda.h>
 
 #ifdef CONFIG_KGDB
 # include <linux/kgdb.h>
diff --git a/arch/blackfin/lib/ins.S b/arch/blackfin/lib/ins.S
index 79caccea85c..d59608deccc 100644
--- a/arch/blackfin/lib/ins.S
+++ b/arch/blackfin/lib/ins.S
@@ -66,7 +66,7 @@
  *  - turns interrupts off every loop (low overhead, but longer latency)
  *  - DMA version, which do not suffer from this issue. DMA versions have
  *      different name (prefixed by dma_ ), and are located in
- *      ../kernel/bfin_dma_5xx.c
+ *      ../kernel/bfin_dma.c
  * Using the dma related functions are recommended for transferring large
  * buffers in/out of FIFOs.
  */
diff --git a/arch/blackfin/mach-bf537/boards/pnav10.c b/arch/blackfin/mach-bf537/boards/pnav10.c
index e9507feea31..6b395510405 100644
--- a/arch/blackfin/mach-bf537/boards/pnav10.c
+++ b/arch/blackfin/mach-bf537/boards/pnav10.c
@@ -101,7 +101,6 @@ static struct platform_device smc91x_device = {
 
 #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
 #include <linux/bfin_mac.h>
-#include <linux/export.h>
 static const unsigned short bfin_mac_peripherals[] = P_RMII0;
 
 static struct bfin_phydev_platform_data bfin_phydev_data[] = {
diff --git a/arch/blackfin/mach-bf537/boards/stamp.c b/arch/blackfin/mach-bf537/boards/stamp.c
index 0b807253f4d..f3562b0922a 100644
--- a/arch/blackfin/mach-bf537/boards/stamp.c
+++ b/arch/blackfin/mach-bf537/boards/stamp.c
@@ -975,7 +975,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
         },
 #endif
 
-#if defined(CONFIG_SND_BF5XX_SOC_AD193X) || defined(CONFIG_SND_BF5XX_SOC_AD193X_MODULE)
+#ifdef CONFIG_SND_SOC_AD193X_SPI
         {
                 .modalias = "ad193x",
                 .max_speed_hz = 3125000,     /* max spi clock (SCK) speed in HZ */
@@ -2171,7 +2171,7 @@ static unsigned long adt7316_i2c_data[2] = {
 #endif
 
 static struct i2c_board_info __initdata bfin_i2c_board_info[] = {
-#if defined(CONFIG_SND_BF5XX_SOC_AD193X) || defined(CONFIG_SND_BF5XX_SOC_AD193X_MODULE)
+#ifdef CONFIG_SND_SOC_AD193X_I2C
         {
                 I2C_BOARD_INFO("ad1937", 0x04),
         },
@@ -2593,6 +2593,21 @@ static struct platform_device bfin_ac97_pcm = {
 };
 #endif
 
+#if defined(CONFIG_SND_BF5XX_SOC_AD73311) || \
+                                defined(CONFIG_SND_BF5XX_SOC_AD73311_MODULE)
+static const unsigned ad73311_gpio[] = {
+        GPIO_PF4,
+};
+
+static struct platform_device bfin_ad73311_machine = {
+        .name = "bfin-snd-ad73311",
+        .id = 1,
+        .dev = {
+                .platform_data = (void *)ad73311_gpio,
+        },
+};
+#endif
+
 #if defined(CONFIG_SND_SOC_AD73311) || defined(CONFIG_SND_SOC_AD73311_MODULE)
 static struct platform_device bfin_ad73311_codec_device = {
         .name = "ad73311",
@@ -2862,6 +2877,11 @@ static struct platform_device *stamp_devices[] __initdata = {
         &bfin_ac97_pcm,
 #endif
 
+#if defined(CONFIG_SND_BF5XX_SOC_AD73311) || \
+                defined(CONFIG_SND_BF5XX_SOC_AD73311_MODULE)
+        &bfin_ad73311_machine,
+#endif
+
 #if defined(CONFIG_SND_SOC_AD73311) || defined(CONFIG_SND_SOC_AD73311_MODULE)
         &bfin_ad73311_codec_device,
 #endif
diff --git a/arch/blackfin/mach-bf548/boards/ezkit.c b/arch/blackfin/mach-bf548/boards/ezkit.c
index 3ea45f8bd61..4cadaf8d0b5 100644
--- a/arch/blackfin/mach-bf548/boards/ezkit.c
+++ b/arch/blackfin/mach-bf548/boards/ezkit.c
@@ -1237,6 +1237,8 @@ static struct bfin_capture_config bfin_capture_data = {
         },
         .ppi_info = &ppi_info,
         .ppi_control = (POLC | PACKEN | DLEN_8 | XFR_TYPE | 0x20),
+        .int_mask = 0xFFFFFFFF, /* disable error interrupt on eppi */
+        .blank_clocks = 8, /* 8 clocks as SAV and EAV */
 };
 #endif
 
@@ -1293,6 +1295,11 @@ static struct platform_device i2c_bfin_twi1_device = {
 #endif
 
 static struct i2c_board_info __initdata bfin_i2c_board_info0[] = {
+#if defined(CONFIG_SND_SOC_SSM2602) || defined(CONFIG_SND_SOC_SSM2602_MODULE)
+        {
+                I2C_BOARD_INFO("ssm2602", 0x1b),
+        },
+#endif
 };
 
 #if !defined(CONFIG_BF542)      /* The BF542 only has 1 TWI */
@@ -1385,6 +1392,8 @@ static struct platform_device bfin_dpmc = {
 static const u16 bfin_snd_pin[][7] = {
         SPORT_REQ(0),
         SPORT_REQ(1),
+        SPORT_REQ(2),
+        SPORT_REQ(3),
 };
 
 static struct bfin_snd_platform_data bfin_snd_data[] = {
@@ -1394,6 +1403,12 @@ static struct bfin_snd_platform_data bfin_snd_data[] = {
         {
                 .pin_req = &bfin_snd_pin[1][0],
         },
+        {
+                .pin_req = &bfin_snd_pin[2][0],
+        },
+        {
+                .pin_req = &bfin_snd_pin[3][0],
+        },
 };
 
 #define BFIN_SND_RES(x) \
@@ -1423,10 +1438,28 @@ static struct bfin_snd_platform_data bfin_snd_data[] = {
 static struct resource bfin_snd_resources[][4] = {
         BFIN_SND_RES(0),
         BFIN_SND_RES(1),
+        BFIN_SND_RES(2),
+        BFIN_SND_RES(3),
 };
+#endif
 
-static struct platform_device bfin_pcm = {
-        .name = "bfin-pcm-audio",
+#if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE)
+static struct platform_device bfin_i2s_pcm = {
+        .name = "bfin-i2s-pcm-audio",
+        .id = -1,
+};
+#endif
+
+#if defined(CONFIG_SND_BF5XX_TDM) || defined(CONFIG_SND_BF5XX_TDM_MODULE)
+static struct platform_device bfin_tdm_pcm = {
+        .name = "bfin-tdm-pcm-audio",
+        .id = -1,
+};
+#endif
+
+#if defined(CONFIG_SND_BF5XX_AC97) || defined(CONFIG_SND_BF5XX_AC97_MODULE)
+static struct platform_device bfin_ac97_pcm = {
+        .name = "bfin-ac97-pcm-audio",
         .id = -1,
 };
 #endif
@@ -1599,10 +1632,14 @@ static struct platform_device *ezkit_devices[] __initdata = {
         &ezkit_flash_device,
 #endif
 
-#if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE) || \
-        defined(CONFIG_SND_BF5XX_TDM) || defined(CONFIG_SND_BF5XX_TDM_MODULE) || \
-        defined(CONFIG_SND_BF5XX_AC97) || defined(CONFIG_SND_BF5XX_AC97_MODULE)
-        &bfin_pcm,
+#if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE)
+        &bfin_i2s_pcm,
+#endif
+#if defined(CONFIG_SND_BF5XX_TDM) || defined(CONFIG_SND_BF5XX_TDM_MODULE)
+        &bfin_tdm_pcm,
+#endif
+#if defined(CONFIG_SND_BF5XX_AC97) || defined(CONFIG_SND_BF5XX_AC97_MODULE)
+        &bfin_ac97_pcm,
 #endif
 
 #if defined(CONFIG_SND_BF5XX_SOC_AD1980) || defined(CONFIG_SND_BF5XX_SOC_AD1980_MODULE)
diff --git a/arch/blackfin/mach-bf561/atomic.S b/arch/blackfin/mach-bf561/atomic.S
index 52d6f73fcce..2a08df8e8c4 100644
--- a/arch/blackfin/mach-bf561/atomic.S
+++ b/arch/blackfin/mach-bf561/atomic.S
@@ -72,6 +72,13 @@ ENTRY(_get_core_lock_noflush)
         SSYNC(r2);
         jump .Lretry_corelock_noflush
 .Ldone_corelock_noflush:
+        /*
+         * SMP kgdb runs into dead loop without NOP here, when one core
+         * single steps over get_core_lock_noflush and the other executes
+         * get_core_lock as a slave node.
+         */
+        nop;
+        CSYNC(r2);
         rts;
 ENDPROC(_get_core_lock_noflush)
 
diff --git a/arch/blackfin/mach-bf561/include/mach/defBF561.h b/arch/blackfin/mach-bf561/include/mach/defBF561.h
index 71e805ea74e..5f0ac5a77a3 100644
--- a/arch/blackfin/mach-bf561/include/mach/defBF561.h
+++ b/arch/blackfin/mach-bf561/include/mach/defBF561.h
@@ -479,61 +479,61 @@
 #define DMA1_11_PERIPHERAL_MAP 0xFFC01EEC       /* DMA1 Channel 11 Peripheral Map Register */
 
 /* Memory DMA1 Controller registers (0xFFC0 1E80-0xFFC0 1FFF) */
-#define MDMA_D2_CONFIG 0xFFC01F08       /*MemDMA1 Stream 0 Destination Configuration */
-#define MDMA_D2_NEXT_DESC_PTR 0xFFC01F00        /*MemDMA1 Stream 0 Destination Next Descriptor Ptr Reg */
-#define MDMA_D2_START_ADDR 0xFFC01F04   /*MemDMA1 Stream 0 Destination Start Address */
-#define MDMA_D2_X_COUNT 0xFFC01F10      /*MemDMA1 Stream 0 Destination Inner-Loop Count */
-#define MDMA_D2_Y_COUNT 0xFFC01F18      /*MemDMA1 Stream 0 Destination Outer-Loop Count */
-#define MDMA_D2_X_MODIFY 0xFFC01F14     /*MemDMA1 Stream 0 Dest Inner-Loop Address-Increment */
-#define MDMA_D2_Y_MODIFY 0xFFC01F1C     /*MemDMA1 Stream 0 Dest Outer-Loop Address-Increment */
-#define MDMA_D2_CURR_DESC_PTR 0xFFC01F20        /*MemDMA1 Stream 0 Dest Current Descriptor Ptr reg */
-#define MDMA_D2_CURR_ADDR 0xFFC01F24    /*MemDMA1 Stream 0 Destination Current Address */
-#define MDMA_D2_CURR_X_COUNT 0xFFC01F30 /*MemDMA1 Stream 0 Dest Current Inner-Loop Count */
-#define MDMA_D2_CURR_Y_COUNT 0xFFC01F38 /*MemDMA1 Stream 0 Dest Current Outer-Loop Count */
-#define MDMA_D2_IRQ_STATUS 0xFFC01F28   /*MemDMA1 Stream 0 Destination Interrupt/Status */
-#define MDMA_D2_PERIPHERAL_MAP 0xFFC01F2C       /*MemDMA1 Stream 0 Destination Peripheral Map */
-
-#define MDMA_S2_CONFIG 0xFFC01F48       /*MemDMA1 Stream 0 Source Configuration */
-#define MDMA_S2_NEXT_DESC_PTR 0xFFC01F40        /*MemDMA1 Stream 0 Source Next Descriptor Ptr Reg */
-#define MDMA_S2_START_ADDR 0xFFC01F44   /*MemDMA1 Stream 0 Source Start Address */
-#define MDMA_S2_X_COUNT 0xFFC01F50      /*MemDMA1 Stream 0 Source Inner-Loop Count */
-#define MDMA_S2_Y_COUNT 0xFFC01F58      /*MemDMA1 Stream 0 Source Outer-Loop Count */
-#define MDMA_S2_X_MODIFY 0xFFC01F54     /*MemDMA1 Stream 0 Source Inner-Loop Address-Increment */
-#define MDMA_S2_Y_MODIFY 0xFFC01F5C     /*MemDMA1 Stream 0 Source Outer-Loop Address-Increment */
-#define MDMA_S2_CURR_DESC_PTR 0xFFC01F60        /*MemDMA1 Stream 0 Source Current Descriptor Ptr reg */
-#define MDMA_S2_CURR_ADDR 0xFFC01F64    /*MemDMA1 Stream 0 Source Current Address */
-#define MDMA_S2_CURR_X_COUNT 0xFFC01F70 /*MemDMA1 Stream 0 Source Current Inner-Loop Count */
-#define MDMA_S2_CURR_Y_COUNT 0xFFC01F78 /*MemDMA1 Stream 0 Source Current Outer-Loop Count */
-#define MDMA_S2_IRQ_STATUS 0xFFC01F68   /*MemDMA1 Stream 0 Source Interrupt/Status */
-#define MDMA_S2_PERIPHERAL_MAP 0xFFC01F6C       /*MemDMA1 Stream 0 Source Peripheral Map */
-
-#define MDMA_D3_CONFIG 0xFFC01F88       /*MemDMA1 Stream 1 Destination Configuration */
-#define MDMA_D3_NEXT_DESC_PTR 0xFFC01F80        /*MemDMA1 Stream 1 Destination Next Descriptor Ptr Reg */
-#define MDMA_D3_START_ADDR 0xFFC01F84   /*MemDMA1 Stream 1 Destination Start Address */
-#define MDMA_D3_X_COUNT 0xFFC01F90      /*MemDMA1 Stream 1 Destination Inner-Loop Count */
-#define MDMA_D3_Y_COUNT 0xFFC01F98      /*MemDMA1 Stream 1 Destination Outer-Loop Count */
-#define MDMA_D3_X_MODIFY 0xFFC01F94     /*MemDMA1 Stream 1 Dest Inner-Loop Address-Increment */
-#define MDMA_D3_Y_MODIFY 0xFFC01F9C     /*MemDMA1 Stream 1 Dest Outer-Loop Address-Increment */
-#define MDMA_D3_CURR_DESC_PTR 0xFFC01FA0        /*MemDMA1 Stream 1 Dest Current Descriptor Ptr reg */
-#define MDMA_D3_CURR_ADDR 0xFFC01FA4    /*MemDMA1 Stream 1 Dest Current Address */
-#define MDMA_D3_CURR_X_COUNT 0xFFC01FB0 /*MemDMA1 Stream 1 Dest Current Inner-Loop Count */
-#define MDMA_D3_CURR_Y_COUNT 0xFFC01FB8 /*MemDMA1 Stream 1 Dest Current Outer-Loop Count */
-#define MDMA_D3_IRQ_STATUS 0xFFC01FA8   /*MemDMA1 Stream 1 Dest Interrupt/Status */
-#define MDMA_D3_PERIPHERAL_MAP 0xFFC01FAC       /*MemDMA1 Stream 1 Dest Peripheral Map */
-
-#define MDMA_S3_CONFIG 0xFFC01FC8       /*MemDMA1 Stream 1 Source Configuration */
-#define MDMA_S3_NEXT_DESC_PTR 0xFFC01FC0        /*MemDMA1 Stream 1 Source Next Descriptor Ptr Reg */
-#define MDMA_S3_START_ADDR 0xFFC01FC4   /*MemDMA1 Stream 1 Source Start Address */
-#define MDMA_S3_X_COUNT 0xFFC01FD0      /*MemDMA1 Stream 1 Source Inner-Loop Count */
-#define MDMA_S3_Y_COUNT 0xFFC01FD8      /*MemDMA1 Stream 1 Source Outer-Loop Count */
-#define MDMA_S3_X_MODIFY 0xFFC01FD4     /*MemDMA1 Stream 1 Source Inner-Loop Address-Increment */
-#define MDMA_S3_Y_MODIFY 0xFFC01FDC     /*MemDMA1 Stream 1 Source Outer-Loop Address-Increment */
-#define MDMA_S3_CURR_DESC_PTR 0xFFC01FE0        /*MemDMA1 Stream 1 Source Current Descriptor Ptr reg */
-#define MDMA_S3_CURR_ADDR 0xFFC01FE4    /*MemDMA1 Stream 1 Source Current Address */
-#define MDMA_S3_CURR_X_COUNT 0xFFC01FF0 /*MemDMA1 Stream 1 Source Current Inner-Loop Count */
-#define MDMA_S3_CURR_Y_COUNT 0xFFC01FF8 /*MemDMA1 Stream 1 Source Current Outer-Loop Count */
-#define MDMA_S3_IRQ_STATUS 0xFFC01FE8   /*MemDMA1 Stream 1 Source Interrupt/Status */
-#define MDMA_S3_PERIPHERAL_MAP 0xFFC01FEC       /*MemDMA1 Stream 1 Source Peripheral Map */
+#define MDMA_D0_CONFIG 0xFFC01F08       /*MemDMA1 Stream 0 Destination Configuration */
+#define MDMA_D0_NEXT_DESC_PTR 0xFFC01F00        /*MemDMA1 Stream 0 Destination Next Descriptor Ptr Reg */
+#define MDMA_D0_START_ADDR 0xFFC01F04   /*MemDMA1 Stream 0 Destination Start Address */
+#define MDMA_D0_X_COUNT 0xFFC01F10      /*MemDMA1 Stream 0 Destination Inner-Loop Count */
+#define MDMA_D0_Y_COUNT 0xFFC01F18      /*MemDMA1 Stream 0 Destination Outer-Loop Count */
+#define MDMA_D0_X_MODIFY 0xFFC01F14     /*MemDMA1 Stream 0 Dest Inner-Loop Address-Increment */
+#define MDMA_D0_Y_MODIFY 0xFFC01F1C     /*MemDMA1 Stream 0 Dest Outer-Loop Address-Increment */
+#define MDMA_D0_CURR_DESC_PTR 0xFFC01F20        /*MemDMA1 Stream 0 Dest Current Descriptor Ptr reg */
+#define MDMA_D0_CURR_ADDR 0xFFC01F24    /*MemDMA1 Stream 0 Destination Current Address */
+#define MDMA_D0_CURR_X_COUNT 0xFFC01F30 /*MemDMA1 Stream 0 Dest Current Inner-Loop Count */
+#define MDMA_D0_CURR_Y_COUNT 0xFFC01F38 /*MemDMA1 Stream 0 Dest Current Outer-Loop Count */
+#define MDMA_D0_IRQ_STATUS 0xFFC01F28   /*MemDMA1 Stream 0 Destination Interrupt/Status */
+#define MDMA_D0_PERIPHERAL_MAP 0xFFC01F2C       /*MemDMA1 Stream 0 Destination Peripheral Map */
+
+#define MDMA_S0_CONFIG 0xFFC01F48       /*MemDMA1 Stream 0 Source Configuration */
+#define MDMA_S0_NEXT_DESC_PTR 0xFFC01F40        /*MemDMA1 Stream 0 Source Next Descriptor Ptr Reg */
+#define MDMA_S0_START_ADDR 0xFFC01F44   /*MemDMA1 Stream 0 Source Start Address */
+#define MDMA_S0_X_COUNT 0xFFC01F50      /*MemDMA1 Stream 0 Source Inner-Loop Count */
+#define MDMA_S0_Y_COUNT 0xFFC01F58      /*MemDMA1 Stream 0 Source Outer-Loop Count */
+#define MDMA_S0_X_MODIFY 0xFFC01F54     /*MemDMA1 Stream 0 Source Inner-Loop Address-Increment */
+#define MDMA_S0_Y_MODIFY 0xFFC01F5C     /*MemDMA1 Stream 0 Source Outer-Loop Address-Increment */
+#define MDMA_S0_CURR_DESC_PTR 0xFFC01F60        /*MemDMA1 Stream 0 Source Current Descriptor Ptr reg */
+#define MDMA_S0_CURR_ADDR 0xFFC01F64    /*MemDMA1 Stream 0 Source Current Address */
+#define MDMA_S0_CURR_X_COUNT 0xFFC01F70 /*MemDMA1 Stream 0 Source Current Inner-Loop Count */
+#define MDMA_S0_CURR_Y_COUNT 0xFFC01F78 /*MemDMA1 Stream 0 Source Current Outer-Loop Count */
+#define MDMA_S0_IRQ_STATUS 0xFFC01F68   /*MemDMA1 Stream 0 Source Interrupt/Status */
+#define MDMA_S0_PERIPHERAL_MAP 0xFFC01F6C       /*MemDMA1 Stream 0 Source Peripheral Map */
+
+#define MDMA_D1_CONFIG 0xFFC01F88       /*MemDMA1 Stream 1 Destination Configuration */
+#define MDMA_D1_NEXT_DESC_PTR 0xFFC01F80        /*MemDMA1 Stream 1 Destination Next Descriptor Ptr Reg */
+#define MDMA_D1_START_ADDR 0xFFC01F84   /*MemDMA1 Stream 1 Destination Start Address */
+#define MDMA_D1_X_COUNT 0xFFC01F90      /*MemDMA1 Stream 1 Destination Inner-Loop Count */
+#define MDMA_D1_Y_COUNT 0xFFC01F98      /*MemDMA1 Stream 1 Destination Outer-Loop Count */
+#define MDMA_D1_X_MODIFY 0xFFC01F94     /*MemDMA1 Stream 1 Dest Inner-Loop Address-Increment */
+#define MDMA_D1_Y_MODIFY 0xFFC01F9C     /*MemDMA1 Stream 1 Dest Outer-Loop Address-Increment */
+#define MDMA_D1_CURR_DESC_PTR 0xFFC01FA0        /*MemDMA1 Stream 1 Dest Current Descriptor Ptr reg */
+#define MDMA_D1_CURR_ADDR 0xFFC01FA4    /*MemDMA1 Stream 1 Dest Current Address */
+#define MDMA_D1_CURR_X_COUNT 0xFFC01FB0 /*MemDMA1 Stream 1 Dest Current Inner-Loop Count */
+#define MDMA_D1_CURR_Y_COUNT 0xFFC01FB8 /*MemDMA1 Stream 1 Dest Current Outer-Loop Count */
+#define MDMA_D1_IRQ_STATUS 0xFFC01FA8   /*MemDMA1 Stream 1 Dest Interrupt/Status */
+#define MDMA_D1_PERIPHERAL_MAP 0xFFC01FAC       /*MemDMA1 Stream 1 Dest Peripheral Map */
+
+#define MDMA_S1_CONFIG 0xFFC01FC8       /*MemDMA1 Stream 1 Source Configuration */
+#define MDMA_S1_NEXT_DESC_PTR 0xFFC01FC0        /*MemDMA1 Stream 1 Source Next Descriptor Ptr Reg */
+#define MDMA_S1_START_ADDR 0xFFC01FC4   /*MemDMA1 Stream 1 Source Start Address */
+#define MDMA_S1_X_COUNT 0xFFC01FD0      /*MemDMA1 Stream 1 Source Inner-Loop Count */
+#define MDMA_S1_Y_COUNT 0xFFC01FD8      /*MemDMA1 Stream 1 Source Outer-Loop Count */
+#define MDMA_S1_X_MODIFY 0xFFC01FD4     /*MemDMA1 Stream 1 Source Inner-Loop Address-Increment */
+#define MDMA_S1_Y_MODIFY 0xFFC01FDC     /*MemDMA1 Stream 1 Source Outer-Loop Address-Increment */
+#define MDMA_S1_CURR_DESC_PTR 0xFFC01FE0        /*MemDMA1 Stream 1 Source Current Descriptor Ptr reg */
+#define MDMA_S1_CURR_ADDR 0xFFC01FE4    /*MemDMA1 Stream 1 Source Current Address */
+#define MDMA_S1_CURR_X_COUNT 0xFFC01FF0 /*MemDMA1 Stream 1 Source Current Inner-Loop Count */
+#define MDMA_S1_CURR_Y_COUNT 0xFFC01FF8 /*MemDMA1 Stream 1 Source Current Outer-Loop Count */
+#define MDMA_S1_IRQ_STATUS 0xFFC01FE8   /*MemDMA1 Stream 1 Source Interrupt/Status */
+#define MDMA_S1_PERIPHERAL_MAP 0xFFC01FEC       /*MemDMA1 Stream 1 Source Peripheral Map */
 
 /* DMA2 Controller registers (0xFFC0 0C00-0xFFC0 0DFF) */
 #define DMA2_0_CONFIG 0xFFC00C08        /* DMA2 Channel 0 Configuration register */
@@ -705,61 +705,61 @@
 #define DMA2_11_PERIPHERAL_MAP 0xFFC00EEC       /* DMA2 Channel 11 Peripheral Map Register */
 
 /* Memory DMA2 Controller registers (0xFFC0 0E80-0xFFC0 0FFF) */
-#define MDMA_D0_CONFIG 0xFFC00F08       /*MemDMA2 Stream 0 Destination Configuration register */
-#define MDMA_D0_NEXT_DESC_PTR 0xFFC00F00        /*MemDMA2 Stream 0 Destination Next Descriptor Ptr Reg */
-#define MDMA_D0_START_ADDR 0xFFC00F04   /*MemDMA2 Stream 0 Destination Start Address */
-#define MDMA_D0_X_COUNT 0xFFC00F10      /*MemDMA2 Stream 0 Dest Inner-Loop Count register */
-#define MDMA_D0_Y_COUNT 0xFFC00F18      /*MemDMA2 Stream 0 Dest Outer-Loop Count register */
-#define MDMA_D0_X_MODIFY 0xFFC00F14     /*MemDMA2 Stream 0 Dest Inner-Loop Address-Increment */
-#define MDMA_D0_Y_MODIFY 0xFFC00F1C     /*MemDMA2 Stream 0 Dest Outer-Loop Address-Increment */
-#define MDMA_D0_CURR_DESC_PTR 0xFFC00F20        /*MemDMA2 Stream 0 Dest Current Descriptor Ptr reg */
-#define MDMA_D0_CURR_ADDR 0xFFC00F24    /*MemDMA2 Stream 0 Destination Current Address */
-#define MDMA_D0_CURR_X_COUNT 0xFFC00F30 /*MemDMA2 Stream 0 Dest Current Inner-Loop Count reg */
-#define MDMA_D0_CURR_Y_COUNT 0xFFC00F38 /*MemDMA2 Stream 0 Dest Current Outer-Loop Count reg */
-#define MDMA_D0_IRQ_STATUS 0xFFC00F28   /*MemDMA2 Stream 0 Dest Interrupt/Status Register */
-#define MDMA_D0_PERIPHERAL_MAP 0xFFC00F2C       /*MemDMA2 Stream 0 Destination Peripheral Map register */
-
-#define MDMA_S0_CONFIG 0xFFC00F48       /*MemDMA2 Stream 0 Source Configuration register */
-#define MDMA_S0_NEXT_DESC_PTR 0xFFC00F40        /*MemDMA2 Stream 0 Source Next Descriptor Ptr Reg */
-#define MDMA_S0_START_ADDR 0xFFC00F44   /*MemDMA2 Stream 0 Source Start Address */
-#define MDMA_S0_X_COUNT 0xFFC00F50      /*MemDMA2 Stream 0 Source Inner-Loop Count register */
-#define MDMA_S0_Y_COUNT 0xFFC00F58      /*MemDMA2 Stream 0 Source Outer-Loop Count register */
-#define MDMA_S0_X_MODIFY 0xFFC00F54     /*MemDMA2 Stream 0 Src Inner-Loop Addr-Increment reg */
-#define MDMA_S0_Y_MODIFY 0xFFC00F5C     /*MemDMA2 Stream 0 Src Outer-Loop Addr-Increment reg */
-#define MDMA_S0_CURR_DESC_PTR 0xFFC00F60        /*MemDMA2 Stream 0 Source Current Descriptor Ptr reg */
-#define MDMA_S0_CURR_ADDR 0xFFC00F64    /*MemDMA2 Stream 0 Source Current Address */
-#define MDMA_S0_CURR_X_COUNT 0xFFC00F70 /*MemDMA2 Stream 0 Src Current Inner-Loop Count reg */
-#define MDMA_S0_CURR_Y_COUNT 0xFFC00F78 /*MemDMA2 Stream 0 Src Current Outer-Loop Count reg */
-#define MDMA_S0_IRQ_STATUS 0xFFC00F68   /*MemDMA2 Stream 0 Source Interrupt/Status Register */
-#define MDMA_S0_PERIPHERAL_MAP 0xFFC00F6C       /*MemDMA2 Stream 0 Source Peripheral Map register */
-
-#define MDMA_D1_CONFIG 0xFFC00F88       /*MemDMA2 Stream 1 Destination Configuration register */
-#define MDMA_D1_NEXT_DESC_PTR 0xFFC00F80        /*MemDMA2 Stream 1 Destination Next Descriptor Ptr Reg */
-#define MDMA_D1_START_ADDR 0xFFC00F84   /*MemDMA2 Stream 1 Destination Start Address */
-#define MDMA_D1_X_COUNT 0xFFC00F90      /*MemDMA2 Stream 1 Dest Inner-Loop Count register */
-#define MDMA_D1_Y_COUNT 0xFFC00F98      /*MemDMA2 Stream 1 Dest Outer-Loop Count register */
-#define MDMA_D1_X_MODIFY 0xFFC00F94     /*MemDMA2 Stream 1 Dest Inner-Loop Address-Increment */
-#define MDMA_D1_Y_MODIFY 0xFFC00F9C     /*MemDMA2 Stream 1 Dest Outer-Loop Address-Increment */
-#define MDMA_D1_CURR_DESC_PTR 0xFFC00FA0        /*MemDMA2 Stream 1 Destination Current Descriptor Ptr */
-#define MDMA_D1_CURR_ADDR 0xFFC00FA4    /*MemDMA2 Stream 1 Destination Current Address reg */
-#define MDMA_D1_CURR_X_COUNT 0xFFC00FB0 /*MemDMA2 Stream 1 Dest Current Inner-Loop Count reg */
-#define MDMA_D1_CURR_Y_COUNT 0xFFC00FB8 /*MemDMA2 Stream 1 Dest Current Outer-Loop Count reg */
-#define MDMA_D1_IRQ_STATUS 0xFFC00FA8   /*MemDMA2 Stream 1 Destination Interrupt/Status Reg */
-#define MDMA_D1_PERIPHERAL_MAP 0xFFC00FAC       /*MemDMA2 Stream 1 Destination Peripheral Map register */
-
-#define MDMA_S1_CONFIG 0xFFC00FC8       /*MemDMA2 Stream 1 Source Configuration register */
-#define MDMA_S1_NEXT_DESC_PTR 0xFFC00FC0        /*MemDMA2 Stream 1 Source Next Descriptor Ptr Reg */
-#define MDMA_S1_START_ADDR 0xFFC00FC4   /*MemDMA2 Stream 1 Source Start Address */
-#define MDMA_S1_X_COUNT 0xFFC00FD0      /*MemDMA2 Stream 1 Source Inner-Loop Count register */
-#define MDMA_S1_Y_COUNT 0xFFC00FD8      /*MemDMA2 Stream 1 Source Outer-Loop Count register */
-#define MDMA_S1_X_MODIFY 0xFFC00FD4     /*MemDMA2 Stream 1 Src Inner-Loop Address-Increment */
-#define MDMA_S1_Y_MODIFY 0xFFC00FDC     /*MemDMA2 Stream 1 Source Outer-Loop Address-Increment */
-#define MDMA_S1_CURR_DESC_PTR 0xFFC00FE0        /*MemDMA2 Stream 1 Source Current Descriptor Ptr reg */
-#define MDMA_S1_CURR_ADDR 0xFFC00FE4    /*MemDMA2 Stream 1 Source Current Address */
-#define MDMA_S1_CURR_X_COUNT 0xFFC00FF0 /*MemDMA2 Stream 1 Source Current Inner-Loop Count */
-#define MDMA_S1_CURR_Y_COUNT 0xFFC00FF8 /*MemDMA2 Stream 1 Source Current Outer-Loop Count */
-#define MDMA_S1_IRQ_STATUS 0xFFC00FE8   /*MemDMA2 Stream 1 Source Interrupt/Status Register */
-#define MDMA_S1_PERIPHERAL_MAP 0xFFC00FEC       /*MemDMA2 Stream 1 Source Peripheral Map register */
+#define MDMA_D2_CONFIG 0xFFC00F08       /*MemDMA2 Stream 0 Destination Configuration register */
+#define MDMA_D2_NEXT_DESC_PTR 0xFFC00F00        /*MemDMA2 Stream 0 Destination Next Descriptor Ptr Reg */
+#define MDMA_D2_START_ADDR 0xFFC00F04   /*MemDMA2 Stream 0 Destination Start Address */
+#define MDMA_D2_X_COUNT 0xFFC00F10      /*MemDMA2 Stream 0 Dest Inner-Loop Count register */
+#define MDMA_D2_Y_COUNT 0xFFC00F18      /*MemDMA2 Stream 0 Dest Outer-Loop Count register */
+#define MDMA_D2_X_MODIFY 0xFFC00F14     /*MemDMA2 Stream 0 Dest Inner-Loop Address-Increment */
+#define MDMA_D2_Y_MODIFY 0xFFC00F1C     /*MemDMA2 Stream 0 Dest Outer-Loop Address-Increment */
+#define MDMA_D2_CURR_DESC_PTR 0xFFC00F20        /*MemDMA2 Stream 0 Dest Current Descriptor Ptr reg */
+#define MDMA_D2_CURR_ADDR 0xFFC00F24    /*MemDMA2 Stream 0 Destination Current Address */
+#define MDMA_D2_CURR_X_COUNT 0xFFC00F30 /*MemDMA2 Stream 0 Dest Current Inner-Loop Count reg */
+#define MDMA_D2_CURR_Y_COUNT 0xFFC00F38 /*MemDMA2 Stream 0 Dest Current Outer-Loop Count reg */
+#define MDMA_D2_IRQ_STATUS 0xFFC00F28   /*MemDMA2 Stream 0 Dest Interrupt/Status Register */
+#define MDMA_D2_PERIPHERAL_MAP 0xFFC00F2C       /*MemDMA2 Stream 0 Destination Peripheral Map register */
+
+#define MDMA_S2_CONFIG 0xFFC00F48       /*MemDMA2 Stream 0 Source Configuration register */
+#define MDMA_S2_NEXT_DESC_PTR 0xFFC00F40        /*MemDMA2 Stream 0 Source Next Descriptor Ptr Reg */
+#define MDMA_S2_START_ADDR 0xFFC00F44   /*MemDMA2 Stream 0 Source Start Address */
+#define MDMA_S2_X_COUNT 0xFFC00F50      /*MemDMA2 Stream 0 Source Inner-Loop Count register */
+#define MDMA_S2_Y_COUNT 0xFFC00F58      /*MemDMA2 Stream 0 Source Outer-Loop Count register */
+#define MDMA_S2_X_MODIFY 0xFFC00F54     /*MemDMA2 Stream 0 Src Inner-Loop Addr-Increment reg */
+#define MDMA_S2_Y_MODIFY 0xFFC00F5C     /*MemDMA2 Stream 0 Src Outer-Loop Addr-Increment reg */
+#define MDMA_S2_CURR_DESC_PTR 0xFFC00F60        /*MemDMA2 Stream 0 Source Current Descriptor Ptr reg */
+#define MDMA_S2_CURR_ADDR 0xFFC00F64    /*MemDMA2 Stream 0 Source Current Address */
+#define MDMA_S2_CURR_X_COUNT 0xFFC00F70 /*MemDMA2 Stream 0 Src Current Inner-Loop Count reg */
+#define MDMA_S2_CURR_Y_COUNT 0xFFC00F78 /*MemDMA2 Stream 0 Src Current Outer-Loop Count reg */
+#define MDMA_S2_IRQ_STATUS 0xFFC00F68   /*MemDMA2 Stream 0 Source Interrupt/Status Register */
+#define MDMA_S2_PERIPHERAL_MAP 0xFFC00F6C       /*MemDMA2 Stream 0 Source Peripheral Map register */
+
+#define MDMA_D3_CONFIG 0xFFC00F88       /*MemDMA2 Stream 1 Destination Configuration register */
+#define MDMA_D3_NEXT_DESC_PTR 0xFFC00F80        /*MemDMA2 Stream 1 Destination Next Descriptor Ptr Reg */
+#define MDMA_D3_START_ADDR 0xFFC00F84   /*MemDMA2 Stream 1 Destination Start Address */
+#define MDMA_D3_X_COUNT 0xFFC00F90      /*MemDMA2 Stream 1 Dest Inner-Loop Count register */
+#define MDMA_D3_Y_COUNT 0xFFC00F98      /*MemDMA2 Stream 1 Dest Outer-Loop Count register */
+#define MDMA_D3_X_MODIFY 0xFFC00F94     /*MemDMA2 Stream 1 Dest Inner-Loop Address-Increment */
+#define MDMA_D3_Y_MODIFY 0xFFC00F9C     /*MemDMA2 Stream 1 Dest Outer-Loop Address-Increment */
+#define MDMA_D3_CURR_DESC_PTR 0xFFC00FA0        /*MemDMA2 Stream 1 Destination Current Descriptor Ptr */
+#define MDMA_D3_CURR_ADDR 0xFFC00FA4    /*MemDMA2 Stream 1 Destination Current Address reg */
+#define MDMA_D3_CURR_X_COUNT 0xFFC00FB0 /*MemDMA2 Stream 1 Dest Current Inner-Loop Count reg */
+#define MDMA_D3_CURR_Y_COUNT 0xFFC00FB8 /*MemDMA2 Stream 1 Dest Current Outer-Loop Count reg */
+#define MDMA_D3_IRQ_STATUS 0xFFC00FA8   /*MemDMA2 Stream 1 Destination Interrupt/Status Reg */
+#define MDMA_D3_PERIPHERAL_MAP 0xFFC00FAC       /*MemDMA2 Stream 1 Destination Peripheral Map register */
+
+#define MDMA_S3_CONFIG 0xFFC00FC8       /*MemDMA2 Stream 1 Source Configuration register */
+#define MDMA_S3_NEXT_DESC_PTR 0xFFC00FC0        /*MemDMA2 Stream 1 Source Next Descriptor Ptr Reg */
+#define MDMA_S3_START_ADDR 0xFFC00FC4   /*MemDMA2 Stream 1 Source Start Address */
+#define MDMA_S3_X_COUNT 0xFFC00FD0      /*MemDMA2 Stream 1 Source Inner-Loop Count register */
+#define MDMA_S3_Y_COUNT 0xFFC00FD8      /*MemDMA2 Stream 1 Source Outer-Loop Count register */
+#define MDMA_S3_X_MODIFY 0xFFC00FD4     /*MemDMA2 Stream 1 Src Inner-Loop Address-Increment */
+#define MDMA_S3_Y_MODIFY 0xFFC00FDC     /*MemDMA2 Stream 1 Source Outer-Loop Address-Increment */
+#define MDMA_S3_CURR_DESC_PTR 0xFFC00FE0        /*MemDMA2 Stream 1 Source Current Descriptor Ptr reg */
+#define MDMA_S3_CURR_ADDR 0xFFC00FE4    /*MemDMA2 Stream 1 Source Current Address */
+#define MDMA_S3_CURR_X_COUNT 0xFFC00FF0 /*MemDMA2 Stream 1 Source Current Inner-Loop Count */
+#define MDMA_S3_CURR_Y_COUNT 0xFFC00FF8 /*MemDMA2 Stream 1 Source Current Outer-Loop Count */
+#define MDMA_S3_IRQ_STATUS 0xFFC00FE8   /*MemDMA2 Stream 1 Source Interrupt/Status Register */
+#define MDMA_S3_PERIPHERAL_MAP 0xFFC00FEC       /*MemDMA2 Stream 1 Source Peripheral Map register */
 
 /* Internal Memory DMA Registers (0xFFC0_1800 - 0xFFC0_19FF) */
 #define IMDMA_D0_CONFIG 0xFFC01808      /*IMDMA Stream 0 Destination Configuration */
@@ -879,6 +879,13 @@
 #define DLENGTH              0x00003800 /* PPI Data Length  */
 #define DLEN_8               0x0        /* PPI Data Length mask for DLEN=8 */
 #define DLEN(x) (((x-9) & 0x07) << 11)  /* PPI Data Length (only works for x=10-->x=16) */
+#define DLEN_10              0x00000800 /* Data Length = 10 Bits */
+#define DLEN_11              0x00001000 /* Data Length = 11 Bits */
+#define DLEN_12              0x00001800 /* Data Length = 12 Bits */
+#define DLEN_13              0x00002000 /* Data Length = 13 Bits */
+#define DLEN_14              0x00002800 /* Data Length = 14 Bits */
+#define DLEN_15              0x00003000 /* Data Length = 15 Bits */
+#define DLEN_16              0x00003800 /* Data Length = 16 Bits */
 #define POL                  0x0000C000 /* PPI Signal Polarities       */
 #define POLC            0x4000          /* PPI Clock Polarity */
 #define POLS            0x8000          /* PPI Frame Sync Polarity */
diff --git a/arch/blackfin/mach-common/entry.S b/arch/blackfin/mach-common/entry.S
index e4137297b79..4698a980052 100644
--- a/arch/blackfin/mach-common/entry.S
+++ b/arch/blackfin/mach-common/entry.S
@@ -1244,7 +1244,7 @@ ENTRY(_software_trace_buff)
         .endr
 #endif /* CONFIG_DEBUG_BFIN_HWTRACE_EXPAND */
 
-#if CONFIG_EARLY_PRINTK
+#ifdef CONFIG_EARLY_PRINTK
 __INIT
 ENTRY(_early_trap)
         SAVE_ALL_SYS
@@ -1755,6 +1755,8 @@ ENTRY(_sys_call_table)
         .long _sys_syncfs
         .long _sys_setns
         .long _sys_sendmmsg             /* 380 */
+        .long _sys_process_vm_readv
+        .long _sys_process_vm_writev
 
         .rept NR_syscalls-(.-_sys_call_table)/4
         .long _sys_ni_syscall
diff --git a/arch/c6x/include/asm/pgtable.h b/arch/c6x/include/asm/pgtable.h
index 68c8af4f1f9..38a4312eb2c 100644
--- a/arch/c6x/include/asm/pgtable.h
+++ b/arch/c6x/include/asm/pgtable.h
@@ -73,9 +73,6 @@ extern unsigned long empty_zero_page;
 #define pgtable_cache_init()   do { } while (0)
 #define io_remap_pfn_range      remap_pfn_range
 
-#define io_remap_page_range(vma, vaddr, paddr, size, prot)              \
-                remap_pfn_range(vma, vaddr, (paddr) >> PAGE_SHIFT, size, prot)
-
 #include <asm-generic/pgtable.h>
 
 #endif /* _ASM_C6X_PGTABLE_H */
diff --git a/arch/hexagon/kernel/signal.c b/arch/hexagon/kernel/signal.c
index b45be318119..ecbab345760 100644
--- a/arch/hexagon/kernel/signal.c
+++ b/arch/hexagon/kernel/signal.c
@@ -192,12 +192,7 @@ static int handle_signal(int sig, siginfo_t *info, struct k_sigaction *ka,
         if (rc)
                 return rc;
 
-        spin_lock_irq(&current->sighand->siglock);
-        sigorsets(&current->blocked, &current->blocked, &ka->sa.sa_mask);
-        if (!(ka->sa.sa_flags & SA_NODEFER))
-                sigaddset(&current->blocked, sig);
-        recalc_sigpending();
-        spin_unlock_irq(&current->sighand->siglock);
+        block_sigmask(ka, sig);
 
         return 0;
 }
@@ -305,10 +300,7 @@ asmlinkage int sys_rt_sigreturn(void)
                 goto badframe;
 
         sigdelsetmask(&blocked, ~_BLOCKABLE);
-        spin_lock_irq(&current->sighand->siglock);
-        current->blocked = blocked;
-        recalc_sigpending();
-        spin_unlock_irq(&current->sighand->siglock);
+        set_current_blocked(&blocked);
 
         if (restore_sigcontext(regs, &frame->uc.uc_mcontext))
                 goto badframe;
diff --git a/arch/hexagon/kernel/vdso.c b/arch/hexagon/kernel/vdso.c
index 16277c33308..f212a453b52 100644
--- a/arch/hexagon/kernel/vdso.c
+++ b/arch/hexagon/kernel/vdso.c
@@ -78,8 +78,7 @@ int arch_setup_additional_pages(struct linux_binprm *bprm, int uses_interp)
         /* MAYWRITE to allow gdb to COW and set breakpoints. */
         ret = install_special_mapping(mm, vdso_base, PAGE_SIZE,
                                       VM_READ|VM_EXEC|
-                                      VM_MAYREAD|VM_MAYWRITE|VM_MAYEXEC|
-                                      VM_ALWAYSDUMP,
+                                      VM_MAYREAD|VM_MAYWRITE|VM_MAYEXEC,
                                       &vdso_page);
 
         if (ret)
diff --git a/arch/ia64/include/asm/pci.h b/arch/ia64/include/asm/pci.h
index 279b38ae74a..b22e5f5fa59 100644
--- a/arch/ia64/include/asm/pci.h
+++ b/arch/ia64/include/asm/pci.h
@@ -108,12 +108,6 @@ static inline int pci_proc_domain(struct pci_bus *bus)
         return (pci_domain_nr(bus) != 0);
 }
 
-extern void pcibios_resource_to_bus(struct pci_dev *dev,
-                struct pci_bus_region *region, struct resource *res);
-
-extern void pcibios_bus_to_resource(struct pci_dev *dev,
-                struct resource *res, struct pci_bus_region *region);
-
 static inline struct resource *
 pcibios_select_root(struct pci_dev *pdev, struct resource *res)
 {
diff --git a/arch/ia64/include/asm/xen/interface.h b/arch/ia64/include/asm/xen/interface.h
index fbb519828aa..09d5f7fd9db 100644
--- a/arch/ia64/include/asm/xen/interface.h
+++ b/arch/ia64/include/asm/xen/interface.h
@@ -77,6 +77,7 @@ DEFINE_GUEST_HANDLE(int);
 DEFINE_GUEST_HANDLE(long);
 DEFINE_GUEST_HANDLE(void);
 DEFINE_GUEST_HANDLE(uint64_t);
+DEFINE_GUEST_HANDLE(uint32_t);
 
 typedef unsigned long xen_pfn_t;
 DEFINE_GUEST_HANDLE(xen_pfn_t);
diff --git a/arch/ia64/kernel/acpi.c b/arch/ia64/kernel/acpi.c
index 5207035dc06..2d801bfe16a 100644
--- a/arch/ia64/kernel/acpi.c
+++ b/arch/ia64/kernel/acpi.c
@@ -349,11 +349,11 @@ acpi_parse_int_src_ovr(struct acpi_subtable_header * header,
 
         iosapic_override_isa_irq(p->source_irq, p->global_irq,
                                  ((p->inti_flags & ACPI_MADT_POLARITY_MASK) ==
-                                  ACPI_MADT_POLARITY_ACTIVE_HIGH) ?
-                                 IOSAPIC_POL_HIGH : IOSAPIC_POL_LOW,
+                                  ACPI_MADT_POLARITY_ACTIVE_LOW) ?
+                                 IOSAPIC_POL_LOW : IOSAPIC_POL_HIGH,
                                  ((p->inti_flags & ACPI_MADT_TRIGGER_MASK) ==
-                                 ACPI_MADT_TRIGGER_EDGE) ?
-                                 IOSAPIC_EDGE : IOSAPIC_LEVEL);
+                                 ACPI_MADT_TRIGGER_LEVEL) ?
+                                 IOSAPIC_LEVEL : IOSAPIC_EDGE);
         return 0;
 }
 
diff --git a/arch/ia64/kernel/machine_kexec.c b/arch/ia64/kernel/machine_kexec.c
index 4eed3581499..070e8effa17 100644
--- a/arch/ia64/kernel/machine_kexec.c
+++ b/arch/ia64/kernel/machine_kexec.c
@@ -157,7 +157,7 @@ void arch_crash_save_vmcoreinfo(void)
 #endif
 #ifdef CONFIG_PGTABLE_3
         VMCOREINFO_CONFIG(PGTABLE_3);
-#elif  CONFIG_PGTABLE_4
+#elif defined(CONFIG_PGTABLE_4)
         VMCOREINFO_CONFIG(PGTABLE_4);
 #endif
 }
diff --git a/arch/ia64/kernel/mca.c b/arch/ia64/kernel/mca.c
index 84fb405eee8..8192009cb92 100644
--- a/arch/ia64/kernel/mca.c
+++ b/arch/ia64/kernel/mca.c
@@ -1447,6 +1447,8 @@ out:
         /* Get the CMC error record and log it */
         ia64_mca_log_sal_error_record(SAL_INFO_TYPE_CMC);
 
+        local_irq_disable();
+
         return IRQ_HANDLED;
 }
 
diff --git a/arch/ia64/pci/pci.c b/arch/ia64/pci/pci.c
index f82f5d4b65f..d1ce3200147 100644
--- a/arch/ia64/pci/pci.c
+++ b/arch/ia64/pci/pci.c
@@ -320,7 +320,8 @@ static __devinit acpi_status add_window(struct acpi_resource *res, void *data)
          * Ignore these tiny memory ranges */
         if (!((window->resource.flags & IORESOURCE_MEM) &&
               (window->resource.end - window->resource.start < 16)))
-                pci_add_resource(&info->resources, &window->resource);
+                pci_add_resource_offset(&info->resources, &window->resource,
+                                        window->offset);
 
         return AE_OK;
 }
@@ -395,54 +396,6 @@ out1:
         return NULL;
 }
 
-void pcibios_resource_to_bus(struct pci_dev *dev,
-                struct pci_bus_region *region, struct resource *res)
-{
-        struct pci_controller *controller = PCI_CONTROLLER(dev);
-        unsigned long offset = 0;
-        int i;
-
-        for (i = 0; i < controller->windows; i++) {
-                struct pci_window *window = &controller->window[i];
-                if (!(window->resource.flags & res->flags))
-                        continue;
-                if (window->resource.start > res->start)
-                        continue;
-                if (window->resource.end < res->end)
-                        continue;
-                offset = window->offset;
-                break;
-        }
-
-        region->start = res->start - offset;
-        region->end = res->end - offset;
-}
-EXPORT_SYMBOL(pcibios_resource_to_bus);
-
-void pcibios_bus_to_resource(struct pci_dev *dev,
-                struct resource *res, struct pci_bus_region *region)
-{
-        struct pci_controller *controller = PCI_CONTROLLER(dev);
-        unsigned long offset = 0;
-        int i;
-
-        for (i = 0; i < controller->windows; i++) {
-                struct pci_window *window = &controller->window[i];
-                if (!(window->resource.flags & res->flags))
-                        continue;
-                if (window->resource.start - window->offset > region->start)
-                        continue;
-                if (window->resource.end - window->offset < region->end)
-                        continue;
-                offset = window->offset;
-                break;
-        }
-
-        res->start = region->start + offset;
-        res->end = region->end + offset;
-}
-EXPORT_SYMBOL(pcibios_bus_to_resource);
-
 static int __devinit is_valid_resource(struct pci_dev *dev, int idx)
 {
         unsigned int i, type_mask = IORESOURCE_IO | IORESOURCE_MEM;
@@ -464,15 +417,11 @@ static int __devinit is_valid_resource(struct pci_dev *dev, int idx)
 static void __devinit
 pcibios_fixup_resources(struct pci_dev *dev, int start, int limit)
 {
-        struct pci_bus_region region;
         int i;
 
         for (i = start; i < limit; i++) {
                 if (!dev->resource[i].flags)
                         continue;
-                region.start = dev->resource[i].start;
-                region.end = dev->resource[i].end;
-                pcibios_bus_to_resource(dev, &dev->resource[i], &region);
                 if ((is_valid_resource(dev, i)))
                         pci_claim_resource(dev, i);
         }
diff --git a/arch/ia64/sn/kernel/huberror.c b/arch/ia64/sn/kernel/huberror.c
index 08b0d9bb62e..f925dec2da9 100644
--- a/arch/ia64/sn/kernel/huberror.c
+++ b/arch/ia64/sn/kernel/huberror.c
@@ -192,6 +192,7 @@ void hub_error_init(struct hubdev_info *hubdev_info)
                     hubdev_info);
                 return;
         }
+        irq_set_handler(SGI_II_ERROR, handle_level_irq);
         sn_set_err_irq_affinity(SGI_II_ERROR);
 }
 
@@ -213,6 +214,7 @@ void ice_error_init(struct hubdev_info *hubdev_info)
                        hubdev_info);
                 return;
         }
+        irq_set_handler(SGI_TIO_ERROR, handle_level_irq);
         sn_set_err_irq_affinity(SGI_TIO_ERROR);
 }
 
diff --git a/arch/ia64/sn/kernel/io_common.c b/arch/ia64/sn/kernel/io_common.c
index 4433dd019d3..fbb5f2f87ee 100644
--- a/arch/ia64/sn/kernel/io_common.c
+++ b/arch/ia64/sn/kernel/io_common.c
@@ -7,6 +7,7 @@
  */
 
 #include <linux/bootmem.h>
+#include <linux/export.h>
 #include <linux/slab.h>
 #include <asm/sn/types.h>
 #include <asm/sn/addrs.h>
diff --git a/arch/ia64/sn/kernel/io_init.c b/arch/ia64/sn/kernel/io_init.c
index 0a36f082eaf..238e2c511d9 100644
--- a/arch/ia64/sn/kernel/io_init.c
+++ b/arch/ia64/sn/kernel/io_init.c
@@ -297,7 +297,8 @@ sn_pci_controller_fixup(int segment, int busnum, struct pci_bus *bus)
         s64 status = 0;
         struct pci_controller *controller;
         struct pcibus_bussoft *prom_bussoft_ptr;
-
+        LIST_HEAD(resources);
+        int i;
 
         status = sal_get_pcibus_info((u64) segment, (u64) busnum,
                                      (u64) ia64_tpa(&prom_bussoft_ptr));
@@ -315,7 +316,15 @@ sn_pci_controller_fixup(int segment, int busnum, struct pci_bus *bus)
          */
         controller->platform_data = prom_bussoft_ptr;
 
-        bus = pci_scan_bus(busnum, &pci_root_ops, controller);
+        sn_legacy_pci_window_fixup(controller,
+                                   prom_bussoft_ptr->bs_legacy_io,
+                                   prom_bussoft_ptr->bs_legacy_mem);
+        for (i = 0; i < controller->windows; i++)
+                pci_add_resource_offset(&resources,
+                                        &controller->window[i].resource,
+                                        controller->window[i].offset);
+        bus = pci_scan_root_bus(NULL, busnum, &pci_root_ops, controller,
+                                &resources);
         if (bus == NULL)
                 goto error_return; /* error, or bus already scanned */
 
@@ -348,9 +357,6 @@ sn_bus_fixup(struct pci_bus *bus)
                         return;
                 }
                 sn_common_bus_fixup(bus, prom_bussoft_ptr);
-                sn_legacy_pci_window_fixup(PCI_CONTROLLER(bus),
-                                           prom_bussoft_ptr->bs_legacy_io,
-                                           prom_bussoft_ptr->bs_legacy_mem);
         }
         list_for_each_entry(pci_dev, &bus->devices, bus_list) {
                 sn_io_slot_fixup(pci_dev);
diff --git a/arch/ia64/sn/kernel/irq.c b/arch/ia64/sn/kernel/irq.c
index dfac09ab027..62cf4dde6a0 100644
--- a/arch/ia64/sn/kernel/irq.c
+++ b/arch/ia64/sn/kernel/irq.c
@@ -352,6 +352,8 @@ void sn_irq_fixup(struct pci_dev *pci_dev, struct sn_irq_info *sn_irq_info)
         spin_lock(&sn_irq_info_lock);
         list_add_rcu(&sn_irq_info->list, sn_irq_lh[sn_irq_info->irq_irq]);
         reserve_irq_vector(sn_irq_info->irq_irq);
+        if (sn_irq_info->irq_int_bit != -1)
+                irq_set_handler(sn_irq_info->irq_irq, handle_level_irq);
         spin_unlock(&sn_irq_info_lock);
 
         register_intr_pda(sn_irq_info);
diff --git a/arch/ia64/sn/kernel/sn2/sn_hwperf.c b/arch/ia64/sn/kernel/sn2/sn_hwperf.c
index 2de41d44266..4554f68b786 100644
--- a/arch/ia64/sn/kernel/sn2/sn_hwperf.c
+++ b/arch/ia64/sn/kernel/sn2/sn_hwperf.c
@@ -25,6 +25,7 @@
 
 #include <linux/fs.h>
 #include <linux/slab.h>
+#include <linux/export.h>
 #include <linux/vmalloc.h>
 #include <linux/seq_file.h>
 #include <linux/miscdevice.h>
diff --git a/arch/ia64/sn/kernel/tiocx.c b/arch/ia64/sn/kernel/tiocx.c
index c1bd1cfda32..2f406f509d4 100644
--- a/arch/ia64/sn/kernel/tiocx.c
+++ b/arch/ia64/sn/kernel/tiocx.c
@@ -191,6 +191,7 @@ cx_device_register(nasid_t nasid, int part_num, int mfg_num,
                    struct hubdev_info *hubdev, int bt)
 {
         struct cx_dev *cx_dev;
+        int r;
 
         cx_dev = kzalloc(sizeof(struct cx_dev), GFP_KERNEL);
         DBG("cx_dev= 0x%p\n", cx_dev);
@@ -207,7 +208,11 @@ cx_device_register(nasid_t nasid, int part_num, int mfg_num,
         cx_dev->dev.bus = &tiocx_bus_type;
         cx_dev->dev.release = tiocx_bus_release;
         dev_set_name(&cx_dev->dev, "%d", cx_dev->cx_id.nasid);
-        device_register(&cx_dev->dev);
+        r = device_register(&cx_dev->dev);
+        if (r) {
+                kfree(cx_dev);
+                return r;
+        }
         get_device(&cx_dev->dev);
 
         device_create_file(&cx_dev->dev, &dev_attr_cxdev_control);
diff --git a/arch/ia64/sn/pci/pcibr/pcibr_provider.c b/arch/ia64/sn/pci/pcibr/pcibr_provider.c
index 8886a0bc4a1..8dbbef4a4f4 100644
--- a/arch/ia64/sn/pci/pcibr/pcibr_provider.c
+++ b/arch/ia64/sn/pci/pcibr/pcibr_provider.c
@@ -146,6 +146,7 @@ pcibr_bus_fixup(struct pcibus_bussoft *prom_bussoft, struct pci_controller *cont
                 printk(KERN_WARNING
                        "pcibr cannot allocate interrupt for error handler\n");
         }
+        irq_set_handler(SGI_PCIASIC_ERROR, handle_level_irq);
         sn_set_err_irq_affinity(SGI_PCIASIC_ERROR);
 
         /* 
diff --git a/arch/ia64/sn/pci/tioca_provider.c b/arch/ia64/sn/pci/tioca_provider.c
index e77c477245f..a70b11fd57d 100644
--- a/arch/ia64/sn/pci/tioca_provider.c
+++ b/arch/ia64/sn/pci/tioca_provider.c
@@ -649,6 +649,7 @@ tioca_bus_fixup(struct pcibus_bussoft *prom_bussoft, struct pci_controller *cont
                        __func__, SGI_TIOCA_ERROR,
                        (int)tioca_common->ca_common.bs_persist_busnum);
 
+        irq_set_handler(SGI_TIOCA_ERROR, handle_level_irq);
         sn_set_err_irq_affinity(SGI_TIOCA_ERROR);
 
         /* Setup locality information */
diff --git a/arch/ia64/sn/pci/tioce_provider.c b/arch/ia64/sn/pci/tioce_provider.c
index 27faba035f3..46d3df4b03a 100644
--- a/arch/ia64/sn/pci/tioce_provider.c
+++ b/arch/ia64/sn/pci/tioce_provider.c
@@ -1037,6 +1037,7 @@ tioce_bus_fixup(struct pcibus_bussoft *prom_bussoft, struct pci_controller *cont
                        tioce_common->ce_pcibus.bs_persist_segment,
                        tioce_common->ce_pcibus.bs_persist_busnum);
 
+        irq_set_handler(SGI_PCIASIC_ERROR, handle_level_irq);
         sn_set_err_irq_affinity(SGI_PCIASIC_ERROR);
         return tioce_common;
 }
diff --git a/arch/m68k/Kconfig b/arch/m68k/Kconfig
index ae413d4a8bb..d318c606c88 100644
--- a/arch/m68k/Kconfig
+++ b/arch/m68k/Kconfig
@@ -7,6 +7,7 @@ config M68K
         select GENERIC_IRQ_SHOW
         select ARCH_HAVE_NMI_SAFE_CMPXCHG if RMW_INSNS
         select GENERIC_CPU_DEVICES
+        select FPU if MMU
 
 config RWSEM_GENERIC_SPINLOCK
         bool
@@ -24,9 +25,6 @@ config ARCH_HAS_ILOG2_U64
 config GENERIC_CLOCKEVENTS
         bool
 
-config GENERIC_CMOS_UPDATE
-        def_bool !MMU
-
 config GENERIC_GPIO
         bool
 
@@ -67,6 +65,9 @@ config CPU_HAS_NO_MULDIV64
 config CPU_HAS_ADDRESS_SPACES
         bool
 
+config FPU
+        bool
+
 config HZ
         int
         default 1000 if CLEOPATRA
diff --git a/arch/m68k/include/asm/m5206sim.h b/arch/m68k/include/asm/m5206sim.h
index 9015eadd5c0..69722366b08 100644
--- a/arch/m68k/include/asm/m5206sim.h
+++ b/arch/m68k/include/asm/m5206sim.h
@@ -100,11 +100,11 @@
 #define MCFDMA_BASE1            (MCF_MBAR + 0x240)      /* Base address DMA 1 */
 
 #if defined(CONFIG_NETtel)
-#define MCFUART_BASE1           0x180           /* Base address of UART1 */
-#define MCFUART_BASE2           0x140           /* Base address of UART2 */
+#define MCFUART_BASE0           (MCF_MBAR + 0x180)      /* Base address UART0 */
+#define MCFUART_BASE1           (MCF_MBAR + 0x140)      /* Base address UART1 */
 #else
-#define MCFUART_BASE1           0x140           /* Base address of UART1 */
-#define MCFUART_BASE2           0x180           /* Base address of UART2 */
+#define MCFUART_BASE0           (MCF_MBAR + 0x140)      /* Base address UART0 */
+#define MCFUART_BASE1           (MCF_MBAR + 0x180)      /* Base address UART1 */
 #endif
 
 /*
@@ -112,6 +112,8 @@
  */
 #define MCF_IRQ_TIMER           30              /* Timer0, Level 6 */
 #define MCF_IRQ_PROFILER        31              /* Timer1, Level 7 */
+#define MCF_IRQ_UART0           73              /* UART0 */
+#define MCF_IRQ_UART1           74              /* UART1 */
 
 /*
  *      Generic GPIO
diff --git a/arch/m68k/include/asm/m520xsim.h b/arch/m68k/include/asm/m520xsim.h
index eda62de7e60..17f2aab9cf9 100644
--- a/arch/m68k/include/asm/m520xsim.h
+++ b/arch/m68k/include/asm/m520xsim.h
@@ -48,8 +48,21 @@
 #define MCFINT_UART1        27          /* Interrupt number for UART1 */
 #define MCFINT_UART2        28          /* Interrupt number for UART2 */
 #define MCFINT_QSPI         31          /* Interrupt number for QSPI */
+#define MCFINT_FECRX0       36          /* Interrupt number for FEC RX */
+#define MCFINT_FECTX0       40          /* Interrupt number for FEC RX */
+#define MCFINT_FECENTC0     42          /* Interrupt number for FEC RX */
 #define MCFINT_PIT1         4           /* Interrupt number for PIT1 (PIT0 in processor) */
 
+#define MCF_IRQ_UART0       (MCFINT_VECBASE + MCFINT_UART0)
+#define MCF_IRQ_UART1       (MCFINT_VECBASE + MCFINT_UART1)
+#define MCF_IRQ_UART2       (MCFINT_VECBASE + MCFINT_UART2)
+
+#define MCF_IRQ_FECRX0      (MCFINT_VECBASE + MCFINT_FECRX0)
+#define MCF_IRQ_FECTX0      (MCFINT_VECBASE + MCFINT_FECTX0)
+#define MCF_IRQ_FECENTC0    (MCFINT_VECBASE + MCFINT_FECENTC0)
+
+#define MCF_IRQ_QSPI        (MCFINT_VECBASE + MCFINT_QSPI)
+
 /*
  *  SDRAM configuration registers.
  */
@@ -144,15 +157,25 @@
 /*
  *  UART module.
  */
-#define MCFUART_BASE1           0xFC060000      /* Base address of UART1 */
-#define MCFUART_BASE2           0xFC064000      /* Base address of UART2 */
-#define MCFUART_BASE3           0xFC068000      /* Base address of UART2 */
+#define MCFUART_BASE0           0xFC060000      /* Base address of UART0 */
+#define MCFUART_BASE1           0xFC064000      /* Base address of UART1 */
+#define MCFUART_BASE2           0xFC068000      /* Base address of UART2 */
 
 /*
  *  FEC module.
  */
-#define MCFFEC_BASE             0xFC030000      /* Base of FEC ethernet */
-#define MCFFEC_SIZE             0x800           /* Register set size */
+#define MCFFEC_BASE0            0xFC030000      /* Base of FEC ethernet */
+#define MCFFEC_SIZE0            0x800           /* Register set size */
+
+/*
+ *  QSPI module.
+ */
+#define MCFQSPI_BASE            0xFC05C000      /* Base of QSPI module */
+#define MCFQSPI_SIZE            0x40            /* Register set size */
+
+#define MCFQSPI_CS0             46
+#define MCFQSPI_CS1             47
+#define MCFQSPI_CS2             27
 
 /*
  *  Reset Control Unit.
diff --git a/arch/m68k/include/asm/m523xsim.h b/arch/m68k/include/asm/m523xsim.h
index 6235921eca4..075062d4eec 100644
--- a/arch/m68k/include/asm/m523xsim.h
+++ b/arch/m68k/include/asm/m523xsim.h
@@ -35,8 +35,23 @@
 
 #define MCFINT_VECBASE          64              /* Vector base number */
 #define MCFINT_UART0            13              /* Interrupt number for UART0 */
-#define MCFINT_PIT1             36              /* Interrupt number for PIT1 */
+#define MCFINT_UART1            14              /* Interrupt number for UART1 */
+#define MCFINT_UART2            15              /* Interrupt number for UART2 */
 #define MCFINT_QSPI             18              /* Interrupt number for QSPI */
+#define MCFINT_FECRX0           23              /* Interrupt number for FEC */
+#define MCFINT_FECTX0           27              /* Interrupt number for FEC */
+#define MCFINT_FECENTC0         29              /* Interrupt number for FEC */
+#define MCFINT_PIT1             36              /* Interrupt number for PIT1 */
+
+#define MCF_IRQ_UART0           (MCFINT_VECBASE + MCFINT_UART0)
+#define MCF_IRQ_UART1           (MCFINT_VECBASE + MCFINT_UART1)
+#define MCF_IRQ_UART2           (MCFINT_VECBASE + MCFINT_UART2)
+
+#define MCF_IRQ_FECRX0          (MCFINT_VECBASE + MCFINT_FECRX0)
+#define MCF_IRQ_FECTX0          (MCFINT_VECBASE + MCFINT_FECTX0)
+#define MCF_IRQ_FECENTC0        (MCFINT_VECBASE + MCFINT_FECENTC0)
+
+#define MCF_IRQ_QSPI            (MCFINT_VECBASE + MCFINT_QSPI)
 
 /*
  *      SDRAM configuration registers.
@@ -50,8 +65,8 @@
 /*
  *  Reset Control Unit (relative to IPSBAR).
  */
-#define MCF_RCR                 0x110000
-#define MCF_RSR                 0x110001
+#define MCF_RCR                 (MCF_IPSBAR + 0x110000)
+#define MCF_RSR                 (MCF_IPSBAR + 0x110001)
 
 #define MCF_RCR_SWRESET         0x80            /* Software reset bit */
 #define MCF_RCR_FRCSTOUT        0x40            /* Force external reset */
@@ -59,15 +74,26 @@
 /*
  *  UART module.
  */
-#define MCFUART_BASE1           (MCF_IPSBAR + 0x200)
-#define MCFUART_BASE2           (MCF_IPSBAR + 0x240)
-#define MCFUART_BASE3           (MCF_IPSBAR + 0x280)
+#define MCFUART_BASE0           (MCF_IPSBAR + 0x200)
+#define MCFUART_BASE1           (MCF_IPSBAR + 0x240)
+#define MCFUART_BASE2           (MCF_IPSBAR + 0x280)
 
 /*
  *  FEC ethernet module.
  */
-#define MCFFEC_BASE             (MCF_IPSBAR + 0x1000)
-#define MCFFEC_SIZE             0x800
+#define MCFFEC_BASE0            (MCF_IPSBAR + 0x1000)
+#define MCFFEC_SIZE0            0x800
+
+/*
+ *  QSPI module.
+ */
+#define MCFQSPI_BASE            (MCF_IPSBAR + 0x340)
+#define MCFQSPI_SIZE            0x40
+
+#define MCFQSPI_CS0             91
+#define MCFQSPI_CS1             92
+#define MCFQSPI_CS2             103
+#define MCFQSPI_CS3             99
 
 /*
  *  GPIO module.
diff --git a/arch/m68k/include/asm/m5249sim.h b/arch/m68k/include/asm/m5249sim.h
index 805714ca8d7..7f0c2c3660f 100644
--- a/arch/m68k/include/asm/m5249sim.h
+++ b/arch/m68k/include/asm/m5249sim.h
@@ -76,8 +76,19 @@
 /*
  *      UART module.
  */
-#define MCFUART_BASE1           0x1c0           /* Base address of UART1 */
-#define MCFUART_BASE2           0x200           /* Base address of UART2 */
+#define MCFUART_BASE0           (MCF_MBAR + 0x1c0)      /* Base address UART0 */
+#define MCFUART_BASE1           (MCF_MBAR + 0x200)      /* Base address UART1 */
+
+/*
+ *      QSPI module.
+ */
+#define MCFQSPI_BASE            (MCF_MBAR + 0x300)      /* Base address QSPI */
+#define MCFQSPI_SIZE            0x40                    /* Register set size */
+
+#define MCFQSPI_CS0             29
+#define MCFQSPI_CS1             24
+#define MCFQSPI_CS2             21
+#define MCFQSPI_CS3             22
 
 /*
  *      DMA unit base addresses.
@@ -108,6 +119,9 @@
 #define MCF_IRQ_TIMER           30              /* Timer0, Level 6 */
 #define MCF_IRQ_PROFILER        31              /* Timer1, Level 7 */
 
+#define MCF_IRQ_UART0           73              /* UART0 */
+#define MCF_IRQ_UART1           74              /* UART1 */
+
 /*
  *      General purpose IO registers (in MBAR2).
  */
diff --git a/arch/m68k/include/asm/m5272sim.h b/arch/m68k/include/asm/m5272sim.h
index 759c2b07a99..a58f1760d85 100644
--- a/arch/m68k/include/asm/m5272sim.h
+++ b/arch/m68k/include/asm/m5272sim.h
@@ -68,8 +68,8 @@
 #define MCFSIM_DCMR1            0x5c            /* DRAM 1 Mask reg (r/w) */
 #define MCFSIM_DCCR1            0x63            /* DRAM 1 Control reg (r/w) */
 
-#define MCFUART_BASE1           0x100           /* Base address of UART1 */
-#define MCFUART_BASE2           0x140           /* Base address of UART2 */
+#define MCFUART_BASE0           (MCF_MBAR + 0x100) /* Base address UART0 */
+#define MCFUART_BASE1           (MCF_MBAR + 0x140) /* Base address UART1 */
 
 #define MCFSIM_PACNT            (MCF_MBAR + 0x80) /* Port A Control (r/w) */
 #define MCFSIM_PADDR            (MCF_MBAR + 0x84) /* Port A Direction (r/w) */
@@ -88,6 +88,9 @@
 #define MCFTIMER_BASE3          (MCF_MBAR + 0x240) /* Base address TIMER4 */
 #define MCFTIMER_BASE4          (MCF_MBAR + 0x260) /* Base address TIMER3 */
 
+#define MCFFEC_BASE0            (MCF_MBAR + 0x840) /* Base FEC ethernet */
+#define MCFFEC_SIZE0            0x1d0
+
 /*
  *      Define system peripheral IRQ usage.
  */
@@ -101,8 +104,8 @@
 #define MCF_IRQ_TIMER2          70              /* Timer 2 */
 #define MCF_IRQ_TIMER3          71              /* Timer 3 */
 #define MCF_IRQ_TIMER4          72              /* Timer 4 */
-#define MCF_IRQ_UART1           73              /* UART 1 */
-#define MCF_IRQ_UART2           74              /* UART 2 */
+#define MCF_IRQ_UART0           73              /* UART 0 */
+#define MCF_IRQ_UART1           74              /* UART 1 */
 #define MCF_IRQ_PLIP            75              /* PLIC 2Khz Periodic */
 #define MCF_IRQ_PLIA            76              /* PLIC Asynchronous */
 #define MCF_IRQ_USB0            77              /* USB Endpoint 0 */
@@ -114,9 +117,9 @@
 #define MCF_IRQ_USB6            83              /* USB Endpoint 6 */
 #define MCF_IRQ_USB7            84              /* USB Endpoint 7 */
 #define MCF_IRQ_DMA             85              /* DMA Controller */
-#define MCF_IRQ_ERX             86              /* Ethernet Receiver */
-#define MCF_IRQ_ETX             87              /* Ethernet Transmitter */
-#define MCF_IRQ_ENTC            88              /* Ethernet Non-Time Critical */
+#define MCF_IRQ_FECRX0          86              /* Ethernet Receiver */
+#define MCF_IRQ_FECTX0          87              /* Ethernet Transmitter */
+#define MCF_IRQ_FECENTC0        88              /* Ethernet Non-Time Critical */
 #define MCF_IRQ_QSPI            89              /* Queued Serial Interface */
 #define MCF_IRQ_EINT5           90              /* External Interrupt 5 */
 #define MCF_IRQ_EINT6           91              /* External Interrupt 6 */
diff --git a/arch/m68k/include/asm/m527xsim.h b/arch/m68k/include/asm/m527xsim.h
index 758810ef91e..83db8106f50 100644
--- a/arch/m68k/include/asm/m527xsim.h
+++ b/arch/m68k/include/asm/m527xsim.h
@@ -38,8 +38,29 @@
 #define MCFINT_UART1            14              /* Interrupt number for UART1 */
 #define MCFINT_UART2            15              /* Interrupt number for UART2 */
 #define MCFINT_QSPI             18              /* Interrupt number for QSPI */
+#define MCFINT_FECRX0           23              /* Interrupt number for FEC0 */
+#define MCFINT_FECTX0           27              /* Interrupt number for FEC0 */
+#define MCFINT_FECENTC0         29              /* Interrupt number for FEC0 */
 #define MCFINT_PIT1             36              /* Interrupt number for PIT1 */
 
+#define MCFINT2_VECBASE         128             /* Vector base number 2 */
+#define MCFINT2_FECRX1          23              /* Interrupt number for FEC1 */
+#define MCFINT2_FECTX1          27              /* Interrupt number for FEC1 */
+#define MCFINT2_FECENTC1        29              /* Interrupt number for FEC1 */
+
+#define MCF_IRQ_UART0           (MCFINT_VECBASE + MCFINT_UART0)
+#define MCF_IRQ_UART1           (MCFINT_VECBASE + MCFINT_UART1)
+#define MCF_IRQ_UART2           (MCFINT_VECBASE + MCFINT_UART2)
+
+#define MCF_IRQ_FECRX0          (MCFINT_VECBASE + MCFINT_FECRX0)
+#define MCF_IRQ_FECTX0          (MCFINT_VECBASE + MCFINT_FECTX0)
+#define MCF_IRQ_FECENTC0        (MCFINT_VECBASE + MCFINT_FECENTC0)
+#define MCF_IRQ_FECRX1          (MCFINT2_VECBASE + MCFINT2_FECRX1)
+#define MCF_IRQ_FECTX1          (MCFINT2_VECBASE + MCFINT2_FECTX1)
+#define MCF_IRQ_FECENTC1        (MCFINT2_VECBASE + MCFINT2_FECENTC1)
+
+#define MCF_IRQ_QSPI            (MCFINT_VECBASE + MCFINT_QSPI)
+
 /*
  *      SDRAM configuration registers.
  */
@@ -72,9 +93,9 @@
 /*
  *      UART module.
  */
-#define MCFUART_BASE1           (MCF_IPSBAR + 0x200)
-#define MCFUART_BASE2           (MCF_IPSBAR + 0x240)
-#define MCFUART_BASE3           (MCF_IPSBAR + 0x280)
+#define MCFUART_BASE0           (MCF_IPSBAR + 0x200)
+#define MCFUART_BASE1           (MCF_IPSBAR + 0x240)
+#define MCFUART_BASE2           (MCF_IPSBAR + 0x280)
 
 /*
  *      FEC ethernet module.
@@ -84,6 +105,28 @@
 #define MCFFEC_BASE1            (MCF_IPSBAR + 0x1800)
 #define MCFFEC_SIZE1            0x800
 
+/*
+ *      QSPI module.
+ */
+#define MCFQSPI_BASE            (MCF_IPSBAR + 0x340)
+#define MCFQSPI_SIZE            0x40
+
+#ifdef CONFIG_M5271
+#define MCFQSPI_CS0             91
+#define MCFQSPI_CS1             92
+#define MCFQSPI_CS2             99
+#define MCFQSPI_CS3             103
+#endif
+#ifdef CONFIG_M5275
+#define MCFQSPI_CS0             59
+#define MCFQSPI_CS1             60
+#define MCFQSPI_CS2             61
+#define MCFQSPI_CS3             62
+#endif
+
+/*
+ *      GPIO module.
+ */
 #ifdef CONFIG_M5271
 #define MCFGPIO_PODR_ADDR       (MCF_IPSBAR + 0x100000)
 #define MCFGPIO_PODR_DATAH      (MCF_IPSBAR + 0x100001)
@@ -285,8 +328,8 @@
 /*
  *  Reset Control Unit (relative to IPSBAR).
  */
-#define MCF_RCR                 0x110000
-#define MCF_RSR                 0x110001
+#define MCF_RCR                 (MCF_IPSBAR + 0x110000)
+#define MCF_RSR                 (MCF_IPSBAR + 0x110001)
 
 #define MCF_RCR_SWRESET         0x80            /* Software reset bit */
 #define MCF_RCR_FRCSTOUT        0x40            /* Force external reset */
diff --git a/arch/m68k/include/asm/m528xsim.h b/arch/m68k/include/asm/m528xsim.h
index d798bd5df56..569476fba18 100644
--- a/arch/m68k/include/asm/m528xsim.h
+++ b/arch/m68k/include/asm/m528xsim.h
@@ -35,9 +35,24 @@
 
 #define MCFINT_VECBASE          64              /* Vector base number */
 #define MCFINT_UART0            13              /* Interrupt number for UART0 */
+#define MCFINT_UART1            14              /* Interrupt number for UART1 */
+#define MCFINT_UART2            15              /* Interrupt number for UART2 */
 #define MCFINT_QSPI             18              /* Interrupt number for QSPI */
+#define MCFINT_FECRX0           23              /* Interrupt number for FEC */
+#define MCFINT_FECTX0           27              /* Interrupt number for FEC */
+#define MCFINT_FECENTC0         29              /* Interrupt number for FEC */
 #define MCFINT_PIT1             55              /* Interrupt number for PIT1 */
 
+#define MCF_IRQ_UART0           (MCFINT_VECBASE + MCFINT_UART0)
+#define MCF_IRQ_UART1           (MCFINT_VECBASE + MCFINT_UART1)
+#define MCF_IRQ_UART2           (MCFINT_VECBASE + MCFINT_UART2)
+
+#define MCF_IRQ_FECRX0          (MCFINT_VECBASE + MCFINT_FECRX0)
+#define MCF_IRQ_FECTX0          (MCFINT_VECBASE + MCFINT_FECTX0)
+#define MCF_IRQ_FECENTC0        (MCFINT_VECBASE + MCFINT_FECENTC0)
+
+#define MCF_IRQ_QSPI            (MCFINT_VECBASE + MCFINT_QSPI)
+
 /*
  *      SDRAM configuration registers.
  */
@@ -58,15 +73,26 @@
 /*
  *      UART module.
  */
-#define MCFUART_BASE1           (MCF_IPSBAR + 0x00000200)
-#define MCFUART_BASE2           (MCF_IPSBAR + 0x00000240)
-#define MCFUART_BASE3           (MCF_IPSBAR + 0x00000280)
+#define MCFUART_BASE0           (MCF_IPSBAR + 0x00000200)
+#define MCFUART_BASE1           (MCF_IPSBAR + 0x00000240)
+#define MCFUART_BASE2           (MCF_IPSBAR + 0x00000280)
 
 /*
  *      FEC ethernet module.
  */
-#define MCFFEC_BASE             (MCF_IPSBAR + 0x00001000)
-#define MCFFEC_SIZE             0x800
+#define MCFFEC_BASE0            (MCF_IPSBAR + 0x00001000)
+#define MCFFEC_SIZE0            0x800
+
+/*
+ *      QSPI module.
+ */
+#define MCFQSPI_IOBASE          (MCF_IPSBAR + 0x340)
+#define MCFQSPI_SIZE            0x40
+
+#define MCFQSPI_CS0             147
+#define MCFQSPI_CS1             148
+#define MCFQSPI_CS2             149
+#define MCFQSPI_CS3             150
 
 /*
  *      GPIO registers
@@ -246,8 +272,8 @@
 /*
  *  Reset Control Unit (relative to IPSBAR).
  */
-#define MCF_RCR                 0x110000
-#define MCF_RSR                 0x110001
+#define MCF_RCR                 (MCF_IPSBAR + 0x110000)
+#define MCF_RSR                 (MCF_IPSBAR + 0x110001)
 
 #define MCF_RCR_SWRESET         0x80            /* Software reset bit */
 #define MCF_RCR_FRCSTOUT        0x40            /* Force external reset */
diff --git a/arch/m68k/include/asm/m5307sim.h b/arch/m68k/include/asm/m5307sim.h
index 8f8609fcc9b..3bc3adaa7ee 100644
--- a/arch/m68k/include/asm/m5307sim.h
+++ b/arch/m68k/include/asm/m5307sim.h
@@ -117,11 +117,11 @@
  *  UART module.
  */
 #if defined(CONFIG_NETtel) || defined(CONFIG_SECUREEDGEMP3)
-#define MCFUART_BASE1           0x200           /* Base address of UART1 */
-#define MCFUART_BASE2           0x1c0           /* Base address of UART2 */
+#define MCFUART_BASE0           (MCF_MBAR + 0x200)      /* Base address UART0 */
+#define MCFUART_BASE1           (MCF_MBAR + 0x1c0)      /* Base address UART1 */
 #else
-#define MCFUART_BASE1           0x1c0           /* Base address of UART1 */
-#define MCFUART_BASE2           0x200           /* Base address of UART2 */
+#define MCFUART_BASE0           (MCF_MBAR + 0x1c0)      /* Base address UART0 */
+#define MCFUART_BASE1           (MCF_MBAR + 0x200)      /* Base address UART1 */
 #endif
 
 /*
@@ -176,6 +176,8 @@
  */
 #define MCF_IRQ_TIMER           30              /* Timer0, Level 6 */
 #define MCF_IRQ_PROFILER        31              /* Timer1, Level 7 */
+#define MCF_IRQ_UART0           73              /* UART0 */
+#define MCF_IRQ_UART1           74              /* UART1 */
 
 /****************************************************************************/
 #endif  /* m5307sim_h */
diff --git a/arch/m68k/include/asm/m532xsim.h b/arch/m68k/include/asm/m532xsim.h
index ba4cc784f57..29b66e21413 100644
--- a/arch/m68k/include/asm/m532xsim.h
+++ b/arch/m68k/include/asm/m532xsim.h
@@ -24,6 +24,19 @@
 #define MCFINT_UART1        27          /* Interrupt number for UART1 */
 #define MCFINT_UART2        28          /* Interrupt number for UART2 */
 #define MCFINT_QSPI         31          /* Interrupt number for QSPI */
+#define MCFINT_FECRX0       36          /* Interrupt number for FEC */
+#define MCFINT_FECTX0       40          /* Interrupt number for FEC */
+#define MCFINT_FECENTC0     42          /* Interrupt number for FEC */
+
+#define MCF_IRQ_UART0       (MCFINT_VECBASE + MCFINT_UART0)
+#define MCF_IRQ_UART1       (MCFINT_VECBASE + MCFINT_UART1)
+#define MCF_IRQ_UART2       (MCFINT_VECBASE + MCFINT_UART2)
+
+#define MCF_IRQ_FECRX0      (MCFINT_VECBASE + MCFINT_FECRX0)
+#define MCF_IRQ_FECTX0      (MCFINT_VECBASE + MCFINT_FECTX0)
+#define MCF_IRQ_FECENTC0    (MCFINT_VECBASE + MCFINT_FECENTC0)
+
+#define MCF_IRQ_QSPI        (MCFINT_VECBASE + MCFINT_QSPI)
 
 #define MCF_WTM_WCR     MCF_REG16(0xFC098000)
 
@@ -82,9 +95,25 @@
 /*
  *  UART module.
  */
-#define MCFUART_BASE1           0xFC060000      /* Base address of UART1 */
-#define MCFUART_BASE2           0xFC064000      /* Base address of UART2 */
-#define MCFUART_BASE3           0xFC068000      /* Base address of UART3 */
+#define MCFUART_BASE0           0xFC060000      /* Base address of UART1 */
+#define MCFUART_BASE1           0xFC064000      /* Base address of UART2 */
+#define MCFUART_BASE2           0xFC068000      /* Base address of UART3 */
+
+/*
+ *  FEC module.
+ */
+#define MCFFEC_BASE0            0xFC030000      /* Base address of FEC0 */
+#define MCFFEC_SIZE0            0x800           /* Size of FEC0 region */
+
+/*
+ *  QSPI module.
+ */
+#define MCFQSPI_BASE            0xFC058000      /* Base address of QSPI */
+#define MCFQSPI_SIZE            0x40            /* Size of QSPI region */
+
+#define MCFQSPI_CS0             84
+#define MCFQSPI_CS1             85
+#define MCFQSPI_CS2             86
 
 /*
  *  Timer module.
diff --git a/arch/m68k/include/asm/m5407sim.h b/arch/m68k/include/asm/m5407sim.h
index 51e00b00b8a..79f58dd6a83 100644
--- a/arch/m68k/include/asm/m5407sim.h
+++ b/arch/m68k/include/asm/m5407sim.h
@@ -85,8 +85,8 @@
 #define MCFTIMER_BASE1          (MCF_MBAR + 0x140)      /* Base of TIMER1 */
 #define MCFTIMER_BASE2          (MCF_MBAR + 0x180)      /* Base of TIMER2 */
 
-#define MCFUART_BASE1           0x1c0           /* Base address of UART1 */
-#define MCFUART_BASE2           0x200           /* Base address of UART2 */
+#define MCFUART_BASE0           (MCF_MBAR + 0x1c0)      /* Base address UART0 */
+#define MCFUART_BASE1           (MCF_MBAR + 0x200)      /* Base address UART1 */
 
 #define MCFSIM_PADDR            (MCF_MBAR + 0x244)
 #define MCFSIM_PADAT            (MCF_MBAR + 0x248)
@@ -139,6 +139,8 @@
  */
 #define MCF_IRQ_TIMER           30              /* Timer0, Level 6 */
 #define MCF_IRQ_PROFILER        31              /* Timer1, Level 7 */
+#define MCF_IRQ_UART0           73              /* UART0 */
+#define MCF_IRQ_UART1           74              /* UART1 */
 
 /****************************************************************************/
 #endif  /* m5407sim_h */
diff --git a/arch/m68k/include/asm/m54xxsim.h b/arch/m68k/include/asm/m54xxsim.h
index 1ed8bfb0277..ae56b8848a9 100644
--- a/arch/m68k/include/asm/m54xxsim.h
+++ b/arch/m68k/include/asm/m54xxsim.h
@@ -31,16 +31,20 @@
 /*
  *      UART module.
  */
-#define MCFUART_BASE1           0x8600          /* Base address of UART1 */
-#define MCFUART_BASE2           0x8700          /* Base address of UART2 */
-#define MCFUART_BASE3           0x8800          /* Base address of UART3 */
-#define MCFUART_BASE4           0x8900          /* Base address of UART4 */
+#define MCFUART_BASE0           (MCF_MBAR + 0x8600)     /* Base address UART0 */
+#define MCFUART_BASE1           (MCF_MBAR + 0x8700)     /* Base address UART1 */
+#define MCFUART_BASE2           (MCF_MBAR + 0x8800)     /* Base address UART2 */
+#define MCFUART_BASE3           (MCF_MBAR + 0x8900)     /* Base address UART3 */
 
 /*
  *      Define system peripheral IRQ usage.
  */
-#define MCF_IRQ_TIMER           (64 + 54)       /* Slice Timer 0 */
-#define MCF_IRQ_PROFILER        (64 + 53)       /* Slice Timer 1 */
+#define MCF_IRQ_TIMER           (MCFINT_VECBASE + 54)   /* Slice Timer 0 */
+#define MCF_IRQ_PROFILER        (MCFINT_VECBASE + 53)   /* Slice Timer 1 */
+#define MCF_IRQ_UART0           (MCFINT_VECBASE + 35)
+#define MCF_IRQ_UART1           (MCFINT_VECBASE + 34)
+#define MCF_IRQ_UART2           (MCFINT_VECBASE + 33)
+#define MCF_IRQ_UART3           (MCFINT_VECBASE + 32)
 
 /*
  *      Generic GPIO support
diff --git a/arch/m68k/include/asm/machdep.h b/arch/m68k/include/asm/machdep.h
index 789f3b2de0e..825c1c81319 100644
--- a/arch/m68k/include/asm/machdep.h
+++ b/arch/m68k/include/asm/machdep.h
@@ -22,8 +22,6 @@ extern unsigned int (*mach_get_ss)(void);
 extern int (*mach_get_rtc_pll)(struct rtc_pll_info *);
 extern int (*mach_set_rtc_pll)(struct rtc_pll_info *);
 extern int (*mach_set_clock_mmss)(unsigned long);
-extern void (*mach_gettod)(int *year, int *mon, int *day, int *hour,
-                            int *min, int *sec);
 extern void (*mach_reset)( void );
 extern void (*mach_halt)( void );
 extern void (*mach_power_off)( void );
@@ -35,9 +33,8 @@ extern void (*mach_l2_flush) (int);
 extern void (*mach_beep) (unsigned int, unsigned int);
 
 /* Hardware clock functions */
-extern void hw_timer_init(void);
+extern void hw_timer_init(irq_handler_t handler);
 extern unsigned long hw_timer_offset(void);
-extern irqreturn_t arch_timer_interrupt(int irq, void *dummy);
 
 extern void config_BSP(char *command, int len);
 
diff --git a/arch/m68k/include/asm/mcfqspi.h b/arch/m68k/include/asm/mcfqspi.h
index 7fe631972f1..7b51416ccae 100644
--- a/arch/m68k/include/asm/mcfqspi.h
+++ b/arch/m68k/include/asm/mcfqspi.h
@@ -21,17 +21,6 @@
 #ifndef mcfqspi_h
 #define mcfqspi_h
 
-#if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x)
-#define MCFQSPI_IOBASE          (MCF_IPSBAR + 0x340)
-#elif defined(CONFIG_M5249)
-#define MCFQSPI_IOBASE         (MCF_MBAR + 0x300)
-#elif defined(CONFIG_M520x)
-#define MCFQSPI_IOBASE         0xFC05C000
-#elif defined(CONFIG_M532x)
-#define MCFQSPI_IOBASE         0xFC058000
-#endif
-#define MCFQSPI_IOSIZE          0x40
-
 /**
  * struct mcfqspi_cs_control - chip select control for the coldfire qspi driver
  * @setup: setup the control; allocate gpio's, etc. May be NULL.
diff --git a/arch/m68k/include/asm/mcfuart.h b/arch/m68k/include/asm/mcfuart.h
index 2abedff0a69..2d3bc774b3c 100644
--- a/arch/m68k/include/asm/mcfuart.h
+++ b/arch/m68k/include/asm/mcfuart.h
@@ -41,7 +41,10 @@ struct mcf_platform_uart {
 #define MCFUART_UTF             0x28            /* Transmitter FIFO (r/w) */
 #define MCFUART_URF             0x2c            /* Receiver FIFO (r/w) */
 #define MCFUART_UFPD            0x30            /* Frac Prec. Divider (r/w) */
-#else
+#endif
+#if defined(CONFIG_M5206) || defined(CONFIG_M5206e) || \
+        defined(CONFIG_M5249) || defined(CONFIG_M5307) || \
+        defined(CONFIG_M5407)
 #define MCFUART_UIVR            0x30            /* Interrupt Vector (r/w) */
 #endif
 #define MCFUART_UIPR            0x34            /* Input Port (r) */
diff --git a/arch/m68k/include/asm/system.h b/arch/m68k/include/asm/system.h
index 47b01f4726b..8dc68178716 100644
--- a/arch/m68k/include/asm/system.h
+++ b/arch/m68k/include/asm/system.h
@@ -3,6 +3,7 @@
 
 #include <linux/linkage.h>
 #include <linux/kernel.h>
+#include <linux/bug.h>
 #include <linux/irqflags.h>
 #include <asm/segment.h>
 #include <asm/entry.h>
diff --git a/arch/m68k/kernel/process.c b/arch/m68k/kernel/process.c
index 6cf4bd6e34f..c54ef927e48 100644
--- a/arch/m68k/kernel/process.c
+++ b/arch/m68k/kernel/process.c
@@ -1,5 +1,378 @@
+/*
+ *  linux/arch/m68k/kernel/process.c
+ *
+ *  Copyright (C) 1995  Hamish Macdonald
+ *
+ *  68060 fixes by Jesper Skov
+ */
+
+/*
+ * This file handles the architecture-dependent parts of process handling..
+ */
+
+#include <linux/errno.h>
+#include <linux/module.h>
+#include <linux/sched.h>
+#include <linux/kernel.h>
+#include <linux/mm.h>
+#include <linux/slab.h>
+#include <linux/fs.h>
+#include <linux/smp.h>
+#include <linux/stddef.h>
+#include <linux/unistd.h>
+#include <linux/ptrace.h>
+#include <linux/user.h>
+#include <linux/reboot.h>
+#include <linux/init_task.h>
+#include <linux/mqueue.h>
+
+#include <asm/uaccess.h>
+#include <asm/system.h>
+#include <asm/traps.h>
+#include <asm/machdep.h>
+#include <asm/setup.h>
+#include <asm/pgtable.h>
+
+
+asmlinkage void ret_from_fork(void);
+
+
+/*
+ * Return saved PC from a blocked thread
+ */
+unsigned long thread_saved_pc(struct task_struct *tsk)
+{
+        struct switch_stack *sw = (struct switch_stack *)tsk->thread.ksp;
+        /* Check whether the thread is blocked in resume() */
+        if (in_sched_functions(sw->retpc))
+                return ((unsigned long *)sw->a6)[1];
+        else
+                return sw->retpc;
+}
+
+/*
+ * The idle loop on an m68k..
+ */
+static void default_idle(void)
+{
+        if (!need_resched())
+#if defined(MACH_ATARI_ONLY)
+                /* block out HSYNC on the atari (falcon) */
+                __asm__("stop #0x2200" : : : "cc");
+#else
+                __asm__("stop #0x2000" : : : "cc");
+#endif
+}
+
+void (*idle)(void) = default_idle;
+
+/*
+ * The idle thread. There's no useful work to be
+ * done, so just try to conserve power and have a
+ * low exit latency (ie sit in a loop waiting for
+ * somebody to say that they'd like to reschedule)
+ */
+void cpu_idle(void)
+{
+        /* endless idle loop with no priority at all */
+        while (1) {
+                while (!need_resched())
+                        idle();
+                schedule_preempt_disabled();
+        }
+}
+
+void machine_restart(char * __unused)
+{
+        if (mach_reset)
+                mach_reset();
+        for (;;);
+}
+
+void machine_halt(void)
+{
+        if (mach_halt)
+                mach_halt();
+        for (;;);
+}
+
+void machine_power_off(void)
+{
+        if (mach_power_off)
+                mach_power_off();
+        for (;;);
+}
+
+void (*pm_power_off)(void) = machine_power_off;
+EXPORT_SYMBOL(pm_power_off);
+
+void show_regs(struct pt_regs * regs)
+{
+        printk("\n");
+        printk("Format %02x  Vector: %04x  PC: %08lx  Status: %04x    %s\n",
+               regs->format, regs->vector, regs->pc, regs->sr, print_tainted());
+        printk("ORIG_D0: %08lx  D0: %08lx  A2: %08lx  A1: %08lx\n",
+               regs->orig_d0, regs->d0, regs->a2, regs->a1);
+        printk("A0: %08lx  D5: %08lx  D4: %08lx\n",
+               regs->a0, regs->d5, regs->d4);
+        printk("D3: %08lx  D2: %08lx  D1: %08lx\n",
+               regs->d3, regs->d2, regs->d1);
+        if (!(regs->sr & PS_S))
+                printk("USP: %08lx\n", rdusp());
+}
+
+/*
+ * Create a kernel thread
+ */
+int kernel_thread(int (*fn)(void *), void * arg, unsigned long flags)
+{
+        int pid;
+        mm_segment_t fs;
+
+        fs = get_fs();
+        set_fs (KERNEL_DS);
+
+        {
+        register long retval __asm__ ("d0");
+        register long clone_arg __asm__ ("d1") = flags | CLONE_VM | CLONE_UNTRACED;
+
+        retval = __NR_clone;
+        __asm__ __volatile__
+          ("clrl %%d2\n\t"
+           "trap #0\n\t"                /* Linux/m68k system call */
+           "tstl %0\n\t"                /* child or parent */
+           "jne 1f\n\t"                 /* parent - jump */
+#ifdef CONFIG_MMU
+           "lea %%sp@(%c7),%6\n\t"      /* reload current */
+           "movel %6@,%6\n\t"
+#endif
+           "movel %3,%%sp@-\n\t"        /* push argument */
+           "jsr %4@\n\t"                /* call fn */
+           "movel %0,%%d1\n\t"          /* pass exit value */
+           "movel %2,%%d0\n\t"          /* exit */
+           "trap #0\n"
+           "1:"
+           : "+d" (retval)
+           : "i" (__NR_clone), "i" (__NR_exit),
+             "r" (arg), "a" (fn), "d" (clone_arg), "r" (current),
+             "i" (-THREAD_SIZE)
+           : "d2");
+
+        pid = retval;
+        }
+
+        set_fs (fs);
+        return pid;
+}
+EXPORT_SYMBOL(kernel_thread);
+
+void flush_thread(void)
+{
+        current->thread.fs = __USER_DS;
+#ifdef CONFIG_FPU
+        if (!FPU_IS_EMU) {
+                unsigned long zero = 0;
+                asm volatile("frestore %0": :"m" (zero));
+        }
+#endif
+}
+
+/*
+ * "m68k_fork()".. By the time we get here, the
+ * non-volatile registers have also been saved on the
+ * stack. We do some ugly pointer stuff here.. (see
+ * also copy_thread)
+ */
+
+asmlinkage int m68k_fork(struct pt_regs *regs)
+{
 #ifdef CONFIG_MMU
-#include "process_mm.c"
+        return do_fork(SIGCHLD, rdusp(), regs, 0, NULL, NULL);
 #else
-#include "process_no.c"
+        return -EINVAL;
 #endif
+}
+
+asmlinkage int m68k_vfork(struct pt_regs *regs)
+{
+        return do_fork(CLONE_VFORK | CLONE_VM | SIGCHLD, rdusp(), regs, 0,
+                       NULL, NULL);
+}
+
+asmlinkage int m68k_clone(struct pt_regs *regs)
+{
+        unsigned long clone_flags;
+        unsigned long newsp;
+        int __user *parent_tidptr, *child_tidptr;
+
+        /* syscall2 puts clone_flags in d1 and usp in d2 */
+        clone_flags = regs->d1;
+        newsp = regs->d2;
+        parent_tidptr = (int __user *)regs->d3;
+        child_tidptr = (int __user *)regs->d4;
+        if (!newsp)
+                newsp = rdusp();
+        return do_fork(clone_flags, newsp, regs, 0,
+                       parent_tidptr, child_tidptr);
+}
+
+int copy_thread(unsigned long clone_flags, unsigned long usp,
+                 unsigned long unused,
+                 struct task_struct * p, struct pt_regs * regs)
+{
+        struct pt_regs * childregs;
+        struct switch_stack * childstack, *stack;
+        unsigned long *retp;
+
+        childregs = (struct pt_regs *) (task_stack_page(p) + THREAD_SIZE) - 1;
+
+        *childregs = *regs;
+        childregs->d0 = 0;
+
+        retp = ((unsigned long *) regs);
+        stack = ((struct switch_stack *) retp) - 1;
+
+        childstack = ((struct switch_stack *) childregs) - 1;
+        *childstack = *stack;
+        childstack->retpc = (unsigned long)ret_from_fork;
+
+        p->thread.usp = usp;
+        p->thread.ksp = (unsigned long)childstack;
+
+        if (clone_flags & CLONE_SETTLS)
+                task_thread_info(p)->tp_value = regs->d5;
+
+        /*
+         * Must save the current SFC/DFC value, NOT the value when
+         * the parent was last descheduled - RGH  10-08-96
+         */
+        p->thread.fs = get_fs().seg;
+
+#ifdef CONFIG_FPU
+        if (!FPU_IS_EMU) {
+                /* Copy the current fpu state */
+                asm volatile ("fsave %0" : : "m" (p->thread.fpstate[0]) : "memory");
+
+                if (!CPU_IS_060 ? p->thread.fpstate[0] : p->thread.fpstate[2]) {
+                        if (CPU_IS_COLDFIRE) {
+                                asm volatile ("fmovemd %/fp0-%/fp7,%0\n\t"
+                                              "fmovel %/fpiar,%1\n\t"
+                                              "fmovel %/fpcr,%2\n\t"
+                                              "fmovel %/fpsr,%3"
+                                              :
+                                              : "m" (p->thread.fp[0]),
+                                                "m" (p->thread.fpcntl[0]),
+                                                "m" (p->thread.fpcntl[1]),
+                                                "m" (p->thread.fpcntl[2])
+                                              : "memory");
+                        } else {
+                                asm volatile ("fmovemx %/fp0-%/fp7,%0\n\t"
+                                              "fmoveml %/fpiar/%/fpcr/%/fpsr,%1"
+                                              :
+                                              : "m" (p->thread.fp[0]),
+                                                "m" (p->thread.fpcntl[0])
+                                              : "memory");
+                        }
+                }
+
+                /* Restore the state in case the fpu was busy */
+                asm volatile ("frestore %0" : : "m" (p->thread.fpstate[0]));
+        }
+#endif /* CONFIG_FPU */
+
+        return 0;
+}
+
+/* Fill in the fpu structure for a core dump.  */
+#ifdef CONFIG_FPU
+int dump_fpu (struct pt_regs *regs, struct user_m68kfp_struct *fpu)
+{
+        char fpustate[216];
+
+        if (FPU_IS_EMU) {
+                int i;
+
+                memcpy(fpu->fpcntl, current->thread.fpcntl, 12);
+                memcpy(fpu->fpregs, current->thread.fp, 96);
+                /* Convert internal fpu reg representation
+                 * into long double format
+                 */
+                for (i = 0; i < 24; i += 3)
+                        fpu->fpregs[i] = ((fpu->fpregs[i] & 0xffff0000) << 15) |
+                                         ((fpu->fpregs[i] & 0x0000ffff) << 16);
+                return 1;
+        }
+
+        /* First dump the fpu context to avoid protocol violation.  */
+        asm volatile ("fsave %0" :: "m" (fpustate[0]) : "memory");
+        if (!CPU_IS_060 ? !fpustate[0] : !fpustate[2])
+                return 0;
+
+        if (CPU_IS_COLDFIRE) {
+                asm volatile ("fmovel %/fpiar,%0\n\t"
+                              "fmovel %/fpcr,%1\n\t"
+                              "fmovel %/fpsr,%2\n\t"
+                              "fmovemd %/fp0-%/fp7,%3"
+                              :
+                              : "m" (fpu->fpcntl[0]),
+                                "m" (fpu->fpcntl[1]),
+                                "m" (fpu->fpcntl[2]),
+                                "m" (fpu->fpregs[0])
+                              : "memory");
+        } else {
+                asm volatile ("fmovem %/fpiar/%/fpcr/%/fpsr,%0"
+                              :
+                              : "m" (fpu->fpcntl[0])
+                              : "memory");
+                asm volatile ("fmovemx %/fp0-%/fp7,%0"
+                              :
+                              : "m" (fpu->fpregs[0])
+                              : "memory");
+        }
+
+        return 1;
+}
+EXPORT_SYMBOL(dump_fpu);
+#endif /* CONFIG_FPU */
+
+/*
+ * sys_execve() executes a new program.
+ */
+asmlinkage int sys_execve(const char __user *name,
+                          const char __user *const __user *argv,
+                          const char __user *const __user *envp)
+{
+        int error;
+        char * filename;
+        struct pt_regs *regs = (struct pt_regs *) &name;
+
+        filename = getname(name);
+        error = PTR_ERR(filename);
+        if (IS_ERR(filename))
+                return error;
+        error = do_execve(filename, argv, envp, regs);
+        putname(filename);
+        return error;
+}
+
+unsigned long get_wchan(struct task_struct *p)
+{
+        unsigned long fp, pc;
+        unsigned long stack_page;
+        int count = 0;
+        if (!p || p == current || p->state == TASK_RUNNING)
+                return 0;
+
+        stack_page = (unsigned long)task_stack_page(p);
+        fp = ((struct switch_stack *)p->thread.ksp)->a6;
+        do {
+                if (fp < stack_page+sizeof(struct thread_info) ||
+                    fp >= 8184+stack_page)
+                        return 0;
+                pc = ((unsigned long *)fp)[1];
+                if (!in_sched_functions(pc))
+                        return pc;
+                fp = *(unsigned long *) fp;
+        } while (count++ < 16);
+        return 0;
+}
diff --git a/arch/m68k/kernel/process_mm.c b/arch/m68k/kernel/process_mm.c
deleted file mode 100644
index fe4186b5fc3..00000000000
--- a/arch/m68k/kernel/process_mm.c
+++ /dev/null
@@ -1,367 +0,0 @@
-/*
- *  linux/arch/m68k/kernel/process.c
- *
- *  Copyright (C) 1995  Hamish Macdonald
- *
- *  68060 fixes by Jesper Skov
- */
-
-/*
- * This file handles the architecture-dependent parts of process handling..
- */
-
-#include <linux/errno.h>
-#include <linux/module.h>
-#include <linux/sched.h>
-#include <linux/kernel.h>
-#include <linux/mm.h>
-#include <linux/slab.h>
-#include <linux/fs.h>
-#include <linux/smp.h>
-#include <linux/stddef.h>
-#include <linux/unistd.h>
-#include <linux/ptrace.h>
-#include <linux/user.h>
-#include <linux/reboot.h>
-#include <linux/init_task.h>
-#include <linux/mqueue.h>
-
-#include <asm/uaccess.h>
-#include <asm/system.h>
-#include <asm/traps.h>
-#include <asm/machdep.h>
-#include <asm/setup.h>
-#include <asm/pgtable.h>
-
-
-asmlinkage void ret_from_fork(void);
-
-
-/*
- * Return saved PC from a blocked thread
- */
-unsigned long thread_saved_pc(struct task_struct *tsk)
-{
-        struct switch_stack *sw = (struct switch_stack *)tsk->thread.ksp;
-        /* Check whether the thread is blocked in resume() */
-        if (in_sched_functions(sw->retpc))
-                return ((unsigned long *)sw->a6)[1];
-        else
-                return sw->retpc;
-}
-
-/*
- * The idle loop on an m68k..
- */
-static void default_idle(void)
-{
-        if (!need_resched())
-#if defined(MACH_ATARI_ONLY)
-                /* block out HSYNC on the atari (falcon) */
-                __asm__("stop #0x2200" : : : "cc");
-#else
-                __asm__("stop #0x2000" : : : "cc");
-#endif
-}
-
-void (*idle)(void) = default_idle;
-
-/*
- * The idle thread. There's no useful work to be
- * done, so just try to conserve power and have a
- * low exit latency (ie sit in a loop waiting for
- * somebody to say that they'd like to reschedule)
- */
-void cpu_idle(void)
-{
-        /* endless idle loop with no priority at all */
-        while (1) {
-                while (!need_resched())
-                        idle();
-                schedule_preempt_disabled();
-        }
-}
-
-void machine_restart(char * __unused)
-{
-        if (mach_reset)
-                mach_reset();
-        for (;;);
-}
-
-void machine_halt(void)
-{
-        if (mach_halt)
-                mach_halt();
-        for (;;);
-}
-
-void machine_power_off(void)
-{
-        if (mach_power_off)
-                mach_power_off();
-        for (;;);
-}
-
-void (*pm_power_off)(void) = machine_power_off;
-EXPORT_SYMBOL(pm_power_off);
-
-void show_regs(struct pt_regs * regs)
-{
-        printk("\n");
-        printk("Format %02x  Vector: %04x  PC: %08lx  Status: %04x    %s\n",
-               regs->format, regs->vector, regs->pc, regs->sr, print_tainted());
-        printk("ORIG_D0: %08lx  D0: %08lx  A2: %08lx  A1: %08lx\n",
-               regs->orig_d0, regs->d0, regs->a2, regs->a1);
-        printk("A0: %08lx  D5: %08lx  D4: %08lx\n",
-               regs->a0, regs->d5, regs->d4);
-        printk("D3: %08lx  D2: %08lx  D1: %08lx\n",
-               regs->d3, regs->d2, regs->d1);
-        if (!(regs->sr & PS_S))
-                printk("USP: %08lx\n", rdusp());
-}
-
-/*
- * Create a kernel thread
- */
-int kernel_thread(int (*fn)(void *), void * arg, unsigned long flags)
-{
-        int pid;
-        mm_segment_t fs;
-
-        fs = get_fs();
-        set_fs (KERNEL_DS);
-
-        {
-        register long retval __asm__ ("d0");
-        register long clone_arg __asm__ ("d1") = flags | CLONE_VM | CLONE_UNTRACED;
-
-        retval = __NR_clone;
-        __asm__ __volatile__
-          ("clrl %%d2\n\t"
-           "trap #0\n\t"                /* Linux/m68k system call */
-           "tstl %0\n\t"                /* child or parent */
-           "jne 1f\n\t"                 /* parent - jump */
-           "lea %%sp@(%c7),%6\n\t"      /* reload current */
-           "movel %6@,%6\n\t"
-           "movel %3,%%sp@-\n\t"        /* push argument */
-           "jsr %4@\n\t"                /* call fn */
-           "movel %0,%%d1\n\t"          /* pass exit value */
-           "movel %2,%%d0\n\t"          /* exit */
-           "trap #0\n"
-           "1:"
-           : "+d" (retval)
-           : "i" (__NR_clone), "i" (__NR_exit),
-             "r" (arg), "a" (fn), "d" (clone_arg), "r" (current),
-             "i" (-THREAD_SIZE)
-           : "d2");
-
-        pid = retval;
-        }
-
-        set_fs (fs);
-        return pid;
-}
-EXPORT_SYMBOL(kernel_thread);
-
-void flush_thread(void)
-{
-        unsigned long zero = 0;
-
-        current->thread.fs = __USER_DS;
-        if (!FPU_IS_EMU)
-                asm volatile("frestore %0": :"m" (zero));
-}
-
-/*
- * "m68k_fork()".. By the time we get here, the
- * non-volatile registers have also been saved on the
- * stack. We do some ugly pointer stuff here.. (see
- * also copy_thread)
- */
-
-asmlinkage int m68k_fork(struct pt_regs *regs)
-{
-        return do_fork(SIGCHLD, rdusp(), regs, 0, NULL, NULL);
-}
-
-asmlinkage int m68k_vfork(struct pt_regs *regs)
-{
-        return do_fork(CLONE_VFORK | CLONE_VM | SIGCHLD, rdusp(), regs, 0,
-                       NULL, NULL);
-}
-
-asmlinkage int m68k_clone(struct pt_regs *regs)
-{
-        unsigned long clone_flags;
-        unsigned long newsp;
-        int __user *parent_tidptr, *child_tidptr;
-
-        /* syscall2 puts clone_flags in d1 and usp in d2 */
-        clone_flags = regs->d1;
-        newsp = regs->d2;
-        parent_tidptr = (int __user *)regs->d3;
-        child_tidptr = (int __user *)regs->d4;
-        if (!newsp)
-                newsp = rdusp();
-        return do_fork(clone_flags, newsp, regs, 0,
-                       parent_tidptr, child_tidptr);
-}
-
-int copy_thread(unsigned long clone_flags, unsigned long usp,
-                 unsigned long unused,
-                 struct task_struct * p, struct pt_regs * regs)
-{
-        struct pt_regs * childregs;
-        struct switch_stack * childstack, *stack;
-        unsigned long *retp;
-
-        childregs = (struct pt_regs *) (task_stack_page(p) + THREAD_SIZE) - 1;
-
-        *childregs = *regs;
-        childregs->d0 = 0;
-
-        retp = ((unsigned long *) regs);
-        stack = ((struct switch_stack *) retp) - 1;
-
-        childstack = ((struct switch_stack *) childregs) - 1;
-        *childstack = *stack;
-        childstack->retpc = (unsigned long)ret_from_fork;
-
-        p->thread.usp = usp;
-        p->thread.ksp = (unsigned long)childstack;
-
-        if (clone_flags & CLONE_SETTLS)
-                task_thread_info(p)->tp_value = regs->d5;
-
-        /*
-         * Must save the current SFC/DFC value, NOT the value when
-         * the parent was last descheduled - RGH  10-08-96
-         */
-        p->thread.fs = get_fs().seg;
-
-        if (!FPU_IS_EMU) {
-                /* Copy the current fpu state */
-                asm volatile ("fsave %0" : : "m" (p->thread.fpstate[0]) : "memory");
-
-                if (!CPU_IS_060 ? p->thread.fpstate[0] : p->thread.fpstate[2]) {
-                        if (CPU_IS_COLDFIRE) {
-                                asm volatile ("fmovemd %/fp0-%/fp7,%0\n\t"
-                                              "fmovel %/fpiar,%1\n\t"
-                                              "fmovel %/fpcr,%2\n\t"
-                                              "fmovel %/fpsr,%3"
-                                              :
-                                              : "m" (p->thread.fp[0]),
-                                                "m" (p->thread.fpcntl[0]),
-                                                "m" (p->thread.fpcntl[1]),
-                                                "m" (p->thread.fpcntl[2])
-                                              : "memory");
-                        } else {
-                                asm volatile ("fmovemx %/fp0-%/fp7,%0\n\t"
-                                              "fmoveml %/fpiar/%/fpcr/%/fpsr,%1"
-                                              :
-                                              : "m" (p->thread.fp[0]),
-                                                "m" (p->thread.fpcntl[0])
-                                              : "memory");
-                        }
-                }
-
-                /* Restore the state in case the fpu was busy */
-                asm volatile ("frestore %0" : : "m" (p->thread.fpstate[0]));
-        }
-
-        return 0;
-}
-
-/* Fill in the fpu structure for a core dump.  */
-
-int dump_fpu (struct pt_regs *regs, struct user_m68kfp_struct *fpu)
-{
-        char fpustate[216];
-
-        if (FPU_IS_EMU) {
-                int i;
-
-                memcpy(fpu->fpcntl, current->thread.fpcntl, 12);
-                memcpy(fpu->fpregs, current->thread.fp, 96);
-                /* Convert internal fpu reg representation
-                 * into long double format
-                 */
-                for (i = 0; i < 24; i += 3)
-                        fpu->fpregs[i] = ((fpu->fpregs[i] & 0xffff0000) << 15) |
-                                         ((fpu->fpregs[i] & 0x0000ffff) << 16);
-                return 1;
-        }
-
-        /* First dump the fpu context to avoid protocol violation.  */
-        asm volatile ("fsave %0" :: "m" (fpustate[0]) : "memory");
-        if (!CPU_IS_060 ? !fpustate[0] : !fpustate[2])
-                return 0;
-
-        if (CPU_IS_COLDFIRE) {
-                asm volatile ("fmovel %/fpiar,%0\n\t"
-                              "fmovel %/fpcr,%1\n\t"
-                              "fmovel %/fpsr,%2\n\t"
-                              "fmovemd %/fp0-%/fp7,%3"
-                              :
-                              : "m" (fpu->fpcntl[0]),
-                                "m" (fpu->fpcntl[1]),
-                                "m" (fpu->fpcntl[2]),
-                                "m" (fpu->fpregs[0])
-                              : "memory");
-        } else {
-                asm volatile ("fmovem %/fpiar/%/fpcr/%/fpsr,%0"
-                              :
-                              : "m" (fpu->fpcntl[0])
-                              : "memory");
-                asm volatile ("fmovemx %/fp0-%/fp7,%0"
-                              :
-                              : "m" (fpu->fpregs[0])
-                              : "memory");
-        }
-
-        return 1;
-}
-EXPORT_SYMBOL(dump_fpu);
-
-/*
- * sys_execve() executes a new program.
- */
-asmlinkage int sys_execve(const char __user *name,
-                          const char __user *const __user *argv,
-                          const char __user *const __user *envp)
-{
-        int error;
-        char * filename;
-        struct pt_regs *regs = (struct pt_regs *) &name;
-
-        filename = getname(name);
-        error = PTR_ERR(filename);
-        if (IS_ERR(filename))
-                return error;
-        error = do_execve(filename, argv, envp, regs);
-        putname(filename);
-        return error;
-}
-
-unsigned long get_wchan(struct task_struct *p)
-{
-        unsigned long fp, pc;
-        unsigned long stack_page;
-        int count = 0;
-        if (!p || p == current || p->state == TASK_RUNNING)
-                return 0;
-
-        stack_page = (unsigned long)task_stack_page(p);
-        fp = ((struct switch_stack *)p->thread.ksp)->a6;
-        do {
-                if (fp < stack_page+sizeof(struct thread_info) ||
-                    fp >= 8184+stack_page)
-                        return 0;
-                pc = ((unsigned long *)fp)[1];
-                if (!in_sched_functions(pc))
-                        return pc;
-                fp = *(unsigned long *) fp;
-        } while (count++ < 16);
-        return 0;
-}
diff --git a/arch/m68k/kernel/process_no.c b/arch/m68k/kernel/process_no.c
deleted file mode 100644
index f7fe6c34859..00000000000
--- a/arch/m68k/kernel/process_no.c
+++ /dev/null
@@ -1,404 +0,0 @@
-/*
- *  linux/arch/m68knommu/kernel/process.c
- *
- *  Copyright (C) 1995  Hamish Macdonald
- *
- *  68060 fixes by Jesper Skov
- *
- *  uClinux changes
- *  Copyright (C) 2000-2002, David McCullough <davidm@snapgear.com>
- */
-
-/*
- * This file handles the architecture-dependent parts of process handling..
- */
-
-#include <linux/module.h>
-#include <linux/errno.h>
-#include <linux/sched.h>
-#include <linux/kernel.h>
-#include <linux/mm.h>
-#include <linux/smp.h>
-#include <linux/stddef.h>
-#include <linux/unistd.h>
-#include <linux/ptrace.h>
-#include <linux/user.h>
-#include <linux/interrupt.h>
-#include <linux/reboot.h>
-#include <linux/fs.h>
-#include <linux/slab.h>
-
-#include <asm/uaccess.h>
-#include <asm/system.h>
-#include <asm/traps.h>
-#include <asm/machdep.h>
-#include <asm/setup.h>
-#include <asm/pgtable.h>
-
-asmlinkage void ret_from_fork(void);
-
-/*
- * The following aren't currently used.
- */
-void (*pm_idle)(void);
-EXPORT_SYMBOL(pm_idle);
-
-void (*pm_power_off)(void);
-EXPORT_SYMBOL(pm_power_off);
-
-/*
- * The idle loop on an m68knommu..
- */
-static void default_idle(void)
-{
-        local_irq_disable();
-        while (!need_resched()) {
-                /* This stop will re-enable interrupts */
-                __asm__("stop #0x2000" : : : "cc");
-                local_irq_disable();
-        }
-        local_irq_enable();
-}
-
-void (*idle)(void) = default_idle;
-
-/*
- * The idle thread. There's no useful work to be
- * done, so just try to conserve power and have a
- * low exit latency (ie sit in a loop waiting for
- * somebody to say that they'd like to reschedule)
- */
-void cpu_idle(void)
-{
-        /* endless idle loop with no priority at all */
-        while (1) {
-                idle();
-                schedule_preempt_disabled();
-        }
-}
-
-void machine_restart(char * __unused)
-{
-        if (mach_reset)
-                mach_reset();
-        for (;;);
-}
-
-void machine_halt(void)
-{
-        if (mach_halt)
-                mach_halt();
-        for (;;);
-}
-
-void machine_power_off(void)
-{
-        if (mach_power_off)
-                mach_power_off();
-        for (;;);
-}
-
-void show_regs(struct pt_regs * regs)
-{
-        printk(KERN_NOTICE "\n");
-        printk(KERN_NOTICE "Format %02x  Vector: %04x  PC: %08lx  Status: %04x    %s\n",
-               regs->format, regs->vector, regs->pc, regs->sr, print_tainted());
-        printk(KERN_NOTICE "ORIG_D0: %08lx  D0: %08lx  A2: %08lx  A1: %08lx\n",
-               regs->orig_d0, regs->d0, regs->a2, regs->a1);
-        printk(KERN_NOTICE "A0: %08lx  D5: %08lx  D4: %08lx\n",
-               regs->a0, regs->d5, regs->d4);
-        printk(KERN_NOTICE "D3: %08lx  D2: %08lx  D1: %08lx\n",
-               regs->d3, regs->d2, regs->d1);
-        if (!(regs->sr & PS_S))
-                printk(KERN_NOTICE "USP: %08lx\n", rdusp());
-}
-
-/*
- * Create a kernel thread
- */
-int kernel_thread(int (*fn)(void *), void * arg, unsigned long flags)
-{
-        int retval;
-        long clone_arg = flags | CLONE_VM;
-        mm_segment_t fs;
-
-        fs = get_fs();
-        set_fs(KERNEL_DS);
-
-        __asm__ __volatile__ (
-                        "movel  %%sp, %%d2\n\t"
-                        "movel  %5, %%d1\n\t"
-                        "movel  %1, %%d0\n\t"
-                        "trap   #0\n\t"
-                        "cmpl   %%sp, %%d2\n\t"
-                        "jeq    1f\n\t"
-                        "movel  %3, %%sp@-\n\t"
-                        "jsr    %4@\n\t"
-                        "movel  %2, %%d0\n\t"
-                        "trap   #0\n"
-                        "1:\n\t"
-                        "movel  %%d0, %0\n"
-                : "=d" (retval)
-                : "i" (__NR_clone),
-                  "i" (__NR_exit),
-                  "a" (arg),
-                  "a" (fn),
-                  "a" (clone_arg)
-                : "cc", "%d0", "%d1", "%d2");
-
-        set_fs(fs);
-        return retval;
-}
-EXPORT_SYMBOL(kernel_thread);
-
-void flush_thread(void)
-{
-#ifdef CONFIG_FPU
-        unsigned long zero = 0;
-#endif
-
-        current->thread.fs = __USER_DS;
-#ifdef CONFIG_FPU
-        if (!FPU_IS_EMU)
-                asm volatile (".chip 68k/68881\n\t"
-                              "frestore %0\n\t"
-                              ".chip 68k" : : "m" (zero));
-#endif
-}
-
-/*
- * "m68k_fork()".. By the time we get here, the
- * non-volatile registers have also been saved on the
- * stack. We do some ugly pointer stuff here.. (see
- * also copy_thread)
- */
-
-asmlinkage int m68k_fork(struct pt_regs *regs)
-{
-        /* fork almost works, enough to trick you into looking elsewhere :-( */
-        return(-EINVAL);
-}
-
-asmlinkage int m68k_vfork(struct pt_regs *regs)
-{
-        return do_fork(CLONE_VFORK | CLONE_VM | SIGCHLD, rdusp(), regs, 0, NULL, NULL);
-}
-
-asmlinkage int m68k_clone(struct pt_regs *regs)
-{
-        unsigned long clone_flags;
-        unsigned long newsp;
-
-        /* syscall2 puts clone_flags in d1 and usp in d2 */
-        clone_flags = regs->d1;
-        newsp = regs->d2;
-        if (!newsp)
-                newsp = rdusp();
-        return do_fork(clone_flags, newsp, regs, 0, NULL, NULL);
-}
-
-int copy_thread(unsigned long clone_flags,
-                unsigned long usp, unsigned long topstk,
-                struct task_struct * p, struct pt_regs * regs)
-{
-        struct pt_regs * childregs;
-        struct switch_stack * childstack, *stack;
-        unsigned long *retp;
-
-        childregs = (struct pt_regs *) (task_stack_page(p) + THREAD_SIZE) - 1;
-
-        *childregs = *regs;
-        childregs->d0 = 0;
-
-        retp = ((unsigned long *) regs);
-        stack = ((struct switch_stack *) retp) - 1;
-
-        childstack = ((struct switch_stack *) childregs) - 1;
-        *childstack = *stack;
-        childstack->retpc = (unsigned long)ret_from_fork;
-
-        p->thread.usp = usp;
-        p->thread.ksp = (unsigned long)childstack;
-
-        if (clone_flags & CLONE_SETTLS)
-                task_thread_info(p)->tp_value = regs->d5;
-
-        /*
-         * Must save the current SFC/DFC value, NOT the value when
-         * the parent was last descheduled - RGH  10-08-96
-         */
-        p->thread.fs = get_fs().seg;
-
-#ifdef CONFIG_FPU
-        if (!FPU_IS_EMU) {
-                /* Copy the current fpu state */
-                asm volatile ("fsave %0" : : "m" (p->thread.fpstate[0]) : "memory");
-
-                if (p->thread.fpstate[0])
-                  asm volatile ("fmovemx %/fp0-%/fp7,%0\n\t"
-                                "fmoveml %/fpiar/%/fpcr/%/fpsr,%1"
-                                : : "m" (p->thread.fp[0]), "m" (p->thread.fpcntl[0])
-                                : "memory");
-                /* Restore the state in case the fpu was busy */
-                asm volatile ("frestore %0" : : "m" (p->thread.fpstate[0]));
-        }
-#endif
-
-        return 0;
-}
-
-/* Fill in the fpu structure for a core dump.  */
-
-int dump_fpu(struct pt_regs *regs, struct user_m68kfp_struct *fpu)
-{
-#ifdef CONFIG_FPU
-        char fpustate[216];
-
-        if (FPU_IS_EMU) {
-                int i;
-
-                memcpy(fpu->fpcntl, current->thread.fpcntl, 12);
-                memcpy(fpu->fpregs, current->thread.fp, 96);
-                /* Convert internal fpu reg representation
-                 * into long double format
-                 */
-                for (i = 0; i < 24; i += 3)
-                        fpu->fpregs[i] = ((fpu->fpregs[i] & 0xffff0000) << 15) |
-                                         ((fpu->fpregs[i] & 0x0000ffff) << 16);
-                return 1;
-        }
-
-        /* First dump the fpu context to avoid protocol violation.  */
-        asm volatile ("fsave %0" :: "m" (fpustate[0]) : "memory");
-        if (!fpustate[0])
-                return 0;
-
-        asm volatile ("fmovem %/fpiar/%/fpcr/%/fpsr,%0"
-                :: "m" (fpu->fpcntl[0])
-                : "memory");
-        asm volatile ("fmovemx %/fp0-%/fp7,%0"
-                :: "m" (fpu->fpregs[0])
-                : "memory");
-#endif
-        return 1;
-}
-EXPORT_SYMBOL(dump_fpu);
-
-/*
- *      Generic dumping code. Used for panic and debug.
- */
-void dump(struct pt_regs *fp)
-{
-        unsigned long   *sp;
-        unsigned char   *tp;
-        int             i;
-
-        printk(KERN_EMERG "\nCURRENT PROCESS:\n\n");
-        printk(KERN_EMERG "COMM=%s PID=%d\n", current->comm, current->pid);
-
-        if (current->mm) {
-                printk(KERN_EMERG "TEXT=%08x-%08x DATA=%08x-%08x BSS=%08x-%08x\n",
-                        (int) current->mm->start_code,
-                        (int) current->mm->end_code,
-                        (int) current->mm->start_data,
-                        (int) current->mm->end_data,
-                        (int) current->mm->end_data,
-                        (int) current->mm->brk);
-                printk(KERN_EMERG "USER-STACK=%08x KERNEL-STACK=%08x\n\n",
-                        (int) current->mm->start_stack,
-                        (int)(((unsigned long) current) + THREAD_SIZE));
-        }
-
-        printk(KERN_EMERG "PC: %08lx\n", fp->pc);
-        printk(KERN_EMERG "SR: %08lx    SP: %08lx\n", (long) fp->sr, (long) fp);
-        printk(KERN_EMERG "d0: %08lx    d1: %08lx    d2: %08lx    d3: %08lx\n",
-                fp->d0, fp->d1, fp->d2, fp->d3);
-        printk(KERN_EMERG "d4: %08lx    d5: %08lx    a0: %08lx    a1: %08lx\n",
-                fp->d4, fp->d5, fp->a0, fp->a1);
-        printk(KERN_EMERG "\nUSP: %08x   TRAPFRAME: %p\n",
-                (unsigned int) rdusp(), fp);
-
-        printk(KERN_EMERG "\nCODE:");
-        tp = ((unsigned char *) fp->pc) - 0x20;
-        for (sp = (unsigned long *) tp, i = 0; (i < 0x40);  i += 4) {
-                if ((i % 0x10) == 0)
-                        printk(KERN_EMERG "%p: ", tp + i);
-                printk("%08x ", (int) *sp++);
-        }
-        printk(KERN_EMERG "\n");
-
-        printk(KERN_EMERG "KERNEL STACK:");
-        tp = ((unsigned char *) fp) - 0x40;
-        for (sp = (unsigned long *) tp, i = 0; (i < 0xc0); i += 4) {
-                if ((i % 0x10) == 0)
-                        printk(KERN_EMERG "%p: ", tp + i);
-                printk("%08x ", (int) *sp++);
-        }
-        printk(KERN_EMERG "\n");
-
-        printk(KERN_EMERG "USER STACK:");
-        tp = (unsigned char *) (rdusp() - 0x10);
-        for (sp = (unsigned long *) tp, i = 0; (i < 0x80); i += 4) {
-                if ((i % 0x10) == 0)
-                        printk(KERN_EMERG "%p: ", tp + i);
-                printk("%08x ", (int) *sp++);
-        }
-        printk(KERN_EMERG "\n");
-}
-
-/*
- * sys_execve() executes a new program.
- */
-asmlinkage int sys_execve(const char *name,
-                          const char *const *argv,
-                          const char *const *envp)
-{
-        int error;
-        char * filename;
-        struct pt_regs *regs = (struct pt_regs *) &name;
-
-        filename = getname(name);
-        error = PTR_ERR(filename);
-        if (IS_ERR(filename))
-                return error;
-        error = do_execve(filename, argv, envp, regs);
-        putname(filename);
-        return error;
-}
-
-unsigned long get_wchan(struct task_struct *p)
-{
-        unsigned long fp, pc;
-        unsigned long stack_page;
-        int count = 0;
-        if (!p || p == current || p->state == TASK_RUNNING)
-                return 0;
-
-        stack_page = (unsigned long)p;
-        fp = ((struct switch_stack *)p->thread.ksp)->a6;
-        do {
-                if (fp < stack_page+sizeof(struct thread_info) ||
-                    fp >= THREAD_SIZE-8+stack_page)
-                        return 0;
-                pc = ((unsigned long *)fp)[1];
-                if (!in_sched_functions(pc))
-                        return pc;
-                fp = *(unsigned long *) fp;
-        } while (count++ < 16);
-        return 0;
-}
-
-/*
- * Return saved PC of a blocked thread.
- */
-unsigned long thread_saved_pc(struct task_struct *tsk)
-{
-        struct switch_stack *sw = (struct switch_stack *)tsk->thread.ksp;
-
-        /* Check whether the thread is blocked in resume() */
-        if (in_sched_functions(sw->retpc))
-                return ((unsigned long *)sw->a6)[1];
-        else
-                return sw->retpc;
-}
-
diff --git a/arch/m68k/kernel/ptrace.c b/arch/m68k/kernel/ptrace.c
index 07a417550e9..149a05f8b9e 100644
--- a/arch/m68k/kernel/ptrace.c
+++ b/arch/m68k/kernel/ptrace.c
@@ -1,5 +1,305 @@
+/*
+ *  linux/arch/m68k/kernel/ptrace.c
+ *
+ *  Copyright (C) 1994 by Hamish Macdonald
+ *  Taken from linux/kernel/ptrace.c and modified for M680x0.
+ *  linux/kernel/ptrace.c is by Ross Biro 1/23/92, edited by Linus Torvalds
+ *
+ * This file is subject to the terms and conditions of the GNU General
+ * Public License.  See the file COPYING in the main directory of
+ * this archive for more details.
+ */
+
+#include <linux/kernel.h>
+#include <linux/sched.h>
+#include <linux/mm.h>
+#include <linux/smp.h>
+#include <linux/errno.h>
+#include <linux/ptrace.h>
+#include <linux/user.h>
+#include <linux/signal.h>
+#include <linux/tracehook.h>
+
+#include <asm/uaccess.h>
+#include <asm/page.h>
+#include <asm/pgtable.h>
+#include <asm/system.h>
+#include <asm/processor.h>
+
+/*
+ * does not yet catch signals sent when the child dies.
+ * in exit.c or in signal.c.
+ */
+
+/* determines which bits in the SR the user has access to. */
+/* 1 = access 0 = no access */
+#define SR_MASK 0x001f
+
+/* sets the trace bits. */
+#define TRACE_BITS 0xC000
+#define T1_BIT 0x8000
+#define T0_BIT 0x4000
+
+/* Find the stack offset for a register, relative to thread.esp0. */
+#define PT_REG(reg)     ((long)&((struct pt_regs *)0)->reg)
+#define SW_REG(reg)     ((long)&((struct switch_stack *)0)->reg \
+                         - sizeof(struct switch_stack))
+/* Mapping from PT_xxx to the stack offset at which the register is
+   saved.  Notice that usp has no stack-slot and needs to be treated
+   specially (see get_reg/put_reg below). */
+static const int regoff[] = {
+        [0]     = PT_REG(d1),
+        [1]     = PT_REG(d2),
+        [2]     = PT_REG(d3),
+        [3]     = PT_REG(d4),
+        [4]     = PT_REG(d5),
+        [5]     = SW_REG(d6),
+        [6]     = SW_REG(d7),
+        [7]     = PT_REG(a0),
+        [8]     = PT_REG(a1),
+        [9]     = PT_REG(a2),
+        [10]    = SW_REG(a3),
+        [11]    = SW_REG(a4),
+        [12]    = SW_REG(a5),
+        [13]    = SW_REG(a6),
+        [14]    = PT_REG(d0),
+        [15]    = -1,
+        [16]    = PT_REG(orig_d0),
+        [17]    = PT_REG(sr),
+        [18]    = PT_REG(pc),
+};
+
+/*
+ * Get contents of register REGNO in task TASK.
+ */
+static inline long get_reg(struct task_struct *task, int regno)
+{
+        unsigned long *addr;
+
+        if (regno == PT_USP)
+                addr = &task->thread.usp;
+        else if (regno < ARRAY_SIZE(regoff))
+                addr = (unsigned long *)(task->thread.esp0 + regoff[regno]);
+        else
+                return 0;
+        /* Need to take stkadj into account. */
+        if (regno == PT_SR || regno == PT_PC) {
+                long stkadj = *(long *)(task->thread.esp0 + PT_REG(stkadj));
+                addr = (unsigned long *) ((unsigned long)addr + stkadj);
+                /* The sr is actually a 16 bit register.  */
+                if (regno == PT_SR)
+                        return *(unsigned short *)addr;
+        }
+        return *addr;
+}
+
+/*
+ * Write contents of register REGNO in task TASK.
+ */
+static inline int put_reg(struct task_struct *task, int regno,
+                          unsigned long data)
+{
+        unsigned long *addr;
+
+        if (regno == PT_USP)
+                addr = &task->thread.usp;
+        else if (regno < ARRAY_SIZE(regoff))
+                addr = (unsigned long *)(task->thread.esp0 + regoff[regno]);
+        else
+                return -1;
+        /* Need to take stkadj into account. */
+        if (regno == PT_SR || regno == PT_PC) {
+                long stkadj = *(long *)(task->thread.esp0 + PT_REG(stkadj));
+                addr = (unsigned long *) ((unsigned long)addr + stkadj);
+                /* The sr is actually a 16 bit register.  */
+                if (regno == PT_SR) {
+                        *(unsigned short *)addr = data;
+                        return 0;
+                }
+        }
+        *addr = data;
+        return 0;
+}
+
+/*
+ * Make sure the single step bit is not set.
+ */
+static inline void singlestep_disable(struct task_struct *child)
+{
+        unsigned long tmp = get_reg(child, PT_SR) & ~TRACE_BITS;
+        put_reg(child, PT_SR, tmp);
+        clear_tsk_thread_flag(child, TIF_DELAYED_TRACE);
+}
+
+/*
+ * Called by kernel/ptrace.c when detaching..
+ */
+void ptrace_disable(struct task_struct *child)
+{
+        singlestep_disable(child);
+}
+
+void user_enable_single_step(struct task_struct *child)
+{
+        unsigned long tmp = get_reg(child, PT_SR) & ~TRACE_BITS;
+        put_reg(child, PT_SR, tmp | T1_BIT);
+        set_tsk_thread_flag(child, TIF_DELAYED_TRACE);
+}
+
 #ifdef CONFIG_MMU
-#include "ptrace_mm.c"
-#else
-#include "ptrace_no.c"
+void user_enable_block_step(struct task_struct *child)
+{
+        unsigned long tmp = get_reg(child, PT_SR) & ~TRACE_BITS;
+        put_reg(child, PT_SR, tmp | T0_BIT);
+}
 #endif
+
+void user_disable_single_step(struct task_struct *child)
+{
+        singlestep_disable(child);
+}
+
+long arch_ptrace(struct task_struct *child, long request,
+                 unsigned long addr, unsigned long data)
+{
+        unsigned long tmp;
+        int i, ret = 0;
+        int regno = addr >> 2; /* temporary hack. */
+        unsigned long __user *datap = (unsigned long __user *) data;
+
+        switch (request) {
+        /* read the word at location addr in the USER area. */
+        case PTRACE_PEEKUSR:
+                if (addr & 3)
+                        goto out_eio;
+
+                if (regno >= 0 && regno < 19) {
+                        tmp = get_reg(child, regno);
+                } else if (regno >= 21 && regno < 49) {
+                        tmp = child->thread.fp[regno - 21];
+                        /* Convert internal fpu reg representation
+                         * into long double format
+                         */
+                        if (FPU_IS_EMU && (regno < 45) && !(regno % 3))
+                                tmp = ((tmp & 0xffff0000) << 15) |
+                                      ((tmp & 0x0000ffff) << 16);
+#ifndef CONFIG_MMU
+                } else if (regno == 49) {
+                        tmp = child->mm->start_code;
+                } else if (regno == 50) {
+                        tmp = child->mm->start_data;
+                } else if (regno == 51) {
+                        tmp = child->mm->end_code;
+#endif
+                } else
+                        goto out_eio;
+                ret = put_user(tmp, datap);
+                break;
+
+        case PTRACE_POKEUSR:
+        /* write the word at location addr in the USER area */
+                if (addr & 3)
+                        goto out_eio;
+
+                if (regno == PT_SR) {
+                        data &= SR_MASK;
+                        data |= get_reg(child, PT_SR) & ~SR_MASK;
+                }
+                if (regno >= 0 && regno < 19) {
+                        if (put_reg(child, regno, data))
+                                goto out_eio;
+                } else if (regno >= 21 && regno < 48) {
+                        /* Convert long double format
+                         * into internal fpu reg representation
+                         */
+                        if (FPU_IS_EMU && (regno < 45) && !(regno % 3)) {
+                                data <<= 15;
+                                data = (data & 0xffff0000) |
+                                       ((data & 0x0000ffff) >> 1);
+                        }
+                        child->thread.fp[regno - 21] = data;
+                } else
+                        goto out_eio;
+                break;
+
+        case PTRACE_GETREGS:    /* Get all gp regs from the child. */
+                for (i = 0; i < 19; i++) {
+                        tmp = get_reg(child, i);
+                        ret = put_user(tmp, datap);
+                        if (ret)
+                                break;
+                        datap++;
+                }
+                break;
+
+        case PTRACE_SETREGS:    /* Set all gp regs in the child. */
+                for (i = 0; i < 19; i++) {
+                        ret = get_user(tmp, datap);
+                        if (ret)
+                                break;
+                        if (i == PT_SR) {
+                                tmp &= SR_MASK;
+                                tmp |= get_reg(child, PT_SR) & ~SR_MASK;
+                        }
+                        put_reg(child, i, tmp);
+                        datap++;
+                }
+                break;
+
+        case PTRACE_GETFPREGS:  /* Get the child FPU state. */
+                if (copy_to_user(datap, &child->thread.fp,
+                                 sizeof(struct user_m68kfp_struct)))
+                        ret = -EFAULT;
+                break;
+
+        case PTRACE_SETFPREGS:  /* Set the child FPU state. */
+                if (copy_from_user(&child->thread.fp, datap,
+                                   sizeof(struct user_m68kfp_struct)))
+                        ret = -EFAULT;
+                break;
+
+        case PTRACE_GET_THREAD_AREA:
+                ret = put_user(task_thread_info(child)->tp_value, datap);
+                break;
+
+        default:
+                ret = ptrace_request(child, request, addr, data);
+                break;
+        }
+
+        return ret;
+out_eio:
+        return -EIO;
+}
+
+asmlinkage void syscall_trace(void)
+{
+        ptrace_notify(SIGTRAP | ((current->ptrace & PT_TRACESYSGOOD)
+                                 ? 0x80 : 0));
+        /*
+         * this isn't the same as continuing with a signal, but it will do
+         * for normal use.  strace only continues with a signal if the
+         * stopping signal is not SIGTRAP.  -brl
+         */
+        if (current->exit_code) {
+                send_sig(current->exit_code, current, 1);
+                current->exit_code = 0;
+        }
+}
+
+#ifdef CONFIG_COLDFIRE
+asmlinkage int syscall_trace_enter(void)
+{
+        int ret = 0;
+
+        if (test_thread_flag(TIF_SYSCALL_TRACE))
+                ret = tracehook_report_syscall_entry(task_pt_regs(current));
+        return ret;
+}
+
+asmlinkage void syscall_trace_leave(void)
+{
+        if (test_thread_flag(TIF_SYSCALL_TRACE))
+                tracehook_report_syscall_exit(task_pt_regs(current), 0);
+}
+#endif /* CONFIG_COLDFIRE */
diff --git a/arch/m68k/kernel/ptrace_mm.c b/arch/m68k/kernel/ptrace_mm.c
deleted file mode 100644
index 7bc999b7352..00000000000
--- a/arch/m68k/kernel/ptrace_mm.c
+++ /dev/null
@@ -1,295 +0,0 @@
-/*
- *  linux/arch/m68k/kernel/ptrace.c
- *
- *  Copyright (C) 1994 by Hamish Macdonald
- *  Taken from linux/kernel/ptrace.c and modified for M680x0.
- *  linux/kernel/ptrace.c is by Ross Biro 1/23/92, edited by Linus Torvalds
- *
- * This file is subject to the terms and conditions of the GNU General
- * Public License.  See the file COPYING in the main directory of
- * this archive for more details.
- */
-
-#include <linux/kernel.h>
-#include <linux/sched.h>
-#include <linux/mm.h>
-#include <linux/smp.h>
-#include <linux/errno.h>
-#include <linux/ptrace.h>
-#include <linux/user.h>
-#include <linux/signal.h>
-#include <linux/tracehook.h>
-
-#include <asm/uaccess.h>
-#include <asm/page.h>
-#include <asm/pgtable.h>
-#include <asm/system.h>
-#include <asm/processor.h>
-
-/*
- * does not yet catch signals sent when the child dies.
- * in exit.c or in signal.c.
- */
-
-/* determines which bits in the SR the user has access to. */
-/* 1 = access 0 = no access */
-#define SR_MASK 0x001f
-
-/* sets the trace bits. */
-#define TRACE_BITS 0xC000
-#define T1_BIT 0x8000
-#define T0_BIT 0x4000
-
-/* Find the stack offset for a register, relative to thread.esp0. */
-#define PT_REG(reg)     ((long)&((struct pt_regs *)0)->reg)
-#define SW_REG(reg)     ((long)&((struct switch_stack *)0)->reg \
-                         - sizeof(struct switch_stack))
-/* Mapping from PT_xxx to the stack offset at which the register is
-   saved.  Notice that usp has no stack-slot and needs to be treated
-   specially (see get_reg/put_reg below). */
-static const int regoff[] = {
-        [0]     = PT_REG(d1),
-        [1]     = PT_REG(d2),
-        [2]     = PT_REG(d3),
-        [3]     = PT_REG(d4),
-        [4]     = PT_REG(d5),
-        [5]     = SW_REG(d6),
-        [6]     = SW_REG(d7),
-        [7]     = PT_REG(a0),
-        [8]     = PT_REG(a1),
-        [9]     = PT_REG(a2),
-        [10]    = SW_REG(a3),
-        [11]    = SW_REG(a4),
-        [12]    = SW_REG(a5),
-        [13]    = SW_REG(a6),
-        [14]    = PT_REG(d0),
-        [15]    = -1,
-        [16]    = PT_REG(orig_d0),
-        [17]    = PT_REG(sr),
-        [18]    = PT_REG(pc),
-};
-
-/*
- * Get contents of register REGNO in task TASK.
- */
-static inline long get_reg(struct task_struct *task, int regno)
-{
-        unsigned long *addr;
-
-        if (regno == PT_USP)
-                addr = &task->thread.usp;
-        else if (regno < ARRAY_SIZE(regoff))
-                addr = (unsigned long *)(task->thread.esp0 + regoff[regno]);
-        else
-                return 0;
-        /* Need to take stkadj into account. */
-        if (regno == PT_SR || regno == PT_PC) {
-                long stkadj = *(long *)(task->thread.esp0 + PT_REG(stkadj));
-                addr = (unsigned long *) ((unsigned long)addr + stkadj);
-                /* The sr is actually a 16 bit register.  */
-                if (regno == PT_SR)
-                        return *(unsigned short *)addr;
-        }
-        return *addr;
-}
-
-/*
- * Write contents of register REGNO in task TASK.
- */
-static inline int put_reg(struct task_struct *task, int regno,
-                          unsigned long data)
-{
-        unsigned long *addr;
-
-        if (regno == PT_USP)
-                addr = &task->thread.usp;
-        else if (regno < ARRAY_SIZE(regoff))
-                addr = (unsigned long *)(task->thread.esp0 + regoff[regno]);
-        else
-                return -1;
-        /* Need to take stkadj into account. */
-        if (regno == PT_SR || regno == PT_PC) {
-                long stkadj = *(long *)(task->thread.esp0 + PT_REG(stkadj));
-                addr = (unsigned long *) ((unsigned long)addr + stkadj);
-                /* The sr is actually a 16 bit register.  */
-                if (regno == PT_SR) {
-                        *(unsigned short *)addr = data;
-                        return 0;
-                }
-        }
-        *addr = data;
-        return 0;
-}
-
-/*
- * Make sure the single step bit is not set.
- */
-static inline void singlestep_disable(struct task_struct *child)
-{
-        unsigned long tmp = get_reg(child, PT_SR) & ~TRACE_BITS;
-        put_reg(child, PT_SR, tmp);
-        clear_tsk_thread_flag(child, TIF_DELAYED_TRACE);
-}
-
-/*
- * Called by kernel/ptrace.c when detaching..
- */
-void ptrace_disable(struct task_struct *child)
-{
-        singlestep_disable(child);
-}
-
-void user_enable_single_step(struct task_struct *child)
-{
-        unsigned long tmp = get_reg(child, PT_SR) & ~TRACE_BITS;
-        put_reg(child, PT_SR, tmp | T1_BIT);
-        set_tsk_thread_flag(child, TIF_DELAYED_TRACE);
-}
-
-void user_enable_block_step(struct task_struct *child)
-{
-        unsigned long tmp = get_reg(child, PT_SR) & ~TRACE_BITS;
-        put_reg(child, PT_SR, tmp | T0_BIT);
-}
-
-void user_disable_single_step(struct task_struct *child)
-{
-        singlestep_disable(child);
-}
-
-long arch_ptrace(struct task_struct *child, long request,
-                 unsigned long addr, unsigned long data)
-{
-        unsigned long tmp;
-        int i, ret = 0;
-        int regno = addr >> 2; /* temporary hack. */
-        unsigned long __user *datap = (unsigned long __user *) data;
-
-        switch (request) {
-        /* read the word at location addr in the USER area. */
-        case PTRACE_PEEKUSR:
-                if (addr & 3)
-                        goto out_eio;
-
-                if (regno >= 0 && regno < 19) {
-                        tmp = get_reg(child, regno);
-                } else if (regno >= 21 && regno < 49) {
-                        tmp = child->thread.fp[regno - 21];
-                        /* Convert internal fpu reg representation
-                         * into long double format
-                         */
-                        if (FPU_IS_EMU && (regno < 45) && !(regno % 3))
-                                tmp = ((tmp & 0xffff0000) << 15) |
-                                      ((tmp & 0x0000ffff) << 16);
-                } else
-                        goto out_eio;
-                ret = put_user(tmp, datap);
-                break;
-
-        case PTRACE_POKEUSR:
-        /* write the word at location addr in the USER area */
-                if (addr & 3)
-                        goto out_eio;
-
-                if (regno == PT_SR) {
-                        data &= SR_MASK;
-                        data |= get_reg(child, PT_SR) & ~SR_MASK;
-                }
-                if (regno >= 0 && regno < 19) {
-                        if (put_reg(child, regno, data))
-                                goto out_eio;
-                } else if (regno >= 21 && regno < 48) {
-                        /* Convert long double format
-                         * into internal fpu reg representation
-                         */
-                        if (FPU_IS_EMU && (regno < 45) && !(regno % 3)) {
-                                data <<= 15;
-                                data = (data & 0xffff0000) |
-                                       ((data & 0x0000ffff) >> 1);
-                        }
-                        child->thread.fp[regno - 21] = data;
-                } else
-                        goto out_eio;
-                break;
-
-        case PTRACE_GETREGS:    /* Get all gp regs from the child. */
-                for (i = 0; i < 19; i++) {
-                        tmp = get_reg(child, i);
-                        ret = put_user(tmp, datap);
-                        if (ret)
-                                break;
-                        datap++;
-                }
-                break;
-
-        case PTRACE_SETREGS:    /* Set all gp regs in the child. */
-                for (i = 0; i < 19; i++) {
-                        ret = get_user(tmp, datap);
-                        if (ret)
-                                break;
-                        if (i == PT_SR) {
-                                tmp &= SR_MASK;
-                                tmp |= get_reg(child, PT_SR) & ~SR_MASK;
-                        }
-                        put_reg(child, i, tmp);
-                        datap++;
-                }
-                break;
-
-        case PTRACE_GETFPREGS:  /* Get the child FPU state. */
-                if (copy_to_user(datap, &child->thread.fp,
-                                 sizeof(struct user_m68kfp_struct)))
-                        ret = -EFAULT;
-                break;
-
-        case PTRACE_SETFPREGS:  /* Set the child FPU state. */
-                if (copy_from_user(&child->thread.fp, datap,
-                                   sizeof(struct user_m68kfp_struct)))
-                        ret = -EFAULT;
-                break;
-
-        case PTRACE_GET_THREAD_AREA:
-                ret = put_user(task_thread_info(child)->tp_value, datap);
-                break;
-
-        default:
-                ret = ptrace_request(child, request, addr, data);
-                break;
-        }
-
-        return ret;
-out_eio:
-        return -EIO;
-}
-
-asmlinkage void syscall_trace(void)
-{
-        ptrace_notify(SIGTRAP | ((current->ptrace & PT_TRACESYSGOOD)
-                                 ? 0x80 : 0));
-        /*
-         * this isn't the same as continuing with a signal, but it will do
-         * for normal use.  strace only continues with a signal if the
-         * stopping signal is not SIGTRAP.  -brl
-         */
-        if (current->exit_code) {
-                send_sig(current->exit_code, current, 1);
-                current->exit_code = 0;
-        }
-}
-
-#ifdef CONFIG_COLDFIRE
-asmlinkage int syscall_trace_enter(void)
-{
-        int ret = 0;
-
-        if (test_thread_flag(TIF_SYSCALL_TRACE))
-                ret = tracehook_report_syscall_entry(task_pt_regs(current));
-        return ret;
-}
-
-asmlinkage void syscall_trace_leave(void)
-{
-        if (test_thread_flag(TIF_SYSCALL_TRACE))
-                tracehook_report_syscall_exit(task_pt_regs(current), 0);
-}
-#endif /* CONFIG_COLDFIRE */
diff --git a/arch/m68k/kernel/ptrace_no.c b/arch/m68k/kernel/ptrace_no.c
deleted file mode 100644
index 6709fb70733..00000000000
--- a/arch/m68k/kernel/ptrace_no.c
+++ /dev/null
@@ -1,255 +0,0 @@
-/*
- *  linux/arch/m68knommu/kernel/ptrace.c
- *
- *  Copyright (C) 1994 by Hamish Macdonald
- *  Taken from linux/kernel/ptrace.c and modified for M680x0.
- *  linux/kernel/ptrace.c is by Ross Biro 1/23/92, edited by Linus Torvalds
- *
- * This file is subject to the terms and conditions of the GNU General
- * Public License.  See the file COPYING in the main directory of
- * this archive for more details.
- */
-
-#include <linux/kernel.h>
-#include <linux/sched.h>
-#include <linux/mm.h>
-#include <linux/smp.h>
-#include <linux/errno.h>
-#include <linux/ptrace.h>
-#include <linux/user.h>
-#include <linux/signal.h>
-#include <linux/tracehook.h>
-
-#include <asm/uaccess.h>
-#include <asm/page.h>
-#include <asm/pgtable.h>
-#include <asm/system.h>
-#include <asm/processor.h>
-
-/*
- * does not yet catch signals sent when the child dies.
- * in exit.c or in signal.c.
- */
-
-/* determines which bits in the SR the user has access to. */
-/* 1 = access 0 = no access */
-#define SR_MASK 0x001f
-
-/* sets the trace bits. */
-#define TRACE_BITS 0x8000
-
-/* Find the stack offset for a register, relative to thread.esp0. */
-#define PT_REG(reg)     ((long)&((struct pt_regs *)0)->reg)
-#define SW_REG(reg)     ((long)&((struct switch_stack *)0)->reg \
-                         - sizeof(struct switch_stack))
-/* Mapping from PT_xxx to the stack offset at which the register is
-   saved.  Notice that usp has no stack-slot and needs to be treated
-   specially (see get_reg/put_reg below). */
-static int regoff[] = {
-        PT_REG(d1), PT_REG(d2), PT_REG(d3), PT_REG(d4),
-        PT_REG(d5), SW_REG(d6), SW_REG(d7), PT_REG(a0),
-        PT_REG(a1), PT_REG(a2), SW_REG(a3), SW_REG(a4),
-        SW_REG(a5), SW_REG(a6), PT_REG(d0), -1,
-        PT_REG(orig_d0), PT_REG(sr), PT_REG(pc),
-};
-
-/*
- * Get contents of register REGNO in task TASK.
- */
-static inline long get_reg(struct task_struct *task, int regno)
-{
-        unsigned long *addr;
-
-        if (regno == PT_USP)
-                addr = &task->thread.usp;
-        else if (regno < ARRAY_SIZE(regoff))
-                addr = (unsigned long *)(task->thread.esp0 + regoff[regno]);
-        else
-                return 0;
-        return *addr;
-}
-
-/*
- * Write contents of register REGNO in task TASK.
- */
-static inline int put_reg(struct task_struct *task, int regno,
-                          unsigned long data)
-{
-        unsigned long *addr;
-
-        if (regno == PT_USP)
-                addr = &task->thread.usp;
-        else if (regno < ARRAY_SIZE(regoff))
-                addr = (unsigned long *) (task->thread.esp0 + regoff[regno]);
-        else
-                return -1;
-        *addr = data;
-        return 0;
-}
-
-void user_enable_single_step(struct task_struct *task)
-{
-        unsigned long srflags;
-        srflags = get_reg(task, PT_SR) | (TRACE_BITS << 16);
-        put_reg(task, PT_SR, srflags);
-}
-
-void user_disable_single_step(struct task_struct *task)
-{
-        unsigned long srflags;
-        srflags = get_reg(task, PT_SR) & ~(TRACE_BITS << 16);
-        put_reg(task, PT_SR, srflags);
-}
-
-/*
- * Called by kernel/ptrace.c when detaching..
- *
- * Make sure the single step bit is not set.
- */
-void ptrace_disable(struct task_struct *child)
-{
-        /* make sure the single step bit is not set. */
-        user_disable_single_step(child);
-}
-
-long arch_ptrace(struct task_struct *child, long request,
-                 unsigned long addr, unsigned long data)
-{
-        int ret;
-        int regno = addr >> 2;
-        unsigned long __user *datap = (unsigned long __user *) data;
-
-        switch (request) {
-                /* read the word at location addr in the USER area. */
-                case PTRACE_PEEKUSR: {
-                        unsigned long tmp;
-                        
-                        ret = -EIO;
-                        if ((addr & 3) || addr > sizeof(struct user) - 3)
-                                break;
-                        
-                        tmp = 0;  /* Default return condition */
-                        ret = -EIO;
-                        if (regno < 19) {
-                                tmp = get_reg(child, regno);
-                                if (regno == PT_SR)
-                                        tmp >>= 16;
-                        } else if (regno >= 21 && regno < 49) {
-                                tmp = child->thread.fp[regno - 21];
-                        } else if (regno == 49) {
-                                tmp = child->mm->start_code;
-                        } else if (regno == 50) {
-                                tmp = child->mm->start_data;
-                        } else if (regno == 51) {
-                                tmp = child->mm->end_code;
-                        } else
-                                break;
-                        ret = put_user(tmp, datap);
-                        break;
-                }
-
-                case PTRACE_POKEUSR: /* write the word at location addr in the USER area */
-                        ret = -EIO;
-                        if ((addr & 3) || addr > sizeof(struct user) - 3)
-                                break;
-
-                        if (regno == PT_SR) {
-                                data &= SR_MASK;
-                                data <<= 16;
-                                data |= get_reg(child, PT_SR) & ~(SR_MASK << 16);
-                        }
-                        if (regno < 19) {
-                                if (put_reg(child, regno, data))
-                                        break;
-                                ret = 0;
-                                break;
-                        }
-                        if (regno >= 21 && regno < 48)
-                        {
-                                child->thread.fp[regno - 21] = data;
-                                ret = 0;
-                        }
-                        break;
-
-                case PTRACE_GETREGS: { /* Get all gp regs from the child. */
-                        int i;
-                        unsigned long tmp;
-                        for (i = 0; i < 19; i++) {
-                            tmp = get_reg(child, i);
-                            if (i == PT_SR)
-                                tmp >>= 16;
-                            if (put_user(tmp, datap)) {
-                                ret = -EFAULT;
-                                break;
-                            }
-                            datap++;
-                        }
-                        ret = 0;
-                        break;
-                }
-
-                case PTRACE_SETREGS: { /* Set all gp regs in the child. */
-                        int i;
-                        unsigned long tmp;
-                        for (i = 0; i < 19; i++) {
-                            if (get_user(tmp, datap)) {
-                                ret = -EFAULT;
-                                break;
-                            }
-                            if (i == PT_SR) {
-                                tmp &= SR_MASK;
-                                tmp <<= 16;
-                                tmp |= get_reg(child, PT_SR) & ~(SR_MASK << 16);
-                            }
-                            put_reg(child, i, tmp);
-                            datap++;
-                        }
-                        ret = 0;
-                        break;
-                }
-
-#ifdef PTRACE_GETFPREGS
-                case PTRACE_GETFPREGS: { /* Get the child FPU state. */
-                        ret = 0;
-                        if (copy_to_user(datap, &child->thread.fp,
-                                         sizeof(struct user_m68kfp_struct)))
-                                ret = -EFAULT;
-                        break;
-                }
-#endif
-
-#ifdef PTRACE_SETFPREGS
-                case PTRACE_SETFPREGS: { /* Set the child FPU state. */
-                        ret = 0;
-                        if (copy_from_user(&child->thread.fp, datap,
-                                           sizeof(struct user_m68kfp_struct)))
-                                ret = -EFAULT;
-                        break;
-                }
-#endif
-
-        case PTRACE_GET_THREAD_AREA:
-                ret = put_user(task_thread_info(child)->tp_value, datap);
-                break;
-
-                default:
-                        ret = ptrace_request(child, request, addr, data);
-                        break;
-        }
-        return ret;
-}
-
-asmlinkage int syscall_trace_enter(void)
-{
-        int ret = 0;
-
-        if (test_thread_flag(TIF_SYSCALL_TRACE))
-                ret = tracehook_report_syscall_entry(task_pt_regs(current));
-        return ret;
-}
-
-asmlinkage void syscall_trace_leave(void)
-{
-        if (test_thread_flag(TIF_SYSCALL_TRACE))
-                tracehook_report_syscall_exit(task_pt_regs(current), 0);
-}
diff --git a/arch/m68k/kernel/setup_no.c b/arch/m68k/kernel/setup_no.c
index ca3df0dc7e8..7dc186b7a85 100644
--- a/arch/m68k/kernel/setup_no.c
+++ b/arch/m68k/kernel/setup_no.c
@@ -31,6 +31,7 @@
 #include <linux/init.h>
 #include <linux/initrd.h>
 #include <linux/root_dev.h>
+#include <linux/rtc.h>
 
 #include <asm/setup.h>
 #include <asm/irq.h>
@@ -47,7 +48,9 @@ EXPORT_SYMBOL(memory_end);
 char __initdata command_line[COMMAND_LINE_SIZE];
 
 /* machine dependent timer functions */
+void (*mach_sched_init)(irq_handler_t handler) __initdata = NULL;
 int (*mach_set_clock_mmss)(unsigned long);
+int (*mach_hwclk) (int, struct rtc_time*);
 
 /* machine dependent reboot functions */
 void (*mach_reset)(void);
diff --git a/arch/m68k/kernel/time.c b/arch/m68k/kernel/time.c
index 75ab79b3bde..d7deb7fc7eb 100644
--- a/arch/m68k/kernel/time.c
+++ b/arch/m68k/kernel/time.c
@@ -1,5 +1,111 @@
-#if defined(CONFIG_MMU) && !defined(CONFIG_COLDFIRE)
-#include "time_mm.c"
-#else
-#include "time_no.c"
-#endif
+/*
+ *  linux/arch/m68k/kernel/time.c
+ *
+ *  Copyright (C) 1991, 1992, 1995  Linus Torvalds
+ *
+ * This file contains the m68k-specific time handling details.
+ * Most of the stuff is located in the machine specific files.
+ *
+ * 1997-09-10   Updated NTP code according to technical memorandum Jan '96
+ *              "A Kernel Model for Precision Timekeeping" by Dave Mills
+ */
+
+#include <linux/errno.h>
+#include <linux/module.h>
+#include <linux/sched.h>
+#include <linux/kernel.h>
+#include <linux/param.h>
+#include <linux/string.h>
+#include <linux/mm.h>
+#include <linux/rtc.h>
+#include <linux/platform_device.h>
+
+#include <asm/machdep.h>
+#include <asm/io.h>
+#include <asm/irq_regs.h>
+
+#include <linux/time.h>
+#include <linux/timex.h>
+#include <linux/profile.h>
+
+/*
+ * timer_interrupt() needs to keep up the real-time clock,
+ * as well as call the "xtime_update()" routine every clocktick
+ */
+static irqreturn_t timer_interrupt(int irq, void *dummy)
+{
+        xtime_update(1);
+        update_process_times(user_mode(get_irq_regs()));
+        profile_tick(CPU_PROFILING);
+
+#ifdef CONFIG_HEARTBEAT
+        /* use power LED as a heartbeat instead -- much more useful
+           for debugging -- based on the version for PReP by Cort */
+        /* acts like an actual heart beat -- ie thump-thump-pause... */
+        if (mach_heartbeat) {
+            static unsigned cnt = 0, period = 0, dist = 0;
+
+            if (cnt == 0 || cnt == dist)
+                mach_heartbeat( 1 );
+            else if (cnt == 7 || cnt == dist+7)
+                mach_heartbeat( 0 );
+
+            if (++cnt > period) {
+                cnt = 0;
+                /* The hyperbolic function below modifies the heartbeat period
+                 * length in dependency of the current (5min) load. It goes
+                 * through the points f(0)=126, f(1)=86, f(5)=51,
+                 * f(inf)->30. */
+                period = ((672<<FSHIFT)/(5*avenrun[0]+(7<<FSHIFT))) + 30;
+                dist = period / 4;
+            }
+        }
+#endif /* CONFIG_HEARTBEAT */
+        return IRQ_HANDLED;
+}
+
+void read_persistent_clock(struct timespec *ts)
+{
+        struct rtc_time time;
+        ts->tv_sec = 0;
+        ts->tv_nsec = 0;
+
+        if (mach_hwclk) {
+                mach_hwclk(0, &time);
+
+                if ((time.tm_year += 1900) < 1970)
+                        time.tm_year += 100;
+                ts->tv_sec = mktime(time.tm_year, time.tm_mon, time.tm_mday,
+                                      time.tm_hour, time.tm_min, time.tm_sec);
+        }
+}
+
+void __init time_init(void)
+{
+        mach_sched_init(timer_interrupt);
+}
+
+#ifdef CONFIG_M68KCLASSIC
+
+u32 arch_gettimeoffset(void)
+{
+        return mach_gettimeoffset() * 1000;
+}
+
+static int __init rtc_init(void)
+{
+        struct platform_device *pdev;
+
+        if (!mach_hwclk)
+                return -ENODEV;
+
+        pdev = platform_device_register_simple("rtc-generic", -1, NULL, 0);
+        if (IS_ERR(pdev))
+                return PTR_ERR(pdev);
+
+        return 0;
+}
+
+module_init(rtc_init);
+
+#endif /* CONFIG_M68KCLASSIC */
diff --git a/arch/m68k/kernel/time_mm.c b/arch/m68k/kernel/time_mm.c
deleted file mode 100644
index 18b34ee5db3..00000000000
--- a/arch/m68k/kernel/time_mm.c
+++ /dev/null
@@ -1,114 +0,0 @@
-/*
- *  linux/arch/m68k/kernel/time.c
- *
- *  Copyright (C) 1991, 1992, 1995  Linus Torvalds
- *
- * This file contains the m68k-specific time handling details.
- * Most of the stuff is located in the machine specific files.
- *
- * 1997-09-10   Updated NTP code according to technical memorandum Jan '96
- *              "A Kernel Model for Precision Timekeeping" by Dave Mills
- */
-
-#include <linux/errno.h>
-#include <linux/module.h>
-#include <linux/sched.h>
-#include <linux/kernel.h>
-#include <linux/param.h>
-#include <linux/string.h>
-#include <linux/mm.h>
-#include <linux/rtc.h>
-#include <linux/platform_device.h>
-
-#include <asm/machdep.h>
-#include <asm/io.h>
-#include <asm/irq_regs.h>
-
-#include <linux/time.h>
-#include <linux/timex.h>
-#include <linux/profile.h>
-
-static inline int set_rtc_mmss(unsigned long nowtime)
-{
-  if (mach_set_clock_mmss)
-    return mach_set_clock_mmss (nowtime);
-  return -1;
-}
-
-/*
- * timer_interrupt() needs to keep up the real-time clock,
- * as well as call the "xtime_update()" routine every clocktick
- */
-static irqreturn_t timer_interrupt(int irq, void *dummy)
-{
-        xtime_update(1);
-        update_process_times(user_mode(get_irq_regs()));
-        profile_tick(CPU_PROFILING);
-
-#ifdef CONFIG_HEARTBEAT
-        /* use power LED as a heartbeat instead -- much more useful
-           for debugging -- based on the version for PReP by Cort */
-        /* acts like an actual heart beat -- ie thump-thump-pause... */
-        if (mach_heartbeat) {
-            static unsigned cnt = 0, period = 0, dist = 0;
-
-            if (cnt == 0 || cnt == dist)
-                mach_heartbeat( 1 );
-            else if (cnt == 7 || cnt == dist+7)
-                mach_heartbeat( 0 );
-
-            if (++cnt > period) {
-                cnt = 0;
-                /* The hyperbolic function below modifies the heartbeat period
-                 * length in dependency of the current (5min) load. It goes
-                 * through the points f(0)=126, f(1)=86, f(5)=51,
-                 * f(inf)->30. */
-                period = ((672<<FSHIFT)/(5*avenrun[0]+(7<<FSHIFT))) + 30;
-                dist = period / 4;
-            }
-        }
-#endif /* CONFIG_HEARTBEAT */
-        return IRQ_HANDLED;
-}
-
-void read_persistent_clock(struct timespec *ts)
-{
-        struct rtc_time time;
-        ts->tv_sec = 0;
-        ts->tv_nsec = 0;
-
-        if (mach_hwclk) {
-                mach_hwclk(0, &time);
-
-                if ((time.tm_year += 1900) < 1970)
-                        time.tm_year += 100;
-                ts->tv_sec = mktime(time.tm_year, time.tm_mon, time.tm_mday,
-                                      time.tm_hour, time.tm_min, time.tm_sec);
-        }
-}
-
-void __init time_init(void)
-{
-        mach_sched_init(timer_interrupt);
-}
-
-u32 arch_gettimeoffset(void)
-{
-        return mach_gettimeoffset() * 1000;
-}
-
-static int __init rtc_init(void)
-{
-        struct platform_device *pdev;
-
-        if (!mach_hwclk)
-                return -ENODEV;
-
-        pdev = platform_device_register_simple("rtc-generic", -1, NULL, 0);
-        if (IS_ERR(pdev))
-                return PTR_ERR(pdev);
-
-        return 0;
-}
-
-module_init(rtc_init);
diff --git a/arch/m68k/kernel/time_no.c b/arch/m68k/kernel/time_no.c
deleted file mode 100644
index 3ef0f7768dc..00000000000
--- a/arch/m68k/kernel/time_no.c
+++ /dev/null
@@ -1,90 +0,0 @@
-/*
- *  linux/arch/m68knommu/kernel/time.c
- *
- *  Copyright (C) 1991, 1992, 1995  Linus Torvalds
- *
- * This file contains the m68k-specific time handling details.
- * Most of the stuff is located in the machine specific files.
- *
- * 1997-09-10   Updated NTP code according to technical memorandum Jan '96
- *              "A Kernel Model for Precision Timekeeping" by Dave Mills
- */
-
-#include <linux/errno.h>
-#include <linux/module.h>
-#include <linux/sched.h>
-#include <linux/kernel.h>
-#include <linux/param.h>
-#include <linux/string.h>
-#include <linux/mm.h>
-#include <linux/profile.h>
-#include <linux/time.h>
-#include <linux/timex.h>
-
-#include <asm/machdep.h>
-#include <asm/irq_regs.h>
-
-#define TICK_SIZE (tick_nsec / 1000)
-
-/* machine dependent timer functions */
-void (*mach_gettod)(int*, int*, int*, int*, int*, int*);
-
-static inline int set_rtc_mmss(unsigned long nowtime)
-{
-        if (mach_set_clock_mmss)
-                return mach_set_clock_mmss (nowtime);
-        return -1;
-}
-
-#ifndef CONFIG_GENERIC_CLOCKEVENTS
-/*
- * timer_interrupt() needs to keep up the real-time clock,
- * as well as call the "xtime_update()" routine every clocktick
- */
-irqreturn_t arch_timer_interrupt(int irq, void *dummy)
-{
-
-        if (current->pid)
-                profile_tick(CPU_PROFILING);
-
-        xtime_update(1);
-
-        update_process_times(user_mode(get_irq_regs()));
-
-        return(IRQ_HANDLED);
-}
-#endif
-
-static unsigned long read_rtc_mmss(void)
-{
-        unsigned int year, mon, day, hour, min, sec;
-
-        if (mach_gettod) {
-                mach_gettod(&year, &mon, &day, &hour, &min, &sec);
-                if ((year += 1900) < 1970)
-                        year += 100;
-        } else {
-                year = 1970;
-                mon = day = 1;
-                hour = min = sec = 0;
-        }
-
-
-        return  mktime(year, mon, day, hour, min, sec);
-}
-
-void read_persistent_clock(struct timespec *ts)
-{
-        ts->tv_sec = read_rtc_mmss();
-        ts->tv_nsec = 0;
-}
-
-int update_persistent_clock(struct timespec now)
-{
-        return set_rtc_mmss(now.tv_sec);
-}
-
-void time_init(void)
-{
-        hw_timer_init();
-}
diff --git a/arch/m68k/kernel/vmlinux-nommu.lds b/arch/m68k/kernel/vmlinux-nommu.lds
index 8e66ccb0935..40e02d9c38b 100644
--- a/arch/m68k/kernel/vmlinux-nommu.lds
+++ b/arch/m68k/kernel/vmlinux-nommu.lds
@@ -1,195 +1,93 @@
 /*
  *      vmlinux.lds.S -- master linker script for m68knommu arch
  *
- *      (C) Copyright 2002-2006, Greg Ungerer <gerg@snapgear.com>
+ *      (C) Copyright 2002-2012, Greg Ungerer <gerg@snapgear.com>
  *
  *      This linker script is equipped to build either ROM loaded or RAM
  *      run kernels.
  */
 
-#include <asm-generic/vmlinux.lds.h>
-#include <asm/page.h>
-#include <asm/thread_info.h>
-
 #if defined(CONFIG_RAMKERNEL)
-#define RAM_START       CONFIG_KERNELBASE
-#define RAM_LENGTH      (CONFIG_RAMBASE + CONFIG_RAMSIZE - CONFIG_KERNELBASE)
-#define TEXT            ram
-#define DATA            ram
-#define INIT            ram
-#define BSSS            ram
-#endif
-#if defined(CONFIG_ROMKERNEL) || defined(CONFIG_HIMEMKERNEL)
-#define RAM_START       CONFIG_RAMBASE
-#define RAM_LENGTH      CONFIG_RAMSIZE
-#define ROMVEC_START    CONFIG_ROMVEC
-#define ROMVEC_LENGTH   CONFIG_ROMVECSIZE
-#define ROM_START       CONFIG_ROMSTART
-#define ROM_LENGTH      CONFIG_ROMSIZE
-#define TEXT            rom
-#define DATA            ram
-#define INIT            ram
-#define BSSS            ram
+#define KTEXT_ADDR      CONFIG_KERNELBASE
 #endif
-
-#ifndef DATA_ADDR
-#define DATA_ADDR
+#if defined(CONFIG_ROMKERNEL)
+#define KTEXT_ADDR      CONFIG_ROMSTART
+#define KDATA_ADDR      CONFIG_KERNELBASE
+#define LOAD_OFFSET     KDATA_ADDR + (ADDR(.text) + SIZEOF(.text))
 #endif
 
+#include <asm/page.h>
+#include <asm/thread_info.h>
+#include <asm-generic/vmlinux.lds.h>
 
 OUTPUT_ARCH(m68k)
 ENTRY(_start)
 
-MEMORY {
-        ram     : ORIGIN = RAM_START, LENGTH = RAM_LENGTH
-#ifdef ROM_START
-        romvec  : ORIGIN = ROMVEC_START, LENGTH = ROMVEC_LENGTH
-        rom     : ORIGIN = ROM_START, LENGTH = ROM_LENGTH
-#endif
-}
-
 jiffies = jiffies_64 + 4;
 
 SECTIONS {
 
-#ifdef ROMVEC_START
-        . = ROMVEC_START ;
+#ifdef CONFIG_ROMVEC
+        . = CONFIG_ROMVEC;
         .romvec : {
-                __rom_start = . ;
+                __rom_start = .;
                 _romvec = .;
+                *(.romvec)
                 *(.data..initvect)
-        } > romvec
+        }
 #endif
 
+        . = KTEXT_ADDR;
+
+        _text = .;
+        _stext = .;
         .text : {
-                _text = .;
-                _stext = . ;
                 HEAD_TEXT
                 TEXT_TEXT
                 SCHED_TEXT
                 LOCK_TEXT
-                *(.text..lock)
                 *(.fixup)
+                . = ALIGN(16);
+        }
+        _etext = .;
+
+#ifdef KDATA_ADDR
+        . = KDATA_ADDR;
+#endif
+
+        _sdata = .;
+        RO_DATA_SECTION(PAGE_SIZE)
+        RW_DATA_SECTION(16, PAGE_SIZE, THREAD_SIZE)
+        _edata = .;
 
-                . = ALIGN(16);          /* Exception table              */
-                __start___ex_table = .;
-                *(__ex_table)
-                __stop___ex_table = .;
-
-                *(.rodata) *(.rodata.*)
-                *(__vermagic)           /* Kernel version magic */
-                *(.rodata1)
-                *(.rodata.str1.1)
-
-                /* Kernel symbol table: Normal symbols */
-                . = ALIGN(4);
-                __start___ksymtab = .;
-                *(SORT(___ksymtab+*))
-                __stop___ksymtab = .;
-
-                /* Kernel symbol table: GPL-only symbols */
-                __start___ksymtab_gpl = .;
-                *(SORT(___ksymtab_gpl+*))
-                __stop___ksymtab_gpl = .;
-
-                /* Kernel symbol table: Normal unused symbols */
-                __start___ksymtab_unused = .;
-                *(SORT(___ksymtab_unused+*))
-                __stop___ksymtab_unused = .;
-
-                /* Kernel symbol table: GPL-only unused symbols */
-                __start___ksymtab_unused_gpl = .;
-                *(SORT(___ksymtab_unused_gpl+*))
-                __stop___ksymtab_unused_gpl = .;
-
-                /* Kernel symbol table: GPL-future symbols */
-                __start___ksymtab_gpl_future = .;
-                *(SORT(___ksymtab_gpl_future+*))
-                __stop___ksymtab_gpl_future = .;
-
-                /* Kernel symbol table: Normal symbols */
-                __start___kcrctab = .;
-                *(SORT(___kcrctab+*))
-                __stop___kcrctab = .;
-
-                /* Kernel symbol table: GPL-only symbols */
-                __start___kcrctab_gpl = .;
-                *(SORT(___kcrctab_gpl+*))
-                __stop___kcrctab_gpl = .;
-
-                /* Kernel symbol table: Normal unused symbols */
-                __start___kcrctab_unused = .;
-                *(SORT(___kcrctab_unused+*))
-                __stop___kcrctab_unused = .;
-
-                /* Kernel symbol table: GPL-only unused symbols */
-                __start___kcrctab_unused_gpl = .;
-                *(SORT(___kcrctab_unused_gpl+*))
-                __stop___kcrctab_unused_gpl = .;
-
-                /* Kernel symbol table: GPL-future symbols */
-                __start___kcrctab_gpl_future = .;
-                *(SORT(___kcrctab_gpl_future+*))
-                __stop___kcrctab_gpl_future = .;
-
-                /* Kernel symbol table: strings */
-                *(__ksymtab_strings)
-
-                /* Built-in module parameters */
-                . = ALIGN(4) ;
-                __start___param = .;
-                *(__param)
-                __stop___param = .;
-
-                /* Built-in module versions */
-                . = ALIGN(4) ;
-                __start___modver = .;
-                *(__modver)
-                __stop___modver = .;
-
-                . = ALIGN(4) ;
-                _etext = . ;
-        } > TEXT
-
-        .data DATA_ADDR : {
-                . = ALIGN(4);
-                _sdata = . ;
-                DATA_DATA
-                CACHELINE_ALIGNED_DATA(32)
-                PAGE_ALIGNED_DATA(PAGE_SIZE)
-                *(.data..shared_aligned)
-                INIT_TASK_DATA(THREAD_SIZE)
-                _edata = . ;
-        } > DATA
+        EXCEPTION_TABLE(16)
+        NOTES
 
+        . = ALIGN(PAGE_SIZE);
+        __init_begin = .;
+        INIT_TEXT_SECTION(PAGE_SIZE)
+        INIT_DATA_SECTION(16)
+        PERCPU_SECTION(16)
         .m68k_fixup : {
                 __start_fixup = .;
                 *(.m68k_fixup)
                 __stop_fixup = .;
-        } > DATA
-        NOTES > DATA
-
-        .init.text : {
-                . = ALIGN(PAGE_SIZE);
-                __init_begin = .;
-        } > INIT
-        INIT_TEXT_SECTION(PAGE_SIZE) > INIT
-        INIT_DATA_SECTION(16) > INIT
+        }
         .init.data : {
                 . = ALIGN(PAGE_SIZE);
                 __init_end = .;
-        } > INIT
-
-        .bss : {
-                . = ALIGN(4);
-                _sbss = . ;
-                *(.bss)
-                *(COMMON)
-                . = ALIGN(4) ;
-                _ebss = . ;
-                _end = . ;
-        } > BSSS
+        }
+
+        _sbss = .;
+        BSS_SECTION(0, 0, 0)
+        _ebss = .;
+
+        _end = .;
+
+        STABS_DEBUG
+        .comment 0 : { *(.comment) }
 
+        /* Sections to be discarded */
         DISCARDS
 }
 
diff --git a/arch/m68k/platform/5206/config.c b/arch/m68k/platform/5206/config.c
index 6fa3f800277..6bfbeebd231 100644
--- a/arch/m68k/platform/5206/config.c
+++ b/arch/m68k/platform/5206/config.c
@@ -16,83 +16,6 @@
 #include <asm/machdep.h>
 #include <asm/coldfire.h>
 #include <asm/mcfsim.h>
-#include <asm/mcfuart.h>
-
-/***************************************************************************/
-
-static struct mcf_platform_uart m5206_uart_platform[] = {
-        {
-                .mapbase        = MCF_MBAR + MCFUART_BASE1,
-                .irq            = 73,
-        },
-        {
-                .mapbase        = MCF_MBAR + MCFUART_BASE2,
-                .irq            = 74,
-        },
-        { },
-};
-
-static struct platform_device m5206_uart = {
-        .name                   = "mcfuart",
-        .id                     = 0,
-        .dev.platform_data      = m5206_uart_platform,
-};
-
-static struct platform_device *m5206_devices[] __initdata = {
-        &m5206_uart,
-};
-
-/***************************************************************************/
-
-static void __init m5206_uart_init_line(int line, int irq)
-{
-        if (line == 0) {
-                writel(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI1, MCF_MBAR + MCFSIM_UART1ICR);
-                writeb(irq, MCFUART_BASE1 + MCFUART_UIVR);
-                mcf_mapirq2imr(irq, MCFINTC_UART0);
-        } else if (line == 1) {
-                writel(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI2, MCF_MBAR + MCFSIM_UART2ICR);
-                writeb(irq, MCFUART_BASE2 + MCFUART_UIVR);
-                mcf_mapirq2imr(irq, MCFINTC_UART1);
-        }
-}
-
-static void __init m5206_uarts_init(void)
-{
-        const int nrlines = ARRAY_SIZE(m5206_uart_platform);
-        int line;
-
-        for (line = 0; (line < nrlines); line++)
-                m5206_uart_init_line(line, m5206_uart_platform[line].irq);
-}
-
-/***************************************************************************/
-
-static void __init m5206_timers_init(void)
-{
-        /* Timer1 is always used as system timer */
-        writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI3,
-                MCF_MBAR + MCFSIM_TIMER1ICR);
-        mcf_mapirq2imr(MCF_IRQ_TIMER, MCFINTC_TIMER1);
-
-#ifdef CONFIG_HIGHPROFILE
-        /* Timer2 is to be used as a high speed profile timer  */
-        writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL7 | MCFSIM_ICR_PRI3,
-                MCF_MBAR + MCFSIM_TIMER2ICR);
-        mcf_mapirq2imr(MCF_IRQ_PROFILER, MCFINTC_TIMER2);
-#endif
-}
-
-/***************************************************************************/
-
-void m5206_cpu_reset(void)
-{
-        local_irq_disable();
-        /* Set watchdog to soft reset, and enabled */
-        __raw_writeb(0xc0, MCF_MBAR + MCFSIM_SYPCR);
-        for (;;)
-                /* wait for watchdog to timeout */;
-}
 
 /***************************************************************************/
 
@@ -104,9 +27,7 @@ void __init config_BSP(char *commandp, int size)
         commandp[size-1] = 0;
 #endif /* CONFIG_NETtel */
 
-        mach_reset = m5206_cpu_reset;
-        m5206_timers_init();
-        m5206_uarts_init();
+        mach_sched_init = hw_timer_init;
 
         /* Only support the external interrupts on their primary level */
         mcf_mapirq2imr(25, MCFINTC_EINT1);
@@ -115,13 +36,3 @@ void __init config_BSP(char *commandp, int size)
 }
 
 /***************************************************************************/
-
-static int __init init_BSP(void)
-{
-        platform_add_devices(m5206_devices, ARRAY_SIZE(m5206_devices));
-        return 0;
-}
-
-arch_initcall(init_BSP);
-
-/***************************************************************************/
diff --git a/arch/m68k/platform/520x/config.c b/arch/m68k/platform/520x/config.c
index 8a98683f1b1..235947844f2 100644
--- a/arch/m68k/platform/520x/config.c
+++ b/arch/m68k/platform/520x/config.c
@@ -15,194 +15,14 @@
 #include <linux/param.h>
 #include <linux/init.h>
 #include <linux/io.h>
-#include <linux/spi/spi.h>
-#include <linux/gpio.h>
 #include <asm/machdep.h>
 #include <asm/coldfire.h>
 #include <asm/mcfsim.h>
 #include <asm/mcfuart.h>
-#include <asm/mcfqspi.h>
 
 /***************************************************************************/
 
-static struct mcf_platform_uart m520x_uart_platform[] = {
-        {
-                .mapbase        = MCFUART_BASE1,
-                .irq            = MCFINT_VECBASE + MCFINT_UART0,
-        },
-        {
-                .mapbase        = MCFUART_BASE2,
-                .irq            = MCFINT_VECBASE + MCFINT_UART1,
-        },
-        {
-                .mapbase        = MCFUART_BASE3,
-                .irq            = MCFINT_VECBASE + MCFINT_UART2,
-        },
-        { },
-};
-
-static struct platform_device m520x_uart = {
-        .name                   = "mcfuart",
-        .id                     = 0,
-        .dev.platform_data      = m520x_uart_platform,
-};
-
-static struct resource m520x_fec_resources[] = {
-        {
-                .start          = MCFFEC_BASE,
-                .end            = MCFFEC_BASE + MCFFEC_SIZE - 1,
-                .flags          = IORESOURCE_MEM,
-        },
-        {
-                .start          = 64 + 36,
-                .end            = 64 + 36,
-                .flags          = IORESOURCE_IRQ,
-        },
-        {
-                .start          = 64 + 40,
-                .end            = 64 + 40,
-                .flags          = IORESOURCE_IRQ,
-        },
-        {
-                .start          = 64 + 42,
-                .end            = 64 + 42,
-                .flags          = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device m520x_fec = {
-        .name                   = "fec",
-        .id                     = 0,
-        .num_resources          = ARRAY_SIZE(m520x_fec_resources),
-        .resource               = m520x_fec_resources,
-};
-
-#if defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE)
-static struct resource m520x_qspi_resources[] = {
-        {
-                .start          = MCFQSPI_IOBASE,
-                .end            = MCFQSPI_IOBASE + MCFQSPI_IOSIZE - 1,
-                .flags          = IORESOURCE_MEM,
-        },
-        {
-                .start          = MCFINT_VECBASE + MCFINT_QSPI,
-                .end            = MCFINT_VECBASE + MCFINT_QSPI,
-                .flags          = IORESOURCE_IRQ,
-        },
-};
-
-#define MCFQSPI_CS0    46
-#define MCFQSPI_CS1    47
-#define MCFQSPI_CS2    27
-
-static int m520x_cs_setup(struct mcfqspi_cs_control *cs_control)
-{
-        int status;
-
-        status = gpio_request(MCFQSPI_CS0, "MCFQSPI_CS0");
-        if (status) {
-                pr_debug("gpio_request for MCFQSPI_CS0 failed\n");
-                goto fail0;
-        }
-        status = gpio_direction_output(MCFQSPI_CS0, 1);
-        if (status) {
-                pr_debug("gpio_direction_output for MCFQSPI_CS0 failed\n");
-                goto fail1;
-        }
-
-        status = gpio_request(MCFQSPI_CS1, "MCFQSPI_CS1");
-        if (status) {
-                pr_debug("gpio_request for MCFQSPI_CS1 failed\n");
-                goto fail1;
-        }
-        status = gpio_direction_output(MCFQSPI_CS1, 1);
-        if (status) {
-                pr_debug("gpio_direction_output for MCFQSPI_CS1 failed\n");
-                goto fail2;
-        }
-
-        status = gpio_request(MCFQSPI_CS2, "MCFQSPI_CS2");
-        if (status) {
-                pr_debug("gpio_request for MCFQSPI_CS2 failed\n");
-                goto fail2;
-        }
-        status = gpio_direction_output(MCFQSPI_CS2, 1);
-        if (status) {
-                pr_debug("gpio_direction_output for MCFQSPI_CS2 failed\n");
-                goto fail3;
-        }
-
-        return 0;
-
-fail3:
-        gpio_free(MCFQSPI_CS2);
-fail2:
-        gpio_free(MCFQSPI_CS1);
-fail1:
-        gpio_free(MCFQSPI_CS0);
-fail0:
-        return status;
-}
-
-static void m520x_cs_teardown(struct mcfqspi_cs_control *cs_control)
-{
-        gpio_free(MCFQSPI_CS2);
-        gpio_free(MCFQSPI_CS1);
-        gpio_free(MCFQSPI_CS0);
-}
-
-static void m520x_cs_select(struct mcfqspi_cs_control *cs_control,
-                            u8 chip_select, bool cs_high)
-{
-        switch (chip_select) {
-        case 0:
-                gpio_set_value(MCFQSPI_CS0, cs_high);
-                break;
-        case 1:
-                gpio_set_value(MCFQSPI_CS1, cs_high);
-                break;
-        case 2:
-                gpio_set_value(MCFQSPI_CS2, cs_high);
-                break;
-        }
-}
-
-static void m520x_cs_deselect(struct mcfqspi_cs_control *cs_control,
-                              u8 chip_select, bool cs_high)
-{
-        switch (chip_select) {
-        case 0:
-                gpio_set_value(MCFQSPI_CS0, !cs_high);
-                break;
-        case 1:
-                gpio_set_value(MCFQSPI_CS1, !cs_high);
-                break;
-        case 2:
-                gpio_set_value(MCFQSPI_CS2, !cs_high);
-                break;
-        }
-}
-
-static struct mcfqspi_cs_control m520x_cs_control = {
-        .setup                  = m520x_cs_setup,
-        .teardown               = m520x_cs_teardown,
-        .select                 = m520x_cs_select,
-        .deselect               = m520x_cs_deselect,
-};
-
-static struct mcfqspi_platform_data m520x_qspi_data = {
-        .bus_num                = 0,
-        .num_chipselect         = 3,
-        .cs_control             = &m520x_cs_control,
-};
-
-static struct platform_device m520x_qspi = {
-        .name                   = "mcfqspi",
-        .id                     = 0,
-        .num_resources          = ARRAY_SIZE(m520x_qspi_resources),
-        .resource               = m520x_qspi_resources,
-        .dev.platform_data      = &m520x_qspi_data,
-};
+#ifdef CONFIG_SPI_COLDFIRE_QSPI
 
 static void __init m520x_qspi_init(void)
 {
@@ -214,54 +34,28 @@ static void __init m520x_qspi_init(void)
         par &= 0x00ff;
         writew(par, MCF_GPIO_PAR_UART);
 }
-#endif /* defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE) */
-
 
-static struct platform_device *m520x_devices[] __initdata = {
-        &m520x_uart,
-        &m520x_fec,
-#if defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE)
-        &m520x_qspi,
-#endif
-};
+#endif /* CONFIG_SPI_COLDFIRE_QSPI */
 
 /***************************************************************************/
 
-static void __init m520x_uart_init_line(int line, int irq)
+static void __init m520x_uarts_init(void)
 {
         u16 par;
         u8 par2;
 
-        switch (line) {
-        case 0:
-                par = readw(MCF_GPIO_PAR_UART);
-                par |= MCF_GPIO_PAR_UART_PAR_UTXD0 |
-                       MCF_GPIO_PAR_UART_PAR_URXD0;
-                writew(par, MCF_GPIO_PAR_UART);
-                break;
-        case 1:
-                par = readw(MCF_GPIO_PAR_UART);
-                par |= MCF_GPIO_PAR_UART_PAR_UTXD1 |
-                       MCF_GPIO_PAR_UART_PAR_URXD1;
-                writew(par, MCF_GPIO_PAR_UART);
-                break;
-        case 2:
-                par2 = readb(MCF_GPIO_PAR_FECI2C);
-                par2 &= ~0x0F;
-                par2 |= MCF_GPIO_PAR_FECI2C_PAR_SCL_UTXD2 |
-                        MCF_GPIO_PAR_FECI2C_PAR_SDA_URXD2;
-                writeb(par2, MCF_GPIO_PAR_FECI2C);
-                break;
-        }
-}
-
-static void __init m520x_uarts_init(void)
-{
-        const int nrlines = ARRAY_SIZE(m520x_uart_platform);
-        int line;
+        /* UART0 and UART1 GPIO pin setup */
+        par = readw(MCF_GPIO_PAR_UART);
+        par |= MCF_GPIO_PAR_UART_PAR_UTXD0 | MCF_GPIO_PAR_UART_PAR_URXD0;
+        par |= MCF_GPIO_PAR_UART_PAR_UTXD1 | MCF_GPIO_PAR_UART_PAR_URXD1;
+        writew(par, MCF_GPIO_PAR_UART);
 
-        for (line = 0; (line < nrlines); line++)
-                m520x_uart_init_line(line, m520x_uart_platform[line].irq);
+        /* UART1 GPIO pin setup */
+        par2 = readb(MCF_GPIO_PAR_FECI2C);
+        par2 &= ~0x0F;
+        par2 |= MCF_GPIO_PAR_FECI2C_PAR_SCL_UTXD2 |
+                MCF_GPIO_PAR_FECI2C_PAR_SDA_URXD2;
+        writeb(par2, MCF_GPIO_PAR_FECI2C);
 }
 
 /***************************************************************************/
@@ -280,32 +74,14 @@ static void __init m520x_fec_init(void)
 
 /***************************************************************************/
 
-static void m520x_cpu_reset(void)
-{
-        local_irq_disable();
-        __raw_writeb(MCF_RCR_SWRESET, MCF_RCR);
-}
-
-/***************************************************************************/
-
 void __init config_BSP(char *commandp, int size)
 {
-        mach_reset = m520x_cpu_reset;
+        mach_sched_init = hw_timer_init;
         m520x_uarts_init();
         m520x_fec_init();
-#if defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE)
+#ifdef CONFIG_SPI_COLDFIRE_QSPI
         m520x_qspi_init();
 #endif
 }
 
 /***************************************************************************/
-
-static int __init init_BSP(void)
-{
-        platform_add_devices(m520x_devices, ARRAY_SIZE(m520x_devices));
-        return 0;
-}
-
-arch_initcall(init_BSP);
-
-/***************************************************************************/
diff --git a/arch/m68k/platform/523x/config.c b/arch/m68k/platform/523x/config.c
index 71f4436ec80..c8b405d5a96 100644
--- a/arch/m68k/platform/523x/config.c
+++ b/arch/m68k/platform/523x/config.c
@@ -16,215 +16,13 @@
 #include <linux/param.h>
 #include <linux/init.h>
 #include <linux/io.h>
-#include <linux/spi/spi.h>
-#include <linux/gpio.h>
 #include <asm/machdep.h>
 #include <asm/coldfire.h>
 #include <asm/mcfsim.h>
-#include <asm/mcfuart.h>
-#include <asm/mcfqspi.h>
 
 /***************************************************************************/
 
-static struct mcf_platform_uart m523x_uart_platform[] = {
-        {
-                .mapbase        = MCFUART_BASE1,
-                .irq            = MCFINT_VECBASE + MCFINT_UART0,
-        },
-        {
-                .mapbase        = MCFUART_BASE2,
-                .irq            = MCFINT_VECBASE + MCFINT_UART0 + 1,
-        },
-        {
-                .mapbase        = MCFUART_BASE3,
-                .irq            = MCFINT_VECBASE + MCFINT_UART0 + 2,
-        },
-        { },
-};
-
-static struct platform_device m523x_uart = {
-        .name                   = "mcfuart",
-        .id                     = 0,
-        .dev.platform_data      = m523x_uart_platform,
-};
-
-static struct resource m523x_fec_resources[] = {
-        {
-                .start          = MCFFEC_BASE,
-                .end            = MCFFEC_BASE + MCFFEC_SIZE - 1,
-                .flags          = IORESOURCE_MEM,
-        },
-        {
-                .start          = 64 + 23,
-                .end            = 64 + 23,
-                .flags          = IORESOURCE_IRQ,
-        },
-        {
-                .start          = 64 + 27,
-                .end            = 64 + 27,
-                .flags          = IORESOURCE_IRQ,
-        },
-        {
-                .start          = 64 + 29,
-                .end            = 64 + 29,
-                .flags          = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device m523x_fec = {
-        .name                   = "fec",
-        .id                     = 0,
-        .num_resources          = ARRAY_SIZE(m523x_fec_resources),
-        .resource               = m523x_fec_resources,
-};
-
-#if defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE)
-static struct resource m523x_qspi_resources[] = {
-        {
-                .start          = MCFQSPI_IOBASE,
-                .end            = MCFQSPI_IOBASE + MCFQSPI_IOSIZE - 1,
-                .flags          = IORESOURCE_MEM,
-        },
-        {
-                .start          = MCFINT_VECBASE + MCFINT_QSPI,
-                .end            = MCFINT_VECBASE + MCFINT_QSPI,
-                .flags          = IORESOURCE_IRQ,
-        },
-};
-
-#define MCFQSPI_CS0    91
-#define MCFQSPI_CS1    92
-#define MCFQSPI_CS2    103
-#define MCFQSPI_CS3    99
-
-static int m523x_cs_setup(struct mcfqspi_cs_control *cs_control)
-{
-        int status;
-
-        status = gpio_request(MCFQSPI_CS0, "MCFQSPI_CS0");
-        if (status) {
-                pr_debug("gpio_request for MCFQSPI_CS0 failed\n");
-                goto fail0;
-        }
-        status = gpio_direction_output(MCFQSPI_CS0, 1);
-        if (status) {
-                pr_debug("gpio_direction_output for MCFQSPI_CS0 failed\n");
-                goto fail1;
-        }
-
-        status = gpio_request(MCFQSPI_CS1, "MCFQSPI_CS1");
-        if (status) {
-                pr_debug("gpio_request for MCFQSPI_CS1 failed\n");
-                goto fail1;
-        }
-        status = gpio_direction_output(MCFQSPI_CS1, 1);
-        if (status) {
-                pr_debug("gpio_direction_output for MCFQSPI_CS1 failed\n");
-                goto fail2;
-        }
-
-        status = gpio_request(MCFQSPI_CS2, "MCFQSPI_CS2");
-        if (status) {
-                pr_debug("gpio_request for MCFQSPI_CS2 failed\n");
-                goto fail2;
-        }
-        status = gpio_direction_output(MCFQSPI_CS2, 1);
-        if (status) {
-                pr_debug("gpio_direction_output for MCFQSPI_CS2 failed\n");
-                goto fail3;
-        }
-
-        status = gpio_request(MCFQSPI_CS3, "MCFQSPI_CS3");
-        if (status) {
-                pr_debug("gpio_request for MCFQSPI_CS3 failed\n");
-                goto fail3;
-        }
-        status = gpio_direction_output(MCFQSPI_CS3, 1);
-        if (status) {
-                pr_debug("gpio_direction_output for MCFQSPI_CS3 failed\n");
-                goto fail4;
-        }
-
-        return 0;
-
-fail4:
-        gpio_free(MCFQSPI_CS3);
-fail3:
-        gpio_free(MCFQSPI_CS2);
-fail2:
-        gpio_free(MCFQSPI_CS1);
-fail1:
-        gpio_free(MCFQSPI_CS0);
-fail0:
-        return status;
-}
-
-static void m523x_cs_teardown(struct mcfqspi_cs_control *cs_control)
-{
-        gpio_free(MCFQSPI_CS3);
-        gpio_free(MCFQSPI_CS2);
-        gpio_free(MCFQSPI_CS1);
-        gpio_free(MCFQSPI_CS0);
-}
-
-static void m523x_cs_select(struct mcfqspi_cs_control *cs_control,
-                            u8 chip_select, bool cs_high)
-{
-        switch (chip_select) {
-        case 0:
-                gpio_set_value(MCFQSPI_CS0, cs_high);
-                break;
-        case 1:
-                gpio_set_value(MCFQSPI_CS1, cs_high);
-                break;
-        case 2:
-                gpio_set_value(MCFQSPI_CS2, cs_high);
-                break;
-        case 3:
-                gpio_set_value(MCFQSPI_CS3, cs_high);
-                break;
-        }
-}
-
-static void m523x_cs_deselect(struct mcfqspi_cs_control *cs_control,
-                              u8 chip_select, bool cs_high)
-{
-        switch (chip_select) {
-        case 0:
-                gpio_set_value(MCFQSPI_CS0, !cs_high);
-                break;
-        case 1:
-                gpio_set_value(MCFQSPI_CS1, !cs_high);
-                break;
-        case 2:
-                gpio_set_value(MCFQSPI_CS2, !cs_high);
-                break;
-        case 3:
-                gpio_set_value(MCFQSPI_CS3, !cs_high);
-                break;
-        }
-}
-
-static struct mcfqspi_cs_control m523x_cs_control = {
-        .setup                  = m523x_cs_setup,
-        .teardown               = m523x_cs_teardown,
-        .select                 = m523x_cs_select,
-        .deselect               = m523x_cs_deselect,
-};
-
-static struct mcfqspi_platform_data m523x_qspi_data = {
-        .bus_num                = 0,
-        .num_chipselect         = 4,
-        .cs_control             = &m523x_cs_control,
-};
-
-static struct platform_device m523x_qspi = {
-        .name                   = "mcfqspi",
-        .id                     = 0,
-        .num_resources          = ARRAY_SIZE(m523x_qspi_resources),
-        .resource               = m523x_qspi_resources,
-        .dev.platform_data      = &m523x_qspi_data,
-};
+#ifdef CONFIG_SPI_COLDFIRE_QSPI
 
 static void __init m523x_qspi_init(void)
 {
@@ -237,15 +35,8 @@ static void __init m523x_qspi_init(void)
         par &= 0x3f3f;
         writew(par, MCFGPIO_PAR_TIMER);
 }
-#endif /* defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE) */
 
-static struct platform_device *m523x_devices[] __initdata = {
-        &m523x_uart,
-        &m523x_fec,
-#if defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE)
-        &m523x_qspi,
-#endif
-};
+#endif /* CONFIG_SPI_COLDFIRE_QSPI */
 
 /***************************************************************************/
 
@@ -263,31 +54,13 @@ static void __init m523x_fec_init(void)
 
 /***************************************************************************/
 
-static void m523x_cpu_reset(void)
-{
-        local_irq_disable();
-        __raw_writeb(MCF_RCR_SWRESET, MCF_IPSBAR + MCF_RCR);
-}
-
-/***************************************************************************/
-
 void __init config_BSP(char *commandp, int size)
 {
-        mach_reset = m523x_cpu_reset;
-}
-
-/***************************************************************************/
-
-static int __init init_BSP(void)
-{
+        mach_sched_init = hw_timer_init;
         m523x_fec_init();
-#if defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE)
+#ifdef CONFIG_SPI_COLDFIRE_QSPI
         m523x_qspi_init();
 #endif
-        platform_add_devices(m523x_devices, ARRAY_SIZE(m523x_devices));
-        return 0;
 }
 
-arch_initcall(init_BSP);
-
 /***************************************************************************/
diff --git a/arch/m68k/platform/5249/config.c b/arch/m68k/platform/5249/config.c
index ceb31e5744a..bbf05135bb9 100644
--- a/arch/m68k/platform/5249/config.c
+++ b/arch/m68k/platform/5249/config.c
@@ -12,34 +12,13 @@
 #include <linux/param.h>
 #include <linux/init.h>
 #include <linux/io.h>
-#include <linux/spi/spi.h>
-#include <linux/gpio.h>
+#include <linux/platform_device.h>
 #include <asm/machdep.h>
 #include <asm/coldfire.h>
 #include <asm/mcfsim.h>
-#include <asm/mcfuart.h>
-#include <asm/mcfqspi.h>
 
 /***************************************************************************/
 
-static struct mcf_platform_uart m5249_uart_platform[] = {
-        {
-                .mapbase        = MCF_MBAR + MCFUART_BASE1,
-                .irq            = 73,
-        },
-        {
-                .mapbase        = MCF_MBAR + MCFUART_BASE2,
-                .irq            = 74,
-        },
-        { },
-};
-
-static struct platform_device m5249_uart = {
-        .name                   = "mcfuart",
-        .id                     = 0,
-        .dev.platform_data      = m5249_uart_platform,
-};
-
 #ifdef CONFIG_M5249C3
 
 static struct resource m5249_smc91x_resources[] = {
@@ -64,153 +43,15 @@ static struct platform_device m5249_smc91x = {
 
 #endif /* CONFIG_M5249C3 */
 
-#if defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE)
-static struct resource m5249_qspi_resources[] = {
-        {
-                .start          = MCFQSPI_IOBASE,
-                .end            = MCFQSPI_IOBASE + MCFQSPI_IOSIZE - 1,
-                .flags          = IORESOURCE_MEM,
-        },
-        {
-                .start          = MCF_IRQ_QSPI,
-                .end            = MCF_IRQ_QSPI,
-                .flags          = IORESOURCE_IRQ,
-        },
-};
-
-#define MCFQSPI_CS0    29
-#define MCFQSPI_CS1    24
-#define MCFQSPI_CS2    21
-#define MCFQSPI_CS3    22
-
-static int m5249_cs_setup(struct mcfqspi_cs_control *cs_control)
-{
-        int status;
-
-        status = gpio_request(MCFQSPI_CS0, "MCFQSPI_CS0");
-        if (status) {
-                pr_debug("gpio_request for MCFQSPI_CS0 failed\n");
-                goto fail0;
-        }
-        status = gpio_direction_output(MCFQSPI_CS0, 1);
-        if (status) {
-                pr_debug("gpio_direction_output for MCFQSPI_CS0 failed\n");
-                goto fail1;
-        }
-
-        status = gpio_request(MCFQSPI_CS1, "MCFQSPI_CS1");
-        if (status) {
-                pr_debug("gpio_request for MCFQSPI_CS1 failed\n");
-                goto fail1;
-        }
-        status = gpio_direction_output(MCFQSPI_CS1, 1);
-        if (status) {
-                pr_debug("gpio_direction_output for MCFQSPI_CS1 failed\n");
-                goto fail2;
-        }
-
-        status = gpio_request(MCFQSPI_CS2, "MCFQSPI_CS2");
-        if (status) {
-                pr_debug("gpio_request for MCFQSPI_CS2 failed\n");
-                goto fail2;
-        }
-        status = gpio_direction_output(MCFQSPI_CS2, 1);
-        if (status) {
-                pr_debug("gpio_direction_output for MCFQSPI_CS2 failed\n");
-                goto fail3;
-        }
-
-        status = gpio_request(MCFQSPI_CS3, "MCFQSPI_CS3");
-        if (status) {
-                pr_debug("gpio_request for MCFQSPI_CS3 failed\n");
-                goto fail3;
-        }
-        status = gpio_direction_output(MCFQSPI_CS3, 1);
-        if (status) {
-                pr_debug("gpio_direction_output for MCFQSPI_CS3 failed\n");
-                goto fail4;
-        }
-
-        return 0;
-
-fail4:
-        gpio_free(MCFQSPI_CS3);
-fail3:
-        gpio_free(MCFQSPI_CS2);
-fail2:
-        gpio_free(MCFQSPI_CS1);
-fail1:
-        gpio_free(MCFQSPI_CS0);
-fail0:
-        return status;
-}
-
-static void m5249_cs_teardown(struct mcfqspi_cs_control *cs_control)
-{
-        gpio_free(MCFQSPI_CS3);
-        gpio_free(MCFQSPI_CS2);
-        gpio_free(MCFQSPI_CS1);
-        gpio_free(MCFQSPI_CS0);
-}
-
-static void m5249_cs_select(struct mcfqspi_cs_control *cs_control,
-                            u8 chip_select, bool cs_high)
-{
-        switch (chip_select) {
-        case 0:
-                gpio_set_value(MCFQSPI_CS0, cs_high);
-                break;
-        case 1:
-                gpio_set_value(MCFQSPI_CS1, cs_high);
-                break;
-        case 2:
-                gpio_set_value(MCFQSPI_CS2, cs_high);
-                break;
-        case 3:
-                gpio_set_value(MCFQSPI_CS3, cs_high);
-                break;
-        }
-}
-
-static void m5249_cs_deselect(struct mcfqspi_cs_control *cs_control,
-                              u8 chip_select, bool cs_high)
-{
-        switch (chip_select) {
-        case 0:
-                gpio_set_value(MCFQSPI_CS0, !cs_high);
-                break;
-        case 1:
-                gpio_set_value(MCFQSPI_CS1, !cs_high);
-                break;
-        case 2:
-                gpio_set_value(MCFQSPI_CS2, !cs_high);
-                break;
-        case 3:
-                gpio_set_value(MCFQSPI_CS3, !cs_high);
-                break;
-        }
-}
-
-static struct mcfqspi_cs_control m5249_cs_control = {
-        .setup                  = m5249_cs_setup,
-        .teardown               = m5249_cs_teardown,
-        .select                 = m5249_cs_select,
-        .deselect               = m5249_cs_deselect,
+static struct platform_device *m5249_devices[] __initdata = {
+#ifdef CONFIG_M5249C3
+        &m5249_smc91x,
+#endif
 };
 
-static struct mcfqspi_platform_data m5249_qspi_data = {
-        .bus_num                = 0,
-        .num_chipselect         = 4,
-        .cs_control             = &m5249_cs_control,
-};
+/***************************************************************************/
 
-static struct platform_device m5249_qspi = {
-        .name                   = "mcfqspi",
-        .id                     = 0,
-        .num_resources          = ARRAY_SIZE(m5249_qspi_resources),
-        .resource               = m5249_qspi_resources,
-        .dev.platform_data      = &m5249_qspi_data,
-};
+#ifdef CONFIG_SPI_COLDFIRE_QSPI
 
 static void __init m5249_qspi_init(void)
 {
@@ -219,42 +60,8 @@ static void __init m5249_qspi_init(void)
                MCF_MBAR + MCFSIM_QSPIICR);
         mcf_mapirq2imr(MCF_IRQ_QSPI, MCFINTC_QSPI);
 }
-#endif /* defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE) */
 
-
-static struct platform_device *m5249_devices[] __initdata = {
-        &m5249_uart,
-#ifdef CONFIG_M5249C3
-        &m5249_smc91x,
-#endif
-#if defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE)
-        &m5249_qspi,
-#endif
-};
-
-/***************************************************************************/
-
-static void __init m5249_uart_init_line(int line, int irq)
-{
-        if (line == 0) {
-                writeb(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI1, MCF_MBAR + MCFSIM_UART1ICR);
-                writeb(irq, MCF_MBAR + MCFUART_BASE1 + MCFUART_UIVR);
-                mcf_mapirq2imr(irq, MCFINTC_UART0);
-        } else if (line == 1) {
-                writeb(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI2, MCF_MBAR + MCFSIM_UART2ICR);
-                writeb(irq, MCF_MBAR + MCFUART_BASE2 + MCFUART_UIVR);
-                mcf_mapirq2imr(irq, MCFINTC_UART1);
-        }
-}
-
-static void __init m5249_uarts_init(void)
-{
-        const int nrlines = ARRAY_SIZE(m5249_uart_platform);
-        int line;
-
-        for (line = 0; (line < nrlines); line++)
-                m5249_uart_init_line(line, m5249_uart_platform[line].irq);
-}
+#endif /* CONFIG_SPI_COLDFIRE_QSPI */
 
 /***************************************************************************/
 
@@ -276,43 +83,14 @@ static void __init m5249_smc91x_init(void)
 
 /***************************************************************************/
 
-static void __init m5249_timers_init(void)
-{
-        /* Timer1 is always used as system timer */
-        writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI3,
-                MCF_MBAR + MCFSIM_TIMER1ICR);
-        mcf_mapirq2imr(MCF_IRQ_TIMER, MCFINTC_TIMER1);
-
-#ifdef CONFIG_HIGHPROFILE
-        /* Timer2 is to be used as a high speed profile timer  */
-        writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL7 | MCFSIM_ICR_PRI3,
-                MCF_MBAR + MCFSIM_TIMER2ICR);
-        mcf_mapirq2imr(MCF_IRQ_PROFILER, MCFINTC_TIMER2);
-#endif
-}
-
-/***************************************************************************/
-
-void m5249_cpu_reset(void)
-{
-        local_irq_disable();
-        /* Set watchdog to soft reset, and enabled */
-        __raw_writeb(0xc0, MCF_MBAR + MCFSIM_SYPCR);
-        for (;;)
-                /* wait for watchdog to timeout */;
-}
-
-/***************************************************************************/
-
 void __init config_BSP(char *commandp, int size)
 {
-        mach_reset = m5249_cpu_reset;
-        m5249_timers_init();
-        m5249_uarts_init();
+        mach_sched_init = hw_timer_init;
+
 #ifdef CONFIG_M5249C3
         m5249_smc91x_init();
 #endif
-#if defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE)
+#ifdef CONFIG_SPI_COLDFIRE_QSPI
         m5249_qspi_init();
 #endif
 }
diff --git a/arch/m68k/platform/5272/config.c b/arch/m68k/platform/5272/config.c
index 65bb582734e..e68bc7a148e 100644
--- a/arch/m68k/platform/5272/config.c
+++ b/arch/m68k/platform/5272/config.c
@@ -30,84 +30,18 @@ unsigned char ledbank = 0xff;
 
 /***************************************************************************/
 
-static struct mcf_platform_uart m5272_uart_platform[] = {
-        {
-                .mapbase        = MCF_MBAR + MCFUART_BASE1,
-                .irq            = MCF_IRQ_UART1,
-        },
-        {
-                .mapbase        = MCF_MBAR + MCFUART_BASE2,
-                .irq            = MCF_IRQ_UART2,
-        },
-        { },
-};
-
-static struct platform_device m5272_uart = {
-        .name                   = "mcfuart",
-        .id                     = 0,
-        .dev.platform_data      = m5272_uart_platform,
-};
-
-static struct resource m5272_fec_resources[] = {
-        {
-                .start          = MCF_MBAR + 0x840,
-                .end            = MCF_MBAR + 0x840 + 0x1cf,
-                .flags          = IORESOURCE_MEM,
-        },
-        {
-                .start          = MCF_IRQ_ERX,
-                .end            = MCF_IRQ_ERX,
-                .flags          = IORESOURCE_IRQ,
-        },
-        {
-                .start          = MCF_IRQ_ETX,
-                .end            = MCF_IRQ_ETX,
-                .flags          = IORESOURCE_IRQ,
-        },
-        {
-                .start          = MCF_IRQ_ENTC,
-                .end            = MCF_IRQ_ENTC,
-                .flags          = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device m5272_fec = {
-        .name                   = "fec",
-        .id                     = 0,
-        .num_resources          = ARRAY_SIZE(m5272_fec_resources),
-        .resource               = m5272_fec_resources,
-};
-
-static struct platform_device *m5272_devices[] __initdata = {
-        &m5272_uart,
-        &m5272_fec,
-};
-
-/***************************************************************************/
-
-static void __init m5272_uart_init_line(int line, int irq)
+static void __init m5272_uarts_init(void)
 {
         u32 v;
 
-        if ((line >= 0) && (line < 2)) {
-                /* Enable the output lines for the serial ports */
-                v = readl(MCF_MBAR + MCFSIM_PBCNT);
-                v = (v & ~0x000000ff) | 0x00000055;
-                writel(v, MCF_MBAR + MCFSIM_PBCNT);
-
-                v = readl(MCF_MBAR + MCFSIM_PDCNT);
-                v = (v & ~0x000003fc) | 0x000002a8;
-                writel(v, MCF_MBAR + MCFSIM_PDCNT);
-        }
-}
-
-static void __init m5272_uarts_init(void)
-{
-        const int nrlines = ARRAY_SIZE(m5272_uart_platform);
-        int line;
+        /* Enable the output lines for the serial ports */
+        v = readl(MCF_MBAR + MCFSIM_PBCNT);
+        v = (v & ~0x000000ff) | 0x00000055;
+        writel(v, MCF_MBAR + MCFSIM_PBCNT);
 
-        for (line = 0; (line < nrlines); line++)
-                m5272_uart_init_line(line, m5272_uart_platform[line].irq);
+        v = readl(MCF_MBAR + MCFSIM_PDCNT);
+        v = (v & ~0x000003fc) | 0x000002a8;
+        writel(v, MCF_MBAR + MCFSIM_PDCNT);
 }
 
 /***************************************************************************/
@@ -146,6 +80,7 @@ void __init config_BSP(char *commandp, int size)
 #endif
 
         mach_reset = m5272_cpu_reset;
+        mach_sched_init = hw_timer_init;
 }
 
 /***************************************************************************/
@@ -167,7 +102,6 @@ static int __init init_BSP(void)
 {
         m5272_uarts_init();
         fixed_phy_add(PHY_POLL, 0, &nettel_fixed_phy_status);
-        platform_add_devices(m5272_devices, ARRAY_SIZE(m5272_devices));
         return 0;
 }
 
diff --git a/arch/m68k/platform/527x/config.c b/arch/m68k/platform/527x/config.c
index 3ebc769cefd..7ed848c3b84 100644
--- a/arch/m68k/platform/527x/config.c
+++ b/arch/m68k/platform/527x/config.c
@@ -16,253 +16,14 @@
 #include <linux/param.h>
 #include <linux/init.h>
 #include <linux/io.h>
-#include <linux/spi/spi.h>
-#include <linux/gpio.h>
 #include <asm/machdep.h>
 #include <asm/coldfire.h>
 #include <asm/mcfsim.h>
 #include <asm/mcfuart.h>
-#include <asm/mcfqspi.h>
 
 /***************************************************************************/
 
-static struct mcf_platform_uart m527x_uart_platform[] = {
-        {
-                .mapbase        = MCFUART_BASE1,
-                .irq            = MCFINT_VECBASE + MCFINT_UART0,
-        },
-        {
-                .mapbase        = MCFUART_BASE2,
-                .irq            = MCFINT_VECBASE + MCFINT_UART1,
-        },
-        {
-                .mapbase        = MCFUART_BASE3,
-                .irq            = MCFINT_VECBASE + MCFINT_UART2,
-        },
-        { },
-};
-
-static struct platform_device m527x_uart = {
-        .name                   = "mcfuart",
-        .id                     = 0,
-        .dev.platform_data      = m527x_uart_platform,
-};
-
-static struct resource m527x_fec0_resources[] = {
-        {
-                .start          = MCFFEC_BASE0,
-                .end            = MCFFEC_BASE0 + MCFFEC_SIZE0 - 1,
-                .flags          = IORESOURCE_MEM,
-        },
-        {
-                .start          = 64 + 23,
-                .end            = 64 + 23,
-                .flags          = IORESOURCE_IRQ,
-        },
-        {
-                .start          = 64 + 27,
-                .end            = 64 + 27,
-                .flags          = IORESOURCE_IRQ,
-        },
-        {
-                .start          = 64 + 29,
-                .end            = 64 + 29,
-                .flags          = IORESOURCE_IRQ,
-        },
-};
-
-static struct resource m527x_fec1_resources[] = {
-        {
-                .start          = MCFFEC_BASE1,
-                .end            = MCFFEC_BASE1 + MCFFEC_SIZE1 - 1,
-                .flags          = IORESOURCE_MEM,
-        },
-        {
-                .start          = 128 + 23,
-                .end            = 128 + 23,
-                .flags          = IORESOURCE_IRQ,
-        },
-        {
-                .start          = 128 + 27,
-                .end            = 128 + 27,
-                .flags          = IORESOURCE_IRQ,
-        },
-        {
-                .start          = 128 + 29,
-                .end            = 128 + 29,
-                .flags          = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device m527x_fec[] = {
-        {
-                .name           = "fec",
-                .id             = 0,
-                .num_resources  = ARRAY_SIZE(m527x_fec0_resources),
-                .resource       = m527x_fec0_resources,
-        },
-        {
-                .name           = "fec",
-                .id             = 1,
-                .num_resources  = ARRAY_SIZE(m527x_fec1_resources),
-                .resource       = m527x_fec1_resources,
-        },
-};
-
-#if defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE)
-static struct resource m527x_qspi_resources[] = {
-        {
-                .start          = MCFQSPI_IOBASE,
-                .end            = MCFQSPI_IOBASE + MCFQSPI_IOSIZE - 1,
-                .flags          = IORESOURCE_MEM,
-        },
-        {
-                .start          = MCFINT_VECBASE + MCFINT_QSPI,
-                .end            = MCFINT_VECBASE + MCFINT_QSPI,
-                .flags          = IORESOURCE_IRQ,
-        },
-};
-
-#if defined(CONFIG_M5271)
-#define MCFQSPI_CS0    91
-#define MCFQSPI_CS1    92
-#define MCFQSPI_CS2    99
-#define MCFQSPI_CS3    103
-#elif defined(CONFIG_M5275)
-#define MCFQSPI_CS0    59
-#define MCFQSPI_CS1    60
-#define MCFQSPI_CS2    61
-#define MCFQSPI_CS3    62
-#endif
-
-static int m527x_cs_setup(struct mcfqspi_cs_control *cs_control)
-{
-        int status;
-
-        status = gpio_request(MCFQSPI_CS0, "MCFQSPI_CS0");
-        if (status) {
-                pr_debug("gpio_request for MCFQSPI_CS0 failed\n");
-                goto fail0;
-        }
-        status = gpio_direction_output(MCFQSPI_CS0, 1);
-        if (status) {
-                pr_debug("gpio_direction_output for MCFQSPI_CS0 failed\n");
-                goto fail1;
-        }
-
-        status = gpio_request(MCFQSPI_CS1, "MCFQSPI_CS1");
-        if (status) {
-                pr_debug("gpio_request for MCFQSPI_CS1 failed\n");
-                goto fail1;
-        }
-        status = gpio_direction_output(MCFQSPI_CS1, 1);
-        if (status) {
-                pr_debug("gpio_direction_output for MCFQSPI_CS1 failed\n");
-                goto fail2;
-        }
-
-        status = gpio_request(MCFQSPI_CS2, "MCFQSPI_CS2");
-        if (status) {
-                pr_debug("gpio_request for MCFQSPI_CS2 failed\n");
-                goto fail2;
-        }
-        status = gpio_direction_output(MCFQSPI_CS2, 1);
-        if (status) {
-                pr_debug("gpio_direction_output for MCFQSPI_CS2 failed\n");
-                goto fail3;
-        }
-
-        status = gpio_request(MCFQSPI_CS3, "MCFQSPI_CS3");
-        if (status) {
-                pr_debug("gpio_request for MCFQSPI_CS3 failed\n");
-                goto fail3;
-        }
-        status = gpio_direction_output(MCFQSPI_CS3, 1);
-        if (status) {
-                pr_debug("gpio_direction_output for MCFQSPI_CS3 failed\n");
-                goto fail4;
-        }
-
-        return 0;
-
-fail4:
-        gpio_free(MCFQSPI_CS3);
-fail3:
-        gpio_free(MCFQSPI_CS2);
-fail2:
-        gpio_free(MCFQSPI_CS1);
-fail1:
-        gpio_free(MCFQSPI_CS0);
-fail0:
-        return status;
-}
-
-static void m527x_cs_teardown(struct mcfqspi_cs_control *cs_control)
-{
-        gpio_free(MCFQSPI_CS3);
-        gpio_free(MCFQSPI_CS2);
-        gpio_free(MCFQSPI_CS1);
-        gpio_free(MCFQSPI_CS0);
-}
-
-static void m527x_cs_select(struct mcfqspi_cs_control *cs_control,
-                            u8 chip_select, bool cs_high)
-{
-        switch (chip_select) {
-        case 0:
-                gpio_set_value(MCFQSPI_CS0, cs_high);
-                break;
-        case 1:
-                gpio_set_value(MCFQSPI_CS1, cs_high);
-                break;
-        case 2:
-                gpio_set_value(MCFQSPI_CS2, cs_high);
-                break;
-        case 3:
-                gpio_set_value(MCFQSPI_CS3, cs_high);
-                break;
-        }
-}
-
-static void m527x_cs_deselect(struct mcfqspi_cs_control *cs_control,
-                              u8 chip_select, bool cs_high)
-{
-        switch (chip_select) {
-        case 0:
-                gpio_set_value(MCFQSPI_CS0, !cs_high);
-                break;
-        case 1:
-                gpio_set_value(MCFQSPI_CS1, !cs_high);
-                break;
-        case 2:
-                gpio_set_value(MCFQSPI_CS2, !cs_high);
-                break;
-        case 3:
-                gpio_set_value(MCFQSPI_CS3, !cs_high);
-                break;
-        }
-}
-
-static struct mcfqspi_cs_control m527x_cs_control = {
-        .setup                  = m527x_cs_setup,
-        .teardown               = m527x_cs_teardown,
-        .select                 = m527x_cs_select,
-        .deselect               = m527x_cs_deselect,
-};
-
-static struct mcfqspi_platform_data m527x_qspi_data = {
-        .bus_num                = 0,
-        .num_chipselect         = 4,
-        .cs_control             = &m527x_cs_control,
-};
-
-static struct platform_device m527x_qspi = {
-        .name                   = "mcfqspi",
-        .id                     = 0,
-        .num_resources          = ARRAY_SIZE(m527x_qspi_resources),
-        .resource               = m527x_qspi_resources,
-        .dev.platform_data      = &m527x_qspi_data,
-};
+#ifdef CONFIG_SPI_COLDFIRE_QSPI
 
 static void __init m527x_qspi_init(void)
 {
@@ -280,50 +41,23 @@ static void __init m527x_qspi_init(void)
         writew(0x003e, MCFGPIO_PAR_QSPI);
 #endif
 }
-#endif /* defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE) */
 
-static struct platform_device *m527x_devices[] __initdata = {
-        &m527x_uart,
-        &m527x_fec[0],
-#ifdef CONFIG_FEC2
-        &m527x_fec[1],
-#endif
-#if defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE)
-        &m527x_qspi,
-#endif
-};
+#endif /* CONFIG_SPI_COLDFIRE_QSPI */
 
 /***************************************************************************/
 
-static void __init m527x_uart_init_line(int line, int irq)
+static void __init m527x_uarts_init(void)
 {
         u16 sepmask;
 
-        if ((line < 0) || (line > 2))
-                return;
-
         /*
          * External Pin Mask Setting & Enable External Pin for Interface
          */
         sepmask = readw(MCF_IPSBAR + MCF_GPIO_PAR_UART);
-        if (line == 0)
-                sepmask |= UART0_ENABLE_MASK;
-        else if (line == 1)
-                sepmask |= UART1_ENABLE_MASK;
-        else if (line == 2)
-                sepmask |= UART2_ENABLE_MASK;
+        sepmask |= UART0_ENABLE_MASK | UART1_ENABLE_MASK | UART2_ENABLE_MASK;
         writew(sepmask, MCF_IPSBAR + MCF_GPIO_PAR_UART);
 }
 
-static void __init m527x_uarts_init(void)
-{
-        const int nrlines = ARRAY_SIZE(m527x_uart_platform);
-        int line;
-
-        for (line = 0; (line < nrlines); line++)
-                m527x_uart_init_line(line, m527x_uart_platform[line].irq);
-}
-
 /***************************************************************************/
 
 static void __init m527x_fec_init(void)
@@ -353,32 +87,14 @@ static void __init m527x_fec_init(void)
 
 /***************************************************************************/
 
-static void m527x_cpu_reset(void)
-{
-        local_irq_disable();
-        __raw_writeb(MCF_RCR_SWRESET, MCF_IPSBAR + MCF_RCR);
-}
-
-/***************************************************************************/
-
 void __init config_BSP(char *commandp, int size)
 {
-        mach_reset = m527x_cpu_reset;
+        mach_sched_init = hw_timer_init;
         m527x_uarts_init();
         m527x_fec_init();
-#if defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE)
+#ifdef CONFIG_SPI_COLDFIRE_QSPI
         m527x_qspi_init();
 #endif
 }
 
 /***************************************************************************/
-
-static int __init init_BSP(void)
-{
-        platform_add_devices(m527x_devices, ARRAY_SIZE(m527x_devices));
-        return 0;
-}
-
-arch_initcall(init_BSP);
-
-/***************************************************************************/
diff --git a/arch/m68k/platform/528x/config.c b/arch/m68k/platform/528x/config.c
index 7abe77a2f3e..d4492926614 100644
--- a/arch/m68k/platform/528x/config.c
+++ b/arch/m68k/platform/528x/config.c
@@ -17,229 +17,33 @@
 #include <linux/init.h>
 #include <linux/platform_device.h>
 #include <linux/io.h>
-#include <linux/spi/spi.h>
-#include <linux/gpio.h>
 #include <asm/machdep.h>
 #include <asm/coldfire.h>
 #include <asm/mcfsim.h>
 #include <asm/mcfuart.h>
-#include <asm/mcfqspi.h>
 
 /***************************************************************************/
 
-static struct mcf_platform_uart m528x_uart_platform[] = {
-        {
-                .mapbase        = MCFUART_BASE1,
-                .irq            = MCFINT_VECBASE + MCFINT_UART0,
-        },
-        {
-                .mapbase        = MCFUART_BASE2,
-                .irq            = MCFINT_VECBASE + MCFINT_UART0 + 1,
-        },
-        {
-                .mapbase        = MCFUART_BASE3,
-                .irq            = MCFINT_VECBASE + MCFINT_UART0 + 2,
-        },
-        { },
-};
-
-static struct platform_device m528x_uart = {
-        .name                   = "mcfuart",
-        .id                     = 0,
-        .dev.platform_data      = m528x_uart_platform,
-};
-
-static struct resource m528x_fec_resources[] = {
-        {
-                .start          = MCFFEC_BASE,
-                .end            = MCFFEC_BASE + MCFFEC_SIZE - 1,
-                .flags          = IORESOURCE_MEM,
-        },
-        {
-                .start          = 64 + 23,
-                .end            = 64 + 23,
-                .flags          = IORESOURCE_IRQ,
-        },
-        {
-                .start          = 64 + 27,
-                .end            = 64 + 27,
-                .flags          = IORESOURCE_IRQ,
-        },
-        {
-                .start          = 64 + 29,
-                .end            = 64 + 29,
-                .flags          = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device m528x_fec = {
-        .name                   = "fec",
-        .id                     = 0,
-        .num_resources          = ARRAY_SIZE(m528x_fec_resources),
-        .resource               = m528x_fec_resources,
-};
-
-#if defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE)
-static struct resource m528x_qspi_resources[] = {
-        {
-                .start          = MCFQSPI_IOBASE,
-                .end            = MCFQSPI_IOBASE + MCFQSPI_IOSIZE - 1,
-                .flags          = IORESOURCE_MEM,
-        },
-        {
-                .start          = MCFINT_VECBASE + MCFINT_QSPI,
-                .end            = MCFINT_VECBASE + MCFINT_QSPI,
-                .flags          = IORESOURCE_IRQ,
-        },
-};
-
-#define MCFQSPI_CS0    147
-#define MCFQSPI_CS1    148
-#define MCFQSPI_CS2    149
-#define MCFQSPI_CS3    150
-
-static int m528x_cs_setup(struct mcfqspi_cs_control *cs_control)
-{
-        int status;
-
-        status = gpio_request(MCFQSPI_CS0, "MCFQSPI_CS0");
-        if (status) {
-                pr_debug("gpio_request for MCFQSPI_CS0 failed\n");
-                goto fail0;
-        }
-        status = gpio_direction_output(MCFQSPI_CS0, 1);
-        if (status) {
-                pr_debug("gpio_direction_output for MCFQSPI_CS0 failed\n");
-                goto fail1;
-        }
-
-        status = gpio_request(MCFQSPI_CS1, "MCFQSPI_CS1");
-        if (status) {
-                pr_debug("gpio_request for MCFQSPI_CS1 failed\n");
-                goto fail1;
-        }
-        status = gpio_direction_output(MCFQSPI_CS1, 1);
-        if (status) {
-                pr_debug("gpio_direction_output for MCFQSPI_CS1 failed\n");
-                goto fail2;
-        }
-
-        status = gpio_request(MCFQSPI_CS2, "MCFQSPI_CS2");
-        if (status) {
-                pr_debug("gpio_request for MCFQSPI_CS2 failed\n");
-                goto fail2;
-        }
-        status = gpio_direction_output(MCFQSPI_CS2, 1);
-        if (status) {
-                pr_debug("gpio_direction_output for MCFQSPI_CS2 failed\n");
-                goto fail3;
-        }
-
-        status = gpio_request(MCFQSPI_CS3, "MCFQSPI_CS3");
-        if (status) {
-                pr_debug("gpio_request for MCFQSPI_CS3 failed\n");
-                goto fail3;
-        }
-        status = gpio_direction_output(MCFQSPI_CS3, 1);
-        if (status) {
-                pr_debug("gpio_direction_output for MCFQSPI_CS3 failed\n");
-                goto fail4;
-        }
-
-        return 0;
-
-fail4:
-        gpio_free(MCFQSPI_CS3);
-fail3:
-        gpio_free(MCFQSPI_CS2);
-fail2:
-        gpio_free(MCFQSPI_CS1);
-fail1:
-        gpio_free(MCFQSPI_CS0);
-fail0:
-        return status;
-}
-
-static void m528x_cs_teardown(struct mcfqspi_cs_control *cs_control)
-{
-        gpio_free(MCFQSPI_CS3);
-        gpio_free(MCFQSPI_CS2);
-        gpio_free(MCFQSPI_CS1);
-        gpio_free(MCFQSPI_CS0);
-}
-
-static void m528x_cs_select(struct mcfqspi_cs_control *cs_control,
-                            u8 chip_select, bool cs_high)
-{
-        gpio_set_value(MCFQSPI_CS0 + chip_select, cs_high);
-}
-
-static void m528x_cs_deselect(struct mcfqspi_cs_control *cs_control,
-                              u8 chip_select, bool cs_high)
-{
-        gpio_set_value(MCFQSPI_CS0 + chip_select, !cs_high);
-}
-
-static struct mcfqspi_cs_control m528x_cs_control = {
-        .setup                  = m528x_cs_setup,
-        .teardown               = m528x_cs_teardown,
-        .select                 = m528x_cs_select,
-        .deselect               = m528x_cs_deselect,
-};
-
-static struct mcfqspi_platform_data m528x_qspi_data = {
-        .bus_num                = 0,
-        .num_chipselect         = 4,
-        .cs_control             = &m528x_cs_control,
-};
-
-static struct platform_device m528x_qspi = {
-        .name                   = "mcfqspi",
-        .id                     = 0,
-        .num_resources          = ARRAY_SIZE(m528x_qspi_resources),
-        .resource               = m528x_qspi_resources,
-        .dev.platform_data      = &m528x_qspi_data,
-};
+#ifdef CONFIG_SPI_COLDFIRE_QSPI
 
 static void __init m528x_qspi_init(void)
 {
         /* setup Port QS for QSPI with gpio CS control */
         __raw_writeb(0x07, MCFGPIO_PQSPAR);
 }
-#endif /* defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE) */
 
-static struct platform_device *m528x_devices[] __initdata = {
-        &m528x_uart,
-        &m528x_fec,
-#if defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE)
-        &m528x_qspi,
-#endif
-};
+#endif /* CONFIG_SPI_COLDFIRE_QSPI */
 
 /***************************************************************************/
 
-static void __init m528x_uart_init_line(int line, int irq)
+static void __init m528x_uarts_init(void)
 {
         u8 port;
 
-        if ((line < 0) || (line > 2))
-                return;
-
         /* make sure PUAPAR is set for UART0 and UART1 */
-        if (line < 2) {
-                port = readb(MCF5282_GPIO_PUAPAR);
-                port |= (0x03 << (line * 2));
-                writeb(port, MCF5282_GPIO_PUAPAR);
-        }
-}
-
-static void __init m528x_uarts_init(void)
-{
-        const int nrlines = ARRAY_SIZE(m528x_uart_platform);
-        int line;
-
-        for (line = 0; (line < nrlines); line++)
-                m528x_uart_init_line(line, m528x_uart_platform[line].irq);
+        port = readb(MCF5282_GPIO_PUAPAR);
+        port |= 0x03 | (0x03 << 2);
+        writeb(port, MCF5282_GPIO_PUAPAR);
 }
 
 /***************************************************************************/
@@ -256,14 +60,6 @@ static void __init m528x_fec_init(void)
 
 /***************************************************************************/
 
-static void m528x_cpu_reset(void)
-{
-        local_irq_disable();
-        __raw_writeb(MCF_RCR_SWRESET, MCF_IPSBAR + MCF_RCR);
-}
-
-/***************************************************************************/
-
 #ifdef CONFIG_WILDFIRE
 void wildfire_halt(void)
 {
@@ -299,22 +95,12 @@ void __init config_BSP(char *commandp, int size)
 #ifdef CONFIG_WILDFIREMOD
         mach_halt = wildfiremod_halt;
 #endif
-}
-
-/***************************************************************************/
-
-static int __init init_BSP(void)
-{
-        mach_reset = m528x_cpu_reset;
+        mach_sched_init = hw_timer_init;
         m528x_uarts_init();
         m528x_fec_init();
-#if defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE)
+#ifdef CONFIG_SPI_COLDFIRE_QSPI
         m528x_qspi_init();
 #endif
-        platform_add_devices(m528x_devices, ARRAY_SIZE(m528x_devices));
-        return 0;
 }
 
-arch_initcall(init_BSP);
-
 /***************************************************************************/
diff --git a/arch/m68k/platform/5307/config.c b/arch/m68k/platform/5307/config.c
index 00900ac06a9..a568d2870d1 100644
--- a/arch/m68k/platform/5307/config.c
+++ b/arch/m68k/platform/5307/config.c
@@ -16,7 +16,6 @@
 #include <asm/machdep.h>
 #include <asm/coldfire.h>
 #include <asm/mcfsim.h>
-#include <asm/mcfuart.h>
 #include <asm/mcfwdebug.h>
 
 /***************************************************************************/
@@ -29,82 +28,6 @@ unsigned char ledbank = 0xff;
 
 /***************************************************************************/
 
-static struct mcf_platform_uart m5307_uart_platform[] = {
-        {
-                .mapbase        = MCF_MBAR + MCFUART_BASE1,
-                .irq            = 73,
-        },
-        {
-                .mapbase        = MCF_MBAR + MCFUART_BASE2,
-                .irq            = 74,
-        },
-        { },
-};
-
-static struct platform_device m5307_uart = {
-        .name                   = "mcfuart",
-        .id                     = 0,
-        .dev.platform_data      = m5307_uart_platform,
-};
-
-static struct platform_device *m5307_devices[] __initdata = {
-        &m5307_uart,
-};
-
-/***************************************************************************/
-
-static void __init m5307_uart_init_line(int line, int irq)
-{
-        if (line == 0) {
-                writeb(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI1, MCF_MBAR + MCFSIM_UART1ICR);
-                writeb(irq, MCF_MBAR + MCFUART_BASE1 + MCFUART_UIVR);
-                mcf_mapirq2imr(irq, MCFINTC_UART0);
-        } else if (line == 1) {
-                writeb(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI2, MCF_MBAR + MCFSIM_UART2ICR);
-                writeb(irq, MCF_MBAR + MCFUART_BASE2 + MCFUART_UIVR);
-                mcf_mapirq2imr(irq, MCFINTC_UART1);
-        }
-}
-
-static void __init m5307_uarts_init(void)
-{
-        const int nrlines = ARRAY_SIZE(m5307_uart_platform);
-        int line;
-
-        for (line = 0; (line < nrlines); line++)
-                m5307_uart_init_line(line, m5307_uart_platform[line].irq);
-}
-
-/***************************************************************************/
-
-static void __init m5307_timers_init(void)
-{
-        /* Timer1 is always used as system timer */
-        writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI3,
-                MCF_MBAR + MCFSIM_TIMER1ICR);
-        mcf_mapirq2imr(MCF_IRQ_TIMER, MCFINTC_TIMER1);
-
-#ifdef CONFIG_HIGHPROFILE
-        /* Timer2 is to be used as a high speed profile timer  */
-        writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL7 | MCFSIM_ICR_PRI3,
-                MCF_MBAR + MCFSIM_TIMER2ICR);
-        mcf_mapirq2imr(MCF_IRQ_PROFILER, MCFINTC_TIMER2);
-#endif
-}
-
-/***************************************************************************/
-
-void m5307_cpu_reset(void)
-{
-        local_irq_disable();
-        /* Set watchdog to soft reset, and enabled */
-        __raw_writeb(0xc0, MCF_MBAR + MCFSIM_SYPCR);
-        for (;;)
-                /* wait for watchdog to timeout */;
-}
-
-/***************************************************************************/
-
 void __init config_BSP(char *commandp, int size)
 {
 #if defined(CONFIG_NETtel) || \
@@ -114,9 +37,7 @@ void __init config_BSP(char *commandp, int size)
         commandp[size-1] = 0;
 #endif
 
-        mach_reset = m5307_cpu_reset;
-        m5307_timers_init();
-        m5307_uarts_init();
+        mach_sched_init = hw_timer_init;
 
         /* Only support the external interrupts on their primary level */
         mcf_mapirq2imr(25, MCFINTC_EINT1);
@@ -135,13 +56,3 @@ void __init config_BSP(char *commandp, int size)
 }
 
 /***************************************************************************/
-
-static int __init init_BSP(void)
-{
-        platform_add_devices(m5307_devices, ARRAY_SIZE(m5307_devices));
-        return 0;
-}
-
-arch_initcall(init_BSP);
-
-/***************************************************************************/
diff --git a/arch/m68k/platform/532x/config.c b/arch/m68k/platform/532x/config.c
index ca51323f957..2bec3477b73 100644
--- a/arch/m68k/platform/532x/config.c
+++ b/arch/m68k/platform/532x/config.c
@@ -21,214 +21,33 @@
 #include <linux/param.h>
 #include <linux/init.h>
 #include <linux/io.h>
-#include <linux/spi/spi.h>
-#include <linux/gpio.h>
 #include <asm/machdep.h>
 #include <asm/coldfire.h>
 #include <asm/mcfsim.h>
 #include <asm/mcfuart.h>
 #include <asm/mcfdma.h>
 #include <asm/mcfwdebug.h>
-#include <asm/mcfqspi.h>
 
 /***************************************************************************/
 
-static struct mcf_platform_uart m532x_uart_platform[] = {
-        {
-                .mapbase        = MCFUART_BASE1,
-                .irq            = MCFINT_VECBASE + MCFINT_UART0,
-        },
-        {
-                .mapbase        = MCFUART_BASE2,
-                .irq            = MCFINT_VECBASE + MCFINT_UART1,
-        },
-        {
-                .mapbase        = MCFUART_BASE3,
-                .irq            = MCFINT_VECBASE + MCFINT_UART2,
-        },
-        { },
-};
-
-static struct platform_device m532x_uart = {
-        .name                   = "mcfuart",
-        .id                     = 0,
-        .dev.platform_data      = m532x_uart_platform,
-};
-
-static struct resource m532x_fec_resources[] = {
-        {
-                .start          = 0xfc030000,
-                .end            = 0xfc0307ff,
-                .flags          = IORESOURCE_MEM,
-        },
-        {
-                .start          = 64 + 36,
-                .end            = 64 + 36,
-                .flags          = IORESOURCE_IRQ,
-        },
-        {
-                .start          = 64 + 40,
-                .end            = 64 + 40,
-                .flags          = IORESOURCE_IRQ,
-        },
-        {
-                .start          = 64 + 42,
-                .end            = 64 + 42,
-                .flags          = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device m532x_fec = {
-        .name                   = "fec",
-        .id                     = 0,
-        .num_resources          = ARRAY_SIZE(m532x_fec_resources),
-        .resource               = m532x_fec_resources,
-};
-
-#if defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE)
-static struct resource m532x_qspi_resources[] = {
-        {
-                .start          = MCFQSPI_IOBASE,
-                .end            = MCFQSPI_IOBASE + MCFQSPI_IOSIZE - 1,
-                .flags          = IORESOURCE_MEM,
-        },
-        {
-                .start          = MCFINT_VECBASE + MCFINT_QSPI,
-                .end            = MCFINT_VECBASE + MCFINT_QSPI,
-                .flags          = IORESOURCE_IRQ,
-        },
-};
-
-#define MCFQSPI_CS0    84
-#define MCFQSPI_CS1    85
-#define MCFQSPI_CS2    86
-
-static int m532x_cs_setup(struct mcfqspi_cs_control *cs_control)
-{
-        int status;
-
-        status = gpio_request(MCFQSPI_CS0, "MCFQSPI_CS0");
-        if (status) {
-                pr_debug("gpio_request for MCFQSPI_CS0 failed\n");
-                goto fail0;
-        }
-        status = gpio_direction_output(MCFQSPI_CS0, 1);
-        if (status) {
-                pr_debug("gpio_direction_output for MCFQSPI_CS0 failed\n");
-                goto fail1;
-        }
-
-        status = gpio_request(MCFQSPI_CS1, "MCFQSPI_CS1");
-        if (status) {
-                pr_debug("gpio_request for MCFQSPI_CS1 failed\n");
-                goto fail1;
-        }
-        status = gpio_direction_output(MCFQSPI_CS1, 1);
-        if (status) {
-                pr_debug("gpio_direction_output for MCFQSPI_CS1 failed\n");
-                goto fail2;
-        }
-
-        status = gpio_request(MCFQSPI_CS2, "MCFQSPI_CS2");
-        if (status) {
-                pr_debug("gpio_request for MCFQSPI_CS2 failed\n");
-                goto fail2;
-        }
-        status = gpio_direction_output(MCFQSPI_CS2, 1);
-        if (status) {
-                pr_debug("gpio_direction_output for MCFQSPI_CS2 failed\n");
-                goto fail3;
-        }
-
-        return 0;
-
-fail3:
-        gpio_free(MCFQSPI_CS2);
-fail2:
-        gpio_free(MCFQSPI_CS1);
-fail1:
-        gpio_free(MCFQSPI_CS0);
-fail0:
-        return status;
-}
-
-static void m532x_cs_teardown(struct mcfqspi_cs_control *cs_control)
-{
-        gpio_free(MCFQSPI_CS2);
-        gpio_free(MCFQSPI_CS1);
-        gpio_free(MCFQSPI_CS0);
-}
-
-static void m532x_cs_select(struct mcfqspi_cs_control *cs_control,
-                            u8 chip_select, bool cs_high)
-{
-        gpio_set_value(MCFQSPI_CS0 + chip_select, cs_high);
-}
-
-static void m532x_cs_deselect(struct mcfqspi_cs_control *cs_control,
-                              u8 chip_select, bool cs_high)
-{
-        gpio_set_value(MCFQSPI_CS0 + chip_select, !cs_high);
-}
-
-static struct mcfqspi_cs_control m532x_cs_control = {
-        .setup                  = m532x_cs_setup,
-        .teardown               = m532x_cs_teardown,
-        .select                 = m532x_cs_select,
-        .deselect               = m532x_cs_deselect,
-};
-
-static struct mcfqspi_platform_data m532x_qspi_data = {
-        .bus_num                = 0,
-        .num_chipselect         = 3,
-        .cs_control             = &m532x_cs_control,
-};
-
-static struct platform_device m532x_qspi = {
-        .name                   = "mcfqspi",
-        .id                     = 0,
-        .num_resources          = ARRAY_SIZE(m532x_qspi_resources),
-        .resource               = m532x_qspi_resources,
-        .dev.platform_data      = &m532x_qspi_data,
-};
+#ifdef CONFIG_SPI_COLDFIRE_QSPI
 
 static void __init m532x_qspi_init(void)
 {
         /* setup QSPS pins for QSPI with gpio CS control */
         writew(0x01f0, MCF_GPIO_PAR_QSPI);
 }
-#endif /* defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE) */
 
-
-static struct platform_device *m532x_devices[] __initdata = {
-        &m532x_uart,
-        &m532x_fec,
-#if defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE)
-        &m532x_qspi,
-#endif
-};
+#endif /* CONFIG_SPI_COLDFIRE_QSPI */
 
 /***************************************************************************/
 
-static void __init m532x_uart_init_line(int line, int irq)
-{
-        if (line == 0) {
-                /* GPIO initialization */
-                MCF_GPIO_PAR_UART |= 0x000F;
-        } else if (line == 1) {
-                /* GPIO initialization */
-                MCF_GPIO_PAR_UART |= 0x0FF0;
-        }
-}
-
 static void __init m532x_uarts_init(void)
 {
-        const int nrlines = ARRAY_SIZE(m532x_uart_platform);
-        int line;
-
-        for (line = 0; (line < nrlines); line++)
-                m532x_uart_init_line(line, m532x_uart_platform[line].irq);
+        /* UART GPIO initialization */
+        MCF_GPIO_PAR_UART |= 0x0FFF;
 }
+
 /***************************************************************************/
 
 static void __init m532x_fec_init(void)
@@ -242,14 +61,6 @@ static void __init m532x_fec_init(void)
 
 /***************************************************************************/
 
-static void m532x_cpu_reset(void)
-{
-        local_irq_disable();
-        __raw_writeb(MCF_RCR_SWRESET, MCF_RCR);
-}
-
-/***************************************************************************/
-
 void __init config_BSP(char *commandp, int size)
 {
 #if !defined(CONFIG_BOOTPARAM)
@@ -263,6 +74,13 @@ void __init config_BSP(char *commandp, int size)
         }
 #endif
 
+        mach_sched_init = hw_timer_init;
+        m532x_uarts_init();
+        m532x_fec_init();
+#ifdef CONFIG_SPI_COLDFIRE_QSPI
+        m532x_qspi_init();
+#endif
+
 #ifdef CONFIG_BDM_DISABLE
         /*
          * Disable the BDM clocking.  This also turns off most of the rest of
@@ -274,21 +92,6 @@ void __init config_BSP(char *commandp, int size)
 }
 
 /***************************************************************************/
-
-static int __init init_BSP(void)
-{
-        m532x_uarts_init();
-        m532x_fec_init();
-#if defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE)
-        m532x_qspi_init();
-#endif
-        platform_add_devices(m532x_devices, ARRAY_SIZE(m532x_devices));
-        return 0;
-}
-
-arch_initcall(init_BSP);
-
-/***************************************************************************/
 /* Board initialization */
 /***************************************************************************/
 /* 
diff --git a/arch/m68k/platform/5407/config.c b/arch/m68k/platform/5407/config.c
index 70ea789a400..bb6c746ae81 100644
--- a/arch/m68k/platform/5407/config.c
+++ b/arch/m68k/platform/5407/config.c
@@ -16,91 +16,12 @@
 #include <asm/machdep.h>
 #include <asm/coldfire.h>
 #include <asm/mcfsim.h>
-#include <asm/mcfuart.h>
-
-/***************************************************************************/
-
-static struct mcf_platform_uart m5407_uart_platform[] = {
-        {
-                .mapbase        = MCF_MBAR + MCFUART_BASE1,
-                .irq            = 73,
-        },
-        {
-                .mapbase        = MCF_MBAR + MCFUART_BASE2,
-                .irq            = 74,
-        },
-        { },
-};
-
-static struct platform_device m5407_uart = {
-        .name                   = "mcfuart",
-        .id                     = 0,
-        .dev.platform_data      = m5407_uart_platform,
-};
-
-static struct platform_device *m5407_devices[] __initdata = {
-        &m5407_uart,
-};
-
-/***************************************************************************/
-
-static void __init m5407_uart_init_line(int line, int irq)
-{
-        if (line == 0) {
-                writeb(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI1, MCF_MBAR + MCFSIM_UART1ICR);
-                writeb(irq, MCF_MBAR + MCFUART_BASE1 + MCFUART_UIVR);
-                mcf_mapirq2imr(irq, MCFINTC_UART0);
-        } else if (line == 1) {
-                writeb(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI2, MCF_MBAR + MCFSIM_UART2ICR);
-                writeb(irq, MCF_MBAR + MCFUART_BASE2 + MCFUART_UIVR);
-                mcf_mapirq2imr(irq, MCFINTC_UART1);
-        }
-}
-
-static void __init m5407_uarts_init(void)
-{
-        const int nrlines = ARRAY_SIZE(m5407_uart_platform);
-        int line;
-
-        for (line = 0; (line < nrlines); line++)
-                m5407_uart_init_line(line, m5407_uart_platform[line].irq);
-}
-
-/***************************************************************************/
-
-static void __init m5407_timers_init(void)
-{
-        /* Timer1 is always used as system timer */
-        writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI3,
-                MCF_MBAR + MCFSIM_TIMER1ICR);
-        mcf_mapirq2imr(MCF_IRQ_TIMER, MCFINTC_TIMER1);
-
-#ifdef CONFIG_HIGHPROFILE
-        /* Timer2 is to be used as a high speed profile timer  */
-        writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL7 | MCFSIM_ICR_PRI3,
-                MCF_MBAR + MCFSIM_TIMER2ICR);
-        mcf_mapirq2imr(MCF_IRQ_PROFILER, MCFINTC_TIMER2);
-#endif
-}
-
-/***************************************************************************/
-
-void m5407_cpu_reset(void)
-{
-        local_irq_disable();
-        /* set watchdog to soft reset, and enabled */
-        __raw_writeb(0xc0, MCF_MBAR + MCFSIM_SYPCR);
-        for (;;)
-                /* wait for watchdog to timeout */;
-}
 
 /***************************************************************************/
 
 void __init config_BSP(char *commandp, int size)
 {
-        mach_reset = m5407_cpu_reset;
-        m5407_timers_init();
-        m5407_uarts_init();
+        mach_sched_init = hw_timer_init;
 
         /* Only support the external interrupts on their primary level */
         mcf_mapirq2imr(25, MCFINTC_EINT1);
@@ -110,13 +31,3 @@ void __init config_BSP(char *commandp, int size)
 }
 
 /***************************************************************************/
-
-static int __init init_BSP(void)
-{
-        platform_add_devices(m5407_devices, ARRAY_SIZE(m5407_devices));
-        return 0;
-}
-
-arch_initcall(init_BSP);
-
-/***************************************************************************/
diff --git a/arch/m68k/platform/54xx/config.c b/arch/m68k/platform/54xx/config.c
index ee043540bfa..2081c6cbb3d 100644
--- a/arch/m68k/platform/54xx/config.c
+++ b/arch/m68k/platform/54xx/config.c
@@ -27,64 +27,17 @@
 
 /***************************************************************************/
 
-static struct mcf_platform_uart m54xx_uart_platform[] = {
-        {
-                .mapbase        = MCF_MBAR + MCFUART_BASE1,
-                .irq            = 64 + 35,
-        },
-        {
-                .mapbase        = MCF_MBAR + MCFUART_BASE2,
-                .irq            = 64 + 34,
-        },
-        {
-                .mapbase        = MCF_MBAR + MCFUART_BASE3,
-                .irq            = 64 + 33,
-        },
-        {
-                .mapbase        = MCF_MBAR + MCFUART_BASE4,
-                .irq            = 64 + 32,
-        },
-};
-
-static struct platform_device m54xx_uart = {
-        .name                   = "mcfuart",
-        .id                     = 0,
-        .dev.platform_data      = m54xx_uart_platform,
-};
-
-static struct platform_device *m54xx_devices[] __initdata = {
-        &m54xx_uart,
-};
-
-
-/***************************************************************************/
-
-static void __init m54xx_uart_init_line(int line, int irq)
-{
-        int rts_cts;
-
-        /* enable io pins */
-        switch (line) {
-        case 0:
-                rts_cts = 0; break;
-        case 1:
-                rts_cts = MCF_PAR_PSC_RTS_RTS; break;
-        case 2:
-                rts_cts = MCF_PAR_PSC_RTS_RTS | MCF_PAR_PSC_CTS_CTS; break;
-        case 3:
-                rts_cts = 0; break;
-        }
-        __raw_writeb(MCF_PAR_PSC_TXD | rts_cts | MCF_PAR_PSC_RXD,
-                                                MCF_MBAR + MCF_PAR_PSC(line));
-}
-
 static void __init m54xx_uarts_init(void)
 {
-        const int nrlines = ARRAY_SIZE(m54xx_uart_platform);
-        int line;
-
-        for (line = 0; (line < nrlines); line++)
-                m54xx_uart_init_line(line, m54xx_uart_platform[line].irq);
+        /* enable io pins */
+        __raw_writeb(MCF_PAR_PSC_TXD | MCF_PAR_PSC_RXD,
+                MCF_MBAR + MCF_PAR_PSC(0));
+        __raw_writeb(MCF_PAR_PSC_TXD | MCF_PAR_PSC_RXD | MCF_PAR_PSC_RTS_RTS,
+                MCF_MBAR + MCF_PAR_PSC(1));
+        __raw_writeb(MCF_PAR_PSC_TXD | MCF_PAR_PSC_RXD | MCF_PAR_PSC_RTS_RTS |
+                MCF_PAR_PSC_CTS_CTS, MCF_MBAR + MCF_PAR_PSC(2));
+        __raw_writeb(MCF_PAR_PSC_TXD | MCF_PAR_PSC_RXD,
+                MCF_MBAR + MCF_PAR_PSC(3));
 }
 
 /***************************************************************************/
@@ -145,18 +98,8 @@ void __init config_BSP(char *commandp, int size)
         mmu_context_init();
 #endif
         mach_reset = mcf54xx_reset;
+        mach_sched_init = hw_timer_init;
         m54xx_uarts_init();
 }
 
 /***************************************************************************/
-
-static int __init init_BSP(void)
-{
-
-        platform_add_devices(m54xx_devices, ARRAY_SIZE(m54xx_devices));
-        return 0;
-}
-
-arch_initcall(init_BSP);
-
-/***************************************************************************/
diff --git a/arch/m68k/platform/68328/config.c b/arch/m68k/platform/68328/config.c
index d70bf2623db..44b86654431 100644
--- a/arch/m68k/platform/68328/config.c
+++ b/arch/m68k/platform/68328/config.c
@@ -17,6 +17,7 @@
 
 #include <linux/types.h>
 #include <linux/kernel.h>
+#include <linux/rtc.h>
 #include <asm/system.h>
 #include <asm/machdep.h>
 #include <asm/MC68328.h>
@@ -26,7 +27,7 @@
 
 /***************************************************************************/
 
-void m68328_timer_gettod(int *year, int *mon, int *day, int *hour, int *min, int *sec);
+int m68328_hwclk(int set, struct rtc_time *t);
 
 /***************************************************************************/
 
@@ -48,7 +49,7 @@ void config_BSP(char *command, int len)
   printk(KERN_INFO "68328 support Kenneth Albanowski <kjahds@kjshds.com>\n");
   printk(KERN_INFO "68328/Pilot support Bernhard Kuhn <kuhn@lpr.e-technik.tu-muenchen.de>\n");
 
-  mach_gettod = m68328_timer_gettod;
+  mach_hwclk = m68328_hwclk;
   mach_reset = m68328_reset;
 }
 
diff --git a/arch/m68k/platform/68328/ints.c b/arch/m68k/platform/68328/ints.c
index 4bd456531f9..b3810febb3e 100644
--- a/arch/m68k/platform/68328/ints.c
+++ b/arch/m68k/platform/68328/ints.c
@@ -68,8 +68,6 @@ asmlinkage irqreturn_t inthandler5(void);
 asmlinkage irqreturn_t inthandler6(void);
 asmlinkage irqreturn_t inthandler7(void);
 
-extern e_vector *_ramvec;
-
 /* The 68k family did not have a good way to determine the source
  * of interrupts until later in the family.  The EC000 core does
  * not provide the vector number on the stack, we vector everything
diff --git a/arch/m68k/platform/68328/timers.c b/arch/m68k/platform/68328/timers.c
index f2678866067..b15ddef1ec7 100644
--- a/arch/m68k/platform/68328/timers.c
+++ b/arch/m68k/platform/68328/timers.c
@@ -20,6 +20,7 @@
 #include <linux/interrupt.h>
 #include <linux/irq.h>
 #include <linux/clocksource.h>
+#include <linux/rtc.h>
 #include <asm/setup.h>
 #include <asm/system.h>
 #include <asm/pgtable.h>
@@ -119,14 +120,17 @@ void hw_timer_init(void)
 
 /***************************************************************************/
 
-void m68328_timer_gettod(int *year, int *mon, int *day, int *hour, int *min, int *sec)
+int m68328_hwclk(int set, struct rtc_time *t)
 {
-        long now = RTCTIME;
-
-        *year = *mon = *day = 1;
-        *hour = (now >> 24) % 24;
-        *min = (now >> 16) % 60;
-        *sec = now % 60;
+        if (!set) {
+                long now = RTCTIME;
+                t->tm_year = t->tm_mon = t->tm_mday = 1;
+                t->tm_hour = (now >> 24) % 24;
+                t->tm_min = (now >> 16) % 60;
+                t->tm_sec = now % 60;
+        }
+
+        return 0;
 }
 
 /***************************************************************************/
diff --git a/arch/m68k/platform/68360/config.c b/arch/m68k/platform/68360/config.c
index 9dd5bca3874..599a5949f32 100644
--- a/arch/m68k/platform/68360/config.c
+++ b/arch/m68k/platform/68360/config.c
@@ -103,11 +103,6 @@ void hw_timer_init(void)
   pquicc->timer_tgcr  = tgcr_save;
 }
 
-void BSP_gettod (int *yearp, int *monp, int *dayp,
-                   int *hourp, int *minp, int *secp)
-{
-}
-
 int BSP_set_clock_mmss(unsigned long nowtime)
 {
 #if 0
@@ -181,6 +176,5 @@ void config_BSP(char *command, int len)
   scc1_hwaddr = "\00\01\02\03\04\05";
 #endif
  
-  mach_gettod          = BSP_gettod;
-  mach_reset           = BSP_reset;
+  mach_reset = BSP_reset;
 }
diff --git a/arch/m68k/platform/68360/ints.c b/arch/m68k/platform/68360/ints.c
index 7b40202d963..8cd42692331 100644
--- a/arch/m68k/platform/68360/ints.c
+++ b/arch/m68k/platform/68360/ints.c
@@ -32,8 +32,6 @@ asmlinkage void trap(void);
 asmlinkage void bad_interrupt(void);
 asmlinkage void inthandler(void);
 
-extern void *_ramvec[];
-
 static void intc_irq_unmask(struct irq_data *d)
 {
         pquicc->intr_cimr |= (1 << d->irq);
diff --git a/arch/m68k/platform/68EZ328/config.c b/arch/m68k/platform/68EZ328/config.c
index 1be1a16f689..dd2c5355434 100644
--- a/arch/m68k/platform/68EZ328/config.c
+++ b/arch/m68k/platform/68EZ328/config.c
@@ -15,6 +15,7 @@
 
 #include <linux/types.h>
 #include <linux/kernel.h>
+#include <linux/rtc.h>
 #include <asm/system.h>
 #include <asm/pgtable.h>
 #include <asm/machdep.h>
@@ -25,7 +26,7 @@
 
 /***************************************************************************/
 
-void m68328_timer_gettod(int *year, int *mon, int *day, int *hour, int *min, int *sec);
+int m68328_hwclk(int set, struct rtc_time *t);
 
 /***************************************************************************/
 
@@ -69,7 +70,7 @@ void config_BSP(char *command, int len)
   else command[0] = 0;
 #endif
  
-  mach_gettod = m68328_timer_gettod;
+  mach_hwclk = m68328_hwclk;
   mach_reset = m68ez328_reset;
 }
 
diff --git a/arch/m68k/platform/68VZ328/config.c b/arch/m68k/platform/68VZ328/config.c
index eabaabe8af3..25ec673edc2 100644
--- a/arch/m68k/platform/68VZ328/config.c
+++ b/arch/m68k/platform/68VZ328/config.c
@@ -20,6 +20,7 @@
 #include <linux/netdevice.h>
 #include <linux/interrupt.h>
 #include <linux/irq.h>
+#include <linux/rtc.h>
 
 #include <asm/system.h>
 #include <asm/pgtable.h>
@@ -33,7 +34,7 @@
 
 /***************************************************************************/
 
-void m68328_timer_gettod(int *year, int *mon, int *day, int *hour, int *min, int *sec);
+int m68328_hwclk(int set, struct rtc_time *t);
 
 /***************************************************************************/
 /*                        Init Drangon Engine hardware                     */
@@ -181,7 +182,7 @@ void config_BSP(char *command, int size)
 
         init_hardware(command, size);
 
-        mach_gettod = m68328_timer_gettod;
+        mach_hwclk = m68328_hwclk;
         mach_reset = m68vz328_reset;
 }
 
diff --git a/arch/m68k/platform/coldfire/Makefile b/arch/m68k/platform/coldfire/Makefile
index a8967baabd7..a0815c61dec 100644
--- a/arch/m68k/platform/coldfire/Makefile
+++ b/arch/m68k/platform/coldfire/Makefile
@@ -14,18 +14,18 @@
 
 asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1
 
-obj-$(CONFIG_COLDFIRE)  += cache.o clk.o dma.o entry.o vectors.o
-obj-$(CONFIG_M5206)     += timers.o intc.o
-obj-$(CONFIG_M5206e)    += timers.o intc.o
-obj-$(CONFIG_M520x)     += pit.o intc-simr.o
-obj-$(CONFIG_M523x)     += pit.o dma_timer.o intc-2.o
-obj-$(CONFIG_M5249)     += timers.o intc.o
-obj-$(CONFIG_M527x)     += pit.o intc-2.o
+obj-$(CONFIG_COLDFIRE)  += cache.o clk.o device.o dma.o entry.o vectors.o
+obj-$(CONFIG_M5206)     += timers.o intc.o reset.o
+obj-$(CONFIG_M5206e)    += timers.o intc.o reset.o
+obj-$(CONFIG_M520x)     += pit.o intc-simr.o reset.o
+obj-$(CONFIG_M523x)     += pit.o dma_timer.o intc-2.o reset.o
+obj-$(CONFIG_M5249)     += timers.o intc.o reset.o
+obj-$(CONFIG_M527x)     += pit.o intc-2.o reset.o
 obj-$(CONFIG_M5272)     += timers.o
-obj-$(CONFIG_M528x)     += pit.o intc-2.o
-obj-$(CONFIG_M5307)     += timers.o intc.o
-obj-$(CONFIG_M532x)     += timers.o intc-simr.o
-obj-$(CONFIG_M5407)     += timers.o intc.o
+obj-$(CONFIG_M528x)     += pit.o intc-2.o reset.o
+obj-$(CONFIG_M5307)     += timers.o intc.o reset.o
+obj-$(CONFIG_M532x)     += timers.o intc-simr.o reset.o
+obj-$(CONFIG_M5407)     += timers.o intc.o reset.o
 obj-$(CONFIG_M54xx)     += sltimers.o intc-2.o
 
 obj-y                   += pinmux.o gpio.o
diff --git a/arch/m68k/platform/coldfire/device.c b/arch/m68k/platform/coldfire/device.c
new file mode 100644
index 00000000000..fa50c48292f
--- /dev/null
+++ b/arch/m68k/platform/coldfire/device.c
@@ -0,0 +1,318 @@
+/*
+ * device.c  -- common ColdFire SoC device support
+ *
+ * (C) Copyright 2011, Greg Ungerer <gerg@uclinux.org>
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file COPYING in the main directory of this archive
+ * for more details.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/spi/spi.h>
+#include <linux/gpio.h>
+#include <asm/traps.h>
+#include <asm/coldfire.h>
+#include <asm/mcfsim.h>
+#include <asm/mcfuart.h>
+#include <asm/mcfqspi.h>
+
+/*
+ *      All current ColdFire parts contain from 2, 3 or 4 UARTS.
+ */
+static struct mcf_platform_uart mcf_uart_platform_data[] = {
+        {
+                .mapbase        = MCFUART_BASE0,
+                .irq            = MCF_IRQ_UART0,
+        },
+        {
+                .mapbase        = MCFUART_BASE1,
+                .irq            = MCF_IRQ_UART1,
+        },
+#ifdef MCFUART_BASE2
+        {
+                .mapbase        = MCFUART_BASE2,
+                .irq            = MCF_IRQ_UART2,
+        },
+#endif
+#ifdef MCFUART_BASE3
+        {
+                .mapbase        = MCFUART_BASE3,
+                .irq            = MCF_IRQ_UART3,
+        },
+#endif
+        { },
+};
+
+static struct platform_device mcf_uart = {
+        .name                   = "mcfuart",
+        .id                     = 0,
+        .dev.platform_data      = mcf_uart_platform_data,
+};
+
+#ifdef CONFIG_FEC
+/*
+ *      Some ColdFire cores contain the Fast Ethernet Controller (FEC)
+ *      block. It is Freescale's own hardware block. Some ColdFires
+ *      have 2 of these.
+ */
+static struct resource mcf_fec0_resources[] = {
+        {
+                .start          = MCFFEC_BASE0,
+                .end            = MCFFEC_BASE0 + MCFFEC_SIZE0 - 1,
+                .flags          = IORESOURCE_MEM,
+        },
+        {
+                .start          = MCF_IRQ_FECRX0,
+                .end            = MCF_IRQ_FECRX0,
+                .flags          = IORESOURCE_IRQ,
+        },
+        {
+                .start          = MCF_IRQ_FECTX0,
+                .end            = MCF_IRQ_FECTX0,
+                .flags          = IORESOURCE_IRQ,
+        },
+        {
+                .start          = MCF_IRQ_FECENTC0,
+                .end            = MCF_IRQ_FECENTC0,
+                .flags          = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device mcf_fec0 = {
+        .name                   = "fec",
+        .id                     = 0,
+        .num_resources          = ARRAY_SIZE(mcf_fec0_resources),
+        .resource               = mcf_fec0_resources,
+};
+
+#ifdef MCFFEC_BASE1
+static struct resource mcf_fec1_resources[] = {
+        {
+                .start          = MCFFEC_BASE1,
+                .end            = MCFFEC_BASE1 + MCFFEC_SIZE1 - 1,
+                .flags          = IORESOURCE_MEM,
+        },
+        {
+                .start          = MCF_IRQ_FECRX1,
+                .end            = MCF_IRQ_FECRX1,
+                .flags          = IORESOURCE_IRQ,
+        },
+        {
+                .start          = MCF_IRQ_FECTX1,
+                .end            = MCF_IRQ_FECTX1,
+                .flags          = IORESOURCE_IRQ,
+        },
+        {
+                .start          = MCF_IRQ_FECENTC1,
+                .end            = MCF_IRQ_FECENTC1,
+                .flags          = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device mcf_fec1 = {
+        .name                   = "fec",
+        .id                     = 0,
+        .num_resources          = ARRAY_SIZE(mcf_fec1_resources),
+        .resource               = mcf_fec1_resources,
+};
+#endif /* MCFFEC_BASE1 */
+#endif /* CONFIG_FEC */
+
+#ifdef CONFIG_SPI_COLDFIRE_QSPI
+/*
+ *      The ColdFire QSPI module is an SPI protocol hardware block used
+ *      on a number of different ColdFire CPUs.
+ */
+static struct resource mcf_qspi_resources[] = {
+        {
+                .start          = MCFQSPI_BASE,
+                .end            = MCFQSPI_BASE + MCFQSPI_SIZE - 1,
+                .flags          = IORESOURCE_MEM,
+        },
+        {
+                .start          = MCF_IRQ_QSPI,
+                .end            = MCF_IRQ_QSPI,
+                .flags          = IORESOURCE_IRQ,
+        },
+};
+
+static int mcf_cs_setup(struct mcfqspi_cs_control *cs_control)
+{
+        int status;
+
+        status = gpio_request(MCFQSPI_CS0, "MCFQSPI_CS0");
+        if (status) {
+                pr_debug("gpio_request for MCFQSPI_CS0 failed\n");
+                goto fail0;
+        }
+        status = gpio_direction_output(MCFQSPI_CS0, 1);
+        if (status) {
+                pr_debug("gpio_direction_output for MCFQSPI_CS0 failed\n");
+                goto fail1;
+        }
+
+        status = gpio_request(MCFQSPI_CS1, "MCFQSPI_CS1");
+        if (status) {
+                pr_debug("gpio_request for MCFQSPI_CS1 failed\n");
+                goto fail1;
+        }
+        status = gpio_direction_output(MCFQSPI_CS1, 1);
+        if (status) {
+                pr_debug("gpio_direction_output for MCFQSPI_CS1 failed\n");
+                goto fail2;
+        }
+
+        status = gpio_request(MCFQSPI_CS2, "MCFQSPI_CS2");
+        if (status) {
+                pr_debug("gpio_request for MCFQSPI_CS2 failed\n");
+                goto fail2;
+        }
+        status = gpio_direction_output(MCFQSPI_CS2, 1);
+        if (status) {
+                pr_debug("gpio_direction_output for MCFQSPI_CS2 failed\n");
+                goto fail3;
+        }
+
+#ifdef MCFQSPI_CS3
+        status = gpio_request(MCFQSPI_CS3, "MCFQSPI_CS3");
+        if (status) {
+                pr_debug("gpio_request for MCFQSPI_CS3 failed\n");
+                goto fail3;
+        }
+        status = gpio_direction_output(MCFQSPI_CS3, 1);
+        if (status) {
+                pr_debug("gpio_direction_output for MCFQSPI_CS3 failed\n");
+                gpio_free(MCFQSPI_CS3);
+                goto fail3;
+        }
+#endif
+
+        return 0;
+
+fail3:
+        gpio_free(MCFQSPI_CS2);
+fail2:
+        gpio_free(MCFQSPI_CS1);
+fail1:
+        gpio_free(MCFQSPI_CS0);
+fail0:
+        return status;
+}
+
+static void mcf_cs_teardown(struct mcfqspi_cs_control *cs_control)
+{
+#ifdef MCFQSPI_CS3
+        gpio_free(MCFQSPI_CS3);
+#endif
+        gpio_free(MCFQSPI_CS2);
+        gpio_free(MCFQSPI_CS1);
+        gpio_free(MCFQSPI_CS0);
+}
+
+static void mcf_cs_select(struct mcfqspi_cs_control *cs_control,
+                          u8 chip_select, bool cs_high)
+{
+        switch (chip_select) {
+        case 0:
+                gpio_set_value(MCFQSPI_CS0, cs_high);
+                break;
+        case 1:
+                gpio_set_value(MCFQSPI_CS1, cs_high);
+                break;
+        case 2:
+                gpio_set_value(MCFQSPI_CS2, cs_high);
+                break;
+#ifdef MCFQSPI_CS3
+        case 3:
+                gpio_set_value(MCFQSPI_CS3, cs_high);
+                break;
+#endif
+        }
+}
+
+static void mcf_cs_deselect(struct mcfqspi_cs_control *cs_control,
+                            u8 chip_select, bool cs_high)
+{
+        switch (chip_select) {
+        case 0:
+                gpio_set_value(MCFQSPI_CS0, !cs_high);
+                break;
+        case 1:
+                gpio_set_value(MCFQSPI_CS1, !cs_high);
+                break;
+        case 2:
+                gpio_set_value(MCFQSPI_CS2, !cs_high);
+                break;
+#ifdef MCFQSPI_CS3
+        case 3:
+                gpio_set_value(MCFQSPI_CS3, !cs_high);
+                break;
+#endif
+        }
+}
+
+static struct mcfqspi_cs_control mcf_cs_control = {
+        .setup                  = mcf_cs_setup,
+        .teardown               = mcf_cs_teardown,
+        .select                 = mcf_cs_select,
+        .deselect               = mcf_cs_deselect,
+};
+
+static struct mcfqspi_platform_data mcf_qspi_data = {
+        .bus_num                = 0,
+        .num_chipselect         = 4,
+        .cs_control             = &mcf_cs_control,
+};
+
+static struct platform_device mcf_qspi = {
+        .name                   = "mcfqspi",
+        .id                     = 0,
+        .num_resources          = ARRAY_SIZE(mcf_qspi_resources),
+        .resource               = mcf_qspi_resources,
+        .dev.platform_data      = &mcf_qspi_data,
+};
+#endif /* CONFIG_SPI_COLDFIRE_QSPI */
+
+static struct platform_device *mcf_devices[] __initdata = {
+        &mcf_uart,
+#ifdef CONFIG_FEC
+        &mcf_fec0,
+#ifdef MCFFEC_BASE1
+        &mcf_fec1,
+#endif
+#endif
+#ifdef CONFIG_SPI_COLDFIRE_QSPI
+        &mcf_qspi,
+#endif
+};
+
+/*
+ *      Some ColdFire UARTs let you set the IRQ line to use.
+ */
+static void __init mcf_uart_set_irq(void)
+{
+#ifdef MCFUART_UIVR
+        /* UART0 interrupt setup */
+        writeb(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI1, MCF_MBAR + MCFSIM_UART1ICR);
+        writeb(MCF_IRQ_UART0, MCFUART_BASE0 + MCFUART_UIVR);
+        mcf_mapirq2imr(MCF_IRQ_UART0, MCFINTC_UART0);
+
+        /* UART1 interrupt setup */
+        writeb(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI2, MCF_MBAR + MCFSIM_UART2ICR);
+        writeb(MCF_IRQ_UART1, MCFUART_BASE1 + MCFUART_UIVR);
+        mcf_mapirq2imr(MCF_IRQ_UART1, MCFINTC_UART1);
+#endif
+}
+
+static int __init mcf_init_devices(void)
+{
+        mcf_uart_set_irq();
+        platform_add_devices(mcf_devices, ARRAY_SIZE(mcf_devices));
+        return 0;
+}
+
+arch_initcall(mcf_init_devices);
+
diff --git a/arch/m68k/platform/coldfire/head.S b/arch/m68k/platform/coldfire/head.S
index 38f04a3f620..c3db70ed33b 100644
--- a/arch/m68k/platform/coldfire/head.S
+++ b/arch/m68k/platform/coldfire/head.S
@@ -158,6 +158,10 @@ _start:
 #if defined(CONFIG_UBOOT)
         movel   %sp,_init_sp                    /* save initial stack pointer */
 #endif
+#ifdef CONFIG_MBAR
+        movel   #CONFIG_MBAR+1,%d0              /* configured MBAR address */
+        movec   %d0,%MBAR                       /* set it */
+#endif
 
         /*
          *      Do any platform or board specific setup now. Most boards
diff --git a/arch/m68k/platform/coldfire/pit.c b/arch/m68k/platform/coldfire/pit.c
index 02663d25822..e62dbbcb10f 100644
--- a/arch/m68k/platform/coldfire/pit.c
+++ b/arch/m68k/platform/coldfire/pit.c
@@ -149,7 +149,7 @@ static struct clocksource pit_clk = {
 
 /***************************************************************************/
 
-void hw_timer_init(void)
+void hw_timer_init(irq_handler_t handler)
 {
         cf_pit_clockevent.cpumask = cpumask_of(smp_processor_id());
         cf_pit_clockevent.mult = div_sc(FREQ, NSEC_PER_SEC, 32);
diff --git a/arch/m68k/platform/coldfire/reset.c b/arch/m68k/platform/coldfire/reset.c
new file mode 100644
index 00000000000..933e54eacc6
--- /dev/null
+++ b/arch/m68k/platform/coldfire/reset.c
@@ -0,0 +1,50 @@
+/*
+ * reset.c  -- common ColdFire SoC reset support
+ *
+ * (C) Copyright 2012, Greg Ungerer <gerg@uclinux.org>
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file COPYING in the main directory of this archive
+ * for more details.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <asm/machdep.h>
+#include <asm/coldfire.h>
+#include <asm/mcfsim.h>
+
+/*
+ *      There are 2 common methods amongst the ColdFure parts for reseting
+ *      the CPU. But there are couple of exceptions, the 5272 and the 547x
+ *      have something completely special to them, and we let their specific
+ *      subarch code handle them.
+ */
+
+#ifdef MCFSIM_SYPCR
+static void mcf_cpu_reset(void)
+{
+        local_irq_disable();
+        /* Set watchdog to soft reset, and enabled */
+        __raw_writeb(0xc0, MCF_MBAR + MCFSIM_SYPCR);
+        for (;;)
+                /* wait for watchdog to timeout */;
+}
+#endif
+
+#ifdef MCF_RCR
+static void mcf_cpu_reset(void)
+{
+        local_irq_disable();
+        __raw_writeb(MCF_RCR_SWRESET, MCF_RCR);
+}
+#endif
+
+static int __init mcf_setup_reset(void)
+{
+        mach_reset = mcf_cpu_reset;
+        return 0;
+}
+
+arch_initcall(mcf_setup_reset);
diff --git a/arch/m68k/platform/coldfire/sltimers.c b/arch/m68k/platform/coldfire/sltimers.c
index 54e1452f853..2027fc20b87 100644
--- a/arch/m68k/platform/coldfire/sltimers.c
+++ b/arch/m68k/platform/coldfire/sltimers.c
@@ -81,12 +81,14 @@ void mcfslt_profile_init(void)
 static u32 mcfslt_cycles_per_jiffy;
 static u32 mcfslt_cnt;
 
+static irq_handler_t timer_interrupt;
+
 static irqreturn_t mcfslt_tick(int irq, void *dummy)
 {
         /* Reset Slice Timer 0 */
         __raw_writel(MCFSLT_SSR_BE | MCFSLT_SSR_TE, TA(MCFSLT_SSR));
         mcfslt_cnt += mcfslt_cycles_per_jiffy;
-        return arch_timer_interrupt(irq, dummy);
+        return timer_interrupt(irq, dummy);
 }
 
 static struct irqaction mcfslt_timer_irq = {
@@ -121,7 +123,7 @@ static struct clocksource mcfslt_clk = {
         .flags  = CLOCK_SOURCE_IS_CONTINUOUS,
 };
 
-void hw_timer_init(void)
+void hw_timer_init(irq_handler_t handler)
 {
         mcfslt_cycles_per_jiffy = MCF_BUSCLK / HZ;
         /*
@@ -136,6 +138,7 @@ void hw_timer_init(void)
         /* initialize mcfslt_cnt knowing that slice timers count down */
         mcfslt_cnt = mcfslt_cycles_per_jiffy;
 
+        timer_interrupt = handler;
         setup_irq(MCF_IRQ_TIMER, &mcfslt_timer_irq);
 
         clocksource_register_hz(&mcfslt_clk, MCF_BUSCLK);
diff --git a/arch/m68k/platform/coldfire/timers.c b/arch/m68k/platform/coldfire/timers.c
index 0d90da32fcd..ed96ce50d79 100644
--- a/arch/m68k/platform/coldfire/timers.c
+++ b/arch/m68k/platform/coldfire/timers.c
@@ -47,6 +47,27 @@ void coldfire_profile_init(void);
 static u32 mcftmr_cycles_per_jiffy;
 static u32 mcftmr_cnt;
 
+static irq_handler_t timer_interrupt;
+
+/***************************************************************************/
+
+static void init_timer_irq(void)
+{
+#ifdef MCFSIM_ICR_AUTOVEC
+        /* Timer1 is always used as system timer */
+        writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI3,
+                MCF_MBAR + MCFSIM_TIMER1ICR);
+        mcf_mapirq2imr(MCF_IRQ_TIMER, MCFINTC_TIMER1);
+
+#ifdef CONFIG_HIGHPROFILE
+        /* Timer2 is to be used as a high speed profile timer  */
+        writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL7 | MCFSIM_ICR_PRI3,
+                MCF_MBAR + MCFSIM_TIMER2ICR);
+        mcf_mapirq2imr(MCF_IRQ_PROFILER, MCFINTC_TIMER2);
+#endif
+#endif /* MCFSIM_ICR_AUTOVEC */
+}
+
 /***************************************************************************/
 
 static irqreturn_t mcftmr_tick(int irq, void *dummy)
@@ -55,7 +76,7 @@ static irqreturn_t mcftmr_tick(int irq, void *dummy)
         __raw_writeb(MCFTIMER_TER_CAP | MCFTIMER_TER_REF, TA(MCFTIMER_TER));
 
         mcftmr_cnt += mcftmr_cycles_per_jiffy;
-        return arch_timer_interrupt(irq, dummy);
+        return timer_interrupt(irq, dummy);
 }
 
 /***************************************************************************/
@@ -94,7 +115,7 @@ static struct clocksource mcftmr_clk = {
 
 /***************************************************************************/
 
-void hw_timer_init(void)
+void hw_timer_init(irq_handler_t handler)
 {
         __raw_writew(MCFTIMER_TMR_DISABLE, TA(MCFTIMER_TMR));
         mcftmr_cycles_per_jiffy = FREQ / HZ;
@@ -110,6 +131,8 @@ void hw_timer_init(void)
 
         clocksource_register_hz(&mcftmr_clk, FREQ);
 
+        timer_interrupt = handler;
+        init_timer_irq();
         setup_irq(MCF_IRQ_TIMER, &mcftmr_timer_irq);
 
 #ifdef CONFIG_HIGHPROFILE
diff --git a/arch/m68k/platform/coldfire/vectors.c b/arch/m68k/platform/coldfire/vectors.c
index 3a7cc524ecd..a4dbdecbec7 100644
--- a/arch/m68k/platform/coldfire/vectors.c
+++ b/arch/m68k/platform/coldfire/vectors.c
@@ -33,8 +33,6 @@ asmlinkage void dbginterrupt_c(struct frame *fp)
 
 /***************************************************************************/
 
-extern e_vector *_ramvec;
-
 /* Assembler routines */
 asmlinkage void buserr(void);
 asmlinkage void trap(void);
diff --git a/arch/m68k/q40/config.c b/arch/m68k/q40/config.c
index ad10fecec2f..be936480b96 100644
--- a/arch/m68k/q40/config.c
+++ b/arch/m68k/q40/config.c
@@ -24,6 +24,7 @@
 #include <linux/rtc.h>
 #include <linux/vt_kern.h>
 #include <linux/bcd.h>
+#include <linux/platform_device.h>
 
 #include <asm/io.h>
 #include <asm/rtc.h>
@@ -329,3 +330,15 @@ static int q40_set_rtc_pll(struct rtc_pll_info *pll)
         } else
                 return -EINVAL;
 }
+
+static __init int q40_add_kbd_device(void)
+{
+        struct platform_device *pdev;
+
+        pdev = platform_device_register_simple("q40kbd", -1, NULL, 0);
+        if (IS_ERR(pdev))
+                return PTR_ERR(pdev);
+
+        return 0;
+}
+arch_initcall(q40_add_kbd_device);
diff --git a/arch/microblaze/include/asm/pci-bridge.h b/arch/microblaze/include/asm/pci-bridge.h
index e9834b2991d..cb5d3979480 100644
--- a/arch/microblaze/include/asm/pci-bridge.h
+++ b/arch/microblaze/include/asm/pci-bridge.h
@@ -10,7 +10,6 @@
 #include <linux/pci.h>
 #include <linux/list.h>
 #include <linux/ioport.h>
-#include <asm-generic/pci-bridge.h>
 
 struct device_node;
 
diff --git a/arch/microblaze/include/asm/pci.h b/arch/microblaze/include/asm/pci.h
index 033137628e8..a0da88bf70c 100644
--- a/arch/microblaze/include/asm/pci.h
+++ b/arch/microblaze/include/asm/pci.h
@@ -94,14 +94,6 @@ extern int pci_mmap_legacy_page_range(struct pci_bus *bus,
  */
 #define PCI_DMA_BUS_IS_PHYS     (1)
 
-extern void pcibios_resource_to_bus(struct pci_dev *dev,
-                        struct pci_bus_region *region,
-                        struct resource *res);
-
-extern void pcibios_bus_to_resource(struct pci_dev *dev,
-                        struct resource *res,
-                        struct pci_bus_region *region);
-
 static inline struct resource *pcibios_select_root(struct pci_dev *pdev,
                         struct resource *res)
 {
diff --git a/arch/microblaze/include/asm/pgtable.h b/arch/microblaze/include/asm/pgtable.h
index b2af42311a1..44dc67aa027 100644
--- a/arch/microblaze/include/asm/pgtable.h
+++ b/arch/microblaze/include/asm/pgtable.h
@@ -543,8 +543,6 @@ extern unsigned long iopa(unsigned long addr);
 /* Needs to be defined here and not in linux/mm.h, as it is arch dependent */
 #define kern_addr_valid(addr)   (1)
 
-#define io_remap_page_range remap_page_range
-
 /*
  * No page table caches to initialise
  */
diff --git a/arch/microblaze/pci/pci-common.c b/arch/microblaze/pci/pci-common.c
index 85f2ac1230a..d10403dadd2 100644
--- a/arch/microblaze/pci/pci-common.c
+++ b/arch/microblaze/pci/pci-common.c
@@ -46,9 +46,6 @@ static int global_phb_number;		/* Global phb counter */
 /* ISA Memory physical address */
 resource_size_t isa_mem_base;
 
-/* Default PCI flags is 0 on ppc32, modified at boot on ppc64 */
-unsigned int pci_flags;
-
 static struct dma_map_ops *pci_dma_ops = &dma_direct_ops;
 
 unsigned long isa_io_base;
@@ -833,64 +830,7 @@ int pci_proc_domain(struct pci_bus *bus)
 {
         struct pci_controller *hose = pci_bus_to_host(bus);
 
-        if (!(pci_flags & PCI_ENABLE_PROC_DOMAINS))
-                return 0;
-        if (pci_flags & PCI_COMPAT_DOMAIN_0)
-                return hose->global_number != 0;
-        return 1;
-}
-
-void pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
-                             struct resource *res)
-{
-        resource_size_t offset = 0, mask = (resource_size_t)-1;
-        struct pci_controller *hose = pci_bus_to_host(dev->bus);
-
-        if (!hose)
-                return;
-        if (res->flags & IORESOURCE_IO) {
-                offset = (unsigned long)hose->io_base_virt - _IO_BASE;
-                mask = 0xffffffffu;
-        } else if (res->flags & IORESOURCE_MEM)
-                offset = hose->pci_mem_offset;
-
-        region->start = (res->start - offset) & mask;
-        region->end = (res->end - offset) & mask;
-}
-EXPORT_SYMBOL(pcibios_resource_to_bus);
-
-void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
-                             struct pci_bus_region *region)
-{
-        resource_size_t offset = 0, mask = (resource_size_t)-1;
-        struct pci_controller *hose = pci_bus_to_host(dev->bus);
-
-        if (!hose)
-                return;
-        if (res->flags & IORESOURCE_IO) {
-                offset = (unsigned long)hose->io_base_virt - _IO_BASE;
-                mask = 0xffffffffu;
-        } else if (res->flags & IORESOURCE_MEM)
-                offset = hose->pci_mem_offset;
-        res->start = (region->start + offset) & mask;
-        res->end = (region->end + offset) & mask;
-}
-EXPORT_SYMBOL(pcibios_bus_to_resource);
-
-/* Fixup a bus resource into a linux resource */
-static void __devinit fixup_resource(struct resource *res, struct pci_dev *dev)
-{
-        struct pci_controller *hose = pci_bus_to_host(dev->bus);
-        resource_size_t offset = 0, mask = (resource_size_t)-1;
-
-        if (res->flags & IORESOURCE_IO) {
-                offset = (unsigned long)hose->io_base_virt - _IO_BASE;
-                mask = 0xffffffffu;
-        } else if (res->flags & IORESOURCE_MEM)
-                offset = hose->pci_mem_offset;
-
-        res->start = (res->start + offset) & mask;
-        res->end = (res->end + offset) & mask;
+        return 0;
 }
 
 /* This header fixup will do the resource fixup for all devices as they are
@@ -910,13 +850,7 @@ static void __devinit pcibios_fixup_resources(struct pci_dev *dev)
                 struct resource *res = dev->resource + i;
                 if (!res->flags)
                         continue;
-                /* On platforms that have PCI_PROBE_ONLY set, we don't
-                 * consider 0 as an unassigned BAR value. It's technically
-                 * a valid value, but linux doesn't like it... so when we can
-                 * re-assign things, we do so, but if we can't, we keep it
-                 * around and hope for the best...
-                 */
-                if (res->start == 0 && !(pci_flags & PCI_PROBE_ONLY)) {
+                if (res->start == 0) {
                         pr_debug("PCI:%s Resource %d %016llx-%016llx [%x]" \
                                                         "is unassigned\n",
                                  pci_name(dev), i,
@@ -929,18 +863,11 @@ static void __devinit pcibios_fixup_resources(struct pci_dev *dev)
                         continue;
                 }
 
-                pr_debug("PCI:%s Resource %d %016llx-%016llx [%x] fixup...\n",
+                pr_debug("PCI:%s Resource %d %016llx-%016llx [%x]\n",
                          pci_name(dev), i,
                          (unsigned long long)res->start,\
                          (unsigned long long)res->end,
                          (unsigned int)res->flags);
-
-                fixup_resource(res, dev);
-
-                pr_debug("PCI:%s            %016llx-%016llx\n",
-                         pci_name(dev),
-                         (unsigned long long)res->start,
-                         (unsigned long long)res->end);
         }
 }
 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pcibios_fixup_resources);
@@ -959,10 +886,6 @@ static int __devinit pcibios_uninitialized_bridge_resource(struct pci_bus *bus,
         u16 command;
         int i;
 
-        /* We don't do anything if PCI_PROBE_ONLY is set */
-        if (pci_flags & PCI_PROBE_ONLY)
-                return 0;
-
         /* Job is a bit different between memory and IO */
         if (res->flags & IORESOURCE_MEM) {
                 /* If the BAR is non-0 (res != pci_mem_offset) then it's
@@ -1037,9 +960,6 @@ static void __devinit pcibios_fixup_bridge(struct pci_bus *bus)
                          (unsigned long long)res->end,
                          (unsigned int)res->flags);
 
-                /* Perform fixup */
-                fixup_resource(res, dev);
-
                 /* Try to detect uninitialized P2P bridge resources,
                  * and clear them out so they get re-assigned later
                  */
@@ -1107,9 +1027,6 @@ EXPORT_SYMBOL(pcibios_fixup_bus);
 
 static int skip_isa_ioresource_align(struct pci_dev *dev)
 {
-        if ((pci_flags & PCI_CAN_SKIP_ISA_ALIGN) &&
-            !(dev->bus->bridge_ctl & PCI_BRIDGE_CTL_ISA))
-                return 1;
         return 0;
 }
 
@@ -1236,8 +1153,6 @@ void pcibios_allocate_bus_resources(struct pci_bus *bus)
                          * and as such ensure proper re-allocation
                          * later.
                          */
-                        if (pci_flags & PCI_REASSIGN_ALL_RSRC)
-                                goto clear_resource;
                         pr = pci_find_parent_resource(bus->self, res);
                         if (pr == res) {
                                 /* this happens when the generic PCI
@@ -1422,27 +1337,19 @@ void __init pcibios_resource_survey(void)
         list_for_each_entry(b, &pci_root_buses, node)
                 pcibios_allocate_bus_resources(b);
 
-        if (!(pci_flags & PCI_REASSIGN_ALL_RSRC)) {
-                pcibios_allocate_resources(0);
-                pcibios_allocate_resources(1);
-        }
+        pcibios_allocate_resources(0);
+        pcibios_allocate_resources(1);
 
         /* Before we start assigning unassigned resource, we try to reserve
          * the low IO area and the VGA memory area if they intersect the
          * bus available resources to avoid allocating things on top of them
          */
-        if (!(pci_flags & PCI_PROBE_ONLY)) {
-                list_for_each_entry(b, &pci_root_buses, node)
-                        pcibios_reserve_legacy_regions(b);
-        }
+        list_for_each_entry(b, &pci_root_buses, node)
+                pcibios_reserve_legacy_regions(b);
 
-        /* Now, if the platform didn't decide to blindly trust the firmware,
-         * we proceed to assigning things that were left unassigned
-         */
-        if (!(pci_flags & PCI_PROBE_ONLY)) {
-                pr_debug("PCI: Assigning unassigned resources...\n");
-                pci_assign_unassigned_resources();
-        }
+        /* Now proceed to assigning things that were left unassigned */
+        pr_debug("PCI: Assigning unassigned resources...\n");
+        pci_assign_unassigned_resources();
 }
 
 #ifdef CONFIG_HOTPLUG
@@ -1535,7 +1442,7 @@ static void __devinit pcibios_setup_phb_resources(struct pci_controller *hose, s
                 res->end = res->start + IO_SPACE_LIMIT;
                 res->flags = IORESOURCE_IO;
         }
-        pci_add_resource(resources, res);
+        pci_add_resource_offset(resources, res, hose->io_base_virt - _IO_BASE);
 
         pr_debug("PCI: PHB IO resource    = %016llx-%016llx [%lx]\n",
                  (unsigned long long)res->start,
@@ -1558,7 +1465,7 @@ static void __devinit pcibios_setup_phb_resources(struct pci_controller *hose, s
                         res->flags = IORESOURCE_MEM;
 
                 }
-                pci_add_resource(resources, res);
+                pci_add_resource_offset(resources, res, hose->pci_mem_offset);
 
                 pr_debug("PCI: PHB MEM resource %d = %016llx-%016llx [%lx]\n",
                         i, (unsigned long long)res->start,
diff --git a/arch/mips/fw/arc/cmdline.c b/arch/mips/fw/arc/cmdline.c
index 9fdf07e50f1..c0122a1dc58 100644
--- a/arch/mips/fw/arc/cmdline.c
+++ b/arch/mips/fw/arc/cmdline.c
@@ -7,6 +7,7 @@
  *
  * Copyright (C) 1996 David S. Miller (davem@davemloft.net)
  */
+#include <linux/bug.h>
 #include <linux/init.h>
 #include <linux/kernel.h>
 #include <linux/string.h>
diff --git a/arch/mips/fw/arc/identify.c b/arch/mips/fw/arc/identify.c
index 788060a53dc..54a33c756f6 100644
--- a/arch/mips/fw/arc/identify.c
+++ b/arch/mips/fw/arc/identify.c
@@ -11,6 +11,7 @@
  *
  * Copyright (C) 1996 David S. Miller (davem@davemloft.net)
  */
+#include <linux/bug.h>
 #include <linux/init.h>
 #include <linux/kernel.h>
 #include <linux/types.h>
diff --git a/arch/mips/include/asm/mman.h b/arch/mips/include/asm/mman.h
index 785b4ea4ec3..46d3da0d4b9 100644
--- a/arch/mips/include/asm/mman.h
+++ b/arch/mips/include/asm/mman.h
@@ -80,6 +80,10 @@
 #define MADV_HUGEPAGE   14              /* Worth backing with hugepages */
 #define MADV_NOHUGEPAGE 15              /* Not worth backing with hugepages */
 
+#define MADV_DONTDUMP   16              /* Explicity exclude from the core dump,
+                                           overrides the coredump filter bits */
+#define MADV_DODUMP     17              /* Clear the MADV_NODUMP flag */
+
 /* compatibility flags */
 #define MAP_FILE        0
 
diff --git a/arch/mips/include/asm/pci.h b/arch/mips/include/asm/pci.h
index 576397c6992..fcd4060f642 100644
--- a/arch/mips/include/asm/pci.h
+++ b/arch/mips/include/asm/pci.h
@@ -92,6 +92,7 @@ extern int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
 #include <asm/scatterlist.h>
 #include <linux/string.h>
 #include <asm/io.h>
+#include <asm-generic/pci-bridge.h>
 
 struct pci_dev;
 
@@ -112,12 +113,6 @@ static inline void pci_dma_burst_advice(struct pci_dev *pdev,
 }
 #endif
 
-extern void pcibios_resource_to_bus(struct pci_dev *dev,
-        struct pci_bus_region *region, struct resource *res);
-
-extern void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
-                                    struct pci_bus_region *region);
-
 #define pci_domain_nr(bus) ((struct pci_controller *)(bus)->sysdata)->index
 
 static inline int pci_proc_domain(struct pci_bus *bus)
@@ -145,8 +140,6 @@ static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel)
 #define arch_setup_msi_irqs arch_setup_msi_irqs
 #endif
 
-extern int pci_probe_only;
-
 extern char * (*pcibios_plat_setup)(char *str);
 
 #endif /* _ASM_PCI_H */
diff --git a/arch/mips/jz4740/board-qi_lb60.c b/arch/mips/jz4740/board-qi_lb60.c
index 639e3ce6c26..9a91fe9de69 100644
--- a/arch/mips/jz4740/board-qi_lb60.c
+++ b/arch/mips/jz4740/board-qi_lb60.c
@@ -418,6 +418,11 @@ static struct platform_device qi_lb60_charger_device = {
         },
 };
 
+/* audio */
+static struct platform_device qi_lb60_audio_device = {
+        .name = "qi-lb60-audio",
+        .id = -1,
+};
 
 static struct platform_device *jz_platform_devices[] __initdata = {
         &jz4740_udc_device,
@@ -434,6 +439,7 @@ static struct platform_device *jz_platform_devices[] __initdata = {
         &qi_lb60_gpio_keys,
         &qi_lb60_pwm_beeper,
         &qi_lb60_charger_device,
+        &qi_lb60_audio_device,
 };
 
 static void __init board_gpio_setup(void)
diff --git a/arch/mips/kernel/vdso.c b/arch/mips/kernel/vdso.c
index e5cdfd603f8..0f1af58b036 100644
--- a/arch/mips/kernel/vdso.c
+++ b/arch/mips/kernel/vdso.c
@@ -88,8 +88,7 @@ int arch_setup_additional_pages(struct linux_binprm *bprm, int uses_interp)
 
         ret = install_special_mapping(mm, addr, PAGE_SIZE,
                                       VM_READ|VM_EXEC|
-                                      VM_MAYREAD|VM_MAYWRITE|VM_MAYEXEC|
-                                      VM_ALWAYSDUMP,
+                                      VM_MAYREAD|VM_MAYWRITE|VM_MAYEXEC,
                                       &vdso_page);
 
         if (ret)
diff --git a/arch/mips/pci/fixup-cobalt.c b/arch/mips/pci/fixup-cobalt.c
index acacd1407c6..9553b14002d 100644
--- a/arch/mips/pci/fixup-cobalt.c
+++ b/arch/mips/pci/fixup-cobalt.c
@@ -51,67 +51,6 @@ static void qube_raq_galileo_early_fixup(struct pci_dev *dev)
 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_MARVELL, PCI_DEVICE_ID_MARVELL_GT64111,
          qube_raq_galileo_early_fixup);
 
-static void __devinit cobalt_legacy_ide_resource_fixup(struct pci_dev *dev,
-                                                       struct resource *res)
-{
-        struct pci_controller *hose = (struct pci_controller *)dev->sysdata;
-        unsigned long offset = hose->io_offset;
-        struct resource orig = *res;
-
-        if (!(res->flags & IORESOURCE_IO) ||
-            !(res->flags & IORESOURCE_PCI_FIXED))
-                return;
-
-        res->start -= offset;
-        res->end -= offset;
-        dev_printk(KERN_DEBUG, &dev->dev, "converted legacy %pR to bus %pR\n",
-                   &orig, res);
-}
-
-static void __devinit cobalt_legacy_ide_fixup(struct pci_dev *dev)
-{
-        u32 class;
-        u8 progif;
-
-        /*
-         * If the IDE controller is in legacy mode, pci_setup_device() fills in
-         * the resources with the legacy addresses that normally appear on the
-         * PCI bus, just as if we had read them from a BAR.
-         *
-         * However, with the GT-64111, those legacy addresses, e.g., 0x1f0,
-         * will never appear on the PCI bus because it converts memory accesses
-         * in the PCI I/O region (which is never at address zero) into I/O port
-         * accesses with no address translation.
-         *
-         * For example, if GT_DEF_PCI0_IO_BASE is 0x10000000, a load or store
-         * to physical address 0x100001f0 will become a PCI access to I/O port
-         * 0x100001f0.  There's no way to generate an access to I/O port 0x1f0,
-         * but the VT82C586 IDE controller does respond at 0x100001f0 because
-         * it only decodes the low 24 bits of the address.
-         *
-         * When this quirk runs, the pci_dev resources should contain bus
-         * addresses, not Linux I/O port numbers, so convert legacy addresses
-         * like 0x1f0 to bus addresses like 0x100001f0.  Later, we'll convert
-         * them back with pcibios_fixup_bus() or pcibios_bus_to_resource().
-         */
-        class = dev->class >> 8;
-        if (class != PCI_CLASS_STORAGE_IDE)
-                return;
-
-        pci_read_config_byte(dev, PCI_CLASS_PROG, &progif);
-        if ((progif & 1) == 0) {
-                cobalt_legacy_ide_resource_fixup(dev, &dev->resource[0]);
-                cobalt_legacy_ide_resource_fixup(dev, &dev->resource[1]);
-        }
-        if ((progif & 4) == 0) {
-                cobalt_legacy_ide_resource_fixup(dev, &dev->resource[2]);
-                cobalt_legacy_ide_resource_fixup(dev, &dev->resource[3]);
-        }
-}
-
-DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_1,
-          cobalt_legacy_ide_fixup);
-
 static void qube_raq_via_bmIDE_fixup(struct pci_dev *dev)
 {
         unsigned short cfgword;
diff --git a/arch/mips/pci/pci-bcm1480.c b/arch/mips/pci/pci-bcm1480.c
index af8c3199696..37b52dc3d27 100644
--- a/arch/mips/pci/pci-bcm1480.c
+++ b/arch/mips/pci/pci-bcm1480.c
@@ -204,7 +204,7 @@ static int __init bcm1480_pcibios_init(void)
         uint64_t reg;
 
         /* CFE will assign PCI resources */
-        pci_probe_only = 1;
+        pci_set_flags(PCI_PROBE_ONLY);
 
         /* Avoid ISA compat ranges.  */
         PCIBIOS_MIN_IO = 0x00008000UL;
diff --git a/arch/mips/pci/pci-ip27.c b/arch/mips/pci/pci-ip27.c
index 193e9494f98..0fbe4c0c170 100644
--- a/arch/mips/pci/pci-ip27.c
+++ b/arch/mips/pci/pci-ip27.c
@@ -50,7 +50,7 @@ int __cpuinit bridge_probe(nasid_t nasid, int widget_id, int masterwid)
         bridge_t *bridge;
         int slot;
 
-        pci_probe_only = 1;
+        pci_set_flags(PCI_PROBE_ONLY);
 
         printk("a bridge\n");
 
diff --git a/arch/mips/pci/pci-lantiq.c b/arch/mips/pci/pci-lantiq.c
index be1e1afe12c..030c77e7926 100644
--- a/arch/mips/pci/pci-lantiq.c
+++ b/arch/mips/pci/pci-lantiq.c
@@ -270,7 +270,8 @@ static int __devinit ltq_pci_probe(struct platform_device *pdev)
 {
         struct ltq_pci_data *ltq_pci_data =
                 (struct ltq_pci_data *) pdev->dev.platform_data;
-        pci_probe_only = 0;
+
+        pci_clear_flags(PCI_PROBE_ONLY);
         ltq_pci_irq_map = ltq_pci_data->irq;
         ltq_pci_membase = ioremap_nocache(PCI_CR_BASE_ADDR, PCI_CR_SIZE);
         ltq_pci_mapped_cfg =
diff --git a/arch/mips/pci/pci-sb1250.c b/arch/mips/pci/pci-sb1250.c
index 1711e8e101b..dd97f3a83ba 100644
--- a/arch/mips/pci/pci-sb1250.c
+++ b/arch/mips/pci/pci-sb1250.c
@@ -213,7 +213,7 @@ static int __init sb1250_pcibios_init(void)
         uint64_t reg;
 
         /* CFE will assign PCI resources */
-        pci_probe_only = 1;
+        pci_set_flags(PCI_PROBE_ONLY);
 
         /* Avoid ISA compat ranges.  */
         PCIBIOS_MIN_IO = 0x00008000UL;
diff --git a/arch/mips/pci/pci-xlr.c b/arch/mips/pci/pci-xlr.c
index 3d701a962ef..1644805a673 100644
--- a/arch/mips/pci/pci-xlr.c
+++ b/arch/mips/pci/pci-xlr.c
@@ -292,7 +292,7 @@ int pcibios_plat_dev_init(struct pci_dev *dev)
 static int __init pcibios_init(void)
 {
         /* PSB assigns PCI resources */
-        pci_probe_only = 1;
+        pci_set_flags(PCI_PROBE_ONLY);
         pci_config_base = ioremap(DEFAULT_PCI_CONFIG_BASE, 16 << 20);
 
         /* Extend IO port for memory mapped io */
diff --git a/arch/mips/pci/pci.c b/arch/mips/pci/pci.c
index 15521505ebe..0514866fa92 100644
--- a/arch/mips/pci/pci.c
+++ b/arch/mips/pci/pci.c
@@ -20,16 +20,9 @@
 #include <asm/cpu-info.h>
 
 /*
- * Indicate whether we respect the PCI setup left by the firmware.
- *
- * Make this long-lived  so that we know when shutting down
- * whether we probed only or not.
+ * If PCI_PROBE_ONLY in pci_flags is set, we don't change any PCI resource
+ * assignments.
  */
-int pci_probe_only;
-
-#define PCI_ASSIGN_ALL_BUSSES   1
-
-unsigned int pci_probe = PCI_ASSIGN_ALL_BUSSES;
 
 /*
  * The PCI controller list.
@@ -92,11 +85,12 @@ static void __devinit pcibios_scanbus(struct pci_controller *hose)
         if (!hose->iommu)
                 PCI_DMA_BUS_IS_PHYS = 1;
 
-        if (hose->get_busno && pci_probe_only)
+        if (hose->get_busno && pci_has_flag(PCI_PROBE_ONLY))
                 next_busno = (*hose->get_busno)();
 
-        pci_add_resource(&resources, hose->mem_resource);
-        pci_add_resource(&resources, hose->io_resource);
+        pci_add_resource_offset(&resources,
+                                hose->mem_resource, hose->mem_offset);
+        pci_add_resource_offset(&resources, hose->io_resource, hose->io_offset);
         bus = pci_scan_root_bus(NULL, next_busno, hose->pci_ops, hose,
                                 &resources);
         if (!bus)
@@ -115,7 +109,7 @@ static void __devinit pcibios_scanbus(struct pci_controller *hose)
                         need_domain_info = 1;
                 }
 
-                if (!pci_probe_only) {
+                if (!pci_has_flag(PCI_PROBE_ONLY)) {
                         pci_bus_size_bridges(bus);
                         pci_bus_assign_resources(bus);
                         pci_enable_bridges(bus);
@@ -241,7 +235,7 @@ static int pcibios_enable_resources(struct pci_dev *dev, int mask)
 
 unsigned int pcibios_assign_all_busses(void)
 {
-        return (pci_probe & PCI_ASSIGN_ALL_BUSSES) ? 1 : 0;
+        return 1;
 }
 
 int pcibios_enable_device(struct pci_dev *dev, int mask)
@@ -254,42 +248,13 @@ int pcibios_enable_device(struct pci_dev *dev, int mask)
         return pcibios_plat_dev_init(dev);
 }
 
-static void pcibios_fixup_device_resources(struct pci_dev *dev,
-        struct pci_bus *bus)
-{
-        /* Update device resources.  */
-        struct pci_controller *hose = (struct pci_controller *)bus->sysdata;
-        unsigned long offset = 0;
-        int i;
-
-        for (i = 0; i < PCI_NUM_RESOURCES; i++) {
-                if (!dev->resource[i].start)
-                        continue;
-                if (dev->resource[i].flags & IORESOURCE_IO)
-                        offset = hose->io_offset;
-                else if (dev->resource[i].flags & IORESOURCE_MEM)
-                        offset = hose->mem_offset;
-
-                dev->resource[i].start += offset;
-                dev->resource[i].end += offset;
-        }
-}
-
 void __devinit pcibios_fixup_bus(struct pci_bus *bus)
 {
-        /* Propagate hose info into the subordinate devices.  */
-
         struct pci_dev *dev = bus->self;
 
-        if (pci_probe_only && dev &&
+        if (pci_has_flag(PCI_PROBE_ONLY) && dev &&
             (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
                 pci_read_bridge_bases(bus);
-                pcibios_fixup_device_resources(dev, bus);
-        }
-
-        list_for_each_entry(dev, &bus->devices, bus_list) {
-                if ((dev->class >> 8) != PCI_CLASS_BRIDGE_PCI)
-                        pcibios_fixup_device_resources(dev, bus);
         }
 }
 
@@ -299,40 +264,7 @@ pcibios_update_irq(struct pci_dev *dev, int irq)
         pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
 }
 
-void pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
-                         struct resource *res)
-{
-        struct pci_controller *hose = (struct pci_controller *)dev->sysdata;
-        unsigned long offset = 0;
-
-        if (res->flags & IORESOURCE_IO)
-                offset = hose->io_offset;
-        else if (res->flags & IORESOURCE_MEM)
-                offset = hose->mem_offset;
-
-        region->start = res->start - offset;
-        region->end = res->end - offset;
-}
-
-void __devinit
-pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
-                        struct pci_bus_region *region)
-{
-        struct pci_controller *hose = (struct pci_controller *)dev->sysdata;
-        unsigned long offset = 0;
-
-        if (res->flags & IORESOURCE_IO)
-                offset = hose->io_offset;
-        else if (res->flags & IORESOURCE_MEM)
-                offset = hose->mem_offset;
-
-        res->start = region->start + offset;
-        res->end = region->end + offset;
-}
-
 #ifdef CONFIG_HOTPLUG
-EXPORT_SYMBOL(pcibios_resource_to_bus);
-EXPORT_SYMBOL(pcibios_bus_to_resource);
 EXPORT_SYMBOL(PCIBIOS_MIN_IO);
 EXPORT_SYMBOL(PCIBIOS_MIN_MEM);
 #endif
diff --git a/arch/mn10300/Kconfig b/arch/mn10300/Kconfig
index 8f1c40d5817..3aa3de01715 100644
--- a/arch/mn10300/Kconfig
+++ b/arch/mn10300/Kconfig
@@ -5,6 +5,7 @@ config MN10300
         select GENERIC_IRQ_SHOW
         select HAVE_ARCH_TRACEHOOK
         select HAVE_ARCH_KGDB
+        select HAVE_NMI_WATCHDOG if MN10300_WD_TIMER
 
 config AM33_2
         def_bool n
diff --git a/arch/mn10300/include/asm/pci.h b/arch/mn10300/include/asm/pci.h
index 6095a28561d..8137c25c4e1 100644
--- a/arch/mn10300/include/asm/pci.h
+++ b/arch/mn10300/include/asm/pci.h
@@ -85,22 +85,6 @@ extern int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
 /* implement the pci_ DMA API in terms of the generic device dma_ one */
 #include <asm-generic/pci-dma-compat.h>
 
-/**
- * pcibios_resource_to_bus - convert resource to PCI bus address
- * @dev: device which owns this resource
- * @region: converted bus-centric region (start,end)
- * @res: resource to convert
- *
- * Convert a resource to a PCI device bus address or bus window.
- */
-extern void pcibios_resource_to_bus(struct pci_dev *dev,
-                                    struct pci_bus_region *region,
-                                    struct resource *res);
-
-extern void pcibios_bus_to_resource(struct pci_dev *dev,
-                                    struct resource *res,
-                                    struct pci_bus_region *region);
-
 static inline struct resource *
 pcibios_select_root(struct pci_dev *pdev, struct resource *res)
 {
diff --git a/arch/mn10300/include/asm/reset-regs.h b/arch/mn10300/include/asm/reset-regs.h
index 10c7502a113..8ca2a42d365 100644
--- a/arch/mn10300/include/asm/reset-regs.h
+++ b/arch/mn10300/include/asm/reset-regs.h
@@ -17,10 +17,6 @@
 
 #ifdef __KERNEL__
 
-#ifdef CONFIG_MN10300_WD_TIMER
-#define ARCH_HAS_NMI_WATCHDOG           /* See include/linux/nmi.h */
-#endif
-
 /*
  * watchdog timer registers
  */
diff --git a/arch/mn10300/unit-asb2305/pci.c b/arch/mn10300/unit-asb2305/pci.c
index a7c5f08ca9f..6dce9fc2cf3 100644
--- a/arch/mn10300/unit-asb2305/pci.c
+++ b/arch/mn10300/unit-asb2305/pci.c
@@ -32,8 +32,7 @@ struct pci_ops *pci_root_ops;
  * insert specific PCI bus resources instead of using the platform-level bus
  * resources directly for the PCI root bus.
  *
- * These are configured and inserted by pcibios_init() and are attached to the
- * root bus by pcibios_fixup_bus().
+ * These are configured and inserted by pcibios_init().
  */
 static struct resource pci_ioport_resource = {
         .name   = "PCI IO",
@@ -78,52 +77,6 @@ static inline int __query(const struct pci_bus *bus, unsigned int devfn)
 }
 
 /*
- * translate Linuxcentric addresses to PCI bus addresses
- */
-void pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
-                             struct resource *res)
-{
-        if (res->flags & IORESOURCE_IO) {
-                region->start = (res->start & 0x00ffffff);
-                region->end   = (res->end   & 0x00ffffff);
-        }
-
-        if (res->flags & IORESOURCE_MEM) {
-                region->start = (res->start & 0x03ffffff) | MEM_PAGING_REG;
-                region->end   = (res->end   & 0x03ffffff) | MEM_PAGING_REG;
-        }
-
-#if 0
-        printk(KERN_DEBUG "RES->BUS: %lx-%lx => %lx-%lx\n",
-               res->start, res->end, region->start, region->end);
-#endif
-}
-EXPORT_SYMBOL(pcibios_resource_to_bus);
-
-/*
- * translate PCI bus addresses to Linuxcentric addresses
- */
-void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
-                             struct pci_bus_region *region)
-{
-        if (res->flags & IORESOURCE_IO) {
-                res->start = (region->start & 0x00ffffff) | 0xbe000000;
-                res->end   = (region->end   & 0x00ffffff) | 0xbe000000;
-        }
-
-        if (res->flags & IORESOURCE_MEM) {
-                res->start = (region->start & 0x03ffffff) | 0xb8000000;
-                res->end   = (region->end   & 0x03ffffff) | 0xb8000000;
-        }
-
-#if 0
-        printk(KERN_INFO "BUS->RES: %lx-%lx => %lx-%lx\n",
-               region->start, region->end, res->start, res->end);
-#endif
-}
-EXPORT_SYMBOL(pcibios_bus_to_resource);
-
-/*
  *
  */
 static int pci_ampci_read_config_byte(struct pci_bus *bus, unsigned int devfn,
@@ -364,9 +317,6 @@ static void __devinit pcibios_fixup_device_resources(struct pci_dev *dev)
                 if (!dev->resource[i].flags)
                         continue;
 
-                region.start = dev->resource[i].start;
-                region.end = dev->resource[i].end;
-                pcibios_bus_to_resource(dev, &dev->resource[i], &region);
                 if (is_valid_resource(dev, i))
                         pci_claim_resource(dev, i);
         }
@@ -397,6 +347,7 @@ void __devinit pcibios_fixup_bus(struct pci_bus *bus)
  */
 static int __init pcibios_init(void)
 {
+        resource_size_t io_offset, mem_offset;
         LIST_HEAD(resources);
 
         ioport_resource.start   = 0xA0000000;
@@ -420,8 +371,13 @@ static int __init pcibios_init(void)
         printk(KERN_INFO "PCI: Probing PCI hardware [mempage %08x]\n",
                MEM_PAGING_REG);
 
-        pci_add_resource(&resources, &pci_ioport_resource);
-        pci_add_resource(&resources, &pci_iomem_resource);
+        io_offset = pci_ioport_resource.start -
+            (pci_ioport_resource.start & 0x00ffffff);
+        mem_offset = pci_iomem_resource.start -
+            ((pci_iomem_resource.start & 0x03ffffff) | MEM_PAGING_REG);
+
+        pci_add_resource_offset(&resources, &pci_ioport_resource, io_offset);
+        pci_add_resource_offset(&resources, &pci_iomem_resource, mem_offset);
         pci_root_bus = pci_scan_root_bus(NULL, 0, &pci_direct_ampci, NULL,
                                          &resources);
 
diff --git a/arch/openrisc/Kconfig b/arch/openrisc/Kconfig
index bc428b5f126..a4787197d8f 100644
--- a/arch/openrisc/Kconfig
+++ b/arch/openrisc/Kconfig
@@ -16,6 +16,7 @@ config OPENRISC
         select GENERIC_IRQ_SHOW
         select GENERIC_IOMAP
         select GENERIC_CPU_DEVICES
+        select GENERIC_ATOMIC64
 
 config MMU
         def_bool y
diff --git a/arch/openrisc/include/asm/page.h b/arch/openrisc/include/asm/page.h
index b041b344b22..108906f991d 100644
--- a/arch/openrisc/include/asm/page.h
+++ b/arch/openrisc/include/asm/page.h
@@ -71,9 +71,6 @@ typedef struct page *pgtable_t;
 #define __pgd(x)        ((pgd_t) { (x) })
 #define __pgprot(x)     ((pgprot_t) { (x) })
 
-extern unsigned long memory_start;
-extern unsigned long memory_end;
-
 #endif /* !__ASSEMBLY__ */
 
 
@@ -94,8 +91,7 @@ extern unsigned long memory_end;
 
 #define pfn_valid(pfn)          ((pfn) < max_mapnr)
 
-#define virt_addr_valid(kaddr)  (((void *)(kaddr) >= (void *)PAGE_OFFSET) && \
-                                ((void *)(kaddr) < (void *)memory_end))
+#define virt_addr_valid(kaddr)  (pfn_valid(virt_to_pfn(kaddr)))
 
 #endif /* __ASSEMBLY__ */
 
diff --git a/arch/openrisc/include/asm/pgtable.h b/arch/openrisc/include/asm/pgtable.h
index 043505d7f68..14c900cfd30 100644
--- a/arch/openrisc/include/asm/pgtable.h
+++ b/arch/openrisc/include/asm/pgtable.h
@@ -455,7 +455,6 @@ static inline void update_mmu_cache(struct vm_area_struct *vma,
  * No page table caches to initialise
  */
 #define pgtable_cache_init()            do { } while (0)
-#define io_remap_page_range             remap_page_range
 
 typedef pte_t *pte_addr_t;
 
diff --git a/arch/openrisc/include/asm/processor.h b/arch/openrisc/include/asm/processor.h
index bb54c97b978..f7516fa78b5 100644
--- a/arch/openrisc/include/asm/processor.h
+++ b/arch/openrisc/include/asm/processor.h
@@ -81,8 +81,8 @@ extern inline void prepare_to_copy(struct task_struct *tsk)
 #define INIT_THREAD  { }
 
 
-#define KSTK_EIP(tsk)   (task_pt_regs(tsk)->pc);
-#define KSTK_ESP(tsk)   (task_pt_regs(tsk)->sp);
+#define KSTK_EIP(tsk)   (task_pt_regs(tsk)->pc)
+#define KSTK_ESP(tsk)   (task_pt_regs(tsk)->sp)
 
 
 extern int kernel_thread(int (*fn)(void *), void * arg, unsigned long flags);
diff --git a/arch/openrisc/include/asm/ptrace.h b/arch/openrisc/include/asm/ptrace.h
index e612ce4512c..4651a737591 100644
--- a/arch/openrisc/include/asm/ptrace.h
+++ b/arch/openrisc/include/asm/ptrace.h
@@ -73,9 +73,13 @@ struct pt_regs {
                 };
         };
         long  pc;
+        /* For restarting system calls:
+         * Set to syscall number for syscall exceptions,
+         * -1 for all other exceptions.
+         */
         long  orig_gpr11;       /* For restarting system calls */
-        long  syscallno;        /* Syscall number (used by strace) */
         long dummy;             /* Cheap alignment fix */
+        long dummy2;            /* Cheap alignment fix */
 };
 
 /* TODO: Rename this to REDZONE because that's what it is */
diff --git a/arch/openrisc/include/asm/syscall.h b/arch/openrisc/include/asm/syscall.h
index 9f0337055d2..b752bb67891 100644
--- a/arch/openrisc/include/asm/syscall.h
+++ b/arch/openrisc/include/asm/syscall.h
@@ -25,7 +25,7 @@
 static inline int
 syscall_get_nr(struct task_struct *task, struct pt_regs *regs)
 {
-        return regs->syscallno ? regs->syscallno : -1;
+        return regs->orig_gpr11;
 }
 
 static inline void
@@ -50,10 +50,7 @@ static inline void
 syscall_set_return_value(struct task_struct *task, struct pt_regs *regs,
                          int error, long val)
 {
-        if (error)
-                regs->gpr[11] = -error;
-        else
-                regs->gpr[11] = val;
+        regs->gpr[11] = (long) error ?: val;
 }
 
 static inline void
diff --git a/arch/openrisc/include/asm/uaccess.h b/arch/openrisc/include/asm/uaccess.h
index c310e45b538..f5abaa0ffc3 100644
--- a/arch/openrisc/include/asm/uaccess.h
+++ b/arch/openrisc/include/asm/uaccess.h
@@ -26,7 +26,6 @@
 #include <linux/thread_info.h>
 #include <linux/prefetch.h>
 #include <linux/string.h>
-#include <linux/thread_info.h>
 #include <asm/page.h>
 
 #define VERIFY_READ     0
diff --git a/arch/openrisc/kernel/entry.S b/arch/openrisc/kernel/entry.S
index d5f9c35a583..6e61af8682b 100644
--- a/arch/openrisc/kernel/entry.S
+++ b/arch/openrisc/kernel/entry.S
@@ -95,7 +95,6 @@ handler:							;\
         /* r1, EPCR, ESR a already saved */                     ;\
         l.sw    PT_GPR2(r1),r2                                  ;\
         l.sw    PT_GPR3(r1),r3                                  ;\
-        l.sw    PT_ORIG_GPR11(r1),r11                           ;\
         /* r4 already save */                                   ;\
         l.sw    PT_GPR5(r1),r5                                  ;\
         l.sw    PT_GPR6(r1),r6                                  ;\
@@ -125,7 +124,9 @@ handler:							;\
         /* r30 already save */                                  ;\
 /*        l.sw    PT_GPR30(r1),r30*/                                    ;\
         l.sw    PT_GPR31(r1),r31                                        ;\
-        l.sw    PT_SYSCALLNO(r1),r0
+        /* Store -1 in orig_gpr11 for non-syscall exceptions */ ;\
+        l.addi  r30,r0,-1                                       ;\
+        l.sw    PT_ORIG_GPR11(r1),r30
 
 #define UNHANDLED_EXCEPTION(handler,vector)                     \
         .global handler                                         ;\
@@ -133,7 +134,6 @@ handler:							;\
         /* r1, EPCR, ESR already saved */                       ;\
         l.sw    PT_GPR2(r1),r2                                  ;\
         l.sw    PT_GPR3(r1),r3                                  ;\
-        l.sw    PT_ORIG_GPR11(r1),r11                           ;\
         l.sw    PT_GPR5(r1),r5                                  ;\
         l.sw    PT_GPR6(r1),r6                                  ;\
         l.sw    PT_GPR7(r1),r7                                  ;\
@@ -162,7 +162,9 @@ handler:							;\
         /* r31 already saved */                                 ;\
         l.sw    PT_GPR30(r1),r30                                        ;\
 /*        l.sw    PT_GPR31(r1),r31      */                              ;\
-        l.sw    PT_SYSCALLNO(r1),r0                             ;\
+        /* Store -1 in orig_gpr11 for non-syscall exceptions */ ;\
+        l.addi  r30,r0,-1                                       ;\
+        l.sw    PT_ORIG_GPR11(r1),r30                           ;\
         l.addi  r3,r1,0                                         ;\
         /* r4 is exception EA */                                ;\
         l.addi  r5,r0,vector                                    ;\
@@ -554,6 +556,7 @@ ENTRY(_sys_call_handler)
         l.sw    PT_GPR9(r1),r9
         /* r10 already saved */
         l.sw    PT_GPR11(r1),r11
+        /* orig_gpr11 must be set for syscalls */
         l.sw    PT_ORIG_GPR11(r1),r11
         /* r12,r13 already saved */
 
@@ -567,9 +570,6 @@ ENTRY(_sys_call_handler)
         /* r30 is the only register we clobber in the fast path */
         /* r30 already saved */
 /*      l.sw    PT_GPR30(r1),r30 */
-        /* This is used by do_signal to determine whether to check for
-         * syscall restart or not */
-        l.sw    PT_SYSCALLNO(r1),r11
 
 _syscall_check_trace_enter:
         /* If TIF_SYSCALL_TRACE is set, then we want to do syscall tracing */
@@ -731,7 +731,7 @@ _syscall_trace_enter:
          * so that we can do the syscall for real and return to the syscall
          * hot path.
          */
-        l.lwz   r11,PT_SYSCALLNO(r1)
+        l.lwz   r11,PT_GPR11(r1)
         l.lwz   r3,PT_GPR3(r1)
         l.lwz   r4,PT_GPR4(r1)
         l.lwz   r5,PT_GPR5(r1)
diff --git a/arch/openrisc/kernel/head.S b/arch/openrisc/kernel/head.S
index c75018d2264..1088b5fca3b 100644
--- a/arch/openrisc/kernel/head.S
+++ b/arch/openrisc/kernel/head.S
@@ -26,6 +26,7 @@
 #include <asm/cache.h>
 #include <asm/spr_defs.h>
 #include <asm/asm-offsets.h>
+#include <linux/of_fdt.h>
 
 #define tophys(rd,rs)                           \
         l.movhi rd,hi(-KERNELBASE)              ;\
@@ -440,6 +441,9 @@ _dispatch_do_ipage_fault:
         __HEAD
         .global _start
 _start:
+        /* save kernel parameters */
+        l.or    r25,r0,r3       /* pointer to fdt */
+
         /*
          * ensure a deterministic start
          */
@@ -471,7 +475,6 @@ _start:
         CLEAR_GPR(r22)
         CLEAR_GPR(r23)
         CLEAR_GPR(r24)
-        CLEAR_GPR(r25)
         CLEAR_GPR(r26)
         CLEAR_GPR(r27)
         CLEAR_GPR(r28)
@@ -565,6 +568,18 @@ enable_mmu:
         // reset the simulation counters
         l.nop 5
 
+        /* check fdt header magic word */
+        l.lwz   r3,0(r25)       /* load magic from fdt into r3 */
+        l.movhi r4,hi(OF_DT_HEADER)
+        l.ori   r4,r4,lo(OF_DT_HEADER)
+        l.sfeq  r3,r4
+        l.bf    _fdt_found
+         l.nop
+        /* magic number mismatch, set fdt pointer to null */
+        l.or    r25,r0,r0
+_fdt_found:
+        /* pass fdt pointer to or32_early_setup in r3 */
+        l.or    r3,r0,r25
         LOAD_SYMBOL_2_GPR(r24, or32_early_setup)
         l.jalr r24
          l.nop
diff --git a/arch/openrisc/kernel/ptrace.c b/arch/openrisc/kernel/ptrace.c
index 7259047d5f9..6deacb6b95a 100644
--- a/arch/openrisc/kernel/ptrace.c
+++ b/arch/openrisc/kernel/ptrace.c
@@ -188,11 +188,11 @@ asmlinkage long do_syscall_trace_enter(struct pt_regs *regs)
                  */
                 ret = -1L;
 
-        audit_syscall_entry(audit_arch(), regs->syscallno,
+        audit_syscall_entry(audit_arch(), regs->gpr[11],
                             regs->gpr[3], regs->gpr[4],
                             regs->gpr[5], regs->gpr[6]);
 
-        return ret ? : regs->syscallno;
+        return ret ? : regs->gpr[11];
 }
 
 asmlinkage void do_syscall_trace_leave(struct pt_regs *regs)
diff --git a/arch/openrisc/kernel/setup.c b/arch/openrisc/kernel/setup.c
index 1422f747f52..bf5eba22ce9 100644
--- a/arch/openrisc/kernel/setup.c
+++ b/arch/openrisc/kernel/setup.c
@@ -207,18 +207,18 @@ void __init setup_cpuinfo(void)
  * Handles the pointer to the device tree that this kernel is to use
  * for establishing the available platform devices.
  *
- * For now, this is limited to using the built-in device tree.  In the future,
- * it is intended that this function will take a pointer to the device tree
- * that is potentially built-in, but potentially also passed in by the
- * bootloader, or discovered by some equally clever means...
+ * Falls back on built-in device tree in case null pointer is passed.
  */
 
-void __init or32_early_setup(void)
+void __init or32_early_setup(unsigned int fdt)
 {
-
-        early_init_devtree(__dtb_start);
-
-        printk(KERN_INFO "Compiled-in FDT at 0x%p\n", __dtb_start);
+        if (fdt) {
+                early_init_devtree((void*) fdt);
+                printk(KERN_INFO "FDT at 0x%08x\n", fdt);
+        } else {
+                early_init_devtree(__dtb_start);
+                printk(KERN_INFO "Compiled-in FDT at %p\n", __dtb_start);
+        }
 }
 
 static int __init openrisc_device_probe(void)
diff --git a/arch/openrisc/kernel/signal.c b/arch/openrisc/kernel/signal.c
index 95207ab0c99..e970743251a 100644
--- a/arch/openrisc/kernel/signal.c
+++ b/arch/openrisc/kernel/signal.c
@@ -102,10 +102,7 @@ asmlinkage long _sys_rt_sigreturn(struct pt_regs *regs)
                 goto badframe;
 
         sigdelsetmask(&set, ~_BLOCKABLE);
-        spin_lock_irq(&current->sighand->siglock);
-        current->blocked = set;
-        recalc_sigpending();
-        spin_unlock_irq(&current->sighand->siglock);
+        set_current_blocked(&set);
 
         if (restore_sigcontext(regs, &frame->uc.uc_mcontext))
                 goto badframe;
@@ -189,8 +186,8 @@ static inline void __user *get_sigframe(struct k_sigaction *ka,
  * trampoline which performs the syscall sigreturn, or a provided
  * user-mode trampoline.
  */
-static void setup_rt_frame(int sig, struct k_sigaction *ka, siginfo_t *info,
-                           sigset_t *set, struct pt_regs *regs)
+static int setup_rt_frame(int sig, struct k_sigaction *ka, siginfo_t *info,
+                          sigset_t *set, struct pt_regs *regs)
 {
         struct rt_sigframe *frame;
         unsigned long return_ip;
@@ -247,31 +244,27 @@ static void setup_rt_frame(int sig, struct k_sigaction *ka, siginfo_t *info,
         /* actually move the usp to reflect the stacked frame */
         regs->sp = (unsigned long)frame;
 
-        return;
+        return 0;
 
 give_sigsegv:
-        if (sig == SIGSEGV)
-                ka->sa.sa_handler = SIG_DFL;
-        force_sig(SIGSEGV, current);
+        force_sigsegv(sig, current);
+        return -EFAULT;
 }
 
-static inline void
+static inline int
 handle_signal(unsigned long sig,
               siginfo_t *info, struct k_sigaction *ka,
               sigset_t *oldset, struct pt_regs *regs)
 {
-        setup_rt_frame(sig, ka, info, oldset, regs);
+        int ret;
 
-        if (ka->sa.sa_flags & SA_ONESHOT)
-                ka->sa.sa_handler = SIG_DFL;
+        ret = setup_rt_frame(sig, ka, info, oldset, regs);
+        if (ret)
+                return ret;
 
-        spin_lock_irq(&current->sighand->siglock);
-        sigorsets(&current->blocked, &current->blocked, &ka->sa.sa_mask);
-        if (!(ka->sa.sa_flags & SA_NODEFER))
-                sigaddset(&current->blocked, sig);
-        recalc_sigpending();
+        block_sigmask(ka, sig);
 
-        spin_unlock_irq(&current->sighand->siglock);
+        return 0;
 }
 
 /*
@@ -312,7 +305,7 @@ void do_signal(struct pt_regs *regs)
          * below mean that the syscall executed to completion and no
          * restart is necessary.
          */
-        if (regs->syscallno) {
+        if (regs->orig_gpr11) {
                 int restart = 0;
 
                 switch (regs->gpr[11]) {
@@ -360,13 +353,13 @@ void do_signal(struct pt_regs *regs)
                         oldset = &current->blocked;
 
                 /* Whee!  Actually deliver the signal.  */
-                handle_signal(signr, &info, &ka, oldset, regs);
-                /* a signal was successfully delivered; the saved
-                 * sigmask will have been stored in the signal frame,
-                 * and will be restored by sigreturn, so we can simply
-                 * clear the TIF_RESTORE_SIGMASK flag */
-                if (test_thread_flag(TIF_RESTORE_SIGMASK))
+                if (!handle_signal(signr, &info, &ka, oldset, regs)) {
+                        /* a signal was successfully delivered; the saved
+                         * sigmask will have been stored in the signal frame,
+                         * and will be restored by sigreturn, so we can simply
+                         * clear the TIF_RESTORE_SIGMASK flag */
                         clear_thread_flag(TIF_RESTORE_SIGMASK);
+                }
 
                 tracehook_signal_handler(signr, &info, &ka, regs,
                                          test_thread_flag(TIF_SINGLESTEP));
diff --git a/arch/openrisc/kernel/time.c b/arch/openrisc/kernel/time.c
index bd946ef1623..7c52e9494a8 100644
--- a/arch/openrisc/kernel/time.c
+++ b/arch/openrisc/kernel/time.c
@@ -125,16 +125,13 @@ irqreturn_t __irq_entry timer_interrupt(struct pt_regs *regs)
 
 static __init void openrisc_clockevent_init(void)
 {
-        clockevents_calc_mult_shift(&clockevent_openrisc_timer,
-                                    cpuinfo.clock_frequency, 4);
+        clockevent_openrisc_timer.cpumask = cpumask_of(0);
 
         /* We only have 28 bits */
-        clockevent_openrisc_timer.max_delta_ns =
-            clockevent_delta2ns((u32) 0x0fffffff, &clockevent_openrisc_timer);
-        clockevent_openrisc_timer.min_delta_ns =
-            clockevent_delta2ns(1, &clockevent_openrisc_timer);
-        clockevent_openrisc_timer.cpumask = cpumask_of(0);
-        clockevents_register_device(&clockevent_openrisc_timer);
+        clockevents_config_and_register(&clockevent_openrisc_timer,
+                                        cpuinfo.clock_frequency,
+                                        100, 0x0fffffff);
+
 }
 
 /**
diff --git a/arch/openrisc/kernel/traps.c b/arch/openrisc/kernel/traps.c
index a4ec44a052b..a2ee12948f4 100644
--- a/arch/openrisc/kernel/traps.c
+++ b/arch/openrisc/kernel/traps.c
@@ -115,6 +115,7 @@ void dump_stack(void)
 
         show_stack(current, &stack);
 }
+EXPORT_SYMBOL(dump_stack);
 
 void show_registers(struct pt_regs *regs)
 {
@@ -145,8 +146,8 @@ void show_registers(struct pt_regs *regs)
                regs->gpr[24], regs->gpr[25], regs->gpr[26], regs->gpr[27]);
         printk("GPR28: %08lx GPR29: %08lx GPR30: %08lx GPR31: %08lx\n",
                regs->gpr[28], regs->gpr[29], regs->gpr[30], regs->gpr[31]);
-        printk("  RES: %08lx oGPR11: %08lx syscallno: %08lx\n",
-               regs->gpr[11], regs->orig_gpr11, regs->syscallno);
+        printk("  RES: %08lx oGPR11: %08lx\n",
+               regs->gpr[11], regs->orig_gpr11);
 
         printk("Process %s (pid: %d, stackpage=%08lx)\n",
                current->comm, current->pid, (unsigned long)current);
@@ -207,8 +208,8 @@ void nommu_dump_state(struct pt_regs *regs,
                regs->gpr[24], regs->gpr[25], regs->gpr[26], regs->gpr[27]);
         printk("GPR28: %08lx GPR29: %08lx GPR30: %08lx GPR31: %08lx\n",
                regs->gpr[28], regs->gpr[29], regs->gpr[30], regs->gpr[31]);
-        printk("  RES: %08lx oGPR11: %08lx syscallno: %08lx\n",
-               regs->gpr[11], regs->orig_gpr11, regs->syscallno);
+        printk("  RES: %08lx oGPR11: %08lx\n",
+               regs->gpr[11], regs->orig_gpr11);
 
         printk("Process %s (pid: %d, stackpage=%08lx)\n",
                ((struct task_struct *)(__pa(current)))->comm,
diff --git a/arch/openrisc/mm/init.c b/arch/openrisc/mm/init.c
index 359dcb20fe8..736f6b2f30a 100644
--- a/arch/openrisc/mm/init.c
+++ b/arch/openrisc/mm/init.c
@@ -222,8 +222,7 @@ void __init mem_init(void)
 {
         int codesize, reservedpages, datasize, initsize;
 
-        if (!mem_map)
-                BUG();
+        BUG_ON(!mem_map);
 
         set_max_mapnr_init();
 
diff --git a/arch/parisc/include/asm/mman.h b/arch/parisc/include/asm/mman.h
index f5b7bf5fba6..12219ebce86 100644
--- a/arch/parisc/include/asm/mman.h
+++ b/arch/parisc/include/asm/mman.h
@@ -62,6 +62,10 @@
 #define MADV_HUGEPAGE   67              /* Worth backing with hugepages */
 #define MADV_NOHUGEPAGE 68              /* Not worth backing with hugepages */
 
+#define MADV_DONTDUMP   69              /* Explicity exclude from the core dump,
+                                           overrides the coredump filter bits */
+#define MADV_DODUMP     70              /* Clear the MADV_NODUMP flag */
+
 /* compatibility flags */
 #define MAP_FILE        0
 #define MAP_VARIABLE    0
diff --git a/arch/parisc/include/asm/pci.h b/arch/parisc/include/asm/pci.h
index 2242a5c636c..3234f492d57 100644
--- a/arch/parisc/include/asm/pci.h
+++ b/arch/parisc/include/asm/pci.h
@@ -82,38 +82,8 @@ struct pci_hba_data {
 
 #ifdef CONFIG_64BIT
 #define PCI_F_EXTEND            0xffffffff00000000UL
-#define PCI_IS_LMMIO(hba,a)     pci_is_lmmio(hba,a)
-
-/* We need to know if an address is LMMMIO or GMMIO.
- * LMMIO requires mangling and GMMIO we must use as-is.
- */
-static __inline__  int pci_is_lmmio(struct pci_hba_data *hba, unsigned long a)
-{
-        return(((a) & PCI_F_EXTEND) == PCI_F_EXTEND);
-}
-
-/*
-** Convert between PCI (IO_VIEW) addresses and processor (PA_VIEW) addresses.
-** See pci.c for more conversions used by Generic PCI code.
-**
-** Platform characteristics/firmware guarantee that
-**      (1) PA_VIEW - IO_VIEW = lmmio_offset for both LMMIO and ELMMIO
-**      (2) PA_VIEW == IO_VIEW for GMMIO
-*/
-#define PCI_BUS_ADDR(hba,a)     (PCI_IS_LMMIO(hba,a)    \
-                ?  ((a) - hba->lmmio_space_offset)      /* mangle LMMIO */ \
-                : (a))                                  /* GMMIO */
-#define PCI_HOST_ADDR(hba,a)    (((a) & PCI_F_EXTEND) == 0 \
-                ? (a) + hba->lmmio_space_offset \
-                : (a))
-
 #else   /* !CONFIG_64BIT */
-
-#define PCI_BUS_ADDR(hba,a)     (a)
-#define PCI_HOST_ADDR(hba,a)    (a)
 #define PCI_F_EXTEND            0UL
-#define PCI_IS_LMMIO(hba,a)     (1)     /* 32-bit doesn't support GMMIO */
-
 #endif /* !CONFIG_64BIT */
 
 /*
@@ -245,14 +215,6 @@ static inline void pci_dma_burst_advice(struct pci_dev *pdev,
 }
 #endif
 
-extern void
-pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
-                         struct resource *res);
-
-extern void
-pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
-                        struct pci_bus_region *region);
-
 static inline void pcibios_penalize_isa_irq(int irq, int active)
 {
         /* We don't need to penalize isa irq's */
diff --git a/arch/parisc/kernel/pci.c b/arch/parisc/kernel/pci.c
index 9efd9740531..74d544b1cd2 100644
--- a/arch/parisc/kernel/pci.c
+++ b/arch/parisc/kernel/pci.c
@@ -195,58 +195,6 @@ void __init pcibios_init_bus(struct pci_bus *bus)
         pci_write_config_word(dev, PCI_BRIDGE_CONTROL, bridge_ctl);
 }
 
-/* called by drivers/pci/setup-bus.c:pci_setup_bridge().  */
-void __devinit pcibios_resource_to_bus(struct pci_dev *dev,
-                struct pci_bus_region *region, struct resource *res)
-{
-#ifdef CONFIG_64BIT
-        struct pci_hba_data *hba = HBA_DATA(dev->bus->bridge->platform_data);
-#endif
-
-        if (res->flags & IORESOURCE_IO) {
-                /*
-                ** I/O space may see busnumbers here. Something
-                ** in the form of 0xbbxxxx where bb is the bus num
-                ** and xxxx is the I/O port space address.
-                ** Remaining address translation are done in the
-                ** PCI Host adapter specific code - ie dino_out8.
-                */
-                region->start = PCI_PORT_ADDR(res->start);
-                region->end   = PCI_PORT_ADDR(res->end);
-        } else if (res->flags & IORESOURCE_MEM) {
-                /* Convert MMIO addr to PCI addr (undo global virtualization) */
-                region->start = PCI_BUS_ADDR(hba, res->start);
-                region->end   = PCI_BUS_ADDR(hba, res->end);
-        }
-
-        DBG_RES("pcibios_resource_to_bus(%02x %s [%lx,%lx])\n",
-                dev->bus->number, res->flags & IORESOURCE_IO ? "IO" : "MEM",
-                region->start, region->end);
-}
-
-void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
-                              struct pci_bus_region *region)
-{
-#ifdef CONFIG_64BIT
-        struct pci_hba_data *hba = HBA_DATA(dev->bus->bridge->platform_data);
-#endif
-
-        if (res->flags & IORESOURCE_MEM) {
-                res->start = PCI_HOST_ADDR(hba, region->start);
-                res->end = PCI_HOST_ADDR(hba, region->end);
-        }
-
-        if (res->flags & IORESOURCE_IO) {
-                res->start = region->start;
-                res->end = region->end;
-        }
-}
-
-#ifdef CONFIG_HOTPLUG
-EXPORT_SYMBOL(pcibios_resource_to_bus);
-EXPORT_SYMBOL(pcibios_bus_to_resource);
-#endif
-
 /*
  * pcibios align resources() is called every time generic PCI code
  * wants to generate a new address. The process of looking for
diff --git a/arch/parisc/math-emu/fpudispatch.c b/arch/parisc/math-emu/fpudispatch.c
index 6e28f9f4c62..673b73e8420 100644
--- a/arch/parisc/math-emu/fpudispatch.c
+++ b/arch/parisc/math-emu/fpudispatch.c
@@ -50,6 +50,7 @@
 #define FPUDEBUG 0
 
 #include "float.h"
+#include <linux/bug.h>
 #include <linux/kernel.h>
 #include <asm/processor.h>
 /* #include <sys/debug.h> */
diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
index 303703d716f..d219ebecabf 100644
--- a/arch/powerpc/Kconfig
+++ b/arch/powerpc/Kconfig
@@ -134,6 +134,7 @@ config PPC
         select HAVE_HW_BREAKPOINT if PERF_EVENTS && PPC_BOOK3S_64
         select HAVE_GENERIC_HARDIRQS
         select HAVE_SPARSE_IRQ
+        select SPARSE_IRQ
         select IRQ_PER_CPU
         select IRQ_DOMAIN
         select GENERIC_IRQ_SHOW
@@ -377,13 +378,16 @@ config CRASH_DUMP
           The same kernel binary can be used as production kernel and dump
           capture kernel.
 
-config PHYP_DUMP
-        bool "Hypervisor-assisted dump (EXPERIMENTAL)"
-        depends on PPC_PSERIES && EXPERIMENTAL
+config FA_DUMP
+        bool "Firmware-assisted dump"
+        depends on PPC64 && PPC_RTAS && CRASH_DUMP
         help
-          Hypervisor-assisted dump is meant to be a kdump replacement
-          offering robustness and speed not possible without system
-          hypervisor assistance.
+          A robust mechanism to get reliable kernel crash dump with
+          assistance from firmware. This approach does not use kexec,
+          instead firmware assists in booting the kdump kernel
+          while preserving memory contents. Firmware-assisted dump
+          is meant to be a kdump replacement offering robustness and
+          speed not possible without system firmware assistance.
 
           If unsure, say "N"
 
@@ -612,7 +616,7 @@ endmenu
 
 config ISA_DMA_API
         bool
-        default !PPC_ISERIES || PCI
+        default PCI
 
 menu "Bus options"
 
diff --git a/arch/powerpc/Kconfig.debug b/arch/powerpc/Kconfig.debug
index 4ccb2a009f7..72d55dbc611 100644
--- a/arch/powerpc/Kconfig.debug
+++ b/arch/powerpc/Kconfig.debug
@@ -196,13 +196,6 @@ config PPC_EARLY_DEBUG_MAPLE
         help
           Select this to enable early debugging for Maple.
 
-config PPC_EARLY_DEBUG_ISERIES
-        bool "iSeries HV Console"
-        depends on PPC_ISERIES
-        help
-          Select this to enable early debugging for legacy iSeries. You need
-          to hit "Ctrl-x Ctrl-x" to see the messages on the console.
-
 config PPC_EARLY_DEBUG_PAS_REALMODE
         bool "PA Semi real mode"
         depends on PPC_PASEMI
diff --git a/arch/powerpc/Makefile b/arch/powerpc/Makefile
index b8b105c01c6..6524c6e2189 100644
--- a/arch/powerpc/Makefile
+++ b/arch/powerpc/Makefile
@@ -157,6 +157,7 @@ core-y				+= arch/powerpc/kernel/ \
                                    arch/powerpc/net/
 core-$(CONFIG_XMON)             += arch/powerpc/xmon/
 core-$(CONFIG_KVM)              += arch/powerpc/kvm/
+core-$(CONFIG_PERF_EVENTS)      += arch/powerpc/perf/
 
 drivers-$(CONFIG_OPROFILE)      += arch/powerpc/oprofile/
 
diff --git a/arch/powerpc/boot/Makefile b/arch/powerpc/boot/Makefile
index 8844a17ce8e..e8461cb18d0 100644
--- a/arch/powerpc/boot/Makefile
+++ b/arch/powerpc/boot/Makefile
@@ -184,7 +184,6 @@ image-$(CONFIG_PPC_EFIKA)		+= zImage.chrp
 image-$(CONFIG_PPC_PMAC)                += zImage.pmac
 image-$(CONFIG_PPC_HOLLY)               += dtbImage.holly
 image-$(CONFIG_PPC_PRPMC2800)           += dtbImage.prpmc2800
-image-$(CONFIG_PPC_ISERIES)             += zImage.iseries
 image-$(CONFIG_DEFAULT_UIMAGE)          += uImage
 image-$(CONFIG_EPAPR_BOOT)              += zImage.epapr
 
@@ -247,7 +246,7 @@ image-$(CONFIG_ASP834x)			+= dtbImage.asp834x-redboot
 image-$(CONFIG_MPC8540_ADS)             += cuImage.mpc8540ads
 image-$(CONFIG_MPC8560_ADS)             += cuImage.mpc8560ads
 image-$(CONFIG_MPC85xx_CDS)             += cuImage.mpc8541cds \
-                                           cuImage.mpc8548cds \
+                                           cuImage.mpc8548cds_32b \
                                            cuImage.mpc8555cds
 image-$(CONFIG_MPC85xx_MDS)             += cuImage.mpc8568mds
 image-$(CONFIG_MPC85xx_DS)              += cuImage.mpc8544ds \
@@ -311,12 +310,6 @@ $(obj)/dtbImage.%: vmlinux $(wrapperbits) $(obj)/%.dtb
 $(obj)/vmlinux.strip: vmlinux
         $(STRIP) -s -R .comment $< -o $@
 
-# The iseries hypervisor won't take an ET_DYN executable, so this
-# changes the type (byte 17) in the file to ET_EXEC (2).
-$(obj)/zImage.iseries: vmlinux
-        $(STRIP) -s -R .comment $< -o $@
-        printf "\x02" | dd of=$@ conv=notrunc bs=1 seek=17
-
 $(obj)/uImage: vmlinux $(wrapperbits)
         $(call if_changed,wrap,uboot)
 
@@ -364,7 +357,7 @@ install: $(CONFIGURE) $(addprefix $(obj)/, $(image-y))
 # anything not in $(targets)
 clean-files += $(image-) $(initrd-) cuImage.* dtbImage.* treeImage.* \
         zImage zImage.initrd zImage.chrp zImage.coff zImage.holly \
-        zImage.iseries zImage.miboot zImage.pmac zImage.pseries \
+        zImage.miboot zImage.pmac zImage.pseries \
         zImage.maple simpleImage.* otheros.bld *.dtb
 
 # clean up files cached by wrapper
diff --git a/arch/powerpc/boot/dts/a4m072.dts b/arch/powerpc/boot/dts/a4m072.dts
new file mode 100644
index 00000000000..fabe7b7d5f1
--- /dev/null
+++ b/arch/powerpc/boot/dts/a4m072.dts
@@ -0,0 +1,168 @@
+/*
+ * a4m072 board Device Tree Source
+ *
+ * Copyright (C) 2011 DENX Software Engineering GmbH
+ * Heiko Schocher <hs@denx.de>
+ *
+ * Copyright (C) 2007 Semihalf
+ * Marian Balakowicz <m8@semihalf.com>
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+/include/ "mpc5200b.dtsi"
+
+/ {
+        model = "anonymous,a4m072";
+        compatible = "anonymous,a4m072";
+
+        soc5200@f0000000 {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "fsl,mpc5200b-immr";
+                ranges = <0 0xf0000000 0x0000c000>;
+                reg = <0xf0000000 0x00000100>;
+                bus-frequency = <0>; /* From boot loader */
+                system-frequency = <0>; /* From boot loader */
+
+                cdm@200 {
+                        fsl,init-ext-48mhz-en = <0x0>;
+                        fsl,init-fd-enable = <0x01>;
+                        fsl,init-fd-counters = <0x3333>;
+                };
+
+                timer@600 {
+                        fsl,has-wdt;
+                };
+
+                gpt3: timer@630 { /* General Purpose Timer in GPIO mode */
+                        compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio";
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                };
+
+                gpt4: timer@640 { /* General Purpose Timer in GPIO mode */
+                        compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio";
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                };
+
+                gpt5: timer@650 { /* General Purpose Timer in GPIO mode */
+                        compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio";
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                };
+
+                spi@f00 {
+                        status = "disabled";
+                };
+
+                psc@2000 {
+                        compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
+                        reg = <0x2000 0x100>;
+                        interrupts = <2 1 0>;
+                };
+
+                psc@2200 {
+                        compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
+                        reg = <0x2200 0x100>;
+                        interrupts = <2 2 0>;
+                };
+
+                psc@2400 {
+                        compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
+                        reg = <0x2400 0x100>;
+                        interrupts = <2 3 0>;
+                };
+
+                psc@2600 {
+                        status = "disabled";
+                };
+
+                psc@2800 {
+                        status = "disabled";
+                };
+
+                psc@2c00 {
+                        compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
+                        reg = <0x2c00 0x100>;
+                        interrupts = <2 4 0>;
+                };
+
+                ethernet@3000 {
+                        phy-handle = <&phy0>;
+                };
+
+                mdio@3000 {
+                        phy0: ethernet-phy@1f {
+                                reg = <0x1f>;
+                                interrupts = <1 2 0>; /* IRQ 2 active low */
+                        };
+                };
+
+                i2c@3d00 {
+                        status = "disabled";
+                };
+
+                i2c@3d40 {
+                        hwmon@2e {
+                                compatible = "nsc,lm87";
+                                reg = <0x2e>;
+                        };
+                        rtc@51 {
+                                compatible = "nxp,rtc8564";
+                                reg = <0x51>;
+                        };
+                };
+        };
+
+        localbus {
+                compatible = "fsl,mpc5200b-lpb","simple-bus";
+                #address-cells = <2>;
+                #size-cells = <1>;
+                ranges = <0 0 0xfe000000 0x02000000
+                          1 0 0x62000000 0x00400000
+                          2 0 0x64000000 0x00200000
+                          3 0 0x66000000 0x01000000
+                          6 0 0x68000000 0x01000000
+                          7 0 0x6a000000 0x00000004>;
+
+                flash@0,0 {
+                        compatible = "cfi-flash";
+                        reg = <0 0 0x02000000>;
+                        bank-width = <2>;
+                        #size-cells = <1>;
+                        #address-cells = <1>;
+                };
+                sram0@1,0 {
+                        compatible = "mtd-ram";
+                        reg = <1 0x00000 0x00400000>;
+                        bank-width = <2>;
+                };
+        };
+
+        pci@f0000d00 {
+                #interrupt-cells = <1>;
+                #size-cells = <2>;
+                #address-cells = <3>;
+                device_type = "pci";
+                compatible = "fsl,mpc5200-pci";
+                reg = <0xf0000d00 0x100>;
+                interrupt-map-mask = <0xf800 0 0 7>;
+                interrupt-map = <
+                                 /* IDSEL 0x16 */
+                                 0xc000 0 0 1 &mpc5200_pic 1 3 3
+                                 0xc000 0 0 2 &mpc5200_pic 1 3 3
+                                 0xc000 0 0 3 &mpc5200_pic 1 3 3
+                                 0xc000 0 0 4 &mpc5200_pic 1 3 3>;
+                clock-frequency = <0>; /* From boot loader */
+                interrupts = <2 8 0 2 9 0 2 10 0>;
+                bus-range = <0 0>;
+                ranges = <0x42000000 0 0x80000000 0x80000000 0 0x10000000
+                          0x02000000 0 0x90000000 0x90000000 0 0x10000000
+                          0x01000000 0 0x00000000 0xa0000000 0 0x01000000>;
+        };
+};
diff --git a/arch/powerpc/boot/dts/bluestone.dts b/arch/powerpc/boot/dts/bluestone.dts
index 74876f73740..7bda373f10e 100644
--- a/arch/powerpc/boot/dts/bluestone.dts
+++ b/arch/powerpc/boot/dts/bluestone.dts
@@ -33,7 +33,7 @@
         aliases {
                 ethernet0 = &EMAC0;
                 serial0 = &UART0;
-                //serial1 = &UART1; --gcl missing UART1 label
+                serial1 = &UART1;
         };
 
         cpus {
@@ -52,7 +52,7 @@
                         d-cache-size = <32768>;
                         dcr-controller;
                         dcr-access-method = "native";
-                        //next-level-cache = <&L2C0>; --gcl missing L2C0 label
+                        next-level-cache = <&L2C0>;
                 };
         };
 
@@ -117,6 +117,16 @@
                 dcr-reg = <0x00c 0x002>;
         };
 
+        L2C0: l2c {
+                compatible = "ibm,l2-cache-apm82181", "ibm,l2-cache";
+                dcr-reg = <0x020 0x008
+                           0x030 0x008>;
+                cache-line-size = <32>;
+                cache-size = <262144>;
+                interrupt-parent = <&UIC1>;
+                interrupts = <11 1>;
+        };
+
         plb {
                 compatible = "ibm,plb4";
                 #address-cells = <2>;
@@ -182,6 +192,53 @@
                                                 reg = <0x001a0000 0x00060000>;
                                         };
                                 };
+
+                                ndfc@1,0 {
+                                        compatible = "ibm,ndfc";
+                                        reg = <0x00000003 0x00000000 0x00002000>;
+                                        ccr = <0x00001000>;
+                                        bank-settings = <0x80002222>;
+                                        #address-cells = <1>;
+                                        #size-cells = <1>;
+                                        /* 2Gb Nand Flash */
+                                        nand {
+                                                #address-cells = <1>;
+                                                #size-cells = <1>;
+
+                                                partition@0 {
+                                                        label = "firmware";
+                                                        reg   = <0x00000000 0x00C00000>;
+                                                };
+                                                partition@c00000 {
+                                                        label = "environment";
+                                                        reg   = <0x00C00000 0x00B00000>;
+                                                };
+                                                partition@1700000 {
+                                                        label = "kernel";
+                                                        reg   = <0x01700000 0x00E00000>;
+                                                };
+                                                partition@2500000 {
+                                                        label = "root";
+                                                        reg   = <0x02500000 0x08200000>;
+                                                };
+                                                partition@a700000 {
+                                                        label = "device-tree";
+                                                        reg   = <0x0A700000 0x00B00000>;
+                                                };
+                                                partition@b200000 {
+                                                        label = "config";
+                                                        reg   = <0x0B200000 0x00D00000>;
+                                                };
+                                                partition@bf00000 {
+                                                        label = "diag";
+                                                        reg   = <0x0BF00000 0x00C00000>;
+                                                };
+                                                partition@cb00000 {
+                                                        label = "vendor";
+                                                        reg   = <0x0CB00000 0x3500000>;
+                                                };
+                                        };
+                                };
                         };
 
                         UART0: serial@ef600300 {
@@ -195,11 +252,36 @@
                                 interrupts = <0x1 0x4>;
                         };
 
+                        UART1: serial@ef600400 {
+                                device_type = "serial";
+                                compatible = "ns16550";
+                                reg = <0xef600400 0x00000008>;
+                                virtual-reg = <0xef600400>;
+                                clock-frequency = <0>; /* Filled in by U-Boot */
+                                current-speed = <0>; /* Filled in by U-Boot */
+                                interrupt-parent = <&UIC0>;
+                                interrupts = <0x1 0x4>;
+                        };
+
                         IIC0: i2c@ef600700 {
                                 compatible = "ibm,iic";
                                 reg = <0xef600700 0x00000014>;
                                 interrupt-parent = <&UIC0>;
                                 interrupts = <0x2 0x4>;
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                rtc@68 {
+                                        compatible = "stm,m41t80";
+                                        reg = <0x68>;
+                                        interrupt-parent = <&UIC0>;
+                                        interrupts = <0x9 0x8>;
+                                };
+                                sttm@4C {
+                                        compatible = "adm,adm1032";
+                                        reg = <0x4C>;
+                                        interrupt-parent = <&UIC1>;
+                                        interrupts = <0x1E 0x8>; /* CPU_THERNAL_L */
+                                };
                         };
 
                         IIC1: i2c@ef600800 {
@@ -250,5 +332,46 @@
                         };
                 };
 
+                PCIE0: pciex@d00000000 {
+                        device_type = "pci";
+                        #interrupt-cells = <1>;
+                        #size-cells = <2>;
+                        #address-cells = <3>;
+                        compatible = "ibm,plb-pciex-apm821xx", "ibm,plb-pciex";
+                        primary;
+                        port = <0x0>; /* port number */
+                        reg = <0x0000000d 0x00000000 0x20000000 /* Config space access */
+                               0x0000000c 0x08010000 0x00001000>;       /* Registers */
+                        dcr-reg = <0x100 0x020>;
+                        sdr-base = <0x300>;
+
+                        /* Outbound ranges, one memory and one IO,
+                         * later cannot be changed
+                         */
+                        ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x00000000 0x00000000 0x80000000
+                                  0x02000000 0x00000000 0x00000000 0x0000000f 0x00000000 0x00000000 0x00100000
+                                  0x01000000 0x00000000 0x00000000 0x0000000f 0x80000000 0x00000000 0x00010000>;
+
+                        /* Inbound 2GB range starting at 0 */
+                        dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
+
+                        /* This drives busses 40 to 0x7f */
+                        bus-range = <0x40 0x7f>;
+
+                        /* Legacy interrupts (note the weird polarity, the bridge seems
+                         * to invert PCIe legacy interrupts).
+                         * We are de-swizzling here because the numbers are actually for
+                         * port of the root complex virtual P2P bridge. But I want
+                         * to avoid putting a node for it in the tree, so the numbers
+                         * below are basically de-swizzled numbers.
+                         * The real slot is on idsel 0, so the swizzling is 1:1
+                         */
+                        interrupt-map-mask = <0x0 0x0 0x0 0x7>;
+                        interrupt-map = <
+                                0x0 0x0 0x0 0x1 &UIC3 0xc 0x4 /* swizzled int A */
+                                0x0 0x0 0x0 0x2 &UIC3 0xd 0x4 /* swizzled int B */
+                                0x0 0x0 0x0 0x3 &UIC3 0xe 0x4 /* swizzled int C */
+                                0x0 0x0 0x0 0x4 &UIC3 0xf 0x4 /* swizzled int D */>;
+                };
         };
 };
diff --git a/arch/powerpc/boot/dts/fsl/mpc8536si-post.dtsi b/arch/powerpc/boot/dts/fsl/mpc8536si-post.dtsi
index b37da56018b..c8b2daa40ac 100644
--- a/arch/powerpc/boot/dts/fsl/mpc8536si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/mpc8536si-post.dtsi
@@ -202,7 +202,7 @@
 /include/ "pq3-etsec1-timer-0.dtsi"
 
         usb@22000 {
-                compatible = "fsl,mpc8536-usb2-mph", "fsl-usb2-mph";
+                compatible = "fsl-usb2-mph-v1.2", "fsl,mpc8536-usb2-mph", "fsl-usb2-mph";
                 reg = <0x22000 0x1000>;
                 #address-cells = <1>;
                 #size-cells = <0>;
@@ -210,7 +210,7 @@
         };
 
         usb@23000 {
-                compatible = "fsl,mpc8536-usb2-mph", "fsl-usb2-mph";
+                compatible = "fsl-usb2-mph-v1.2", "fsl,mpc8536-usb2-mph", "fsl-usb2-mph";
                 reg = <0x23000 0x1000>;
                 #address-cells = <1>;
                 #size-cells = <0>;
diff --git a/arch/powerpc/boot/dts/fsl/mpc8548si-post.dtsi b/arch/powerpc/boot/dts/fsl/mpc8548si-post.dtsi
index 9d8023a69d7..579d76cb8e3 100644
--- a/arch/powerpc/boot/dts/fsl/mpc8548si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/mpc8548si-post.dtsi
@@ -89,6 +89,21 @@
         };
 };
 
+&rio {
+        compatible = "fsl,srio";
+        interrupts = <48 2 0 0>;
+        #address-cells = <2>;
+        #size-cells = <2>;
+        fsl,srio-rmu-handle = <&rmu>;
+        ranges;
+
+        port1 {
+                #address-cells = <2>;
+                #size-cells = <2>;
+                cell-index = <1>;
+        };
+};
+
 &soc {
         #address-cells = <1>;
         #size-cells = <1>;
@@ -134,6 +149,7 @@
 
 /include/ "pq3-sec2.1-0.dtsi"
 /include/ "pq3-mpic.dtsi"
+/include/ "pq3-rmu-0.dtsi"
 
         global-utilities@e0000 {
                 compatible = "fsl,mpc8548-guts";
diff --git a/arch/powerpc/boot/dts/fsl/mpc8548si-pre.dtsi b/arch/powerpc/boot/dts/fsl/mpc8548si-pre.dtsi
index 289f1218d75..720422d8352 100644
--- a/arch/powerpc/boot/dts/fsl/mpc8548si-pre.dtsi
+++ b/arch/powerpc/boot/dts/fsl/mpc8548si-pre.dtsi
@@ -43,7 +43,9 @@
                 serial0 = &serial0;
                 serial1 = &serial1;
                 ethernet0 = &enet0;
-                ethernet1 = &enet2;
+                ethernet1 = &enet1;
+                ethernet2 = &enet2;
+                ethernet3 = &enet3;
                 pci0 = &pci0;
                 pci1 = &pci1;
                 pci2 = &pci2;
diff --git a/arch/powerpc/boot/dts/fsl/p1010si-post.dtsi b/arch/powerpc/boot/dts/fsl/p1010si-post.dtsi
index a97d1263372..0bde9ee8afa 100644
--- a/arch/powerpc/boot/dts/fsl/p1010si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p1010si-post.dtsi
@@ -156,6 +156,9 @@
 
 /include/ "pq3-dma-0.dtsi"
 /include/ "pq3-usb2-dr-0.dtsi"
+        usb@22000 {
+                compatible = "fsl-usb2-dr-v1.6", "fsl-usb2-dr";
+        };
 /include/ "pq3-esdhc-0.dtsi"
         sdhc@2e000 {
                 compatible = "fsl,p1010-esdhc", "fsl,esdhc";
diff --git a/arch/powerpc/boot/dts/fsl/p1020si-post.dtsi b/arch/powerpc/boot/dts/fsl/p1020si-post.dtsi
index 5de5fc35131..68cc5e7f647 100644
--- a/arch/powerpc/boot/dts/fsl/p1020si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p1020si-post.dtsi
@@ -142,7 +142,13 @@
 
 /include/ "pq3-dma-0.dtsi"
 /include/ "pq3-usb2-dr-0.dtsi"
+        usb@22000 {
+                compatible = "fsl-usb2-dr-v1.6", "fsl-usb2-dr";
+        };
 /include/ "pq3-usb2-dr-1.dtsi"
+        usb@23000 {
+                compatible = "fsl-usb2-dr-v1.6", "fsl-usb2-dr";
+        };
 
 /include/ "pq3-esdhc-0.dtsi"
         sdhc@2e000 {
diff --git a/arch/powerpc/boot/dts/fsl/p1021si-post.dtsi b/arch/powerpc/boot/dts/fsl/p1021si-post.dtsi
index 38ba54d1e32..4252ef85fb7 100644
--- a/arch/powerpc/boot/dts/fsl/p1021si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p1021si-post.dtsi
@@ -142,8 +142,15 @@
 
 /include/ "pq3-dma-0.dtsi"
 /include/ "pq3-usb2-dr-0.dtsi"
+        usb@22000 {
+                compatible = "fsl-usb2-dr-v1.6", "fsl-usb2-dr";
+        };
 
 /include/ "pq3-esdhc-0.dtsi"
+        sdhc@2e000 {
+                sdhci,auto-cmd12;
+        };
+
 /include/ "pq3-sec3.3-0.dtsi"
 
 /include/ "pq3-mpic.dtsi"
diff --git a/arch/powerpc/boot/dts/fsl/p1022si-post.dtsi b/arch/powerpc/boot/dts/fsl/p1022si-post.dtsi
index ff9ed1d8792..06216b8c0af 100644
--- a/arch/powerpc/boot/dts/fsl/p1022si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p1022si-post.dtsi
@@ -35,7 +35,11 @@
 &lbc {
         #address-cells = <2>;
         #size-cells = <1>;
-        compatible = "fsl,p1022-elbc", "fsl,elbc", "simple-bus";
+        /*
+         * The localbus on the P1022 is not a simple-bus because of the eLBC
+         * pin muxing when the DIU is enabled.
+         */
+        compatible = "fsl,p1022-elbc", "fsl,elbc";
         interrupts = <19 2 0 0>;
 };
 
@@ -199,7 +203,13 @@
 
 /include/ "pq3-dma-0.dtsi"
 /include/ "pq3-usb2-dr-0.dtsi"
+        usb@22000 {
+                compatible = "fsl-usb2-dr-v1.6", "fsl-usb2-dr";
+        };
 /include/ "pq3-usb2-dr-1.dtsi"
+        usb@23000 {
+                compatible = "fsl-usb2-dr-v1.6", "fsl-usb2-dr";
+        };
 
 /include/ "pq3-esdhc-0.dtsi"
         sdhc@2e000 {
diff --git a/arch/powerpc/boot/dts/fsl/p1023si-post.dtsi b/arch/powerpc/boot/dts/fsl/p1023si-post.dtsi
index b06bb4cc1fe..941fa159cef 100644
--- a/arch/powerpc/boot/dts/fsl/p1023si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p1023si-post.dtsi
@@ -142,6 +142,9 @@
 
 /include/ "pq3-dma-0.dtsi"
 /include/ "pq3-usb2-dr-0.dtsi"
+        usb@22000 {
+                compatible = "fsl-usb2-dr-v1.6", "fsl-usb2-dr";
+        };
 
         crypto: crypto@300000 {
                 compatible = "fsl,sec-v4.2", "fsl,sec-v4.0";
diff --git a/arch/powerpc/boot/dts/fsl/p2020si-post.dtsi b/arch/powerpc/boot/dts/fsl/p2020si-post.dtsi
index 332e9e75e6c..884e01bcb24 100644
--- a/arch/powerpc/boot/dts/fsl/p2020si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p2020si-post.dtsi
@@ -171,6 +171,9 @@
 
 /include/ "pq3-dma-0.dtsi"
 /include/ "pq3-usb2-dr-0.dtsi"
+        usb@22000 {
+                compatible = "fsl-usb2-dr-v1.6", "fsl-usb2-dr";
+        };
 /include/ "pq3-etsec1-0.dtsi"
 /include/ "pq3-etsec1-timer-0.dtsi"
 
diff --git a/arch/powerpc/boot/dts/fsl/p2041si-post.dtsi b/arch/powerpc/boot/dts/fsl/p2041si-post.dtsi
index 234a399ddeb..531eab82c6c 100644
--- a/arch/powerpc/boot/dts/fsl/p2041si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p2041si-post.dtsi
@@ -309,12 +309,14 @@
 /include/ "qoriq-gpio-0.dtsi"
 /include/ "qoriq-usb2-mph-0.dtsi"
                 usb0: usb@210000 {
+                        compatible = "fsl-usb2-mph-v1.6", "fsl,mpc85xx-usb2-mph", "fsl-usb2-mph";
                         phy_type = "utmi";
                         port0;
                 };
 
 /include/ "qoriq-usb2-dr-0.dtsi"
                 usb1: usb@211000 {
+                        compatible = "fsl-usb2-dr-v1.6", "fsl,mpc85xx-usb2-dr", "fsl-usb2-dr";
                         dr_mode = "host";
                         phy_type = "utmi";
                 };
diff --git a/arch/powerpc/boot/dts/fsl/p3041si-post.dtsi b/arch/powerpc/boot/dts/fsl/p3041si-post.dtsi
index d41d08de7f7..af4ebc8009e 100644
--- a/arch/powerpc/boot/dts/fsl/p3041si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p3041si-post.dtsi
@@ -336,12 +336,14 @@
 /include/ "qoriq-gpio-0.dtsi"
 /include/ "qoriq-usb2-mph-0.dtsi"
                 usb0: usb@210000 {
+                        compatible = "fsl-usb2-mph-v1.6", "fsl-usb2-mph";
                         phy_type = "utmi";
                         port0;
                 };
 
 /include/ "qoriq-usb2-dr-0.dtsi"
                 usb1: usb@211000 {
+                        compatible = "fsl-usb2-dr-v1.6", "fsl,mpc85xx-usb2-dr", "fsl-usb2-dr";
                         dr_mode = "host";
                         phy_type = "utmi";
                 };
diff --git a/arch/powerpc/boot/dts/fsl/p3060si-post.dtsi b/arch/powerpc/boot/dts/fsl/p3060si-post.dtsi
index a63edd195ae..b3e56929eee 100644
--- a/arch/powerpc/boot/dts/fsl/p3060si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p3060si-post.dtsi
@@ -291,6 +291,12 @@
 /include/ "qoriq-duart-1.dtsi"
 /include/ "qoriq-gpio-0.dtsi"
 /include/ "qoriq-usb2-mph-0.dtsi"
+        usb@210000 {
+                compatible = "fsl-usb2-mph-v2.2", "fsl,mpc85xx-usb2-mph", "fsl-usb2-mph";
+        };
 /include/ "qoriq-usb2-dr-0.dtsi"
+        usb@211000 {
+                compatible = "fsl-usb2-dr-v2.2", "fsl,mpc85xx-usb2-dr", "fsl-usb2-dr";
+        };
 /include/ "qoriq-sec4.1-0.dtsi"
 };
diff --git a/arch/powerpc/boot/dts/fsl/p5020si-post.dtsi b/arch/powerpc/boot/dts/fsl/p5020si-post.dtsi
index 914074b91a8..64b6abea846 100644
--- a/arch/powerpc/boot/dts/fsl/p5020si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p5020si-post.dtsi
@@ -339,12 +339,14 @@
 /include/ "qoriq-gpio-0.dtsi"
 /include/ "qoriq-usb2-mph-0.dtsi"
                 usb0: usb@210000 {
+                        compatible = "fsl-usb2-mph-v1.6", "fsl,mpc85xx-usb2-mph", "fsl-usb2-mph";
                         phy_type = "utmi";
                         port0;
                 };
 
 /include/ "qoriq-usb2-dr-0.dtsi"
                 usb1: usb@211000 {
+                        compatible = "fsl-usb2-dr-v1.6", "fsl,mpc85xx-usb2-dr", "fsl-usb2-dr";
                         dr_mode = "host";
                         phy_type = "utmi";
                 };
diff --git a/arch/powerpc/boot/dts/fsl/pq3-etsec1-0.dtsi b/arch/powerpc/boot/dts/fsl/pq3-etsec1-0.dtsi
index a1979ae334a..3b0650a9847 100644
--- a/arch/powerpc/boot/dts/fsl/pq3-etsec1-0.dtsi
+++ b/arch/powerpc/boot/dts/fsl/pq3-etsec1-0.dtsi
@@ -1,7 +1,7 @@
 /*
  * PQ3 eTSEC device tree stub [ @ offsets 0x24000 ]
  *
- * Copyright 2011 Freescale Semiconductor Inc.
+ * Copyright 2011-2012 Freescale Semiconductor Inc.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are met:
@@ -41,6 +41,7 @@ ethernet@24000 {
         compatible = "gianfar";
         reg = <0x24000 0x1000>;
         ranges = <0x0 0x24000 0x1000>;
+        fsl,magic-packet;
         local-mac-address = [ 00 00 00 00 00 00 ];
         interrupts = <29 2 0 0 30 2 0 0 34 2 0 0>;
 };
diff --git a/arch/powerpc/boot/dts/fsl/pq3-etsec1-1.dtsi b/arch/powerpc/boot/dts/fsl/pq3-etsec1-1.dtsi
index 4c4fdde1ec2..96693b41f0f 100644
--- a/arch/powerpc/boot/dts/fsl/pq3-etsec1-1.dtsi
+++ b/arch/powerpc/boot/dts/fsl/pq3-etsec1-1.dtsi
@@ -1,7 +1,7 @@
 /*
  * PQ3 eTSEC device tree stub [ @ offsets 0x25000 ]
  *
- * Copyright 2011 Freescale Semiconductor Inc.
+ * Copyright 2011-2012 Freescale Semiconductor Inc.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are met:
@@ -41,6 +41,7 @@ ethernet@25000 {
         compatible = "gianfar";
         reg = <0x25000 0x1000>;
         ranges = <0x0 0x25000 0x1000>;
+        fsl,magic-packet;
         local-mac-address = [ 00 00 00 00 00 00 ];
         interrupts = <35 2 0 0 36 2 0 0 40 2 0 0>;
 };
diff --git a/arch/powerpc/boot/dts/fsl/pq3-etsec1-2.dtsi b/arch/powerpc/boot/dts/fsl/pq3-etsec1-2.dtsi
index 4b8ab438668..6b3fab19da1 100644
--- a/arch/powerpc/boot/dts/fsl/pq3-etsec1-2.dtsi
+++ b/arch/powerpc/boot/dts/fsl/pq3-etsec1-2.dtsi
@@ -1,7 +1,7 @@
 /*
  * PQ3 eTSEC device tree stub [ @ offsets 0x26000 ]
  *
- * Copyright 2011 Freescale Semiconductor Inc.
+ * Copyright 2011-2012 Freescale Semiconductor Inc.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are met:
@@ -41,6 +41,7 @@ ethernet@26000 {
         compatible = "gianfar";
         reg = <0x26000 0x1000>;
         ranges = <0x0 0x26000 0x1000>;
+        fsl,magic-packet;
         local-mac-address = [ 00 00 00 00 00 00 ];
         interrupts = <31 2 0 0 32 2 0 0 33 2 0 0>;
 };
diff --git a/arch/powerpc/boot/dts/fsl/pq3-etsec1-3.dtsi b/arch/powerpc/boot/dts/fsl/pq3-etsec1-3.dtsi
index 40c9137729a..0da592d93dd 100644
--- a/arch/powerpc/boot/dts/fsl/pq3-etsec1-3.dtsi
+++ b/arch/powerpc/boot/dts/fsl/pq3-etsec1-3.dtsi
@@ -1,7 +1,7 @@
 /*
  * PQ3 eTSEC device tree stub [ @ offsets 0x27000 ]
  *
- * Copyright 2011 Freescale Semiconductor Inc.
+ * Copyright 2011-2012 Freescale Semiconductor Inc.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are met:
@@ -41,6 +41,7 @@ ethernet@27000 {
         compatible = "gianfar";
         reg = <0x27000 0x1000>;
         ranges = <0x0 0x27000 0x1000>;
+        fsl,magic-packet;
         local-mac-address = [ 00 00 00 00 00 00 ];
         interrupts = <37 2 0 0 38 2 0 0 39 2 0 0>;
 };
diff --git a/arch/powerpc/boot/dts/fsl/pq3-mpic.dtsi b/arch/powerpc/boot/dts/fsl/pq3-mpic.dtsi
index 5c804606584..fdedf7b1fe0 100644
--- a/arch/powerpc/boot/dts/fsl/pq3-mpic.dtsi
+++ b/arch/powerpc/boot/dts/fsl/pq3-mpic.dtsi
@@ -39,6 +39,9 @@ mpic: pic@40000 {
         reg = <0x40000 0x40000>;
         compatible = "fsl,mpic";
         device_type = "open-pic";
+        big-endian;
+        single-cpu-affinity;
+        last-interrupt-source = <255>;
 };
 
 timer@41100 {
diff --git a/arch/powerpc/boot/dts/fsl/pq3-sec4.4-0.dtsi b/arch/powerpc/boot/dts/fsl/pq3-sec4.4-0.dtsi
index bf957a7fca2..d4c9d5daab2 100644
--- a/arch/powerpc/boot/dts/fsl/pq3-sec4.4-0.dtsi
+++ b/arch/powerpc/boot/dts/fsl/pq3-sec4.4-0.dtsi
@@ -33,32 +33,32 @@
  */
 
 crypto@30000 {
-        compatible = "fsl,sec4.4", "fsl,sec4.0";
+        compatible = "fsl,sec-v4.4", "fsl,sec-v4.0";
         #address-cells = <1>;
         #size-cells = <1>;
         reg              = <0x30000 0x10000>;
         interrupts       = <58 2 0 0>;
 
         sec_jr0: jr@1000 {
-                compatible = "fsl,sec4.4-job-ring", "fsl,sec4.0-job-ring";
+                compatible = "fsl,sec-v4.4-job-ring", "fsl,sec-v4.0-job-ring";
                 reg        = <0x1000 0x1000>;
                 interrupts       = <45 2 0 0>;
         };
 
         sec_jr1: jr@2000 {
-                compatible = "fsl,sec4.4-job-ring", "fsl,sec4.0-job-ring";
+                compatible = "fsl,sec-v4.4-job-ring", "fsl,sec-v4.0-job-ring";
                 reg        = <0x2000 0x1000>;
                 interrupts       = <45 2 0 0>;
         };
 
         sec_jr2: jr@3000 {
-                compatible = "fsl,sec4.4-job-ring", "fsl,sec4.0-job-ring";
+                compatible = "fsl,sec-v4.4-job-ring", "fsl,sec-v4.0-job-ring";
                 reg        = <0x3000 0x1000>;
                 interrupts       = <45 2 0 0>;
         };
 
         sec_jr3: jr@4000 {
-                compatible = "fsl,sec4.4-job-ring", "fsl,sec4.0-job-ring";
+                compatible = "fsl,sec-v4.4-job-ring", "fsl,sec-v4.0-job-ring";
                 reg        = <0x4000 0x1000>;
                 interrupts       = <45 2 0 0>;
         };
diff --git a/arch/powerpc/boot/dts/fsl/qoriq-mpic.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-mpic.dtsi
index b9bada6a87d..08f42271f86 100644
--- a/arch/powerpc/boot/dts/fsl/qoriq-mpic.dtsi
+++ b/arch/powerpc/boot/dts/fsl/qoriq-mpic.dtsi
@@ -53,7 +53,7 @@ timer@41100 {
 
 msi0: msi@41600 {
         compatible = "fsl,mpic-msi";
-        reg = <0x41600 0x200>;
+        reg = <0x41600 0x200 0x44140 4>;
         msi-available-ranges = <0 0x100>;
         interrupts = <
                 0xe0 0 0 0
@@ -68,7 +68,7 @@ msi0: msi@41600 {
 
 msi1: msi@41800 {
         compatible = "fsl,mpic-msi";
-        reg = <0x41800 0x200>;
+        reg = <0x41800 0x200 0x45140 4>;
         msi-available-ranges = <0 0x100>;
         interrupts = <
                 0xe8 0 0 0
@@ -83,7 +83,7 @@ msi1: msi@41800 {
 
 msi2: msi@41a00 {
         compatible = "fsl,mpic-msi";
-        reg = <0x41a00 0x200>;
+        reg = <0x41a00 0x200 0x46140 4>;
         msi-available-ranges = <0 0x100>;
         interrupts = <
                 0xf0 0 0 0
diff --git a/arch/powerpc/boot/dts/ge_imp3a.dts b/arch/powerpc/boot/dts/ge_imp3a.dts
new file mode 100644
index 00000000000..fefae416a09
--- /dev/null
+++ b/arch/powerpc/boot/dts/ge_imp3a.dts
@@ -0,0 +1,255 @@
+/*
+ * GE IMP3A Device Tree Source
+ *
+ * Copyright 2010-2011 GE Intelligent Platforms Embedded Systems, Inc.
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ *
+ * Based on: P2020 DS Device Tree Source
+ * Copyright 2009 Freescale Semiconductor Inc.
+ */
+
+/include/ "fsl/p2020si-pre.dtsi"
+
+/ {
+        model = "GE_IMP3A";
+        compatible = "ge,imp3a";
+
+        memory {
+                device_type = "memory";
+        };
+
+        lbc: localbus@fef05000 {
+                reg = <0 0xfef05000 0 0x1000>;
+
+                ranges = <0x0 0x0 0x0 0xff000000 0x01000000
+                          0x1 0x0 0x0 0xe0000000 0x08000000
+                          0x2 0x0 0x0 0xe8000000 0x08000000
+                          0x3 0x0 0x0 0xfc100000 0x00020000
+                          0x4 0x0 0x0 0xfc000000 0x00008000
+                          0x5 0x0 0x0 0xfc008000 0x00008000
+                          0x6 0x0 0x0 0xfee00000 0x00040000
+                          0x7 0x0 0x0 0xfee80000 0x00040000>;
+
+                /* nor@0,0 is a mirror of part of the memory in nor@1,0
+                nor@0,0 {
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        compatible = "ge,imp3a-firmware-mirror", "cfi-flash";
+                        reg = <0x0 0x0 0x1000000>;
+                        bank-width = <2>;
+                        device-width = <1>;
+
+                        partition@0 {
+                                label = "firmware";
+                                reg = <0x0 0x1000000>;
+                                read-only;
+                        };
+                };
+                */
+
+                nor@1,0 {
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        compatible = "ge,imp3a-paged-flash", "cfi-flash";
+                        reg = <0x1 0x0 0x8000000>;
+                        bank-width = <2>;
+                        device-width = <1>;
+
+                        partition@0 {
+                                label = "user";
+                                reg = <0x0 0x7800000>;
+                        };
+
+                        partition@7800000 {
+                                label = "firmware";
+                                reg = <0x7800000 0x800000>;
+                                read-only;
+                        };
+                };
+
+                nvram@3,0 {
+                        device_type = "nvram";
+                        compatible = "simtek,stk14ca8";
+                        reg = <0x3 0x0 0x20000>;
+                };
+
+                fpga@4,0 {
+                        compatible = "ge,imp3a-fpga-regs";
+                        reg = <0x4 0x0 0x20>;
+                };
+
+                gef_pic: pic@4,20 {
+                        #interrupt-cells = <1>;
+                        interrupt-controller;
+                        device_type = "interrupt-controller";
+                        compatible = "ge,imp3a-fpga-pic", "gef,fpga-pic-1.00";
+                        reg = <0x4 0x20 0x20>;
+                        interrupts = <6 7 0 0>;
+                };
+
+                gef_gpio: gpio@4,400 {
+                        #gpio-cells = <2>;
+                        compatible = "ge,imp3a-gpio";
+                        reg = <0x4 0x400 0x24>;
+                        gpio-controller;
+                };
+
+                wdt@4,800 {
+                        compatible = "ge,imp3a-fpga-wdt", "gef,fpga-wdt-1.00",
+                                "gef,fpga-wdt";
+                        reg = <0x4 0x800 0x8>;
+                        interrupts = <10 4>;
+                        interrupt-parent = <&gef_pic>;
+                };
+
+                /* Second watchdog available, driver currently supports one.
+                wdt@4,808 {
+                        compatible = "gef,imp3a-fpga-wdt", "gef,fpga-wdt-1.00",
+                                "gef,fpga-wdt";
+                        reg = <0x4 0x808 0x8>;
+                        interrupts = <9 4>;
+                        interrupt-parent = <&gef_pic>;
+                };
+                */
+
+                nand@6,0 {
+                        compatible = "fsl,elbc-fcm-nand";
+                        reg = <0x6 0x0 0x40000>;
+                };
+
+                nand@7,0 {
+                        compatible = "fsl,elbc-fcm-nand";
+                        reg = <0x7 0x0 0x40000>;
+                };
+        };
+
+        soc: soc@fef00000 {
+                ranges = <0x0 0 0xfef00000 0x100000>;
+
+                i2c@3000 {
+                        hwmon@48 {
+                                compatible = "national,lm92";
+                                reg = <0x48>;
+                        };
+
+                        hwmon@4c {
+                                compatible = "adi,adt7461";
+                                reg = <0x4c>;
+                        };
+
+                        rtc@51 {
+                                compatible = "epson,rx8581";
+                                reg = <0x51>;
+                        };
+
+                        eti@6b {
+                                compatible = "dallas,ds1682";
+                                reg = <0x6b>;
+                        };
+                };
+
+                usb@22000 {
+                        phy_type = "ulpi";
+                        dr_mode = "host";
+                };
+
+                mdio@24520 {
+                        phy0: ethernet-phy@0 {
+                                interrupt-parent = <&gef_pic>;
+                                interrupts = <0xc 0x4>;
+                                reg = <0x1>;
+                        };
+                        phy1: ethernet-phy@1 {
+                                interrupt-parent = <&gef_pic>;
+                                interrupts = <0xb 0x4>;
+                                reg = <0x2>;
+                        };
+                        tbi0: tbi-phy@11 {
+                                reg = <0x11>;
+                                device_type = "tbi-phy";
+                        };
+                };
+
+                mdio@25520 {
+                        tbi1: tbi-phy@11 {
+                                reg = <0x11>;
+                                device_type = "tbi-phy";
+                        };
+                };
+
+                mdio@26520 {
+                        status = "disabled";
+                };
+
+                enet0: ethernet@24000 {
+                        tbi-handle = <&tbi0>;
+                        phy-handle = <&phy0>;
+                        phy-connection-type = "gmii";
+                };
+
+                enet1: ethernet@25000 {
+                        tbi-handle = <&tbi1>;
+                        phy-handle = <&phy1>;
+                        phy-connection-type = "gmii";
+                };
+
+                enet2: ethernet@26000 {
+                        status = "disabled";
+                };
+        };
+
+        pci0: pcie@fef08000 {
+                ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x20000000
+                          0x1000000 0x0 0x00000000 0 0xfe020000 0x0 0x10000>;
+                reg = <0 0xfef08000 0 0x1000>;
+
+                pcie@0 {
+                        ranges = <0x2000000 0x0 0xc0000000
+                                  0x2000000 0x0 0xc0000000
+                                  0x0 0x20000000
+
+                                  0x1000000 0x0 0x0
+                                  0x1000000 0x0 0x0
+                                  0x0 0x10000>;
+                };
+        };
+
+        pci1: pcie@fef09000 {
+                reg = <0 0xfef09000 0 0x1000>;
+                ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
+                          0x1000000 0x0 0x00000000 0 0xfe010000 0x0 0x10000>;
+
+                pcie@0 {
+                        ranges = <0x2000000 0x0 0xa0000000
+                                  0x2000000 0x0 0xa0000000
+                                  0x0 0x20000000
+
+                                  0x1000000 0x0 0x0
+                                  0x1000000 0x0 0x0
+                                  0x0 0x10000>;
+                };
+
+        };
+
+        pci2: pcie@fef0a000 {
+                reg = <0 0xfef0a000 0 0x1000>;
+                ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
+                          0x1000000 0x0 0x00000000 0 0xfe000000 0x0 0x10000>;
+
+                pcie@0 {
+                        ranges = <0x2000000 0x0 0x80000000
+                                  0x2000000 0x0 0x80000000
+                                  0x0 0x20000000
+
+                                  0x1000000 0x0 0x0
+                                  0x1000000 0x0 0x0
+                                  0x0 0x10000>;
+                };
+        };
+};
+
+/include/ "fsl/p2020si-post.dtsi"
diff --git a/arch/powerpc/boot/dts/mpc836x_mds.dts b/arch/powerpc/boot/dts/mpc836x_mds.dts
index c0e450a551b..81dd513d630 100644
--- a/arch/powerpc/boot/dts/mpc836x_mds.dts
+++ b/arch/powerpc/boot/dts/mpc836x_mds.dts
@@ -405,6 +405,10 @@
                                 reg = <0x1>;
                                 device_type = "ethernet-phy";
                         };
+                        tbi-phy@2 {
+                                device_type = "tbi-phy";
+                                reg = <0x2>;
+                        };
                 };
 
                 qeic: interrupt-controller@80 {
diff --git a/arch/powerpc/boot/dts/mpc8536ds.dts b/arch/powerpc/boot/dts/mpc8536ds.dts
index c15881574fd..19736222a0b 100644
--- a/arch/powerpc/boot/dts/mpc8536ds.dts
+++ b/arch/powerpc/boot/dts/mpc8536ds.dts
@@ -1,7 +1,7 @@
 /*
  * MPC8536 DS Device Tree Source
  *
- * Copyright 2008 Freescale Semiconductor, Inc.
+ * Copyright 2008, 2011 Freescale Semiconductor, Inc.
  *
  * This program is free software; you can redistribute  it and/or modify it
  * under  the terms of  the GNU General  Public License as published by the
@@ -34,6 +34,10 @@
 
         lbc: localbus@ffe05000 {
                 reg = <0 0xffe05000 0 0x1000>;
+
+                ranges = <0x0 0x0 0x0 0xe8000000 0x08000000
+                          0x2 0x0 0x0 0xffa00000 0x00040000
+                          0x3 0x0 0x0 0xffdf0000 0x00008000>;
         };
 
         board_soc: soc: soc@ffe00000 {
diff --git a/arch/powerpc/boot/dts/mpc8536ds.dtsi b/arch/powerpc/boot/dts/mpc8536ds.dtsi
index 1462e4cf49d..cc46dbd9746 100644
--- a/arch/powerpc/boot/dts/mpc8536ds.dtsi
+++ b/arch/powerpc/boot/dts/mpc8536ds.dtsi
@@ -32,6 +32,99 @@
  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
+&lbc {
+        nor@0,0 {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "cfi-flash";
+                reg = <0x0 0x0 0x8000000>;
+                bank-width = <2>;
+                device-width = <1>;
+
+                partition@0 {
+                        reg = <0x0 0x03000000>;
+                        label = "ramdisk-nor";
+                };
+
+                partition@3000000 {
+                        reg = <0x03000000 0x00e00000>;
+                        label = "diagnostic-nor";
+                        read-only;
+                };
+
+                partition@3e00000 {
+                        reg = <0x03e00000 0x00200000>;
+                        label = "dink-nor";
+                        read-only;
+                };
+
+                partition@4000000 {
+                        reg = <0x04000000 0x00400000>;
+                        label = "kernel-nor";
+                };
+
+                partition@4400000 {
+                        reg = <0x04400000 0x03b00000>;
+                        label = "fs-nor";
+                };
+
+                partition@7f00000 {
+                        reg = <0x07f00000 0x00080000>;
+                        label = "dtb-nor";
+                };
+
+                partition@7f80000 {
+                        reg = <0x07f80000 0x00080000>;
+                        label = "u-boot-nor";
+                        read-only;
+                };
+        };
+
+        nand@2,0 {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "fsl,mpc8536-fcm-nand",
+                             "fsl,elbc-fcm-nand";
+                reg = <0x2 0x0 0x40000>;
+
+                partition@0 {
+                        reg = <0x0 0x02000000>;
+                        label = "u-boot-nand";
+                        read-only;
+                };
+
+                partition@2000000 {
+                        reg = <0x02000000 0x10000000>;
+                        label = "fs-nand";
+                };
+
+                partition@12000000 {
+                        reg = <0x12000000 0x08000000>;
+                        label = "ramdisk-nand";
+                };
+
+                partition@1a000000 {
+                        reg = <0x1a000000 0x04000000>;
+                        label = "kernel-nand";
+                };
+
+                partition@1e000000 {
+                        reg = <0x1e000000 0x01000000>;
+                        label = "dtb-nand";
+                };
+
+                partition@1f000000 {
+                        reg = <0x1f000000 0x21000000>;
+                        label = "empty-nand";
+                };
+        };
+
+        board-control@3,0 {
+                compatible = "fsl,mpc8536ds-fpga-pixis";
+                reg = <0x3 0x0 0x8000>;
+        };
+};
+
 &board_soc {
         i2c@3100 {
                 rtc@68 {
diff --git a/arch/powerpc/boot/dts/mpc8536ds_36b.dts b/arch/powerpc/boot/dts/mpc8536ds_36b.dts
index 8f4b929b1d1..f8a3b341317 100644
--- a/arch/powerpc/boot/dts/mpc8536ds_36b.dts
+++ b/arch/powerpc/boot/dts/mpc8536ds_36b.dts
@@ -1,7 +1,7 @@
 /*
  * MPC8536DS Device Tree Source (36-bit address map)
  *
- * Copyright 2008-2009 Freescale Semiconductor, Inc.
+ * Copyright 2008-2009, 2011 Freescale Semiconductor, Inc.
  *
  * This program is free software; you can redistribute  it and/or modify it
  * under  the terms of  the GNU General  Public License as published by the
@@ -33,7 +33,11 @@
         };
 
         lbc: localbus@ffe05000 {
-                reg = <0 0xffe05000 0 0x1000>;
+                reg = <0xf 0xffe05000 0 0x1000>;
+
+                ranges = <0x0 0x0 0xf 0xe8000000 0x08000000
+                          0x2 0x0 0xf 0xffa00000 0x00040000
+                          0x3 0x0 0xf 0xffdf0000 0x00008000>;
         };
 
         board_soc: soc: soc@fffe00000 {
diff --git a/arch/powerpc/boot/dts/mpc8548cds.dts b/arch/powerpc/boot/dts/mpc8548cds.dts
deleted file mode 100644
index 07b8dae0f46..00000000000
--- a/arch/powerpc/boot/dts/mpc8548cds.dts
+++ /dev/null
@@ -1,306 +0,0 @@
-/*
- * MPC8548 CDS Device Tree Source
- *
- * Copyright 2006, 2008 Freescale Semiconductor Inc.
- *
- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
- * Free Software Foundation;  either version 2 of the  License, or (at your
- * option) any later version.
- */
-
-/include/ "fsl/mpc8548si-pre.dtsi"
-
-/ {
-        model = "MPC8548CDS";
-        compatible = "MPC8548CDS", "MPC85xxCDS";
-
-        aliases {
-                ethernet0 = &enet0;
-                ethernet1 = &enet1;
-                ethernet2 = &enet2;
-                ethernet3 = &enet3;
-                serial0 = &serial0;
-                serial1 = &serial1;
-                pci0 = &pci0;
-                pci1 = &pci1;
-                pci2 = &pci2;
-        };
-
-        memory {
-                device_type = "memory";
-                reg = <0 0 0x0 0x8000000>;      // 128M at 0x0
-        };
-
-        lbc: localbus@e0005000 {
-                reg = <0 0xe0005000 0 0x1000>;
-        };
-
-        soc: soc8548@e0000000 {
-                ranges = <0 0x0 0xe0000000 0x100000>;
-
-                i2c@3000 {
-                        eeprom@50 {
-                                compatible = "atmel,24c64";
-                                reg = <0x50>;
-                        };
-
-                        eeprom@56 {
-                                compatible = "atmel,24c64";
-                                reg = <0x56>;
-                        };
-
-                        eeprom@57 {
-                                compatible = "atmel,24c64";
-                                reg = <0x57>;
-                        };
-                };
-
-                i2c@3100 {
-                        eeprom@50 {
-                                compatible = "atmel,24c64";
-                                reg = <0x50>;
-                        };
-                };
-
-                enet0: ethernet@24000 {
-                        tbi-handle = <&tbi0>;
-                        phy-handle = <&phy0>;
-                };
-
-                mdio@24520 {
-                        phy0: ethernet-phy@0 {
-                                interrupts = <5 1 0 0>;
-                                reg = <0x0>;
-                                device_type = "ethernet-phy";
-                        };
-                        phy1: ethernet-phy@1 {
-                                interrupts = <5 1 0 0>;
-                                reg = <0x1>;
-                                device_type = "ethernet-phy";
-                        };
-                        phy2: ethernet-phy@2 {
-                                interrupts = <5 1 0 0>;
-                                reg = <0x2>;
-                                device_type = "ethernet-phy";
-                        };
-                        phy3: ethernet-phy@3 {
-                                interrupts = <5 1 0 0>;
-                                reg = <0x3>;
-                                device_type = "ethernet-phy";
-                        };
-                        tbi0: tbi-phy@11 {
-                                reg = <0x11>;
-                                device_type = "tbi-phy";
-                        };
-                };
-
-                enet1: ethernet@25000 {
-                        tbi-handle = <&tbi1>;
-                        phy-handle = <&phy1>;
-                };
-
-                mdio@25520 {
-                        tbi1: tbi-phy@11 {
-                                reg = <0x11>;
-                                device_type = "tbi-phy";
-                        };
-                };
-
-                enet2: ethernet@26000 {
-                        tbi-handle = <&tbi2>;
-                        phy-handle = <&phy2>;
-                };
-
-                mdio@26520 {
-                        tbi2: tbi-phy@11 {
-                                reg = <0x11>;
-                                device_type = "tbi-phy";
-                        };
-                };
-
-                enet3: ethernet@27000 {
-                        tbi-handle = <&tbi3>;
-                        phy-handle = <&phy3>;
-                };
-
-                mdio@27520 {
-                        tbi3: tbi-phy@11 {
-                                reg = <0x11>;
-                                device_type = "tbi-phy";
-                        };
-                };
-        };
-
-        pci0: pci@e0008000 {
-                reg = <0 0xe0008000 0 0x1000>;
-                ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x10000000
-                          0x1000000 0x0 0x00000000 0 0xe2000000 0x0 0x800000>;
-                clock-frequency = <66666666>;
-                interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
-                interrupt-map = <
-                        /* IDSEL 0x4 (PCIX Slot 2) */
-                        0x2000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0
-                        0x2000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
-                        0x2000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
-                        0x2000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0
-
-                        /* IDSEL 0x5 (PCIX Slot 3) */
-                        0x2800 0x0 0x0 0x1 &mpic 0x1 0x1 0 0
-                        0x2800 0x0 0x0 0x2 &mpic 0x2 0x1 0 0
-                        0x2800 0x0 0x0 0x3 &mpic 0x3 0x1 0 0
-                        0x2800 0x0 0x0 0x4 &mpic 0x0 0x1 0 0
-
-                        /* IDSEL 0x6 (PCIX Slot 4) */
-                        0x3000 0x0 0x0 0x1 &mpic 0x2 0x1 0 0
-                        0x3000 0x0 0x0 0x2 &mpic 0x3 0x1 0 0
-                        0x3000 0x0 0x0 0x3 &mpic 0x0 0x1 0 0
-                        0x3000 0x0 0x0 0x4 &mpic 0x1 0x1 0 0
-
-                        /* IDSEL 0x8 (PCIX Slot 5) */
-                        0x4000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0
-                        0x4000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
-                        0x4000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
-                        0x4000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0
-
-                        /* IDSEL 0xC (Tsi310 bridge) */
-                        0x6000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0
-                        0x6000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
-                        0x6000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
-                        0x6000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0
-
-                        /* IDSEL 0x14 (Slot 2) */
-                        0xa000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0
-                        0xa000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
-                        0xa000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
-                        0xa000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0
-
-                        /* IDSEL 0x15 (Slot 3) */
-                        0xa800 0x0 0x0 0x1 &mpic 0x1 0x1 0 0
-                        0xa800 0x0 0x0 0x2 &mpic 0x2 0x1 0 0
-                        0xa800 0x0 0x0 0x3 &mpic 0x3 0x1 0 0
-                        0xa800 0x0 0x0 0x4 &mpic 0x0 0x1 0 0
-
-                        /* IDSEL 0x16 (Slot 4) */
-                        0xb000 0x0 0x0 0x1 &mpic 0x2 0x1 0 0
-                        0xb000 0x0 0x0 0x2 &mpic 0x3 0x1 0 0
-                        0xb000 0x0 0x0 0x3 &mpic 0x0 0x1 0 0
-                        0xb000 0x0 0x0 0x4 &mpic 0x1 0x1 0 0
-
-                        /* IDSEL 0x18 (Slot 5) */
-                        0xc000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0
-                        0xc000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
-                        0xc000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
-                        0xc000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0
-
-                        /* IDSEL 0x1C (Tsi310 bridge PCI primary) */
-                        0xe000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0
-                        0xe000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
-                        0xe000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
-                        0xe000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0>;
-
-                pci_bridge@1c {
-                        interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
-                        interrupt-map = <
-
-                                /* IDSEL 0x00 (PrPMC Site) */
-                                0000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0
-                                0000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
-                                0000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
-                                0000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0
-
-                                /* IDSEL 0x04 (VIA chip) */
-                                0x2000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0
-                                0x2000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
-                                0x2000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
-                                0x2000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0
-
-                                /* IDSEL 0x05 (8139) */
-                                0x2800 0x0 0x0 0x1 &mpic 0x1 0x1 0 0
-
-                                /* IDSEL 0x06 (Slot 6) */
-                                0x3000 0x0 0x0 0x1 &mpic 0x2 0x1 0 0
-                                0x3000 0x0 0x0 0x2 &mpic 0x3 0x1 0 0
-                                0x3000 0x0 0x0 0x3 &mpic 0x0 0x1 0 0
-                                0x3000 0x0 0x0 0x4 &mpic 0x1 0x1 0 0
-
-                                /* IDESL 0x07 (Slot 7) */
-                                0x3800 0x0 0x0 0x1 &mpic 0x3 0x1 0 0
-                                0x3800 0x0 0x0 0x2 &mpic 0x0 0x1 0 0
-                                0x3800 0x0 0x0 0x3 &mpic 0x1 0x1 0 0
-                                0x3800 0x0 0x0 0x4 &mpic 0x2 0x1 0 0>;
-
-                        reg = <0xe000 0x0 0x0 0x0 0x0>;
-                        #interrupt-cells = <1>;
-                        #size-cells = <2>;
-                        #address-cells = <3>;
-                        ranges = <0x2000000 0x0 0x80000000
-                                  0x2000000 0x0 0x80000000
-                                  0x0 0x20000000
-                                  0x1000000 0x0 0x0
-                                  0x1000000 0x0 0x0
-                                  0x0 0x80000>;
-                        clock-frequency = <33333333>;
-
-                        isa@4 {
-                                device_type = "isa";
-                                #interrupt-cells = <2>;
-                                #size-cells = <1>;
-                                #address-cells = <2>;
-                                reg = <0x2000 0x0 0x0 0x0 0x0>;
-                                ranges = <0x1 0x0 0x1000000 0x0 0x0 0x1000>;
-                                interrupt-parent = <&i8259>;
-
-                                i8259: interrupt-controller@20 {
-                                        interrupt-controller;
-                                        device_type = "interrupt-controller";
-                                        reg = <0x1 0x20 0x2
-                                               0x1 0xa0 0x2
-                                               0x1 0x4d0 0x2>;
-                                        #address-cells = <0>;
-                                        #interrupt-cells = <2>;
-                                        compatible = "chrp,iic";
-                                        interrupts = <0 1 0 0>;
-                                        interrupt-parent = <&mpic>;
-                                };
-
-                                rtc@70 {
-                                        compatible = "pnpPNP,b00";
-                                        reg = <0x1 0x70 0x2>;
-                                };
-                        };
-                };
-        };
-
-        pci1: pci@e0009000 {
-                reg = <0 0xe0009000 0 0x1000>;
-                ranges = <0x2000000 0x0 0x90000000 0 0x90000000 0x0 0x10000000
-                          0x1000000 0x0 0x00000000 0 0xe2800000 0x0 0x800000>;
-                clock-frequency = <66666666>;
-                interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
-                interrupt-map = <
-
-                        /* IDSEL 0x15 */
-                        0xa800 0x0 0x0 0x1 &mpic 0xb 0x1 0 0
-                        0xa800 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
-                        0xa800 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
-                        0xa800 0x0 0x0 0x4 &mpic 0x3 0x1 0 0>;
-        };
-
-        pci2: pcie@e000a000 {
-                reg = <0 0xe000a000 0 0x1000>;
-                ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
-                          0x1000000 0x0 0x00000000 0 0xe3000000 0x0 0x100000>;
-                pcie@0 {
-                        ranges = <0x2000000 0x0 0xa0000000
-                                  0x2000000 0x0 0xa0000000
-                                  0x0 0x20000000
-
-                                  0x1000000 0x0 0x0
-                                  0x1000000 0x0 0x0
-                                  0x0 0x100000>;
-                };
-        };
-};
-
-/include/ "fsl/mpc8548si-post.dtsi"
diff --git a/arch/powerpc/boot/dts/mpc8548cds.dtsi b/arch/powerpc/boot/dts/mpc8548cds.dtsi
new file mode 100644
index 00000000000..c61f525e474
--- /dev/null
+++ b/arch/powerpc/boot/dts/mpc8548cds.dtsi
@@ -0,0 +1,306 @@
+/*
+ * MPC8548CDS Device Tree Source stub (no addresses or top-level ranges)
+ *
+ * Copyright 2012 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+&board_lbc {
+        nor@0,0 {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "cfi-flash";
+                reg = <0x0 0x0 0x01000000>;
+                bank-width = <2>;
+                device-width = <2>;
+
+                partition@0 {
+                        reg = <0x0 0x0b00000>;
+                        label = "ramdisk-nor";
+                };
+
+                partition@300000 {
+                        reg = <0x0b00000 0x0400000>;
+                        label = "kernel-nor";
+                };
+
+                partition@700000 {
+                        reg = <0x0f00000 0x060000>;
+                        label = "dtb-nor";
+                };
+
+                partition@760000 {
+                        reg = <0x0f60000 0x020000>;
+                        label = "env-nor";
+                        read-only;
+                };
+
+                partition@780000 {
+                        reg = <0x0f80000 0x080000>;
+                        label = "u-boot-nor";
+                        read-only;
+                };
+        };
+
+        board-control@1,0 {
+                compatible = "fsl,mpc8548cds-fpga";
+                reg = <0x1 0x0 0x1000>;
+        };
+};
+
+&board_soc {
+        i2c@3000 {
+                eeprom@50 {
+                        compatible = "atmel,24c64";
+                        reg = <0x50>;
+                };
+
+                eeprom@56 {
+                        compatible = "atmel,24c64";
+                        reg = <0x56>;
+                };
+
+                eeprom@57 {
+                        compatible = "atmel,24c64";
+                        reg = <0x57>;
+                };
+        };
+
+        i2c@3100 {
+                eeprom@50 {
+                        compatible = "atmel,24c64";
+                        reg = <0x50>;
+                };
+        };
+
+        enet0: ethernet@24000 {
+                tbi-handle = <&tbi0>;
+                phy-handle = <&phy0>;
+        };
+
+        mdio@24520 {
+                phy0: ethernet-phy@0 {
+                        interrupts = <5 1 0 0>;
+                        reg = <0x0>;
+                        device_type = "ethernet-phy";
+                };
+                phy1: ethernet-phy@1 {
+                        interrupts = <5 1 0 0>;
+                        reg = <0x1>;
+                        device_type = "ethernet-phy";
+                };
+                phy2: ethernet-phy@2 {
+                        interrupts = <5 1 0 0>;
+                        reg = <0x2>;
+                        device_type = "ethernet-phy";
+                };
+                phy3: ethernet-phy@3 {
+                        interrupts = <5 1 0 0>;
+                        reg = <0x3>;
+                        device_type = "ethernet-phy";
+                };
+                tbi0: tbi-phy@11 {
+                        reg = <0x11>;
+                        device_type = "tbi-phy";
+                };
+        };
+
+        enet1: ethernet@25000 {
+                tbi-handle = <&tbi1>;
+                phy-handle = <&phy1>;
+        };
+
+        mdio@25520 {
+                tbi1: tbi-phy@11 {
+                        reg = <0x11>;
+                        device_type = "tbi-phy";
+                };
+        };
+
+        enet2: ethernet@26000 {
+                tbi-handle = <&tbi2>;
+                phy-handle = <&phy2>;
+        };
+
+        mdio@26520 {
+                tbi2: tbi-phy@11 {
+                        reg = <0x11>;
+                        device_type = "tbi-phy";
+                };
+        };
+
+        enet3: ethernet@27000 {
+                tbi-handle = <&tbi3>;
+                phy-handle = <&phy3>;
+        };
+
+        mdio@27520 {
+                tbi3: tbi-phy@11 {
+                        reg = <0x11>;
+                        device_type = "tbi-phy";
+                };
+        };
+};
+
+&board_pci0 {
+        interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
+        interrupt-map = <
+                /* IDSEL 0x4 (PCIX Slot 2) */
+                0x2000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0
+                0x2000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
+                0x2000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
+                0x2000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0
+
+                /* IDSEL 0x5 (PCIX Slot 3) */
+                0x2800 0x0 0x0 0x1 &mpic 0x1 0x1 0 0
+                0x2800 0x0 0x0 0x2 &mpic 0x2 0x1 0 0
+                0x2800 0x0 0x0 0x3 &mpic 0x3 0x1 0 0
+                0x2800 0x0 0x0 0x4 &mpic 0x0 0x1 0 0
+
+                /* IDSEL 0x6 (PCIX Slot 4) */
+                0x3000 0x0 0x0 0x1 &mpic 0x2 0x1 0 0
+                0x3000 0x0 0x0 0x2 &mpic 0x3 0x1 0 0
+                0x3000 0x0 0x0 0x3 &mpic 0x0 0x1 0 0
+                0x3000 0x0 0x0 0x4 &mpic 0x1 0x1 0 0
+
+                /* IDSEL 0x8 (PCIX Slot 5) */
+                0x4000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0
+                0x4000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
+                0x4000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
+                0x4000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0
+
+                /* IDSEL 0xC (Tsi310 bridge) */
+                0x6000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0
+                0x6000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
+                0x6000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
+                0x6000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0
+
+                /* IDSEL 0x14 (Slot 2) */
+                0xa000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0
+                0xa000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
+                0xa000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
+                0xa000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0
+
+                /* IDSEL 0x15 (Slot 3) */
+                0xa800 0x0 0x0 0x1 &mpic 0x1 0x1 0 0
+                0xa800 0x0 0x0 0x2 &mpic 0x2 0x1 0 0
+                0xa800 0x0 0x0 0x3 &mpic 0x3 0x1 0 0
+                0xa800 0x0 0x0 0x4 &mpic 0x0 0x1 0 0
+
+                /* IDSEL 0x16 (Slot 4) */
+                0xb000 0x0 0x0 0x1 &mpic 0x2 0x1 0 0
+                0xb000 0x0 0x0 0x2 &mpic 0x3 0x1 0 0
+                0xb000 0x0 0x0 0x3 &mpic 0x0 0x1 0 0
+                0xb000 0x0 0x0 0x4 &mpic 0x1 0x1 0 0
+
+                /* IDSEL 0x18 (Slot 5) */
+                0xc000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0
+                0xc000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
+                0xc000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
+                0xc000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0
+
+                /* IDSEL 0x1C (Tsi310 bridge PCI primary) */
+                0xe000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0
+                0xe000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
+                0xe000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
+                0xe000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0>;
+
+        pci_bridge@1c {
+                interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
+                interrupt-map = <
+
+                        /* IDSEL 0x00 (PrPMC Site) */
+                        0000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0
+                        0000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
+                        0000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
+                        0000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0
+
+                        /* IDSEL 0x04 (VIA chip) */
+                        0x2000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0
+                        0x2000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
+                        0x2000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
+                        0x2000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0
+
+                        /* IDSEL 0x05 (8139) */
+                        0x2800 0x0 0x0 0x1 &mpic 0x1 0x1 0 0
+
+                        /* IDSEL 0x06 (Slot 6) */
+                        0x3000 0x0 0x0 0x1 &mpic 0x2 0x1 0 0
+                        0x3000 0x0 0x0 0x2 &mpic 0x3 0x1 0 0
+                        0x3000 0x0 0x0 0x3 &mpic 0x0 0x1 0 0
+                        0x3000 0x0 0x0 0x4 &mpic 0x1 0x1 0 0
+
+                        /* IDESL 0x07 (Slot 7) */
+                        0x3800 0x0 0x0 0x1 &mpic 0x3 0x1 0 0
+                        0x3800 0x0 0x0 0x2 &mpic 0x0 0x1 0 0
+                        0x3800 0x0 0x0 0x3 &mpic 0x1 0x1 0 0
+                        0x3800 0x0 0x0 0x4 &mpic 0x2 0x1 0 0>;
+
+                reg = <0xe000 0x0 0x0 0x0 0x0>;
+                #interrupt-cells = <1>;
+                #size-cells = <2>;
+                #address-cells = <3>;
+                ranges = <0x2000000 0x0 0x80000000
+                          0x2000000 0x0 0x80000000
+                          0x0 0x20000000
+                          0x1000000 0x0 0x0
+                          0x1000000 0x0 0x0
+                          0x0 0x80000>;
+                clock-frequency = <33333333>;
+
+                isa@4 {
+                        device_type = "isa";
+                        #interrupt-cells = <2>;
+                        #size-cells = <1>;
+                        #address-cells = <2>;
+                        reg = <0x2000 0x0 0x0 0x0 0x0>;
+                        ranges = <0x1 0x0 0x1000000 0x0 0x0 0x1000>;
+                        interrupt-parent = <&i8259>;
+
+                        i8259: interrupt-controller@20 {
+                                interrupt-controller;
+                                device_type = "interrupt-controller";
+                                reg = <0x1 0x20 0x2
+                                       0x1 0xa0 0x2
+                                       0x1 0x4d0 0x2>;
+                                #address-cells = <0>;
+                                #interrupt-cells = <2>;
+                                compatible = "chrp,iic";
+                                interrupts = <0 1 0 0>;
+                                interrupt-parent = <&mpic>;
+                        };
+
+                        rtc@70 {
+                                compatible = "pnpPNP,b00";
+                                reg = <0x1 0x70 0x2>;
+                        };
+                };
+        };
+};
diff --git a/arch/powerpc/boot/dts/mpc8548cds_32b.dts b/arch/powerpc/boot/dts/mpc8548cds_32b.dts
new file mode 100644
index 00000000000..6fd63163fc6
--- /dev/null
+++ b/arch/powerpc/boot/dts/mpc8548cds_32b.dts
@@ -0,0 +1,86 @@
+/*
+ * MPC8548 CDS Device Tree Source (32-bit address map)
+ *
+ * Copyright 2006, 2008, 2011-2012 Freescale Semiconductor Inc.
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+/include/ "fsl/mpc8548si-pre.dtsi"
+
+/ {
+        model = "MPC8548CDS";
+        compatible = "MPC8548CDS", "MPC85xxCDS";
+
+        memory {
+                device_type = "memory";
+                reg = <0 0 0x0 0x8000000>;      // 128M at 0x0
+        };
+
+        board_lbc: lbc: localbus@e0005000 {
+                reg = <0 0xe0005000 0 0x1000>;
+
+                ranges = <0x0 0x0 0x0 0xff000000 0x01000000
+                          0x1 0x0 0x0 0xf8004000 0x00001000>;
+
+        };
+
+        board_soc: soc: soc8548@e0000000 {
+                ranges = <0 0x0 0xe0000000 0x100000>;
+        };
+
+        board_pci0: pci0: pci@e0008000 {
+                reg = <0 0xe0008000 0 0x1000>;
+                ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x10000000
+                          0x1000000 0x0 0x00000000 0 0xe2000000 0x0 0x800000>;
+                clock-frequency = <66666666>;
+        };
+
+        pci1: pci@e0009000 {
+                reg = <0 0xe0009000 0 0x1000>;
+                ranges = <0x2000000 0x0 0x90000000 0 0x90000000 0x0 0x10000000
+                          0x1000000 0x0 0x00000000 0 0xe2800000 0x0 0x800000>;
+                clock-frequency = <66666666>;
+                interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
+                interrupt-map = <
+
+                        /* IDSEL 0x15 */
+                        0xa800 0x0 0x0 0x1 &mpic 0xb 0x1 0 0
+                        0xa800 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
+                        0xa800 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
+                        0xa800 0x0 0x0 0x4 &mpic 0x3 0x1 0 0>;
+        };
+
+        pci2: pcie@e000a000 {
+                reg = <0 0xe000a000 0 0x1000>;
+                ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
+                          0x1000000 0x0 0x00000000 0 0xe3000000 0x0 0x100000>;
+                pcie@0 {
+                        ranges = <0x2000000 0x0 0xa0000000
+                                  0x2000000 0x0 0xa0000000
+                                  0x0 0x20000000
+
+                                  0x1000000 0x0 0x0
+                                  0x1000000 0x0 0x0
+                                  0x0 0x100000>;
+                };
+        };
+
+        rio: rapidio@e00c0000 {
+                reg = <0x0 0xe00c0000 0x0 0x20000>;
+                port1 {
+                        ranges = <0x0 0x0 0x0 0xc0000000 0x0 0x20000000>;
+                };
+        };
+};
+
+/*
+ * mpc8548cds.dtsi must be last to ensure board_pci0 overrides pci0 settings
+ * for interrupt-map & interrupt-map-mask.
+ */
+
+/include/ "fsl/mpc8548si-post.dtsi"
+/include/ "mpc8548cds.dtsi"
diff --git a/arch/powerpc/boot/dts/mpc8548cds_36b.dts b/arch/powerpc/boot/dts/mpc8548cds_36b.dts
new file mode 100644
index 00000000000..10e551b11bd
--- /dev/null
+++ b/arch/powerpc/boot/dts/mpc8548cds_36b.dts
@@ -0,0 +1,86 @@
+/*
+ * MPC8548 CDS Device Tree Source (36-bit address map)
+ *
+ * Copyright 2012 Freescale Semiconductor Inc.
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+/include/ "fsl/mpc8548si-pre.dtsi"
+
+/ {
+        model = "MPC8548CDS";
+        compatible = "MPC8548CDS", "MPC85xxCDS";
+
+        memory {
+                device_type = "memory";
+                reg = <0 0 0x0 0x8000000>;      // 128M at 0x0
+        };
+
+        board_lbc: lbc: localbus@fe0005000 {
+                reg = <0xf 0xe0005000 0 0x1000>;
+
+                ranges = <0x0 0x0 0xf 0xff000000 0x01000000
+                          0x1 0x0 0xf 0xf8004000 0x00001000>;
+
+        };
+
+        board_soc: soc: soc8548@fe0000000 {
+                ranges = <0 0xf 0xe0000000 0x100000>;
+        };
+
+        board_pci0: pci0: pci@fe0008000 {
+                reg = <0xf 0xe0008000 0 0x1000>;
+                ranges = <0x2000000 0x0 0xe0000000 0xc 0x00000000 0x0 0x10000000
+                          0x1000000 0x0 0x00000000 0xf 0xe2000000 0x0 0x800000>;
+                clock-frequency = <66666666>;
+        };
+
+        pci1: pci@fe0009000 {
+                reg = <0xf 0xe0009000 0 0x1000>;
+                ranges = <0x2000000 0x0 0xe0000000 0xc 0x10000000 0x0 0x10000000
+                          0x1000000 0x0 0x00000000 0xf 0xe2800000 0x0 0x800000>;
+                clock-frequency = <66666666>;
+                interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
+                interrupt-map = <
+
+                        /* IDSEL 0x15 */
+                        0xa800 0x0 0x0 0x1 &mpic 0xb 0x1 0 0
+                        0xa800 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
+                        0xa800 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
+                        0xa800 0x0 0x0 0x4 &mpic 0x3 0x1 0 0>;
+        };
+
+        pci2: pcie@fe000a000 {
+                reg = <0xf 0xe000a000 0 0x1000>;
+                ranges = <0x2000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000
+                          0x1000000 0x0 0x00000000 0xf 0xe3000000 0x0 0x100000>;
+                pcie@0 {
+                        ranges = <0x2000000 0x0 0xa0000000
+                                  0x2000000 0x0 0xa0000000
+                                  0x0 0x20000000
+
+                                  0x1000000 0x0 0x0
+                                  0x1000000 0x0 0x0
+                                  0x0 0x100000>;
+                };
+        };
+
+        rio: rapidio@fe00c0000 {
+                reg = <0xf 0xe00c0000 0x0 0x20000>;
+                port1 {
+                        ranges = <0x0 0x0 0xc 0x40000000 0x0 0x20000000>;
+                };
+        };
+};
+
+/*
+ * mpc8548cds.dtsi must be last to ensure board_pci0 overrides pci0 settings
+ * for interrupt-map & interrupt-map-mask.
+ */
+
+/include/ "fsl/mpc8548si-post.dtsi"
+/include/ "mpc8548cds.dtsi"
diff --git a/arch/powerpc/boot/dts/mpc8572ds.dtsi b/arch/powerpc/boot/dts/mpc8572ds.dtsi
index c3d4fac0532..14178944e22 100644
--- a/arch/powerpc/boot/dts/mpc8572ds.dtsi
+++ b/arch/powerpc/boot/dts/mpc8572ds.dtsi
@@ -41,37 +41,47 @@
                 bank-width = <2>;
                 device-width = <1>;
 
-                ramdisk@0 {
+                partition@0 {
                         reg = <0x0 0x03000000>;
-                        read-only;
+                        label = "ramdisk-nor";
                 };
 
-                diagnostic@3000000 {
+                partition@3000000 {
                         reg = <0x03000000 0x00e00000>;
+                        label = "diagnostic-nor";
                         read-only;
                 };
 
-                dink@3e00000 {
+                partition@3e00000 {
                         reg = <0x03e00000 0x00200000>;
+                        label = "dink-nor";
                         read-only;
                 };
 
-                kernel@4000000 {
+                partition@4000000 {
                         reg = <0x04000000 0x00400000>;
-                        read-only;
+                        label = "kernel-nor";
                 };
 
-                jffs2@4400000 {
+                partition@4400000 {
                         reg = <0x04400000 0x03b00000>;
+                        label = "fs-nor";
+                };
+
+                partition@7f00000 {
+                        reg = <0x07f00000 0x00060000>;
+                        label = "dtb-nor";
                 };
 
-                dtb@7f00000 {
-                        reg = <0x07f00000 0x00080000>;
+                partition@7f60000 {
+                        reg = <0x07f60000 0x00020000>;
+                        label = "env-nor";
                         read-only;
                 };
 
-                u-boot@7f80000 {
+                partition@7f80000 {
                         reg = <0x07f80000 0x00080000>;
+                        label = "u-boot-nor";
                         read-only;
                 };
         };
@@ -83,31 +93,35 @@
                              "fsl,elbc-fcm-nand";
                 reg = <0x2 0x0 0x40000>;
 
-                u-boot@0 {
+                partition@0 {
                         reg = <0x0 0x02000000>;
+                        label = "u-boot-nand";
                         read-only;
                 };
 
-                jffs2@2000000 {
+                partition@2000000 {
                         reg = <0x02000000 0x10000000>;
+                        label = "fs-nand";
                 };
 
-                ramdisk@12000000 {
+                partition@12000000 {
                         reg = <0x12000000 0x08000000>;
-                        read-only;
+                        label = "ramdisk-nand";
                 };
 
-                kernel@1a000000 {
+                partition@1a000000 {
                         reg = <0x1a000000 0x04000000>;
+                        label = "kernel-nand";
                 };
 
-                dtb@1e000000 {
+                partition@1e000000 {
                         reg = <0x1e000000 0x01000000>;
-                        read-only;
+                        label = "dtb-nand";
                 };
 
-                empty@1f000000 {
+                partition@1f000000 {
                         reg = <0x1f000000 0x21000000>;
+                        label = "empty-nand";
                 };
         };
 
diff --git a/arch/powerpc/boot/dts/p1010rdb.dtsi b/arch/powerpc/boot/dts/p1010rdb.dtsi
index d4c4a773028..49776143a1b 100644
--- a/arch/powerpc/boot/dts/p1010rdb.dtsi
+++ b/arch/powerpc/boot/dts/p1010rdb.dtsi
@@ -138,7 +138,7 @@
                         #size-cells = <1>;
                         compatible = "spansion,s25sl12801";
                         reg = <0>;
-                        spi-max-frequency = <50000000>;
+                        spi-max-frequency = <40000000>;
 
                         partition@0 {
                                 /* 1MB for u-boot Bootloader Image */
@@ -196,7 +196,7 @@
                 };
 
                 tbi-phy@3 {
-                        device-type = "tbi-phy";
+                        device_type = "tbi-phy";
                         reg = <0x3>;
                 };
         };
diff --git a/arch/powerpc/boot/dts/p1020rdb-pc.dtsi b/arch/powerpc/boot/dts/p1020rdb-pc.dtsi
new file mode 100644
index 00000000000..c952cd37cf6
--- /dev/null
+++ b/arch/powerpc/boot/dts/p1020rdb-pc.dtsi
@@ -0,0 +1,247 @@
+/*
+ * P1020 RDB-PC Device Tree Source stub (no addresses or top-level ranges)
+ *
+ * Copyright 2012 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+&lbc {
+        nor@0,0 {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "cfi-flash";
+                reg = <0x0 0x0 0x1000000>;
+                bank-width = <2>;
+                device-width = <1>;
+
+                partition@0 {
+                        /* This location must not be altered  */
+                        /* 256KB for Vitesse 7385 Switch firmware */
+                        reg = <0x0 0x00040000>;
+                        label = "NOR Vitesse-7385 Firmware";
+                        read-only;
+                };
+
+                partition@40000 {
+                        /* 256KB for DTB Image */
+                        reg = <0x00040000 0x00040000>;
+                        label = "NOR DTB Image";
+                };
+
+                partition@80000 {
+                        /* 3.5 MB for Linux Kernel Image */
+                        reg = <0x00080000 0x00380000>;
+                        label = "NOR Linux Kernel Image";
+                };
+
+                partition@400000 {
+                        /* 11MB for JFFS2 based Root file System */
+                        reg = <0x00400000 0x00b00000>;
+                        label = "NOR JFFS2 Root File System";
+                };
+
+                partition@f00000 {
+                        /* This location must not be altered  */
+                        /* 512KB for u-boot Bootloader Image */
+                        /* 512KB for u-boot Environment Variables */
+                        reg = <0x00f00000 0x00100000>;
+                        label = "NOR U-Boot Image";
+                        read-only;
+                };
+        };
+
+        nand@1,0 {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "fsl,p1020-fcm-nand",
+                             "fsl,elbc-fcm-nand";
+                reg = <0x1 0x0 0x40000>;
+
+                partition@0 {
+                        /* This location must not be altered  */
+                        /* 1MB for u-boot Bootloader Image */
+                        reg = <0x0 0x00100000>;
+                        label = "NAND U-Boot Image";
+                        read-only;
+                };
+
+                partition@100000 {
+                        /* 1MB for DTB Image */
+                        reg = <0x00100000 0x00100000>;
+                        label = "NAND DTB Image";
+                };
+
+                partition@200000 {
+                        /* 4MB for Linux Kernel Image */
+                        reg = <0x00200000 0x00400000>;
+                        label = "NAND Linux Kernel Image";
+                };
+
+                partition@600000 {
+                        /* 4MB for Compressed Root file System Image */
+                        reg = <0x00600000 0x00400000>;
+                        label = "NAND Compressed RFS Image";
+                };
+
+                partition@a00000 {
+                        /* 7MB for JFFS2 based Root file System */
+                        reg = <0x00a00000 0x00700000>;
+                        label = "NAND JFFS2 Root File System";
+                };
+
+                partition@1100000 {
+                        /* 15MB for JFFS2 based Root file System */
+                        reg = <0x01100000 0x00f00000>;
+                        label = "NAND Writable User area";
+                };
+        };
+
+        L2switch@2,0 {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "vitesse-7385";
+                reg = <0x2 0x0 0x20000>;
+        };
+
+        cpld@3,0 {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "cpld";
+                reg = <0x3 0x0 0x20000>;
+                read-only;
+        };
+};
+
+&soc {
+        i2c@3000 {
+                rtc@68 {
+                        compatible = "pericom,pt7c4338";
+                        reg = <0x68>;
+                };
+        };
+
+        spi@7000 {
+                flash@0 {
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        compatible = "spansion,s25sl12801";
+                        reg = <0>;
+                        spi-max-frequency = <40000000>; /* input clock */
+
+                        partition@u-boot {
+                                /* 512KB for u-boot Bootloader Image */
+                                reg = <0x0 0x00080000>;
+                                label = "u-boot";
+                                read-only;
+                        };
+
+                        partition@dtb {
+                                /* 512KB for DTB Image*/
+                                reg = <0x00080000 0x00080000>;
+                                label = "dtb";
+                        };
+
+                        partition@kernel {
+                                /* 4MB for Linux Kernel Image */
+                                reg = <0x00100000 0x00400000>;
+                                label = "kernel";
+                        };
+
+                        partition@fs {
+                                /* 4MB for Compressed RFS Image */
+                                reg = <0x00500000 0x00400000>;
+                                label = "file system";
+                        };
+
+                        partition@jffs-fs {
+                                /* 7MB for JFFS2 based RFS */
+                                reg = <0x00900000 0x00700000>;
+                                label = "file system jffs2";
+                        };
+                };
+        };
+
+        usb@22000 {
+                phy_type = "ulpi";
+        };
+
+        /* USB2 is shared with localbus, so it must be disabled
+           by default. We can't put 'status = "disabled";' here
+           since U-Boot doesn't clear the status property when
+           it enables USB2. OTOH, U-Boot does create a new node
+           when there isn't any. So, just comment it out.
+        usb@23000 {
+                phy_type = "ulpi";
+        };
+        */
+
+        mdio@24000 {
+                phy0: ethernet-phy@0 {
+                        interrupt-parent = <&mpic>;
+                        interrupts = <3 1>;
+                        reg = <0x0>;
+                };
+
+                phy1: ethernet-phy@1 {
+                        interrupt-parent = <&mpic>;
+                        interrupts = <2 1>;
+                        reg = <0x1>;
+                };
+
+                tbi0: tbi-phy@11 {
+                        device_type = "tbi-phy";
+                        reg = <0x11>;
+                };
+        };
+
+        mdio@25000 {
+                tbi1: tbi-phy@11 {
+                        reg = <0x11>;
+                        device_type = "tbi-phy";
+                };
+        };
+
+        enet0: ethernet@b0000 {
+                fixed-link = <1 1 1000 0 0>;
+                phy-connection-type = "rgmii-id";
+
+        };
+
+        enet1: ethernet@b1000 {
+                phy-handle = <&phy0>;
+                tbi-handle = <&tbi1>;
+                phy-connection-type = "sgmii";
+        };
+
+        enet2: ethernet@b2000 {
+                phy-handle = <&phy1>;
+                phy-connection-type = "rgmii-id";
+        };
+};
diff --git a/arch/powerpc/boot/dts/p1020rdb-pc_32b.dts b/arch/powerpc/boot/dts/p1020rdb-pc_32b.dts
new file mode 100644
index 00000000000..4de69b726dc
--- /dev/null
+++ b/arch/powerpc/boot/dts/p1020rdb-pc_32b.dts
@@ -0,0 +1,90 @@
+/*
+ * P1020 RDB-PC Device Tree Source (32-bit address map)
+ *
+ * Copyright 2012 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/include/ "fsl/p1020si-pre.dtsi"
+/ {
+        model = "fsl,P1020RDB-PC";
+        compatible = "fsl,P1020RDB-PC";
+
+        memory {
+                device_type = "memory";
+        };
+
+        lbc: localbus@ffe05000 {
+                reg = <0 0xffe05000 0 0x1000>;
+
+                /* NOR, NAND Flashes and Vitesse 5 port L2 switch */
+                ranges = <0x0 0x0 0x0 0xef000000 0x01000000
+                          0x1 0x0 0x0 0xff800000 0x00040000
+                          0x2 0x0 0x0 0xffb00000 0x00020000
+                          0x3 0x0 0x0 0xffa00000 0x00020000>;
+        };
+
+        soc: soc@ffe00000 {
+                ranges = <0x0 0x0 0xffe00000 0x100000>;
+        };
+
+        pci0: pcie@ffe09000 {
+                ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
+                          0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
+                reg = <0 0xffe09000 0 0x1000>;
+                pcie@0 {
+                        ranges = <0x2000000 0x0 0xa0000000
+                                  0x2000000 0x0 0xa0000000
+                                  0x0 0x20000000
+
+                                  0x1000000 0x0 0x0
+                                  0x1000000 0x0 0x0
+                                  0x0 0x100000>;
+                };
+        };
+
+        pci1: pcie@ffe0a000 {
+                reg = <0 0xffe0a000 0 0x1000>;
+                ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
+                          0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
+                pcie@0 {
+                        ranges = <0x2000000 0x0 0x80000000
+                                  0x2000000 0x0 0x80000000
+                                  0x0 0x20000000
+
+                                  0x1000000 0x0 0x0
+                                  0x1000000 0x0 0x0
+                                  0x0 0x100000>;
+                };
+        };
+};
+
+/include/ "p1020rdb-pc.dtsi"
+/include/ "fsl/p1020si-post.dtsi"
diff --git a/arch/powerpc/boot/dts/p1020rdb-pc_36b.dts b/arch/powerpc/boot/dts/p1020rdb-pc_36b.dts
new file mode 100644
index 00000000000..5237da7441b
--- /dev/null
+++ b/arch/powerpc/boot/dts/p1020rdb-pc_36b.dts
@@ -0,0 +1,90 @@
+/*
+ * P1020 RDB-PC Device Tree Source (36-bit address map)
+ *
+ * Copyright 2012 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/include/ "fsl/p1020si-pre.dtsi"
+/ {
+        model = "fsl,P1020RDB-PC";
+        compatible = "fsl,P1020RDB-PC";
+
+        memory {
+                device_type = "memory";
+        };
+
+        lbc: localbus@fffe05000 {
+                reg = <0xf 0xffe05000 0 0x1000>;
+
+                /* NOR, NAND Flashes and Vitesse 5 port L2 switch */
+                ranges = <0x0 0x0 0xf 0xef000000 0x01000000
+                          0x1 0x0 0xf 0xff800000 0x00040000
+                          0x2 0x0 0xf 0xffb00000 0x00040000
+                          0x3 0x0 0xf 0xffa00000 0x00020000>;
+        };
+
+        soc: soc@fffe00000 {
+                ranges = <0x0 0xf 0xffe00000 0x100000>;
+        };
+
+        pci0: pcie@fffe09000 {
+                reg = <0xf 0xffe09000 0 0x1000>;
+                ranges = <0x2000000 0x0 0xc0000000 0xc 0x20000000 0x0 0x20000000
+                          0x1000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x10000>;
+                pcie@0 {
+                        ranges = <0x2000000 0x0 0xc0000000
+                                  0x2000000 0x0 0xc0000000
+                                  0x0 0x20000000
+
+                                  0x1000000 0x0 0x0
+                                  0x1000000 0x0 0x0
+                                  0x0 0x100000>;
+                };
+        };
+
+        pci1: pcie@fffe0a000 {
+                reg = <0xf 0xffe0a000 0 0x1000>;
+                ranges = <0x2000000 0x0 0x80000000 0xc 0x00000000 0x0 0x20000000
+                          0x1000000 0x0 0x00000000 0xf 0xffc00000 0x0 0x10000>;
+                pcie@0 {
+                        ranges = <0x2000000 0x0 0x80000000
+                                  0x2000000 0x0 0x80000000
+                                  0x0 0x20000000
+
+                                  0x1000000 0x0 0x0
+                                  0x1000000 0x0 0x0
+                                  0x0 0x100000>;
+                };
+        };
+};
+
+/include/ "p1020rdb-pc.dtsi"
+/include/ "fsl/p1020si-post.dtsi"
diff --git a/arch/powerpc/boot/dts/p1020rdb-pc_camp_core0.dts b/arch/powerpc/boot/dts/p1020rdb-pc_camp_core0.dts
new file mode 100644
index 00000000000..f411515937e
--- /dev/null
+++ b/arch/powerpc/boot/dts/p1020rdb-pc_camp_core0.dts
@@ -0,0 +1,64 @@
+/*
+ * P1020 RDB-PC  Core0 Device Tree Source in CAMP mode.
+ *
+ * In CAMP mode, each core needs to have its own dts. Only mpic and L2 cache
+ * can be shared, all the other devices must be assigned to one core only.
+ * This dts file allows core0 to have memory, l2, i2c, spi, gpio, tdm, dma, usb,
+ * eth1, eth2, sdhc, crypto, global-util, message, pci0, pci1, msi.
+ *
+ * Please note to add "-b 0" for core0's dts compiling.
+ *
+ * Copyright 2012 Freescale Semiconductor Inc.
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+/include/ "p1020rdb-pc_32b.dts"
+
+/ {
+        model = "fsl,P1020RDB-PC";
+        compatible = "fsl,P1020RDB-PC";
+
+        aliases {
+                ethernet1 = &enet1;
+                ethernet2 = &enet2;
+                serial0 = &serial0;
+                pci0 = &pci0;
+                pci1 = &pci1;
+        };
+
+        cpus {
+                PowerPC,P1020@1 {
+                        status = "disabled";
+                };
+        };
+
+        memory {
+                device_type = "memory";
+        };
+
+        localbus@ffe05000 {
+                status = "disabled";
+        };
+
+        soc@ffe00000 {
+                serial1: serial@4600 {
+                        status = "disabled";
+                };
+
+                enet0: ethernet@b0000 {
+                        status = "disabled";
+                };
+
+                mpic: pic@40000 {
+                        protected-sources = <
+                        42 29 30 34     /* serial1, enet0-queue-group0 */
+                        17 18 24 45     /* enet0-queue-group1, crypto */
+                        >;
+                        pic-no-reset;
+                };
+        };
+};
diff --git a/arch/powerpc/boot/dts/p1020rdb-pc_camp_core1.dts b/arch/powerpc/boot/dts/p1020rdb-pc_camp_core1.dts
new file mode 100644
index 00000000000..a91335ad82c
--- /dev/null
+++ b/arch/powerpc/boot/dts/p1020rdb-pc_camp_core1.dts
@@ -0,0 +1,142 @@
+/*
+ * P1020 RDB-PC Core1 Device Tree Source in CAMP mode.
+ *
+ * In CAMP mode, each core needs to have its own dts. Only mpic and L2 cache
+ * can be shared, all the other devices must be assigned to one core only.
+ * This dts allows core1 to have l2, eth0, crypto.
+ *
+ * Please note to add "-b 1" for core1's dts compiling.
+ *
+ * Copyright 2012 Freescale Semiconductor Inc.
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+/include/ "p1020rdb-pc_32b.dts"
+
+/ {
+        model = "fsl,P1020RDB-PC";
+        compatible = "fsl,P1020RDB-PC";
+
+        aliases {
+                ethernet0 = &enet0;
+                serial0 = &serial1;
+                };
+
+        cpus {
+                PowerPC,P1020@0 {
+                        status = "disabled";
+                };
+        };
+
+        memory {
+                device_type = "memory";
+        };
+
+        localbus@ffe05000 {
+                status = "disabled";
+        };
+
+        soc@ffe00000 {
+                ecm-law@0 {
+                        status = "disabled";
+                };
+
+                ecm@1000 {
+                        status = "disabled";
+                };
+
+                memory-controller@2000 {
+                        status = "disabled";
+                };
+
+                i2c@3000 {
+                        status = "disabled";
+                };
+
+                i2c@3100 {
+                        status = "disabled";
+                };
+
+                serial0: serial@4500 {
+                        status = "disabled";
+                };
+
+                spi@7000 {
+                        status = "disabled";
+                };
+
+                gpio: gpio-controller@f000 {
+                        status = "disabled";
+                };
+
+                dma@21300 {
+                        status = "disabled";
+                };
+
+                mdio@24000 {
+                        status = "disabled";
+                };
+
+                mdio@25000 {
+                        status = "disabled";
+                };
+
+                enet1: ethernet@b1000 {
+                        status = "disabled";
+                };
+
+                enet2: ethernet@b2000 {
+                        status = "disabled";
+                };
+
+                usb@22000 {
+                        status = "disabled";
+                };
+
+                sdhci@2e000 {
+                        status = "disabled";
+                };
+
+                mpic: pic@40000 {
+                        protected-sources = <
+                        16              /* ecm, mem, L2, pci0, pci1 */
+                        43 42 59        /* i2c, serial0, spi */
+                        47 63 62        /* gpio, tdm */
+                        20 21 22 23     /* dma */
+                        03 02           /* mdio */
+                        35 36 40        /* enet1-queue-group0 */
+                        51 52 67        /* enet1-queue-group1 */
+                        31 32 33        /* enet2-queue-group0 */
+                        25 26 27        /* enet2-queue-group1 */
+                        28 72 58        /* usb, sdhci, crypto */
+                        0xb0 0xb1 0xb2  /* message */
+                        0xb3 0xb4 0xb5
+                        0xb6 0xb7
+                        0xe0 0xe1 0xe2  /* msi */
+                        0xe3 0xe4 0xe5
+                        0xe6 0xe7               /* sdhci, crypto , pci */
+                        >;
+                        pic-no-reset;
+                };
+
+                msi@41600 {
+                        status = "disabled";
+                };
+
+                global-utilities@e0000 {        //global utilities block
+                        status = "disabled";
+                };
+        };
+
+        pci0: pcie@ffe09000 {
+                status = "disabled";
+        };
+
+        pci1: pcie@ffe0a000 {
+                status = "disabled";
+        };
+};
diff --git a/arch/powerpc/boot/dts/p1021rdb.dts b/arch/powerpc/boot/dts/p1021rdb.dts
new file mode 100644
index 00000000000..90b6b4caa27
--- /dev/null
+++ b/arch/powerpc/boot/dts/p1021rdb.dts
@@ -0,0 +1,96 @@
+/*
+ * P1021 RDB Device Tree Source
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/include/ "fsl/p1021si-pre.dtsi"
+/ {
+        model = "fsl,P1021RDB";
+        compatible = "fsl,P1021RDB-PC";
+
+        memory {
+                device_type = "memory";
+        };
+
+        lbc: localbus@ffe05000 {
+                reg = <0 0xffe05000 0 0x1000>;
+
+                /* NOR, NAND Flashes and Vitesse 5 port L2 switch */
+                ranges = <0x0 0x0 0x0 0xef000000 0x01000000
+                          0x1 0x0 0x0 0xff800000 0x00040000
+                          0x2 0x0 0x0 0xffb00000 0x00020000>;
+        };
+
+        soc: soc@ffe00000 {
+                ranges = <0x0 0x0 0xffe00000 0x100000>;
+        };
+
+        pci0: pcie@ffe09000 {
+                ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
+                          0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
+                reg = <0 0xffe09000 0 0x1000>;
+                pcie@0 {
+                        ranges = <0x2000000 0x0 0xa0000000
+                                  0x2000000 0x0 0xa0000000
+                                  0x0 0x20000000
+
+                                  0x1000000 0x0 0x0
+                                  0x1000000 0x0 0x0
+                                  0x0 0x100000>;
+                };
+        };
+
+        pci1: pcie@ffe0a000 {
+                reg = <0 0xffe0a000 0 0x1000>;
+                ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
+                          0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
+                pcie@0 {
+                        ranges = <0x2000000 0x0 0x80000000
+                                  0x2000000 0x0 0x80000000
+                                  0x0 0x20000000
+
+                                  0x1000000 0x0 0x0
+                                  0x1000000 0x0 0x0
+                                  0x0 0x100000>;
+                };
+        };
+
+        qe: qe@ffe80000 {
+                ranges = <0x0 0x0 0xffe80000 0x40000>;
+                reg = <0 0xffe80000 0 0x480>;
+                brg-frequency = <0>;
+                bus-frequency = <0>;
+        };
+};
+
+/include/ "p1021rdb.dtsi"
+/include/ "fsl/p1021si-post.dtsi"
diff --git a/arch/powerpc/boot/dts/p1021rdb.dtsi b/arch/powerpc/boot/dts/p1021rdb.dtsi
new file mode 100644
index 00000000000..b973461ab75
--- /dev/null
+++ b/arch/powerpc/boot/dts/p1021rdb.dtsi
@@ -0,0 +1,236 @@
+/*
+ * P1021 RDB Device Tree Source stub (no addresses or top-level ranges)
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+&lbc {
+        nor@0,0 {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "cfi-flash";
+                reg = <0x0 0x0 0x1000000>;
+                bank-width = <2>;
+                device-width = <1>;
+
+                partition@0 {
+                        /* This location must not be altered  */
+                        /* 256KB for Vitesse 7385 Switch firmware */
+                        reg = <0x0 0x00040000>;
+                        label = "NOR Vitesse-7385 Firmware";
+                        read-only;
+                };
+
+                partition@40000 {
+                        /* 256KB for DTB Image */
+                        reg = <0x00040000 0x00040000>;
+                        label = "NOR DTB Image";
+                };
+
+                partition@80000 {
+                        /* 3.5 MB for Linux Kernel Image */
+                        reg = <0x00080000 0x00380000>;
+                        label = "NOR Linux Kernel Image";
+                };
+
+                partition@400000 {
+                        /* 11MB for JFFS2 based Root file System */
+                        reg = <0x00400000 0x00b00000>;
+                        label = "NOR JFFS2 Root File System";
+                };
+
+                partition@f00000 {
+                        /* This location must not be altered  */
+                        /* 512KB for u-boot Bootloader Image */
+                        /* 512KB for u-boot Environment Variables */
+                        reg = <0x00f00000 0x00100000>;
+                        label = "NOR U-Boot Image";
+                };
+        };
+
+        nand@1,0 {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "fsl,p1021-fcm-nand",
+                             "fsl,elbc-fcm-nand";
+                reg = <0x1 0x0 0x40000>;
+
+                partition@0 {
+                        /* This location must not be altered  */
+                        /* 1MB for u-boot Bootloader Image */
+                        reg = <0x0 0x00100000>;
+                        label = "NAND U-Boot Image";
+                        read-only;
+                };
+
+                partition@100000 {
+                        /* 1MB for DTB Image */
+                        reg = <0x00100000 0x00100000>;
+                        label = "NAND DTB Image";
+                };
+
+                partition@200000 {
+                        /* 4MB for Linux Kernel Image */
+                        reg = <0x00200000 0x00400000>;
+                        label = "NAND Linux Kernel Image";
+                };
+
+                partition@600000 {
+                        /* 4MB for Compressed Root file System Image */
+                        reg = <0x00600000 0x00400000>;
+                        label = "NAND Compressed RFS Image";
+                };
+
+                partition@a00000 {
+                        /* 7MB for JFFS2 based Root file System */
+                        reg = <0x00a00000 0x00700000>;
+                        label = "NAND JFFS2 Root File System";
+                };
+
+                partition@1100000 {
+                        /* 15MB for User Writable Area  */
+                        reg = <0x01100000 0x00f00000>;
+                        label = "NAND Writable User area";
+                };
+        };
+
+        L2switch@2,0 {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "vitesse-7385";
+                reg = <0x2 0x0 0x20000>;
+        };
+};
+
+&soc {
+        i2c@3000 {
+                rtc@68 {
+                        compatible = "pericom,pt7c4338";
+                        reg = <0x68>;
+                };
+        };
+
+        spi@7000 {
+                flash@0 {
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        compatible = "spansion,s25sl12801";
+                        reg = <0>;
+                        spi-max-frequency = <40000000>; /* input clock */
+
+                        partition@u-boot {
+                                /* 512KB for u-boot Bootloader Image */
+                                reg = <0x0 0x00080000>;
+                                label = "SPI Flash U-Boot Image";
+                                read-only;
+                        };
+
+                        partition@dtb {
+                                /* 512KB for DTB Image */
+                                reg = <0x00080000 0x00080000>;
+                                label = "SPI Flash DTB Image";
+                        };
+
+                        partition@kernel {
+                                /* 4MB for Linux Kernel Image */
+                                reg = <0x00100000 0x00400000>;
+                                label = "SPI Flash Linux Kernel Image";
+                        };
+
+                        partition@fs {
+                                /* 4MB for Compressed RFS Image */
+                                reg = <0x00500000 0x00400000>;
+                                label = "SPI Flash Compressed RFSImage";
+                        };
+
+                        partition@jffs-fs {
+                                /* 7MB for JFFS2 based RFS */
+                                reg = <0x00900000 0x00700000>;
+                                label = "SPI Flash JFFS2 RFS";
+                        };
+                };
+        };
+
+        usb@22000 {
+                phy_type = "ulpi";
+        };
+
+        mdio@24000 {
+                phy0: ethernet-phy@0 {
+                        interrupt-parent = <&mpic>;
+                        interrupts = <3 1 0 0>;
+                        reg = <0x0>;
+                };
+
+                phy1: ethernet-phy@1 {
+                        interrupt-parent = <&mpic>;
+                        interrupts = <2 1 0 0>;
+                        reg = <0x1>;
+                };
+
+                tbi0: tbi-phy@11 {
+                        reg = <0x11>;
+                        device_type = "tbi-phy";
+                };
+        };
+
+        mdio@25000 {
+                tbi1: tbi-phy@11 {
+                        reg = <0x11>;
+                        device_type = "tbi-phy";
+                };
+        };
+
+        mdio@26000 {
+                tbi2: tbi-phy@11 {
+                        reg = <0x11>;
+                        device_type = "tbi-phy";
+                };
+        };
+
+        enet0: ethernet@b0000 {
+                fixed-link = <1 1 1000 0 0>;
+                phy-connection-type = "rgmii-id";
+
+        };
+
+        enet1: ethernet@b1000 {
+                phy-handle = <&phy0>;
+                tbi-handle = <&tbi1>;
+                phy-connection-type = "sgmii";
+        };
+
+        enet2: ethernet@b2000 {
+                phy-handle = <&phy1>;
+                tbi-handle = <&tbi2>;
+                phy-connection-type = "rgmii-id";
+        };
+};
diff --git a/arch/powerpc/boot/dts/p1021rdb_36b.dts b/arch/powerpc/boot/dts/p1021rdb_36b.dts
new file mode 100644
index 00000000000..ea6d8b5fa10
--- /dev/null
+++ b/arch/powerpc/boot/dts/p1021rdb_36b.dts
@@ -0,0 +1,96 @@
+/*
+ * P1021 RDB Device Tree Source (36-bit address map)
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/include/ "fsl/p1021si-pre.dtsi"
+/ {
+        model = "fsl,P1021RDB";
+        compatible = "fsl,P1021RDB-PC";
+
+        memory {
+                device_type = "memory";
+        };
+
+        lbc: localbus@fffe05000 {
+                reg = <0xf 0xffe05000 0 0x1000>;
+
+                /* NOR, NAND Flashes and Vitesse 5 port L2 switch */
+                ranges = <0x0 0x0 0xf 0xef000000 0x01000000
+                          0x1 0x0 0xf 0xff800000 0x00040000
+                          0x2 0x0 0xf 0xffb00000 0x00020000>;
+        };
+
+        soc: soc@fffe00000 {
+                ranges = <0x0 0xf 0xffe00000 0x100000>;
+        };
+
+        pci0: pcie@fffe09000 {
+                ranges = <0x2000000 0x0 0xc0000000 0xc 0x20000000 0x0 0x20000000
+                          0x1000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x10000>;
+                reg = <0xf 0xffe09000 0 0x1000>;
+                pcie@0 {
+                        ranges = <0x2000000 0x0 0xa0000000
+                                  0x2000000 0x0 0xa0000000
+                                  0x0 0x20000000
+
+                                  0x1000000 0x0 0x0
+                                  0x1000000 0x0 0x0
+                                  0x0 0x100000>;
+                };
+        };
+
+        pci1: pcie@fffe0a000 {
+                reg = <0xf 0xffe0a000 0 0x1000>;
+                ranges = <0x2000000 0x0 0x80000000 0xc 0x00000000 0x0 0x20000000
+                          0x1000000 0x0 0x00000000 0xf 0xffc00000 0x0 0x10000>;
+                pcie@0 {
+                        ranges = <0x2000000 0x0 0xc0000000
+                                  0x2000000 0x0 0xc0000000
+                                  0x0 0x20000000
+
+                                  0x1000000 0x0 0x0
+                                  0x1000000 0x0 0x0
+                                  0x0 0x100000>;
+                };
+        };
+
+        qe: qe@fffe80000 {
+                ranges = <0x0 0xf 0xffe80000 0x40000>;
+                reg = <0xf 0xffe80000 0 0x480>;
+                brg-frequency = <0>;
+                bus-frequency = <0>;
+        };
+};
+
+/include/ "p1021rdb.dtsi"
+/include/ "fsl/p1021si-post.dtsi"
diff --git a/arch/powerpc/boot/dts/p1022ds.dts b/arch/powerpc/boot/dts/p1022ds.dts
deleted file mode 100644
index ef95717db4b..00000000000
--- a/arch/powerpc/boot/dts/p1022ds.dts
+++ /dev/null
@@ -1,274 +0,0 @@
-/*
- * P1022 DS 36Bit Physical Address Map Device Tree Source
- *
- * Copyright 2010 Freescale Semiconductor, Inc.
- *
- * This file is licensed under the terms of the GNU General Public License
- * version 2.  This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
- */
-
-/include/ "fsl/p1022si-pre.dtsi"
-/ {
-        model = "fsl,P1022DS";
-        compatible = "fsl,P1022DS";
-
-        memory {
-                device_type = "memory";
-        };
-
-        lbc: localbus@fffe05000 {
-                reg = <0xf 0xffe05000 0 0x1000>;
-                ranges = <0x0 0x0 0xf 0xe8000000 0x08000000
-                          0x1 0x0 0xf 0xe0000000 0x08000000
-                          0x2 0x0 0xf 0xff800000 0x00040000
-                          0x3 0x0 0xf 0xffdf0000 0x00008000>;
-
-                /*
-                 * This node is used to access the pixis via "indirect" mode,
-                 * which is done by writing the pixis register index to chip
-                 * select 0 and the value to/from chip select 1.  Indirect
-                 * mode is the only way to access the pixis when DIU video
-                 * is enabled.  Note that this assumes that the first column
-                 * of the 'ranges' property above is the chip select number.
-                 */
-                board-control@0,0 {
-                        compatible = "fsl,p1022ds-indirect-pixis";
-                        reg = <0x0 0x0 1        /* CS0 */
-                               0x1 0x0 1>;      /* CS1 */
-                };
-
-                nor@0,0 {
-                        #address-cells = <1>;
-                        #size-cells = <1>;
-                        compatible = "cfi-flash";
-                        reg = <0x0 0x0 0x8000000>;
-                        bank-width = <2>;
-                        device-width = <1>;
-
-                        partition@0 {
-                                reg = <0x0 0x03000000>;
-                                label = "ramdisk-nor";
-                                read-only;
-                        };
-
-                        partition@3000000 {
-                                reg = <0x03000000 0x00e00000>;
-                                label = "diagnostic-nor";
-                                read-only;
-                        };
-
-                        partition@3e00000 {
-                                reg = <0x03e00000 0x00200000>;
-                                label = "dink-nor";
-                                read-only;
-                        };
-
-                        partition@4000000 {
-                                reg = <0x04000000 0x00400000>;
-                                label = "kernel-nor";
-                                read-only;
-                        };
-
-                        partition@4400000 {
-                                reg = <0x04400000 0x03b00000>;
-                                label = "jffs2-nor";
-                        };
-
-                        partition@7f00000 {
-                                reg = <0x07f00000 0x00080000>;
-                                label = "dtb-nor";
-                                read-only;
-                        };
-
-                        partition@7f80000 {
-                                reg = <0x07f80000 0x00080000>;
-                                label = "u-boot-nor";
-                                read-only;
-                        };
-                };
-
-                nand@2,0 {
-                        #address-cells = <1>;
-                        #size-cells = <1>;
-                        compatible = "fsl,elbc-fcm-nand";
-                        reg = <0x2 0x0 0x40000>;
-
-                        partition@0 {
-                                reg = <0x0 0x02000000>;
-                                label = "u-boot-nand";
-                                read-only;
-                        };
-
-                        partition@2000000 {
-                                reg = <0x02000000 0x10000000>;
-                                label = "jffs2-nand";
-                        };
-
-                        partition@12000000 {
-                                reg = <0x12000000 0x10000000>;
-                                label = "ramdisk-nand";
-                                read-only;
-                        };
-
-                        partition@22000000 {
-                                reg = <0x22000000 0x04000000>;
-                                label = "kernel-nand";
-                        };
-
-                        partition@26000000 {
-                                reg = <0x26000000 0x01000000>;
-                                label = "dtb-nand";
-                                read-only;
-                        };
-
-                        partition@27000000 {
-                                reg = <0x27000000 0x19000000>;
-                                label = "reserved-nand";
-                        };
-                };
-
-                board-control@3,0 {
-                        compatible = "fsl,p1022ds-fpga", "fsl,fpga-ngpixis";
-                        reg = <3 0 0x30>;
-                        interrupt-parent = <&mpic>;
-                        /*
-                         * IRQ8 is generated if the "EVENT" switch is pressed
-                         * and PX_CTL[EVESEL] is set to 00.
-                         */
-                        interrupts = <8 8 0 0>;
-                };
-        };
-
-        soc: soc@fffe00000 {
-                ranges = <0x0 0xf 0xffe00000 0x100000>;
-
-                i2c@3100 {
-                        wm8776:codec@1a {
-                                compatible = "wlf,wm8776";
-                                reg = <0x1a>;
-                                /*
-                                 * clock-frequency will be set by U-Boot if
-                                 * the clock is enabled.
-                                 */
-                        };
-                };
-
-                spi@7000 {
-                        flash@0 {
-                                #address-cells = <1>;
-                                #size-cells = <1>;
-                                compatible = "spansion,s25sl12801";
-                                reg = <0>;
-                                spi-max-frequency = <40000000>; /* input clock */
-
-                                partition@0 {
-                                        label = "u-boot-spi";
-                                        reg = <0x00000000 0x00100000>;
-                                        read-only;
-                                };
-                                partition@100000 {
-                                        label = "kernel-spi";
-                                        reg = <0x00100000 0x00500000>;
-                                        read-only;
-                                };
-                                partition@600000 {
-                                        label = "dtb-spi";
-                                        reg = <0x00600000 0x00100000>;
-                                        read-only;
-                                };
-                                partition@700000 {
-                                        label = "file system-spi";
-                                        reg = <0x00700000 0x00900000>;
-                                };
-                        };
-                };
-
-                ssi@15000 {
-                        fsl,mode = "i2s-slave";
-                        codec-handle = <&wm8776>;
-                        fsl,ssi-asynchronous;
-                };
-
-                usb@22000 {
-                        phy_type = "ulpi";
-                };
-
-                usb@23000 {
-                        status = "disabled";
-                };
-
-                mdio@24000 {
-                        phy0: ethernet-phy@0 {
-                                interrupts = <3 1 0 0>;
-                                reg = <0x1>;
-                        };
-                        phy1: ethernet-phy@1 {
-                                interrupts = <9 1 0 0>;
-                                reg = <0x2>;
-                        };
-                        tbi-phy@2 {
-                                device_type = "tbi-phy";
-                                reg = <0x2>;
-                        };
-                };
-
-                ethernet@b0000 {
-                        phy-handle = <&phy0>;
-                        phy-connection-type = "rgmii-id";
-                };
-
-                ethernet@b1000 {
-                        phy-handle = <&phy1>;
-                        phy-connection-type = "rgmii-id";
-                };
-        };
-
-        pci0: pcie@fffe09000 {
-                reg = <0xf 0xffe09000 0 0x1000>;
-                ranges = <0x2000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000
-                          0x1000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x10000>;
-                pcie@0 {
-                        ranges = <0x2000000 0x0 0xe0000000
-                                  0x2000000 0x0 0xe0000000
-                                  0x0 0x20000000
-
-                                  0x1000000 0x0 0x0
-                                  0x1000000 0x0 0x0
-                                  0x0 0x100000>;
-                };
-        };
-
-        pci1: pcie@fffe0a000 {
-                reg = <0xf 0xffe0a000 0 0x1000>;
-                ranges = <0x2000000 0x0 0xe0000000 0xc 0x40000000 0x0 0x20000000
-                          0x1000000 0x0 0x00000000 0xf 0xffc20000 0x0 0x10000>;
-                pcie@0 {
-                        reg = <0x0 0x0 0x0 0x0 0x0>;
-                        ranges = <0x2000000 0x0 0xe0000000
-                                  0x2000000 0x0 0xe0000000
-                                  0x0 0x20000000
-
-                                  0x1000000 0x0 0x0
-                                  0x1000000 0x0 0x0
-                                  0x0 0x100000>;
-                };
-        };
-
-        pci2: pcie@fffe0b000 {
-                reg = <0xf 0xffe0b000 0 0x1000>;
-                ranges = <0x2000000 0x0 0xe0000000 0xc 0x00000000 0x0 0x20000000
-                          0x1000000 0x0 0x00000000 0xf 0xffc00000 0x0 0x10000>;
-                pcie@0 {
-                        ranges = <0x2000000 0x0 0xe0000000
-                                  0x2000000 0x0 0xe0000000
-                                  0x0 0x20000000
-
-                                  0x1000000 0x0 0x0
-                                  0x1000000 0x0 0x0
-                                  0x0 0x100000>;
-                };
-        };
-};
-
-/include/ "fsl/p1022si-post.dtsi"
diff --git a/arch/powerpc/boot/dts/p1022ds.dtsi b/arch/powerpc/boot/dts/p1022ds.dtsi
new file mode 100644
index 00000000000..7cdb505036b
--- /dev/null
+++ b/arch/powerpc/boot/dts/p1022ds.dtsi
@@ -0,0 +1,234 @@
+/*
+ * P1022 DS Device Tree Source stub (no addresses or top-level ranges)
+ *
+ * Copyright 2012 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+&board_lbc {
+        /*
+         * This node is used to access the pixis via "indirect" mode,
+         * which is done by writing the pixis register index to chip
+         * select 0 and the value to/from chip select 1.  Indirect
+         * mode is the only way to access the pixis when DIU video
+         * is enabled.  Note that this assumes that the first column
+         * of the 'ranges' property above is the chip select number.
+         */
+        board-control@0,0 {
+                compatible = "fsl,p1022ds-indirect-pixis";
+                reg = <0x0 0x0 1        /* CS0 */
+                       0x1 0x0 1>;      /* CS1 */
+                interrupt-parent = <&mpic>;
+                interrupts = <8 0 0 0>;
+        };
+
+        nor@0,0 {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "cfi-flash";
+                reg = <0x0 0x0 0x8000000>;
+                bank-width = <2>;
+                device-width = <1>;
+
+                partition@0 {
+                        reg = <0x0 0x03000000>;
+                        label = "ramdisk-nor";
+                        read-only;
+                };
+
+                partition@3000000 {
+                        reg = <0x03000000 0x00e00000>;
+                        label = "diagnostic-nor";
+                        read-only;
+                };
+
+                partition@3e00000 {
+                        reg = <0x03e00000 0x00200000>;
+                        label = "dink-nor";
+                        read-only;
+                };
+
+                partition@4000000 {
+                        reg = <0x04000000 0x00400000>;
+                        label = "kernel-nor";
+                        read-only;
+                };
+
+                partition@4400000 {
+                        reg = <0x04400000 0x03b00000>;
+                        label = "jffs2-nor";
+                };
+
+                partition@7f00000 {
+                        reg = <0x07f00000 0x00080000>;
+                        label = "dtb-nor";
+                        read-only;
+                };
+
+                partition@7f80000 {
+                        reg = <0x07f80000 0x00080000>;
+                        label = "u-boot-nor";
+                        read-only;
+                };
+        };
+
+        nand@2,0 {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "fsl,elbc-fcm-nand";
+                reg = <0x2 0x0 0x40000>;
+
+                partition@0 {
+                        reg = <0x0 0x02000000>;
+                        label = "u-boot-nand";
+                        read-only;
+                };
+
+                partition@2000000 {
+                        reg = <0x02000000 0x10000000>;
+                        label = "jffs2-nand";
+                };
+
+                partition@12000000 {
+                        reg = <0x12000000 0x10000000>;
+                        label = "ramdisk-nand";
+                        read-only;
+                };
+
+                partition@22000000 {
+                        reg = <0x22000000 0x04000000>;
+                        label = "kernel-nand";
+                };
+
+                partition@26000000 {
+                        reg = <0x26000000 0x01000000>;
+                        label = "dtb-nand";
+                        read-only;
+                };
+
+                partition@27000000 {
+                        reg = <0x27000000 0x19000000>;
+                        label = "reserved-nand";
+                };
+        };
+
+        board-control@3,0 {
+                compatible = "fsl,p1022ds-fpga", "fsl,fpga-ngpixis";
+                reg = <3 0 0x30>;
+                interrupt-parent = <&mpic>;
+                /*
+                 * IRQ8 is generated if the "EVENT" switch is pressed
+                 * and PX_CTL[EVESEL] is set to 00.
+                 */
+                interrupts = <8 0 0 0>;
+        };
+};
+
+&board_soc {
+        i2c@3100 {
+                wm8776:codec@1a {
+                        compatible = "wlf,wm8776";
+                        reg = <0x1a>;
+                        /*
+                         * clock-frequency will be set by U-Boot if
+                         * the clock is enabled.
+                         */
+                };
+        };
+
+        spi@7000 {
+                flash@0 {
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        compatible = "spansion,s25sl12801";
+                        reg = <0>;
+                        spi-max-frequency = <40000000>; /* input clock */
+
+                        partition@0 {
+                                label = "u-boot-spi";
+                                reg = <0x00000000 0x00100000>;
+                                read-only;
+                        };
+                        partition@100000 {
+                                label = "kernel-spi";
+                                reg = <0x00100000 0x00500000>;
+                                read-only;
+                        };
+                        partition@600000 {
+                                label = "dtb-spi";
+                                reg = <0x00600000 0x00100000>;
+                                read-only;
+                        };
+                        partition@700000 {
+                                label = "file system-spi";
+                                reg = <0x00700000 0x00900000>;
+                        };
+                };
+        };
+
+        ssi@15000 {
+                fsl,mode = "i2s-slave";
+                codec-handle = <&wm8776>;
+                fsl,ssi-asynchronous;
+        };
+
+        usb@22000 {
+                phy_type = "ulpi";
+        };
+
+        usb@23000 {
+                status = "disabled";
+        };
+
+        mdio@24000 {
+                phy0: ethernet-phy@0 {
+                        interrupts = <3 1 0 0>;
+                        reg = <0x1>;
+                };
+                phy1: ethernet-phy@1 {
+                        interrupts = <9 1 0 0>;
+                        reg = <0x2>;
+                };
+                tbi-phy@2 {
+                        device_type = "tbi-phy";
+                        reg = <0x2>;
+                };
+        };
+
+        ethernet@b0000 {
+                phy-handle = <&phy0>;
+                phy-connection-type = "rgmii-id";
+        };
+
+        ethernet@b1000 {
+                phy-handle = <&phy1>;
+                phy-connection-type = "rgmii-id";
+        };
+};
diff --git a/arch/powerpc/boot/dts/p1022ds_32b.dts b/arch/powerpc/boot/dts/p1022ds_32b.dts
new file mode 100644
index 00000000000..d96cae00a9e
--- /dev/null
+++ b/arch/powerpc/boot/dts/p1022ds_32b.dts
@@ -0,0 +1,103 @@
+/*
+ * P1022 DS 32-bit Physical Address Map Device Tree Source
+ *
+ * Copyright 2012 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/include/ "fsl/p1022si-pre.dtsi"
+/ {
+        model = "fsl,P1022DS";
+        compatible = "fsl,P1022DS";
+
+        memory {
+                device_type = "memory";
+        };
+
+        board_lbc: lbc: localbus@ffe05000 {
+                ranges = <0x0 0x0 0x0 0xe8000000 0x08000000
+                          0x1 0x0 0x0 0xe0000000 0x08000000
+                          0x2 0x0 0x0 0xff800000 0x00040000
+                          0x3 0x0 0x0 0xffdf0000 0x00008000>;
+                reg = <0x0 0xffe05000 0 0x1000>;
+        };
+
+        board_soc: soc: soc@ffe00000 {
+                ranges = <0x0 0x0 0xffe00000 0x100000>;
+        };
+
+        pci0: pcie@ffe09000 {
+                ranges = <0x2000000 0x0 0xe0000000 0 0xa0000000 0x0 0x20000000
+                          0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
+                reg = <0x0 0xffe09000 0 0x1000>;
+                pcie@0 {
+                        ranges = <0x2000000 0x0 0xe0000000
+                                  0x2000000 0x0 0xe0000000
+                                  0x0 0x20000000
+
+                                  0x1000000 0x0 0x0
+                                  0x1000000 0x0 0x0
+                                  0x0 0x100000>;
+                };
+        };
+
+        pci1: pcie@ffe0a000 {
+                ranges = <0x2000000 0x0 0xe0000000 0 0xc0000000 0x0 0x20000000
+                          0x1000000 0x0 0x00000000 0 0xffc20000 0x0 0x10000>;
+                reg = <0 0xffe0a000 0 0x1000>;
+                pcie@0 {
+                        ranges = <0x2000000 0x0 0xe0000000
+                                  0x2000000 0x0 0xe0000000
+                                  0x0 0x20000000
+
+                                  0x1000000 0x0 0x0
+                                  0x1000000 0x0 0x0
+                                  0x0 0x100000>;
+                };
+        };
+
+        pci2: pcie@ffe0b000 {
+                ranges = <0x2000000 0x0 0xe0000000 0 0x80000000 0x0 0x20000000
+                          0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
+                reg = <0 0xffe0b000 0 0x1000>;
+                pcie@0 {
+                        ranges = <0x2000000 0x0 0xe0000000
+                                  0x2000000 0x0 0xe0000000
+                                  0x0 0x20000000
+
+                                  0x1000000 0x0 0x0
+                                  0x1000000 0x0 0x0
+                                  0x0 0x100000>;
+                };
+        };
+};
+
+/include/ "fsl/p1022si-post.dtsi"
+/include/ "p1022ds.dtsi"
diff --git a/arch/powerpc/boot/dts/p1022ds_36b.dts b/arch/powerpc/boot/dts/p1022ds_36b.dts
new file mode 100644
index 00000000000..f7aacce40bf
--- /dev/null
+++ b/arch/powerpc/boot/dts/p1022ds_36b.dts
@@ -0,0 +1,103 @@
+/*
+ * P1022 DS 36-bit Physical Address Map Device Tree Source
+ *
+ * Copyright 2012 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/include/ "fsl/p1022si-pre.dtsi"
+/ {
+        model = "fsl,P1022DS";
+        compatible = "fsl,P1022DS";
+
+        memory {
+                device_type = "memory";
+        };
+
+        board_lbc: lbc: localbus@fffe05000 {
+                ranges = <0x0 0x0 0xf 0xe8000000 0x08000000
+                          0x1 0x0 0xf 0xe0000000 0x08000000
+                          0x2 0x0 0xf 0xff800000 0x00040000
+                          0x3 0x0 0xf 0xffdf0000 0x00008000>;
+                reg = <0xf 0xffe05000 0 0x1000>;
+        };
+
+        board_soc: soc: soc@fffe00000 {
+                ranges = <0x0 0xf 0xffe00000 0x100000>;
+        };
+
+        pci0: pcie@fffe09000 {
+                ranges = <0x2000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000
+                          0x1000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x10000>;
+                reg = <0xf 0xffe09000 0 0x1000>;
+                pcie@0 {
+                        ranges = <0x2000000 0x0 0xe0000000
+                                  0x2000000 0x0 0xe0000000
+                                  0x0 0x20000000
+
+                                  0x1000000 0x0 0x0
+                                  0x1000000 0x0 0x0
+                                  0x0 0x100000>;
+                };
+        };
+
+        pci1: pcie@fffe0a000 {
+                ranges = <0x2000000 0x0 0xe0000000 0xc 0x40000000 0x0 0x20000000
+                          0x1000000 0x0 0x00000000 0xf 0xffc20000 0x0 0x10000>;
+                reg = <0xf 0xffe0a000 0 0x1000>;
+                pcie@0 {
+                        ranges = <0x2000000 0x0 0xe0000000
+                                  0x2000000 0x0 0xe0000000
+                                  0x0 0x20000000
+
+                                  0x1000000 0x0 0x0
+                                  0x1000000 0x0 0x0
+                                  0x0 0x100000>;
+                };
+        };
+
+        pci2: pcie@fffe0b000 {
+                ranges = <0x2000000 0x0 0xe0000000 0xc 0x00000000 0x0 0x20000000
+                          0x1000000 0x0 0x00000000 0xf 0xffc00000 0x0 0x10000>;
+                reg = <0xf 0xffe0b000 0 0x1000>;
+                pcie@0 {
+                        ranges = <0x2000000 0x0 0xe0000000
+                                  0x2000000 0x0 0xe0000000
+                                  0x0 0x20000000
+
+                                  0x1000000 0x0 0x0
+                                  0x1000000 0x0 0x0
+                                  0x0 0x100000>;
+                };
+        };
+};
+
+/include/ "fsl/p1022si-post.dtsi"
+/include/ "p1022ds.dtsi"
diff --git a/arch/powerpc/boot/dts/p1025rdb.dtsi b/arch/powerpc/boot/dts/p1025rdb.dtsi
new file mode 100644
index 00000000000..cf3676fc714
--- /dev/null
+++ b/arch/powerpc/boot/dts/p1025rdb.dtsi
@@ -0,0 +1,286 @@
+/*
+ * P1025 RDB Device Tree Source stub (no addresses or top-level ranges)
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+&lbc {
+        nor@0,0 {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "cfi-flash";
+                reg = <0x0 0x0 0x1000000>;
+                bank-width = <2>;
+                device-width = <1>;
+
+                partition@0 {
+                        /* This location must not be altered  */
+                        /* 256KB for Vitesse 7385 Switch firmware */
+                        reg = <0x0 0x00040000>;
+                        label = "NOR Vitesse-7385 Firmware";
+                        read-only;
+                };
+
+                partition@40000 {
+                        /* 256KB for DTB Image */
+                        reg = <0x00040000 0x00040000>;
+                        label = "NOR DTB Image";
+                };
+
+                partition@80000 {
+                        /* 3.5 MB for Linux Kernel Image */
+                        reg = <0x00080000 0x00380000>;
+                        label = "NOR Linux Kernel Image";
+                };
+
+                partition@400000 {
+                        /* 11MB for JFFS2 based Root file System */
+                        reg = <0x00400000 0x00b00000>;
+                        label = "NOR JFFS2 Root File System";
+                };
+
+                partition@f00000 {
+                        /* This location must not be altered  */
+                        /* 512KB for u-boot Bootloader Image */
+                        /* 512KB for u-boot Environment Variables */
+                        reg = <0x00f00000 0x00100000>;
+                        label = "NOR U-Boot Image";
+                        read-only;
+                };
+        };
+
+        nand@1,0 {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "fsl,p1025-fcm-nand",
+                             "fsl,elbc-fcm-nand";
+                reg = <0x1 0x0 0x40000>;
+
+                partition@0 {
+                        /* This location must not be altered  */
+                        /* 1MB for u-boot Bootloader Image */
+                        reg = <0x0 0x00100000>;
+                        label = "NAND U-Boot Image";
+                        read-only;
+                };
+
+                partition@100000 {
+                        /* 1MB for DTB Image */
+                        reg = <0x00100000 0x00100000>;
+                        label = "NAND DTB Image";
+                };
+
+                partition@200000 {
+                        /* 4MB for Linux Kernel Image */
+                        reg = <0x00200000 0x00400000>;
+                        label = "NAND Linux Kernel Image";
+                };
+
+                partition@600000 {
+                        /* 4MB for Compressed Root file System Image */
+                        reg = <0x00600000 0x00400000>;
+                        label = "NAND Compressed RFS Image";
+                };
+
+                partition@a00000 {
+                        /* 7MB for JFFS2 based Root file System */
+                        reg = <0x00a00000 0x00700000>;
+                        label = "NAND JFFS2 Root File System";
+                };
+
+                partition@1100000 {
+                        /* 15MB for JFFS2 based Root file System */
+                        reg = <0x01100000 0x00f00000>;
+                        label = "NAND Writable User area";
+                };
+        };
+
+};
+
+&soc {
+        i2c@3000 {
+                rtc@68 {
+                        compatible = "dallas,ds1339";
+                        reg = <0x68>;
+                };
+        };
+
+        spi@7000 {
+                flash@0 {
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        compatible = "spansion,s25sl12801";
+                        reg = <0>;
+                        spi-max-frequency = <40000000>; /* input clock */
+
+                        partition@u-boot {
+                                /* 512KB for u-boot Bootloader Image */
+                                reg = <0x0 0x00080000>;
+                                label = "u-boot";
+                                read-only;
+                        };
+
+                        partition@dtb {
+                                /* 512KB for DTB Image */
+                                reg = <0x00080000 0x00080000>;
+                                label = "dtb";
+                        };
+
+                        partition@kernel {
+                                /* 4MB for Linux Kernel Image */
+                                reg = <0x00100000 0x00400000>;
+                                label = "kernel";
+                        };
+
+                        partition@fs {
+                                /* 4MB for Compressed RFS Image */
+                                reg = <0x00500000 0x00400000>;
+                                label = "file system";
+                        };
+
+                        partition@jffs-fs {
+                                /* 7MB for JFFS2 based RFS */
+                                reg = <0x00900000 0x00700000>;
+                                label = "file system jffs2";
+                        };
+                };
+        };
+
+        usb@22000 {
+                phy_type = "ulpi";
+        };
+
+        /* USB2 is shared with localbus, so it must be disabled
+           by default. We can't put 'status = "disabled";' here
+           since U-Boot doesn't clear the status property when
+           it enables USB2. OTOH, U-Boot does create a new node
+           when there isn't any. So, just comment it out.
+        usb@23000 {
+                phy_type = "ulpi";
+        };
+        */
+
+        mdio@24000 {
+                phy0: ethernet-phy@0 {
+                        interrupt-parent = <&mpic>;
+                        interrupts = <3 1>;
+                        reg = <0x0>;
+                };
+
+                phy1: ethernet-phy@1 {
+                        interrupt-parent = <&mpic>;
+                        interrupts = <2 1>;
+                        reg = <0x1>;
+                };
+
+                tbi0: tbi-phy@11 {
+                        reg = <0x11>;
+                        device_type = "tbi-phy";
+                };
+        };
+
+        mdio@25000 {
+                tbi1: tbi-phy@11 {
+                        reg = <0x11>;
+                        device_type = "tbi-phy";
+                };
+        };
+
+        mdio@26000 {
+                tbi2: tbi-phy@11 {
+                        reg = <0x11>;
+                        device_type = "tbi-phy";
+                };
+        };
+
+        enet0: ethernet@b0000 {
+                fixed-link = <1 1 1000 0 0>;
+                phy-connection-type = "rgmii-id";
+
+        };
+
+        enet1: ethernet@b1000 {
+                phy-handle = <&phy0>;
+                tbi-handle = <&tbi1>;
+                phy-connection-type = "sgmii";
+        };
+
+        enet2: ethernet@b2000 {
+                phy-handle = <&phy1>;
+                phy-connection-type = "rgmii-id";
+        };
+
+        par_io@e0100 {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                reg = <0xe0100 0x60>;
+                ranges = <0x0 0xe0100 0x60>;
+                device_type = "par_io";
+                num-ports = <3>;
+                pio1: ucc_pin@01 {
+                        pio-map = <
+                /* port  pin  dir  open_drain  assignment  has_irq */
+                                0x1  0x13 0x1  0x0  0x1  0x0    /* QE_MUX_MDC */
+                                0x1  0x14 0x3  0x0  0x1  0x0    /* QE_MUX_MDIO */
+                                0x0  0x17 0x2  0x0  0x2  0x0    /* CLK12 */
+                                0x0  0x18 0x2  0x0  0x1  0x0    /* CLK9 */
+                                0x0  0x7  0x1  0x0  0x2  0x0    /* ENET1_TXD0_SER1_TXD0 */
+                                0x0  0x9  0x1  0x0  0x2  0x0    /* ENET1_TXD1_SER1_TXD1 */
+                                0x0  0xb  0x1  0x0  0x2  0x0    /* ENET1_TXD2_SER1_TXD2 */
+                                0x0  0xc  0x1  0x0  0x2  0x0    /* ENET1_TXD3_SER1_TXD3 */
+                                0x0  0x6  0x2  0x0  0x2  0x0    /* ENET1_RXD0_SER1_RXD0 */
+                                0x0  0xa  0x2  0x0  0x2  0x0    /* ENET1_RXD1_SER1_RXD1 */
+                                0x0  0xe  0x2  0x0  0x2  0x0    /* ENET1_RXD2_SER1_RXD2 */
+                                0x0  0xf  0x2  0x0  0x2  0x0    /* ENET1_RXD3_SER1_RXD3 */
+                                0x0  0x5  0x1  0x0  0x2  0x0    /* ENET1_TX_EN_SER1_RTS_B */
+                                0x0  0xd  0x1  0x0  0x2  0x0    /* ENET1_TX_ER */
+                                0x0  0x4  0x2  0x0  0x2  0x0    /* ENET1_RX_DV_SER1_CTS_B */
+                                0x0  0x8  0x2  0x0  0x2  0x0    /* ENET1_RX_ER_SER1_CD_B */
+                                0x0  0x11 0x2  0x0  0x2  0x0    /* ENET1_CRS */
+                                0x0  0x10 0x2  0x0  0x2  0x0>;    /* ENET1_COL */
+                };
+
+                pio2: ucc_pin@02 {
+                        pio-map = <
+                /* port  pin  dir  open_drain  assignment  has_irq */
+                                0x1  0x13 0x1  0x0  0x1  0x0    /* QE_MUX_MDC */
+                                0x1  0x14 0x3  0x0  0x1  0x0    /* QE_MUX_MDIO */
+                                0x1  0xb  0x2  0x0  0x1  0x0    /* CLK13 */
+                                0x1  0x7  0x1  0x0  0x2  0x0    /* ENET5_TXD0_SER5_TXD0 */
+                                0x1  0xa  0x1  0x0  0x2  0x0    /* ENET5_TXD1_SER5_TXD1 */
+                                0x1  0x6  0x2  0x0  0x2  0x0    /* ENET5_RXD0_SER5_RXD0 */
+                                0x1  0x9  0x2  0x0  0x2  0x0    /* ENET5_RXD1_SER5_RXD1 */
+                                0x1  0x5  0x1  0x0  0x2  0x0    /* ENET5_TX_EN_SER5_RTS_B */
+                                0x1  0x4  0x2  0x0  0x2  0x0    /* ENET5_RX_DV_SER5_CTS_B */
+                                0x1  0x8  0x2  0x0  0x2  0x0>;    /* ENET5_RX_ER_SER5_CD_B */
+                };
+        };
+};
diff --git a/arch/powerpc/boot/dts/p1025rdb_32b.dts b/arch/powerpc/boot/dts/p1025rdb_32b.dts
new file mode 100644
index 00000000000..ac5729c14ed
--- /dev/null
+++ b/arch/powerpc/boot/dts/p1025rdb_32b.dts
@@ -0,0 +1,135 @@
+/*
+ * P1025 RDB Device Tree Source (32-bit address map)
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/include/ "fsl/p1021si-pre.dtsi"
+/ {
+        model = "fsl,P1025RDB";
+        compatible = "fsl,P1025RDB";
+
+        memory {
+                device_type = "memory";
+        };
+
+        lbc: localbus@ffe05000 {
+                reg = <0 0xffe05000 0 0x1000>;
+
+                /* NOR, NAND Flashes */
+                ranges = <0x0 0x0 0x0 0xef000000 0x01000000
+                          0x1 0x0 0x0 0xff800000 0x00040000>;
+        };
+
+        soc: soc@ffe00000 {
+                ranges = <0x0 0x0 0xffe00000 0x100000>;
+        };
+
+        pci0: pcie@ffe09000 {
+                ranges = <0x2000000 0x0 0xe0000000 0 0xe0000000 0x0 0x20000000
+                          0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
+                reg = <0 0xffe09000 0 0x1000>;
+                pcie@0 {
+                        ranges = <0x2000000 0x0 0xe0000000
+                                  0x2000000 0x0 0xe0000000
+                                  0x0 0x20000000
+
+                                  0x1000000 0x0 0x0
+                                  0x1000000 0x0 0x0
+                                  0x0 0x100000>;
+                };
+        };
+
+        pci1: pcie@ffe0a000 {
+                reg = <0 0xffe0a000 0 0x1000>;
+                ranges = <0x2000000 0x0 0xe0000000 0 0xe0000000 0x0 0x20000000
+                          0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
+                pcie@0 {
+                        ranges = <0x2000000 0x0 0xe0000000
+                                  0x2000000 0x0 0xe0000000
+                                  0x0 0x20000000
+
+                                  0x1000000 0x0 0x0
+                                  0x1000000 0x0 0x0
+                                  0x0 0x100000>;
+                };
+        };
+
+        qe: qe@ffe80000 {
+                ranges = <0x0 0x0 0xffe80000 0x40000>;
+                reg = <0 0xffe80000 0 0x480>;
+                brg-frequency = <0>;
+                bus-frequency = <0>;
+                status = "disabled"; /* no firmware loaded */
+
+                enet3: ucc@2000 {
+                        device_type = "network";
+                        compatible = "ucc_geth";
+                        rx-clock-name = "clk12";
+                        tx-clock-name = "clk9";
+                        pio-handle = <&pio1>;
+                        phy-handle = <&qe_phy0>;
+                        phy-connection-type = "mii";
+                };
+
+                mdio@2120 {
+                        qe_phy0: ethernet-phy@0 {
+                                interrupt-parent = <&mpic>;
+                                interrupts = <4 1 0 0>;
+                                reg = <0x6>;
+                                device_type = "ethernet-phy";
+                        };
+                        qe_phy1: ethernet-phy@03 {
+                                interrupt-parent = <&mpic>;
+                                interrupts = <5 1 0 0>;
+                                reg = <0x3>;
+                                device_type = "ethernet-phy";
+                        };
+                        tbi-phy@11 {
+                                reg = <0x11>;
+                                device_type = "tbi-phy";
+                        };
+                };
+
+                enet4: ucc@2400 {
+                        device_type = "network";
+                        compatible = "ucc_geth";
+                        rx-clock-name = "none";
+                        tx-clock-name = "clk13";
+                        pio-handle = <&pio2>;
+                        phy-handle = <&qe_phy1>;
+                        phy-connection-type = "rmii";
+                };
+        };
+};
+
+/include/ "p1025rdb.dtsi"
+/include/ "fsl/p1021si-post.dtsi"
diff --git a/arch/powerpc/boot/dts/p1025rdb_36b.dts b/arch/powerpc/boot/dts/p1025rdb_36b.dts
new file mode 100644
index 00000000000..4ce4bfa0eda
--- /dev/null
+++ b/arch/powerpc/boot/dts/p1025rdb_36b.dts
@@ -0,0 +1,88 @@
+/*
+ * P1025 RDB Device Tree Source (36-bit address map)
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/include/ "fsl/p1021si-pre.dtsi"
+/ {
+        model = "fsl,P1025RDB";
+        compatible = "fsl,P1025RDB";
+
+        memory {
+                device_type = "memory";
+        };
+
+        lbc: localbus@fffe05000 {
+                reg = <0xf 0xffe05000 0 0x1000>;
+
+                /* NOR, NAND Flashes */
+                ranges = <0x0 0x0 0xf 0xef000000 0x01000000
+                          0x1 0x0 0xf 0xff800000 0x00040000>;
+        };
+
+        soc: soc@fffe00000 {
+                ranges = <0x0 0xf 0xffe00000 0x100000>;
+        };
+
+        pci0: pcie@fffe09000 {
+                reg = <0xf 0xffe09000 0 0x1000>;
+                ranges = <0x2000000 0x0 0xe0000000 0xe 0x20000000 0x0 0x20000000
+                          0x1000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x10000>;
+                pcie@0 {
+                        ranges = <0x2000000 0x0 0xe0000000
+                                  0x2000000 0x0 0xe0000000
+                                  0x0 0x20000000
+
+                                  0x1000000 0x0 0x0
+                                  0x1000000 0x0 0x0
+                                  0x0 0x100000>;
+                };
+        };
+
+        pci1: pcie@fffe0a000 {
+                reg = <0xf 0xffe0a000 0 0x1000>;
+                ranges = <0x2000000 0x0 0xe0000000 0xc 0x00000000 0x0 0x20000000
+                          0x1000000 0x0 0x00000000 0xf 0xffc00000 0x0 0x10000>;
+                pcie@0 {
+                        ranges = <0x2000000 0x0 0xe0000000
+                                  0x2000000 0x0 0xe0000000
+                                  0x0 0x20000000
+
+                                  0x1000000 0x0 0x0
+                                  0x1000000 0x0 0x0
+                                  0x0 0x100000>;
+                };
+        };
+};
+
+/include/ "p1025rdb.dtsi"
+/include/ "fsl/p1021si-post.dtsi"
diff --git a/arch/powerpc/boot/dts/p2020rdb-pc.dtsi b/arch/powerpc/boot/dts/p2020rdb-pc.dtsi
new file mode 100644
index 00000000000..c21d1c7d16c
--- /dev/null
+++ b/arch/powerpc/boot/dts/p2020rdb-pc.dtsi
@@ -0,0 +1,241 @@
+/*
+ * P2020 RDB-PC Device Tree Source stub (no addresses or top-level ranges)
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+&lbc {
+        nor@0,0 {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "cfi-flash";
+                reg = <0x0 0x0 0x1000000>;
+                bank-width = <2>;
+                device-width = <1>;
+
+                partition@0 {
+                        /* This location must not be altered  */
+                        /* 256KB for Vitesse 7385 Switch firmware */
+                        reg = <0x0 0x00040000>;
+                        label = "NOR Vitesse-7385 Firmware";
+                        read-only;
+                };
+
+                partition@40000 {
+                        /* 256KB for DTB Image */
+                        reg = <0x00040000 0x00040000>;
+                        label = "NOR DTB Image";
+                };
+
+                partition@80000 {
+                        /* 3.5 MB for Linux Kernel Image */
+                        reg = <0x00080000 0x00380000>;
+                        label = "NOR Linux Kernel Image";
+                };
+
+                partition@400000 {
+                        /* 11MB for JFFS2 based Root file System */
+                        reg = <0x00400000 0x00b00000>;
+                        label = "NOR JFFS2 Root File System";
+                };
+
+                partition@f00000 {
+                        /* This location must not be altered  */
+                        /* 512KB for u-boot Bootloader Image */
+                        /* 512KB for u-boot Environment Variables */
+                        reg = <0x00f00000 0x00100000>;
+                        label = "NOR U-Boot Image";
+                        read-only;
+                };
+        };
+
+        nand@1,0 {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "fsl,p2020-fcm-nand",
+                                 "fsl,elbc-fcm-nand";
+                reg = <0x1 0x0 0x40000>;
+
+                partition@0 {
+                        /* This location must not be altered  */
+                        /* 1MB for u-boot Bootloader Image */
+                        reg = <0x0 0x00100000>;
+                        label = "NAND U-Boot Image";
+                        read-only;
+                };
+
+                partition@100000 {
+                        /* 1MB for DTB Image */
+                        reg = <0x00100000 0x00100000>;
+                        label = "NAND DTB Image";
+                };
+
+                partition@200000 {
+                        /* 4MB for Linux Kernel Image */
+                        reg = <0x00200000 0x00400000>;
+                        label = "NAND Linux Kernel Image";
+                };
+
+                partition@600000 {
+                        /* 4MB for Compressed Root file System Image */
+                        reg = <0x00600000 0x00400000>;
+                        label = "NAND Compressed RFS Image";
+                };
+
+                partition@a00000 {
+                        /* 7MB for JFFS2 based Root file System */
+                        reg = <0x00a00000 0x00700000>;
+                        label = "NAND JFFS2 Root File System";
+                };
+
+                partition@1100000 {
+                        /* 15MB for JFFS2 based Root file System */
+                        reg = <0x01100000 0x00f00000>;
+                        label = "NAND Writable User area";
+                };
+        };
+
+        L2switch@2,0 {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "vitesse-7385";
+                reg = <0x2 0x0 0x20000>;
+        };
+
+        cpld@3,0 {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "cpld";
+                reg = <0x3 0x0 0x20000>;
+                read-only;
+        };
+};
+
+&soc {
+        i2c@3000 {
+                rtc@68 {
+                        compatible = "pericom,pt7c4338";
+                        reg = <0x68>;
+                };
+        };
+
+        spi@7000 {
+                flash@0 {
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        compatible = "spansion,m25p80";
+                        reg = <0>;
+                        spi-max-frequency = <40000000>;
+
+                        partition@0 {
+                                /* 512KB for u-boot Bootloader Image */
+                                reg = <0x0 0x00080000>;
+                                label = "SPI U-Boot Image";
+                                read-only;
+                        };
+
+                        partition@80000 {
+                                /* 512KB for DTB Image */
+                                reg = <0x00080000 0x00080000>;
+                                label = "SPI DTB Image";
+                        };
+
+                        partition@100000 {
+                                /* 4MB for Linux Kernel Image */
+                                reg = <0x00100000 0x00400000>;
+                                label = "SPI Linux Kernel Image";
+                        };
+
+                        partition@500000 {
+                                /* 4MB for Compressed RFS Image */
+                                reg = <0x00500000 0x00400000>;
+                                label = "SPI Compressed RFS Image";
+                        };
+
+                        partition@900000 {
+                                /* 7MB for JFFS2 based RFS */
+                                reg = <0x00900000 0x00700000>;
+                                label = "SPI JFFS2 RFS";
+                        };
+                };
+        };
+
+        usb@22000 {
+                phy_type = "ulpi";
+        };
+
+        mdio@24520 {
+                phy0: ethernet-phy@0 {
+                        interrupts = <3 1 0 0>;
+                        reg = <0x0>;
+                        };
+                phy1: ethernet-phy@1 {
+                        interrupts = <2 1 0 0>;
+                        reg = <0x1>;
+                        };
+        };
+
+        mdio@25520 {
+                tbi0: tbi-phy@11 {
+                        reg = <0x11>;
+                        device_type = "tbi-phy";
+                };
+        };
+
+        mdio@26520 {
+                status = "disabled";
+        };
+
+        ptp_clock@24e00 {
+                fsl,tclk-period = <5>;
+                fsl,tmr-prsc = <200>;
+                fsl,tmr-add = <0xCCCCCCCD>;
+                fsl,tmr-fiper1 = <0x3B9AC9FB>;
+                fsl,tmr-fiper2 = <0x0001869B>;
+                fsl,max-adj = <249999999>;
+        };
+
+        enet0: ethernet@24000 {
+                fixed-link = <1 1 1000 0 0>;
+                phy-connection-type = "rgmii-id";
+        };
+
+        enet1: ethernet@25000 {
+                tbi-handle = <&tbi0>;
+                phy-handle = <&phy0>;
+                phy-connection-type = "sgmii";
+        };
+
+        enet2: ethernet@26000 {
+                phy-handle = <&phy1>;
+                phy-connection-type = "rgmii-id";
+        };
+};
diff --git a/arch/powerpc/boot/dts/p2020rdb-pc_32b.dts b/arch/powerpc/boot/dts/p2020rdb-pc_32b.dts
new file mode 100644
index 00000000000..852e5b27485
--- /dev/null
+++ b/arch/powerpc/boot/dts/p2020rdb-pc_32b.dts
@@ -0,0 +1,96 @@
+/*
+ * P2020 RDB-PC 32Bit Physical Address Map Device Tree Source
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/include/ "fsl/p2020si-pre.dtsi"
+
+/ {
+        model = "fsl,P2020RDB";
+        compatible = "fsl,P2020RDB-PC";
+
+        memory {
+                device_type = "memory";
+        };
+
+        lbc: localbus@ffe05000 {
+                reg = <0 0xffe05000 0 0x1000>;
+
+                /* NOR and NAND Flashes */
+                ranges = <0x0 0x0 0x0 0xef000000 0x01000000
+                          0x1 0x0 0x0 0xff800000 0x00040000
+                          0x2 0x0 0x0 0xffb00000 0x00020000
+                          0x3 0x0 0x0 0xffa00000 0x00020000>;
+        };
+
+        soc: soc@ffe00000 {
+                ranges = <0x0 0x0 0xffe00000 0x100000>;
+        };
+
+        pci0: pcie@ffe08000 {
+                reg = <0 0xffe08000 0 0x1000>;
+                status = "disabled";
+        };
+
+        pci1: pcie@ffe09000 {
+                reg = <0 0xffe09000 0 0x1000>;
+                ranges = <0x2000000 0x0 0xe0000000 0 0xa0000000 0x0 0x20000000
+                          0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
+                pcie@0 {
+                        ranges = <0x2000000 0x0 0xe0000000
+                                  0x2000000 0x0 0xe0000000
+                                  0x0 0x20000000
+
+                                  0x1000000 0x0 0x0
+                                  0x1000000 0x0 0x0
+                                  0x0 0x100000>;
+                };
+        };
+
+        pci2: pcie@ffe0a000 {
+                reg = <0 0xffe0a000 0 0x1000>;
+                ranges = <0x2000000 0x0 0xe0000000 0 0x80000000 0x0 0x20000000
+                          0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
+                pcie@0 {
+                        ranges = <0x2000000 0x0 0xe0000000
+                                  0x2000000 0x0 0xe0000000
+                                  0x0 0x20000000
+
+                                  0x1000000 0x0 0x0
+                                  0x1000000 0x0 0x0
+                                  0x0 0x100000>;
+                };
+        };
+};
+
+/include/ "p2020rdb-pc.dtsi"
+/include/ "fsl/p2020si-post.dtsi"
diff --git a/arch/powerpc/boot/dts/p2020rdb-pc_36b.dts b/arch/powerpc/boot/dts/p2020rdb-pc_36b.dts
new file mode 100644
index 00000000000..b5a56ca51cf
--- /dev/null
+++ b/arch/powerpc/boot/dts/p2020rdb-pc_36b.dts
@@ -0,0 +1,96 @@
+/*
+ * P2020 RDB-PC 36Bit Physical Address Map Device Tree Source
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/include/ "fsl/p2020si-pre.dtsi"
+
+/ {
+        model = "fsl,P2020RDB";
+        compatible = "fsl,P2020RDB-PC";
+
+        memory {
+                device_type = "memory";
+        };
+
+        lbc: localbus@fffe05000 {
+                reg = <0xf 0xffe05000 0 0x1000>;
+
+                /* NOR and NAND Flashes */
+                ranges = <0x0 0x0 0xf 0xef000000 0x01000000
+                          0x1 0x0 0xf 0xff800000 0x00040000
+                          0x2 0x0 0xf 0xffb00000 0x00020000
+                          0x3 0x0 0xf 0xffa00000 0x00020000>;
+        };
+
+        soc: soc@fffe00000 {
+                ranges = <0x0 0xf 0xffe00000 0x100000>;
+        };
+
+        pci0: pcie@fffe08000 {
+                reg = <0xf 0xffe08000 0 0x1000>;
+                status = "disabled";
+        };
+
+        pci1: pcie@fffe09000 {
+                reg = <0xf 0xffe09000 0 0x1000>;
+                ranges = <0x2000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000
+                          0x1000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x10000>;
+                pcie@0 {
+                        ranges = <0x2000000 0x0 0xe0000000
+                                  0x2000000 0x0 0xe0000000
+                                  0x0 0x20000000
+
+                                  0x1000000 0x0 0x0
+                                  0x1000000 0x0 0x0
+                                  0x0 0x100000>;
+                };
+        };
+
+        pci2: pcie@fffe0a000 {
+                reg = <0xf 0xffe0a000 0 0x1000>;
+                ranges = <0x2000000 0x0 0xe0000000 0xc 0x00000000 0x0 0x20000000
+                          0x1000000 0x0 0x00000000 0xf 0xffc00000 0x0 0x10000>;
+                pcie@0 {
+                        ranges = <0x2000000 0x0 0xe0000000
+                                  0x2000000 0x0 0xe0000000
+                                  0x0 0x20000000
+
+                                  0x1000000 0x0 0x0
+                                  0x1000000 0x0 0x0
+                                  0x0 0x100000>;
+                };
+        };
+};
+
+/include/ "p2020rdb-pc.dtsi"
+/include/ "fsl/p2020si-post.dtsi"
diff --git a/arch/powerpc/boot/dts/p2020rdb.dts b/arch/powerpc/boot/dts/p2020rdb.dts
index eb8a6aa2bda..153bc76bb48 100644
--- a/arch/powerpc/boot/dts/p2020rdb.dts
+++ b/arch/powerpc/boot/dts/p2020rdb.dts
@@ -34,7 +34,7 @@
 
                 /* NOR and NAND Flashes */
                 ranges = <0x0 0x0 0x0 0xef000000 0x01000000
-                          0x1 0x0 0x0 0xffa00000 0x00040000
+                          0x1 0x0 0x0 0xff800000 0x00040000
                           0x2 0x0 0x0 0xffb00000 0x00020000>;
 
                 nor@0,0 {
@@ -157,7 +157,7 @@
                                 #size-cells = <1>;
                                 compatible = "spansion,s25sl12801";
                                 reg = <0>;
-                                spi-max-frequency = <50000000>;
+                                spi-max-frequency = <40000000>;
 
                                 partition@0 {
                                         /* 512KB for u-boot Bootloader Image */
diff --git a/arch/powerpc/boot/wrapper b/arch/powerpc/boot/wrapper
index f090e6d2907..6761c746048 100755
--- a/arch/powerpc/boot/wrapper
+++ b/arch/powerpc/boot/wrapper
@@ -144,6 +144,7 @@ tmp=$tmpdir/zImage.$$.o
 ksection=.kernel:vmlinux.strip
 isection=.kernel:initrd
 link_address='0x400000'
+make_space=y
 
 case "$platform" in
 pseries)
@@ -210,6 +211,7 @@ ps3)
     ksection=.kernel:vmlinux.bin
     isection=.kernel:initrd
     link_address=''
+    make_space=n
     pie=
     ;;
 ep88xc|ep405|ep8248e)
@@ -278,17 +280,19 @@ else
     rm -f $vmz.$$
 fi
 
-# Round the size to next higher MB limit
-round_size=$(((strip_size + 0xfffff) & 0xfff00000))
+if [ "$make_space" = "y" ]; then
+        # Round the size to next higher MB limit
+        round_size=$(((strip_size + 0xfffff) & 0xfff00000))
 
-round_size=0x$(printf "%x" $round_size)
-link_addr=$(printf "%d" $link_address)
+        round_size=0x$(printf "%x" $round_size)
+        link_addr=$(printf "%d" $link_address)
 
-if [ $link_addr -lt $strip_size ]; then
-    echo "INFO: Uncompressed kernel (size 0x$(printf "%x\n" $strip_size))" \
-                "overlaps the address of the wrapper($link_address)"
-    echo "INFO: Fixing the link_address of wrapper to ($round_size)"
-    link_address=$round_size
+        if [ $link_addr -lt $strip_size ]; then
+            echo "INFO: Uncompressed kernel (size 0x$(printf "%x\n" $strip_size))" \
+                        "overlaps the address of the wrapper($link_address)"
+            echo "INFO: Fixing the link_address of wrapper to ($round_size)"
+            link_address=$round_size
+        fi
 fi
 
 vmz="$vmz$gzip"
diff --git a/arch/powerpc/configs/85xx/ge_imp3a_defconfig b/arch/powerpc/configs/85xx/ge_imp3a_defconfig
new file mode 100644
index 00000000000..f8c51a4ab99
--- /dev/null
+++ b/arch/powerpc/configs/85xx/ge_imp3a_defconfig
@@ -0,0 +1,257 @@
+CONFIG_PPC_85xx=y
+CONFIG_SMP=y
+CONFIG_NR_CPUS=2
+CONFIG_EXPERIMENTAL=y
+CONFIG_SYSVIPC=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_BSD_PROCESS_ACCT=y
+CONFIG_BSD_PROCESS_ACCT_V3=y
+CONFIG_SPARSE_IRQ=y
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+# CONFIG_UTS_NS is not set
+# CONFIG_IPC_NS is not set
+# CONFIG_USER_NS is not set
+# CONFIG_PID_NS is not set
+# CONFIG_NET_NS is not set
+CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
+CONFIG_RELAY=y
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_PERF_EVENTS=y
+CONFIG_SLAB=y
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_BLK_DEV_BSG is not set
+CONFIG_GE_IMP3A=y
+CONFIG_QUICC_ENGINE=y
+CONFIG_QE_GPIO=y
+CONFIG_CPM2=y
+CONFIG_HIGHMEM=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_HZ_1000=y
+CONFIG_PREEMPT=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_BINFMT_MISC=m
+CONFIG_MATH_EMULATION=y
+CONFIG_IRQ_ALL_CPUS=y
+CONFIG_FORCE_MAX_ZONEORDER=17
+CONFIG_PCI=y
+CONFIG_PCIEPORTBUS=y
+CONFIG_PCI_MSI=y
+CONFIG_PCCARD=y
+# CONFIG_PCMCIA_LOAD_CIS is not set
+CONFIG_YENTA=y
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_XFRM_USER=m
+CONFIG_NET_KEY=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_ADVANCED_ROUTER=y
+CONFIG_IP_MULTIPLE_TABLES=y
+CONFIG_IP_ROUTE_MULTIPATH=y
+CONFIG_IP_ROUTE_VERBOSE=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+CONFIG_IP_PNP_RARP=y
+CONFIG_NET_IPIP=m
+CONFIG_IP_MROUTE=y
+CONFIG_IP_PIMSM_V1=y
+CONFIG_IP_PIMSM_V2=y
+CONFIG_SYN_COOKIES=y
+CONFIG_INET_AH=m
+CONFIG_INET_ESP=m
+CONFIG_INET_IPCOMP=m
+# CONFIG_INET_XFRM_MODE_BEET is not set
+CONFIG_INET6_AH=m
+CONFIG_INET6_IPCOMP=m
+CONFIG_IPV6_TUNNEL=m
+CONFIG_NET_PKTGEN=m
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_MTD=y
+CONFIG_MTD_OF_PARTS=y
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLOCK=y
+CONFIG_MTD_CFI=y
+CONFIG_MTD_JEDECPROBE=y
+CONFIG_MTD_CFI_INTELEXT=y
+CONFIG_MTD_CFI_AMDSTD=y
+CONFIG_MTD_PHYSMAP_OF=y
+CONFIG_MTD_NAND=y
+CONFIG_MTD_NAND_FSL_ELBC=y
+CONFIG_PROC_DEVICETREE=y
+CONFIG_BLK_DEV_LOOP=m
+CONFIG_BLK_DEV_CRYPTOLOOP=m
+CONFIG_BLK_DEV_NBD=m
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_SIZE=131072
+CONFIG_MISC_DEVICES=y
+CONFIG_DS1682=y
+CONFIG_BLK_DEV_SD=y
+CONFIG_CHR_DEV_ST=y
+CONFIG_BLK_DEV_SR=y
+CONFIG_ATA=y
+CONFIG_SATA_AHCI=y
+CONFIG_SATA_SIL24=y
+# CONFIG_ATA_SFF is not set
+CONFIG_NETDEVICES=y
+CONFIG_BONDING=m
+CONFIG_DUMMY=m
+CONFIG_NETCONSOLE=y
+CONFIG_NETPOLL_TRAP=y
+CONFIG_TUN=m
+# CONFIG_NET_VENDOR_3COM is not set
+CONFIG_FS_ENET=y
+CONFIG_UCC_GETH=y
+CONFIG_GIANFAR=y
+CONFIG_PPP=m
+CONFIG_PPP_BSDCOMP=m
+CONFIG_PPP_DEFLATE=m
+CONFIG_PPP_FILTER=y
+CONFIG_PPP_MULTILINK=y
+CONFIG_PPPOE=m
+CONFIG_PPP_ASYNC=m
+CONFIG_PPP_SYNC_TTY=m
+CONFIG_SLIP=m
+CONFIG_SLIP_COMPRESSED=y
+CONFIG_SLIP_SMART=y
+CONFIG_SLIP_MODE_SLIP6=y
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_SERIO is not set
+# CONFIG_LEGACY_PTYS is not set
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_NR_UARTS=2
+CONFIG_SERIAL_8250_RUNTIME_UARTS=2
+CONFIG_SERIAL_8250_EXTENDED=y
+CONFIG_SERIAL_8250_MANY_PORTS=y
+CONFIG_SERIAL_8250_DETECT_IRQ=y
+CONFIG_SERIAL_8250_RSA=y
+CONFIG_SERIAL_QE=m
+CONFIG_NVRAM=y
+CONFIG_I2C=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_CPM=m
+CONFIG_I2C_MPC=y
+CONFIG_GPIO_SYSFS=y
+CONFIG_GPIO_GE_FPGA=y
+CONFIG_SENSORS_LM90=y
+CONFIG_SENSORS_LM92=y
+CONFIG_WATCHDOG=y
+CONFIG_GEF_WDT=y
+CONFIG_VIDEO_OUTPUT_CONTROL=m
+CONFIG_HID_DRAGONRISE=y
+CONFIG_HID_GYRATION=y
+CONFIG_HID_TWINHAN=y
+CONFIG_HID_ORTEK=y
+CONFIG_HID_PANTHERLORD=y
+CONFIG_HID_PETALYNX=y
+CONFIG_HID_SAMSUNG=y
+CONFIG_HID_SONY=y
+CONFIG_HID_SUNPLUS=y
+CONFIG_HID_GREENASIA=y
+CONFIG_HID_SMARTJOYPLUS=y
+CONFIG_HID_TOPSEED=y
+CONFIG_HID_THRUSTMASTER=y
+CONFIG_HID_ZEROPLUS=y
+CONFIG_USB=y
+CONFIG_USB_DEVICEFS=y
+CONFIG_USB_EHCI_HCD=y
+# CONFIG_USB_EHCI_TT_NEWSCHED is not set
+CONFIG_USB_EHCI_FSL=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_HCD_PPC_OF_BE=y
+CONFIG_USB_OHCI_HCD_PPC_OF_LE=y
+CONFIG_USB_STORAGE=y
+CONFIG_EDAC=y
+CONFIG_EDAC_MM_EDAC=y
+CONFIG_EDAC_MPC85XX=y
+CONFIG_RTC_CLASS=y
+# CONFIG_RTC_INTF_PROC is not set
+CONFIG_RTC_DRV_RX8581=y
+CONFIG_DMADEVICES=y
+CONFIG_FSL_DMA=y
+# CONFIG_NET_DMA is not set
+CONFIG_EXT2_FS=y
+CONFIG_EXT2_FS_XATTR=y
+CONFIG_EXT2_FS_POSIX_ACL=y
+CONFIG_EXT3_FS=y
+# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
+CONFIG_EXT3_FS_POSIX_ACL=y
+CONFIG_EXT4_FS=y
+CONFIG_FUSE_FS=y
+CONFIG_ISO9660_FS=y
+CONFIG_JOLIET=y
+CONFIG_ZISOFS=y
+CONFIG_UDF_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_FAT_DEFAULT_CODEPAGE=850
+CONFIG_FAT_DEFAULT_IOCHARSET="ascii"
+CONFIG_NTFS_FS=y
+CONFIG_PROC_KCORE=y
+CONFIG_TMPFS=y
+CONFIG_JFFS2_FS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+CONFIG_NFS_V4=y
+CONFIG_ROOT_NFS=y
+CONFIG_NFSD=y
+CONFIG_NFSD_V4=y
+CONFIG_CIFS=m
+CONFIG_CIFS_XATTR=y
+CONFIG_CIFS_POSIX=y
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_CODEPAGE_737=m
+CONFIG_NLS_CODEPAGE_775=m
+CONFIG_NLS_CODEPAGE_850=y
+CONFIG_NLS_CODEPAGE_852=m
+CONFIG_NLS_CODEPAGE_855=m
+CONFIG_NLS_CODEPAGE_857=m
+CONFIG_NLS_CODEPAGE_860=m
+CONFIG_NLS_CODEPAGE_861=m
+CONFIG_NLS_CODEPAGE_862=m
+CONFIG_NLS_CODEPAGE_863=m
+CONFIG_NLS_CODEPAGE_864=m
+CONFIG_NLS_CODEPAGE_865=m
+CONFIG_NLS_CODEPAGE_866=m
+CONFIG_NLS_CODEPAGE_869=m
+CONFIG_NLS_CODEPAGE_936=m
+CONFIG_NLS_CODEPAGE_950=m
+CONFIG_NLS_CODEPAGE_932=m
+CONFIG_NLS_CODEPAGE_949=m
+CONFIG_NLS_CODEPAGE_874=m
+CONFIG_NLS_ISO8859_8=m
+CONFIG_NLS_CODEPAGE_1250=m
+CONFIG_NLS_CODEPAGE_1251=m
+CONFIG_NLS_ASCII=y
+CONFIG_NLS_ISO8859_1=y
+CONFIG_NLS_ISO8859_2=m
+CONFIG_NLS_ISO8859_3=m
+CONFIG_NLS_ISO8859_4=m
+CONFIG_NLS_ISO8859_5=m
+CONFIG_NLS_ISO8859_6=m
+CONFIG_NLS_ISO8859_7=m
+CONFIG_NLS_ISO8859_9=m
+CONFIG_NLS_ISO8859_13=m
+CONFIG_NLS_ISO8859_14=m
+CONFIG_NLS_ISO8859_15=y
+CONFIG_NLS_KOI8_R=m
+CONFIG_NLS_KOI8_U=m
+CONFIG_NLS_UTF8=y
+CONFIG_CRC_CCITT=y
+CONFIG_CRC_T10DIF=y
+CONFIG_LIBCRC32C=y
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_SYSCTL_SYSCALL_CHECK=y
+CONFIG_CRYPTO_CBC=y
+CONFIG_CRYPTO_MD5=y
+CONFIG_CRYPTO_SHA256=m
+CONFIG_CRYPTO_SHA512=m
+CONFIG_CRYPTO_DES=y
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
+CONFIG_CRYPTO_DEV_TALITOS=y
diff --git a/arch/powerpc/configs/86xx/gef_ppc9a_defconfig b/arch/powerpc/configs/86xx/gef_ppc9a_defconfig
index d41857a5152..da731c2fe98 100644
--- a/arch/powerpc/configs/86xx/gef_ppc9a_defconfig
+++ b/arch/powerpc/configs/86xx/gef_ppc9a_defconfig
@@ -131,6 +131,7 @@ CONFIG_I2C=y
 CONFIG_I2C_CHARDEV=y
 CONFIG_I2C_MPC=y
 CONFIG_GPIO_SYSFS=y
+CONFIG_GPIO_GE_FPGA=y
 CONFIG_SENSORS_LM90=y
 CONFIG_SENSORS_LM92=y
 CONFIG_WATCHDOG=y
diff --git a/arch/powerpc/configs/86xx/gef_sbc310_defconfig b/arch/powerpc/configs/86xx/gef_sbc310_defconfig
index 38303ec11bc..2149360a1e6 100644
--- a/arch/powerpc/configs/86xx/gef_sbc310_defconfig
+++ b/arch/powerpc/configs/86xx/gef_sbc310_defconfig
@@ -132,6 +132,7 @@ CONFIG_I2C=y
 CONFIG_I2C_CHARDEV=y
 CONFIG_I2C_MPC=y
 CONFIG_GPIO_SYSFS=y
+CONFIG_GPIO_GE_FPGA=y
 CONFIG_SENSORS_LM90=y
 CONFIG_SENSORS_LM92=y
 CONFIG_WATCHDOG=y
diff --git a/arch/powerpc/configs/86xx/gef_sbc610_defconfig b/arch/powerpc/configs/86xx/gef_sbc610_defconfig
index 98533973d20..af2e8e1edba 100644
--- a/arch/powerpc/configs/86xx/gef_sbc610_defconfig
+++ b/arch/powerpc/configs/86xx/gef_sbc610_defconfig
@@ -183,6 +183,8 @@ CONFIG_NVRAM=y
 CONFIG_I2C=y
 CONFIG_I2C_CHARDEV=y
 CONFIG_I2C_MPC=y
+CONFIG_GPIO_SYSFS=y
+CONFIG_GPIO_GE_FPGA=y
 CONFIG_SENSORS_LM90=y
 CONFIG_SENSORS_LM92=y
 CONFIG_WATCHDOG=y
diff --git a/arch/powerpc/configs/iseries_defconfig b/arch/powerpc/configs/iseries_defconfig
deleted file mode 100644
index 27c46d67996..00000000000
--- a/arch/powerpc/configs/iseries_defconfig
+++ /dev/null
@@ -1,236 +0,0 @@
-CONFIG_PPC64=y
-CONFIG_SMP=y
-CONFIG_EXPERIMENTAL=y
-CONFIG_SYSVIPC=y
-CONFIG_POSIX_MQUEUE=y
-CONFIG_AUDIT=y
-CONFIG_AUDITSYSCALL=y
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_BLK_DEV_INITRD=y
-# CONFIG_COMPAT_BRK is not set
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-CONFIG_MODVERSIONS=y
-CONFIG_MODULE_SRCVERSION_ALL=y
-# CONFIG_PPC_PSERIES is not set
-CONFIG_LPARCFG=y
-CONFIG_PPC_ISERIES=y
-CONFIG_VIODASD=y
-CONFIG_VIOCD=m
-CONFIG_VIOTAPE=m
-# CONFIG_PPC_PMAC is not set
-CONFIG_NO_HZ=y
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_IRQ_ALL_CPUS=y
-# CONFIG_MIGRATION is not set
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_XFRM_USER=m
-CONFIG_XFRM_SUB_POLICY=y
-CONFIG_NET_KEY=m
-CONFIG_INET=y
-CONFIG_IP_MULTICAST=y
-CONFIG_NET_IPIP=y
-CONFIG_SYN_COOKIES=y
-CONFIG_INET_AH=m
-CONFIG_INET_ESP=m
-CONFIG_INET_IPCOMP=m
-CONFIG_INET_XFRM_MODE_BEET=m
-# CONFIG_INET_LRO is not set
-# CONFIG_IPV6 is not set
-CONFIG_NETFILTER=y
-CONFIG_NETFILTER_NETLINK_QUEUE=m
-CONFIG_NETFILTER_NETLINK_LOG=m
-CONFIG_NF_CONNTRACK=m
-CONFIG_NF_CONNTRACK_EVENTS=y
-# CONFIG_NF_CT_PROTO_SCTP is not set
-CONFIG_NF_CONNTRACK_FTP=m
-CONFIG_NF_CONNTRACK_IRC=m
-CONFIG_NF_CONNTRACK_TFTP=m
-CONFIG_NF_CT_NETLINK=m
-CONFIG_NETFILTER_TPROXY=m
-CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
-CONFIG_NETFILTER_XT_TARGET_CONNMARK=m
-CONFIG_NETFILTER_XT_TARGET_DSCP=m
-CONFIG_NETFILTER_XT_TARGET_MARK=m
-CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m
-CONFIG_NETFILTER_XT_TARGET_TPROXY=m
-CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m
-CONFIG_NETFILTER_XT_MATCH_COMMENT=m
-CONFIG_NETFILTER_XT_MATCH_CONNMARK=m
-CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
-CONFIG_NETFILTER_XT_MATCH_DSCP=m
-CONFIG_NETFILTER_XT_MATCH_IPRANGE=m
-CONFIG_NETFILTER_XT_MATCH_LENGTH=m
-CONFIG_NETFILTER_XT_MATCH_LIMIT=m
-CONFIG_NETFILTER_XT_MATCH_MAC=m
-CONFIG_NETFILTER_XT_MATCH_MARK=m
-CONFIG_NETFILTER_XT_MATCH_OWNER=m
-CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m
-CONFIG_NETFILTER_XT_MATCH_RATEEST=m
-CONFIG_NETFILTER_XT_MATCH_REALM=m
-CONFIG_NETFILTER_XT_MATCH_RECENT=m
-CONFIG_NETFILTER_XT_MATCH_STRING=m
-CONFIG_NETFILTER_XT_MATCH_TCPMSS=m
-CONFIG_NETFILTER_XT_MATCH_TIME=m
-CONFIG_NF_CONNTRACK_IPV4=m
-CONFIG_IP_NF_QUEUE=m
-CONFIG_IP_NF_IPTABLES=m
-CONFIG_IP_NF_MATCH_ADDRTYPE=m
-CONFIG_IP_NF_MATCH_ECN=m
-CONFIG_IP_NF_MATCH_TTL=m
-CONFIG_IP_NF_FILTER=m
-CONFIG_IP_NF_TARGET_REJECT=m
-CONFIG_IP_NF_TARGET_LOG=m
-CONFIG_IP_NF_TARGET_ULOG=m
-CONFIG_NF_NAT=m
-CONFIG_IP_NF_TARGET_MASQUERADE=m
-CONFIG_IP_NF_TARGET_NETMAP=m
-CONFIG_IP_NF_TARGET_REDIRECT=m
-CONFIG_IP_NF_MANGLE=m
-CONFIG_IP_NF_TARGET_CLUSTERIP=m
-CONFIG_IP_NF_TARGET_ECN=m
-CONFIG_IP_NF_TARGET_TTL=m
-CONFIG_IP_NF_RAW=m
-CONFIG_IP_NF_ARPTABLES=m
-CONFIG_IP_NF_ARPFILTER=m
-CONFIG_IP_NF_ARP_MANGLE=m
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-CONFIG_PROC_DEVICETREE=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_NBD=m
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_SIZE=65536
-CONFIG_SCSI=y
-CONFIG_BLK_DEV_SD=y
-CONFIG_CHR_DEV_ST=y
-CONFIG_BLK_DEV_SR=y
-CONFIG_BLK_DEV_SR_VENDOR=y
-CONFIG_CHR_DEV_SG=y
-CONFIG_SCSI_MULTI_LUN=y
-CONFIG_SCSI_CONSTANTS=y
-CONFIG_SCSI_SPI_ATTRS=y
-CONFIG_SCSI_FC_ATTRS=y
-CONFIG_SCSI_SAS_LIBSAS=m
-CONFIG_SCSI_IBMVSCSI=m
-CONFIG_MD=y
-CONFIG_BLK_DEV_MD=y
-CONFIG_MD_LINEAR=y
-CONFIG_MD_RAID0=y
-CONFIG_MD_RAID1=y
-CONFIG_MD_RAID10=m
-CONFIG_MD_MULTIPATH=m
-CONFIG_MD_FAULTY=m
-CONFIG_BLK_DEV_DM=y
-CONFIG_DM_CRYPT=m
-CONFIG_DM_SNAPSHOT=m
-CONFIG_DM_MIRROR=m
-CONFIG_DM_ZERO=m
-CONFIG_NETDEVICES=y
-CONFIG_DUMMY=m
-CONFIG_BONDING=m
-CONFIG_TUN=m
-CONFIG_NET_ETHERNET=y
-CONFIG_NET_PCI=y
-CONFIG_PCNET32=y
-CONFIG_E100=y
-CONFIG_ACENIC=m
-CONFIG_E1000=m
-CONFIG_ISERIES_VETH=y
-CONFIG_PPP=m
-CONFIG_PPP_ASYNC=m
-CONFIG_PPP_SYNC_TTY=m
-CONFIG_PPP_DEFLATE=m
-CONFIG_PPP_BSDCOMP=m
-CONFIG_PPPOE=m
-CONFIG_NETCONSOLE=y
-CONFIG_NETPOLL_TRAP=y
-# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-# CONFIG_SERIO is not set
-CONFIG_SERIAL_ICOM=m
-# CONFIG_HW_RANDOM is not set
-CONFIG_GEN_RTC=y
-CONFIG_RAW_DRIVER=y
-# CONFIG_HWMON is not set
-# CONFIG_HID_SUPPORT is not set
-# CONFIG_USB_SUPPORT is not set
-CONFIG_EXT2_FS=y
-CONFIG_EXT2_FS_XATTR=y
-CONFIG_EXT2_FS_POSIX_ACL=y
-CONFIG_EXT2_FS_SECURITY=y
-CONFIG_EXT2_FS_XIP=y
-CONFIG_EXT3_FS=y
-CONFIG_EXT3_FS_POSIX_ACL=y
-CONFIG_EXT3_FS_SECURITY=y
-CONFIG_EXT4_FS=y
-CONFIG_REISERFS_FS=y
-CONFIG_REISERFS_FS_XATTR=y
-CONFIG_REISERFS_FS_POSIX_ACL=y
-CONFIG_REISERFS_FS_SECURITY=y
-CONFIG_JFS_FS=m
-CONFIG_JFS_POSIX_ACL=y
-CONFIG_JFS_SECURITY=y
-CONFIG_XFS_FS=m
-CONFIG_XFS_POSIX_ACL=y
-CONFIG_GFS2_FS=m
-CONFIG_AUTOFS_FS=m
-CONFIG_ISO9660_FS=y
-CONFIG_JOLIET=y
-CONFIG_ZISOFS=y
-CONFIG_UDF_FS=m
-CONFIG_MSDOS_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_PROC_KCORE=y
-CONFIG_TMPFS=y
-CONFIG_TMPFS_POSIX_ACL=y
-CONFIG_CRAMFS=y
-CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
-CONFIG_NFS_V3_ACL=y
-CONFIG_NFS_V4=y
-CONFIG_NFSD=m
-CONFIG_NFSD_V3_ACL=y
-CONFIG_NFSD_V4=y
-CONFIG_RPCSEC_GSS_SPKM3=m
-CONFIG_CIFS=m
-CONFIG_CIFS_XATTR=y
-CONFIG_CIFS_POSIX=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_ASCII=y
-CONFIG_NLS_ISO8859_1=y
-CONFIG_DLM=m
-CONFIG_CRC_T10DIF=y
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_DEBUG_FS=y
-CONFIG_DEBUG_KERNEL=y
-# CONFIG_RCU_CPU_STALL_DETECTOR is not set
-CONFIG_LATENCYTOP=y
-CONFIG_SYSCTL_SYSCALL_CHECK=y
-CONFIG_DEBUG_STACKOVERFLOW=y
-CONFIG_DEBUG_STACK_USAGE=y
-CONFIG_CRYPTO_NULL=m
-CONFIG_CRYPTO_TEST=m
-CONFIG_CRYPTO_ECB=m
-CONFIG_CRYPTO_PCBC=m
-CONFIG_CRYPTO_HMAC=y
-CONFIG_CRYPTO_MD4=m
-CONFIG_CRYPTO_MICHAEL_MIC=m
-CONFIG_CRYPTO_SHA256=m
-CONFIG_CRYPTO_SHA512=m
-CONFIG_CRYPTO_TGR192=m
-CONFIG_CRYPTO_WP512=m
-CONFIG_CRYPTO_AES=m
-CONFIG_CRYPTO_ANUBIS=m
-CONFIG_CRYPTO_ARC4=m
-CONFIG_CRYPTO_BLOWFISH=m
-CONFIG_CRYPTO_CAST6=m
-CONFIG_CRYPTO_KHAZAD=m
-CONFIG_CRYPTO_SEED=m
-CONFIG_CRYPTO_SERPENT=m
-CONFIG_CRYPTO_TEA=m
-CONFIG_CRYPTO_TWOFISH=m
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
-# CONFIG_CRYPTO_HW is not set
diff --git a/arch/powerpc/configs/mpc5200_defconfig b/arch/powerpc/configs/mpc5200_defconfig
index 2a1320fb272..6640a35bebb 100644
--- a/arch/powerpc/configs/mpc5200_defconfig
+++ b/arch/powerpc/configs/mpc5200_defconfig
@@ -1,8 +1,8 @@
 CONFIG_EXPERIMENTAL=y
 CONFIG_SYSVIPC=y
+CONFIG_SPARSE_IRQ=y
 CONFIG_LOG_BUF_SHIFT=14
 CONFIG_BLK_DEV_INITRD=y
-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
 CONFIG_MODULES=y
 CONFIG_MODULE_UNLOAD=y
 # CONFIG_BLK_DEV_BSG is not set
@@ -13,15 +13,12 @@ CONFIG_PPC_EFIKA=y
 CONFIG_PPC_LITE5200=y
 CONFIG_PPC_MEDIA5200=y
 CONFIG_PPC_MPC5200_BUGFIX=y
-CONFIG_PPC_MPC5200_GPIO=y
 CONFIG_PPC_MPC5200_LPBFIFO=m
 # CONFIG_PPC_PMAC is not set
 CONFIG_PPC_BESTCOMM=y
 CONFIG_SIMPLE_GPIO=y
 CONFIG_NO_HZ=y
 CONFIG_HIGH_RES_TIMERS=y
-CONFIG_SPARSE_IRQ=y
-CONFIG_PM=y
 CONFIG_NET=y
 CONFIG_PACKET=y
 CONFIG_UNIX=y
@@ -36,23 +33,20 @@ CONFIG_SYN_COOKIES=y
 # CONFIG_IPV6 is not set
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 CONFIG_MTD=y
-CONFIG_MTD_CONCAT=y
-CONFIG_MTD_PARTITIONS=y
 CONFIG_MTD_CMDLINE_PARTS=y
 CONFIG_MTD_OF_PARTS=y
 CONFIG_MTD_CHAR=y
 CONFIG_MTD_BLOCK=y
 CONFIG_MTD_CFI=y
 CONFIG_MTD_CFI_AMDSTD=y
-CONFIG_MTD_RAM=y
 CONFIG_MTD_ROM=y
 CONFIG_MTD_PHYSMAP_OF=y
+CONFIG_MTD_PLATRAM=y
 CONFIG_MTD_UBI=m
 CONFIG_PROC_DEVICETREE=y
 CONFIG_BLK_DEV_LOOP=y
 CONFIG_BLK_DEV_RAM=y
 CONFIG_BLK_DEV_RAM_SIZE=32768
-CONFIG_MISC_DEVICES=y
 CONFIG_EEPROM_AT24=y
 CONFIG_SCSI_TGT=y
 CONFIG_BLK_DEV_SD=y
@@ -61,11 +55,10 @@ CONFIG_ATA=y
 CONFIG_PATA_MPC52xx=y
 CONFIG_PATA_PLATFORM=y
 CONFIG_NETDEVICES=y
-CONFIG_LXT_PHY=y
-CONFIG_NET_ETHERNET=y
 CONFIG_FEC_MPC52xx=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
+CONFIG_AMD_PHY=y
+CONFIG_LXT_PHY=y
+CONFIG_FIXED_PHY=y
 # CONFIG_INPUT_KEYBOARD is not set
 # CONFIG_INPUT_MOUSE is not set
 # CONFIG_SERIO is not set
@@ -80,11 +73,17 @@ CONFIG_SPI_GPIO=m
 CONFIG_SPI_MPC52xx=m
 CONFIG_SPI_MPC52xx_PSC=m
 CONFIG_SPI_SPIDEV=m
+CONFIG_GPIO_SYSFS=y
+CONFIG_SENSORS_LM80=y
+CONFIG_SENSORS_LM87=m
 CONFIG_WATCHDOG=y
+CONFIG_MFD_SM501=m
 CONFIG_DRM=y
 CONFIG_VIDEO_OUTPUT_CONTROL=y
 CONFIG_FB=y
+CONFIG_FB_FOREIGN_ENDIAN=y
 CONFIG_FB_RADEON=y
+CONFIG_FB_SM501=m
 # CONFIG_VGA_CONSOLE is not set
 CONFIG_FRAMEBUFFER_CONSOLE=y
 CONFIG_LOGO=y
@@ -124,10 +123,11 @@ CONFIG_USB_STORAGE=y
 CONFIG_NEW_LEDS=y
 CONFIG_RTC_CLASS=y
 CONFIG_RTC_DRV_DS1307=y
+CONFIG_RTC_DRV_DS1374=y
+CONFIG_RTC_DRV_PCF8563=m
 CONFIG_EXT2_FS=y
 CONFIG_EXT3_FS=y
 # CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
-CONFIG_INOTIFY=y
 CONFIG_MSDOS_FS=y
 CONFIG_VFAT_FS=y
 CONFIG_PROC_KCORE=y
@@ -145,5 +145,4 @@ CONFIG_PRINTK_TIME=y
 CONFIG_DEBUG_KERNEL=y
 CONFIG_DETECT_HUNG_TASK=y
 CONFIG_DEBUG_INFO=y
-# CONFIG_RCU_CPU_STALL_DETECTOR is not set
 # CONFIG_CRYPTO_ANSI_CPRNG is not set
diff --git a/arch/powerpc/configs/mpc85xx_defconfig b/arch/powerpc/configs/mpc85xx_defconfig
index f37a2ab4888..5fb0c8a9481 100644
--- a/arch/powerpc/configs/mpc85xx_defconfig
+++ b/arch/powerpc/configs/mpc85xx_defconfig
@@ -1,4 +1,5 @@
 CONFIG_PPC_85xx=y
+CONFIG_PHYS_64BIT=y
 CONFIG_EXPERIMENTAL=y
 CONFIG_SYSVIPC=y
 CONFIG_POSIX_MQUEUE=y
diff --git a/arch/powerpc/configs/mpc85xx_smp_defconfig b/arch/powerpc/configs/mpc85xx_smp_defconfig
index abdcd317cda..fb51bc90edd 100644
--- a/arch/powerpc/configs/mpc85xx_smp_defconfig
+++ b/arch/powerpc/configs/mpc85xx_smp_defconfig
@@ -1,4 +1,5 @@
 CONFIG_PPC_85xx=y
+CONFIG_PHYS_64BIT=y
 CONFIG_SMP=y
 CONFIG_NR_CPUS=8
 CONFIG_EXPERIMENTAL=y
diff --git a/arch/powerpc/include/asm/abs_addr.h b/arch/powerpc/include/asm/abs_addr.h
index 5ab0b71531b..9d92ba04b03 100644
--- a/arch/powerpc/include/asm/abs_addr.h
+++ b/arch/powerpc/include/asm/abs_addr.h
@@ -17,7 +17,6 @@
 #include <asm/types.h>
 #include <asm/page.h>
 #include <asm/prom.h>
-#include <asm/firmware.h>
 
 struct mschunks_map {
         unsigned long num_chunks;
@@ -46,30 +45,12 @@ static inline unsigned long addr_to_chunk(unsigned long addr)
 
 static inline unsigned long phys_to_abs(unsigned long pa)
 {
-        unsigned long chunk;
-
-        /* This is a no-op on non-iSeries */
-        if (!firmware_has_feature(FW_FEATURE_ISERIES))
-                return pa;
-
-        chunk = addr_to_chunk(pa);
-
-        if (chunk < mschunks_map.num_chunks)
-                chunk = mschunks_map.mapping[chunk];
-
-        return chunk_to_addr(chunk) + (pa & MSCHUNKS_OFFSET_MASK);
+        return pa;
 }
 
 /* Convenience macros */
 #define virt_to_abs(va) phys_to_abs(__pa(va))
 #define abs_to_virt(aa) __va(aa)
 
-/*
- * Converts Virtual Address to Real Address for
- * Legacy iSeries Hypervisor calls
- */
-#define iseries_hv_addr(virtaddr)       \
-        (0x8000000000000000UL | virt_to_abs(virtaddr))
-
 #endif /* __KERNEL__ */
 #endif /* _ASM_POWERPC_ABS_ADDR_H */
diff --git a/arch/powerpc/include/asm/atomic.h b/arch/powerpc/include/asm/atomic.h
index 02e41b53488..14174e838ad 100644
--- a/arch/powerpc/include/asm/atomic.h
+++ b/arch/powerpc/include/asm/atomic.h
@@ -212,6 +212,36 @@ static __inline__ int __atomic_add_unless(atomic_t *v, int a, int u)
         return t;
 }
 
+/**
+ * atomic_inc_not_zero - increment unless the number is zero
+ * @v: pointer of type atomic_t
+ *
+ * Atomically increments @v by 1, so long as @v is non-zero.
+ * Returns non-zero if @v was non-zero, and zero otherwise.
+ */
+static __inline__ int atomic_inc_not_zero(atomic_t *v)
+{
+        int t1, t2;
+
+        __asm__ __volatile__ (
+        PPC_ATOMIC_ENTRY_BARRIER
+"1:     lwarx   %0,0,%2         # atomic_inc_not_zero\n\
+        cmpwi   0,%0,0\n\
+        beq-    2f\n\
+        addic   %1,%0,1\n"
+        PPC405_ERR77(0,%2)
+"       stwcx.  %1,0,%2\n\
+        bne-    1b\n"
+        PPC_ATOMIC_EXIT_BARRIER
+        "\n\
+2:"
+        : "=&r" (t1), "=&r" (t2)
+        : "r" (&v->counter)
+        : "cc", "xer", "memory");
+
+        return t1;
+}
+#define atomic_inc_not_zero(v) atomic_inc_not_zero((v))
 
 #define atomic_sub_and_test(a, v)       (atomic_sub_return((a), (v)) == 0)
 #define atomic_dec_and_test(v)          (atomic_dec_return((v)) == 0)
@@ -467,7 +497,34 @@ static __inline__ int atomic64_add_unless(atomic64_t *v, long a, long u)
         return t != u;
 }
 
-#define atomic64_inc_not_zero(v) atomic64_add_unless((v), 1, 0)
+/**
+ * atomic_inc64_not_zero - increment unless the number is zero
+ * @v: pointer of type atomic64_t
+ *
+ * Atomically increments @v by 1, so long as @v is non-zero.
+ * Returns non-zero if @v was non-zero, and zero otherwise.
+ */
+static __inline__ long atomic64_inc_not_zero(atomic64_t *v)
+{
+        long t1, t2;
+
+        __asm__ __volatile__ (
+        PPC_ATOMIC_ENTRY_BARRIER
+"1:     ldarx   %0,0,%2         # atomic64_inc_not_zero\n\
+        cmpdi   0,%0,0\n\
+        beq-    2f\n\
+        addic   %1,%0,1\n\
+        stdcx.  %1,0,%2\n\
+        bne-    1b\n"
+        PPC_ATOMIC_EXIT_BARRIER
+        "\n\
+2:"
+        : "=&r" (t1), "=&r" (t2)
+        : "r" (&v->counter)
+        : "cc", "xer", "memory");
+
+        return t1;
+}
 
 #endif /* __powerpc64__ */
 
diff --git a/arch/powerpc/include/asm/cputable.h b/arch/powerpc/include/asm/cputable.h
index ad55a1ccb9f..b9219e99bd2 100644
--- a/arch/powerpc/include/asm/cputable.h
+++ b/arch/powerpc/include/asm/cputable.h
@@ -390,6 +390,10 @@ extern const char *powerpc_base_platform;
             CPU_FTR_L2CSR | CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \
             CPU_FTR_DBELL | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
             CPU_FTR_DEBUG_LVL_EXC)
+#define CPU_FTRS_E6500  (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | \
+            CPU_FTR_L2CSR | CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \
+            CPU_FTR_DBELL | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
+            CPU_FTR_DEBUG_LVL_EXC)
 #define CPU_FTRS_GENERIC_32     (CPU_FTR_COMMON | CPU_FTR_NODSISRALIGN)
 
 /* 64-bit CPUs */
@@ -442,7 +446,7 @@ extern const char *powerpc_base_platform;
 
 #ifdef __powerpc64__
 #ifdef CONFIG_PPC_BOOK3E
-#define CPU_FTRS_POSSIBLE       (CPU_FTRS_E5500 | CPU_FTRS_A2)
+#define CPU_FTRS_POSSIBLE       (CPU_FTRS_E6500 | CPU_FTRS_E5500 | CPU_FTRS_A2)
 #else
 #define CPU_FTRS_POSSIBLE       \
             (CPU_FTRS_POWER3 | CPU_FTRS_RS64 | CPU_FTRS_POWER4 |        \
@@ -483,7 +487,7 @@ enum {
 #endif
 #ifdef CONFIG_E500
             CPU_FTRS_E500 | CPU_FTRS_E500_2 | CPU_FTRS_E500MC |
-            CPU_FTRS_E5500 |
+            CPU_FTRS_E5500 | CPU_FTRS_E6500 |
 #endif
             0,
 };
@@ -491,7 +495,7 @@ enum {
 
 #ifdef __powerpc64__
 #ifdef CONFIG_PPC_BOOK3E
-#define CPU_FTRS_ALWAYS         (CPU_FTRS_E5500 & CPU_FTRS_A2)
+#define CPU_FTRS_ALWAYS         (CPU_FTRS_E6500 & CPU_FTRS_E5500 & CPU_FTRS_A2)
 #else
 #define CPU_FTRS_ALWAYS         \
             (CPU_FTRS_POWER3 & CPU_FTRS_RS64 & CPU_FTRS_POWER4 &        \
@@ -528,7 +532,7 @@ enum {
 #endif
 #ifdef CONFIG_E500
             CPU_FTRS_E500 & CPU_FTRS_E500_2 & CPU_FTRS_E500MC &
-            CPU_FTRS_E5500 &
+            CPU_FTRS_E5500 & CPU_FTRS_E6500 &
 #endif
             CPU_FTRS_POSSIBLE,
 };
diff --git a/arch/powerpc/include/asm/device.h b/arch/powerpc/include/asm/device.h
index d57c08acedf..63d5ca49cec 100644
--- a/arch/powerpc/include/asm/device.h
+++ b/arch/powerpc/include/asm/device.h
@@ -31,6 +31,9 @@ struct dev_archdata {
 #ifdef CONFIG_SWIOTLB
         dma_addr_t              max_direct_dma_addr;
 #endif
+#ifdef CONFIG_EEH
+        struct eeh_dev          *edev;
+#endif
 };
 
 struct pdev_archdata {
diff --git a/arch/powerpc/include/asm/dma.h b/arch/powerpc/include/asm/dma.h
index a7e06e25c70..adadb994361 100644
--- a/arch/powerpc/include/asm/dma.h
+++ b/arch/powerpc/include/asm/dma.h
@@ -34,8 +34,6 @@
 /* Doesn't really apply... */
 #define MAX_DMA_ADDRESS         (~0UL)
 
-#if !defined(CONFIG_PPC_ISERIES) || defined(CONFIG_PCI)
-
 #ifdef HAVE_REALLY_SLOW_DMA_CONTROLLER
 #define dma_outb        outb_p
 #else
@@ -354,7 +352,5 @@ extern int isa_dma_bridge_buggy;
 #define isa_dma_bridge_buggy    (0)
 #endif
 
-#endif  /* !defined(CONFIG_PPC_ISERIES) || defined(CONFIG_PCI) */
-
 #endif /* __KERNEL__ */
 #endif  /* _ASM_POWERPC_DMA_H */
diff --git a/arch/powerpc/include/asm/eeh.h b/arch/powerpc/include/asm/eeh.h
index 66ea9b8b95c..d60f99814ff 100644
--- a/arch/powerpc/include/asm/eeh.h
+++ b/arch/powerpc/include/asm/eeh.h
@@ -1,6 +1,6 @@
 /*
- * eeh.h
  * Copyright (C) 2001  Dave Engebretsen & Todd Inglett IBM Corporation.
+ * Copyright 2001-2012 IBM Corporation.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -31,44 +31,105 @@ struct device_node;
 
 #ifdef CONFIG_EEH
 
-extern int eeh_subsystem_enabled;
+/*
+ * The struct is used to trace EEH state for the associated
+ * PCI device node or PCI device. In future, it might
+ * represent PE as well so that the EEH device to form
+ * another tree except the currently existing tree of PCI
+ * buses and PCI devices
+ */
+#define EEH_MODE_SUPPORTED      (1<<0)  /* EEH supported on the device  */
+#define EEH_MODE_NOCHECK        (1<<1)  /* EEH check should be skipped  */
+#define EEH_MODE_ISOLATED       (1<<2)  /* The device has been isolated */
+#define EEH_MODE_RECOVERING     (1<<3)  /* Recovering the device        */
+#define EEH_MODE_IRQ_DISABLED   (1<<4)  /* Interrupt disabled           */
+
+struct eeh_dev {
+        int mode;                       /* EEH mode                     */
+        int class_code;                 /* Class code of the device     */
+        int config_addr;                /* Config address               */
+        int pe_config_addr;             /* PE config address            */
+        int check_count;                /* Times of ignored error       */
+        int freeze_count;               /* Times of froze up            */
+        int false_positives;            /* Times of reported #ff's      */
+        u32 config_space[16];           /* Saved PCI config space       */
+        struct pci_controller *phb;     /* Associated PHB               */
+        struct device_node *dn;         /* Associated device node       */
+        struct pci_dev *pdev;           /* Associated PCI device        */
+};
+
+static inline struct device_node *eeh_dev_to_of_node(struct eeh_dev *edev)
+{
+        return edev->dn;
+}
+
+static inline struct pci_dev *eeh_dev_to_pci_dev(struct eeh_dev *edev)
+{
+        return edev->pdev;
+}
 
-/* Values for eeh_mode bits in device_node */
-#define EEH_MODE_SUPPORTED     (1<<0)
-#define EEH_MODE_NOCHECK       (1<<1)
-#define EEH_MODE_ISOLATED      (1<<2)
-#define EEH_MODE_RECOVERING    (1<<3)
-#define EEH_MODE_IRQ_DISABLED  (1<<4)
+/*
+ * The struct is used to trace the registered EEH operation
+ * callback functions. Actually, those operation callback
+ * functions are heavily platform dependent. That means the
+ * platform should register its own EEH operation callback
+ * functions before any EEH further operations.
+ */
+#define EEH_OPT_DISABLE         0       /* EEH disable  */
+#define EEH_OPT_ENABLE          1       /* EEH enable   */
+#define EEH_OPT_THAW_MMIO       2       /* MMIO enable  */
+#define EEH_OPT_THAW_DMA        3       /* DMA enable   */
+#define EEH_STATE_UNAVAILABLE   (1 << 0)        /* State unavailable    */
+#define EEH_STATE_NOT_SUPPORT   (1 << 1)        /* EEH not supported    */
+#define EEH_STATE_RESET_ACTIVE  (1 << 2)        /* Active reset         */
+#define EEH_STATE_MMIO_ACTIVE   (1 << 3)        /* Active MMIO          */
+#define EEH_STATE_DMA_ACTIVE    (1 << 4)        /* Active DMA           */
+#define EEH_STATE_MMIO_ENABLED  (1 << 5)        /* MMIO enabled         */
+#define EEH_STATE_DMA_ENABLED   (1 << 6)        /* DMA enabled          */
+#define EEH_RESET_DEACTIVATE    0       /* Deactivate the PE reset      */
+#define EEH_RESET_HOT           1       /* Hot reset                    */
+#define EEH_RESET_FUNDAMENTAL   3       /* Fundamental reset            */
+#define EEH_LOG_TEMP            1       /* EEH temporary error log      */
+#define EEH_LOG_PERM            2       /* EEH permanent error log      */
+
+struct eeh_ops {
+        char *name;
+        int (*init)(void);
+        int (*set_option)(struct device_node *dn, int option);
+        int (*get_pe_addr)(struct device_node *dn);
+        int (*get_state)(struct device_node *dn, int *state);
+        int (*reset)(struct device_node *dn, int option);
+        int (*wait_state)(struct device_node *dn, int max_wait);
+        int (*get_log)(struct device_node *dn, int severity, char *drv_log, unsigned long len);
+        int (*configure_bridge)(struct device_node *dn);
+        int (*read_config)(struct device_node *dn, int where, int size, u32 *val);
+        int (*write_config)(struct device_node *dn, int where, int size, u32 val);
+};
+
+extern struct eeh_ops *eeh_ops;
+extern int eeh_subsystem_enabled;
 
-/* Max number of EEH freezes allowed before we consider the device
- * to be permanently disabled. */
+/*
+ * Max number of EEH freezes allowed before we consider the device
+ * to be permanently disabled.
+ */
 #define EEH_MAX_ALLOWED_FREEZES 5
 
+void * __devinit eeh_dev_init(struct device_node *dn, void *data);
+void __devinit eeh_dev_phb_init_dynamic(struct pci_controller *phb);
+void __init eeh_dev_phb_init(void);
 void __init eeh_init(void);
+#ifdef CONFIG_PPC_PSERIES
+int __init eeh_pseries_init(void);
+#endif
+int __init eeh_ops_register(struct eeh_ops *ops);
+int __exit eeh_ops_unregister(const char *name);
 unsigned long eeh_check_failure(const volatile void __iomem *token,
                                 unsigned long val);
 int eeh_dn_check_failure(struct device_node *dn, struct pci_dev *dev);
 void __init pci_addr_cache_build(void);
-
-/**
- * eeh_add_device_early
- * eeh_add_device_late
- *
- * Perform eeh initialization for devices added after boot.
- * Call eeh_add_device_early before doing any i/o to the
- * device (including config space i/o).  Call eeh_add_device_late
- * to finish the eeh setup for this device.
- */
 void eeh_add_device_tree_early(struct device_node *);
 void eeh_add_device_tree_late(struct pci_bus *);
-
-/**
- * eeh_remove_device_recursive - undo EEH for device & children.
- * @dev: pci device to be removed
- *
- * As above, this removes the device; it also removes child
- * pci devices as well.
- */
 void eeh_remove_bus_device(struct pci_dev *);
 
 /**
@@ -87,8 +148,25 @@ void eeh_remove_bus_device(struct pci_dev *);
 #define EEH_IO_ERROR_VALUE(size)        (~0U >> ((4 - (size)) * 8))
 
 #else /* !CONFIG_EEH */
+
+static inline void *eeh_dev_init(struct device_node *dn, void *data)
+{
+        return NULL;
+}
+
+static inline void eeh_dev_phb_init_dynamic(struct pci_controller *phb) { }
+
+static inline void eeh_dev_phb_init(void) { }
+
 static inline void eeh_init(void) { }
 
+#ifdef CONFIG_PPC_PSERIES
+static inline int eeh_pseries_init(void)
+{
+        return 0;
+}
+#endif /* CONFIG_PPC_PSERIES */
+
 static inline unsigned long eeh_check_failure(const volatile void __iomem *token, unsigned long val)
 {
         return val;
diff --git a/arch/powerpc/include/asm/eeh_event.h b/arch/powerpc/include/asm/eeh_event.h
index cc3cb04539a..c68b012b779 100644
--- a/arch/powerpc/include/asm/eeh_event.h
+++ b/arch/powerpc/include/asm/eeh_event.h
@@ -1,6 +1,4 @@
 /*
- *      eeh_event.h
- *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
  * the Free Software Foundation; either version 2 of the License, or
@@ -22,32 +20,19 @@
 #define ASM_POWERPC_EEH_EVENT_H
 #ifdef __KERNEL__
 
-/** EEH event -- structure holding pci controller data that describes
- *  a change in the isolation status of a PCI slot.  A pointer
- *  to this struct is passed as the data pointer in a notify callback.
+/*
+ * structure holding pci controller data that describes a
+ * change in the isolation status of a PCI slot.  A pointer
+ * to this struct is passed as the data pointer in a notify
+ * callback.
  */
 struct eeh_event {
-        struct list_head     list;
-        struct device_node      *dn;   /* struct device node */
-        struct pci_dev       *dev;  /* affected device */
+        struct list_head        list;   /* to form event queue  */
+        struct eeh_dev          *edev;  /* EEH device           */
 };
 
-/**
- * eeh_send_failure_event - generate a PCI error event
- * @dev pci device
- *
- * This routine builds a PCI error event which will be delivered
- * to all listeners on the eeh_notifier_chain.
- *
- * This routine can be called within an interrupt context;
- * the actual event will be delivered in a normal context
- * (from a workqueue).
- */
-int eeh_send_failure_event (struct device_node *dn,
-                            struct pci_dev *dev);
-
-/* Main recovery function */
-struct pci_dn * handle_eeh_events (struct eeh_event *);
+int eeh_send_failure_event(struct eeh_dev *edev);
+struct eeh_dev *handle_eeh_events(struct eeh_event *);
 
 #endif /* __KERNEL__ */
 #endif /* ASM_POWERPC_EEH_EVENT_H */
diff --git a/arch/powerpc/include/asm/exception-64s.h b/arch/powerpc/include/asm/exception-64s.h
index 8057f4f6980..548da3aa0a3 100644
--- a/arch/powerpc/include/asm/exception-64s.h
+++ b/arch/powerpc/include/asm/exception-64s.h
@@ -232,23 +232,30 @@ label##_hv:						\
         EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, label##_common,    \
                                  EXC_HV, KVMTEST, vec)
 
-#define __SOFTEN_TEST(h)                                                \
+/* This associate vector numbers with bits in paca->irq_happened */
+#define SOFTEN_VALUE_0x500      PACA_IRQ_EE
+#define SOFTEN_VALUE_0x502      PACA_IRQ_EE
+#define SOFTEN_VALUE_0x900      PACA_IRQ_DEC
+#define SOFTEN_VALUE_0x982      PACA_IRQ_DEC
+
+#define __SOFTEN_TEST(h, vec)                                           \
         lbz     r10,PACASOFTIRQEN(r13);                                 \
         cmpwi   r10,0;                                                  \
+        li      r10,SOFTEN_VALUE_##vec;                                 \
         beq     masked_##h##interrupt
-#define _SOFTEN_TEST(h) __SOFTEN_TEST(h)
+#define _SOFTEN_TEST(h, vec)    __SOFTEN_TEST(h, vec)
 
 #define SOFTEN_TEST_PR(vec)                                             \
         KVMTEST_PR(vec);                                                \
-        _SOFTEN_TEST(EXC_STD)
+        _SOFTEN_TEST(EXC_STD, vec)
 
 #define SOFTEN_TEST_HV(vec)                                             \
         KVMTEST(vec);                                                   \
-        _SOFTEN_TEST(EXC_HV)
+        _SOFTEN_TEST(EXC_HV, vec)
 
 #define SOFTEN_TEST_HV_201(vec)                                         \
         KVMTEST(vec);                                                   \
-        _SOFTEN_TEST(EXC_STD)
+        _SOFTEN_TEST(EXC_STD, vec)
 
 #define __MASKABLE_EXCEPTION_PSERIES(vec, label, h, extra)              \
         HMT_MEDIUM;                                                     \
@@ -272,73 +279,55 @@ label##_hv:								\
         _MASKABLE_EXCEPTION_PSERIES(vec, label,                         \
                                     EXC_HV, SOFTEN_TEST_HV)
 
-#ifdef CONFIG_PPC_ISERIES
-#define DISABLE_INTS                            \
-        li      r11,0;                          \
-        stb     r11,PACASOFTIRQEN(r13);         \
-BEGIN_FW_FTR_SECTION;                           \
-        stb     r11,PACAHARDIRQEN(r13);         \
-END_FW_FTR_SECTION_IFCLR(FW_FEATURE_ISERIES);   \
-        TRACE_DISABLE_INTS;                     \
-BEGIN_FW_FTR_SECTION;                           \
-        mfmsr   r10;                            \
-        ori     r10,r10,MSR_EE;                 \
-        mtmsrd  r10,1;                          \
-END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES)
-#else
-#define DISABLE_INTS                            \
-        li      r11,0;                          \
-        stb     r11,PACASOFTIRQEN(r13);         \
-        stb     r11,PACAHARDIRQEN(r13);         \
-        TRACE_DISABLE_INTS
-#endif /* CONFIG_PPC_ISERIES */
+/*
+ * Our exception common code can be passed various "additions"
+ * to specify the behaviour of interrupts, whether to kick the
+ * runlatch, etc...
+ */
+
+/* Exception addition: Hard disable interrupts */
+#define DISABLE_INTS    SOFT_DISABLE_INTS(r10,r11)
 
+/* Exception addition: Keep interrupt state */
 #define ENABLE_INTS                             \
+        ld      r11,PACAKMSR(r13);              \
         ld      r12,_MSR(r1);                   \
-        mfmsr   r11;                            \
         rlwimi  r11,r12,0,MSR_EE;               \
         mtmsrd  r11,1
 
-#define STD_EXCEPTION_COMMON(trap, label, hdlr)         \
-        .align  7;                                      \
-        .globl label##_common;                          \
-label##_common:                                         \
-        EXCEPTION_PROLOG_COMMON(trap, PACA_EXGEN);      \
-        DISABLE_INTS;                                   \
-        bl      .save_nvgprs;                           \
-        addi    r3,r1,STACK_FRAME_OVERHEAD;             \
-        bl      hdlr;                                   \
-        b       .ret_from_except
+#define ADD_NVGPRS                              \
+        bl      .save_nvgprs
+
+#define RUNLATCH_ON                             \
+BEGIN_FTR_SECTION                               \
+        clrrdi  r3,r1,THREAD_SHIFT;             \
+        ld      r4,TI_LOCAL_FLAGS(r3);          \
+        andi.   r0,r4,_TLF_RUNLATCH;            \
+        beql    ppc64_runlatch_on_trampoline;   \
+END_FTR_SECTION_IFSET(CPU_FTR_CTRL)
+
+#define EXCEPTION_COMMON(trap, label, hdlr, ret, additions)     \
+        .align  7;                                              \
+        .globl label##_common;                                  \
+label##_common:                                                 \
+        EXCEPTION_PROLOG_COMMON(trap, PACA_EXGEN);              \
+        additions;                                              \
+        addi    r3,r1,STACK_FRAME_OVERHEAD;                     \
+        bl      hdlr;                                           \
+        b       ret
+
+#define STD_EXCEPTION_COMMON(trap, label, hdlr)                 \
+        EXCEPTION_COMMON(trap, label, hdlr, ret_from_except,    \
+                         ADD_NVGPRS;DISABLE_INTS)
 
 /*
  * Like STD_EXCEPTION_COMMON, but for exceptions that can occur
- * in the idle task and therefore need the special idle handling.
+ * in the idle task and therefore need the special idle handling
+ * (finish nap and runlatch)
  */
-#define STD_EXCEPTION_COMMON_IDLE(trap, label, hdlr)    \
-        .align  7;                                      \
-        .globl label##_common;                          \
-label##_common:                                         \
-        EXCEPTION_PROLOG_COMMON(trap, PACA_EXGEN);      \
-        FINISH_NAP;                                     \
-        DISABLE_INTS;                                   \
-        bl      .save_nvgprs;                           \
-        addi    r3,r1,STACK_FRAME_OVERHEAD;             \
-        bl      hdlr;                                   \
-        b       .ret_from_except
-
-#define STD_EXCEPTION_COMMON_LITE(trap, label, hdlr)    \
-        .align  7;                                      \
-        .globl label##_common;                          \
-label##_common:                                         \
-        EXCEPTION_PROLOG_COMMON(trap, PACA_EXGEN);      \
-        FINISH_NAP;                                     \
-        DISABLE_INTS;                                   \
-BEGIN_FTR_SECTION                                       \
-        bl      .ppc64_runlatch_on;                     \
-END_FTR_SECTION_IFSET(CPU_FTR_CTRL)                     \
-        addi    r3,r1,STACK_FRAME_OVERHEAD;             \
-        bl      hdlr;                                   \
-        b       .ret_from_except_lite
+#define STD_EXCEPTION_COMMON_ASYNC(trap, label, hdlr)             \
+        EXCEPTION_COMMON(trap, label, hdlr, ret_from_except_lite, \
+                         FINISH_NAP;RUNLATCH_ON;DISABLE_INTS)
 
 /*
  * When the idle code in power4_idle puts the CPU into NAP mode,
diff --git a/arch/powerpc/include/asm/fadump.h b/arch/powerpc/include/asm/fadump.h
new file mode 100644
index 00000000000..88dbf965918
--- /dev/null
+++ b/arch/powerpc/include/asm/fadump.h
@@ -0,0 +1,218 @@
+/*
+ * Firmware Assisted dump header file.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Copyright 2011 IBM Corporation
+ * Author: Mahesh Salgaonkar <mahesh@linux.vnet.ibm.com>
+ */
+
+#ifndef __PPC64_FA_DUMP_H__
+#define __PPC64_FA_DUMP_H__
+
+#ifdef CONFIG_FA_DUMP
+
+/*
+ * The RMA region will be saved for later dumping when kernel crashes.
+ * RMA is Real Mode Area, the first block of logical memory address owned
+ * by logical partition, containing the storage that may be accessed with
+ * translate off.
+ */
+#define RMA_START       0x0
+#define RMA_END         (ppc64_rma_size)
+
+/*
+ * On some Power systems where RMO is 128MB, it still requires minimum of
+ * 256MB for kernel to boot successfully. When kdump infrastructure is
+ * configured to save vmcore over network, we run into OOM issue while
+ * loading modules related to network setup. Hence we need aditional 64M
+ * of memory to avoid OOM issue.
+ */
+#define MIN_BOOT_MEM    (((RMA_END < (0x1UL << 28)) ? (0x1UL << 28) : RMA_END) \
+                        + (0x1UL << 26))
+
+#define memblock_num_regions(memblock_type)     (memblock.memblock_type.cnt)
+
+#ifndef ELF_CORE_EFLAGS
+#define ELF_CORE_EFLAGS 0
+#endif
+
+/* Firmware provided dump sections */
+#define FADUMP_CPU_STATE_DATA   0x0001
+#define FADUMP_HPTE_REGION      0x0002
+#define FADUMP_REAL_MODE_REGION 0x0011
+
+/* Dump request flag */
+#define FADUMP_REQUEST_FLAG     0x00000001
+
+/* FAD commands */
+#define FADUMP_REGISTER         1
+#define FADUMP_UNREGISTER       2
+#define FADUMP_INVALIDATE       3
+
+/* Dump status flag */
+#define FADUMP_ERROR_FLAG       0x2000
+
+#define FADUMP_CPU_ID_MASK      ((1UL << 32) - 1)
+
+#define CPU_UNKNOWN             (~((u32)0))
+
+/* Utility macros */
+#define SKIP_TO_NEXT_CPU(reg_entry)                     \
+({                                                      \
+        while (reg_entry->reg_id != REG_ID("CPUEND"))   \
+                reg_entry++;                            \
+        reg_entry++;                                    \
+})
+
+/* Kernel Dump section info */
+struct fadump_section {
+        u32     request_flag;
+        u16     source_data_type;
+        u16     error_flags;
+        u64     source_address;
+        u64     source_len;
+        u64     bytes_dumped;
+        u64     destination_address;
+};
+
+/* ibm,configure-kernel-dump header. */
+struct fadump_section_header {
+        u32     dump_format_version;
+        u16     dump_num_sections;
+        u16     dump_status_flag;
+        u32     offset_first_dump_section;
+
+        /* Fields for disk dump option. */
+        u32     dd_block_size;
+        u64     dd_block_offset;
+        u64     dd_num_blocks;
+        u32     dd_offset_disk_path;
+
+        /* Maximum time allowed to prevent an automatic dump-reboot. */
+        u32     max_time_auto;
+};
+
+/*
+ * Firmware Assisted dump memory structure. This structure is required for
+ * registering future kernel dump with power firmware through rtas call.
+ *
+ * No disk dump option. Hence disk dump path string section is not included.
+ */
+struct fadump_mem_struct {
+        struct fadump_section_header    header;
+
+        /* Kernel dump sections */
+        struct fadump_section           cpu_state_data;
+        struct fadump_section           hpte_region;
+        struct fadump_section           rmr_region;
+};
+
+/* Firmware-assisted dump configuration details. */
+struct fw_dump {
+        unsigned long   cpu_state_data_size;
+        unsigned long   hpte_region_size;
+        unsigned long   boot_memory_size;
+        unsigned long   reserve_dump_area_start;
+        unsigned long   reserve_dump_area_size;
+        /* cmd line option during boot */
+        unsigned long   reserve_bootvar;
+
+        unsigned long   fadumphdr_addr;
+        unsigned long   cpu_notes_buf;
+        unsigned long   cpu_notes_buf_size;
+
+        int             ibm_configure_kernel_dump;
+
+        unsigned long   fadump_enabled:1;
+        unsigned long   fadump_supported:1;
+        unsigned long   dump_active:1;
+        unsigned long   dump_registered:1;
+};
+
+/*
+ * Copy the ascii values for first 8 characters from a string into u64
+ * variable at their respective indexes.
+ * e.g.
+ *  The string "FADMPINF" will be converted into 0x4641444d50494e46
+ */
+static inline u64 str_to_u64(const char *str)
+{
+        u64 val = 0;
+        int i;
+
+        for (i = 0; i < sizeof(val); i++)
+                val = (*str) ? (val << 8) | *str++ : val << 8;
+        return val;
+}
+#define STR_TO_HEX(x)   str_to_u64(x)
+#define REG_ID(x)       str_to_u64(x)
+
+#define FADUMP_CRASH_INFO_MAGIC         STR_TO_HEX("FADMPINF")
+#define REGSAVE_AREA_MAGIC              STR_TO_HEX("REGSAVE")
+
+/* The firmware-assisted dump format.
+ *
+ * The register save area is an area in the partition's memory used to preserve
+ * the register contents (CPU state data) for the active CPUs during a firmware
+ * assisted dump. The dump format contains register save area header followed
+ * by register entries. Each list of registers for a CPU starts with
+ * "CPUSTRT" and ends with "CPUEND".
+ */
+
+/* Register save area header. */
+struct fadump_reg_save_area_header {
+        u64             magic_number;
+        u32             version;
+        u32             num_cpu_offset;
+};
+
+/* Register entry. */
+struct fadump_reg_entry {
+        u64             reg_id;
+        u64             reg_value;
+};
+
+/* fadump crash info structure */
+struct fadump_crash_info_header {
+        u64             magic_number;
+        u64             elfcorehdr_addr;
+        u32             crashing_cpu;
+        struct pt_regs  regs;
+        struct cpumask  cpu_online_mask;
+};
+
+/* Crash memory ranges */
+#define INIT_CRASHMEM_RANGES    (INIT_MEMBLOCK_REGIONS + 2)
+
+struct fad_crash_memory_ranges {
+        unsigned long long      base;
+        unsigned long long      size;
+};
+
+extern int early_init_dt_scan_fw_dump(unsigned long node,
+                const char *uname, int depth, void *data);
+extern int fadump_reserve_mem(void);
+extern int setup_fadump(void);
+extern int is_fadump_active(void);
+extern void crash_fadump(struct pt_regs *, const char *);
+extern void fadump_cleanup(void);
+
+extern void vmcore_cleanup(void);
+#else   /* CONFIG_FA_DUMP */
+static inline int is_fadump_active(void) { return 0; }
+static inline void crash_fadump(struct pt_regs *regs, const char *str) { }
+#endif
+#endif
diff --git a/arch/powerpc/include/asm/firmware.h b/arch/powerpc/include/asm/firmware.h
index 14db29b18d0..ad0b751b0d7 100644
--- a/arch/powerpc/include/asm/firmware.h
+++ b/arch/powerpc/include/asm/firmware.h
@@ -41,7 +41,6 @@
 #define FW_FEATURE_XDABR        ASM_CONST(0x0000000000040000)
 #define FW_FEATURE_MULTITCE     ASM_CONST(0x0000000000080000)
 #define FW_FEATURE_SPLPAR       ASM_CONST(0x0000000000100000)
-#define FW_FEATURE_ISERIES      ASM_CONST(0x0000000000200000)
 #define FW_FEATURE_LPAR         ASM_CONST(0x0000000000400000)
 #define FW_FEATURE_PS3_LV1      ASM_CONST(0x0000000000800000)
 #define FW_FEATURE_BEAT         ASM_CONST(0x0000000001000000)
@@ -65,8 +64,6 @@ enum {
                 FW_FEATURE_MULTITCE | FW_FEATURE_SPLPAR | FW_FEATURE_LPAR |
                 FW_FEATURE_CMO | FW_FEATURE_VPHN | FW_FEATURE_XCMO,
         FW_FEATURE_PSERIES_ALWAYS = 0,
-        FW_FEATURE_ISERIES_POSSIBLE = FW_FEATURE_ISERIES | FW_FEATURE_LPAR,
-        FW_FEATURE_ISERIES_ALWAYS = FW_FEATURE_ISERIES | FW_FEATURE_LPAR,
         FW_FEATURE_POWERNV_POSSIBLE = FW_FEATURE_OPAL | FW_FEATURE_OPALv2,
         FW_FEATURE_POWERNV_ALWAYS = 0,
         FW_FEATURE_PS3_POSSIBLE = FW_FEATURE_LPAR | FW_FEATURE_PS3_LV1,
@@ -79,9 +76,6 @@ enum {
 #ifdef CONFIG_PPC_PSERIES
                 FW_FEATURE_PSERIES_POSSIBLE |
 #endif
-#ifdef CONFIG_PPC_ISERIES
-                FW_FEATURE_ISERIES_POSSIBLE |
-#endif
 #ifdef CONFIG_PPC_POWERNV
                 FW_FEATURE_POWERNV_POSSIBLE |
 #endif
@@ -99,9 +93,6 @@ enum {
 #ifdef CONFIG_PPC_PSERIES
                 FW_FEATURE_PSERIES_ALWAYS &
 #endif
-#ifdef CONFIG_PPC_ISERIES
-                FW_FEATURE_ISERIES_ALWAYS &
-#endif
 #ifdef CONFIG_PPC_POWERNV
                 FW_FEATURE_POWERNV_ALWAYS &
 #endif
diff --git a/arch/powerpc/include/asm/fsl_guts.h b/arch/powerpc/include/asm/fsl_guts.h
index bebd12463ec..ce04530d200 100644
--- a/arch/powerpc/include/asm/fsl_guts.h
+++ b/arch/powerpc/include/asm/fsl_guts.h
@@ -4,7 +4,7 @@
  * Authors: Jeff Brown
  *          Timur Tabi <timur@freescale.com>
  *
- * Copyright 2004,2007 Freescale Semiconductor, Inc
+ * Copyright 2004,2007,2012 Freescale Semiconductor, Inc
  *
  * This program is free software; you can redistribute  it and/or modify it
  * under  the terms of  the GNU General  Public License as published by the
@@ -114,6 +114,10 @@ struct ccsr_guts_86xx {
         __be32  srds2cr1;       /* 0x.0f44 - SerDes2 Control Register 0 */
 } __attribute__ ((packed));
 
+
+/* Alternate function signal multiplex control */
+#define MPC85xx_PMUXCR_QE(x) (0x8000 >> (x))
+
 #ifdef CONFIG_PPC_86xx
 
 #define CCSR_GUTS_DMACR_DEV_SSI 0       /* DMA controller/channel set to SSI */
diff --git a/arch/powerpc/include/asm/hw_irq.h b/arch/powerpc/include/asm/hw_irq.h
index bb712c9488b..51010bfc792 100644
--- a/arch/powerpc/include/asm/hw_irq.h
+++ b/arch/powerpc/include/asm/hw_irq.h
@@ -11,6 +11,27 @@
 #include <asm/ptrace.h>
 #include <asm/processor.h>
 
+#ifdef CONFIG_PPC64
+
+/*
+ * PACA flags in paca->irq_happened.
+ *
+ * This bits are set when interrupts occur while soft-disabled
+ * and allow a proper replay. Additionally, PACA_IRQ_HARD_DIS
+ * is set whenever we manually hard disable.
+ */
+#define PACA_IRQ_HARD_DIS       0x01
+#define PACA_IRQ_DBELL          0x02
+#define PACA_IRQ_EE             0x04
+#define PACA_IRQ_DEC            0x08 /* Or FIT */
+#define PACA_IRQ_EE_EDGE        0x10 /* BookE only */
+
+#endif /* CONFIG_PPC64 */
+
+#ifndef __ASSEMBLY__
+
+extern void __replay_interrupt(unsigned int vector);
+
 extern void timer_interrupt(struct pt_regs *);
 
 #ifdef CONFIG_PPC64
@@ -42,7 +63,6 @@ static inline unsigned long arch_local_irq_disable(void)
 }
 
 extern void arch_local_irq_restore(unsigned long);
-extern void iseries_handle_interrupts(void);
 
 static inline void arch_local_irq_enable(void)
 {
@@ -68,16 +88,33 @@ static inline bool arch_irqs_disabled(void)
 #define __hard_irq_enable()     asm volatile("wrteei 1" : : : "memory");
 #define __hard_irq_disable()    asm volatile("wrteei 0" : : : "memory");
 #else
-#define __hard_irq_enable()     __mtmsrd(mfmsr() | MSR_EE, 1)
-#define __hard_irq_disable()    __mtmsrd(mfmsr() & ~MSR_EE, 1)
+#define __hard_irq_enable()     __mtmsrd(local_paca->kernel_msr | MSR_EE, 1)
+#define __hard_irq_disable()    __mtmsrd(local_paca->kernel_msr, 1)
 #endif
 
-#define  hard_irq_disable()                     \
-        do {                                    \
-                __hard_irq_disable();           \
-                get_paca()->soft_enabled = 0;   \
-                get_paca()->hard_enabled = 0;   \
-        } while(0)
+static inline void hard_irq_disable(void)
+{
+        __hard_irq_disable();
+        get_paca()->soft_enabled = 0;
+        get_paca()->irq_happened |= PACA_IRQ_HARD_DIS;
+}
+
+/*
+ * This is called by asynchronous interrupts to conditionally
+ * re-enable hard interrupts when soft-disabled after having
+ * cleared the source of the interrupt
+ */
+static inline void may_hard_irq_enable(void)
+{
+        get_paca()->irq_happened &= ~PACA_IRQ_HARD_DIS;
+        if (!(get_paca()->irq_happened & PACA_IRQ_EE))
+                __hard_irq_enable();
+}
+
+static inline bool arch_irq_disabled_regs(struct pt_regs *regs)
+{
+        return !regs->softe;
+}
 
 #else /* CONFIG_PPC64 */
 
@@ -139,6 +176,13 @@ static inline bool arch_irqs_disabled(void)
 
 #define hard_irq_disable()              arch_local_irq_disable()
 
+static inline bool arch_irq_disabled_regs(struct pt_regs *regs)
+{
+        return !(regs->msr & MSR_EE);
+}
+
+static inline void may_hard_irq_enable(void) { }
+
 #endif /* CONFIG_PPC64 */
 
 #define ARCH_IRQ_INIT_FLAGS     IRQ_NOREQUEST
@@ -149,5 +193,6 @@ static inline bool arch_irqs_disabled(void)
  */
 struct irq_chip;
 
+#endif  /* __ASSEMBLY__ */
 #endif  /* __KERNEL__ */
 #endif  /* _ASM_POWERPC_HW_IRQ_H */
diff --git a/arch/powerpc/include/asm/irqflags.h b/arch/powerpc/include/asm/irqflags.h
index b0b06d85788..6f9b6e23dc5 100644
--- a/arch/powerpc/include/asm/irqflags.h
+++ b/arch/powerpc/include/asm/irqflags.h
@@ -39,24 +39,31 @@
 #define TRACE_ENABLE_INTS       TRACE_WITH_FRAME_BUFFER(.trace_hardirqs_on)
 #define TRACE_DISABLE_INTS      TRACE_WITH_FRAME_BUFFER(.trace_hardirqs_off)
 
-#define TRACE_AND_RESTORE_IRQ_PARTIAL(en,skip)          \
-        cmpdi   en,0;                                   \
-        bne     95f;                                    \
-        stb     en,PACASOFTIRQEN(r13);                  \
-        TRACE_WITH_FRAME_BUFFER(.trace_hardirqs_off)    \
-        b       skip;                                   \
-95:     TRACE_WITH_FRAME_BUFFER(.trace_hardirqs_on)     \
-        li      en,1;
-#define TRACE_AND_RESTORE_IRQ(en)               \
-        TRACE_AND_RESTORE_IRQ_PARTIAL(en,96f);  \
-        stb     en,PACASOFTIRQEN(r13);          \
-96:
+/*
+ * This is used by assembly code to soft-disable interrupts
+ */
+#define SOFT_DISABLE_INTS(__rA, __rB)           \
+        lbz     __rA,PACASOFTIRQEN(r13);        \
+        lbz     __rB,PACAIRQHAPPENED(r13);      \
+        cmpwi   cr0,__rA,0;                     \
+        li      __rA,0;                         \
+        ori     __rB,__rB,PACA_IRQ_HARD_DIS;    \
+        stb     __rB,PACAIRQHAPPENED(r13);      \
+        beq     44f;                            \
+        stb     __rA,PACASOFTIRQEN(r13);        \
+        TRACE_DISABLE_INTS;                     \
+44:
+
 #else
 #define TRACE_ENABLE_INTS
 #define TRACE_DISABLE_INTS
-#define TRACE_AND_RESTORE_IRQ_PARTIAL(en,skip)
-#define TRACE_AND_RESTORE_IRQ(en)               \
-        stb     en,PACASOFTIRQEN(r13)
+
+#define SOFT_DISABLE_INTS(__rA, __rB)           \
+        lbz     __rA,PACAIRQHAPPENED(r13);      \
+        li      __rB,0;                         \
+        ori     __rA,__rA,PACA_IRQ_HARD_DIS;    \
+        stb     __rB,PACASOFTIRQEN(r13);        \
+        stb     __rA,PACAIRQHAPPENED(r13)
 #endif
 #endif
 
diff --git a/arch/powerpc/include/asm/iseries/alpaca.h b/arch/powerpc/include/asm/iseries/alpaca.h
deleted file mode 100644
index c0cce6727a6..00000000000
--- a/arch/powerpc/include/asm/iseries/alpaca.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/*
- * Copyright © 2008  Stephen Rothwell IBM Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
- */
-#ifndef _ASM_POWERPC_ISERIES_ALPACA_H
-#define _ASM_POWERPC_ISERIES_ALPACA_H
-
-/*
- * This is the part of the paca that the iSeries hypervisor
- * needs to be statically initialised. Immediately after boot
- * we switch to the normal Linux paca.
- */
-struct alpaca {
-        struct lppaca *lppaca_ptr;      /* Pointer to LpPaca for PLIC */
-        const void *reg_save_ptr;       /* Pointer to LpRegSave for PLIC */
-};
-
-#endif /* _ASM_POWERPC_ISERIES_ALPACA_H */
diff --git a/arch/powerpc/include/asm/iseries/hv_call.h b/arch/powerpc/include/asm/iseries/hv_call.h
deleted file mode 100644
index 162d653ad51..00000000000
--- a/arch/powerpc/include/asm/iseries/hv_call.h
+++ /dev/null
@@ -1,111 +0,0 @@
-/*
- * Copyright (C) 2001  Mike Corrigan IBM Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
- *
- * This file contains the "hypervisor call" interface which is used to
- * drive the hypervisor from the OS.
- */
-#ifndef _ASM_POWERPC_ISERIES_HV_CALL_H
-#define _ASM_POWERPC_ISERIES_HV_CALL_H
-
-#include <asm/iseries/hv_call_sc.h>
-#include <asm/iseries/hv_types.h>
-#include <asm/paca.h>
-
-/* Type of yield for HvCallBaseYieldProcessor */
-#define HvCall_YieldTimed       0       /* Yield until specified time (tb) */
-#define HvCall_YieldToActive    1       /* Yield until all active procs have run */
-#define HvCall_YieldToProc      2       /* Yield until the specified processor has run */
-
-/* interrupt masks for setEnabledInterrupts */
-#define HvCall_MaskIPI          0x00000001
-#define HvCall_MaskLpEvent      0x00000002
-#define HvCall_MaskLpProd       0x00000004
-#define HvCall_MaskTimeout      0x00000008
-
-/* Log buffer formats */
-#define HvCall_LogBuffer_ASCII          0
-#define HvCall_LogBuffer_EBCDIC         1
-
-#define HvCallBaseAckDeferredInts                       HvCallBase +  0
-#define HvCallBaseCpmPowerOff                           HvCallBase +  1
-#define HvCallBaseGetHwPatch                            HvCallBase +  2
-#define HvCallBaseReIplSpAttn                           HvCallBase +  3
-#define HvCallBaseSetASR                                HvCallBase +  4
-#define HvCallBaseSetASRAndRfi                          HvCallBase +  5
-#define HvCallBaseSetIMR                                HvCallBase +  6
-#define HvCallBaseSendIPI                               HvCallBase +  7
-#define HvCallBaseTerminateMachine                      HvCallBase +  8
-#define HvCallBaseTerminateMachineSrc                   HvCallBase +  9
-#define HvCallBaseProcessPlicInterrupts                 HvCallBase + 10
-#define HvCallBaseIsPrimaryCpmOrMsdIpl                  HvCallBase + 11
-#define HvCallBaseSetVirtualSIT                         HvCallBase + 12
-#define HvCallBaseVaryOffThisProcessor                  HvCallBase + 13
-#define HvCallBaseVaryOffMemoryChunk                    HvCallBase + 14
-#define HvCallBaseVaryOffInteractivePercentage          HvCallBase + 15
-#define HvCallBaseSendLpProd                            HvCallBase + 16
-#define HvCallBaseSetEnabledInterrupts                  HvCallBase + 17
-#define HvCallBaseYieldProcessor                        HvCallBase + 18
-#define HvCallBaseVaryOffSharedProcUnits                HvCallBase + 19
-#define HvCallBaseSetVirtualDecr                        HvCallBase + 20
-#define HvCallBaseClearLogBuffer                        HvCallBase + 21
-#define HvCallBaseGetLogBufferCodePage                  HvCallBase + 22
-#define HvCallBaseGetLogBufferFormat                    HvCallBase + 23
-#define HvCallBaseGetLogBufferLength                    HvCallBase + 24
-#define HvCallBaseReadLogBuffer                         HvCallBase + 25
-#define HvCallBaseSetLogBufferFormatAndCodePage         HvCallBase + 26
-#define HvCallBaseWriteLogBuffer                        HvCallBase + 27
-#define HvCallBaseRouter28                              HvCallBase + 28
-#define HvCallBaseRouter29                              HvCallBase + 29
-#define HvCallBaseRouter30                              HvCallBase + 30
-#define HvCallBaseSetDebugBus                           HvCallBase + 31
-
-#define HvCallCcSetDABR                                 HvCallCc + 7
-
-static inline void HvCall_setVirtualDecr(void)
-{
-        /*
-         * Ignore any error return codes - most likely means that the
-         * target value for the LP has been increased and this vary off
-         * would bring us below the new target.
-         */
-        HvCall0(HvCallBaseSetVirtualDecr);
-}
-
-static inline void HvCall_yieldProcessor(unsigned typeOfYield, u64 yieldParm)
-{
-        HvCall2(HvCallBaseYieldProcessor, typeOfYield, yieldParm);
-}
-
-static inline void HvCall_setEnabledInterrupts(u64 enabledInterrupts)
-{
-        HvCall1(HvCallBaseSetEnabledInterrupts, enabledInterrupts);
-}
-
-static inline void HvCall_setLogBufferFormatAndCodepage(int format,
-                u32 codePage)
-{
-        HvCall2(HvCallBaseSetLogBufferFormatAndCodePage, format, codePage);
-}
-
-extern void HvCall_writeLogBuffer(const void *buffer, u64 bufLen);
-
-static inline void HvCall_sendIPI(struct paca_struct *targetPaca)
-{
-        HvCall1(HvCallBaseSendIPI, targetPaca->paca_index);
-}
-
-#endif /* _ASM_POWERPC_ISERIES_HV_CALL_H */
diff --git a/arch/powerpc/include/asm/iseries/hv_call_event.h b/arch/powerpc/include/asm/iseries/hv_call_event.h
deleted file mode 100644
index cc029d388e1..00000000000
--- a/arch/powerpc/include/asm/iseries/hv_call_event.h
+++ /dev/null
@@ -1,201 +0,0 @@
-/*
- * Copyright (C) 2001  Mike Corrigan IBM Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
- *
- * This file contains the "hypervisor call" interface which is used to
- * drive the hypervisor from the OS.
- */
-#ifndef _ASM_POWERPC_ISERIES_HV_CALL_EVENT_H
-#define _ASM_POWERPC_ISERIES_HV_CALL_EVENT_H
-
-#include <linux/types.h>
-#include <linux/dma-mapping.h>
-
-#include <asm/iseries/hv_call_sc.h>
-#include <asm/iseries/hv_types.h>
-#include <asm/abs_addr.h>
-
-struct HvLpEvent;
-
-typedef u8 HvLpEvent_Type;
-typedef u8 HvLpEvent_AckInd;
-typedef u8 HvLpEvent_AckType;
-
-typedef u8 HvLpDma_Direction;
-typedef u8 HvLpDma_AddressType;
-
-typedef u64 HvLpEvent_Rc;
-typedef u64 HvLpDma_Rc;
-
-#define HvCallEventAckLpEvent                           HvCallEvent +  0
-#define HvCallEventCancelLpEvent                        HvCallEvent +  1
-#define HvCallEventCloseLpEventPath                     HvCallEvent +  2
-#define HvCallEventDmaBufList                           HvCallEvent +  3
-#define HvCallEventDmaSingle                            HvCallEvent +  4
-#define HvCallEventDmaToSp                              HvCallEvent +  5
-#define HvCallEventGetOverflowLpEvents                  HvCallEvent +  6
-#define HvCallEventGetSourceLpInstanceId                HvCallEvent +  7
-#define HvCallEventGetTargetLpInstanceId                HvCallEvent +  8
-#define HvCallEventOpenLpEventPath                      HvCallEvent +  9
-#define HvCallEventSetLpEventStack                      HvCallEvent + 10
-#define HvCallEventSignalLpEvent                        HvCallEvent + 11
-#define HvCallEventSignalLpEventParms                   HvCallEvent + 12
-#define HvCallEventSetInterLpQueueIndex                 HvCallEvent + 13
-#define HvCallEventSetLpEventQueueInterruptProc         HvCallEvent + 14
-#define HvCallEventRouter15                             HvCallEvent + 15
-
-static inline void HvCallEvent_getOverflowLpEvents(u8 queueIndex)
-{
-        HvCall1(HvCallEventGetOverflowLpEvents, queueIndex);
-}
-
-static inline void HvCallEvent_setInterLpQueueIndex(u8 queueIndex)
-{
-        HvCall1(HvCallEventSetInterLpQueueIndex, queueIndex);
-}
-
-static inline void HvCallEvent_setLpEventStack(u8 queueIndex,
-                char *eventStackAddr, u32 eventStackSize)
-{
-        HvCall3(HvCallEventSetLpEventStack, queueIndex,
-                        virt_to_abs(eventStackAddr), eventStackSize);
-}
-
-static inline void HvCallEvent_setLpEventQueueInterruptProc(u8 queueIndex,
-                u16 lpLogicalProcIndex)
-{
-        HvCall2(HvCallEventSetLpEventQueueInterruptProc, queueIndex,
-                        lpLogicalProcIndex);
-}
-
-static inline HvLpEvent_Rc HvCallEvent_signalLpEvent(struct HvLpEvent *event)
-{
-        return HvCall1(HvCallEventSignalLpEvent, virt_to_abs(event));
-}
-
-static inline HvLpEvent_Rc HvCallEvent_signalLpEventFast(HvLpIndex targetLp,
-                HvLpEvent_Type type, u16 subtype, HvLpEvent_AckInd ackInd,
-                HvLpEvent_AckType ackType, HvLpInstanceId sourceInstanceId,
-                HvLpInstanceId targetInstanceId, u64 correlationToken,
-                u64 eventData1, u64 eventData2, u64 eventData3,
-                u64 eventData4, u64 eventData5)
-{
-        /* Pack the misc bits into a single Dword to pass to PLIC */
-        union {
-                struct {
-                        u8              ack_and_target;
-                        u8              type;
-                        u16             subtype;
-                        HvLpInstanceId  src_inst;
-                        HvLpInstanceId  target_inst;
-                } parms;
-                u64             dword;
-        } packed;
-
-        packed.parms.ack_and_target = (ackType << 7) | (ackInd << 6) | targetLp;
-        packed.parms.type = type;
-        packed.parms.subtype = subtype;
-        packed.parms.src_inst = sourceInstanceId;
-        packed.parms.target_inst = targetInstanceId;
-
-        return HvCall7(HvCallEventSignalLpEventParms, packed.dword,
-                        correlationToken, eventData1, eventData2,
-                        eventData3, eventData4, eventData5);
-}
-
-extern void *iseries_hv_alloc(size_t size, dma_addr_t *dma_handle, gfp_t flag);
-extern void iseries_hv_free(size_t size, void *vaddr, dma_addr_t dma_handle);
-extern dma_addr_t iseries_hv_map(void *vaddr, size_t size,
-                        enum dma_data_direction direction);
-extern void iseries_hv_unmap(dma_addr_t dma_handle, size_t size,
-                        enum dma_data_direction direction);
-
-static inline HvLpEvent_Rc HvCallEvent_ackLpEvent(struct HvLpEvent *event)
-{
-        return HvCall1(HvCallEventAckLpEvent, virt_to_abs(event));
-}
-
-static inline HvLpEvent_Rc HvCallEvent_cancelLpEvent(struct HvLpEvent *event)
-{
-        return HvCall1(HvCallEventCancelLpEvent, virt_to_abs(event));
-}
-
-static inline HvLpInstanceId HvCallEvent_getSourceLpInstanceId(
-                HvLpIndex targetLp, HvLpEvent_Type type)
-{
-        return HvCall2(HvCallEventGetSourceLpInstanceId, targetLp, type);
-}
-
-static inline HvLpInstanceId HvCallEvent_getTargetLpInstanceId(
-                HvLpIndex targetLp, HvLpEvent_Type type)
-{
-        return HvCall2(HvCallEventGetTargetLpInstanceId, targetLp, type);
-}
-
-static inline void HvCallEvent_openLpEventPath(HvLpIndex targetLp,
-                HvLpEvent_Type type)
-{
-        HvCall2(HvCallEventOpenLpEventPath, targetLp, type);
-}
-
-static inline void HvCallEvent_closeLpEventPath(HvLpIndex targetLp,
-                HvLpEvent_Type type)
-{
-        HvCall2(HvCallEventCloseLpEventPath, targetLp, type);
-}
-
-static inline HvLpDma_Rc HvCallEvent_dmaBufList(HvLpEvent_Type type,
-                HvLpIndex remoteLp, HvLpDma_Direction direction,
-                HvLpInstanceId localInstanceId,
-                HvLpInstanceId remoteInstanceId,
-                HvLpDma_AddressType localAddressType,
-                HvLpDma_AddressType remoteAddressType,
-                /* Do these need to be converted to absolute addresses? */
-                u64 localBufList, u64 remoteBufList, u32 transferLength)
-{
-        /* Pack the misc bits into a single Dword to pass to PLIC */
-        union {
-                struct {
-                        u8              flags;
-                        HvLpIndex       remote;
-                        u8              type;
-                        u8              reserved;
-                        HvLpInstanceId  local_inst;
-                        HvLpInstanceId  remote_inst;
-                } parms;
-                u64             dword;
-        } packed;
-
-        packed.parms.flags = (direction << 7) |
-                (localAddressType << 6) | (remoteAddressType << 5);
-        packed.parms.remote = remoteLp;
-        packed.parms.type = type;
-        packed.parms.reserved = 0;
-        packed.parms.local_inst = localInstanceId;
-        packed.parms.remote_inst = remoteInstanceId;
-
-        return HvCall4(HvCallEventDmaBufList, packed.dword, localBufList,
-                        remoteBufList, transferLength);
-}
-
-static inline HvLpDma_Rc HvCallEvent_dmaToSp(void *local, u32 remote,
-                u32 length, HvLpDma_Direction dir)
-{
-        return HvCall4(HvCallEventDmaToSp, virt_to_abs(local), remote,
-                        length, dir);
-}
-
-#endif /* _ASM_POWERPC_ISERIES_HV_CALL_EVENT_H */
diff --git a/arch/powerpc/include/asm/iseries/hv_call_sc.h b/arch/powerpc/include/asm/iseries/hv_call_sc.h
deleted file mode 100644
index f5d21095925..00000000000
--- a/arch/powerpc/include/asm/iseries/hv_call_sc.h
+++ /dev/null
@@ -1,50 +0,0 @@
-/*
- * Copyright (C) 2001  Mike Corrigan IBM Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
- */
-#ifndef _ASM_POWERPC_ISERIES_HV_CALL_SC_H
-#define _ASM_POWERPC_ISERIES_HV_CALL_SC_H
-
-#include <linux/types.h>
-
-#define HvCallBase              0x8000000000000000ul
-#define HvCallCc                0x8001000000000000ul
-#define HvCallCfg               0x8002000000000000ul
-#define HvCallEvent             0x8003000000000000ul
-#define HvCallHpt               0x8004000000000000ul
-#define HvCallPci               0x8005000000000000ul
-#define HvCallSm                0x8007000000000000ul
-#define HvCallXm                0x8009000000000000ul
-
-extern u64 HvCall0(u64);
-extern u64 HvCall1(u64, u64);
-extern u64 HvCall2(u64, u64, u64);
-extern u64 HvCall3(u64, u64, u64, u64);
-extern u64 HvCall4(u64, u64, u64, u64, u64);
-extern u64 HvCall5(u64, u64, u64, u64, u64, u64);
-extern u64 HvCall6(u64, u64, u64, u64, u64, u64, u64);
-extern u64 HvCall7(u64, u64, u64, u64, u64, u64, u64, u64);
-
-extern u64 HvCall0Ret16(u64, void *);
-extern u64 HvCall1Ret16(u64, void *, u64);
-extern u64 HvCall2Ret16(u64, void *, u64, u64);
-extern u64 HvCall3Ret16(u64, void *, u64, u64, u64);
-extern u64 HvCall4Ret16(u64, void *, u64, u64, u64, u64);
-extern u64 HvCall5Ret16(u64, void *, u64, u64, u64, u64, u64);
-extern u64 HvCall6Ret16(u64, void *, u64, u64, u64, u64, u64, u64);
-extern u64 HvCall7Ret16(u64, void *, u64, u64 ,u64 ,u64 ,u64 ,u64 ,u64);
-
-#endif /* _ASM_POWERPC_ISERIES_HV_CALL_SC_H */
diff --git a/arch/powerpc/include/asm/iseries/hv_call_xm.h b/arch/powerpc/include/asm/iseries/hv_call_xm.h
deleted file mode 100644
index 392ac3f54df..00000000000
--- a/arch/powerpc/include/asm/iseries/hv_call_xm.h
+++ /dev/null
@@ -1,61 +0,0 @@
-/*
- * This file contains the "hypervisor call" interface which is used to
- * drive the hypervisor from SLIC.
- */
-#ifndef _ASM_POWERPC_ISERIES_HV_CALL_XM_H
-#define _ASM_POWERPC_ISERIES_HV_CALL_XM_H
-
-#include <asm/iseries/hv_call_sc.h>
-#include <asm/iseries/hv_types.h>
-
-#define HvCallXmGetTceTableParms        HvCallXm +  0
-#define HvCallXmTestBus                 HvCallXm +  1
-#define HvCallXmConnectBusUnit          HvCallXm +  2
-#define HvCallXmLoadTod                 HvCallXm +  8
-#define HvCallXmTestBusUnit             HvCallXm +  9
-#define HvCallXmSetTce                  HvCallXm + 11
-#define HvCallXmSetTces                 HvCallXm + 13
-
-static inline void HvCallXm_getTceTableParms(u64 cb)
-{
-        HvCall1(HvCallXmGetTceTableParms, cb);
-}
-
-static inline u64 HvCallXm_setTce(u64 tceTableToken, u64 tceOffset, u64 tce)
-{
-        return HvCall3(HvCallXmSetTce, tceTableToken, tceOffset, tce);
-}
-
-static inline u64 HvCallXm_setTces(u64 tceTableToken, u64 tceOffset,
-                u64 numTces, u64 tce1, u64 tce2, u64 tce3, u64 tce4)
-{
-        return HvCall7(HvCallXmSetTces, tceTableToken, tceOffset, numTces,
-                             tce1, tce2, tce3, tce4);
-}
-
-static inline u64 HvCallXm_testBus(u16 busNumber)
-{
-        return HvCall1(HvCallXmTestBus, busNumber);
-}
-
-static inline u64 HvCallXm_testBusUnit(u16 busNumber, u8 subBusNumber,
-                u8 deviceId)
-{
-        return HvCall2(HvCallXmTestBusUnit, busNumber,
-                        (subBusNumber << 8) | deviceId);
-}
-
-static inline u64 HvCallXm_connectBusUnit(u16 busNumber, u8 subBusNumber,
-                u8 deviceId, u64 interruptToken)
-{
-        return HvCall5(HvCallXmConnectBusUnit, busNumber,
-                        (subBusNumber << 8) | deviceId, interruptToken, 0,
-                        0 /* HvLpConfig::mapDsaToQueueIndex(HvLpDSA(busNumber, xBoard, xCard)) */);
-}
-
-static inline u64 HvCallXm_loadTod(void)
-{
-        return HvCall0(HvCallXmLoadTod);
-}
-
-#endif /* _ASM_POWERPC_ISERIES_HV_CALL_XM_H */
diff --git a/arch/powerpc/include/asm/iseries/hv_lp_config.h b/arch/powerpc/include/asm/iseries/hv_lp_config.h
deleted file mode 100644
index a006fd1e4a2..00000000000
--- a/arch/powerpc/include/asm/iseries/hv_lp_config.h
+++ /dev/null
@@ -1,128 +0,0 @@
-/*
- * Copyright (C) 2001  Mike Corrigan IBM Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
- */
-#ifndef _ASM_POWERPC_ISERIES_HV_LP_CONFIG_H
-#define _ASM_POWERPC_ISERIES_HV_LP_CONFIG_H
-
-/*
- * This file contains the interface to the LPAR configuration data
- * to determine which resources should be allocated to each partition.
- */
-
-#include <asm/iseries/hv_call_sc.h>
-#include <asm/iseries/hv_types.h>
-
-enum {
-        HvCallCfg_Cur   = 0,
-        HvCallCfg_Init  = 1,
-        HvCallCfg_Max   = 2,
-        HvCallCfg_Min   = 3
-};
-
-#define HvCallCfgGetSystemPhysicalProcessors            HvCallCfg +  6
-#define HvCallCfgGetPhysicalProcessors                  HvCallCfg +  7
-#define HvCallCfgGetMsChunks                            HvCallCfg +  9
-#define HvCallCfgGetSharedPoolIndex                     HvCallCfg + 20
-#define HvCallCfgGetSharedProcUnits                     HvCallCfg + 21
-#define HvCallCfgGetNumProcsInSharedPool                HvCallCfg + 22
-#define HvCallCfgGetVirtualLanIndexMap                  HvCallCfg + 30
-#define HvCallCfgGetHostingLpIndex                      HvCallCfg + 32
-
-extern HvLpIndex HvLpConfig_getLpIndex_outline(void);
-extern HvLpIndex HvLpConfig_getLpIndex(void);
-extern HvLpIndex HvLpConfig_getPrimaryLpIndex(void);
-
-static inline u64 HvLpConfig_getMsChunks(void)
-{
-        return HvCall2(HvCallCfgGetMsChunks, HvLpConfig_getLpIndex(),
-                        HvCallCfg_Cur);
-}
-
-static inline u64 HvLpConfig_getSystemPhysicalProcessors(void)
-{
-        return HvCall0(HvCallCfgGetSystemPhysicalProcessors);
-}
-
-static inline u64 HvLpConfig_getNumProcsInSharedPool(HvLpSharedPoolIndex sPI)
-{
-        return (u16)HvCall1(HvCallCfgGetNumProcsInSharedPool, sPI);
-}
-
-static inline u64 HvLpConfig_getPhysicalProcessors(void)
-{
-        return HvCall2(HvCallCfgGetPhysicalProcessors, HvLpConfig_getLpIndex(),
-                        HvCallCfg_Cur);
-}
-
-static inline HvLpSharedPoolIndex HvLpConfig_getSharedPoolIndex(void)
-{
-        return HvCall1(HvCallCfgGetSharedPoolIndex, HvLpConfig_getLpIndex());
-}
-
-static inline u64 HvLpConfig_getSharedProcUnits(void)
-{
-        return HvCall2(HvCallCfgGetSharedProcUnits, HvLpConfig_getLpIndex(),
-                        HvCallCfg_Cur);
-}
-
-static inline u64 HvLpConfig_getMaxSharedProcUnits(void)
-{
-        return HvCall2(HvCallCfgGetSharedProcUnits, HvLpConfig_getLpIndex(),
-                        HvCallCfg_Max);
-}
-
-static inline u64 HvLpConfig_getMaxPhysicalProcessors(void)
-{
-        return HvCall2(HvCallCfgGetPhysicalProcessors, HvLpConfig_getLpIndex(),
-                        HvCallCfg_Max);
-}
-
-static inline HvLpVirtualLanIndexMap HvLpConfig_getVirtualLanIndexMapForLp(
-                HvLpIndex lp)
-{
-        /*
-         * This is a new function in V5R1 so calls to this on older
-         * hypervisors will return -1
-         */
-        u64 retVal = HvCall1(HvCallCfgGetVirtualLanIndexMap, lp);
-        if (retVal == -1)
-                retVal = 0;
-        return retVal;
-}
-
-static inline HvLpVirtualLanIndexMap HvLpConfig_getVirtualLanIndexMap(void)
-{
-        return HvLpConfig_getVirtualLanIndexMapForLp(
-                        HvLpConfig_getLpIndex_outline());
-}
-
-static inline int HvLpConfig_doLpsCommunicateOnVirtualLan(HvLpIndex lp1,
-                HvLpIndex lp2)
-{
-        HvLpVirtualLanIndexMap virtualLanIndexMap1 =
-                HvLpConfig_getVirtualLanIndexMapForLp(lp1);
-        HvLpVirtualLanIndexMap virtualLanIndexMap2 =
-                HvLpConfig_getVirtualLanIndexMapForLp(lp2);
-        return ((virtualLanIndexMap1 & virtualLanIndexMap2) != 0);
-}
-
-static inline HvLpIndex HvLpConfig_getHostingLpIndex(HvLpIndex lp)
-{
-        return HvCall1(HvCallCfgGetHostingLpIndex, lp);
-}
-
-#endif /* _ASM_POWERPC_ISERIES_HV_LP_CONFIG_H */
diff --git a/arch/powerpc/include/asm/iseries/hv_lp_event.h b/arch/powerpc/include/asm/iseries/hv_lp_event.h
deleted file mode 100644
index 8f5da7d7720..00000000000
--- a/arch/powerpc/include/asm/iseries/hv_lp_event.h
+++ /dev/null
@@ -1,162 +0,0 @@
-/*
- * Copyright (C) 2001  Mike Corrigan IBM Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
- */
-
-/* This file contains the class for HV events in the system. */
-
-#ifndef _ASM_POWERPC_ISERIES_HV_LP_EVENT_H
-#define _ASM_POWERPC_ISERIES_HV_LP_EVENT_H
-
-#include <asm/types.h>
-#include <asm/ptrace.h>
-#include <asm/iseries/hv_types.h>
-#include <asm/iseries/hv_call_event.h>
-
-/*
- * HvLpEvent is the structure for Lp Event messages passed between
- * partitions through PLIC.
- */
-
-struct HvLpEvent {
-        u8      flags;                  /* Event flags                x00-x00 */
-        u8      xType;                  /* Type of message            x01-x01 */
-        u16     xSubtype;               /* Subtype for event          x02-x03 */
-        u8      xSourceLp;              /* Source LP                  x04-x04 */
-        u8      xTargetLp;              /* Target LP                  x05-x05 */
-        u8      xSizeMinus1;            /* Size of Derived class - 1  x06-x06 */
-        u8      xRc;                    /* RC for Ack flows           x07-x07 */
-        u16     xSourceInstanceId;      /* Source sides instance id   x08-x09 */
-        u16     xTargetInstanceId;      /* Target sides instance id   x0A-x0B */
-        union {
-                u32     xSubtypeData;   /* Data usable by the subtype x0C-x0F */
-                u16     xSubtypeDataShort[2];   /* Data as 2 shorts */
-                u8      xSubtypeDataChar[4];    /* Data as 4 chars */
-        } x;
-
-        u64     xCorrelationToken;      /* Unique value for source/type x10-x17 */
-};
-
-typedef void (*LpEventHandler)(struct HvLpEvent *);
-
-/* Register a handler for an event type - returns 0 on success */
-extern int HvLpEvent_registerHandler(HvLpEvent_Type eventType,
-                LpEventHandler hdlr);
-
-/*
- * Unregister a handler for an event type
- *
- * This call will sleep until the handler being removed is guaranteed to
- * be no longer executing on any CPU. Do not call with locks held.
- *
- *  returns 0 on success
- *  Unregister will fail if there are any paths open for the type
- */
-extern int HvLpEvent_unregisterHandler(HvLpEvent_Type eventType);
-
-/*
- * Open an Lp Event Path for an event type
- * returns 0 on success
- * openPath will fail if there is no handler registered for the event type.
- * The lpIndex specified is the partition index for the target partition
- * (for VirtualIo, VirtualLan and SessionMgr) other types specify zero)
- */
-extern int HvLpEvent_openPath(HvLpEvent_Type eventType, HvLpIndex lpIndex);
-
-/*
- * Close an Lp Event Path for a type and partition
- * returns 0 on success
- */
-extern int HvLpEvent_closePath(HvLpEvent_Type eventType, HvLpIndex lpIndex);
-
-#define HvLpEvent_Type_Hypervisor 0
-#define HvLpEvent_Type_MachineFac 1
-#define HvLpEvent_Type_SessionMgr 2
-#define HvLpEvent_Type_SpdIo      3
-#define HvLpEvent_Type_VirtualBus 4
-#define HvLpEvent_Type_PciIo      5
-#define HvLpEvent_Type_RioIo      6
-#define HvLpEvent_Type_VirtualLan 7
-#define HvLpEvent_Type_VirtualIo  8
-#define HvLpEvent_Type_NumTypes   9
-
-#define HvLpEvent_Rc_Good 0
-#define HvLpEvent_Rc_BufferNotAvailable 1
-#define HvLpEvent_Rc_Cancelled 2
-#define HvLpEvent_Rc_GenericError 3
-#define HvLpEvent_Rc_InvalidAddress 4
-#define HvLpEvent_Rc_InvalidPartition 5
-#define HvLpEvent_Rc_InvalidSize 6
-#define HvLpEvent_Rc_InvalidSubtype 7
-#define HvLpEvent_Rc_InvalidSubtypeData 8
-#define HvLpEvent_Rc_InvalidType 9
-#define HvLpEvent_Rc_PartitionDead 10
-#define HvLpEvent_Rc_PathClosed 11
-#define HvLpEvent_Rc_SubtypeError 12
-
-#define HvLpEvent_Function_Ack 0
-#define HvLpEvent_Function_Int 1
-
-#define HvLpEvent_AckInd_NoAck 0
-#define HvLpEvent_AckInd_DoAck 1
-
-#define HvLpEvent_AckType_ImmediateAck 0
-#define HvLpEvent_AckType_DeferredAck 1
-
-#define HV_LP_EVENT_INT                 0x01
-#define HV_LP_EVENT_DO_ACK              0x02
-#define HV_LP_EVENT_DEFERRED_ACK        0x04
-#define HV_LP_EVENT_VALID               0x80
-
-#define HvLpDma_Direction_LocalToRemote 0
-#define HvLpDma_Direction_RemoteToLocal 1
-
-#define HvLpDma_AddressType_TceIndex 0
-#define HvLpDma_AddressType_RealAddress 1
-
-#define HvLpDma_Rc_Good 0
-#define HvLpDma_Rc_Error 1
-#define HvLpDma_Rc_PartitionDead 2
-#define HvLpDma_Rc_PathClosed 3
-#define HvLpDma_Rc_InvalidAddress 4
-#define HvLpDma_Rc_InvalidLength 5
-
-static inline int hvlpevent_is_valid(struct HvLpEvent *h)
-{
-        return h->flags & HV_LP_EVENT_VALID;
-}
-
-static inline void hvlpevent_invalidate(struct HvLpEvent *h)
-{
-        h->flags &= ~ HV_LP_EVENT_VALID;
-}
-
-static inline int hvlpevent_is_int(struct HvLpEvent *h)
-{
-        return h->flags & HV_LP_EVENT_INT;
-}
-
-static inline int hvlpevent_is_ack(struct HvLpEvent *h)
-{
-        return !hvlpevent_is_int(h);
-}
-
-static inline int hvlpevent_need_ack(struct HvLpEvent *h)
-{
-        return h->flags & HV_LP_EVENT_DO_ACK;
-}
-
-#endif /* _ASM_POWERPC_ISERIES_HV_LP_EVENT_H */
diff --git a/arch/powerpc/include/asm/iseries/hv_types.h b/arch/powerpc/include/asm/iseries/hv_types.h
deleted file mode 100644
index c3e6d2a1d1c..00000000000
--- a/arch/powerpc/include/asm/iseries/hv_types.h
+++ /dev/null
@@ -1,112 +0,0 @@
-/*
- * Copyright (C) 2001  Mike Corrigan IBM Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
- */
-#ifndef _ASM_POWERPC_ISERIES_HV_TYPES_H
-#define _ASM_POWERPC_ISERIES_HV_TYPES_H
-
-/*
- * General typedefs for the hypervisor.
- */
-
-#include <asm/types.h>
-
-typedef u8      HvLpIndex;
-typedef u16     HvLpInstanceId;
-typedef u64     HvLpTOD;
-typedef u64     HvLpSystemSerialNum;
-typedef u8      HvLpDeviceSerialNum[12];
-typedef u16     HvLpSanHwSet;
-typedef u16     HvLpBus;
-typedef u16     HvLpBoard;
-typedef u16     HvLpCard;
-typedef u8      HvLpDeviceType[4];
-typedef u8      HvLpDeviceModel[3];
-typedef u64     HvIoToken;
-typedef u8      HvLpName[8];
-typedef u32     HvIoId;
-typedef u64     HvRealMemoryIndex;
-typedef u32     HvLpIndexMap;   /* Must hold HVMAXARCHITECTEDLPS bits!!! */
-typedef u16     HvLpVrmIndex;
-typedef u32     HvXmGenerationId;
-typedef u8      HvLpBusPool;
-typedef u8      HvLpSharedPoolIndex;
-typedef u16     HvLpSharedProcUnitsX100;
-typedef u8      HvLpVirtualLanIndex;
-typedef u16     HvLpVirtualLanIndexMap; /* Must hold HVMAXARCHITECTEDVIRTUALLANS bits!!! */
-typedef u16     HvBusNumber;    /* Hypervisor Bus Number */
-typedef u8      HvSubBusNumber; /* Hypervisor SubBus Number */
-typedef u8      HvAgentId;      /* Hypervisor DevFn */
-
-
-#define HVMAXARCHITECTEDLPS             32
-#define HVMAXARCHITECTEDVIRTUALLANS     16
-#define HVMAXARCHITECTEDVIRTUALDISKS    32
-#define HVMAXARCHITECTEDVIRTUALCDROMS   8
-#define HVMAXARCHITECTEDVIRTUALTAPES    8
-#define HVCHUNKSIZE                     (256 * 1024)
-#define HVPAGESIZE                      (4 * 1024)
-#define HVLPMINMEGSPRIMARY              256
-#define HVLPMINMEGSSECONDARY            64
-#define HVCHUNKSPERMEG                  4
-#define HVPAGESPERMEG                   256
-#define HVPAGESPERCHUNK                 64
-
-#define HvLpIndexInvalid                ((HvLpIndex)0xff)
-
-/*
- * Enums for the sub-components under PLIC
- * Used in HvCall  and HvPrimaryCall
- */
-enum {
-        HvCallCompId = 0,
-        HvCallCpuCtlsCompId = 1,
-        HvCallCfgCompId = 2,
-        HvCallEventCompId = 3,
-        HvCallHptCompId = 4,
-        HvCallPciCompId = 5,
-        HvCallSlmCompId = 6,
-        HvCallSmCompId = 7,
-        HvCallSpdCompId = 8,
-        HvCallXmCompId = 9,
-        HvCallRioCompId = 10,
-        HvCallRsvd3CompId = 11,
-        HvCallRsvd2CompId = 12,
-        HvCallRsvd1CompId = 13,
-        HvCallMaxCompId = 14,
-        HvPrimaryCallCompId = 0,
-        HvPrimaryCallCfgCompId = 1,
-        HvPrimaryCallPciCompId = 2,
-        HvPrimaryCallSmCompId = 3,
-        HvPrimaryCallSpdCompId = 4,
-        HvPrimaryCallXmCompId = 5,
-        HvPrimaryCallRioCompId = 6,
-        HvPrimaryCallRsvd7CompId = 7,
-        HvPrimaryCallRsvd6CompId = 8,
-        HvPrimaryCallRsvd5CompId = 9,
-        HvPrimaryCallRsvd4CompId = 10,
-        HvPrimaryCallRsvd3CompId = 11,
-        HvPrimaryCallRsvd2CompId = 12,
-        HvPrimaryCallRsvd1CompId = 13,
-        HvPrimaryCallMaxCompId = HvCallMaxCompId
-};
-
-struct HvLpBufferList {
-        u64 addr;
-        u64 len;
-};
-
-#endif /* _ASM_POWERPC_ISERIES_HV_TYPES_H */
diff --git a/arch/powerpc/include/asm/iseries/iommu.h b/arch/powerpc/include/asm/iseries/iommu.h
deleted file mode 100644
index 1b9692c6089..00000000000
--- a/arch/powerpc/include/asm/iseries/iommu.h
+++ /dev/null
@@ -1,37 +0,0 @@
-#ifndef _ASM_POWERPC_ISERIES_IOMMU_H
-#define _ASM_POWERPC_ISERIES_IOMMU_H
-
-/*
- * Copyright (C) 2005  Stephen Rothwell, IBM Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the:
- * Free Software Foundation, Inc.,
- * 59 Temple Place, Suite 330,
- * Boston, MA  02111-1307  USA
- */
-
-struct pci_dev;
-struct vio_dev;
-struct device_node;
-struct iommu_table;
-
-/* Get table parameters from HV */
-extern void iommu_table_getparms_iSeries(unsigned long busno,
-                unsigned char slotno, unsigned char virtbus,
-                struct iommu_table *tbl);
-
-extern struct iommu_table *vio_build_iommu_table_iseries(struct vio_dev *dev);
-extern void iommu_vio_init(void);
-
-#endif /* _ASM_POWERPC_ISERIES_IOMMU_H */
diff --git a/arch/powerpc/include/asm/iseries/it_lp_queue.h b/arch/powerpc/include/asm/iseries/it_lp_queue.h
deleted file mode 100644
index 42827883882..00000000000
--- a/arch/powerpc/include/asm/iseries/it_lp_queue.h
+++ /dev/null
@@ -1,78 +0,0 @@
-/*
- * Copyright (C) 2001  Mike Corrigan IBM Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
- */
-#ifndef _ASM_POWERPC_ISERIES_IT_LP_QUEUE_H
-#define _ASM_POWERPC_ISERIES_IT_LP_QUEUE_H
-
-/*
- *      This control block defines the simple LP queue structure that is
- *      shared between the hypervisor (PLIC) and the OS in order to send
- *      events to an LP.
- */
-
-#include <asm/types.h>
-#include <asm/ptrace.h>
-
-#define IT_LP_MAX_QUEUES        8
-
-#define IT_LP_NOT_USED          0       /* Queue will not be used by PLIC */
-#define IT_LP_DEDICATED_IO      1       /* Queue dedicated to IO processor specified */
-#define IT_LP_DEDICATED_LP      2       /* Queue dedicated to LP specified */
-#define IT_LP_SHARED            3       /* Queue shared for both IO and LP */
-
-#define IT_LP_EVENT_STACK_SIZE  4096
-#define IT_LP_EVENT_MAX_SIZE    256
-#define IT_LP_EVENT_ALIGN       64
-
-struct hvlpevent_queue {
-/*
- * The hq_current_event is the pointer to the next event stack entry
- * that will become valid.  The OS must peek at this entry to determine
- * if it is valid.  PLIC will set the valid indicator as the very last
- * store into that entry.
- *
- * When the OS has completed processing of the event then it will mark
- * the event as invalid so that PLIC knows it can store into that event
- * location again.
- *
- * If the event stack fills and there are overflow events, then PLIC
- * will set the hq_overflow_pending flag in which case the OS will
- * have to fetch the additional LP events once they have drained the
- * event stack.
- *
- * The first 16-bytes are known by both the OS and PLIC.  The remainder
- * of the cache line is for use by the OS.
- */
-        u8              hq_overflow_pending;    /* 0x00 Overflow events are pending */
-        u8              hq_status;              /* 0x01 DedicatedIo or DedicatedLp or NotUsed */
-        u16             hq_proc_index;          /* 0x02 Logical Proc Index for correlation */
-        u8              hq_reserved1[12];       /* 0x04 */
-        char            *hq_current_event;      /* 0x10 */
-        char            *hq_last_event;         /* 0x18 */
-        char            *hq_event_stack;        /* 0x20 */
-        u8              hq_index;               /* 0x28 unique sequential index. */
-        u8              hq_reserved2[3];        /* 0x29-2b */
-        spinlock_t      hq_lock;
-};
-
-extern struct hvlpevent_queue hvlpevent_queue;
-
-extern int hvlpevent_is_pending(void);
-extern void process_hvlpevents(void);
-extern void setup_hvlpevent_queue(void);
-
-#endif /* _ASM_POWERPC_ISERIES_IT_LP_QUEUE_H */
diff --git a/arch/powerpc/include/asm/iseries/lpar_map.h b/arch/powerpc/include/asm/iseries/lpar_map.h
deleted file mode 100644
index 5e9f3e128ee..00000000000
--- a/arch/powerpc/include/asm/iseries/lpar_map.h
+++ /dev/null
@@ -1,85 +0,0 @@
-/*
- * Copyright (C) 2001  Mike Corrigan IBM Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
- */
-#ifndef _ASM_POWERPC_ISERIES_LPAR_MAP_H
-#define _ASM_POWERPC_ISERIES_LPAR_MAP_H
-
-#ifndef __ASSEMBLY__
-
-#include <asm/types.h>
-
-#endif
-
-/*
- * The iSeries hypervisor will set up mapping for one or more
- * ESID/VSID pairs (in SLB/segment registers) and will set up
- * mappings of one or more ranges of pages to VAs.
- * We will have the hypervisor set up the ESID->VSID mapping
- * for the four kernel segments (C-F).  With shared processors,
- * the hypervisor will clear all segment registers and reload
- * these four whenever the processor is switched from one
- * partition to another.
- */
-
-/* The Vsid and Esid identified below will be used by the hypervisor
- * to set up a memory mapping for part of the load area before giving
- * control to the Linux kernel.  The load area is 64 MB, but this must
- * not attempt to map the whole load area.  The Hashed Page Table may
- * need to be located within the load area (if the total partition size
- * is 64 MB), but cannot be mapped.  Typically, this should specify
- * to map half (32 MB) of the load area.
- *
- * The hypervisor will set up page table entries for the number of
- * pages specified.
- *
- * In 32-bit mode, the hypervisor will load all four of the
- * segment registers (identified by the low-order four bits of the
- * Esid field.  In 64-bit mode, the hypervisor will load one SLB
- * entry to map the Esid to the Vsid.
-*/
-
-#define HvEsidsToMap    2
-#define HvRangesToMap   1
-
-/* Hypervisor initially maps 32MB of the load area */
-#define HvPagesToMap    8192
-
-#ifndef __ASSEMBLY__
-struct LparMap {
-        u64     xNumberEsids;   // Number of ESID/VSID pairs
-        u64     xNumberRanges;  // Number of VA ranges to map
-        u64     xSegmentTableOffs; // Page number within load area of seg table
-        u64     xRsvd[5];
-        struct {
-                u64     xKernelEsid;    // Esid used to map kernel load
-                u64     xKernelVsid;    // Vsid used to map kernel load
-        } xEsids[HvEsidsToMap];
-        struct {
-                u64     xPages;         // Number of pages to be mapped
-                u64     xOffset;        // Offset from start of load area
-                u64     xVPN;           // Virtual Page Number
-        } xRanges[HvRangesToMap];
-};
-
-extern const struct LparMap     xLparMap;
-
-#endif /* __ASSEMBLY__ */
-
-/* the fixed address where the LparMap exists */
-#define LPARMAP_PHYS            0x7000
-
-#endif /* _ASM_POWERPC_ISERIES_LPAR_MAP_H */
diff --git a/arch/powerpc/include/asm/iseries/mf.h b/arch/powerpc/include/asm/iseries/mf.h
deleted file mode 100644
index eb851a9c9e5..00000000000
--- a/arch/powerpc/include/asm/iseries/mf.h
+++ /dev/null
@@ -1,51 +0,0 @@
-/*
- * Copyright (C) 2001  Troy D. Armstrong IBM Corporation
- * Copyright (C) 2004  Stephen Rothwell IBM Corporation
- *
- * This modules exists as an interface between a Linux secondary partition
- * running on an iSeries and the primary partition's Virtual Service
- * Processor (VSP) object.  The VSP has final authority over powering on/off
- * all partitions in the iSeries.  It also provides miscellaneous low-level
- * machine facility type operations.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
- */
-#ifndef _ASM_POWERPC_ISERIES_MF_H
-#define _ASM_POWERPC_ISERIES_MF_H
-
-#include <linux/types.h>
-
-#include <asm/iseries/hv_types.h>
-#include <asm/iseries/hv_call_event.h>
-
-struct rtc_time;
-
-typedef void (*MFCompleteHandler)(void *clientToken, int returnCode);
-
-extern void mf_allocate_lp_events(HvLpIndex targetLp, HvLpEvent_Type type,
-                unsigned size, unsigned amount, MFCompleteHandler hdlr,
-                void *userToken);
-extern void mf_deallocate_lp_events(HvLpIndex targetLp, HvLpEvent_Type type,
-                unsigned count, MFCompleteHandler hdlr, void *userToken);
-
-extern void mf_power_off(void);
-extern void mf_reboot(char *cmd);
-
-extern void mf_display_src(u32 word);
-extern void mf_display_progress(u16 value);
-
-extern void mf_init(void);
-
-#endif /* _ASM_POWERPC_ISERIES_MF_H */
diff --git a/arch/powerpc/include/asm/iseries/vio.h b/arch/powerpc/include/asm/iseries/vio.h
deleted file mode 100644
index f9ac0d00b95..00000000000
--- a/arch/powerpc/include/asm/iseries/vio.h
+++ /dev/null
@@ -1,265 +0,0 @@
-/* -*- linux-c -*-
- *
- *  iSeries Virtual I/O Message Path header
- *
- *  Authors: Dave Boutcher <boutcher@us.ibm.com>
- *           Ryan Arnold <ryanarn@us.ibm.com>
- *           Colin Devilbiss <devilbis@us.ibm.com>
- *
- * (C) Copyright 2000 IBM Corporation
- *
- * This header file is used by the iSeries virtual I/O device
- * drivers.  It defines the interfaces to the common functions
- * (implemented in drivers/char/viopath.h) as well as defining
- * common functions and structures.  Currently (at the time I
- * wrote this comment) the iSeries virtual I/O device drivers
- * that use this are
- *   drivers/block/viodasd.c
- *   drivers/char/viocons.c
- *   drivers/char/viotape.c
- *   drivers/cdrom/viocd.c
- *
- * The iSeries virtual ethernet support (veth.c) uses a whole
- * different set of functions.
- *
- * This program is free software;  you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) anyu later version.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
- * General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software Foundation,
- * Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- */
-#ifndef _ASM_POWERPC_ISERIES_VIO_H
-#define _ASM_POWERPC_ISERIES_VIO_H
-
-#include <asm/iseries/hv_types.h>
-#include <asm/iseries/hv_lp_event.h>
-
-/*
- * iSeries virtual I/O events use the subtype field in
- * HvLpEvent to figure out what kind of vio event is coming
- * in.  We use a table to route these, and this defines
- * the maximum number of distinct subtypes
- */
-#define VIO_MAX_SUBTYPES 8
-
-#define VIOMAXBLOCKDMA  12
-
-struct open_data {
-        u64     disk_size;
-        u16     max_disk;
-        u16     cylinders;
-        u16     tracks;
-        u16     sectors;
-        u16     bytes_per_sector;
-};
-
-struct rw_data {
-        u64     offset;
-        struct {
-                u32     token;
-                u32     reserved;
-                u64     len;
-        } dma_info[VIOMAXBLOCKDMA];
-};
-
-struct vioblocklpevent {
-        struct HvLpEvent        event;
-        u32                     reserved;
-        u16                     version;
-        u16                     sub_result;
-        u16                     disk;
-        u16                     flags;
-        union {
-                struct open_data        open_data;
-                struct rw_data          rw_data;
-                u64                     changed;
-        } u;
-};
-
-#define vioblockflags_ro   0x0001
-
-enum vioblocksubtype {
-        vioblockopen = 0x0001,
-        vioblockclose = 0x0002,
-        vioblockread = 0x0003,
-        vioblockwrite = 0x0004,
-        vioblockflush = 0x0005,
-        vioblockcheck = 0x0007
-};
-
-struct viocdlpevent {
-        struct HvLpEvent        event;
-        u32                     reserved;
-        u16                     version;
-        u16                     sub_result;
-        u16                     disk;
-        u16                     flags;
-        u32                     token;
-        u64                     offset;         /* On open, max number of disks */
-        u64                     len;            /* On open, size of the disk */
-        u32                     block_size;     /* Only set on open */
-        u32                     media_size;     /* Only set on open */
-};
-
-enum viocdsubtype {
-        viocdopen = 0x0001,
-        viocdclose = 0x0002,
-        viocdread = 0x0003,
-        viocdwrite = 0x0004,
-        viocdlockdoor = 0x0005,
-        viocdgetinfo = 0x0006,
-        viocdcheck = 0x0007
-};
-
-struct viotapelpevent {
-        struct HvLpEvent event;
-        u32 reserved;
-        u16 version;
-        u16 sub_type_result;
-        u16 tape;
-        u16 flags;
-        u32 token;
-        u64 len;
-        union {
-                struct {
-                        u32 tape_op;
-                        u32 count;
-                } op;
-                struct {
-                        u32 type;
-                        u32 resid;
-                        u32 dsreg;
-                        u32 gstat;
-                        u32 erreg;
-                        u32 file_no;
-                        u32 block_no;
-                } get_status;
-                struct {
-                        u32 block_no;
-                } get_pos;
-        } u;
-};
-
-enum viotapesubtype {
-        viotapeopen = 0x0001,
-        viotapeclose = 0x0002,
-        viotaperead = 0x0003,
-        viotapewrite = 0x0004,
-        viotapegetinfo = 0x0005,
-        viotapeop = 0x0006,
-        viotapegetpos = 0x0007,
-        viotapesetpos = 0x0008,
-        viotapegetstatus = 0x0009
-};
-
-/*
- * Each subtype can register a handler to process their events.
- * The handler must have this interface.
- */
-typedef void (vio_event_handler_t) (struct HvLpEvent * event);
-
-extern int viopath_open(HvLpIndex remoteLp, int subtype, int numReq);
-extern int viopath_close(HvLpIndex remoteLp, int subtype, int numReq);
-extern int vio_setHandler(int subtype, vio_event_handler_t * beh);
-extern int vio_clearHandler(int subtype);
-extern int viopath_isactive(HvLpIndex lp);
-extern HvLpInstanceId viopath_sourceinst(HvLpIndex lp);
-extern HvLpInstanceId viopath_targetinst(HvLpIndex lp);
-extern void vio_set_hostlp(void);
-extern void *vio_get_event_buffer(int subtype);
-extern void vio_free_event_buffer(int subtype, void *buffer);
-
-extern struct vio_dev *vio_create_viodasd(u32 unit);
-
-extern HvLpIndex viopath_hostLp;
-extern HvLpIndex viopath_ourLp;
-
-#define VIOCHAR_MAX_DATA        200
-
-#define VIOMAJOR_SUBTYPE_MASK   0xff00
-#define VIOMINOR_SUBTYPE_MASK   0x00ff
-#define VIOMAJOR_SUBTYPE_SHIFT  8
-
-#define VIOVERSION              0x0101
-
-/*
- * This is the general structure for VIO errors; each module should have
- * a table of them, and each table should be terminated by an entry of
- * { 0, 0, NULL }.  Then, to find a specific error message, a module
- * should pass its local table and the return code.
- */
-struct vio_error_entry {
-        u16 rc;
-        int errno;
-        const char *msg;
-};
-extern const struct vio_error_entry *vio_lookup_rc(
-                const struct vio_error_entry *local_table, u16 rc);
-
-enum viosubtypes {
-        viomajorsubtype_monitor = 0x0100,
-        viomajorsubtype_blockio = 0x0200,
-        viomajorsubtype_chario = 0x0300,
-        viomajorsubtype_config = 0x0400,
-        viomajorsubtype_cdio = 0x0500,
-        viomajorsubtype_tape = 0x0600,
-        viomajorsubtype_scsi = 0x0700
-};
-
-enum vioconfigsubtype {
-        vioconfigget = 0x0001,
-};
-
-enum viorc {
-        viorc_good = 0x0000,
-        viorc_noConnection = 0x0001,
-        viorc_noReceiver = 0x0002,
-        viorc_noBufferAvailable = 0x0003,
-        viorc_invalidMessageType = 0x0004,
-        viorc_invalidRange = 0x0201,
-        viorc_invalidToken = 0x0202,
-        viorc_DMAError = 0x0203,
-        viorc_useError = 0x0204,
-        viorc_releaseError = 0x0205,
-        viorc_invalidDisk = 0x0206,
-        viorc_openRejected = 0x0301
-};
-
-/*
- * The structure of the events that flow between us and OS/400 for chario
- * events.  You can't mess with this unless the OS/400 side changes too.
- */
-struct viocharlpevent {
-        struct HvLpEvent event;
-        u32 reserved;
-        u16 version;
-        u16 subtype_result_code;
-        u8 virtual_device;
-        u8 len;
-        u8 data[VIOCHAR_MAX_DATA];
-};
-
-#define VIOCHAR_WINDOW          10
-
-enum viocharsubtype {
-        viocharopen = 0x0001,
-        viocharclose = 0x0002,
-        viochardata = 0x0003,
-        viocharack = 0x0004,
-        viocharconfig = 0x0005
-};
-
-enum viochar_rc {
-        viochar_rc_ebusy = 1
-};
-
-#endif /* _ASM_POWERPC_ISERIES_VIO_H */
diff --git a/arch/powerpc/include/asm/lppaca.h b/arch/powerpc/include/asm/lppaca.h
index e0298d26ce5..a76254af0aa 100644
--- a/arch/powerpc/include/asm/lppaca.h
+++ b/arch/powerpc/include/asm/lppaca.h
@@ -41,15 +41,7 @@
  * We only have to have statically allocated lppaca structs on
  * legacy iSeries, which supports at most 64 cpus.
  */
-#ifdef CONFIG_PPC_ISERIES
-#if NR_CPUS < 64
-#define NR_LPPACAS      NR_CPUS
-#else
-#define NR_LPPACAS      64
-#endif
-#else /* not iSeries */
 #define NR_LPPACAS      1
-#endif
 
 
 /* The Hypervisor barfs if the lppaca crosses a page boundary.  A 1k
diff --git a/arch/powerpc/include/asm/mpic.h b/arch/powerpc/include/asm/mpic.h
index a5b7c56237f..c65b9294376 100644
--- a/arch/powerpc/include/asm/mpic.h
+++ b/arch/powerpc/include/asm/mpic.h
@@ -273,7 +273,6 @@ struct mpic
         unsigned int            isu_size;
         unsigned int            isu_shift;
         unsigned int            isu_mask;
-        unsigned int            irq_count;
         /* Number of sources */
         unsigned int            num_sources;
         /* default senses array */
@@ -349,8 +348,6 @@ struct mpic
 #define MPIC_U3_HT_IRQS                 0x00000004
 /* Broken IPI registers (autodetected) */
 #define MPIC_BROKEN_IPI                 0x00000008
-/* MPIC wants a reset */
-#define MPIC_WANTS_RESET                0x00000010
 /* Spurious vector requires EOI */
 #define MPIC_SPV_EOI                    0x00000020
 /* No passthrough disable */
@@ -363,15 +360,11 @@ struct mpic
 #define MPIC_ENABLE_MCK                 0x00000200
 /* Disable bias among target selection, spread interrupts evenly */
 #define MPIC_NO_BIAS                    0x00000400
-/* Ignore NIRQS as reported by FRR */
-#define MPIC_BROKEN_FRR_NIRQS           0x00000800
 /* Destination only supports a single CPU at a time */
 #define MPIC_SINGLE_DEST_CPU            0x00001000
 /* Enable CoreInt delivery of interrupts */
 #define MPIC_ENABLE_COREINT             0x00002000
-/* Disable resetting of the MPIC.
- * NOTE: This flag trumps MPIC_WANTS_RESET.
- */
+/* Do not reset the MPIC during initialization */
 #define MPIC_NO_RESET                   0x00004000
 /* Freescale MPIC (compatible includes "fsl,mpic") */
 #define MPIC_FSL                        0x00008000
diff --git a/arch/powerpc/include/asm/mpic_msgr.h b/arch/powerpc/include/asm/mpic_msgr.h
new file mode 100644
index 00000000000..3ec37dc9003
--- /dev/null
+++ b/arch/powerpc/include/asm/mpic_msgr.h
@@ -0,0 +1,132 @@
+/*
+ * Copyright 2011-2012, Meador Inge, Mentor Graphics Corporation.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; version 2 of the
+ * License.
+ *
+ */
+
+#ifndef _ASM_MPIC_MSGR_H
+#define _ASM_MPIC_MSGR_H
+
+#include <linux/types.h>
+#include <linux/spinlock.h>
+
+struct mpic_msgr {
+        u32 __iomem *base;
+        u32 __iomem *mer;
+        int irq;
+        unsigned char in_use;
+        raw_spinlock_t lock;
+        int num;
+};
+
+/* Get a message register
+ *
+ * @reg_num:    the MPIC message register to get
+ *
+ * A pointer to the message register is returned.  If
+ * the message register asked for is already in use, then
+ * EBUSY is returned.  If the number given is not associated
+ * with an actual message register, then ENODEV is returned.
+ * Successfully getting the register marks it as in use.
+ */
+extern struct mpic_msgr *mpic_msgr_get(unsigned int reg_num);
+
+/* Relinquish a message register
+ *
+ * @msgr:       the message register to return
+ *
+ * Disables the given message register and marks it as free.
+ * After this call has completed successully the message
+ * register is available to be acquired by a call to
+ * mpic_msgr_get.
+ */
+extern void mpic_msgr_put(struct mpic_msgr *msgr);
+
+/* Enable a message register
+ *
+ * @msgr:       the message register to enable
+ *
+ * The given message register is enabled for sending
+ * messages.
+ */
+extern void mpic_msgr_enable(struct mpic_msgr *msgr);
+
+/* Disable a message register
+ *
+ * @msgr:       the message register to disable
+ *
+ * The given message register is disabled for sending
+ * messages.
+ */
+extern void mpic_msgr_disable(struct mpic_msgr *msgr);
+
+/* Write a message to a message register
+ *
+ * @msgr:       the message register to write to
+ * @message:    the message to write
+ *
+ * The given 32-bit message is written to the given message
+ * register.  Writing to an enabled message registers fires
+ * an interrupt.
+ */
+static inline void mpic_msgr_write(struct mpic_msgr *msgr, u32 message)
+{
+        out_be32(msgr->base, message);
+}
+
+/* Read a message from a message register
+ *
+ * @msgr:       the message register to read from
+ *
+ * Returns the 32-bit value currently in the given message register.
+ * Upon reading the register any interrupts for that register are
+ * cleared.
+ */
+static inline u32 mpic_msgr_read(struct mpic_msgr *msgr)
+{
+        return in_be32(msgr->base);
+}
+
+/* Clear a message register
+ *
+ * @msgr:       the message register to clear
+ *
+ * Clears any interrupts associated with the given message register.
+ */
+static inline void mpic_msgr_clear(struct mpic_msgr *msgr)
+{
+        (void) mpic_msgr_read(msgr);
+}
+
+/* Set the destination CPU for the message register
+ *
+ * @msgr:       the message register whose destination is to be set
+ * @cpu_num:    the Linux CPU number to bind the message register to
+ *
+ * Note that the CPU number given is the CPU number used by the kernel
+ * and *not* the actual hardware CPU number.
+ */
+static inline void mpic_msgr_set_destination(struct mpic_msgr *msgr,
+                                             u32 cpu_num)
+{
+        out_be32(msgr->base, 1 << get_hard_smp_processor_id(cpu_num));
+}
+
+/* Get the IRQ number for the message register
+ * @msgr:       the message register whose IRQ is to be returned
+ *
+ * Returns the IRQ number associated with the given message register.
+ * NO_IRQ is returned if this message register is not capable of
+ * receiving interrupts.  What message register can and cannot receive
+ * interrupts is specified in the device tree for the system.
+ */
+static inline int mpic_msgr_get_irq(struct mpic_msgr *msgr)
+{
+        return msgr->irq;
+}
+
+#endif
diff --git a/arch/powerpc/include/asm/paca.h b/arch/powerpc/include/asm/paca.h
index 269c05a36d9..daf813fea91 100644
--- a/arch/powerpc/include/asm/paca.h
+++ b/arch/powerpc/include/asm/paca.h
@@ -132,7 +132,7 @@ struct paca_struct {
         u64 saved_msr;                  /* MSR saved here by enter_rtas */
         u16 trap_save;                  /* Used when bad stack is encountered */
         u8 soft_enabled;                /* irq soft-enable flag */
-        u8 hard_enabled;                /* set if irqs are enabled in MSR */
+        u8 irq_happened;                /* irq happened while soft-disabled */
         u8 io_sync;                     /* writel() needs spin_unlock sync */
         u8 irq_work_pending;            /* IRQ_WORK interrupt while soft-disable */
         u8 nap_state_lost;              /* NV GPR values lost in power7_idle */
diff --git a/arch/powerpc/include/asm/pci.h b/arch/powerpc/include/asm/pci.h
index f54b3d26ce9..6653f2743c4 100644
--- a/arch/powerpc/include/asm/pci.h
+++ b/arch/powerpc/include/asm/pci.h
@@ -154,14 +154,6 @@ extern int pci_mmap_legacy_page_range(struct pci_bus *bus,
 
 #endif /* CONFIG_PPC64 */
 
-extern void pcibios_resource_to_bus(struct pci_dev *dev,
-                        struct pci_bus_region *region,
-                        struct resource *res);
-
-extern void pcibios_bus_to_resource(struct pci_dev *dev,
-                        struct resource *res,
-                        struct pci_bus_region *region);
-
 extern void pcibios_claim_one_bus(struct pci_bus *b);
 
 extern void pcibios_finish_adding_to_bus(struct pci_bus *bus);
@@ -190,6 +182,7 @@ extern void pci_resource_to_user(const struct pci_dev *dev, int bar,
                                  const struct resource *rsrc,
                                  resource_size_t *start, resource_size_t *end);
 
+extern resource_size_t pcibios_io_space_offset(struct pci_controller *hose);
 extern void pcibios_setup_bus_devices(struct pci_bus *bus);
 extern void pcibios_setup_bus_self(struct pci_bus *bus);
 extern void pcibios_setup_phb_io_space(struct pci_controller *hose);
diff --git a/arch/powerpc/include/asm/phyp_dump.h b/arch/powerpc/include/asm/phyp_dump.h
deleted file mode 100644
index fa74c6c3e10..00000000000
--- a/arch/powerpc/include/asm/phyp_dump.h
+++ /dev/null
@@ -1,47 +0,0 @@
-/*
- * Hypervisor-assisted dump
- *
- * Linas Vepstas, Manish Ahuja 2008
- * Copyright 2008 IBM Corp.
- *
- *      This program is free software; you can redistribute it and/or
- *      modify it under the terms of the GNU General Public License
- *      as published by the Free Software Foundation; either version
- *      2 of the License, or (at your option) any later version.
- */
-
-#ifndef _PPC64_PHYP_DUMP_H
-#define _PPC64_PHYP_DUMP_H
-
-#ifdef CONFIG_PHYP_DUMP
-
-/* The RMR region will be saved for later dumping
- * whenever the kernel crashes. Set this to 256MB. */
-#define PHYP_DUMP_RMR_START 0x0
-#define PHYP_DUMP_RMR_END   (1UL<<28)
-
-struct phyp_dump {
-        /* Memory that is reserved during very early boot. */
-        unsigned long init_reserve_start;
-        unsigned long init_reserve_size;
-        /* cmd line options during boot */
-        unsigned long reserve_bootvar;
-        unsigned long phyp_dump_at_boot;
-        /* Check status during boot if dump supported, active & present*/
-        unsigned long phyp_dump_configured;
-        unsigned long phyp_dump_is_active;
-        /* store cpu & hpte size */
-        unsigned long cpu_state_size;
-        unsigned long hpte_region_size;
-        /* previous scratch area values */
-        unsigned long reserved_scratch_addr;
-        unsigned long reserved_scratch_size;
-};
-
-extern struct phyp_dump *phyp_dump_info;
-
-int early_init_dt_scan_phyp_dump(unsigned long node,
-                const char *uname, int depth, void *data);
-
-#endif /* CONFIG_PHYP_DUMP */
-#endif /* _PPC64_PHYP_DUMP_H */
diff --git a/arch/powerpc/include/asm/ppc-pci.h b/arch/powerpc/include/asm/ppc-pci.h
index 6d422979eba..80fa704d410 100644
--- a/arch/powerpc/include/asm/ppc-pci.h
+++ b/arch/powerpc/include/asm/ppc-pci.h
@@ -45,94 +45,21 @@ extern void init_pci_config_tokens (void);
 extern unsigned long get_phb_buid (struct device_node *);
 extern int rtas_setup_phb(struct pci_controller *phb);
 
-extern unsigned long pci_probe_only;
-
-/* ---- EEH internal-use-only related routines ---- */
 #ifdef CONFIG_EEH
 
+void pci_addr_cache_build(void);
 void pci_addr_cache_insert_device(struct pci_dev *dev);
 void pci_addr_cache_remove_device(struct pci_dev *dev);
-void pci_addr_cache_build(void);
-struct pci_dev *pci_get_device_by_addr(unsigned long addr);
-
-/**
- * eeh_slot_error_detail -- record and EEH error condition to the log
- * @pdn:      pci device node
- * @severity: EEH_LOG_TEMP_FAILURE or EEH_LOG_PERM_FAILURE
- *
- * Obtains the EEH error details from the RTAS subsystem,
- * and then logs these details with the RTAS error log system.
- */
-#define EEH_LOG_TEMP_FAILURE 1
-#define EEH_LOG_PERM_FAILURE 2
-void eeh_slot_error_detail (struct pci_dn *pdn, int severity);
-
-/**
- * rtas_pci_enable - enable IO transfers for this slot
- * @pdn:       pci device node
- * @function:  either EEH_THAW_MMIO or EEH_THAW_DMA 
- *
- * Enable I/O transfers to this slot 
- */
-#define EEH_THAW_MMIO 2
-#define EEH_THAW_DMA  3
-int rtas_pci_enable(struct pci_dn *pdn, int function);
-
-/**
- * rtas_set_slot_reset -- unfreeze a frozen slot
- * @pdn:       pci device node
- *
- * Clear the EEH-frozen condition on a slot.  This routine
- * does this by asserting the PCI #RST line for 1/8th of
- * a second; this routine will sleep while the adapter is
- * being reset.
- *
- * Returns a non-zero value if the reset failed.
- */
-int rtas_set_slot_reset (struct pci_dn *);
-int eeh_wait_for_slot_status(struct pci_dn *pdn, int max_wait_msecs);
-
-/** 
- * eeh_restore_bars - Restore device configuration info.
- * @pdn:       pci device node
- *
- * A reset of a PCI device will clear out its config space.
- * This routines will restore the config space for this
- * device, and is children, to values previously obtained
- * from the firmware.
- */
-void eeh_restore_bars(struct pci_dn *);
-
-/**
- * rtas_configure_bridge -- firmware initialization of pci bridge
- * @pdn:       pci device node
- *
- * Ask the firmware to configure all PCI bridges devices
- * located behind the indicated node. Required after a
- * pci device reset. Does essentially the same hing as
- * eeh_restore_bars, but for brdges, and lets firmware 
- * do the work.
- */
-void rtas_configure_bridge(struct pci_dn *);
-
+struct pci_dev *pci_addr_cache_get_device(unsigned long addr);
+void eeh_slot_error_detail(struct eeh_dev *edev, int severity);
+int eeh_pci_enable(struct eeh_dev *edev, int function);
+int eeh_reset_pe(struct eeh_dev *);
+void eeh_restore_bars(struct eeh_dev *);
 int rtas_write_config(struct pci_dn *, int where, int size, u32 val);
 int rtas_read_config(struct pci_dn *, int where, int size, u32 *val);
-
-/**
- * eeh_mark_slot -- set mode flags for pertition endpoint
- * @pdn:       pci device node
- *
- * mark and clear slots: find "partition endpoint" PE and set or 
- * clear the flags for each subnode of the PE.
- */
-void eeh_mark_slot (struct device_node *dn, int mode_flag);
-void eeh_clear_slot (struct device_node *dn, int mode_flag);
-
-/**
- * find_device_pe -- Find the associated "Partiationable Endpoint" PE
- * @pdn:       pci device node
- */
-struct device_node * find_device_pe(struct device_node *dn);
+void eeh_mark_slot(struct device_node *dn, int mode_flag);
+void eeh_clear_slot(struct device_node *dn, int mode_flag);
+struct device_node *eeh_find_device_pe(struct device_node *dn);
 
 void eeh_sysfs_add_device(struct pci_dev *pdev);
 void eeh_sysfs_remove_device(struct pci_dev *pdev);
diff --git a/arch/powerpc/include/asm/ppc_asm.h b/arch/powerpc/include/asm/ppc_asm.h
index 368f72f7980..50f73aa2ba2 100644
--- a/arch/powerpc/include/asm/ppc_asm.h
+++ b/arch/powerpc/include/asm/ppc_asm.h
@@ -60,6 +60,8 @@ BEGIN_FW_FTR_SECTION;							\
         cmpd    cr1,r11,r10;                                            \
         beq+    cr1,33f;                                                \
         bl      .accumulate_stolen_time;                                \
+        ld      r12,_MSR(r1);                                           \
+        andi.   r10,r12,MSR_PR;         /* Restore cr0 (coming from user) */ \
 33:                                                                     \
 END_FW_FTR_SECTION_IFSET(FW_FEATURE_SPLPAR)
 
diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h
index 7fdc2c0b7fa..b1a215eabef 100644
--- a/arch/powerpc/include/asm/reg.h
+++ b/arch/powerpc/include/asm/reg.h
@@ -1079,30 +1079,12 @@
 
 #define proc_trap()     asm volatile("trap")
 
-#ifdef CONFIG_PPC64
-
-extern void ppc64_runlatch_on(void);
-extern void __ppc64_runlatch_off(void);
-
-#define ppc64_runlatch_off()                                    \
-        do {                                                    \
-                if (cpu_has_feature(CPU_FTR_CTRL) &&            \
-                    test_thread_flag(TIF_RUNLATCH))             \
-                        __ppc64_runlatch_off();                 \
-        } while (0)
+#define __get_SP()      ({unsigned long sp; \
+                        asm volatile("mr %0,1": "=r" (sp)); sp;})
 
 extern unsigned long scom970_read(unsigned int address);
 extern void scom970_write(unsigned int address, unsigned long value);
 
-#else
-#define ppc64_runlatch_on()
-#define ppc64_runlatch_off()
-
-#endif /* CONFIG_PPC64 */
-
-#define __get_SP()      ({unsigned long sp; \
-                        asm volatile("mr %0,1": "=r" (sp)); sp;})
-
 struct pt_regs;
 
 extern void ppc_save_regs(struct pt_regs *regs);
diff --git a/arch/powerpc/include/asm/reg_booke.h b/arch/powerpc/include/asm/reg_booke.h
index 500fe1dc43e..8a97aa7289d 100644
--- a/arch/powerpc/include/asm/reg_booke.h
+++ b/arch/powerpc/include/asm/reg_booke.h
@@ -62,6 +62,7 @@
 #define SPRN_DVC2       0x13F   /* Data Value Compare Register 2 */
 #define SPRN_MAS8       0x155   /* MMU Assist Register 8 */
 #define SPRN_TLB0PS     0x158   /* TLB 0 Page Size Register */
+#define SPRN_TLB1PS     0x159   /* TLB 1 Page Size Register */
 #define SPRN_MAS5_MAS6  0x15c   /* MMU Assist Register 5 || 6 */
 #define SPRN_MAS8_MAS1  0x15d   /* MMU Assist Register 8 || 1 */
 #define SPRN_EPTCFG     0x15e   /* Embedded Page Table Config */
diff --git a/arch/powerpc/include/asm/spinlock.h b/arch/powerpc/include/asm/spinlock.h
index f9611bd69ed..7124fc06ad4 100644
--- a/arch/powerpc/include/asm/spinlock.h
+++ b/arch/powerpc/include/asm/spinlock.h
@@ -23,7 +23,6 @@
 #ifdef CONFIG_PPC64
 #include <asm/paca.h>
 #include <asm/hvcall.h>
-#include <asm/iseries/hv_call.h>
 #endif
 #include <asm/asm-compat.h>
 #include <asm/synch.h>
@@ -95,12 +94,12 @@ static inline int arch_spin_trylock(arch_spinlock_t *lock)
  * value.
  */
 
-#if defined(CONFIG_PPC_SPLPAR) || defined(CONFIG_PPC_ISERIES)
+#if defined(CONFIG_PPC_SPLPAR)
 /* We only yield to the hypervisor if we are in shared processor mode */
 #define SHARED_PROCESSOR (get_lppaca()->shared_proc)
 extern void __spin_yield(arch_spinlock_t *lock);
 extern void __rw_yield(arch_rwlock_t *lock);
-#else /* SPLPAR || ISERIES */
+#else /* SPLPAR */
 #define __spin_yield(x) barrier()
 #define __rw_yield(x)   barrier()
 #define SHARED_PROCESSOR        0
diff --git a/arch/powerpc/include/asm/system.h b/arch/powerpc/include/asm/system.h
index c377457d1b8..a02883d5af4 100644
--- a/arch/powerpc/include/asm/system.h
+++ b/arch/powerpc/include/asm/system.h
@@ -550,5 +550,43 @@ extern void reloc_got2(unsigned long);
 
 extern struct dentry *powerpc_debugfs_root;
 
+#ifdef CONFIG_PPC64
+
+extern void __ppc64_runlatch_on(void);
+extern void __ppc64_runlatch_off(void);
+
+/*
+ * We manually hard enable-disable, this is called
+ * in the idle loop and we don't want to mess up
+ * with soft-disable/enable & interrupt replay.
+ */
+#define ppc64_runlatch_off()                                    \
+        do {                                                    \
+                if (cpu_has_feature(CPU_FTR_CTRL) &&            \
+                    test_thread_local_flags(_TLF_RUNLATCH)) {   \
+                        unsigned long msr = mfmsr();            \
+                        __hard_irq_disable();                   \
+                        __ppc64_runlatch_off();                 \
+                        if (msr & MSR_EE)                       \
+                                __hard_irq_enable();            \
+                }                                               \
+        } while (0)
+
+#define ppc64_runlatch_on()                                     \
+        do {                                                    \
+                if (cpu_has_feature(CPU_FTR_CTRL) &&            \
+                    !test_thread_local_flags(_TLF_RUNLATCH)) {  \
+                        unsigned long msr = mfmsr();            \
+                        __hard_irq_disable();                   \
+                        __ppc64_runlatch_on();                  \
+                        if (msr & MSR_EE)                       \
+                                __hard_irq_enable();            \
+                }                                               \
+        } while (0)
+#else
+#define ppc64_runlatch_on()
+#define ppc64_runlatch_off()
+#endif /* CONFIG_PPC64 */
+
 #endif /* __KERNEL__ */
 #endif /* _ASM_POWERPC_SYSTEM_H */
diff --git a/arch/powerpc/include/asm/thread_info.h b/arch/powerpc/include/asm/thread_info.h
index 96471494096..4a741c7efd0 100644
--- a/arch/powerpc/include/asm/thread_info.h
+++ b/arch/powerpc/include/asm/thread_info.h
@@ -110,7 +110,6 @@ static inline struct thread_info *current_thread_info(void)
 #define TIF_NOERROR             12      /* Force successful syscall return */
 #define TIF_NOTIFY_RESUME       13      /* callback before returning to user */
 #define TIF_SYSCALL_TRACEPOINT  15      /* syscall tracepoint instrumentation */
-#define TIF_RUNLATCH            16      /* Is the runlatch enabled? */
 
 /* as above, but as bit values */
 #define _TIF_SYSCALL_TRACE      (1<<TIF_SYSCALL_TRACE)
@@ -141,11 +140,13 @@ static inline struct thread_info *current_thread_info(void)
 #define TLF_SLEEPING            1       /* suspend code enabled SLEEP mode */
 #define TLF_RESTORE_SIGMASK     2       /* Restore signal mask in do_signal */
 #define TLF_LAZY_MMU            3       /* tlb_batch is active */
+#define TLF_RUNLATCH            4       /* Is the runlatch enabled? */
 
 #define _TLF_NAPPING            (1 << TLF_NAPPING)
 #define _TLF_SLEEPING           (1 << TLF_SLEEPING)
 #define _TLF_RESTORE_SIGMASK    (1 << TLF_RESTORE_SIGMASK)
 #define _TLF_LAZY_MMU           (1 << TLF_LAZY_MMU)
+#define _TLF_RUNLATCH           (1 << TLF_RUNLATCH)
 
 #ifndef __ASSEMBLY__
 #define HAVE_SET_RESTORE_SIGMASK        1
@@ -156,6 +157,12 @@ static inline void set_restore_sigmask(void)
         set_bit(TIF_SIGPENDING, &ti->flags);
 }
 
+static inline bool test_thread_local_flags(unsigned int flags)
+{
+        struct thread_info *ti = current_thread_info();
+        return (ti->local_flags & flags) != 0;
+}
+
 #ifdef CONFIG_PPC64
 #define is_32bit_task() (test_thread_flag(TIF_32BIT))
 #else
diff --git a/arch/powerpc/include/asm/time.h b/arch/powerpc/include/asm/time.h
index 7eb10fb96cd..2136f58a54e 100644
--- a/arch/powerpc/include/asm/time.h
+++ b/arch/powerpc/include/asm/time.h
@@ -18,11 +18,6 @@
 #include <linux/percpu.h>
 
 #include <asm/processor.h>
-#ifdef CONFIG_PPC_ISERIES
-#include <asm/paca.h>
-#include <asm/firmware.h>
-#include <asm/iseries/hv_call.h>
-#endif
 
 /* time.c */
 extern unsigned long tb_ticks_per_jiffy;
@@ -167,15 +162,6 @@ static inline void set_dec(int val)
 #ifndef CONFIG_BOOKE
         --val;
 #endif
-#ifdef CONFIG_PPC_ISERIES
-        if (firmware_has_feature(FW_FEATURE_ISERIES) &&
-                        get_lppaca()->shared_proc) {
-                get_lppaca()->virtual_decr = val;
-                if (get_dec() > val)
-                        HvCall_setVirtualDecr();
-                return;
-        }
-#endif
         mtspr(SPRN_DEC, val);
 #endif /* not 40x or 8xx_CPU6 */
 }
@@ -217,7 +203,6 @@ DECLARE_PER_CPU(struct cpu_usage, cpu_usage_array);
 #endif
 
 extern void secondary_cpu_time_init(void);
-extern void iSeries_time_init_early(void);
 
 DECLARE_PER_CPU(u64, decrementers_next_tb);
 
diff --git a/arch/powerpc/kernel/Makefile b/arch/powerpc/kernel/Makefile
index ee728e433aa..f5808a35688 100644
--- a/arch/powerpc/kernel/Makefile
+++ b/arch/powerpc/kernel/Makefile
@@ -60,6 +60,7 @@ obj-$(CONFIG_IBMVIO)		+= vio.o
 obj-$(CONFIG_IBMEBUS)           += ibmebus.o
 obj-$(CONFIG_GENERIC_TBSYNC)    += smp-tbsync.o
 obj-$(CONFIG_CRASH_DUMP)        += crash_dump.o
+obj-$(CONFIG_FA_DUMP)           += fadump.o
 ifeq ($(CONFIG_PPC32),y)
 obj-$(CONFIG_E500)              += idle_e500.o
 endif
@@ -113,15 +114,6 @@ obj-$(CONFIG_PPC_IO_WORKAROUNDS)	+= io-workarounds.o
 obj-$(CONFIG_DYNAMIC_FTRACE)    += ftrace.o
 obj-$(CONFIG_FUNCTION_GRAPH_TRACER)     += ftrace.o
 obj-$(CONFIG_FTRACE_SYSCALLS)   += ftrace.o
-obj-$(CONFIG_PERF_EVENTS)       += perf_callchain.o
-
-obj-$(CONFIG_PPC_PERF_CTRS)     += perf_event.o
-obj64-$(CONFIG_PPC_PERF_CTRS)   += power4-pmu.o ppc970-pmu.o power5-pmu.o \
-                                   power5+-pmu.o power6-pmu.o power7-pmu.o
-obj32-$(CONFIG_PPC_PERF_CTRS)   += mpc7450-pmu.o
-
-obj-$(CONFIG_FSL_EMB_PERF_EVENT) += perf_event_fsl_emb.o
-obj-$(CONFIG_FSL_EMB_PERF_EVENT_E500) += e500-pmu.o
 
 obj-$(CONFIG_8XX_MINIMAL_FPEMU) += softemu8xx.o
 
diff --git a/arch/powerpc/kernel/asm-offsets.c b/arch/powerpc/kernel/asm-offsets.c
index 04caee7d9bc..cc492e48ddf 100644
--- a/arch/powerpc/kernel/asm-offsets.c
+++ b/arch/powerpc/kernel/asm-offsets.c
@@ -46,9 +46,6 @@
 #include <asm/hvcall.h>
 #include <asm/xics.h>
 #endif
-#ifdef CONFIG_PPC_ISERIES
-#include <asm/iseries/alpaca.h>
-#endif
 #ifdef CONFIG_PPC_POWERNV
 #include <asm/opal.h>
 #endif
@@ -147,7 +144,7 @@ int main(void)
         DEFINE(PACAKBASE, offsetof(struct paca_struct, kernelbase));
         DEFINE(PACAKMSR, offsetof(struct paca_struct, kernel_msr));
         DEFINE(PACASOFTIRQEN, offsetof(struct paca_struct, soft_enabled));
-        DEFINE(PACAHARDIRQEN, offsetof(struct paca_struct, hard_enabled));
+        DEFINE(PACAIRQHAPPENED, offsetof(struct paca_struct, irq_happened));
         DEFINE(PACACONTEXTID, offsetof(struct paca_struct, context.id));
 #ifdef CONFIG_PPC_MM_SLICES
         DEFINE(PACALOWSLICESPSIZE, offsetof(struct paca_struct,
@@ -384,17 +381,6 @@ int main(void)
         DEFINE(BUG_ENTRY_SIZE, sizeof(struct bug_entry));
 #endif
 
-#ifdef CONFIG_PPC_ISERIES
-        /* the assembler miscalculates the VSID values */
-        DEFINE(PAGE_OFFSET_ESID, GET_ESID(PAGE_OFFSET));
-        DEFINE(PAGE_OFFSET_VSID, KERNEL_VSID(PAGE_OFFSET));
-        DEFINE(VMALLOC_START_ESID, GET_ESID(VMALLOC_START));
-        DEFINE(VMALLOC_START_VSID, KERNEL_VSID(VMALLOC_START));
-
-        /* alpaca */
-        DEFINE(ALPACA_SIZE, sizeof(struct alpaca));
-#endif
-
         DEFINE(PGD_TABLE_SIZE, PGD_TABLE_SIZE);
         DEFINE(PTE_SIZE, sizeof(pte_t));
 
diff --git a/arch/powerpc/kernel/cputable.c b/arch/powerpc/kernel/cputable.c
index 81db9e2a8a2..138ae183c44 100644
--- a/arch/powerpc/kernel/cputable.c
+++ b/arch/powerpc/kernel/cputable.c
@@ -1816,7 +1816,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
                 .platform               = "ppc440",
         },
         { /* 464 in APM821xx */
-                .pvr_mask               = 0xffffff00,
+                .pvr_mask               = 0xfffffff0,
                 .pvr_value              = 0x12C41C80,
                 .cpu_name               = "APM821XX",
                 .cpu_features           = CPU_FTRS_44X,
@@ -2019,6 +2019,24 @@ static struct cpu_spec __initdata cpu_specs[] = {
                 .machine_check          = machine_check_e500mc,
                 .platform               = "ppce5500",
         },
+        {       /* e6500 */
+                .pvr_mask               = 0xffff0000,
+                .pvr_value              = 0x80400000,
+                .cpu_name               = "e6500",
+                .cpu_features           = CPU_FTRS_E6500,
+                .cpu_user_features      = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU,
+                .mmu_features           = MMU_FTR_TYPE_FSL_E | MMU_FTR_BIG_PHYS |
+                        MMU_FTR_USE_TLBILX,
+                .icache_bsize           = 64,
+                .dcache_bsize           = 64,
+                .num_pmcs               = 4,
+                .oprofile_cpu_type      = "ppc/e6500",
+                .oprofile_type          = PPC_OPROFILE_FSL_EMB,
+                .cpu_setup              = __setup_cpu_e5500,
+                .cpu_restore            = __restore_cpu_e5500,
+                .machine_check          = machine_check_e500mc,
+                .platform               = "ppce6500",
+        },
 #ifdef CONFIG_PPC32
         {       /* default match */
                 .pvr_mask               = 0x00000000,
diff --git a/arch/powerpc/kernel/dbell.c b/arch/powerpc/kernel/dbell.c
index 2cc451aaaca..5b25c8060fd 100644
--- a/arch/powerpc/kernel/dbell.c
+++ b/arch/powerpc/kernel/dbell.c
@@ -37,6 +37,8 @@ void doorbell_exception(struct pt_regs *regs)
 
         irq_enter();
 
+        may_hard_irq_enable();
+
         smp_ipi_demux();
 
         irq_exit();
diff --git a/arch/powerpc/kernel/entry_64.S b/arch/powerpc/kernel/entry_64.S
index 866462cbe2d..f8a7a1a1a9f 100644
--- a/arch/powerpc/kernel/entry_64.S
+++ b/arch/powerpc/kernel/entry_64.S
@@ -32,6 +32,7 @@
 #include <asm/ptrace.h>
 #include <asm/irqflags.h>
 #include <asm/ftrace.h>
+#include <asm/hw_irq.h>
 
 /*
  * System calls.
@@ -115,39 +116,33 @@ BEGIN_FW_FTR_SECTION
 END_FW_FTR_SECTION_IFSET(FW_FEATURE_SPLPAR)
 #endif /* CONFIG_VIRT_CPU_ACCOUNTING && CONFIG_PPC_SPLPAR */
 
-#ifdef CONFIG_TRACE_IRQFLAGS
-        bl      .trace_hardirqs_on
-        REST_GPR(0,r1)
-        REST_4GPRS(3,r1)
-        REST_2GPRS(7,r1)
-        addi    r9,r1,STACK_FRAME_OVERHEAD
-        ld      r12,_MSR(r1)
-#endif /* CONFIG_TRACE_IRQFLAGS */
-        li      r10,1
-        stb     r10,PACASOFTIRQEN(r13)
-        stb     r10,PACAHARDIRQEN(r13)
-        std     r10,SOFTE(r1)
-#ifdef CONFIG_PPC_ISERIES
-BEGIN_FW_FTR_SECTION
-        /* Hack for handling interrupts when soft-enabling on iSeries */
-        cmpdi   cr1,r0,0x5555           /* syscall 0x5555 */
-        andi.   r10,r12,MSR_PR          /* from kernel */
-        crand   4*cr0+eq,4*cr1+eq,4*cr0+eq
-        bne     2f
-        b       hardware_interrupt_entry
-2:
-END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES)
-#endif /* CONFIG_PPC_ISERIES */
+        /*
+         * A syscall should always be called with interrupts enabled
+         * so we just unconditionally hard-enable here. When some kind
+         * of irq tracing is used, we additionally check that condition
+         * is correct
+         */
+#if defined(CONFIG_TRACE_IRQFLAGS) && defined(CONFIG_BUG)
+        lbz     r10,PACASOFTIRQEN(r13)
+        xori    r10,r10,1
+1:      tdnei   r10,0
+        EMIT_BUG_ENTRY 1b,__FILE__,__LINE__,BUGFLAG_WARNING
+#endif
 
-        /* Hard enable interrupts */
 #ifdef CONFIG_PPC_BOOK3E
         wrteei  1
 #else
-        mfmsr   r11
+        ld      r11,PACAKMSR(r13)
         ori     r11,r11,MSR_EE
         mtmsrd  r11,1
 #endif /* CONFIG_PPC_BOOK3E */
 
+        /* We do need to set SOFTE in the stack frame or the return
+         * from interrupt will be painful
+         */
+        li      r10,1
+        std     r10,SOFTE(r1)
+
 #ifdef SHOW_SYSCALLS
         bl      .do_show_syscall
         REST_GPR(0,r1)
@@ -198,16 +193,14 @@ syscall_exit:
         andi.   r10,r8,MSR_RI
         beq-    unrecov_restore
 #endif
-
-        /* Disable interrupts so current_thread_info()->flags can't change,
+        /*
+         * Disable interrupts so current_thread_info()->flags can't change,
          * and so that we don't get interrupted after loading SRR0/1.
          */
 #ifdef CONFIG_PPC_BOOK3E
         wrteei  0
 #else
-        mfmsr   r10
-        rldicl  r10,r10,48,1
-        rotldi  r10,r10,16
+        ld      r10,PACAKMSR(r13)
         mtmsrd  r10,1
 #endif /* CONFIG_PPC_BOOK3E */
 
@@ -319,7 +312,7 @@ syscall_exit_work:
 #ifdef CONFIG_PPC_BOOK3E
         wrteei  1
 #else
-        mfmsr   r10
+        ld      r10,PACAKMSR(r13)
         ori     r10,r10,MSR_EE
         mtmsrd  r10,1
 #endif /* CONFIG_PPC_BOOK3E */
@@ -565,10 +558,8 @@ _GLOBAL(ret_from_except_lite)
 #ifdef CONFIG_PPC_BOOK3E
         wrteei  0
 #else
-        mfmsr   r10             /* Get current interrupt state */
-        rldicl  r9,r10,48,1     /* clear MSR_EE */
-        rotldi  r9,r9,16
-        mtmsrd  r9,1            /* Update machine state */
+        ld      r10,PACAKMSR(r13) /* Get kernel MSR without EE */
+        mtmsrd  r10,1             /* Update machine state */
 #endif /* CONFIG_PPC_BOOK3E */
 
 #ifdef CONFIG_PREEMPT
@@ -591,25 +582,74 @@ _GLOBAL(ret_from_except_lite)
         ld      r4,TI_FLAGS(r9)
         andi.   r0,r4,_TIF_USER_WORK_MASK
         bne     do_work
-#endif
+#endif /* !CONFIG_PREEMPT */
 
+        .globl  fast_exc_return_irq
+fast_exc_return_irq:
 restore:
-BEGIN_FW_FTR_SECTION
+        /*
+         * This is the main kernel exit path, we first check if we
+         * have to change our interrupt state.
+         */
         ld      r5,SOFTE(r1)
-FW_FTR_SECTION_ELSE
-        b       .Liseries_check_pending_irqs
-ALT_FW_FTR_SECTION_END_IFCLR(FW_FEATURE_ISERIES)
-2:
-        TRACE_AND_RESTORE_IRQ(r5);
+        lbz     r6,PACASOFTIRQEN(r13)
+        cmpwi   cr1,r5,0
+        cmpw    cr0,r5,r6
+        beq     cr0,4f
+
+        /* We do, handle disable first, which is easy */
+        bne     cr1,3f;
+        li      r0,0
+        stb     r0,PACASOFTIRQEN(r13);
+        TRACE_DISABLE_INTS
+        b       4f
 
-        /* extract EE bit and use it to restore paca->hard_enabled */
-        ld      r3,_MSR(r1)
-        rldicl  r4,r3,49,63             /* r0 = (r3 >> 15) & 1 */
-        stb     r4,PACAHARDIRQEN(r13)
+3:      /*
+         * We are about to soft-enable interrupts (we are hard disabled
+         * at this point). We check if there's anything that needs to
+         * be replayed first.
+         */
+        lbz     r0,PACAIRQHAPPENED(r13)
+        cmpwi   cr0,r0,0
+        bne-    restore_check_irq_replay
 
+        /*
+         * Get here when nothing happened while soft-disabled, just
+         * soft-enable and move-on. We will hard-enable as a side
+         * effect of rfi
+         */
+restore_no_replay:
+        TRACE_ENABLE_INTS
+        li      r0,1
+        stb     r0,PACASOFTIRQEN(r13);
+
+        /*
+         * Final return path. BookE is handled in a different file
+         */
+4:
 #ifdef CONFIG_PPC_BOOK3E
         b       .exception_return_book3e
 #else
+        /*
+         * Clear the reservation. If we know the CPU tracks the address of
+         * the reservation then we can potentially save some cycles and use
+         * a larx. On POWER6 and POWER7 this is significantly faster.
+         */
+BEGIN_FTR_SECTION
+        stdcx.  r0,0,r1         /* to clear the reservation */
+FTR_SECTION_ELSE
+        ldarx   r4,0,r1
+ALT_FTR_SECTION_END_IFCLR(CPU_FTR_STCX_CHECKS_ADDRESS)
+
+        /*
+         * Some code path such as load_up_fpu or altivec return directly
+         * here. They run entirely hard disabled and do not alter the
+         * interrupt state. They also don't use lwarx/stwcx. and thus
+         * are known not to leave dangling reservations.
+         */
+        .globl  fast_exception_return
+fast_exception_return:
+        ld      r3,_MSR(r1)
         ld      r4,_CTR(r1)
         ld      r0,_LINK(r1)
         mtctr   r4
@@ -623,28 +663,18 @@ ALT_FW_FTR_SECTION_END_IFCLR(FW_FEATURE_ISERIES)
         beq-    unrecov_restore
 
         /*
-         * Clear the reservation. If we know the CPU tracks the address of
-         * the reservation then we can potentially save some cycles and use
-         * a larx. On POWER6 and POWER7 this is significantly faster.
-         */
-BEGIN_FTR_SECTION
-        stdcx.  r0,0,r1         /* to clear the reservation */
-FTR_SECTION_ELSE
-        ldarx   r4,0,r1
-ALT_FTR_SECTION_END_IFCLR(CPU_FTR_STCX_CHECKS_ADDRESS)
-
-        /*
          * Clear RI before restoring r13.  If we are returning to
          * userspace and we take an exception after restoring r13,
          * we end up corrupting the userspace r13 value.
          */
-        mfmsr   r4
-        andc    r4,r4,r0        /* r0 contains MSR_RI here */
+        ld      r4,PACAKMSR(r13) /* Get kernel MSR without EE */
+        andc    r4,r4,r0         /* r0 contains MSR_RI here */
         mtmsrd  r4,1
 
         /*
          * r13 is our per cpu area, only restore it if we are returning to
-         * userspace
+         * userspace the value stored in the stack frame may belong to
+         * another CPU.
          */
         andi.   r0,r3,MSR_PR
         beq     1f
@@ -669,30 +699,55 @@ ALT_FTR_SECTION_END_IFCLR(CPU_FTR_STCX_CHECKS_ADDRESS)
 
 #endif /* CONFIG_PPC_BOOK3E */
 
-.Liseries_check_pending_irqs:
-#ifdef CONFIG_PPC_ISERIES
-        ld      r5,SOFTE(r1)
-        cmpdi   0,r5,0
-        beq     2b
-        /* Check for pending interrupts (iSeries) */
-        ld      r3,PACALPPACAPTR(r13)
-        ld      r3,LPPACAANYINT(r3)
-        cmpdi   r3,0
-        beq+    2b                      /* skip do_IRQ if no interrupts */
-
-        li      r3,0
-        stb     r3,PACASOFTIRQEN(r13)   /* ensure we are soft-disabled */
-#ifdef CONFIG_TRACE_IRQFLAGS
-        bl      .trace_hardirqs_off
-        mfmsr   r10
-#endif
-        ori     r10,r10,MSR_EE
-        mtmsrd  r10                     /* hard-enable again */
-        addi    r3,r1,STACK_FRAME_OVERHEAD
-        bl      .do_IRQ
-        b       .ret_from_except_lite           /* loop back and handle more */
-#endif
+        /*
+         * Something did happen, check if a re-emit is needed
+         * (this also clears paca->irq_happened)
+         */
+restore_check_irq_replay:
+        /* XXX: We could implement a fast path here where we check
+         * for irq_happened being just 0x01, in which case we can
+         * clear it and return. That means that we would potentially
+         * miss a decrementer having wrapped all the way around.
+         *
+         * Still, this might be useful for things like hash_page
+         */
+        bl      .__check_irq_replay
+        cmpwi   cr0,r3,0
+        beq     restore_no_replay
+ 
+        /*
+         * We need to re-emit an interrupt. We do so by re-using our
+         * existing exception frame. We first change the trap value,
+         * but we need to ensure we preserve the low nibble of it
+         */
+        ld      r4,_TRAP(r1)
+        clrldi  r4,r4,60
+        or      r4,r4,r3
+        std     r4,_TRAP(r1)
 
+        /*
+         * Then find the right handler and call it. Interrupts are
+         * still soft-disabled and we keep them that way.
+        */
+        cmpwi   cr0,r3,0x500
+        bne     1f
+        addi    r3,r1,STACK_FRAME_OVERHEAD;
+        bl      .do_IRQ
+        b       .ret_from_except
+1:      cmpwi   cr0,r3,0x900
+        bne     1f
+        addi    r3,r1,STACK_FRAME_OVERHEAD;
+        bl      .timer_interrupt
+        b       .ret_from_except
+#ifdef CONFIG_PPC_BOOK3E
+1:      cmpwi   cr0,r3,0x280
+        bne     1f
+        addi    r3,r1,STACK_FRAME_OVERHEAD;
+        bl      .doorbell_exception
+        b       .ret_from_except
+#endif /* CONFIG_PPC_BOOK3E */
+1:      b       .ret_from_except /* What else to do here ? */
+ 
 do_work:
 #ifdef CONFIG_PREEMPT
         andi.   r0,r3,MSR_PR    /* Returning to user mode? */
@@ -705,31 +760,22 @@ do_work:
         crandc  eq,cr1*4+eq,eq
         bne     restore
 
-        /* Here we are preempting the current task.
-         *
-         * Ensure interrupts are soft-disabled. We also properly mark
-         * the PACA to reflect the fact that they are hard-disabled
-         * and trace the change
+        /*
+         * Here we are preempting the current task. We want to make
+         * sure we are soft-disabled first
          */
-        li      r0,0
-        stb     r0,PACASOFTIRQEN(r13)
-        stb     r0,PACAHARDIRQEN(r13)
-        TRACE_DISABLE_INTS
-
-        /* Call the scheduler with soft IRQs off */
+        SOFT_DISABLE_INTS(r3,r4)
 1:      bl      .preempt_schedule_irq
 
         /* Hard-disable interrupts again (and update PACA) */
 #ifdef CONFIG_PPC_BOOK3E
         wrteei  0
 #else
-        mfmsr   r10
-        rldicl  r10,r10,48,1
-        rotldi  r10,r10,16
+        ld      r10,PACAKMSR(r13) /* Get kernel MSR without EE */
         mtmsrd  r10,1
 #endif /* CONFIG_PPC_BOOK3E */
-        li      r0,0
-        stb     r0,PACAHARDIRQEN(r13)
+        li      r0,PACA_IRQ_HARD_DIS
+        stb     r0,PACAIRQHAPPENED(r13)
 
         /* Re-test flags and eventually loop */
         clrrdi  r9,r1,THREAD_SHIFT
@@ -751,14 +797,12 @@ user_work:
 
         andi.   r0,r4,_TIF_NEED_RESCHED
         beq     1f
-        li      r5,1
-        TRACE_AND_RESTORE_IRQ(r5);
+        bl      .restore_interrupts
         bl      .schedule
         b       .ret_from_except_lite
 
 1:      bl      .save_nvgprs
-        li      r5,1
-        TRACE_AND_RESTORE_IRQ(r5);
+        bl      .restore_interrupts
         addi    r3,r1,STACK_FRAME_OVERHEAD
         bl      .do_notify_resume
         b       .ret_from_except
diff --git a/arch/powerpc/kernel/exceptions-64e.S b/arch/powerpc/kernel/exceptions-64e.S
index 429983c06f9..7215cc2495d 100644
--- a/arch/powerpc/kernel/exceptions-64e.S
+++ b/arch/powerpc/kernel/exceptions-64e.S
@@ -24,6 +24,7 @@
 #include <asm/ptrace.h>
 #include <asm/ppc-opcode.h>
 #include <asm/mmu.h>
+#include <asm/hw_irq.h>
 
 /* XXX This will ultimately add space for a special exception save
  *     structure used to save things like SRR0/SRR1, SPRGs, MAS, etc...
@@ -77,59 +78,55 @@
 #define SPRN_MC_SRR1    SPRN_MCSRR1
 
 #define NORMAL_EXCEPTION_PROLOG(n, addition)                                \
-        EXCEPTION_PROLOG(n, GEN, addition##_GEN)
+        EXCEPTION_PROLOG(n, GEN, addition##_GEN(n))
 
 #define CRIT_EXCEPTION_PROLOG(n, addition)                                  \
-        EXCEPTION_PROLOG(n, CRIT, addition##_CRIT)
+        EXCEPTION_PROLOG(n, CRIT, addition##_CRIT(n))
 
 #define DBG_EXCEPTION_PROLOG(n, addition)                                   \
-        EXCEPTION_PROLOG(n, DBG, addition##_DBG)
+        EXCEPTION_PROLOG(n, DBG, addition##_DBG(n))
 
 #define MC_EXCEPTION_PROLOG(n, addition)                                    \
-        EXCEPTION_PROLOG(n, MC, addition##_MC)
+        EXCEPTION_PROLOG(n, MC, addition##_MC(n))
 
 
 /* Variants of the "addition" argument for the prolog
  */
-#define PROLOG_ADDITION_NONE_GEN
-#define PROLOG_ADDITION_NONE_CRIT
-#define PROLOG_ADDITION_NONE_DBG
-#define PROLOG_ADDITION_NONE_MC
+#define PROLOG_ADDITION_NONE_GEN(n)
+#define PROLOG_ADDITION_NONE_CRIT(n)
+#define PROLOG_ADDITION_NONE_DBG(n)
+#define PROLOG_ADDITION_NONE_MC(n)
 
-#define PROLOG_ADDITION_MASKABLE_GEN                                        \
+#define PROLOG_ADDITION_MASKABLE_GEN(n)                                     \
         lbz     r11,PACASOFTIRQEN(r13); /* are irqs soft-disabled ? */      \
         cmpwi   cr0,r11,0;              /* yes -> go out of line */         \
-        beq     masked_interrupt_book3e;
+        beq     masked_interrupt_book3e_##n
 
-#define PROLOG_ADDITION_2REGS_GEN                                           \
+#define PROLOG_ADDITION_2REGS_GEN(n)                                        \
         std     r14,PACA_EXGEN+EX_R14(r13);                                 \
         std     r15,PACA_EXGEN+EX_R15(r13)
 
-#define PROLOG_ADDITION_1REG_GEN                                            \
+#define PROLOG_ADDITION_1REG_GEN(n)                                         \
         std     r14,PACA_EXGEN+EX_R14(r13);
 
-#define PROLOG_ADDITION_2REGS_CRIT                                          \
+#define PROLOG_ADDITION_2REGS_CRIT(n)                                       \
         std     r14,PACA_EXCRIT+EX_R14(r13);                                \
         std     r15,PACA_EXCRIT+EX_R15(r13)
 
-#define PROLOG_ADDITION_2REGS_DBG                                           \
+#define PROLOG_ADDITION_2REGS_DBG(n)                                        \
         std     r14,PACA_EXDBG+EX_R14(r13);                                 \
         std     r15,PACA_EXDBG+EX_R15(r13)
 
-#define PROLOG_ADDITION_2REGS_MC                                            \
+#define PROLOG_ADDITION_2REGS_MC(n)                                         \
         std     r14,PACA_EXMC+EX_R14(r13);                                  \
         std     r15,PACA_EXMC+EX_R15(r13)
 
-#define PROLOG_ADDITION_DOORBELL_GEN                                        \
-        lbz     r11,PACASOFTIRQEN(r13); /* are irqs soft-disabled ? */      \
-        cmpwi   cr0,r11,0;              /* yes -> go out of line */         \
-        beq     masked_doorbell_book3e
-
 
 /* Core exception code for all exceptions except TLB misses.
  * XXX: Needs to make SPRN_SPRG_GEN depend on exception type
  */
 #define EXCEPTION_COMMON(n, excf, ints)                                     \
+exc_##n##_common:                                                           \
         std     r0,GPR0(r1);            /* save r0 in stackframe */         \
         std     r2,GPR2(r1);            /* save r2 in stackframe */         \
         SAVE_4GPRS(3, r1);              /* save r3 - r6 in stackframe */    \
@@ -167,20 +164,21 @@
         std     r0,RESULT(r1);          /* clear regs->result */            \
         ints;
 
-/* Variants for the "ints" argument */
+/* Variants for the "ints" argument. This one does nothing when we want
+ * to keep interrupts in their original state
+ */
 #define INTS_KEEP
-#define INTS_DISABLE_SOFT                                                   \
-        stb     r0,PACASOFTIRQEN(r13);  /* mark interrupts soft-disabled */ \
-        TRACE_DISABLE_INTS;
-#define INTS_DISABLE_HARD                                                   \
-        stb     r0,PACAHARDIRQEN(r13); /* and hard disabled */
-#define INTS_DISABLE_ALL                                                    \
-        INTS_DISABLE_SOFT                                                   \
-        INTS_DISABLE_HARD
-
-/* This is called by exceptions that used INTS_KEEP (that is did not clear
- * neither soft nor hard IRQ indicators in the PACA. This will restore MSR:EE
- * to it's previous value
+
+/* This second version is meant for exceptions that don't immediately
+ * hard-enable. We set a bit in paca->irq_happened to ensure that
+ * a subsequent call to arch_local_irq_restore() will properly
+ * hard-enable and avoid the fast-path
+ */
+#define INTS_DISABLE    SOFT_DISABLE_INTS(r3,r4)
+
+/* This is called by exceptions that used INTS_KEEP (that did not touch
+ * irq indicators in the PACA). This will restore MSR:EE to it's previous
+ * value
  *
  * XXX In the long run, we may want to open-code it in order to separate the
  *     load from the wrtee, thus limiting the latency caused by the dependency
@@ -238,7 +236,7 @@ exc_##n##_bad_stack:							    \
 #define MASKABLE_EXCEPTION(trapnum, label, hdlr, ack)                   \
         START_EXCEPTION(label);                                         \
         NORMAL_EXCEPTION_PROLOG(trapnum, PROLOG_ADDITION_MASKABLE)      \
-        EXCEPTION_COMMON(trapnum, PACA_EXGEN, INTS_DISABLE_ALL)         \
+        EXCEPTION_COMMON(trapnum, PACA_EXGEN, INTS_DISABLE)             \
         ack(r8);                                                        \
         CHECK_NAPPING();                                                \
         addi    r3,r1,STACK_FRAME_OVERHEAD;                             \
@@ -289,7 +287,7 @@ interrupt_end_book3e:
 /* Critical Input Interrupt */
         START_EXCEPTION(critical_input);
         CRIT_EXCEPTION_PROLOG(0x100, PROLOG_ADDITION_NONE)
-//      EXCEPTION_COMMON(0x100, PACA_EXCRIT, INTS_DISABLE_ALL)
+//      EXCEPTION_COMMON(0x100, PACA_EXCRIT, INTS_DISABLE)
 //      bl      special_reg_save_crit
 //      CHECK_NAPPING();
 //      addi    r3,r1,STACK_FRAME_OVERHEAD
@@ -300,7 +298,7 @@ interrupt_end_book3e:
 /* Machine Check Interrupt */
         START_EXCEPTION(machine_check);
         CRIT_EXCEPTION_PROLOG(0x200, PROLOG_ADDITION_NONE)
-//      EXCEPTION_COMMON(0x200, PACA_EXMC, INTS_DISABLE_ALL)
+//      EXCEPTION_COMMON(0x200, PACA_EXMC, INTS_DISABLE)
 //      bl      special_reg_save_mc
 //      addi    r3,r1,STACK_FRAME_OVERHEAD
 //      CHECK_NAPPING();
@@ -313,7 +311,7 @@ interrupt_end_book3e:
         NORMAL_EXCEPTION_PROLOG(0x300, PROLOG_ADDITION_2REGS)
         mfspr   r14,SPRN_DEAR
         mfspr   r15,SPRN_ESR
-        EXCEPTION_COMMON(0x300, PACA_EXGEN, INTS_KEEP)
+        EXCEPTION_COMMON(0x300, PACA_EXGEN, INTS_DISABLE)
         b       storage_fault_common
 
 /* Instruction Storage Interrupt */
@@ -321,7 +319,7 @@ interrupt_end_book3e:
         NORMAL_EXCEPTION_PROLOG(0x400, PROLOG_ADDITION_2REGS)
         li      r15,0
         mr      r14,r10
-        EXCEPTION_COMMON(0x400, PACA_EXGEN, INTS_KEEP)
+        EXCEPTION_COMMON(0x400, PACA_EXGEN, INTS_DISABLE)
         b       storage_fault_common
 
 /* External Input Interrupt */
@@ -339,12 +337,11 @@ interrupt_end_book3e:
         START_EXCEPTION(program);
         NORMAL_EXCEPTION_PROLOG(0x700, PROLOG_ADDITION_1REG)
         mfspr   r14,SPRN_ESR
-        EXCEPTION_COMMON(0x700, PACA_EXGEN, INTS_DISABLE_SOFT)
+        EXCEPTION_COMMON(0x700, PACA_EXGEN, INTS_DISABLE)
         std     r14,_DSISR(r1)
         addi    r3,r1,STACK_FRAME_OVERHEAD
         ld      r14,PACA_EXGEN+EX_R14(r13)
         bl      .save_nvgprs
-        INTS_RESTORE_HARD
         bl      .program_check_exception
         b       .ret_from_except
 
@@ -353,15 +350,16 @@ interrupt_end_book3e:
         NORMAL_EXCEPTION_PROLOG(0x800, PROLOG_ADDITION_NONE)
         /* we can probably do a shorter exception entry for that one... */
         EXCEPTION_COMMON(0x800, PACA_EXGEN, INTS_KEEP)
-        bne     1f                      /* if from user, just load it up */
+        ld      r12,_MSR(r1)
+        andi.   r0,r12,MSR_PR;
+        beq-    1f
+        bl      .load_up_fpu
+        b       fast_exception_return
+1:      INTS_DISABLE
         bl      .save_nvgprs
         addi    r3,r1,STACK_FRAME_OVERHEAD
-        INTS_RESTORE_HARD
         bl      .kernel_fp_unavailable_exception
-        BUG_OPCODE
-1:      ld      r12,_MSR(r1)
-        bl      .load_up_fpu
-        b       fast_exception_return
+        b       .ret_from_except
 
 /* Decrementer Interrupt */
         MASKABLE_EXCEPTION(0x900, decrementer, .timer_interrupt, ACK_DEC)
@@ -372,7 +370,7 @@ interrupt_end_book3e:
 /* Watchdog Timer Interrupt */
         START_EXCEPTION(watchdog);
         CRIT_EXCEPTION_PROLOG(0x9f0, PROLOG_ADDITION_NONE)
-//      EXCEPTION_COMMON(0x9f0, PACA_EXCRIT, INTS_DISABLE_ALL)
+//      EXCEPTION_COMMON(0x9f0, PACA_EXCRIT, INTS_DISABLE)
 //      bl      special_reg_save_crit
 //      CHECK_NAPPING();
 //      addi    r3,r1,STACK_FRAME_OVERHEAD
@@ -391,10 +389,9 @@ interrupt_end_book3e:
 /* Auxiliary Processor Unavailable Interrupt */
         START_EXCEPTION(ap_unavailable);
         NORMAL_EXCEPTION_PROLOG(0xf20, PROLOG_ADDITION_NONE)
-        EXCEPTION_COMMON(0xf20, PACA_EXGEN, INTS_KEEP)
-        addi    r3,r1,STACK_FRAME_OVERHEAD
+        EXCEPTION_COMMON(0xf20, PACA_EXGEN, INTS_DISABLE)
         bl      .save_nvgprs
-        INTS_RESTORE_HARD
+        addi    r3,r1,STACK_FRAME_OVERHEAD
         bl      .unknown_exception
         b       .ret_from_except
 
@@ -450,7 +447,7 @@ interrupt_end_book3e:
         mfspr   r15,SPRN_SPRG_CRIT_SCRATCH
         mtspr   SPRN_SPRG_GEN_SCRATCH,r15
         mfspr   r14,SPRN_DBSR
-        EXCEPTION_COMMON(0xd00, PACA_EXCRIT, INTS_DISABLE_ALL)
+        EXCEPTION_COMMON(0xd00, PACA_EXCRIT, INTS_DISABLE)
         std     r14,_DSISR(r1)
         addi    r3,r1,STACK_FRAME_OVERHEAD
         mr      r4,r14
@@ -465,7 +462,7 @@ kernel_dbg_exc:
 
 /* Debug exception as a debug interrupt*/
         START_EXCEPTION(debug_debug);
-        DBG_EXCEPTION_PROLOG(0xd00, PROLOG_ADDITION_2REGS)
+        DBG_EXCEPTION_PROLOG(0xd08, PROLOG_ADDITION_2REGS)
 
         /*
          * If there is a single step or branch-taken exception in an
@@ -515,7 +512,7 @@ kernel_dbg_exc:
         mfspr   r15,SPRN_SPRG_DBG_SCRATCH
         mtspr   SPRN_SPRG_GEN_SCRATCH,r15
         mfspr   r14,SPRN_DBSR
-        EXCEPTION_COMMON(0xd00, PACA_EXDBG, INTS_DISABLE_ALL)
+        EXCEPTION_COMMON(0xd08, PACA_EXDBG, INTS_DISABLE)
         std     r14,_DSISR(r1)
         addi    r3,r1,STACK_FRAME_OVERHEAD
         mr      r4,r14
@@ -525,21 +522,20 @@ kernel_dbg_exc:
         bl      .DebugException
         b       .ret_from_except
 
-        MASKABLE_EXCEPTION(0x260, perfmon, .performance_monitor_exception, ACK_NONE)
-
-/* Doorbell interrupt */
-        START_EXCEPTION(doorbell)
-        NORMAL_EXCEPTION_PROLOG(0x2070, PROLOG_ADDITION_DOORBELL)
-        EXCEPTION_COMMON(0x2070, PACA_EXGEN, INTS_DISABLE_ALL)
-        CHECK_NAPPING()
+        START_EXCEPTION(perfmon);
+        NORMAL_EXCEPTION_PROLOG(0x260, PROLOG_ADDITION_NONE)
+        EXCEPTION_COMMON(0x260, PACA_EXGEN, INTS_DISABLE)
         addi    r3,r1,STACK_FRAME_OVERHEAD
-        bl      .doorbell_exception
+        bl      .performance_monitor_exception
         b       .ret_from_except_lite
 
+/* Doorbell interrupt */
+        MASKABLE_EXCEPTION(0x280, doorbell, .doorbell_exception, ACK_NONE)
+
 /* Doorbell critical Interrupt */
         START_EXCEPTION(doorbell_crit);
-        CRIT_EXCEPTION_PROLOG(0x2080, PROLOG_ADDITION_NONE)
-//      EXCEPTION_COMMON(0x2080, PACA_EXCRIT, INTS_DISABLE_ALL)
+        CRIT_EXCEPTION_PROLOG(0x2a0, PROLOG_ADDITION_NONE)
+//      EXCEPTION_COMMON(0x2a0, PACA_EXCRIT, INTS_DISABLE)
 //      bl      special_reg_save_crit
 //      CHECK_NAPPING();
 //      addi    r3,r1,STACK_FRAME_OVERHEAD
@@ -547,36 +543,114 @@ kernel_dbg_exc:
 //      b       ret_from_crit_except
         b       .
 
+/* Guest Doorbell */
         MASKABLE_EXCEPTION(0x2c0, guest_doorbell, .unknown_exception, ACK_NONE)
-        MASKABLE_EXCEPTION(0x2e0, guest_doorbell_crit, .unknown_exception, ACK_NONE)
-        MASKABLE_EXCEPTION(0x310, hypercall, .unknown_exception, ACK_NONE)
-        MASKABLE_EXCEPTION(0x320, ehpriv, .unknown_exception, ACK_NONE)
 
+/* Guest Doorbell critical Interrupt */
+        START_EXCEPTION(guest_doorbell_crit);
+        CRIT_EXCEPTION_PROLOG(0x2e0, PROLOG_ADDITION_NONE)
+//      EXCEPTION_COMMON(0x2e0, PACA_EXCRIT, INTS_DISABLE)
+//      bl      special_reg_save_crit
+//      CHECK_NAPPING();
+//      addi    r3,r1,STACK_FRAME_OVERHEAD
+//      bl      .guest_doorbell_critical_exception
+//      b       ret_from_crit_except
+        b       .
+
+/* Hypervisor call */
+        START_EXCEPTION(hypercall);
+        NORMAL_EXCEPTION_PROLOG(0x310, PROLOG_ADDITION_NONE)
+        EXCEPTION_COMMON(0x310, PACA_EXGEN, INTS_KEEP)
+        addi    r3,r1,STACK_FRAME_OVERHEAD
+        bl      .save_nvgprs
+        INTS_RESTORE_HARD
+        bl      .unknown_exception
+        b       .ret_from_except
+
+/* Embedded Hypervisor priviledged  */
+        START_EXCEPTION(ehpriv);
+        NORMAL_EXCEPTION_PROLOG(0x320, PROLOG_ADDITION_NONE)
+        EXCEPTION_COMMON(0x320, PACA_EXGEN, INTS_KEEP)
+        addi    r3,r1,STACK_FRAME_OVERHEAD
+        bl      .save_nvgprs
+        INTS_RESTORE_HARD
+        bl      .unknown_exception
+        b       .ret_from_except
 
 /*
- * An interrupt came in while soft-disabled; clear EE in SRR1,
- * clear paca->hard_enabled and return.
+ * An interrupt came in while soft-disabled; We mark paca->irq_happened
+ * accordingly and if the interrupt is level sensitive, we hard disable
  */
-masked_doorbell_book3e:
-        mtcr    r10
-        /* Resend the doorbell to fire again when ints enabled */
-        mfspr   r10,SPRN_PIR
-        PPC_MSGSND(r10)
-        b       masked_interrupt_book3e_common
 
-masked_interrupt_book3e:
+masked_interrupt_book3e_0x500:
+        /* XXX When adding support for EPR, use PACA_IRQ_EE_EDGE */
+        li      r11,PACA_IRQ_EE
+        b       masked_interrupt_book3e_full_mask
+
+masked_interrupt_book3e_0x900:
+        ACK_DEC(r11);
+        li      r11,PACA_IRQ_DEC
+        b       masked_interrupt_book3e_no_mask
+masked_interrupt_book3e_0x980:
+        ACK_FIT(r11);
+        li      r11,PACA_IRQ_DEC
+        b       masked_interrupt_book3e_no_mask
+masked_interrupt_book3e_0x280:
+masked_interrupt_book3e_0x2c0:
+        li      r11,PACA_IRQ_DBELL
+        b       masked_interrupt_book3e_no_mask
+
+masked_interrupt_book3e_no_mask:
+        mtcr    r10
+        lbz     r10,PACAIRQHAPPENED(r13)
+        or      r10,r10,r11
+        stb     r10,PACAIRQHAPPENED(r13)
+        b       1f
+masked_interrupt_book3e_full_mask:
         mtcr    r10
-masked_interrupt_book3e_common:
-        stb     r11,PACAHARDIRQEN(r13)
+        lbz     r10,PACAIRQHAPPENED(r13)
+        or      r10,r10,r11
+        stb     r10,PACAIRQHAPPENED(r13)
         mfspr   r10,SPRN_SRR1
         rldicl  r11,r10,48,1            /* clear MSR_EE */
         rotldi  r10,r11,16
         mtspr   SPRN_SRR1,r10
-        ld      r10,PACA_EXGEN+EX_R10(r13);     /* restore registers */
+1:      ld      r10,PACA_EXGEN+EX_R10(r13);
         ld      r11,PACA_EXGEN+EX_R11(r13);
         mfspr   r13,SPRN_SPRG_GEN_SCRATCH;
         rfi
         b       .
+/*
+ * Called from arch_local_irq_enable when an interrupt needs
+ * to be resent. r3 contains either 0x500,0x900,0x260 or 0x280
+ * to indicate the kind of interrupt. MSR:EE is already off.
+ * We generate a stackframe like if a real interrupt had happened.
+ *
+ * Note: While MSR:EE is off, we need to make sure that _MSR
+ * in the generated frame has EE set to 1 or the exception
+ * handler will not properly re-enable them.
+ */
+_GLOBAL(__replay_interrupt)
+        /* We are going to jump to the exception common code which
+         * will retrieve various register values from the PACA which
+         * we don't give a damn about.
+         */
+        mflr    r10
+        mfmsr   r11
+        mfcr    r4
+        mtspr   SPRN_SPRG_GEN_SCRATCH,r13;
+        std     r1,PACA_EXGEN+EX_R1(r13);
+        stw     r4,PACA_EXGEN+EX_CR(r13);
+        ori     r11,r11,MSR_EE
+        subi    r1,r1,INT_FRAME_SIZE;
+        cmpwi   cr0,r3,0x500
+        beq     exc_0x500_common
+        cmpwi   cr0,r3,0x900
+        beq     exc_0x900_common
+        cmpwi   cr0,r3,0x280
+        beq     exc_0x280_common
+        blr
+
 
 /*
  * This is called from 0x300 and 0x400 handlers after the prologs with
@@ -591,7 +665,6 @@ storage_fault_common:
         mr      r5,r15
         ld      r14,PACA_EXGEN+EX_R14(r13)
         ld      r15,PACA_EXGEN+EX_R15(r13)
-        INTS_RESTORE_HARD
         bl      .do_page_fault
         cmpdi   r3,0
         bne-    1f
@@ -680,6 +753,8 @@ BAD_STACK_TRAMPOLINE(0x000)
 BAD_STACK_TRAMPOLINE(0x100)
 BAD_STACK_TRAMPOLINE(0x200)
 BAD_STACK_TRAMPOLINE(0x260)
+BAD_STACK_TRAMPOLINE(0x280)
+BAD_STACK_TRAMPOLINE(0x2a0)
 BAD_STACK_TRAMPOLINE(0x2c0)
 BAD_STACK_TRAMPOLINE(0x2e0)
 BAD_STACK_TRAMPOLINE(0x300)
@@ -697,11 +772,10 @@ BAD_STACK_TRAMPOLINE(0xa00)
 BAD_STACK_TRAMPOLINE(0xb00)
 BAD_STACK_TRAMPOLINE(0xc00)
 BAD_STACK_TRAMPOLINE(0xd00)
+BAD_STACK_TRAMPOLINE(0xd08)
 BAD_STACK_TRAMPOLINE(0xe00)
 BAD_STACK_TRAMPOLINE(0xf00)
 BAD_STACK_TRAMPOLINE(0xf20)
-BAD_STACK_TRAMPOLINE(0x2070)
-BAD_STACK_TRAMPOLINE(0x2080)
 
         .globl  bad_stack_book3e
 bad_stack_book3e:
diff --git a/arch/powerpc/kernel/exceptions-64s.S b/arch/powerpc/kernel/exceptions-64s.S
index 15c5a4f6de0..2d0868a4e2f 100644
--- a/arch/powerpc/kernel/exceptions-64s.S
+++ b/arch/powerpc/kernel/exceptions-64s.S
@@ -12,6 +12,7 @@
  *
  */
 
+#include <asm/hw_irq.h>
 #include <asm/exception-64s.h>
 #include <asm/ptrace.h>
 
@@ -19,7 +20,7 @@
  * We layout physical memory as follows:
  * 0x0000 - 0x00ff : Secondary processor spin code
  * 0x0100 - 0x2fff : pSeries Interrupt prologs
- * 0x3000 - 0x5fff : interrupt support, iSeries and common interrupt prologs
+ * 0x3000 - 0x5fff : interrupt support common interrupt prologs
  * 0x6000 - 0x6fff : Initial (CPU0) segment table
  * 0x7000 - 0x7fff : FWNMI data area
  * 0x8000 -        : Early init and support code
@@ -356,34 +357,60 @@ do_stab_bolted_pSeries:
         KVM_HANDLER_PR(PACA_EXGEN, EXC_STD, 0xf40)
 
 /*
- * An interrupt came in while soft-disabled; clear EE in SRR1,
- * clear paca->hard_enabled and return.
+ * An interrupt came in while soft-disabled. We set paca->irq_happened,
+ * then, if it was a decrementer interrupt, we bump the dec to max and
+ * and return, else we hard disable and return. This is called with
+ * r10 containing the value to OR to the paca field.
  */
-masked_interrupt:
-        stb     r10,PACAHARDIRQEN(r13)
-        mtcrf   0x80,r9
-        ld      r9,PACA_EXGEN+EX_R9(r13)
-        mfspr   r10,SPRN_SRR1
-        rldicl  r10,r10,48,1            /* clear MSR_EE */
-        rotldi  r10,r10,16
-        mtspr   SPRN_SRR1,r10
-        ld      r10,PACA_EXGEN+EX_R10(r13)
-        GET_SCRATCH0(r13)
-        rfid
+#define MASKED_INTERRUPT(_H)                            \
+masked_##_H##interrupt:                                 \
+        std     r11,PACA_EXGEN+EX_R11(r13);             \
+        lbz     r11,PACAIRQHAPPENED(r13);               \
+        or      r11,r11,r10;                            \
+        stb     r11,PACAIRQHAPPENED(r13);               \
+        andi.   r10,r10,PACA_IRQ_DEC;                   \
+        beq     1f;                                     \
+        lis     r10,0x7fff;                             \
+        ori     r10,r10,0xffff;                         \
+        mtspr   SPRN_DEC,r10;                           \
+        b       2f;                                     \
+1:      mfspr   r10,SPRN_##_H##SRR1;                    \
+        rldicl  r10,r10,48,1; /* clear MSR_EE */        \
+        rotldi  r10,r10,16;                             \
+        mtspr   SPRN_##_H##SRR1,r10;                    \
+2:      mtcrf   0x80,r9;                                \
+        ld      r9,PACA_EXGEN+EX_R9(r13);               \
+        ld      r10,PACA_EXGEN+EX_R10(r13);             \
+        ld      r11,PACA_EXGEN+EX_R11(r13);             \
+        GET_SCRATCH0(r13);                              \
+        ##_H##rfid;                                     \
         b       .
+        
+        MASKED_INTERRUPT()
+        MASKED_INTERRUPT(H)
 
-masked_Hinterrupt:
-        stb     r10,PACAHARDIRQEN(r13)
-        mtcrf   0x80,r9
-        ld      r9,PACA_EXGEN+EX_R9(r13)
-        mfspr   r10,SPRN_HSRR1
-        rldicl  r10,r10,48,1            /* clear MSR_EE */
-        rotldi  r10,r10,16
-        mtspr   SPRN_HSRR1,r10
-        ld      r10,PACA_EXGEN+EX_R10(r13)
-        GET_SCRATCH0(r13)
-        hrfid
-        b       .
+/*
+ * Called from arch_local_irq_enable when an interrupt needs
+ * to be resent. r3 contains 0x500 or 0x900 to indicate which
+ * kind of interrupt. MSR:EE is already off. We generate a
+ * stackframe like if a real interrupt had happened.
+ *
+ * Note: While MSR:EE is off, we need to make sure that _MSR
+ * in the generated frame has EE set to 1 or the exception
+ * handler will not properly re-enable them.
+ */
+_GLOBAL(__replay_interrupt)
+        /* We are going to jump to the exception common code which
+         * will retrieve various register values from the PACA which
+         * we don't give a damn about, so we don't bother storing them.
+         */
+        mfmsr   r12
+        mflr    r11
+        mfcr    r9
+        ori     r12,r12,MSR_EE
+        andi.   r3,r3,0x0800
+        bne     decrementer_common
+        b       hardware_interrupt_common
 
 #ifdef CONFIG_PPC_PSERIES
 /*
@@ -458,14 +485,15 @@ machine_check_common:
         bl      .machine_check_exception
         b       .ret_from_except
 
-        STD_EXCEPTION_COMMON_LITE(0x900, decrementer, .timer_interrupt)
+        STD_EXCEPTION_COMMON_ASYNC(0x500, hardware_interrupt, do_IRQ)
+        STD_EXCEPTION_COMMON_ASYNC(0x900, decrementer, .timer_interrupt)
         STD_EXCEPTION_COMMON(0xa00, trap_0a, .unknown_exception)
         STD_EXCEPTION_COMMON(0xb00, trap_0b, .unknown_exception)
         STD_EXCEPTION_COMMON(0xd00, single_step, .single_step_exception)
         STD_EXCEPTION_COMMON(0xe00, trap_0e, .unknown_exception)
         STD_EXCEPTION_COMMON(0xe40, emulation_assist, .program_check_exception)
         STD_EXCEPTION_COMMON(0xe60, hmi_exception, .unknown_exception)
-        STD_EXCEPTION_COMMON_IDLE(0xf00, performance_monitor, .performance_monitor_exception)
+        STD_EXCEPTION_COMMON_ASYNC(0xf00, performance_monitor, .performance_monitor_exception)
         STD_EXCEPTION_COMMON(0x1300, instruction_breakpoint, .instruction_breakpoint_exception)
 #ifdef CONFIG_ALTIVEC
         STD_EXCEPTION_COMMON(0x1700, altivec_assist, .altivec_assist_exception)
@@ -482,6 +510,9 @@ machine_check_common:
 system_call_entry:
         b       system_call_common
 
+ppc64_runlatch_on_trampoline:
+        b       .__ppc64_runlatch_on
+
 /*
  * Here we have detected that the kernel stack pointer is bad.
  * R9 contains the saved CR, r13 points to the paca,
@@ -555,6 +586,8 @@ data_access_common:
         mfspr   r10,SPRN_DSISR
         stw     r10,PACA_EXGEN+EX_DSISR(r13)
         EXCEPTION_PROLOG_COMMON(0x300, PACA_EXGEN)
+        DISABLE_INTS
+        ld      r12,_MSR(r1)
         ld      r3,PACA_EXGEN+EX_DAR(r13)
         lwz     r4,PACA_EXGEN+EX_DSISR(r13)
         li      r5,0x300
@@ -569,6 +602,7 @@ h_data_storage_common:
         stw     r10,PACA_EXGEN+EX_DSISR(r13)
         EXCEPTION_PROLOG_COMMON(0xe00, PACA_EXGEN)
         bl      .save_nvgprs
+        DISABLE_INTS
         addi    r3,r1,STACK_FRAME_OVERHEAD
         bl      .unknown_exception
         b       .ret_from_except
@@ -577,6 +611,8 @@ h_data_storage_common:
         .globl instruction_access_common
 instruction_access_common:
         EXCEPTION_PROLOG_COMMON(0x400, PACA_EXGEN)
+        DISABLE_INTS
+        ld      r12,_MSR(r1)
         ld      r3,_NIP(r1)
         andis.  r4,r12,0x5820
         li      r5,0x400
@@ -672,12 +708,6 @@ _GLOBAL(slb_miss_realmode)
         ld      r10,PACA_EXSLB+EX_LR(r13)
         ld      r3,PACA_EXSLB+EX_R3(r13)
         lwz     r9,PACA_EXSLB+EX_CCR(r13)       /* get saved CR */
-#ifdef CONFIG_PPC_ISERIES
-BEGIN_FW_FTR_SECTION
-        ld      r11,PACALPPACAPTR(r13)
-        ld      r11,LPPACASRR0(r11)             /* get SRR0 value */
-END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES)
-#endif /* CONFIG_PPC_ISERIES */
 
         mtlr    r10
 
@@ -690,12 +720,6 @@ END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES)
         mtcrf   0x01,r9         /* slb_allocate uses cr0 and cr7 */
 .machine        pop
 
-#ifdef CONFIG_PPC_ISERIES
-BEGIN_FW_FTR_SECTION
-        mtspr   SPRN_SRR0,r11
-        mtspr   SPRN_SRR1,r12
-END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES)
-#endif /* CONFIG_PPC_ISERIES */
         ld      r9,PACA_EXSLB+EX_R9(r13)
         ld      r10,PACA_EXSLB+EX_R10(r13)
         ld      r11,PACA_EXSLB+EX_R11(r13)
@@ -704,13 +728,7 @@ END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES)
         rfid
         b       .       /* prevent speculative execution */
 
-2:
-#ifdef CONFIG_PPC_ISERIES
-BEGIN_FW_FTR_SECTION
-        b       unrecov_slb
-END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES)
-#endif /* CONFIG_PPC_ISERIES */
-        mfspr   r11,SPRN_SRR0
+2:      mfspr   r11,SPRN_SRR0
         ld      r10,PACAKBASE(r13)
         LOAD_HANDLER(r10,unrecov_slb)
         mtspr   SPRN_SRR0,r10
@@ -727,20 +745,6 @@ unrecov_slb:
         bl      .unrecoverable_exception
         b       1b
 
-        .align  7
-        .globl hardware_interrupt_common
-        .globl hardware_interrupt_entry
-hardware_interrupt_common:
-        EXCEPTION_PROLOG_COMMON(0x500, PACA_EXGEN)
-        FINISH_NAP
-hardware_interrupt_entry:
-        DISABLE_INTS
-BEGIN_FTR_SECTION
-        bl      .ppc64_runlatch_on
-END_FTR_SECTION_IFSET(CPU_FTR_CTRL)
-        addi    r3,r1,STACK_FRAME_OVERHEAD
-        bl      .do_IRQ
-        b       .ret_from_except_lite
 
 #ifdef CONFIG_PPC_970_NAP
 power4_fixup_nap:
@@ -785,8 +789,8 @@ fp_unavailable_common:
         EXCEPTION_PROLOG_COMMON(0x800, PACA_EXGEN)
         bne     1f                      /* if from user, just load it up */
         bl      .save_nvgprs
+        DISABLE_INTS
         addi    r3,r1,STACK_FRAME_OVERHEAD
-        ENABLE_INTS
         bl      .kernel_fp_unavailable_exception
         BUG_OPCODE
 1:      bl      .load_up_fpu
@@ -805,8 +809,8 @@ BEGIN_FTR_SECTION
 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
 #endif
         bl      .save_nvgprs
+        DISABLE_INTS
         addi    r3,r1,STACK_FRAME_OVERHEAD
-        ENABLE_INTS
         bl      .altivec_unavailable_exception
         b       .ret_from_except
 
@@ -816,13 +820,14 @@ vsx_unavailable_common:
         EXCEPTION_PROLOG_COMMON(0xf40, PACA_EXGEN)
 #ifdef CONFIG_VSX
 BEGIN_FTR_SECTION
-        bne     .load_up_vsx
+        beq     1f
+        b       .load_up_vsx
 1:
 END_FTR_SECTION_IFSET(CPU_FTR_VSX)
 #endif
         bl      .save_nvgprs
+        DISABLE_INTS
         addi    r3,r1,STACK_FRAME_OVERHEAD
-        ENABLE_INTS
         bl      .vsx_unavailable_exception
         b       .ret_from_except
 
@@ -831,66 +836,6 @@ END_FTR_SECTION_IFSET(CPU_FTR_VSX)
 __end_handlers:
 
 /*
- * Return from an exception with minimal checks.
- * The caller is assumed to have done EXCEPTION_PROLOG_COMMON.
- * If interrupts have been enabled, or anything has been
- * done that might have changed the scheduling status of
- * any task or sent any task a signal, you should use
- * ret_from_except or ret_from_except_lite instead of this.
- */
-fast_exc_return_irq:                    /* restores irq state too */
-        ld      r3,SOFTE(r1)
-        TRACE_AND_RESTORE_IRQ(r3);
-        ld      r12,_MSR(r1)
-        rldicl  r4,r12,49,63            /* get MSR_EE to LSB */
-        stb     r4,PACAHARDIRQEN(r13)   /* restore paca->hard_enabled */
-        b       1f
-
-        .globl  fast_exception_return
-fast_exception_return:
-        ld      r12,_MSR(r1)
-1:      ld      r11,_NIP(r1)
-        andi.   r3,r12,MSR_RI           /* check if RI is set */
-        beq-    unrecov_fer
-
-#ifdef CONFIG_VIRT_CPU_ACCOUNTING
-        andi.   r3,r12,MSR_PR
-        beq     2f
-        ACCOUNT_CPU_USER_EXIT(r3, r4)
-2:
-#endif
-
-        ld      r3,_CCR(r1)
-        ld      r4,_LINK(r1)
-        ld      r5,_CTR(r1)
-        ld      r6,_XER(r1)
-        mtcr    r3
-        mtlr    r4
-        mtctr   r5
-        mtxer   r6
-        REST_GPR(0, r1)
-        REST_8GPRS(2, r1)
-
-        mfmsr   r10
-        rldicl  r10,r10,48,1            /* clear EE */
-        rldicr  r10,r10,16,61           /* clear RI (LE is 0 already) */
-        mtmsrd  r10,1
-
-        mtspr   SPRN_SRR1,r12
-        mtspr   SPRN_SRR0,r11
-        REST_4GPRS(10, r1)
-        ld      r1,GPR1(r1)
-        rfid
-        b       .       /* prevent speculative execution */
-
-unrecov_fer:
-        bl      .save_nvgprs
-1:      addi    r3,r1,STACK_FRAME_OVERHEAD
-        bl      .unrecoverable_exception
-        b       1b
-
-
-/*
  * Hash table stuff
  */
         .align  7
@@ -912,28 +857,6 @@ END_MMU_FTR_SECTION_IFCLR(MMU_FTR_SLB)
         lwz     r0,TI_PREEMPT(r11)      /* If we're in an "NMI" */
         andis.  r0,r0,NMI_MASK@h        /* (i.e. an irq when soft-disabled) */
         bne     77f                     /* then don't call hash_page now */
-
-        /*
-         * On iSeries, we soft-disable interrupts here, then
-         * hard-enable interrupts so that the hash_page code can spin on
-         * the hash_table_lock without problems on a shared processor.
-         */
-        DISABLE_INTS
-
-        /*
-         * Currently, trace_hardirqs_off() will be called by DISABLE_INTS
-         * and will clobber volatile registers when irq tracing is enabled
-         * so we need to reload them. It may be possible to be smarter here
-         * and move the irq tracing elsewhere but let's keep it simple for
-         * now
-         */
-#ifdef CONFIG_TRACE_IRQFLAGS
-        ld      r3,_DAR(r1)
-        ld      r4,_DSISR(r1)
-        ld      r5,_TRAP(r1)
-        ld      r12,_MSR(r1)
-        clrrdi  r5,r5,4
-#endif /* CONFIG_TRACE_IRQFLAGS */
         /*
          * We need to set the _PAGE_USER bit if MSR_PR is set or if we are
          * accessing a userspace segment (even from the kernel). We assume
@@ -951,62 +874,25 @@ END_MMU_FTR_SECTION_IFCLR(MMU_FTR_SLB)
          * r4 contains the required access permissions
          * r5 contains the trap number
          *
-         * at return r3 = 0 for success
+         * at return r3 = 0 for success, 1 for page fault, negative for error
          */
         bl      .hash_page              /* build HPTE if possible */
         cmpdi   r3,0                    /* see if hash_page succeeded */
 
-BEGIN_FW_FTR_SECTION
-        /*
-         * If we had interrupts soft-enabled at the point where the
-         * DSI/ISI occurred, and an interrupt came in during hash_page,
-         * handle it now.
-         * We jump to ret_from_except_lite rather than fast_exception_return
-         * because ret_from_except_lite will check for and handle pending
-         * interrupts if necessary.
-         */
-        beq     13f
-END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES)
-
-BEGIN_FW_FTR_SECTION
-        /*
-         * Here we have interrupts hard-disabled, so it is sufficient
-         * to restore paca->{soft,hard}_enable and get out.
-         */
+        /* Success */
         beq     fast_exc_return_irq     /* Return from exception on success */
-END_FW_FTR_SECTION_IFCLR(FW_FEATURE_ISERIES)
-
-        /* For a hash failure, we don't bother re-enabling interrupts */
-        ble-    12f
-
-        /*
-         * hash_page couldn't handle it, set soft interrupt enable back
-         * to what it was before the trap.  Note that .arch_local_irq_restore
-         * handles any interrupts pending at this point.
-         */
-        ld      r3,SOFTE(r1)
-        TRACE_AND_RESTORE_IRQ_PARTIAL(r3, 11f)
-        bl      .arch_local_irq_restore
-        b       11f
 
-/* We have a data breakpoint exception - handle it */
-handle_dabr_fault:
-        bl      .save_nvgprs
-        ld      r4,_DAR(r1)
-        ld      r5,_DSISR(r1)
-        addi    r3,r1,STACK_FRAME_OVERHEAD
-        bl      .do_dabr
-        b       .ret_from_except_lite
+        /* Error */
+        blt-    13f
 
 /* Here we have a page fault that hash_page can't handle. */
 handle_page_fault:
-        ENABLE_INTS
 11:     ld      r4,_DAR(r1)
         ld      r5,_DSISR(r1)
         addi    r3,r1,STACK_FRAME_OVERHEAD
         bl      .do_page_fault
         cmpdi   r3,0
-        beq+    13f
+        beq+    12f
         bl      .save_nvgprs
         mr      r5,r3
         addi    r3,r1,STACK_FRAME_OVERHEAD
@@ -1014,12 +900,20 @@ handle_page_fault:
         bl      .bad_page_fault
         b       .ret_from_except
 
-13:     b       .ret_from_except_lite
+/* We have a data breakpoint exception - handle it */
+handle_dabr_fault:
+        bl      .save_nvgprs
+        ld      r4,_DAR(r1)
+        ld      r5,_DSISR(r1)
+        addi    r3,r1,STACK_FRAME_OVERHEAD
+        bl      .do_dabr
+12:     b       .ret_from_except_lite
+
 
 /* We have a page fault that hash_page could handle but HV refused
  * the PTE insertion
  */
-12:     bl      .save_nvgprs
+13:     bl      .save_nvgprs
         mr      r5,r3
         addi    r3,r1,STACK_FRAME_OVERHEAD
         ld      r4,_DAR(r1)
@@ -1141,51 +1035,19 @@ _GLOBAL(do_stab_bolted)
         .= 0x7000
         .globl fwnmi_data_area
 fwnmi_data_area:
-#endif /* defined(CONFIG_PPC_PSERIES) || defined(CONFIG_PPC_POWERNV) */
 
-        /* iSeries does not use the FWNMI stuff, so it is safe to put
-         * this here, even if we later allow kernels that will boot on
-         * both pSeries and iSeries */
-#ifdef CONFIG_PPC_ISERIES
-        . = LPARMAP_PHYS
-        .globl xLparMap
-xLparMap:
-        .quad   HvEsidsToMap            /* xNumberEsids */
-        .quad   HvRangesToMap           /* xNumberRanges */
-        .quad   STAB0_PAGE              /* xSegmentTableOffs */
-        .zero   40                      /* xRsvd */
-        /* xEsids (HvEsidsToMap entries of 2 quads) */
-        .quad   PAGE_OFFSET_ESID        /* xKernelEsid */
-        .quad   PAGE_OFFSET_VSID        /* xKernelVsid */
-        .quad   VMALLOC_START_ESID      /* xKernelEsid */
-        .quad   VMALLOC_START_VSID      /* xKernelVsid */
-        /* xRanges (HvRangesToMap entries of 3 quads) */
-        .quad   HvPagesToMap            /* xPages */
-        .quad   0                       /* xOffset */
-        .quad   PAGE_OFFSET_VSID << (SID_SHIFT - HW_PAGE_SHIFT) /* xVPN */
-
-#endif /* CONFIG_PPC_ISERIES */
-
-#if defined(CONFIG_PPC_PSERIES) || defined(CONFIG_PPC_POWERNV)
         /* pseries and powernv need to keep the whole page from
          * 0x7000 to 0x8000 free for use by the firmware
          */
         . = 0x8000
 #endif /* defined(CONFIG_PPC_PSERIES) || defined(CONFIG_PPC_POWERNV) */
 
-/*
- * Space for CPU0's segment table.
- *
- * On iSeries, the hypervisor must fill in at least one entry before
- * we get control (with relocate on).  The address is given to the hv
- * as a page number (see xLparMap above), so this must be at a
- * fixed address (the linker can't compute (u64)&initial_stab >>
- * PAGE_SHIFT).
- */
-        . = STAB0_OFFSET        /* 0x8000 */
+/* Space for CPU0's segment table */
+        .balign 4096
         .globl initial_stab
 initial_stab:
         .space  4096
+
 #ifdef CONFIG_PPC_POWERNV
 _GLOBAL(opal_mc_secondary_handler)
         HMT_MEDIUM
diff --git a/arch/powerpc/kernel/fadump.c b/arch/powerpc/kernel/fadump.c
new file mode 100644
index 00000000000..cfe7a38708c
--- /dev/null
+++ b/arch/powerpc/kernel/fadump.c
@@ -0,0 +1,1315 @@
+/*
+ * Firmware Assisted dump: A robust mechanism to get reliable kernel crash
+ * dump with assistance from firmware. This approach does not use kexec,
+ * instead firmware assists in booting the kdump kernel while preserving
+ * memory contents. The most of the code implementation has been adapted
+ * from phyp assisted dump implementation written by Linas Vepstas and
+ * Manish Ahuja
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Copyright 2011 IBM Corporation
+ * Author: Mahesh Salgaonkar <mahesh@linux.vnet.ibm.com>
+ */
+
+#undef DEBUG
+#define pr_fmt(fmt) "fadump: " fmt
+
+#include <linux/string.h>
+#include <linux/memblock.h>
+#include <linux/delay.h>
+#include <linux/debugfs.h>
+#include <linux/seq_file.h>
+#include <linux/crash_dump.h>
+#include <linux/kobject.h>
+#include <linux/sysfs.h>
+
+#include <asm/page.h>
+#include <asm/prom.h>
+#include <asm/rtas.h>
+#include <asm/fadump.h>
+
+static struct fw_dump fw_dump;
+static struct fadump_mem_struct fdm;
+static const struct fadump_mem_struct *fdm_active;
+
+static DEFINE_MUTEX(fadump_mutex);
+struct fad_crash_memory_ranges crash_memory_ranges[INIT_CRASHMEM_RANGES];
+int crash_mem_ranges;
+
+/* Scan the Firmware Assisted dump configuration details. */
+int __init early_init_dt_scan_fw_dump(unsigned long node,
+                        const char *uname, int depth, void *data)
+{
+        __be32 *sections;
+        int i, num_sections;
+        unsigned long size;
+        const int *token;
+
+        if (depth != 1 || strcmp(uname, "rtas") != 0)
+                return 0;
+
+        /*
+         * Check if Firmware Assisted dump is supported. if yes, check
+         * if dump has been initiated on last reboot.
+         */
+        token = of_get_flat_dt_prop(node, "ibm,configure-kernel-dump", NULL);
+        if (!token)
+                return 0;
+
+        fw_dump.fadump_supported = 1;
+        fw_dump.ibm_configure_kernel_dump = *token;
+
+        /*
+         * The 'ibm,kernel-dump' rtas node is present only if there is
+         * dump data waiting for us.
+         */
+        fdm_active = of_get_flat_dt_prop(node, "ibm,kernel-dump", NULL);
+        if (fdm_active)
+                fw_dump.dump_active = 1;
+
+        /* Get the sizes required to store dump data for the firmware provided
+         * dump sections.
+         * For each dump section type supported, a 32bit cell which defines
+         * the ID of a supported section followed by two 32 bit cells which
+         * gives teh size of the section in bytes.
+         */
+        sections = of_get_flat_dt_prop(node, "ibm,configure-kernel-dump-sizes",
+                                        &size);
+
+        if (!sections)
+                return 0;
+
+        num_sections = size / (3 * sizeof(u32));
+
+        for (i = 0; i < num_sections; i++, sections += 3) {
+                u32 type = (u32)of_read_number(sections, 1);
+
+                switch (type) {
+                case FADUMP_CPU_STATE_DATA:
+                        fw_dump.cpu_state_data_size =
+                                        of_read_ulong(&sections[1], 2);
+                        break;
+                case FADUMP_HPTE_REGION:
+                        fw_dump.hpte_region_size =
+                                        of_read_ulong(&sections[1], 2);
+                        break;
+                }
+        }
+        return 1;
+}
+
+int is_fadump_active(void)
+{
+        return fw_dump.dump_active;
+}
+
+/* Print firmware assisted dump configurations for debugging purpose. */
+static void fadump_show_config(void)
+{
+        pr_debug("Support for firmware-assisted dump (fadump): %s\n",
+                        (fw_dump.fadump_supported ? "present" : "no support"));
+
+        if (!fw_dump.fadump_supported)
+                return;
+
+        pr_debug("Fadump enabled    : %s\n",
+                                (fw_dump.fadump_enabled ? "yes" : "no"));
+        pr_debug("Dump Active       : %s\n",
+                                (fw_dump.dump_active ? "yes" : "no"));
+        pr_debug("Dump section sizes:\n");
+        pr_debug("    CPU state data size: %lx\n", fw_dump.cpu_state_data_size);
+        pr_debug("    HPTE region size   : %lx\n", fw_dump.hpte_region_size);
+        pr_debug("Boot memory size  : %lx\n", fw_dump.boot_memory_size);
+}
+
+static unsigned long init_fadump_mem_struct(struct fadump_mem_struct *fdm,
+                                unsigned long addr)
+{
+        if (!fdm)
+                return 0;
+
+        memset(fdm, 0, sizeof(struct fadump_mem_struct));
+        addr = addr & PAGE_MASK;
+
+        fdm->header.dump_format_version = 0x00000001;
+        fdm->header.dump_num_sections = 3;
+        fdm->header.dump_status_flag = 0;
+        fdm->header.offset_first_dump_section =
+                (u32)offsetof(struct fadump_mem_struct, cpu_state_data);
+
+        /*
+         * Fields for disk dump option.
+         * We are not using disk dump option, hence set these fields to 0.
+         */
+        fdm->header.dd_block_size = 0;
+        fdm->header.dd_block_offset = 0;
+        fdm->header.dd_num_blocks = 0;
+        fdm->header.dd_offset_disk_path = 0;
+
+        /* set 0 to disable an automatic dump-reboot. */
+        fdm->header.max_time_auto = 0;
+
+        /* Kernel dump sections */
+        /* cpu state data section. */
+        fdm->cpu_state_data.request_flag = FADUMP_REQUEST_FLAG;
+        fdm->cpu_state_data.source_data_type = FADUMP_CPU_STATE_DATA;
+        fdm->cpu_state_data.source_address = 0;
+        fdm->cpu_state_data.source_len = fw_dump.cpu_state_data_size;
+        fdm->cpu_state_data.destination_address = addr;
+        addr += fw_dump.cpu_state_data_size;
+
+        /* hpte region section */
+        fdm->hpte_region.request_flag = FADUMP_REQUEST_FLAG;
+        fdm->hpte_region.source_data_type = FADUMP_HPTE_REGION;
+        fdm->hpte_region.source_address = 0;
+        fdm->hpte_region.source_len = fw_dump.hpte_region_size;
+        fdm->hpte_region.destination_address = addr;
+        addr += fw_dump.hpte_region_size;
+
+        /* RMA region section */
+        fdm->rmr_region.request_flag = FADUMP_REQUEST_FLAG;
+        fdm->rmr_region.source_data_type = FADUMP_REAL_MODE_REGION;
+        fdm->rmr_region.source_address = RMA_START;
+        fdm->rmr_region.source_len = fw_dump.boot_memory_size;
+        fdm->rmr_region.destination_address = addr;
+        addr += fw_dump.boot_memory_size;
+
+        return addr;
+}
+
+/**
+ * fadump_calculate_reserve_size(): reserve variable boot area 5% of System RAM
+ *
+ * Function to find the largest memory size we need to reserve during early
+ * boot process. This will be the size of the memory that is required for a
+ * kernel to boot successfully.
+ *
+ * This function has been taken from phyp-assisted dump feature implementation.
+ *
+ * returns larger of 256MB or 5% rounded down to multiples of 256MB.
+ *
+ * TODO: Come up with better approach to find out more accurate memory size
+ * that is required for a kernel to boot successfully.
+ *
+ */
+static inline unsigned long fadump_calculate_reserve_size(void)
+{
+        unsigned long size;
+
+        /*
+         * Check if the size is specified through fadump_reserve_mem= cmdline
+         * option. If yes, then use that.
+         */
+        if (fw_dump.reserve_bootvar)
+                return fw_dump.reserve_bootvar;
+
+        /* divide by 20 to get 5% of value */
+        size = memblock_end_of_DRAM() / 20;
+
+        /* round it down in multiples of 256 */
+        size = size & ~0x0FFFFFFFUL;
+
+        /* Truncate to memory_limit. We don't want to over reserve the memory.*/
+        if (memory_limit && size > memory_limit)
+                size = memory_limit;
+
+        return (size > MIN_BOOT_MEM ? size : MIN_BOOT_MEM);
+}
+
+/*
+ * Calculate the total memory size required to be reserved for
+ * firmware-assisted dump registration.
+ */
+static unsigned long get_fadump_area_size(void)
+{
+        unsigned long size = 0;
+
+        size += fw_dump.cpu_state_data_size;
+        size += fw_dump.hpte_region_size;
+        size += fw_dump.boot_memory_size;
+        size += sizeof(struct fadump_crash_info_header);
+        size += sizeof(struct elfhdr); /* ELF core header.*/
+        size += sizeof(struct elf_phdr); /* place holder for cpu notes */
+        /* Program headers for crash memory regions. */
+        size += sizeof(struct elf_phdr) * (memblock_num_regions(memory) + 2);
+
+        size = PAGE_ALIGN(size);
+        return size;
+}
+
+int __init fadump_reserve_mem(void)
+{
+        unsigned long base, size, memory_boundary;
+
+        if (!fw_dump.fadump_enabled)
+                return 0;
+
+        if (!fw_dump.fadump_supported) {
+                printk(KERN_INFO "Firmware-assisted dump is not supported on"
+                                " this hardware\n");
+                fw_dump.fadump_enabled = 0;
+                return 0;
+        }
+        /*
+         * Initialize boot memory size
+         * If dump is active then we have already calculated the size during
+         * first kernel.
+         */
+        if (fdm_active)
+                fw_dump.boot_memory_size = fdm_active->rmr_region.source_len;
+        else
+                fw_dump.boot_memory_size = fadump_calculate_reserve_size();
+
+        /*
+         * Calculate the memory boundary.
+         * If memory_limit is less than actual memory boundary then reserve
+         * the memory for fadump beyond the memory_limit and adjust the
+         * memory_limit accordingly, so that the running kernel can run with
+         * specified memory_limit.
+         */
+        if (memory_limit && memory_limit < memblock_end_of_DRAM()) {
+                size = get_fadump_area_size();
+                if ((memory_limit + size) < memblock_end_of_DRAM())
+                        memory_limit += size;
+                else
+                        memory_limit = memblock_end_of_DRAM();
+                printk(KERN_INFO "Adjusted memory_limit for firmware-assisted"
+                                " dump, now %#016llx\n",
+                                (unsigned long long)memory_limit);
+        }
+        if (memory_limit)
+                memory_boundary = memory_limit;
+        else
+                memory_boundary = memblock_end_of_DRAM();
+
+        if (fw_dump.dump_active) {
+                printk(KERN_INFO "Firmware-assisted dump is active.\n");
+                /*
+                 * If last boot has crashed then reserve all the memory
+                 * above boot_memory_size so that we don't touch it until
+                 * dump is written to disk by userspace tool. This memory
+                 * will be released for general use once the dump is saved.
+                 */
+                base = fw_dump.boot_memory_size;
+                size = memory_boundary - base;
+                memblock_reserve(base, size);
+                printk(KERN_INFO "Reserved %ldMB of memory at %ldMB "
+                                "for saving crash dump\n",
+                                (unsigned long)(size >> 20),
+                                (unsigned long)(base >> 20));
+
+                fw_dump.fadumphdr_addr =
+                                fdm_active->rmr_region.destination_address +
+                                fdm_active->rmr_region.source_len;
+                pr_debug("fadumphdr_addr = %p\n",
+                                (void *) fw_dump.fadumphdr_addr);
+        } else {
+                /* Reserve the memory at the top of memory. */
+                size = get_fadump_area_size();
+                base = memory_boundary - size;
+                memblock_reserve(base, size);
+                printk(KERN_INFO "Reserved %ldMB of memory at %ldMB "
+                                "for firmware-assisted dump\n",
+                                (unsigned long)(size >> 20),
+                                (unsigned long)(base >> 20));
+        }
+        fw_dump.reserve_dump_area_start = base;
+        fw_dump.reserve_dump_area_size = size;
+        return 1;
+}
+
+/* Look for fadump= cmdline option. */
+static int __init early_fadump_param(char *p)
+{
+        if (!p)
+                return 1;
+
+        if (strncmp(p, "on", 2) == 0)
+                fw_dump.fadump_enabled = 1;
+        else if (strncmp(p, "off", 3) == 0)
+                fw_dump.fadump_enabled = 0;
+
+        return 0;
+}
+early_param("fadump", early_fadump_param);
+
+/* Look for fadump_reserve_mem= cmdline option */
+static int __init early_fadump_reserve_mem(char *p)
+{
+        if (p)
+                fw_dump.reserve_bootvar = memparse(p, &p);
+        return 0;
+}
+early_param("fadump_reserve_mem", early_fadump_reserve_mem);
+
+static void register_fw_dump(struct fadump_mem_struct *fdm)
+{
+        int rc;
+        unsigned int wait_time;
+
+        pr_debug("Registering for firmware-assisted kernel dump...\n");
+
+        /* TODO: Add upper time limit for the delay */
+        do {
+                rc = rtas_call(fw_dump.ibm_configure_kernel_dump, 3, 1, NULL,
+                        FADUMP_REGISTER, fdm,
+                        sizeof(struct fadump_mem_struct));
+
+                wait_time = rtas_busy_delay_time(rc);
+                if (wait_time)
+                        mdelay(wait_time);
+
+        } while (wait_time);
+
+        switch (rc) {
+        case -1:
+                printk(KERN_ERR "Failed to register firmware-assisted kernel"
+                        " dump. Hardware Error(%d).\n", rc);
+                break;
+        case -3:
+                printk(KERN_ERR "Failed to register firmware-assisted kernel"
+                        " dump. Parameter Error(%d).\n", rc);
+                break;
+        case -9:
+                printk(KERN_ERR "firmware-assisted kernel dump is already "
+                        " registered.");
+                fw_dump.dump_registered = 1;
+                break;
+        case 0:
+                printk(KERN_INFO "firmware-assisted kernel dump registration"
+                        " is successful\n");
+                fw_dump.dump_registered = 1;
+                break;
+        }
+}
+
+void crash_fadump(struct pt_regs *regs, const char *str)
+{
+        struct fadump_crash_info_header *fdh = NULL;
+
+        if (!fw_dump.dump_registered || !fw_dump.fadumphdr_addr)
+                return;
+
+        fdh = __va(fw_dump.fadumphdr_addr);
+        crashing_cpu = smp_processor_id();
+        fdh->crashing_cpu = crashing_cpu;
+        crash_save_vmcoreinfo();
+
+        if (regs)
+                fdh->regs = *regs;
+        else
+                ppc_save_regs(&fdh->regs);
+
+        fdh->cpu_online_mask = *cpu_online_mask;
+
+        /* Call ibm,os-term rtas call to trigger firmware assisted dump */
+        rtas_os_term((char *)str);
+}
+
+#define GPR_MASK        0xffffff0000000000
+static inline int fadump_gpr_index(u64 id)
+{
+        int i = -1;
+        char str[3];
+
+        if ((id & GPR_MASK) == REG_ID("GPR")) {
+                /* get the digits at the end */
+                id &= ~GPR_MASK;
+                id >>= 24;
+                str[2] = '\0';
+                str[1] = id & 0xff;
+                str[0] = (id >> 8) & 0xff;
+                sscanf(str, "%d", &i);
+                if (i > 31)
+                        i = -1;
+        }
+        return i;
+}
+
+static inline void fadump_set_regval(struct pt_regs *regs, u64 reg_id,
+                                                                u64 reg_val)
+{
+        int i;
+
+        i = fadump_gpr_index(reg_id);
+        if (i >= 0)
+                regs->gpr[i] = (unsigned long)reg_val;
+        else if (reg_id == REG_ID("NIA"))
+                regs->nip = (unsigned long)reg_val;
+        else if (reg_id == REG_ID("MSR"))
+                regs->msr = (unsigned long)reg_val;
+        else if (reg_id == REG_ID("CTR"))
+                regs->ctr = (unsigned long)reg_val;
+        else if (reg_id == REG_ID("LR"))
+                regs->link = (unsigned long)reg_val;
+        else if (reg_id == REG_ID("XER"))
+                regs->xer = (unsigned long)reg_val;
+        else if (reg_id == REG_ID("CR"))
+                regs->ccr = (unsigned long)reg_val;
+        else if (reg_id == REG_ID("DAR"))
+                regs->dar = (unsigned long)reg_val;
+        else if (reg_id == REG_ID("DSISR"))
+                regs->dsisr = (unsigned long)reg_val;
+}
+
+static struct fadump_reg_entry*
+fadump_read_registers(struct fadump_reg_entry *reg_entry, struct pt_regs *regs)
+{
+        memset(regs, 0, sizeof(struct pt_regs));
+
+        while (reg_entry->reg_id != REG_ID("CPUEND")) {
+                fadump_set_regval(regs, reg_entry->reg_id,
+                                        reg_entry->reg_value);
+                reg_entry++;
+        }
+        reg_entry++;
+        return reg_entry;
+}
+
+static u32 *fadump_append_elf_note(u32 *buf, char *name, unsigned type,
+                                                void *data, size_t data_len)
+{
+        struct elf_note note;
+
+        note.n_namesz = strlen(name) + 1;
+        note.n_descsz = data_len;
+        note.n_type   = type;
+        memcpy(buf, &note, sizeof(note));
+        buf += (sizeof(note) + 3)/4;
+        memcpy(buf, name, note.n_namesz);
+        buf += (note.n_namesz + 3)/4;
+        memcpy(buf, data, note.n_descsz);
+        buf += (note.n_descsz + 3)/4;
+
+        return buf;
+}
+
+static void fadump_final_note(u32 *buf)
+{
+        struct elf_note note;
+
+        note.n_namesz = 0;
+        note.n_descsz = 0;
+        note.n_type   = 0;
+        memcpy(buf, &note, sizeof(note));
+}
+
+static u32 *fadump_regs_to_elf_notes(u32 *buf, struct pt_regs *regs)
+{
+        struct elf_prstatus prstatus;
+
+        memset(&prstatus, 0, sizeof(prstatus));
+        /*
+         * FIXME: How do i get PID? Do I really need it?
+         * prstatus.pr_pid = ????
+         */
+        elf_core_copy_kernel_regs(&prstatus.pr_reg, regs);
+        buf = fadump_append_elf_note(buf, KEXEC_CORE_NOTE_NAME, NT_PRSTATUS,
+                                &prstatus, sizeof(prstatus));
+        return buf;
+}
+
+static void fadump_update_elfcore_header(char *bufp)
+{
+        struct elfhdr *elf;
+        struct elf_phdr *phdr;
+
+        elf = (struct elfhdr *)bufp;
+        bufp += sizeof(struct elfhdr);
+
+        /* First note is a place holder for cpu notes info. */
+        phdr = (struct elf_phdr *)bufp;
+
+        if (phdr->p_type == PT_NOTE) {
+                phdr->p_paddr = fw_dump.cpu_notes_buf;
+                phdr->p_offset  = phdr->p_paddr;
+                phdr->p_filesz  = fw_dump.cpu_notes_buf_size;
+                phdr->p_memsz = fw_dump.cpu_notes_buf_size;
+        }
+        return;
+}
+
+static void *fadump_cpu_notes_buf_alloc(unsigned long size)
+{
+        void *vaddr;
+        struct page *page;
+        unsigned long order, count, i;
+
+        order = get_order(size);
+        vaddr = (void *)__get_free_pages(GFP_KERNEL|__GFP_ZERO, order);
+        if (!vaddr)
+                return NULL;
+
+        count = 1 << order;
+        page = virt_to_page(vaddr);
+        for (i = 0; i < count; i++)
+                SetPageReserved(page + i);
+        return vaddr;
+}
+
+static void fadump_cpu_notes_buf_free(unsigned long vaddr, unsigned long size)
+{
+        struct page *page;
+        unsigned long order, count, i;
+
+        order = get_order(size);
+        count = 1 << order;
+        page = virt_to_page(vaddr);
+        for (i = 0; i < count; i++)
+                ClearPageReserved(page + i);
+        __free_pages(page, order);
+}
+
+/*
+ * Read CPU state dump data and convert it into ELF notes.
+ * The CPU dump starts with magic number "REGSAVE". NumCpusOffset should be
+ * used to access the data to allow for additional fields to be added without
+ * affecting compatibility. Each list of registers for a CPU starts with
+ * "CPUSTRT" and ends with "CPUEND". Each register entry is of 16 bytes,
+ * 8 Byte ASCII identifier and 8 Byte register value. The register entry
+ * with identifier "CPUSTRT" and "CPUEND" contains 4 byte cpu id as part
+ * of register value. For more details refer to PAPR document.
+ *
+ * Only for the crashing cpu we ignore the CPU dump data and get exact
+ * state from fadump crash info structure populated by first kernel at the
+ * time of crash.
+ */
+static int __init fadump_build_cpu_notes(const struct fadump_mem_struct *fdm)
+{
+        struct fadump_reg_save_area_header *reg_header;
+        struct fadump_reg_entry *reg_entry;
+        struct fadump_crash_info_header *fdh = NULL;
+        void *vaddr;
+        unsigned long addr;
+        u32 num_cpus, *note_buf;
+        struct pt_regs regs;
+        int i, rc = 0, cpu = 0;
+
+        if (!fdm->cpu_state_data.bytes_dumped)
+                return -EINVAL;
+
+        addr = fdm->cpu_state_data.destination_address;
+        vaddr = __va(addr);
+
+        reg_header = vaddr;
+        if (reg_header->magic_number != REGSAVE_AREA_MAGIC) {
+                printk(KERN_ERR "Unable to read register save area.\n");
+                return -ENOENT;
+        }
+        pr_debug("--------CPU State Data------------\n");
+        pr_debug("Magic Number: %llx\n", reg_header->magic_number);
+        pr_debug("NumCpuOffset: %x\n", reg_header->num_cpu_offset);
+
+        vaddr += reg_header->num_cpu_offset;
+        num_cpus = *((u32 *)(vaddr));
+        pr_debug("NumCpus     : %u\n", num_cpus);
+        vaddr += sizeof(u32);
+        reg_entry = (struct fadump_reg_entry *)vaddr;
+
+        /* Allocate buffer to hold cpu crash notes. */
+        fw_dump.cpu_notes_buf_size = num_cpus * sizeof(note_buf_t);
+        fw_dump.cpu_notes_buf_size = PAGE_ALIGN(fw_dump.cpu_notes_buf_size);
+        note_buf = fadump_cpu_notes_buf_alloc(fw_dump.cpu_notes_buf_size);
+        if (!note_buf) {
+                printk(KERN_ERR "Failed to allocate 0x%lx bytes for "
+                        "cpu notes buffer\n", fw_dump.cpu_notes_buf_size);
+                return -ENOMEM;
+        }
+        fw_dump.cpu_notes_buf = __pa(note_buf);
+
+        pr_debug("Allocated buffer for cpu notes of size %ld at %p\n",
+                        (num_cpus * sizeof(note_buf_t)), note_buf);
+
+        if (fw_dump.fadumphdr_addr)
+                fdh = __va(fw_dump.fadumphdr_addr);
+
+        for (i = 0; i < num_cpus; i++) {
+                if (reg_entry->reg_id != REG_ID("CPUSTRT")) {
+                        printk(KERN_ERR "Unable to read CPU state data\n");
+                        rc = -ENOENT;
+                        goto error_out;
+                }
+                /* Lower 4 bytes of reg_value contains logical cpu id */
+                cpu = reg_entry->reg_value & FADUMP_CPU_ID_MASK;
+                if (!cpumask_test_cpu(cpu, &fdh->cpu_online_mask)) {
+                        SKIP_TO_NEXT_CPU(reg_entry);
+                        continue;
+                }
+                pr_debug("Reading register data for cpu %d...\n", cpu);
+                if (fdh && fdh->crashing_cpu == cpu) {
+                        regs = fdh->regs;
+                        note_buf = fadump_regs_to_elf_notes(note_buf, &regs);
+                        SKIP_TO_NEXT_CPU(reg_entry);
+                } else {
+                        reg_entry++;
+                        reg_entry = fadump_read_registers(reg_entry, &regs);
+                        note_buf = fadump_regs_to_elf_notes(note_buf, &regs);
+                }
+        }
+        fadump_final_note(note_buf);
+
+        pr_debug("Updating elfcore header (%llx) with cpu notes\n",
+                                                        fdh->elfcorehdr_addr);
+        fadump_update_elfcore_header((char *)__va(fdh->elfcorehdr_addr));
+        return 0;
+
+error_out:
+        fadump_cpu_notes_buf_free((unsigned long)__va(fw_dump.cpu_notes_buf),
+                                        fw_dump.cpu_notes_buf_size);
+        fw_dump.cpu_notes_buf = 0;
+        fw_dump.cpu_notes_buf_size = 0;
+        return rc;
+
+}
+
+/*
+ * Validate and process the dump data stored by firmware before exporting
+ * it through '/proc/vmcore'.
+ */
+static int __init process_fadump(const struct fadump_mem_struct *fdm_active)
+{
+        struct fadump_crash_info_header *fdh;
+        int rc = 0;
+
+        if (!fdm_active || !fw_dump.fadumphdr_addr)
+                return -EINVAL;
+
+        /* Check if the dump data is valid. */
+        if ((fdm_active->header.dump_status_flag == FADUMP_ERROR_FLAG) ||
+                        (fdm_active->cpu_state_data.error_flags != 0) ||
+                        (fdm_active->rmr_region.error_flags != 0)) {
+                printk(KERN_ERR "Dump taken by platform is not valid\n");
+                return -EINVAL;
+        }
+        if ((fdm_active->rmr_region.bytes_dumped !=
+                        fdm_active->rmr_region.source_len) ||
+                        !fdm_active->cpu_state_data.bytes_dumped) {
+                printk(KERN_ERR "Dump taken by platform is incomplete\n");
+                return -EINVAL;
+        }
+
+        /* Validate the fadump crash info header */
+        fdh = __va(fw_dump.fadumphdr_addr);
+        if (fdh->magic_number != FADUMP_CRASH_INFO_MAGIC) {
+                printk(KERN_ERR "Crash info header is not valid.\n");
+                return -EINVAL;
+        }
+
+        rc = fadump_build_cpu_notes(fdm_active);
+        if (rc)
+                return rc;
+
+        /*
+         * We are done validating dump info and elfcore header is now ready
+         * to be exported. set elfcorehdr_addr so that vmcore module will
+         * export the elfcore header through '/proc/vmcore'.
+         */
+        elfcorehdr_addr = fdh->elfcorehdr_addr;
+
+        return 0;
+}
+
+static inline void fadump_add_crash_memory(unsigned long long base,
+                                        unsigned long long end)
+{
+        if (base == end)
+                return;
+
+        pr_debug("crash_memory_range[%d] [%#016llx-%#016llx], %#llx bytes\n",
+                crash_mem_ranges, base, end - 1, (end - base));
+        crash_memory_ranges[crash_mem_ranges].base = base;
+        crash_memory_ranges[crash_mem_ranges].size = end - base;
+        crash_mem_ranges++;
+}
+
+static void fadump_exclude_reserved_area(unsigned long long start,
+                                        unsigned long long end)
+{
+        unsigned long long ra_start, ra_end;
+
+        ra_start = fw_dump.reserve_dump_area_start;
+        ra_end = ra_start + fw_dump.reserve_dump_area_size;
+
+        if ((ra_start < end) && (ra_end > start)) {
+                if ((start < ra_start) && (end > ra_end)) {
+                        fadump_add_crash_memory(start, ra_start);
+                        fadump_add_crash_memory(ra_end, end);
+                } else if (start < ra_start) {
+                        fadump_add_crash_memory(start, ra_start);
+                } else if (ra_end < end) {
+                        fadump_add_crash_memory(ra_end, end);
+                }
+        } else
+                fadump_add_crash_memory(start, end);
+}
+
+static int fadump_init_elfcore_header(char *bufp)
+{
+        struct elfhdr *elf;
+
+        elf = (struct elfhdr *) bufp;
+        bufp += sizeof(struct elfhdr);
+        memcpy(elf->e_ident, ELFMAG, SELFMAG);
+        elf->e_ident[EI_CLASS] = ELF_CLASS;
+        elf->e_ident[EI_DATA] = ELF_DATA;
+        elf->e_ident[EI_VERSION] = EV_CURRENT;
+        elf->e_ident[EI_OSABI] = ELF_OSABI;
+        memset(elf->e_ident+EI_PAD, 0, EI_NIDENT-EI_PAD);
+        elf->e_type = ET_CORE;
+        elf->e_machine = ELF_ARCH;
+        elf->e_version = EV_CURRENT;
+        elf->e_entry = 0;
+        elf->e_phoff = sizeof(struct elfhdr);
+        elf->e_shoff = 0;
+        elf->e_flags = ELF_CORE_EFLAGS;
+        elf->e_ehsize = sizeof(struct elfhdr);
+        elf->e_phentsize = sizeof(struct elf_phdr);
+        elf->e_phnum = 0;
+        elf->e_shentsize = 0;
+        elf->e_shnum = 0;
+        elf->e_shstrndx = 0;
+
+        return 0;
+}
+
+/*
+ * Traverse through memblock structure and setup crash memory ranges. These
+ * ranges will be used create PT_LOAD program headers in elfcore header.
+ */
+static void fadump_setup_crash_memory_ranges(void)
+{
+        struct memblock_region *reg;
+        unsigned long long start, end;
+
+        pr_debug("Setup crash memory ranges.\n");
+        crash_mem_ranges = 0;
+        /*
+         * add the first memory chunk (RMA_START through boot_memory_size) as
+         * a separate memory chunk. The reason is, at the time crash firmware
+         * will move the content of this memory chunk to different location
+         * specified during fadump registration. We need to create a separate
+         * program header for this chunk with the correct offset.
+         */
+        fadump_add_crash_memory(RMA_START, fw_dump.boot_memory_size);
+
+        for_each_memblock(memory, reg) {
+                start = (unsigned long long)reg->base;
+                end = start + (unsigned long long)reg->size;
+                if (start == RMA_START && end >= fw_dump.boot_memory_size)
+                        start = fw_dump.boot_memory_size;
+
+                /* add this range excluding the reserved dump area. */
+                fadump_exclude_reserved_area(start, end);
+        }
+}
+
+/*
+ * If the given physical address falls within the boot memory region then
+ * return the relocated address that points to the dump region reserved
+ * for saving initial boot memory contents.
+ */
+static inline unsigned long fadump_relocate(unsigned long paddr)
+{
+        if (paddr > RMA_START && paddr < fw_dump.boot_memory_size)
+                return fdm.rmr_region.destination_address + paddr;
+        else
+                return paddr;
+}
+
+static int fadump_create_elfcore_headers(char *bufp)
+{
+        struct elfhdr *elf;
+        struct elf_phdr *phdr;
+        int i;
+
+        fadump_init_elfcore_header(bufp);
+        elf = (struct elfhdr *)bufp;
+        bufp += sizeof(struct elfhdr);
+
+        /*
+         * setup ELF PT_NOTE, place holder for cpu notes info. The notes info
+         * will be populated during second kernel boot after crash. Hence
+         * this PT_NOTE will always be the first elf note.
+         *
+         * NOTE: Any new ELF note addition should be placed after this note.
+         */
+        phdr = (struct elf_phdr *)bufp;
+        bufp += sizeof(struct elf_phdr);
+        phdr->p_type = PT_NOTE;
+        phdr->p_flags = 0;
+        phdr->p_vaddr = 0;
+        phdr->p_align = 0;
+
+        phdr->p_offset = 0;
+        phdr->p_paddr = 0;
+        phdr->p_filesz = 0;
+        phdr->p_memsz = 0;
+
+        (elf->e_phnum)++;
+
+        /* setup ELF PT_NOTE for vmcoreinfo */
+        phdr = (struct elf_phdr *)bufp;
+        bufp += sizeof(struct elf_phdr);
+        phdr->p_type    = PT_NOTE;
+        phdr->p_flags   = 0;
+        phdr->p_vaddr   = 0;
+        phdr->p_align   = 0;
+
+        phdr->p_paddr   = fadump_relocate(paddr_vmcoreinfo_note());
+        phdr->p_offset  = phdr->p_paddr;
+        phdr->p_memsz   = vmcoreinfo_max_size;
+        phdr->p_filesz  = vmcoreinfo_max_size;
+
+        /* Increment number of program headers. */
+        (elf->e_phnum)++;
+
+        /* setup PT_LOAD sections. */
+
+        for (i = 0; i < crash_mem_ranges; i++) {
+                unsigned long long mbase, msize;
+                mbase = crash_memory_ranges[i].base;
+                msize = crash_memory_ranges[i].size;
+
+                if (!msize)
+                        continue;
+
+                phdr = (struct elf_phdr *)bufp;
+                bufp += sizeof(struct elf_phdr);
+                phdr->p_type    = PT_LOAD;
+                phdr->p_flags   = PF_R|PF_W|PF_X;
+                phdr->p_offset  = mbase;
+
+                if (mbase == RMA_START) {
+                        /*
+                         * The entire RMA region will be moved by firmware
+                         * to the specified destination_address. Hence set
+                         * the correct offset.
+                         */
+                        phdr->p_offset = fdm.rmr_region.destination_address;
+                }
+
+                phdr->p_paddr = mbase;
+                phdr->p_vaddr = (unsigned long)__va(mbase);
+                phdr->p_filesz = msize;
+                phdr->p_memsz = msize;
+                phdr->p_align = 0;
+
+                /* Increment number of program headers. */
+                (elf->e_phnum)++;
+        }
+        return 0;
+}
+
+static unsigned long init_fadump_header(unsigned long addr)
+{
+        struct fadump_crash_info_header *fdh;
+
+        if (!addr)
+                return 0;
+
+        fw_dump.fadumphdr_addr = addr;
+        fdh = __va(addr);
+        addr += sizeof(struct fadump_crash_info_header);
+
+        memset(fdh, 0, sizeof(struct fadump_crash_info_header));
+        fdh->magic_number = FADUMP_CRASH_INFO_MAGIC;
+        fdh->elfcorehdr_addr = addr;
+        /* We will set the crashing cpu id in crash_fadump() during crash. */
+        fdh->crashing_cpu = CPU_UNKNOWN;
+
+        return addr;
+}
+
+static void register_fadump(void)
+{
+        unsigned long addr;
+        void *vaddr;
+
+        /*
+         * If no memory is reserved then we can not register for firmware-
+         * assisted dump.
+         */
+        if (!fw_dump.reserve_dump_area_size)
+                return;
+
+        fadump_setup_crash_memory_ranges();
+
+        addr = fdm.rmr_region.destination_address + fdm.rmr_region.source_len;
+        /* Initialize fadump crash info header. */
+        addr = init_fadump_header(addr);
+        vaddr = __va(addr);
+
+        pr_debug("Creating ELF core headers at %#016lx\n", addr);
+        fadump_create_elfcore_headers(vaddr);
+
+        /* register the future kernel dump with firmware. */
+        register_fw_dump(&fdm);
+}
+
+static int fadump_unregister_dump(struct fadump_mem_struct *fdm)
+{
+        int rc = 0;
+        unsigned int wait_time;
+
+        pr_debug("Un-register firmware-assisted dump\n");
+
+        /* TODO: Add upper time limit for the delay */
+        do {
+                rc = rtas_call(fw_dump.ibm_configure_kernel_dump, 3, 1, NULL,
+                        FADUMP_UNREGISTER, fdm,
+                        sizeof(struct fadump_mem_struct));
+
+                wait_time = rtas_busy_delay_time(rc);
+                if (wait_time)
+                        mdelay(wait_time);
+        } while (wait_time);
+
+        if (rc) {
+                printk(KERN_ERR "Failed to un-register firmware-assisted dump."
+                        " unexpected error(%d).\n", rc);
+                return rc;
+        }
+        fw_dump.dump_registered = 0;
+        return 0;
+}
+
+static int fadump_invalidate_dump(struct fadump_mem_struct *fdm)
+{
+        int rc = 0;
+        unsigned int wait_time;
+
+        pr_debug("Invalidating firmware-assisted dump registration\n");
+
+        /* TODO: Add upper time limit for the delay */
+        do {
+                rc = rtas_call(fw_dump.ibm_configure_kernel_dump, 3, 1, NULL,
+                        FADUMP_INVALIDATE, fdm,
+                        sizeof(struct fadump_mem_struct));
+
+                wait_time = rtas_busy_delay_time(rc);
+                if (wait_time)
+                        mdelay(wait_time);
+        } while (wait_time);
+
+        if (rc) {
+                printk(KERN_ERR "Failed to invalidate firmware-assisted dump "
+                        "rgistration. unexpected error(%d).\n", rc);
+                return rc;
+        }
+        fw_dump.dump_active = 0;
+        fdm_active = NULL;
+        return 0;
+}
+
+void fadump_cleanup(void)
+{
+        /* Invalidate the registration only if dump is active. */
+        if (fw_dump.dump_active) {
+                init_fadump_mem_struct(&fdm,
+                        fdm_active->cpu_state_data.destination_address);
+                fadump_invalidate_dump(&fdm);
+        }
+}
+
+/*
+ * Release the memory that was reserved in early boot to preserve the memory
+ * contents. The released memory will be available for general use.
+ */
+static void fadump_release_memory(unsigned long begin, unsigned long end)
+{
+        unsigned long addr;
+        unsigned long ra_start, ra_end;
+
+        ra_start = fw_dump.reserve_dump_area_start;
+        ra_end = ra_start + fw_dump.reserve_dump_area_size;
+
+        for (addr = begin; addr < end; addr += PAGE_SIZE) {
+                /*
+                 * exclude the dump reserve area. Will reuse it for next
+                 * fadump registration.
+                 */
+                if (addr <= ra_end && ((addr + PAGE_SIZE) > ra_start))
+                        continue;
+
+                ClearPageReserved(pfn_to_page(addr >> PAGE_SHIFT));
+                init_page_count(pfn_to_page(addr >> PAGE_SHIFT));
+                free_page((unsigned long)__va(addr));
+                totalram_pages++;
+        }
+}
+
+static void fadump_invalidate_release_mem(void)
+{
+        unsigned long reserved_area_start, reserved_area_end;
+        unsigned long destination_address;
+
+        mutex_lock(&fadump_mutex);
+        if (!fw_dump.dump_active) {
+                mutex_unlock(&fadump_mutex);
+                return;
+        }
+
+        destination_address = fdm_active->cpu_state_data.destination_address;
+        fadump_cleanup();
+        mutex_unlock(&fadump_mutex);
+
+        /*
+         * Save the current reserved memory bounds we will require them
+         * later for releasing the memory for general use.
+         */
+        reserved_area_start = fw_dump.reserve_dump_area_start;
+        reserved_area_end = reserved_area_start +
+                        fw_dump.reserve_dump_area_size;
+        /*
+         * Setup reserve_dump_area_start and its size so that we can
+         * reuse this reserved memory for Re-registration.
+         */
+        fw_dump.reserve_dump_area_start = destination_address;
+        fw_dump.reserve_dump_area_size = get_fadump_area_size();
+
+        fadump_release_memory(reserved_area_start, reserved_area_end);
+        if (fw_dump.cpu_notes_buf) {
+                fadump_cpu_notes_buf_free(
+                                (unsigned long)__va(fw_dump.cpu_notes_buf),
+                                fw_dump.cpu_notes_buf_size);
+                fw_dump.cpu_notes_buf = 0;
+                fw_dump.cpu_notes_buf_size = 0;
+        }
+        /* Initialize the kernel dump memory structure for FAD registration. */
+        init_fadump_mem_struct(&fdm, fw_dump.reserve_dump_area_start);
+}
+
+static ssize_t fadump_release_memory_store(struct kobject *kobj,
+                                        struct kobj_attribute *attr,
+                                        const char *buf, size_t count)
+{
+        if (!fw_dump.dump_active)
+                return -EPERM;
+
+        if (buf[0] == '1') {
+                /*
+                 * Take away the '/proc/vmcore'. We are releasing the dump
+                 * memory, hence it will not be valid anymore.
+                 */
+                vmcore_cleanup();
+                fadump_invalidate_release_mem();
+
+        } else
+                return -EINVAL;
+        return count;
+}
+
+static ssize_t fadump_enabled_show(struct kobject *kobj,
+                                        struct kobj_attribute *attr,
+                                        char *buf)
+{
+        return sprintf(buf, "%d\n", fw_dump.fadump_enabled);
+}
+
+static ssize_t fadump_register_show(struct kobject *kobj,
+                                        struct kobj_attribute *attr,
+                                        char *buf)
+{
+        return sprintf(buf, "%d\n", fw_dump.dump_registered);
+}
+
+static ssize_t fadump_register_store(struct kobject *kobj,
+                                        struct kobj_attribute *attr,
+                                        const char *buf, size_t count)
+{
+        int ret = 0;
+
+        if (!fw_dump.fadump_enabled || fdm_active)
+                return -EPERM;
+
+        mutex_lock(&fadump_mutex);
+
+        switch (buf[0]) {
+        case '0':
+                if (fw_dump.dump_registered == 0) {
+                        ret = -EINVAL;
+                        goto unlock_out;
+                }
+                /* Un-register Firmware-assisted dump */
+                fadump_unregister_dump(&fdm);
+                break;
+        case '1':
+                if (fw_dump.dump_registered == 1) {
+                        ret = -EINVAL;
+                        goto unlock_out;
+                }
+                /* Register Firmware-assisted dump */
+                register_fadump();
+                break;
+        default:
+                ret = -EINVAL;
+                break;
+        }
+
+unlock_out:
+        mutex_unlock(&fadump_mutex);
+        return ret < 0 ? ret : count;
+}
+
+static int fadump_region_show(struct seq_file *m, void *private)
+{
+        const struct fadump_mem_struct *fdm_ptr;
+
+        if (!fw_dump.fadump_enabled)
+                return 0;
+
+        mutex_lock(&fadump_mutex);
+        if (fdm_active)
+                fdm_ptr = fdm_active;
+        else {
+                mutex_unlock(&fadump_mutex);
+                fdm_ptr = &fdm;
+        }
+
+        seq_printf(m,
+                        "CPU : [%#016llx-%#016llx] %#llx bytes, "
+                        "Dumped: %#llx\n",
+                        fdm_ptr->cpu_state_data.destination_address,
+                        fdm_ptr->cpu_state_data.destination_address +
+                        fdm_ptr->cpu_state_data.source_len - 1,
+                        fdm_ptr->cpu_state_data.source_len,
+                        fdm_ptr->cpu_state_data.bytes_dumped);
+        seq_printf(m,
+                        "HPTE: [%#016llx-%#016llx] %#llx bytes, "
+                        "Dumped: %#llx\n",
+                        fdm_ptr->hpte_region.destination_address,
+                        fdm_ptr->hpte_region.destination_address +
+                        fdm_ptr->hpte_region.source_len - 1,
+                        fdm_ptr->hpte_region.source_len,
+                        fdm_ptr->hpte_region.bytes_dumped);
+        seq_printf(m,
+                        "DUMP: [%#016llx-%#016llx] %#llx bytes, "
+                        "Dumped: %#llx\n",
+                        fdm_ptr->rmr_region.destination_address,
+                        fdm_ptr->rmr_region.destination_address +
+                        fdm_ptr->rmr_region.source_len - 1,
+                        fdm_ptr->rmr_region.source_len,
+                        fdm_ptr->rmr_region.bytes_dumped);
+
+        if (!fdm_active ||
+                (fw_dump.reserve_dump_area_start ==
+                fdm_ptr->cpu_state_data.destination_address))
+                goto out;
+
+        /* Dump is active. Show reserved memory region. */
+        seq_printf(m,
+                        "    : [%#016llx-%#016llx] %#llx bytes, "
+                        "Dumped: %#llx\n",
+                        (unsigned long long)fw_dump.reserve_dump_area_start,
+                        fdm_ptr->cpu_state_data.destination_address - 1,
+                        fdm_ptr->cpu_state_data.destination_address -
+                        fw_dump.reserve_dump_area_start,
+                        fdm_ptr->cpu_state_data.destination_address -
+                        fw_dump.reserve_dump_area_start);
+out:
+        if (fdm_active)
+                mutex_unlock(&fadump_mutex);
+        return 0;
+}
+
+static struct kobj_attribute fadump_release_attr = __ATTR(fadump_release_mem,
+                                                0200, NULL,
+                                                fadump_release_memory_store);
+static struct kobj_attribute fadump_attr = __ATTR(fadump_enabled,
+                                                0444, fadump_enabled_show,
+                                                NULL);
+static struct kobj_attribute fadump_register_attr = __ATTR(fadump_registered,
+                                                0644, fadump_register_show,
+                                                fadump_register_store);
+
+static int fadump_region_open(struct inode *inode, struct file *file)
+{
+        return single_open(file, fadump_region_show, inode->i_private);
+}
+
+static const struct file_operations fadump_region_fops = {
+        .open    = fadump_region_open,
+        .read    = seq_read,
+        .llseek  = seq_lseek,
+        .release = single_release,
+};
+
+static void fadump_init_files(void)
+{
+        struct dentry *debugfs_file;
+        int rc = 0;
+
+        rc = sysfs_create_file(kernel_kobj, &fadump_attr.attr);
+        if (rc)
+                printk(KERN_ERR "fadump: unable to create sysfs file"
+                        " fadump_enabled (%d)\n", rc);
+
+        rc = sysfs_create_file(kernel_kobj, &fadump_register_attr.attr);
+        if (rc)
+                printk(KERN_ERR "fadump: unable to create sysfs file"
+                        " fadump_registered (%d)\n", rc);
+
+        debugfs_file = debugfs_create_file("fadump_region", 0444,
+                                        powerpc_debugfs_root, NULL,
+                                        &fadump_region_fops);
+        if (!debugfs_file)
+                printk(KERN_ERR "fadump: unable to create debugfs file"
+                                " fadump_region\n");
+
+        if (fw_dump.dump_active) {
+                rc = sysfs_create_file(kernel_kobj, &fadump_release_attr.attr);
+                if (rc)
+                        printk(KERN_ERR "fadump: unable to create sysfs file"
+                                " fadump_release_mem (%d)\n", rc);
+        }
+        return;
+}
+
+/*
+ * Prepare for firmware-assisted dump.
+ */
+int __init setup_fadump(void)
+{
+        if (!fw_dump.fadump_enabled)
+                return 0;
+
+        if (!fw_dump.fadump_supported) {
+                printk(KERN_ERR "Firmware-assisted dump is not supported on"
+                        " this hardware\n");
+                return 0;
+        }
+
+        fadump_show_config();
+        /*
+         * If dump data is available then see if it is valid and prepare for
+         * saving it to the disk.
+         */
+        if (fw_dump.dump_active) {
+                /*
+                 * if dump process fails then invalidate the registration
+                 * and release memory before proceeding for re-registration.
+                 */
+                if (process_fadump(fdm_active) < 0)
+                        fadump_invalidate_release_mem();
+        }
+        /* Initialize the kernel dump memory structure for FAD registration. */
+        else if (fw_dump.reserve_dump_area_size)
+                init_fadump_mem_struct(&fdm, fw_dump.reserve_dump_area_start);
+        fadump_init_files();
+
+        return 1;
+}
+subsys_initcall(setup_fadump);
diff --git a/arch/powerpc/kernel/head_32.S b/arch/powerpc/kernel/head_32.S
index 0654dba2c1f..dc0488b6f6e 100644
--- a/arch/powerpc/kernel/head_32.S
+++ b/arch/powerpc/kernel/head_32.S
@@ -395,7 +395,7 @@ DataAccess:
         bl      hash_page
 1:      lwz     r5,_DSISR(r11)          /* get DSISR value */
         mfspr   r4,SPRN_DAR
-        EXC_XFER_EE_LITE(0x300, handle_page_fault)
+        EXC_XFER_LITE(0x300, handle_page_fault)
 
 
 /* Instruction access exception. */
@@ -410,7 +410,7 @@ InstructionAccess:
         bl      hash_page
 1:      mr      r4,r12
         mr      r5,r9
-        EXC_XFER_EE_LITE(0x400, handle_page_fault)
+        EXC_XFER_LITE(0x400, handle_page_fault)
 
 /* External interrupt */
         EXCEPTION(0x500, HardwareInterrupt, do_IRQ, EXC_XFER_LITE)
diff --git a/arch/powerpc/kernel/head_40x.S b/arch/powerpc/kernel/head_40x.S
index 872a6af83ba..4989661b710 100644
--- a/arch/powerpc/kernel/head_40x.S
+++ b/arch/powerpc/kernel/head_40x.S
@@ -394,7 +394,7 @@ label:
         NORMAL_EXCEPTION_PROLOG
         mr      r4,r12                  /* Pass SRR0 as arg2 */
         li      r5,0                    /* Pass zero as arg3 */
-        EXC_XFER_EE_LITE(0x400, handle_page_fault)
+        EXC_XFER_LITE(0x400, handle_page_fault)
 
 /* 0x0500 - External Interrupt Exception */
         EXCEPTION(0x0500, HardwareInterrupt, do_IRQ, EXC_XFER_LITE)
@@ -747,7 +747,7 @@ DataAccess:
         mfspr   r5,SPRN_ESR             /* Grab the ESR, save it, pass arg3 */
         stw     r5,_ESR(r11)
         mfspr   r4,SPRN_DEAR            /* Grab the DEAR, save it, pass arg2 */
-        EXC_XFER_EE_LITE(0x300, handle_page_fault)
+        EXC_XFER_LITE(0x300, handle_page_fault)
 
 /* Other PowerPC processors, namely those derived from the 6xx-series
  * have vectors from 0x2100 through 0x2F00 defined, but marked as reserved.
diff --git a/arch/powerpc/kernel/head_64.S b/arch/powerpc/kernel/head_64.S
index 06c7251c1bf..58bddee8e1e 100644
--- a/arch/powerpc/kernel/head_64.S
+++ b/arch/powerpc/kernel/head_64.S
@@ -32,13 +32,13 @@
 #include <asm/cputable.h>
 #include <asm/setup.h>
 #include <asm/hvcall.h>
-#include <asm/iseries/lpar_map.h>
 #include <asm/thread_info.h>
 #include <asm/firmware.h>
 #include <asm/page_64.h>
 #include <asm/irqflags.h>
 #include <asm/kvm_book3s_asm.h>
 #include <asm/ptrace.h>
+#include <asm/hw_irq.h>
 
 /* The physical memory is laid out such that the secondary processor
  * spin code sits at 0x0000...0x00ff. On server, the vectors follow
@@ -57,10 +57,6 @@
  *      entry in r9 for debugging purposes
  *   2. Secondary processors enter at 0x60 with PIR in gpr3
  *
- *  For iSeries:
- *   1. The MMU is on (as it always is for iSeries)
- *   2. The kernel is entered at system_reset_iSeries
- *
  *  For Book3E processors:
  *   1. The MMU is on running in AS0 in a state defined in ePAPR
  *   2. The kernel is entered at __start
@@ -93,15 +89,6 @@ __secondary_hold_spinloop:
 __secondary_hold_acknowledge:
         .llong  0x0
 
-#ifdef CONFIG_PPC_ISERIES
-        /*
-         * At offset 0x20, there is a pointer to iSeries LPAR data.
-         * This is required by the hypervisor
-         */
-        . = 0x20
-        .llong hvReleaseData-KERNELBASE
-#endif /* CONFIG_PPC_ISERIES */
-
 #ifdef CONFIG_RELOCATABLE
         /* This flag is set to 1 by a loader if the kernel should run
          * at the loaded address instead of the linked address.  This
@@ -564,7 +551,8 @@ _GLOBAL(pmac_secondary_start)
          */
         li      r0,0
         stb     r0,PACASOFTIRQEN(r13)
-        stb     r0,PACAHARDIRQEN(r13)
+        li      r0,PACA_IRQ_HARD_DIS
+        stb     r0,PACAIRQHAPPENED(r13)
 
         /* Create a temp kernel stack for use before relocation is on.  */
         ld      r1,PACAEMERGSP(r13)
@@ -582,7 +570,7 @@ _GLOBAL(pmac_secondary_start)
  *   1. Processor number
  *   2. Segment table pointer (virtual address)
  * On entry the following are set:
- *   r1        = stack pointer.  vaddr for iSeries, raddr (temp stack) for pSeries
+ *   r1        = stack pointer (real addr of temp stack)
  *   r24       = cpu# (in Linux terms)
  *   r13       = paca virtual address
  *   SPRG_PACA = paca virtual address
@@ -595,7 +583,7 @@ __secondary_start:
         /* Set thread priority to MEDIUM */
         HMT_MEDIUM
 
-        /* Initialize the kernel stack.  Just a repeat for iSeries.      */
+        /* Initialize the kernel stack */
         LOAD_REG_ADDR(r3, current_set)
         sldi    r28,r24,3               /* get current_set[cpu#]         */
         ldx     r14,r3,r28
@@ -615,20 +603,16 @@ __secondary_start:
         li      r7,0
         mtlr    r7
 
+        /* Mark interrupts soft and hard disabled (they might be enabled
+         * in the PACA when doing hotplug)
+         */
+        stb     r7,PACASOFTIRQEN(r13)
+        li      r0,PACA_IRQ_HARD_DIS
+        stb     r0,PACAIRQHAPPENED(r13)
+
         /* enable MMU and jump to start_secondary */
         LOAD_REG_ADDR(r3, .start_secondary_prolog)
         LOAD_REG_IMMEDIATE(r4, MSR_KERNEL)
-#ifdef CONFIG_PPC_ISERIES
-BEGIN_FW_FTR_SECTION
-        ori     r4,r4,MSR_EE
-        li      r8,1
-        stb     r8,PACAHARDIRQEN(r13)
-END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES)
-#endif
-BEGIN_FW_FTR_SECTION
-        stb     r7,PACAHARDIRQEN(r13)
-END_FW_FTR_SECTION_IFCLR(FW_FEATURE_ISERIES)
-        stb     r7,PACASOFTIRQEN(r13)
 
         mtspr   SPRN_SRR0,r3
         mtspr   SPRN_SRR1,r4
@@ -771,22 +755,18 @@ _INIT_GLOBAL(start_here_common)
         /* Load the TOC (virtual address) */
         ld      r2,PACATOC(r13)
 
+        /* Do more system initializations in virtual mode */
         bl      .setup_system
 
-        /* Load up the kernel context */
-5:
-        li      r5,0
-        stb     r5,PACASOFTIRQEN(r13)   /* Soft Disabled */
-#ifdef CONFIG_PPC_ISERIES
-BEGIN_FW_FTR_SECTION
-        mfmsr   r5
-        ori     r5,r5,MSR_EE            /* Hard Enabled on iSeries*/
-        mtmsrd  r5
-        li      r5,1
-END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES)
-#endif
-        stb     r5,PACAHARDIRQEN(r13)   /* Hard Disabled on others */
+        /* Mark interrupts soft and hard disabled (they might be enabled
+         * in the PACA when doing hotplug)
+         */
+        li      r0,0
+        stb     r0,PACASOFTIRQEN(r13)
+        li      r0,PACA_IRQ_HARD_DIS
+        stb     r0,PACAIRQHAPPENED(r13)
 
+        /* Generic kernel entry */
         bl      .start_kernel
 
         /* Not reached */
diff --git a/arch/powerpc/kernel/head_8xx.S b/arch/powerpc/kernel/head_8xx.S
index b68cb173ba2..b2a5860accf 100644
--- a/arch/powerpc/kernel/head_8xx.S
+++ b/arch/powerpc/kernel/head_8xx.S
@@ -220,7 +220,7 @@ DataAccess:
         mfspr   r4,SPRN_DAR
         li      r10,0x00f0
         mtspr   SPRN_DAR,r10    /* Tag DAR, to be used in DTLB Error */
-        EXC_XFER_EE_LITE(0x300, handle_page_fault)
+        EXC_XFER_LITE(0x300, handle_page_fault)
 
 /* Instruction access exception.
  * This is "never generated" by the MPC8xx.  We jump to it for other
@@ -231,7 +231,7 @@ InstructionAccess:
         EXCEPTION_PROLOG
         mr      r4,r12
         mr      r5,r9
-        EXC_XFER_EE_LITE(0x400, handle_page_fault)
+        EXC_XFER_LITE(0x400, handle_page_fault)
 
 /* External interrupt */
         EXCEPTION(0x500, HardwareInterrupt, do_IRQ, EXC_XFER_LITE)
diff --git a/arch/powerpc/kernel/head_booke.h b/arch/powerpc/kernel/head_booke.h
index fc921bf62e1..0e4175388f4 100644
--- a/arch/powerpc/kernel/head_booke.h
+++ b/arch/powerpc/kernel/head_booke.h
@@ -359,7 +359,7 @@ label:
         mfspr   r5,SPRN_ESR;            /* Grab the ESR and save it */        \
         stw     r5,_ESR(r11);                                                 \
         mfspr   r4,SPRN_DEAR;           /* Grab the DEAR */                   \
-        EXC_XFER_EE_LITE(0x0300, handle_page_fault)
+        EXC_XFER_LITE(0x0300, handle_page_fault)
 
 #define INSTRUCTION_STORAGE_EXCEPTION                                         \
         START_EXCEPTION(InstructionStorage)                                   \
@@ -368,7 +368,7 @@ label:
         stw     r5,_ESR(r11);                                                 \
         mr      r4,r12;                 /* Pass SRR0 as arg2 */               \
         li      r5,0;                   /* Pass zero as arg3 */               \
-        EXC_XFER_EE_LITE(0x0400, handle_page_fault)
+        EXC_XFER_LITE(0x0400, handle_page_fault)
 
 #define ALIGNMENT_EXCEPTION                                                   \
         START_EXCEPTION(Alignment)                                            \
diff --git a/arch/powerpc/kernel/head_fsl_booke.S b/arch/powerpc/kernel/head_fsl_booke.S
index d5d78c4ceef..28e62598d0e 100644
--- a/arch/powerpc/kernel/head_fsl_booke.S
+++ b/arch/powerpc/kernel/head_fsl_booke.S
@@ -319,7 +319,7 @@ interrupt_base:
         mfspr   r4,SPRN_DEAR            /* Grab the DEAR, save it, pass arg2 */
         andis.  r10,r5,(ESR_ILK|ESR_DLK)@h
         bne     1f
-        EXC_XFER_EE_LITE(0x0300, handle_page_fault)
+        EXC_XFER_LITE(0x0300, handle_page_fault)
 1:
         addi    r3,r1,STACK_FRAME_OVERHEAD
         EXC_XFER_EE_LITE(0x0300, CacheLockingException)
diff --git a/arch/powerpc/kernel/idle.c b/arch/powerpc/kernel/idle.c
index c97fc60c790..e8e821146f3 100644
--- a/arch/powerpc/kernel/idle.c
+++ b/arch/powerpc/kernel/idle.c
@@ -84,7 +84,11 @@ void cpu_idle(void)
 
                                 start_critical_timings();
 
-                                local_irq_enable();
+                                /* Some power_save functions return with
+                                 * interrupts enabled, some don't.
+                                 */
+                                if (irqs_disabled())
+                                        local_irq_enable();
                                 set_thread_flag(TIF_POLLING_NRFLAG);
 
                         } else {
diff --git a/arch/powerpc/kernel/idle_book3e.S b/arch/powerpc/kernel/idle_book3e.S
index 16c002d6bdf..ff007b59448 100644
--- a/arch/powerpc/kernel/idle_book3e.S
+++ b/arch/powerpc/kernel/idle_book3e.S
@@ -29,43 +29,30 @@ _GLOBAL(book3e_idle)
         wrteei  0
 
         /* Now check if an interrupt came in while we were soft disabled
-         * since we may otherwise lose it (doorbells etc...). We know
-         * that since PACAHARDIRQEN will have been cleared in that case.
+         * since we may otherwise lose it (doorbells etc...).
          */
-        lbz     r3,PACAHARDIRQEN(r13)
+        lbz     r3,PACAIRQHAPPENED(r13)
         cmpwi   cr0,r3,0
-        beqlr
+        bnelr
 
-        /* Now we are going to mark ourselves as soft and hard enables in
+        /* Now we are going to mark ourselves as soft and hard enabled in
          * order to be able to take interrupts while asleep. We inform lockdep
          * of that. We don't actually turn interrupts on just yet tho.
          */
 #ifdef CONFIG_TRACE_IRQFLAGS
         stdu    r1,-128(r1)
         bl      .trace_hardirqs_on
+        addi    r1,r1,128
 #endif
         li      r0,1
         stb     r0,PACASOFTIRQEN(r13)
-        stb     r0,PACAHARDIRQEN(r13)
         
         /* Interrupts will make use return to LR, so get something we want
          * in there
          */
         bl      1f
 
-        /* Hard disable interrupts again */
-        wrteei  0
-
-        /* Mark them off again in the PACA as well */
-        li      r0,0
-        stb     r0,PACASOFTIRQEN(r13)
-        stb     r0,PACAHARDIRQEN(r13)
-
-        /* Tell lockdep about it */
-#ifdef CONFIG_TRACE_IRQFLAGS
-        bl      .trace_hardirqs_off
-        addi    r1,r1,128
-#endif
+        /* And return (interrupts are on) */
         ld      r0,16(r1)
         mtlr    r0
         blr
diff --git a/arch/powerpc/kernel/idle_power4.S b/arch/powerpc/kernel/idle_power4.S
index ba319547860..2c71b0fc9f9 100644
--- a/arch/powerpc/kernel/idle_power4.S
+++ b/arch/powerpc/kernel/idle_power4.S
@@ -14,6 +14,7 @@
 #include <asm/thread_info.h>
 #include <asm/ppc_asm.h>
 #include <asm/asm-offsets.h>
+#include <asm/irqflags.h>
 
 #undef DEBUG
 
@@ -29,14 +30,31 @@ END_FTR_SECTION_IFCLR(CPU_FTR_CAN_NAP)
         cmpwi   0,r4,0
         beqlr
 
-        /* Go to NAP now */
+        /* Hard disable interrupts */
         mfmsr   r7
         rldicl  r0,r7,48,1
         rotldi  r0,r0,16
-        mtmsrd  r0,1                    /* hard-disable interrupts */
+        mtmsrd  r0,1
+
+        /* Check if something happened while soft-disabled */
+        lbz     r0,PACAIRQHAPPENED(r13)
+        cmpwi   cr0,r0,0
+        bnelr
+
+        /* Soft-enable interrupts */
+#ifdef CONFIG_TRACE_IRQFLAGS
+        mflr    r0
+        std     r0,16(r1)
+        stdu    r1,-128(r1)
+        bl      .trace_hardirqs_on
+        addi    r1,r1,128
+        ld      r0,16(r1)
+        mtlr    r0
+        mfmsr   r7
+#endif /* CONFIG_TRACE_IRQFLAGS */
+
         li      r0,1
         stb     r0,PACASOFTIRQEN(r13)   /* we'll hard-enable shortly */
-        stb     r0,PACAHARDIRQEN(r13)
 BEGIN_FTR_SECTION
         DSSALL
         sync
diff --git a/arch/powerpc/kernel/idle_power7.S b/arch/powerpc/kernel/idle_power7.S
index fcdff198da4..0cdc9a39283 100644
--- a/arch/powerpc/kernel/idle_power7.S
+++ b/arch/powerpc/kernel/idle_power7.S
@@ -1,5 +1,5 @@
 /*
- *  This file contains the power_save function for 970-family CPUs.
+ *  This file contains the power_save function for Power7 CPUs.
  *
  *  This program is free software; you can redistribute it and/or
  *  modify it under the terms of the GNU General Public License
@@ -15,6 +15,7 @@
 #include <asm/ppc_asm.h>
 #include <asm/asm-offsets.h>
 #include <asm/ppc-opcode.h>
+#include <asm/hw_irq.h>
 
 #undef DEBUG
 
@@ -51,9 +52,25 @@ _GLOBAL(power7_idle)
         rldicl  r9,r9,48,1
         rotldi  r9,r9,16
         mtmsrd  r9,1                    /* hard-disable interrupts */
+
+        /* Check if something happened while soft-disabled */
+        lbz     r0,PACAIRQHAPPENED(r13)
+        cmpwi   cr0,r0,0
+        beq     1f
+        addi    r1,r1,INT_FRAME_SIZE
+        ld      r0,16(r1)
+        mtlr    r0
+        blr
+
+1:      /* We mark irqs hard disabled as this is the state we'll
+         * be in when returning and we need to tell arch_local_irq_restore()
+         * about it
+         */
+        li      r0,PACA_IRQ_HARD_DIS
+        stb     r0,PACAIRQHAPPENED(r13)
+
+        /* We haven't lost state ... yet */
         li      r0,0
-        stb     r0,PACASOFTIRQEN(r13)   /* we'll hard-enable shortly */
-        stb     r0,PACAHARDIRQEN(r13)
         stb     r0,PACA_NAPSTATELOST(r13)
 
         /* Continue saving state */
diff --git a/arch/powerpc/kernel/iommu.c b/arch/powerpc/kernel/iommu.c
index 0cfcf98aafc..359f078571c 100644
--- a/arch/powerpc/kernel/iommu.c
+++ b/arch/powerpc/kernel/iommu.c
@@ -39,6 +39,7 @@
 #include <asm/pci-bridge.h>
 #include <asm/machdep.h>
 #include <asm/kdump.h>
+#include <asm/fadump.h>
 
 #define DBG(...)
 
@@ -445,7 +446,12 @@ void iommu_unmap_sg(struct iommu_table *tbl, struct scatterlist *sglist,
 
 static void iommu_table_clear(struct iommu_table *tbl)
 {
-        if (!is_kdump_kernel()) {
+        /*
+         * In case of firmware assisted dump system goes through clean
+         * reboot process at the time of system crash. Hence it's safe to
+         * clear the TCE entries if firmware assisted dump is active.
+         */
+        if (!is_kdump_kernel() || is_fadump_active()) {
                 /* Clear the table in case firmware left allocations in it */
                 ppc_md.tce_free(tbl, tbl->it_offset, tbl->it_size);
                 return;
diff --git a/arch/powerpc/kernel/irq.c b/arch/powerpc/kernel/irq.c
index bdfb3eee3e6..a3d128e94cf 100644
--- a/arch/powerpc/kernel/irq.c
+++ b/arch/powerpc/kernel/irq.c
@@ -93,20 +93,16 @@ extern int tau_interrupts(int);
 
 #ifdef CONFIG_PPC64
 
-#ifndef CONFIG_SPARSE_IRQ
-EXPORT_SYMBOL(irq_desc);
-#endif
-
 int distribute_irqs = 1;
 
-static inline notrace unsigned long get_hard_enabled(void)
+static inline notrace unsigned long get_irq_happened(void)
 {
-        unsigned long enabled;
+        unsigned long happened;
 
         __asm__ __volatile__("lbz %0,%1(13)"
-        : "=r" (enabled) : "i" (offsetof(struct paca_struct, hard_enabled)));
+        : "=r" (happened) : "i" (offsetof(struct paca_struct, irq_happened)));
 
-        return enabled;
+        return happened;
 }
 
 static inline notrace void set_soft_enabled(unsigned long enable)
@@ -115,88 +111,162 @@ static inline notrace void set_soft_enabled(unsigned long enable)
         : : "r" (enable), "i" (offsetof(struct paca_struct, soft_enabled)));
 }
 
-static inline notrace void decrementer_check_overflow(void)
+static inline notrace int decrementer_check_overflow(void)
 {
-        u64 now = get_tb_or_rtc();
-        u64 *next_tb;
-
-        preempt_disable();
-        next_tb = &__get_cpu_var(decrementers_next_tb);
-
+        u64 now = get_tb_or_rtc();
+        u64 *next_tb = &__get_cpu_var(decrementers_next_tb);
+ 
         if (now >= *next_tb)
                 set_dec(1);
-        preempt_enable();
+        return now >= *next_tb;
 }
 
-notrace void arch_local_irq_restore(unsigned long en)
+/* This is called whenever we are re-enabling interrupts
+ * and returns either 0 (nothing to do) or 500/900 if there's
+ * either an EE or a DEC to generate.
+ *
+ * This is called in two contexts: From arch_local_irq_restore()
+ * before soft-enabling interrupts, and from the exception exit
+ * path when returning from an interrupt from a soft-disabled to
+ * a soft enabled context. In both case we have interrupts hard
+ * disabled.
+ *
+ * We take care of only clearing the bits we handled in the
+ * PACA irq_happened field since we can only re-emit one at a
+ * time and we don't want to "lose" one.
+ */
+notrace unsigned int __check_irq_replay(void)
 {
         /*
-         * get_paca()->soft_enabled = en;
-         * Is it ever valid to use local_irq_restore(0) when soft_enabled is 1?
-         * That was allowed before, and in such a case we do need to take care
-         * that gcc will set soft_enabled directly via r13, not choose to use
-         * an intermediate register, lest we're preempted to a different cpu.
+         * We use local_paca rather than get_paca() to avoid all
+         * the debug_smp_processor_id() business in this low level
+         * function
          */
-        set_soft_enabled(en);
-        if (!en)
-                return;
+        unsigned char happened = local_paca->irq_happened;
 
-#ifdef CONFIG_PPC_STD_MMU_64
-        if (firmware_has_feature(FW_FEATURE_ISERIES)) {
-                /*
-                 * Do we need to disable preemption here?  Not really: in the
-                 * unlikely event that we're preempted to a different cpu in
-                 * between getting r13, loading its lppaca_ptr, and loading
-                 * its any_int, we might call iseries_handle_interrupts without
-                 * an interrupt pending on the new cpu, but that's no disaster,
-                 * is it?  And the business of preempting us off the old cpu
-                 * would itself involve a local_irq_restore which handles the
-                 * interrupt to that cpu.
-                 *
-                 * But use "local_paca->lppaca_ptr" instead of "get_lppaca()"
-                 * to avoid any preemption checking added into get_paca().
-                 */
-                if (local_paca->lppaca_ptr->int_dword.any_int)
-                        iseries_handle_interrupts();
+        /* Clear bit 0 which we wouldn't clear otherwise */
+        local_paca->irq_happened &= ~PACA_IRQ_HARD_DIS;
+
+        /*
+         * Force the delivery of pending soft-disabled interrupts on PS3.
+         * Any HV call will have this side effect.
+         */
+        if (firmware_has_feature(FW_FEATURE_PS3_LV1)) {
+                u64 tmp, tmp2;
+                lv1_get_version_info(&tmp, &tmp2);
         }
-#endif /* CONFIG_PPC_STD_MMU_64 */
 
         /*
-         * if (get_paca()->hard_enabled) return;
-         * But again we need to take care that gcc gets hard_enabled directly
-         * via r13, not choose to use an intermediate register, lest we're
-         * preempted to a different cpu in between the two instructions.
+         * We may have missed a decrementer interrupt. We check the
+         * decrementer itself rather than the paca irq_happened field
+         * in case we also had a rollover while hard disabled
+         */
+        local_paca->irq_happened &= ~PACA_IRQ_DEC;
+        if (decrementer_check_overflow())
+                return 0x900;
+
+        /* Finally check if an external interrupt happened */
+        local_paca->irq_happened &= ~PACA_IRQ_EE;
+        if (happened & PACA_IRQ_EE)
+                return 0x500;
+
+#ifdef CONFIG_PPC_BOOK3E
+        /* Finally check if an EPR external interrupt happened
+         * this bit is typically set if we need to handle another
+         * "edge" interrupt from within the MPIC "EPR" handler
          */
-        if (get_hard_enabled())
+        local_paca->irq_happened &= ~PACA_IRQ_EE_EDGE;
+        if (happened & PACA_IRQ_EE_EDGE)
+                return 0x500;
+
+        local_paca->irq_happened &= ~PACA_IRQ_DBELL;
+        if (happened & PACA_IRQ_DBELL)
+                return 0x280;
+#endif /* CONFIG_PPC_BOOK3E */
+
+        /* There should be nothing left ! */
+        BUG_ON(local_paca->irq_happened != 0);
+
+        return 0;
+}
+
+notrace void arch_local_irq_restore(unsigned long en)
+{
+        unsigned char irq_happened;
+        unsigned int replay;
+
+        /* Write the new soft-enabled value */
+        set_soft_enabled(en);
+        if (!en)
+                return;
+        /*
+         * From this point onward, we can take interrupts, preempt,
+         * etc... unless we got hard-disabled. We check if an event
+         * happened. If none happened, we know we can just return.
+         *
+         * We may have preempted before the check below, in which case
+         * we are checking the "new" CPU instead of the old one. This
+         * is only a problem if an event happened on the "old" CPU.
+         *
+         * External interrupt events on non-iseries will have caused
+         * interrupts to be hard-disabled, so there is no problem, we
+         * cannot have preempted.
+         */
+        irq_happened = get_irq_happened();
+        if (!irq_happened)
                 return;
 
         /*
-         * Need to hard-enable interrupts here.  Since currently disabled,
-         * no need to take further asm precautions against preemption; but
-         * use local_paca instead of get_paca() to avoid preemption checking.
+         * We need to hard disable to get a trusted value from
+         * __check_irq_replay(). We also need to soft-disable
+         * again to avoid warnings in there due to the use of
+         * per-cpu variables.
+         *
+         * We know that if the value in irq_happened is exactly 0x01
+         * then we are already hard disabled (there are other less
+         * common cases that we'll ignore for now), so we skip the
+         * (expensive) mtmsrd.
          */
-        local_paca->hard_enabled = en;
+        if (unlikely(irq_happened != PACA_IRQ_HARD_DIS))
+                __hard_irq_disable();
+        set_soft_enabled(0);
 
         /*
-         * Trigger the decrementer if we have a pending event. Some processors
-         * only trigger on edge transitions of the sign bit. We might also
-         * have disabled interrupts long enough that the decrementer wrapped
-         * to positive.
+         * Check if anything needs to be re-emitted. We haven't
+         * soft-enabled yet to avoid warnings in decrementer_check_overflow
+         * accessing per-cpu variables
          */
-        decrementer_check_overflow();
+        replay = __check_irq_replay();
+
+        /* We can soft-enable now */
+        set_soft_enabled(1);
 
         /*
-         * Force the delivery of pending soft-disabled interrupts on PS3.
-         * Any HV call will have this side effect.
+         * And replay if we have to. This will return with interrupts
+         * hard-enabled.
          */
-        if (firmware_has_feature(FW_FEATURE_PS3_LV1)) {
-                u64 tmp, tmp2;
-                lv1_get_version_info(&tmp, &tmp2);
+        if (replay) {
+                __replay_interrupt(replay);
+                return;
         }
 
+        /* Finally, let's ensure we are hard enabled */
         __hard_irq_enable();
 }
 EXPORT_SYMBOL(arch_local_irq_restore);
+
+/*
+ * This is specifically called by assembly code to re-enable interrupts
+ * if they are currently disabled. This is typically called before
+ * schedule() or do_signal() when returning to userspace. We do it
+ * in C to avoid the burden of dealing with lockdep etc...
+ */
+void restore_interrupts(void)
+{
+        if (irqs_disabled())
+                local_irq_enable();
+}
+
 #endif /* CONFIG_PPC64 */
 
 int arch_show_interrupts(struct seq_file *p, int prec)
@@ -364,8 +434,17 @@ void do_IRQ(struct pt_regs *regs)
 
         check_stack_overflow();
 
+        /*
+         * Query the platform PIC for the interrupt & ack it.
+         *
+         * This will typically lower the interrupt line to the CPU
+         */
         irq = ppc_md.get_irq();
 
+        /* We can hard enable interrupts now */
+        may_hard_irq_enable();
+
+        /* And finally process it */
         if (irq != NO_IRQ && irq != NO_IRQ_IGNORE)
                 handle_one_irq(irq);
         else if (irq != NO_IRQ_IGNORE)
@@ -374,15 +453,6 @@ void do_IRQ(struct pt_regs *regs)
         irq_exit();
         set_irq_regs(old_regs);
 
-#ifdef CONFIG_PPC_ISERIES
-        if (firmware_has_feature(FW_FEATURE_ISERIES) &&
-                        get_lppaca()->int_dword.fields.decr_int) {
-                get_lppaca()->int_dword.fields.decr_int = 0;
-                /* Signal a fake decrementer interrupt */
-                timer_interrupt(regs);
-        }
-#endif
-
         trace_irq_exit(regs);
 }
 
diff --git a/arch/powerpc/kernel/isa-bridge.c b/arch/powerpc/kernel/isa-bridge.c
index 479752901ec..d45ec58703c 100644
--- a/arch/powerpc/kernel/isa-bridge.c
+++ b/arch/powerpc/kernel/isa-bridge.c
@@ -29,7 +29,6 @@
 #include <asm/pci-bridge.h>
 #include <asm/machdep.h>
 #include <asm/ppc-pci.h>
-#include <asm/firmware.h>
 
 unsigned long isa_io_base;      /* NULL if no ISA bus */
 EXPORT_SYMBOL(isa_io_base);
@@ -261,8 +260,6 @@ static struct notifier_block isa_bridge_notifier = {
  */
 static int __init isa_bridge_init(void)
 {
-        if (firmware_has_feature(FW_FEATURE_ISERIES))
-                return 0;
         bus_register_notifier(&pci_bus_type, &isa_bridge_notifier);
         return 0;
 }
diff --git a/arch/powerpc/kernel/lparcfg.c b/arch/powerpc/kernel/lparcfg.c
index 578f35f1872..ac12bd80ad9 100644
--- a/arch/powerpc/kernel/lparcfg.c
+++ b/arch/powerpc/kernel/lparcfg.c
@@ -26,7 +26,6 @@
 #include <linux/seq_file.h>
 #include <linux/slab.h>
 #include <asm/uaccess.h>
-#include <asm/iseries/hv_lp_config.h>
 #include <asm/lppaca.h>
 #include <asm/hvcall.h>
 #include <asm/firmware.h>
@@ -55,80 +54,14 @@ static unsigned long get_purr(void)
         int cpu;
 
         for_each_possible_cpu(cpu) {
-                if (firmware_has_feature(FW_FEATURE_ISERIES))
-                        sum_purr += lppaca_of(cpu).emulated_time_base;
-                else {
-                        struct cpu_usage *cu;
+                struct cpu_usage *cu;
 
-                        cu = &per_cpu(cpu_usage_array, cpu);
-                        sum_purr += cu->current_tb;
-                }
+                cu = &per_cpu(cpu_usage_array, cpu);
+                sum_purr += cu->current_tb;
         }
         return sum_purr;
 }
 
-#ifdef CONFIG_PPC_ISERIES
-
-/*
- * Methods used to fetch LPAR data when running on an iSeries platform.
- */
-static int iseries_lparcfg_data(struct seq_file *m, void *v)
-{
-        unsigned long pool_id;
-        int shared, entitled_capacity, max_entitled_capacity;
-        int processors, max_processors;
-        unsigned long purr = get_purr();
-
-        shared = (int)(local_paca->lppaca_ptr->shared_proc);
-
-        seq_printf(m, "system_active_processors=%d\n",
-                   (int)HvLpConfig_getSystemPhysicalProcessors());
-
-        seq_printf(m, "system_potential_processors=%d\n",
-                   (int)HvLpConfig_getSystemPhysicalProcessors());
-
-        processors = (int)HvLpConfig_getPhysicalProcessors();
-        seq_printf(m, "partition_active_processors=%d\n", processors);
-
-        max_processors = (int)HvLpConfig_getMaxPhysicalProcessors();
-        seq_printf(m, "partition_potential_processors=%d\n", max_processors);
-
-        if (shared) {
-                entitled_capacity = HvLpConfig_getSharedProcUnits();
-                max_entitled_capacity = HvLpConfig_getMaxSharedProcUnits();
-        } else {
-                entitled_capacity = processors * 100;
-                max_entitled_capacity = max_processors * 100;
-        }
-        seq_printf(m, "partition_entitled_capacity=%d\n", entitled_capacity);
-
-        seq_printf(m, "partition_max_entitled_capacity=%d\n",
-                   max_entitled_capacity);
-
-        if (shared) {
-                pool_id = HvLpConfig_getSharedPoolIndex();
-                seq_printf(m, "pool=%d\n", (int)pool_id);
-                seq_printf(m, "pool_capacity=%d\n",
-                           (int)(HvLpConfig_getNumProcsInSharedPool(pool_id) *
-                                 100));
-                seq_printf(m, "purr=%ld\n", purr);
-        }
-
-        seq_printf(m, "shared_processor_mode=%d\n", shared);
-
-        return 0;
-}
-
-#else                           /* CONFIG_PPC_ISERIES */
-
-static int iseries_lparcfg_data(struct seq_file *m, void *v)
-{
-        return 0;
-}
-
-#endif                          /* CONFIG_PPC_ISERIES */
-
-#ifdef CONFIG_PPC_PSERIES
 /*
  * Methods used to fetch LPAR data when running on a pSeries platform.
  */
@@ -648,8 +581,7 @@ static ssize_t lparcfg_write(struct file *file, const char __user * buf,
         u8 new_weight, *new_weight_ptr = &new_weight;
         ssize_t retval;
 
-        if (!firmware_has_feature(FW_FEATURE_SPLPAR) ||
-                        firmware_has_feature(FW_FEATURE_ISERIES))
+        if (!firmware_has_feature(FW_FEATURE_SPLPAR))
                 return -EINVAL;
 
         if (count > kbuf_sz)
@@ -709,21 +641,6 @@ static ssize_t lparcfg_write(struct file *file, const char __user * buf,
         return retval;
 }
 
-#else                           /* CONFIG_PPC_PSERIES */
-
-static int pseries_lparcfg_data(struct seq_file *m, void *v)
-{
-        return 0;
-}
-
-static ssize_t lparcfg_write(struct file *file, const char __user * buf,
-                             size_t count, loff_t * off)
-{
-        return -EINVAL;
-}
-
-#endif                          /* CONFIG_PPC_PSERIES */
-
 static int lparcfg_data(struct seq_file *m, void *v)
 {
         struct device_node *rootdn;
@@ -738,19 +655,11 @@ static int lparcfg_data(struct seq_file *m, void *v)
         rootdn = of_find_node_by_path("/");
         if (rootdn) {
                 tmp = of_get_property(rootdn, "model", NULL);
-                if (tmp) {
+                if (tmp)
                         model = tmp;
-                        /* Skip "IBM," - see platforms/iseries/dt.c */
-                        if (firmware_has_feature(FW_FEATURE_ISERIES))
-                                model += 4;
-                }
                 tmp = of_get_property(rootdn, "system-id", NULL);
-                if (tmp) {
+                if (tmp)
                         system_id = tmp;
-                        /* Skip "IBM," - see platforms/iseries/dt.c */
-                        if (firmware_has_feature(FW_FEATURE_ISERIES))
-                                system_id += 4;
-                }
                 lp_index_ptr = of_get_property(rootdn, "ibm,partition-no",
                                         NULL);
                 if (lp_index_ptr)
@@ -761,8 +670,6 @@ static int lparcfg_data(struct seq_file *m, void *v)
         seq_printf(m, "system_type=%s\n", model);
         seq_printf(m, "partition_id=%d\n", (int)lp_index);
 
-        if (firmware_has_feature(FW_FEATURE_ISERIES))
-                return iseries_lparcfg_data(m, v);
         return pseries_lparcfg_data(m, v);
 }
 
@@ -786,8 +693,7 @@ static int __init lparcfg_init(void)
         umode_t mode = S_IRUSR | S_IRGRP | S_IROTH;
 
         /* Allow writing if we have FW_FEATURE_SPLPAR */
-        if (firmware_has_feature(FW_FEATURE_SPLPAR) &&
-                        !firmware_has_feature(FW_FEATURE_ISERIES))
+        if (firmware_has_feature(FW_FEATURE_SPLPAR))
                 mode |= S_IWUSR;
 
         ent = proc_create("powerpc/lparcfg", mode, NULL, &lparcfg_fops);
diff --git a/arch/powerpc/kernel/misc.S b/arch/powerpc/kernel/misc.S
index b69463ec201..ba16874fe29 100644
--- a/arch/powerpc/kernel/misc.S
+++ b/arch/powerpc/kernel/misc.S
@@ -5,7 +5,6 @@
  * Largely rewritten by Cort Dougan (cort@cs.nmt.edu)
  * and Paul Mackerras.
  *
- * Adapted for iSeries by Mike Corrigan (mikejc@us.ibm.com)
  * PPC64 updates by Dave Engebretsen (engebret@us.ibm.com)
  *
  * setjmp/longjmp code by Paul Mackerras.
diff --git a/arch/powerpc/kernel/of_platform.c b/arch/powerpc/kernel/of_platform.c
index e1612dfb4a9..2049f2d00ff 100644
--- a/arch/powerpc/kernel/of_platform.c
+++ b/arch/powerpc/kernel/of_platform.c
@@ -21,12 +21,13 @@
 #include <linux/of.h>
 #include <linux/of_device.h>
 #include <linux/of_platform.h>
+#include <linux/atomic.h>
 
 #include <asm/errno.h>
 #include <asm/topology.h>
 #include <asm/pci-bridge.h>
 #include <asm/ppc-pci.h>
-#include <linux/atomic.h>
+#include <asm/eeh.h>
 
 #ifdef CONFIG_PPC_OF_PLATFORM_PCI
 
@@ -66,6 +67,9 @@ static int __devinit of_pci_phb_probe(struct platform_device *dev)
         /* Init pci_dn data structures */
         pci_devs_phb_init_dynamic(phb);
 
+        /* Create EEH devices for the PHB */
+        eeh_dev_phb_init_dynamic(phb);
+
         /* Register devices with EEH */
 #ifdef CONFIG_EEH
         if (dev->dev.of_node->child)
diff --git a/arch/powerpc/kernel/paca.c b/arch/powerpc/kernel/paca.c
index 41456ff55e1..0bb1f98613b 100644
--- a/arch/powerpc/kernel/paca.c
+++ b/arch/powerpc/kernel/paca.c
@@ -11,13 +11,10 @@
 #include <linux/export.h>
 #include <linux/memblock.h>
 
-#include <asm/firmware.h>
 #include <asm/lppaca.h>
 #include <asm/paca.h>
 #include <asm/sections.h>
 #include <asm/pgtable.h>
-#include <asm/iseries/lpar_map.h>
-#include <asm/iseries/hv_types.h>
 #include <asm/kexec.h>
 
 /* This symbol is provided by the linker - let it fill in the paca
@@ -30,8 +27,8 @@ extern unsigned long __toc_start;
  * The structure which the hypervisor knows about - this structure
  * should not cross a page boundary.  The vpa_init/register_vpa call
  * is now known to fail if the lppaca structure crosses a page
- * boundary.  The lppaca is also used on legacy iSeries and POWER5
- * pSeries boxes.  The lppaca is 640 bytes long, and cannot readily
+ * boundary.  The lppaca is also used on POWER5 pSeries boxes.
+ * The lppaca is 640 bytes long, and cannot readily
  * change since the hypervisor knows its layout, so a 1kB alignment
  * will suffice to ensure that it doesn't cross a page boundary.
  */
@@ -183,12 +180,9 @@ void __init allocate_pacas(void)
         /*
          * We can't take SLB misses on the paca, and we want to access them
          * in real mode, so allocate them within the RMA and also within
-         * the first segment. On iSeries they must be within the area mapped
-         * by the HV, which is HvPagesToMap * HVPAGESIZE bytes.
+         * the first segment.
          */
         limit = min(0x10000000ULL, ppc64_rma_size);
-        if (firmware_has_feature(FW_FEATURE_ISERIES))
-                limit = min(limit, HvPagesToMap * HVPAGESIZE);
 
         paca_size = PAGE_ALIGN(sizeof(struct paca_struct) * nr_cpu_ids);
 
diff --git a/arch/powerpc/kernel/pci-common.c b/arch/powerpc/kernel/pci-common.c
index cce98d76e90..8e78e93c818 100644
--- a/arch/powerpc/kernel/pci-common.c
+++ b/arch/powerpc/kernel/pci-common.c
@@ -38,7 +38,6 @@
 #include <asm/byteorder.h>
 #include <asm/machdep.h>
 #include <asm/ppc-pci.h>
-#include <asm/firmware.h>
 #include <asm/eeh.h>
 
 static DEFINE_SPINLOCK(hose_spinlock);
@@ -50,9 +49,6 @@ static int global_phb_number;		/* Global phb counter */
 /* ISA Memory physical address */
 resource_size_t isa_mem_base;
 
-/* Default PCI flags is 0 on ppc32, modified at boot on ppc64 */
-unsigned int pci_flags = 0;
-
 
 static struct dma_map_ops *pci_dma_ops = &dma_direct_ops;
 
@@ -219,20 +215,6 @@ static int pci_read_irq_line(struct pci_dev *pci_dev)
         struct of_irq oirq;
         unsigned int virq;
 
-        /* The current device-tree that iSeries generates from the HV
-         * PCI informations doesn't contain proper interrupt routing,
-         * and all the fallback would do is print out crap, so we
-         * don't attempt to resolve the interrupts here at all, some
-         * iSeries specific fixup does it.
-         *
-         * In the long run, we will hopefully fix the generated device-tree
-         * instead.
-         */
-#ifdef CONFIG_PPC_ISERIES
-        if (firmware_has_feature(FW_FEATURE_ISERIES))
-                return -1;
-#endif
-
         pr_debug("PCI: Try to map irq for %s...\n", pci_name(pci_dev));
 
 #ifdef DEBUG
@@ -849,60 +831,6 @@ int pci_proc_domain(struct pci_bus *bus)
         return 1;
 }
 
-void pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
-                             struct resource *res)
-{
-        resource_size_t offset = 0, mask = (resource_size_t)-1;
-        struct pci_controller *hose = pci_bus_to_host(dev->bus);
-
-        if (!hose)
-                return;
-        if (res->flags & IORESOURCE_IO) {
-                offset = (unsigned long)hose->io_base_virt - _IO_BASE;
-                mask = 0xffffffffu;
-        } else if (res->flags & IORESOURCE_MEM)
-                offset = hose->pci_mem_offset;
-
-        region->start = (res->start - offset) & mask;
-        region->end = (res->end - offset) & mask;
-}
-EXPORT_SYMBOL(pcibios_resource_to_bus);
-
-void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
-                             struct pci_bus_region *region)
-{
-        resource_size_t offset = 0, mask = (resource_size_t)-1;
-        struct pci_controller *hose = pci_bus_to_host(dev->bus);
-
-        if (!hose)
-                return;
-        if (res->flags & IORESOURCE_IO) {
-                offset = (unsigned long)hose->io_base_virt - _IO_BASE;
-                mask = 0xffffffffu;
-        } else if (res->flags & IORESOURCE_MEM)
-                offset = hose->pci_mem_offset;
-        res->start = (region->start + offset) & mask;
-        res->end = (region->end + offset) & mask;
-}
-EXPORT_SYMBOL(pcibios_bus_to_resource);
-
-/* Fixup a bus resource into a linux resource */
-static void __devinit fixup_resource(struct resource *res, struct pci_dev *dev)
-{
-        struct pci_controller *hose = pci_bus_to_host(dev->bus);
-        resource_size_t offset = 0, mask = (resource_size_t)-1;
-
-        if (res->flags & IORESOURCE_IO) {
-                offset = (unsigned long)hose->io_base_virt - _IO_BASE;
-                mask = 0xffffffffu;
-        } else if (res->flags & IORESOURCE_MEM)
-                offset = hose->pci_mem_offset;
-
-        res->start = (res->start + offset) & mask;
-        res->end = (res->end + offset) & mask;
-}
-
-
 /* This header fixup will do the resource fixup for all devices as they are
  * probed, but not for bridge ranges
  */
@@ -942,18 +870,11 @@ static void __devinit pcibios_fixup_resources(struct pci_dev *dev)
                         continue;
                 }
 
-                pr_debug("PCI:%s Resource %d %016llx-%016llx [%x] fixup...\n",
+                pr_debug("PCI:%s Resource %d %016llx-%016llx [%x]\n",
                          pci_name(dev), i,
                          (unsigned long long)res->start,\
                          (unsigned long long)res->end,
                          (unsigned int)res->flags);
-
-                fixup_resource(res, dev);
-
-                pr_debug("PCI:%s            %016llx-%016llx\n",
-                         pci_name(dev),
-                         (unsigned long long)res->start,
-                         (unsigned long long)res->end);
         }
 
         /* Call machine specific resource fixup */
@@ -1055,27 +976,18 @@ static void __devinit pcibios_fixup_bridge(struct pci_bus *bus)
                         continue;
                 }
 
-                pr_debug("PCI:%s Bus rsrc %d %016llx-%016llx [%x] fixup...\n",
+                pr_debug("PCI:%s Bus rsrc %d %016llx-%016llx [%x]\n",
                          pci_name(dev), i,
                          (unsigned long long)res->start,\
                          (unsigned long long)res->end,
                          (unsigned int)res->flags);
 
-                /* Perform fixup */
-                fixup_resource(res, dev);
-
                 /* Try to detect uninitialized P2P bridge resources,
                  * and clear them out so they get re-assigned later
                  */
                 if (pcibios_uninitialized_bridge_resource(bus, res)) {
                         res->flags = 0;
                         pr_debug("PCI:%s            (unassigned)\n", pci_name(dev));
-                } else {
-
-                        pr_debug("PCI:%s            %016llx-%016llx\n",
-                                 pci_name(dev),
-                                 (unsigned long long)res->start,
-                                 (unsigned long long)res->end);
                 }
         }
 }
@@ -1565,6 +1477,11 @@ int pcibios_enable_device(struct pci_dev *dev, int mask)
         return pci_enable_resources(dev, mask);
 }
 
+resource_size_t pcibios_io_space_offset(struct pci_controller *hose)
+{
+        return (unsigned long) hose->io_base_virt - _IO_BASE;
+}
+
 static void __devinit pcibios_setup_phb_resources(struct pci_controller *hose, struct list_head *resources)
 {
         struct resource *res;
@@ -1589,7 +1506,7 @@ static void __devinit pcibios_setup_phb_resources(struct pci_controller *hose, s
                  (unsigned long long)res->start,
                  (unsigned long long)res->end,
                  (unsigned long)res->flags);
-        pci_add_resource(resources, res);
+        pci_add_resource_offset(resources, res, pcibios_io_space_offset(hose));
 
         /* Hookup PHB Memory resources */
         for (i = 0; i < 3; ++i) {
@@ -1612,7 +1529,7 @@ static void __devinit pcibios_setup_phb_resources(struct pci_controller *hose, s
                          (unsigned long long)res->start,
                          (unsigned long long)res->end,
                          (unsigned long)res->flags);
-                pci_add_resource(resources, res);
+                pci_add_resource_offset(resources, res, hose->pci_mem_offset);
         }
 
         pr_debug("PCI: PHB MEM offset     = %016llx\n",
diff --git a/arch/powerpc/kernel/pci_32.c b/arch/powerpc/kernel/pci_32.c
index fdd1a3d951d..4b06ec5a502 100644
--- a/arch/powerpc/kernel/pci_32.c
+++ b/arch/powerpc/kernel/pci_32.c
@@ -219,9 +219,9 @@ void __devinit pcibios_setup_phb_io_space(struct pci_controller *hose)
         struct resource *res = &hose->io_resource;
 
         /* Fixup IO space offset */
-        io_offset = (unsigned long)hose->io_base_virt - isa_io_base;
-        res->start = (res->start + io_offset) & 0xffffffffu;
-        res->end = (res->end + io_offset) & 0xffffffffu;
+        io_offset = pcibios_io_space_offset(hose);
+        res->start += io_offset;
+        res->end += io_offset;
 }
 
 static int __init pcibios_init(void)
diff --git a/arch/powerpc/kernel/pci_64.c b/arch/powerpc/kernel/pci_64.c
index 3318d39b7d4..94a54f61d34 100644
--- a/arch/powerpc/kernel/pci_64.c
+++ b/arch/powerpc/kernel/pci_64.c
@@ -33,8 +33,6 @@
 #include <asm/machdep.h>
 #include <asm/ppc-pci.h>
 
-unsigned long pci_probe_only = 1;
-
 /* pci_io_base -- the base address from which io bars are offsets.
  * This is the lowest I/O base address (so bar values are always positive),
  * and it *must* be the start of ISA space if an ISA bus exists because
@@ -55,9 +53,6 @@ static int __init pcibios_init(void)
          */
         ppc_md.phys_mem_access_prot = pci_phys_mem_access_prot;
 
-        if (pci_probe_only)
-                pci_add_flags(PCI_PROBE_ONLY);
-
         /* On ppc64, we always enable PCI domains and we keep domain 0
          * backward compatible in /proc for video cards
          */
@@ -173,7 +168,7 @@ static int __devinit pcibios_map_phb_io_space(struct pci_controller *hose)
                 return -ENOMEM;
 
         /* Fixup hose IO resource */
-        io_virt_offset = (unsigned long)hose->io_base_virt - _IO_BASE;
+        io_virt_offset = pcibios_io_space_offset(hose);
         hose->io_resource.start += io_virt_offset;
         hose->io_resource.end += io_virt_offset;
 
diff --git a/arch/powerpc/kernel/pci_of_scan.c b/arch/powerpc/kernel/pci_of_scan.c
index b37d0b5a796..89dde171a6f 100644
--- a/arch/powerpc/kernel/pci_of_scan.c
+++ b/arch/powerpc/kernel/pci_of_scan.c
@@ -75,6 +75,7 @@ static void of_pci_parse_addrs(struct device_node *node, struct pci_dev *dev)
 {
         u64 base, size;
         unsigned int flags;
+        struct pci_bus_region region;
         struct resource *res;
         const u32 *addrs;
         u32 i;
@@ -106,10 +107,11 @@ static void of_pci_parse_addrs(struct device_node *node, struct pci_dev *dev)
                         printk(KERN_ERR "PCI: bad cfg reg num 0x%x\n", i);
                         continue;
                 }
-                res->start = base;
-                res->end = base + size - 1;
                 res->flags = flags;
                 res->name = pci_name(dev);
+                region.start = base;
+                region.end = base + size - 1;
+                pcibios_bus_to_resource(dev, res, &region);
         }
 }
 
@@ -209,6 +211,7 @@ void __devinit of_scan_pci_bridge(struct pci_dev *dev)
         struct pci_bus *bus;
         const u32 *busrange, *ranges;
         int len, i, mode;
+        struct pci_bus_region region;
         struct resource *res;
         unsigned int flags;
         u64 size;
@@ -270,9 +273,10 @@ void __devinit of_scan_pci_bridge(struct pci_dev *dev)
                         res = bus->resource[i];
                         ++i;
                 }
-                res->start = of_read_number(&ranges[1], 2);
-                res->end = res->start + size - 1;
                 res->flags = flags;
+                region.start = of_read_number(&ranges[1], 2);
+                region.end = region.start + size - 1;
+                pcibios_bus_to_resource(dev, res, &region);
         }
         sprintf(bus->name, "PCI Bus %04x:%02x", pci_domain_nr(bus),
                 bus->number);
diff --git a/arch/powerpc/kernel/pmc.c b/arch/powerpc/kernel/pmc.c
index a841a9d136a..58eaa3ddf7b 100644
--- a/arch/powerpc/kernel/pmc.c
+++ b/arch/powerpc/kernel/pmc.c
@@ -13,6 +13,7 @@
  */
 
 #include <linux/errno.h>
+#include <linux/bug.h>
 #include <linux/spinlock.h>
 #include <linux/export.h>
 
diff --git a/arch/powerpc/kernel/process.c b/arch/powerpc/kernel/process.c
index d817ab01848..e40707032ac 100644
--- a/arch/powerpc/kernel/process.c
+++ b/arch/powerpc/kernel/process.c
@@ -647,6 +647,9 @@ void show_regs(struct pt_regs * regs)
         printk("MSR: "REG" ", regs->msr);
         printbits(regs->msr, msr_bits);
         printk("  CR: %08lx  XER: %08lx\n", regs->ccr, regs->xer);
+#ifdef CONFIG_PPC64
+        printk("SOFTE: %ld\n", regs->softe);
+#endif
         trap = TRAP(regs);
         if ((regs->trap != 0xc00) && cpu_has_feature(CPU_FTR_CFAR))
                 printk("CFAR: "REG"\n", regs->orig_gpr3);
@@ -1220,34 +1223,32 @@ void dump_stack(void)
 EXPORT_SYMBOL(dump_stack);
 
 #ifdef CONFIG_PPC64
-void ppc64_runlatch_on(void)
+/* Called with hard IRQs off */
+void __ppc64_runlatch_on(void)
 {
+        struct thread_info *ti = current_thread_info();
         unsigned long ctrl;
 
-        if (cpu_has_feature(CPU_FTR_CTRL) && !test_thread_flag(TIF_RUNLATCH)) {
-                HMT_medium();
-
-                ctrl = mfspr(SPRN_CTRLF);
-                ctrl |= CTRL_RUNLATCH;
-                mtspr(SPRN_CTRLT, ctrl);
+        ctrl = mfspr(SPRN_CTRLF);
+        ctrl |= CTRL_RUNLATCH;
+        mtspr(SPRN_CTRLT, ctrl);
 
-                set_thread_flag(TIF_RUNLATCH);
-        }
+        ti->local_flags |= TLF_RUNLATCH;
 }
 
+/* Called with hard IRQs off */
 void __ppc64_runlatch_off(void)
 {
+        struct thread_info *ti = current_thread_info();
         unsigned long ctrl;
 
-        HMT_medium();
-
-        clear_thread_flag(TIF_RUNLATCH);
+        ti->local_flags &= ~TLF_RUNLATCH;
 
         ctrl = mfspr(SPRN_CTRLF);
         ctrl &= ~CTRL_RUNLATCH;
         mtspr(SPRN_CTRLT, ctrl);
 }
-#endif
+#endif /* CONFIG_PPC64 */
 
 #if THREAD_SHIFT < PAGE_SHIFT
 
diff --git a/arch/powerpc/kernel/prom.c b/arch/powerpc/kernel/prom.c
index abe405dab34..89e850af3dd 100644
--- a/arch/powerpc/kernel/prom.c
+++ b/arch/powerpc/kernel/prom.c
@@ -52,9 +52,9 @@
 #include <asm/machdep.h>
 #include <asm/pSeries_reconfig.h>
 #include <asm/pci-bridge.h>
-#include <asm/phyp_dump.h>
 #include <asm/kexec.h>
 #include <asm/opal.h>
+#include <asm/fadump.h>
 
 #include <mm/mmu_decl.h>
 
@@ -615,86 +615,6 @@ static void __init early_reserve_mem(void)
         }
 }
 
-#ifdef CONFIG_PHYP_DUMP
-/**
- * phyp_dump_calculate_reserve_size() - reserve variable boot area 5% or arg
- *
- * Function to find the largest size we need to reserve
- * during early boot process.
- *
- * It either looks for boot param and returns that OR
- * returns larger of 256 or 5% rounded down to multiples of 256MB.
- *
- */
-static inline unsigned long phyp_dump_calculate_reserve_size(void)
-{
-        unsigned long tmp;
-
-        if (phyp_dump_info->reserve_bootvar)
-                return phyp_dump_info->reserve_bootvar;
-
-        /* divide by 20 to get 5% of value */
-        tmp = memblock_end_of_DRAM();
-        do_div(tmp, 20);
-
-        /* round it down in multiples of 256 */
-        tmp = tmp & ~0x0FFFFFFFUL;
-
-        return (tmp > PHYP_DUMP_RMR_END ? tmp : PHYP_DUMP_RMR_END);
-}
-
-/**
- * phyp_dump_reserve_mem() - reserve all not-yet-dumped mmemory
- *
- * This routine may reserve memory regions in the kernel only
- * if the system is supported and a dump was taken in last
- * boot instance or if the hardware is supported and the
- * scratch area needs to be setup. In other instances it returns
- * without reserving anything. The memory in case of dump being
- * active is freed when the dump is collected (by userland tools).
- */
-static void __init phyp_dump_reserve_mem(void)
-{
-        unsigned long base, size;
-        unsigned long variable_reserve_size;
-
-        if (!phyp_dump_info->phyp_dump_configured) {
-                printk(KERN_ERR "Phyp-dump not supported on this hardware\n");
-                return;
-        }
-
-        if (!phyp_dump_info->phyp_dump_at_boot) {
-                printk(KERN_INFO "Phyp-dump disabled at boot time\n");
-                return;
-        }
-
-        variable_reserve_size = phyp_dump_calculate_reserve_size();
-
-        if (phyp_dump_info->phyp_dump_is_active) {
-                /* Reserve *everything* above RMR.Area freed by userland tools*/
-                base = variable_reserve_size;
-                size = memblock_end_of_DRAM() - base;
-
-                /* XXX crashed_ram_end is wrong, since it may be beyond
-                 * the memory_limit, it will need to be adjusted. */
-                memblock_reserve(base, size);
-
-                phyp_dump_info->init_reserve_start = base;
-                phyp_dump_info->init_reserve_size = size;
-        } else {
-                size = phyp_dump_info->cpu_state_size +
-                        phyp_dump_info->hpte_region_size +
-                        variable_reserve_size;
-                base = memblock_end_of_DRAM() - size;
-                memblock_reserve(base, size);
-                phyp_dump_info->init_reserve_start = base;
-                phyp_dump_info->init_reserve_size = size;
-        }
-}
-#else
-static inline void __init phyp_dump_reserve_mem(void) {}
-#endif /* CONFIG_PHYP_DUMP  && CONFIG_PPC_RTAS */
-
 void __init early_init_devtree(void *params)
 {
         phys_addr_t limit;
@@ -714,9 +634,9 @@ void __init early_init_devtree(void *params)
         of_scan_flat_dt(early_init_dt_scan_opal, NULL);
 #endif
 
-#ifdef CONFIG_PHYP_DUMP
-        /* scan tree to see if dump occurred during last boot */
-        of_scan_flat_dt(early_init_dt_scan_phyp_dump, NULL);
+#ifdef CONFIG_FA_DUMP
+        /* scan tree to see if dump is active during last boot */
+        of_scan_flat_dt(early_init_dt_scan_fw_dump, NULL);
 #endif
 
         /* Pre-initialize the cmd_line with the content of boot_commmand_line,
@@ -750,9 +670,15 @@ void __init early_init_devtree(void *params)
         if (PHYSICAL_START > MEMORY_START)
                 memblock_reserve(MEMORY_START, 0x8000);
         reserve_kdump_trampoline();
-        reserve_crashkernel();
+#ifdef CONFIG_FA_DUMP
+        /*
+         * If we fail to reserve memory for firmware-assisted dump then
+         * fallback to kexec based kdump.
+         */
+        if (fadump_reserve_mem() == 0)
+#endif
+                reserve_crashkernel();
         early_reserve_mem();
-        phyp_dump_reserve_mem();
 
         /*
          * Ensure that total memory size is page-aligned, because otherwise
diff --git a/arch/powerpc/kernel/prom_init.c b/arch/powerpc/kernel/prom_init.c
index eca626ea3f2..e2d59904814 100644
--- a/arch/powerpc/kernel/prom_init.c
+++ b/arch/powerpc/kernel/prom_init.c
@@ -48,14 +48,6 @@
 #include <linux/linux_logo.h>
 
 /*
- * Properties whose value is longer than this get excluded from our
- * copy of the device tree. This value does need to be big enough to
- * ensure that we don't lose things like the interrupt-map property
- * on a PCI-PCI bridge.
- */
-#define MAX_PROPERTY_LENGTH     (1UL * 1024 * 1024)
-
-/*
  * Eventually bump that one up
  */
 #define DEVTREE_CHUNK_SIZE      0x100000
@@ -2273,13 +2265,6 @@ static void __init scan_dt_build_struct(phandle node, unsigned long *mem_start,
                 /* sanity checks */
                 if (l == PROM_ERROR)
                         continue;
-                if (l > MAX_PROPERTY_LENGTH) {
-                        prom_printf("WARNING: ignoring large property ");
-                        /* It seems OF doesn't null-terminate the path :-( */
-                        prom_printf("[%s] ", path);
-                        prom_printf("%s length 0x%x\n", RELOC(pname), l);
-                        continue;
-                }
 
                 /* push property head */
                 dt_push_token(OF_DT_PROP, mem_start, mem_end);
diff --git a/arch/powerpc/kernel/rtas_pci.c b/arch/powerpc/kernel/rtas_pci.c
index 6cd8f0196b6..179af906dcd 100644
--- a/arch/powerpc/kernel/rtas_pci.c
+++ b/arch/powerpc/kernel/rtas_pci.c
@@ -275,8 +275,11 @@ void __init find_and_init_phbs(void)
         of_node_put(root);
         pci_devs_phb_init();
 
+        /* Create EEH devices for all PHBs */
+        eeh_dev_phb_init();
+
         /*
-         * pci_probe_only and pci_assign_all_buses can be set via properties
+         * PCI_PROBE_ONLY and PCI_REASSIGN_ALL_BUS can be set via properties
          * in chosen.
          */
         if (of_chosen) {
@@ -284,8 +287,12 @@ void __init find_and_init_phbs(void)
 
                 prop = of_get_property(of_chosen,
                                 "linux,pci-probe-only", NULL);
-                if (prop)
-                        pci_probe_only = *prop;
+                if (prop) {
+                        if (*prop)
+                                pci_add_flags(PCI_PROBE_ONLY);
+                        else
+                                pci_clear_flags(PCI_PROBE_ONLY);
+                }
 
 #ifdef CONFIG_PPC32 /* Will be made generic soon */
                 prop = of_get_property(of_chosen,
diff --git a/arch/powerpc/kernel/setup-common.c b/arch/powerpc/kernel/setup-common.c
index 77bb77da05c..b0ebdeab949 100644
--- a/arch/powerpc/kernel/setup-common.c
+++ b/arch/powerpc/kernel/setup-common.c
@@ -61,6 +61,7 @@
 #include <asm/xmon.h>
 #include <asm/cputhreads.h>
 #include <mm/mmu_decl.h>
+#include <asm/fadump.h>
 
 #include "setup.h"
 
@@ -109,6 +110,14 @@ EXPORT_SYMBOL(ppc_do_canonicalize_irqs);
 /* also used by kexec */
 void machine_shutdown(void)
 {
+#ifdef CONFIG_FA_DUMP
+        /*
+         * if fadump is active, cleanup the fadump registration before we
+         * shutdown.
+         */
+        fadump_cleanup();
+#endif
+
         if (ppc_md.machine_shutdown)
                 ppc_md.machine_shutdown();
 }
@@ -639,6 +648,11 @@ EXPORT_SYMBOL(check_legacy_ioport);
 static int ppc_panic_event(struct notifier_block *this,
                              unsigned long event, void *ptr)
 {
+        /*
+         * If firmware-assisted dump has been registered then trigger
+         * firmware-assisted dump and let firmware handle everything else.
+         */
+        crash_fadump(NULL, ptr);
         ppc_md.panic(ptr);  /* May not return */
         return NOTIFY_DONE;
 }
diff --git a/arch/powerpc/kernel/signal.c b/arch/powerpc/kernel/signal.c
index ac6e437b102..7006b7f4267 100644
--- a/arch/powerpc/kernel/signal.c
+++ b/arch/powerpc/kernel/signal.c
@@ -57,10 +57,7 @@ void __user * get_sigframe(struct k_sigaction *ka, struct pt_regs *regs,
 void restore_sigmask(sigset_t *set)
 {
         sigdelsetmask(set, ~_BLOCKABLE);
-        spin_lock_irq(&current->sighand->siglock);
-        current->blocked = *set;
-        recalc_sigpending();
-        spin_unlock_irq(&current->sighand->siglock);
+        set_current_blocked(set);
 }
 
 static void check_syscall_restart(struct pt_regs *regs, struct k_sigaction *ka,
@@ -169,13 +166,7 @@ static int do_signal(struct pt_regs *regs)
 
         regs->trap = 0;
         if (ret) {
-                spin_lock_irq(&current->sighand->siglock);
-                sigorsets(&current->blocked, &current->blocked,
-                          &ka.sa.sa_mask);
-                if (!(ka.sa.sa_flags & SA_NODEFER))
-                        sigaddset(&current->blocked, signr);
-                recalc_sigpending();
-                spin_unlock_irq(&current->sighand->siglock);
+                block_sigmask(&ka, signr);
 
                 /*
                  * A signal was successfully delivered; the saved sigmask is in
diff --git a/arch/powerpc/kernel/signal_32.c b/arch/powerpc/kernel/signal_32.c
index 836a5a19eb2..e061ef5dd44 100644
--- a/arch/powerpc/kernel/signal_32.c
+++ b/arch/powerpc/kernel/signal_32.c
@@ -242,12 +242,13 @@ static inline int restore_general_regs(struct pt_regs *regs,
  */
 long sys_sigsuspend(old_sigset_t mask)
 {
-        mask &= _BLOCKABLE;
-        spin_lock_irq(&current->sighand->siglock);
+        sigset_t blocked;
+
         current->saved_sigmask = current->blocked;
-        siginitset(&current->blocked, mask);
-        recalc_sigpending();
-        spin_unlock_irq(&current->sighand->siglock);
+
+        mask &= _BLOCKABLE;
+        siginitset(&blocked, mask);
+        set_current_blocked(&blocked);
 
         current->state = TASK_INTERRUPTIBLE;
         schedule();
diff --git a/arch/powerpc/kernel/sysfs.c b/arch/powerpc/kernel/sysfs.c
index 883e74c0d1b..0c683d376b1 100644
--- a/arch/powerpc/kernel/sysfs.c
+++ b/arch/powerpc/kernel/sysfs.c
@@ -12,7 +12,6 @@
 #include <asm/current.h>
 #include <asm/processor.h>
 #include <asm/cputable.h>
-#include <asm/firmware.h>
 #include <asm/hvcall.h>
 #include <asm/prom.h>
 #include <asm/machdep.h>
@@ -341,8 +340,7 @@ static void __cpuinit register_cpu_online(unsigned int cpu)
         int i, nattrs;
 
 #ifdef CONFIG_PPC64
-        if (!firmware_has_feature(FW_FEATURE_ISERIES) &&
-                        cpu_has_feature(CPU_FTR_SMT))
+        if (cpu_has_feature(CPU_FTR_SMT))
                 device_create_file(s, &dev_attr_smt_snooze_delay);
 #endif
 
@@ -414,8 +412,7 @@ static void unregister_cpu_online(unsigned int cpu)
         BUG_ON(!c->hotpluggable);
 
 #ifdef CONFIG_PPC64
-        if (!firmware_has_feature(FW_FEATURE_ISERIES) &&
-                        cpu_has_feature(CPU_FTR_SMT))
+        if (cpu_has_feature(CPU_FTR_SMT))
                 device_remove_file(s, &dev_attr_smt_snooze_delay);
 #endif
 
diff --git a/arch/powerpc/kernel/time.c b/arch/powerpc/kernel/time.c
index 567dd7c3ac2..2c42cd72d0f 100644
--- a/arch/powerpc/kernel/time.c
+++ b/arch/powerpc/kernel/time.c
@@ -17,8 +17,7 @@
  *
  * TODO (not necessarily in this file):
  * - improve precision and reproducibility of timebase frequency
- * measurement at boot time. (for iSeries, we calibrate the timebase
- * against the Titan chip's clock.)
+ * measurement at boot time.
  * - for astronomical applications: add a new function to get
  * non ambiguous timestamps even around leap seconds. This needs
  * a new timestamp format and a good name.
@@ -70,10 +69,6 @@
 #include <asm/vdso_datapage.h>
 #include <asm/firmware.h>
 #include <asm/cputime.h>
-#ifdef CONFIG_PPC_ISERIES
-#include <asm/iseries/it_lp_queue.h>
-#include <asm/iseries/hv_call_xm.h>
-#endif
 
 /* powerpc clocksource/clockevent code */
 
@@ -117,14 +112,6 @@ static struct clock_event_device decrementer_clockevent = {
 DEFINE_PER_CPU(u64, decrementers_next_tb);
 static DEFINE_PER_CPU(struct clock_event_device, decrementers);
 
-#ifdef CONFIG_PPC_ISERIES
-static unsigned long __initdata iSeries_recal_titan;
-static signed long __initdata iSeries_recal_tb;
-
-/* Forward declaration is only needed for iSereis compiles */
-static void __init clocksource_init(void);
-#endif
-
 #define XSEC_PER_SEC (1024*1024)
 
 #ifdef CONFIG_PPC64
@@ -259,7 +246,6 @@ void accumulate_stolen_time(void)
         u64 sst, ust;
 
         u8 save_soft_enabled = local_paca->soft_enabled;
-        u8 save_hard_enabled = local_paca->hard_enabled;
 
         /* We are called early in the exception entry, before
          * soft/hard_enabled are sync'ed to the expected state
@@ -268,7 +254,6 @@ void accumulate_stolen_time(void)
          * complain
          */
         local_paca->soft_enabled = 0;
-        local_paca->hard_enabled = 0;
 
         sst = scan_dispatch_log(local_paca->starttime_user);
         ust = scan_dispatch_log(local_paca->starttime);
@@ -277,7 +262,6 @@ void accumulate_stolen_time(void)
         local_paca->stolen_time += ust + sst;
 
         local_paca->soft_enabled = save_soft_enabled;
-        local_paca->hard_enabled = save_hard_enabled;
 }
 
 static inline u64 calculate_stolen_time(u64 stop_tb)
@@ -426,74 +410,6 @@ unsigned long profile_pc(struct pt_regs *regs)
 EXPORT_SYMBOL(profile_pc);
 #endif
 
-#ifdef CONFIG_PPC_ISERIES
-
-/* 
- * This function recalibrates the timebase based on the 49-bit time-of-day
- * value in the Titan chip.  The Titan is much more accurate than the value
- * returned by the service processor for the timebase frequency.
- */
-
-static int __init iSeries_tb_recal(void)
-{
-        unsigned long titan, tb;
-
-        /* Make sure we only run on iSeries */
-        if (!firmware_has_feature(FW_FEATURE_ISERIES))
-                return -ENODEV;
-
-        tb = get_tb();
-        titan = HvCallXm_loadTod();
-        if ( iSeries_recal_titan ) {
-                unsigned long tb_ticks = tb - iSeries_recal_tb;
-                unsigned long titan_usec = (titan - iSeries_recal_titan) >> 12;
-                unsigned long new_tb_ticks_per_sec   = (tb_ticks * USEC_PER_SEC)/titan_usec;
-                unsigned long new_tb_ticks_per_jiffy =
-                        DIV_ROUND_CLOSEST(new_tb_ticks_per_sec, HZ);
-                long tick_diff = new_tb_ticks_per_jiffy - tb_ticks_per_jiffy;
-                char sign = '+';                
-                /* make sure tb_ticks_per_sec and tb_ticks_per_jiffy are consistent */
-                new_tb_ticks_per_sec = new_tb_ticks_per_jiffy * HZ;
-
-                if ( tick_diff < 0 ) {
-                        tick_diff = -tick_diff;
-                        sign = '-';
-                }
-                if ( tick_diff ) {
-                        if ( tick_diff < tb_ticks_per_jiffy/25 ) {
-                                printk( "Titan recalibrate: new tb_ticks_per_jiffy = %lu (%c%ld)\n",
-                                                new_tb_ticks_per_jiffy, sign, tick_diff );
-                                tb_ticks_per_jiffy = new_tb_ticks_per_jiffy;
-                                tb_ticks_per_sec   = new_tb_ticks_per_sec;
-                                calc_cputime_factors();
-                                vdso_data->tb_ticks_per_sec = tb_ticks_per_sec;
-                                setup_cputime_one_jiffy();
-                        }
-                        else {
-                                printk( "Titan recalibrate: FAILED (difference > 4 percent)\n"
-                                        "                   new tb_ticks_per_jiffy = %lu\n"
-                                        "                   old tb_ticks_per_jiffy = %lu\n",
-                                        new_tb_ticks_per_jiffy, tb_ticks_per_jiffy );
-                        }
-                }
-        }
-        iSeries_recal_titan = titan;
-        iSeries_recal_tb = tb;
-
-        /* Called here as now we know accurate values for the timebase */
-        clocksource_init();
-        return 0;
-}
-late_initcall(iSeries_tb_recal);
-
-/* Called from platform early init */
-void __init iSeries_time_init_early(void)
-{
-        iSeries_recal_tb = get_tb();
-        iSeries_recal_titan = HvCallXm_loadTod();
-}
-#endif /* CONFIG_PPC_ISERIES */
-
 #ifdef CONFIG_IRQ_WORK
 
 /*
@@ -550,16 +466,6 @@ void arch_irq_work_raise(void)
 #endif /* CONFIG_IRQ_WORK */
 
 /*
- * For iSeries shared processors, we have to let the hypervisor
- * set the hardware decrementer.  We set a virtual decrementer
- * in the lppaca and call the hypervisor if the virtual
- * decrementer is less than the current value in the hardware
- * decrementer. (almost always the new decrementer value will
- * be greater than the current hardware decementer so the hypervisor
- * call will not be needed)
- */
-
-/*
  * timer_interrupt - gets called when the decrementer overflows,
  * with interrupts disabled.
  */
@@ -580,6 +486,11 @@ void timer_interrupt(struct pt_regs * regs)
         if (!cpu_online(smp_processor_id()))
                 return;
 
+        /* Conditionally hard-enable interrupts now that the DEC has been
+         * bumped to its maximum value
+         */
+        may_hard_irq_enable();
+
         trace_timer_interrupt_entry(regs);
 
         __get_cpu_var(irq_stat).timer_irqs++;
@@ -597,20 +508,10 @@ void timer_interrupt(struct pt_regs * regs)
                 irq_work_run();
         }
 
-#ifdef CONFIG_PPC_ISERIES
-        if (firmware_has_feature(FW_FEATURE_ISERIES))
-                get_lppaca()->int_dword.fields.decr_int = 0;
-#endif
-
         *next_tb = ~(u64)0;
         if (evt->event_handler)
                 evt->event_handler(evt);
 
-#ifdef CONFIG_PPC_ISERIES
-        if (firmware_has_feature(FW_FEATURE_ISERIES) && hvlpevent_is_pending())
-                process_hvlpevents();
-#endif
-
 #ifdef CONFIG_PPC64
         /* collect purr register values often, for accurate calculations */
         if (firmware_has_feature(FW_FEATURE_SPLPAR)) {
@@ -982,9 +883,8 @@ void __init time_init(void)
          */
         start_cpu_decrementer();
 
-        /* Register the clocksource, if we're not running on iSeries */
-        if (!firmware_has_feature(FW_FEATURE_ISERIES))
-                clocksource_init();
+        /* Register the clocksource */
+        clocksource_init();
 
         init_decrementer_clockevent();
 }
diff --git a/arch/powerpc/kernel/traps.c b/arch/powerpc/kernel/traps.c
index c091527efd8..a750409ccc4 100644
--- a/arch/powerpc/kernel/traps.c
+++ b/arch/powerpc/kernel/traps.c
@@ -57,6 +57,7 @@
 #include <asm/kexec.h>
 #include <asm/ppc-opcode.h>
 #include <asm/rio.h>
+#include <asm/fadump.h>
 
 #if defined(CONFIG_DEBUGGER) || defined(CONFIG_KEXEC)
 int (*__debugger)(struct pt_regs *regs) __read_mostly;
@@ -145,6 +146,8 @@ static void __kprobes oops_end(unsigned long flags, struct pt_regs *regs,
                 arch_spin_unlock(&die_lock);
         raw_local_irq_restore(flags);
 
+        crash_fadump(regs, "die oops");
+
         /*
          * A system reset (0x100) is a request to dump, so we always send
          * it through the crashdump code.
@@ -244,6 +247,9 @@ void _exception(int signr, struct pt_regs *regs, int code, unsigned long addr)
                                    addr, regs->nip, regs->link, code);
         }
 
+        if (!arch_irq_disabled_regs(regs))
+                local_irq_enable();
+
         memset(&info, 0, sizeof(info));
         info.si_signo = signr;
         info.si_code = code;
diff --git a/arch/powerpc/kernel/vdso.c b/arch/powerpc/kernel/vdso.c
index 7d14bb697d4..d36ee1055f8 100644
--- a/arch/powerpc/kernel/vdso.c
+++ b/arch/powerpc/kernel/vdso.c
@@ -263,17 +263,11 @@ int arch_setup_additional_pages(struct linux_binprm *bprm, int uses_interp)
          * the "data" page of the vDSO or you'll stop getting kernel updates
          * and your nice userland gettimeofday will be totally dead.
          * It's fine to use that for setting breakpoints in the vDSO code
-         * pages though
-         *
-         * Make sure the vDSO gets into every core dump.
-         * Dumping its contents makes post-mortem fully interpretable later
-         * without matching up the same kernel and hardware config to see
-         * what PC values meant.
+         * pages though.
          */
         rc = install_special_mapping(mm, vdso_base, vdso_pages << PAGE_SHIFT,
                                      VM_READ|VM_EXEC|
-                                     VM_MAYREAD|VM_MAYWRITE|VM_MAYEXEC|
-                                     VM_ALWAYSDUMP,
+                                     VM_MAYREAD|VM_MAYWRITE|VM_MAYEXEC,
                                      vdso_pagelist);
         if (rc) {
                 current->mm->context.vdso_base = 0;
diff --git a/arch/powerpc/kernel/vio.c b/arch/powerpc/kernel/vio.c
index 8b086299ba2..bca3fc427b4 100644
--- a/arch/powerpc/kernel/vio.c
+++ b/arch/powerpc/kernel/vio.c
@@ -34,11 +34,6 @@
 #include <asm/abs_addr.h>
 #include <asm/page.h>
 #include <asm/hvcall.h>
-#include <asm/iseries/vio.h>
-#include <asm/iseries/hv_types.h>
-#include <asm/iseries/hv_lp_config.h>
-#include <asm/iseries/hv_call_xm.h>
-#include <asm/iseries/iommu.h>
 
 static struct bus_type vio_bus_type;
 
@@ -1042,7 +1037,6 @@ static void vio_cmo_sysfs_init(void)
         vio_bus_type.bus_attrs = vio_cmo_bus_attrs;
 }
 #else /* CONFIG_PPC_SMLPAR */
-/* Dummy functions for iSeries platform */
 int vio_cmo_entitlement_update(size_t new_entitlement) { return 0; }
 void vio_cmo_set_dev_desired(struct vio_dev *viodev, size_t desired) {}
 static int vio_cmo_bus_probe(struct vio_dev *viodev) { return 0; }
@@ -1060,9 +1054,6 @@ static struct iommu_table *vio_build_iommu_table(struct vio_dev *dev)
         struct iommu_table *tbl;
         unsigned long offset, size;
 
-        if (firmware_has_feature(FW_FEATURE_ISERIES))
-                return vio_build_iommu_table_iseries(dev);
-
         dma_window = of_get_property(dev->dev.of_node,
                                   "ibm,my-dma-window", NULL);
         if (!dma_window)
@@ -1195,8 +1186,7 @@ static void __devinit vio_dev_release(struct device *dev)
 {
         struct iommu_table *tbl = get_iommu_table_base(dev);
 
-        /* iSeries uses a common table for all vio devices */
-        if (!firmware_has_feature(FW_FEATURE_ISERIES) && tbl)
+        if (tbl)
                 iommu_free_table(tbl, dev->of_node ?
                         dev->of_node->full_name : dev_name(dev));
         of_node_put(dev->of_node);
@@ -1244,12 +1234,6 @@ struct vio_dev *vio_register_device_node(struct device_node *of_node)
         viodev->name = of_node->name;
         viodev->type = of_node->type;
         viodev->unit_address = *unit_address;
-        if (firmware_has_feature(FW_FEATURE_ISERIES)) {
-                unit_address = of_get_property(of_node,
-                                "linux,unit_address", NULL);
-                if (unit_address != NULL)
-                        viodev->unit_address = *unit_address;
-        }
         viodev->dev.of_node = of_node_get(of_node);
 
         if (firmware_has_feature(FW_FEATURE_CMO))
diff --git a/arch/powerpc/kernel/vmlinux.lds.S b/arch/powerpc/kernel/vmlinux.lds.S
index 710a54005df..65d1c08cf09 100644
--- a/arch/powerpc/kernel/vmlinux.lds.S
+++ b/arch/powerpc/kernel/vmlinux.lds.S
@@ -109,11 +109,6 @@ SECTIONS
                 __ptov_table_begin = .;
                 *(.ptov_fixup);
                 __ptov_table_end = .;
-#ifdef CONFIG_PPC_ISERIES
-                __dt_strings_start = .;
-                *(.dt_strings);
-                __dt_strings_end = .;
-#endif
         }
 
         .init.setup : AT(ADDR(.init.setup) - LOAD_OFFSET) {
diff --git a/arch/powerpc/kvm/book3s_hv.c b/arch/powerpc/kvm/book3s_hv.c
index 336983da9e7..a7267167a55 100644
--- a/arch/powerpc/kvm/book3s_hv.c
+++ b/arch/powerpc/kvm/book3s_hv.c
@@ -46,7 +46,6 @@
 #include <asm/page.h>
 #include <asm/hvcall.h>
 #include <linux/gfp.h>
-#include <linux/sched.h>
 #include <linux/vmalloc.h>
 #include <linux/highmem.h>
 
diff --git a/arch/powerpc/lib/locks.c b/arch/powerpc/lib/locks.c
index a6ebba56fdd..bb7cfecf278 100644
--- a/arch/powerpc/lib/locks.c
+++ b/arch/powerpc/lib/locks.c
@@ -19,11 +19,9 @@
 #include <linux/smp.h>
 
 /* waiting for a spinlock... */
-#if defined(CONFIG_PPC_SPLPAR) || defined(CONFIG_PPC_ISERIES)
+#if defined(CONFIG_PPC_SPLPAR)
 #include <asm/hvcall.h>
-#include <asm/iseries/hv_call.h>
 #include <asm/smp.h>
-#include <asm/firmware.h>
 
 void __spin_yield(arch_spinlock_t *lock)
 {
@@ -40,14 +38,8 @@ void __spin_yield(arch_spinlock_t *lock)
         rmb();
         if (lock->slock != lock_value)
                 return;         /* something has changed */
-        if (firmware_has_feature(FW_FEATURE_ISERIES))
-                HvCall2(HvCallBaseYieldProcessor, HvCall_YieldToProc,
-                        ((u64)holder_cpu << 32) | yield_count);
-#ifdef CONFIG_PPC_SPLPAR
-        else
-                plpar_hcall_norets(H_CONFER,
-                        get_hard_smp_processor_id(holder_cpu), yield_count);
-#endif
+        plpar_hcall_norets(H_CONFER,
+                get_hard_smp_processor_id(holder_cpu), yield_count);
 }
 
 /*
@@ -71,14 +63,8 @@ void __rw_yield(arch_rwlock_t *rw)
         rmb();
         if (rw->lock != lock_value)
                 return;         /* something has changed */
-        if (firmware_has_feature(FW_FEATURE_ISERIES))
-                HvCall2(HvCallBaseYieldProcessor, HvCall_YieldToProc,
-                        ((u64)holder_cpu << 32) | yield_count);
-#ifdef CONFIG_PPC_SPLPAR
-        else
-                plpar_hcall_norets(H_CONFER,
-                        get_hard_smp_processor_id(holder_cpu), yield_count);
-#endif
+        plpar_hcall_norets(H_CONFER,
+                get_hard_smp_processor_id(holder_cpu), yield_count);
 }
 #endif
 
diff --git a/arch/powerpc/mm/fault.c b/arch/powerpc/mm/fault.c
index 2f0d1b032a8..19f2f9498b2 100644
--- a/arch/powerpc/mm/fault.c
+++ b/arch/powerpc/mm/fault.c
@@ -105,6 +105,82 @@ static int store_updates_sp(struct pt_regs *regs)
         }
         return 0;
 }
+/*
+ * do_page_fault error handling helpers
+ */
+
+#define MM_FAULT_RETURN         0
+#define MM_FAULT_CONTINUE       -1
+#define MM_FAULT_ERR(sig)       (sig)
+
+static int out_of_memory(struct pt_regs *regs)
+{
+        /*
+         * We ran out of memory, or some other thing happened to us that made
+         * us unable to handle the page fault gracefully.
+         */
+        up_read(&current->mm->mmap_sem);
+        if (!user_mode(regs))
+                return MM_FAULT_ERR(SIGKILL);
+        pagefault_out_of_memory();
+        return MM_FAULT_RETURN;
+}
+
+static int do_sigbus(struct pt_regs *regs, unsigned long address)
+{
+        siginfo_t info;
+
+        up_read(&current->mm->mmap_sem);
+
+        if (user_mode(regs)) {
+                info.si_signo = SIGBUS;
+                info.si_errno = 0;
+                info.si_code = BUS_ADRERR;
+                info.si_addr = (void __user *)address;
+                force_sig_info(SIGBUS, &info, current);
+                return MM_FAULT_RETURN;
+        }
+        return MM_FAULT_ERR(SIGBUS);
+}
+
+static int mm_fault_error(struct pt_regs *regs, unsigned long addr, int fault)
+{
+        /*
+         * Pagefault was interrupted by SIGKILL. We have no reason to
+         * continue the pagefault.
+         */
+        if (fatal_signal_pending(current)) {
+                /*
+                 * If we have retry set, the mmap semaphore will have
+                 * alrady been released in __lock_page_or_retry(). Else
+                 * we release it now.
+                 */
+                if (!(fault & VM_FAULT_RETRY))
+                        up_read(&current->mm->mmap_sem);
+                /* Coming from kernel, we need to deal with uaccess fixups */
+                if (user_mode(regs))
+                        return MM_FAULT_RETURN;
+                return MM_FAULT_ERR(SIGKILL);
+        }
+
+        /* No fault: be happy */
+        if (!(fault & VM_FAULT_ERROR))
+                return MM_FAULT_CONTINUE;
+
+        /* Out of memory */
+        if (fault & VM_FAULT_OOM)
+                return out_of_memory(regs);
+
+        /* Bus error. x86 handles HWPOISON here, we'll add this if/when
+         * we support the feature in HW
+         */
+        if (fault & VM_FAULT_SIGBUS)
+                return do_sigbus(regs, addr);
+
+        /* We don't understand the fault code, this is fatal */
+        BUG();
+        return MM_FAULT_CONTINUE;
+}
 
 /*
  * For 600- and 800-family processors, the error_code parameter is DSISR
@@ -124,11 +200,12 @@ int __kprobes do_page_fault(struct pt_regs *regs, unsigned long address,
 {
         struct vm_area_struct * vma;
         struct mm_struct *mm = current->mm;
-        siginfo_t info;
+        unsigned int flags = FAULT_FLAG_ALLOW_RETRY | FAULT_FLAG_KILLABLE;
         int code = SEGV_MAPERR;
-        int is_write = 0, ret;
+        int is_write = 0;
         int trap = TRAP(regs);
         int is_exec = trap == 0x400;
+        int fault;
 
 #if !(defined(CONFIG_4xx) || defined(CONFIG_BOOKE))
         /*
@@ -145,6 +222,9 @@ int __kprobes do_page_fault(struct pt_regs *regs, unsigned long address,
         is_write = error_code & ESR_DST;
 #endif /* CONFIG_4xx || CONFIG_BOOKE */
 
+        if (is_write)
+                flags |= FAULT_FLAG_WRITE;
+
 #ifdef CONFIG_PPC_ICSWX
         /*
          * we need to do this early because this "data storage
@@ -152,13 +232,11 @@ int __kprobes do_page_fault(struct pt_regs *regs, unsigned long address,
          * look at it
          */
         if (error_code & ICSWX_DSI_UCT) {
-                int ret;
-
-                ret = acop_handle_fault(regs, address, error_code);
-                if (ret)
-                        return ret;
+                int rc = acop_handle_fault(regs, address, error_code);
+                if (rc)
+                        return rc;
         }
-#endif
+#endif /* CONFIG_PPC_ICSWX */
 
         if (notify_page_fault(regs))
                 return 0;
@@ -179,6 +257,10 @@ int __kprobes do_page_fault(struct pt_regs *regs, unsigned long address,
         }
 #endif
 
+        /* We restore the interrupt state now */
+        if (!arch_irq_disabled_regs(regs))
+                local_irq_enable();
+
         if (in_atomic() || mm == NULL) {
                 if (!user_mode(regs))
                         return SIGSEGV;
@@ -212,7 +294,15 @@ int __kprobes do_page_fault(struct pt_regs *regs, unsigned long address,
                 if (!user_mode(regs) && !search_exception_tables(regs->nip))
                         goto bad_area_nosemaphore;
 
+retry:
                 down_read(&mm->mmap_sem);
+        } else {
+                /*
+                 * The above down_read_trylock() might have succeeded in
+                 * which case we'll have missed the might_sleep() from
+                 * down_read():
+                 */
+                might_sleep();
         }
 
         vma = find_vma(mm, address);
@@ -327,30 +417,43 @@ good_area:
          * make sure we exit gracefully rather than endlessly redo
          * the fault.
          */
-        ret = handle_mm_fault(mm, vma, address, is_write ? FAULT_FLAG_WRITE : 0);
-        if (unlikely(ret & VM_FAULT_ERROR)) {
-                if (ret & VM_FAULT_OOM)
-                        goto out_of_memory;
-                else if (ret & VM_FAULT_SIGBUS)
-                        goto do_sigbus;
-                BUG();
+        fault = handle_mm_fault(mm, vma, address, flags);
+        if (unlikely(fault & (VM_FAULT_RETRY|VM_FAULT_ERROR))) {
+                int rc = mm_fault_error(regs, address, fault);
+                if (rc >= MM_FAULT_RETURN)
+                        return rc;
         }
-        if (ret & VM_FAULT_MAJOR) {
-                current->maj_flt++;
-                perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS_MAJ, 1,
-                                     regs, address);
+
+        /*
+         * Major/minor page fault accounting is only done on the
+         * initial attempt. If we go through a retry, it is extremely
+         * likely that the page will be found in page cache at that point.
+         */
+        if (flags & FAULT_FLAG_ALLOW_RETRY) {
+                if (fault & VM_FAULT_MAJOR) {
+                        current->maj_flt++;
+                        perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS_MAJ, 1,
+                                      regs, address);
 #ifdef CONFIG_PPC_SMLPAR
-                if (firmware_has_feature(FW_FEATURE_CMO)) {
-                        preempt_disable();
-                        get_lppaca()->page_ins += (1 << PAGE_FACTOR);
-                        preempt_enable();
+                        if (firmware_has_feature(FW_FEATURE_CMO)) {
+                                preempt_disable();
+                                get_lppaca()->page_ins += (1 << PAGE_FACTOR);
+                                preempt_enable();
+                        }
+#endif /* CONFIG_PPC_SMLPAR */
+                } else {
+                        current->min_flt++;
+                        perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS_MIN, 1,
+                                      regs, address);
+                }
+                if (fault & VM_FAULT_RETRY) {
+                        /* Clear FAULT_FLAG_ALLOW_RETRY to avoid any risk
+                         * of starvation. */
+                        flags &= ~FAULT_FLAG_ALLOW_RETRY;
+                        goto retry;
                 }
-#endif
-        } else {
-                current->min_flt++;
-                perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS_MIN, 1,
-                                     regs, address);
         }
+
         up_read(&mm->mmap_sem);
         return 0;
 
@@ -371,28 +474,6 @@ bad_area_nosemaphore:
 
         return SIGSEGV;
 
-/*
- * We ran out of memory, or some other thing happened to us that made
- * us unable to handle the page fault gracefully.
- */
-out_of_memory:
-        up_read(&mm->mmap_sem);
-        if (!user_mode(regs))
-                return SIGKILL;
-        pagefault_out_of_memory();
-        return 0;
-
-do_sigbus:
-        up_read(&mm->mmap_sem);
-        if (user_mode(regs)) {
-                info.si_signo = SIGBUS;
-                info.si_errno = 0;
-                info.si_code = BUS_ADRERR;
-                info.si_addr = (void __user *)address;
-                force_sig_info(SIGBUS, &info, current);
-                return 0;
-        }
-        return SIGBUS;
 }
 
 /*
diff --git a/arch/powerpc/mm/fsl_booke_mmu.c b/arch/powerpc/mm/fsl_booke_mmu.c
index 66a6fd38e9c..07ba45b0f07 100644
--- a/arch/powerpc/mm/fsl_booke_mmu.c
+++ b/arch/powerpc/mm/fsl_booke_mmu.c
@@ -149,12 +149,19 @@ static void settlbcam(int index, unsigned long virt, phys_addr_t phys,
 unsigned long calc_cam_sz(unsigned long ram, unsigned long virt,
                           phys_addr_t phys)
 {
-        unsigned int camsize = __ilog2(ram) & ~1U;
-        unsigned int align = __ffs(virt | phys) & ~1U;
-        unsigned long max_cam = (mfspr(SPRN_TLB1CFG) >> 16) & 0xf;
-
-        /* Convert (4^max) kB to (2^max) bytes */
-        max_cam = max_cam * 2 + 10;
+        unsigned int camsize = __ilog2(ram);
+        unsigned int align = __ffs(virt | phys);
+        unsigned long max_cam;
+
+        if ((mfspr(SPRN_MMUCFG) & MMUCFG_MAVN) == MMUCFG_MAVN_V1) {
+                /* Convert (4^max) kB to (2^max) bytes */
+                max_cam = ((mfspr(SPRN_TLB1CFG) >> 16) & 0xf) * 2 + 10;
+                camsize &= ~1U;
+                align &= ~1U;
+        } else {
+                /* Convert (2^max) kB to (2^max) bytes */
+                max_cam = __ilog2(mfspr(SPRN_TLB1PS)) + 10;
+        }
 
         if (camsize > align)
                 camsize = align;
diff --git a/arch/powerpc/mm/hash_utils_64.c b/arch/powerpc/mm/hash_utils_64.c
index 2d282186cb4..3e8c37a4e39 100644
--- a/arch/powerpc/mm/hash_utils_64.c
+++ b/arch/powerpc/mm/hash_utils_64.c
@@ -55,6 +55,8 @@
 #include <asm/spu.h>
 #include <asm/udbg.h>
 #include <asm/code-patching.h>
+#include <asm/fadump.h>
+#include <asm/firmware.h>
 
 #ifdef DEBUG
 #define DBG(fmt...) udbg_printf(fmt)
@@ -625,6 +627,16 @@ static void __init htab_initialize(void)
                 /* Using a hypervisor which owns the htab */
                 htab_address = NULL;
                 _SDR1 = 0; 
+#ifdef CONFIG_FA_DUMP
+                /*
+                 * If firmware assisted dump is active firmware preserves
+                 * the contents of htab along with entire partition memory.
+                 * Clear the htab if firmware assisted dump is active so
+                 * that we dont end up using old mappings.
+                 */
+                if (is_fadump_active() && ppc_md.hpte_clear_all)
+                        ppc_md.hpte_clear_all();
+#endif
         } else {
                 /* Find storage for the HPT.  Must be contiguous in
                  * the absolute address space. On cell we want it to be
@@ -745,12 +757,9 @@ void __init early_init_mmu(void)
          */
         htab_initialize();
 
-        /* Initialize stab / SLB management except on iSeries
-         */
+        /* Initialize stab / SLB management */
         if (mmu_has_feature(MMU_FTR_SLB))
                 slb_initialize();
-        else if (!firmware_has_feature(FW_FEATURE_ISERIES))
-                stab_initialize(get_paca()->stab_real);
 }
 
 #ifdef CONFIG_SMP
@@ -761,8 +770,7 @@ void __cpuinit early_init_mmu_secondary(void)
                 mtspr(SPRN_SDR1, _SDR1);
 
         /* Initialize STAB/SLB. We use a virtual address as it works
-         * in real mode on pSeries and we want a virtual address on
-         * iSeries anyway
+         * in real mode on pSeries.
          */
         if (mmu_has_feature(MMU_FTR_SLB))
                 slb_initialize();
diff --git a/arch/powerpc/mm/icswx.c b/arch/powerpc/mm/icswx.c
index 5d9a59eaad9..8cdbd8634a5 100644
--- a/arch/powerpc/mm/icswx.c
+++ b/arch/powerpc/mm/icswx.c
@@ -163,7 +163,7 @@ EXPORT_SYMBOL_GPL(drop_cop);
 
 static int acop_use_cop(int ct)
 {
-        /* todo */
+        /* There is no alternate policy, yet */
         return -1;
 }
 
@@ -227,11 +227,30 @@ int acop_handle_fault(struct pt_regs *regs, unsigned long address,
                 ct = (ccw >> 16) & 0x3f;
         }
 
+        /*
+         * We could be here because another thread has enabled acop
+         * but the ACOP register has yet to be updated.
+         *
+         * This should have been taken care of by the IPI to sync all
+         * the threads (see smp_call_function(sync_cop, mm, 1)), but
+         * that could take forever if there are a significant amount
+         * of threads.
+         *
+         * Given the number of threads on some of these systems,
+         * perhaps this is the best way to sync ACOP rather than whack
+         * every thread with an IPI.
+         */
+        if ((acop_copro_type_bit(ct) & current->active_mm->context.acop) != 0) {
+                sync_cop(current->active_mm);
+                return 0;
+        }
+
+        /* check for alternate policy */
         if (!acop_use_cop(ct))
                 return 0;
 
         /* at this point the CT is unknown to the system */
-        pr_warn("%s[%d]: Coprocessor %d is unavailable",
+        pr_warn("%s[%d]: Coprocessor %d is unavailable\n",
                 current->comm, current->pid, ct);
 
         /* get inst if we don't already have it */
diff --git a/arch/powerpc/mm/icswx.h b/arch/powerpc/mm/icswx.h
index 42176bd0884..6dedc08e62c 100644
--- a/arch/powerpc/mm/icswx.h
+++ b/arch/powerpc/mm/icswx.h
@@ -59,4 +59,10 @@ extern void free_cop_pid(int free_pid);
 
 extern int acop_handle_fault(struct pt_regs *regs, unsigned long address,
                              unsigned long error_code);
+
+static inline u64 acop_copro_type_bit(unsigned int type)
+{
+        return 1ULL << (63 - type);
+}
+
 #endif /* !_ARCH_POWERPC_MM_ICSWX_H_ */
diff --git a/arch/powerpc/mm/pgtable_32.c b/arch/powerpc/mm/pgtable_32.c
index 51f87956f8f..0907f92ce30 100644
--- a/arch/powerpc/mm/pgtable_32.c
+++ b/arch/powerpc/mm/pgtable_32.c
@@ -207,7 +207,7 @@ __ioremap_caller(phys_addr_t addr, unsigned long size, unsigned long flags,
          */
         if (mem_init_done && (p < virt_to_phys(high_memory)) &&
             !(__allow_ioremap_reserved && memblock_is_region_reserved(p, size))) {
-                printk("__ioremap(): phys addr 0x%llx is RAM lr %p\n",
+                printk("__ioremap(): phys addr 0x%llx is RAM lr %pf\n",
                        (unsigned long long)p, __builtin_return_address(0));
                 return NULL;
         }
diff --git a/arch/powerpc/mm/slb.c b/arch/powerpc/mm/slb.c
index e22276cb67a..a538c80db2d 100644
--- a/arch/powerpc/mm/slb.c
+++ b/arch/powerpc/mm/slb.c
@@ -21,7 +21,6 @@
 #include <asm/cputable.h>
 #include <asm/cacheflush.h>
 #include <asm/smp.h>
-#include <asm/firmware.h>
 #include <linux/compiler.h>
 #include <asm/udbg.h>
 #include <asm/code-patching.h>
@@ -307,11 +306,6 @@ void slb_initialize(void)
 
         get_paca()->stab_rr = SLB_NUM_BOLTED;
 
-        /* On iSeries the bolted entries have already been set up by
-         * the hypervisor from the lparMap data in head.S */
-        if (firmware_has_feature(FW_FEATURE_ISERIES))
-                return;
-
         lflags = SLB_VSID_KERNEL | linear_llp;
         vflags = SLB_VSID_KERNEL | vmalloc_llp;
 
diff --git a/arch/powerpc/mm/slb_low.S b/arch/powerpc/mm/slb_low.S
index ef653dc95b6..b9ee79ce220 100644
--- a/arch/powerpc/mm/slb_low.S
+++ b/arch/powerpc/mm/slb_low.S
@@ -217,21 +217,6 @@ slb_finish_load:
          * free slot first but that took too long. Unfortunately we
          * dont have any LRU information to help us choose a slot.
          */
-#ifdef CONFIG_PPC_ISERIES
-BEGIN_FW_FTR_SECTION
-        /*
-         * On iSeries, the "bolted" stack segment can be cast out on
-         * shared processor switch so we need to check for a miss on
-         * it and restore it to the right slot.
-         */
-        ld      r9,PACAKSAVE(r13)
-        clrrdi  r9,r9,28
-        clrrdi  r3,r3,28
-        li      r10,SLB_NUM_BOLTED-1    /* Stack goes in last bolted slot */
-        cmpld   r9,r3
-        beq     3f
-END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES)
-#endif /* CONFIG_PPC_ISERIES */
 
 7:      ld      r10,PACASTABRR(r13)
         addi    r10,r10,1
@@ -282,7 +267,6 @@ _GLOBAL(slb_compare_rr_to_size)
 
 /*
  * Finish loading of a 1T SLB entry (for the kernel linear mapping) and return.
- * We assume legacy iSeries will never have 1T segments.
  *
  * r3 = EA, r10 = proto-VSID, r11 = flags, clobbers r9
  */
diff --git a/arch/powerpc/mm/stab.c b/arch/powerpc/mm/stab.c
index 41e31642a86..9106ebb118f 100644
--- a/arch/powerpc/mm/stab.c
+++ b/arch/powerpc/mm/stab.c
@@ -21,8 +21,6 @@
 #include <asm/cputable.h>
 #include <asm/prom.h>
 #include <asm/abs_addr.h>
-#include <asm/firmware.h>
-#include <asm/iseries/hv_call.h>
 
 struct stab_entry {
         unsigned long esid_data;
@@ -285,12 +283,5 @@ void stab_initialize(unsigned long stab)
         /* Set ASR */
         stabreal = get_paca()->stab_real | 0x1ul;
 
-#ifdef CONFIG_PPC_ISERIES
-        if (firmware_has_feature(FW_FEATURE_ISERIES)) {
-                HvCall1(HvCallBaseSetASR, stabreal);
-                return;
-        }
-#endif /* CONFIG_PPC_ISERIES */
-
         mtspr(SPRN_ASR, stabreal);
 }
diff --git a/arch/powerpc/oprofile/common.c b/arch/powerpc/oprofile/common.c
index d65e68f3cb2..6f01624f317 100644
--- a/arch/powerpc/oprofile/common.c
+++ b/arch/powerpc/oprofile/common.c
@@ -195,9 +195,6 @@ int __init oprofile_arch_init(struct oprofile_operations *ops)
         if (!cur_cpu_spec->oprofile_cpu_type)
                 return -ENODEV;
 
-        if (firmware_has_feature(FW_FEATURE_ISERIES))
-                return -ENODEV;
-
         switch (cur_cpu_spec->oprofile_type) {
 #ifdef CONFIG_PPC_BOOK3S_64
 #ifdef CONFIG_OPROFILE_CELL
diff --git a/arch/powerpc/perf/Makefile b/arch/powerpc/perf/Makefile
new file mode 100644
index 00000000000..af3fac23768
--- /dev/null
+++ b/arch/powerpc/perf/Makefile
@@ -0,0 +1,14 @@
+subdir-ccflags-$(CONFIG_PPC_WERROR) := -Werror
+
+obj-$(CONFIG_PERF_EVENTS)       += callchain.o
+
+obj-$(CONFIG_PPC_PERF_CTRS)     += core-book3s.o
+obj64-$(CONFIG_PPC_PERF_CTRS)   += power4-pmu.o ppc970-pmu.o power5-pmu.o \
+                                   power5+-pmu.o power6-pmu.o power7-pmu.o
+obj32-$(CONFIG_PPC_PERF_CTRS)   += mpc7450-pmu.o
+
+obj-$(CONFIG_FSL_EMB_PERF_EVENT) += core-fsl-emb.o
+obj-$(CONFIG_FSL_EMB_PERF_EVENT_E500) += e500-pmu.o
+
+obj-$(CONFIG_PPC64)             += $(obj64-y)
+obj-$(CONFIG_PPC32)             += $(obj32-y)
diff --git a/arch/powerpc/kernel/perf_callchain.c b/arch/powerpc/perf/callchain.c
index 564c1d8bdb5..e8a18d1cc7c 100644
--- a/arch/powerpc/kernel/perf_callchain.c
+++ b/arch/powerpc/perf/callchain.c
@@ -20,7 +20,7 @@
 #include <asm/ucontext.h>
 #include <asm/vdso.h>
 #ifdef CONFIG_PPC64
-#include "ppc32.h"
+#include "../kernel/ppc32.h"
 #endif
 
 
diff --git a/arch/powerpc/kernel/perf_event.c b/arch/powerpc/perf/core-book3s.c
index c2e27ede07e..c2e27ede07e 100644
--- a/arch/powerpc/kernel/perf_event.c
+++ b/arch/powerpc/perf/core-book3s.c
diff --git a/arch/powerpc/kernel/perf_event_fsl_emb.c b/arch/powerpc/perf/core-fsl-emb.c
index 0a6d2a9d569..0a6d2a9d569 100644
--- a/arch/powerpc/kernel/perf_event_fsl_emb.c
+++ b/arch/powerpc/perf/core-fsl-emb.c
diff --git a/arch/powerpc/kernel/e500-pmu.c b/arch/powerpc/perf/e500-pmu.c
index cb2e2949c8d..cb2e2949c8d 100644
--- a/arch/powerpc/kernel/e500-pmu.c
+++ b/arch/powerpc/perf/e500-pmu.c
diff --git a/arch/powerpc/kernel/mpc7450-pmu.c b/arch/powerpc/perf/mpc7450-pmu.c
index fe21b515ca4..fe21b515ca4 100644
--- a/arch/powerpc/kernel/mpc7450-pmu.c
+++ b/arch/powerpc/perf/mpc7450-pmu.c
diff --git a/arch/powerpc/kernel/power4-pmu.c b/arch/powerpc/perf/power4-pmu.c
index b4f1dda4d08..b4f1dda4d08 100644
--- a/arch/powerpc/kernel/power4-pmu.c
+++ b/arch/powerpc/perf/power4-pmu.c
diff --git a/arch/powerpc/kernel/power5+-pmu.c b/arch/powerpc/perf/power5+-pmu.c
index a8757baa28f..a8757baa28f 100644
--- a/arch/powerpc/kernel/power5+-pmu.c
+++ b/arch/powerpc/perf/power5+-pmu.c
diff --git a/arch/powerpc/kernel/power5-pmu.c b/arch/powerpc/perf/power5-pmu.c
index e7f06eb7a86..e7f06eb7a86 100644
--- a/arch/powerpc/kernel/power5-pmu.c
+++ b/arch/powerpc/perf/power5-pmu.c
diff --git a/arch/powerpc/kernel/power6-pmu.c b/arch/powerpc/perf/power6-pmu.c
index 0bbc901e7ef..31128e086fe 100644
--- a/arch/powerpc/kernel/power6-pmu.c
+++ b/arch/powerpc/perf/power6-pmu.c
@@ -131,7 +131,7 @@ static u32 marked_bus_events[16] = {
         0x00000022,     /* BFP set 2: byte 0 bits 1, 5 */
         0, 0
 };
-        
+
 /*
  * Returns 1 if event counts things relating to marked instructions
  * and thus needs the MMCRA_SAMPLE_ENABLE bit set, or 0 if not.
diff --git a/arch/powerpc/kernel/power7-pmu.c b/arch/powerpc/perf/power7-pmu.c
index 1251e4d7e26..1251e4d7e26 100644
--- a/arch/powerpc/kernel/power7-pmu.c
+++ b/arch/powerpc/perf/power7-pmu.c
diff --git a/arch/powerpc/kernel/ppc970-pmu.c b/arch/powerpc/perf/ppc970-pmu.c
index 8c219020696..111eb25bb0b 100644
--- a/arch/powerpc/kernel/ppc970-pmu.c
+++ b/arch/powerpc/perf/ppc970-pmu.c
@@ -252,7 +252,7 @@ static int p970_get_alternatives(u64 event, unsigned int flags, u64 alt[])
                 alt[1] = event ^ 0x1000;
                 return 2;
         }
-                
+
         return 1;
 }
 
diff --git a/arch/powerpc/platforms/44x/Kconfig b/arch/powerpc/platforms/44x/Kconfig
index fcf6bf2ceee..2e4e64abfab 100644
--- a/arch/powerpc/platforms/44x/Kconfig
+++ b/arch/powerpc/platforms/44x/Kconfig
@@ -23,6 +23,7 @@ config BLUESTONE
         default n
         select PPC44x_SIMPLE
         select APM821xx
+        select PPC4xx_PCI_EXPRESS
         select IBM_EMAC_RGMII
         help
           This option enables support for the APM APM821xx Evaluation board.
diff --git a/arch/powerpc/platforms/44x/currituck.c b/arch/powerpc/platforms/44x/currituck.c
index 3f6229b5dee..583e67fee37 100644
--- a/arch/powerpc/platforms/44x/currituck.c
+++ b/arch/powerpc/platforms/44x/currituck.c
@@ -83,7 +83,7 @@ static void __init ppc47x_init_irq(void)
                  * device-tree, just pass 0 to all arguments
                  */
                 struct mpic *mpic =
-                        mpic_alloc(np, 0, 0, 0, 0, " MPIC     ");
+                        mpic_alloc(np, 0, MPIC_NO_RESET, 0, 0, " MPIC     ");
                 BUG_ON(mpic == NULL);
                 mpic_init(mpic);
                 ppc_md.get_irq = mpic_get_irq;
diff --git a/arch/powerpc/platforms/44x/iss4xx.c b/arch/powerpc/platforms/44x/iss4xx.c
index 5b8cdbb82f8..a28a8629727 100644
--- a/arch/powerpc/platforms/44x/iss4xx.c
+++ b/arch/powerpc/platforms/44x/iss4xx.c
@@ -71,8 +71,7 @@ static void __init iss4xx_init_irq(void)
                 /* The MPIC driver will get everything it needs from the
                  * device-tree, just pass 0 to all arguments
                  */
-                struct mpic *mpic = mpic_alloc(np, 0, 0, 0, 0,
-                                               " MPIC     ");
+                struct mpic *mpic = mpic_alloc(np, 0, MPIC_NO_RESET, 0, 0, " MPIC     ");
                 BUG_ON(mpic == NULL);
                 mpic_init(mpic);
                 ppc_md.get_irq = mpic_get_irq;
diff --git a/arch/powerpc/platforms/44x/ppc44x_simple.c b/arch/powerpc/platforms/44x/ppc44x_simple.c
index 8d220276341..3ffb915446e 100644
--- a/arch/powerpc/platforms/44x/ppc44x_simple.c
+++ b/arch/powerpc/platforms/44x/ppc44x_simple.c
@@ -52,7 +52,7 @@ machine_device_initcall(ppc44x_simple, ppc44x_device_probe);
 static char *board[] __initdata = {
         "amcc,arches",
         "amcc,bamboo",
-        "amcc,bluestone",
+        "apm,bluestone",
         "amcc,glacier",
         "ibm,ebony",
         "amcc,eiger",
diff --git a/arch/powerpc/platforms/52xx/mpc5200_simple.c b/arch/powerpc/platforms/52xx/mpc5200_simple.c
index 846b789fb19..c0aa04068d6 100644
--- a/arch/powerpc/platforms/52xx/mpc5200_simple.c
+++ b/arch/powerpc/platforms/52xx/mpc5200_simple.c
@@ -50,6 +50,7 @@ static void __init mpc5200_simple_setup_arch(void)
 
 /* list of the supported boards */
 static const char *board[] __initdata = {
+        "anonymous,a4m072",
         "anon,charon",
         "intercontrol,digsy-mtc",
         "manroland,mucmc52",
diff --git a/arch/powerpc/platforms/52xx/mpc52xx_common.c b/arch/powerpc/platforms/52xx/mpc52xx_common.c
index 369fd5457a3..d7e94f49532 100644
--- a/arch/powerpc/platforms/52xx/mpc52xx_common.c
+++ b/arch/powerpc/platforms/52xx/mpc52xx_common.c
@@ -98,13 +98,11 @@ struct mpc52xx_gpio_wkup __iomem *wkup_gpio;
  *                                      of the localplus bus to the of_platform
  *                                      bus.
  */
-void __init
-mpc52xx_declare_of_platform_devices(void)
+void __init mpc52xx_declare_of_platform_devices(void)
 {
-        /* Find every child of the SOC node and add it to of_platform */
-        if (of_platform_bus_probe(NULL, mpc52xx_bus_ids, NULL))
-                printk(KERN_ERR __FILE__ ": "
-                        "Error while probing of_platform bus\n");
+        /* Find all the 'platform' devices and register them. */
+        if (of_platform_populate(NULL, mpc52xx_bus_ids, NULL, NULL))
+                pr_err(__FILE__ ": Error while populating devices from DT\n");
 }
 
 /*
diff --git a/arch/powerpc/platforms/85xx/Kconfig b/arch/powerpc/platforms/85xx/Kconfig
index d7946be298b..f000d81c4e3 100644
--- a/arch/powerpc/platforms/85xx/Kconfig
+++ b/arch/powerpc/platforms/85xx/Kconfig
@@ -6,6 +6,7 @@ menuconfig FSL_SOC_BOOKE
         select MPIC
         select PPC_PCI_CHOICE
         select FSL_PCI if PCI
+        select SERIAL_8250_EXTENDED if SERIAL_8250
         select SERIAL_8250_SHARE_IRQ if SERIAL_8250
         default y
 
@@ -13,6 +14,15 @@ if FSL_SOC_BOOKE
 
 if PPC32
 
+config FSL_85XX_CACHE_SRAM
+        bool
+        select PPC_LIB_RHEAP
+        help
+          When selected, this option enables cache-sram support
+          for memory allocation on P1/P2 QorIQ platforms.
+          cache-sram-size and cache-sram-offset kernel boot
+          parameters should be passed when this option is enabled.
+
 config MPC8540_ADS
         bool "Freescale MPC8540 ADS"
         select DEFAULT_UIMAGE
@@ -30,6 +40,7 @@ config MPC85xx_CDS
         bool "Freescale MPC85xx CDS"
         select DEFAULT_UIMAGE
         select PPC_I8259
+        select HAS_RAPIDIO
         help
           This option enables support for the MPC85xx CDS board
 
@@ -80,7 +91,6 @@ config P1010_RDB
 config P1022_DS
         bool "Freescale P1022 DS"
         select DEFAULT_UIMAGE
-        select PHYS_64BIT       # The DTS has 36-bit addresses
         select SWIOTLB
         help
           This option enables support for the Freescale P1022DS reference board.
@@ -171,6 +181,21 @@ config SBC8560
         help
           This option enables support for the Wind River SBC8560 board
 
+config GE_IMP3A
+        bool "GE Intelligent Platforms IMP3A"
+        select DEFAULT_UIMAGE
+        select SWIOTLB
+        select MMIO_NVRAM
+        select GENERIC_GPIO
+        select ARCH_REQUIRE_GPIOLIB
+        select GE_FPGA
+        help
+          This option enables support for the GE Intelligent Platforms IMP3A
+          board.
+
+          This board is a 3U CompactPCI Single Board Computer with a Freescale
+          P2020 processor.
+
 config P2041_RDB
         bool "Freescale P2041 RDB"
         select DEFAULT_UIMAGE
diff --git a/arch/powerpc/platforms/85xx/Makefile b/arch/powerpc/platforms/85xx/Makefile
index 9cb2d4320dc..2125d4ca068 100644
--- a/arch/powerpc/platforms/85xx/Makefile
+++ b/arch/powerpc/platforms/85xx/Makefile
@@ -27,3 +27,4 @@ obj-$(CONFIG_SBC8548)     += sbc8548.o
 obj-$(CONFIG_SOCRATES)    += socrates.o socrates_fpga_pic.o
 obj-$(CONFIG_KSI8560)     += ksi8560.o
 obj-$(CONFIG_XES_MPC85xx) += xes_mpc85xx.o
+obj-$(CONFIG_GE_IMP3A)    += ge_imp3a.o
diff --git a/arch/powerpc/platforms/85xx/corenet_ds.c b/arch/powerpc/platforms/85xx/corenet_ds.c
index 07e3e6c4737..df69e99e511 100644
--- a/arch/powerpc/platforms/85xx/corenet_ds.c
+++ b/arch/powerpc/platforms/85xx/corenet_ds.c
@@ -36,8 +36,8 @@
 void __init corenet_ds_pic_init(void)
 {
         struct mpic *mpic;
-        unsigned int flags = MPIC_BIG_ENDIAN |
-                                MPIC_BROKEN_FRR_NIRQS | MPIC_SINGLE_DEST_CPU;
+        unsigned int flags = MPIC_BIG_ENDIAN | MPIC_SINGLE_DEST_CPU |
+                MPIC_NO_RESET;
 
         if (ppc_md.get_irq == mpic_get_coreint_irq)
                 flags |= MPIC_ENABLE_COREINT;
diff --git a/arch/powerpc/platforms/85xx/ge_imp3a.c b/arch/powerpc/platforms/85xx/ge_imp3a.c
new file mode 100644
index 00000000000..d50056f424f
--- /dev/null
+++ b/arch/powerpc/platforms/85xx/ge_imp3a.c
@@ -0,0 +1,246 @@
+/*
+ * GE IMP3A Board Setup
+ *
+ * Author Martyn Welch <martyn.welch@ge.com>
+ *
+ * Copyright 2010 GE Intelligent Platforms Embedded Systems, Inc.
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ *
+ * Based on: mpc85xx_ds.c (MPC85xx DS Board Setup)
+ * Copyright 2007 Freescale Semiconductor Inc.
+ */
+
+#include <linux/stddef.h>
+#include <linux/kernel.h>
+#include <linux/pci.h>
+#include <linux/kdev_t.h>
+#include <linux/delay.h>
+#include <linux/seq_file.h>
+#include <linux/interrupt.h>
+#include <linux/of_platform.h>
+#include <linux/memblock.h>
+
+#include <asm/system.h>
+#include <asm/time.h>
+#include <asm/machdep.h>
+#include <asm/pci-bridge.h>
+#include <mm/mmu_decl.h>
+#include <asm/prom.h>
+#include <asm/udbg.h>
+#include <asm/mpic.h>
+#include <asm/swiotlb.h>
+#include <asm/nvram.h>
+
+#include <sysdev/fsl_soc.h>
+#include <sysdev/fsl_pci.h>
+#include "smp.h"
+
+#include "mpc85xx.h"
+#include <sysdev/ge/ge_pic.h>
+
+void __iomem *imp3a_regs;
+
+void __init ge_imp3a_pic_init(void)
+{
+        struct mpic *mpic;
+        struct device_node *np;
+        struct device_node *cascade_node = NULL;
+        unsigned long root = of_get_flat_dt_root();
+
+        if (of_flat_dt_is_compatible(root, "fsl,MPC8572DS-CAMP")) {
+                mpic = mpic_alloc(NULL, 0,
+                        MPIC_NO_RESET |
+                        MPIC_BIG_ENDIAN |
+                        MPIC_SINGLE_DEST_CPU,
+                        0, 256, " OpenPIC  ");
+        } else {
+                mpic = mpic_alloc(NULL, 0,
+                          MPIC_BIG_ENDIAN |
+                          MPIC_SINGLE_DEST_CPU,
+                        0, 256, " OpenPIC  ");
+        }
+
+        BUG_ON(mpic == NULL);
+        mpic_init(mpic);
+        /*
+         * There is a simple interrupt handler in the main FPGA, this needs
+         * to be cascaded into the MPIC
+         */
+        for_each_node_by_type(np, "interrupt-controller")
+                if (of_device_is_compatible(np, "gef,fpga-pic-1.00")) {
+                        cascade_node = np;
+                        break;
+                }
+
+        if (cascade_node == NULL) {
+                printk(KERN_WARNING "IMP3A: No FPGA PIC\n");
+                return;
+        }
+
+        gef_pic_init(cascade_node);
+        of_node_put(cascade_node);
+}
+
+#ifdef CONFIG_PCI
+static int primary_phb_addr;
+#endif  /* CONFIG_PCI */
+
+/*
+ * Setup the architecture
+ */
+static void __init ge_imp3a_setup_arch(void)
+{
+        struct device_node *regs;
+#ifdef CONFIG_PCI
+        struct device_node *np;
+        struct pci_controller *hose;
+#endif
+        dma_addr_t max = 0xffffffff;
+
+        if (ppc_md.progress)
+                ppc_md.progress("ge_imp3a_setup_arch()", 0);
+
+#ifdef CONFIG_PCI
+        for_each_node_by_type(np, "pci") {
+                if (of_device_is_compatible(np, "fsl,mpc8540-pci") ||
+                    of_device_is_compatible(np, "fsl,mpc8548-pcie") ||
+                    of_device_is_compatible(np, "fsl,p2020-pcie")) {
+                        struct resource rsrc;
+                        of_address_to_resource(np, 0, &rsrc);
+                        if ((rsrc.start & 0xfffff) == primary_phb_addr)
+                                fsl_add_bridge(np, 1);
+                        else
+                                fsl_add_bridge(np, 0);
+
+                        hose = pci_find_hose_for_OF_device(np);
+                        max = min(max, hose->dma_window_base_cur +
+                                        hose->dma_window_size);
+                }
+        }
+#endif
+
+        mpc85xx_smp_init();
+
+#ifdef CONFIG_SWIOTLB
+        if (memblock_end_of_DRAM() > max) {
+                ppc_swiotlb_enable = 1;
+                set_pci_dma_ops(&swiotlb_dma_ops);
+                ppc_md.pci_dma_dev_setup = pci_dma_dev_setup_swiotlb;
+        }
+#endif
+
+        /* Remap basic board registers */
+        regs = of_find_compatible_node(NULL, NULL, "ge,imp3a-fpga-regs");
+        if (regs) {
+                imp3a_regs = of_iomap(regs, 0);
+                if (imp3a_regs == NULL)
+                        printk(KERN_WARNING "Unable to map board registers\n");
+                of_node_put(regs);
+        }
+
+#if defined(CONFIG_MMIO_NVRAM)
+        mmio_nvram_init();
+#endif
+
+        printk(KERN_INFO "GE Intelligent Platforms IMP3A 3U cPCI SBC\n");
+}
+
+/* Return the PCB revision */
+static unsigned int ge_imp3a_get_pcb_rev(void)
+{
+        unsigned int reg;
+
+        reg = ioread16(imp3a_regs);
+        return (reg >> 8) & 0xff;
+}
+
+/* Return the board (software) revision */
+static unsigned int ge_imp3a_get_board_rev(void)
+{
+        unsigned int reg;
+
+        reg = ioread16(imp3a_regs + 0x2);
+        return reg & 0xff;
+}
+
+/* Return the FPGA revision */
+static unsigned int ge_imp3a_get_fpga_rev(void)
+{
+        unsigned int reg;
+
+        reg = ioread16(imp3a_regs + 0x2);
+        return (reg >> 8) & 0xff;
+}
+
+/* Return compactPCI Geographical Address */
+static unsigned int ge_imp3a_get_cpci_geo_addr(void)
+{
+        unsigned int reg;
+
+        reg = ioread16(imp3a_regs + 0x6);
+        return (reg & 0x0f00) >> 8;
+}
+
+/* Return compactPCI System Controller Status */
+static unsigned int ge_imp3a_get_cpci_is_syscon(void)
+{
+        unsigned int reg;
+
+        reg = ioread16(imp3a_regs + 0x6);
+        return reg & (1 << 12);
+}
+
+static void ge_imp3a_show_cpuinfo(struct seq_file *m)
+{
+        seq_printf(m, "Vendor\t\t: GE Intelligent Platforms\n");
+
+        seq_printf(m, "Revision\t: %u%c\n", ge_imp3a_get_pcb_rev(),
+                ('A' + ge_imp3a_get_board_rev() - 1));
+
+        seq_printf(m, "FPGA Revision\t: %u\n", ge_imp3a_get_fpga_rev());
+
+        seq_printf(m, "cPCI geo. addr\t: %u\n", ge_imp3a_get_cpci_geo_addr());
+
+        seq_printf(m, "cPCI syscon\t: %s\n",
+                ge_imp3a_get_cpci_is_syscon() ? "yes" : "no");
+}
+
+/*
+ * Called very early, device-tree isn't unflattened
+ */
+static int __init ge_imp3a_probe(void)
+{
+        unsigned long root = of_get_flat_dt_root();
+
+        if (of_flat_dt_is_compatible(root, "ge,IMP3A")) {
+#ifdef CONFIG_PCI
+                primary_phb_addr = 0x9000;
+#endif
+                return 1;
+        }
+
+        return 0;
+}
+
+machine_device_initcall(ge_imp3a, mpc85xx_common_publish_devices);
+
+machine_arch_initcall(ge_imp3a, swiotlb_setup_bus_notifier);
+
+define_machine(ge_imp3a) {
+        .name                   = "GE_IMP3A",
+        .probe                  = ge_imp3a_probe,
+        .setup_arch             = ge_imp3a_setup_arch,
+        .init_IRQ               = ge_imp3a_pic_init,
+        .show_cpuinfo           = ge_imp3a_show_cpuinfo,
+#ifdef CONFIG_PCI
+        .pcibios_fixup_bus      = fsl_pcibios_fixup_bus,
+#endif
+        .get_irq                = mpic_get_irq,
+        .restart                = fsl_rstcr_restart,
+        .calibrate_decr         = generic_calibrate_decr,
+        .progress               = udbg_progress,
+};
diff --git a/arch/powerpc/platforms/85xx/ksi8560.c b/arch/powerpc/platforms/85xx/ksi8560.c
index 20f75d7819c..60120e55da4 100644
--- a/arch/powerpc/platforms/85xx/ksi8560.c
+++ b/arch/powerpc/platforms/85xx/ksi8560.c
@@ -57,8 +57,7 @@ static void machine_restart(char *cmd)
 
 static void __init ksi8560_pic_init(void)
 {
-        struct mpic *mpic = mpic_alloc(NULL, 0,
-                        MPIC_WANTS_RESET | MPIC_BIG_ENDIAN,
+        struct mpic *mpic = mpic_alloc(NULL, 0, MPIC_BIG_ENDIAN,
                         0, 256, " OpenPIC  ");
         BUG_ON(mpic == NULL);
         mpic_init(mpic);
diff --git a/arch/powerpc/platforms/85xx/mpc8536_ds.c b/arch/powerpc/platforms/85xx/mpc8536_ds.c
index cf266826682..f58872688d8 100644
--- a/arch/powerpc/platforms/85xx/mpc8536_ds.c
+++ b/arch/powerpc/platforms/85xx/mpc8536_ds.c
@@ -36,9 +36,7 @@
 
 void __init mpc8536_ds_pic_init(void)
 {
-        struct mpic *mpic = mpic_alloc(NULL, 0,
-                          MPIC_WANTS_RESET |
-                          MPIC_BIG_ENDIAN | MPIC_BROKEN_FRR_NIRQS,
+        struct mpic *mpic = mpic_alloc(NULL, 0, MPIC_BIG_ENDIAN,
                         0, 256, " OpenPIC  ");
         BUG_ON(mpic == NULL);
         mpic_init(mpic);
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_ads.c b/arch/powerpc/platforms/85xx/mpc85xx_ads.c
index 3bebb5173bf..d19f675cb36 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_ads.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_ads.c
@@ -50,8 +50,7 @@ static int mpc85xx_exclude_device(struct pci_controller *hose,
 
 static void __init mpc85xx_ads_pic_init(void)
 {
-        struct mpic *mpic = mpic_alloc(NULL, 0,
-                        MPIC_WANTS_RESET | MPIC_BIG_ENDIAN,
+        struct mpic *mpic = mpic_alloc(NULL, 0, MPIC_BIG_ENDIAN,
                         0, 256, " OpenPIC  ");
         BUG_ON(mpic == NULL);
         mpic_init(mpic);
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_cds.c b/arch/powerpc/platforms/85xx/mpc85xx_cds.c
index 40f03da616a..ab5f0bf1945 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_cds.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_cds.c
@@ -3,7 +3,7 @@
  *
  * Maintained by Kumar Gala (see MAINTAINERS for contact information)
  *
- * Copyright 2005 Freescale Semiconductor Inc.
+ * Copyright 2005, 2011-2012 Freescale Semiconductor Inc.
  *
  * This program is free software; you can redistribute  it and/or modify it
  * under  the terms of  the GNU General  Public License as published by the
@@ -48,17 +48,24 @@
 
 #include "mpc85xx.h"
 
-/* CADMUS info */
-/* xxx - galak, move into device tree */
-#define CADMUS_BASE (0xf8004000)
-#define CADMUS_SIZE (256)
-#define CM_VER  (0)
-#define CM_CSR  (1)
-#define CM_RST  (2)
-
+/*
+ * The CDS board contains an FPGA/CPLD called "Cadmus", which collects
+ * various logic and performs system control functions.
+ * Here is the FPGA/CPLD register map.
+ */
+struct cadmus_reg {
+        u8 cm_ver;              /* Board version */
+        u8 cm_csr;              /* General control/status */
+        u8 cm_rst;              /* Reset control */
+        u8 cm_hsclk;    /* High speed clock */
+        u8 cm_hsxclk;   /* High speed clock extended */
+        u8 cm_led;              /* LED data */
+        u8 cm_pci;              /* PCI control/status */
+        u8 cm_dma;              /* DMA control */
+        u8 res[248];    /* Total 256 bytes */
+};
 
-static int cds_pci_slot = 2;
-static volatile u8 *cadmus;
+static struct cadmus_reg *cadmus;
 
 #ifdef CONFIG_PCI
 
@@ -158,6 +165,33 @@ DECLARE_PCI_FIXUP_EARLY(0x1957, 0x3fff, skip_fake_bridge);
 DECLARE_PCI_FIXUP_EARLY(0x3fff, 0x1957, skip_fake_bridge);
 DECLARE_PCI_FIXUP_EARLY(0xff3f, 0x5719, skip_fake_bridge);
 
+#define PCI_DEVICE_ID_IDT_TSI310        0x01a7
+
+/*
+ * Fix Tsi310 PCI-X bridge resource.
+ * Force the bridge to open a window from 0x0000-0x1fff in PCI I/O space.
+ * This allows legacy I/O(i8259, etc) on the VIA southbridge to be accessed.
+ */
+void mpc85xx_cds_fixup_bus(struct pci_bus *bus)
+{
+        struct pci_dev *dev = bus->self;
+        struct resource *res = bus->resource[0];
+
+        if (dev != NULL &&
+            dev->vendor == PCI_VENDOR_ID_IBM &&
+            dev->device == PCI_DEVICE_ID_IDT_TSI310) {
+                if (res) {
+                        res->start = 0;
+                        res->end   = 0x1fff;
+                        res->flags = IORESOURCE_IO;
+                        pr_info("mpc85xx_cds: PCI bridge resource fixup applied\n");
+                        pr_info("mpc85xx_cds: %pR\n", res);
+                }
+        }
+
+        fsl_pcibios_fixup_bus(bus);
+}
+
 #ifdef CONFIG_PPC_I8259
 static void mpc85xx_8259_cascade_handler(unsigned int irq,
                                          struct irq_desc *desc)
@@ -188,8 +222,7 @@ static struct irqaction mpc85xxcds_8259_irqaction = {
 static void __init mpc85xx_cds_pic_init(void)
 {
         struct mpic *mpic;
-        mpic = mpic_alloc(NULL, 0,
-                        MPIC_WANTS_RESET | MPIC_BIG_ENDIAN,
+        mpic = mpic_alloc(NULL, 0, MPIC_BIG_ENDIAN,
                         0, 256, " OpenPIC  ");
         BUG_ON(mpic == NULL);
         mpic_init(mpic);
@@ -249,20 +282,30 @@ machine_device_initcall(mpc85xx_cds, mpc85xx_cds_8259_attach);
  */
 static void __init mpc85xx_cds_setup_arch(void)
 {
-#ifdef CONFIG_PCI
         struct device_node *np;
-#endif
+        int cds_pci_slot;
 
         if (ppc_md.progress)
                 ppc_md.progress("mpc85xx_cds_setup_arch()", 0);
 
-        cadmus = ioremap(CADMUS_BASE, CADMUS_SIZE);
-        cds_pci_slot = ((cadmus[CM_CSR] >> 6) & 0x3) + 1;
+        np = of_find_compatible_node(NULL, NULL, "fsl,mpc8548cds-fpga");
+        if (!np) {
+                pr_err("Could not find FPGA node.\n");
+                return;
+        }
+
+        cadmus = of_iomap(np, 0);
+        of_node_put(np);
+        if (!cadmus) {
+                pr_err("Fail to map FPGA area.\n");
+                return;
+        }
 
         if (ppc_md.progress) {
                 char buf[40];
+                cds_pci_slot = ((in_8(&cadmus->cm_csr) >> 6) & 0x3) + 1;
                 snprintf(buf, 40, "CDS Version = 0x%x in slot %d\n",
-                                cadmus[CM_VER], cds_pci_slot);
+                                in_8(&cadmus->cm_ver), cds_pci_slot);
                 ppc_md.progress(buf, 0);
         }
 
@@ -292,7 +335,8 @@ static void mpc85xx_cds_show_cpuinfo(struct seq_file *m)
         svid = mfspr(SPRN_SVR);
 
         seq_printf(m, "Vendor\t\t: Freescale Semiconductor\n");
-        seq_printf(m, "Machine\t\t: MPC85xx CDS (0x%x)\n", cadmus[CM_VER]);
+        seq_printf(m, "Machine\t\t: MPC85xx CDS (0x%x)\n",
+                        in_8(&cadmus->cm_ver));
         seq_printf(m, "PVR\t\t: 0x%x\n", pvid);
         seq_printf(m, "SVR\t\t: 0x%x\n", svid);
 
@@ -323,7 +367,7 @@ define_machine(mpc85xx_cds) {
         .get_irq        = mpic_get_irq,
 #ifdef CONFIG_PCI
         .restart        = mpc85xx_cds_restart,
-        .pcibios_fixup_bus      = fsl_pcibios_fixup_bus,
+        .pcibios_fixup_bus      = mpc85xx_cds_fixup_bus,
 #else
         .restart        = fsl_rstcr_restart,
 #endif
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_ds.c b/arch/powerpc/platforms/85xx/mpc85xx_ds.c
index eefbb91e1d6..6e23e3e34bd 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_ds.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_ds.c
@@ -72,13 +72,13 @@ void __init mpc85xx_ds_pic_init(void)
 
         if (of_flat_dt_is_compatible(root, "fsl,MPC8572DS-CAMP")) {
                 mpic = mpic_alloc(NULL, 0,
-                        MPIC_BIG_ENDIAN | MPIC_BROKEN_FRR_NIRQS |
+                        MPIC_NO_RESET |
+                        MPIC_BIG_ENDIAN |
                         MPIC_SINGLE_DEST_CPU,
                         0, 256, " OpenPIC  ");
         } else {
                 mpic = mpic_alloc(NULL, 0,
-                          MPIC_WANTS_RESET |
-                          MPIC_BIG_ENDIAN | MPIC_BROKEN_FRR_NIRQS |
+                          MPIC_BIG_ENDIAN |
                           MPIC_SINGLE_DEST_CPU,
                         0, 256, " OpenPIC  ");
         }
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_mds.c b/arch/powerpc/platforms/85xx/mpc85xx_mds.c
index 1d15a0cd2c8..f33662b46b8 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_mds.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_mds.c
@@ -1,5 +1,6 @@
 /*
- * Copyright (C) Freescale Semicondutor, Inc. 2006-2010. All rights reserved.
+ * Copyright (C) 2006-2010, 2012 Freescale Semicondutor, Inc.
+ * All rights reserved.
  *
  * Author: Andy Fleming <afleming@freescale.com>
  *
@@ -51,6 +52,7 @@
 #include <asm/qe_ic.h>
 #include <asm/mpic.h>
 #include <asm/swiotlb.h>
+#include <asm/fsl_guts.h>
 #include "smp.h"
 
 #include "mpc85xx.h"
@@ -268,34 +270,27 @@ static void __init mpc85xx_mds_qe_init(void)
         mpc85xx_mds_reset_ucc_phys();
 
         if (machine_is(p1021_mds)) {
-#define MPC85xx_PMUXCR_OFFSET           0x60
-#define MPC85xx_PMUXCR_QE0              0x00008000
-#define MPC85xx_PMUXCR_QE3              0x00001000
-#define MPC85xx_PMUXCR_QE9              0x00000040
-#define MPC85xx_PMUXCR_QE12             0x00000008
-                static __be32 __iomem *pmuxcr;
 
-                np = of_find_node_by_name(NULL, "global-utilities");
+                struct ccsr_guts_85xx __iomem *guts;
 
+                np = of_find_node_by_name(NULL, "global-utilities");
                 if (np) {
-                        pmuxcr = of_iomap(np, 0) + MPC85xx_PMUXCR_OFFSET;
-
-                        if (!pmuxcr)
-                                printk(KERN_EMERG "Error: Alternate function"
-                                        " signal multiplex control register not"
-                                        " mapped!\n");
-                        else
+                        guts = of_iomap(np, 0);
+                        if (!guts)
+                                pr_err("mpc85xx-rdb: could not map global utilities register\n");
+                        else{
                         /* P1021 has pins muxed for QE and other functions. To
                          * enable QE UEC mode, we need to set bit QE0 for UCC1
                          * in Eth mode, QE0 and QE3 for UCC5 in Eth mode, QE9
                          * and QE12 for QE MII management signals in PMUXCR
                          * register.
                          */
-                                setbits32(pmuxcr, MPC85xx_PMUXCR_QE0 |
-                                                  MPC85xx_PMUXCR_QE3 |
-                                                  MPC85xx_PMUXCR_QE9 |
-                                                  MPC85xx_PMUXCR_QE12);
-
+                                setbits32(&guts->pmuxcr, MPC85xx_PMUXCR_QE(0) |
+                                                  MPC85xx_PMUXCR_QE(3) |
+                                                  MPC85xx_PMUXCR_QE(9) |
+                                                  MPC85xx_PMUXCR_QE(12));
+                                iounmap(guts);
+                        }
                         of_node_put(np);
                 }
 
@@ -434,9 +429,8 @@ machine_arch_initcall(p1021_mds, swiotlb_setup_bus_notifier);
 
 static void __init mpc85xx_mds_pic_init(void)
 {
-        struct mpic *mpic = mpic_alloc(NULL, 0,
-                        MPIC_WANTS_RESET | MPIC_BIG_ENDIAN |
-                        MPIC_BROKEN_FRR_NIRQS | MPIC_SINGLE_DEST_CPU,
+        struct mpic *mpic = mpic_alloc(NULL, 0, MPIC_BIG_ENDIAN |
+                        MPIC_SINGLE_DEST_CPU,
                         0, 256, " OpenPIC  ");
         BUG_ON(mpic == NULL);
 
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_rdb.c b/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
index ccf520e890b..db214cd4c82 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
@@ -1,7 +1,7 @@
 /*
  * MPC85xx RDB Board Setup
  *
- * Copyright 2009 Freescale Semiconductor Inc.
+ * Copyright 2009,2012 Freescale Semiconductor Inc.
  *
  * This program is free software; you can redistribute  it and/or modify it
  * under  the terms of  the GNU General  Public License as published by the
@@ -26,6 +26,9 @@
 #include <asm/prom.h>
 #include <asm/udbg.h>
 #include <asm/mpic.h>
+#include <asm/qe.h>
+#include <asm/qe_ic.h>
+#include <asm/fsl_guts.h>
 
 #include <sysdev/fsl_soc.h>
 #include <sysdev/fsl_pci.h>
@@ -47,21 +50,36 @@ void __init mpc85xx_rdb_pic_init(void)
         struct mpic *mpic;
         unsigned long root = of_get_flat_dt_root();
 
+#ifdef CONFIG_QUICC_ENGINE
+        struct device_node *np;
+#endif
+
         if (of_flat_dt_is_compatible(root, "fsl,MPC85XXRDB-CAMP")) {
-                mpic = mpic_alloc(NULL, 0,
-                        MPIC_BIG_ENDIAN | MPIC_BROKEN_FRR_NIRQS |
+                mpic = mpic_alloc(NULL, 0, MPIC_NO_RESET |
+                        MPIC_BIG_ENDIAN |
                         MPIC_SINGLE_DEST_CPU,
                         0, 256, " OpenPIC  ");
         } else {
                 mpic = mpic_alloc(NULL, 0,
-                  MPIC_WANTS_RESET |
-                  MPIC_BIG_ENDIAN | MPIC_BROKEN_FRR_NIRQS |
+                  MPIC_BIG_ENDIAN |
                   MPIC_SINGLE_DEST_CPU,
                   0, 256, " OpenPIC  ");
         }
 
         BUG_ON(mpic == NULL);
         mpic_init(mpic);
+
+#ifdef CONFIG_QUICC_ENGINE
+        np = of_find_compatible_node(NULL, NULL, "fsl,qe-ic");
+        if (np) {
+                qe_ic_init(np, 0, qe_ic_cascade_low_mpic,
+                                qe_ic_cascade_high_mpic);
+                of_node_put(np);
+
+        } else
+                pr_err("%s: Could not find qe-ic node\n", __func__);
+#endif
+
 }
 
 /*
@@ -69,7 +87,7 @@ void __init mpc85xx_rdb_pic_init(void)
  */
 static void __init mpc85xx_rdb_setup_arch(void)
 {
-#ifdef CONFIG_PCI
+#if defined(CONFIG_PCI) || defined(CONFIG_QUICC_ENGINE)
         struct device_node *np;
 #endif
 
@@ -85,11 +103,73 @@ static void __init mpc85xx_rdb_setup_arch(void)
 #endif
 
         mpc85xx_smp_init();
+
+#ifdef CONFIG_QUICC_ENGINE
+        np = of_find_compatible_node(NULL, NULL, "fsl,qe");
+        if (!np) {
+                pr_err("%s: Could not find Quicc Engine node\n", __func__);
+                goto qe_fail;
+        }
+
+        qe_reset();
+        of_node_put(np);
+
+        np = of_find_node_by_name(NULL, "par_io");
+        if (np) {
+                struct device_node *ucc;
+
+                par_io_init(np);
+                of_node_put(np);
+
+                for_each_node_by_name(ucc, "ucc")
+                        par_io_of_config(ucc);
+
+        }
+#if defined(CONFIG_UCC_GETH) || defined(CONFIG_SERIAL_QE)
+        if (machine_is(p1025_rdb)) {
+
+                struct ccsr_guts_85xx __iomem *guts;
+
+                np = of_find_node_by_name(NULL, "global-utilities");
+                if (np) {
+                        guts = of_iomap(np, 0);
+                        if (!guts) {
+
+                                pr_err("mpc85xx-rdb: could not map global utilities register\n");
+
+                        } else {
+                        /* P1025 has pins muxed for QE and other functions. To
+                        * enable QE UEC mode, we need to set bit QE0 for UCC1
+                        * in Eth mode, QE0 and QE3 for UCC5 in Eth mode, QE9
+                        * and QE12 for QE MII management singals in PMUXCR
+                        * register.
+                        */
+                                setbits32(&guts->pmuxcr, MPC85xx_PMUXCR_QE(0) |
+                                                MPC85xx_PMUXCR_QE(3) |
+                                                MPC85xx_PMUXCR_QE(9) |
+                                                MPC85xx_PMUXCR_QE(12));
+                                iounmap(guts);
+                        }
+                        of_node_put(np);
+                }
+
+        }
+#endif
+
+qe_fail:
+#endif  /* CONFIG_QUICC_ENGINE */
+
         printk(KERN_INFO "MPC85xx RDB board from Freescale Semiconductor\n");
 }
 
 machine_device_initcall(p2020_rdb, mpc85xx_common_publish_devices);
+machine_device_initcall(p2020_rdb_pc, mpc85xx_common_publish_devices);
+machine_device_initcall(p1020_mbg_pc, mpc85xx_common_publish_devices);
 machine_device_initcall(p1020_rdb, mpc85xx_common_publish_devices);
+machine_device_initcall(p1020_rdb_pc, mpc85xx_common_publish_devices);
+machine_device_initcall(p1020_utm_pc, mpc85xx_common_publish_devices);
+machine_device_initcall(p1021_rdb_pc, mpc85xx_common_publish_devices);
+machine_device_initcall(p1025_rdb, mpc85xx_common_publish_devices);
 
 /*
  * Called very early, device-tree isn't unflattened
@@ -112,6 +192,52 @@ static int __init p1020_rdb_probe(void)
         return 0;
 }
 
+static int __init p1020_rdb_pc_probe(void)
+{
+        unsigned long root = of_get_flat_dt_root();
+
+        return of_flat_dt_is_compatible(root, "fsl,P1020RDB-PC");
+}
+
+static int __init p1021_rdb_pc_probe(void)
+{
+        unsigned long root = of_get_flat_dt_root();
+
+        if (of_flat_dt_is_compatible(root, "fsl,P1021RDB-PC"))
+                return 1;
+        return 0;
+}
+
+static int __init p2020_rdb_pc_probe(void)
+{
+        unsigned long root = of_get_flat_dt_root();
+
+        if (of_flat_dt_is_compatible(root, "fsl,P2020RDB-PC"))
+                return 1;
+        return 0;
+}
+
+static int __init p1025_rdb_probe(void)
+{
+        unsigned long root = of_get_flat_dt_root();
+
+        return of_flat_dt_is_compatible(root, "fsl,P1025RDB");
+}
+
+static int __init p1020_mbg_pc_probe(void)
+{
+        unsigned long root = of_get_flat_dt_root();
+
+        return of_flat_dt_is_compatible(root, "fsl,P1020MBG-PC");
+}
+
+static int __init p1020_utm_pc_probe(void)
+{
+        unsigned long root = of_get_flat_dt_root();
+
+        return of_flat_dt_is_compatible(root, "fsl,P1020UTM-PC");
+}
+
 define_machine(p2020_rdb) {
         .name                   = "P2020 RDB",
         .probe                  = p2020_rdb_probe,
@@ -139,3 +265,87 @@ define_machine(p1020_rdb) {
         .calibrate_decr         = generic_calibrate_decr,
         .progress               = udbg_progress,
 };
+
+define_machine(p1021_rdb_pc) {
+        .name                   = "P1021 RDB-PC",
+        .probe                  = p1021_rdb_pc_probe,
+        .setup_arch             = mpc85xx_rdb_setup_arch,
+        .init_IRQ               = mpc85xx_rdb_pic_init,
+#ifdef CONFIG_PCI
+        .pcibios_fixup_bus      = fsl_pcibios_fixup_bus,
+#endif
+        .get_irq                = mpic_get_irq,
+        .restart                = fsl_rstcr_restart,
+        .calibrate_decr         = generic_calibrate_decr,
+        .progress               = udbg_progress,
+};
+
+define_machine(p2020_rdb_pc) {
+        .name                   = "P2020RDB-PC",
+        .probe                  = p2020_rdb_pc_probe,
+        .setup_arch             = mpc85xx_rdb_setup_arch,
+        .init_IRQ               = mpc85xx_rdb_pic_init,
+#ifdef CONFIG_PCI
+        .pcibios_fixup_bus      = fsl_pcibios_fixup_bus,
+#endif
+        .get_irq                = mpic_get_irq,
+        .restart                = fsl_rstcr_restart,
+        .calibrate_decr         = generic_calibrate_decr,
+        .progress               = udbg_progress,
+};
+
+define_machine(p1025_rdb) {
+        .name                   = "P1025 RDB",
+        .probe                  = p1025_rdb_probe,
+        .setup_arch             = mpc85xx_rdb_setup_arch,
+        .init_IRQ               = mpc85xx_rdb_pic_init,
+#ifdef CONFIG_PCI
+        .pcibios_fixup_bus      = fsl_pcibios_fixup_bus,
+#endif
+        .get_irq                = mpic_get_irq,
+        .restart                = fsl_rstcr_restart,
+        .calibrate_decr         = generic_calibrate_decr,
+        .progress               = udbg_progress,
+};
+
+define_machine(p1020_mbg_pc) {
+        .name                   = "P1020 MBG-PC",
+        .probe                  = p1020_mbg_pc_probe,
+        .setup_arch             = mpc85xx_rdb_setup_arch,
+        .init_IRQ               = mpc85xx_rdb_pic_init,
+#ifdef CONFIG_PCI
+        .pcibios_fixup_bus      = fsl_pcibios_fixup_bus,
+#endif
+        .get_irq                = mpic_get_irq,
+        .restart                = fsl_rstcr_restart,
+        .calibrate_decr         = generic_calibrate_decr,
+        .progress               = udbg_progress,
+};
+
+define_machine(p1020_utm_pc) {
+        .name                   = "P1020 UTM-PC",
+        .probe                  = p1020_utm_pc_probe,
+        .setup_arch             = mpc85xx_rdb_setup_arch,
+        .init_IRQ               = mpc85xx_rdb_pic_init,
+#ifdef CONFIG_PCI
+        .pcibios_fixup_bus      = fsl_pcibios_fixup_bus,
+#endif
+        .get_irq                = mpic_get_irq,
+        .restart                = fsl_rstcr_restart,
+        .calibrate_decr         = generic_calibrate_decr,
+        .progress               = udbg_progress,
+};
+
+define_machine(p1020_rdb_pc) {
+        .name                   = "P1020RDB-PC",
+        .probe                  = p1020_rdb_pc_probe,
+        .setup_arch             = mpc85xx_rdb_setup_arch,
+        .init_IRQ               = mpc85xx_rdb_pic_init,
+#ifdef CONFIG_PCI
+        .pcibios_fixup_bus      = fsl_pcibios_fixup_bus,
+#endif
+        .get_irq                = mpic_get_irq,
+        .restart                = fsl_rstcr_restart,
+        .calibrate_decr         = generic_calibrate_decr,
+        .progress               = udbg_progress,
+};
diff --git a/arch/powerpc/platforms/85xx/p1010rdb.c b/arch/powerpc/platforms/85xx/p1010rdb.c
index 538bc3f57e9..d8bd6563d9c 100644
--- a/arch/powerpc/platforms/85xx/p1010rdb.c
+++ b/arch/powerpc/platforms/85xx/p1010rdb.c
@@ -32,9 +32,8 @@
 
 void __init p1010_rdb_pic_init(void)
 {
-        struct mpic *mpic = mpic_alloc(NULL, 0,
-          MPIC_WANTS_RESET | MPIC_BIG_ENDIAN |
-          MPIC_BROKEN_FRR_NIRQS | MPIC_SINGLE_DEST_CPU,
+        struct mpic *mpic = mpic_alloc(NULL, 0, MPIC_BIG_ENDIAN |
+          MPIC_SINGLE_DEST_CPU,
           0, 256, " OpenPIC  ");
 
         BUG_ON(mpic == NULL);
diff --git a/arch/powerpc/platforms/85xx/p1022_ds.c b/arch/powerpc/platforms/85xx/p1022_ds.c
index b0984ada3f8..0fe88e39945 100644
--- a/arch/powerpc/platforms/85xx/p1022_ds.c
+++ b/arch/powerpc/platforms/85xx/p1022_ds.c
@@ -33,6 +33,10 @@
 
 #if defined(CONFIG_FB_FSL_DIU) || defined(CONFIG_FB_FSL_DIU_MODULE)
 
+#define PMUXCR_ELBCDIU_MASK     0xc0000000
+#define PMUXCR_ELBCDIU_NOR16    0x80000000
+#define PMUXCR_ELBCDIU_DIU      0x40000000
+
 /*
  * Board-specific initialization of the DIU.  This code should probably be
  * executed when the DIU is opened, rather than in arch code, but the DIU
@@ -50,11 +54,22 @@
 #define CLKDVDR_PXCLK_MASK      0x00FF0000
 
 /* Some ngPIXIS register definitions */
+#define PX_CTL          3
+#define PX_BRDCFG0      8
+#define PX_BRDCFG1      9
+
+#define PX_BRDCFG0_ELBC_SPI_MASK        0xc0
+#define PX_BRDCFG0_ELBC_SPI_ELBC        0x00
+#define PX_BRDCFG0_ELBC_SPI_NULL        0xc0
+#define PX_BRDCFG0_ELBC_DIU             0x02
+
 #define PX_BRDCFG1_DVIEN        0x80
 #define PX_BRDCFG1_DFPEN        0x40
 #define PX_BRDCFG1_BACKLIGHT    0x20
 #define PX_BRDCFG1_DDCEN        0x10
 
+#define PX_CTL_ALTACC           0x80
+
 /*
  * DIU Area Descriptor
  *
@@ -133,44 +148,117 @@ static void p1022ds_set_gamma_table(enum fsl_diu_monitor_port port,
  */
 static void p1022ds_set_monitor_port(enum fsl_diu_monitor_port port)
 {
-        struct device_node *np;
-        void __iomem *pixis;
-        u8 __iomem *brdcfg1;
-
-        np = of_find_compatible_node(NULL, NULL, "fsl,p1022ds-fpga");
-        if (!np)
-                /* older device trees used "fsl,p1022ds-pixis" */
-                np = of_find_compatible_node(NULL, NULL, "fsl,p1022ds-pixis");
-        if (!np) {
-                pr_err("p1022ds: missing ngPIXIS node\n");
+        struct device_node *guts_node;
+        struct device_node *indirect_node = NULL;
+        struct ccsr_guts_85xx __iomem *guts;
+        u8 __iomem *lbc_lcs0_ba = NULL;
+        u8 __iomem *lbc_lcs1_ba = NULL;
+        u8 b;
+
+        /* Map the global utilities registers. */
+        guts_node = of_find_compatible_node(NULL, NULL, "fsl,p1022-guts");
+        if (!guts_node) {
+                pr_err("p1022ds: missing global utilties device node\n");
                 return;
         }
 
-        pixis = of_iomap(np, 0);
-        if (!pixis) {
-                pr_err("p1022ds: could not map ngPIXIS registers\n");
-                return;
+        guts = of_iomap(guts_node, 0);
+        if (!guts) {
+                pr_err("p1022ds: could not map global utilties device\n");
+                goto exit;
         }
-        brdcfg1 = pixis + 9;    /* BRDCFG1 is at offset 9 in the ngPIXIS */
+
+        indirect_node = of_find_compatible_node(NULL, NULL,
+                                             "fsl,p1022ds-indirect-pixis");
+        if (!indirect_node) {
+                pr_err("p1022ds: missing pixis indirect mode node\n");
+                goto exit;
+        }
+
+        lbc_lcs0_ba = of_iomap(indirect_node, 0);
+        if (!lbc_lcs0_ba) {
+                pr_err("p1022ds: could not map localbus chip select 0\n");
+                goto exit;
+        }
+
+        lbc_lcs1_ba = of_iomap(indirect_node, 1);
+        if (!lbc_lcs1_ba) {
+                pr_err("p1022ds: could not map localbus chip select 1\n");
+                goto exit;
+        }
+
+        /* Make sure we're in indirect mode first. */
+        if ((in_be32(&guts->pmuxcr) & PMUXCR_ELBCDIU_MASK) !=
+            PMUXCR_ELBCDIU_DIU) {
+                struct device_node *pixis_node;
+                void __iomem *pixis;
+
+                pixis_node =
+                        of_find_compatible_node(NULL, NULL, "fsl,p1022ds-fpga");
+                if (!pixis_node) {
+                        pr_err("p1022ds: missing pixis node\n");
+                        goto exit;
+                }
+
+                pixis = of_iomap(pixis_node, 0);
+                of_node_put(pixis_node);
+                if (!pixis) {
+                        pr_err("p1022ds: could not map pixis registers\n");
+                        goto exit;
+                }
+
+                /* Enable indirect PIXIS mode.  */
+                setbits8(pixis + PX_CTL, PX_CTL_ALTACC);
+                iounmap(pixis);
+
+                /* Switch the board mux to the DIU */
+                out_8(lbc_lcs0_ba, PX_BRDCFG0); /* BRDCFG0 */
+                b = in_8(lbc_lcs1_ba);
+                b |= PX_BRDCFG0_ELBC_DIU;
+                out_8(lbc_lcs1_ba, b);
+
+                /* Set the chip mux to DIU mode. */
+                clrsetbits_be32(&guts->pmuxcr, PMUXCR_ELBCDIU_MASK,
+                                PMUXCR_ELBCDIU_DIU);
+                in_be32(&guts->pmuxcr);
+        }
+
 
         switch (port) {
         case FSL_DIU_PORT_DVI:
-                printk(KERN_INFO "%s:%u\n", __func__, __LINE__);
                 /* Enable the DVI port, disable the DFP and the backlight */
-                clrsetbits_8(brdcfg1, PX_BRDCFG1_DFPEN | PX_BRDCFG1_BACKLIGHT,
-                             PX_BRDCFG1_DVIEN);
+                out_8(lbc_lcs0_ba, PX_BRDCFG1);
+                b = in_8(lbc_lcs1_ba);
+                b &= ~(PX_BRDCFG1_DFPEN | PX_BRDCFG1_BACKLIGHT);
+                b |= PX_BRDCFG1_DVIEN;
+                out_8(lbc_lcs1_ba, b);
                 break;
         case FSL_DIU_PORT_LVDS:
-                printk(KERN_INFO "%s:%u\n", __func__, __LINE__);
+                /*
+                 * LVDS also needs backlight enabled, otherwise the display
+                 * will be blank.
+                 */
                 /* Enable the DFP port, disable the DVI and the backlight */
-                clrsetbits_8(brdcfg1, PX_BRDCFG1_DVIEN | PX_BRDCFG1_BACKLIGHT,
-                             PX_BRDCFG1_DFPEN);
+                out_8(lbc_lcs0_ba, PX_BRDCFG1);
+                b = in_8(lbc_lcs1_ba);
+                b &= ~PX_BRDCFG1_DVIEN;
+                b |= PX_BRDCFG1_DFPEN | PX_BRDCFG1_BACKLIGHT;
+                out_8(lbc_lcs1_ba, b);
                 break;
         default:
                 pr_err("p1022ds: unsupported monitor port %i\n", port);
         }
 
-        iounmap(pixis);
+exit:
+        if (lbc_lcs1_ba)
+                iounmap(lbc_lcs1_ba);
+        if (lbc_lcs0_ba)
+                iounmap(lbc_lcs0_ba);
+        if (guts)
+                iounmap(guts);
+
+        of_node_put(indirect_node);
+        of_node_put(guts_node);
 }
 
 /**
@@ -242,15 +330,56 @@ p1022ds_valid_monitor_port(enum fsl_diu_monitor_port port)
 
 void __init p1022_ds_pic_init(void)
 {
-        struct mpic *mpic = mpic_alloc(NULL, 0,
-                MPIC_WANTS_RESET |
-                MPIC_BIG_ENDIAN | MPIC_BROKEN_FRR_NIRQS |
+        struct mpic *mpic = mpic_alloc(NULL, 0, MPIC_BIG_ENDIAN |
                 MPIC_SINGLE_DEST_CPU,
                 0, 256, " OpenPIC  ");
         BUG_ON(mpic == NULL);
         mpic_init(mpic);
 }
 
+#if defined(CONFIG_FB_FSL_DIU) || defined(CONFIG_FB_FSL_DIU_MODULE)
+
+/*
+ * Disables a node in the device tree.
+ *
+ * This function is called before kmalloc() is available, so the 'new' object
+ * should be allocated in the global area.  The easiest way is to do that is
+ * to allocate one static local variable for each call to this function.
+ */
+static void __init disable_one_node(struct device_node *np, struct property *new)
+{
+        struct property *old;
+
+        old = of_find_property(np, new->name, NULL);
+        if (old)
+                prom_update_property(np, new, old);
+        else
+                prom_add_property(np, new);
+}
+
+/* TRUE if there is a "video=fslfb" command-line parameter. */
+static bool fslfb;
+
+/*
+ * Search for a "video=fslfb" command-line parameter, and set 'fslfb' to
+ * true if we find it.
+ *
+ * We need to use early_param() instead of __setup() because the normal
+ * __setup() gets called to late.  However, early_param() gets called very
+ * early, before the device tree is unflattened, so all we can do now is set a
+ * global variable.  Later on, p1022_ds_setup_arch() will use that variable
+ * to determine if we need to update the device tree.
+ */
+static int __init early_video_setup(char *options)
+{
+        fslfb = (strncmp(options, "fslfb:", 6) == 0);
+
+        return 0;
+}
+early_param("video", early_video_setup);
+
+#endif
+
 /*
  * Setup the architecture
  */
@@ -288,6 +417,34 @@ static void __init p1022_ds_setup_arch(void)
         diu_ops.set_monitor_port        = p1022ds_set_monitor_port;
         diu_ops.set_pixel_clock         = p1022ds_set_pixel_clock;
         diu_ops.valid_monitor_port      = p1022ds_valid_monitor_port;
+
+        /*
+         * Disable the NOR flash node if there is video=fslfb... command-line
+         * parameter.  When the DIU is active, NOR flash is unavailable, so we
+         * have to disable the node before the MTD driver loads.
+         */
+        if (fslfb) {
+                struct device_node *np =
+                        of_find_compatible_node(NULL, NULL, "fsl,p1022-elbc");
+
+                if (np) {
+                        np = of_find_compatible_node(np, NULL, "cfi-flash");
+                        if (np) {
+                                static struct property nor_status = {
+                                        .name = "status",
+                                        .value = "disabled",
+                                        .length = sizeof("disabled"),
+                                };
+
+                                pr_info("p1022ds: disabling %s node",
+                                        np->full_name);
+                                disable_one_node(np, &nor_status);
+                                of_node_put(np);
+                        }
+                }
+
+        }
+
 #endif
 
         mpc85xx_smp_init();
diff --git a/arch/powerpc/platforms/85xx/p1023_rds.c b/arch/powerpc/platforms/85xx/p1023_rds.c
index d951e7027bb..6b07398e436 100644
--- a/arch/powerpc/platforms/85xx/p1023_rds.c
+++ b/arch/powerpc/platforms/85xx/p1023_rds.c
@@ -93,9 +93,8 @@ machine_device_initcall(p1023_rds, mpc85xx_common_publish_devices);
 
 static void __init mpc85xx_rds_pic_init(void)
 {
-        struct mpic *mpic = mpic_alloc(NULL, 0,
-                MPIC_WANTS_RESET | MPIC_BIG_ENDIAN |
-                MPIC_BROKEN_FRR_NIRQS | MPIC_SINGLE_DEST_CPU,
+        struct mpic *mpic = mpic_alloc(NULL, 0, MPIC_BIG_ENDIAN |
+                MPIC_SINGLE_DEST_CPU,
                 0, 256, " OpenPIC  ");
 
         BUG_ON(mpic == NULL);
diff --git a/arch/powerpc/platforms/85xx/sbc8548.c b/arch/powerpc/platforms/85xx/sbc8548.c
index 184a5078461..1677b8a2267 100644
--- a/arch/powerpc/platforms/85xx/sbc8548.c
+++ b/arch/powerpc/platforms/85xx/sbc8548.c
@@ -54,8 +54,7 @@ static int sbc_rev;
 
 static void __init sbc8548_pic_init(void)
 {
-        struct mpic *mpic = mpic_alloc(NULL, 0,
-                        MPIC_WANTS_RESET | MPIC_BIG_ENDIAN,
+        struct mpic *mpic = mpic_alloc(NULL, 0, MPIC_BIG_ENDIAN,
                         0, 256, " OpenPIC  ");
         BUG_ON(mpic == NULL);
         mpic_init(mpic);
diff --git a/arch/powerpc/platforms/85xx/sbc8560.c b/arch/powerpc/platforms/85xx/sbc8560.c
index 940752e9305..3c3bbcc2756 100644
--- a/arch/powerpc/platforms/85xx/sbc8560.c
+++ b/arch/powerpc/platforms/85xx/sbc8560.c
@@ -41,8 +41,7 @@
 
 static void __init sbc8560_pic_init(void)
 {
-        struct mpic *mpic = mpic_alloc(NULL, 0,
-                        MPIC_WANTS_RESET | MPIC_BIG_ENDIAN,
+        struct mpic *mpic = mpic_alloc(NULL, 0, MPIC_BIG_ENDIAN,
                         0, 256, " OpenPIC  ");
         BUG_ON(mpic == NULL);
         mpic_init(mpic);
diff --git a/arch/powerpc/platforms/85xx/socrates.c b/arch/powerpc/platforms/85xx/socrates.c
index 18f635906b2..b7191921775 100644
--- a/arch/powerpc/platforms/85xx/socrates.c
+++ b/arch/powerpc/platforms/85xx/socrates.c
@@ -48,8 +48,7 @@ static void __init socrates_pic_init(void)
 {
         struct device_node *np;
 
-        struct mpic *mpic = mpic_alloc(NULL, 0,
-                        MPIC_WANTS_RESET | MPIC_BIG_ENDIAN,
+        struct mpic *mpic = mpic_alloc(NULL, 0, MPIC_BIG_ENDIAN,
                         0, 256, " OpenPIC  ");
         BUG_ON(mpic == NULL);
         mpic_init(mpic);
diff --git a/arch/powerpc/platforms/85xx/stx_gp3.c b/arch/powerpc/platforms/85xx/stx_gp3.c
index e9e5234b4e7..27ca3a7b04a 100644
--- a/arch/powerpc/platforms/85xx/stx_gp3.c
+++ b/arch/powerpc/platforms/85xx/stx_gp3.c
@@ -48,8 +48,7 @@
 
 static void __init stx_gp3_pic_init(void)
 {
-        struct mpic *mpic = mpic_alloc(NULL, 0,
-                        MPIC_WANTS_RESET | MPIC_BIG_ENDIAN,
+        struct mpic *mpic = mpic_alloc(NULL, 0, MPIC_BIG_ENDIAN,
                         0, 256, " OpenPIC  ");
         BUG_ON(mpic == NULL);
         mpic_init(mpic);
diff --git a/arch/powerpc/platforms/85xx/tqm85xx.c b/arch/powerpc/platforms/85xx/tqm85xx.c
index bf7c89fb75b..d7504cefe01 100644
--- a/arch/powerpc/platforms/85xx/tqm85xx.c
+++ b/arch/powerpc/platforms/85xx/tqm85xx.c
@@ -47,7 +47,7 @@
 static void __init tqm85xx_pic_init(void)
 {
         struct mpic *mpic = mpic_alloc(NULL, 0,
-                        MPIC_WANTS_RESET | MPIC_BIG_ENDIAN,
+                        MPIC_BIG_ENDIAN,
                         0, 256, " OpenPIC  ");
         BUG_ON(mpic == NULL);
         mpic_init(mpic);
diff --git a/arch/powerpc/platforms/85xx/xes_mpc85xx.c b/arch/powerpc/platforms/85xx/xes_mpc85xx.c
index 3a69f8b77de..503c21596c6 100644
--- a/arch/powerpc/platforms/85xx/xes_mpc85xx.c
+++ b/arch/powerpc/platforms/85xx/xes_mpc85xx.c
@@ -43,9 +43,7 @@
 
 void __init xes_mpc85xx_pic_init(void)
 {
-        struct mpic *mpic = mpic_alloc(NULL, 0,
-                          MPIC_WANTS_RESET |
-                          MPIC_BIG_ENDIAN | MPIC_BROKEN_FRR_NIRQS,
+        struct mpic *mpic = mpic_alloc(NULL, 0, MPIC_BIG_ENDIAN,
                         0, 256, " OpenPIC  ");
         BUG_ON(mpic == NULL);
         mpic_init(mpic);
diff --git a/arch/powerpc/platforms/86xx/Kconfig b/arch/powerpc/platforms/86xx/Kconfig
index 8d6599d54ea..7a6279e3821 100644
--- a/arch/powerpc/platforms/86xx/Kconfig
+++ b/arch/powerpc/platforms/86xx/Kconfig
@@ -39,6 +39,7 @@ config GEF_PPC9A
         select MMIO_NVRAM
         select GENERIC_GPIO
         select ARCH_REQUIRE_GPIOLIB
+        select GE_FPGA
         help
           This option enables support for the GE PPC9A.
 
@@ -48,6 +49,7 @@ config GEF_SBC310
         select MMIO_NVRAM
         select GENERIC_GPIO
         select ARCH_REQUIRE_GPIOLIB
+        select GE_FPGA
         help
           This option enables support for the GE SBC310.
 
@@ -57,6 +59,7 @@ config GEF_SBC610
         select MMIO_NVRAM
         select GENERIC_GPIO
         select ARCH_REQUIRE_GPIOLIB
+        select GE_FPGA
         select HAS_RAPIDIO
         help
           This option enables support for the GE SBC610.
diff --git a/arch/powerpc/platforms/86xx/Makefile b/arch/powerpc/platforms/86xx/Makefile
index 4b0d7b1aa00..ede815d6489 100644
--- a/arch/powerpc/platforms/86xx/Makefile
+++ b/arch/powerpc/platforms/86xx/Makefile
@@ -7,7 +7,6 @@ obj-$(CONFIG_SMP)		+= mpc86xx_smp.o
 obj-$(CONFIG_MPC8641_HPCN)      += mpc86xx_hpcn.o
 obj-$(CONFIG_SBC8641D)          += sbc8641d.o
 obj-$(CONFIG_MPC8610_HPCD)      += mpc8610_hpcd.o
-gef-gpio-$(CONFIG_GPIOLIB)      += gef_gpio.o
-obj-$(CONFIG_GEF_SBC610)        += gef_sbc610.o gef_pic.o $(gef-gpio-y)
-obj-$(CONFIG_GEF_SBC310)        += gef_sbc310.o gef_pic.o $(gef-gpio-y)
-obj-$(CONFIG_GEF_PPC9A)         += gef_ppc9a.o gef_pic.o $(gef-gpio-y)
+obj-$(CONFIG_GEF_SBC610)        += gef_sbc610.o
+obj-$(CONFIG_GEF_SBC310)        += gef_sbc310.o
+obj-$(CONFIG_GEF_PPC9A)         += gef_ppc9a.o
diff --git a/arch/powerpc/platforms/86xx/gef_gpio.c b/arch/powerpc/platforms/86xx/gef_gpio.c
deleted file mode 100644
index 2a703365e66..00000000000
--- a/arch/powerpc/platforms/86xx/gef_gpio.c
+++ /dev/null
@@ -1,171 +0,0 @@
-/*
- * Driver for GE FPGA based GPIO
- *
- * Author: Martyn Welch <martyn.welch@ge.com>
- *
- * 2008 (c) GE Intelligent Platforms Embedded Systems, Inc.
- *
- * This file is licensed under the terms of the GNU General Public License
- * version 2.  This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
- */
-
-/* TODO
- *
- * Configuration of output modes (totem-pole/open-drain)
- * Interrupt configuration - interrupts are always generated the FPGA relies on
- *      the I/O interrupt controllers mask to stop them propergating
- */
-
-#include <linux/kernel.h>
-#include <linux/compiler.h>
-#include <linux/init.h>
-#include <linux/io.h>
-#include <linux/of.h>
-#include <linux/of_device.h>
-#include <linux/of_platform.h>
-#include <linux/of_gpio.h>
-#include <linux/gpio.h>
-#include <linux/slab.h>
-#include <linux/module.h>
-
-#define GEF_GPIO_DIRECT         0x00
-#define GEF_GPIO_IN             0x04
-#define GEF_GPIO_OUT            0x08
-#define GEF_GPIO_TRIG           0x0C
-#define GEF_GPIO_POLAR_A        0x10
-#define GEF_GPIO_POLAR_B        0x14
-#define GEF_GPIO_INT_STAT       0x18
-#define GEF_GPIO_OVERRUN        0x1C
-#define GEF_GPIO_MODE           0x20
-
-static void _gef_gpio_set(void __iomem *reg, unsigned int offset, int value)
-{
-        unsigned int data;
-
-        data = ioread32be(reg);
-        /* value: 0=low; 1=high */
-        if (value & 0x1)
-                data = data | (0x1 << offset);
-        else
-                data = data & ~(0x1 << offset);
-
-        iowrite32be(data, reg);
-}
-
-
-static int gef_gpio_dir_in(struct gpio_chip *chip, unsigned offset)
-{
-        unsigned int data;
-        struct of_mm_gpio_chip *mmchip = to_of_mm_gpio_chip(chip);
-
-        data = ioread32be(mmchip->regs + GEF_GPIO_DIRECT);
-        data = data | (0x1 << offset);
-        iowrite32be(data, mmchip->regs + GEF_GPIO_DIRECT);
-
-        return 0;
-}
-
-static int gef_gpio_dir_out(struct gpio_chip *chip, unsigned offset, int value)
-{
-        unsigned int data;
-        struct of_mm_gpio_chip *mmchip = to_of_mm_gpio_chip(chip);
-
-        /* Set direction before switching to input */
-        _gef_gpio_set(mmchip->regs + GEF_GPIO_OUT, offset, value);
-
-        data = ioread32be(mmchip->regs + GEF_GPIO_DIRECT);
-        data = data & ~(0x1 << offset);
-        iowrite32be(data, mmchip->regs + GEF_GPIO_DIRECT);
-
-        return 0;
-}
-
-static int gef_gpio_get(struct gpio_chip *chip, unsigned offset)
-{
-        unsigned int data;
-        int state = 0;
-        struct of_mm_gpio_chip *mmchip = to_of_mm_gpio_chip(chip);
-
-        data = ioread32be(mmchip->regs + GEF_GPIO_IN);
-        state = (int)((data >> offset) & 0x1);
-
-        return state;
-}
-
-static void gef_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
-{
-        struct of_mm_gpio_chip *mmchip = to_of_mm_gpio_chip(chip);
-
-        _gef_gpio_set(mmchip->regs + GEF_GPIO_OUT, offset, value);
-}
-
-static int __init gef_gpio_init(void)
-{
-        struct device_node *np;
-        int retval;
-        struct of_mm_gpio_chip *gef_gpio_chip;
-
-        for_each_compatible_node(np, NULL, "gef,sbc610-gpio") {
-
-                pr_debug("%s: Initialising GEF GPIO\n", np->full_name);
-
-                /* Allocate chip structure */
-                gef_gpio_chip = kzalloc(sizeof(*gef_gpio_chip), GFP_KERNEL);
-                if (!gef_gpio_chip) {
-                        pr_err("%s: Unable to allocate structure\n",
-                                np->full_name);
-                        continue;
-                }
-
-                /* Setup pointers to chip functions */
-                gef_gpio_chip->gc.of_gpio_n_cells = 2;
-                gef_gpio_chip->gc.ngpio = 19;
-                gef_gpio_chip->gc.direction_input = gef_gpio_dir_in;
-                gef_gpio_chip->gc.direction_output = gef_gpio_dir_out;
-                gef_gpio_chip->gc.get = gef_gpio_get;
-                gef_gpio_chip->gc.set = gef_gpio_set;
-
-                /* This function adds a memory mapped GPIO chip */
-                retval = of_mm_gpiochip_add(np, gef_gpio_chip);
-                if (retval) {
-                        kfree(gef_gpio_chip);
-                        pr_err("%s: Unable to add GPIO\n", np->full_name);
-                }
-        }
-
-        for_each_compatible_node(np, NULL, "gef,sbc310-gpio") {
-
-                pr_debug("%s: Initialising GEF GPIO\n", np->full_name);
-
-                /* Allocate chip structure */
-                gef_gpio_chip = kzalloc(sizeof(*gef_gpio_chip), GFP_KERNEL);
-                if (!gef_gpio_chip) {
-                        pr_err("%s: Unable to allocate structure\n",
-                                np->full_name);
-                        continue;
-                }
-
-                /* Setup pointers to chip functions */
-                gef_gpio_chip->gc.of_gpio_n_cells = 2;
-                gef_gpio_chip->gc.ngpio = 6;
-                gef_gpio_chip->gc.direction_input = gef_gpio_dir_in;
-                gef_gpio_chip->gc.direction_output = gef_gpio_dir_out;
-                gef_gpio_chip->gc.get = gef_gpio_get;
-                gef_gpio_chip->gc.set = gef_gpio_set;
-
-                /* This function adds a memory mapped GPIO chip */
-                retval = of_mm_gpiochip_add(np, gef_gpio_chip);
-                if (retval) {
-                        kfree(gef_gpio_chip);
-                        pr_err("%s: Unable to add GPIO\n", np->full_name);
-                }
-        }
-
-        return 0;
-};
-arch_initcall(gef_gpio_init);
-
-MODULE_DESCRIPTION("GE I/O FPGA GPIO driver");
-MODULE_AUTHOR("Martyn Welch <martyn.welch@ge.com");
-MODULE_LICENSE("GPL");
diff --git a/arch/powerpc/platforms/86xx/gef_ppc9a.c b/arch/powerpc/platforms/86xx/gef_ppc9a.c
index 60ce07e3910..ed58b6cfd60 100644
--- a/arch/powerpc/platforms/86xx/gef_ppc9a.c
+++ b/arch/powerpc/platforms/86xx/gef_ppc9a.c
@@ -37,9 +37,9 @@
 
 #include <sysdev/fsl_pci.h>
 #include <sysdev/fsl_soc.h>
+#include <sysdev/ge/ge_pic.h>
 
 #include "mpc86xx.h"
-#include "gef_pic.h"
 
 #undef DEBUG
 
diff --git a/arch/powerpc/platforms/86xx/gef_sbc310.c b/arch/powerpc/platforms/86xx/gef_sbc310.c
index 3ecee25bf3e..710db69bd52 100644
--- a/arch/powerpc/platforms/86xx/gef_sbc310.c
+++ b/arch/powerpc/platforms/86xx/gef_sbc310.c
@@ -37,9 +37,9 @@
 
 #include <sysdev/fsl_pci.h>
 #include <sysdev/fsl_soc.h>
+#include <sysdev/ge/ge_pic.h>
 
 #include "mpc86xx.h"
-#include "gef_pic.h"
 
 #undef DEBUG
 
diff --git a/arch/powerpc/platforms/86xx/gef_sbc610.c b/arch/powerpc/platforms/86xx/gef_sbc610.c
index 5090d608d9e..4a13d2f4ac2 100644
--- a/arch/powerpc/platforms/86xx/gef_sbc610.c
+++ b/arch/powerpc/platforms/86xx/gef_sbc610.c
@@ -37,9 +37,9 @@
 
 #include <sysdev/fsl_pci.h>
 #include <sysdev/fsl_soc.h>
+#include <sysdev/ge/ge_pic.h>
 
 #include "mpc86xx.h"
-#include "gef_pic.h"
 
 #undef DEBUG
 
diff --git a/arch/powerpc/platforms/86xx/pic.c b/arch/powerpc/platforms/86xx/pic.c
index 52bbfa03153..22cc3571ae1 100644
--- a/arch/powerpc/platforms/86xx/pic.c
+++ b/arch/powerpc/platforms/86xx/pic.c
@@ -37,9 +37,8 @@ void __init mpc86xx_init_irq(void)
         int cascade_irq;
 #endif
 
-        struct mpic *mpic = mpic_alloc(NULL, 0,
-                        MPIC_WANTS_RESET | MPIC_BIG_ENDIAN |
-                        MPIC_BROKEN_FRR_NIRQS | MPIC_SINGLE_DEST_CPU,
+        struct mpic *mpic = mpic_alloc(NULL, 0, MPIC_BIG_ENDIAN |
+                        MPIC_SINGLE_DEST_CPU,
                         0, 256, " MPIC     ");
         BUG_ON(mpic == NULL);
 
diff --git a/arch/powerpc/platforms/Kconfig b/arch/powerpc/platforms/Kconfig
index 0cfb46d54b8..a35ca44ade6 100644
--- a/arch/powerpc/platforms/Kconfig
+++ b/arch/powerpc/platforms/Kconfig
@@ -2,7 +2,6 @@ menu "Platform support"
 
 source "arch/powerpc/platforms/powernv/Kconfig"
 source "arch/powerpc/platforms/pseries/Kconfig"
-source "arch/powerpc/platforms/iseries/Kconfig"
 source "arch/powerpc/platforms/chrp/Kconfig"
 source "arch/powerpc/platforms/512x/Kconfig"
 source "arch/powerpc/platforms/52xx/Kconfig"
@@ -87,6 +86,14 @@ config MPIC_WEIRD
         bool
         default n
 
+config MPIC_MSGR
+        bool "MPIC message register support"
+        depends on MPIC
+        default n
+        help
+          Enables support for the MPIC message registers.  These
+          registers are used for inter-processor communication.
+
 config PPC_I8259
         bool
         default n
@@ -138,7 +145,7 @@ config MPIC_BROKEN_REGREAD
           of the register contents in software.
 
 config IBMVIO
-        depends on PPC_PSERIES || PPC_ISERIES
+        depends on PPC_PSERIES
         bool
         default y
 
diff --git a/arch/powerpc/platforms/Makefile b/arch/powerpc/platforms/Makefile
index 2635a22bade..879b4a44849 100644
--- a/arch/powerpc/platforms/Makefile
+++ b/arch/powerpc/platforms/Makefile
@@ -16,7 +16,6 @@ obj-$(CONFIG_FSL_SOC_BOOKE)	+= 85xx/
 obj-$(CONFIG_PPC_86xx)          += 86xx/
 obj-$(CONFIG_PPC_POWERNV)       += powernv/
 obj-$(CONFIG_PPC_PSERIES)       += pseries/
-obj-$(CONFIG_PPC_ISERIES)       += iseries/
 obj-$(CONFIG_PPC_MAPLE)         += maple/
 obj-$(CONFIG_PPC_PASEMI)        += pasemi/
 obj-$(CONFIG_PPC_CELL)          += cell/
diff --git a/arch/powerpc/platforms/cell/setup.c b/arch/powerpc/platforms/cell/setup.c
index 62002a7edfe..fa3e294fd34 100644
--- a/arch/powerpc/platforms/cell/setup.c
+++ b/arch/powerpc/platforms/cell/setup.c
@@ -197,7 +197,8 @@ static void __init mpic_init_IRQ(void)
                 /* The MPIC driver will get everything it needs from the
                  * device-tree, just pass 0 to all arguments
                  */
-                mpic = mpic_alloc(dn, 0, MPIC_SECONDARY, 0, 0, " MPIC     ");
+                mpic = mpic_alloc(dn, 0, MPIC_SECONDARY | MPIC_NO_RESET,
+                                0, 0, " MPIC     ");
                 if (mpic == NULL)
                         continue;
                 mpic_init(mpic);
diff --git a/arch/powerpc/platforms/cell/spufs/inode.c b/arch/powerpc/platforms/cell/spufs/inode.c
index d4a094ca96f..1d75c92ea8f 100644
--- a/arch/powerpc/platforms/cell/spufs/inode.c
+++ b/arch/powerpc/platforms/cell/spufs/inode.c
@@ -646,6 +646,7 @@ long spufs_create(struct path *path, struct dentry *dentry,
 
 out:
         mutex_unlock(&path->dentry->d_inode->i_mutex);
+        dput(dentry);
         return ret;
 }
 
@@ -757,9 +758,9 @@ spufs_create_root(struct super_block *sb, void *data)
                 goto out_iput;
 
         ret = -ENOMEM;
-        sb->s_root = d_alloc_root(inode);
+        sb->s_root = d_make_root(inode);
         if (!sb->s_root)
-                goto out_iput;
+                goto out;
 
         return 0;
 out_iput:
@@ -828,19 +829,19 @@ static int __init spufs_init(void)
         ret = spu_sched_init();
         if (ret)
                 goto out_cache;
-        ret = register_filesystem(&spufs_type);
+        ret = register_spu_syscalls(&spufs_calls);
         if (ret)
                 goto out_sched;
-        ret = register_spu_syscalls(&spufs_calls);
+        ret = register_filesystem(&spufs_type);
         if (ret)
-                goto out_fs;
+                goto out_syscalls;
 
         spufs_init_isolated_loader();
 
         return 0;
 
-out_fs:
-        unregister_filesystem(&spufs_type);
+out_syscalls:
+        unregister_spu_syscalls(&spufs_calls);
 out_sched:
         spu_sched_exit();
 out_cache:
diff --git a/arch/powerpc/platforms/cell/spufs/syscalls.c b/arch/powerpc/platforms/cell/spufs/syscalls.c
index 8591bb62d7f..5665dcc382c 100644
--- a/arch/powerpc/platforms/cell/spufs/syscalls.c
+++ b/arch/powerpc/platforms/cell/spufs/syscalls.c
@@ -70,8 +70,6 @@ static long do_spu_create(const char __user *pathname, unsigned int flags,
         ret = PTR_ERR(dentry);
         if (!IS_ERR(dentry)) {
                 ret = spufs_create(&path, dentry, flags, mode, neighbor);
-                mutex_unlock(&path.dentry->d_inode->i_mutex);
-                dput(dentry);
                 path_put(&path);
         }
 
diff --git a/arch/powerpc/platforms/chrp/setup.c b/arch/powerpc/platforms/chrp/setup.c
index f1f17bb2c33..c665d7de6c9 100644
--- a/arch/powerpc/platforms/chrp/setup.c
+++ b/arch/powerpc/platforms/chrp/setup.c
@@ -435,7 +435,8 @@ static void __init chrp_find_openpic(void)
         if (len > 1)
                 isu_size = iranges[3];
 
-        chrp_mpic = mpic_alloc(np, opaddr, 0, isu_size, 0, " MPIC    ");
+        chrp_mpic = mpic_alloc(np, opaddr, MPIC_NO_RESET,
+                        isu_size, 0, " MPIC    ");
         if (chrp_mpic == NULL) {
                 printk(KERN_ERR "Failed to allocate MPIC structure\n");
                 goto bail;
diff --git a/arch/powerpc/platforms/embedded6xx/holly.c b/arch/powerpc/platforms/embedded6xx/holly.c
index 9cfcf20c056..ab51b21b4bd 100644
--- a/arch/powerpc/platforms/embedded6xx/holly.c
+++ b/arch/powerpc/platforms/embedded6xx/holly.c
@@ -154,11 +154,9 @@ static void __init holly_init_IRQ(void)
         struct device_node *cascade_node = NULL;
 #endif
 
-        mpic = mpic_alloc(NULL, 0,
-                        MPIC_BIG_ENDIAN | MPIC_WANTS_RESET |
+        mpic = mpic_alloc(NULL, 0, MPIC_BIG_ENDIAN |
                         MPIC_SPV_EOI | MPIC_NO_PTHROU_DIS | MPIC_REGSET_TSI108,
-                        24,
-                        NR_IRQS-4, /* num_sources used */
+                        24, 0,
                         "Tsi108_PIC");
 
         BUG_ON(mpic == NULL);
diff --git a/arch/powerpc/platforms/embedded6xx/linkstation.c b/arch/powerpc/platforms/embedded6xx/linkstation.c
index bcfad92c9ce..455e7c08742 100644
--- a/arch/powerpc/platforms/embedded6xx/linkstation.c
+++ b/arch/powerpc/platforms/embedded6xx/linkstation.c
@@ -82,8 +82,7 @@ static void __init linkstation_init_IRQ(void)
 {
         struct mpic *mpic;
 
-        mpic = mpic_alloc(NULL, 0, MPIC_WANTS_RESET,
-                        4, 32, " EPIC     ");
+        mpic = mpic_alloc(NULL, 0, 0, 4, 0, " EPIC     ");
         BUG_ON(mpic == NULL);
 
         /* PCI IRQs */
diff --git a/arch/powerpc/platforms/embedded6xx/mpc7448_hpc2.c b/arch/powerpc/platforms/embedded6xx/mpc7448_hpc2.c
index f3350d786f5..74ccce36bae 100644
--- a/arch/powerpc/platforms/embedded6xx/mpc7448_hpc2.c
+++ b/arch/powerpc/platforms/embedded6xx/mpc7448_hpc2.c
@@ -108,11 +108,9 @@ static void __init mpc7448_hpc2_init_IRQ(void)
         struct device_node *cascade_node = NULL;
 #endif
 
-        mpic = mpic_alloc(NULL, 0,
-                        MPIC_BIG_ENDIAN | MPIC_WANTS_RESET |
+        mpic = mpic_alloc(NULL, 0, MPIC_BIG_ENDIAN |
                         MPIC_SPV_EOI | MPIC_NO_PTHROU_DIS | MPIC_REGSET_TSI108,
-                        24,
-                        NR_IRQS-4, /* num_sources used */
+                        24, 0,
                         "Tsi108_PIC");
 
         BUG_ON(mpic == NULL);
diff --git a/arch/powerpc/platforms/embedded6xx/storcenter.c b/arch/powerpc/platforms/embedded6xx/storcenter.c
index afa63883496..e0ed3c71d69 100644
--- a/arch/powerpc/platforms/embedded6xx/storcenter.c
+++ b/arch/powerpc/platforms/embedded6xx/storcenter.c
@@ -84,8 +84,7 @@ static void __init storcenter_init_IRQ(void)
 {
         struct mpic *mpic;
 
-        mpic = mpic_alloc(NULL, 0, MPIC_WANTS_RESET,
-                        16, 32, " OpenPIC  ");
+        mpic = mpic_alloc(NULL, 0, 0, 16, 0, " OpenPIC  ");
         BUG_ON(mpic == NULL);
 
         /*
diff --git a/arch/powerpc/platforms/iseries/Kconfig b/arch/powerpc/platforms/iseries/Kconfig
deleted file mode 100644
index 63835e09e5c..00000000000
--- a/arch/powerpc/platforms/iseries/Kconfig
+++ /dev/null
@@ -1,39 +0,0 @@
-config PPC_ISERIES
-        bool "IBM Legacy iSeries"
-        depends on PPC64 && PPC_BOOK3S
-        select OF_DYNAMIC
-        select PPC_SMP_MUXED_IPI
-        select PPC_INDIRECT_PIO
-        select PPC_INDIRECT_MMIO
-        select PPC_PCI_CHOICE if EXPERT
-
-menu "iSeries device drivers"
-        depends on PPC_ISERIES
-
-config VIODASD
-        tristate "iSeries Virtual I/O disk support"
-        depends on BLOCK
-        select VIOPATH
-        help
-          If you are running on an iSeries system and you want to use
-          virtual disks created and managed by OS/400, say Y.
-
-config VIOCD
-        tristate "iSeries Virtual I/O CD support"
-        depends on BLOCK
-        select VIOPATH
-        help
-          If you are running Linux on an IBM iSeries system and you want to
-          read a CD drive owned by OS/400, say Y here.
-
-config VIOTAPE
-        tristate "iSeries Virtual Tape Support"
-        select VIOPATH
-        help
-          If you are running Linux on an iSeries system and you want Linux
-          to read and/or write a tape drive owned by OS/400, say Y here.
-
-endmenu
-
-config VIOPATH
-        bool
diff --git a/arch/powerpc/platforms/iseries/Makefile b/arch/powerpc/platforms/iseries/Makefile
deleted file mode 100644
index a7602b11ed9..00000000000
--- a/arch/powerpc/platforms/iseries/Makefile
+++ /dev/null
@@ -1,9 +0,0 @@
-ccflags-y       := -mno-minimal-toc
-
-obj-y += exception.o
-obj-y += hvlog.o hvlpconfig.o lpardata.o setup.o dt.o mf.o lpevents.o \
-        hvcall.o proc.o htab.o iommu.o misc.o irq.o
-obj-$(CONFIG_PCI) += pci.o
-obj-$(CONFIG_SMP) += smp.o
-obj-$(CONFIG_VIOPATH) += viopath.o vio.o
-obj-$(CONFIG_MODULES) += ksyms.o
diff --git a/arch/powerpc/platforms/iseries/call_hpt.h b/arch/powerpc/platforms/iseries/call_hpt.h
deleted file mode 100644
index 8d95fe4b554..00000000000
--- a/arch/powerpc/platforms/iseries/call_hpt.h
+++ /dev/null
@@ -1,102 +0,0 @@
-/*
- * Copyright (C) 2001  Mike Corrigan IBM Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
- */
-#ifndef _PLATFORMS_ISERIES_CALL_HPT_H
-#define _PLATFORMS_ISERIES_CALL_HPT_H
-
-/*
- * This file contains the "hypervisor call" interface which is used to
- * drive the hypervisor from the OS.
- */
-
-#include <asm/iseries/hv_call_sc.h>
-#include <asm/iseries/hv_types.h>
-#include <asm/mmu.h>
-
-#define HvCallHptGetHptAddress          HvCallHpt +  0
-#define HvCallHptGetHptPages            HvCallHpt +  1
-#define HvCallHptSetPp                  HvCallHpt +  5
-#define HvCallHptSetSwBits              HvCallHpt +  6
-#define HvCallHptUpdate                 HvCallHpt +  7
-#define HvCallHptInvalidateNoSyncICache HvCallHpt +  8
-#define HvCallHptGet                    HvCallHpt + 11
-#define HvCallHptFindNextValid          HvCallHpt + 12
-#define HvCallHptFindValid              HvCallHpt + 13
-#define HvCallHptAddValidate            HvCallHpt + 16
-#define HvCallHptInvalidateSetSwBitsGet HvCallHpt + 18
-
-
-static inline u64 HvCallHpt_getHptAddress(void)
-{
-        return HvCall0(HvCallHptGetHptAddress);
-}
-
-static inline u64 HvCallHpt_getHptPages(void)
-{
-        return HvCall0(HvCallHptGetHptPages);
-}
-
-static inline void HvCallHpt_setPp(u32 hpteIndex, u8 value)
-{
-        HvCall2(HvCallHptSetPp, hpteIndex, value);
-}
-
-static inline void HvCallHpt_setSwBits(u32 hpteIndex, u8 bitson, u8 bitsoff)
-{
-        HvCall3(HvCallHptSetSwBits, hpteIndex, bitson, bitsoff);
-}
-
-static inline void HvCallHpt_invalidateNoSyncICache(u32 hpteIndex)
-{
-        HvCall1(HvCallHptInvalidateNoSyncICache, hpteIndex);
-}
-
-static inline u64 HvCallHpt_invalidateSetSwBitsGet(u32 hpteIndex, u8 bitson,
-                u8 bitsoff)
-{
-        u64 compressedStatus;
-
-        compressedStatus = HvCall4(HvCallHptInvalidateSetSwBitsGet,
-                        hpteIndex, bitson, bitsoff, 1);
-        HvCall1(HvCallHptInvalidateNoSyncICache, hpteIndex);
-        return compressedStatus;
-}
-
-static inline u64 HvCallHpt_findValid(struct hash_pte *hpte, u64 vpn)
-{
-        return HvCall3Ret16(HvCallHptFindValid, hpte, vpn, 0, 0);
-}
-
-static inline u64 HvCallHpt_findNextValid(struct hash_pte *hpte, u32 hpteIndex,
-                u8 bitson, u8 bitsoff)
-{
-        return HvCall3Ret16(HvCallHptFindNextValid, hpte, hpteIndex,
-                        bitson, bitsoff);
-}
-
-static inline void HvCallHpt_get(struct hash_pte *hpte, u32 hpteIndex)
-{
-        HvCall2Ret16(HvCallHptGet, hpte, hpteIndex, 0);
-}
-
-static inline void HvCallHpt_addValidate(u32 hpteIndex, u32 hBit,
-                                         struct hash_pte *hpte)
-{
-        HvCall4(HvCallHptAddValidate, hpteIndex, hBit, hpte->v, hpte->r);
-}
-
-#endif /* _PLATFORMS_ISERIES_CALL_HPT_H */
diff --git a/arch/powerpc/platforms/iseries/call_pci.h b/arch/powerpc/platforms/iseries/call_pci.h
deleted file mode 100644
index dbdf69850ed..00000000000
--- a/arch/powerpc/platforms/iseries/call_pci.h
+++ /dev/null
@@ -1,309 +0,0 @@
-/*
- * Provides the Hypervisor PCI calls for iSeries Linux Parition.
- * Copyright (C) 2001  <Wayne G Holm> <IBM Corporation>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the:
- * Free Software Foundation, Inc.,
- * 59 Temple Place, Suite 330,
- * Boston, MA  02111-1307  USA
- *
- * Change Activity:
- *   Created, Jan 9, 2001
- */
-
-#ifndef _PLATFORMS_ISERIES_CALL_PCI_H
-#define _PLATFORMS_ISERIES_CALL_PCI_H
-
-#include <asm/iseries/hv_call_sc.h>
-#include <asm/iseries/hv_types.h>
-
-/*
- * DSA == Direct Select Address
- * this struct must be 64 bits in total
- */
-struct HvCallPci_DsaAddr {
-        u16             busNumber;              /* PHB index? */
-        u8              subBusNumber;           /* PCI bus number? */
-        u8              deviceId;               /* device and function? */
-        u8              barNumber;
-        u8              reserved[3];
-};
-
-union HvDsaMap {
-        u64     DsaAddr;
-        struct HvCallPci_DsaAddr Dsa;
-};
-
-struct HvCallPci_LoadReturn {
-        u64             rc;
-        u64             value;
-};
-
-enum HvCallPci_DeviceType {
-        HvCallPci_NodeDevice    = 1,
-        HvCallPci_SpDevice      = 2,
-        HvCallPci_IopDevice     = 3,
-        HvCallPci_BridgeDevice  = 4,
-        HvCallPci_MultiFunctionDevice = 5,
-        HvCallPci_IoaDevice     = 6
-};
-
-
-struct HvCallPci_DeviceInfo {
-        u32     deviceType;             /* See DeviceType enum for values */
-};
-
-struct HvCallPci_BusUnitInfo {
-        u32     sizeReturned;           /* length of data returned */
-        u32     deviceType;             /* see DeviceType enum for values */
-};
-
-struct HvCallPci_BridgeInfo {
-        struct HvCallPci_BusUnitInfo busUnitInfo;  /* Generic bus unit info */
-        u8              subBusNumber;   /* Bus number of secondary bus */
-        u8              maxAgents;      /* Max idsels on secondary bus */
-        u8              maxSubBusNumber; /* Max Sub Bus */
-        u8              logicalSlotNumber; /* Logical Slot Number for IOA */
-};
-
-
-/*
- * Maximum BusUnitInfo buffer size.  Provided for clients so
- * they can allocate a buffer big enough for any type of bus
- * unit.  Increase as needed.
- */
-enum {HvCallPci_MaxBusUnitInfoSize = 128};
-
-struct HvCallPci_BarParms {
-        u64             vaddr;
-        u64             raddr;
-        u64             size;
-        u64             protectStart;
-        u64             protectEnd;
-        u64             relocationOffset;
-        u64             pciAddress;
-        u64             reserved[3];
-};
-
-enum HvCallPci_VpdType {
-        HvCallPci_BusVpd        = 1,
-        HvCallPci_BusAdapterVpd = 2
-};
-
-#define HvCallPciConfigLoad8            HvCallPci + 0
-#define HvCallPciConfigLoad16           HvCallPci + 1
-#define HvCallPciConfigLoad32           HvCallPci + 2
-#define HvCallPciConfigStore8           HvCallPci + 3
-#define HvCallPciConfigStore16          HvCallPci + 4
-#define HvCallPciConfigStore32          HvCallPci + 5
-#define HvCallPciEoi                    HvCallPci + 16
-#define HvCallPciGetBarParms            HvCallPci + 18
-#define HvCallPciMaskFisr               HvCallPci + 20
-#define HvCallPciUnmaskFisr             HvCallPci + 21
-#define HvCallPciSetSlotReset           HvCallPci + 25
-#define HvCallPciGetDeviceInfo          HvCallPci + 27
-#define HvCallPciGetCardVpd             HvCallPci + 28
-#define HvCallPciBarLoad8               HvCallPci + 40
-#define HvCallPciBarLoad16              HvCallPci + 41
-#define HvCallPciBarLoad32              HvCallPci + 42
-#define HvCallPciBarLoad64              HvCallPci + 43
-#define HvCallPciBarStore8              HvCallPci + 44
-#define HvCallPciBarStore16             HvCallPci + 45
-#define HvCallPciBarStore32             HvCallPci + 46
-#define HvCallPciBarStore64             HvCallPci + 47
-#define HvCallPciMaskInterrupts         HvCallPci + 48
-#define HvCallPciUnmaskInterrupts       HvCallPci + 49
-#define HvCallPciGetBusUnitInfo         HvCallPci + 50
-
-static inline u64 HvCallPci_configLoad16(u16 busNumber, u8 subBusNumber,
-                u8 deviceId, u32 offset, u16 *value)
-{
-        struct HvCallPci_DsaAddr dsa;
-        struct HvCallPci_LoadReturn retVal;
-
-        *((u64*)&dsa) = 0;
-
-        dsa.busNumber = busNumber;
-        dsa.subBusNumber = subBusNumber;
-        dsa.deviceId = deviceId;
-
-        HvCall3Ret16(HvCallPciConfigLoad16, &retVal, *(u64 *)&dsa, offset, 0);
-
-        *value = retVal.value;
-
-        return retVal.rc;
-}
-
-static inline u64 HvCallPci_configLoad32(u16 busNumber, u8 subBusNumber,
-                u8 deviceId, u32 offset, u32 *value)
-{
-        struct HvCallPci_DsaAddr dsa;
-        struct HvCallPci_LoadReturn retVal;
-
-        *((u64*)&dsa) = 0;
-
-        dsa.busNumber = busNumber;
-        dsa.subBusNumber = subBusNumber;
-        dsa.deviceId = deviceId;
-
-        HvCall3Ret16(HvCallPciConfigLoad32, &retVal, *(u64 *)&dsa, offset, 0);
-
-        *value = retVal.value;
-
-        return retVal.rc;
-}
-
-static inline u64 HvCallPci_configStore8(u16 busNumber, u8 subBusNumber,
-                u8 deviceId, u32 offset, u8 value)
-{
-        struct HvCallPci_DsaAddr dsa;
-
-        *((u64*)&dsa) = 0;
-
-        dsa.busNumber = busNumber;
-        dsa.subBusNumber = subBusNumber;
-        dsa.deviceId = deviceId;
-
-        return HvCall4(HvCallPciConfigStore8, *(u64 *)&dsa, offset, value, 0);
-}
-
-static inline u64 HvCallPci_eoi(u16 busNumberParm, u8 subBusParm,
-                u8 deviceIdParm)
-{
-        struct HvCallPci_DsaAddr dsa;
-        struct HvCallPci_LoadReturn retVal;
-
-        *((u64*)&dsa) = 0;
-
-        dsa.busNumber = busNumberParm;
-        dsa.subBusNumber = subBusParm;
-        dsa.deviceId = deviceIdParm;
-
-        HvCall1Ret16(HvCallPciEoi, &retVal, *(u64*)&dsa);
-
-        return retVal.rc;
-}
-
-static inline u64 HvCallPci_getBarParms(u16 busNumberParm, u8 subBusParm,
-                u8 deviceIdParm, u8 barNumberParm, u64 parms, u32 sizeofParms)
-{
-        struct HvCallPci_DsaAddr dsa;
-
-        *((u64*)&dsa) = 0;
-
-        dsa.busNumber = busNumberParm;
-        dsa.subBusNumber = subBusParm;
-        dsa.deviceId = deviceIdParm;
-        dsa.barNumber = barNumberParm;
-
-        return HvCall3(HvCallPciGetBarParms, *(u64*)&dsa, parms, sizeofParms);
-}
-
-static inline u64 HvCallPci_maskFisr(u16 busNumberParm, u8 subBusParm,
-                u8 deviceIdParm, u64 fisrMask)
-{
-        struct HvCallPci_DsaAddr dsa;
-
-        *((u64*)&dsa) = 0;
-
-        dsa.busNumber = busNumberParm;
-        dsa.subBusNumber = subBusParm;
-        dsa.deviceId = deviceIdParm;
-
-        return HvCall2(HvCallPciMaskFisr, *(u64*)&dsa, fisrMask);
-}
-
-static inline u64 HvCallPci_unmaskFisr(u16 busNumberParm, u8 subBusParm,
-                u8 deviceIdParm, u64 fisrMask)
-{
-        struct HvCallPci_DsaAddr dsa;
-
-        *((u64*)&dsa) = 0;
-
-        dsa.busNumber = busNumberParm;
-        dsa.subBusNumber = subBusParm;
-        dsa.deviceId = deviceIdParm;
-
-        return HvCall2(HvCallPciUnmaskFisr, *(u64*)&dsa, fisrMask);
-}
-
-static inline u64 HvCallPci_getDeviceInfo(u16 busNumberParm, u8 subBusParm,
-                u8 deviceNumberParm, u64 parms, u32 sizeofParms)
-{
-        struct HvCallPci_DsaAddr dsa;
-
-        *((u64*)&dsa) = 0;
-
-        dsa.busNumber = busNumberParm;
-        dsa.subBusNumber = subBusParm;
-        dsa.deviceId = deviceNumberParm << 4;
-
-        return HvCall3(HvCallPciGetDeviceInfo, *(u64*)&dsa, parms, sizeofParms);
-}
-
-static inline u64 HvCallPci_maskInterrupts(u16 busNumberParm, u8 subBusParm,
-                u8 deviceIdParm, u64 interruptMask)
-{
-        struct HvCallPci_DsaAddr dsa;
-
-        *((u64*)&dsa) = 0;
-
-        dsa.busNumber = busNumberParm;
-        dsa.subBusNumber = subBusParm;
-        dsa.deviceId = deviceIdParm;
-
-        return HvCall2(HvCallPciMaskInterrupts, *(u64*)&dsa, interruptMask);
-}
-
-static inline u64 HvCallPci_unmaskInterrupts(u16 busNumberParm, u8 subBusParm,
-                u8 deviceIdParm, u64 interruptMask)
-{
-        struct HvCallPci_DsaAddr dsa;
-
-        *((u64*)&dsa) = 0;
-
-        dsa.busNumber = busNumberParm;
-        dsa.subBusNumber = subBusParm;
-        dsa.deviceId = deviceIdParm;
-
-        return HvCall2(HvCallPciUnmaskInterrupts, *(u64*)&dsa, interruptMask);
-}
-
-static inline u64 HvCallPci_getBusUnitInfo(u16 busNumberParm, u8 subBusParm,
-                u8 deviceIdParm, u64 parms, u32 sizeofParms)
-{
-        struct HvCallPci_DsaAddr dsa;
-
-        *((u64*)&dsa) = 0;
-
-        dsa.busNumber = busNumberParm;
-        dsa.subBusNumber = subBusParm;
-        dsa.deviceId = deviceIdParm;
-
-        return HvCall3(HvCallPciGetBusUnitInfo, *(u64*)&dsa, parms,
-                        sizeofParms);
-}
-
-static inline int HvCallPci_getBusVpd(u16 busNumParm, u64 destParm,
-                u16 sizeParm)
-{
-        u64 xRc = HvCall4(HvCallPciGetCardVpd, busNumParm, destParm,
-                        sizeParm, HvCallPci_BusVpd);
-        if (xRc == -1)
-                return -1;
-        else
-                return xRc & 0xFFFF;
-}
-
-#endif /* _PLATFORMS_ISERIES_CALL_PCI_H */
diff --git a/arch/powerpc/platforms/iseries/call_sm.h b/arch/powerpc/platforms/iseries/call_sm.h
deleted file mode 100644
index c7e251619f4..00000000000
--- a/arch/powerpc/platforms/iseries/call_sm.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/*
- * Copyright (C) 2001  Mike Corrigan IBM Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
- */
-#ifndef _ISERIES_CALL_SM_H
-#define _ISERIES_CALL_SM_H
-
-/*
- * This file contains the "hypervisor call" interface which is used to
- * drive the hypervisor from the OS.
- */
-
-#include <asm/iseries/hv_call_sc.h>
-#include <asm/iseries/hv_types.h>
-
-#define HvCallSmGet64BitsOfAccessMap    HvCallSm  + 11
-
-static inline u64 HvCallSm_get64BitsOfAccessMap(HvLpIndex lpIndex,
-                u64 indexIntoBitMap)
-{
-        return HvCall2(HvCallSmGet64BitsOfAccessMap, lpIndex, indexIntoBitMap);
-}
-
-#endif /* _ISERIES_CALL_SM_H */
diff --git a/arch/powerpc/platforms/iseries/dt.c b/arch/powerpc/platforms/iseries/dt.c
deleted file mode 100644
index f0491cc2890..00000000000
--- a/arch/powerpc/platforms/iseries/dt.c
+++ /dev/null
@@ -1,643 +0,0 @@
-/*
- *    Copyright (C) 2005-2006 Michael Ellerman, IBM Corporation
- *    Copyright (C) 2000-2004, IBM Corporation
- *
- *    Description:
- *      This file contains all the routines to build a flattened device
- *      tree for a legacy iSeries machine.
- *
- *      This program is free software; you can redistribute it and/or
- *      modify it under the terms of the GNU General Public License
- *      as published by the Free Software Foundation; either version
- *      2 of the License, or (at your option) any later version.
- */
-
-#undef DEBUG
-
-#include <linux/types.h>
-#include <linux/init.h>
-#include <linux/pci.h>
-#include <linux/pci_regs.h>
-#include <linux/pci_ids.h>
-#include <linux/threads.h>
-#include <linux/bitops.h>
-#include <linux/string.h>
-#include <linux/kernel.h>
-#include <linux/if_ether.h>     /* ETH_ALEN */
-
-#include <asm/machdep.h>
-#include <asm/prom.h>
-#include <asm/lppaca.h>
-#include <asm/cputable.h>
-#include <asm/abs_addr.h>
-#include <asm/system.h>
-#include <asm/iseries/hv_types.h>
-#include <asm/iseries/hv_lp_config.h>
-#include <asm/iseries/hv_call_xm.h>
-#include <asm/udbg.h>
-
-#include "processor_vpd.h"
-#include "call_hpt.h"
-#include "call_pci.h"
-#include "pci.h"
-#include "it_exp_vpd_panel.h"
-#include "naca.h"
-
-#ifdef DEBUG
-#define DBG(fmt...) udbg_printf(fmt)
-#else
-#define DBG(fmt...)
-#endif
-
-/*
- * These are created by the linker script at the start and end
- * of the section containing all the strings marked with the DS macro.
- */
-extern char __dt_strings_start[];
-extern char __dt_strings_end[];
-
-#define DS(s)   ({      \
-        static const char __s[] __attribute__((section(".dt_strings"))) = s; \
-        __s;            \
-})
-
-struct iseries_flat_dt {
-        struct boot_param_header header;
-        u64 reserve_map[2];
-};
-
-static void * __initdata dt_data;
-
-/*
- * Putting these strings here keeps them out of the .dt_strings section
- * that we capture for the strings blob of the flattened device tree.
- */
-static char __initdata device_type_cpu[] = "cpu";
-static char __initdata device_type_memory[] = "memory";
-static char __initdata device_type_serial[] = "serial";
-static char __initdata device_type_network[] = "network";
-static char __initdata device_type_pci[] = "pci";
-static char __initdata device_type_vdevice[] = "vdevice";
-static char __initdata device_type_vscsi[] = "vscsi";
-
-
-/* EBCDIC to ASCII conversion routines */
-
-static unsigned char __init e2a(unsigned char x)
-{
-        switch (x) {
-        case 0x81 ... 0x89:
-                return x - 0x81 + 'a';
-        case 0x91 ... 0x99:
-                return x - 0x91 + 'j';
-        case 0xA2 ... 0xA9:
-                return x - 0xA2 + 's';
-        case 0xC1 ... 0xC9:
-                return x - 0xC1 + 'A';
-        case 0xD1 ... 0xD9:
-                return x - 0xD1 + 'J';
-        case 0xE2 ... 0xE9:
-                return x - 0xE2 + 'S';
-        case 0xF0 ... 0xF9:
-                return x - 0xF0 + '0';
-        }
-        return ' ';
-}
-
-static unsigned char * __init strne2a(unsigned char *dest,
-                const unsigned char *src, size_t n)
-{
-        int i;
-
-        n = strnlen(src, n);
-
-        for (i = 0; i < n; i++)
-                dest[i] = e2a(src[i]);
-
-        return dest;
-}
-
-static struct iseries_flat_dt * __init dt_init(void)
-{
-        struct iseries_flat_dt *dt;
-        unsigned long str_len;
-
-        str_len = __dt_strings_end - __dt_strings_start;
-        dt = (struct iseries_flat_dt *)ALIGN(klimit, 8);
-        dt->header.off_mem_rsvmap =
-                offsetof(struct iseries_flat_dt, reserve_map);
-        dt->header.off_dt_strings = ALIGN(sizeof(*dt), 8);
-        dt->header.off_dt_struct = dt->header.off_dt_strings
-                + ALIGN(str_len, 8);
-        dt_data = (void *)((unsigned long)dt + dt->header.off_dt_struct);
-        dt->header.dt_strings_size = str_len;
-
-        /* There is no notion of hardware cpu id on iSeries */
-        dt->header.boot_cpuid_phys = smp_processor_id();
-
-        memcpy((char *)dt + dt->header.off_dt_strings, __dt_strings_start,
-                        str_len);
-
-        dt->header.magic = OF_DT_HEADER;
-        dt->header.version = 0x10;
-        dt->header.last_comp_version = 0x10;
-
-        dt->reserve_map[0] = 0;
-        dt->reserve_map[1] = 0;
-
-        return dt;
-}
-
-static void __init dt_push_u32(struct iseries_flat_dt *dt, u32 value)
-{
-        *((u32 *)dt_data) = value;
-        dt_data += sizeof(u32);
-}
-
-#ifdef notyet
-static void __init dt_push_u64(struct iseries_flat_dt *dt, u64 value)
-{
-        *((u64 *)dt_data) = value;
-        dt_data += sizeof(u64);
-}
-#endif
-
-static void __init dt_push_bytes(struct iseries_flat_dt *dt, const char *data,
-                int len)
-{
-        memcpy(dt_data, data, len);
-        dt_data += ALIGN(len, 4);
-}
-
-static void __init dt_start_node(struct iseries_flat_dt *dt, const char *name)
-{
-        dt_push_u32(dt, OF_DT_BEGIN_NODE);
-        dt_push_bytes(dt, name, strlen(name) + 1);
-}
-
-#define dt_end_node(dt) dt_push_u32(dt, OF_DT_END_NODE)
-
-static void __init __dt_prop(struct iseries_flat_dt *dt, const char *name,
-                const void *data, int len)
-{
-        unsigned long offset;
-
-        dt_push_u32(dt, OF_DT_PROP);
-
-        /* Length of the data */
-        dt_push_u32(dt, len);
-
-        offset = name - __dt_strings_start;
-
-        /* The offset of the properties name in the string blob. */
-        dt_push_u32(dt, (u32)offset);
-
-        /* The actual data. */
-        dt_push_bytes(dt, data, len);
-}
-#define dt_prop(dt, name, data, len)    __dt_prop((dt), DS(name), (data), (len))
-
-#define dt_prop_str(dt, name, data)     \
-        dt_prop((dt), name, (data), strlen((data)) + 1); /* + 1 for NULL */
-
-static void __init __dt_prop_u32(struct iseries_flat_dt *dt, const char *name,
-                u32 data)
-{
-        __dt_prop(dt, name, &data, sizeof(u32));
-}
-#define dt_prop_u32(dt, name, data)     __dt_prop_u32((dt), DS(name), (data))
-
-static void __init __maybe_unused __dt_prop_u64(struct iseries_flat_dt *dt,
-                const char *name, u64 data)
-{
-        __dt_prop(dt, name, &data, sizeof(u64));
-}
-#define dt_prop_u64(dt, name, data)     __dt_prop_u64((dt), DS(name), (data))
-
-#define dt_prop_u64_list(dt, name, data, n)     \
-        dt_prop((dt), name, (data), sizeof(u64) * (n))
-
-#define dt_prop_u32_list(dt, name, data, n)     \
-        dt_prop((dt), name, (data), sizeof(u32) * (n))
-
-#define dt_prop_empty(dt, name)         dt_prop((dt), name, NULL, 0)
-
-static void __init dt_cpus(struct iseries_flat_dt *dt)
-{
-        unsigned char buf[32];
-        unsigned char *p;
-        unsigned int i, index;
-        struct IoHriProcessorVpd *d;
-        u32 pft_size[2];
-
-        /* yuck */
-        snprintf(buf, 32, "PowerPC,%s", cur_cpu_spec->cpu_name);
-        p = strchr(buf, ' ');
-        if (!p) p = buf + strlen(buf);
-
-        dt_start_node(dt, "cpus");
-        dt_prop_u32(dt, "#address-cells", 1);
-        dt_prop_u32(dt, "#size-cells", 0);
-
-        pft_size[0] = 0; /* NUMA CEC cookie, 0 for non NUMA  */
-        pft_size[1] = __ilog2(HvCallHpt_getHptPages() * HW_PAGE_SIZE);
-
-        for (i = 0; i < NR_LPPACAS; i++) {
-                if (lppaca[i].dyn_proc_status >= 2)
-                        continue;
-
-                snprintf(p, 32 - (p - buf), "@%d", i);
-                dt_start_node(dt, buf);
-
-                dt_prop_str(dt, "device_type", device_type_cpu);
-
-                index = lppaca[i].dyn_hv_phys_proc_index;
-                d = &xIoHriProcessorVpd[index];
-
-                dt_prop_u32(dt, "i-cache-size", d->xInstCacheSize * 1024);
-                dt_prop_u32(dt, "i-cache-line-size", d->xInstCacheOperandSize);
-
-                dt_prop_u32(dt, "d-cache-size", d->xDataL1CacheSizeKB * 1024);
-                dt_prop_u32(dt, "d-cache-line-size", d->xDataCacheOperandSize);
-
-                /* magic conversions to Hz copied from old code */
-                dt_prop_u32(dt, "clock-frequency",
-                        ((1UL << 34) * 1000000) / d->xProcFreq);
-                dt_prop_u32(dt, "timebase-frequency",
-                        ((1UL << 32) * 1000000) / d->xTimeBaseFreq);
-
-                dt_prop_u32(dt, "reg", i);
-
-                dt_prop_u32_list(dt, "ibm,pft-size", pft_size, 2);
-
-                dt_end_node(dt);
-        }
-
-        dt_end_node(dt);
-}
-
-static void __init dt_model(struct iseries_flat_dt *dt)
-{
-        char buf[16] = "IBM,";
-
-        /* N.B. lparcfg.c knows about the "IBM," prefixes ... */
-        /* "IBM," + mfgId[2:3] + systemSerial[1:5] */
-        strne2a(buf + 4, xItExtVpdPanel.mfgID + 2, 2);
-        strne2a(buf + 6, xItExtVpdPanel.systemSerial + 1, 5);
-        buf[11] = '\0';
-        dt_prop_str(dt, "system-id", buf);
-
-        /* "IBM," + machineType[0:4] */
-        strne2a(buf + 4, xItExtVpdPanel.machineType, 4);
-        buf[8] = '\0';
-        dt_prop_str(dt, "model", buf);
-
-        dt_prop_str(dt, "compatible", "IBM,iSeries");
-        dt_prop_u32(dt, "ibm,partition-no", HvLpConfig_getLpIndex());
-}
-
-static void __init dt_initrd(struct iseries_flat_dt *dt)
-{
-#ifdef CONFIG_BLK_DEV_INITRD
-        if (naca.xRamDisk) {
-                dt_prop_u64(dt, "linux,initrd-start", (u64)naca.xRamDisk);
-                dt_prop_u64(dt, "linux,initrd-end",
-                        (u64)naca.xRamDisk + naca.xRamDiskSize * HW_PAGE_SIZE);
-        }
-#endif
-}
-
-static void __init dt_do_vdevice(struct iseries_flat_dt *dt,
-                const char *name, u32 reg, int unit,
-                const char *type, const char *compat, int end)
-{
-        char buf[32];
-
-        snprintf(buf, 32, "%s@%08x", name, reg + ((unit >= 0) ? unit : 0));
-        dt_start_node(dt, buf);
-        dt_prop_str(dt, "device_type", type);
-        if (compat)
-                dt_prop_str(dt, "compatible", compat);
-        dt_prop_u32(dt, "reg", reg + ((unit >= 0) ? unit : 0));
-        if (unit >= 0)
-                dt_prop_u32(dt, "linux,unit_address", unit);
-        if (end)
-                dt_end_node(dt);
-}
-
-static void __init dt_vdevices(struct iseries_flat_dt *dt)
-{
-        u32 reg = 0;
-        HvLpIndexMap vlan_map;
-        int i;
-
-        dt_start_node(dt, "vdevice");
-        dt_prop_str(dt, "device_type", device_type_vdevice);
-        dt_prop_str(dt, "compatible", "IBM,iSeries-vdevice");
-        dt_prop_u32(dt, "#address-cells", 1);
-        dt_prop_u32(dt, "#size-cells", 0);
-
-        dt_do_vdevice(dt, "vty", reg, -1, device_type_serial,
-                        "IBM,iSeries-vty", 1);
-        reg++;
-
-        dt_do_vdevice(dt, "v-scsi", reg, -1, device_type_vscsi,
-                        "IBM,v-scsi", 1);
-        reg++;
-
-        vlan_map = HvLpConfig_getVirtualLanIndexMap();
-        for (i = 0; i < HVMAXARCHITECTEDVIRTUALLANS; i++) {
-                unsigned char mac_addr[ETH_ALEN];
-
-                if ((vlan_map & (0x8000 >> i)) == 0)
-                        continue;
-                dt_do_vdevice(dt, "l-lan", reg, i, device_type_network,
-                                "IBM,iSeries-l-lan", 0);
-                mac_addr[0] = 0x02;
-                mac_addr[1] = 0x01;
-                mac_addr[2] = 0xff;
-                mac_addr[3] = i;
-                mac_addr[4] = 0xff;
-                mac_addr[5] = HvLpConfig_getLpIndex_outline();
-                dt_prop(dt, "local-mac-address", (char *)mac_addr, ETH_ALEN);
-                dt_prop(dt, "mac-address", (char *)mac_addr, ETH_ALEN);
-                dt_prop_u32(dt, "max-frame-size", 9000);
-                dt_prop_u32(dt, "address-bits", 48);
-
-                dt_end_node(dt);
-        }
-
-        dt_end_node(dt);
-}
-
-struct pci_class_name {
-        u16 code;
-        const char *name;
-        const char *type;
-};
-
-static struct pci_class_name __initdata pci_class_name[] = {
-        { PCI_CLASS_NETWORK_ETHERNET, "ethernet", device_type_network },
-};
-
-static struct pci_class_name * __init dt_find_pci_class_name(u16 class_code)
-{
-        struct pci_class_name *cp;
-
-        for (cp = pci_class_name;
-                        cp < &pci_class_name[ARRAY_SIZE(pci_class_name)]; cp++)
-                if (cp->code == class_code)
-                        return cp;
-        return NULL;
-}
-
-/*
- * This assumes that the node slot is always on the primary bus!
- */
-static void __init scan_bridge_slot(struct iseries_flat_dt *dt,
-                HvBusNumber bus, struct HvCallPci_BridgeInfo *bridge_info)
-{
-        HvSubBusNumber sub_bus = bridge_info->subBusNumber;
-        u16 vendor_id;
-        u16 device_id;
-        u32 class_id;
-        int err;
-        char buf[32];
-        u32 reg[5];
-        int id_sel = ISERIES_GET_DEVICE_FROM_SUBBUS(sub_bus);
-        int function = ISERIES_GET_FUNCTION_FROM_SUBBUS(sub_bus);
-        HvAgentId eads_id_sel = ISERIES_PCI_AGENTID(id_sel, function);
-        u8 devfn;
-        struct pci_class_name *cp;
-
-        /*
-         * Connect all functions of any device found.
-         */
-        for (id_sel = 1; id_sel <= bridge_info->maxAgents; id_sel++) {
-                for (function = 0; function < 8; function++) {
-                        HvAgentId agent_id = ISERIES_PCI_AGENTID(id_sel,
-                                        function);
-                        err = HvCallXm_connectBusUnit(bus, sub_bus,
-                                        agent_id, 0);
-                        if (err) {
-                                if (err != 0x302)
-                                        DBG("connectBusUnit(%x, %x, %x) %x\n",
-                                                bus, sub_bus, agent_id, err);
-                                continue;
-                        }
-
-                        err = HvCallPci_configLoad16(bus, sub_bus, agent_id,
-                                        PCI_VENDOR_ID, &vendor_id);
-                        if (err) {
-                                DBG("ReadVendor(%x, %x, %x) %x\n",
-                                        bus, sub_bus, agent_id, err);
-                                continue;
-                        }
-                        err = HvCallPci_configLoad16(bus, sub_bus, agent_id,
-                                        PCI_DEVICE_ID, &device_id);
-                        if (err) {
-                                DBG("ReadDevice(%x, %x, %x) %x\n",
-                                        bus, sub_bus, agent_id, err);
-                                continue;
-                        }
-                        err = HvCallPci_configLoad32(bus, sub_bus, agent_id,
-                                        PCI_CLASS_REVISION , &class_id);
-                        if (err) {
-                                DBG("ReadClass(%x, %x, %x) %x\n",
-                                        bus, sub_bus, agent_id, err);
-                                continue;
-                        }
-
-                        devfn = PCI_DEVFN(ISERIES_ENCODE_DEVICE(eads_id_sel),
-                                        function);
-                        cp = dt_find_pci_class_name(class_id >> 16);
-                        if (cp && cp->name)
-                                strncpy(buf, cp->name, sizeof(buf) - 1);
-                        else
-                                snprintf(buf, sizeof(buf), "pci%x,%x",
-                                                vendor_id, device_id);
-                        buf[sizeof(buf) - 1] = '\0';
-                        snprintf(buf + strlen(buf), sizeof(buf) - strlen(buf),
-                                        "@%x", PCI_SLOT(devfn));
-                        buf[sizeof(buf) - 1] = '\0';
-                        if (function != 0)
-                                snprintf(buf + strlen(buf),
-                                        sizeof(buf) - strlen(buf),
-                                        ",%x", function);
-                        dt_start_node(dt, buf);
-                        reg[0] = (bus << 16) | (devfn << 8);
-                        reg[1] = 0;
-                        reg[2] = 0;
-                        reg[3] = 0;
-                        reg[4] = 0;
-                        dt_prop_u32_list(dt, "reg", reg, 5);
-                        if (cp && (cp->type || cp->name))
-                                dt_prop_str(dt, "device_type",
-                                        cp->type ? cp->type : cp->name);
-                        dt_prop_u32(dt, "vendor-id", vendor_id);
-                        dt_prop_u32(dt, "device-id", device_id);
-                        dt_prop_u32(dt, "class-code", class_id >> 8);
-                        dt_prop_u32(dt, "revision-id", class_id & 0xff);
-                        dt_prop_u32(dt, "linux,subbus", sub_bus);
-                        dt_prop_u32(dt, "linux,agent-id", agent_id);
-                        dt_prop_u32(dt, "linux,logical-slot-number",
-                                        bridge_info->logicalSlotNumber);
-                        dt_end_node(dt);
-
-                }
-        }
-}
-
-static void __init scan_bridge(struct iseries_flat_dt *dt, HvBusNumber bus,
-                HvSubBusNumber sub_bus, int id_sel)
-{
-        struct HvCallPci_BridgeInfo bridge_info;
-        HvAgentId agent_id;
-        int function;
-        int ret;
-
-        /* Note: hvSubBus and irq is always be 0 at this level! */
-        for (function = 0; function < 8; ++function) {
-                agent_id = ISERIES_PCI_AGENTID(id_sel, function);
-                ret = HvCallXm_connectBusUnit(bus, sub_bus, agent_id, 0);
-                if (ret != 0) {
-                        if (ret != 0xb)
-                                DBG("connectBusUnit(%x, %x, %x) %x\n",
-                                                bus, sub_bus, agent_id, ret);
-                        continue;
-                }
-                DBG("found device at bus %d idsel %d func %d (AgentId %x)\n",
-                                bus, id_sel, function, agent_id);
-                ret = HvCallPci_getBusUnitInfo(bus, sub_bus, agent_id,
-                                iseries_hv_addr(&bridge_info),
-                                sizeof(struct HvCallPci_BridgeInfo));
-                if (ret != 0)
-                        continue;
-                DBG("bridge info: type %x subbus %x "
-                        "maxAgents %x maxsubbus %x logslot %x\n",
-                        bridge_info.busUnitInfo.deviceType,
-                        bridge_info.subBusNumber,
-                        bridge_info.maxAgents,
-                        bridge_info.maxSubBusNumber,
-                        bridge_info.logicalSlotNumber);
-                if (bridge_info.busUnitInfo.deviceType ==
-                                HvCallPci_BridgeDevice)
-                        scan_bridge_slot(dt, bus, &bridge_info);
-                else
-                        DBG("PCI: Invalid Bridge Configuration(0x%02X)",
-                                bridge_info.busUnitInfo.deviceType);
-        }
-}
-
-static void __init scan_phb(struct iseries_flat_dt *dt, HvBusNumber bus)
-{
-        struct HvCallPci_DeviceInfo dev_info;
-        const HvSubBusNumber sub_bus = 0;       /* EADs is always 0. */
-        int err;
-        int id_sel;
-        const int max_agents = 8;
-
-        /*
-         * Probe for EADs Bridges
-         */
-        for (id_sel = 1; id_sel < max_agents; ++id_sel) {
-                err = HvCallPci_getDeviceInfo(bus, sub_bus, id_sel,
-                                iseries_hv_addr(&dev_info),
-                                sizeof(struct HvCallPci_DeviceInfo));
-                if (err) {
-                        if (err != 0x302)
-                                DBG("getDeviceInfo(%x, %x, %x) %x\n",
-                                                bus, sub_bus, id_sel, err);
-                        continue;
-                }
-                if (dev_info.deviceType != HvCallPci_NodeDevice) {
-                        DBG("PCI: Invalid System Configuration"
-                                        "(0x%02X) for bus 0x%02x id 0x%02x.\n",
-                                        dev_info.deviceType, bus, id_sel);
-                        continue;
-                }
-                scan_bridge(dt, bus, sub_bus, id_sel);
-        }
-}
-
-static void __init dt_pci_devices(struct iseries_flat_dt *dt)
-{
-        HvBusNumber bus;
-        char buf[32];
-        u32 buses[2];
-        int phb_num = 0;
-
-        /* Check all possible buses. */
-        for (bus = 0; bus < 256; bus++) {
-                int err = HvCallXm_testBus(bus);
-
-                if (err) {
-                        /*
-                         * Check for Unexpected Return code, a clue that
-                         * something has gone wrong.
-                         */
-                        if (err != 0x0301)
-                                DBG("Unexpected Return on Probe(0x%02X) "
-                                                "0x%04X\n", bus, err);
-                        continue;
-                }
-                DBG("bus %d appears to exist\n", bus);
-                snprintf(buf, 32, "pci@%d", phb_num);
-                dt_start_node(dt, buf);
-                dt_prop_str(dt, "device_type", device_type_pci);
-                dt_prop_str(dt, "compatible", "IBM,iSeries-Logical-PHB");
-                dt_prop_u32(dt, "#address-cells", 3);
-                dt_prop_u32(dt, "#size-cells", 2);
-                buses[0] = buses[1] = bus;
-                dt_prop_u32_list(dt, "bus-range", buses, 2);
-                scan_phb(dt, bus);
-                dt_end_node(dt);
-                phb_num++;
-        }
-}
-
-static void dt_finish(struct iseries_flat_dt *dt)
-{
-        dt_push_u32(dt, OF_DT_END);
-        dt->header.totalsize = (unsigned long)dt_data - (unsigned long)dt;
-        klimit = ALIGN((unsigned long)dt_data, 8);
-}
-
-void * __init build_flat_dt(unsigned long phys_mem_size)
-{
-        struct iseries_flat_dt *iseries_dt;
-        u64 tmp[2];
-
-        iseries_dt = dt_init();
-
-        dt_start_node(iseries_dt, "");
-
-        dt_prop_u32(iseries_dt, "#address-cells", 2);
-        dt_prop_u32(iseries_dt, "#size-cells", 2);
-        dt_model(iseries_dt);
-
-        /* /memory */
-        dt_start_node(iseries_dt, "memory@0");
-        dt_prop_str(iseries_dt, "device_type", device_type_memory);
-        tmp[0] = 0;
-        tmp[1] = phys_mem_size;
-        dt_prop_u64_list(iseries_dt, "reg", tmp, 2);
-        dt_end_node(iseries_dt);
-
-        /* /chosen */
-        dt_start_node(iseries_dt, "chosen");
-        dt_prop_str(iseries_dt, "bootargs", cmd_line);
-        dt_initrd(iseries_dt);
-        dt_end_node(iseries_dt);
-
-        dt_cpus(iseries_dt);
-
-        dt_vdevices(iseries_dt);
-        dt_pci_devices(iseries_dt);
-
-        dt_end_node(iseries_dt);
-
-        dt_finish(iseries_dt);
-
-        return iseries_dt;
-}
diff --git a/arch/powerpc/platforms/iseries/exception.S b/arch/powerpc/platforms/iseries/exception.S
deleted file mode 100644
index f519ee17ff7..00000000000
--- a/arch/powerpc/platforms/iseries/exception.S
+++ /dev/null
@@ -1,311 +0,0 @@
-/*
- *  Low level routines for legacy iSeries support.
- *
- *  Extracted from head_64.S
- *
- *  PowerPC version
- *    Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
- *
- *  Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP
- *    Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu>
- *  Adapted for Power Macintosh by Paul Mackerras.
- *  Low-level exception handlers and MMU support
- *  rewritten by Paul Mackerras.
- *    Copyright (C) 1996 Paul Mackerras.
- *
- *  Adapted for 64bit PowerPC by Dave Engebretsen, Peter Bergner, and
- *    Mike Corrigan {engebret|bergner|mikejc}@us.ibm.com
- *
- *  This file contains the low-level support and setup for the
- *  PowerPC-64 platform, including trap and interrupt dispatch.
- *
- *  This program is free software; you can redistribute it and/or
- *  modify it under the terms of the GNU General Public License
- *  as published by the Free Software Foundation; either version
- *  2 of the License, or (at your option) any later version.
- */
-
-#include <asm/reg.h>
-#include <asm/ppc_asm.h>
-#include <asm/asm-offsets.h>
-#include <asm/thread_info.h>
-#include <asm/ptrace.h>
-#include <asm/cputable.h>
-#include <asm/mmu.h>
-
-#include "exception.h"
-
-        .text
-
-        .globl system_reset_iSeries
-system_reset_iSeries:
-        bl      .relative_toc
-        mfspr   r13,SPRN_SPRG3          /* Get alpaca address */
-        LOAD_REG_ADDR(r23, alpaca)
-        li      r0,ALPACA_SIZE
-        sub     r23,r13,r23
-        divdu   r24,r23,r0              /* r24 has cpu number */
-        cmpwi   0,r24,0                 /* Are we processor 0? */
-        bne     1f
-        LOAD_REG_ADDR(r13, boot_paca)
-        mtspr   SPRN_SPRG_PACA,r13      /* Save it away for the future */
-        mfmsr   r23
-        ori     r23,r23,MSR_RI
-        mtmsrd  r23                     /* RI on */
-        b       .__start_initialization_iSeries /* Start up the first processor */
-1:      mfspr   r4,SPRN_CTRLF
-        li      r5,CTRL_RUNLATCH        /* Turn off the run light */
-        andc    r4,r4,r5
-        mtspr   SPRN_CTRLT,r4
-
-/* Spin on __secondary_hold_spinloop until it is updated by the boot cpu. */
-/* In the UP case we'll yield() later, and we will not access the paca anyway */
-#ifdef CONFIG_SMP
-iSeries_secondary_wait_paca:
-        HMT_LOW
-        LOAD_REG_ADDR(r23, __secondary_hold_spinloop)
-        ld      r23,0(r23)
-
-        cmpdi   0,r23,0
-        bne     2f                      /* go on when the master is ready */
-
-        /* Keep poking the Hypervisor until we're released */
-        /* 8002 is a call to HvCallCfg::getLps, a harmless Hypervisor function */
-        lis     r3,0x8002
-        rldicr  r3,r3,32,15             /* r0 = (r3 << 32) & 0xffff000000000000 */
-        li      r0,-1                   /* r0=-1 indicates a Hypervisor call */
-        sc                              /* Invoke the hypervisor via a system call */
-        b       iSeries_secondary_wait_paca
-
-2:
-        HMT_MEDIUM
-        sync
-
-        LOAD_REG_ADDR(r3, nr_cpu_ids)   /* get number of pacas allocated */
-        lwz     r3,0(r3)                /* nr_cpus= or NR_CPUS can limit */
-        cmpld   0,r24,r3                /* is our cpu number allocated? */
-        bge     iSeries_secondary_yield /* no, yield forever */
-
-        /* Load our paca now that it's been allocated */
-        LOAD_REG_ADDR(r13, paca)
-        ld      r13,0(r13)
-        mulli   r0,r24,PACA_SIZE
-        add     r13,r13,r0
-        mtspr   SPRN_SPRG_PACA,r13      /* Save it away for the future */
-        mfmsr   r23
-        ori     r23,r23,MSR_RI
-        mtmsrd  r23                     /* RI on */
-
-iSeries_secondary_smp_loop:
-        lbz     r23,PACAPROCSTART(r13)  /* Test if this processor
-                                         * should start */
-        cmpwi   0,r23,0
-        bne     3f                      /* go on when we are told */
-
-        HMT_LOW
-        /* Let the Hypervisor know we are alive */
-        /* 8002 is a call to HvCallCfg::getLps, a harmless Hypervisor function */
-        lis     r3,0x8002
-        rldicr  r3,r3,32,15             /* r0 = (r3 << 32) & 0xffff000000000000 */
-        li      r0,-1                   /* r0=-1 indicates a Hypervisor call */
-        sc                              /* Invoke the hypervisor via a system call */
-        mfspr   r13,SPRN_SPRG_PACA      /* Put r13 back ???? */
-        b       iSeries_secondary_smp_loop /* wait for signal to start */
-
-3:
-        HMT_MEDIUM
-        sync
-        LOAD_REG_ADDR(r3,current_set)
-        sldi    r28,r24,3               /* get current_set[cpu#] */
-        ldx     r3,r3,r28
-        addi    r1,r3,THREAD_SIZE
-        subi    r1,r1,STACK_FRAME_OVERHEAD
-
-        b       __secondary_start               /* Loop until told to go */
-#endif /* CONFIG_SMP */
-
-iSeries_secondary_yield:
-        /* Yield the processor.  This is required for non-SMP kernels
-                which are running on multi-threaded machines. */
-        HMT_LOW
-        lis     r3,0x8000
-        rldicr  r3,r3,32,15             /* r3 = (r3 << 32) & 0xffff000000000000 */
-        addi    r3,r3,18                /* r3 = 0x8000000000000012 which is "yield" */
-        li      r4,0                    /* "yield timed" */
-        li      r5,-1                   /* "yield forever" */
-        li      r0,-1                   /* r0=-1 indicates a Hypervisor call */
-        sc                              /* Invoke the hypervisor via a system call */
-        mfspr   r13,SPRN_SPRG_PACA      /* Put r13 back ???? */
-        b       iSeries_secondary_yield /* If SMP not configured, secondaries
-                                         * loop forever */
-
-/***  ISeries-LPAR interrupt handlers ***/
-
-        STD_EXCEPTION_ISERIES(machine_check, PACA_EXMC)
-
-        .globl data_access_iSeries
-data_access_iSeries:
-        mtspr   SPRN_SPRG_SCRATCH0,r13
-BEGIN_FTR_SECTION
-        mfspr   r13,SPRN_SPRG_PACA
-        std     r9,PACA_EXSLB+EX_R9(r13)
-        std     r10,PACA_EXSLB+EX_R10(r13)
-        mfspr   r10,SPRN_DAR
-        mfspr   r9,SPRN_DSISR
-        srdi    r10,r10,60
-        rlwimi  r10,r9,16,0x20
-        mfcr    r9
-        cmpwi   r10,0x2c
-        beq     .do_stab_bolted_iSeries
-        ld      r10,PACA_EXSLB+EX_R10(r13)
-        std     r11,PACA_EXGEN+EX_R11(r13)
-        ld      r11,PACA_EXSLB+EX_R9(r13)
-        std     r12,PACA_EXGEN+EX_R12(r13)
-        mfspr   r12,SPRN_SPRG_SCRATCH0
-        std     r10,PACA_EXGEN+EX_R10(r13)
-        std     r11,PACA_EXGEN+EX_R9(r13)
-        std     r12,PACA_EXGEN+EX_R13(r13)
-        EXCEPTION_PROLOG_ISERIES_1
-FTR_SECTION_ELSE
-        EXCEPTION_PROLOG_1(PACA_EXGEN, NOTEST, 0)
-        EXCEPTION_PROLOG_ISERIES_1
-ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_SLB)
-        b       data_access_common
-
-.do_stab_bolted_iSeries:
-        std     r11,PACA_EXSLB+EX_R11(r13)
-        std     r12,PACA_EXSLB+EX_R12(r13)
-        mfspr   r10,SPRN_SPRG_SCRATCH0
-        std     r10,PACA_EXSLB+EX_R13(r13)
-        EXCEPTION_PROLOG_ISERIES_1
-        b       .do_stab_bolted
-
-        .globl  data_access_slb_iSeries
-data_access_slb_iSeries:
-        mtspr   SPRN_SPRG_SCRATCH0,r13  /* save r13 */
-        mfspr   r13,SPRN_SPRG_PACA      /* get paca address into r13 */
-        std     r3,PACA_EXSLB+EX_R3(r13)
-        mfspr   r3,SPRN_DAR
-        std     r9,PACA_EXSLB+EX_R9(r13)
-        mfcr    r9
-#ifdef __DISABLED__
-        cmpdi   r3,0
-        bge     slb_miss_user_iseries
-#endif
-        std     r10,PACA_EXSLB+EX_R10(r13)
-        std     r11,PACA_EXSLB+EX_R11(r13)
-        std     r12,PACA_EXSLB+EX_R12(r13)
-        mfspr   r10,SPRN_SPRG_SCRATCH0
-        std     r10,PACA_EXSLB+EX_R13(r13)
-        ld      r12,PACALPPACAPTR(r13)
-        ld      r12,LPPACASRR1(r12)
-        b       .slb_miss_realmode
-
-        STD_EXCEPTION_ISERIES(instruction_access, PACA_EXGEN)
-
-        .globl  instruction_access_slb_iSeries
-instruction_access_slb_iSeries:
-        mtspr   SPRN_SPRG_SCRATCH0,r13  /* save r13 */
-        mfspr   r13,SPRN_SPRG_PACA      /* get paca address into r13 */
-        std     r3,PACA_EXSLB+EX_R3(r13)
-        ld      r3,PACALPPACAPTR(r13)
-        ld      r3,LPPACASRR0(r3)       /* get SRR0 value */
-        std     r9,PACA_EXSLB+EX_R9(r13)
-        mfcr    r9
-#ifdef __DISABLED__
-        cmpdi   r3,0
-        bge     slb_miss_user_iseries
-#endif
-        std     r10,PACA_EXSLB+EX_R10(r13)
-        std     r11,PACA_EXSLB+EX_R11(r13)
-        std     r12,PACA_EXSLB+EX_R12(r13)
-        mfspr   r10,SPRN_SPRG_SCRATCH0
-        std     r10,PACA_EXSLB+EX_R13(r13)
-        ld      r12,PACALPPACAPTR(r13)
-        ld      r12,LPPACASRR1(r12)
-        b       .slb_miss_realmode
-
-#ifdef __DISABLED__
-slb_miss_user_iseries:
-        std     r10,PACA_EXGEN+EX_R10(r13)
-        std     r11,PACA_EXGEN+EX_R11(r13)
-        std     r12,PACA_EXGEN+EX_R12(r13)
-        mfspr   r10,SPRG_SCRATCH0
-        ld      r11,PACA_EXSLB+EX_R9(r13)
-        ld      r12,PACA_EXSLB+EX_R3(r13)
-        std     r10,PACA_EXGEN+EX_R13(r13)
-        std     r11,PACA_EXGEN+EX_R9(r13)
-        std     r12,PACA_EXGEN+EX_R3(r13)
-        EXCEPTION_PROLOG_ISERIES_1
-        b       slb_miss_user_common
-#endif
-
-        MASKABLE_EXCEPTION_ISERIES(hardware_interrupt)
-        STD_EXCEPTION_ISERIES(alignment, PACA_EXGEN)
-        STD_EXCEPTION_ISERIES(program_check, PACA_EXGEN)
-        STD_EXCEPTION_ISERIES(fp_unavailable, PACA_EXGEN)
-        MASKABLE_EXCEPTION_ISERIES(decrementer)
-        STD_EXCEPTION_ISERIES(trap_0a, PACA_EXGEN)
-        STD_EXCEPTION_ISERIES(trap_0b, PACA_EXGEN)
-
-        .globl  system_call_iSeries
-system_call_iSeries:
-        mr      r9,r13
-        mfspr   r13,SPRN_SPRG_PACA
-        EXCEPTION_PROLOG_ISERIES_1
-        b       system_call_common
-
-        STD_EXCEPTION_ISERIES(single_step, PACA_EXGEN)
-        STD_EXCEPTION_ISERIES(trap_0e, PACA_EXGEN)
-        STD_EXCEPTION_ISERIES(performance_monitor, PACA_EXGEN)
-
-decrementer_iSeries_masked:
-        /* We may not have a valid TOC pointer in here. */
-        li      r11,1
-        ld      r12,PACALPPACAPTR(r13)
-        stb     r11,LPPACADECRINT(r12)
-        li      r12,-1
-        clrldi  r12,r12,33      /* set DEC to 0x7fffffff */
-        mtspr   SPRN_DEC,r12
-        /* fall through */
-
-hardware_interrupt_iSeries_masked:
-        mtcrf   0x80,r9         /* Restore regs */
-        ld      r12,PACALPPACAPTR(r13)
-        ld      r11,LPPACASRR0(r12)
-        ld      r12,LPPACASRR1(r12)
-        mtspr   SPRN_SRR0,r11
-        mtspr   SPRN_SRR1,r12
-        ld      r9,PACA_EXGEN+EX_R9(r13)
-        ld      r10,PACA_EXGEN+EX_R10(r13)
-        ld      r11,PACA_EXGEN+EX_R11(r13)
-        ld      r12,PACA_EXGEN+EX_R12(r13)
-        ld      r13,PACA_EXGEN+EX_R13(r13)
-        rfid
-        b       .       /* prevent speculative execution */
-
-_INIT_STATIC(__start_initialization_iSeries)
-        /* Clear out the BSS */
-        LOAD_REG_ADDR(r11,__bss_stop)
-        LOAD_REG_ADDR(r8,__bss_start)
-        sub     r11,r11,r8              /* bss size                     */
-        addi    r11,r11,7               /* round up to an even double word */
-        rldicl. r11,r11,61,3            /* shift right by 3             */
-        beq     4f
-        addi    r8,r8,-8
-        li      r0,0
-        mtctr   r11                     /* zero this many doublewords   */
-3:      stdu    r0,8(r8)
-        bdnz    3b
-4:
-        LOAD_REG_ADDR(r1,init_thread_union)
-        addi    r1,r1,THREAD_SIZE
-        li      r0,0
-        stdu    r0,-STACK_FRAME_OVERHEAD(r1)
-
-        bl      .iSeries_early_setup
-        bl      .early_setup
-
-        /* relocation is on at this point */
-
-        b       .start_here_common
diff --git a/arch/powerpc/platforms/iseries/exception.h b/arch/powerpc/platforms/iseries/exception.h
deleted file mode 100644
index 50271b550a9..00000000000
--- a/arch/powerpc/platforms/iseries/exception.h
+++ /dev/null
@@ -1,58 +0,0 @@
-#ifndef _ASM_POWERPC_ISERIES_EXCEPTION_H
-#define _ASM_POWERPC_ISERIES_EXCEPTION_H
-/*
- * Extracted from head_64.S
- *
- *  PowerPC version
- *    Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
- *
- *  Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP
- *    Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu>
- *  Adapted for Power Macintosh by Paul Mackerras.
- *  Low-level exception handlers and MMU support
- *  rewritten by Paul Mackerras.
- *    Copyright (C) 1996 Paul Mackerras.
- *
- *  Adapted for 64bit PowerPC by Dave Engebretsen, Peter Bergner, and
- *    Mike Corrigan {engebret|bergner|mikejc}@us.ibm.com
- *
- *  This file contains the low-level support and setup for the
- *  PowerPC-64 platform, including trap and interrupt dispatch.
- *
- *  This program is free software; you can redistribute it and/or
- *  modify it under the terms of the GNU General Public License
- *  as published by the Free Software Foundation; either version
- *  2 of the License, or (at your option) any later version.
- */
-#include <asm/exception-64s.h>
-
-#define EXCEPTION_PROLOG_ISERIES_1                                      \
-        mfmsr   r10;                                                    \
-        ld      r12,PACALPPACAPTR(r13);                                 \
-        ld      r11,LPPACASRR0(r12);                                    \
-        ld      r12,LPPACASRR1(r12);                                    \
-        ori     r10,r10,MSR_RI;                                         \
-        mtmsrd  r10,1
-
-#define STD_EXCEPTION_ISERIES(label, area)                              \
-        .globl label##_iSeries;                                         \
-label##_iSeries:                                                        \
-        HMT_MEDIUM;                                                     \
-        mtspr   SPRN_SPRG_SCRATCH0,r13; /* save r13 */                  \
-        EXCEPTION_PROLOG_1(area, NOTEST, 0);                            \
-        EXCEPTION_PROLOG_ISERIES_1;                                     \
-        b       label##_common
-
-#define MASKABLE_EXCEPTION_ISERIES(label)                               \
-        .globl label##_iSeries;                                         \
-label##_iSeries:                                                        \
-        HMT_MEDIUM;                                                     \
-        mtspr   SPRN_SPRG_SCRATCH0,r13; /* save r13 */                  \
-        EXCEPTION_PROLOG_1(PACA_EXGEN, NOTEST, 0);                      \
-        lbz     r10,PACASOFTIRQEN(r13);                                 \
-        cmpwi   0,r10,0;                                                \
-        beq-    label##_iSeries_masked;                                 \
-        EXCEPTION_PROLOG_ISERIES_1;                                     \
-        b       label##_common;                                         \
-
-#endif  /* _ASM_POWERPC_ISERIES_EXCEPTION_H */
diff --git a/arch/powerpc/platforms/iseries/htab.c b/arch/powerpc/platforms/iseries/htab.c
deleted file mode 100644
index 3ae66ab9d5e..00000000000
--- a/arch/powerpc/platforms/iseries/htab.c
+++ /dev/null
@@ -1,257 +0,0 @@
-/*
- * iSeries hashtable management.
- *      Derived from pSeries_htab.c
- *
- * SMP scalability work:
- *    Copyright (C) 2001 Anton Blanchard <anton@au.ibm.com>, IBM
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-#include <asm/machdep.h>
-#include <asm/pgtable.h>
-#include <asm/mmu.h>
-#include <asm/mmu_context.h>
-#include <asm/abs_addr.h>
-#include <linux/spinlock.h>
-
-#include "call_hpt.h"
-
-static spinlock_t iSeries_hlocks[64] __cacheline_aligned_in_smp;
-
-/*
- * Very primitive algorithm for picking up a lock
- */
-static inline void iSeries_hlock(unsigned long slot)
-{
-        if (slot & 0x8)
-                slot = ~slot;
-        spin_lock(&iSeries_hlocks[(slot >> 4) & 0x3f]);
-}
-
-static inline void iSeries_hunlock(unsigned long slot)
-{
-        if (slot & 0x8)
-                slot = ~slot;
-        spin_unlock(&iSeries_hlocks[(slot >> 4) & 0x3f]);
-}
-
-static long iSeries_hpte_insert(unsigned long hpte_group, unsigned long va,
-                         unsigned long pa, unsigned long rflags,
-                         unsigned long vflags, int psize, int ssize)
-{
-        long slot;
-        struct hash_pte lhpte;
-        int secondary = 0;
-
-        BUG_ON(psize != MMU_PAGE_4K);
-
-        /*
-         * The hypervisor tries both primary and secondary.
-         * If we are being called to insert in the secondary,
-         * it means we have already tried both primary and secondary,
-         * so we return failure immediately.
-         */
-        if (vflags & HPTE_V_SECONDARY)
-                return -1;
-
-        iSeries_hlock(hpte_group);
-
-        slot = HvCallHpt_findValid(&lhpte, va >> HW_PAGE_SHIFT);
-        if (unlikely(lhpte.v & HPTE_V_VALID)) {
-                if (vflags & HPTE_V_BOLTED) {
-                        HvCallHpt_setSwBits(slot, 0x10, 0);
-                        HvCallHpt_setPp(slot, PP_RWXX);
-                        iSeries_hunlock(hpte_group);
-                        if (slot < 0)
-                                return 0x8 | (slot & 7);
-                        else
-                                return slot & 7;
-                }
-                BUG();
-        }
-
-        if (slot == -1) { /* No available entry found in either group */
-                iSeries_hunlock(hpte_group);
-                return -1;
-        }
-
-        if (slot < 0) {         /* MSB set means secondary group */
-                vflags |= HPTE_V_SECONDARY;
-                secondary = 1;
-                slot &= 0x7fffffffffffffff;
-        }
-
-
-        lhpte.v = hpte_encode_v(va, MMU_PAGE_4K, MMU_SEGSIZE_256M) |
-                vflags | HPTE_V_VALID;
-        lhpte.r = hpte_encode_r(phys_to_abs(pa), MMU_PAGE_4K) | rflags;
-
-        /* Now fill in the actual HPTE */
-        HvCallHpt_addValidate(slot, secondary, &lhpte);
-
-        iSeries_hunlock(hpte_group);
-
-        return (secondary << 3) | (slot & 7);
-}
-
-static unsigned long iSeries_hpte_getword0(unsigned long slot)
-{
-        struct hash_pte hpte;
-
-        HvCallHpt_get(&hpte, slot);
-        return hpte.v;
-}
-
-static long iSeries_hpte_remove(unsigned long hpte_group)
-{
-        unsigned long slot_offset;
-        int i;
-        unsigned long hpte_v;
-
-        /* Pick a random slot to start at */
-        slot_offset = mftb() & 0x7;
-
-        iSeries_hlock(hpte_group);
-
-        for (i = 0; i < HPTES_PER_GROUP; i++) {
-                hpte_v = iSeries_hpte_getword0(hpte_group + slot_offset);
-
-                if (! (hpte_v & HPTE_V_BOLTED)) {
-                        HvCallHpt_invalidateSetSwBitsGet(hpte_group +
-                                                         slot_offset, 0, 0);
-                        iSeries_hunlock(hpte_group);
-                        return i;
-                }
-
-                slot_offset++;
-                slot_offset &= 0x7;
-        }
-
-        iSeries_hunlock(hpte_group);
-
-        return -1;
-}
-
-/*
- * The HyperVisor expects the "flags" argument in this form:
- *      bits  0..59 : reserved
- *      bit      60 : N
- *      bits 61..63 : PP2,PP1,PP0
- */
-static long iSeries_hpte_updatepp(unsigned long slot, unsigned long newpp,
-                        unsigned long va, int psize, int ssize, int local)
-{
-        struct hash_pte hpte;
-        unsigned long want_v;
-
-        iSeries_hlock(slot);
-
-        HvCallHpt_get(&hpte, slot);
-        want_v = hpte_encode_v(va, MMU_PAGE_4K, MMU_SEGSIZE_256M);
-
-        if (HPTE_V_COMPARE(hpte.v, want_v) && (hpte.v & HPTE_V_VALID)) {
-                /*
-                 * Hypervisor expects bits as NPPP, which is
-                 * different from how they are mapped in our PP.
-                 */
-                HvCallHpt_setPp(slot, (newpp & 0x3) | ((newpp & 0x4) << 1));
-                iSeries_hunlock(slot);
-                return 0;
-        }
-        iSeries_hunlock(slot);
-
-        return -1;
-}
-
-/*
- * Functions used to find the PTE for a particular virtual address.
- * Only used during boot when bolting pages.
- *
- * Input : vpn      : virtual page number
- * Output: PTE index within the page table of the entry
- *         -1 on failure
- */
-static long iSeries_hpte_find(unsigned long vpn)
-{
-        struct hash_pte hpte;
-        long slot;
-
-        /*
-         * The HvCallHpt_findValid interface is as follows:
-         * 0xffffffffffffffff : No entry found.
-         * 0x00000000xxxxxxxx : Entry found in primary group, slot x
-         * 0x80000000xxxxxxxx : Entry found in secondary group, slot x
-         */
-        slot = HvCallHpt_findValid(&hpte, vpn);
-        if (hpte.v & HPTE_V_VALID) {
-                if (slot < 0) {
-                        slot &= 0x7fffffffffffffff;
-                        slot = -slot;
-                }
-        } else
-                slot = -1;
-        return slot;
-}
-
-/*
- * Update the page protection bits. Intended to be used to create
- * guard pages for kernel data structures on pages which are bolted
- * in the HPT. Assumes pages being operated on will not be stolen.
- * Does not work on large pages.
- *
- * No need to lock here because we should be the only user.
- */
-static void iSeries_hpte_updateboltedpp(unsigned long newpp, unsigned long ea,
-                                        int psize, int ssize)
-{
-        unsigned long vsid,va,vpn;
-        long slot;
-
-        BUG_ON(psize != MMU_PAGE_4K);
-
-        vsid = get_kernel_vsid(ea, MMU_SEGSIZE_256M);
-        va = (vsid << 28) | (ea & 0x0fffffff);
-        vpn = va >> HW_PAGE_SHIFT;
-        slot = iSeries_hpte_find(vpn);
-        if (slot == -1)
-                panic("updateboltedpp: Could not find page to bolt\n");
-        HvCallHpt_setPp(slot, newpp);
-}
-
-static void iSeries_hpte_invalidate(unsigned long slot, unsigned long va,
-                                    int psize, int ssize, int local)
-{
-        unsigned long hpte_v;
-        unsigned long avpn = va >> 23;
-        unsigned long flags;
-
-        local_irq_save(flags);
-
-        iSeries_hlock(slot);
-
-        hpte_v = iSeries_hpte_getword0(slot);
-
-        if ((HPTE_V_AVPN_VAL(hpte_v) == avpn) && (hpte_v & HPTE_V_VALID))
-                HvCallHpt_invalidateSetSwBitsGet(slot, 0, 0);
-
-        iSeries_hunlock(slot);
-
-        local_irq_restore(flags);
-}
-
-void __init hpte_init_iSeries(void)
-{
-        int i;
-
-        for (i = 0; i < ARRAY_SIZE(iSeries_hlocks); i++)
-                spin_lock_init(&iSeries_hlocks[i]);
-
-        ppc_md.hpte_invalidate  = iSeries_hpte_invalidate;
-        ppc_md.hpte_updatepp    = iSeries_hpte_updatepp;
-        ppc_md.hpte_updateboltedpp = iSeries_hpte_updateboltedpp;
-        ppc_md.hpte_insert      = iSeries_hpte_insert;
-        ppc_md.hpte_remove      = iSeries_hpte_remove;
-}
diff --git a/arch/powerpc/platforms/iseries/hvcall.S b/arch/powerpc/platforms/iseries/hvcall.S
deleted file mode 100644
index 07ae6ad5f49..00000000000
--- a/arch/powerpc/platforms/iseries/hvcall.S
+++ /dev/null
@@ -1,94 +0,0 @@
-/*
- * This file contains the code to perform calls to the
- * iSeries LPAR hypervisor
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#include <asm/ppc_asm.h>
-#include <asm/processor.h>
-#include <asm/ptrace.h>         /* XXX for STACK_FRAME_OVERHEAD */
-
-        .text
-
-/*
- * Hypervisor call
- *
- * Invoke the iSeries hypervisor via the System Call instruction
- * Parameters are passed to this routine in registers r3 - r10
- *
- * r3 contains the HV function to be called
- * r4-r10 contain the operands to the hypervisor function
- *
- */
-
-_GLOBAL(HvCall)
-_GLOBAL(HvCall0)
-_GLOBAL(HvCall1)
-_GLOBAL(HvCall2)
-_GLOBAL(HvCall3)
-_GLOBAL(HvCall4)
-_GLOBAL(HvCall5)
-_GLOBAL(HvCall6)
-_GLOBAL(HvCall7)
-
-
-        mfcr    r0
-        std     r0,-8(r1)
-        stdu    r1,-(STACK_FRAME_OVERHEAD+16)(r1)
-
-        /* r0 = 0xffffffffffffffff indicates a hypervisor call */
-
-        li      r0,-1
-
-        /* Invoke the hypervisor */
-
-        sc
-
-        ld      r1,0(r1)
-        ld      r0,-8(r1)
-        mtcrf   0xff,r0
-
-        /*  return to caller, return value in r3 */
-
-        blr
-
-_GLOBAL(HvCall0Ret16)
-_GLOBAL(HvCall1Ret16)
-_GLOBAL(HvCall2Ret16)
-_GLOBAL(HvCall3Ret16)
-_GLOBAL(HvCall4Ret16)
-_GLOBAL(HvCall5Ret16)
-_GLOBAL(HvCall6Ret16)
-_GLOBAL(HvCall7Ret16)
-
-        mfcr    r0
-        std     r0,-8(r1)
-        std     r31,-16(r1)
-        stdu    r1,-(STACK_FRAME_OVERHEAD+32)(r1)
-
-        mr      r31,r4
-        li      r0,-1
-        mr      r4,r5
-        mr      r5,r6
-        mr      r6,r7
-        mr      r7,r8
-        mr      r8,r9
-        mr      r9,r10
-
-        sc
-
-        std     r3,0(r31)
-        std     r4,8(r31)
-
-        mr      r3,r5
-
-        ld      r1,0(r1)
-        ld      r0,-8(r1)
-        mtcrf   0xff,r0
-        ld      r31,-16(r1)
-
-        blr
diff --git a/arch/powerpc/platforms/iseries/hvlog.c b/arch/powerpc/platforms/iseries/hvlog.c
deleted file mode 100644
index f476d71194f..00000000000
--- a/arch/powerpc/platforms/iseries/hvlog.c
+++ /dev/null
@@ -1,35 +0,0 @@
-/*
- * Copyright (C) 2001  Mike Corrigan IBM Corporation
- * 
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-
-#include <asm/page.h>
-#include <asm/abs_addr.h>
-#include <asm/iseries/hv_call.h>
-#include <asm/iseries/hv_call_sc.h>
-#include <asm/iseries/hv_types.h>
-
-
-void HvCall_writeLogBuffer(const void *buffer, u64 len)
-{
-        struct HvLpBufferList hv_buf;
-        u64 left_this_page;
-        u64 cur = virt_to_abs(buffer);
-
-        while (len) {
-                hv_buf.addr = cur;
-                left_this_page = ((cur & HW_PAGE_MASK) + HW_PAGE_SIZE) - cur;
-                if (left_this_page > len)
-                        left_this_page = len;
-                hv_buf.len = left_this_page;
-                len -= left_this_page;
-                HvCall2(HvCallBaseWriteLogBuffer,
-                                virt_to_abs(&hv_buf),
-                                left_this_page);
-                cur = (cur & HW_PAGE_MASK) + HW_PAGE_SIZE;
-        }
-}
diff --git a/arch/powerpc/platforms/iseries/hvlpconfig.c b/arch/powerpc/platforms/iseries/hvlpconfig.c
deleted file mode 100644
index f62a0c5fa67..00000000000
--- a/arch/powerpc/platforms/iseries/hvlpconfig.c
+++ /dev/null
@@ -1,39 +0,0 @@
-/*
- * Copyright (C) 2001  Kyle A. Lucke, IBM Corporation
- * 
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- * 
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- * 
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
- */
-
-#include <linux/export.h>
-#include <asm/iseries/hv_lp_config.h>
-#include "it_lp_naca.h"
-
-HvLpIndex HvLpConfig_getLpIndex_outline(void)
-{
-        return HvLpConfig_getLpIndex();
-}
-EXPORT_SYMBOL(HvLpConfig_getLpIndex_outline);
-
-HvLpIndex HvLpConfig_getLpIndex(void)
-{
-        return itLpNaca.xLpIndex;
-}
-EXPORT_SYMBOL(HvLpConfig_getLpIndex);
-
-HvLpIndex HvLpConfig_getPrimaryLpIndex(void)
-{
-        return itLpNaca.xPrimaryLpIndex;
-}
-EXPORT_SYMBOL_GPL(HvLpConfig_getPrimaryLpIndex);
diff --git a/arch/powerpc/platforms/iseries/iommu.c b/arch/powerpc/platforms/iseries/iommu.c
deleted file mode 100644
index 2f3d9110248..00000000000
--- a/arch/powerpc/platforms/iseries/iommu.c
+++ /dev/null
@@ -1,260 +0,0 @@
-/*
- * Copyright (C) 2001 Mike Corrigan & Dave Engebretsen, IBM Corporation
- *
- * Rewrite, cleanup:
- *
- * Copyright (C) 2004 Olof Johansson <olof@lixom.net>, IBM Corporation
- * Copyright (C) 2006 Olof Johansson <olof@lixom.net>
- *
- * Dynamic DMA mapping support, iSeries-specific parts.
- *
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
- */
-
-#include <linux/types.h>
-#include <linux/dma-mapping.h>
-#include <linux/list.h>
-#include <linux/pci.h>
-#include <linux/export.h>
-#include <linux/slab.h>
-
-#include <asm/iommu.h>
-#include <asm/vio.h>
-#include <asm/tce.h>
-#include <asm/machdep.h>
-#include <asm/abs_addr.h>
-#include <asm/prom.h>
-#include <asm/pci-bridge.h>
-#include <asm/iseries/hv_call_xm.h>
-#include <asm/iseries/hv_call_event.h>
-#include <asm/iseries/iommu.h>
-
-static int tce_build_iSeries(struct iommu_table *tbl, long index, long npages,
-                unsigned long uaddr, enum dma_data_direction direction,
-                struct dma_attrs *attrs)
-{
-        u64 rc;
-        u64 tce, rpn;
-
-        while (npages--) {
-                rpn = virt_to_abs(uaddr) >> TCE_SHIFT;
-                tce = (rpn & TCE_RPN_MASK) << TCE_RPN_SHIFT;
-
-                if (tbl->it_type == TCE_VB) {
-                        /* Virtual Bus */
-                        tce |= TCE_VALID|TCE_ALLIO;
-                        if (direction != DMA_TO_DEVICE)
-                                tce |= TCE_VB_WRITE;
-                } else {
-                        /* PCI Bus */
-                        tce |= TCE_PCI_READ; /* Read allowed */
-                        if (direction != DMA_TO_DEVICE)
-                                tce |= TCE_PCI_WRITE;
-                }
-
-                rc = HvCallXm_setTce((u64)tbl->it_index, (u64)index, tce);
-                if (rc)
-                        panic("PCI_DMA: HvCallXm_setTce failed, Rc: 0x%llx\n",
-                                        rc);
-                index++;
-                uaddr += TCE_PAGE_SIZE;
-        }
-        return 0;
-}
-
-static void tce_free_iSeries(struct iommu_table *tbl, long index, long npages)
-{
-        u64 rc;
-
-        while (npages--) {
-                rc = HvCallXm_setTce((u64)tbl->it_index, (u64)index, 0);
-                if (rc)
-                        panic("PCI_DMA: HvCallXm_setTce failed, Rc: 0x%llx\n",
-                                        rc);
-                index++;
-        }
-}
-
-/*
- * Structure passed to HvCallXm_getTceTableParms
- */
-struct iommu_table_cb {
-        unsigned long   itc_busno;      /* Bus number for this tce table */
-        unsigned long   itc_start;      /* Will be NULL for secondary */
-        unsigned long   itc_totalsize;  /* Size (in pages) of whole table */
-        unsigned long   itc_offset;     /* Index into real tce table of the
-                                           start of our section */
-        unsigned long   itc_size;       /* Size (in pages) of our section */
-        unsigned long   itc_index;      /* Index of this tce table */
-        unsigned short  itc_maxtables;  /* Max num of tables for partition */
-        unsigned char   itc_virtbus;    /* Flag to indicate virtual bus */
-        unsigned char   itc_slotno;     /* IOA Tce Slot Index */
-        unsigned char   itc_rsvd[4];
-};
-
-/*
- * Call Hv with the architected data structure to get TCE table info.
- * info. Put the returned data into the Linux representation of the
- * TCE table data.
- * The Hardware Tce table comes in three flavors.
- * 1. TCE table shared between Buses.
- * 2. TCE table per Bus.
- * 3. TCE Table per IOA.
- */
-void iommu_table_getparms_iSeries(unsigned long busno,
-                                  unsigned char slotno,
-                                  unsigned char virtbus,
-                                  struct iommu_table* tbl)
-{
-        struct iommu_table_cb *parms;
-
-        parms = kzalloc(sizeof(*parms), GFP_KERNEL);
-        if (parms == NULL)
-                panic("PCI_DMA: TCE Table Allocation failed.");
-
-        parms->itc_busno = busno;
-        parms->itc_slotno = slotno;
-        parms->itc_virtbus = virtbus;
-
-        HvCallXm_getTceTableParms(iseries_hv_addr(parms));
-
-        if (parms->itc_size == 0)
-                panic("PCI_DMA: parms->size is zero, parms is 0x%p", parms);
-
-        /* itc_size is in pages worth of table, it_size is in # of entries */
-        tbl->it_size = (parms->itc_size * TCE_PAGE_SIZE) / TCE_ENTRY_SIZE;
-        tbl->it_busno = parms->itc_busno;
-        tbl->it_offset = parms->itc_offset;
-        tbl->it_index = parms->itc_index;
-        tbl->it_blocksize = 1;
-        tbl->it_type = virtbus ? TCE_VB : TCE_PCI;
-
-        kfree(parms);
-}
-
-
-#ifdef CONFIG_PCI
-/*
- * This function compares the known tables to find an iommu_table
- * that has already been built for hardware TCEs.
- */
-static struct iommu_table *iommu_table_find(struct iommu_table * tbl)
-{
-        struct device_node *node;
-
-        for (node = NULL; (node = of_find_all_nodes(node)); ) {
-                struct pci_dn *pdn = PCI_DN(node);
-                struct iommu_table *it;
-
-                if (pdn == NULL)
-                        continue;
-                it = pdn->iommu_table;
-                if ((it != NULL) &&
-                    (it->it_type == TCE_PCI) &&
-                    (it->it_offset == tbl->it_offset) &&
-                    (it->it_index == tbl->it_index) &&
-                    (it->it_size == tbl->it_size)) {
-                        of_node_put(node);
-                        return it;
-                }
-        }
-        return NULL;
-}
-
-
-static void pci_dma_dev_setup_iseries(struct pci_dev *pdev)
-{
-        struct iommu_table *tbl;
-        struct device_node *dn = pci_device_to_OF_node(pdev);
-        struct pci_dn *pdn = PCI_DN(dn);
-        const u32 *lsn = of_get_property(dn, "linux,logical-slot-number", NULL);
-
-        BUG_ON(lsn == NULL);
-
-        tbl = kzalloc(sizeof(struct iommu_table), GFP_KERNEL);
-
-        iommu_table_getparms_iSeries(pdn->busno, *lsn, 0, tbl);
-
-        /* Look for existing tce table */
-        pdn->iommu_table = iommu_table_find(tbl);
-        if (pdn->iommu_table == NULL)
-                pdn->iommu_table = iommu_init_table(tbl, -1);
-        else
-                kfree(tbl);
-        set_iommu_table_base(&pdev->dev, pdn->iommu_table);
-}
-#else
-#define pci_dma_dev_setup_iseries       NULL
-#endif
-
-static struct iommu_table veth_iommu_table;
-static struct iommu_table vio_iommu_table;
-
-void *iseries_hv_alloc(size_t size, dma_addr_t *dma_handle, gfp_t flag)
-{
-        return iommu_alloc_coherent(NULL, &vio_iommu_table, size, dma_handle,
-                                DMA_BIT_MASK(32), flag, -1);
-}
-EXPORT_SYMBOL_GPL(iseries_hv_alloc);
-
-void iseries_hv_free(size_t size, void *vaddr, dma_addr_t dma_handle)
-{
-        iommu_free_coherent(&vio_iommu_table, size, vaddr, dma_handle);
-}
-EXPORT_SYMBOL_GPL(iseries_hv_free);
-
-dma_addr_t iseries_hv_map(void *vaddr, size_t size,
-                        enum dma_data_direction direction)
-{
-        return iommu_map_page(NULL, &vio_iommu_table, virt_to_page(vaddr),
-                              (unsigned long)vaddr % PAGE_SIZE, size,
-                              DMA_BIT_MASK(32), direction, NULL);
-}
-
-void iseries_hv_unmap(dma_addr_t dma_handle, size_t size,
-                        enum dma_data_direction direction)
-{
-        iommu_unmap_page(&vio_iommu_table, dma_handle, size, direction, NULL);
-}
-
-void __init iommu_vio_init(void)
-{
-        iommu_table_getparms_iSeries(255, 0, 0xff, &veth_iommu_table);
-        veth_iommu_table.it_size /= 2;
-        vio_iommu_table = veth_iommu_table;
-        vio_iommu_table.it_offset += veth_iommu_table.it_size;
-
-        if (!iommu_init_table(&veth_iommu_table, -1))
-                printk("Virtual Bus VETH TCE table failed.\n");
-        if (!iommu_init_table(&vio_iommu_table, -1))
-                printk("Virtual Bus VIO TCE table failed.\n");
-}
-
-struct iommu_table *vio_build_iommu_table_iseries(struct vio_dev *dev)
-{
-        if (strcmp(dev->type, "network") == 0)
-                return &veth_iommu_table;
-        return &vio_iommu_table;
-}
-
-void iommu_init_early_iSeries(void)
-{
-        ppc_md.tce_build = tce_build_iSeries;
-        ppc_md.tce_free  = tce_free_iSeries;
-
-        ppc_md.pci_dma_dev_setup = pci_dma_dev_setup_iseries;
-        set_pci_dma_ops(&dma_iommu_ops);
-}
diff --git a/arch/powerpc/platforms/iseries/ipl_parms.h b/arch/powerpc/platforms/iseries/ipl_parms.h
deleted file mode 100644
index 83e4ca42fc5..00000000000
--- a/arch/powerpc/platforms/iseries/ipl_parms.h
+++ /dev/null
@@ -1,68 +0,0 @@
-/*
- * Copyright (C) 2001  Mike Corrigan IBM Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
- */
-#ifndef _ISERIES_IPL_PARMS_H
-#define _ISERIES_IPL_PARMS_H
-
-/*
- *      This struct maps the IPL Parameters DMA'd from the SP.
- *
- * Warning:
- *      This data must map in exactly 64 bytes and match the architecture for
- *      the IPL parms
- */
-
-#include <asm/types.h>
-
-struct ItIplParmsReal {
-        u8      xFormat;                // Defines format of IplParms   x00-x00
-        u8      xRsvd01:6;              // Reserved                     x01-x01
-        u8      xAlternateSearch:1;     // Alternate search indicator   ...
-        u8      xUaSupplied:1;          // UA Supplied on programmed IPL...
-        u8      xLsUaFormat;            // Format byte for UA           x02-x02
-        u8      xRsvd02;                // Reserved                     x03-x03
-        u32     xLsUa;                  // LS UA                        x04-x07
-        u32     xUnusedLsLid;           // First OS LID to load         x08-x0B
-        u16     xLsBusNumber;           // LS Bus Number                x0C-x0D
-        u8      xLsCardAdr;             // LS Card Address              x0E-x0E
-        u8      xLsBoardAdr;            // LS Board Address             x0F-x0F
-        u32     xRsvd03;                // Reserved                     x10-x13
-        u8      xSpcnPresent:1;         // SPCN present                 x14-x14
-        u8      xCpmPresent:1;          // CPM present                  ...
-        u8      xRsvd04:6;              // Reserved                     ...
-        u8      xRsvd05:4;              // Reserved                     x15-x15
-        u8      xKeyLock:4;             // Keylock setting              ...
-        u8      xRsvd06:6;              // Reserved                     x16-x16
-        u8      xIplMode:2;             // Ipl mode (A|B|C|D)           ...
-        u8      xHwIplType;             // Fast v slow v slow EC HW IPL x17-x17
-        u16     xCpmEnabledIpl:1;       // CPM in effect when IPL initiatedx18-x19
-        u16     xPowerOnResetIpl:1;     // Indicate POR condition       ...
-        u16     xMainStorePreserved:1;  // Main Storage is preserved    ...
-        u16     xRsvd07:13;             // Reserved                     ...
-        u16     xIplSource:16;          // Ipl source                   x1A-x1B
-        u8      xIplReason:8;           // Reason for this IPL          x1C-x1C
-        u8      xRsvd08;                // Reserved                     x1D-x1D
-        u16     xRsvd09;                // Reserved                     x1E-x1F
-        u16     xSysBoxType;            // System Box Type              x20-x21
-        u16     xSysProcType;           // System Processor Type        x22-x23
-        u32     xRsvd10;                // Reserved                     x24-x27
-        u64     xRsvd11;                // Reserved                     x28-x2F
-        u64     xRsvd12;                // Reserved                     x30-x37
-        u64     xRsvd13;                // Reserved                     x38-x3F
-};
-
-#endif /* _ISERIES_IPL_PARMS_H */
diff --git a/arch/powerpc/platforms/iseries/irq.c b/arch/powerpc/platforms/iseries/irq.c
deleted file mode 100644
index 05ce5164caf..00000000000
--- a/arch/powerpc/platforms/iseries/irq.c
+++ /dev/null
@@ -1,399 +0,0 @@
-/*
- * This module supports the iSeries PCI bus interrupt handling
- * Copyright (C) 20yy  <Robert L Holtorf> <IBM Corp>
- * Copyright (C) 2004-2005 IBM Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the:
- * Free Software Foundation, Inc.,
- * 59 Temple Place, Suite 330,
- * Boston, MA  02111-1307  USA
- *
- * Change Activity:
- *   Created, December 13, 2000 by Wayne Holm
- * End Change Activity
- */
-#include <linux/pci.h>
-#include <linux/init.h>
-#include <linux/threads.h>
-#include <linux/smp.h>
-#include <linux/param.h>
-#include <linux/string.h>
-#include <linux/bootmem.h>
-#include <linux/irq.h>
-#include <linux/spinlock.h>
-
-#include <asm/paca.h>
-#include <asm/iseries/hv_types.h>
-#include <asm/iseries/hv_lp_event.h>
-#include <asm/iseries/hv_call_xm.h>
-#include <asm/iseries/it_lp_queue.h>
-
-#include "irq.h"
-#include "pci.h"
-#include "call_pci.h"
-
-#ifdef CONFIG_PCI
-
-enum pci_event_type {
-        pe_bus_created          = 0,    /* PHB has been created */
-        pe_bus_error            = 1,    /* PHB has failed */
-        pe_bus_failed           = 2,    /* Msg to Secondary, Primary failed bus */
-        pe_node_failed          = 4,    /* Multi-adapter bridge has failed */
-        pe_node_recovered       = 5,    /* Multi-adapter bridge has recovered */
-        pe_bus_recovered        = 12,   /* PHB has been recovered */
-        pe_unquiese_bus         = 18,   /* Secondary bus unqiescing */
-        pe_bridge_error         = 21,   /* Bridge Error */
-        pe_slot_interrupt       = 22    /* Slot interrupt */
-};
-
-struct pci_event {
-        struct HvLpEvent event;
-        union {
-                u64 __align;            /* Align on an 8-byte boundary */
-                struct {
-                        u32             fisr;
-                        HvBusNumber     bus_number;
-                        HvSubBusNumber  sub_bus_number;
-                        HvAgentId       dev_id;
-                } slot;
-                struct {
-                        HvBusNumber     bus_number;
-                        HvSubBusNumber  sub_bus_number;
-                } bus;
-                struct {
-                        HvBusNumber     bus_number;
-                        HvSubBusNumber  sub_bus_number;
-                        HvAgentId       dev_id;
-                } node;
-        } data;
-};
-
-static DEFINE_SPINLOCK(pending_irqs_lock);
-static int num_pending_irqs;
-static int pending_irqs[NR_IRQS];
-
-static void int_received(struct pci_event *event)
-{
-        int irq;
-
-        switch (event->event.xSubtype) {
-        case pe_slot_interrupt:
-                irq = event->event.xCorrelationToken;
-                if (irq < NR_IRQS) {
-                        spin_lock(&pending_irqs_lock);
-                        pending_irqs[irq]++;
-                        num_pending_irqs++;
-                        spin_unlock(&pending_irqs_lock);
-                } else {
-                        printk(KERN_WARNING "int_received: bad irq number %d\n",
-                                        irq);
-                        HvCallPci_eoi(event->data.slot.bus_number,
-                                        event->data.slot.sub_bus_number,
-                                        event->data.slot.dev_id);
-                }
-                break;
-                /* Ignore error recovery events for now */
-        case pe_bus_created:
-                printk(KERN_INFO "int_received: system bus %d created\n",
-                        event->data.bus.bus_number);
-                break;
-        case pe_bus_error:
-        case pe_bus_failed:
-                printk(KERN_INFO "int_received: system bus %d failed\n",
-                        event->data.bus.bus_number);
-                break;
-        case pe_bus_recovered:
-        case pe_unquiese_bus:
-                printk(KERN_INFO "int_received: system bus %d recovered\n",
-                        event->data.bus.bus_number);
-                break;
-        case pe_node_failed:
-        case pe_bridge_error:
-                printk(KERN_INFO
-                        "int_received: multi-adapter bridge %d/%d/%d failed\n",
-                        event->data.node.bus_number,
-                        event->data.node.sub_bus_number,
-                        event->data.node.dev_id);
-                break;
-        case pe_node_recovered:
-                printk(KERN_INFO
-                        "int_received: multi-adapter bridge %d/%d/%d recovered\n",
-                        event->data.node.bus_number,
-                        event->data.node.sub_bus_number,
-                        event->data.node.dev_id);
-                break;
-        default:
-                printk(KERN_ERR
-                        "int_received: unrecognized event subtype 0x%x\n",
-                        event->event.xSubtype);
-                break;
-        }
-}
-
-static void pci_event_handler(struct HvLpEvent *event)
-{
-        if (event && (event->xType == HvLpEvent_Type_PciIo)) {
-                if (hvlpevent_is_int(event))
-                        int_received((struct pci_event *)event);
-                else
-                        printk(KERN_ERR
-                                "pci_event_handler: unexpected ack received\n");
-        } else if (event)
-                printk(KERN_ERR
-                        "pci_event_handler: Unrecognized PCI event type 0x%x\n",
-                        (int)event->xType);
-        else
-                printk(KERN_ERR "pci_event_handler: NULL event received\n");
-}
-
-#define REAL_IRQ_TO_SUBBUS(irq) (((irq) >> 14) & 0xff)
-#define REAL_IRQ_TO_BUS(irq)    ((((irq) >> 6) & 0xff) + 1)
-#define REAL_IRQ_TO_IDSEL(irq)  ((((irq) >> 3) & 7) + 1)
-#define REAL_IRQ_TO_FUNC(irq)   ((irq) & 7)
-
-/*
- * This will be called by device drivers (via enable_IRQ)
- * to enable INTA in the bridge interrupt status register.
- */
-static void iseries_enable_IRQ(struct irq_data *d)
-{
-        u32 bus, dev_id, function, mask;
-        const u32 sub_bus = 0;
-        unsigned int rirq = (unsigned int)irqd_to_hwirq(d);
-
-        /* The IRQ has already been locked by the caller */
-        bus = REAL_IRQ_TO_BUS(rirq);
-        function = REAL_IRQ_TO_FUNC(rirq);
-        dev_id = (REAL_IRQ_TO_IDSEL(rirq) << 4) + function;
-
-        /* Unmask secondary INTA */
-        mask = 0x80000000;
-        HvCallPci_unmaskInterrupts(bus, sub_bus, dev_id, mask);
-}
-
-/* This is called by iseries_activate_IRQs */
-static unsigned int iseries_startup_IRQ(struct irq_data *d)
-{
-        u32 bus, dev_id, function, mask;
-        const u32 sub_bus = 0;
-        unsigned int rirq = (unsigned int)irqd_to_hwirq(d);
-
-        bus = REAL_IRQ_TO_BUS(rirq);
-        function = REAL_IRQ_TO_FUNC(rirq);
-        dev_id = (REAL_IRQ_TO_IDSEL(rirq) << 4) + function;
-
-        /* Link the IRQ number to the bridge */
-        HvCallXm_connectBusUnit(bus, sub_bus, dev_id, d->irq);
-
-        /* Unmask bridge interrupts in the FISR */
-        mask = 0x01010000 << function;
-        HvCallPci_unmaskFisr(bus, sub_bus, dev_id, mask);
-        iseries_enable_IRQ(d);
-        return 0;
-}
-
-/*
- * This is called out of iSeries_fixup to activate interrupt
- * generation for usable slots
- */
-void __init iSeries_activate_IRQs()
-{
-        int irq;
-        unsigned long flags;
-
-        for_each_irq (irq) {
-                struct irq_desc *desc = irq_to_desc(irq);
-                struct irq_chip *chip;
-
-                if (!desc)
-                        continue;
-
-                chip = irq_desc_get_chip(desc);
-                if (chip && chip->irq_startup) {
-                        raw_spin_lock_irqsave(&desc->lock, flags);
-                        chip->irq_startup(&desc->irq_data);
-                        raw_spin_unlock_irqrestore(&desc->lock, flags);
-                }
-        }
-}
-
-/*  this is not called anywhere currently */
-static void iseries_shutdown_IRQ(struct irq_data *d)
-{
-        u32 bus, dev_id, function, mask;
-        const u32 sub_bus = 0;
-        unsigned int rirq = (unsigned int)irqd_to_hwirq(d);
-
-        /* irq should be locked by the caller */
-        bus = REAL_IRQ_TO_BUS(rirq);
-        function = REAL_IRQ_TO_FUNC(rirq);
-        dev_id = (REAL_IRQ_TO_IDSEL(rirq) << 4) + function;
-
-        /* Invalidate the IRQ number in the bridge */
-        HvCallXm_connectBusUnit(bus, sub_bus, dev_id, 0);
-
-        /* Mask bridge interrupts in the FISR */
-        mask = 0x01010000 << function;
-        HvCallPci_maskFisr(bus, sub_bus, dev_id, mask);
-}
-
-/*
- * This will be called by device drivers (via disable_IRQ)
- * to disable INTA in the bridge interrupt status register.
- */
-static void iseries_disable_IRQ(struct irq_data *d)
-{
-        u32 bus, dev_id, function, mask;
-        const u32 sub_bus = 0;
-        unsigned int rirq = (unsigned int)irqd_to_hwirq(d);
-
-        /* The IRQ has already been locked by the caller */
-        bus = REAL_IRQ_TO_BUS(rirq);
-        function = REAL_IRQ_TO_FUNC(rirq);
-        dev_id = (REAL_IRQ_TO_IDSEL(rirq) << 4) + function;
-
-        /* Mask secondary INTA   */
-        mask = 0x80000000;
-        HvCallPci_maskInterrupts(bus, sub_bus, dev_id, mask);
-}
-
-static void iseries_end_IRQ(struct irq_data *d)
-{
-        unsigned int rirq = (unsigned int)irqd_to_hwirq(d);
-
-        HvCallPci_eoi(REAL_IRQ_TO_BUS(rirq), REAL_IRQ_TO_SUBBUS(rirq),
-                (REAL_IRQ_TO_IDSEL(rirq) << 4) + REAL_IRQ_TO_FUNC(rirq));
-}
-
-static struct irq_chip iseries_pic = {
-        .name           = "iSeries",
-        .irq_startup    = iseries_startup_IRQ,
-        .irq_shutdown   = iseries_shutdown_IRQ,
-        .irq_unmask     = iseries_enable_IRQ,
-        .irq_mask       = iseries_disable_IRQ,
-        .irq_eoi        = iseries_end_IRQ
-};
-
-/*
- * This is called out of iSeries_scan_slot to allocate an IRQ for an EADS slot
- * It calculates the irq value for the slot.
- * Note that sub_bus is always 0 (at the moment at least).
- */
-int __init iSeries_allocate_IRQ(HvBusNumber bus,
-                HvSubBusNumber sub_bus, u32 bsubbus)
-{
-        unsigned int realirq;
-        u8 idsel = ISERIES_GET_DEVICE_FROM_SUBBUS(bsubbus);
-        u8 function = ISERIES_GET_FUNCTION_FROM_SUBBUS(bsubbus);
-
-        realirq = (((((sub_bus << 8) + (bus - 1)) << 3) + (idsel - 1)) << 3)
-                + function;
-
-        return irq_create_mapping(NULL, realirq);
-}
-
-#endif /* CONFIG_PCI */
-
-/*
- * Get the next pending IRQ.
- */
-unsigned int iSeries_get_irq(void)
-{
-        int irq = NO_IRQ_IGNORE;
-
-#ifdef CONFIG_SMP
-        if (get_lppaca()->int_dword.fields.ipi_cnt) {
-                get_lppaca()->int_dword.fields.ipi_cnt = 0;
-                smp_ipi_demux();
-        }
-#endif /* CONFIG_SMP */
-        if (hvlpevent_is_pending())
-                process_hvlpevents();
-
-#ifdef CONFIG_PCI
-        if (num_pending_irqs) {
-                spin_lock(&pending_irqs_lock);
-                for (irq = 0; irq < NR_IRQS; irq++) {
-                        if (pending_irqs[irq]) {
-                                pending_irqs[irq]--;
-                                num_pending_irqs--;
-                                break;
-                        }
-                }
-                spin_unlock(&pending_irqs_lock);
-                if (irq >= NR_IRQS)
-                        irq = NO_IRQ_IGNORE;
-        }
-#endif
-
-        return irq;
-}
-
-#ifdef CONFIG_PCI
-
-static int iseries_irq_host_map(struct irq_domain *h, unsigned int virq,
-                                irq_hw_number_t hw)
-{
-        irq_set_chip_and_handler(virq, &iseries_pic, handle_fasteoi_irq);
-
-        return 0;
-}
-
-static int iseries_irq_host_match(struct irq_domain *h, struct device_node *np)
-{
-        /* Match all */
-        return 1;
-}
-
-static const struct irq_domain_ops iseries_irq_domain_ops = {
-        .map = iseries_irq_host_map,
-        .match = iseries_irq_host_match,
-};
-
-/*
- * This is called by init_IRQ.  set in ppc_md.init_IRQ by iSeries_setup.c
- * It must be called before the bus walk.
- */
-void __init iSeries_init_IRQ(void)
-{
-        /* Register PCI event handler and open an event path */
-        struct irq_domain *host;
-        int ret;
-
-        /*
-         * The Hypervisor only allows us up to 256 interrupt
-         * sources (the irq number is passed in a u8).
-         */
-        irq_set_virq_count(256);
-
-        /* Create irq host. No need for a revmap since HV will give us
-         * back our virtual irq number
-         */
-        host = irq_domain_add_nomap(NULL, &iseries_irq_domain_ops, NULL);
-        BUG_ON(host == NULL);
-        irq_set_default_host(host);
-
-        ret = HvLpEvent_registerHandler(HvLpEvent_Type_PciIo,
-                        &pci_event_handler);
-        if (ret == 0) {
-                ret = HvLpEvent_openPath(HvLpEvent_Type_PciIo, 0);
-                if (ret != 0)
-                        printk(KERN_ERR "iseries_init_IRQ: open event path "
-                                        "failed with rc 0x%x\n", ret);
-        } else
-                printk(KERN_ERR "iseries_init_IRQ: register handler "
-                                "failed with rc 0x%x\n", ret);
-}
-
-#endif  /* CONFIG_PCI */
diff --git a/arch/powerpc/platforms/iseries/irq.h b/arch/powerpc/platforms/iseries/irq.h
deleted file mode 100644
index a1c23607403..00000000000
--- a/arch/powerpc/platforms/iseries/irq.h
+++ /dev/null
@@ -1,13 +0,0 @@
-#ifndef _ISERIES_IRQ_H
-#define _ISERIES_IRQ_H
-
-#ifdef CONFIG_PCI
-extern void iSeries_init_IRQ(void);
-extern int  iSeries_allocate_IRQ(HvBusNumber, HvSubBusNumber, u32);
-extern void iSeries_activate_IRQs(void);
-#else
-#define iSeries_init_IRQ        NULL
-#endif
-extern unsigned int iSeries_get_irq(void);
-
-#endif /* _ISERIES_IRQ_H */
diff --git a/arch/powerpc/platforms/iseries/it_exp_vpd_panel.h b/arch/powerpc/platforms/iseries/it_exp_vpd_panel.h
deleted file mode 100644
index 6de9097b7f5..00000000000
--- a/arch/powerpc/platforms/iseries/it_exp_vpd_panel.h
+++ /dev/null
@@ -1,51 +0,0 @@
-/*
- * Copyright (C) 2002  Dave Boutcher IBM Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
- */
-#ifndef _PLATFORMS_ISERIES_IT_EXT_VPD_PANEL_H
-#define _PLATFORMS_ISERIES_IT_EXT_VPD_PANEL_H
-
-/*
- *      This struct maps the panel information
- *
- * Warning:
- *      This data must match the architecture for the panel information
- */
-
-#include <asm/types.h>
-
-struct ItExtVpdPanel {
-        /* Definition of the Extended Vpd On Panel Data Area */
-        char    systemSerial[8];
-        char    mfgID[4];
-        char    reserved1[24];
-        char    machineType[4];
-        char    systemID[6];
-        char    somUniqueCnt[4];
-        char    serialNumberCount;
-        char    reserved2[7];
-        u16     bbu3;
-        u16     bbu2;
-        u16     bbu1;
-        char    xLocationLabel[8];
-        u8      xRsvd1[6];
-        u16     xFrameId;
-        u8      xRsvd2[48];
-};
-
-extern struct ItExtVpdPanel     xItExtVpdPanel;
-
-#endif /* _PLATFORMS_ISERIES_IT_EXT_VPD_PANEL_H */
diff --git a/arch/powerpc/platforms/iseries/it_lp_naca.h b/arch/powerpc/platforms/iseries/it_lp_naca.h
deleted file mode 100644
index cf6dcf6ef07..00000000000
--- a/arch/powerpc/platforms/iseries/it_lp_naca.h
+++ /dev/null
@@ -1,80 +0,0 @@
-/*
- * Copyright (C) 2001  Mike Corrigan IBM Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
- */
-#ifndef _PLATFORMS_ISERIES_IT_LP_NACA_H
-#define _PLATFORMS_ISERIES_IT_LP_NACA_H
-
-#include <linux/types.h>
-
-/*
- *      This control block contains the data that is shared between the
- *      hypervisor (PLIC) and the OS.
- */
-
-struct ItLpNaca {
-// CACHE_LINE_1 0x0000 - 0x007F Contains read-only data
-        u32     xDesc;                  // Eye catcher                  x00-x03
-        u16     xSize;                  // Size of this class           x04-x05
-        u16     xIntHdlrOffset;         // Offset to IntHdlr array      x06-x07
-        u8      xMaxIntHdlrEntries;     // Number of entries in array   x08-x08
-        u8      xPrimaryLpIndex;        // LP Index of Primary          x09-x09
-        u8      xServiceLpIndex;        // LP Ind of Service Focal Pointx0A-x0A
-        u8      xLpIndex;               // LP Index                     x0B-x0B
-        u16     xMaxLpQueues;           // Number of allocated queues   x0C-x0D
-        u16     xLpQueueOffset;         // Offset to start of LP queues x0E-x0F
-        u8      xPirEnvironMode;        // Piranha or hardware          x10-x10
-        u8      xPirConsoleMode;        // Piranha console indicator    x11-x11
-        u8      xPirDasdMode;           // Piranha dasd indicator       x12-x12
-        u8      xRsvd1_0[5];            // Reserved for Piranha related x13-x17
-        u8      flags;                  // flags, see below             x18-x1F
-        u8      xSpVpdFormat;           // VPD areas are in CSP format  ...
-        u8      xIntProcRatio;          // Ratio of int procs to procs  ...
-        u8      xRsvd1_2[5];            // Reserved                     ...
-        u16     xRsvd1_3;               // Reserved                     x20-x21
-        u16     xPlicVrmIndex;          // VRM index of PLIC            x22-x23
-        u16     xMinSupportedSlicVrmInd;// Min supported OS VRM index   x24-x25
-        u16     xMinCompatableSlicVrmInd;// Min compatible OS VRM index x26-x27
-        u64     xLoadAreaAddr;          // ER address of load area      x28-x2F
-        u32     xLoadAreaChunks;        // Chunks for the load area     x30-x33
-        u32     xPaseSysCallCRMask;     // Mask used to test CR before  x34-x37
-                                        // doing an ASR switch on PASE
-                                        // system call.
-        u64     xSlicSegmentTablePtr;   // Pointer to Slic seg table.   x38-x3f
-        u8      xRsvd1_4[64];           //                              x40-x7F
-
-// CACHE_LINE_2 0x0080 - 0x00FF Contains local read-write data
-        u8      xRsvd2_0[128];          // Reserved                     x00-x7F
-
-// CACHE_LINE_3-6 0x0100 - 0x02FF Contains LP Queue indicators
-// NB: Padding required to keep xInterruptHdlr at x300 which is required
-// for v4r4 PLIC.
-        u8      xOldLpQueue[128];       // LP Queue needed for v4r4     100-17F
-        u8      xRsvd3_0[384];          // Reserved                     180-2FF
-
-// CACHE_LINE_7-8 0x0300 - 0x03FF Contains the address of the OS interrupt
-//  handlers
-        u64     xInterruptHdlr[32];     // Interrupt handlers           300-x3FF
-};
-
-extern struct ItLpNaca          itLpNaca;
-
-#define ITLPNACA_LPAR           0x80    /* Is LPAR installed on the system */
-#define ITLPNACA_PARTITIONED    0x40    /* Is the system partitioned */
-#define ITLPNACA_HWSYNCEDTBS    0x20    /* Hardware synced TBs */
-#define ITLPNACA_HMTINT         0x10    /* Utilize MHT for interrupts */
-
-#endif /* _PLATFORMS_ISERIES_IT_LP_NACA_H */
diff --git a/arch/powerpc/platforms/iseries/ksyms.c b/arch/powerpc/platforms/iseries/ksyms.c
deleted file mode 100644
index 997e234fb8b..00000000000
--- a/arch/powerpc/platforms/iseries/ksyms.c
+++ /dev/null
@@ -1,21 +0,0 @@
-/*
- * (C) 2001-2005 PPC 64 Team, IBM Corp
- *
- *      This program is free software; you can redistribute it and/or
- *      modify it under the terms of the GNU General Public License
- *      as published by the Free Software Foundation; either version
- *      2 of the License, or (at your option) any later version.
- */
-#include <linux/export.h>
-
-#include <asm/hw_irq.h>
-#include <asm/iseries/hv_call_sc.h>
-
-EXPORT_SYMBOL(HvCall0);
-EXPORT_SYMBOL(HvCall1);
-EXPORT_SYMBOL(HvCall2);
-EXPORT_SYMBOL(HvCall3);
-EXPORT_SYMBOL(HvCall4);
-EXPORT_SYMBOL(HvCall5);
-EXPORT_SYMBOL(HvCall6);
-EXPORT_SYMBOL(HvCall7);
diff --git a/arch/powerpc/platforms/iseries/lpardata.c b/arch/powerpc/platforms/iseries/lpardata.c
deleted file mode 100644
index 00e0ec813a1..00000000000
--- a/arch/powerpc/platforms/iseries/lpardata.c
+++ /dev/null
@@ -1,318 +0,0 @@
-/*
- * Copyright 2001 Mike Corrigan, IBM Corp
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-#include <linux/types.h>
-#include <linux/threads.h>
-#include <linux/bitops.h>
-#include <asm/processor.h>
-#include <asm/ptrace.h>
-#include <asm/abs_addr.h>
-#include <asm/lppaca.h>
-#include <asm/paca.h>
-#include <asm/iseries/lpar_map.h>
-#include <asm/iseries/it_lp_queue.h>
-#include <asm/iseries/alpaca.h>
-
-#include "naca.h"
-#include "vpd_areas.h"
-#include "spcomm_area.h"
-#include "ipl_parms.h"
-#include "processor_vpd.h"
-#include "release_data.h"
-#include "it_exp_vpd_panel.h"
-#include "it_lp_naca.h"
-
-/* The HvReleaseData is the root of the information shared between
- * the hypervisor and Linux.
- */
-const struct HvReleaseData hvReleaseData = {
-        .xDesc = 0xc8a5d9c4,    /* "HvRD" ebcdic */
-        .xSize = sizeof(struct HvReleaseData),
-        .xVpdAreasPtrOffset = offsetof(struct naca_struct, xItVpdAreas),
-        .xSlicNacaAddr = &naca,         /* 64-bit Naca address */
-        .xMsNucDataOffset = LPARMAP_PHYS,
-        .xFlags = HVREL_TAGSINACTIVE    /* tags inactive       */
-                                        /* 64 bit              */
-                                        /* shared processors   */
-                                        /* HMT allowed         */
-                  | 6,                  /* TEMP: This allows non-GA driver */
-        .xVrmIndex = 4,                 /* We are v5r2m0               */
-        .xMinSupportedPlicVrmIndex = 3,         /* v5r1m0 */
-        .xMinCompatablePlicVrmIndex = 3,        /* v5r1m0 */
-        .xVrmName = { 0xd3, 0x89, 0x95, 0xa4,   /* "Linux 2.4.64" ebcdic */
-                0xa7, 0x40, 0xf2, 0x4b,
-                0xf4, 0x4b, 0xf6, 0xf4 },
-};
-
-/*
- * The NACA.  The first dword of the naca is required by the iSeries
- * hypervisor to point to itVpdAreas.  The hypervisor finds the NACA
- * through the pointer in hvReleaseData.
- */
-struct naca_struct naca = {
-        .xItVpdAreas = &itVpdAreas,
-        .xRamDisk = 0,
-        .xRamDiskSize = 0,
-};
-
-struct ItLpRegSave {
-        u32     xDesc;          // Eye catcher  "LpRS" ebcdic   000-003
-        u16     xSize;          // Size of this class           004-005
-        u8      xInUse;         // Area is live                 006-007
-        u8      xRsvd1[9];      // Reserved                     007-00F
-
-        u8      xFixedRegSave[352]; // Fixed Register Save Area 010-16F
-        u32     xCTRL;          // Control Register             170-173
-        u32     xDEC;           // Decrementer                  174-177
-        u32     xFPSCR;         // FP Status and Control Reg    178-17B
-        u32     xPVR;           // Processor Version Number     17C-17F
-
-        u64     xMMCR0;         // Monitor Mode Control Reg 0   180-187
-        u32     xPMC1;          // Perf Monitor Counter 1       188-18B
-        u32     xPMC2;          // Perf Monitor Counter 2       18C-18F
-        u32     xPMC3;          // Perf Monitor Counter 3       190-193
-        u32     xPMC4;          // Perf Monitor Counter 4       194-197
-        u32     xPIR;           // Processor ID Reg             198-19B
-
-        u32     xMMCR1;         // Monitor Mode Control Reg 1   19C-19F
-        u32     xMMCRA;         // Monitor Mode Control Reg A   1A0-1A3
-        u32     xPMC5;          // Perf Monitor Counter 5       1A4-1A7
-        u32     xPMC6;          // Perf Monitor Counter 6       1A8-1AB
-        u32     xPMC7;          // Perf Monitor Counter 7       1AC-1AF
-        u32     xPMC8;          // Perf Monitor Counter 8       1B0-1B3
-        u32     xTSC;           // Thread Switch Control        1B4-1B7
-        u32     xTST;           // Thread Switch Timeout        1B8-1BB
-        u32     xRsvd;          // Reserved                     1BC-1BF
-
-        u64     xACCR;          // Address Compare Control Reg  1C0-1C7
-        u64     xIMR;           // Instruction Match Register   1C8-1CF
-        u64     xSDR1;          // Storage Description Reg 1    1D0-1D7
-        u64     xSPRG0;         // Special Purpose Reg General0 1D8-1DF
-        u64     xSPRG1;         // Special Purpose Reg General1 1E0-1E7
-        u64     xSPRG2;         // Special Purpose Reg General2 1E8-1EF
-        u64     xSPRG3;         // Special Purpose Reg General3 1F0-1F7
-        u64     xTB;            // Time Base Register           1F8-1FF
-
-        u64     xFPR[32];       // Floating Point Registers     200-2FF
-
-        u64     xMSR;           // Machine State Register       300-307
-        u64     xNIA;           // Next Instruction Address     308-30F
-
-        u64     xDABR;          // Data Address Breakpoint Reg  310-317
-        u64     xIABR;          // Inst Address Breakpoint Reg  318-31F
-
-        u64     xHID0;          // HW Implementation Dependent0 320-327
-
-        u64     xHID4;          // HW Implementation Dependent4 328-32F
-        u64     xSCOMd;         // SCON Data Reg (SPRG4)        330-337
-        u64     xSCOMc;         // SCON Command Reg (SPRG5)     338-33F
-        u64     xSDAR;          // Sample Data Address Register 340-347
-        u64     xSIAR;          // Sample Inst Address Register 348-34F
-
-        u8      xRsvd3[176];    // Reserved                     350-3FF
-};
-
-extern void system_reset_iSeries(void);
-extern void machine_check_iSeries(void);
-extern void data_access_iSeries(void);
-extern void instruction_access_iSeries(void);
-extern void hardware_interrupt_iSeries(void);
-extern void alignment_iSeries(void);
-extern void program_check_iSeries(void);
-extern void fp_unavailable_iSeries(void);
-extern void decrementer_iSeries(void);
-extern void trap_0a_iSeries(void);
-extern void trap_0b_iSeries(void);
-extern void system_call_iSeries(void);
-extern void single_step_iSeries(void);
-extern void trap_0e_iSeries(void);
-extern void performance_monitor_iSeries(void);
-extern void data_access_slb_iSeries(void);
-extern void instruction_access_slb_iSeries(void);
-
-struct ItLpNaca itLpNaca = {
-        .xDesc = 0xd397d581,            /* "LpNa" ebcdic */
-        .xSize = 0x0400,                /* size of ItLpNaca */
-        .xIntHdlrOffset = 0x0300,       /* offset to int array */
-        .xMaxIntHdlrEntries = 19,       /* # ents */
-        .xPrimaryLpIndex = 0,           /* Part # of primary */
-        .xServiceLpIndex = 0,           /* Part # of serv */
-        .xLpIndex = 0,                  /* Part # of me */
-        .xMaxLpQueues = 0,              /* # of LP queues */
-        .xLpQueueOffset = 0x100,        /* offset of start of LP queues */
-        .xPirEnvironMode = 0,           /* Piranha stuff */
-        .xPirConsoleMode = 0,
-        .xPirDasdMode = 0,
-        .flags = 0,
-        .xSpVpdFormat = 0,
-        .xIntProcRatio = 0,
-        .xPlicVrmIndex = 0,             /* VRM index of PLIC */
-        .xMinSupportedSlicVrmInd = 0,   /* min supported SLIC */
-        .xMinCompatableSlicVrmInd = 0,  /* min compat SLIC */
-        .xLoadAreaAddr = 0,             /* 64-bit addr of load area */
-        .xLoadAreaChunks = 0,           /* chunks for load area */
-        .xPaseSysCallCRMask = 0,        /* PASE mask */
-        .xSlicSegmentTablePtr = 0,      /* seg table */
-        .xOldLpQueue = { 0 },           /* Old LP Queue */
-        .xInterruptHdlr = {
-                (u64)system_reset_iSeries,      /* 0x100 System Reset */
-                (u64)machine_check_iSeries,     /* 0x200 Machine Check */
-                (u64)data_access_iSeries,       /* 0x300 Data Access */
-                (u64)instruction_access_iSeries, /* 0x400 Instruction Access */
-                (u64)hardware_interrupt_iSeries, /* 0x500 External */
-                (u64)alignment_iSeries,         /* 0x600 Alignment */
-                (u64)program_check_iSeries,     /* 0x700 Program Check */
-                (u64)fp_unavailable_iSeries,    /* 0x800 FP Unavailable */
-                (u64)decrementer_iSeries,       /* 0x900 Decrementer */
-                (u64)trap_0a_iSeries,           /* 0xa00 Trap 0A */
-                (u64)trap_0b_iSeries,           /* 0xb00 Trap 0B */
-                (u64)system_call_iSeries,       /* 0xc00 System Call */
-                (u64)single_step_iSeries,       /* 0xd00 Single Step */
-                (u64)trap_0e_iSeries,           /* 0xe00 Trap 0E */
-                (u64)performance_monitor_iSeries,/* 0xf00 Performance Monitor */
-                0,                              /* int 0x1000 */
-                0,                              /* int 0x1010 */
-                0,                              /* int 0x1020 CPU ctls */
-                (u64)hardware_interrupt_iSeries, /* SC Ret Hdlr */
-                (u64)data_access_slb_iSeries,   /* 0x380 D-SLB */
-                (u64)instruction_access_slb_iSeries /* 0x480 I-SLB */
-        }
-};
-
-/* May be filled in by the hypervisor so cannot end up in the BSS */
-static struct ItIplParmsReal xItIplParmsReal __attribute__((__section__(".data")));
-
-/* May be filled in by the hypervisor so cannot end up in the BSS */
-struct ItExtVpdPanel xItExtVpdPanel __attribute__((__section__(".data")));
-
-#define maxPhysicalProcessors 32
-
-struct IoHriProcessorVpd xIoHriProcessorVpd[maxPhysicalProcessors] = {
-        {
-                .xInstCacheOperandSize = 32,
-                .xDataCacheOperandSize = 32,
-                .xProcFreq     = 50000000,
-                .xTimeBaseFreq = 50000000,
-                .xPVR = 0x3600
-        }
-};
-
-/* Space for Main Store Vpd 27,200 bytes */
-/* May be filled in by the hypervisor so cannot end up in the BSS */
-u64    xMsVpd[3400] __attribute__((__section__(".data")));
-
-/* Space for Recovery Log Buffer */
-/* May be filled in by the hypervisor so cannot end up in the BSS */
-static u64    xRecoveryLogBuffer[32] __attribute__((__section__(".data")));
-
-static const struct SpCommArea xSpCommArea = {
-        .xDesc = 0xE2D7C3C2,
-        .xFormat = 1,
-};
-
-static const struct ItLpRegSave iseries_reg_save[] = {
-        [0 ... (NR_CPUS-1)] = {
-                .xDesc = 0xd397d9e2,    /* "LpRS" */
-                .xSize = sizeof(struct ItLpRegSave),
-        },
-};
-
-#define ALPACA_INIT(number)                                             \
-{                                                                       \
-        .lppaca_ptr = &lppaca[number],                                  \
-        .reg_save_ptr = &iseries_reg_save[number],                      \
-}
-
-const struct alpaca alpaca[] = {
-        ALPACA_INIT( 0),
-#if NR_CPUS > 1
-        ALPACA_INIT( 1), ALPACA_INIT( 2), ALPACA_INIT( 3),
-#if NR_CPUS > 4
-        ALPACA_INIT( 4), ALPACA_INIT( 5), ALPACA_INIT( 6), ALPACA_INIT( 7),
-#if NR_CPUS > 8
-        ALPACA_INIT( 8), ALPACA_INIT( 9), ALPACA_INIT(10), ALPACA_INIT(11),
-        ALPACA_INIT(12), ALPACA_INIT(13), ALPACA_INIT(14), ALPACA_INIT(15),
-        ALPACA_INIT(16), ALPACA_INIT(17), ALPACA_INIT(18), ALPACA_INIT(19),
-        ALPACA_INIT(20), ALPACA_INIT(21), ALPACA_INIT(22), ALPACA_INIT(23),
-        ALPACA_INIT(24), ALPACA_INIT(25), ALPACA_INIT(26), ALPACA_INIT(27),
-        ALPACA_INIT(28), ALPACA_INIT(29), ALPACA_INIT(30), ALPACA_INIT(31),
-#if NR_CPUS > 32
-        ALPACA_INIT(32), ALPACA_INIT(33), ALPACA_INIT(34), ALPACA_INIT(35),
-        ALPACA_INIT(36), ALPACA_INIT(37), ALPACA_INIT(38), ALPACA_INIT(39),
-        ALPACA_INIT(40), ALPACA_INIT(41), ALPACA_INIT(42), ALPACA_INIT(43),
-        ALPACA_INIT(44), ALPACA_INIT(45), ALPACA_INIT(46), ALPACA_INIT(47),
-        ALPACA_INIT(48), ALPACA_INIT(49), ALPACA_INIT(50), ALPACA_INIT(51),
-        ALPACA_INIT(52), ALPACA_INIT(53), ALPACA_INIT(54), ALPACA_INIT(55),
-        ALPACA_INIT(56), ALPACA_INIT(57), ALPACA_INIT(58), ALPACA_INIT(59),
-        ALPACA_INIT(60), ALPACA_INIT(61), ALPACA_INIT(62), ALPACA_INIT(63),
-#endif
-#endif
-#endif
-#endif
-};
-
-/* The LparMap data is now located at offset 0x6000 in head.S
- * It was put there so that the HvReleaseData could address it
- * with a 32-bit offset as required by the iSeries hypervisor
- *
- * The Naca has a pointer to the ItVpdAreas.  The hypervisor finds
- * the Naca via the HvReleaseData area.  The HvReleaseData has the
- * offset into the Naca of the pointer to the ItVpdAreas.
- */
-const struct ItVpdAreas itVpdAreas = {
-        .xSlicDesc = 0xc9a3e5c1,                /* "ItVA" */
-        .xSlicSize = sizeof(struct ItVpdAreas),
-        .xSlicVpdEntries = ItVpdMaxEntries,     /* # VPD array entries */
-        .xSlicDmaEntries = ItDmaMaxEntries,     /* # DMA array entries */
-        .xSlicMaxLogicalProcs = NR_CPUS * 2,    /* Max logical procs */
-        .xSlicMaxPhysicalProcs = maxPhysicalProcessors, /* Max physical procs */
-        .xSlicDmaToksOffset = offsetof(struct ItVpdAreas, xPlicDmaToks),
-        .xSlicVpdAdrsOffset = offsetof(struct ItVpdAreas, xSlicVpdAdrs),
-        .xSlicDmaLensOffset = offsetof(struct ItVpdAreas, xPlicDmaLens),
-        .xSlicVpdLensOffset = offsetof(struct ItVpdAreas, xSlicVpdLens),
-        .xSlicMaxSlotLabels = 0,                /* max slot labels */
-        .xSlicMaxLpQueues = 1,                  /* max LP queues */
-        .xPlicDmaLens = { 0 },                  /* DMA lengths */
-        .xPlicDmaToks = { 0 },                  /* DMA tokens */
-        .xSlicVpdLens = {                       /* VPD lengths */
-                0,0,0,                  /*  0 - 2 */
-                sizeof(xItExtVpdPanel), /*       3 Extended VPD   */
-                sizeof(struct alpaca),  /*       4 length of (fake) Paca  */
-                0,                      /*       5 */
-                sizeof(struct ItIplParmsReal),/* 6 length of IPL parms */
-                26992,                  /*       7 length of MS VPD */
-                0,                      /*       8 */
-                sizeof(struct ItLpNaca),/*       9 length of LP Naca */
-                0,                      /*      10 */
-                256,                    /*      11 length of Recovery Log Buf */
-                sizeof(struct SpCommArea), /*   12 length of SP Comm Area */
-                0,0,0,                  /* 13 - 15 */
-                sizeof(struct IoHriProcessorVpd),/* 16 length of Proc Vpd */
-                0,0,0,0,0,0,            /* 17 - 22  */
-                sizeof(struct hvlpevent_queue), /* 23 length of Lp Queue */
-                0,0                     /* 24 - 25 */
-                },
-        .xSlicVpdAdrs = {                       /* VPD addresses */
-                0,0,0,                  /*       0 -  2 */
-                &xItExtVpdPanel,        /*       3 Extended VPD */
-                &alpaca[0],             /*       4 first (fake) Paca */
-                0,                      /*       5 */
-                &xItIplParmsReal,       /*       6 IPL parms */
-                &xMsVpd,                /*       7 MS Vpd */
-                0,                      /*       8 */
-                &itLpNaca,              /*       9 LpNaca */
-                0,                      /*      10 */
-                &xRecoveryLogBuffer,    /*      11 Recovery Log Buffer */
-                &xSpCommArea,           /*      12 SP Comm Area */
-                0,0,0,                  /* 13 - 15 */
-                &xIoHriProcessorVpd,    /*      16 Proc Vpd */
-                0,0,0,0,0,0,            /* 17 - 22 */
-                &hvlpevent_queue,       /*      23 Lp Queue */
-                0,0
-        }
-};
diff --git a/arch/powerpc/platforms/iseries/lpevents.c b/arch/powerpc/platforms/iseries/lpevents.c
deleted file mode 100644
index 202e22798d3..00000000000
--- a/arch/powerpc/platforms/iseries/lpevents.c
+++ /dev/null
@@ -1,341 +0,0 @@
-/*
- * Copyright (C) 2001 Mike Corrigan  IBM Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-
-#include <linux/stddef.h>
-#include <linux/kernel.h>
-#include <linux/sched.h>
-#include <linux/bootmem.h>
-#include <linux/seq_file.h>
-#include <linux/proc_fs.h>
-#include <linux/export.h>
-
-#include <asm/system.h>
-#include <asm/paca.h>
-#include <asm/firmware.h>
-#include <asm/iseries/it_lp_queue.h>
-#include <asm/iseries/hv_lp_event.h>
-#include <asm/iseries/hv_call_event.h>
-#include "it_lp_naca.h"
-
-/*
- * The LpQueue is used to pass event data from the hypervisor to
- * the partition.  This is where I/O interrupt events are communicated.
- *
- * It is written to by the hypervisor so cannot end up in the BSS.
- */
-struct hvlpevent_queue hvlpevent_queue __attribute__((__section__(".data")));
-
-DEFINE_PER_CPU(unsigned long[HvLpEvent_Type_NumTypes], hvlpevent_counts);
-
-static char *event_types[HvLpEvent_Type_NumTypes] = {
-        "Hypervisor",
-        "Machine Facilities",
-        "Session Manager",
-        "SPD I/O",
-        "Virtual Bus",
-        "PCI I/O",
-        "RIO I/O",
-        "Virtual Lan",
-        "Virtual I/O"
-};
-
-/* Array of LpEvent handler functions */
-static LpEventHandler lpEventHandler[HvLpEvent_Type_NumTypes];
-static unsigned lpEventHandlerPaths[HvLpEvent_Type_NumTypes];
-
-static struct HvLpEvent * get_next_hvlpevent(void)
-{
-        struct HvLpEvent * event;
-        event = (struct HvLpEvent *)hvlpevent_queue.hq_current_event;
-
-        if (hvlpevent_is_valid(event)) {
-                /* rmb() needed only for weakly consistent machines (regatta) */
-                rmb();
-                /* Set pointer to next potential event */
-                hvlpevent_queue.hq_current_event += ((event->xSizeMinus1 +
-                                IT_LP_EVENT_ALIGN) / IT_LP_EVENT_ALIGN) *
-                                        IT_LP_EVENT_ALIGN;
-
-                /* Wrap to beginning if no room at end */
-                if (hvlpevent_queue.hq_current_event >
-                                hvlpevent_queue.hq_last_event) {
-                        hvlpevent_queue.hq_current_event =
-                                hvlpevent_queue.hq_event_stack;
-                }
-        } else {
-                event = NULL;
-        }
-
-        return event;
-}
-
-static unsigned long spread_lpevents = NR_CPUS;
-
-int hvlpevent_is_pending(void)
-{
-        struct HvLpEvent *next_event;
-
-        if (smp_processor_id() >= spread_lpevents)
-                return 0;
-
-        next_event = (struct HvLpEvent *)hvlpevent_queue.hq_current_event;
-
-        return hvlpevent_is_valid(next_event) ||
-                hvlpevent_queue.hq_overflow_pending;
-}
-
-static void hvlpevent_clear_valid(struct HvLpEvent * event)
-{
-        /* Tell the Hypervisor that we're done with this event.
-         * Also clear bits within this event that might look like valid bits.
-         * ie. on 64-byte boundaries.
-         */
-        struct HvLpEvent *tmp;
-        unsigned extra = ((event->xSizeMinus1 + IT_LP_EVENT_ALIGN) /
-                                IT_LP_EVENT_ALIGN) - 1;
-
-        switch (extra) {
-        case 3:
-                tmp = (struct HvLpEvent*)((char*)event + 3 * IT_LP_EVENT_ALIGN);
-                hvlpevent_invalidate(tmp);
-        case 2:
-                tmp = (struct HvLpEvent*)((char*)event + 2 * IT_LP_EVENT_ALIGN);
-                hvlpevent_invalidate(tmp);
-        case 1:
-                tmp = (struct HvLpEvent*)((char*)event + 1 * IT_LP_EVENT_ALIGN);
-                hvlpevent_invalidate(tmp);
-        }
-
-        mb();
-
-        hvlpevent_invalidate(event);
-}
-
-void process_hvlpevents(void)
-{
-        struct HvLpEvent * event;
-
- restart:
-        /* If we have recursed, just return */
-        if (!spin_trylock(&hvlpevent_queue.hq_lock))
-                return;
-
-        for (;;) {
-                event = get_next_hvlpevent();
-                if (event) {
-                        /* Call appropriate handler here, passing
-                         * a pointer to the LpEvent.  The handler
-                         * must make a copy of the LpEvent if it
-                         * needs it in a bottom half. (perhaps for
-                         * an ACK)
-                         *
-                         *  Handlers are responsible for ACK processing
-                         *
-                         * The Hypervisor guarantees that LpEvents will
-                         * only be delivered with types that we have
-                         * registered for, so no type check is necessary
-                         * here!
-                         */
-                        if (event->xType < HvLpEvent_Type_NumTypes)
-                                __get_cpu_var(hvlpevent_counts)[event->xType]++;
-                        if (event->xType < HvLpEvent_Type_NumTypes &&
-                                        lpEventHandler[event->xType])
-                                lpEventHandler[event->xType](event);
-                        else {
-                                u8 type = event->xType;
-
-                                /*
-                                 * Don't printk in the spinlock as printk
-                                 * may require ack events form the HV to send
-                                 * any characters there.
-                                 */
-                                hvlpevent_clear_valid(event);
-                                spin_unlock(&hvlpevent_queue.hq_lock);
-                                printk(KERN_INFO
-                                        "Unexpected Lp Event type=%d\n", type);
-                                goto restart;
-                        }
-
-                        hvlpevent_clear_valid(event);
-                } else if (hvlpevent_queue.hq_overflow_pending)
-                        /*
-                         * No more valid events. If overflow events are
-                         * pending process them
-                         */
-                        HvCallEvent_getOverflowLpEvents(hvlpevent_queue.hq_index);
-                else
-                        break;
-        }
-
-        spin_unlock(&hvlpevent_queue.hq_lock);
-}
-
-static int set_spread_lpevents(char *str)
-{
-        unsigned long val = simple_strtoul(str, NULL, 0);
-
-        /*
-         * The parameter is the number of processors to share in processing
-         * lp events.
-         */
-        if (( val > 0) && (val <= NR_CPUS)) {
-                spread_lpevents = val;
-                printk("lpevent processing spread over %ld processors\n", val);
-        } else {
-                printk("invalid spread_lpevents %ld\n", val);
-        }
-
-        return 1;
-}
-__setup("spread_lpevents=", set_spread_lpevents);
-
-void __init setup_hvlpevent_queue(void)
-{
-        void *eventStack;
-
-        spin_lock_init(&hvlpevent_queue.hq_lock);
-
-        /* Allocate a page for the Event Stack. */
-        eventStack = alloc_bootmem_pages(IT_LP_EVENT_STACK_SIZE);
-        memset(eventStack, 0, IT_LP_EVENT_STACK_SIZE);
-
-        /* Invoke the hypervisor to initialize the event stack */
-        HvCallEvent_setLpEventStack(0, eventStack, IT_LP_EVENT_STACK_SIZE);
-
-        hvlpevent_queue.hq_event_stack = eventStack;
-        hvlpevent_queue.hq_current_event = eventStack;
-        hvlpevent_queue.hq_last_event = (char *)eventStack +
-                (IT_LP_EVENT_STACK_SIZE - IT_LP_EVENT_MAX_SIZE);
-        hvlpevent_queue.hq_index = 0;
-}
-
-/* Register a handler for an LpEvent type */
-int HvLpEvent_registerHandler(HvLpEvent_Type eventType, LpEventHandler handler)
-{
-        if (eventType < HvLpEvent_Type_NumTypes) {
-                lpEventHandler[eventType] = handler;
-                return 0;
-        }
-        return 1;
-}
-EXPORT_SYMBOL(HvLpEvent_registerHandler);
-
-int HvLpEvent_unregisterHandler(HvLpEvent_Type eventType)
-{
-        might_sleep();
-
-        if (eventType < HvLpEvent_Type_NumTypes) {
-                if (!lpEventHandlerPaths[eventType]) {
-                        lpEventHandler[eventType] = NULL;
-                        /*
-                         * We now sleep until all other CPUs have scheduled.
-                         * This ensures that the deletion is seen by all
-                         * other CPUs, and that the deleted handler isn't
-                         * still running on another CPU when we return.
-                         */
-                        synchronize_sched();
-                        return 0;
-                }
-        }
-        return 1;
-}
-EXPORT_SYMBOL(HvLpEvent_unregisterHandler);
-
-/*
- * lpIndex is the partition index of the target partition.
- * needed only for VirtualIo, VirtualLan and SessionMgr.  Zero
- * indicates to use our partition index - for the other types.
- */
-int HvLpEvent_openPath(HvLpEvent_Type eventType, HvLpIndex lpIndex)
-{
-        if ((eventType < HvLpEvent_Type_NumTypes) &&
-                        lpEventHandler[eventType]) {
-                if (lpIndex == 0)
-                        lpIndex = itLpNaca.xLpIndex;
-                HvCallEvent_openLpEventPath(lpIndex, eventType);
-                ++lpEventHandlerPaths[eventType];
-                return 0;
-        }
-        return 1;
-}
-
-int HvLpEvent_closePath(HvLpEvent_Type eventType, HvLpIndex lpIndex)
-{
-        if ((eventType < HvLpEvent_Type_NumTypes) &&
-                        lpEventHandler[eventType] &&
-                        lpEventHandlerPaths[eventType]) {
-                if (lpIndex == 0)
-                        lpIndex = itLpNaca.xLpIndex;
-                HvCallEvent_closeLpEventPath(lpIndex, eventType);
-                --lpEventHandlerPaths[eventType];
-                return 0;
-        }
-        return 1;
-}
-
-static int proc_lpevents_show(struct seq_file *m, void *v)
-{
-        int cpu, i;
-        unsigned long sum;
-        static unsigned long cpu_totals[NR_CPUS];
-
-        /* FIXME: do we care that there's no locking here? */
-        sum = 0;
-        for_each_online_cpu(cpu) {
-                cpu_totals[cpu] = 0;
-                for (i = 0; i < HvLpEvent_Type_NumTypes; i++) {
-                        cpu_totals[cpu] += per_cpu(hvlpevent_counts, cpu)[i];
-                }
-                sum += cpu_totals[cpu];
-        }
-
-        seq_printf(m, "LpEventQueue 0\n");
-        seq_printf(m, "  events processed:\t%lu\n", sum);
-
-        for (i = 0; i < HvLpEvent_Type_NumTypes; ++i) {
-                sum = 0;
-                for_each_online_cpu(cpu) {
-                        sum += per_cpu(hvlpevent_counts, cpu)[i];
-                }
-
-                seq_printf(m, "    %-20s %10lu\n", event_types[i], sum);
-        }
-
-        seq_printf(m, "\n  events processed by processor:\n");
-
-        for_each_online_cpu(cpu) {
-                seq_printf(m, "    CPU%02d  %10lu\n", cpu, cpu_totals[cpu]);
-        }
-
-        return 0;
-}
-
-static int proc_lpevents_open(struct inode *inode, struct file *file)
-{
-        return single_open(file, proc_lpevents_show, NULL);
-}
-
-static const struct file_operations proc_lpevents_operations = {
-        .open           = proc_lpevents_open,
-        .read           = seq_read,
-        .llseek         = seq_lseek,
-        .release        = single_release,
-};
-
-static int __init proc_lpevents_init(void)
-{
-        if (!firmware_has_feature(FW_FEATURE_ISERIES))
-                return 0;
-
-        proc_create("iSeries/lpevents", S_IFREG|S_IRUGO, NULL,
-                    &proc_lpevents_operations);
-        return 0;
-}
-__initcall(proc_lpevents_init);
-
diff --git a/arch/powerpc/platforms/iseries/main_store.h b/arch/powerpc/platforms/iseries/main_store.h
deleted file mode 100644
index 1a7a3f50e40..00000000000
--- a/arch/powerpc/platforms/iseries/main_store.h
+++ /dev/null
@@ -1,165 +0,0 @@
-/*
- * Copyright (C) 2001  Mike Corrigan IBM Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
- */
-
-#ifndef _ISERIES_MAIN_STORE_H
-#define _ISERIES_MAIN_STORE_H
-
-/* Main Store Vpd for Condor,iStar,sStar */
-struct IoHriMainStoreSegment4 {
-        u8      msArea0Exists:1;
-        u8      msArea1Exists:1;
-        u8      msArea2Exists:1;
-        u8      msArea3Exists:1;
-        u8      reserved1:4;
-        u8      reserved2;
-
-        u8      msArea0Functional:1;
-        u8      msArea1Functional:1;
-        u8      msArea2Functional:1;
-        u8      msArea3Functional:1;
-        u8      reserved3:4;
-        u8      reserved4;
-
-        u32     totalMainStore;
-
-        u64     msArea0Ptr;
-        u64     msArea1Ptr;
-        u64     msArea2Ptr;
-        u64     msArea3Ptr;
-
-        u32     cardProductionLevel;
-
-        u32     msAdrHole;
-
-        u8      msArea0HasRiserVpd:1;
-        u8      msArea1HasRiserVpd:1;
-        u8      msArea2HasRiserVpd:1;
-        u8      msArea3HasRiserVpd:1;
-        u8      reserved5:4;
-        u8      reserved6;
-        u16     reserved7;
-
-        u8      reserved8[28];
-
-        u64     nonInterleavedBlocksStartAdr;
-        u64     nonInterleavedBlocksEndAdr;
-};
-
-/* Main Store VPD for Power4 */
-struct __attribute((packed)) IoHriMainStoreChipInfo1 {
-        u32     chipMfgID;
-        char    chipECLevel[4];
-};
-
-struct IoHriMainStoreVpdIdData {
-        char    typeNumber[4];
-        char    modelNumber[4];
-        char    partNumber[12];
-        char    serialNumber[12];
-};
-
-struct  __attribute((packed)) IoHriMainStoreVpdFruData {
-        char    fruLabel[8];
-        u8      numberOfSlots;
-        u8      pluggingType;
-        u16     slotMapIndex;
-};
-
-struct  __attribute((packed)) IoHriMainStoreAdrRangeBlock {
-        void    *blockStart;
-        void    *blockEnd;
-        u32     blockProcChipId;
-};
-
-#define MaxAreaAdrRangeBlocks 4
-
-struct __attribute((packed)) IoHriMainStoreArea4 {
-        u32     msVpdFormat;
-        u8      containedVpdType;
-        u8      reserved1;
-        u16     reserved2;
-
-        u64     msExists;
-        u64     msFunctional;
-
-        u32     memorySize;
-        u32     procNodeId;
-
-        u32     numAdrRangeBlocks;
-        struct IoHriMainStoreAdrRangeBlock xAdrRangeBlock[MaxAreaAdrRangeBlocks];
-
-        struct IoHriMainStoreChipInfo1  chipInfo0;
-        struct IoHriMainStoreChipInfo1  chipInfo1;
-        struct IoHriMainStoreChipInfo1  chipInfo2;
-        struct IoHriMainStoreChipInfo1  chipInfo3;
-        struct IoHriMainStoreChipInfo1  chipInfo4;
-        struct IoHriMainStoreChipInfo1  chipInfo5;
-        struct IoHriMainStoreChipInfo1  chipInfo6;
-        struct IoHriMainStoreChipInfo1  chipInfo7;
-
-        void    *msRamAreaArray;
-        u32     msRamAreaArrayNumEntries;
-        u32     msRamAreaArrayEntrySize;
-
-        u32     numaDimmExists;
-        u32     numaDimmFunctional;
-        void    *numaDimmArray;
-        u32     numaDimmArrayNumEntries;
-        u32     numaDimmArrayEntrySize;
-
-        struct IoHriMainStoreVpdIdData idData;
-
-        u64     powerData;
-        u64     cardAssemblyPartNum;
-        u64     chipSerialNum;
-
-        u64     reserved3;
-        char    reserved4[16];
-
-        struct IoHriMainStoreVpdFruData fruData;
-
-        u8      vpdPortNum;
-        u8      reserved5;
-        u8      frameId;
-        u8      rackUnit;
-        char    asciiKeywordVpd[256];
-        u32     reserved6;
-};
-
-
-struct IoHriMainStoreSegment5 {
-        u16     reserved1;
-        u8      reserved2;
-        u8      msVpdFormat;
-
-        u32     totalMainStore;
-        u64     maxConfiguredMsAdr;
-
-        struct IoHriMainStoreArea4      *msAreaArray;
-        u32     msAreaArrayNumEntries;
-        u32     msAreaArrayEntrySize;
-
-        u32     msAreaExists;
-        u32     msAreaFunctional;
-
-        u64     reserved3;
-};
-
-extern u64      xMsVpd[];
-
-#endif  /* _ISERIES_MAIN_STORE_H */
diff --git a/arch/powerpc/platforms/iseries/mf.c b/arch/powerpc/platforms/iseries/mf.c
deleted file mode 100644
index 254c1fc3d8d..00000000000
--- a/arch/powerpc/platforms/iseries/mf.c
+++ /dev/null
@@ -1,1275 +0,0 @@
-/*
- * Copyright (C) 2001 Troy D. Armstrong  IBM Corporation
- * Copyright (C) 2004-2005 Stephen Rothwell  IBM Corporation
- *
- * This modules exists as an interface between a Linux secondary partition
- * running on an iSeries and the primary partition's Virtual Service
- * Processor (VSP) object.  The VSP has final authority over powering on/off
- * all partitions in the iSeries.  It also provides miscellaneous low-level
- * machine facility type operations.
- *
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
- */
-
-#include <linux/types.h>
-#include <linux/errno.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/completion.h>
-#include <linux/delay.h>
-#include <linux/export.h>
-#include <linux/proc_fs.h>
-#include <linux/dma-mapping.h>
-#include <linux/bcd.h>
-#include <linux/rtc.h>
-#include <linux/slab.h>
-
-#include <asm/time.h>
-#include <asm/uaccess.h>
-#include <asm/paca.h>
-#include <asm/abs_addr.h>
-#include <asm/firmware.h>
-#include <asm/iseries/mf.h>
-#include <asm/iseries/hv_lp_config.h>
-#include <asm/iseries/hv_lp_event.h>
-#include <asm/iseries/it_lp_queue.h>
-
-#include "setup.h"
-
-static int mf_initialized;
-
-/*
- * This is the structure layout for the Machine Facilities LPAR event
- * flows.
- */
-struct vsp_cmd_data {
-        u64 token;
-        u16 cmd;
-        HvLpIndex lp_index;
-        u8 result_code;
-        u32 reserved;
-        union {
-                u64 state;      /* GetStateOut */
-                u64 ipl_type;   /* GetIplTypeOut, Function02SelectIplTypeIn */
-                u64 ipl_mode;   /* GetIplModeOut, Function02SelectIplModeIn */
-                u64 page[4];    /* GetSrcHistoryIn */
-                u64 flag;       /* GetAutoIplWhenPrimaryIplsOut,
-                                   SetAutoIplWhenPrimaryIplsIn,
-                                   WhiteButtonPowerOffIn,
-                                   Function08FastPowerOffIn,
-                                   IsSpcnRackPowerIncompleteOut */
-                struct {
-                        u64 token;
-                        u64 address_type;
-                        u64 side;
-                        u32 length;
-                        u32 offset;
-                } kern;         /* SetKernelImageIn, GetKernelImageIn,
-                                   SetKernelCmdLineIn, GetKernelCmdLineIn */
-                u32 length_out; /* GetKernelImageOut, GetKernelCmdLineOut */
-                u8 reserved[80];
-        } sub_data;
-};
-
-struct vsp_rsp_data {
-        struct completion com;
-        struct vsp_cmd_data *response;
-};
-
-struct alloc_data {
-        u16 size;
-        u16 type;
-        u32 count;
-        u16 reserved1;
-        u8 reserved2;
-        HvLpIndex target_lp;
-};
-
-struct ce_msg_data;
-
-typedef void (*ce_msg_comp_hdlr)(void *token, struct ce_msg_data *vsp_cmd_rsp);
-
-struct ce_msg_comp_data {
-        ce_msg_comp_hdlr handler;
-        void *token;
-};
-
-struct ce_msg_data {
-        u8 ce_msg[12];
-        char reserved[4];
-        struct ce_msg_comp_data *completion;
-};
-
-struct io_mf_lp_event {
-        struct HvLpEvent hp_lp_event;
-        u16 subtype_result_code;
-        u16 reserved1;
-        u32 reserved2;
-        union {
-                struct alloc_data alloc;
-                struct ce_msg_data ce_msg;
-                struct vsp_cmd_data vsp_cmd;
-        } data;
-};
-
-#define subtype_data(a, b, c, d)        \
-                (((a) << 24) + ((b) << 16) + ((c) << 8) + (d))
-
-/*
- * All outgoing event traffic is kept on a FIFO queue.  The first
- * pointer points to the one that is outstanding, and all new
- * requests get stuck on the end.  Also, we keep a certain number of
- * preallocated pending events so that we can operate very early in
- * the boot up sequence (before kmalloc is ready).
- */
-struct pending_event {
-        struct pending_event *next;
-        struct io_mf_lp_event event;
-        MFCompleteHandler hdlr;
-        char dma_data[72];
-        unsigned dma_data_length;
-        unsigned remote_address;
-};
-static spinlock_t pending_event_spinlock;
-static struct pending_event *pending_event_head;
-static struct pending_event *pending_event_tail;
-static struct pending_event *pending_event_avail;
-#define PENDING_EVENT_PREALLOC_LEN 16
-static struct pending_event pending_event_prealloc[PENDING_EVENT_PREALLOC_LEN];
-
-/*
- * Put a pending event onto the available queue, so it can get reused.
- * Attention! You must have the pending_event_spinlock before calling!
- */
-static void free_pending_event(struct pending_event *ev)
-{
-        if (ev != NULL) {
-                ev->next = pending_event_avail;
-                pending_event_avail = ev;
-        }
-}
-
-/*
- * Enqueue the outbound event onto the stack.  If the queue was
- * empty to begin with, we must also issue it via the Hypervisor
- * interface.  There is a section of code below that will touch
- * the first stack pointer without the protection of the pending_event_spinlock.
- * This is OK, because we know that nobody else will be modifying
- * the first pointer when we do this.
- */
-static int signal_event(struct pending_event *ev)
-{
-        int rc = 0;
-        unsigned long flags;
-        int go = 1;
-        struct pending_event *ev1;
-        HvLpEvent_Rc hv_rc;
-
-        /* enqueue the event */
-        if (ev != NULL) {
-                ev->next = NULL;
-                spin_lock_irqsave(&pending_event_spinlock, flags);
-                if (pending_event_head == NULL)
-                        pending_event_head = ev;
-                else {
-                        go = 0;
-                        pending_event_tail->next = ev;
-                }
-                pending_event_tail = ev;
-                spin_unlock_irqrestore(&pending_event_spinlock, flags);
-        }
-
-        /* send the event */
-        while (go) {
-                go = 0;
-
-                /* any DMA data to send beforehand? */
-                if (pending_event_head->dma_data_length > 0)
-                        HvCallEvent_dmaToSp(pending_event_head->dma_data,
-                                        pending_event_head->remote_address,
-                                        pending_event_head->dma_data_length,
-                                        HvLpDma_Direction_LocalToRemote);
-
-                hv_rc = HvCallEvent_signalLpEvent(
-                                &pending_event_head->event.hp_lp_event);
-                if (hv_rc != HvLpEvent_Rc_Good) {
-                        printk(KERN_ERR "mf.c: HvCallEvent_signalLpEvent() "
-                                        "failed with %d\n", (int)hv_rc);
-
-                        spin_lock_irqsave(&pending_event_spinlock, flags);
-                        ev1 = pending_event_head;
-                        pending_event_head = pending_event_head->next;
-                        if (pending_event_head != NULL)
-                                go = 1;
-                        spin_unlock_irqrestore(&pending_event_spinlock, flags);
-
-                        if (ev1 == ev)
-                                rc = -EIO;
-                        else if (ev1->hdlr != NULL)
-                                (*ev1->hdlr)((void *)ev1->event.hp_lp_event.xCorrelationToken, -EIO);
-
-                        spin_lock_irqsave(&pending_event_spinlock, flags);
-                        free_pending_event(ev1);
-                        spin_unlock_irqrestore(&pending_event_spinlock, flags);
-                }
-        }
-
-        return rc;
-}
-
-/*
- * Allocate a new pending_event structure, and initialize it.
- */
-static struct pending_event *new_pending_event(void)
-{
-        struct pending_event *ev = NULL;
-        HvLpIndex primary_lp = HvLpConfig_getPrimaryLpIndex();
-        unsigned long flags;
-        struct HvLpEvent *hev;
-
-        spin_lock_irqsave(&pending_event_spinlock, flags);
-        if (pending_event_avail != NULL) {
-                ev = pending_event_avail;
-                pending_event_avail = pending_event_avail->next;
-        }
-        spin_unlock_irqrestore(&pending_event_spinlock, flags);
-        if (ev == NULL) {
-                ev = kmalloc(sizeof(struct pending_event), GFP_ATOMIC);
-                if (ev == NULL) {
-                        printk(KERN_ERR "mf.c: unable to kmalloc %ld bytes\n",
-                                        sizeof(struct pending_event));
-                        return NULL;
-                }
-        }
-        memset(ev, 0, sizeof(struct pending_event));
-        hev = &ev->event.hp_lp_event;
-        hev->flags = HV_LP_EVENT_VALID | HV_LP_EVENT_DO_ACK | HV_LP_EVENT_INT;
-        hev->xType = HvLpEvent_Type_MachineFac;
-        hev->xSourceLp = HvLpConfig_getLpIndex();
-        hev->xTargetLp = primary_lp;
-        hev->xSizeMinus1 = sizeof(ev->event) - 1;
-        hev->xRc = HvLpEvent_Rc_Good;
-        hev->xSourceInstanceId = HvCallEvent_getSourceLpInstanceId(primary_lp,
-                        HvLpEvent_Type_MachineFac);
-        hev->xTargetInstanceId = HvCallEvent_getTargetLpInstanceId(primary_lp,
-                        HvLpEvent_Type_MachineFac);
-
-        return ev;
-}
-
-static int __maybe_unused
-signal_vsp_instruction(struct vsp_cmd_data *vsp_cmd)
-{
-        struct pending_event *ev = new_pending_event();
-        int rc;
-        struct vsp_rsp_data response;
-
-        if (ev == NULL)
-                return -ENOMEM;
-
-        init_completion(&response.com);
-        response.response = vsp_cmd;
-        ev->event.hp_lp_event.xSubtype = 6;
-        ev->event.hp_lp_event.x.xSubtypeData =
-                subtype_data('M', 'F',  'V',  'I');
-        ev->event.data.vsp_cmd.token = (u64)&response;
-        ev->event.data.vsp_cmd.cmd = vsp_cmd->cmd;
-        ev->event.data.vsp_cmd.lp_index = HvLpConfig_getLpIndex();
-        ev->event.data.vsp_cmd.result_code = 0xFF;
-        ev->event.data.vsp_cmd.reserved = 0;
-        memcpy(&(ev->event.data.vsp_cmd.sub_data),
-                        &(vsp_cmd->sub_data), sizeof(vsp_cmd->sub_data));
-        mb();
-
-        rc = signal_event(ev);
-        if (rc == 0)
-                wait_for_completion(&response.com);
-        return rc;
-}
-
-
-/*
- * Send a 12-byte CE message to the primary partition VSP object
- */
-static int signal_ce_msg(char *ce_msg, struct ce_msg_comp_data *completion)
-{
-        struct pending_event *ev = new_pending_event();
-
-        if (ev == NULL)
-                return -ENOMEM;
-
-        ev->event.hp_lp_event.xSubtype = 0;
-        ev->event.hp_lp_event.x.xSubtypeData =
-                subtype_data('M',  'F',  'C',  'E');
-        memcpy(ev->event.data.ce_msg.ce_msg, ce_msg, 12);
-        ev->event.data.ce_msg.completion = completion;
-        return signal_event(ev);
-}
-
-/*
- * Send a 12-byte CE message (with no data) to the primary partition VSP object
- */
-static int signal_ce_msg_simple(u8 ce_op, struct ce_msg_comp_data *completion)
-{
-        u8 ce_msg[12];
-
-        memset(ce_msg, 0, sizeof(ce_msg));
-        ce_msg[3] = ce_op;
-        return signal_ce_msg(ce_msg, completion);
-}
-
-/*
- * Send a 12-byte CE message and DMA data to the primary partition VSP object
- */
-static int dma_and_signal_ce_msg(char *ce_msg,
-                struct ce_msg_comp_data *completion, void *dma_data,
-                unsigned dma_data_length, unsigned remote_address)
-{
-        struct pending_event *ev = new_pending_event();
-
-        if (ev == NULL)
-                return -ENOMEM;
-
-        ev->event.hp_lp_event.xSubtype = 0;
-        ev->event.hp_lp_event.x.xSubtypeData =
-                subtype_data('M', 'F', 'C', 'E');
-        memcpy(ev->event.data.ce_msg.ce_msg, ce_msg, 12);
-        ev->event.data.ce_msg.completion = completion;
-        memcpy(ev->dma_data, dma_data, dma_data_length);
-        ev->dma_data_length = dma_data_length;
-        ev->remote_address = remote_address;
-        return signal_event(ev);
-}
-
-/*
- * Initiate a nice (hopefully) shutdown of Linux.  We simply are
- * going to try and send the init process a SIGINT signal.  If
- * this fails (why?), we'll simply force it off in a not-so-nice
- * manner.
- */
-static int shutdown(void)
-{
-        int rc = kill_cad_pid(SIGINT, 1);
-
-        if (rc) {
-                printk(KERN_ALERT "mf.c: SIGINT to init failed (%d), "
-                                "hard shutdown commencing\n", rc);
-                mf_power_off();
-        } else
-                printk(KERN_INFO "mf.c: init has been successfully notified "
-                                "to proceed with shutdown\n");
-        return rc;
-}
-
-/*
- * The primary partition VSP object is sending us a new
- * event flow.  Handle it...
- */
-static void handle_int(struct io_mf_lp_event *event)
-{
-        struct ce_msg_data *ce_msg_data;
-        struct ce_msg_data *pce_msg_data;
-        unsigned long flags;
-        struct pending_event *pev;
-
-        /* ack the interrupt */
-        event->hp_lp_event.xRc = HvLpEvent_Rc_Good;
-        HvCallEvent_ackLpEvent(&event->hp_lp_event);
-
-        /* process interrupt */
-        switch (event->hp_lp_event.xSubtype) {
-        case 0: /* CE message */
-                ce_msg_data = &event->data.ce_msg;
-                switch (ce_msg_data->ce_msg[3]) {
-                case 0x5B:      /* power control notification */
-                        if ((ce_msg_data->ce_msg[5] & 0x20) != 0) {
-                                printk(KERN_INFO "mf.c: Commencing partition shutdown\n");
-                                if (shutdown() == 0)
-                                        signal_ce_msg_simple(0xDB, NULL);
-                        }
-                        break;
-                case 0xC0:      /* get time */
-                        spin_lock_irqsave(&pending_event_spinlock, flags);
-                        pev = pending_event_head;
-                        if (pev != NULL)
-                                pending_event_head = pending_event_head->next;
-                        spin_unlock_irqrestore(&pending_event_spinlock, flags);
-                        if (pev == NULL)
-                                break;
-                        pce_msg_data = &pev->event.data.ce_msg;
-                        if (pce_msg_data->ce_msg[3] != 0x40)
-                                break;
-                        if (pce_msg_data->completion != NULL) {
-                                ce_msg_comp_hdlr handler =
-                                        pce_msg_data->completion->handler;
-                                void *token = pce_msg_data->completion->token;
-
-                                if (handler != NULL)
-                                        (*handler)(token, ce_msg_data);
-                        }
-                        spin_lock_irqsave(&pending_event_spinlock, flags);
-                        free_pending_event(pev);
-                        spin_unlock_irqrestore(&pending_event_spinlock, flags);
-                        /* send next waiting event */
-                        if (pending_event_head != NULL)
-                                signal_event(NULL);
-                        break;
-                }
-                break;
-        case 1: /* IT sys shutdown */
-                printk(KERN_INFO "mf.c: Commencing system shutdown\n");
-                shutdown();
-                break;
-        }
-}
-
-/*
- * The primary partition VSP object is acknowledging the receipt
- * of a flow we sent to them.  If there are other flows queued
- * up, we must send another one now...
- */
-static void handle_ack(struct io_mf_lp_event *event)
-{
-        unsigned long flags;
-        struct pending_event *two = NULL;
-        unsigned long free_it = 0;
-        struct ce_msg_data *ce_msg_data;
-        struct ce_msg_data *pce_msg_data;
-        struct vsp_rsp_data *rsp;
-
-        /* handle current event */
-        if (pending_event_head == NULL) {
-                printk(KERN_ERR "mf.c: stack empty for receiving ack\n");
-                return;
-        }
-
-        switch (event->hp_lp_event.xSubtype) {
-        case 0:     /* CE msg */
-                ce_msg_data = &event->data.ce_msg;
-                if (ce_msg_data->ce_msg[3] != 0x40) {
-                        free_it = 1;
-                        break;
-                }
-                if (ce_msg_data->ce_msg[2] == 0)
-                        break;
-                free_it = 1;
-                pce_msg_data = &pending_event_head->event.data.ce_msg;
-                if (pce_msg_data->completion != NULL) {
-                        ce_msg_comp_hdlr handler =
-                                pce_msg_data->completion->handler;
-                        void *token = pce_msg_data->completion->token;
-
-                        if (handler != NULL)
-                                (*handler)(token, ce_msg_data);
-                }
-                break;
-        case 4: /* allocate */
-        case 5: /* deallocate */
-                if (pending_event_head->hdlr != NULL)
-                        (*pending_event_head->hdlr)((void *)event->hp_lp_event.xCorrelationToken, event->data.alloc.count);
-                free_it = 1;
-                break;
-        case 6:
-                free_it = 1;
-                rsp = (struct vsp_rsp_data *)event->data.vsp_cmd.token;
-                if (rsp == NULL) {
-                        printk(KERN_ERR "mf.c: no rsp\n");
-                        break;
-                }
-                if (rsp->response != NULL)
-                        memcpy(rsp->response, &event->data.vsp_cmd,
-                                        sizeof(event->data.vsp_cmd));
-                complete(&rsp->com);
-                break;
-        }
-
-        /* remove from queue */
-        spin_lock_irqsave(&pending_event_spinlock, flags);
-        if ((pending_event_head != NULL) && (free_it == 1)) {
-                struct pending_event *oldHead = pending_event_head;
-
-                pending_event_head = pending_event_head->next;
-                two = pending_event_head;
-                free_pending_event(oldHead);
-        }
-        spin_unlock_irqrestore(&pending_event_spinlock, flags);
-
-        /* send next waiting event */
-        if (two != NULL)
-                signal_event(NULL);
-}
-
-/*
- * This is the generic event handler we are registering with
- * the Hypervisor.  Ensure the flows are for us, and then
- * parse it enough to know if it is an interrupt or an
- * acknowledge.
- */
-static void hv_handler(struct HvLpEvent *event)
-{
-        if ((event != NULL) && (event->xType == HvLpEvent_Type_MachineFac)) {
-                if (hvlpevent_is_ack(event))
-                        handle_ack((struct io_mf_lp_event *)event);
-                else
-                        handle_int((struct io_mf_lp_event *)event);
-        } else
-                printk(KERN_ERR "mf.c: alien event received\n");
-}
-
-/*
- * Global kernel interface to allocate and seed events into the
- * Hypervisor.
- */
-void mf_allocate_lp_events(HvLpIndex target_lp, HvLpEvent_Type type,
-                unsigned size, unsigned count, MFCompleteHandler hdlr,
-                void *user_token)
-{
-        struct pending_event *ev = new_pending_event();
-        int rc;
-
-        if (ev == NULL) {
-                rc = -ENOMEM;
-        } else {
-                ev->event.hp_lp_event.xSubtype = 4;
-                ev->event.hp_lp_event.xCorrelationToken = (u64)user_token;
-                ev->event.hp_lp_event.x.xSubtypeData =
-                        subtype_data('M', 'F', 'M', 'A');
-                ev->event.data.alloc.target_lp = target_lp;
-                ev->event.data.alloc.type = type;
-                ev->event.data.alloc.size = size;
-                ev->event.data.alloc.count = count;
-                ev->hdlr = hdlr;
-                rc = signal_event(ev);
-        }
-        if ((rc != 0) && (hdlr != NULL))
-                (*hdlr)(user_token, rc);
-}
-EXPORT_SYMBOL(mf_allocate_lp_events);
-
-/*
- * Global kernel interface to unseed and deallocate events already in
- * Hypervisor.
- */
-void mf_deallocate_lp_events(HvLpIndex target_lp, HvLpEvent_Type type,
-                unsigned count, MFCompleteHandler hdlr, void *user_token)
-{
-        struct pending_event *ev = new_pending_event();
-        int rc;
-
-        if (ev == NULL)
-                rc = -ENOMEM;
-        else {
-                ev->event.hp_lp_event.xSubtype = 5;
-                ev->event.hp_lp_event.xCorrelationToken = (u64)user_token;
-                ev->event.hp_lp_event.x.xSubtypeData =
-                        subtype_data('M', 'F', 'M', 'D');
-                ev->event.data.alloc.target_lp = target_lp;
-                ev->event.data.alloc.type = type;
-                ev->event.data.alloc.count = count;
-                ev->hdlr = hdlr;
-                rc = signal_event(ev);
-        }
-        if ((rc != 0) && (hdlr != NULL))
-                (*hdlr)(user_token, rc);
-}
-EXPORT_SYMBOL(mf_deallocate_lp_events);
-
-/*
- * Global kernel interface to tell the VSP object in the primary
- * partition to power this partition off.
- */
-void mf_power_off(void)
-{
-        printk(KERN_INFO "mf.c: Down it goes...\n");
-        signal_ce_msg_simple(0x4d, NULL);
-        for (;;)
-                ;
-}
-
-/*
- * Global kernel interface to tell the VSP object in the primary
- * partition to reboot this partition.
- */
-void mf_reboot(char *cmd)
-{
-        printk(KERN_INFO "mf.c: Preparing to bounce...\n");
-        signal_ce_msg_simple(0x4e, NULL);
-        for (;;)
-                ;
-}
-
-/*
- * Display a single word SRC onto the VSP control panel.
- */
-void mf_display_src(u32 word)
-{
-        u8 ce[12];
-
-        memset(ce, 0, sizeof(ce));
-        ce[3] = 0x4a;
-        ce[7] = 0x01;
-        ce[8] = word >> 24;
-        ce[9] = word >> 16;
-        ce[10] = word >> 8;
-        ce[11] = word;
-        signal_ce_msg(ce, NULL);
-}
-
-/*
- * Display a single word SRC of the form "PROGXXXX" on the VSP control panel.
- */
-static __init void mf_display_progress_src(u16 value)
-{
-        u8 ce[12];
-        u8 src[72];
-
-        memcpy(ce, "\x00\x00\x04\x4A\x00\x00\x00\x48\x00\x00\x00\x00", 12);
-        memcpy(src, "\x01\x00\x00\x01\x00\x00\x00\x00\x00\x00\x00\x00"
-                "\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00"
-                "\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00"
-                "\x00\x00\x00\x00PROGxxxx                        ",
-                72);
-        src[6] = value >> 8;
-        src[7] = value & 255;
-        src[44] = "0123456789ABCDEF"[(value >> 12) & 15];
-        src[45] = "0123456789ABCDEF"[(value >> 8) & 15];
-        src[46] = "0123456789ABCDEF"[(value >> 4) & 15];
-        src[47] = "0123456789ABCDEF"[value & 15];
-        dma_and_signal_ce_msg(ce, NULL, src, sizeof(src), 9 * 64 * 1024);
-}
-
-/*
- * Clear the VSP control panel.  Used to "erase" an SRC that was
- * previously displayed.
- */
-static void mf_clear_src(void)
-{
-        signal_ce_msg_simple(0x4b, NULL);
-}
-
-void __init mf_display_progress(u16 value)
-{
-        if (!mf_initialized)
-                return;
-
-        if (0xFFFF == value)
-                mf_clear_src();
-        else
-                mf_display_progress_src(value);
-}
-
-/*
- * Initialization code here.
- */
-void __init mf_init(void)
-{
-        int i;
-
-        spin_lock_init(&pending_event_spinlock);
-
-        for (i = 0; i < PENDING_EVENT_PREALLOC_LEN; i++)
-                free_pending_event(&pending_event_prealloc[i]);
-
-        HvLpEvent_registerHandler(HvLpEvent_Type_MachineFac, &hv_handler);
-
-        /* virtual continue ack */
-        signal_ce_msg_simple(0x57, NULL);
-
-        mf_initialized = 1;
-        mb();
-
-        printk(KERN_NOTICE "mf.c: iSeries Linux LPAR Machine Facilities "
-                        "initialized\n");
-}
-
-struct rtc_time_data {
-        struct completion com;
-        struct ce_msg_data ce_msg;
-        int rc;
-};
-
-static void get_rtc_time_complete(void *token, struct ce_msg_data *ce_msg)
-{
-        struct rtc_time_data *rtc = token;
-
-        memcpy(&rtc->ce_msg, ce_msg, sizeof(rtc->ce_msg));
-        rtc->rc = 0;
-        complete(&rtc->com);
-}
-
-static int mf_set_rtc(struct rtc_time *tm)
-{
-        char ce_time[12];
-        u8 day, mon, hour, min, sec, y1, y2;
-        unsigned year;
-
-        year = 1900 + tm->tm_year;
-        y1 = year / 100;
-        y2 = year % 100;
-
-        sec = tm->tm_sec;
-        min = tm->tm_min;
-        hour = tm->tm_hour;
-        day = tm->tm_mday;
-        mon = tm->tm_mon + 1;
-
-        sec = bin2bcd(sec);
-        min = bin2bcd(min);
-        hour = bin2bcd(hour);
-        mon = bin2bcd(mon);
-        day = bin2bcd(day);
-        y1 = bin2bcd(y1);
-        y2 = bin2bcd(y2);
-
-        memset(ce_time, 0, sizeof(ce_time));
-        ce_time[3] = 0x41;
-        ce_time[4] = y1;
-        ce_time[5] = y2;
-        ce_time[6] = sec;
-        ce_time[7] = min;
-        ce_time[8] = hour;
-        ce_time[10] = day;
-        ce_time[11] = mon;
-
-        return signal_ce_msg(ce_time, NULL);
-}
-
-static int rtc_set_tm(int rc, u8 *ce_msg, struct rtc_time *tm)
-{
-        tm->tm_wday = 0;
-        tm->tm_yday = 0;
-        tm->tm_isdst = 0;
-        if (rc) {
-                tm->tm_sec = 0;
-                tm->tm_min = 0;
-                tm->tm_hour = 0;
-                tm->tm_mday = 15;
-                tm->tm_mon = 5;
-                tm->tm_year = 52;
-                return rc;
-        }
-
-        if ((ce_msg[2] == 0xa9) ||
-            (ce_msg[2] == 0xaf)) {
-                /* TOD clock is not set */
-                tm->tm_sec = 1;
-                tm->tm_min = 1;
-                tm->tm_hour = 1;
-                tm->tm_mday = 10;
-                tm->tm_mon = 8;
-                tm->tm_year = 71;
-                mf_set_rtc(tm);
-        }
-        {
-                u8 year = ce_msg[5];
-                u8 sec = ce_msg[6];
-                u8 min = ce_msg[7];
-                u8 hour = ce_msg[8];
-                u8 day = ce_msg[10];
-                u8 mon = ce_msg[11];
-
-                sec = bcd2bin(sec);
-                min = bcd2bin(min);
-                hour = bcd2bin(hour);
-                day = bcd2bin(day);
-                mon = bcd2bin(mon);
-                year = bcd2bin(year);
-
-                if (year <= 69)
-                        year += 100;
-
-                tm->tm_sec = sec;
-                tm->tm_min = min;
-                tm->tm_hour = hour;
-                tm->tm_mday = day;
-                tm->tm_mon = mon;
-                tm->tm_year = year;
-        }
-
-        return 0;
-}
-
-static int mf_get_rtc(struct rtc_time *tm)
-{
-        struct ce_msg_comp_data ce_complete;
-        struct rtc_time_data rtc_data;
-        int rc;
-
-        memset(&ce_complete, 0, sizeof(ce_complete));
-        memset(&rtc_data, 0, sizeof(rtc_data));
-        init_completion(&rtc_data.com);
-        ce_complete.handler = &get_rtc_time_complete;
-        ce_complete.token = &rtc_data;
-        rc = signal_ce_msg_simple(0x40, &ce_complete);
-        if (rc)
-                return rc;
-        wait_for_completion(&rtc_data.com);
-        return rtc_set_tm(rtc_data.rc, rtc_data.ce_msg.ce_msg, tm);
-}
-
-struct boot_rtc_time_data {
-        int busy;
-        struct ce_msg_data ce_msg;
-        int rc;
-};
-
-static void get_boot_rtc_time_complete(void *token, struct ce_msg_data *ce_msg)
-{
-        struct boot_rtc_time_data *rtc = token;
-
-        memcpy(&rtc->ce_msg, ce_msg, sizeof(rtc->ce_msg));
-        rtc->rc = 0;
-        rtc->busy = 0;
-}
-
-static int mf_get_boot_rtc(struct rtc_time *tm)
-{
-        struct ce_msg_comp_data ce_complete;
-        struct boot_rtc_time_data rtc_data;
-        int rc;
-
-        memset(&ce_complete, 0, sizeof(ce_complete));
-        memset(&rtc_data, 0, sizeof(rtc_data));
-        rtc_data.busy = 1;
-        ce_complete.handler = &get_boot_rtc_time_complete;
-        ce_complete.token = &rtc_data;
-        rc = signal_ce_msg_simple(0x40, &ce_complete);
-        if (rc)
-                return rc;
-        /* We need to poll here as we are not yet taking interrupts */
-        while (rtc_data.busy) {
-                if (hvlpevent_is_pending())
-                        process_hvlpevents();
-        }
-        return rtc_set_tm(rtc_data.rc, rtc_data.ce_msg.ce_msg, tm);
-}
-
-#ifdef CONFIG_PROC_FS
-static int mf_cmdline_proc_show(struct seq_file *m, void *v)
-{
-        char *page, *p;
-        struct vsp_cmd_data vsp_cmd;
-        int rc;
-        dma_addr_t dma_addr;
-
-        /* The HV appears to return no more than 256 bytes of command line */
-        page = kmalloc(256, GFP_KERNEL);
-        if (!page)
-                return -ENOMEM;
-
-        dma_addr = iseries_hv_map(page, 256, DMA_FROM_DEVICE);
-        if (dma_addr == DMA_ERROR_CODE) {
-                kfree(page);
-                return -ENOMEM;
-        }
-        memset(page, 0, 256);
-        memset(&vsp_cmd, 0, sizeof(vsp_cmd));
-        vsp_cmd.cmd = 33;
-        vsp_cmd.sub_data.kern.token = dma_addr;
-        vsp_cmd.sub_data.kern.address_type = HvLpDma_AddressType_TceIndex;
-        vsp_cmd.sub_data.kern.side = (u64)m->private;
-        vsp_cmd.sub_data.kern.length = 256;
-        mb();
-        rc = signal_vsp_instruction(&vsp_cmd);
-        iseries_hv_unmap(dma_addr, 256, DMA_FROM_DEVICE);
-        if (rc) {
-                kfree(page);
-                return rc;
-        }
-        if (vsp_cmd.result_code != 0) {
-                kfree(page);
-                return -ENOMEM;
-        }
-        p = page;
-        while (p - page < 256) {
-                if (*p == '\0' || *p == '\n') {
-                        *p = '\n';
-                        break;
-                }
-                p++;
-
-        }
-        seq_write(m, page, p - page);
-        kfree(page);
-        return 0;
-}
-
-static int mf_cmdline_proc_open(struct inode *inode, struct file *file)
-{
-        return single_open(file, mf_cmdline_proc_show, PDE(inode)->data);
-}
-
-#if 0
-static int mf_getVmlinuxChunk(char *buffer, int *size, int offset, u64 side)
-{
-        struct vsp_cmd_data vsp_cmd;
-        int rc;
-        int len = *size;
-        dma_addr_t dma_addr;
-
-        dma_addr = iseries_hv_map(buffer, len, DMA_FROM_DEVICE);
-        memset(buffer, 0, len);
-        memset(&vsp_cmd, 0, sizeof(vsp_cmd));
-        vsp_cmd.cmd = 32;
-        vsp_cmd.sub_data.kern.token = dma_addr;
-        vsp_cmd.sub_data.kern.address_type = HvLpDma_AddressType_TceIndex;
-        vsp_cmd.sub_data.kern.side = side;
-        vsp_cmd.sub_data.kern.offset = offset;
-        vsp_cmd.sub_data.kern.length = len;
-        mb();
-        rc = signal_vsp_instruction(&vsp_cmd);
-        if (rc == 0) {
-                if (vsp_cmd.result_code == 0)
-                        *size = vsp_cmd.sub_data.length_out;
-                else
-                        rc = -ENOMEM;
-        }
-
-        iseries_hv_unmap(dma_addr, len, DMA_FROM_DEVICE);
-
-        return rc;
-}
-
-static int proc_mf_dump_vmlinux(char *page, char **start, off_t off,
-                int count, int *eof, void *data)
-{
-        int sizeToGet = count;
-
-        if (!capable(CAP_SYS_ADMIN))
-                return -EACCES;
-
-        if (mf_getVmlinuxChunk(page, &sizeToGet, off, (u64)data) == 0) {
-                if (sizeToGet != 0) {
-                        *start = page + off;
-                        return sizeToGet;
-                }
-                *eof = 1;
-                return 0;
-        }
-        *eof = 1;
-        return 0;
-}
-#endif
-
-static int mf_side_proc_show(struct seq_file *m, void *v)
-{
-        char mf_current_side = ' ';
-        struct vsp_cmd_data vsp_cmd;
-
-        memset(&vsp_cmd, 0, sizeof(vsp_cmd));
-        vsp_cmd.cmd = 2;
-        vsp_cmd.sub_data.ipl_type = 0;
-        mb();
-
-        if (signal_vsp_instruction(&vsp_cmd) == 0) {
-                if (vsp_cmd.result_code == 0) {
-                        switch (vsp_cmd.sub_data.ipl_type) {
-                        case 0: mf_current_side = 'A';
-                                break;
-                        case 1: mf_current_side = 'B';
-                                break;
-                        case 2: mf_current_side = 'C';
-                                break;
-                        default:        mf_current_side = 'D';
-                                break;
-                        }
-                }
-        }
-
-        seq_printf(m, "%c\n", mf_current_side);
-        return 0;
-}
-
-static int mf_side_proc_open(struct inode *inode, struct file *file)
-{
-        return single_open(file, mf_side_proc_show, NULL);
-}
-
-static ssize_t mf_side_proc_write(struct file *file, const char __user *buffer,
-                                  size_t count, loff_t *pos)
-{
-        char side;
-        u64 newSide;
-        struct vsp_cmd_data vsp_cmd;
-
-        if (!capable(CAP_SYS_ADMIN))
-                return -EACCES;
-
-        if (count == 0)
-                return 0;
-
-        if (get_user(side, buffer))
-                return -EFAULT;
-
-        switch (side) {
-        case 'A':       newSide = 0;
-                        break;
-        case 'B':       newSide = 1;
-                        break;
-        case 'C':       newSide = 2;
-                        break;
-        case 'D':       newSide = 3;
-                        break;
-        default:
-                printk(KERN_ERR "mf_proc.c: proc_mf_change_side: invalid side\n");
-                return -EINVAL;
-        }
-
-        memset(&vsp_cmd, 0, sizeof(vsp_cmd));
-        vsp_cmd.sub_data.ipl_type = newSide;
-        vsp_cmd.cmd = 10;
-
-        (void)signal_vsp_instruction(&vsp_cmd);
-
-        return count;
-}
-
-static const struct file_operations mf_side_proc_fops = {
-        .owner          = THIS_MODULE,
-        .open           = mf_side_proc_open,
-        .read           = seq_read,
-        .llseek         = seq_lseek,
-        .release        = single_release,
-        .write          = mf_side_proc_write,
-};
-
-static int mf_src_proc_show(struct seq_file *m, void *v)
-{
-        return 0;
-}
-
-static int mf_src_proc_open(struct inode *inode, struct file *file)
-{
-        return single_open(file, mf_src_proc_show, NULL);
-}
-
-static ssize_t mf_src_proc_write(struct file *file, const char __user *buffer,
-                                 size_t count, loff_t *pos)
-{
-        char stkbuf[10];
-
-        if (!capable(CAP_SYS_ADMIN))
-                return -EACCES;
-
-        if ((count < 4) && (count != 1)) {
-                printk(KERN_ERR "mf_proc: invalid src\n");
-                return -EINVAL;
-        }
-
-        if (count > (sizeof(stkbuf) - 1))
-                count = sizeof(stkbuf) - 1;
-        if (copy_from_user(stkbuf, buffer, count))
-                return -EFAULT;
-
-        if ((count == 1) && (*stkbuf == '\0'))
-                mf_clear_src();
-        else
-                mf_display_src(*(u32 *)stkbuf);
-
-        return count;
-}
-
-static const struct file_operations mf_src_proc_fops = {
-        .owner          = THIS_MODULE,
-        .open           = mf_src_proc_open,
-        .read           = seq_read,
-        .llseek         = seq_lseek,
-        .release        = single_release,
-        .write          = mf_src_proc_write,
-};
-
-static ssize_t mf_cmdline_proc_write(struct file *file, const char __user *buffer,
-                                     size_t count, loff_t *pos)
-{
-        void *data = PDE(file->f_path.dentry->d_inode)->data;
-        struct vsp_cmd_data vsp_cmd;
-        dma_addr_t dma_addr;
-        char *page;
-        int ret = -EACCES;
-
-        if (!capable(CAP_SYS_ADMIN))
-                goto out;
-
-        dma_addr = 0;
-        page = iseries_hv_alloc(count, &dma_addr, GFP_ATOMIC);
-        ret = -ENOMEM;
-        if (page == NULL)
-                goto out;
-
-        ret = -EFAULT;
-        if (copy_from_user(page, buffer, count))
-                goto out_free;
-
-        memset(&vsp_cmd, 0, sizeof(vsp_cmd));
-        vsp_cmd.cmd = 31;
-        vsp_cmd.sub_data.kern.token = dma_addr;
-        vsp_cmd.sub_data.kern.address_type = HvLpDma_AddressType_TceIndex;
-        vsp_cmd.sub_data.kern.side = (u64)data;
-        vsp_cmd.sub_data.kern.length = count;
-        mb();
-        (void)signal_vsp_instruction(&vsp_cmd);
-        ret = count;
-
-out_free:
-        iseries_hv_free(count, page, dma_addr);
-out:
-        return ret;
-}
-
-static const struct file_operations mf_cmdline_proc_fops = {
-        .owner          = THIS_MODULE,
-        .open           = mf_cmdline_proc_open,
-        .read           = seq_read,
-        .llseek         = seq_lseek,
-        .release        = single_release,
-        .write          = mf_cmdline_proc_write,
-};
-
-static ssize_t proc_mf_change_vmlinux(struct file *file,
-                                      const char __user *buf,
-                                      size_t count, loff_t *ppos)
-{
-        struct proc_dir_entry *dp = PDE(file->f_path.dentry->d_inode);
-        ssize_t rc;
-        dma_addr_t dma_addr;
-        char *page;
-        struct vsp_cmd_data vsp_cmd;
-
-        rc = -EACCES;
-        if (!capable(CAP_SYS_ADMIN))
-                goto out;
-
-        dma_addr = 0;
-        page = iseries_hv_alloc(count, &dma_addr, GFP_ATOMIC);
-        rc = -ENOMEM;
-        if (page == NULL) {
-                printk(KERN_ERR "mf.c: couldn't allocate memory to set vmlinux chunk\n");
-                goto out;
-        }
-        rc = -EFAULT;
-        if (copy_from_user(page, buf, count))
-                goto out_free;
-
-        memset(&vsp_cmd, 0, sizeof(vsp_cmd));
-        vsp_cmd.cmd = 30;
-        vsp_cmd.sub_data.kern.token = dma_addr;
-        vsp_cmd.sub_data.kern.address_type = HvLpDma_AddressType_TceIndex;
-        vsp_cmd.sub_data.kern.side = (u64)dp->data;
-        vsp_cmd.sub_data.kern.offset = *ppos;
-        vsp_cmd.sub_data.kern.length = count;
-        mb();
-        rc = signal_vsp_instruction(&vsp_cmd);
-        if (rc)
-                goto out_free;
-        rc = -ENOMEM;
-        if (vsp_cmd.result_code != 0)
-                goto out_free;
-
-        *ppos += count;
-        rc = count;
-out_free:
-        iseries_hv_free(count, page, dma_addr);
-out:
-        return rc;
-}
-
-static const struct file_operations proc_vmlinux_operations = {
-        .write          = proc_mf_change_vmlinux,
-        .llseek         = default_llseek,
-};
-
-static int __init mf_proc_init(void)
-{
-        struct proc_dir_entry *mf_proc_root;
-        struct proc_dir_entry *ent;
-        struct proc_dir_entry *mf;
-        char name[2];
-        int i;
-
-        if (!firmware_has_feature(FW_FEATURE_ISERIES))
-                return 0;
-
-        mf_proc_root = proc_mkdir("iSeries/mf", NULL);
-        if (!mf_proc_root)
-                return 1;
-
-        name[1] = '\0';
-        for (i = 0; i < 4; i++) {
-                name[0] = 'A' + i;
-                mf = proc_mkdir(name, mf_proc_root);
-                if (!mf)
-                        return 1;
-
-                ent = proc_create_data("cmdline", S_IRUSR|S_IWUSR, mf,
-                                       &mf_cmdline_proc_fops, (void *)(long)i);
-                if (!ent)
-                        return 1;
-
-                if (i == 3)     /* no vmlinux entry for 'D' */
-                        continue;
-
-                ent = proc_create_data("vmlinux", S_IFREG|S_IWUSR, mf,
-                                       &proc_vmlinux_operations,
-                                       (void *)(long)i);
-                if (!ent)
-                        return 1;
-        }
-
-        ent = proc_create("side", S_IFREG|S_IRUSR|S_IWUSR, mf_proc_root,
-                          &mf_side_proc_fops);
-        if (!ent)
-                return 1;
-
-        ent = proc_create("src", S_IFREG|S_IRUSR|S_IWUSR, mf_proc_root,
-                          &mf_src_proc_fops);
-        if (!ent)
-                return 1;
-
-        return 0;
-}
-
-__initcall(mf_proc_init);
-
-#endif /* CONFIG_PROC_FS */
-
-/*
- * Get the RTC from the virtual service processor
- * This requires flowing LpEvents to the primary partition
- */
-void iSeries_get_rtc_time(struct rtc_time *rtc_tm)
-{
-        mf_get_rtc(rtc_tm);
-        rtc_tm->tm_mon--;
-}
-
-/*
- * Set the RTC in the virtual service processor
- * This requires flowing LpEvents to the primary partition
- */
-int iSeries_set_rtc_time(struct rtc_time *tm)
-{
-        mf_set_rtc(tm);
-        return 0;
-}
-
-unsigned long iSeries_get_boot_time(void)
-{
-        struct rtc_time tm;
-
-        mf_get_boot_rtc(&tm);
-        return mktime(tm.tm_year + 1900, tm.tm_mon, tm.tm_mday,
-                      tm.tm_hour, tm.tm_min, tm.tm_sec);
-}
diff --git a/arch/powerpc/platforms/iseries/misc.S b/arch/powerpc/platforms/iseries/misc.S
deleted file mode 100644
index 2c6ff0fdac9..00000000000
--- a/arch/powerpc/platforms/iseries/misc.S
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * This file contains miscellaneous low-level functions.
- *    Copyright (C) 1995-2005 IBM Corp
- *
- * Largely rewritten by Cort Dougan (cort@cs.nmt.edu)
- * and Paul Mackerras.
- * Adapted for iSeries by Mike Corrigan (mikejc@us.ibm.com)
- * PPC64 updates by Dave Engebretsen (engebret@us.ibm.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#include <asm/processor.h>
-#include <asm/asm-offsets.h>
-#include <asm/ppc_asm.h>
-
-        .text
-
-/* Handle pending interrupts in interrupt context */
-_GLOBAL(iseries_handle_interrupts)
-        li      r0,0x5555
-        sc
-        blr
diff --git a/arch/powerpc/platforms/iseries/naca.h b/arch/powerpc/platforms/iseries/naca.h
deleted file mode 100644
index f01708e1286..00000000000
--- a/arch/powerpc/platforms/iseries/naca.h
+++ /dev/null
@@ -1,24 +0,0 @@
-#ifndef _PLATFORMS_ISERIES_NACA_H
-#define _PLATFORMS_ISERIES_NACA_H
-
-/*
- * c 2001 PPC 64 Team, IBM Corp
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#include <asm/types.h>
-
-struct naca_struct {
-        /* Kernel only data - undefined for user space */
-        const void *xItVpdAreas;        /* VPD Data                  0x00 */
-        void *xRamDisk;                 /* iSeries ramdisk           0x08 */
-        u64   xRamDiskSize;             /* In pages                  0x10 */
-};
-
-extern struct naca_struct naca;
-
-#endif /* _PLATFORMS_ISERIES_NACA_H */
diff --git a/arch/powerpc/platforms/iseries/pci.c b/arch/powerpc/platforms/iseries/pci.c
deleted file mode 100644
index c7541288462..00000000000
--- a/arch/powerpc/platforms/iseries/pci.c
+++ /dev/null
@@ -1,919 +0,0 @@
-/*
- * Copyright (C) 2001 Allan Trautman, IBM Corporation
- * Copyright (C) 2005,2007  Stephen Rothwell, IBM Corp
- *
- * iSeries specific routines for PCI.
- *
- * Based on code from pci.c and iSeries_pci.c 32bit
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
- */
-
-#undef DEBUG
-
-#include <linux/jiffies.h>
-#include <linux/kernel.h>
-#include <linux/list.h>
-#include <linux/string.h>
-#include <linux/slab.h>
-#include <linux/init.h>
-#include <linux/pci.h>
-#include <linux/of.h>
-#include <linux/ratelimit.h>
-
-#include <asm/types.h>
-#include <asm/io.h>
-#include <asm/irq.h>
-#include <asm/prom.h>
-#include <asm/machdep.h>
-#include <asm/pci-bridge.h>
-#include <asm/iommu.h>
-#include <asm/abs_addr.h>
-#include <asm/firmware.h>
-
-#include <asm/iseries/hv_types.h>
-#include <asm/iseries/hv_call_xm.h>
-#include <asm/iseries/mf.h>
-#include <asm/iseries/iommu.h>
-
-#include <asm/ppc-pci.h>
-
-#include "irq.h"
-#include "pci.h"
-#include "call_pci.h"
-
-#define PCI_RETRY_MAX   3
-static int limit_pci_retries = 1;       /* Set Retry Error on. */
-
-/*
- * Table defines
- * Each Entry size is 4 MB * 1024 Entries = 4GB I/O address space.
- */
-#define IOMM_TABLE_MAX_ENTRIES  1024
-#define IOMM_TABLE_ENTRY_SIZE   0x0000000000400000UL
-#define BASE_IO_MEMORY          0xE000000000000000UL
-#define END_IO_MEMORY           0xEFFFFFFFFFFFFFFFUL
-
-static unsigned long max_io_memory = BASE_IO_MEMORY;
-static long current_iomm_table_entry;
-
-/*
- * Lookup Tables.
- */
-static struct device_node *iomm_table[IOMM_TABLE_MAX_ENTRIES];
-static u64 ds_addr_table[IOMM_TABLE_MAX_ENTRIES];
-
-static DEFINE_SPINLOCK(iomm_table_lock);
-
-/*
- * Generate a Direct Select Address for the Hypervisor
- */
-static inline u64 iseries_ds_addr(struct device_node *node)
-{
-        struct pci_dn *pdn = PCI_DN(node);
-        const u32 *sbp = of_get_property(node, "linux,subbus", NULL);
-
-        return ((u64)pdn->busno << 48) + ((u64)(sbp ? *sbp : 0) << 40)
-                        + ((u64)0x10 << 32);
-}
-
-/*
- * Size of Bus VPD data
- */
-#define BUS_VPDSIZE      1024
-
-/*
- * Bus Vpd Tags
- */
-#define VPD_END_OF_AREA         0x79
-#define VPD_ID_STRING           0x82
-#define VPD_VENDOR_AREA         0x84
-
-/*
- * Mfg Area Tags
- */
-#define VPD_FRU_FRAME_ID        0x4649  /* "FI" */
-#define VPD_SLOT_MAP_FORMAT     0x4D46  /* "MF" */
-#define VPD_SLOT_MAP            0x534D  /* "SM" */
-
-/*
- * Structures of the areas
- */
-struct mfg_vpd_area {
-        u16     tag;
-        u8      length;
-        u8      data1;
-        u8      data2;
-};
-#define MFG_ENTRY_SIZE   3
-
-struct slot_map {
-        u8      agent;
-        u8      secondary_agent;
-        u8      phb;
-        char    card_location[3];
-        char    parms[8];
-        char    reserved[2];
-};
-#define SLOT_ENTRY_SIZE   16
-
-/*
- * Parse the Slot Area
- */
-static void __init iseries_parse_slot_area(struct slot_map *map, int len,
-                HvAgentId agent, u8 *phb, char card[4])
-{
-        /*
-         * Parse Slot label until we find the one requested
-         */
-        while (len > 0) {
-                if (map->agent == agent) {
-                        /*
-                         * If Phb wasn't found, grab the entry first one found.
-                         */
-                        if (*phb == 0xff)
-                                *phb = map->phb;
-                        /* Found it, extract the data. */
-                        if (map->phb == *phb) {
-                                memcpy(card, &map->card_location, 3);
-                                card[3]  = 0;
-                                break;
-                        }
-                }
-                /* Point to the next Slot */
-                map = (struct slot_map *)((char *)map + SLOT_ENTRY_SIZE);
-                len -= SLOT_ENTRY_SIZE;
-        }
-}
-
-/*
- * Parse the Mfg Area
- */
-static void __init iseries_parse_mfg_area(struct mfg_vpd_area *area, int len,
-                HvAgentId agent, u8 *phb, u8 *frame, char card[4])
-{
-        u16 slot_map_fmt = 0;
-
-        /* Parse Mfg Data */
-        while (len > 0) {
-                int mfg_tag_len = area->length;
-                /* Frame ID         (FI 4649020310 ) */
-                if (area->tag == VPD_FRU_FRAME_ID)
-                        *frame = area->data1;
-                /* Slot Map Format  (MF 4D46020004 ) */
-                else if (area->tag == VPD_SLOT_MAP_FORMAT)
-                        slot_map_fmt = (area->data1 * 256)
-                                + area->data2;
-                /* Slot Map         (SM 534D90 */
-                else if (area->tag == VPD_SLOT_MAP) {
-                        struct slot_map *slot_map;
-
-                        if (slot_map_fmt == 0x1004)
-                                slot_map = (struct slot_map *)((char *)area
-                                                + MFG_ENTRY_SIZE + 1);
-                        else
-                                slot_map = (struct slot_map *)((char *)area
-                                                + MFG_ENTRY_SIZE);
-                        iseries_parse_slot_area(slot_map, mfg_tag_len,
-                                        agent, phb, card);
-                }
-                /*
-                 * Point to the next Mfg Area
-                 * Use defined size, sizeof give wrong answer
-                 */
-                area = (struct mfg_vpd_area *)((char *)area + mfg_tag_len
-                                + MFG_ENTRY_SIZE);
-                len -= (mfg_tag_len + MFG_ENTRY_SIZE);
-        }
-}
-
-/*
- * Look for "BUS".. Data is not Null terminated.
- * PHBID of 0xFF indicates PHB was not found in VPD Data.
- */
-static u8 __init iseries_parse_phbid(u8 *area, int len)
-{
-        while (len > 0) {
-                if ((*area == 'B') && (*(area + 1) == 'U')
-                                && (*(area + 2) == 'S')) {
-                        area += 3;
-                        while (*area == ' ')
-                                area++;
-                        return *area & 0x0F;
-                }
-                area++;
-                len--;
-        }
-        return 0xff;
-}
-
-/*
- * Parse out the VPD Areas
- */
-static void __init iseries_parse_vpd(u8 *data, int data_len,
-                HvAgentId agent, u8 *frame, char card[4])
-{
-        u8 phb = 0xff;
-
-        while (data_len > 0) {
-                int len;
-                u8 tag = *data;
-
-                if (tag == VPD_END_OF_AREA)
-                        break;
-                len = *(data + 1) + (*(data + 2) * 256);
-                data += 3;
-                data_len -= 3;
-                if (tag == VPD_ID_STRING)
-                        phb = iseries_parse_phbid(data, len);
-                else if (tag == VPD_VENDOR_AREA)
-                        iseries_parse_mfg_area((struct mfg_vpd_area *)data, len,
-                                        agent, &phb, frame, card);
-                /* Point to next Area. */
-                data += len;
-                data_len -= len;
-        }
-}
-
-static int __init iseries_get_location_code(u16 bus, HvAgentId agent,
-                u8 *frame, char card[4])
-{
-        int status = 0;
-        int bus_vpd_len = 0;
-        u8 *bus_vpd = kmalloc(BUS_VPDSIZE, GFP_KERNEL);
-
-        if (bus_vpd == NULL) {
-                printk("PCI: Bus VPD Buffer allocation failure.\n");
-                return 0;
-        }
-        bus_vpd_len = HvCallPci_getBusVpd(bus, iseries_hv_addr(bus_vpd),
-                                        BUS_VPDSIZE);
-        if (bus_vpd_len == 0) {
-                printk("PCI: Bus VPD Buffer zero length.\n");
-                goto out_free;
-        }
-        /* printk("PCI: bus_vpd: %p, %d\n",bus_vpd, bus_vpd_len); */
-        /* Make sure this is what I think it is */
-        if (*bus_vpd != VPD_ID_STRING) {
-                printk("PCI: Bus VPD Buffer missing starting tag.\n");
-                goto out_free;
-        }
-        iseries_parse_vpd(bus_vpd, bus_vpd_len, agent, frame, card);
-        status = 1;
-out_free:
-        kfree(bus_vpd);
-        return status;
-}
-
-/*
- * Prints the device information.
- * - Pass in pci_dev* pointer to the device.
- * - Pass in the device count
- *
- * Format:
- * PCI: Bus  0, Device 26, Vendor 0x12AE  Frame  1, Card  C10  Ethernet
- * controller
- */
-static void __init iseries_device_information(struct pci_dev *pdev,
-                                              u16 bus, HvSubBusNumber subbus)
-{
-        u8 frame = 0;
-        char card[4];
-        HvAgentId agent;
-
-        agent = ISERIES_PCI_AGENTID(ISERIES_GET_DEVICE_FROM_SUBBUS(subbus),
-                        ISERIES_GET_FUNCTION_FROM_SUBBUS(subbus));
-
-        if (iseries_get_location_code(bus, agent, &frame, card)) {
-                printk(KERN_INFO "PCI: %s, Vendor %04X Frame%3d, "
-                       "Card %4s  0x%04X\n", pci_name(pdev), pdev->vendor,
-                       frame, card, (int)(pdev->class >> 8));
-        }
-}
-
-/*
- * iomm_table_allocate_entry
- *
- * Adds pci_dev entry in address translation table
- *
- * - Allocates the number of entries required in table base on BAR
- *   size.
- * - Allocates starting at BASE_IO_MEMORY and increases.
- * - The size is round up to be a multiple of entry size.
- * - CurrentIndex is incremented to keep track of the last entry.
- * - Builds the resource entry for allocated BARs.
- */
-static void __init iomm_table_allocate_entry(struct pci_dev *dev, int bar_num)
-{
-        struct resource *bar_res = &dev->resource[bar_num];
-        long bar_size = pci_resource_len(dev, bar_num);
-        struct device_node *dn = pci_device_to_OF_node(dev);
-
-        /*
-         * No space to allocate, quick exit, skip Allocation.
-         */
-        if (bar_size == 0)
-                return;
-        /*
-         * Set Resource values.
-         */
-        spin_lock(&iomm_table_lock);
-        bar_res->start = BASE_IO_MEMORY +
-                IOMM_TABLE_ENTRY_SIZE * current_iomm_table_entry;
-        bar_res->end = bar_res->start + bar_size - 1;
-        /*
-         * Allocate the number of table entries needed for BAR.
-         */
-        while (bar_size > 0 ) {
-                iomm_table[current_iomm_table_entry] = dn;
-                ds_addr_table[current_iomm_table_entry] =
-                        iseries_ds_addr(dn) | (bar_num << 24);
-                bar_size -= IOMM_TABLE_ENTRY_SIZE;
-                ++current_iomm_table_entry;
-        }
-        max_io_memory = BASE_IO_MEMORY +
-                IOMM_TABLE_ENTRY_SIZE * current_iomm_table_entry;
-        spin_unlock(&iomm_table_lock);
-}
-
-/*
- * allocate_device_bars
- *
- * - Allocates ALL pci_dev BAR's and updates the resources with the
- *   BAR value.  BARS with zero length will have the resources
- *   The HvCallPci_getBarParms is used to get the size of the BAR
- *   space.  It calls iomm_table_allocate_entry to allocate
- *   each entry.
- * - Loops through The Bar resources(0 - 5) including the ROM
- *   is resource(6).
- */
-static void __init allocate_device_bars(struct pci_dev *dev)
-{
-        int bar_num;
-
-        for (bar_num = 0; bar_num <= PCI_ROM_RESOURCE; ++bar_num)
-                iomm_table_allocate_entry(dev, bar_num);
-}
-
-/*
- * Log error information to system console.
- * Filter out the device not there errors.
- * PCI: EADs Connect Failed 0x18.58.10 Rc: 0x00xx
- * PCI: Read Vendor Failed 0x18.58.10 Rc: 0x00xx
- * PCI: Connect Bus Unit Failed 0x18.58.10 Rc: 0x00xx
- */
-static void pci_log_error(char *error, int bus, int subbus,
-                int agent, int hv_res)
-{
-        if (hv_res == 0x0302)
-                return;
-        printk(KERN_ERR "PCI: %s Failed: 0x%02X.%02X.%02X Rc: 0x%04X",
-               error, bus, subbus, agent, hv_res);
-}
-
-/*
- * Look down the chain to find the matching Device Device
- */
-static struct device_node *find_device_node(int bus, int devfn)
-{
-        struct device_node *node;
-
-        for (node = NULL; (node = of_find_all_nodes(node)); ) {
-                struct pci_dn *pdn = PCI_DN(node);
-
-                if (pdn && (bus == pdn->busno) && (devfn == pdn->devfn))
-                        return node;
-        }
-        return NULL;
-}
-
-/*
- * iSeries_pcibios_fixup_resources
- *
- * Fixes up all resources for devices
- */
-void __init iSeries_pcibios_fixup_resources(struct pci_dev *pdev)
-{
-        const u32 *agent;
-        const u32 *sub_bus;
-        unsigned char bus = pdev->bus->number;
-        struct device_node *node;
-        int i;
-
-        node = pci_device_to_OF_node(pdev);
-        pr_debug("PCI: iSeries %s, pdev %p, node %p\n",
-                 pci_name(pdev), pdev, node);
-        if (!node) {
-                printk("PCI: %s disabled, device tree entry not found !\n",
-                       pci_name(pdev));
-                for (i = 0; i <= PCI_ROM_RESOURCE; i++)
-                        pdev->resource[i].flags = 0;
-                return;
-        }
-        sub_bus = of_get_property(node, "linux,subbus", NULL);
-        agent = of_get_property(node, "linux,agent-id", NULL);
-        if (agent && sub_bus) {
-                u8 irq = iSeries_allocate_IRQ(bus, 0, *sub_bus);
-                int err;
-
-                err = HvCallXm_connectBusUnit(bus, *sub_bus, *agent, irq);
-                if (err)
-                        pci_log_error("Connect Bus Unit",
-                                      bus, *sub_bus, *agent, err);
-                else {
-                        err = HvCallPci_configStore8(bus, *sub_bus,
-                                        *agent, PCI_INTERRUPT_LINE, irq);
-                        if (err)
-                                pci_log_error("PciCfgStore Irq Failed!",
-                                                bus, *sub_bus, *agent, err);
-                        else
-                                pdev->irq = irq;
-                }
-        }
-
-        allocate_device_bars(pdev);
-        if (likely(sub_bus))
-                iseries_device_information(pdev, bus, *sub_bus);
-        else
-                printk(KERN_ERR "PCI: Device node %s has missing or invalid "
-                                "linux,subbus property\n", node->full_name);
-}
-
-/*
- * iSeries_pci_final_fixup(void)
- */
-void __init iSeries_pci_final_fixup(void)
-{
-        /* Fix up at the device node and pci_dev relationship */
-        mf_display_src(0xC9000100);
-        iSeries_activate_IRQs();
-        mf_display_src(0xC9000200);
-}
-
-/*
- * Config space read and write functions.
- * For now at least, we look for the device node for the bus and devfn
- * that we are asked to access.  It may be possible to translate the devfn
- * to a subbus and deviceid more directly.
- */
-static u64 hv_cfg_read_func[4]  = {
-        HvCallPciConfigLoad8, HvCallPciConfigLoad16,
-        HvCallPciConfigLoad32, HvCallPciConfigLoad32
-};
-
-static u64 hv_cfg_write_func[4] = {
-        HvCallPciConfigStore8, HvCallPciConfigStore16,
-        HvCallPciConfigStore32, HvCallPciConfigStore32
-};
-
-/*
- * Read PCI config space
- */
-static int iSeries_pci_read_config(struct pci_bus *bus, unsigned int devfn,
-                int offset, int size, u32 *val)
-{
-        struct device_node *node = find_device_node(bus->number, devfn);
-        u64 fn;
-        struct HvCallPci_LoadReturn ret;
-
-        if (node == NULL)
-                return PCIBIOS_DEVICE_NOT_FOUND;
-        if (offset > 255) {
-                *val = ~0;
-                return PCIBIOS_BAD_REGISTER_NUMBER;
-        }
-
-        fn = hv_cfg_read_func[(size - 1) & 3];
-        HvCall3Ret16(fn, &ret, iseries_ds_addr(node), offset, 0);
-
-        if (ret.rc != 0) {
-                *val = ~0;
-                return PCIBIOS_DEVICE_NOT_FOUND;        /* or something */
-        }
-
-        *val = ret.value;
-        return 0;
-}
-
-/*
- * Write PCI config space
- */
-
-static int iSeries_pci_write_config(struct pci_bus *bus, unsigned int devfn,
-                int offset, int size, u32 val)
-{
-        struct device_node *node = find_device_node(bus->number, devfn);
-        u64 fn;
-        u64 ret;
-
-        if (node == NULL)
-                return PCIBIOS_DEVICE_NOT_FOUND;
-        if (offset > 255)
-                return PCIBIOS_BAD_REGISTER_NUMBER;
-
-        fn = hv_cfg_write_func[(size - 1) & 3];
-        ret = HvCall4(fn, iseries_ds_addr(node), offset, val, 0);
-
-        if (ret != 0)
-                return PCIBIOS_DEVICE_NOT_FOUND;
-
-        return 0;
-}
-
-static struct pci_ops iSeries_pci_ops = {
-        .read = iSeries_pci_read_config,
-        .write = iSeries_pci_write_config
-};
-
-/*
- * Check Return Code
- * -> On Failure, print and log information.
- *    Increment Retry Count, if exceeds max, panic partition.
- *
- * PCI: Device 23.90 ReadL I/O Error( 0): 0x1234
- * PCI: Device 23.90 ReadL Retry( 1)
- * PCI: Device 23.90 ReadL Retry Successful(1)
- */
-static int check_return_code(char *type, struct device_node *dn,
-                int *retry, u64 ret)
-{
-        if (ret != 0)  {
-                struct pci_dn *pdn = PCI_DN(dn);
-
-                (*retry)++;
-                printk("PCI: %s: Device 0x%04X:%02X  I/O Error(%2d): 0x%04X\n",
-                                type, pdn->busno, pdn->devfn,
-                                *retry, (int)ret);
-                /*
-                 * Bump the retry and check for retry count exceeded.
-                 * If, Exceeded, panic the system.
-                 */
-                if (((*retry) > PCI_RETRY_MAX) &&
-                                (limit_pci_retries > 0)) {
-                        mf_display_src(0xB6000103);
-                        panic_timeout = 0;
-                        panic("PCI: Hardware I/O Error, SRC B6000103, "
-                                        "Automatic Reboot Disabled.\n");
-                }
-                return -1;      /* Retry Try */
-        }
-        return 0;
-}
-
-/*
- * Translate the I/O Address into a device node, bar, and bar offset.
- * Note: Make sure the passed variable end up on the stack to avoid
- * the exposure of being device global.
- */
-static inline struct device_node *xlate_iomm_address(
-                const volatile void __iomem *addr,
-                u64 *dsaptr, u64 *bar_offset, const char *func)
-{
-        unsigned long orig_addr;
-        unsigned long base_addr;
-        unsigned long ind;
-        struct device_node *dn;
-
-        orig_addr = (unsigned long __force)addr;
-        if ((orig_addr < BASE_IO_MEMORY) || (orig_addr >= max_io_memory)) {
-                static DEFINE_RATELIMIT_STATE(ratelimit, 60 * HZ, 10);
-
-                if (__ratelimit(&ratelimit))
-                        printk(KERN_ERR
-                                "iSeries_%s: invalid access at IO address %p\n",
-                                func, addr);
-                return NULL;
-        }
-        base_addr = orig_addr - BASE_IO_MEMORY;
-        ind = base_addr / IOMM_TABLE_ENTRY_SIZE;
-        dn = iomm_table[ind];
-
-        if (dn != NULL) {
-                *dsaptr = ds_addr_table[ind];
-                *bar_offset = base_addr % IOMM_TABLE_ENTRY_SIZE;
-        } else
-                panic("PCI: Invalid PCI IO address detected!\n");
-        return dn;
-}
-
-/*
- * Read MM I/O Instructions for the iSeries
- * On MM I/O error, all ones are returned and iSeries_pci_IoError is cal
- * else, data is returned in Big Endian format.
- */
-static u8 iseries_readb(const volatile void __iomem *addr)
-{
-        u64 bar_offset;
-        u64 dsa;
-        int retry = 0;
-        struct HvCallPci_LoadReturn ret;
-        struct device_node *dn =
-                xlate_iomm_address(addr, &dsa, &bar_offset, "read_byte");
-
-        if (dn == NULL)
-                return 0xff;
-        do {
-                HvCall3Ret16(HvCallPciBarLoad8, &ret, dsa, bar_offset, 0);
-        } while (check_return_code("RDB", dn, &retry, ret.rc) != 0);
-
-        return ret.value;
-}
-
-static u16 iseries_readw_be(const volatile void __iomem *addr)
-{
-        u64 bar_offset;
-        u64 dsa;
-        int retry = 0;
-        struct HvCallPci_LoadReturn ret;
-        struct device_node *dn =
-                xlate_iomm_address(addr, &dsa, &bar_offset, "read_word");
-
-        if (dn == NULL)
-                return 0xffff;
-        do {
-                HvCall3Ret16(HvCallPciBarLoad16, &ret, dsa,
-                                bar_offset, 0);
-        } while (check_return_code("RDW", dn, &retry, ret.rc) != 0);
-
-        return ret.value;
-}
-
-static u32 iseries_readl_be(const volatile void __iomem *addr)
-{
-        u64 bar_offset;
-        u64 dsa;
-        int retry = 0;
-        struct HvCallPci_LoadReturn ret;
-        struct device_node *dn =
-                xlate_iomm_address(addr, &dsa, &bar_offset, "read_long");
-
-        if (dn == NULL)
-                return 0xffffffff;
-        do {
-                HvCall3Ret16(HvCallPciBarLoad32, &ret, dsa,
-                                bar_offset, 0);
-        } while (check_return_code("RDL", dn, &retry, ret.rc) != 0);
-
-        return ret.value;
-}
-
-/*
- * Write MM I/O Instructions for the iSeries
- *
- */
-static void iseries_writeb(u8 data, volatile void __iomem *addr)
-{
-        u64 bar_offset;
-        u64 dsa;
-        int retry = 0;
-        u64 rc;
-        struct device_node *dn =
-                xlate_iomm_address(addr, &dsa, &bar_offset, "write_byte");
-
-        if (dn == NULL)
-                return;
-        do {
-                rc = HvCall4(HvCallPciBarStore8, dsa, bar_offset, data, 0);
-        } while (check_return_code("WWB", dn, &retry, rc) != 0);
-}
-
-static void iseries_writew_be(u16 data, volatile void __iomem *addr)
-{
-        u64 bar_offset;
-        u64 dsa;
-        int retry = 0;
-        u64 rc;
-        struct device_node *dn =
-                xlate_iomm_address(addr, &dsa, &bar_offset, "write_word");
-
-        if (dn == NULL)
-                return;
-        do {
-                rc = HvCall4(HvCallPciBarStore16, dsa, bar_offset, data, 0);
-        } while (check_return_code("WWW", dn, &retry, rc) != 0);
-}
-
-static void iseries_writel_be(u32 data, volatile void __iomem *addr)
-{
-        u64 bar_offset;
-        u64 dsa;
-        int retry = 0;
-        u64 rc;
-        struct device_node *dn =
-                xlate_iomm_address(addr, &dsa, &bar_offset, "write_long");
-
-        if (dn == NULL)
-                return;
-        do {
-                rc = HvCall4(HvCallPciBarStore32, dsa, bar_offset, data, 0);
-        } while (check_return_code("WWL", dn, &retry, rc) != 0);
-}
-
-static u16 iseries_readw(const volatile void __iomem *addr)
-{
-        return le16_to_cpu(iseries_readw_be(addr));
-}
-
-static u32 iseries_readl(const volatile void __iomem *addr)
-{
-        return le32_to_cpu(iseries_readl_be(addr));
-}
-
-static void iseries_writew(u16 data, volatile void __iomem *addr)
-{
-        iseries_writew_be(cpu_to_le16(data), addr);
-}
-
-static void iseries_writel(u32 data, volatile void __iomem *addr)
-{
-        iseries_writel(cpu_to_le32(data), addr);
-}
-
-static void iseries_readsb(const volatile void __iomem *addr, void *buf,
-                           unsigned long count)
-{
-        u8 *dst = buf;
-        while(count-- > 0)
-                *(dst++) = iseries_readb(addr);
-}
-
-static void iseries_readsw(const volatile void __iomem *addr, void *buf,
-                           unsigned long count)
-{
-        u16 *dst = buf;
-        while(count-- > 0)
-                *(dst++) = iseries_readw_be(addr);
-}
-
-static void iseries_readsl(const volatile void __iomem *addr, void *buf,
-                           unsigned long count)
-{
-        u32 *dst = buf;
-        while(count-- > 0)
-                *(dst++) = iseries_readl_be(addr);
-}
-
-static void iseries_writesb(volatile void __iomem *addr, const void *buf,
-                            unsigned long count)
-{
-        const u8 *src = buf;
-        while(count-- > 0)
-                iseries_writeb(*(src++), addr);
-}
-
-static void iseries_writesw(volatile void __iomem *addr, const void *buf,
-                            unsigned long count)
-{
-        const u16 *src = buf;
-        while(count-- > 0)
-                iseries_writew_be(*(src++), addr);
-}
-
-static void iseries_writesl(volatile void __iomem *addr, const void *buf,
-                            unsigned long count)
-{
-        const u32 *src = buf;
-        while(count-- > 0)
-                iseries_writel_be(*(src++), addr);
-}
-
-static void iseries_memset_io(volatile void __iomem *addr, int c,
-                              unsigned long n)
-{
-        volatile char __iomem *d = addr;
-
-        while (n-- > 0)
-                iseries_writeb(c, d++);
-}
-
-static void iseries_memcpy_fromio(void *dest, const volatile void __iomem *src,
-                                  unsigned long n)
-{
-        char *d = dest;
-        const volatile char __iomem *s = src;
-
-        while (n-- > 0)
-                *d++ = iseries_readb(s++);
-}
-
-static void iseries_memcpy_toio(volatile void __iomem *dest, const void *src,
-                                unsigned long n)
-{
-        const char *s = src;
-        volatile char __iomem *d = dest;
-
-        while (n-- > 0)
-                iseries_writeb(*s++, d++);
-}
-
-/* We only set MMIO ops. The default PIO ops will be default
- * to the MMIO ops + pci_io_base which is 0 on iSeries as
- * expected so both should work.
- *
- * Note that we don't implement the readq/writeq versions as
- * I don't know of an HV call for doing so. Thus, the default
- * operation will be used instead, which will fault a the value
- * return by iSeries for MMIO addresses always hits a non mapped
- * area. This is as good as the BUG() we used to have there.
- */
-static struct ppc_pci_io __initdata iseries_pci_io = {
-        .readb = iseries_readb,
-        .readw = iseries_readw,
-        .readl = iseries_readl,
-        .readw_be = iseries_readw_be,
-        .readl_be = iseries_readl_be,
-        .writeb = iseries_writeb,
-        .writew = iseries_writew,
-        .writel = iseries_writel,
-        .writew_be = iseries_writew_be,
-        .writel_be = iseries_writel_be,
-        .readsb = iseries_readsb,
-        .readsw = iseries_readsw,
-        .readsl = iseries_readsl,
-        .writesb = iseries_writesb,
-        .writesw = iseries_writesw,
-        .writesl = iseries_writesl,
-        .memset_io = iseries_memset_io,
-        .memcpy_fromio = iseries_memcpy_fromio,
-        .memcpy_toio = iseries_memcpy_toio,
-};
-
-/*
- * iSeries_pcibios_init
- *
- * Description:
- *   This function checks for all possible system PCI host bridges that connect
- *   PCI buses.  The system hypervisor is queried as to the guest partition
- *   ownership status.  A pci_controller is built for any bus which is partially
- *   owned or fully owned by this guest partition.
- */
-void __init iSeries_pcibios_init(void)
-{
-        struct pci_controller *phb;
-        struct device_node *root = of_find_node_by_path("/");
-        struct device_node *node = NULL;
-
-        /* Install IO hooks */
-        ppc_pci_io = iseries_pci_io;
-
-        pci_probe_only = 1;
-
-        /* iSeries has no IO space in the common sense, it needs to set
-         * the IO base to 0
-         */
-        pci_io_base = 0;
-
-        if (root == NULL) {
-                printk(KERN_CRIT "iSeries_pcibios_init: can't find root "
-                                "of device tree\n");
-                return;
-        }
-        while ((node = of_get_next_child(root, node)) != NULL) {
-                HvBusNumber bus;
-                const u32 *busp;
-
-                if ((node->type == NULL) || (strcmp(node->type, "pci") != 0))
-                        continue;
-
-                busp = of_get_property(node, "bus-range", NULL);
-                if (busp == NULL)
-                        continue;
-                bus = *busp;
-                printk("bus %d appears to exist\n", bus);
-                phb = pcibios_alloc_controller(node);
-                if (phb == NULL)
-                        continue;
-                /* All legacy iSeries PHBs are in domain zero */
-                phb->global_number = 0;
-
-                phb->first_busno = bus;
-                phb->last_busno = bus;
-                phb->ops = &iSeries_pci_ops;
-                phb->io_base_virt = (void __iomem *)_IO_BASE;
-                phb->io_resource.flags = IORESOURCE_IO;
-                phb->io_resource.start = BASE_IO_MEMORY;
-                phb->io_resource.end = END_IO_MEMORY;
-                phb->io_resource.name = "iSeries PCI IO";
-                phb->mem_resources[0].flags = IORESOURCE_MEM;
-                phb->mem_resources[0].start = BASE_IO_MEMORY;
-                phb->mem_resources[0].end = END_IO_MEMORY;
-                phb->mem_resources[0].name = "Series PCI MEM";
-        }
-
-        of_node_put(root);
-
-        pci_devs_phb_init();
-}
-
diff --git a/arch/powerpc/platforms/iseries/pci.h b/arch/powerpc/platforms/iseries/pci.h
deleted file mode 100644
index d9cf974c271..00000000000
--- a/arch/powerpc/platforms/iseries/pci.h
+++ /dev/null
@@ -1,58 +0,0 @@
-#ifndef _PLATFORMS_ISERIES_PCI_H
-#define _PLATFORMS_ISERIES_PCI_H
-
-/*
- * Created by Allan Trautman on Tue Feb 20, 2001.
- *
- * Define some useful macros for the iSeries pci routines.
- * Copyright (C) 2001  Allan H Trautman, IBM Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the:
- * Free Software Foundation, Inc.,
- * 59 Temple Place, Suite 330,
- * Boston, MA  02111-1307  USA
- *
- * Change Activity:
- *   Created Feb 20, 2001
- *   Added device reset, March 22, 2001
- *   Ported to ppc64, May 25, 2001
- * End Change Activity
- */
-
-/*
- * Decodes Linux DevFn to iSeries DevFn, bridge device, or function.
- * For Linux, see PCI_SLOT and PCI_FUNC in include/linux/pci.h
- */
-
-#define ISERIES_PCI_AGENTID(idsel, func)        \
-        (((idsel & 0x0F) << 4) | (func & 0x07))
-#define ISERIES_ENCODE_DEVICE(agentid)          \
-        ((0x10) | ((agentid & 0x20) >> 2) | (agentid & 0x07))
-
-#define ISERIES_GET_DEVICE_FROM_SUBBUS(subbus)          ((subbus >> 5) & 0x7)
-#define ISERIES_GET_FUNCTION_FROM_SUBBUS(subbus)        ((subbus >> 2) & 0x7)
-
-struct pci_dev;
-
-#ifdef CONFIG_PCI
-extern void     iSeries_pcibios_init(void);
-extern void     iSeries_pci_final_fixup(void);
-extern void     iSeries_pcibios_fixup_resources(struct pci_dev *dev);
-#else
-static inline void      iSeries_pcibios_init(void) { }
-static inline void      iSeries_pci_final_fixup(void) { }
-static inline void      iSeries_pcibios_fixup_resources(struct pci_dev *dev) {}
-#endif
-
-#endif /* _PLATFORMS_ISERIES_PCI_H */
diff --git a/arch/powerpc/platforms/iseries/proc.c b/arch/powerpc/platforms/iseries/proc.c
deleted file mode 100644
index 06763682db4..00000000000
--- a/arch/powerpc/platforms/iseries/proc.c
+++ /dev/null
@@ -1,120 +0,0 @@
-/*
- * Copyright (C) 2001  Kyle A. Lucke IBM Corporation
- * Copyright (C) 2001 Mike Corrigan & Dave Engebretsen IBM Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
- */
-#include <linux/init.h>
-#include <linux/proc_fs.h>
-#include <linux/seq_file.h>
-#include <linux/param.h>                /* for HZ */
-#include <asm/paca.h>
-#include <asm/processor.h>
-#include <asm/time.h>
-#include <asm/lppaca.h>
-#include <asm/firmware.h>
-#include <asm/iseries/hv_call_xm.h>
-
-#include "processor_vpd.h"
-#include "main_store.h"
-
-static int __init iseries_proc_create(void)
-{
-        struct proc_dir_entry *e;
-
-        if (!firmware_has_feature(FW_FEATURE_ISERIES))
-                return 0;
-
-        e = proc_mkdir("iSeries", 0);
-        if (!e)
-                return 1;
-
-        return 0;
-}
-core_initcall(iseries_proc_create);
-
-static unsigned long startTitan = 0;
-static unsigned long startTb = 0;
-
-static int proc_titantod_show(struct seq_file *m, void *v)
-{
-        unsigned long tb0, titan_tod;
-
-        tb0 = get_tb();
-        titan_tod = HvCallXm_loadTod();
-
-        seq_printf(m, "Titan\n" );
-        seq_printf(m, "  time base =          %016lx\n", tb0);
-        seq_printf(m, "  titan tod =          %016lx\n", titan_tod);
-        seq_printf(m, "  xProcFreq =          %016x\n",
-                   xIoHriProcessorVpd[0].xProcFreq);
-        seq_printf(m, "  xTimeBaseFreq =      %016x\n",
-                   xIoHriProcessorVpd[0].xTimeBaseFreq);
-        seq_printf(m, "  tb_ticks_per_jiffy = %lu\n", tb_ticks_per_jiffy);
-        seq_printf(m, "  tb_ticks_per_usec  = %lu\n", tb_ticks_per_usec);
-
-        if (!startTitan) {
-                startTitan = titan_tod;
-                startTb = tb0;
-        } else {
-                unsigned long titan_usec = (titan_tod - startTitan) >> 12;
-                unsigned long tb_ticks = (tb0 - startTb);
-                unsigned long titan_jiffies = titan_usec / (1000000/HZ);
-                unsigned long titan_jiff_usec = titan_jiffies * (1000000/HZ);
-                unsigned long titan_jiff_rem_usec =
-                        titan_usec - titan_jiff_usec;
-                unsigned long tb_jiffies = tb_ticks / tb_ticks_per_jiffy;
-                unsigned long tb_jiff_ticks = tb_jiffies * tb_ticks_per_jiffy;
-                unsigned long tb_jiff_rem_ticks = tb_ticks - tb_jiff_ticks;
-                unsigned long tb_jiff_rem_usec =
-                        tb_jiff_rem_ticks / tb_ticks_per_usec;
-                unsigned long new_tb_ticks_per_jiffy =
-                        (tb_ticks * (1000000/HZ))/titan_usec;
-
-                seq_printf(m, "  titan elapsed = %lu uSec\n", titan_usec);
-                seq_printf(m, "  tb elapsed    = %lu ticks\n", tb_ticks);
-                seq_printf(m, "  titan jiffies = %lu.%04lu\n", titan_jiffies,
-                           titan_jiff_rem_usec);
-                seq_printf(m, "  tb jiffies    = %lu.%04lu\n", tb_jiffies,
-                           tb_jiff_rem_usec);
-                seq_printf(m, "  new tb_ticks_per_jiffy = %lu\n",
-                           new_tb_ticks_per_jiffy);
-        }
-
-        return 0;
-}
-
-static int proc_titantod_open(struct inode *inode, struct file *file)
-{
-        return single_open(file, proc_titantod_show, NULL);
-}
-
-static const struct file_operations proc_titantod_operations = {
-        .open           = proc_titantod_open,
-        .read           = seq_read,
-        .llseek         = seq_lseek,
-        .release        = single_release,
-};
-
-static int __init iseries_proc_init(void)
-{
-        if (!firmware_has_feature(FW_FEATURE_ISERIES))
-                return 0;
-
-        proc_create("iSeries/titanTod", S_IFREG|S_IRUGO, NULL,
-                    &proc_titantod_operations);
-        return 0;
-}
-__initcall(iseries_proc_init);
diff --git a/arch/powerpc/platforms/iseries/processor_vpd.h b/arch/powerpc/platforms/iseries/processor_vpd.h
deleted file mode 100644
index 7ac5d0d0dbf..00000000000
--- a/arch/powerpc/platforms/iseries/processor_vpd.h
+++ /dev/null
@@ -1,85 +0,0 @@
-/*
- * Copyright (C) 2001  Mike Corrigan IBM Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
- */
-#ifndef _ISERIES_PROCESSOR_VPD_H
-#define _ISERIES_PROCESSOR_VPD_H
-
-#include <asm/types.h>
-
-/*
- * This struct maps Processor Vpd that is DMAd to SLIC by CSP
- */
-struct IoHriProcessorVpd {
-        u8      xFormat;                // VPD format indicator         x00-x00
-        u8      xProcStatus:8;          // Processor State              x01-x01
-        u8      xSecondaryThreadCount;  // Secondary thread cnt         x02-x02
-        u8      xSrcType:1;             // Src Type                     x03-x03
-        u8      xSrcSoft:1;             // Src stay soft                ...
-        u8      xSrcParable:1;          // Src parable                  ...
-        u8      xRsvd1:5;               // Reserved                     ...
-        u16     xHvPhysicalProcIndex;   // Hypervisor physical proc index04-x05
-        u16     xRsvd2;                 // Reserved                     x06-x07
-        u32     xHwNodeId;              // Hardware node id             x08-x0B
-        u32     xHwProcId;              // Hardware processor id        x0C-x0F
-
-        u32     xTypeNum;               // Card Type/CCIN number        x10-x13
-        u32     xModelNum;              // Model/Feature number         x14-x17
-        u64     xSerialNum;             // Serial number                x18-x1F
-        char    xPartNum[12];           // Book Part or FPU number      x20-x2B
-        char    xMfgID[4];              // Manufacturing ID             x2C-x2F
-
-        u32     xProcFreq;              // Processor Frequency          x30-x33
-        u32     xTimeBaseFreq;          // Time Base Frequency          x34-x37
-
-        u32     xChipEcLevel;           // Chip EC Levels               x38-x3B
-        u32     xProcIdReg;             // PIR SPR value                x3C-x3F
-        u32     xPVR;                   // PVR value                    x40-x43
-        u8      xRsvd3[12];             // Reserved                     x44-x4F
-
-        u32     xInstCacheSize;         // Instruction cache size in KB x50-x53
-        u32     xInstBlockSize;         // Instruction cache block size x54-x57
-        u32     xDataCacheOperandSize;  // Data cache operand size      x58-x5B
-        u32     xInstCacheOperandSize;  // Inst cache operand size      x5C-x5F
-
-        u32     xDataL1CacheSizeKB;     // L1 data cache size in KB     x60-x63
-        u32     xDataL1CacheLineSize;   // L1 data cache block size     x64-x67
-        u64     xRsvd4;                 // Reserved                     x68-x6F
-
-        u32     xDataL2CacheSizeKB;     // L2 data cache size in KB     x70-x73
-        u32     xDataL2CacheLineSize;   // L2 data cache block size     x74-x77
-        u64     xRsvd5;                 // Reserved                     x78-x7F
-
-        u32     xDataL3CacheSizeKB;     // L3 data cache size in KB     x80-x83
-        u32     xDataL3CacheLineSize;   // L3 data cache block size     x84-x87
-        u64     xRsvd6;                 // Reserved                     x88-x8F
-
-        u64     xFruLabel;              // Card Location Label          x90-x97
-        u8      xSlotsOnCard;           // Slots on card (0=no slots)   x98-x98
-        u8      xPartLocFlag;           // Location flag (0-pluggable 1-imbedded) x99-x99
-        u16     xSlotMapIndex;          // Index in slot map table      x9A-x9B
-        u8      xSmartCardPortNo;       // Smart card port number       x9C-x9C
-        u8      xRsvd7;                 // Reserved                     x9D-x9D
-        u16     xFrameIdAndRackUnit;    // Frame ID and rack unit adr   x9E-x9F
-
-        u8      xRsvd8[24];             // Reserved                     xA0-xB7
-
-        char    xProcSrc[72];           // CSP format SRC               xB8-xFF
-};
-
-extern struct IoHriProcessorVpd xIoHriProcessorVpd[];
-
-#endif /* _ISERIES_PROCESSOR_VPD_H */
diff --git a/arch/powerpc/platforms/iseries/release_data.h b/arch/powerpc/platforms/iseries/release_data.h
deleted file mode 100644
index 6ad7d843e8f..00000000000
--- a/arch/powerpc/platforms/iseries/release_data.h
+++ /dev/null
@@ -1,63 +0,0 @@
-/*
- * Copyright (C) 2001  Mike Corrigan IBM Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
- */
-#ifndef _ISERIES_RELEASE_DATA_H
-#define _ISERIES_RELEASE_DATA_H
-
-/*
- * This control block contains the critical information about the
- * release so that it can be changed in the future (ie, the virtual
- * address of the OS's NACA).
- */
-#include <asm/types.h>
-#include "naca.h"
-
-/*
- * When we IPL a secondary partition, we will check if if the
- * secondary xMinPlicVrmIndex > the primary xVrmIndex.
- * If it is then this tells PLIC that this secondary is not
- * supported running on this "old" of a level of PLIC.
- *
- * Likewise, we will compare the primary xMinSlicVrmIndex to
- * the secondary xVrmIndex.
- * If the primary xMinSlicVrmDelta > secondary xVrmDelta then we
- * know that this PLIC does not support running an OS "that old".
- */
-
-#define HVREL_TAGSINACTIVE      0x8000
-#define HVREL_32BIT             0x4000
-#define HVREL_NOSHAREDPROCS     0x2000
-#define HVREL_NOHMT             0x1000
-
-struct HvReleaseData {
-        u32     xDesc;          /* Descriptor "HvRD" ebcdic     x00-x03 */
-        u16     xSize;          /* Size of this control block   x04-x05 */
-        u16     xVpdAreasPtrOffset; /* Offset in NACA of ItVpdAreas x06-x07 */
-        struct  naca_struct     *xSlicNacaAddr; /* Virt addr of SLIC NACA x08-x0F */
-        u32     xMsNucDataOffset; /* Offset of Linux Mapping Data x10-x13 */
-        u32     xRsvd1;         /* Reserved                     x14-x17 */
-        u16     xFlags;
-        u16     xVrmIndex;      /* VRM Index of OS image        x1A-x1B */
-        u16     xMinSupportedPlicVrmIndex; /* Min PLIC level  (soft) x1C-x1D */
-        u16     xMinCompatablePlicVrmIndex; /* Min PLIC levelP (hard) x1E-x1F */
-        char    xVrmName[12];   /* Displayable name             x20-x2B */
-        char    xRsvd3[20];     /* Reserved                     x2C-x3F */
-};
-
-extern const struct HvReleaseData       hvReleaseData;
-
-#endif /* _ISERIES_RELEASE_DATA_H */
diff --git a/arch/powerpc/platforms/iseries/setup.c b/arch/powerpc/platforms/iseries/setup.c
deleted file mode 100644
index a5fbf4cb632..00000000000
--- a/arch/powerpc/platforms/iseries/setup.c
+++ /dev/null
@@ -1,718 +0,0 @@
-/*
- *    Copyright (c) 2000 Mike Corrigan <mikejc@us.ibm.com>
- *    Copyright (c) 1999-2000 Grant Erickson <grant@lcse.umn.edu>
- *
- *    Description:
- *      Architecture- / platform-specific boot-time initialization code for
- *      the IBM iSeries LPAR.  Adapted from original code by Grant Erickson and
- *      code by Gary Thomas, Cort Dougan <cort@fsmlabs.com>, and Dan Malek
- *      <dan@net4x.com>.
- *
- *      This program is free software; you can redistribute it and/or
- *      modify it under the terms of the GNU General Public License
- *      as published by the Free Software Foundation; either version
- *      2 of the License, or (at your option) any later version.
- */
-
-#undef DEBUG
-
-#include <linux/init.h>
-#include <linux/threads.h>
-#include <linux/smp.h>
-#include <linux/param.h>
-#include <linux/string.h>
-#include <linux/export.h>
-#include <linux/seq_file.h>
-#include <linux/kdev_t.h>
-#include <linux/kexec.h>
-#include <linux/major.h>
-#include <linux/root_dev.h>
-#include <linux/kernel.h>
-#include <linux/hrtimer.h>
-#include <linux/tick.h>
-
-#include <asm/processor.h>
-#include <asm/machdep.h>
-#include <asm/page.h>
-#include <asm/mmu.h>
-#include <asm/pgtable.h>
-#include <asm/mmu_context.h>
-#include <asm/cputable.h>
-#include <asm/sections.h>
-#include <asm/iommu.h>
-#include <asm/firmware.h>
-#include <asm/system.h>
-#include <asm/time.h>
-#include <asm/paca.h>
-#include <asm/cache.h>
-#include <asm/abs_addr.h>
-#include <asm/iseries/hv_lp_config.h>
-#include <asm/iseries/hv_call_event.h>
-#include <asm/iseries/hv_call_xm.h>
-#include <asm/iseries/it_lp_queue.h>
-#include <asm/iseries/mf.h>
-#include <asm/iseries/hv_lp_event.h>
-#include <asm/iseries/lpar_map.h>
-#include <asm/udbg.h>
-#include <asm/irq.h>
-
-#include "naca.h"
-#include "setup.h"
-#include "irq.h"
-#include "vpd_areas.h"
-#include "processor_vpd.h"
-#include "it_lp_naca.h"
-#include "main_store.h"
-#include "call_sm.h"
-#include "call_hpt.h"
-#include "pci.h"
-
-#ifdef DEBUG
-#define DBG(fmt...) udbg_printf(fmt)
-#else
-#define DBG(fmt...)
-#endif
-
-/* Function Prototypes */
-static unsigned long build_iSeries_Memory_Map(void);
-static void iseries_shared_idle(void);
-static void iseries_dedicated_idle(void);
-
-
-struct MemoryBlock {
-        unsigned long absStart;
-        unsigned long absEnd;
-        unsigned long logicalStart;
-        unsigned long logicalEnd;
-};
-
-/*
- * Process the main store vpd to determine where the holes in memory are
- * and return the number of physical blocks and fill in the array of
- * block data.
- */
-static unsigned long iSeries_process_Condor_mainstore_vpd(
-                struct MemoryBlock *mb_array, unsigned long max_entries)
-{
-        unsigned long holeFirstChunk, holeSizeChunks;
-        unsigned long numMemoryBlocks = 1;
-        struct IoHriMainStoreSegment4 *msVpd =
-                (struct IoHriMainStoreSegment4 *)xMsVpd;
-        unsigned long holeStart = msVpd->nonInterleavedBlocksStartAdr;
-        unsigned long holeEnd = msVpd->nonInterleavedBlocksEndAdr;
-        unsigned long holeSize = holeEnd - holeStart;
-
-        printk("Mainstore_VPD: Condor\n");
-        /*
-         * Determine if absolute memory has any
-         * holes so that we can interpret the
-         * access map we get back from the hypervisor
-         * correctly.
-         */
-        mb_array[0].logicalStart = 0;
-        mb_array[0].logicalEnd = 0x100000000UL;
-        mb_array[0].absStart = 0;
-        mb_array[0].absEnd = 0x100000000UL;
-
-        if (holeSize) {
-                numMemoryBlocks = 2;
-                holeStart = holeStart & 0x000fffffffffffffUL;
-                holeStart = addr_to_chunk(holeStart);
-                holeFirstChunk = holeStart;
-                holeSize = addr_to_chunk(holeSize);
-                holeSizeChunks = holeSize;
-                printk( "Main store hole: start chunk = %0lx, size = %0lx chunks\n",
-                                holeFirstChunk, holeSizeChunks );
-                mb_array[0].logicalEnd = holeFirstChunk;
-                mb_array[0].absEnd = holeFirstChunk;
-                mb_array[1].logicalStart = holeFirstChunk;
-                mb_array[1].logicalEnd = 0x100000000UL - holeSizeChunks;
-                mb_array[1].absStart = holeFirstChunk + holeSizeChunks;
-                mb_array[1].absEnd = 0x100000000UL;
-        }
-        return numMemoryBlocks;
-}
-
-#define MaxSegmentAreas                 32
-#define MaxSegmentAdrRangeBlocks        128
-#define MaxAreaRangeBlocks              4
-
-static unsigned long iSeries_process_Regatta_mainstore_vpd(
-                struct MemoryBlock *mb_array, unsigned long max_entries)
-{
-        struct IoHriMainStoreSegment5 *msVpdP =
-                (struct IoHriMainStoreSegment5 *)xMsVpd;
-        unsigned long numSegmentBlocks = 0;
-        u32 existsBits = msVpdP->msAreaExists;
-        unsigned long area_num;
-
-        printk("Mainstore_VPD: Regatta\n");
-
-        for (area_num = 0; area_num < MaxSegmentAreas; ++area_num ) {
-                unsigned long numAreaBlocks;
-                struct IoHriMainStoreArea4 *currentArea;
-
-                if (existsBits & 0x80000000) {
-                        unsigned long block_num;
-
-                        currentArea = &msVpdP->msAreaArray[area_num];
-                        numAreaBlocks = currentArea->numAdrRangeBlocks;
-                        printk("ms_vpd: processing area %2ld  blocks=%ld",
-                                        area_num, numAreaBlocks);
-                        for (block_num = 0; block_num < numAreaBlocks;
-                                        ++block_num ) {
-                                /* Process an address range block */
-                                struct MemoryBlock tempBlock;
-                                unsigned long i;
-
-                                tempBlock.absStart =
-                                        (unsigned long)currentArea->xAdrRangeBlock[block_num].blockStart;
-                                tempBlock.absEnd =
-                                        (unsigned long)currentArea->xAdrRangeBlock[block_num].blockEnd;
-                                tempBlock.logicalStart = 0;
-                                tempBlock.logicalEnd   = 0;
-                                printk("\n          block %ld absStart=%016lx absEnd=%016lx",
-                                                block_num, tempBlock.absStart,
-                                                tempBlock.absEnd);
-
-                                for (i = 0; i < numSegmentBlocks; ++i) {
-                                        if (mb_array[i].absStart ==
-                                                        tempBlock.absStart)
-                                                break;
-                                }
-                                if (i == numSegmentBlocks) {
-                                        if (numSegmentBlocks == max_entries)
-                                                panic("iSeries_process_mainstore_vpd: too many memory blocks");
-                                        mb_array[numSegmentBlocks] = tempBlock;
-                                        ++numSegmentBlocks;
-                                } else
-                                        printk(" (duplicate)");
-                        }
-                        printk("\n");
-                }
-                existsBits <<= 1;
-        }
-        /* Now sort the blocks found into ascending sequence */
-        if (numSegmentBlocks > 1) {
-                unsigned long m, n;
-
-                for (m = 0; m < numSegmentBlocks - 1; ++m) {
-                        for (n = numSegmentBlocks - 1; m < n; --n) {
-                                if (mb_array[n].absStart <
-                                                mb_array[n-1].absStart) {
-                                        struct MemoryBlock tempBlock;
-
-                                        tempBlock = mb_array[n];
-                                        mb_array[n] = mb_array[n-1];
-                                        mb_array[n-1] = tempBlock;
-                                }
-                        }
-                }
-        }
-        /*
-         * Assign "logical" addresses to each block.  These
-         * addresses correspond to the hypervisor "bitmap" space.
-         * Convert all addresses into units of 256K chunks.
-         */
-        {
-        unsigned long i, nextBitmapAddress;
-
-        printk("ms_vpd: %ld sorted memory blocks\n", numSegmentBlocks);
-        nextBitmapAddress = 0;
-        for (i = 0; i < numSegmentBlocks; ++i) {
-                unsigned long length = mb_array[i].absEnd -
-                        mb_array[i].absStart;
-
-                mb_array[i].logicalStart = nextBitmapAddress;
-                mb_array[i].logicalEnd = nextBitmapAddress + length;
-                nextBitmapAddress += length;
-                printk("          Bitmap range: %016lx - %016lx\n"
-                                "        Absolute range: %016lx - %016lx\n",
-                                mb_array[i].logicalStart,
-                                mb_array[i].logicalEnd,
-                                mb_array[i].absStart, mb_array[i].absEnd);
-                mb_array[i].absStart = addr_to_chunk(mb_array[i].absStart &
-                                0x000fffffffffffffUL);
-                mb_array[i].absEnd = addr_to_chunk(mb_array[i].absEnd &
-                                0x000fffffffffffffUL);
-                mb_array[i].logicalStart =
-                        addr_to_chunk(mb_array[i].logicalStart);
-                mb_array[i].logicalEnd = addr_to_chunk(mb_array[i].logicalEnd);
-        }
-        }
-
-        return numSegmentBlocks;
-}
-
-static unsigned long iSeries_process_mainstore_vpd(struct MemoryBlock *mb_array,
-                unsigned long max_entries)
-{
-        unsigned long i;
-        unsigned long mem_blocks = 0;
-
-        if (mmu_has_feature(MMU_FTR_SLB))
-                mem_blocks = iSeries_process_Regatta_mainstore_vpd(mb_array,
-                                max_entries);
-        else
-                mem_blocks = iSeries_process_Condor_mainstore_vpd(mb_array,
-                                max_entries);
-
-        printk("Mainstore_VPD: numMemoryBlocks = %ld\n", mem_blocks);
-        for (i = 0; i < mem_blocks; ++i) {
-                printk("Mainstore_VPD: block %3ld logical chunks %016lx - %016lx\n"
-                       "                             abs chunks %016lx - %016lx\n",
-                        i, mb_array[i].logicalStart, mb_array[i].logicalEnd,
-                        mb_array[i].absStart, mb_array[i].absEnd);
-        }
-        return mem_blocks;
-}
-
-static void __init iSeries_get_cmdline(void)
-{
-        char *p, *q;
-
-        /* copy the command line parameter from the primary VSP  */
-        HvCallEvent_dmaToSp(cmd_line, 2 * 64* 1024, 256,
-                        HvLpDma_Direction_RemoteToLocal);
-
-        p = cmd_line;
-        q = cmd_line + 255;
-        while(p < q) {
-                if (!*p || *p == '\n')
-                        break;
-                ++p;
-        }
-        *p = 0;
-}
-
-static void __init iSeries_init_early(void)
-{
-        DBG(" -> iSeries_init_early()\n");
-
-        /* Snapshot the timebase, for use in later recalibration */
-        iSeries_time_init_early();
-
-        /*
-         * Initialize the DMA/TCE management
-         */
-        iommu_init_early_iSeries();
-
-        /* Initialize machine-dependency vectors */
-#ifdef CONFIG_SMP
-        smp_init_iSeries();
-#endif
-
-        /* Associate Lp Event Queue 0 with processor 0 */
-        HvCallEvent_setLpEventQueueInterruptProc(0, 0);
-
-        mf_init();
-
-        DBG(" <- iSeries_init_early()\n");
-}
-
-struct mschunks_map mschunks_map = {
-        /* XXX We don't use these, but Piranha might need them. */
-        .chunk_size  = MSCHUNKS_CHUNK_SIZE,
-        .chunk_shift = MSCHUNKS_CHUNK_SHIFT,
-        .chunk_mask  = MSCHUNKS_OFFSET_MASK,
-};
-EXPORT_SYMBOL(mschunks_map);
-
-static void mschunks_alloc(unsigned long num_chunks)
-{
-        klimit = _ALIGN(klimit, sizeof(u32));
-        mschunks_map.mapping = (u32 *)klimit;
-        klimit += num_chunks * sizeof(u32);
-        mschunks_map.num_chunks = num_chunks;
-}
-
-/*
- * The iSeries may have very large memories ( > 128 GB ) and a partition
- * may get memory in "chunks" that may be anywhere in the 2**52 real
- * address space.  The chunks are 256K in size.  To map this to the
- * memory model Linux expects, the AS/400 specific code builds a
- * translation table to translate what Linux thinks are "physical"
- * addresses to the actual real addresses.  This allows us to make
- * it appear to Linux that we have contiguous memory starting at
- * physical address zero while in fact this could be far from the truth.
- * To avoid confusion, I'll let the words physical and/or real address
- * apply to the Linux addresses while I'll use "absolute address" to
- * refer to the actual hardware real address.
- *
- * build_iSeries_Memory_Map gets information from the Hypervisor and
- * looks at the Main Store VPD to determine the absolute addresses
- * of the memory that has been assigned to our partition and builds
- * a table used to translate Linux's physical addresses to these
- * absolute addresses.  Absolute addresses are needed when
- * communicating with the hypervisor (e.g. to build HPT entries)
- *
- * Returns the physical memory size
- */
-
-static unsigned long __init build_iSeries_Memory_Map(void)
-{
-        u32 loadAreaFirstChunk, loadAreaLastChunk, loadAreaSize;
-        u32 nextPhysChunk;
-        u32 hptFirstChunk, hptLastChunk, hptSizeChunks, hptSizePages;
-        u32 totalChunks,moreChunks;
-        u32 currChunk, thisChunk, absChunk;
-        u32 currDword;
-        u32 chunkBit;
-        u64 map;
-        struct MemoryBlock mb[32];
-        unsigned long numMemoryBlocks, curBlock;
-
-        /* Chunk size on iSeries is 256K bytes */
-        totalChunks = (u32)HvLpConfig_getMsChunks();
-        mschunks_alloc(totalChunks);
-
-        /*
-         * Get absolute address of our load area
-         * and map it to physical address 0
-         * This guarantees that the loadarea ends up at physical 0
-         * otherwise, it might not be returned by PLIC as the first
-         * chunks
-         */
-
-        loadAreaFirstChunk = (u32)addr_to_chunk(itLpNaca.xLoadAreaAddr);
-        loadAreaSize =  itLpNaca.xLoadAreaChunks;
-
-        /*
-         * Only add the pages already mapped here.
-         * Otherwise we might add the hpt pages
-         * The rest of the pages of the load area
-         * aren't in the HPT yet and can still
-         * be assigned an arbitrary physical address
-         */
-        if ((loadAreaSize * 64) > HvPagesToMap)
-                loadAreaSize = HvPagesToMap / 64;
-
-        loadAreaLastChunk = loadAreaFirstChunk + loadAreaSize - 1;
-
-        /*
-         * TODO Do we need to do something if the HPT is in the 64MB load area?
-         * This would be required if the itLpNaca.xLoadAreaChunks includes
-         * the HPT size
-         */
-
-        printk("Mapping load area - physical addr = 0000000000000000\n"
-                "                    absolute addr = %016lx\n",
-                chunk_to_addr(loadAreaFirstChunk));
-        printk("Load area size %dK\n", loadAreaSize * 256);
-
-        for (nextPhysChunk = 0; nextPhysChunk < loadAreaSize; ++nextPhysChunk)
-                mschunks_map.mapping[nextPhysChunk] =
-                        loadAreaFirstChunk + nextPhysChunk;
-
-        /*
-         * Get absolute address of our HPT and remember it so
-         * we won't map it to any physical address
-         */
-        hptFirstChunk = (u32)addr_to_chunk(HvCallHpt_getHptAddress());
-        hptSizePages = (u32)HvCallHpt_getHptPages();
-        hptSizeChunks = hptSizePages >>
-                (MSCHUNKS_CHUNK_SHIFT - HW_PAGE_SHIFT);
-        hptLastChunk = hptFirstChunk + hptSizeChunks - 1;
-
-        printk("HPT absolute addr = %016lx, size = %dK\n",
-                        chunk_to_addr(hptFirstChunk), hptSizeChunks * 256);
-
-        /*
-         * Determine if absolute memory has any
-         * holes so that we can interpret the
-         * access map we get back from the hypervisor
-         * correctly.
-         */
-        numMemoryBlocks = iSeries_process_mainstore_vpd(mb, 32);
-
-        /*
-         * Process the main store access map from the hypervisor
-         * to build up our physical -> absolute translation table
-         */
-        curBlock = 0;
-        currChunk = 0;
-        currDword = 0;
-        moreChunks = totalChunks;
-
-        while (moreChunks) {
-                map = HvCallSm_get64BitsOfAccessMap(itLpNaca.xLpIndex,
-                                currDword);
-                thisChunk = currChunk;
-                while (map) {
-                        chunkBit = map >> 63;
-                        map <<= 1;
-                        if (chunkBit) {
-                                --moreChunks;
-                                while (thisChunk >= mb[curBlock].logicalEnd) {
-                                        ++curBlock;
-                                        if (curBlock >= numMemoryBlocks)
-                                                panic("out of memory blocks");
-                                }
-                                if (thisChunk < mb[curBlock].logicalStart)
-                                        panic("memory block error");
-
-                                absChunk = mb[curBlock].absStart +
-                                        (thisChunk - mb[curBlock].logicalStart);
-                                if (((absChunk < hptFirstChunk) ||
-                                     (absChunk > hptLastChunk)) &&
-                                    ((absChunk < loadAreaFirstChunk) ||
-                                     (absChunk > loadAreaLastChunk))) {
-                                        mschunks_map.mapping[nextPhysChunk] =
-                                                absChunk;
-                                        ++nextPhysChunk;
-                                }
-                        }
-                        ++thisChunk;
-                }
-                ++currDword;
-                currChunk += 64;
-        }
-
-        /*
-         * main store size (in chunks) is
-         *   totalChunks - hptSizeChunks
-         * which should be equal to
-         *   nextPhysChunk
-         */
-        return chunk_to_addr(nextPhysChunk);
-}
-
-/*
- * Document me.
- */
-static void __init iSeries_setup_arch(void)
-{
-        if (get_lppaca()->shared_proc) {
-                ppc_md.idle_loop = iseries_shared_idle;
-                printk(KERN_DEBUG "Using shared processor idle loop\n");
-        } else {
-                ppc_md.idle_loop = iseries_dedicated_idle;
-                printk(KERN_DEBUG "Using dedicated idle loop\n");
-        }
-
-        /* Setup the Lp Event Queue */
-        setup_hvlpevent_queue();
-
-        printk("Max  logical processors = %d\n",
-                        itVpdAreas.xSlicMaxLogicalProcs);
-        printk("Max physical processors = %d\n",
-                        itVpdAreas.xSlicMaxPhysicalProcs);
-
-        iSeries_pcibios_init();
-}
-
-static void iSeries_show_cpuinfo(struct seq_file *m)
-{
-        seq_printf(m, "machine\t\t: 64-bit iSeries Logical Partition\n");
-}
-
-static void __init iSeries_progress(char * st, unsigned short code)
-{
-        printk("Progress: [%04x] - %s\n", (unsigned)code, st);
-        mf_display_progress(code);
-}
-
-static void __init iSeries_fixup_klimit(void)
-{
-        /*
-         * Change klimit to take into account any ram disk
-         * that may be included
-         */
-        if (naca.xRamDisk)
-                klimit = KERNELBASE + (u64)naca.xRamDisk +
-                        (naca.xRamDiskSize * HW_PAGE_SIZE);
-}
-
-static int __init iSeries_src_init(void)
-{
-        /* clear the progress line */
-        if (firmware_has_feature(FW_FEATURE_ISERIES))
-                ppc_md.progress(" ", 0xffff);
-        return 0;
-}
-
-late_initcall(iSeries_src_init);
-
-static inline void process_iSeries_events(void)
-{
-        asm volatile ("li 0,0x5555; sc" : : : "r0", "r3");
-}
-
-static void yield_shared_processor(void)
-{
-        unsigned long tb;
-
-        HvCall_setEnabledInterrupts(HvCall_MaskIPI |
-                                    HvCall_MaskLpEvent |
-                                    HvCall_MaskLpProd |
-                                    HvCall_MaskTimeout);
-
-        tb = get_tb();
-        /* Compute future tb value when yield should expire */
-        HvCall_yieldProcessor(HvCall_YieldTimed, tb+tb_ticks_per_jiffy);
-
-        /*
-         * The decrementer stops during the yield.  Force a fake decrementer
-         * here and let the timer_interrupt code sort out the actual time.
-         */
-        get_lppaca()->int_dword.fields.decr_int = 1;
-        ppc64_runlatch_on();
-        process_iSeries_events();
-}
-
-static void iseries_shared_idle(void)
-{
-        while (1) {
-                tick_nohz_idle_enter();
-                rcu_idle_enter();
-                while (!need_resched() && !hvlpevent_is_pending()) {
-                        local_irq_disable();
-                        ppc64_runlatch_off();
-
-                        /* Recheck with irqs off */
-                        if (!need_resched() && !hvlpevent_is_pending())
-                                yield_shared_processor();
-
-                        HMT_medium();
-                        local_irq_enable();
-                }
-
-                ppc64_runlatch_on();
-                rcu_idle_exit();
-                tick_nohz_idle_exit();
-
-                if (hvlpevent_is_pending())
-                        process_iSeries_events();
-
-                schedule_preempt_disabled();
-        }
-}
-
-static void iseries_dedicated_idle(void)
-{
-        set_thread_flag(TIF_POLLING_NRFLAG);
-
-        while (1) {
-                tick_nohz_idle_enter();
-                rcu_idle_enter();
-                if (!need_resched()) {
-                        while (!need_resched()) {
-                                ppc64_runlatch_off();
-                                HMT_low();
-
-                                if (hvlpevent_is_pending()) {
-                                        HMT_medium();
-                                        ppc64_runlatch_on();
-                                        process_iSeries_events();
-                                }
-                        }
-
-                        HMT_medium();
-                }
-
-                ppc64_runlatch_on();
-                rcu_idle_exit();
-                tick_nohz_idle_exit();
-                schedule_preempt_disabled();
-        }
-}
-
-static void __iomem *iseries_ioremap(phys_addr_t address, unsigned long size,
-                                     unsigned long flags, void *caller)
-{
-        return (void __iomem *)address;
-}
-
-static void iseries_iounmap(volatile void __iomem *token)
-{
-}
-
-static int __init iseries_probe(void)
-{
-        unsigned long root = of_get_flat_dt_root();
-        if (!of_flat_dt_is_compatible(root, "IBM,iSeries"))
-                return 0;
-
-        hpte_init_iSeries();
-        /* iSeries does not support 16M pages */
-        cur_cpu_spec->mmu_features &= ~MMU_FTR_16M_PAGE;
-
-        return 1;
-}
-
-#ifdef CONFIG_KEXEC
-static int iseries_kexec_prepare(struct kimage *image)
-{
-        return -ENOSYS;
-}
-#endif
-
-define_machine(iseries) {
-        .name                   = "iSeries",
-        .setup_arch             = iSeries_setup_arch,
-        .show_cpuinfo           = iSeries_show_cpuinfo,
-        .init_IRQ               = iSeries_init_IRQ,
-        .get_irq                = iSeries_get_irq,
-        .init_early             = iSeries_init_early,
-        .pcibios_fixup          = iSeries_pci_final_fixup,
-        .pcibios_fixup_resources= iSeries_pcibios_fixup_resources,
-        .restart                = mf_reboot,
-        .power_off              = mf_power_off,
-        .halt                   = mf_power_off,
-        .get_boot_time          = iSeries_get_boot_time,
-        .set_rtc_time           = iSeries_set_rtc_time,
-        .get_rtc_time           = iSeries_get_rtc_time,
-        .calibrate_decr         = generic_calibrate_decr,
-        .progress               = iSeries_progress,
-        .probe                  = iseries_probe,
-        .ioremap                = iseries_ioremap,
-        .iounmap                = iseries_iounmap,
-#ifdef CONFIG_KEXEC
-        .machine_kexec_prepare  = iseries_kexec_prepare,
-#endif
-        /* XXX Implement enable_pmcs for iSeries */
-};
-
-void * __init iSeries_early_setup(void)
-{
-        unsigned long phys_mem_size;
-
-        /* Identify CPU type. This is done again by the common code later
-         * on but calling this function multiple times is fine.
-         */
-        identify_cpu(0, mfspr(SPRN_PVR));
-        initialise_paca(&boot_paca, 0);
-
-        powerpc_firmware_features |= FW_FEATURE_ISERIES;
-        powerpc_firmware_features |= FW_FEATURE_LPAR;
-
-#ifdef CONFIG_SMP
-        /* On iSeries we know we can never have more than 64 cpus */
-        nr_cpu_ids = max(nr_cpu_ids, 64);
-#endif
-
-        iSeries_fixup_klimit();
-
-        /*
-         * Initialize the table which translate Linux physical addresses to
-         * AS/400 absolute addresses
-         */
-        phys_mem_size = build_iSeries_Memory_Map();
-
-        iSeries_get_cmdline();
-
-        return (void *) __pa(build_flat_dt(phys_mem_size));
-}
-
-static void hvputc(char c)
-{
-        if (c == '\n')
-                hvputc('\r');
-
-        HvCall_writeLogBuffer(&c, 1);
-}
-
-void __init udbg_init_iseries(void)
-{
-        udbg_putc = hvputc;
-}
diff --git a/arch/powerpc/platforms/iseries/setup.h b/arch/powerpc/platforms/iseries/setup.h
deleted file mode 100644
index 729754bbb01..00000000000
--- a/arch/powerpc/platforms/iseries/setup.h
+++ /dev/null
@@ -1,27 +0,0 @@
-/*
- *    Copyright (c) 2000 Mike Corrigan <mikejc@us.ibm.com>
- *    Copyright (c) 1999-2000 Grant Erickson <grant@lcse.umn.edu>
- *
- *    Description:
- *      Architecture- / platform-specific boot-time initialization code for
- *      the IBM AS/400 LPAR. Adapted from original code by Grant Erickson and
- *      code by Gary Thomas, Cort Dougan <cort@cs.nmt.edu>, and Dan Malek
- *      <dan@netx4.com>.
- *
- *      This program is free software; you can redistribute it and/or
- *      modify it under the terms of the GNU General Public License
- *      as published by the Free Software Foundation; either version
- *      2 of the License, or (at your option) any later version.
- */
-
-#ifndef __ISERIES_SETUP_H__
-#define __ISERIES_SETUP_H__
-
-extern void *iSeries_early_setup(void);
-extern unsigned long iSeries_get_boot_time(void);
-extern int iSeries_set_rtc_time(struct rtc_time *tm);
-extern void iSeries_get_rtc_time(struct rtc_time *tm);
-
-extern void *build_flat_dt(unsigned long phys_mem_size);
-
-#endif /* __ISERIES_SETUP_H__ */
diff --git a/arch/powerpc/platforms/iseries/smp.c b/arch/powerpc/platforms/iseries/smp.c
deleted file mode 100644
index 02df49fb59f..00000000000
--- a/arch/powerpc/platforms/iseries/smp.c
+++ /dev/null
@@ -1,88 +0,0 @@
-/*
- * SMP support for iSeries machines.
- *
- * Dave Engebretsen, Peter Bergner, and
- * Mike Corrigan {engebret|bergner|mikec}@us.ibm.com
- *
- * Plus various changes from other IBM teams...
- *
- *      This program is free software; you can redistribute it and/or
- *      modify it under the terms of the GNU General Public License
- *      as published by the Free Software Foundation; either version
- *      2 of the License, or (at your option) any later version.
- */
-
-#undef DEBUG
-
-#include <linux/kernel.h>
-#include <linux/sched.h>
-#include <linux/smp.h>
-#include <linux/interrupt.h>
-#include <linux/kernel_stat.h>
-#include <linux/delay.h>
-#include <linux/init.h>
-#include <linux/spinlock.h>
-#include <linux/cache.h>
-#include <linux/err.h>
-#include <linux/device.h>
-#include <linux/cpu.h>
-
-#include <asm/ptrace.h>
-#include <linux/atomic.h>
-#include <asm/irq.h>
-#include <asm/page.h>
-#include <asm/pgtable.h>
-#include <asm/io.h>
-#include <asm/smp.h>
-#include <asm/paca.h>
-#include <asm/iseries/hv_call.h>
-#include <asm/time.h>
-#include <asm/machdep.h>
-#include <asm/cputable.h>
-#include <asm/system.h>
-
-static void smp_iSeries_cause_ipi(int cpu, unsigned long data)
-{
-        HvCall_sendIPI(&(paca[cpu]));
-}
-
-static int smp_iSeries_probe(void)
-{
-        return cpumask_weight(cpu_possible_mask);
-}
-
-static int smp_iSeries_kick_cpu(int nr)
-{
-        BUG_ON((nr < 0) || (nr >= NR_CPUS));
-
-        /* Verify that our partition has a processor nr */
-        if (lppaca_of(nr).dyn_proc_status >= 2)
-                return -ENOENT;
-
-        /* The processor is currently spinning, waiting
-         * for the cpu_start field to become non-zero
-         * After we set cpu_start, the processor will
-         * continue on to secondary_start in iSeries_head.S
-         */
-        paca[nr].cpu_start = 1;
-
-        return 0;
-}
-
-static void __devinit smp_iSeries_setup_cpu(int nr)
-{
-}
-
-static struct smp_ops_t iSeries_smp_ops = {
-        .message_pass = NULL,   /* Use smp_muxed_ipi_message_pass */
-        .cause_ipi    = smp_iSeries_cause_ipi,
-        .probe        = smp_iSeries_probe,
-        .kick_cpu     = smp_iSeries_kick_cpu,
-        .setup_cpu    = smp_iSeries_setup_cpu,
-};
-
-/* This is called very early. */
-void __init smp_init_iSeries(void)
-{
-        smp_ops = &iSeries_smp_ops;
-}
diff --git a/arch/powerpc/platforms/iseries/spcomm_area.h b/arch/powerpc/platforms/iseries/spcomm_area.h
deleted file mode 100644
index 598b7c14573..00000000000
--- a/arch/powerpc/platforms/iseries/spcomm_area.h
+++ /dev/null
@@ -1,34 +0,0 @@
-/*
- * Copyright (C) 2001  Mike Corrigan IBM Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
- */
-
-#ifndef _ISERIES_SPCOMM_AREA_H
-#define _ISERIES_SPCOMM_AREA_H
-
-
-struct SpCommArea {
-        u32     xDesc;                  // Descriptor (only in new formats)     000-003
-        u8      xFormat;                // Format (only in new formats)         004-004
-        u8      xRsvd1[11];             // Reserved                             005-00F
-        u64     xRawTbAtIplStart;       // Raw HW TB value when IPL is started  010-017
-        u64     xRawTodAtIplStart;      // Raw HW TOD value when IPL is started 018-01F
-        u64     xBcdTimeAtIplStart;     // BCD time when IPL is started         020-027
-        u64     xBcdTimeAtOsStart;      // BCD time when OS passed control      028-02F
-        u8      xRsvd2[80];             // Reserved                             030-07F
-};
-
-#endif /* _ISERIES_SPCOMM_AREA_H */
diff --git a/arch/powerpc/platforms/iseries/vio.c b/arch/powerpc/platforms/iseries/vio.c
deleted file mode 100644
index 04be62d368a..00000000000
--- a/arch/powerpc/platforms/iseries/vio.c
+++ /dev/null
@@ -1,556 +0,0 @@
-/*
- * Legacy iSeries specific vio initialisation
- * that needs to be built in (not a module).
- *
- * © Copyright 2007 IBM Corporation
- *      Author: Stephen Rothwell
- *      Some parts collected from various other files
- *
- * This program is free software;  you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
- * General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software Foundation,
- * Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- */
-#include <linux/of.h>
-#include <linux/init.h>
-#include <linux/slab.h>
-#include <linux/completion.h>
-#include <linux/proc_fs.h>
-#include <linux/export.h>
-
-#include <asm/firmware.h>
-#include <asm/vio.h>
-#include <asm/iseries/vio.h>
-#include <asm/iseries/iommu.h>
-#include <asm/iseries/hv_types.h>
-#include <asm/iseries/hv_lp_event.h>
-
-#define FIRST_VTY       0
-#define NUM_VTYS        1
-#define FIRST_VSCSI     (FIRST_VTY + NUM_VTYS)
-#define NUM_VSCSIS      1
-#define FIRST_VLAN      (FIRST_VSCSI + NUM_VSCSIS)
-#define NUM_VLANS       HVMAXARCHITECTEDVIRTUALLANS
-#define FIRST_VIODASD   (FIRST_VLAN + NUM_VLANS)
-#define NUM_VIODASDS    HVMAXARCHITECTEDVIRTUALDISKS
-#define FIRST_VIOCD     (FIRST_VIODASD + NUM_VIODASDS)
-#define NUM_VIOCDS      HVMAXARCHITECTEDVIRTUALCDROMS
-#define FIRST_VIOTAPE   (FIRST_VIOCD + NUM_VIOCDS)
-#define NUM_VIOTAPES    HVMAXARCHITECTEDVIRTUALTAPES
-
-struct vio_waitevent {
-        struct completion       com;
-        int                     rc;
-        u16                     sub_result;
-};
-
-struct vio_resource {
-        char    rsrcname[10];
-        char    type[4];
-        char    model[3];
-};
-
-static struct property *new_property(const char *name, int length,
-                const void *value)
-{
-        struct property *np = kzalloc(sizeof(*np) + strlen(name) + 1 + length,
-                        GFP_KERNEL);
-
-        if (!np)
-                return NULL;
-        np->name = (char *)(np + 1);
-        np->value = np->name + strlen(name) + 1;
-        strcpy(np->name, name);
-        memcpy(np->value, value, length);
-        np->length = length;
-        return np;
-}
-
-static void free_property(struct property *np)
-{
-        kfree(np);
-}
-
-static struct device_node *new_node(const char *path,
-                struct device_node *parent)
-{
-        struct device_node *np = kzalloc(sizeof(*np), GFP_KERNEL);
-
-        if (!np)
-                return NULL;
-        np->full_name = kstrdup(path, GFP_KERNEL);
-        if (!np->full_name) {
-                kfree(np);
-                return NULL;
-        }
-        of_node_set_flag(np, OF_DYNAMIC);
-        kref_init(&np->kref);
-        np->parent = of_node_get(parent);
-        return np;
-}
-
-static void free_node(struct device_node *np)
-{
-        struct property *next;
-        struct property *prop;
-
-        next = np->properties;
-        while (next) {
-                prop = next;
-                next = prop->next;
-                free_property(prop);
-        }
-        of_node_put(np->parent);
-        kfree(np->full_name);
-        kfree(np);
-}
-
-static int add_string_property(struct device_node *np, const char *name,
-                const char *value)
-{
-        struct property *nprop = new_property(name, strlen(value) + 1, value);
-
-        if (!nprop)
-                return 0;
-        prom_add_property(np, nprop);
-        return 1;
-}
-
-static int add_raw_property(struct device_node *np, const char *name,
-                int length, const void *value)
-{
-        struct property *nprop = new_property(name, length, value);
-
-        if (!nprop)
-                return 0;
-        prom_add_property(np, nprop);
-        return 1;
-}
-
-static struct device_node *do_device_node(struct device_node *parent,
-                const char *name, u32 reg, u32 unit, const char *type,
-                const char *compat, struct vio_resource *res)
-{
-        struct device_node *np;
-        char path[32];
-
-        snprintf(path, sizeof(path), "/vdevice/%s@%08x", name, reg);
-        np = new_node(path, parent);
-        if (!np)
-                return NULL;
-        if (!add_string_property(np, "name", name) ||
-                !add_string_property(np, "device_type", type) ||
-                !add_string_property(np, "compatible", compat) ||
-                !add_raw_property(np, "reg", sizeof(reg), &reg) ||
-                !add_raw_property(np, "linux,unit_address",
-                        sizeof(unit), &unit)) {
-                goto node_free;
-        }
-        if (res) {
-                if (!add_raw_property(np, "linux,vio_rsrcname",
-                                sizeof(res->rsrcname), res->rsrcname) ||
-                        !add_raw_property(np, "linux,vio_type",
-                                sizeof(res->type), res->type) ||
-                        !add_raw_property(np, "linux,vio_model",
-                                sizeof(res->model), res->model))
-                        goto node_free;
-        }
-        np->name = of_get_property(np, "name", NULL);
-        np->type = of_get_property(np, "device_type", NULL);
-        of_attach_node(np);
-#ifdef CONFIG_PROC_DEVICETREE
-        if (parent->pde) {
-                struct proc_dir_entry *ent;
-
-                ent = proc_mkdir(strrchr(np->full_name, '/') + 1, parent->pde);
-                if (ent)
-                        proc_device_tree_add_node(np, ent);
-        }
-#endif
-        return np;
-
- node_free:
-        free_node(np);
-        return NULL;
-}
-
-/*
- * This is here so that we can dynamically add viodasd
- * devices without exposing all the above infrastructure.
- */
-struct vio_dev *vio_create_viodasd(u32 unit)
-{
-        struct device_node *vio_root;
-        struct device_node *np;
-        struct vio_dev *vdev = NULL;
-
-        vio_root = of_find_node_by_path("/vdevice");
-        if (!vio_root)
-                return NULL;
-        np = do_device_node(vio_root, "viodasd", FIRST_VIODASD + unit, unit,
-                        "block", "IBM,iSeries-viodasd", NULL);
-        of_node_put(vio_root);
-        if (np) {
-                vdev = vio_register_device_node(np);
-                if (!vdev)
-                        free_node(np);
-        }
-        return vdev;
-}
-EXPORT_SYMBOL_GPL(vio_create_viodasd);
-
-static void __init handle_block_event(struct HvLpEvent *event)
-{
-        struct vioblocklpevent *bevent = (struct vioblocklpevent *)event;
-        struct vio_waitevent *pwe;
-
-        if (event == NULL)
-                /* Notification that a partition went away! */
-                return;
-        /* First, we should NEVER get an int here...only acks */
-        if (hvlpevent_is_int(event)) {
-                printk(KERN_WARNING "handle_viod_request: "
-                       "Yikes! got an int in viodasd event handler!\n");
-                if (hvlpevent_need_ack(event)) {
-                        event->xRc = HvLpEvent_Rc_InvalidSubtype;
-                        HvCallEvent_ackLpEvent(event);
-                }
-                return;
-        }
-
-        switch (event->xSubtype & VIOMINOR_SUBTYPE_MASK) {
-        case vioblockopen:
-                /*
-                 * Handle a response to an open request.  We get all the
-                 * disk information in the response, so update it.  The
-                 * correlation token contains a pointer to a waitevent
-                 * structure that has a completion in it.  update the
-                 * return code in the waitevent structure and post the
-                 * completion to wake up the guy who sent the request
-                 */
-                pwe = (struct vio_waitevent *)event->xCorrelationToken;
-                pwe->rc = event->xRc;
-                pwe->sub_result = bevent->sub_result;
-                complete(&pwe->com);
-                break;
-        case vioblockclose:
-                break;
-        default:
-                printk(KERN_WARNING "handle_viod_request: unexpected subtype!");
-                if (hvlpevent_need_ack(event)) {
-                        event->xRc = HvLpEvent_Rc_InvalidSubtype;
-                        HvCallEvent_ackLpEvent(event);
-                }
-        }
-}
-
-static void __init probe_disk(struct device_node *vio_root, u32 unit)
-{
-        HvLpEvent_Rc hvrc;
-        struct vio_waitevent we;
-        u16 flags = 0;
-
-retry:
-        init_completion(&we.com);
-
-        /* Send the open event to OS/400 */
-        hvrc = HvCallEvent_signalLpEventFast(viopath_hostLp,
-                        HvLpEvent_Type_VirtualIo,
-                        viomajorsubtype_blockio | vioblockopen,
-                        HvLpEvent_AckInd_DoAck, HvLpEvent_AckType_ImmediateAck,
-                        viopath_sourceinst(viopath_hostLp),
-                        viopath_targetinst(viopath_hostLp),
-                        (u64)(unsigned long)&we, VIOVERSION << 16,
-                        ((u64)unit << 48) | ((u64)flags<< 32),
-                        0, 0, 0);
-        if (hvrc != 0) {
-                printk(KERN_WARNING "probe_disk: bad rc on HV open %d\n",
-                        (int)hvrc);
-                return;
-        }
-
-        wait_for_completion(&we.com);
-
-        if (we.rc != 0) {
-                if (flags != 0)
-                        return;
-                /* try again with read only flag set */
-                flags = vioblockflags_ro;
-                goto retry;
-        }
-
-        /* Send the close event to OS/400.  We DON'T expect a response */
-        hvrc = HvCallEvent_signalLpEventFast(viopath_hostLp,
-                        HvLpEvent_Type_VirtualIo,
-                        viomajorsubtype_blockio | vioblockclose,
-                        HvLpEvent_AckInd_NoAck, HvLpEvent_AckType_ImmediateAck,
-                        viopath_sourceinst(viopath_hostLp),
-                        viopath_targetinst(viopath_hostLp),
-                        0, VIOVERSION << 16,
-                        ((u64)unit << 48) | ((u64)flags << 32),
-                        0, 0, 0);
-        if (hvrc != 0) {
-                printk(KERN_WARNING "probe_disk: "
-                       "bad rc sending event to OS/400 %d\n", (int)hvrc);
-                return;
-        }
-
-        do_device_node(vio_root, "viodasd", FIRST_VIODASD + unit, unit,
-                        "block", "IBM,iSeries-viodasd", NULL);
-}
-
-static void __init get_viodasd_info(struct device_node *vio_root)
-{
-        int rc;
-        u32 unit;
-
-        rc = viopath_open(viopath_hostLp, viomajorsubtype_blockio, 2);
-        if (rc) {
-                printk(KERN_WARNING "get_viodasd_info: "
-                       "error opening path to host partition %d\n",
-                       viopath_hostLp);
-                return;
-        }
-
-        /* Initialize our request handler */
-        vio_setHandler(viomajorsubtype_blockio, handle_block_event);
-
-        for (unit = 0; unit < HVMAXARCHITECTEDVIRTUALDISKS; unit++)
-                probe_disk(vio_root, unit);
-
-        vio_clearHandler(viomajorsubtype_blockio);
-        viopath_close(viopath_hostLp, viomajorsubtype_blockio, 2);
-}
-
-static void __init handle_cd_event(struct HvLpEvent *event)
-{
-        struct viocdlpevent *bevent;
-        struct vio_waitevent *pwe;
-
-        if (!event)
-                /* Notification that a partition went away! */
-                return;
-
-        /* First, we should NEVER get an int here...only acks */
-        if (hvlpevent_is_int(event)) {
-                printk(KERN_WARNING "handle_cd_event: got an unexpected int\n");
-                if (hvlpevent_need_ack(event)) {
-                        event->xRc = HvLpEvent_Rc_InvalidSubtype;
-                        HvCallEvent_ackLpEvent(event);
-                }
-                return;
-        }
-
-        bevent = (struct viocdlpevent *)event;
-
-        switch (event->xSubtype & VIOMINOR_SUBTYPE_MASK) {
-        case viocdgetinfo:
-                pwe = (struct vio_waitevent *)event->xCorrelationToken;
-                pwe->rc = event->xRc;
-                pwe->sub_result = bevent->sub_result;
-                complete(&pwe->com);
-                break;
-
-        default:
-                printk(KERN_WARNING "handle_cd_event: "
-                        "message with unexpected subtype %0x04X!\n",
-                        event->xSubtype & VIOMINOR_SUBTYPE_MASK);
-                if (hvlpevent_need_ack(event)) {
-                        event->xRc = HvLpEvent_Rc_InvalidSubtype;
-                        HvCallEvent_ackLpEvent(event);
-                }
-        }
-}
-
-static void __init get_viocd_info(struct device_node *vio_root)
-{
-        HvLpEvent_Rc hvrc;
-        u32 unit;
-        struct vio_waitevent we;
-        struct vio_resource *unitinfo;
-        dma_addr_t unitinfo_dmaaddr;
-        int ret;
-
-        ret = viopath_open(viopath_hostLp, viomajorsubtype_cdio, 2);
-        if (ret) {
-                printk(KERN_WARNING
-                        "get_viocd_info: error opening path to host partition %d\n",
-                        viopath_hostLp);
-                return;
-        }
-
-        /* Initialize our request handler */
-        vio_setHandler(viomajorsubtype_cdio, handle_cd_event);
-
-        unitinfo = iseries_hv_alloc(
-                        sizeof(*unitinfo) * HVMAXARCHITECTEDVIRTUALCDROMS,
-                        &unitinfo_dmaaddr, GFP_ATOMIC);
-        if (!unitinfo) {
-                printk(KERN_WARNING
-                        "get_viocd_info: error allocating unitinfo\n");
-                goto clear_handler;
-        }
-
-        memset(unitinfo, 0, sizeof(*unitinfo) * HVMAXARCHITECTEDVIRTUALCDROMS);
-
-        init_completion(&we.com);
-
-        hvrc = HvCallEvent_signalLpEventFast(viopath_hostLp,
-                        HvLpEvent_Type_VirtualIo,
-                        viomajorsubtype_cdio | viocdgetinfo,
-                        HvLpEvent_AckInd_DoAck, HvLpEvent_AckType_ImmediateAck,
-                        viopath_sourceinst(viopath_hostLp),
-                        viopath_targetinst(viopath_hostLp),
-                        (u64)&we, VIOVERSION << 16, unitinfo_dmaaddr, 0,
-                        sizeof(*unitinfo) * HVMAXARCHITECTEDVIRTUALCDROMS, 0);
-        if (hvrc != HvLpEvent_Rc_Good) {
-                printk(KERN_WARNING
-                        "get_viocd_info: cdrom error sending event. rc %d\n",
-                        (int)hvrc);
-                goto hv_free;
-        }
-
-        wait_for_completion(&we.com);
-
-        if (we.rc) {
-                printk(KERN_WARNING "get_viocd_info: bad rc %d:0x%04X\n",
-                        we.rc, we.sub_result);
-                goto hv_free;
-        }
-
-        for (unit = 0; (unit < HVMAXARCHITECTEDVIRTUALCDROMS) &&
-                        unitinfo[unit].rsrcname[0]; unit++) {
-                if (!do_device_node(vio_root, "viocd", FIRST_VIOCD + unit, unit,
-                                "block", "IBM,iSeries-viocd", &unitinfo[unit]))
-                        break;
-        }
-
- hv_free:
-        iseries_hv_free(sizeof(*unitinfo) * HVMAXARCHITECTEDVIRTUALCDROMS,
-                        unitinfo, unitinfo_dmaaddr);
- clear_handler:
-        vio_clearHandler(viomajorsubtype_cdio);
-        viopath_close(viopath_hostLp, viomajorsubtype_cdio, 2);
-}
-
-/* Handle interrupt events for tape */
-static void __init handle_tape_event(struct HvLpEvent *event)
-{
-        struct vio_waitevent *we;
-        struct viotapelpevent *tevent = (struct viotapelpevent *)event;
-
-        if (event == NULL)
-                /* Notification that a partition went away! */
-                return;
-
-        we = (struct vio_waitevent *)event->xCorrelationToken;
-        switch (event->xSubtype & VIOMINOR_SUBTYPE_MASK) {
-        case viotapegetinfo:
-                we->rc = tevent->sub_type_result;
-                complete(&we->com);
-                break;
-        default:
-                printk(KERN_WARNING "handle_tape_event: weird ack\n");
-        }
-}
-
-static void __init get_viotape_info(struct device_node *vio_root)
-{
-        HvLpEvent_Rc hvrc;
-        u32 unit;
-        struct vio_resource *unitinfo;
-        dma_addr_t unitinfo_dmaaddr;
-        size_t len = sizeof(*unitinfo) * HVMAXARCHITECTEDVIRTUALTAPES;
-        struct vio_waitevent we;
-        int ret;
-
-        init_completion(&we.com);
-
-        ret = viopath_open(viopath_hostLp, viomajorsubtype_tape, 2);
-        if (ret) {
-                printk(KERN_WARNING "get_viotape_info: "
-                        "error on viopath_open to hostlp %d\n", ret);
-                return;
-        }
-
-        vio_setHandler(viomajorsubtype_tape, handle_tape_event);
-
-        unitinfo = iseries_hv_alloc(len, &unitinfo_dmaaddr, GFP_ATOMIC);
-        if (!unitinfo)
-                goto clear_handler;
-
-        memset(unitinfo, 0, len);
-
-        hvrc = HvCallEvent_signalLpEventFast(viopath_hostLp,
-                        HvLpEvent_Type_VirtualIo,
-                        viomajorsubtype_tape | viotapegetinfo,
-                        HvLpEvent_AckInd_DoAck, HvLpEvent_AckType_ImmediateAck,
-                        viopath_sourceinst(viopath_hostLp),
-                        viopath_targetinst(viopath_hostLp),
-                        (u64)(unsigned long)&we, VIOVERSION << 16,
-                        unitinfo_dmaaddr, len, 0, 0);
-        if (hvrc != HvLpEvent_Rc_Good) {
-                printk(KERN_WARNING "get_viotape_info: hv error on op %d\n",
-                                (int)hvrc);
-                goto hv_free;
-        }
-
-        wait_for_completion(&we.com);
-
-        for (unit = 0; (unit < HVMAXARCHITECTEDVIRTUALTAPES) &&
-                        unitinfo[unit].rsrcname[0]; unit++) {
-                if (!do_device_node(vio_root, "viotape", FIRST_VIOTAPE + unit,
-                                unit, "byte", "IBM,iSeries-viotape",
-                                &unitinfo[unit]))
-                        break;
-        }
-
- hv_free:
-        iseries_hv_free(len, unitinfo, unitinfo_dmaaddr);
- clear_handler:
-        vio_clearHandler(viomajorsubtype_tape);
-        viopath_close(viopath_hostLp, viomajorsubtype_tape, 2);
-}
-
-static int __init iseries_vio_init(void)
-{
-        struct device_node *vio_root;
-        int ret = -ENODEV;
-
-        if (!firmware_has_feature(FW_FEATURE_ISERIES))
-                goto out;
-
-        iommu_vio_init();
-
-        vio_root = of_find_node_by_path("/vdevice");
-        if (!vio_root)
-                goto out;
-
-        if (viopath_hostLp == HvLpIndexInvalid) {
-                vio_set_hostlp();
-                /* If we don't have a host, bail out */
-                if (viopath_hostLp == HvLpIndexInvalid)
-                        goto put_node;
-        }
-
-        get_viodasd_info(vio_root);
-        get_viocd_info(vio_root);
-        get_viotape_info(vio_root);
-
-        ret = 0;
-
- put_node:
-        of_node_put(vio_root);
- out:
-        return ret;
-}
-arch_initcall(iseries_vio_init);
diff --git a/arch/powerpc/platforms/iseries/viopath.c b/arch/powerpc/platforms/iseries/viopath.c
deleted file mode 100644
index 40dad0840eb..00000000000
--- a/arch/powerpc/platforms/iseries/viopath.c
+++ /dev/null
@@ -1,677 +0,0 @@
-/* -*- linux-c -*-
- *
- *  iSeries Virtual I/O Message Path code
- *
- *  Authors: Dave Boutcher <boutcher@us.ibm.com>
- *           Ryan Arnold <ryanarn@us.ibm.com>
- *           Colin Devilbiss <devilbis@us.ibm.com>
- *
- * (C) Copyright 2000-2005 IBM Corporation
- *
- * This code is used by the iSeries virtual disk, cd,
- * tape, and console to communicate with OS/400 in another
- * partition.
- *
- * This program is free software;  you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) anyu later version.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
- * General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software Foundation,
- * Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- */
-#include <linux/export.h>
-#include <linux/kernel.h>
-#include <linux/slab.h>
-#include <linux/errno.h>
-#include <linux/vmalloc.h>
-#include <linux/string.h>
-#include <linux/proc_fs.h>
-#include <linux/dma-mapping.h>
-#include <linux/wait.h>
-#include <linux/seq_file.h>
-#include <linux/interrupt.h>
-#include <linux/completion.h>
-
-#include <asm/system.h>
-#include <asm/uaccess.h>
-#include <asm/prom.h>
-#include <asm/firmware.h>
-#include <asm/iseries/hv_types.h>
-#include <asm/iseries/hv_lp_event.h>
-#include <asm/iseries/hv_lp_config.h>
-#include <asm/iseries/mf.h>
-#include <asm/iseries/vio.h>
-
-/* Status of the path to each other partition in the system.
- * This is overkill, since we will only ever establish connections
- * to our hosting partition and the primary partition on the system.
- * But this allows for other support in the future.
- */
-static struct viopathStatus {
-        int isOpen;             /* Did we open the path?            */
-        int isActive;           /* Do we have a mon msg outstanding */
-        int users[VIO_MAX_SUBTYPES];
-        HvLpInstanceId mSourceInst;
-        HvLpInstanceId mTargetInst;
-        int numberAllocated;
-} viopathStatus[HVMAXARCHITECTEDLPS];
-
-static DEFINE_SPINLOCK(statuslock);
-
-/*
- * For each kind of event we allocate a buffer that is
- * guaranteed not to cross a page boundary
- */
-static unsigned char event_buffer[VIO_MAX_SUBTYPES * 256]
-        __attribute__((__aligned__(4096)));
-static atomic_t event_buffer_available[VIO_MAX_SUBTYPES];
-static int event_buffer_initialised;
-
-static void handleMonitorEvent(struct HvLpEvent *event);
-
-/*
- * We use this structure to handle asynchronous responses.  The caller
- * blocks on the semaphore and the handler posts the semaphore.  However,
- * if system_state is not SYSTEM_RUNNING, then wait_atomic is used ...
- */
-struct alloc_parms {
-        struct completion done;
-        int number;
-        atomic_t wait_atomic;
-        int used_wait_atomic;
-};
-
-/* Put a sequence number in each mon msg.  The value is not
- * important.  Start at something other than 0 just for
- * readability.  wrapping this is ok.
- */
-static u8 viomonseq = 22;
-
-/* Our hosting logical partition.  We get this at startup
- * time, and different modules access this variable directly.
- */
-HvLpIndex viopath_hostLp = HvLpIndexInvalid;
-EXPORT_SYMBOL(viopath_hostLp);
-HvLpIndex viopath_ourLp = HvLpIndexInvalid;
-EXPORT_SYMBOL(viopath_ourLp);
-
-/* For each kind of incoming event we set a pointer to a
- * routine to call.
- */
-static vio_event_handler_t *vio_handler[VIO_MAX_SUBTYPES];
-
-#define VIOPATH_KERN_WARN       KERN_WARNING "viopath: "
-#define VIOPATH_KERN_INFO       KERN_INFO "viopath: "
-
-static int proc_viopath_show(struct seq_file *m, void *v)
-{
-        char *buf;
-        u16 vlanMap;
-        dma_addr_t handle;
-        HvLpEvent_Rc hvrc;
-        DECLARE_COMPLETION_ONSTACK(done);
-        struct device_node *node;
-        const char *sysid;
-
-        buf = kzalloc(HW_PAGE_SIZE, GFP_KERNEL);
-        if (!buf)
-                return 0;
-
-        handle = iseries_hv_map(buf, HW_PAGE_SIZE, DMA_FROM_DEVICE);
-
-        hvrc = HvCallEvent_signalLpEventFast(viopath_hostLp,
-                        HvLpEvent_Type_VirtualIo,
-                        viomajorsubtype_config | vioconfigget,
-                        HvLpEvent_AckInd_DoAck, HvLpEvent_AckType_ImmediateAck,
-                        viopath_sourceinst(viopath_hostLp),
-                        viopath_targetinst(viopath_hostLp),
-                        (u64)(unsigned long)&done, VIOVERSION << 16,
-                        ((u64)handle) << 32, HW_PAGE_SIZE, 0, 0);
-
-        if (hvrc != HvLpEvent_Rc_Good)
-                printk(VIOPATH_KERN_WARN "hv error on op %d\n", (int)hvrc);
-
-        wait_for_completion(&done);
-
-        vlanMap = HvLpConfig_getVirtualLanIndexMap();
-
-        buf[HW_PAGE_SIZE-1] = '\0';
-        seq_printf(m, "%s", buf);
-
-        iseries_hv_unmap(handle, HW_PAGE_SIZE, DMA_FROM_DEVICE);
-        kfree(buf);
-
-        seq_printf(m, "AVAILABLE_VETH=%x\n", vlanMap);
-
-        node = of_find_node_by_path("/");
-        sysid = NULL;
-        if (node != NULL)
-                sysid = of_get_property(node, "system-id", NULL);
-
-        if (sysid == NULL)
-                seq_printf(m, "SRLNBR=<UNKNOWN>\n");
-        else
-                /* Skip "IBM," on front of serial number, see dt.c */
-                seq_printf(m, "SRLNBR=%s\n", sysid + 4);
-
-        of_node_put(node);
-
-        return 0;
-}
-
-static int proc_viopath_open(struct inode *inode, struct file *file)
-{
-        return single_open(file, proc_viopath_show, NULL);
-}
-
-static const struct file_operations proc_viopath_operations = {
-        .open           = proc_viopath_open,
-        .read           = seq_read,
-        .llseek         = seq_lseek,
-        .release        = single_release,
-};
-
-static int __init vio_proc_init(void)
-{
-        if (!firmware_has_feature(FW_FEATURE_ISERIES))
-                return 0;
-
-        proc_create("iSeries/config", 0, NULL, &proc_viopath_operations);
-        return 0;
-}
-__initcall(vio_proc_init);
-
-/* See if a given LP is active.  Allow for invalid lps to be passed in
- * and just return invalid
- */
-int viopath_isactive(HvLpIndex lp)
-{
-        if (lp == HvLpIndexInvalid)
-                return 0;
-        if (lp < HVMAXARCHITECTEDLPS)
-                return viopathStatus[lp].isActive;
-        else
-                return 0;
-}
-EXPORT_SYMBOL(viopath_isactive);
-
-/*
- * We cache the source and target instance ids for each
- * partition.
- */
-HvLpInstanceId viopath_sourceinst(HvLpIndex lp)
-{
-        return viopathStatus[lp].mSourceInst;
-}
-EXPORT_SYMBOL(viopath_sourceinst);
-
-HvLpInstanceId viopath_targetinst(HvLpIndex lp)
-{
-        return viopathStatus[lp].mTargetInst;
-}
-EXPORT_SYMBOL(viopath_targetinst);
-
-/*
- * Send a monitor message.  This is a message with the acknowledge
- * bit on that the other side will NOT explicitly acknowledge.  When
- * the other side goes down, the hypervisor will acknowledge any
- * outstanding messages....so we will know when the other side dies.
- */
-static void sendMonMsg(HvLpIndex remoteLp)
-{
-        HvLpEvent_Rc hvrc;
-
-        viopathStatus[remoteLp].mSourceInst =
-                HvCallEvent_getSourceLpInstanceId(remoteLp,
-                                HvLpEvent_Type_VirtualIo);
-        viopathStatus[remoteLp].mTargetInst =
-                HvCallEvent_getTargetLpInstanceId(remoteLp,
-                                HvLpEvent_Type_VirtualIo);
-
-        /*
-         * Deliberately ignore the return code here.  if we call this
-         * more than once, we don't care.
-         */
-        vio_setHandler(viomajorsubtype_monitor, handleMonitorEvent);
-
-        hvrc = HvCallEvent_signalLpEventFast(remoteLp, HvLpEvent_Type_VirtualIo,
-                        viomajorsubtype_monitor, HvLpEvent_AckInd_DoAck,
-                        HvLpEvent_AckType_DeferredAck,
-                        viopathStatus[remoteLp].mSourceInst,
-                        viopathStatus[remoteLp].mTargetInst,
-                        viomonseq++, 0, 0, 0, 0, 0);
-
-        if (hvrc == HvLpEvent_Rc_Good)
-                viopathStatus[remoteLp].isActive = 1;
-        else {
-                printk(VIOPATH_KERN_WARN "could not connect to partition %d\n",
-                                remoteLp);
-                viopathStatus[remoteLp].isActive = 0;
-        }
-}
-
-static void handleMonitorEvent(struct HvLpEvent *event)
-{
-        HvLpIndex remoteLp;
-        int i;
-
-        /*
-         * This handler is _also_ called as part of the loop
-         * at the end of this routine, so it must be able to
-         * ignore NULL events...
-         */
-        if (!event)
-                return;
-
-        /*
-         * First see if this is just a normal monitor message from the
-         * other partition
-         */
-        if (hvlpevent_is_int(event)) {
-                remoteLp = event->xSourceLp;
-                if (!viopathStatus[remoteLp].isActive)
-                        sendMonMsg(remoteLp);
-                return;
-        }
-
-        /*
-         * This path is for an acknowledgement; the other partition
-         * died
-         */
-        remoteLp = event->xTargetLp;
-        if ((event->xSourceInstanceId != viopathStatus[remoteLp].mSourceInst) ||
-            (event->xTargetInstanceId != viopathStatus[remoteLp].mTargetInst)) {
-                printk(VIOPATH_KERN_WARN "ignoring ack....mismatched instances\n");
-                return;
-        }
-
-        printk(VIOPATH_KERN_WARN "partition %d ended\n", remoteLp);
-
-        viopathStatus[remoteLp].isActive = 0;
-
-        /*
-         * For each active handler, pass them a NULL
-         * message to indicate that the other partition
-         * died
-         */
-        for (i = 0; i < VIO_MAX_SUBTYPES; i++) {
-                if (vio_handler[i] != NULL)
-                        (*vio_handler[i])(NULL);
-        }
-}
-
-int vio_setHandler(int subtype, vio_event_handler_t *beh)
-{
-        subtype = subtype >> VIOMAJOR_SUBTYPE_SHIFT;
-        if ((subtype < 0) || (subtype >= VIO_MAX_SUBTYPES))
-                return -EINVAL;
-        if (vio_handler[subtype] != NULL)
-                return -EBUSY;
-        vio_handler[subtype] = beh;
-        return 0;
-}
-EXPORT_SYMBOL(vio_setHandler);
-
-int vio_clearHandler(int subtype)
-{
-        subtype = subtype >> VIOMAJOR_SUBTYPE_SHIFT;
-        if ((subtype < 0) || (subtype >= VIO_MAX_SUBTYPES))
-                return -EINVAL;
-        if (vio_handler[subtype] == NULL)
-                return -EAGAIN;
-        vio_handler[subtype] = NULL;
-        return 0;
-}
-EXPORT_SYMBOL(vio_clearHandler);
-
-static void handleConfig(struct HvLpEvent *event)
-{
-        if (!event)
-                return;
-        if (hvlpevent_is_int(event)) {
-                printk(VIOPATH_KERN_WARN
-                       "unexpected config request from partition %d",
-                       event->xSourceLp);
-
-                if (hvlpevent_need_ack(event)) {
-                        event->xRc = HvLpEvent_Rc_InvalidSubtype;
-                        HvCallEvent_ackLpEvent(event);
-                }
-                return;
-        }
-
-        complete((struct completion *)event->xCorrelationToken);
-}
-
-/*
- * Initialization of the hosting partition
- */
-void vio_set_hostlp(void)
-{
-        /*
-         * If this has already been set then we DON'T want to either change
-         * it or re-register the proc file system
-         */
-        if (viopath_hostLp != HvLpIndexInvalid)
-                return;
-
-        /*
-         * Figure out our hosting partition.  This isn't allowed to change
-         * while we're active
-         */
-        viopath_ourLp = HvLpConfig_getLpIndex();
-        viopath_hostLp = HvLpConfig_getHostingLpIndex(viopath_ourLp);
-
-        if (viopath_hostLp != HvLpIndexInvalid)
-                vio_setHandler(viomajorsubtype_config, handleConfig);
-}
-EXPORT_SYMBOL(vio_set_hostlp);
-
-static void vio_handleEvent(struct HvLpEvent *event)
-{
-        HvLpIndex remoteLp;
-        int subtype = (event->xSubtype & VIOMAJOR_SUBTYPE_MASK)
-                >> VIOMAJOR_SUBTYPE_SHIFT;
-
-        if (hvlpevent_is_int(event)) {
-                remoteLp = event->xSourceLp;
-                /*
-                 * The isActive is checked because if the hosting partition
-                 * went down and came back up it would not be active but it
-                 * would have different source and target instances, in which
-                 * case we'd want to reset them.  This case really protects
-                 * against an unauthorized active partition sending interrupts
-                 * or acks to this linux partition.
-                 */
-                if (viopathStatus[remoteLp].isActive
-                    && (event->xSourceInstanceId !=
-                        viopathStatus[remoteLp].mTargetInst)) {
-                        printk(VIOPATH_KERN_WARN
-                               "message from invalid partition. "
-                               "int msg rcvd, source inst (%d) doesn't match (%d)\n",
-                               viopathStatus[remoteLp].mTargetInst,
-                               event->xSourceInstanceId);
-                        return;
-                }
-
-                if (viopathStatus[remoteLp].isActive
-                    && (event->xTargetInstanceId !=
-                        viopathStatus[remoteLp].mSourceInst)) {
-                        printk(VIOPATH_KERN_WARN
-                               "message from invalid partition. "
-                               "int msg rcvd, target inst (%d) doesn't match (%d)\n",
-                               viopathStatus[remoteLp].mSourceInst,
-                               event->xTargetInstanceId);
-                        return;
-                }
-        } else {
-                remoteLp = event->xTargetLp;
-                if (event->xSourceInstanceId !=
-                    viopathStatus[remoteLp].mSourceInst) {
-                        printk(VIOPATH_KERN_WARN
-                               "message from invalid partition. "
-                               "ack msg rcvd, source inst (%d) doesn't match (%d)\n",
-                               viopathStatus[remoteLp].mSourceInst,
-                               event->xSourceInstanceId);
-                        return;
-                }
-
-                if (event->xTargetInstanceId !=
-                    viopathStatus[remoteLp].mTargetInst) {
-                        printk(VIOPATH_KERN_WARN
-                               "message from invalid partition. "
-                               "viopath: ack msg rcvd, target inst (%d) doesn't match (%d)\n",
-                               viopathStatus[remoteLp].mTargetInst,
-                               event->xTargetInstanceId);
-                        return;
-                }
-        }
-
-        if (vio_handler[subtype] == NULL) {
-                printk(VIOPATH_KERN_WARN
-                       "unexpected virtual io event subtype %d from partition %d\n",
-                       event->xSubtype, remoteLp);
-                /* No handler.  Ack if necessary */
-                if (hvlpevent_is_int(event) && hvlpevent_need_ack(event)) {
-                        event->xRc = HvLpEvent_Rc_InvalidSubtype;
-                        HvCallEvent_ackLpEvent(event);
-                }
-                return;
-        }
-
-        /* This innocuous little line is where all the real work happens */
-        (*vio_handler[subtype])(event);
-}
-
-static void viopath_donealloc(void *parm, int number)
-{
-        struct alloc_parms *parmsp = parm;
-
-        parmsp->number = number;
-        if (parmsp->used_wait_atomic)
-                atomic_set(&parmsp->wait_atomic, 0);
-        else
-                complete(&parmsp->done);
-}
-
-static int allocateEvents(HvLpIndex remoteLp, int numEvents)
-{
-        struct alloc_parms parms;
-
-        if (system_state != SYSTEM_RUNNING) {
-                parms.used_wait_atomic = 1;
-                atomic_set(&parms.wait_atomic, 1);
-        } else {
-                parms.used_wait_atomic = 0;
-                init_completion(&parms.done);
-        }
-        mf_allocate_lp_events(remoteLp, HvLpEvent_Type_VirtualIo, 250,  /* It would be nice to put a real number here! */
-                            numEvents, &viopath_donealloc, &parms);
-        if (system_state != SYSTEM_RUNNING) {
-                while (atomic_read(&parms.wait_atomic))
-                        mb();
-        } else
-                wait_for_completion(&parms.done);
-        return parms.number;
-}
-
-int viopath_open(HvLpIndex remoteLp, int subtype, int numReq)
-{
-        int i;
-        unsigned long flags;
-        int tempNumAllocated;
-
-        if ((remoteLp >= HVMAXARCHITECTEDLPS) || (remoteLp == HvLpIndexInvalid))
-                return -EINVAL;
-
-        subtype = subtype >> VIOMAJOR_SUBTYPE_SHIFT;
-        if ((subtype < 0) || (subtype >= VIO_MAX_SUBTYPES))
-                return -EINVAL;
-
-        spin_lock_irqsave(&statuslock, flags);
-
-        if (!event_buffer_initialised) {
-                for (i = 0; i < VIO_MAX_SUBTYPES; i++)
-                        atomic_set(&event_buffer_available[i], 1);
-                event_buffer_initialised = 1;
-        }
-
-        viopathStatus[remoteLp].users[subtype]++;
-
-        if (!viopathStatus[remoteLp].isOpen) {
-                viopathStatus[remoteLp].isOpen = 1;
-                HvCallEvent_openLpEventPath(remoteLp, HvLpEvent_Type_VirtualIo);
-
-                /*
-                 * Don't hold the spinlock during an operation that
-                 * can sleep.
-                 */
-                spin_unlock_irqrestore(&statuslock, flags);
-                tempNumAllocated = allocateEvents(remoteLp, 1);
-                spin_lock_irqsave(&statuslock, flags);
-
-                viopathStatus[remoteLp].numberAllocated += tempNumAllocated;
-
-                if (viopathStatus[remoteLp].numberAllocated == 0) {
-                        HvCallEvent_closeLpEventPath(remoteLp,
-                                        HvLpEvent_Type_VirtualIo);
-
-                        spin_unlock_irqrestore(&statuslock, flags);
-                        return -ENOMEM;
-                }
-
-                viopathStatus[remoteLp].mSourceInst =
-                        HvCallEvent_getSourceLpInstanceId(remoteLp,
-                                        HvLpEvent_Type_VirtualIo);
-                viopathStatus[remoteLp].mTargetInst =
-                        HvCallEvent_getTargetLpInstanceId(remoteLp,
-                                        HvLpEvent_Type_VirtualIo);
-                HvLpEvent_registerHandler(HvLpEvent_Type_VirtualIo,
-                                          &vio_handleEvent);
-                sendMonMsg(remoteLp);
-                printk(VIOPATH_KERN_INFO "opening connection to partition %d, "
-                                "setting sinst %d, tinst %d\n",
-                                remoteLp, viopathStatus[remoteLp].mSourceInst,
-                                viopathStatus[remoteLp].mTargetInst);
-        }
-
-        spin_unlock_irqrestore(&statuslock, flags);
-        tempNumAllocated = allocateEvents(remoteLp, numReq);
-        spin_lock_irqsave(&statuslock, flags);
-        viopathStatus[remoteLp].numberAllocated += tempNumAllocated;
-        spin_unlock_irqrestore(&statuslock, flags);
-
-        return 0;
-}
-EXPORT_SYMBOL(viopath_open);
-
-int viopath_close(HvLpIndex remoteLp, int subtype, int numReq)
-{
-        unsigned long flags;
-        int i;
-        int numOpen;
-        struct alloc_parms parms;
-
-        if ((remoteLp >= HVMAXARCHITECTEDLPS) || (remoteLp == HvLpIndexInvalid))
-                return -EINVAL;
-
-        subtype = subtype >> VIOMAJOR_SUBTYPE_SHIFT;
-        if ((subtype < 0) || (subtype >= VIO_MAX_SUBTYPES))
-                return -EINVAL;
-
-        spin_lock_irqsave(&statuslock, flags);
-        /*
-         * If the viopath_close somehow gets called before a
-         * viopath_open it could decrement to -1 which is a non
-         * recoverable state so we'll prevent this from
-         * happening.
-         */
-        if (viopathStatus[remoteLp].users[subtype] > 0)
-                viopathStatus[remoteLp].users[subtype]--;
-
-        spin_unlock_irqrestore(&statuslock, flags);
-
-        parms.used_wait_atomic = 0;
-        init_completion(&parms.done);
-        mf_deallocate_lp_events(remoteLp, HvLpEvent_Type_VirtualIo,
-                              numReq, &viopath_donealloc, &parms);
-        wait_for_completion(&parms.done);
-
-        spin_lock_irqsave(&statuslock, flags);
-        for (i = 0, numOpen = 0; i < VIO_MAX_SUBTYPES; i++)
-                numOpen += viopathStatus[remoteLp].users[i];
-
-        if ((viopathStatus[remoteLp].isOpen) && (numOpen == 0)) {
-                printk(VIOPATH_KERN_INFO "closing connection to partition %d\n",
-                                remoteLp);
-
-                HvCallEvent_closeLpEventPath(remoteLp,
-                                             HvLpEvent_Type_VirtualIo);
-                viopathStatus[remoteLp].isOpen = 0;
-                viopathStatus[remoteLp].isActive = 0;
-
-                for (i = 0; i < VIO_MAX_SUBTYPES; i++)
-                        atomic_set(&event_buffer_available[i], 0);
-                event_buffer_initialised = 0;
-        }
-        spin_unlock_irqrestore(&statuslock, flags);
-        return 0;
-}
-EXPORT_SYMBOL(viopath_close);
-
-void *vio_get_event_buffer(int subtype)
-{
-        subtype = subtype >> VIOMAJOR_SUBTYPE_SHIFT;
-        if ((subtype < 0) || (subtype >= VIO_MAX_SUBTYPES))
-                return NULL;
-
-        if (atomic_dec_if_positive(&event_buffer_available[subtype]) == 0)
-                return &event_buffer[subtype * 256];
-        else
-                return NULL;
-}
-EXPORT_SYMBOL(vio_get_event_buffer);
-
-void vio_free_event_buffer(int subtype, void *buffer)
-{
-        subtype = subtype >> VIOMAJOR_SUBTYPE_SHIFT;
-        if ((subtype < 0) || (subtype >= VIO_MAX_SUBTYPES)) {
-                printk(VIOPATH_KERN_WARN
-                       "unexpected subtype %d freeing event buffer\n", subtype);
-                return;
-        }
-
-        if (atomic_read(&event_buffer_available[subtype]) != 0) {
-                printk(VIOPATH_KERN_WARN
-                       "freeing unallocated event buffer, subtype %d\n",
-                       subtype);
-                return;
-        }
-
-        if (buffer != &event_buffer[subtype * 256]) {
-                printk(VIOPATH_KERN_WARN
-                       "freeing invalid event buffer, subtype %d\n", subtype);
-        }
-
-        atomic_set(&event_buffer_available[subtype], 1);
-}
-EXPORT_SYMBOL(vio_free_event_buffer);
-
-static const struct vio_error_entry vio_no_error =
-    { 0, 0, "Non-VIO Error" };
-static const struct vio_error_entry vio_unknown_error =
-    { 0, EIO, "Unknown Error" };
-
-static const struct vio_error_entry vio_default_errors[] = {
-        {0x0001, EIO, "No Connection"},
-        {0x0002, EIO, "No Receiver"},
-        {0x0003, EIO, "No Buffer Available"},
-        {0x0004, EBADRQC, "Invalid Message Type"},
-        {0x0000, 0, NULL},
-};
-
-const struct vio_error_entry *vio_lookup_rc(
-                const struct vio_error_entry *local_table, u16 rc)
-{
-        const struct vio_error_entry *cur;
-
-        if (!rc)
-                return &vio_no_error;
-        if (local_table)
-                for (cur = local_table; cur->rc; ++cur)
-                        if (cur->rc == rc)
-                                return cur;
-        for (cur = vio_default_errors; cur->rc; ++cur)
-                if (cur->rc == rc)
-                        return cur;
-        return &vio_unknown_error;
-}
-EXPORT_SYMBOL(vio_lookup_rc);
diff --git a/arch/powerpc/platforms/iseries/vpd_areas.h b/arch/powerpc/platforms/iseries/vpd_areas.h
deleted file mode 100644
index feb001f3a5f..00000000000
--- a/arch/powerpc/platforms/iseries/vpd_areas.h
+++ /dev/null
@@ -1,88 +0,0 @@
-/*
- * Copyright (C) 2001  Mike Corrigan IBM Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
- */
-#ifndef _ISERIES_VPD_AREAS_H
-#define _ISERIES_VPD_AREAS_H
-
-/*
- * This file defines the address and length of all of the VPD area passed to
- * the OS from PLIC (most of which start from the SP).
- */
-
-#include <asm/types.h>
-
-/* VPD Entry index is carved in stone - cannot be changed (easily). */
-#define ItVpdCecVpd                             0
-#define ItVpdDynamicSpace                       1
-#define ItVpdExtVpd                             2
-#define ItVpdExtVpdOnPanel                      3
-#define ItVpdFirstPaca                          4
-#define ItVpdIoVpd                              5
-#define ItVpdIplParms                           6
-#define ItVpdMsVpd                              7
-#define ItVpdPanelVpd                           8
-#define ItVpdLpNaca                             9
-#define ItVpdBackplaneAndMaybeClockCardVpd      10
-#define ItVpdRecoveryLogBuffer                  11
-#define ItVpdSpCommArea                         12
-#define ItVpdSpLogBuffer                        13
-#define ItVpdSpLogBufferSave                    14
-#define ItVpdSpCardVpd                          15
-#define ItVpdFirstProcVpd                       16
-#define ItVpdApModelVpd                         17
-#define ItVpdClockCardVpd                       18
-#define ItVpdBusExtCardVpd                      19
-#define ItVpdProcCapacityVpd                    20
-#define ItVpdInteractiveCapacityVpd             21
-#define ItVpdFirstSlotLabel                     22
-#define ItVpdFirstLpQueue                       23
-#define ItVpdFirstL3CacheVpd                    24
-#define ItVpdFirstProcFruVpd                    25
-
-#define ItVpdMaxEntries                         26
-
-#define ItDmaMaxEntries                         10
-
-#define ItVpdAreasMaxSlotLabels                 192
-
-
-struct ItVpdAreas {
-        u32     xSlicDesc;              // Descriptor                   000-003
-        u16     xSlicSize;              // Size of this control block   004-005
-        u16     xPlicAdjustVpdLens:1;   // Flag to indicate new interface006-007
-        u16     xRsvd1:15;              // Reserved bits                ...
-        u16     xSlicVpdEntries;        // Number of VPD entries        008-009
-        u16     xSlicDmaEntries;        // Number of DMA entries        00A-00B
-        u16     xSlicMaxLogicalProcs;   // Maximum logical processors   00C-00D
-        u16     xSlicMaxPhysicalProcs;  // Maximum physical processors  00E-00F
-        u16     xSlicDmaToksOffset;     // Offset into this of array    010-011
-        u16     xSlicVpdAdrsOffset;     // Offset into this of array    012-013
-        u16     xSlicDmaLensOffset;     // Offset into this of array    014-015
-        u16     xSlicVpdLensOffset;     // Offset into this of array    016-017
-        u16     xSlicMaxSlotLabels;     // Maximum number of slot labels018-019
-        u16     xSlicMaxLpQueues;       // Maximum number of LP Queues  01A-01B
-        u8      xRsvd2[4];              // Reserved                     01C-01F
-        u64     xRsvd3[12];             // Reserved                     020-07F
-        u32     xPlicDmaLens[ItDmaMaxEntries];// Array of DMA lengths   080-0A7
-        u32     xPlicDmaToks[ItDmaMaxEntries];// Array of DMA tokens    0A8-0CF
-        u32     xSlicVpdLens[ItVpdMaxEntries];// Array of VPD lengths   0D0-12F
-        const void *xSlicVpdAdrs[ItVpdMaxEntries];// Array of VPD buffers 130-1EF
-};
-
-extern const struct ItVpdAreas  itVpdAreas;
-
-#endif /* _ISERIES_VPD_AREAS_H */
diff --git a/arch/powerpc/platforms/maple/pci.c b/arch/powerpc/platforms/maple/pci.c
index 401e3f3f74c..465ee8f5c08 100644
--- a/arch/powerpc/platforms/maple/pci.c
+++ b/arch/powerpc/platforms/maple/pci.c
@@ -620,7 +620,7 @@ void __init maple_pci_init(void)
         }
 
         /* Tell pci.c to not change any resource allocations.  */
-        pci_probe_only = 1;
+        pci_add_flags(PCI_PROBE_ONLY);
 }
 
 int maple_pci_get_legacy_ide_irq(struct pci_dev *pdev, int channel)
diff --git a/arch/powerpc/platforms/maple/setup.c b/arch/powerpc/platforms/maple/setup.c
index 0bcbfe7b2c5..3b7545a51aa 100644
--- a/arch/powerpc/platforms/maple/setup.c
+++ b/arch/powerpc/platforms/maple/setup.c
@@ -262,7 +262,7 @@ static void __init maple_init_IRQ(void)
                 flags |= MPIC_BIG_ENDIAN;
 
         /* XXX Maple specific bits */
-        flags |= MPIC_U3_HT_IRQS | MPIC_WANTS_RESET;
+        flags |= MPIC_U3_HT_IRQS;
         /* All U3/U4 are big-endian, older SLOF firmware doesn't encode this */
         flags |= MPIC_BIG_ENDIAN;
 
diff --git a/arch/powerpc/platforms/pasemi/pci.c b/arch/powerpc/platforms/pasemi/pci.c
index b6a0ec45c69..aa862713258 100644
--- a/arch/powerpc/platforms/pasemi/pci.c
+++ b/arch/powerpc/platforms/pasemi/pci.c
@@ -229,9 +229,6 @@ void __init pas_pci_init(void)
 
         /* Setup the linkage between OF nodes and PHBs */
         pci_devs_phb_init();
-
-        /* Use the common resource allocation mechanism */
-        pci_probe_only = 1;
 }
 
 void __iomem *pasemi_pci_getcfgaddr(struct pci_dev *dev, int offset)
diff --git a/arch/powerpc/platforms/pasemi/setup.c b/arch/powerpc/platforms/pasemi/setup.c
index 98b7a7c1317..e777ad471a4 100644
--- a/arch/powerpc/platforms/pasemi/setup.c
+++ b/arch/powerpc/platforms/pasemi/setup.c
@@ -224,7 +224,7 @@ static __init void pas_init_IRQ(void)
         openpic_addr = of_read_number(opprop, naddr);
         printk(KERN_DEBUG "OpenPIC addr: %lx\n", openpic_addr);
 
-        mpic_flags = MPIC_LARGE_VECTORS | MPIC_NO_BIAS;
+        mpic_flags = MPIC_LARGE_VECTORS | MPIC_NO_BIAS | MPIC_NO_RESET;
 
         nmiprop = of_get_property(mpic_node, "nmi-source", NULL);
         if (nmiprop)
diff --git a/arch/powerpc/platforms/powermac/nvram.c b/arch/powerpc/platforms/powermac/nvram.c
index 54d227127c9..da18b26dcc6 100644
--- a/arch/powerpc/platforms/powermac/nvram.c
+++ b/arch/powerpc/platforms/powermac/nvram.c
@@ -279,7 +279,7 @@ static u32 core99_check(u8* datas)
 
 static int sm_erase_bank(int bank)
 {
-        int stat, i;
+        int stat;
         unsigned long timeout;
 
         u8 __iomem *base = (u8 __iomem *)nvram_data + core99_bank*NVRAM_SIZE;
@@ -301,11 +301,10 @@ static int sm_erase_bank(int bank)
         out_8(base, SM_FLASH_CMD_CLEAR_STATUS);
         out_8(base, SM_FLASH_CMD_RESET);
 
-        for (i=0; i<NVRAM_SIZE; i++)
-                if (base[i] != 0xff) {
-                        printk(KERN_ERR "nvram: Sharp/Micron flash erase failed !\n");
-                        return -ENXIO;
-                }
+        if (memchr_inv(base, 0xff, NVRAM_SIZE)) {
+                printk(KERN_ERR "nvram: Sharp/Micron flash erase failed !\n");
+                return -ENXIO;
+        }
         return 0;
 }
 
@@ -336,17 +335,16 @@ static int sm_write_bank(int bank, u8* datas)
         }
         out_8(base, SM_FLASH_CMD_CLEAR_STATUS);
         out_8(base, SM_FLASH_CMD_RESET);
-        for (i=0; i<NVRAM_SIZE; i++)
-                if (base[i] != datas[i]) {
-                        printk(KERN_ERR "nvram: Sharp/Micron flash write failed !\n");
-                        return -ENXIO;
-                }
+        if (memcmp(base, datas, NVRAM_SIZE)) {
+                printk(KERN_ERR "nvram: Sharp/Micron flash write failed !\n");
+                return -ENXIO;
+        }
         return 0;
 }
 
 static int amd_erase_bank(int bank)
 {
-        int i, stat = 0;
+        int stat = 0;
         unsigned long timeout;
 
         u8 __iomem *base = (u8 __iomem *)nvram_data + core99_bank*NVRAM_SIZE;
@@ -382,12 +380,11 @@ static int amd_erase_bank(int bank)
         /* Reset */
         out_8(base, 0xf0);
         udelay(1);
-        
-        for (i=0; i<NVRAM_SIZE; i++)
-                if (base[i] != 0xff) {
-                        printk(KERN_ERR "nvram: AMD flash erase failed !\n");
-                        return -ENXIO;
-                }
+
+        if (memchr_inv(base, 0xff, NVRAM_SIZE)) {
+                printk(KERN_ERR "nvram: AMD flash erase failed !\n");
+                return -ENXIO;
+        }
         return 0;
 }
 
@@ -429,11 +426,10 @@ static int amd_write_bank(int bank, u8* datas)
         out_8(base, 0xf0);
         udelay(1);
 
-        for (i=0; i<NVRAM_SIZE; i++)
-                if (base[i] != datas[i]) {
-                        printk(KERN_ERR "nvram: AMD flash write failed !\n");
-                        return -ENXIO;
-                }
+        if (memcmp(base, datas, NVRAM_SIZE)) {
+                printk(KERN_ERR "nvram: AMD flash write failed !\n");
+                return -ENXIO;
+        }
         return 0;
 }
 
diff --git a/arch/powerpc/platforms/powermac/pci.c b/arch/powerpc/platforms/powermac/pci.c
index 31a7d3a7ce2..43bbe1bda93 100644
--- a/arch/powerpc/platforms/powermac/pci.c
+++ b/arch/powerpc/platforms/powermac/pci.c
@@ -1059,9 +1059,6 @@ void __init pmac_pci_init(void)
         }
         /* pmac_check_ht_link(); */
 
-        /* We can allocate missing resources if any */
-        pci_probe_only = 0;
-
 #else /* CONFIG_PPC64 */
         init_p2pbridge();
         init_second_ohare();
diff --git a/arch/powerpc/platforms/powermac/pic.c b/arch/powerpc/platforms/powermac/pic.c
index 92afc382a49..66ad93de1d5 100644
--- a/arch/powerpc/platforms/powermac/pic.c
+++ b/arch/powerpc/platforms/powermac/pic.c
@@ -457,7 +457,6 @@ static struct mpic * __init pmac_setup_one_mpic(struct device_node *np,
 
         pmac_call_feature(PMAC_FTR_ENABLE_MPIC, np, 0, 0);
 
-        flags |= MPIC_WANTS_RESET;
         if (of_get_property(np, "big-endian", NULL))
                 flags |= MPIC_BIG_ENDIAN;
 
diff --git a/arch/powerpc/platforms/powernv/pci-ioda.c b/arch/powerpc/platforms/powernv/pci-ioda.c
index 5e155dfc432..fbdd74dac3a 100644
--- a/arch/powerpc/platforms/powernv/pci-ioda.c
+++ b/arch/powerpc/platforms/powernv/pci-ioda.c
@@ -1299,15 +1299,14 @@ void __init pnv_pci_init_ioda1_phb(struct device_node *np)
         /* Setup MSI support */
         pnv_pci_init_ioda_msis(phb);
 
-        /* We set both probe_only and PCI_REASSIGN_ALL_RSRC. This is an
+        /* We set both PCI_PROBE_ONLY and PCI_REASSIGN_ALL_RSRC. This is an
          * odd combination which essentially means that we skip all resource
          * fixups and assignments in the generic code, and do it all
          * ourselves here
          */
-        pci_probe_only = 1;
         ppc_md.pcibios_fixup_phb = pnv_pci_ioda_fixup_phb;
         ppc_md.pcibios_enable_device_hook = pnv_pci_enable_device_hook;
-        pci_add_flags(PCI_REASSIGN_ALL_RSRC);
+        pci_add_flags(PCI_PROBE_ONLY | PCI_REASSIGN_ALL_RSRC);
 
         /* Reset IODA tables to a clean state */
         rc = opal_pci_reset(phb_id, OPAL_PCI_IODA_TABLE_RESET, OPAL_ASSERT_RESET);
diff --git a/arch/powerpc/platforms/powernv/pci.c b/arch/powerpc/platforms/powernv/pci.c
index f92b9ef7340..be3cfc5ceab 100644
--- a/arch/powerpc/platforms/powernv/pci.c
+++ b/arch/powerpc/platforms/powernv/pci.c
@@ -31,6 +31,7 @@
 #include <asm/iommu.h>
 #include <asm/tce.h>
 #include <asm/abs_addr.h>
+#include <asm/firmware.h>
 
 #include "powernv.h"
 #include "pci.h"
@@ -561,10 +562,7 @@ void __init pnv_pci_init(void)
 {
         struct device_node *np;
 
-        pci_set_flags(PCI_CAN_SKIP_ISA_ALIGN);
-
-        /* We do not want to just probe */
-        pci_probe_only = 0;
+        pci_add_flags(PCI_CAN_SKIP_ISA_ALIGN);
 
         /* OPAL absent, try POPAL first then RTAS detection of PHBs */
         if (!firmware_has_feature(FW_FEATURE_OPAL)) {
diff --git a/arch/powerpc/platforms/powernv/setup.c b/arch/powerpc/platforms/powernv/setup.c
index 467bd4ac682..db1ad1c8f68 100644
--- a/arch/powerpc/platforms/powernv/setup.c
+++ b/arch/powerpc/platforms/powernv/setup.c
@@ -31,7 +31,6 @@
 #include <asm/xics.h>
 #include <asm/rtas.h>
 #include <asm/opal.h>
-#include <asm/xics.h>
 
 #include "powernv.h"
 
diff --git a/arch/powerpc/platforms/pseries/Kconfig b/arch/powerpc/platforms/pseries/Kconfig
index f2556257bbd..aadbe4f6d53 100644
--- a/arch/powerpc/platforms/pseries/Kconfig
+++ b/arch/powerpc/platforms/pseries/Kconfig
@@ -73,7 +73,7 @@ config IO_EVENT_IRQ
 
 config LPARCFG
         bool "LPAR Configuration Data"
-        depends on PPC_PSERIES || PPC_ISERIES
+        depends on PPC_PSERIES
         help
         Provide system capacity information via human readable
         <key word>=<value> pairs through a /proc/ppc64/lparcfg interface.
diff --git a/arch/powerpc/platforms/pseries/Makefile b/arch/powerpc/platforms/pseries/Makefile
index 236db46b407..c222189f5bb 100644
--- a/arch/powerpc/platforms/pseries/Makefile
+++ b/arch/powerpc/platforms/pseries/Makefile
@@ -6,7 +6,8 @@ obj-y			:= lpar.o hvCall.o nvram.o reconfig.o \
                            firmware.o power.o dlpar.o mobility.o
 obj-$(CONFIG_SMP)       += smp.o
 obj-$(CONFIG_SCANLOG)   += scanlog.o
-obj-$(CONFIG_EEH)       += eeh.o eeh_cache.o eeh_driver.o eeh_event.o eeh_sysfs.o
+obj-$(CONFIG_EEH)       += eeh.o eeh_dev.o eeh_cache.o eeh_driver.o \
+                           eeh_event.o eeh_sysfs.o eeh_pseries.o
 obj-$(CONFIG_KEXEC)     += kexec.o
 obj-$(CONFIG_PCI)       += pci.o pci_dlpar.o
 obj-$(CONFIG_PSERIES_MSI)       += msi.o
@@ -18,7 +19,6 @@ obj-$(CONFIG_MEMORY_HOTPLUG)	+= hotplug-memory.o
 obj-$(CONFIG_HVC_CONSOLE)       += hvconsole.o
 obj-$(CONFIG_HVCS)              += hvcserver.o
 obj-$(CONFIG_HCALL_STATS)       += hvCall_inst.o
-obj-$(CONFIG_PHYP_DUMP)         += phyp_dump.o
 obj-$(CONFIG_CMM)               += cmm.o
 obj-$(CONFIG_DTL)               += dtl.o
 obj-$(CONFIG_IO_EVENT_IRQ)      += io_event_irq.o
diff --git a/arch/powerpc/platforms/pseries/eeh.c b/arch/powerpc/platforms/pseries/eeh.c
index c0b40af4ce4..8011088392d 100644
--- a/arch/powerpc/platforms/pseries/eeh.c
+++ b/arch/powerpc/platforms/pseries/eeh.c
@@ -1,8 +1,8 @@
 /*
- * eeh.c
  * Copyright IBM Corporation 2001, 2005, 2006
  * Copyright Dave Engebretsen & Todd Inglett 2001
  * Copyright Linas Vepstas 2005, 2006
+ * Copyright 2001-2012 IBM Corporation.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -22,7 +22,7 @@
  */
 
 #include <linux/delay.h>
-#include <linux/sched.h>        /* for init_mm */
+#include <linux/sched.h>
 #include <linux/init.h>
 #include <linux/list.h>
 #include <linux/pci.h>
@@ -86,16 +86,8 @@
 /* Time to wait for a PCI slot to report status, in milliseconds */
 #define PCI_BUS_RESET_WAIT_MSEC (60*1000)
 
-/* RTAS tokens */
-static int ibm_set_eeh_option;
-static int ibm_set_slot_reset;
-static int ibm_read_slot_reset_state;
-static int ibm_read_slot_reset_state2;
-static int ibm_slot_error_detail;
-static int ibm_get_config_addr_info;
-static int ibm_get_config_addr_info2;
-static int ibm_configure_bridge;
-static int ibm_configure_pe;
+/* Platform dependent EEH operations */
+struct eeh_ops *eeh_ops = NULL;
 
 int eeh_subsystem_enabled;
 EXPORT_SYMBOL(eeh_subsystem_enabled);
@@ -103,14 +95,6 @@ EXPORT_SYMBOL(eeh_subsystem_enabled);
 /* Lock to avoid races due to multiple reports of an error */
 static DEFINE_RAW_SPINLOCK(confirm_error_lock);
 
-/* Buffer for reporting slot-error-detail rtas calls. Its here
- * in BSS, and not dynamically alloced, so that it ends up in
- * RMO where RTAS can access it.
- */
-static unsigned char slot_errbuf[RTAS_ERROR_LOG_MAX];
-static DEFINE_SPINLOCK(slot_errbuf_lock);
-static int eeh_error_buf_size;
-
 /* Buffer for reporting pci register dumps. Its here in BSS, and
  * not dynamically alloced, so that it ends up in RMO where RTAS
  * can access it.
@@ -118,74 +102,50 @@ static int eeh_error_buf_size;
 #define EEH_PCI_REGS_LOG_LEN 4096
 static unsigned char pci_regs_buf[EEH_PCI_REGS_LOG_LEN];
 
-/* System monitoring statistics */
-static unsigned long no_device;
-static unsigned long no_dn;
-static unsigned long no_cfg_addr;
-static unsigned long ignored_check;
-static unsigned long total_mmio_ffs;
-static unsigned long false_positives;
-static unsigned long slot_resets;
-
-#define IS_BRIDGE(class_code) (((class_code)<<16) == PCI_BASE_CLASS_BRIDGE)
-
-/* --------------------------------------------------------------- */
-/* Below lies the EEH event infrastructure */
+/*
+ * The struct is used to maintain the EEH global statistic
+ * information. Besides, the EEH global statistics will be
+ * exported to user space through procfs
+ */
+struct eeh_stats {
+        u64 no_device;          /* PCI device not found         */
+        u64 no_dn;              /* OF node not found            */
+        u64 no_cfg_addr;        /* Config address not found     */
+        u64 ignored_check;      /* EEH check skipped            */
+        u64 total_mmio_ffs;     /* Total EEH checks             */
+        u64 false_positives;    /* Unnecessary EEH checks       */
+        u64 slot_resets;        /* PE reset                     */
+};
 
-static void rtas_slot_error_detail(struct pci_dn *pdn, int severity,
-                                   char *driver_log, size_t loglen)
-{
-        int config_addr;
-        unsigned long flags;
-        int rc;
+static struct eeh_stats eeh_stats;
 
-        /* Log the error with the rtas logger */
-        spin_lock_irqsave(&slot_errbuf_lock, flags);
-        memset(slot_errbuf, 0, eeh_error_buf_size);
-
-        /* Use PE configuration address, if present */
-        config_addr = pdn->eeh_config_addr;
-        if (pdn->eeh_pe_config_addr)
-                config_addr = pdn->eeh_pe_config_addr;
-
-        rc = rtas_call(ibm_slot_error_detail,
-                       8, 1, NULL, config_addr,
-                       BUID_HI(pdn->phb->buid),
-                       BUID_LO(pdn->phb->buid),
-                       virt_to_phys(driver_log), loglen,
-                       virt_to_phys(slot_errbuf),
-                       eeh_error_buf_size,
-                       severity);
-
-        if (rc == 0)
-                log_error(slot_errbuf, ERR_TYPE_RTAS_LOG, 0);
-        spin_unlock_irqrestore(&slot_errbuf_lock, flags);
-}
+#define IS_BRIDGE(class_code) (((class_code)<<16) == PCI_BASE_CLASS_BRIDGE)
 
 /**
- * gather_pci_data - copy assorted PCI config space registers to buff
- * @pdn: device to report data for
+ * eeh_gather_pci_data - Copy assorted PCI config space registers to buff
+ * @edev: device to report data for
  * @buf: point to buffer in which to log
  * @len: amount of room in buffer
  *
  * This routine captures assorted PCI configuration space data,
  * and puts them into a buffer for RTAS error logging.
  */
-static size_t gather_pci_data(struct pci_dn *pdn, char * buf, size_t len)
+static size_t eeh_gather_pci_data(struct eeh_dev *edev, char * buf, size_t len)
 {
-        struct pci_dev *dev = pdn->pcidev;
+        struct device_node *dn = eeh_dev_to_of_node(edev);
+        struct pci_dev *dev = eeh_dev_to_pci_dev(edev);
         u32 cfg;
         int cap, i;
         int n = 0;
 
-        n += scnprintf(buf+n, len-n, "%s\n", pdn->node->full_name);
-        printk(KERN_WARNING "EEH: of node=%s\n", pdn->node->full_name);
+        n += scnprintf(buf+n, len-n, "%s\n", dn->full_name);
+        printk(KERN_WARNING "EEH: of node=%s\n", dn->full_name);
 
-        rtas_read_config(pdn, PCI_VENDOR_ID, 4, &cfg);
+        eeh_ops->read_config(dn, PCI_VENDOR_ID, 4, &cfg);
         n += scnprintf(buf+n, len-n, "dev/vend:%08x\n", cfg);
         printk(KERN_WARNING "EEH: PCI device/vendor: %08x\n", cfg);
 
-        rtas_read_config(pdn, PCI_COMMAND, 4, &cfg);
+        eeh_ops->read_config(dn, PCI_COMMAND, 4, &cfg);
         n += scnprintf(buf+n, len-n, "cmd/stat:%x\n", cfg);
         printk(KERN_WARNING "EEH: PCI cmd/status register: %08x\n", cfg);
 
@@ -196,11 +156,11 @@ static size_t gather_pci_data(struct pci_dn *pdn, char * buf, size_t len)
 
         /* Gather bridge-specific registers */
         if (dev->class >> 16 == PCI_BASE_CLASS_BRIDGE) {
-                rtas_read_config(pdn, PCI_SEC_STATUS, 2, &cfg);
+                eeh_ops->read_config(dn, PCI_SEC_STATUS, 2, &cfg);
                 n += scnprintf(buf+n, len-n, "sec stat:%x\n", cfg);
                 printk(KERN_WARNING "EEH: Bridge secondary status: %04x\n", cfg);
 
-                rtas_read_config(pdn, PCI_BRIDGE_CONTROL, 2, &cfg);
+                eeh_ops->read_config(dn, PCI_BRIDGE_CONTROL, 2, &cfg);
                 n += scnprintf(buf+n, len-n, "brdg ctl:%x\n", cfg);
                 printk(KERN_WARNING "EEH: Bridge control: %04x\n", cfg);
         }
@@ -208,11 +168,11 @@ static size_t gather_pci_data(struct pci_dn *pdn, char * buf, size_t len)
         /* Dump out the PCI-X command and status regs */
         cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
         if (cap) {
-                rtas_read_config(pdn, cap, 4, &cfg);
+                eeh_ops->read_config(dn, cap, 4, &cfg);
                 n += scnprintf(buf+n, len-n, "pcix-cmd:%x\n", cfg);
                 printk(KERN_WARNING "EEH: PCI-X cmd: %08x\n", cfg);
 
-                rtas_read_config(pdn, cap+4, 4, &cfg);
+                eeh_ops->read_config(dn, cap+4, 4, &cfg);
                 n += scnprintf(buf+n, len-n, "pcix-stat:%x\n", cfg);
                 printk(KERN_WARNING "EEH: PCI-X status: %08x\n", cfg);
         }
@@ -225,7 +185,7 @@ static size_t gather_pci_data(struct pci_dn *pdn, char * buf, size_t len)
                        "EEH: PCI-E capabilities and status follow:\n");
 
                 for (i=0; i<=8; i++) {
-                        rtas_read_config(pdn, cap+4*i, 4, &cfg);
+                        eeh_ops->read_config(dn, cap+4*i, 4, &cfg);
                         n += scnprintf(buf+n, len-n, "%02x:%x\n", 4*i, cfg);
                         printk(KERN_WARNING "EEH: PCI-E %02x: %08x\n", i, cfg);
                 }
@@ -237,7 +197,7 @@ static size_t gather_pci_data(struct pci_dn *pdn, char * buf, size_t len)
                                "EEH: PCI-E AER capability register set follows:\n");
 
                         for (i=0; i<14; i++) {
-                                rtas_read_config(pdn, cap+4*i, 4, &cfg);
+                                eeh_ops->read_config(dn, cap+4*i, 4, &cfg);
                                 n += scnprintf(buf+n, len-n, "%02x:%x\n", 4*i, cfg);
                                 printk(KERN_WARNING "EEH: PCI-E AER %02x: %08x\n", i, cfg);
                         }
@@ -246,111 +206,46 @@ static size_t gather_pci_data(struct pci_dn *pdn, char * buf, size_t len)
 
         /* Gather status on devices under the bridge */
         if (dev->class >> 16 == PCI_BASE_CLASS_BRIDGE) {
-                struct device_node *dn;
+                struct device_node *child;
 
-                for_each_child_of_node(pdn->node, dn) {
-                        pdn = PCI_DN(dn);
-                        if (pdn)
-                                n += gather_pci_data(pdn, buf+n, len-n);
+                for_each_child_of_node(dn, child) {
+                        if (of_node_to_eeh_dev(child))
+                                n += eeh_gather_pci_data(of_node_to_eeh_dev(child), buf+n, len-n);
                 }
         }
 
         return n;
 }
 
-void eeh_slot_error_detail(struct pci_dn *pdn, int severity)
-{
-        size_t loglen = 0;
-        pci_regs_buf[0] = 0;
-
-        rtas_pci_enable(pdn, EEH_THAW_MMIO);
-        rtas_configure_bridge(pdn);
-        eeh_restore_bars(pdn);
-        loglen = gather_pci_data(pdn, pci_regs_buf, EEH_PCI_REGS_LOG_LEN);
-
-        rtas_slot_error_detail(pdn, severity, pci_regs_buf, loglen);
-}
-
 /**
- * read_slot_reset_state - Read the reset state of a device node's slot
- * @dn: device node to read
- * @rets: array to return results in
- */
-static int read_slot_reset_state(struct pci_dn *pdn, int rets[])
-{
-        int token, outputs;
-        int config_addr;
-
-        if (ibm_read_slot_reset_state2 != RTAS_UNKNOWN_SERVICE) {
-                token = ibm_read_slot_reset_state2;
-                outputs = 4;
-        } else {
-                token = ibm_read_slot_reset_state;
-                rets[2] = 0; /* fake PE Unavailable info */
-                outputs = 3;
-        }
-
-        /* Use PE configuration address, if present */
-        config_addr = pdn->eeh_config_addr;
-        if (pdn->eeh_pe_config_addr)
-                config_addr = pdn->eeh_pe_config_addr;
-
-        return rtas_call(token, 3, outputs, rets, config_addr,
-                         BUID_HI(pdn->phb->buid), BUID_LO(pdn->phb->buid));
-}
-
-/**
- * eeh_wait_for_slot_status - returns error status of slot
- * @pdn pci device node
- * @max_wait_msecs maximum number to millisecs to wait
- *
- * Return negative value if a permanent error, else return
- * Partition Endpoint (PE) status value.
+ * eeh_slot_error_detail - Generate combined log including driver log and error log
+ * @edev: device to report error log for
+ * @severity: temporary or permanent error log
  *
- * If @max_wait_msecs is positive, then this routine will
- * sleep until a valid status can be obtained, or until
- * the max allowed wait time is exceeded, in which case
- * a -2 is returned.
+ * This routine should be called to generate the combined log, which
+ * is comprised of driver log and error log. The driver log is figured
+ * out from the config space of the corresponding PCI device, while
+ * the error log is fetched through platform dependent function call.
  */
-int
-eeh_wait_for_slot_status(struct pci_dn *pdn, int max_wait_msecs)
+void eeh_slot_error_detail(struct eeh_dev *edev, int severity)
 {
-        int rc;
-        int rets[3];
-        int mwait;
-
-        while (1) {
-                rc = read_slot_reset_state(pdn, rets);
-                if (rc) return rc;
-                if (rets[1] == 0) return -1;  /* EEH is not supported */
-
-                if (rets[0] != 5) return rets[0]; /* return actual status */
-
-                if (rets[2] == 0) return -1; /* permanently unavailable */
+        size_t loglen = 0;
+        pci_regs_buf[0] = 0;
 
-                if (max_wait_msecs <= 0) break;
+        eeh_pci_enable(edev, EEH_OPT_THAW_MMIO);
+        eeh_ops->configure_bridge(eeh_dev_to_of_node(edev));
+        eeh_restore_bars(edev);
+        loglen = eeh_gather_pci_data(edev, pci_regs_buf, EEH_PCI_REGS_LOG_LEN);
 
-                mwait = rets[2];
-                if (mwait <= 0) {
-                        printk (KERN_WARNING
-                                "EEH: Firmware returned bad wait value=%d\n", mwait);
-                        mwait = 1000;
-                } else if (mwait > 300*1000) {
-                        printk (KERN_WARNING
-                                "EEH: Firmware is taking too long, time=%d\n", mwait);
-                        mwait = 300*1000;
-                }
-                max_wait_msecs -= mwait;
-                msleep (mwait);
-        }
-
-        printk(KERN_WARNING "EEH: Timed out waiting for slot status\n");
-        return -2;
+        eeh_ops->get_log(eeh_dev_to_of_node(edev), severity, pci_regs_buf, loglen);
 }
 
 /**
- * eeh_token_to_phys - convert EEH address token to phys address
- * @token i/o token, should be address in the form 0xA....
+ * eeh_token_to_phys - Convert EEH address token to phys address
+ * @token: I/O token, should be address in the form 0xA....
+ *
+ * This routine should be called to convert virtual I/O address
+ * to physical one.
  */
 static inline unsigned long eeh_token_to_phys(unsigned long token)
 {
@@ -365,36 +260,43 @@ static inline unsigned long eeh_token_to_phys(unsigned long token)
         return pa | (token & (PAGE_SIZE-1));
 }
 
-/** 
- * Return the "partitionable endpoint" (pe) under which this device lies
+/**
+ * eeh_find_device_pe - Retrieve the PE for the given device
+ * @dn: device node
+ *
+ * Return the PE under which this device lies
  */
-struct device_node * find_device_pe(struct device_node *dn)
+struct device_node *eeh_find_device_pe(struct device_node *dn)
 {
-        while ((dn->parent) && PCI_DN(dn->parent) &&
-              (PCI_DN(dn->parent)->eeh_mode & EEH_MODE_SUPPORTED)) {
+        while (dn->parent && of_node_to_eeh_dev(dn->parent) &&
+               (of_node_to_eeh_dev(dn->parent)->mode & EEH_MODE_SUPPORTED)) {
                 dn = dn->parent;
         }
         return dn;
 }
 
-/** Mark all devices that are children of this device as failed.
- *  Mark the device driver too, so that it can see the failure
- *  immediately; this is critical, since some drivers poll
- *  status registers in interrupts ... If a driver is polling,
- *  and the slot is frozen, then the driver can deadlock in
- *  an interrupt context, which is bad.
+/**
+ * __eeh_mark_slot - Mark all child devices as failed
+ * @parent: parent device
+ * @mode_flag: failure flag
+ *
+ * Mark all devices that are children of this device as failed.
+ * Mark the device driver too, so that it can see the failure
+ * immediately; this is critical, since some drivers poll
+ * status registers in interrupts ... If a driver is polling,
+ * and the slot is frozen, then the driver can deadlock in
+ * an interrupt context, which is bad.
  */
-
 static void __eeh_mark_slot(struct device_node *parent, int mode_flag)
 {
         struct device_node *dn;
 
         for_each_child_of_node(parent, dn) {
-                if (PCI_DN(dn)) {
+                if (of_node_to_eeh_dev(dn)) {
                         /* Mark the pci device driver too */
-                        struct pci_dev *dev = PCI_DN(dn)->pcidev;
+                        struct pci_dev *dev = of_node_to_eeh_dev(dn)->pdev;
 
-                        PCI_DN(dn)->eeh_mode |= mode_flag;
+                        of_node_to_eeh_dev(dn)->mode |= mode_flag;
 
                         if (dev && dev->driver)
                                 dev->error_state = pci_channel_io_frozen;
@@ -404,92 +306,81 @@ static void __eeh_mark_slot(struct device_node *parent, int mode_flag)
         }
 }
 
-void eeh_mark_slot (struct device_node *dn, int mode_flag)
+/**
+ * eeh_mark_slot - Mark the indicated device and its children as failed
+ * @dn: parent device
+ * @mode_flag: failure flag
+ *
+ * Mark the indicated device and its child devices as failed.
+ * The device drivers are marked as failed as well.
+ */
+void eeh_mark_slot(struct device_node *dn, int mode_flag)
 {
         struct pci_dev *dev;
-        dn = find_device_pe (dn);
+        dn = eeh_find_device_pe(dn);
 
         /* Back up one, since config addrs might be shared */
-        if (!pcibios_find_pci_bus(dn) && PCI_DN(dn->parent))
+        if (!pcibios_find_pci_bus(dn) && of_node_to_eeh_dev(dn->parent))
                 dn = dn->parent;
 
-        PCI_DN(dn)->eeh_mode |= mode_flag;
+        of_node_to_eeh_dev(dn)->mode |= mode_flag;
 
         /* Mark the pci device too */
-        dev = PCI_DN(dn)->pcidev;
+        dev = of_node_to_eeh_dev(dn)->pdev;
         if (dev)
                 dev->error_state = pci_channel_io_frozen;
 
         __eeh_mark_slot(dn, mode_flag);
 }
 
+/**
+ * __eeh_clear_slot - Clear failure flag for the child devices
+ * @parent: parent device
+ * @mode_flag: flag to be cleared
+ *
+ * Clear failure flag for the child devices.
+ */
 static void __eeh_clear_slot(struct device_node *parent, int mode_flag)
 {
         struct device_node *dn;
 
         for_each_child_of_node(parent, dn) {
-                if (PCI_DN(dn)) {
-                        PCI_DN(dn)->eeh_mode &= ~mode_flag;
-                        PCI_DN(dn)->eeh_check_count = 0;
+                if (of_node_to_eeh_dev(dn)) {
+                        of_node_to_eeh_dev(dn)->mode &= ~mode_flag;
+                        of_node_to_eeh_dev(dn)->check_count = 0;
                         __eeh_clear_slot(dn, mode_flag);
                 }
         }
 }
 
-void eeh_clear_slot (struct device_node *dn, int mode_flag)
+/**
+ * eeh_clear_slot - Clear failure flag for the indicated device and its children
+ * @dn: parent device
+ * @mode_flag: flag to be cleared
+ *
+ * Clear failure flag for the indicated device and its children.
+ */
+void eeh_clear_slot(struct device_node *dn, int mode_flag)
 {
         unsigned long flags;
         raw_spin_lock_irqsave(&confirm_error_lock, flags);
         
-        dn = find_device_pe (dn);
+        dn = eeh_find_device_pe(dn);
         
         /* Back up one, since config addrs might be shared */
-        if (!pcibios_find_pci_bus(dn) && PCI_DN(dn->parent))
+        if (!pcibios_find_pci_bus(dn) && of_node_to_eeh_dev(dn->parent))
                 dn = dn->parent;
 
-        PCI_DN(dn)->eeh_mode &= ~mode_flag;
-        PCI_DN(dn)->eeh_check_count = 0;
+        of_node_to_eeh_dev(dn)->mode &= ~mode_flag;
+        of_node_to_eeh_dev(dn)->check_count = 0;
         __eeh_clear_slot(dn, mode_flag);
         raw_spin_unlock_irqrestore(&confirm_error_lock, flags);
 }
 
-void __eeh_set_pe_freset(struct device_node *parent, unsigned int *freset)
-{
-        struct device_node *dn;
-
-        for_each_child_of_node(parent, dn) {
-                if (PCI_DN(dn)) {
-
-                        struct pci_dev *dev = PCI_DN(dn)->pcidev;
-
-                        if (dev && dev->driver)
-                                *freset |= dev->needs_freset;
-
-                        __eeh_set_pe_freset(dn, freset);
-                }
-        }
-}
-
-void eeh_set_pe_freset(struct device_node *dn, unsigned int *freset)
-{
-        struct pci_dev *dev;
-        dn = find_device_pe(dn);
-
-        /* Back up one, since config addrs might be shared */
-        if (!pcibios_find_pci_bus(dn) && PCI_DN(dn->parent))
-                dn = dn->parent;
-
-        dev = PCI_DN(dn)->pcidev;
-        if (dev)
-                *freset |= dev->needs_freset;
-
-        __eeh_set_pe_freset(dn, freset);
-}
-
 /**
- * eeh_dn_check_failure - check if all 1's data is due to EEH slot freeze
- * @dn device node
- * @dev pci device, if known
+ * eeh_dn_check_failure - Check if all 1's data is due to EEH slot freeze
+ * @dn: device node
+ * @dev: pci device, if known
  *
  * Check for an EEH failure for the given device node.  Call this
  * routine if the result of a read was all 0xff's and you want to
@@ -504,35 +395,34 @@ void eeh_set_pe_freset(struct device_node *dn, unsigned int *freset)
 int eeh_dn_check_failure(struct device_node *dn, struct pci_dev *dev)
 {
         int ret;
-        int rets[3];
         unsigned long flags;
-        struct pci_dn *pdn;
+        struct eeh_dev *edev;
         int rc = 0;
         const char *location;
 
-        total_mmio_ffs++;
+        eeh_stats.total_mmio_ffs++;
 
         if (!eeh_subsystem_enabled)
                 return 0;
 
         if (!dn) {
-                no_dn++;
+                eeh_stats.no_dn++;
                 return 0;
         }
-        dn = find_device_pe(dn);
-        pdn = PCI_DN(dn);
+        dn = eeh_find_device_pe(dn);
+        edev = of_node_to_eeh_dev(dn);
 
         /* Access to IO BARs might get this far and still not want checking. */
-        if (!(pdn->eeh_mode & EEH_MODE_SUPPORTED) ||
-            pdn->eeh_mode & EEH_MODE_NOCHECK) {
-                ignored_check++;
+        if (!(edev->mode & EEH_MODE_SUPPORTED) ||
+            edev->mode & EEH_MODE_NOCHECK) {
+                eeh_stats.ignored_check++;
                 pr_debug("EEH: Ignored check (%x) for %s %s\n",
-                         pdn->eeh_mode, eeh_pci_name(dev), dn->full_name);
+                        edev->mode, eeh_pci_name(dev), dn->full_name);
                 return 0;
         }
 
-        if (!pdn->eeh_config_addr && !pdn->eeh_pe_config_addr) {
-                no_cfg_addr++;
+        if (!edev->config_addr && !edev->pe_config_addr) {
+                eeh_stats.no_cfg_addr++;
                 return 0;
         }
 
@@ -544,15 +434,15 @@ int eeh_dn_check_failure(struct device_node *dn, struct pci_dev *dev)
          */
         raw_spin_lock_irqsave(&confirm_error_lock, flags);
         rc = 1;
-        if (pdn->eeh_mode & EEH_MODE_ISOLATED) {
-                pdn->eeh_check_count ++;
-                if (pdn->eeh_check_count % EEH_MAX_FAILS == 0) {
+        if (edev->mode & EEH_MODE_ISOLATED) {
+                edev->check_count++;
+                if (edev->check_count % EEH_MAX_FAILS == 0) {
                         location = of_get_property(dn, "ibm,loc-code", NULL);
-                        printk (KERN_ERR "EEH: %d reads ignored for recovering device at "
+                        printk(KERN_ERR "EEH: %d reads ignored for recovering device at "
                                 "location=%s driver=%s pci addr=%s\n",
-                                pdn->eeh_check_count, location,
+                                edev->check_count, location,
                                 eeh_driver_name(dev), eeh_pci_name(dev));
-                        printk (KERN_ERR "EEH: Might be infinite loop in %s driver\n",
+                        printk(KERN_ERR "EEH: Might be infinite loop in %s driver\n",
                                 eeh_driver_name(dev));
                         dump_stack();
                 }
@@ -566,58 +456,39 @@ int eeh_dn_check_failure(struct device_node *dn, struct pci_dev *dev)
          * function zero of a multi-function device.
          * In any case they must share a common PHB.
          */
-        ret = read_slot_reset_state(pdn, rets);
-
-        /* If the call to firmware failed, punt */
-        if (ret != 0) {
-                printk(KERN_WARNING "EEH: read_slot_reset_state() failed; rc=%d dn=%s\n",
-                       ret, dn->full_name);
-                false_positives++;
-                pdn->eeh_false_positives ++;
-                rc = 0;
-                goto dn_unlock;
-        }
+        ret = eeh_ops->get_state(dn, NULL);
 
         /* Note that config-io to empty slots may fail;
-         * they are empty when they don't have children. */
-        if ((rets[0] == 5) && (rets[2] == 0) && (dn->child == NULL)) {
-                false_positives++;
-                pdn->eeh_false_positives ++;
-                rc = 0;
-                goto dn_unlock;
-        }
-
-        /* If EEH is not supported on this device, punt. */
-        if (rets[1] != 1) {
-                printk(KERN_WARNING "EEH: event on unsupported device, rc=%d dn=%s\n",
-                       ret, dn->full_name);
-                false_positives++;
-                pdn->eeh_false_positives ++;
-                rc = 0;
-                goto dn_unlock;
-        }
-
-        /* If not the kind of error we know about, punt. */
-        if (rets[0] != 1 && rets[0] != 2 && rets[0] != 4 && rets[0] != 5) {
-                false_positives++;
-                pdn->eeh_false_positives ++;
+         * they are empty when they don't have children.
+         * We will punt with the following conditions: Failure to get
+         * PE's state, EEH not support and Permanently unavailable
+         * state, PE is in good state.
+         */
+        if ((ret < 0) ||
+            (ret == EEH_STATE_NOT_SUPPORT) ||
+            (ret & (EEH_STATE_MMIO_ACTIVE | EEH_STATE_DMA_ACTIVE)) ==
+            (EEH_STATE_MMIO_ACTIVE | EEH_STATE_DMA_ACTIVE)) {
+                eeh_stats.false_positives++;
+                edev->false_positives ++;
                 rc = 0;
                 goto dn_unlock;
         }
 
-        slot_resets++;
+        eeh_stats.slot_resets++;
  
         /* Avoid repeated reports of this failure, including problems
          * with other functions on this device, and functions under
-         * bridges. */
-        eeh_mark_slot (dn, EEH_MODE_ISOLATED);
+         * bridges.
+         */
+        eeh_mark_slot(dn, EEH_MODE_ISOLATED);
         raw_spin_unlock_irqrestore(&confirm_error_lock, flags);
 
-        eeh_send_failure_event (dn, dev);
+        eeh_send_failure_event(edev);
 
         /* Most EEH events are due to device driver bugs.  Having
          * a stack trace will help the device-driver authors figure
-         * out what happened.  So print that out. */
+         * out what happened.  So print that out.
+         */
         dump_stack();
         return 1;
 
@@ -629,9 +500,9 @@ dn_unlock:
 EXPORT_SYMBOL_GPL(eeh_dn_check_failure);
 
 /**
- * eeh_check_failure - check if all 1's data is due to EEH slot freeze
- * @token i/o token, should be address in the form 0xA....
- * @val value, should be all 1's (XXX why do we need this arg??)
+ * eeh_check_failure - Check if all 1's data is due to EEH slot freeze
+ * @token: I/O token, should be address in the form 0xA....
+ * @val: value, should be all 1's (XXX why do we need this arg??)
  *
  * Check for an EEH failure at the given token address.  Call this
  * routine if the result of a read was all 0xff's and you want to
@@ -648,14 +519,14 @@ unsigned long eeh_check_failure(const volatile void __iomem *token, unsigned lon
 
         /* Finding the phys addr + pci device; this is pretty quick. */
         addr = eeh_token_to_phys((unsigned long __force) token);
-        dev = pci_get_device_by_addr(addr);
+        dev = pci_addr_cache_get_device(addr);
         if (!dev) {
-                no_device++;
+                eeh_stats.no_device++;
                 return val;
         }
 
         dn = pci_device_to_OF_node(dev);
-        eeh_dn_check_failure (dn, dev);
+        eeh_dn_check_failure(dn, dev);
 
         pci_dev_put(dev);
         return val;
@@ -663,115 +534,54 @@ unsigned long eeh_check_failure(const volatile void __iomem *token, unsigned lon
 
 EXPORT_SYMBOL(eeh_check_failure);
 
-/* ------------------------------------------------------------- */
-/* The code below deals with error recovery */
 
 /**
- * rtas_pci_enable - enable MMIO or DMA transfers for this slot
- * @pdn pci device node
+ * eeh_pci_enable - Enable MMIO or DMA transfers for this slot
+ * @edev: pci device node
+ *
+ * This routine should be called to reenable frozen MMIO or DMA
+ * so that it would work correctly again. It's useful while doing
+ * recovery or log collection on the indicated device.
  */
-
-int
-rtas_pci_enable(struct pci_dn *pdn, int function)
+int eeh_pci_enable(struct eeh_dev *edev, int function)
 {
-        int config_addr;
         int rc;
+        struct device_node *dn = eeh_dev_to_of_node(edev);
 
-        /* Use PE configuration address, if present */
-        config_addr = pdn->eeh_config_addr;
-        if (pdn->eeh_pe_config_addr)
-                config_addr = pdn->eeh_pe_config_addr;
-
-        rc = rtas_call(ibm_set_eeh_option, 4, 1, NULL,
-                       config_addr,
-                       BUID_HI(pdn->phb->buid),
-                       BUID_LO(pdn->phb->buid),
-                            function);
-
+        rc = eeh_ops->set_option(dn, function);
         if (rc)
                 printk(KERN_WARNING "EEH: Unexpected state change %d, err=%d dn=%s\n",
-                        function, rc, pdn->node->full_name);
+                        function, rc, dn->full_name);
 
-        rc = eeh_wait_for_slot_status (pdn, PCI_BUS_RESET_WAIT_MSEC);
-        if ((rc == 4) && (function == EEH_THAW_MMIO))
+        rc = eeh_ops->wait_state(dn, PCI_BUS_RESET_WAIT_MSEC);
+        if (rc > 0 && (rc & EEH_STATE_MMIO_ENABLED) &&
+           (function == EEH_OPT_THAW_MMIO))
                 return 0;
 
         return rc;
 }
 
 /**
- * rtas_pci_slot_reset - raises/lowers the pci #RST line
- * @pdn pci device node
- * @state: 1/0 to raise/lower the #RST
- *
- * Clear the EEH-frozen condition on a slot.  This routine
- * asserts the PCI #RST line if the 'state' argument is '1',
- * and drops the #RST line if 'state is '0'.  This routine is
- * safe to call in an interrupt context.
- *
- */
-
-static void
-rtas_pci_slot_reset(struct pci_dn *pdn, int state)
-{
-        int config_addr;
-        int rc;
-
-        BUG_ON (pdn==NULL); 
-
-        if (!pdn->phb) {
-                printk (KERN_WARNING "EEH: in slot reset, device node %s has no phb\n",
-                        pdn->node->full_name);
-                return;
-        }
-
-        /* Use PE configuration address, if present */
-        config_addr = pdn->eeh_config_addr;
-        if (pdn->eeh_pe_config_addr)
-                config_addr = pdn->eeh_pe_config_addr;
-
-        rc = rtas_call(ibm_set_slot_reset, 4, 1, NULL,
-                       config_addr,
-                       BUID_HI(pdn->phb->buid),
-                       BUID_LO(pdn->phb->buid),
-                       state);
-
-        /* Fundamental-reset not supported on this PE, try hot-reset */
-        if (rc == -8 && state == 3) {
-                rc = rtas_call(ibm_set_slot_reset, 4, 1, NULL,
-                               config_addr,
-                               BUID_HI(pdn->phb->buid),
-                               BUID_LO(pdn->phb->buid), 1);
-                if (rc)
-                        printk(KERN_WARNING
-                                "EEH: Unable to reset the failed slot,"
-                                " #RST=%d dn=%s\n",
-                                rc, pdn->node->full_name);
-        }
-}
-
-/**
  * pcibios_set_pcie_slot_reset - Set PCI-E reset state
- * @dev:        pci device struct
- * @state:      reset state to enter
+ * @dev: pci device struct
+ * @state: reset state to enter
  *
  * Return value:
  *      0 if success
- **/
+ */
 int pcibios_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state)
 {
         struct device_node *dn = pci_device_to_OF_node(dev);
-        struct pci_dn *pdn = PCI_DN(dn);
 
         switch (state) {
         case pcie_deassert_reset:
-                rtas_pci_slot_reset(pdn, 0);
+                eeh_ops->reset(dn, EEH_RESET_DEACTIVATE);
                 break;
         case pcie_hot_reset:
-                rtas_pci_slot_reset(pdn, 1);
+                eeh_ops->reset(dn, EEH_RESET_HOT);
                 break;
         case pcie_warm_reset:
-                rtas_pci_slot_reset(pdn, 3);
+                eeh_ops->reset(dn, EEH_RESET_FUNDAMENTAL);
                 break;
         default:
                 return -EINVAL;
@@ -781,13 +591,66 @@ int pcibios_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state stat
 }
 
 /**
- * rtas_set_slot_reset -- assert the pci #RST line for 1/4 second
- * @pdn: pci device node to be reset.
+ * __eeh_set_pe_freset - Check the required reset for child devices
+ * @parent: parent device
+ * @freset: return value
+ *
+ * Each device might have its preferred reset type: fundamental or
+ * hot reset. The routine is used to collect the information from
+ * the child devices so that they could be reset accordingly.
+ */
+void __eeh_set_pe_freset(struct device_node *parent, unsigned int *freset)
+{
+        struct device_node *dn;
+
+        for_each_child_of_node(parent, dn) {
+                if (of_node_to_eeh_dev(dn)) {
+                        struct pci_dev *dev = of_node_to_eeh_dev(dn)->pdev;
+
+                        if (dev && dev->driver)
+                                *freset |= dev->needs_freset;
+
+                        __eeh_set_pe_freset(dn, freset);
+                }
+        }
+}
+
+/**
+ * eeh_set_pe_freset - Check the required reset for the indicated device and its children
+ * @dn: parent device
+ * @freset: return value
+ *
+ * Each device might have its preferred reset type: fundamental or
+ * hot reset. The routine is used to collected the information for
+ * the indicated device and its children so that the bunch of the
+ * devices could be reset properly.
  */
+void eeh_set_pe_freset(struct device_node *dn, unsigned int *freset)
+{
+        struct pci_dev *dev;
+        dn = eeh_find_device_pe(dn);
+
+        /* Back up one, since config addrs might be shared */
+        if (!pcibios_find_pci_bus(dn) && of_node_to_eeh_dev(dn->parent))
+                dn = dn->parent;
+
+        dev = of_node_to_eeh_dev(dn)->pdev;
+        if (dev)
+                *freset |= dev->needs_freset;
 
-static void __rtas_set_slot_reset(struct pci_dn *pdn)
+        __eeh_set_pe_freset(dn, freset);
+}
+
+/**
+ * eeh_reset_pe_once - Assert the pci #RST line for 1/4 second
+ * @edev: pci device node to be reset.
+ *
+ * Assert the PCI #RST line for 1/4 second.
+ */
+static void eeh_reset_pe_once(struct eeh_dev *edev)
 {
         unsigned int freset = 0;
+        struct device_node *dn = eeh_dev_to_of_node(edev);
 
         /* Determine type of EEH reset required for
          * Partitionable Endpoint, a hot-reset (1)
@@ -795,58 +658,68 @@ static void __rtas_set_slot_reset(struct pci_dn *pdn)
          * A fundamental reset required by any device under
          * Partitionable Endpoint trumps hot-reset.
          */
-        eeh_set_pe_freset(pdn->node, &freset);
+        eeh_set_pe_freset(dn, &freset);
 
         if (freset)
-                rtas_pci_slot_reset(pdn, 3);
+                eeh_ops->reset(dn, EEH_RESET_FUNDAMENTAL);
         else
-                rtas_pci_slot_reset(pdn, 1);
+                eeh_ops->reset(dn, EEH_RESET_HOT);
 
         /* The PCI bus requires that the reset be held high for at least
-         * a 100 milliseconds. We wait a bit longer 'just in case'.  */
-
+         * a 100 milliseconds. We wait a bit longer 'just in case'.
+         */
 #define PCI_BUS_RST_HOLD_TIME_MSEC 250
-        msleep (PCI_BUS_RST_HOLD_TIME_MSEC);
+        msleep(PCI_BUS_RST_HOLD_TIME_MSEC);
         
         /* We might get hit with another EEH freeze as soon as the 
          * pci slot reset line is dropped. Make sure we don't miss
-         * these, and clear the flag now. */
-        eeh_clear_slot (pdn->node, EEH_MODE_ISOLATED);
+         * these, and clear the flag now.
+         */
+        eeh_clear_slot(dn, EEH_MODE_ISOLATED);
 
-        rtas_pci_slot_reset (pdn, 0);
+        eeh_ops->reset(dn, EEH_RESET_DEACTIVATE);
 
         /* After a PCI slot has been reset, the PCI Express spec requires
          * a 1.5 second idle time for the bus to stabilize, before starting
-         * up traffic. */
+         * up traffic.
+         */
 #define PCI_BUS_SETTLE_TIME_MSEC 1800
-        msleep (PCI_BUS_SETTLE_TIME_MSEC);
+        msleep(PCI_BUS_SETTLE_TIME_MSEC);
 }
 
-int rtas_set_slot_reset(struct pci_dn *pdn)
+/**
+ * eeh_reset_pe - Reset the indicated PE
+ * @edev: PCI device associated EEH device
+ *
+ * This routine should be called to reset indicated device, including
+ * PE. A PE might include multiple PCI devices and sometimes PCI bridges
+ * might be involved as well.
+ */
+int eeh_reset_pe(struct eeh_dev *edev)
 {
         int i, rc;
+        struct device_node *dn = eeh_dev_to_of_node(edev);
 
         /* Take three shots at resetting the bus */
         for (i=0; i<3; i++) {
-                __rtas_set_slot_reset(pdn);
+                eeh_reset_pe_once(edev);
 
-                rc = eeh_wait_for_slot_status(pdn, PCI_BUS_RESET_WAIT_MSEC);
-                if (rc == 0)
+                rc = eeh_ops->wait_state(dn, PCI_BUS_RESET_WAIT_MSEC);
+                if (rc == (EEH_STATE_MMIO_ACTIVE | EEH_STATE_DMA_ACTIVE))
                         return 0;
 
                 if (rc < 0) {
                         printk(KERN_ERR "EEH: unrecoverable slot failure %s\n",
-                               pdn->node->full_name);
+                               dn->full_name);
                         return -1;
                 }
                 printk(KERN_ERR "EEH: bus reset %d failed on slot %s, rc=%d\n",
-                       i+1, pdn->node->full_name, rc);
+                       i+1, dn->full_name, rc);
         }
 
         return -1;
 }
 
-/* ------------------------------------------------------- */
 /** Save and restore of PCI BARs
  *
  * Although firmware will set up BARs during boot, it doesn't
@@ -856,181 +729,122 @@ int rtas_set_slot_reset(struct pci_dn *pdn)
  */
 
 /**
- * __restore_bars - Restore the Base Address Registers
- * @pdn: pci device node
+ * eeh_restore_one_device_bars - Restore the Base Address Registers for one device
+ * @edev: PCI device associated EEH device
  *
  * Loads the PCI configuration space base address registers,
  * the expansion ROM base address, the latency timer, and etc.
  * from the saved values in the device node.
  */
-static inline void __restore_bars (struct pci_dn *pdn)
+static inline void eeh_restore_one_device_bars(struct eeh_dev *edev)
 {
         int i;
         u32 cmd;
+        struct device_node *dn = eeh_dev_to_of_node(edev);
+
+        if (!edev->phb)
+                return;
 
-        if (NULL==pdn->phb) return;
         for (i=4; i<10; i++) {
-                rtas_write_config(pdn, i*4, 4, pdn->config_space[i]);
+                eeh_ops->write_config(dn, i*4, 4, edev->config_space[i]);
         }
 
         /* 12 == Expansion ROM Address */
-        rtas_write_config(pdn, 12*4, 4, pdn->config_space[12]);
+        eeh_ops->write_config(dn, 12*4, 4, edev->config_space[12]);
 
 #define BYTE_SWAP(OFF) (8*((OFF)/4)+3-(OFF))
-#define SAVED_BYTE(OFF) (((u8 *)(pdn->config_space))[BYTE_SWAP(OFF)])
+#define SAVED_BYTE(OFF) (((u8 *)(edev->config_space))[BYTE_SWAP(OFF)])
 
-        rtas_write_config (pdn, PCI_CACHE_LINE_SIZE, 1,
+        eeh_ops->write_config(dn, PCI_CACHE_LINE_SIZE, 1,
                     SAVED_BYTE(PCI_CACHE_LINE_SIZE));
 
-        rtas_write_config (pdn, PCI_LATENCY_TIMER, 1,
+        eeh_ops->write_config(dn, PCI_LATENCY_TIMER, 1,
                     SAVED_BYTE(PCI_LATENCY_TIMER));
 
         /* max latency, min grant, interrupt pin and line */
-        rtas_write_config(pdn, 15*4, 4, pdn->config_space[15]);
+        eeh_ops->write_config(dn, 15*4, 4, edev->config_space[15]);
 
         /* Restore PERR & SERR bits, some devices require it,
-           don't touch the other command bits */
-        rtas_read_config(pdn, PCI_COMMAND, 4, &cmd);
-        if (pdn->config_space[1] & PCI_COMMAND_PARITY)
+         * don't touch the other command bits
+         */
+        eeh_ops->read_config(dn, PCI_COMMAND, 4, &cmd);
+        if (edev->config_space[1] & PCI_COMMAND_PARITY)
                 cmd |= PCI_COMMAND_PARITY;
         else
                 cmd &= ~PCI_COMMAND_PARITY;
-        if (pdn->config_space[1] & PCI_COMMAND_SERR)
+        if (edev->config_space[1] & PCI_COMMAND_SERR)
                 cmd |= PCI_COMMAND_SERR;
         else
                 cmd &= ~PCI_COMMAND_SERR;
-        rtas_write_config(pdn, PCI_COMMAND, 4, cmd);
+        eeh_ops->write_config(dn, PCI_COMMAND, 4, cmd);
 }
 
 /**
- * eeh_restore_bars - restore the PCI config space info
+ * eeh_restore_bars - Restore the PCI config space info
+ * @edev: EEH device
  *
  * This routine performs a recursive walk to the children
  * of this device as well.
  */
-void eeh_restore_bars(struct pci_dn *pdn)
+void eeh_restore_bars(struct eeh_dev *edev)
 {
         struct device_node *dn;
-        if (!pdn) 
+        if (!edev)
                 return;
         
-        if ((pdn->eeh_mode & EEH_MODE_SUPPORTED) && !IS_BRIDGE(pdn->class_code))
-                __restore_bars (pdn);
+        if ((edev->mode & EEH_MODE_SUPPORTED) && !IS_BRIDGE(edev->class_code))
+                eeh_restore_one_device_bars(edev);
 
-        for_each_child_of_node(pdn->node, dn)
-                eeh_restore_bars (PCI_DN(dn));
+        for_each_child_of_node(eeh_dev_to_of_node(edev), dn)
+                eeh_restore_bars(of_node_to_eeh_dev(dn));
 }
 
 /**
- * eeh_save_bars - save device bars
+ * eeh_save_bars - Save device bars
+ * @edev: PCI device associated EEH device
  *
  * Save the values of the device bars. Unlike the restore
  * routine, this routine is *not* recursive. This is because
  * PCI devices are added individually; but, for the restore,
  * an entire slot is reset at a time.
  */
-static void eeh_save_bars(struct pci_dn *pdn)
+static void eeh_save_bars(struct eeh_dev *edev)
 {
         int i;
+        struct device_node *dn;
 
-        if (!pdn )
+        if (!edev)
                 return;
+        dn = eeh_dev_to_of_node(edev);
         
         for (i = 0; i < 16; i++)
-                rtas_read_config(pdn, i * 4, 4, &pdn->config_space[i]);
-}
-
-void
-rtas_configure_bridge(struct pci_dn *pdn)
-{
-        int config_addr;
-        int rc;
-        int token;
-
-        /* Use PE configuration address, if present */
-        config_addr = pdn->eeh_config_addr;
-        if (pdn->eeh_pe_config_addr)
-                config_addr = pdn->eeh_pe_config_addr;
-
-        /* Use new configure-pe function, if supported */
-        if (ibm_configure_pe != RTAS_UNKNOWN_SERVICE)
-                token = ibm_configure_pe;
-        else
-                token = ibm_configure_bridge;
-
-        rc = rtas_call(token, 3, 1, NULL,
-                       config_addr,
-                       BUID_HI(pdn->phb->buid),
-                       BUID_LO(pdn->phb->buid));
-        if (rc) {
-                printk (KERN_WARNING "EEH: Unable to configure device bridge (%d) for %s\n",
-                        rc, pdn->node->full_name);
-        }
+                eeh_ops->read_config(dn, i * 4, 4, &edev->config_space[i]);
 }
 
-/* ------------------------------------------------------------- */
-/* The code below deals with enabling EEH for devices during  the
- * early boot sequence.  EEH must be enabled before any PCI probing
- * can be done.
+/**
+ * eeh_early_enable - Early enable EEH on the indicated device
+ * @dn: device node
+ * @data: BUID
+ *
+ * Enable EEH functionality on the specified PCI device. The function
+ * is expected to be called before real PCI probing is done. However,
+ * the PHBs have been initialized at this point.
  */
-
-#define EEH_ENABLE 1
-
-struct eeh_early_enable_info {
-        unsigned int buid_hi;
-        unsigned int buid_lo;
-};
-
-static int get_pe_addr (int config_addr,
-                        struct eeh_early_enable_info *info)
+static void *eeh_early_enable(struct device_node *dn, void *data)
 {
-        unsigned int rets[3];
-        int ret;
-
-        /* Use latest config-addr token on power6 */
-        if (ibm_get_config_addr_info2 != RTAS_UNKNOWN_SERVICE) {
-                /* Make sure we have a PE in hand */
-                ret = rtas_call (ibm_get_config_addr_info2, 4, 2, rets,
-                        config_addr, info->buid_hi, info->buid_lo, 1);
-                if (ret || (rets[0]==0))
-                        return 0;
-
-                ret = rtas_call (ibm_get_config_addr_info2, 4, 2, rets,
-                        config_addr, info->buid_hi, info->buid_lo, 0);
-                if (ret)
-                        return 0;
-                return rets[0];
-        }
-
-        /* Use older config-addr token on power5 */
-        if (ibm_get_config_addr_info != RTAS_UNKNOWN_SERVICE) {
-                ret = rtas_call (ibm_get_config_addr_info, 4, 2, rets,
-                        config_addr, info->buid_hi, info->buid_lo, 0);
-                if (ret)
-                        return 0;
-                return rets[0];
-        }
-        return 0;
-}
-
-/* Enable eeh for the given device node. */
-static void *early_enable_eeh(struct device_node *dn, void *data)
-{
-        unsigned int rets[3];
-        struct eeh_early_enable_info *info = data;
         int ret;
         const u32 *class_code = of_get_property(dn, "class-code", NULL);
         const u32 *vendor_id = of_get_property(dn, "vendor-id", NULL);
         const u32 *device_id = of_get_property(dn, "device-id", NULL);
         const u32 *regs;
         int enable;
-        struct pci_dn *pdn = PCI_DN(dn);
+        struct eeh_dev *edev = of_node_to_eeh_dev(dn);
 
-        pdn->class_code = 0;
-        pdn->eeh_mode = 0;
-        pdn->eeh_check_count = 0;
-        pdn->eeh_freeze_count = 0;
-        pdn->eeh_false_positives = 0;
+        edev->class_code = 0;
+        edev->mode = 0;
+        edev->check_count = 0;
+        edev->freeze_count = 0;
+        edev->false_positives = 0;
 
         if (!of_device_is_available(dn))
                 return NULL;
@@ -1041,54 +855,56 @@ static void *early_enable_eeh(struct device_node *dn, void *data)
 
         /* There is nothing to check on PCI to ISA bridges */
         if (dn->type && !strcmp(dn->type, "isa")) {
-                pdn->eeh_mode |= EEH_MODE_NOCHECK;
+                edev->mode |= EEH_MODE_NOCHECK;
                 return NULL;
         }
-        pdn->class_code = *class_code;
+        edev->class_code = *class_code;
 
         /* Ok... see if this device supports EEH.  Some do, some don't,
-         * and the only way to find out is to check each and every one. */
+         * and the only way to find out is to check each and every one.
+         */
         regs = of_get_property(dn, "reg", NULL);
         if (regs) {
                 /* First register entry is addr (00BBSS00)  */
                 /* Try to enable eeh */
-                ret = rtas_call(ibm_set_eeh_option, 4, 1, NULL,
-                                regs[0], info->buid_hi, info->buid_lo,
-                                EEH_ENABLE);
+                ret = eeh_ops->set_option(dn, EEH_OPT_ENABLE);
 
                 enable = 0;
                 if (ret == 0) {
-                        pdn->eeh_config_addr = regs[0];
+                        edev->config_addr = regs[0];
 
                         /* If the newer, better, ibm,get-config-addr-info is supported, 
-                         * then use that instead. */
-                        pdn->eeh_pe_config_addr = get_pe_addr(pdn->eeh_config_addr, info);
+                         * then use that instead.
+                         */
+                        edev->pe_config_addr = eeh_ops->get_pe_addr(dn);
 
                         /* Some older systems (Power4) allow the
                          * ibm,set-eeh-option call to succeed even on nodes
                          * where EEH is not supported. Verify support
-                         * explicitly. */
-                        ret = read_slot_reset_state(pdn, rets);
-                        if ((ret == 0) && (rets[1] == 1))
+                         * explicitly.
+                         */
+                        ret = eeh_ops->get_state(dn, NULL);
+                        if (ret > 0 && ret != EEH_STATE_NOT_SUPPORT)
                                 enable = 1;
                 }
 
                 if (enable) {
                         eeh_subsystem_enabled = 1;
-                        pdn->eeh_mode |= EEH_MODE_SUPPORTED;
+                        edev->mode |= EEH_MODE_SUPPORTED;
 
                         pr_debug("EEH: %s: eeh enabled, config=%x pe_config=%x\n",
-                                 dn->full_name, pdn->eeh_config_addr,
-                                 pdn->eeh_pe_config_addr);
+                                 dn->full_name, edev->config_addr,
+                                 edev->pe_config_addr);
                 } else {
 
                         /* This device doesn't support EEH, but it may have an
-                         * EEH parent, in which case we mark it as supported. */
-                        if (dn->parent && PCI_DN(dn->parent)
-                            && (PCI_DN(dn->parent)->eeh_mode & EEH_MODE_SUPPORTED)) {
+                         * EEH parent, in which case we mark it as supported.
+                         */
+                        if (dn->parent && of_node_to_eeh_dev(dn->parent) &&
+                            (of_node_to_eeh_dev(dn->parent)->mode & EEH_MODE_SUPPORTED)) {
                                 /* Parent supports EEH. */
-                                pdn->eeh_mode |= EEH_MODE_SUPPORTED;
-                                pdn->eeh_config_addr = PCI_DN(dn->parent)->eeh_config_addr;
+                                edev->mode |= EEH_MODE_SUPPORTED;
+                                edev->config_addr = of_node_to_eeh_dev(dn->parent)->config_addr;
                                 return NULL;
                         }
                 }
@@ -1097,11 +913,63 @@ static void *early_enable_eeh(struct device_node *dn, void *data)
                        dn->full_name);
         }
 
-        eeh_save_bars(pdn);
+        eeh_save_bars(edev);
         return NULL;
 }
 
-/*
+/**
+ * eeh_ops_register - Register platform dependent EEH operations
+ * @ops: platform dependent EEH operations
+ *
+ * Register the platform dependent EEH operation callback
+ * functions. The platform should call this function before
+ * any other EEH operations.
+ */
+int __init eeh_ops_register(struct eeh_ops *ops)
+{
+        if (!ops->name) {
+                pr_warning("%s: Invalid EEH ops name for %p\n",
+                        __func__, ops);
+                return -EINVAL;
+        }
+
+        if (eeh_ops && eeh_ops != ops) {
+                pr_warning("%s: EEH ops of platform %s already existing (%s)\n",
+                        __func__, eeh_ops->name, ops->name);
+                return -EEXIST;
+        }
+
+        eeh_ops = ops;
+
+        return 0;
+}
+
+/**
+ * eeh_ops_unregister - Unreigster platform dependent EEH operations
+ * @name: name of EEH platform operations
+ *
+ * Unregister the platform dependent EEH operation callback
+ * functions.
+ */
+int __exit eeh_ops_unregister(const char *name)
+{
+        if (!name || !strlen(name)) {
+                pr_warning("%s: Invalid EEH ops name\n",
+                        __func__);
+                return -EINVAL;
+        }
+
+        if (eeh_ops && !strcmp(eeh_ops->name, name)) {
+                eeh_ops = NULL;
+                return 0;
+        }
+
+        return -EEXIST;
+}
+
+/**
+ * eeh_init - EEH initialization
+ *
  * Initialize EEH by trying to enable it for all of the adapters in the system.
  * As a side effect we can determine here if eeh is supported at all.
  * Note that we leave EEH on so failed config cycles won't cause a machine
@@ -1117,50 +985,35 @@ static void *early_enable_eeh(struct device_node *dn, void *data)
 void __init eeh_init(void)
 {
         struct device_node *phb, *np;
-        struct eeh_early_enable_info info;
+        int ret;
+
+        /* call platform initialization function */
+        if (!eeh_ops) {
+                pr_warning("%s: Platform EEH operation not found\n",
+                        __func__);
+                return;
+        } else if ((ret = eeh_ops->init())) {
+                pr_warning("%s: Failed to call platform init function (%d)\n",
+                        __func__, ret);
+                return;
+        }
 
         raw_spin_lock_init(&confirm_error_lock);
-        spin_lock_init(&slot_errbuf_lock);
 
         np = of_find_node_by_path("/rtas");
         if (np == NULL)
                 return;
 
-        ibm_set_eeh_option = rtas_token("ibm,set-eeh-option");
-        ibm_set_slot_reset = rtas_token("ibm,set-slot-reset");
-        ibm_read_slot_reset_state2 = rtas_token("ibm,read-slot-reset-state2");
-        ibm_read_slot_reset_state = rtas_token("ibm,read-slot-reset-state");
-        ibm_slot_error_detail = rtas_token("ibm,slot-error-detail");
-        ibm_get_config_addr_info = rtas_token("ibm,get-config-addr-info");
-        ibm_get_config_addr_info2 = rtas_token("ibm,get-config-addr-info2");
-        ibm_configure_bridge = rtas_token ("ibm,configure-bridge");
-        ibm_configure_pe = rtas_token("ibm,configure-pe");
-
-        if (ibm_set_eeh_option == RTAS_UNKNOWN_SERVICE)
-                return;
-
-        eeh_error_buf_size = rtas_token("rtas-error-log-max");
-        if (eeh_error_buf_size == RTAS_UNKNOWN_SERVICE) {
-                eeh_error_buf_size = 1024;
-        }
-        if (eeh_error_buf_size > RTAS_ERROR_LOG_MAX) {
-                printk(KERN_WARNING "EEH: rtas-error-log-max is bigger than allocated "
-                      "buffer ! (%d vs %d)", eeh_error_buf_size, RTAS_ERROR_LOG_MAX);
-                eeh_error_buf_size = RTAS_ERROR_LOG_MAX;
-        }
-
         /* Enable EEH for all adapters.  Note that eeh requires buid's */
         for (phb = of_find_node_by_name(NULL, "pci"); phb;
              phb = of_find_node_by_name(phb, "pci")) {
                 unsigned long buid;
 
                 buid = get_phb_buid(phb);
-                if (buid == 0 || PCI_DN(phb) == NULL)
+                if (buid == 0 || !of_node_to_eeh_dev(phb))
                         continue;
 
-                info.buid_lo = BUID_LO(buid);
-                info.buid_hi = BUID_HI(buid);
-                traverse_pci_devices(phb, early_enable_eeh, &info);
+                traverse_pci_devices(phb, eeh_early_enable, NULL);
         }
 
         if (eeh_subsystem_enabled)
@@ -1170,7 +1023,7 @@ void __init eeh_init(void)
 }
 
 /**
- * eeh_add_device_early - enable EEH for the indicated device_node
+ * eeh_add_device_early - Enable EEH for the indicated device_node
  * @dn: device node for which to set up EEH
  *
  * This routine must be used to perform EEH initialization for PCI
@@ -1184,21 +1037,26 @@ void __init eeh_init(void)
 static void eeh_add_device_early(struct device_node *dn)
 {
         struct pci_controller *phb;
-        struct eeh_early_enable_info info;
 
-        if (!dn || !PCI_DN(dn))
+        if (!dn || !of_node_to_eeh_dev(dn))
                 return;
-        phb = PCI_DN(dn)->phb;
+        phb = of_node_to_eeh_dev(dn)->phb;
 
         /* USB Bus children of PCI devices will not have BUID's */
         if (NULL == phb || 0 == phb->buid)
                 return;
 
-        info.buid_hi = BUID_HI(phb->buid);
-        info.buid_lo = BUID_LO(phb->buid);
-        early_enable_eeh(dn, &info);
+        eeh_early_enable(dn, NULL);
 }
 
+/**
+ * eeh_add_device_tree_early - Enable EEH for the indicated device
+ * @dn: device node
+ *
+ * This routine must be used to perform EEH initialization for the
+ * indicated PCI device that was added after system boot (e.g.
+ * hotplug, dlpar).
+ */
 void eeh_add_device_tree_early(struct device_node *dn)
 {
         struct device_node *sib;
@@ -1210,7 +1068,7 @@ void eeh_add_device_tree_early(struct device_node *dn)
 EXPORT_SYMBOL_GPL(eeh_add_device_tree_early);
 
 /**
- * eeh_add_device_late - perform EEH initialization for the indicated pci device
+ * eeh_add_device_late - Perform EEH initialization for the indicated pci device
  * @dev: pci device for which to set up EEH
  *
  * This routine must be used to complete EEH initialization for PCI
@@ -1219,7 +1077,7 @@ EXPORT_SYMBOL_GPL(eeh_add_device_tree_early);
 static void eeh_add_device_late(struct pci_dev *dev)
 {
         struct device_node *dn;
-        struct pci_dn *pdn;
+        struct eeh_dev *edev;
 
         if (!dev || !eeh_subsystem_enabled)
                 return;
@@ -1227,20 +1085,29 @@ static void eeh_add_device_late(struct pci_dev *dev)
         pr_debug("EEH: Adding device %s\n", pci_name(dev));
 
         dn = pci_device_to_OF_node(dev);
-        pdn = PCI_DN(dn);
-        if (pdn->pcidev == dev) {
+        edev = pci_dev_to_eeh_dev(dev);
+        if (edev->pdev == dev) {
                 pr_debug("EEH: Already referenced !\n");
                 return;
         }
-        WARN_ON(pdn->pcidev);
+        WARN_ON(edev->pdev);
 
-        pci_dev_get (dev);
-        pdn->pcidev = dev;
+        pci_dev_get(dev);
+        edev->pdev = dev;
+        dev->dev.archdata.edev = edev;
 
         pci_addr_cache_insert_device(dev);
         eeh_sysfs_add_device(dev);
 }
 
+/**
+ * eeh_add_device_tree_late - Perform EEH initialization for the indicated PCI bus
+ * @bus: PCI bus
+ *
+ * This routine must be used to perform EEH initialization for PCI
+ * devices which are attached to the indicated PCI bus. The PCI bus
+ * is added after system boot through hotplug or dlpar.
+ */
 void eeh_add_device_tree_late(struct pci_bus *bus)
 {
         struct pci_dev *dev;
@@ -1257,7 +1124,7 @@ void eeh_add_device_tree_late(struct pci_bus *bus)
 EXPORT_SYMBOL_GPL(eeh_add_device_tree_late);
 
 /**
- * eeh_remove_device - undo EEH setup for the indicated pci device
+ * eeh_remove_device - Undo EEH setup for the indicated pci device
  * @dev: pci device to be removed
  *
  * This routine should be called when a device is removed from
@@ -1268,25 +1135,35 @@ EXPORT_SYMBOL_GPL(eeh_add_device_tree_late);
  */
 static void eeh_remove_device(struct pci_dev *dev)
 {
-        struct device_node *dn;
+        struct eeh_dev *edev;
+
         if (!dev || !eeh_subsystem_enabled)
                 return;
+        edev = pci_dev_to_eeh_dev(dev);
 
         /* Unregister the device with the EEH/PCI address search system */
         pr_debug("EEH: Removing device %s\n", pci_name(dev));
 
-        dn = pci_device_to_OF_node(dev);
-        if (PCI_DN(dn)->pcidev == NULL) {
+        if (!edev || !edev->pdev) {
                 pr_debug("EEH: Not referenced !\n");
                 return;
         }
-        PCI_DN(dn)->pcidev = NULL;
-        pci_dev_put (dev);
+        edev->pdev = NULL;
+        dev->dev.archdata.edev = NULL;
+        pci_dev_put(dev);
 
         pci_addr_cache_remove_device(dev);
         eeh_sysfs_remove_device(dev);
 }
 
+/**
+ * eeh_remove_bus_device - Undo EEH setup for the indicated PCI device
+ * @dev: PCI device
+ *
+ * This routine must be called when a device is removed from the
+ * running system through hotplug or dlpar. The corresponding
+ * PCI address cache will be removed.
+ */
 void eeh_remove_bus_device(struct pci_dev *dev)
 {
         struct pci_bus *bus = dev->subordinate;
@@ -1305,21 +1182,24 @@ static int proc_eeh_show(struct seq_file *m, void *v)
 {
         if (0 == eeh_subsystem_enabled) {
                 seq_printf(m, "EEH Subsystem is globally disabled\n");
-                seq_printf(m, "eeh_total_mmio_ffs=%ld\n", total_mmio_ffs);
+                seq_printf(m, "eeh_total_mmio_ffs=%llu\n", eeh_stats.total_mmio_ffs);
         } else {
                 seq_printf(m, "EEH Subsystem is enabled\n");
                 seq_printf(m,
-                                "no device=%ld\n"
-                                "no device node=%ld\n"
-                                "no config address=%ld\n"
-                                "check not wanted=%ld\n"
-                                "eeh_total_mmio_ffs=%ld\n"
-                                "eeh_false_positives=%ld\n"
-                                "eeh_slot_resets=%ld\n",
-                                no_device, no_dn, no_cfg_addr, 
-                                ignored_check, total_mmio_ffs, 
-                                false_positives,
-                                slot_resets);
+                                "no device=%llu\n"
+                                "no device node=%llu\n"
+                                "no config address=%llu\n"
+                                "check not wanted=%llu\n"
+                                "eeh_total_mmio_ffs=%llu\n"
+                                "eeh_false_positives=%llu\n"
+                                "eeh_slot_resets=%llu\n",
+                                eeh_stats.no_device,
+                                eeh_stats.no_dn,
+                                eeh_stats.no_cfg_addr,
+                                eeh_stats.ignored_check,
+                                eeh_stats.total_mmio_ffs,
+                                eeh_stats.false_positives,
+                                eeh_stats.slot_resets);
         }
 
         return 0;
diff --git a/arch/powerpc/platforms/pseries/eeh_cache.c b/arch/powerpc/platforms/pseries/eeh_cache.c
index fc5ae767989..e5ae1c687c6 100644
--- a/arch/powerpc/platforms/pseries/eeh_cache.c
+++ b/arch/powerpc/platforms/pseries/eeh_cache.c
@@ -1,5 +1,4 @@
 /*
- * eeh_cache.c
  * PCI address cache; allows the lookup of PCI devices based on I/O address
  *
  * Copyright IBM Corporation 2004
@@ -47,8 +46,7 @@
  * than any hash algo I could think of for this problem, even
  * with the penalty of slow pointer chases for d-cache misses).
  */
-struct pci_io_addr_range
-{
+struct pci_io_addr_range {
         struct rb_node rb_node;
         unsigned long addr_lo;
         unsigned long addr_hi;
@@ -56,13 +54,12 @@ struct pci_io_addr_range
         unsigned int flags;
 };
 
-static struct pci_io_addr_cache
-{
+static struct pci_io_addr_cache {
         struct rb_root rb_root;
         spinlock_t piar_lock;
 } pci_io_addr_cache_root;
 
-static inline struct pci_dev *__pci_get_device_by_addr(unsigned long addr)
+static inline struct pci_dev *__pci_addr_cache_get_device(unsigned long addr)
 {
         struct rb_node *n = pci_io_addr_cache_root.rb_root.rb_node;
 
@@ -86,7 +83,7 @@ static inline struct pci_dev *__pci_get_device_by_addr(unsigned long addr)
 }
 
 /**
- * pci_get_device_by_addr - Get device, given only address
+ * pci_addr_cache_get_device - Get device, given only address
  * @addr: mmio (PIO) phys address or i/o port number
  *
  * Given an mmio phys address, or a port number, find a pci device
@@ -95,13 +92,13 @@ static inline struct pci_dev *__pci_get_device_by_addr(unsigned long addr)
  * from zero (that is, they do *not* have pci_io_addr added in).
  * It is safe to call this function within an interrupt.
  */
-struct pci_dev *pci_get_device_by_addr(unsigned long addr)
+struct pci_dev *pci_addr_cache_get_device(unsigned long addr)
 {
         struct pci_dev *dev;
         unsigned long flags;
 
         spin_lock_irqsave(&pci_io_addr_cache_root.piar_lock, flags);
-        dev = __pci_get_device_by_addr(addr);
+        dev = __pci_addr_cache_get_device(addr);
         spin_unlock_irqrestore(&pci_io_addr_cache_root.piar_lock, flags);
         return dev;
 }
@@ -166,7 +163,7 @@ pci_addr_cache_insert(struct pci_dev *dev, unsigned long alo,
 
 #ifdef DEBUG
         printk(KERN_DEBUG "PIAR: insert range=[%lx:%lx] dev=%s\n",
-                          alo, ahi, pci_name (dev));
+                          alo, ahi, pci_name(dev));
 #endif
 
         rb_link_node(&piar->rb_node, parent, p);
@@ -178,7 +175,7 @@ pci_addr_cache_insert(struct pci_dev *dev, unsigned long alo,
 static void __pci_addr_cache_insert_device(struct pci_dev *dev)
 {
         struct device_node *dn;
-        struct pci_dn *pdn;
+        struct eeh_dev *edev;
         int i;
 
         dn = pci_device_to_OF_node(dev);
@@ -187,13 +184,19 @@ static void __pci_addr_cache_insert_device(struct pci_dev *dev)
                 return;
         }
 
+        edev = of_node_to_eeh_dev(dn);
+        if (!edev) {
+                pr_warning("PCI: no EEH dev found for dn=%s\n",
+                        dn->full_name);
+                return;
+        }
+
         /* Skip any devices for which EEH is not enabled. */
-        pdn = PCI_DN(dn);
-        if (!(pdn->eeh_mode & EEH_MODE_SUPPORTED) ||
-            pdn->eeh_mode & EEH_MODE_NOCHECK) {
+        if (!(edev->mode & EEH_MODE_SUPPORTED) ||
+            edev->mode & EEH_MODE_NOCHECK) {
 #ifdef DEBUG
-                printk(KERN_INFO "PCI: skip building address cache for=%s - %s\n",
-                       pci_name(dev), pdn->node->full_name);
+                pr_info("PCI: skip building address cache for=%s - %s\n",
+                        pci_name(dev), dn->full_name);
 #endif
                 return;
         }
@@ -284,6 +287,7 @@ void pci_addr_cache_remove_device(struct pci_dev *dev)
 void __init pci_addr_cache_build(void)
 {
         struct device_node *dn;
+        struct eeh_dev *edev;
         struct pci_dev *dev = NULL;
 
         spin_lock_init(&pci_io_addr_cache_root.piar_lock);
@@ -294,8 +298,14 @@ void __init pci_addr_cache_build(void)
                 dn = pci_device_to_OF_node(dev);
                 if (!dn)
                         continue;
+
+                edev = of_node_to_eeh_dev(dn);
+                if (!edev)
+                        continue;
+
                 pci_dev_get(dev);  /* matching put is in eeh_remove_device() */
-                PCI_DN(dn)->pcidev = dev;
+                dev->dev.archdata.edev = edev;
+                edev->pdev = dev;
 
                 eeh_sysfs_add_device(dev);
         }
diff --git a/arch/powerpc/platforms/pseries/eeh_dev.c b/arch/powerpc/platforms/pseries/eeh_dev.c
new file mode 100644
index 00000000000..f3aed7dcae9
--- /dev/null
+++ b/arch/powerpc/platforms/pseries/eeh_dev.c
@@ -0,0 +1,102 @@
+/*
+ * The file intends to implement dynamic creation of EEH device, which will
+ * be bound with OF node and PCI device simutaneously. The EEH devices would
+ * be foundamental information for EEH core components to work proerly. Besides,
+ * We have to support multiple situations where dynamic creation of EEH device
+ * is required:
+ *
+ * 1) Before PCI emunation starts, we need create EEH devices according to the
+ *    PCI sensitive OF nodes.
+ * 2) When PCI emunation is done, we need do the binding between PCI device and
+ *    the associated EEH device.
+ * 3) DR (Dynamic Reconfiguration) would create PCI sensitive OF node. EEH device
+ *    will be created while PCI sensitive OF node is detected from DR.
+ * 4) PCI hotplug needs redoing the binding between PCI device and EEH device. If
+ *    PHB is newly inserted, we also need create EEH devices accordingly.
+ *
+ * Copyright Benjamin Herrenschmidt & Gavin Shan, IBM Corporation 2012.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
+ */
+
+#include <linux/export.h>
+#include <linux/gfp.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/pci.h>
+#include <linux/string.h>
+
+#include <asm/pci-bridge.h>
+#include <asm/ppc-pci.h>
+
+/**
+ * eeh_dev_init - Create EEH device according to OF node
+ * @dn: device node
+ * @data: PHB
+ *
+ * It will create EEH device according to the given OF node. The function
+ * might be called by PCI emunation, DR, PHB hotplug.
+ */
+void * __devinit eeh_dev_init(struct device_node *dn, void *data)
+{
+        struct pci_controller *phb = data;
+        struct eeh_dev *edev;
+
+        /* Allocate EEH device */
+        edev = zalloc_maybe_bootmem(sizeof(*edev), GFP_KERNEL);
+        if (!edev) {
+                pr_warning("%s: out of memory\n", __func__);
+                return NULL;
+        }
+
+        /* Associate EEH device with OF node */
+        dn->edev  = edev;
+        edev->dn  = dn;
+        edev->phb = phb;
+
+        return NULL;
+}
+
+/**
+ * eeh_dev_phb_init_dynamic - Create EEH devices for devices included in PHB
+ * @phb: PHB
+ *
+ * Scan the PHB OF node and its child association, then create the
+ * EEH devices accordingly
+ */
+void __devinit eeh_dev_phb_init_dynamic(struct pci_controller *phb)
+{
+        struct device_node *dn = phb->dn;
+
+        /* EEH device for PHB */
+        eeh_dev_init(dn, phb);
+
+        /* EEH devices for children OF nodes */
+        traverse_pci_devices(dn, eeh_dev_init, phb);
+}
+
+/**
+ * eeh_dev_phb_init - Create EEH devices for devices included in existing PHBs
+ *
+ * Scan all the existing PHBs and create EEH devices for their OF
+ * nodes and their children OF nodes
+ */
+void __init eeh_dev_phb_init(void)
+{
+        struct pci_controller *phb, *tmp;
+
+        list_for_each_entry_safe(phb, tmp, &hose_list, list_node)
+                eeh_dev_phb_init_dynamic(phb);
+}
diff --git a/arch/powerpc/platforms/pseries/eeh_driver.c b/arch/powerpc/platforms/pseries/eeh_driver.c
index 1b6cb10589e..baf92cd9dfa 100644
--- a/arch/powerpc/platforms/pseries/eeh_driver.c
+++ b/arch/powerpc/platforms/pseries/eeh_driver.c
@@ -33,8 +33,14 @@
 #include <asm/prom.h>
 #include <asm/rtas.h>
 
-
-static inline const char * pcid_name (struct pci_dev *pdev)
+/**
+ * eeh_pcid_name - Retrieve name of PCI device driver
+ * @pdev: PCI device
+ *
+ * This routine is used to retrieve the name of PCI device driver
+ * if that's valid.
+ */
+static inline const char *eeh_pcid_name(struct pci_dev *pdev)
 {
         if (pdev && pdev->dev.driver)
                 return pdev->dev.driver->name;
@@ -64,48 +70,59 @@ static void print_device_node_tree(struct pci_dn *pdn, int dent)
 #endif
 
 /**
- * eeh_disable_irq - disable interrupt for the recovering device
+ * eeh_disable_irq - Disable interrupt for the recovering device
+ * @dev: PCI device
+ *
+ * This routine must be called when reporting temporary or permanent
+ * error to the particular PCI device to disable interrupt of that
+ * device. If the device has enabled MSI or MSI-X interrupt, we needn't
+ * do real work because EEH should freeze DMA transfers for those PCI
+ * devices encountering EEH errors, which includes MSI or MSI-X.
  */
 static void eeh_disable_irq(struct pci_dev *dev)
 {
-        struct device_node *dn = pci_device_to_OF_node(dev);
+        struct eeh_dev *edev = pci_dev_to_eeh_dev(dev);
 
         /* Don't disable MSI and MSI-X interrupts. They are
          * effectively disabled by the DMA Stopped state
          * when an EEH error occurs.
-        */
+         */
         if (dev->msi_enabled || dev->msix_enabled)
                 return;
 
         if (!irq_has_action(dev->irq))
                 return;
 
-        PCI_DN(dn)->eeh_mode |= EEH_MODE_IRQ_DISABLED;
+        edev->mode |= EEH_MODE_IRQ_DISABLED;
         disable_irq_nosync(dev->irq);
 }
 
 /**
- * eeh_enable_irq - enable interrupt for the recovering device
+ * eeh_enable_irq - Enable interrupt for the recovering device
+ * @dev: PCI device
+ *
+ * This routine must be called to enable interrupt while failed
+ * device could be resumed.
  */
 static void eeh_enable_irq(struct pci_dev *dev)
 {
-        struct device_node *dn = pci_device_to_OF_node(dev);
+        struct eeh_dev *edev = pci_dev_to_eeh_dev(dev);
 
-        if ((PCI_DN(dn)->eeh_mode) & EEH_MODE_IRQ_DISABLED) {
-                PCI_DN(dn)->eeh_mode &= ~EEH_MODE_IRQ_DISABLED;
+        if ((edev->mode) & EEH_MODE_IRQ_DISABLED) {
+                edev->mode &= ~EEH_MODE_IRQ_DISABLED;
                 enable_irq(dev->irq);
         }
 }
 
-/* ------------------------------------------------------- */
 /**
- * eeh_report_error - report pci error to each device driver
+ * eeh_report_error - Report pci error to each device driver
+ * @dev: PCI device
+ * @userdata: return value
  * 
  * Report an EEH error to each device driver, collect up and 
  * merge the device driver responses. Cumulative response 
  * passed back in "userdata".
  */
-
 static int eeh_report_error(struct pci_dev *dev, void *userdata)
 {
         enum pci_ers_result rc, *res = userdata;
@@ -122,7 +139,7 @@ static int eeh_report_error(struct pci_dev *dev, void *userdata)
             !driver->err_handler->error_detected)
                 return 0;
 
-        rc = driver->err_handler->error_detected (dev, pci_channel_io_frozen);
+        rc = driver->err_handler->error_detected(dev, pci_channel_io_frozen);
 
         /* A driver that needs a reset trumps all others */
         if (rc == PCI_ERS_RESULT_NEED_RESET) *res = rc;
@@ -132,13 +149,14 @@ static int eeh_report_error(struct pci_dev *dev, void *userdata)
 }
 
 /**
- * eeh_report_mmio_enabled - tell drivers that MMIO has been enabled
+ * eeh_report_mmio_enabled - Tell drivers that MMIO has been enabled
+ * @dev: PCI device
+ * @userdata: return value
  *
  * Tells each device driver that IO ports, MMIO and config space I/O
  * are now enabled. Collects up and merges the device driver responses.
  * Cumulative response passed back in "userdata".
  */
-
 static int eeh_report_mmio_enabled(struct pci_dev *dev, void *userdata)
 {
         enum pci_ers_result rc, *res = userdata;
@@ -149,7 +167,7 @@ static int eeh_report_mmio_enabled(struct pci_dev *dev, void *userdata)
             !driver->err_handler->mmio_enabled)
                 return 0;
 
-        rc = driver->err_handler->mmio_enabled (dev);
+        rc = driver->err_handler->mmio_enabled(dev);
 
         /* A driver that needs a reset trumps all others */
         if (rc == PCI_ERS_RESULT_NEED_RESET) *res = rc;
@@ -159,9 +177,15 @@ static int eeh_report_mmio_enabled(struct pci_dev *dev, void *userdata)
 }
 
 /**
- * eeh_report_reset - tell device that slot has been reset
+ * eeh_report_reset - Tell device that slot has been reset
+ * @dev: PCI device
+ * @userdata: return value
+ *
+ * This routine must be called while EEH tries to reset particular
+ * PCI device so that the associated PCI device driver could take
+ * some actions, usually to save data the driver needs so that the
+ * driver can work again while the device is recovered.
  */
-
 static int eeh_report_reset(struct pci_dev *dev, void *userdata)
 {
         enum pci_ers_result rc, *res = userdata;
@@ -188,9 +212,14 @@ static int eeh_report_reset(struct pci_dev *dev, void *userdata)
 }
 
 /**
- * eeh_report_resume - tell device to resume normal operations
+ * eeh_report_resume - Tell device to resume normal operations
+ * @dev: PCI device
+ * @userdata: return value
+ *
+ * This routine must be called to notify the device driver that it
+ * could resume so that the device driver can do some initialization
+ * to make the recovered device work again.
  */
-
 static int eeh_report_resume(struct pci_dev *dev, void *userdata)
 {
         struct pci_driver *driver = dev->driver;
@@ -212,12 +241,13 @@ static int eeh_report_resume(struct pci_dev *dev, void *userdata)
 }
 
 /**
- * eeh_report_failure - tell device driver that device is dead.
+ * eeh_report_failure - Tell device driver that device is dead.
+ * @dev: PCI device
+ * @userdata: return value
  *
  * This informs the device driver that the device is permanently
  * dead, and that no further recovery attempts will be made on it.
  */
-
 static int eeh_report_failure(struct pci_dev *dev, void *userdata)
 {
         struct pci_driver *driver = dev->driver;
@@ -238,65 +268,46 @@ static int eeh_report_failure(struct pci_dev *dev, void *userdata)
         return 0;
 }
 
-/* ------------------------------------------------------- */
 /**
- * handle_eeh_events -- reset a PCI device after hard lockup.
- *
- * pSeries systems will isolate a PCI slot if the PCI-Host
- * bridge detects address or data parity errors, DMA's
- * occurring to wild addresses (which usually happen due to
- * bugs in device drivers or in PCI adapter firmware).
- * Slot isolations also occur if #SERR, #PERR or other misc
- * PCI-related errors are detected.
+ * eeh_reset_device - Perform actual reset of a pci slot
+ * @edev: PE associated EEH device
+ * @bus: PCI bus corresponding to the isolcated slot
  *
- * Recovery process consists of unplugging the device driver
- * (which generated hotplug events to userspace), then issuing
- * a PCI #RST to the device, then reconfiguring the PCI config
- * space for all bridges & devices under this slot, and then
- * finally restarting the device drivers (which cause a second
- * set of hotplug events to go out to userspace).
+ * This routine must be called to do reset on the indicated PE.
+ * During the reset, udev might be invoked because those affected
+ * PCI devices will be removed and then added.
  */
-
-/**
- * eeh_reset_device() -- perform actual reset of a pci slot
- * @bus: pointer to the pci bus structure corresponding
- *            to the isolated slot. A non-null value will
- *            cause all devices under the bus to be removed
- *            and then re-added.
- * @pe_dn: pointer to a "Partionable Endpoint" device node.
- *            This is the top-level structure on which pci
- *            bus resets can be performed.
- */
-
-static int eeh_reset_device (struct pci_dn *pe_dn, struct pci_bus *bus)
+static int eeh_reset_device(struct eeh_dev *edev, struct pci_bus *bus)
 {
         struct device_node *dn;
         int cnt, rc;
 
         /* pcibios will clear the counter; save the value */
-        cnt = pe_dn->eeh_freeze_count;
+        cnt = edev->freeze_count;
 
         if (bus)
                 pcibios_remove_pci_devices(bus);
 
         /* Reset the pci controller. (Asserts RST#; resets config space).
          * Reconfigure bridges and devices. Don't try to bring the system
-         * up if the reset failed for some reason. */
-        rc = rtas_set_slot_reset(pe_dn);
+         * up if the reset failed for some reason.
+         */
+        rc = eeh_reset_pe(edev);
         if (rc)
                 return rc;
 
-        /* Walk over all functions on this device.  */
-        dn = pe_dn->node;
-        if (!pcibios_find_pci_bus(dn) && PCI_DN(dn->parent))
+        /* Walk over all functions on this device. */
+        dn = eeh_dev_to_of_node(edev);
+        if (!pcibios_find_pci_bus(dn) && of_node_to_eeh_dev(dn->parent))
                 dn = dn->parent->child;
 
         while (dn) {
-                struct pci_dn *ppe = PCI_DN(dn);
+                struct eeh_dev *pedev = of_node_to_eeh_dev(dn);
+
                 /* On Power4, always true because eeh_pe_config_addr=0 */
-                if (pe_dn->eeh_pe_config_addr == ppe->eeh_pe_config_addr) {
-                        rtas_configure_bridge(ppe);
-                        eeh_restore_bars(ppe);
+                if (edev->pe_config_addr == pedev->pe_config_addr) {
+                        eeh_ops->configure_bridge(dn);
+                        eeh_restore_bars(pedev);
                 }
                 dn = dn->sibling;
         }
@@ -308,10 +319,10 @@ static int eeh_reset_device (struct pci_dn *pe_dn, struct pci_bus *bus)
          * potentially weird things happen.
          */
         if (bus) {
-                ssleep (5);
+                ssleep(5);
                 pcibios_add_pci_devices(bus);
         }
-        pe_dn->eeh_freeze_count = cnt;
+        edev->freeze_count = cnt;
 
         return 0;
 }
@@ -321,23 +332,39 @@ static int eeh_reset_device (struct pci_dn *pe_dn, struct pci_bus *bus)
  */
 #define MAX_WAIT_FOR_RECOVERY 150
 
-struct pci_dn * handle_eeh_events (struct eeh_event *event)
+/**
+ * eeh_handle_event - Reset a PCI device after hard lockup.
+ * @event: EEH event
+ *
+ * While PHB detects address or data parity errors on particular PCI
+ * slot, the associated PE will be frozen. Besides, DMA's occurring
+ * to wild addresses (which usually happen due to bugs in device
+ * drivers or in PCI adapter firmware) can cause EEH error. #SERR,
+ * #PERR or other misc PCI-related errors also can trigger EEH errors.
+ *
+ * Recovery process consists of unplugging the device driver (which
+ * generated hotplug events to userspace), then issuing a PCI #RST to
+ * the device, then reconfiguring the PCI config space for all bridges
+ * & devices under this slot, and then finally restarting the device
+ * drivers (which cause a second set of hotplug events to go out to
+ * userspace).
+ */
+struct eeh_dev *handle_eeh_events(struct eeh_event *event)
 {
         struct device_node *frozen_dn;
-        struct pci_dn *frozen_pdn;
+        struct eeh_dev *frozen_edev;
         struct pci_bus *frozen_bus;
         int rc = 0;
         enum pci_ers_result result = PCI_ERS_RESULT_NONE;
         const char *location, *pci_str, *drv_str, *bus_pci_str, *bus_drv_str;
 
-        frozen_dn = find_device_pe(event->dn);
+        frozen_dn = eeh_find_device_pe(eeh_dev_to_of_node(event->edev));
         if (!frozen_dn) {
-
-                location = of_get_property(event->dn, "ibm,loc-code", NULL);
+                location = of_get_property(eeh_dev_to_of_node(event->edev), "ibm,loc-code", NULL);
                 location = location ? location : "unknown";
                 printk(KERN_ERR "EEH: Error: Cannot find partition endpoint "
                                 "for location=%s pci addr=%s\n",
-                        location, eeh_pci_name(event->dev));
+                        location, eeh_pci_name(eeh_dev_to_pci_dev(event->edev)));
                 return NULL;
         }
 
@@ -350,9 +377,10 @@ struct pci_dn * handle_eeh_events (struct eeh_event *event)
          * which was always an EADS pci bridge.  In the new style,
          * there might not be any EADS bridges, and even when there are,
          * the firmware marks them as "EEH incapable". So another
-         * two-step is needed to find the pci bus.. */
+         * two-step is needed to find the pci bus..
+         */
         if (!frozen_bus)
-                frozen_bus = pcibios_find_pci_bus (frozen_dn->parent);
+                frozen_bus = pcibios_find_pci_bus(frozen_dn->parent);
 
         if (!frozen_bus) {
                 printk(KERN_ERR "EEH: Cannot find PCI bus "
@@ -361,22 +389,21 @@ struct pci_dn * handle_eeh_events (struct eeh_event *event)
                 return NULL;
         }
 
-        frozen_pdn = PCI_DN(frozen_dn);
-        frozen_pdn->eeh_freeze_count++;
+        frozen_edev = of_node_to_eeh_dev(frozen_dn);
+        frozen_edev->freeze_count++;
+        pci_str = eeh_pci_name(eeh_dev_to_pci_dev(event->edev));
+        drv_str = eeh_pcid_name(eeh_dev_to_pci_dev(event->edev));
 
-        pci_str = eeh_pci_name(event->dev);
-        drv_str = pcid_name(event->dev);
-        
-        if (frozen_pdn->eeh_freeze_count > EEH_MAX_ALLOWED_FREEZES)
+        if (frozen_edev->freeze_count > EEH_MAX_ALLOWED_FREEZES)
                 goto excess_failures;
 
         printk(KERN_WARNING
            "EEH: This PCI device has failed %d times in the last hour:\n",
-                frozen_pdn->eeh_freeze_count);
+                frozen_edev->freeze_count);
 
-        if (frozen_pdn->pcidev) {
-                bus_pci_str = pci_name(frozen_pdn->pcidev);
-                bus_drv_str = pcid_name(frozen_pdn->pcidev);
+        if (frozen_edev->pdev) {
+                bus_pci_str = pci_name(frozen_edev->pdev);
+                bus_drv_str = eeh_pcid_name(frozen_edev->pdev);
                 printk(KERN_WARNING
                         "EEH: Bus location=%s driver=%s pci addr=%s\n",
                         location, bus_drv_str, bus_pci_str);
@@ -395,9 +422,10 @@ struct pci_dn * handle_eeh_events (struct eeh_event *event)
         pci_walk_bus(frozen_bus, eeh_report_error, &result);
 
         /* Get the current PCI slot state. This can take a long time,
-         * sometimes over 3 seconds for certain systems. */
-        rc = eeh_wait_for_slot_status (frozen_pdn, MAX_WAIT_FOR_RECOVERY*1000);
-        if (rc < 0) {
+         * sometimes over 3 seconds for certain systems.
+         */
+        rc = eeh_ops->wait_state(eeh_dev_to_of_node(frozen_edev), MAX_WAIT_FOR_RECOVERY*1000);
+        if (rc < 0 || rc == EEH_STATE_NOT_SUPPORT) {
                 printk(KERN_WARNING "EEH: Permanent failure\n");
                 goto hard_fail;
         }
@@ -406,14 +434,14 @@ struct pci_dn * handle_eeh_events (struct eeh_event *event)
          * don't post the error log until after all dev drivers
          * have been informed.
          */
-        eeh_slot_error_detail(frozen_pdn, EEH_LOG_TEMP_FAILURE);
+        eeh_slot_error_detail(frozen_edev, EEH_LOG_TEMP);
 
         /* If all device drivers were EEH-unaware, then shut
          * down all of the device drivers, and hope they
          * go down willingly, without panicing the system.
          */
         if (result == PCI_ERS_RESULT_NONE) {
-                rc = eeh_reset_device(frozen_pdn, frozen_bus);
+                rc = eeh_reset_device(frozen_edev, frozen_bus);
                 if (rc) {
                         printk(KERN_WARNING "EEH: Unable to reset, rc=%d\n", rc);
                         goto hard_fail;
@@ -422,7 +450,7 @@ struct pci_dn * handle_eeh_events (struct eeh_event *event)
 
         /* If all devices reported they can proceed, then re-enable MMIO */
         if (result == PCI_ERS_RESULT_CAN_RECOVER) {
-                rc = rtas_pci_enable(frozen_pdn, EEH_THAW_MMIO);
+                rc = eeh_pci_enable(frozen_edev, EEH_OPT_THAW_MMIO);
 
                 if (rc < 0)
                         goto hard_fail;
@@ -436,7 +464,7 @@ struct pci_dn * handle_eeh_events (struct eeh_event *event)
 
         /* If all devices reported they can proceed, then re-enable DMA */
         if (result == PCI_ERS_RESULT_CAN_RECOVER) {
-                rc = rtas_pci_enable(frozen_pdn, EEH_THAW_DMA);
+                rc = eeh_pci_enable(frozen_edev, EEH_OPT_THAW_DMA);
 
                 if (rc < 0)
                         goto hard_fail;
@@ -454,7 +482,7 @@ struct pci_dn * handle_eeh_events (struct eeh_event *event)
 
         /* If any device called out for a reset, then reset the slot */
         if (result == PCI_ERS_RESULT_NEED_RESET) {
-                rc = eeh_reset_device(frozen_pdn, NULL);
+                rc = eeh_reset_device(frozen_edev, NULL);
                 if (rc) {
                         printk(KERN_WARNING "EEH: Cannot reset, rc=%d\n", rc);
                         goto hard_fail;
@@ -473,7 +501,7 @@ struct pci_dn * handle_eeh_events (struct eeh_event *event)
         /* Tell all device drivers that they can resume operations */
         pci_walk_bus(frozen_bus, eeh_report_resume, NULL);
 
-        return frozen_pdn;
+        return frozen_edev;
         
 excess_failures:
         /*
@@ -486,7 +514,7 @@ excess_failures:
                 "has failed %d times in the last hour "
                 "and has been permanently disabled.\n"
                 "Please try reseating this device or replacing it.\n",
-                location, drv_str, pci_str, frozen_pdn->eeh_freeze_count);
+                location, drv_str, pci_str, frozen_edev->freeze_count);
         goto perm_error;
 
 hard_fail:
@@ -497,7 +525,7 @@ hard_fail:
                 location, drv_str, pci_str);
 
 perm_error:
-        eeh_slot_error_detail(frozen_pdn, EEH_LOG_PERM_FAILURE);
+        eeh_slot_error_detail(frozen_edev, EEH_LOG_PERM);
 
         /* Notify all devices that they're about to go down. */
         pci_walk_bus(frozen_bus, eeh_report_failure, NULL);
@@ -508,4 +536,3 @@ perm_error:
         return NULL;
 }
 
-/* ---------- end of file ---------- */
diff --git a/arch/powerpc/platforms/pseries/eeh_event.c b/arch/powerpc/platforms/pseries/eeh_event.c
index d2383cfb6df..4a475256585 100644
--- a/arch/powerpc/platforms/pseries/eeh_event.c
+++ b/arch/powerpc/platforms/pseries/eeh_event.c
@@ -1,6 +1,4 @@
 /*
- * eeh_event.c
- *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
  * the Free Software Foundation; either version 2 of the License, or
@@ -46,7 +44,7 @@ DECLARE_WORK(eeh_event_wq, eeh_thread_launcher);
 DEFINE_MUTEX(eeh_event_mutex);
 
 /**
- * eeh_event_handler - dispatch EEH events.
+ * eeh_event_handler - Dispatch EEH events.
  * @dummy - unused
  *
  * The detection of a frozen slot can occur inside an interrupt,
@@ -58,10 +56,10 @@ DEFINE_MUTEX(eeh_event_mutex);
 static int eeh_event_handler(void * dummy)
 {
         unsigned long flags;
-        struct eeh_event        *event;
-        struct pci_dn *pdn;
+        struct eeh_event *event;
+        struct eeh_dev *edev;
 
-        daemonize ("eehd");
+        daemonize("eehd");
         set_current_state(TASK_INTERRUPTIBLE);
 
         spin_lock_irqsave(&eeh_eventlist_lock, flags);
@@ -79,31 +77,37 @@ static int eeh_event_handler(void * dummy)
 
         /* Serialize processing of EEH events */
         mutex_lock(&eeh_event_mutex);
-        eeh_mark_slot(event->dn, EEH_MODE_RECOVERING);
+        edev = event->edev;
+        eeh_mark_slot(eeh_dev_to_of_node(edev), EEH_MODE_RECOVERING);
 
         printk(KERN_INFO "EEH: Detected PCI bus error on device %s\n",
-               eeh_pci_name(event->dev));
+               eeh_pci_name(edev->pdev));
+
+        edev = handle_eeh_events(event);
 
-        pdn = handle_eeh_events(event);
+        eeh_clear_slot(eeh_dev_to_of_node(edev), EEH_MODE_RECOVERING);
+        pci_dev_put(edev->pdev);
 
-        eeh_clear_slot(event->dn, EEH_MODE_RECOVERING);
-        pci_dev_put(event->dev);
         kfree(event);
         mutex_unlock(&eeh_event_mutex);
 
         /* If there are no new errors after an hour, clear the counter. */
-        if (pdn && pdn->eeh_freeze_count>0) {
-                msleep_interruptible (3600*1000);
-                if (pdn->eeh_freeze_count>0)
-                        pdn->eeh_freeze_count--;
+        if (edev && edev->freeze_count>0) {
+                msleep_interruptible(3600*1000);
+                if (edev->freeze_count>0)
+                        edev->freeze_count--;
+
         }
 
         return 0;
 }
 
 /**
- * eeh_thread_launcher
+ * eeh_thread_launcher - Start kernel thread to handle EEH events
  * @dummy - unused
+ *
+ * This routine is called to start the kernel thread for processing
+ * EEH event.
  */
 static void eeh_thread_launcher(struct work_struct *dummy)
 {
@@ -112,18 +116,18 @@ static void eeh_thread_launcher(struct work_struct *dummy)
 }
 
 /**
- * eeh_send_failure_event - generate a PCI error event
- * @dev pci device
+ * eeh_send_failure_event - Generate a PCI error event
+ * @edev: EEH device
  *
  * This routine can be called within an interrupt context;
  * the actual event will be delivered in a normal context
  * (from a workqueue).
  */
-int eeh_send_failure_event (struct device_node *dn,
-                            struct pci_dev *dev)
+int eeh_send_failure_event(struct eeh_dev *edev)
 {
         unsigned long flags;
         struct eeh_event *event;
+        struct device_node *dn = eeh_dev_to_of_node(edev);
         const char *location;
 
         if (!mem_init_done) {
@@ -135,15 +139,14 @@ int eeh_send_failure_event (struct device_node *dn,
         }
         event = kmalloc(sizeof(*event), GFP_ATOMIC);
         if (event == NULL) {
-                printk (KERN_ERR "EEH: out of memory, event not handled\n");
+                printk(KERN_ERR "EEH: out of memory, event not handled\n");
                 return 1;
         }
 
-        if (dev)
-                pci_dev_get(dev);
+        if (edev->pdev)
+                pci_dev_get(edev->pdev);
 
-        event->dn = dn;
-        event->dev = dev;
+        event->edev = edev;
 
         /* We may or may not be called in an interrupt context */
         spin_lock_irqsave(&eeh_eventlist_lock, flags);
@@ -154,5 +157,3 @@ int eeh_send_failure_event (struct device_node *dn,
 
         return 0;
 }
-
-/********************** END OF FILE ******************************/
diff --git a/arch/powerpc/platforms/pseries/eeh_pseries.c b/arch/powerpc/platforms/pseries/eeh_pseries.c
new file mode 100644
index 00000000000..8752f79a6af
--- /dev/null
+++ b/arch/powerpc/platforms/pseries/eeh_pseries.c
@@ -0,0 +1,565 @@
+/*
+ * The file intends to implement the platform dependent EEH operations on pseries.
+ * Actually, the pseries platform is built based on RTAS heavily. That means the
+ * pseries platform dependent EEH operations will be built on RTAS calls. The functions
+ * are devired from arch/powerpc/platforms/pseries/eeh.c and necessary cleanup has
+ * been done.
+ *
+ * Copyright Benjamin Herrenschmidt & Gavin Shan, IBM Corporation 2011.
+ * Copyright IBM Corporation 2001, 2005, 2006
+ * Copyright Dave Engebretsen & Todd Inglett 2001
+ * Copyright Linas Vepstas 2005, 2006
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
+ */
+
+#include <linux/atomic.h>
+#include <linux/delay.h>
+#include <linux/export.h>
+#include <linux/init.h>
+#include <linux/list.h>
+#include <linux/of.h>
+#include <linux/pci.h>
+#include <linux/proc_fs.h>
+#include <linux/rbtree.h>
+#include <linux/sched.h>
+#include <linux/seq_file.h>
+#include <linux/spinlock.h>
+
+#include <asm/eeh.h>
+#include <asm/eeh_event.h>
+#include <asm/io.h>
+#include <asm/machdep.h>
+#include <asm/ppc-pci.h>
+#include <asm/rtas.h>
+
+/* RTAS tokens */
+static int ibm_set_eeh_option;
+static int ibm_set_slot_reset;
+static int ibm_read_slot_reset_state;
+static int ibm_read_slot_reset_state2;
+static int ibm_slot_error_detail;
+static int ibm_get_config_addr_info;
+static int ibm_get_config_addr_info2;
+static int ibm_configure_bridge;
+static int ibm_configure_pe;
+
+/*
+ * Buffer for reporting slot-error-detail rtas calls. Its here
+ * in BSS, and not dynamically alloced, so that it ends up in
+ * RMO where RTAS can access it.
+ */
+static unsigned char slot_errbuf[RTAS_ERROR_LOG_MAX];
+static DEFINE_SPINLOCK(slot_errbuf_lock);
+static int eeh_error_buf_size;
+
+/**
+ * pseries_eeh_init - EEH platform dependent initialization
+ *
+ * EEH platform dependent initialization on pseries.
+ */
+static int pseries_eeh_init(void)
+{
+        /* figure out EEH RTAS function call tokens */
+        ibm_set_eeh_option              = rtas_token("ibm,set-eeh-option");
+        ibm_set_slot_reset              = rtas_token("ibm,set-slot-reset");
+        ibm_read_slot_reset_state2      = rtas_token("ibm,read-slot-reset-state2");
+        ibm_read_slot_reset_state       = rtas_token("ibm,read-slot-reset-state");
+        ibm_slot_error_detail           = rtas_token("ibm,slot-error-detail");
+        ibm_get_config_addr_info2       = rtas_token("ibm,get-config-addr-info2");
+        ibm_get_config_addr_info        = rtas_token("ibm,get-config-addr-info");
+        ibm_configure_pe                = rtas_token("ibm,configure-pe");
+        ibm_configure_bridge            = rtas_token ("ibm,configure-bridge");
+
+        /* necessary sanity check */
+        if (ibm_set_eeh_option == RTAS_UNKNOWN_SERVICE) {
+                pr_warning("%s: RTAS service <ibm,set-eeh-option> invalid\n",
+                        __func__);
+                return -EINVAL;
+        } else if (ibm_set_slot_reset == RTAS_UNKNOWN_SERVICE) {
+                pr_warning("%s: RTAS service <ibm, set-slot-reset> invalid\n",
+                        __func__);
+                return -EINVAL;
+        } else if (ibm_read_slot_reset_state2 == RTAS_UNKNOWN_SERVICE &&
+                   ibm_read_slot_reset_state == RTAS_UNKNOWN_SERVICE) {
+                pr_warning("%s: RTAS service <ibm,read-slot-reset-state2> and "
+                        "<ibm,read-slot-reset-state> invalid\n",
+                        __func__);
+                return -EINVAL;
+        } else if (ibm_slot_error_detail == RTAS_UNKNOWN_SERVICE) {
+                pr_warning("%s: RTAS service <ibm,slot-error-detail> invalid\n",
+                        __func__);
+                return -EINVAL;
+        } else if (ibm_get_config_addr_info2 == RTAS_UNKNOWN_SERVICE &&
+                   ibm_get_config_addr_info == RTAS_UNKNOWN_SERVICE) {
+                pr_warning("%s: RTAS service <ibm,get-config-addr-info2> and "
+                        "<ibm,get-config-addr-info> invalid\n",
+                        __func__);
+                return -EINVAL;
+        } else if (ibm_configure_pe == RTAS_UNKNOWN_SERVICE &&
+                   ibm_configure_bridge == RTAS_UNKNOWN_SERVICE) {
+                pr_warning("%s: RTAS service <ibm,configure-pe> and "
+                        "<ibm,configure-bridge> invalid\n",
+                        __func__);
+                return -EINVAL;
+        }
+
+        /* Initialize error log lock and size */
+        spin_lock_init(&slot_errbuf_lock);
+        eeh_error_buf_size = rtas_token("rtas-error-log-max");
+        if (eeh_error_buf_size == RTAS_UNKNOWN_SERVICE) {
+                pr_warning("%s: unknown EEH error log size\n",
+                        __func__);
+                eeh_error_buf_size = 1024;
+        } else if (eeh_error_buf_size > RTAS_ERROR_LOG_MAX) {
+                pr_warning("%s: EEH error log size %d exceeds the maximal %d\n",
+                        __func__, eeh_error_buf_size, RTAS_ERROR_LOG_MAX);
+                eeh_error_buf_size = RTAS_ERROR_LOG_MAX;
+        }
+
+        return 0;
+}
+
+/**
+ * pseries_eeh_set_option - Initialize EEH or MMIO/DMA reenable
+ * @dn: device node
+ * @option: operation to be issued
+ *
+ * The function is used to control the EEH functionality globally.
+ * Currently, following options are support according to PAPR:
+ * Enable EEH, Disable EEH, Enable MMIO and Enable DMA
+ */
+static int pseries_eeh_set_option(struct device_node *dn, int option)
+{
+        int ret = 0;
+        struct eeh_dev *edev;
+        const u32 *reg;
+        int config_addr;
+
+        edev = of_node_to_eeh_dev(dn);
+
+        /*
+         * When we're enabling or disabling EEH functioality on
+         * the particular PE, the PE config address is possibly
+         * unavailable. Therefore, we have to figure it out from
+         * the FDT node.
+         */
+        switch (option) {
+        case EEH_OPT_DISABLE:
+        case EEH_OPT_ENABLE:
+                reg = of_get_property(dn, "reg", NULL);
+                config_addr = reg[0];
+                break;
+
+        case EEH_OPT_THAW_MMIO:
+        case EEH_OPT_THAW_DMA:
+                config_addr = edev->config_addr;
+                if (edev->pe_config_addr)
+                        config_addr = edev->pe_config_addr;
+                break;
+
+        default:
+                pr_err("%s: Invalid option %d\n",
+                        __func__, option);
+                return -EINVAL;
+        }
+
+        ret = rtas_call(ibm_set_eeh_option, 4, 1, NULL,
+                        config_addr, BUID_HI(edev->phb->buid),
+                        BUID_LO(edev->phb->buid), option);
+
+        return ret;
+}
+
+/**
+ * pseries_eeh_get_pe_addr - Retrieve PE address
+ * @dn: device node
+ *
+ * Retrieve the assocated PE address. Actually, there're 2 RTAS
+ * function calls dedicated for the purpose. We need implement
+ * it through the new function and then the old one. Besides,
+ * you should make sure the config address is figured out from
+ * FDT node before calling the function.
+ *
+ * It's notable that zero'ed return value means invalid PE config
+ * address.
+ */
+static int pseries_eeh_get_pe_addr(struct device_node *dn)
+{
+        struct eeh_dev *edev;
+        int ret = 0;
+        int rets[3];
+
+        edev = of_node_to_eeh_dev(dn);
+
+        if (ibm_get_config_addr_info2 != RTAS_UNKNOWN_SERVICE) {
+                /*
+                 * First of all, we need to make sure there has one PE
+                 * associated with the device. Otherwise, PE address is
+                 * meaningless.
+                 */
+                ret = rtas_call(ibm_get_config_addr_info2, 4, 2, rets,
+                                edev->config_addr, BUID_HI(edev->phb->buid),
+                                BUID_LO(edev->phb->buid), 1);
+                if (ret || (rets[0] == 0))
+                        return 0;
+
+                /* Retrieve the associated PE config address */
+                ret = rtas_call(ibm_get_config_addr_info2, 4, 2, rets,
+                                edev->config_addr, BUID_HI(edev->phb->buid),
+                                BUID_LO(edev->phb->buid), 0);
+                if (ret) {
+                        pr_warning("%s: Failed to get PE address for %s\n",
+                                __func__, dn->full_name);
+                        return 0;
+                }
+
+                return rets[0];
+        }
+
+        if (ibm_get_config_addr_info != RTAS_UNKNOWN_SERVICE) {
+                ret = rtas_call(ibm_get_config_addr_info, 4, 2, rets,
+                                edev->config_addr, BUID_HI(edev->phb->buid),
+                                BUID_LO(edev->phb->buid), 0);
+                if (ret) {
+                        pr_warning("%s: Failed to get PE address for %s\n",
+                                __func__, dn->full_name);
+                        return 0;
+                }
+
+                return rets[0];
+        }
+
+        return ret;
+}
+
+/**
+ * pseries_eeh_get_state - Retrieve PE state
+ * @dn: PE associated device node
+ * @state: return value
+ *
+ * Retrieve the state of the specified PE. On RTAS compliant
+ * pseries platform, there already has one dedicated RTAS function
+ * for the purpose. It's notable that the associated PE config address
+ * might be ready when calling the function. Therefore, endeavour to
+ * use the PE config address if possible. Further more, there're 2
+ * RTAS calls for the purpose, we need to try the new one and back
+ * to the old one if the new one couldn't work properly.
+ */
+static int pseries_eeh_get_state(struct device_node *dn, int *state)
+{
+        struct eeh_dev *edev;
+        int config_addr;
+        int ret;
+        int rets[4];
+        int result;
+
+        /* Figure out PE config address if possible */
+        edev = of_node_to_eeh_dev(dn);
+        config_addr = edev->config_addr;
+        if (edev->pe_config_addr)
+                config_addr = edev->pe_config_addr;
+
+        if (ibm_read_slot_reset_state2 != RTAS_UNKNOWN_SERVICE) {
+                ret = rtas_call(ibm_read_slot_reset_state2, 3, 4, rets,
+                                config_addr, BUID_HI(edev->phb->buid),
+                                BUID_LO(edev->phb->buid));
+        } else if (ibm_read_slot_reset_state != RTAS_UNKNOWN_SERVICE) {
+                /* Fake PE unavailable info */
+                rets[2] = 0;
+                ret = rtas_call(ibm_read_slot_reset_state, 3, 3, rets,
+                                config_addr, BUID_HI(edev->phb->buid),
+                                BUID_LO(edev->phb->buid));
+        } else {
+                return EEH_STATE_NOT_SUPPORT;
+        }
+
+        if (ret)
+                return ret;
+
+        /* Parse the result out */
+        result = 0;
+        if (rets[1]) {
+                switch(rets[0]) {
+                case 0:
+                        result &= ~EEH_STATE_RESET_ACTIVE;
+                        result |= EEH_STATE_MMIO_ACTIVE;
+                        result |= EEH_STATE_DMA_ACTIVE;
+                        break;
+                case 1:
+                        result |= EEH_STATE_RESET_ACTIVE;
+                        result |= EEH_STATE_MMIO_ACTIVE;
+                        result |= EEH_STATE_DMA_ACTIVE;
+                        break;
+                case 2:
+                        result &= ~EEH_STATE_RESET_ACTIVE;
+                        result &= ~EEH_STATE_MMIO_ACTIVE;
+                        result &= ~EEH_STATE_DMA_ACTIVE;
+                        break;
+                case 4:
+                        result &= ~EEH_STATE_RESET_ACTIVE;
+                        result &= ~EEH_STATE_MMIO_ACTIVE;
+                        result &= ~EEH_STATE_DMA_ACTIVE;
+                        result |= EEH_STATE_MMIO_ENABLED;
+                        break;
+                case 5:
+                        if (rets[2]) {
+                                if (state) *state = rets[2];
+                                result = EEH_STATE_UNAVAILABLE;
+                        } else {
+                                result = EEH_STATE_NOT_SUPPORT;
+                        }
+                default:
+                        result = EEH_STATE_NOT_SUPPORT;
+                }
+        } else {
+                result = EEH_STATE_NOT_SUPPORT;
+        }
+
+        return result;
+}
+
+/**
+ * pseries_eeh_reset - Reset the specified PE
+ * @dn: PE associated device node
+ * @option: reset option
+ *
+ * Reset the specified PE
+ */
+static int pseries_eeh_reset(struct device_node *dn, int option)
+{
+        struct eeh_dev *edev;
+        int config_addr;
+        int ret;
+
+        /* Figure out PE address */
+        edev = of_node_to_eeh_dev(dn);
+        config_addr = edev->config_addr;
+        if (edev->pe_config_addr)
+                config_addr = edev->pe_config_addr;
+
+        /* Reset PE through RTAS call */
+        ret = rtas_call(ibm_set_slot_reset, 4, 1, NULL,
+                        config_addr, BUID_HI(edev->phb->buid),
+                        BUID_LO(edev->phb->buid), option);
+
+        /* If fundamental-reset not supported, try hot-reset */
+        if (option == EEH_RESET_FUNDAMENTAL &&
+            ret == -8) {
+                ret = rtas_call(ibm_set_slot_reset, 4, 1, NULL,
+                                config_addr, BUID_HI(edev->phb->buid),
+                                BUID_LO(edev->phb->buid), EEH_RESET_HOT);
+        }
+
+        return ret;
+}
+
+/**
+ * pseries_eeh_wait_state - Wait for PE state
+ * @dn: PE associated device node
+ * @max_wait: maximal period in microsecond
+ *
+ * Wait for the state of associated PE. It might take some time
+ * to retrieve the PE's state.
+ */
+static int pseries_eeh_wait_state(struct device_node *dn, int max_wait)
+{
+        int ret;
+        int mwait;
+
+        /*
+         * According to PAPR, the state of PE might be temporarily
+         * unavailable. Under the circumstance, we have to wait
+         * for indicated time determined by firmware. The maximal
+         * wait time is 5 minutes, which is acquired from the original
+         * EEH implementation. Also, the original implementation
+         * also defined the minimal wait time as 1 second.
+         */
+#define EEH_STATE_MIN_WAIT_TIME (1000)
+#define EEH_STATE_MAX_WAIT_TIME (300 * 1000)
+
+        while (1) {
+                ret = pseries_eeh_get_state(dn, &mwait);
+
+                /*
+                 * If the PE's state is temporarily unavailable,
+                 * we have to wait for the specified time. Otherwise,
+                 * the PE's state will be returned immediately.
+                 */
+                if (ret != EEH_STATE_UNAVAILABLE)
+                        return ret;
+
+                if (max_wait <= 0) {
+                        pr_warning("%s: Timeout when getting PE's state (%d)\n",
+                                __func__, max_wait);
+                        return EEH_STATE_NOT_SUPPORT;
+                }
+
+                if (mwait <= 0) {
+                        pr_warning("%s: Firmware returned bad wait value %d\n",
+                                __func__, mwait);
+                        mwait = EEH_STATE_MIN_WAIT_TIME;
+                } else if (mwait > EEH_STATE_MAX_WAIT_TIME) {
+                        pr_warning("%s: Firmware returned too long wait value %d\n",
+                                __func__, mwait);
+                        mwait = EEH_STATE_MAX_WAIT_TIME;
+                }
+
+                max_wait -= mwait;
+                msleep(mwait);
+        }
+
+        return EEH_STATE_NOT_SUPPORT;
+}
+
+/**
+ * pseries_eeh_get_log - Retrieve error log
+ * @dn: device node
+ * @severity: temporary or permanent error log
+ * @drv_log: driver log to be combined with retrieved error log
+ * @len: length of driver log
+ *
+ * Retrieve the temporary or permanent error from the PE.
+ * Actually, the error will be retrieved through the dedicated
+ * RTAS call.
+ */
+static int pseries_eeh_get_log(struct device_node *dn, int severity, char *drv_log, unsigned long len)
+{
+        struct eeh_dev *edev;
+        int config_addr;
+        unsigned long flags;
+        int ret;
+
+        edev = of_node_to_eeh_dev(dn);
+        spin_lock_irqsave(&slot_errbuf_lock, flags);
+        memset(slot_errbuf, 0, eeh_error_buf_size);
+
+        /* Figure out the PE address */
+        config_addr = edev->config_addr;
+        if (edev->pe_config_addr)
+                config_addr = edev->pe_config_addr;
+
+        ret = rtas_call(ibm_slot_error_detail, 8, 1, NULL, config_addr,
+                        BUID_HI(edev->phb->buid), BUID_LO(edev->phb->buid),
+                        virt_to_phys(drv_log), len,
+                        virt_to_phys(slot_errbuf), eeh_error_buf_size,
+                        severity);
+        if (!ret)
+                log_error(slot_errbuf, ERR_TYPE_RTAS_LOG, 0);
+        spin_unlock_irqrestore(&slot_errbuf_lock, flags);
+
+        return ret;
+}
+
+/**
+ * pseries_eeh_configure_bridge - Configure PCI bridges in the indicated PE
+ * @dn: PE associated device node
+ *
+ * The function will be called to reconfigure the bridges included
+ * in the specified PE so that the mulfunctional PE would be recovered
+ * again.
+ */
+static int pseries_eeh_configure_bridge(struct device_node *dn)
+{
+        struct eeh_dev *edev;
+        int config_addr;
+        int ret;
+
+        /* Figure out the PE address */
+        edev = of_node_to_eeh_dev(dn);
+        config_addr = edev->config_addr;
+        if (edev->pe_config_addr)
+                config_addr = edev->pe_config_addr;
+
+        /* Use new configure-pe function, if supported */
+        if (ibm_configure_pe != RTAS_UNKNOWN_SERVICE) {
+                ret = rtas_call(ibm_configure_pe, 3, 1, NULL,
+                                config_addr, BUID_HI(edev->phb->buid),
+                                BUID_LO(edev->phb->buid));
+        } else if (ibm_configure_bridge != RTAS_UNKNOWN_SERVICE) {
+                ret = rtas_call(ibm_configure_bridge, 3, 1, NULL,
+                                config_addr, BUID_HI(edev->phb->buid),
+                                BUID_LO(edev->phb->buid));
+        } else {
+                return -EFAULT;
+        }
+
+        if (ret)
+                pr_warning("%s: Unable to configure bridge %d for %s\n",
+                        __func__, ret, dn->full_name);
+
+        return ret;
+}
+
+/**
+ * pseries_eeh_read_config - Read PCI config space
+ * @dn: device node
+ * @where: PCI address
+ * @size: size to read
+ * @val: return value
+ *
+ * Read config space from the speicifed device
+ */
+static int pseries_eeh_read_config(struct device_node *dn, int where, int size, u32 *val)
+{
+        struct pci_dn *pdn;
+
+        pdn = PCI_DN(dn);
+
+        return rtas_read_config(pdn, where, size, val);
+}
+
+/**
+ * pseries_eeh_write_config - Write PCI config space
+ * @dn: device node
+ * @where: PCI address
+ * @size: size to write
+ * @val: value to be written
+ *
+ * Write config space to the specified device
+ */
+static int pseries_eeh_write_config(struct device_node *dn, int where, int size, u32 val)
+{
+        struct pci_dn *pdn;
+
+        pdn = PCI_DN(dn);
+
+        return rtas_write_config(pdn, where, size, val);
+}
+
+static struct eeh_ops pseries_eeh_ops = {
+        .name                   = "pseries",
+        .init                   = pseries_eeh_init,
+        .set_option             = pseries_eeh_set_option,
+        .get_pe_addr            = pseries_eeh_get_pe_addr,
+        .get_state              = pseries_eeh_get_state,
+        .reset                  = pseries_eeh_reset,
+        .wait_state             = pseries_eeh_wait_state,
+        .get_log                = pseries_eeh_get_log,
+        .configure_bridge       = pseries_eeh_configure_bridge,
+        .read_config            = pseries_eeh_read_config,
+        .write_config           = pseries_eeh_write_config
+};
+
+/**
+ * eeh_pseries_init - Register platform dependent EEH operations
+ *
+ * EEH initialization on pseries platform. This function should be
+ * called before any EEH related functions.
+ */
+int __init eeh_pseries_init(void)
+{
+        return eeh_ops_register(&pseries_eeh_ops);
+}
diff --git a/arch/powerpc/platforms/pseries/eeh_sysfs.c b/arch/powerpc/platforms/pseries/eeh_sysfs.c
index eb744ee234d..243b3510d70 100644
--- a/arch/powerpc/platforms/pseries/eeh_sysfs.c
+++ b/arch/powerpc/platforms/pseries/eeh_sysfs.c
@@ -28,7 +28,7 @@
 #include <asm/pci-bridge.h>
 
 /**
- * EEH_SHOW_ATTR -- create sysfs entry for eeh statistic
+ * EEH_SHOW_ATTR -- Create sysfs entry for eeh statistic
  * @_name: name of file in sysfs directory
  * @_memb: name of member in struct pci_dn to access
  * @_format: printf format for display
@@ -41,24 +41,21 @@ static ssize_t eeh_show_##_name(struct device *dev,      \
                 struct device_attribute *attr, char *buf)          \
 {                                                        \
         struct pci_dev *pdev = to_pci_dev(dev);               \
-        struct device_node *dn = pci_device_to_OF_node(pdev); \
-        struct pci_dn *pdn;                                   \
+        struct eeh_dev *edev = pci_dev_to_eeh_dev(pdev);      \
                                                               \
-        if (!dn || PCI_DN(dn) == NULL)                        \
-                return 0;                                          \
+        if (!edev)                                            \
+                return 0;                                     \
                                                               \
-        pdn = PCI_DN(dn);                                     \
-        return sprintf(buf, _format "\n", pdn->_memb);        \
+        return sprintf(buf, _format "\n", edev->_memb);       \
 }                                                        \
 static DEVICE_ATTR(_name, S_IRUGO, eeh_show_##_name, NULL);
 
-
-EEH_SHOW_ATTR(eeh_mode, eeh_mode, "0x%x");
-EEH_SHOW_ATTR(eeh_config_addr, eeh_config_addr, "0x%x");
-EEH_SHOW_ATTR(eeh_pe_config_addr, eeh_pe_config_addr, "0x%x");
-EEH_SHOW_ATTR(eeh_check_count, eeh_check_count, "%d");
-EEH_SHOW_ATTR(eeh_freeze_count, eeh_freeze_count, "%d");
-EEH_SHOW_ATTR(eeh_false_positives, eeh_false_positives, "%d");
+EEH_SHOW_ATTR(eeh_mode,            mode,            "0x%x");
+EEH_SHOW_ATTR(eeh_config_addr,     config_addr,     "0x%x");
+EEH_SHOW_ATTR(eeh_pe_config_addr,  pe_config_addr,  "0x%x");
+EEH_SHOW_ATTR(eeh_check_count,     check_count,     "%d"  );
+EEH_SHOW_ATTR(eeh_freeze_count,    freeze_count,    "%d"  );
+EEH_SHOW_ATTR(eeh_false_positives, false_positives, "%d"  );
 
 void eeh_sysfs_add_device(struct pci_dev *pdev)
 {
diff --git a/arch/powerpc/platforms/pseries/lpar.c b/arch/powerpc/platforms/pseries/lpar.c
index 7bc73af6c7b..5f3ef876ded 100644
--- a/arch/powerpc/platforms/pseries/lpar.c
+++ b/arch/powerpc/platforms/pseries/lpar.c
@@ -41,6 +41,7 @@
 #include <asm/udbg.h>
 #include <asm/smp.h>
 #include <asm/trace.h>
+#include <asm/firmware.h>
 
 #include "plpar_wrappers.h"
 #include "pseries.h"
diff --git a/arch/powerpc/platforms/pseries/msi.c b/arch/powerpc/platforms/pseries/msi.c
index 38d24e7e7bb..109fdb75578 100644
--- a/arch/powerpc/platforms/pseries/msi.c
+++ b/arch/powerpc/platforms/pseries/msi.c
@@ -217,7 +217,7 @@ static struct device_node *find_pe_dn(struct pci_dev *dev, int *total)
         if (!dn)
                 return NULL;
 
-        dn = find_device_pe(dn);
+        dn = eeh_find_device_pe(dn);
         if (!dn)
                 return NULL;
 
diff --git a/arch/powerpc/platforms/pseries/pci_dlpar.c b/arch/powerpc/platforms/pseries/pci_dlpar.c
index 55d4ec1bd1a..8b7bafa489c 100644
--- a/arch/powerpc/platforms/pseries/pci_dlpar.c
+++ b/arch/powerpc/platforms/pseries/pci_dlpar.c
@@ -84,7 +84,7 @@ void pcibios_remove_pci_devices(struct pci_bus *bus)
         list_for_each_entry_safe(dev, tmp, &bus->devices, bus_list) {
                 pr_debug("     * Removing %s...\n", pci_name(dev));
                 eeh_remove_bus_device(dev);
-                pci_remove_bus_device(dev);
+                pci_stop_and_remove_bus_device(dev);
         }
 }
 EXPORT_SYMBOL_GPL(pcibios_remove_pci_devices);
@@ -147,6 +147,9 @@ struct pci_controller * __devinit init_phb_dynamic(struct device_node *dn)
 
         pci_devs_phb_init_dynamic(phb);
 
+        /* Create EEH devices for the PHB */
+        eeh_dev_phb_init_dynamic(phb);
+
         if (dn->child)
                 eeh_add_device_tree_early(dn);
 
diff --git a/arch/powerpc/platforms/pseries/phyp_dump.c b/arch/powerpc/platforms/pseries/phyp_dump.c
deleted file mode 100644
index 6e7742da007..00000000000
--- a/arch/powerpc/platforms/pseries/phyp_dump.c
+++ /dev/null
@@ -1,513 +0,0 @@
-/*
- * Hypervisor-assisted dump
- *
- * Linas Vepstas, Manish Ahuja 2008
- * Copyright 2008 IBM Corp.
- *
- *      This program is free software; you can redistribute it and/or
- *      modify it under the terms of the GNU General Public License
- *      as published by the Free Software Foundation; either version
- *      2 of the License, or (at your option) any later version.
- *
- */
-
-#include <linux/gfp.h>
-#include <linux/init.h>
-#include <linux/kobject.h>
-#include <linux/mm.h>
-#include <linux/of.h>
-#include <linux/pfn.h>
-#include <linux/swap.h>
-#include <linux/sysfs.h>
-
-#include <asm/page.h>
-#include <asm/phyp_dump.h>
-#include <asm/machdep.h>
-#include <asm/prom.h>
-#include <asm/rtas.h>
-
-/* Variables, used to communicate data between early boot and late boot */
-static struct phyp_dump phyp_dump_vars;
-struct phyp_dump *phyp_dump_info = &phyp_dump_vars;
-
-static int ibm_configure_kernel_dump;
-/* ------------------------------------------------- */
-/* RTAS interfaces to declare the dump regions */
-
-struct dump_section {
-        u32 dump_flags;
-        u16 source_type;
-        u16 error_flags;
-        u64 source_address;
-        u64 source_length;
-        u64 length_copied;
-        u64 destination_address;
-};
-
-struct phyp_dump_header {
-        u32 version;
-        u16 num_of_sections;
-        u16 status;
-
-        u32 first_offset_section;
-        u32 dump_disk_section;
-        u64 block_num_dd;
-        u64 num_of_blocks_dd;
-        u32 offset_dd;
-        u32 maxtime_to_auto;
-        /* No dump disk path string used */
-
-        struct dump_section cpu_data;
-        struct dump_section hpte_data;
-        struct dump_section kernel_data;
-};
-
-/* The dump header *must be* in low memory, so .bss it */
-static struct phyp_dump_header phdr;
-
-#define NUM_DUMP_SECTIONS       3
-#define DUMP_HEADER_VERSION     0x1
-#define DUMP_REQUEST_FLAG       0x1
-#define DUMP_SOURCE_CPU         0x0001
-#define DUMP_SOURCE_HPTE        0x0002
-#define DUMP_SOURCE_RMO         0x0011
-#define DUMP_ERROR_FLAG         0x2000
-#define DUMP_TRIGGERED          0x4000
-#define DUMP_PERFORMED          0x8000
-
-
-/**
- * init_dump_header() - initialize the header declaring a dump
- * Returns: length of dump save area.
- *
- * When the hypervisor saves crashed state, it needs to put
- * it somewhere. The dump header tells the hypervisor where
- * the data can be saved.
- */
-static unsigned long init_dump_header(struct phyp_dump_header *ph)
-{
-        unsigned long addr_offset = 0;
-
-        /* Set up the dump header */
-        ph->version = DUMP_HEADER_VERSION;
-        ph->num_of_sections = NUM_DUMP_SECTIONS;
-        ph->status = 0;
-
-        ph->first_offset_section =
-                (u32)offsetof(struct phyp_dump_header, cpu_data);
-        ph->dump_disk_section = 0;
-        ph->block_num_dd = 0;
-        ph->num_of_blocks_dd = 0;
-        ph->offset_dd = 0;
-
-        ph->maxtime_to_auto = 0; /* disabled */
-
-        /* The first two sections are mandatory */
-        ph->cpu_data.dump_flags = DUMP_REQUEST_FLAG;
-        ph->cpu_data.source_type = DUMP_SOURCE_CPU;
-        ph->cpu_data.source_address = 0;
-        ph->cpu_data.source_length = phyp_dump_info->cpu_state_size;
-        ph->cpu_data.destination_address = addr_offset;
-        addr_offset += phyp_dump_info->cpu_state_size;
-
-        ph->hpte_data.dump_flags = DUMP_REQUEST_FLAG;
-        ph->hpte_data.source_type = DUMP_SOURCE_HPTE;
-        ph->hpte_data.source_address = 0;
-        ph->hpte_data.source_length = phyp_dump_info->hpte_region_size;
-        ph->hpte_data.destination_address = addr_offset;
-        addr_offset += phyp_dump_info->hpte_region_size;
-
-        /* This section describes the low kernel region */
-        ph->kernel_data.dump_flags = DUMP_REQUEST_FLAG;
-        ph->kernel_data.source_type = DUMP_SOURCE_RMO;
-        ph->kernel_data.source_address = PHYP_DUMP_RMR_START;
-        ph->kernel_data.source_length = PHYP_DUMP_RMR_END;
-        ph->kernel_data.destination_address = addr_offset;
-        addr_offset += ph->kernel_data.source_length;
-
-        return addr_offset;
-}
-
-static void print_dump_header(const struct phyp_dump_header *ph)
-{
-#ifdef DEBUG
-        if (ph == NULL)
-                return;
-
-        printk(KERN_INFO "dump header:\n");
-        /* setup some ph->sections required */
-        printk(KERN_INFO "version = %d\n", ph->version);
-        printk(KERN_INFO "Sections = %d\n", ph->num_of_sections);
-        printk(KERN_INFO "Status = 0x%x\n", ph->status);
-
-        /* No ph->disk, so all should be set to 0 */
-        printk(KERN_INFO "Offset to first section 0x%x\n",
-                ph->first_offset_section);
-        printk(KERN_INFO "dump disk sections should be zero\n");
-        printk(KERN_INFO "dump disk section = %d\n", ph->dump_disk_section);
-        printk(KERN_INFO "block num = %lld\n", ph->block_num_dd);
-        printk(KERN_INFO "number of blocks = %lld\n", ph->num_of_blocks_dd);
-        printk(KERN_INFO "dump disk offset = %d\n", ph->offset_dd);
-        printk(KERN_INFO "Max auto time= %d\n", ph->maxtime_to_auto);
-
-        /*set cpu state and hpte states as well scratch pad area */
-        printk(KERN_INFO " CPU AREA\n");
-        printk(KERN_INFO "cpu dump_flags =%d\n", ph->cpu_data.dump_flags);
-        printk(KERN_INFO "cpu source_type =%d\n", ph->cpu_data.source_type);
-        printk(KERN_INFO "cpu error_flags =%d\n", ph->cpu_data.error_flags);
-        printk(KERN_INFO "cpu source_address =%llx\n",
-                ph->cpu_data.source_address);
-        printk(KERN_INFO "cpu source_length =%llx\n",
-                ph->cpu_data.source_length);
-        printk(KERN_INFO "cpu length_copied =%llx\n",
-                ph->cpu_data.length_copied);
-
-        printk(KERN_INFO " HPTE AREA\n");
-        printk(KERN_INFO "HPTE dump_flags =%d\n", ph->hpte_data.dump_flags);
-        printk(KERN_INFO "HPTE source_type =%d\n", ph->hpte_data.source_type);
-        printk(KERN_INFO "HPTE error_flags =%d\n", ph->hpte_data.error_flags);
-        printk(KERN_INFO "HPTE source_address =%llx\n",
-                ph->hpte_data.source_address);
-        printk(KERN_INFO "HPTE source_length =%llx\n",
-                ph->hpte_data.source_length);
-        printk(KERN_INFO "HPTE length_copied =%llx\n",
-                ph->hpte_data.length_copied);
-
-        printk(KERN_INFO " SRSD AREA\n");
-        printk(KERN_INFO "SRSD dump_flags =%d\n", ph->kernel_data.dump_flags);
-        printk(KERN_INFO "SRSD source_type =%d\n", ph->kernel_data.source_type);
-        printk(KERN_INFO "SRSD error_flags =%d\n", ph->kernel_data.error_flags);
-        printk(KERN_INFO "SRSD source_address =%llx\n",
-                ph->kernel_data.source_address);
-        printk(KERN_INFO "SRSD source_length =%llx\n",
-                ph->kernel_data.source_length);
-        printk(KERN_INFO "SRSD length_copied =%llx\n",
-                ph->kernel_data.length_copied);
-#endif
-}
-
-static ssize_t show_phyp_dump_active(struct kobject *kobj,
-                        struct kobj_attribute *attr, char *buf)
-{
-
-        /* create filesystem entry so kdump is phyp-dump aware */
-        return sprintf(buf, "%lx\n", phyp_dump_info->phyp_dump_at_boot);
-}
-
-static struct kobj_attribute pdl = __ATTR(phyp_dump_active, 0600,
-                                        show_phyp_dump_active,
-                                        NULL);
-
-static void register_dump_area(struct phyp_dump_header *ph, unsigned long addr)
-{
-        int rc;
-
-        /* Add addr value if not initialized before */
-        if (ph->cpu_data.destination_address == 0) {
-                ph->cpu_data.destination_address += addr;
-                ph->hpte_data.destination_address += addr;
-                ph->kernel_data.destination_address += addr;
-        }
-
-        /* ToDo Invalidate kdump and free memory range. */
-
-        do {
-                rc = rtas_call(ibm_configure_kernel_dump, 3, 1, NULL,
-                                1, ph, sizeof(struct phyp_dump_header));
-        } while (rtas_busy_delay(rc));
-
-        if (rc) {
-                printk(KERN_ERR "phyp-dump: unexpected error (%d) on "
-                                                "register\n", rc);
-                print_dump_header(ph);
-                return;
-        }
-
-        rc = sysfs_create_file(kernel_kobj, &pdl.attr);
-        if (rc)
-                printk(KERN_ERR "phyp-dump: unable to create sysfs"
-                                " file (%d)\n", rc);
-}
-
-static
-void invalidate_last_dump(struct phyp_dump_header *ph, unsigned long addr)
-{
-        int rc;
-
-        /* Add addr value if not initialized before */
-        if (ph->cpu_data.destination_address == 0) {
-                ph->cpu_data.destination_address += addr;
-                ph->hpte_data.destination_address += addr;
-                ph->kernel_data.destination_address += addr;
-        }
-
-        do {
-                rc = rtas_call(ibm_configure_kernel_dump, 3, 1, NULL,
-                                2, ph, sizeof(struct phyp_dump_header));
-        } while (rtas_busy_delay(rc));
-
-        if (rc) {
-                printk(KERN_ERR "phyp-dump: unexpected error (%d) "
-                                                "on invalidate\n", rc);
-                print_dump_header(ph);
-        }
-}
-
-/* ------------------------------------------------- */
-/**
- * release_memory_range -- release memory previously memblock_reserved
- * @start_pfn: starting physical frame number
- * @nr_pages: number of pages to free.
- *
- * This routine will release memory that had been previously
- * memblock_reserved in early boot. The released memory becomes
- * available for genreal use.
- */
-static void release_memory_range(unsigned long start_pfn,
-                        unsigned long nr_pages)
-{
-        struct page *rpage;
-        unsigned long end_pfn;
-        long i;
-
-        end_pfn = start_pfn + nr_pages;
-
-        for (i = start_pfn; i <= end_pfn; i++) {
-                rpage = pfn_to_page(i);
-                if (PageReserved(rpage)) {
-                        ClearPageReserved(rpage);
-                        init_page_count(rpage);
-                        __free_page(rpage);
-                        totalram_pages++;
-                }
-        }
-}
-
-/**
- * track_freed_range -- Counts the range being freed.
- * Once the counter goes to zero, it re-registers dump for
- * future use.
- */
-static void
-track_freed_range(unsigned long addr, unsigned long length)
-{
-        static unsigned long scratch_area_size, reserved_area_size;
-
-        if (addr < phyp_dump_info->init_reserve_start)
-                return;
-
-        if ((addr >= phyp_dump_info->init_reserve_start) &&
-            (addr <= phyp_dump_info->init_reserve_start +
-             phyp_dump_info->init_reserve_size))
-                reserved_area_size += length;
-
-        if ((addr >= phyp_dump_info->reserved_scratch_addr) &&
-            (addr <= phyp_dump_info->reserved_scratch_addr +
-             phyp_dump_info->reserved_scratch_size))
-                scratch_area_size += length;
-
-        if ((reserved_area_size == phyp_dump_info->init_reserve_size) &&
-            (scratch_area_size == phyp_dump_info->reserved_scratch_size)) {
-
-                invalidate_last_dump(&phdr,
-                                phyp_dump_info->reserved_scratch_addr);
-                register_dump_area(&phdr,
-                                phyp_dump_info->reserved_scratch_addr);
-        }
-}
-
-/* ------------------------------------------------- */
-/**
- * sysfs_release_region -- sysfs interface to release memory range.
- *
- * Usage:
- *   "echo <start addr> <length> > /sys/kernel/release_region"
- *
- * Example:
- *   "echo 0x40000000 0x10000000 > /sys/kernel/release_region"
- *
- * will release 256MB starting at 1GB.
- */
-static ssize_t store_release_region(struct kobject *kobj,
-                                struct kobj_attribute *attr,
-                                const char *buf, size_t count)
-{
-        unsigned long start_addr, length, end_addr;
-        unsigned long start_pfn, nr_pages;
-        ssize_t ret;
-
-        ret = sscanf(buf, "%lx %lx", &start_addr, &length);
-        if (ret != 2)
-                return -EINVAL;
-
-        track_freed_range(start_addr, length);
-
-        /* Range-check - don't free any reserved memory that
-         * wasn't reserved for phyp-dump */
-        if (start_addr < phyp_dump_info->init_reserve_start)
-                start_addr = phyp_dump_info->init_reserve_start;
-
-        end_addr = phyp_dump_info->init_reserve_start +
-                        phyp_dump_info->init_reserve_size;
-        if (start_addr+length > end_addr)
-                length = end_addr - start_addr;
-
-        /* Release the region of memory assed in by user */
-        start_pfn = PFN_DOWN(start_addr);
-        nr_pages = PFN_DOWN(length);
-        release_memory_range(start_pfn, nr_pages);
-
-        return count;
-}
-
-static ssize_t show_release_region(struct kobject *kobj,
-                        struct kobj_attribute *attr, char *buf)
-{
-        u64 second_addr_range;
-
-        /* total reserved size - start of scratch area */
-        second_addr_range = phyp_dump_info->init_reserve_size -
-                                phyp_dump_info->reserved_scratch_size;
-        return sprintf(buf, "CPU:0x%llx-0x%llx: HPTE:0x%llx-0x%llx:"
-                            " DUMP:0x%llx-0x%llx, 0x%lx-0x%llx:\n",
-                phdr.cpu_data.destination_address,
-                phdr.cpu_data.length_copied,
-                phdr.hpte_data.destination_address,
-                phdr.hpte_data.length_copied,
-                phdr.kernel_data.destination_address,
-                phdr.kernel_data.length_copied,
-                phyp_dump_info->init_reserve_start,
-                second_addr_range);
-}
-
-static struct kobj_attribute rr = __ATTR(release_region, 0600,
-                                        show_release_region,
-                                        store_release_region);
-
-static int __init phyp_dump_setup(void)
-{
-        struct device_node *rtas;
-        const struct phyp_dump_header *dump_header = NULL;
-        unsigned long dump_area_start;
-        unsigned long dump_area_length;
-        int header_len = 0;
-        int rc;
-
-        /* If no memory was reserved in early boot, there is nothing to do */
-        if (phyp_dump_info->init_reserve_size == 0)
-                return 0;
-
-        /* Return if phyp dump not supported */
-        if (!phyp_dump_info->phyp_dump_configured)
-                return -ENOSYS;
-
-        /* Is there dump data waiting for us? If there isn't,
-         * then register a new dump area, and release all of
-         * the rest of the reserved ram.
-         *
-         * The /rtas/ibm,kernel-dump rtas node is present only
-         * if there is dump data waiting for us.
-         */
-        rtas = of_find_node_by_path("/rtas");
-        if (rtas) {
-                dump_header = of_get_property(rtas, "ibm,kernel-dump",
-                                                &header_len);
-                of_node_put(rtas);
-        }
-
-        ibm_configure_kernel_dump = rtas_token("ibm,configure-kernel-dump");
-
-        print_dump_header(dump_header);
-        dump_area_length = init_dump_header(&phdr);
-        /* align down */
-        dump_area_start = phyp_dump_info->init_reserve_start & PAGE_MASK;
-
-        if (dump_header == NULL) {
-                register_dump_area(&phdr, dump_area_start);
-                return 0;
-        }
-
-        /* re-register the dump area, if old dump was invalid */
-        if ((dump_header) && (dump_header->status & DUMP_ERROR_FLAG)) {
-                invalidate_last_dump(&phdr, dump_area_start);
-                register_dump_area(&phdr, dump_area_start);
-                return 0;
-        }
-
-        if (dump_header) {
-                phyp_dump_info->reserved_scratch_addr =
-                                dump_header->cpu_data.destination_address;
-                phyp_dump_info->reserved_scratch_size =
-                                dump_header->cpu_data.source_length +
-                                dump_header->hpte_data.source_length +
-                                dump_header->kernel_data.source_length;
-        }
-
-        /* Should we create a dump_subsys, analogous to s390/ipl.c ? */
-        rc = sysfs_create_file(kernel_kobj, &rr.attr);
-        if (rc)
-                printk(KERN_ERR "phyp-dump: unable to create sysfs file (%d)\n",
-                                                                        rc);
-
-        /* ToDo: re-register the dump area, for next time. */
-        return 0;
-}
-machine_subsys_initcall(pseries, phyp_dump_setup);
-
-int __init early_init_dt_scan_phyp_dump(unsigned long node,
-                const char *uname, int depth, void *data)
-{
-        const unsigned int *sizes;
-
-        phyp_dump_info->phyp_dump_configured = 0;
-        phyp_dump_info->phyp_dump_is_active = 0;
-
-        if (depth != 1 || strcmp(uname, "rtas") != 0)
-                return 0;
-
-        if (of_get_flat_dt_prop(node, "ibm,configure-kernel-dump", NULL))
-                phyp_dump_info->phyp_dump_configured++;
-
-        if (of_get_flat_dt_prop(node, "ibm,dump-kernel", NULL))
-                phyp_dump_info->phyp_dump_is_active++;
-
-        sizes = of_get_flat_dt_prop(node, "ibm,configure-kernel-dump-sizes",
-                                    NULL);
-        if (!sizes)
-                return 0;
-
-        if (sizes[0] == 1)
-                phyp_dump_info->cpu_state_size = *((unsigned long *)&sizes[1]);
-
-        if (sizes[3] == 2)
-                phyp_dump_info->hpte_region_size =
-                                                *((unsigned long *)&sizes[4]);
-        return 1;
-}
-
-/* Look for phyp_dump= cmdline option */
-static int __init early_phyp_dump_enabled(char *p)
-{
-        phyp_dump_info->phyp_dump_at_boot = 1;
-
-        if (!p)
-                return 0;
-
-        if (strncmp(p, "1", 1) == 0)
-                phyp_dump_info->phyp_dump_at_boot = 1;
-        else if (strncmp(p, "0", 1) == 0)
-                phyp_dump_info->phyp_dump_at_boot = 0;
-
-        return 0;
-}
-early_param("phyp_dump", early_phyp_dump_enabled);
-
-/* Look for phyp_dump_reserve_size= cmdline option */
-static int __init early_phyp_dump_reserve_size(char *p)
-{
-        if (p)
-                phyp_dump_info->reserve_bootvar = memparse(p, &p);
-
-        return 0;
-}
-early_param("phyp_dump_reserve_size", early_phyp_dump_reserve_size);
diff --git a/arch/powerpc/platforms/pseries/processor_idle.c b/arch/powerpc/platforms/pseries/processor_idle.c
index 085fd3f45ad..a12e95af693 100644
--- a/arch/powerpc/platforms/pseries/processor_idle.c
+++ b/arch/powerpc/platforms/pseries/processor_idle.c
@@ -96,6 +96,20 @@ out:
         return index;
 }
 
+static void check_and_cede_processor(void)
+{
+        /*
+         * Interrupts are soft-disabled at this point,
+         * but not hard disabled. So an interrupt might have
+         * occurred before entering NAP, and would be potentially
+         * lost (edge events, decrementer events, etc...) unless
+         * we first hard disable then check.
+         */
+        hard_irq_disable();
+        if (get_paca()->irq_happened == 0)
+                cede_processor();
+}
+
 static int dedicated_cede_loop(struct cpuidle_device *dev,
                                 struct cpuidle_driver *drv,
                                 int index)
@@ -108,7 +122,7 @@ static int dedicated_cede_loop(struct cpuidle_device *dev,
 
         ppc64_runlatch_off();
         HMT_medium();
-        cede_processor();
+        check_and_cede_processor();
 
         get_lppaca()->donate_dedicated_cpu = 0;
         dev->last_residency =
@@ -132,7 +146,7 @@ static int shared_cede_loop(struct cpuidle_device *dev,
          * processor. When returning here, external interrupts
          * are enabled.
          */
-        cede_processor();
+        check_and_cede_processor();
 
         dev->last_residency =
                 (int)idle_loop_epilog(in_purr, kt_before);
diff --git a/arch/powerpc/platforms/pseries/setup.c b/arch/powerpc/platforms/pseries/setup.c
index f79f1278dfc..51ecac920dd 100644
--- a/arch/powerpc/platforms/pseries/setup.c
+++ b/arch/powerpc/platforms/pseries/setup.c
@@ -190,9 +190,8 @@ static void __init pseries_mpic_init_IRQ(void)
         BUG_ON(openpic_addr == 0);
 
         /* Setup the openpic driver */
-        mpic = mpic_alloc(pSeries_mpic_node, openpic_addr, 0,
-                          16, 250, /* isu size, irq count */
-                          " MPIC     ");
+        mpic = mpic_alloc(pSeries_mpic_node, openpic_addr,
+                        MPIC_NO_RESET, 16, 0, " MPIC     ");
         BUG_ON(mpic == NULL);
 
         /* Add ISUs */
@@ -261,8 +260,12 @@ static int pci_dn_reconfig_notifier(struct notifier_block *nb, unsigned long act
         switch (action) {
         case PSERIES_RECONFIG_ADD:
                 pci = np->parent->data;
-                if (pci)
+                if (pci) {
                         update_dn_pci_info(np, pci->phb);
+
+                        /* Create EEH device for the OF node */
+                        eeh_dev_init(np, pci->phb);
+                }
                 break;
         default:
                 err = NOTIFY_DONE;
@@ -380,8 +383,12 @@ static void __init pSeries_setup_arch(void)
 
         fwnmi_init();
 
+        /* By default, only probe PCI (can be overriden by rtas_pci) */
+        pci_add_flags(PCI_PROBE_ONLY);
+
         /* Find and initialize PCI host bridges */
         init_pci_config_tokens();
+        eeh_pseries_init();
         find_and_init_phbs();
         pSeries_reconfig_notifier_register(&pci_dn_reconfig_nb);
         eeh_init();
diff --git a/arch/powerpc/platforms/wsp/wsp_pci.c b/arch/powerpc/platforms/wsp/wsp_pci.c
index d24b3acf858..763014cd1e6 100644
--- a/arch/powerpc/platforms/wsp/wsp_pci.c
+++ b/arch/powerpc/platforms/wsp/wsp_pci.c
@@ -682,7 +682,6 @@ static int __init wsp_setup_one_phb(struct device_node *np)
         /* XXX Force re-assigning of everything for now */
         pci_add_flags(PCI_REASSIGN_ALL_BUS | PCI_REASSIGN_ALL_RSRC |
                       PCI_ENABLE_PROC_DOMAINS);
-        pci_probe_only = 0;
 
         /* Calculate how the TCE space is divided */
         phb->dma32_base         = 0;
diff --git a/arch/powerpc/sysdev/Kconfig b/arch/powerpc/sysdev/Kconfig
index 7b4df37ac38..a84fecf63c4 100644
--- a/arch/powerpc/sysdev/Kconfig
+++ b/arch/powerpc/sysdev/Kconfig
@@ -29,3 +29,7 @@ config SCOM_DEBUGFS
         bool "Expose SCOM controllers via debugfs"
         depends on PPC_SCOM
         default n
+
+config GE_FPGA
+        bool
+        default n
diff --git a/arch/powerpc/sysdev/Makefile b/arch/powerpc/sysdev/Makefile
index 5e37b471786..1bd7ecb2462 100644
--- a/arch/powerpc/sysdev/Makefile
+++ b/arch/powerpc/sysdev/Makefile
@@ -4,6 +4,8 @@ ccflags-$(CONFIG_PPC64)		:= -mno-minimal-toc
 
 mpic-msi-obj-$(CONFIG_PCI_MSI)  += mpic_msi.o mpic_u3msi.o mpic_pasemi_msi.o
 obj-$(CONFIG_MPIC)              += mpic.o $(mpic-msi-obj-y)
+mpic-msgr-obj-$(CONFIG_MPIC_MSGR)       += mpic_msgr.o
+obj-$(CONFIG_MPIC)              += mpic.o $(mpic-msi-obj-y) $(mpic-msgr-obj-y)
 obj-$(CONFIG_PPC_EPAPR_HV_PIC)  += ehv_pic.o
 fsl-msi-obj-$(CONFIG_PCI_MSI)   += fsl_msi.o
 obj-$(CONFIG_PPC_MSI_BITMAP)    += msi_bitmap.o
@@ -65,3 +67,5 @@ obj-$(CONFIG_PPC_SCOM)		+= scom.o
 subdir-ccflags-$(CONFIG_PPC_WERROR) := -Werror
 
 obj-$(CONFIG_PPC_XICS)          += xics/
+
+obj-$(CONFIG_GE_FPGA)           += ge/
diff --git a/arch/powerpc/sysdev/fsl_85xx_cache_sram.c b/arch/powerpc/sysdev/fsl_85xx_cache_sram.c
index 11641589917..37a69097e02 100644
--- a/arch/powerpc/sysdev/fsl_85xx_cache_sram.c
+++ b/arch/powerpc/sysdev/fsl_85xx_cache_sram.c
@@ -24,6 +24,7 @@
  */
 
 #include <linux/kernel.h>
+#include <linux/export.h>
 #include <linux/slab.h>
 #include <linux/err.h>
 #include <linux/of_platform.h>
diff --git a/arch/powerpc/sysdev/fsl_85xx_l2ctlr.c b/arch/powerpc/sysdev/fsl_85xx_l2ctlr.c
index 5f88797dce7..cedabd0f4bf 100644
--- a/arch/powerpc/sysdev/fsl_85xx_l2ctlr.c
+++ b/arch/powerpc/sysdev/fsl_85xx_l2ctlr.c
@@ -21,6 +21,7 @@
  */
 
 #include <linux/kernel.h>
+#include <linux/module.h>
 #include <linux/of_platform.h>
 #include <asm/io.h>
 
@@ -200,6 +201,9 @@ static struct of_device_id mpc85xx_l2ctlr_of_match[] = {
         {
                 .compatible = "fsl,p1022-l2-cache-controller",
         },
+        {
+                .compatible = "fsl,mpc8548-l2-cache-controller",
+        },
         {},
 };
 
diff --git a/arch/powerpc/sysdev/fsl_msi.c b/arch/powerpc/sysdev/fsl_msi.c
index 0c01debe963..6e097de00e0 100644
--- a/arch/powerpc/sysdev/fsl_msi.c
+++ b/arch/powerpc/sysdev/fsl_msi.c
@@ -410,6 +410,7 @@ static int __devinit fsl_of_msi_probe(struct platform_device *dev)
 
                 msi->msi_regs = ioremap(res.start, resource_size(&res));
                 if (!msi->msi_regs) {
+                        err = -ENOMEM;
                         dev_err(&dev->dev, "could not map node %s\n",
                                 dev->dev.of_node->full_name);
                         goto error_out;
diff --git a/arch/powerpc/sysdev/fsl_rio.c b/arch/powerpc/sysdev/fsl_rio.c
index a4c4f4a932d..5b6f556094d 100644
--- a/arch/powerpc/sysdev/fsl_rio.c
+++ b/arch/powerpc/sysdev/fsl_rio.c
@@ -66,8 +66,8 @@
                 "       li %0,%3\n"                     \
                 "       b 2b\n"                         \
                 ".section __ex_table,\"a\"\n"           \
-                "       .align 2\n"                     \
-                "       .long 1b,3b\n"                  \
+                        PPC_LONG_ALIGN "\n"             \
+                        PPC_LONG "1b,3b\n"              \
                 ".text"                                 \
                 : "=r" (err), "=r" (x)                  \
                 : "b" (addr), "i" (-EFAULT), "0" (err))
diff --git a/arch/powerpc/sysdev/fsl_rmu.c b/arch/powerpc/sysdev/fsl_rmu.c
index 15485789e9d..14bd5221f28 100644
--- a/arch/powerpc/sysdev/fsl_rmu.c
+++ b/arch/powerpc/sysdev/fsl_rmu.c
@@ -100,14 +100,8 @@
 #define DOORBELL_DSR_TE         0x00000080
 #define DOORBELL_DSR_QFI        0x00000010
 #define DOORBELL_DSR_DIQI       0x00000001
-#define DOORBELL_TID_OFFSET     0x02
-#define DOORBELL_SID_OFFSET     0x04
-#define DOORBELL_INFO_OFFSET    0x06
 
 #define DOORBELL_MESSAGE_SIZE   0x08
-#define DBELL_SID(x)            (*(u16 *)(x + DOORBELL_SID_OFFSET))
-#define DBELL_TID(x)            (*(u16 *)(x + DOORBELL_TID_OFFSET))
-#define DBELL_INF(x)            (*(u16 *)(x + DOORBELL_INFO_OFFSET))
 
 struct rio_msg_regs {
         u32 omr;
@@ -193,6 +187,13 @@ struct fsl_rmu {
         int rxirq;
 };
 
+struct rio_dbell_msg {
+        u16 pad1;
+        u16 tid;
+        u16 sid;
+        u16 info;
+};
+
 /**
  * fsl_rio_tx_handler - MPC85xx outbound message interrupt handler
  * @irq: Linux interrupt number
@@ -311,8 +312,8 @@ fsl_rio_dbell_handler(int irq, void *dev_instance)
 
         /* XXX Need to check/dispatch until queue empty */
         if (dsr & DOORBELL_DSR_DIQI) {
-                u32 dmsg =
-                        (u32) fsl_dbell->dbell_ring.virt +
+                struct rio_dbell_msg *dmsg =
+                        fsl_dbell->dbell_ring.virt +
                         (in_be32(&fsl_dbell->dbell_regs->dqdpar) & 0xfff);
                 struct rio_dbell *dbell;
                 int found = 0;
@@ -320,25 +321,25 @@ fsl_rio_dbell_handler(int irq, void *dev_instance)
                 pr_debug
                         ("RIO: processing doorbell,"
                         " sid %2.2x tid %2.2x info %4.4x\n",
-                        DBELL_SID(dmsg), DBELL_TID(dmsg), DBELL_INF(dmsg));
+                        dmsg->sid, dmsg->tid, dmsg->info);
 
                 for (i = 0; i < MAX_PORT_NUM; i++) {
                         if (fsl_dbell->mport[i]) {
                                 list_for_each_entry(dbell,
                                         &fsl_dbell->mport[i]->dbells, node) {
                                         if ((dbell->res->start
-                                                <= DBELL_INF(dmsg))
+                                                <= dmsg->info)
                                                 && (dbell->res->end
-                                                >= DBELL_INF(dmsg))) {
+                                                >= dmsg->info)) {
                                                 found = 1;
                                                 break;
                                         }
                                 }
                                 if (found && dbell->dinb) {
                                         dbell->dinb(fsl_dbell->mport[i],
-                                                dbell->dev_id, DBELL_SID(dmsg),
-                                                DBELL_TID(dmsg),
-                                                DBELL_INF(dmsg));
+                                                dbell->dev_id, dmsg->sid,
+                                                dmsg->tid,
+                                                dmsg->info);
                                         break;
                                 }
                         }
@@ -348,8 +349,8 @@ fsl_rio_dbell_handler(int irq, void *dev_instance)
                         pr_debug
                                 ("RIO: spurious doorbell,"
                                 " sid %2.2x tid %2.2x info %4.4x\n",
-                                DBELL_SID(dmsg), DBELL_TID(dmsg),
-                                DBELL_INF(dmsg));
+                                dmsg->sid, dmsg->tid,
+                                dmsg->info);
                 }
                 setbits32(&fsl_dbell->dbell_regs->dmr, DOORBELL_DMR_DI);
                 out_be32(&fsl_dbell->dbell_regs->dsr, DOORBELL_DSR_DIQI);
@@ -657,7 +658,7 @@ fsl_add_outb_message(struct rio_mport *mport, struct rio_dev *rdev, int mbox,
         int ret = 0;
 
         pr_debug("RIO: fsl_add_outb_message(): destid %4.4x mbox %d buffer " \
-                 "%8.8x len %8.8x\n", rdev->destid, mbox, (int)buffer, len);
+                 "%p len %8.8zx\n", rdev->destid, mbox, buffer, len);
         if ((len < 8) || (len > RIO_MAX_MSG_SIZE)) {
                 ret = -EINVAL;
                 goto out;
@@ -972,7 +973,8 @@ out:
 void *fsl_get_inb_message(struct rio_mport *mport, int mbox)
 {
         struct fsl_rmu *rmu = GET_RMM_HANDLE(mport);
-        u32 phys_buf, virt_buf;
+        u32 phys_buf;
+        void *virt_buf;
         void *buf = NULL;
         int buf_idx;
 
@@ -982,7 +984,7 @@ void *fsl_get_inb_message(struct rio_mport *mport, int mbox)
         if (phys_buf == in_be32(&rmu->msg_regs->ifqepar))
                 goto out2;
 
-        virt_buf = (u32) rmu->msg_rx_ring.virt + (phys_buf
+        virt_buf = rmu->msg_rx_ring.virt + (phys_buf
                                                 - rmu->msg_rx_ring.phys);
         buf_idx = (phys_buf - rmu->msg_rx_ring.phys) / RIO_MAX_MSG_SIZE;
         buf = rmu->msg_rx_ring.virt_buffer[buf_idx];
@@ -994,7 +996,7 @@ void *fsl_get_inb_message(struct rio_mport *mport, int mbox)
         }
 
         /* Copy max message size, caller is expected to allocate that big */
-        memcpy(buf, (void *)virt_buf, RIO_MAX_MSG_SIZE);
+        memcpy(buf, virt_buf, RIO_MAX_MSG_SIZE);
 
         /* Clear the available buffer */
         rmu->msg_rx_ring.virt_buffer[buf_idx] = NULL;
diff --git a/arch/powerpc/sysdev/ge/Makefile b/arch/powerpc/sysdev/ge/Makefile
new file mode 100644
index 00000000000..8731ffcb79b
--- /dev/null
+++ b/arch/powerpc/sysdev/ge/Makefile
@@ -0,0 +1 @@
+obj-$(CONFIG_GE_FPGA)           += ge_pic.o
diff --git a/arch/powerpc/platforms/86xx/gef_pic.c b/arch/powerpc/sysdev/ge/ge_pic.c
index af3fd697de8..2bcb78bb3a1 100644
--- a/arch/powerpc/platforms/86xx/gef_pic.c
+++ b/arch/powerpc/sysdev/ge/ge_pic.c
@@ -22,7 +22,7 @@
 #include <asm/prom.h>
 #include <asm/irq.h>
 
-#include "gef_pic.h"
+#include "ge_pic.h"
 
 #define DEBUG
 #undef DEBUG
diff --git a/arch/powerpc/platforms/86xx/gef_pic.h b/arch/powerpc/sysdev/ge/ge_pic.h
index 6149916da3f..6149916da3f 100644
--- a/arch/powerpc/platforms/86xx/gef_pic.h
+++ b/arch/powerpc/sysdev/ge/ge_pic.h
diff --git a/arch/powerpc/sysdev/mpic.c b/arch/powerpc/sysdev/mpic.c
index c83a512fa17..9ac71ebd2c4 100644
--- a/arch/powerpc/sysdev/mpic.c
+++ b/arch/powerpc/sysdev/mpic.c
@@ -873,7 +873,7 @@ int mpic_set_irq_type(struct irq_data *d, unsigned int flow_type)
         DBG("mpic: set_irq_type(mpic:@%p,virq:%d,src:0x%x,type:0x%x)\n",
             mpic, d->irq, src, flow_type);
 
-        if (src >= mpic->irq_count)
+        if (src >= mpic->num_sources)
                 return -EINVAL;
 
         if (flow_type == IRQ_TYPE_NONE)
@@ -909,7 +909,7 @@ void mpic_set_vector(unsigned int virq, unsigned int vector)
         DBG("mpic: set_vector(mpic:@%p,virq:%d,src:%d,vector:0x%x)\n",
             mpic, virq, src, vector);
 
-        if (src >= mpic->irq_count)
+        if (src >= mpic->num_sources)
                 return;
 
         vecpri = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI));
@@ -926,7 +926,7 @@ void mpic_set_destination(unsigned int virq, unsigned int cpuid)
         DBG("mpic: set_destination(mpic:@%p,virq:%d,src:%d,cpuid:0x%x)\n",
             mpic, virq, src, cpuid);
 
-        if (src >= mpic->irq_count)
+        if (src >= mpic->num_sources)
                 return;
 
         mpic_irq_write(src, MPIC_INFO(IRQ_DESTINATION), 1 << cpuid);
@@ -1006,7 +1006,7 @@ static int mpic_host_map(struct irq_domain *h, unsigned int virq,
                 return 0;
         }
 
-        if (hw >= mpic->irq_count)
+        if (hw >= mpic->num_sources)
                 return -EINVAL;
 
         mpic_msi_reserve_hwirq(mpic, hw);
@@ -1149,6 +1149,7 @@ struct mpic * __init mpic_alloc(struct device_node *node,
         u32 greg_feature;
         const char *vers;
         const u32 *psrc;
+        u32 last_irq;
 
         /* Default MPIC search parameters */
         static const struct of_device_id __initconst mpic_device_id[] = {
@@ -1182,6 +1183,16 @@ struct mpic * __init mpic_alloc(struct device_node *node,
                 }
         }
 
+        /* Read extra device-tree properties into the flags variable */
+        if (of_get_property(node, "big-endian", NULL))
+                flags |= MPIC_BIG_ENDIAN;
+        if (of_get_property(node, "pic-no-reset", NULL))
+                flags |= MPIC_NO_RESET;
+        if (of_get_property(node, "single-cpu-affinity", NULL))
+                flags |= MPIC_SINGLE_DEST_CPU;
+        if (of_device_is_compatible(node, "fsl,mpic"))
+                flags |= MPIC_FSL;
+
         mpic = kzalloc(sizeof(struct mpic), GFP_KERNEL);
         if (mpic == NULL)
                 goto err_of_node_put;
@@ -1189,15 +1200,16 @@ struct mpic * __init mpic_alloc(struct device_node *node,
         mpic->name = name;
         mpic->node = node;
         mpic->paddr = phys_addr;
+        mpic->flags = flags;
 
         mpic->hc_irq = mpic_irq_chip;
         mpic->hc_irq.name = name;
-        if (!(flags & MPIC_SECONDARY))
+        if (!(mpic->flags & MPIC_SECONDARY))
                 mpic->hc_irq.irq_set_affinity = mpic_set_affinity;
 #ifdef CONFIG_MPIC_U3_HT_IRQS
         mpic->hc_ht_irq = mpic_irq_ht_chip;
         mpic->hc_ht_irq.name = name;
-        if (!(flags & MPIC_SECONDARY))
+        if (!(mpic->flags & MPIC_SECONDARY))
                 mpic->hc_ht_irq.irq_set_affinity = mpic_set_affinity;
 #endif /* CONFIG_MPIC_U3_HT_IRQS */
 
@@ -1209,12 +1221,9 @@ struct mpic * __init mpic_alloc(struct device_node *node,
         mpic->hc_tm = mpic_tm_chip;
         mpic->hc_tm.name = name;
 
-        mpic->flags = flags;
-        mpic->isu_size = isu_size;
-        mpic->irq_count = irq_count;
         mpic->num_sources = 0; /* so far */
 
-        if (flags & MPIC_LARGE_VECTORS)
+        if (mpic->flags & MPIC_LARGE_VECTORS)
                 intvec_top = 2047;
         else
                 intvec_top = 255;
@@ -1233,12 +1242,6 @@ struct mpic * __init mpic_alloc(struct device_node *node,
         mpic->ipi_vecs[3]   = intvec_top - 1;
         mpic->spurious_vec  = intvec_top;
 
-        /* Check for "big-endian" in device-tree */
-        if (of_get_property(mpic->node, "big-endian", NULL) != NULL)
-                mpic->flags |= MPIC_BIG_ENDIAN;
-        if (of_device_is_compatible(mpic->node, "fsl,mpic"))
-                mpic->flags |= MPIC_FSL;
-
         /* Look for protected sources */
         psrc = of_get_property(mpic->node, "protected-sources", &psize);
         if (psrc) {
@@ -1254,11 +1257,11 @@ struct mpic * __init mpic_alloc(struct device_node *node,
         }
 
 #ifdef CONFIG_MPIC_WEIRD
-        mpic->hw_set = mpic_infos[MPIC_GET_REGSET(flags)];
+        mpic->hw_set = mpic_infos[MPIC_GET_REGSET(mpic->flags)];
 #endif
 
         /* default register type */
-        if (flags & MPIC_BIG_ENDIAN)
+        if (mpic->flags & MPIC_BIG_ENDIAN)
                 mpic->reg_type = mpic_access_mmio_be;
         else
                 mpic->reg_type = mpic_access_mmio_le;
@@ -1268,10 +1271,10 @@ struct mpic * __init mpic_alloc(struct device_node *node,
          * only if the kernel includes DCR support.
          */
 #ifdef CONFIG_PPC_DCR
-        if (flags & MPIC_USES_DCR)
+        if (mpic->flags & MPIC_USES_DCR)
                 mpic->reg_type = mpic_access_dcr;
 #else
-        BUG_ON(flags & MPIC_USES_DCR);
+        BUG_ON(mpic->flags & MPIC_USES_DCR);
 #endif
 
         /* Map the global registers */
@@ -1283,10 +1286,7 @@ struct mpic * __init mpic_alloc(struct device_node *node,
         /* When using a device-node, reset requests are only honored if the MPIC
          * is allowed to reset.
          */
-        if (of_get_property(mpic->node, "pic-no-reset", NULL))
-                mpic->flags |= MPIC_NO_RESET;
-
-        if ((flags & MPIC_WANTS_RESET) && !(mpic->flags & MPIC_NO_RESET)) {
+        if (!(mpic->flags & MPIC_NO_RESET)) {
                 printk(KERN_DEBUG "mpic: Resetting\n");
                 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
                            mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
@@ -1297,31 +1297,17 @@ struct mpic * __init mpic_alloc(struct device_node *node,
         }
 
         /* CoreInt */
-        if (flags & MPIC_ENABLE_COREINT)
+        if (mpic->flags & MPIC_ENABLE_COREINT)
                 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
                            mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
                            | MPIC_GREG_GCONF_COREINT);
 
-        if (flags & MPIC_ENABLE_MCK)
+        if (mpic->flags & MPIC_ENABLE_MCK)
                 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
                            mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
                            | MPIC_GREG_GCONF_MCK);
 
         /*
-         * Read feature register.  For non-ISU MPICs, num sources as well. On
-         * ISU MPICs, sources are counted as ISUs are added
-         */
-        greg_feature = mpic_read(mpic->gregs, MPIC_INFO(GREG_FEATURE_0));
-        if (isu_size == 0) {
-                if (flags & MPIC_BROKEN_FRR_NIRQS)
-                        mpic->num_sources = mpic->irq_count;
-                else
-                        mpic->num_sources =
-                                ((greg_feature & MPIC_GREG_FEATURE_LAST_SRC_MASK)
-                                 >> MPIC_GREG_FEATURE_LAST_SRC_SHIFT) + 1;
-        }
-
-        /*
          * The MPIC driver will crash if there are more cores than we
          * can initialize, so we may as well catch that problem here.
          */
@@ -1336,17 +1322,41 @@ struct mpic * __init mpic_alloc(struct device_node *node,
                          0x1000);
         }
 
+        /*
+         * Read feature register.  For non-ISU MPICs, num sources as well. On
+         * ISU MPICs, sources are counted as ISUs are added
+         */
+        greg_feature = mpic_read(mpic->gregs, MPIC_INFO(GREG_FEATURE_0));
+
+        /*
+         * By default, the last source number comes from the MPIC, but the
+         * device-tree and board support code can override it on buggy hw.
+         * If we get passed an isu_size (multi-isu MPIC) then we use that
+         * as a default instead of the value read from the HW.
+         */
+        last_irq = (greg_feature & MPIC_GREG_FEATURE_LAST_SRC_MASK)
+                                >> MPIC_GREG_FEATURE_LAST_SRC_SHIFT;    
+        if (isu_size)
+                last_irq = isu_size  * MPIC_MAX_ISU - 1;
+        of_property_read_u32(mpic->node, "last-interrupt-source", &last_irq);
+        if (irq_count)
+                last_irq = irq_count - 1;
+
         /* Initialize main ISU if none provided */
-        if (mpic->isu_size == 0) {
-                mpic->isu_size = mpic->num_sources;
+        if (!isu_size) {
+                isu_size = last_irq + 1;
+                mpic->num_sources = isu_size;
                 mpic_map(mpic, mpic->paddr, &mpic->isus[0],
-                         MPIC_INFO(IRQ_BASE), MPIC_INFO(IRQ_STRIDE) * mpic->isu_size);
+                                MPIC_INFO(IRQ_BASE),
+                                MPIC_INFO(IRQ_STRIDE) * isu_size);
         }
+
+        mpic->isu_size = isu_size;
         mpic->isu_shift = 1 + __ilog2(mpic->isu_size - 1);
         mpic->isu_mask = (1 << mpic->isu_shift) - 1;
 
         mpic->irqhost = irq_domain_add_linear(mpic->node,
-                                       isu_size ? isu_size : mpic->num_sources,
+                                       last_irq + 1,
                                        &mpic_host_ops, mpic);
 
         /*
@@ -1380,7 +1390,7 @@ struct mpic * __init mpic_alloc(struct device_node *node,
         mpic->next = mpics;
         mpics = mpic;
 
-        if (!(flags & MPIC_SECONDARY)) {
+        if (!(mpic->flags & MPIC_SECONDARY)) {
                 mpic_primary = mpic;
                 irq_set_default_host(mpic->irqhost);
         }
@@ -1447,10 +1457,6 @@ void __init mpic_init(struct mpic *mpic)
                                (mpic->ipi_vecs[0] + i));
         }
 
-        /* Initialize interrupt sources */
-        if (mpic->irq_count == 0)
-                mpic->irq_count = mpic->num_sources;
-
         /* Do the HT PIC fixups on U3 broken mpic */
         DBG("MPIC flags: %x\n", mpic->flags);
         if ((mpic->flags & MPIC_U3_HT_IRQS) && !(mpic->flags & MPIC_SECONDARY)) {
diff --git a/arch/powerpc/sysdev/mpic_msgr.c b/arch/powerpc/sysdev/mpic_msgr.c
new file mode 100644
index 00000000000..6e7fa386e76
--- /dev/null
+++ b/arch/powerpc/sysdev/mpic_msgr.c
@@ -0,0 +1,282 @@
+/*
+ * Copyright 2011-2012, Meador Inge, Mentor Graphics Corporation.
+ *
+ * Some ideas based on un-pushed work done by Vivek Mahajan, Jason Jin, and
+ * Mingkai Hu from Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; version 2 of the
+ * License.
+ *
+ */
+
+#include <linux/list.h>
+#include <linux/of_platform.h>
+#include <linux/errno.h>
+#include <asm/prom.h>
+#include <asm/hw_irq.h>
+#include <asm/ppc-pci.h>
+#include <asm/mpic_msgr.h>
+
+#define MPIC_MSGR_REGISTERS_PER_BLOCK   4
+#define MPIC_MSGR_STRIDE                0x10
+#define MPIC_MSGR_MER_OFFSET            0x100
+#define MSGR_INUSE                      0
+#define MSGR_FREE                       1
+
+static struct mpic_msgr **mpic_msgrs;
+static unsigned int mpic_msgr_count;
+
+static inline void _mpic_msgr_mer_write(struct mpic_msgr *msgr, u32 value)
+{
+        out_be32(msgr->mer, value);
+}
+
+static inline u32 _mpic_msgr_mer_read(struct mpic_msgr *msgr)
+{
+        return in_be32(msgr->mer);
+}
+
+static inline void _mpic_msgr_disable(struct mpic_msgr *msgr)
+{
+        u32 mer = _mpic_msgr_mer_read(msgr);
+
+        _mpic_msgr_mer_write(msgr, mer & ~(1 << msgr->num));
+}
+
+struct mpic_msgr *mpic_msgr_get(unsigned int reg_num)
+{
+        unsigned long flags;
+        struct mpic_msgr *msgr;
+
+        /* Assume busy until proven otherwise.  */
+        msgr = ERR_PTR(-EBUSY);
+
+        if (reg_num >= mpic_msgr_count)
+                return ERR_PTR(-ENODEV);
+
+        raw_spin_lock_irqsave(&msgr->lock, flags);
+        if (mpic_msgrs[reg_num]->in_use == MSGR_FREE) {
+                msgr = mpic_msgrs[reg_num];
+                msgr->in_use = MSGR_INUSE;
+        }
+        raw_spin_unlock_irqrestore(&msgr->lock, flags);
+
+        return msgr;
+}
+EXPORT_SYMBOL_GPL(mpic_msgr_get);
+
+void mpic_msgr_put(struct mpic_msgr *msgr)
+{
+        unsigned long flags;
+
+        raw_spin_lock_irqsave(&msgr->lock, flags);
+        msgr->in_use = MSGR_FREE;
+        _mpic_msgr_disable(msgr);
+        raw_spin_unlock_irqrestore(&msgr->lock, flags);
+}
+EXPORT_SYMBOL_GPL(mpic_msgr_put);
+
+void mpic_msgr_enable(struct mpic_msgr *msgr)
+{
+        unsigned long flags;
+        u32 mer;
+
+        raw_spin_lock_irqsave(&msgr->lock, flags);
+        mer = _mpic_msgr_mer_read(msgr);
+        _mpic_msgr_mer_write(msgr, mer | (1 << msgr->num));
+        raw_spin_unlock_irqrestore(&msgr->lock, flags);
+}
+EXPORT_SYMBOL_GPL(mpic_msgr_enable);
+
+void mpic_msgr_disable(struct mpic_msgr *msgr)
+{
+        unsigned long flags;
+
+        raw_spin_lock_irqsave(&msgr->lock, flags);
+        _mpic_msgr_disable(msgr);
+        raw_spin_unlock_irqrestore(&msgr->lock, flags);
+}
+EXPORT_SYMBOL_GPL(mpic_msgr_disable);
+
+/* The following three functions are used to compute the order and number of
+ * the message register blocks.  They are clearly very inefficent.  However,
+ * they are called *only* a few times during device initialization.
+ */
+static unsigned int mpic_msgr_number_of_blocks(void)
+{
+        unsigned int count;
+        struct device_node *aliases;
+
+        count = 0;
+        aliases = of_find_node_by_name(NULL, "aliases");
+
+        if (aliases) {
+                char buf[32];
+
+                for (;;) {
+                        snprintf(buf, sizeof(buf), "mpic-msgr-block%d", count);
+                        if (!of_find_property(aliases, buf, NULL))
+                                break;
+
+                        count += 1;
+                }
+        }
+
+        return count;
+}
+
+static unsigned int mpic_msgr_number_of_registers(void)
+{
+        return mpic_msgr_number_of_blocks() * MPIC_MSGR_REGISTERS_PER_BLOCK;
+}
+
+static int mpic_msgr_block_number(struct device_node *node)
+{
+        struct device_node *aliases;
+        unsigned int index, number_of_blocks;
+        char buf[64];
+
+        number_of_blocks = mpic_msgr_number_of_blocks();
+        aliases = of_find_node_by_name(NULL, "aliases");
+        if (!aliases)
+                return -1;
+
+        for (index = 0; index < number_of_blocks; ++index) {
+                struct property *prop;
+
+                snprintf(buf, sizeof(buf), "mpic-msgr-block%d", index);
+                prop = of_find_property(aliases, buf, NULL);
+                if (node == of_find_node_by_path(prop->value))
+                        break;
+        }
+
+        return index == number_of_blocks ? -1 : index;
+}
+
+/* The probe function for a single message register block.
+ */
+static __devinit int mpic_msgr_probe(struct platform_device *dev)
+{
+        void __iomem *msgr_block_addr;
+        int block_number;
+        struct resource rsrc;
+        unsigned int i;
+        unsigned int irq_index;
+        struct device_node *np = dev->dev.of_node;
+        unsigned int receive_mask;
+        const unsigned int *prop;
+
+        if (!np) {
+                dev_err(&dev->dev, "Device OF-Node is NULL");
+                return -EFAULT;
+        }
+
+        /* Allocate the message register array upon the first device
+         * registered.
+         */
+        if (!mpic_msgrs) {
+                mpic_msgr_count = mpic_msgr_number_of_registers();
+                dev_info(&dev->dev, "Found %d message registers\n",
+                                mpic_msgr_count);
+
+                mpic_msgrs = kzalloc(sizeof(struct mpic_msgr) * mpic_msgr_count,
+                                                         GFP_KERNEL);
+                if (!mpic_msgrs) {
+                        dev_err(&dev->dev,
+                                "No memory for message register blocks\n");
+                        return -ENOMEM;
+                }
+        }
+        dev_info(&dev->dev, "Of-device full name %s\n", np->full_name);
+
+        /* IO map the message register block. */
+        of_address_to_resource(np, 0, &rsrc);
+        msgr_block_addr = ioremap(rsrc.start, rsrc.end - rsrc.start);
+        if (!msgr_block_addr) {
+                dev_err(&dev->dev, "Failed to iomap MPIC message registers");
+                return -EFAULT;
+        }
+
+        /* Ensure the block has a defined order. */
+        block_number = mpic_msgr_block_number(np);
+        if (block_number < 0) {
+                dev_err(&dev->dev,
+                        "Failed to find message register block alias\n");
+                return -ENODEV;
+        }
+        dev_info(&dev->dev, "Setting up message register block %d\n",
+                        block_number);
+
+        /* Grab the receive mask which specifies what registers can receive
+         * interrupts.
+         */
+        prop = of_get_property(np, "mpic-msgr-receive-mask", NULL);
+        receive_mask = (prop) ? *prop : 0xF;
+
+        /* Build up the appropriate message register data structures. */
+        for (i = 0, irq_index = 0; i < MPIC_MSGR_REGISTERS_PER_BLOCK; ++i) {
+                struct mpic_msgr *msgr;
+                unsigned int reg_number;
+
+                msgr = kzalloc(sizeof(struct mpic_msgr), GFP_KERNEL);
+                if (!msgr) {
+                        dev_err(&dev->dev, "No memory for message register\n");
+                        return -ENOMEM;
+                }
+
+                reg_number = block_number * MPIC_MSGR_REGISTERS_PER_BLOCK + i;
+                msgr->base = msgr_block_addr + i * MPIC_MSGR_STRIDE;
+                msgr->mer = msgr->base + MPIC_MSGR_MER_OFFSET;
+                msgr->in_use = MSGR_FREE;
+                msgr->num = i;
+                raw_spin_lock_init(&msgr->lock);
+
+                if (receive_mask & (1 << i)) {
+                        struct resource irq;
+
+                        if (of_irq_to_resource(np, irq_index, &irq) == NO_IRQ) {
+                                dev_err(&dev->dev,
+                                                "Missing interrupt specifier");
+                                kfree(msgr);
+                                return -EFAULT;
+                        }
+                        msgr->irq = irq.start;
+                        irq_index += 1;
+                } else {
+                        msgr->irq = NO_IRQ;
+                }
+
+                mpic_msgrs[reg_number] = msgr;
+                mpic_msgr_disable(msgr);
+                dev_info(&dev->dev, "Register %d initialized: irq %d\n",
+                                reg_number, msgr->irq);
+
+        }
+
+        return 0;
+}
+
+static const struct of_device_id mpic_msgr_ids[] = {
+        {
+                .compatible = "fsl,mpic-v3.1-msgr",
+                .data = NULL,
+        },
+        {}
+};
+
+static struct platform_driver mpic_msgr_driver = {
+        .driver = {
+                .name = "mpic-msgr",
+                .owner = THIS_MODULE,
+                .of_match_table = mpic_msgr_ids,
+        },
+        .probe = mpic_msgr_probe,
+};
+
+static __init int mpic_msgr_init(void)
+{
+        return platform_driver_register(&mpic_msgr_driver);
+}
+subsys_initcall(mpic_msgr_init);
diff --git a/arch/powerpc/sysdev/mpic_msi.c b/arch/powerpc/sysdev/mpic_msi.c
index 0622aa91b18..bbf342c8831 100644
--- a/arch/powerpc/sysdev/mpic_msi.c
+++ b/arch/powerpc/sysdev/mpic_msi.c
@@ -54,7 +54,7 @@ static int mpic_msi_reserve_u3_hwirqs(struct mpic *mpic)
         for (i = 100; i < 105; i++)
                 msi_bitmap_reserve_hwirq(&mpic->msi_bitmap, i);
 
-        for (i = 124; i < mpic->irq_count; i++)
+        for (i = 124; i < mpic->num_sources; i++)
                 msi_bitmap_reserve_hwirq(&mpic->msi_bitmap, i);
 
 
@@ -83,7 +83,7 @@ int mpic_msi_init_allocator(struct mpic *mpic)
 {
         int rc;
 
-        rc = msi_bitmap_alloc(&mpic->msi_bitmap, mpic->irq_count,
+        rc = msi_bitmap_alloc(&mpic->msi_bitmap, mpic->num_sources,
                               mpic->irqhost->of_node);
         if (rc)
                 return rc;
diff --git a/arch/powerpc/sysdev/ppc4xx_pci.c b/arch/powerpc/sysdev/ppc4xx_pci.c
index 4f05f754234..56e8b3c3c89 100644
--- a/arch/powerpc/sysdev/ppc4xx_pci.c
+++ b/arch/powerpc/sysdev/ppc4xx_pci.c
@@ -1050,6 +1050,74 @@ static struct ppc4xx_pciex_hwops ppc460ex_pcie_hwops __initdata =
         .check_link     = ppc4xx_pciex_check_link_sdr,
 };
 
+static int __init apm821xx_pciex_core_init(struct device_node *np)
+{
+        /* Return the number of pcie port */
+        return 1;
+}
+
+static int apm821xx_pciex_init_port_hw(struct ppc4xx_pciex_port *port)
+{
+        u32 val;
+
+        /*
+         * Do a software reset on PCIe ports.
+         * This code is to fix the issue that pci drivers doesn't re-assign
+         * bus number for PCIE devices after Uboot
+         * scanned and configured all the buses (eg. PCIE NIC IntelPro/1000
+         * PT quad port, SAS LSI 1064E)
+         */
+
+        mtdcri(SDR0, PESDR0_460EX_PHY_CTL_RST, 0x0);
+        mdelay(10);
+
+        if (port->endpoint)
+                val = PTYPE_LEGACY_ENDPOINT << 20;
+        else
+                val = PTYPE_ROOT_PORT << 20;
+
+        val |= LNKW_X1 << 12;
+
+        mtdcri(SDR0, port->sdr_base + PESDRn_DLPSET, val);
+        mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET1, 0x00000000);
+        mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET2, 0x01010000);
+
+        mtdcri(SDR0, PESDR0_460EX_L0CDRCTL, 0x00003230);
+        mtdcri(SDR0, PESDR0_460EX_L0DRV, 0x00000130);
+        mtdcri(SDR0, PESDR0_460EX_L0CLK, 0x00000006);
+
+        mtdcri(SDR0, PESDR0_460EX_PHY_CTL_RST, 0x10000000);
+        mdelay(50);
+        mtdcri(SDR0, PESDR0_460EX_PHY_CTL_RST, 0x30000000);
+
+        mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET,
+                mfdcri(SDR0, port->sdr_base + PESDRn_RCSSET) |
+                (PESDRx_RCSSET_RSTGU | PESDRx_RCSSET_RSTPYN));
+
+        /* Poll for PHY reset */
+        val = PESDR0_460EX_RSTSTA - port->sdr_base;
+        if (ppc4xx_pciex_wait_on_sdr(port, val, 0x1, 1, 100)) {
+                printk(KERN_WARNING "%s: PCIE: Can't reset PHY\n", __func__);
+                return -EBUSY;
+        } else {
+                mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET,
+                        (mfdcri(SDR0, port->sdr_base + PESDRn_RCSSET) &
+                        ~(PESDRx_RCSSET_RSTGU | PESDRx_RCSSET_RSTDL)) |
+                        PESDRx_RCSSET_RSTPYN);
+
+                port->has_ibpre = 1;
+                return 0;
+        }
+}
+
+static struct ppc4xx_pciex_hwops apm821xx_pcie_hwops __initdata = {
+        .want_sdr   = true,
+        .core_init      = apm821xx_pciex_core_init,
+        .port_init_hw   = apm821xx_pciex_init_port_hw,
+        .setup_utl      = ppc460ex_pciex_init_utl,
+        .check_link = ppc4xx_pciex_check_link_sdr,
+};
+
 static int __init ppc460sx_pciex_core_init(struct device_node *np)
 {
         /* HSS drive amplitude */
@@ -1362,6 +1430,8 @@ static int __init ppc4xx_pciex_check_core_init(struct device_node *np)
                 ppc4xx_pciex_hwops = &ppc460ex_pcie_hwops;
         if (of_device_is_compatible(np, "ibm,plb-pciex-460sx"))
                 ppc4xx_pciex_hwops = &ppc460sx_pcie_hwops;
+        if (of_device_is_compatible(np, "ibm,plb-pciex-apm821xx"))
+                ppc4xx_pciex_hwops = &apm821xx_pcie_hwops;
 #endif /* CONFIG_44x    */
 #ifdef CONFIG_40x
         if (of_device_is_compatible(np, "ibm,plb-pciex-405ex"))
diff --git a/arch/powerpc/xmon/ppc-opc.c b/arch/powerpc/xmon/ppc-opc.c
index af3780e52e7..6845e91ba04 100644
--- a/arch/powerpc/xmon/ppc-opc.c
+++ b/arch/powerpc/xmon/ppc-opc.c
@@ -22,6 +22,7 @@
 
 #include <linux/stddef.h>
 #include <linux/kernel.h>
+#include <linux/bug.h>
 #include "nonstdio.h"
 #include "ppc.h"
 
diff --git a/arch/powerpc/xmon/spu-opc.c b/arch/powerpc/xmon/spu-opc.c
index 530df3d6d7b..7d37597c4bc 100644
--- a/arch/powerpc/xmon/spu-opc.c
+++ b/arch/powerpc/xmon/spu-opc.c
@@ -19,6 +19,7 @@
    51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
 
 #include <linux/kernel.h>
+#include <linux/bug.h>
 #include "spu.h"
 
 /* This file holds the Spu opcode table */
diff --git a/arch/powerpc/xmon/xmon.c b/arch/powerpc/xmon/xmon.c
index cb95eea74d3..68a9cbbab45 100644
--- a/arch/powerpc/xmon/xmon.c
+++ b/arch/powerpc/xmon/xmon.c
@@ -39,7 +39,6 @@
 #include <asm/irq_regs.h>
 #include <asm/spu.h>
 #include <asm/spu_priv1.h>
-#include <asm/firmware.h>
 #include <asm/setjmp.h>
 #include <asm/reg.h>
 
@@ -1437,7 +1436,8 @@ static void excprint(struct pt_regs *fp)
 
         printf("  current = 0x%lx\n", current);
 #ifdef CONFIG_PPC64
-        printf("  paca    = 0x%lx\n", get_paca());
+        printf("  paca    = 0x%lx\t softe: %d\t irq_happened: 0x%02x\n",
+               local_paca, local_paca->soft_enabled, local_paca->irq_happened);
 #endif
         if (current) {
                 printf("    pid   = %ld, comm = %s\n",
@@ -1634,25 +1634,6 @@ static void super_regs(void)
                        mfspr(SPRN_DEC), mfspr(SPRN_SPRG2));
                 printf("sp   = "REG"  sprg3= "REG"\n", sp, mfspr(SPRN_SPRG3));
                 printf("toc  = "REG"  dar  = "REG"\n", toc, mfspr(SPRN_DAR));
-#ifdef CONFIG_PPC_ISERIES
-                if (firmware_has_feature(FW_FEATURE_ISERIES)) {
-                        struct paca_struct *ptrPaca;
-                        struct lppaca *ptrLpPaca;
-
-                        /* Dump out relevant Paca data areas. */
-                        printf("Paca: \n");
-                        ptrPaca = get_paca();
-
-                        printf("  Local Processor Control Area (LpPaca): \n");
-                        ptrLpPaca = ptrPaca->lppaca_ptr;
-                        printf("    Saved Srr0=%.16lx  Saved Srr1=%.16lx \n",
-                               ptrLpPaca->saved_srr0, ptrLpPaca->saved_srr1);
-                        printf("    Saved Gpr3=%.16lx  Saved Gpr4=%.16lx \n",
-                               ptrLpPaca->saved_gpr3, ptrLpPaca->saved_gpr4);
-                        printf("    Saved Gpr5=%.16lx \n",
-                                ptrLpPaca->gpr5_dword.saved_gpr5);
-                }
-#endif
 
                 return;
         }
@@ -2644,7 +2625,7 @@ static void dump_slb(void)
 static void dump_stab(void)
 {
         int i;
-        unsigned long *tmp = (unsigned long *)get_paca()->stab_addr;
+        unsigned long *tmp = (unsigned long *)local_paca->stab_addr;
 
         printf("Segment table contents of cpu %x\n", smp_processor_id());
 
@@ -2855,10 +2836,6 @@ static void dump_tlb_book3e(void)
 
 static void xmon_init(int enable)
 {
-#ifdef CONFIG_PPC_ISERIES
-        if (firmware_has_feature(FW_FEATURE_ISERIES))
-                return;
-#endif
         if (enable) {
                 __debugger = xmon;
                 __debugger_ipi = xmon_ipi;
@@ -2895,10 +2872,6 @@ static struct sysrq_key_op sysrq_xmon_op = {
 
 static int __init setup_xmon_sysrq(void)
 {
-#ifdef CONFIG_PPC_ISERIES
-        if (firmware_has_feature(FW_FEATURE_ISERIES))
-                return 0;
-#endif
         register_sysrq_key('x', &sysrq_xmon_op);
         return 0;
 }
diff --git a/arch/s390/hypfs/inode.c b/arch/s390/hypfs/inode.c
index 8a2a887478c..6a2cb560e96 100644
--- a/arch/s390/hypfs/inode.c
+++ b/arch/s390/hypfs/inode.c
@@ -293,11 +293,9 @@ static int hypfs_fill_super(struct super_block *sb, void *data, int silent)
                 return -ENOMEM;
         root_inode->i_op = &simple_dir_inode_operations;
         root_inode->i_fop = &simple_dir_operations;
-        sb->s_root = root_dentry = d_alloc_root(root_inode);
-        if (!root_dentry) {
-                iput(root_inode);
+        sb->s_root = root_dentry = d_make_root(root_inode);
+        if (!root_dentry)
                 return -ENOMEM;
-        }
         if (MACHINE_IS_VM)
                 rc = hypfs_vm_create_files(sb, root_dentry);
         else
diff --git a/arch/s390/include/asm/cputime.h b/arch/s390/include/asm/cputime.h
index c23c3900c30..24ef186a1c4 100644
--- a/arch/s390/include/asm/cputime.h
+++ b/arch/s390/include/asm/cputime.h
@@ -170,24 +170,17 @@ struct s390_idle_data {
         unsigned int sequence;
         unsigned long long idle_count;
         unsigned long long idle_enter;
+        unsigned long long idle_exit;
         unsigned long long idle_time;
         int nohz_delay;
 };
 
 DECLARE_PER_CPU(struct s390_idle_data, s390_idle);
 
-void vtime_start_cpu(__u64 int_clock, __u64 enter_timer);
 cputime64_t s390_get_idle_time(int cpu);
 
 #define arch_idle_time(cpu) s390_get_idle_time(cpu)
 
-static inline void s390_idle_check(struct pt_regs *regs, __u64 int_clock,
-                                   __u64 enter_timer)
-{
-        if (regs->psw.mask & PSW_MASK_WAIT)
-                vtime_start_cpu(int_clock, enter_timer);
-}
-
 static inline int s390_nohz_delay(int cpu)
 {
         return __get_cpu_var(s390_idle).nohz_delay != 0;
diff --git a/arch/s390/include/asm/debug.h b/arch/s390/include/asm/debug.h
index 9d88db1f55d..8a8245ed14d 100644
--- a/arch/s390/include/asm/debug.h
+++ b/arch/s390/include/asm/debug.h
@@ -131,6 +131,7 @@ void debug_unregister(debug_info_t* id);
 
 void debug_set_level(debug_info_t* id, int new_level);
 
+void debug_set_critical(void);
 void debug_stop_all(void);
 
 static inline debug_entry_t*
diff --git a/arch/s390/include/asm/hardirq.h b/arch/s390/include/asm/hardirq.h
index e4155d3eb2c..510ba9ef424 100644
--- a/arch/s390/include/asm/hardirq.h
+++ b/arch/s390/include/asm/hardirq.h
@@ -18,6 +18,7 @@
 
 #define __ARCH_IRQ_STAT
 #define __ARCH_HAS_DO_SOFTIRQ
+#define __ARCH_IRQ_EXIT_IRQS_DISABLED
 
 #define HARDIRQ_BITS    8
 
diff --git a/arch/s390/include/asm/ipl.h b/arch/s390/include/asm/ipl.h
index 6940abfbe1d..2bd6cb897b9 100644
--- a/arch/s390/include/asm/ipl.h
+++ b/arch/s390/include/asm/ipl.h
@@ -169,5 +169,6 @@ enum diag308_rc {
 extern int diag308(unsigned long subcode, void *addr);
 extern void diag308_reset(void);
 extern void store_status(void);
+extern void lgr_info_log(void);
 
 #endif /* _ASM_S390_IPL_H */
diff --git a/arch/s390/include/asm/irq.h b/arch/s390/include/asm/irq.h
index ba6d85f88d5..acee1806f61 100644
--- a/arch/s390/include/asm/irq.h
+++ b/arch/s390/include/asm/irq.h
@@ -34,7 +34,12 @@ enum interruption_class {
         NR_IRQS,
 };
 
-typedef void (*ext_int_handler_t)(unsigned int, unsigned int, unsigned long);
+struct ext_code {
+        unsigned short subcode;
+        unsigned short code;
+};
+
+typedef void (*ext_int_handler_t)(struct ext_code, unsigned int, unsigned long);
 
 int register_external_interrupt(u16 code, ext_int_handler_t handler);
 int unregister_external_interrupt(u16 code, ext_int_handler_t handler);
diff --git a/arch/s390/include/asm/lowcore.h b/arch/s390/include/asm/lowcore.h
index 707f2306725..47853debb3b 100644
--- a/arch/s390/include/asm/lowcore.h
+++ b/arch/s390/include/asm/lowcore.h
@@ -1,5 +1,5 @@
 /*
- *    Copyright IBM Corp. 1999,2010
+ *    Copyright IBM Corp. 1999,2012
  *    Author(s): Hartmut Penner <hp@de.ibm.com>,
  *               Martin Schwidefsky <schwidefsky@de.ibm.com>,
  *               Denis Joseph Barrow,
@@ -12,14 +12,6 @@
 #include <asm/ptrace.h>
 #include <asm/cpu.h>
 
-void restart_int_handler(void);
-void ext_int_handler(void);
-void system_call(void);
-void pgm_check_handler(void);
-void mcck_int_handler(void);
-void io_int_handler(void);
-void psw_restart_int_handler(void);
-
 #ifdef CONFIG_32BIT
 
 #define LC_ORDER 0
@@ -56,7 +48,7 @@ struct _lowcore {
         psw_t   mcck_new_psw;                   /* 0x0070 */
         psw_t   io_new_psw;                     /* 0x0078 */
         __u32   ext_params;                     /* 0x0080 */
-        __u16   cpu_addr;                       /* 0x0084 */
+        __u16   ext_cpu_addr;                   /* 0x0084 */
         __u16   ext_int_code;                   /* 0x0086 */
         __u16   svc_ilc;                        /* 0x0088 */
         __u16   svc_code;                       /* 0x008a */
@@ -117,32 +109,37 @@ struct _lowcore {
         __u64   steal_timer;                    /* 0x0288 */
         __u64   last_update_timer;              /* 0x0290 */
         __u64   last_update_clock;              /* 0x0298 */
+        __u64   int_clock;                      /* 0x02a0 */
+        __u64   mcck_clock;                     /* 0x02a8 */
+        __u64   clock_comparator;               /* 0x02b0 */
 
         /* Current process. */
-        __u32   current_task;                   /* 0x02a0 */
-        __u32   thread_info;                    /* 0x02a4 */
-        __u32   kernel_stack;                   /* 0x02a8 */
+        __u32   current_task;                   /* 0x02b8 */
+        __u32   thread_info;                    /* 0x02bc */
+        __u32   kernel_stack;                   /* 0x02c0 */
+
+        /* Interrupt, panic and restart stack. */
+        __u32   async_stack;                    /* 0x02c4 */
+        __u32   panic_stack;                    /* 0x02c8 */
+        __u32   restart_stack;                  /* 0x02cc */
 
-        /* Interrupt and panic stack. */
-        __u32   async_stack;                    /* 0x02ac */
-        __u32   panic_stack;                    /* 0x02b0 */
+        /* Restart function and parameter. */
+        __u32   restart_fn;                     /* 0x02d0 */
+        __u32   restart_data;                   /* 0x02d4 */
+        __u32   restart_source;                 /* 0x02d8 */
 
         /* Address space pointer. */
-        __u32   kernel_asce;                    /* 0x02b4 */
-        __u32   user_asce;                      /* 0x02b8 */
-        __u32   current_pid;                    /* 0x02bc */
+        __u32   kernel_asce;                    /* 0x02dc */
+        __u32   user_asce;                      /* 0x02e0 */
+        __u32   current_pid;                    /* 0x02e4 */
 
         /* SMP info area */
-        __u32   cpu_nr;                         /* 0x02c0 */
-        __u32   softirq_pending;                /* 0x02c4 */
-        __u32   percpu_offset;                  /* 0x02c8 */
-        __u32   ext_call_fast;                  /* 0x02cc */
-        __u64   int_clock;                      /* 0x02d0 */
-        __u64   mcck_clock;                     /* 0x02d8 */
-        __u64   clock_comparator;               /* 0x02e0 */
-        __u32   machine_flags;                  /* 0x02e8 */
-        __u32   ftrace_func;                    /* 0x02ec */
-        __u8    pad_0x02f8[0x0300-0x02f0];      /* 0x02f0 */
+        __u32   cpu_nr;                         /* 0x02e8 */
+        __u32   softirq_pending;                /* 0x02ec */
+        __u32   percpu_offset;                  /* 0x02f0 */
+        __u32   machine_flags;                  /* 0x02f4 */
+        __u32   ftrace_func;                    /* 0x02f8 */
+        __u8    pad_0x02fc[0x0300-0x02fc];      /* 0x02fc */
 
         /* Interrupt response block */
         __u8    irb[64];                        /* 0x0300 */
@@ -157,7 +154,9 @@ struct _lowcore {
         __u32   ipib;                           /* 0x0e00 */
         __u32   ipib_checksum;                  /* 0x0e04 */
         __u32   vmcore_info;                    /* 0x0e08 */
-        __u8    pad_0x0e0c[0x0f00-0x0e0c];      /* 0x0e0c */
+        __u8    pad_0x0e0c[0x0e18-0x0e0c];      /* 0x0e0c */
+        __u32   os_info;                        /* 0x0e18 */
+        __u8    pad_0x0e1c[0x0f00-0x0e1c];      /* 0x0e1c */
 
         /* Extended facility list */
         __u64   stfle_fac_list[32];             /* 0x0f00 */
@@ -189,7 +188,7 @@ struct _lowcore {
         __u32   ipl_parmblock_ptr;              /* 0x0014 */
         __u8    pad_0x0018[0x0080-0x0018];      /* 0x0018 */
         __u32   ext_params;                     /* 0x0080 */
-        __u16   cpu_addr;                       /* 0x0084 */
+        __u16   ext_cpu_addr;                   /* 0x0084 */
         __u16   ext_int_code;                   /* 0x0086 */
         __u16   svc_ilc;                        /* 0x0088 */
         __u16   svc_code;                       /* 0x008a */
@@ -254,34 +253,39 @@ struct _lowcore {
         __u64   steal_timer;                    /* 0x02e0 */
         __u64   last_update_timer;              /* 0x02e8 */
         __u64   last_update_clock;              /* 0x02f0 */
+        __u64   int_clock;                      /* 0x02f8 */
+        __u64   mcck_clock;                     /* 0x0300 */
+        __u64   clock_comparator;               /* 0x0308 */
 
         /* Current process. */
-        __u64   current_task;                   /* 0x02f8 */
-        __u64   thread_info;                    /* 0x0300 */
-        __u64   kernel_stack;                   /* 0x0308 */
+        __u64   current_task;                   /* 0x0310 */
+        __u64   thread_info;                    /* 0x0318 */
+        __u64   kernel_stack;                   /* 0x0320 */
+
+        /* Interrupt, panic and restart stack. */
+        __u64   async_stack;                    /* 0x0328 */
+        __u64   panic_stack;                    /* 0x0330 */
+        __u64   restart_stack;                  /* 0x0338 */
 
-        /* Interrupt and panic stack. */
-        __u64   async_stack;                    /* 0x0310 */
-        __u64   panic_stack;                    /* 0x0318 */
+        /* Restart function and parameter. */
+        __u64   restart_fn;                     /* 0x0340 */
+        __u64   restart_data;                   /* 0x0348 */
+        __u64   restart_source;                 /* 0x0350 */
 
         /* Address space pointer. */
-        __u64   kernel_asce;                    /* 0x0320 */
-        __u64   user_asce;                      /* 0x0328 */
-        __u64   current_pid;                    /* 0x0330 */
+        __u64   kernel_asce;                    /* 0x0358 */
+        __u64   user_asce;                      /* 0x0360 */
+        __u64   current_pid;                    /* 0x0368 */
 
         /* SMP info area */
-        __u32   cpu_nr;                         /* 0x0338 */
-        __u32   softirq_pending;                /* 0x033c */
-        __u64   percpu_offset;                  /* 0x0340 */
-        __u64   ext_call_fast;                  /* 0x0348 */
-        __u64   int_clock;                      /* 0x0350 */
-        __u64   mcck_clock;                     /* 0x0358 */
-        __u64   clock_comparator;               /* 0x0360 */
-        __u64   vdso_per_cpu_data;              /* 0x0368 */
-        __u64   machine_flags;                  /* 0x0370 */
-        __u64   ftrace_func;                    /* 0x0378 */
-        __u64   gmap;                           /* 0x0380 */
-        __u8    pad_0x0388[0x0400-0x0388];      /* 0x0388 */
+        __u32   cpu_nr;                         /* 0x0370 */
+        __u32   softirq_pending;                /* 0x0374 */
+        __u64   percpu_offset;                  /* 0x0378 */
+        __u64   vdso_per_cpu_data;              /* 0x0380 */
+        __u64   machine_flags;                  /* 0x0388 */
+        __u64   ftrace_func;                    /* 0x0390 */
+        __u64   gmap;                           /* 0x0398 */
+        __u8    pad_0x03a0[0x0400-0x03a0];      /* 0x03a0 */
 
         /* Interrupt response block. */
         __u8    irb[64];                        /* 0x0400 */
@@ -298,8 +302,15 @@ struct _lowcore {
          */
         __u64   ipib;                           /* 0x0e00 */
         __u32   ipib_checksum;                  /* 0x0e08 */
-        __u64   vmcore_info;                    /* 0x0e0c */
-        __u8    pad_0x0e14[0x0f00-0x0e14];      /* 0x0e14 */
+        /*
+         * Because the vmcore_info pointer is not 8 byte aligned it never
+         * should not be accessed directly. For accessing the pointer, first
+         * copy it to a local pointer variable.
+         */
+        __u8    vmcore_info[8];                 /* 0x0e0c */
+        __u8    pad_0x0e14[0x0e18-0x0e14];      /* 0x0e14 */
+        __u64   os_info;                        /* 0x0e18 */
+        __u8    pad_0x0e20[0x0f00-0x0e20];      /* 0x0e20 */
 
         /* Extended facility list */
         __u64   stfle_fac_list[32];             /* 0x0f00 */
diff --git a/arch/s390/include/asm/os_info.h b/arch/s390/include/asm/os_info.h
new file mode 100644
index 00000000000..d07518af09e
--- /dev/null
+++ b/arch/s390/include/asm/os_info.h
@@ -0,0 +1,50 @@
+/*
+ * OS info memory interface
+ *
+ * Copyright IBM Corp. 2012
+ * Author(s): Michael Holzheu <holzheu@linux.vnet.ibm.com>
+ */
+#ifndef _ASM_S390_OS_INFO_H
+#define _ASM_S390_OS_INFO_H
+
+#define OS_INFO_VERSION_MAJOR   1
+#define OS_INFO_VERSION_MINOR   1
+#define OS_INFO_MAGIC           0x4f53494e464f535aULL /* OSINFOSZ */
+
+#define OS_INFO_VMCOREINFO      0
+#define OS_INFO_REIPL_BLOCK     1
+#define OS_INFO_INIT_FN         2
+
+struct os_info_entry {
+        u64     addr;
+        u64     size;
+        u32     csum;
+} __packed;
+
+struct os_info {
+        u64     magic;
+        u32     csum;
+        u16     version_major;
+        u16     version_minor;
+        u64     crashkernel_addr;
+        u64     crashkernel_size;
+        struct os_info_entry entry[3];
+        u8      reserved[4004];
+} __packed;
+
+void os_info_init(void);
+void os_info_entry_add(int nr, void *ptr, u64 len);
+void os_info_crashkernel_add(unsigned long base, unsigned long size);
+u32 os_info_csum(struct os_info *os_info);
+
+#ifdef CONFIG_CRASH_DUMP
+void *os_info_old_entry(int nr, unsigned long *size);
+int copy_from_oldmem(void *dest, void *src, size_t count);
+#else
+static inline void *os_info_old_entry(int nr, unsigned long *size)
+{
+        return NULL;
+}
+#endif
+
+#endif /* _ASM_S390_OS_INFO_H */
diff --git a/arch/s390/include/asm/sigp.h b/arch/s390/include/asm/sigp.h
deleted file mode 100644
index 7040b8567cd..00000000000
--- a/arch/s390/include/asm/sigp.h
+++ /dev/null
@@ -1,132 +0,0 @@
-/*
- *  Routines and structures for signalling other processors.
- *
- *    Copyright IBM Corp. 1999,2010
- *    Author(s): Denis Joseph Barrow,
- *               Martin Schwidefsky <schwidefsky@de.ibm.com>,
- *               Heiko Carstens <heiko.carstens@de.ibm.com>,
- */
-
-#ifndef __ASM_SIGP_H
-#define __ASM_SIGP_H
-
-#include <asm/system.h>
-
-/* Get real cpu address from logical cpu number. */
-extern unsigned short __cpu_logical_map[];
-
-static inline int cpu_logical_map(int cpu)
-{
-#ifdef CONFIG_SMP
-        return __cpu_logical_map[cpu];
-#else
-        return stap();
-#endif
-}
-
-enum {
-        sigp_sense = 1,
-        sigp_external_call = 2,
-        sigp_emergency_signal = 3,
-        sigp_start = 4,
-        sigp_stop = 5,
-        sigp_restart = 6,
-        sigp_stop_and_store_status = 9,
-        sigp_initial_cpu_reset = 11,
-        sigp_cpu_reset = 12,
-        sigp_set_prefix = 13,
-        sigp_store_status_at_address = 14,
-        sigp_store_extended_status_at_address = 15,
-        sigp_set_architecture = 18,
-        sigp_conditional_emergency_signal = 19,
-        sigp_sense_running = 21,
-};
-
-enum {
-        sigp_order_code_accepted = 0,
-        sigp_status_stored = 1,
-        sigp_busy = 2,
-        sigp_not_operational = 3,
-};
-
-/*
- * Definitions for external call.
- */
-enum {
-        ec_schedule = 0,
-        ec_call_function,
-        ec_call_function_single,
-        ec_stop_cpu,
-};
-
-/*
- * Signal processor.
- */
-static inline int raw_sigp(u16 cpu, int order)
-{
-        register unsigned long reg1 asm ("1") = 0;
-        int ccode;
-
-        asm volatile(
-                "       sigp    %1,%2,0(%3)\n"
-                "       ipm     %0\n"
-                "       srl     %0,28\n"
-                :       "=d"    (ccode)
-                : "d" (reg1), "d" (cpu),
-                  "a" (order) : "cc" , "memory");
-        return ccode;
-}
-
-/*
- * Signal processor with parameter.
- */
-static inline int raw_sigp_p(u32 parameter, u16 cpu, int order)
-{
-        register unsigned int reg1 asm ("1") = parameter;
-        int ccode;
-
-        asm volatile(
-                "       sigp    %1,%2,0(%3)\n"
-                "       ipm     %0\n"
-                "       srl     %0,28\n"
-                : "=d" (ccode)
-                : "d" (reg1), "d" (cpu),
-                  "a" (order) : "cc" , "memory");
-        return ccode;
-}
-
-/*
- * Signal processor with parameter and return status.
- */
-static inline int raw_sigp_ps(u32 *status, u32 parm, u16 cpu, int order)
-{
-        register unsigned int reg1 asm ("1") = parm;
-        int ccode;
-
-        asm volatile(
-                "       sigp    %1,%2,0(%3)\n"
-                "       ipm     %0\n"
-                "       srl     %0,28\n"
-                : "=d" (ccode), "+d" (reg1)
-                : "d" (cpu), "a" (order)
-                : "cc" , "memory");
-        *status = reg1;
-        return ccode;
-}
-
-static inline int sigp(int cpu, int order)
-{
-        return raw_sigp(cpu_logical_map(cpu), order);
-}
-
-static inline int sigp_p(u32 parameter, int cpu, int order)
-{
-        return raw_sigp_p(parameter, cpu_logical_map(cpu), order);
-}
-
-static inline int sigp_ps(u32 *status, u32 parm, int cpu, int order)
-{
-        return raw_sigp_ps(status, parm, cpu_logical_map(cpu), order);
-}
-
-#endif /* __ASM_SIGP_H */
diff --git a/arch/s390/include/asm/smp.h b/arch/s390/include/asm/smp.h
index c32e9123b40..797f7872968 100644
--- a/arch/s390/include/asm/smp.h
+++ b/arch/s390/include/asm/smp.h
@@ -1,5 +1,5 @@
 /*
- *    Copyright IBM Corp. 1999,2009
+ *    Copyright IBM Corp. 1999,2012
  *    Author(s): Denis Joseph Barrow,
  *               Martin Schwidefsky <schwidefsky@de.ibm.com>,
  *               Heiko Carstens <heiko.carstens@de.ibm.com>,
@@ -10,71 +10,52 @@
 #ifdef CONFIG_SMP
 
 #include <asm/system.h>
-#include <asm/sigp.h>
-
-extern void machine_restart_smp(char *);
-extern void machine_halt_smp(void);
-extern void machine_power_off_smp(void);
 
 #define raw_smp_processor_id()  (S390_lowcore.cpu_nr)
 
-extern int __cpu_disable (void);
-extern void __cpu_die (unsigned int cpu);
-extern int __cpu_up (unsigned int cpu);
-
 extern struct mutex smp_cpu_state_mutex;
+extern struct save_area *zfcpdump_save_areas[NR_CPUS + 1];
+
+extern int __cpu_up(unsigned int cpu);
 
 extern void arch_send_call_function_single_ipi(int cpu);
 extern void arch_send_call_function_ipi_mask(const struct cpumask *mask);
 
-extern struct save_area *zfcpdump_save_areas[NR_CPUS + 1];
-
-extern void smp_switch_to_ipl_cpu(void (*func)(void *), void *);
-extern void smp_switch_to_cpu(void (*)(void *), void *, unsigned long sp,
-                              int from, int to);
-extern void smp_restart_with_online_cpu(void);
-extern void smp_restart_cpu(void);
+extern void smp_call_online_cpu(void (*func)(void *), void *);
+extern void smp_call_ipl_cpu(void (*func)(void *), void *);
 
-/*
- * returns 1 if (virtual) cpu is scheduled
- * returns 0 otherwise
- */
-static inline int smp_vcpu_scheduled(int cpu)
-{
-        u32 status;
-
-        switch (sigp_ps(&status, 0, cpu, sigp_sense_running)) {
-        case sigp_status_stored:
-                /* Check for running status */
-                if (status & 0x400)
-                        return 0;
-                break;
-        case sigp_not_operational:
-                return 0;
-        default:
-                break;
-        }
-        return 1;
-}
+extern int smp_find_processor_id(u16 address);
+extern int smp_store_status(int cpu);
+extern int smp_vcpu_scheduled(int cpu);
+extern void smp_yield_cpu(int cpu);
+extern void smp_yield(void);
+extern void smp_stop_cpu(void);
 
 #else /* CONFIG_SMP */
 
-static inline void smp_switch_to_ipl_cpu(void (*func)(void *), void *data)
+static inline void smp_call_ipl_cpu(void (*func)(void *), void *data)
 {
         func(data);
 }
 
-static inline void smp_restart_with_online_cpu(void)
+static inline void smp_call_online_cpu(void (*func)(void *), void *data)
 {
+        func(data);
 }
 
-#define smp_vcpu_scheduled      (1)
+static inline int smp_find_processor_id(int address) { return 0; }
+static inline int smp_vcpu_scheduled(int cpu) { return 1; }
+static inline void smp_yield_cpu(int cpu) { }
+static inline void smp_yield(void) { }
+static inline void smp_stop_cpu(void) { }
 
 #endif /* CONFIG_SMP */
 
 #ifdef CONFIG_HOTPLUG_CPU
 extern int smp_rescan_cpus(void);
 extern void __noreturn cpu_die(void);
+extern void __cpu_die(unsigned int cpu);
+extern int __cpu_disable(void);
 #else
 static inline int smp_rescan_cpus(void) { return 0; }
 static inline void cpu_die(void) { }
diff --git a/arch/s390/include/asm/system.h b/arch/s390/include/asm/system.h
index d73cc6b6000..2e0bb7f0f9b 100644
--- a/arch/s390/include/asm/system.h
+++ b/arch/s390/include/asm/system.h
@@ -7,8 +7,10 @@
 #ifndef __ASM_SYSTEM_H
 #define __ASM_SYSTEM_H
 
+#include <linux/preempt.h>
 #include <linux/kernel.h>
 #include <linux/errno.h>
+#include <linux/string.h>
 #include <asm/types.h>
 #include <asm/ptrace.h>
 #include <asm/setup.h>
@@ -248,6 +250,38 @@ static inline int test_facility(unsigned long nr)
         return (*ptr & (0x80 >> (nr & 7))) != 0;
 }
 
+/**
+ * stfle - Store facility list extended
+ * @stfle_fac_list: array where facility list can be stored
+ * @size: size of passed in array in double words
+ */
+static inline void stfle(u64 *stfle_fac_list, int size)
+{
+        unsigned long nr;
+
+        preempt_disable();
+        S390_lowcore.stfl_fac_list = 0;
+        asm volatile(
+                "       .insn s,0xb2b10000,0(0)\n" /* stfl */
+                "0:\n"
+                EX_TABLE(0b, 0b)
+                : "=m" (S390_lowcore.stfl_fac_list));
+        nr = 4; /* bytes stored by stfl */
+        memcpy(stfle_fac_list, &S390_lowcore.stfl_fac_list, 4);
+        if (S390_lowcore.stfl_fac_list & 0x01000000) {
+                /* More facility bits available with stfle */
+                register unsigned long reg0 asm("0") = size - 1;
+
+                asm volatile(".insn s,0xb2b00000,0(%1)" /* stfle */
+                             : "+d" (reg0)
+                             : "a" (stfle_fac_list)
+                             : "memory", "cc");
+                nr = (reg0 + 1) * 8; /* # bytes stored by stfle */
+        }
+        memset((char *) stfle_fac_list + nr, 0, size * 8 - nr);
+        preempt_enable();
+}
+
 static inline unsigned short stap(void)
 {
         unsigned short cpu_address;
diff --git a/arch/s390/include/asm/timer.h b/arch/s390/include/asm/timer.h
index 814243cafdf..e63069ba39e 100644
--- a/arch/s390/include/asm/timer.h
+++ b/arch/s390/include/asm/timer.h
@@ -33,8 +33,8 @@ struct vtimer_queue {
         spinlock_t lock;
         __u64 timer;            /* last programmed timer */
         __u64 elapsed;          /* elapsed time of timer expire values */
-        __u64 idle;             /* temp var for idle */
-        int do_spt;             /* =1: reprogram cpu timer in idle */
+        __u64 idle_enter;       /* cpu timer on idle enter */
+        __u64 idle_exit;        /* cpu timer on idle exit */
 };
 
 extern void init_virt_timer(struct vtimer_list *timer);
diff --git a/arch/s390/include/asm/vdso.h b/arch/s390/include/asm/vdso.h
index 533f35751ae..c4a11cfad3c 100644
--- a/arch/s390/include/asm/vdso.h
+++ b/arch/s390/include/asm/vdso.h
@@ -40,8 +40,8 @@ struct vdso_per_cpu_data {
 extern struct vdso_data *vdso_data;
 
 #ifdef CONFIG_64BIT
-int vdso_alloc_per_cpu(int cpu, struct _lowcore *lowcore);
-void vdso_free_per_cpu(int cpu, struct _lowcore *lowcore);
+int vdso_alloc_per_cpu(struct _lowcore *lowcore);
+void vdso_free_per_cpu(struct _lowcore *lowcore);
 #endif
 
 #endif /* __ASSEMBLY__ */
diff --git a/arch/s390/kernel/Makefile b/arch/s390/kernel/Makefile
index 7d9ec924e7e..16b0b433f1f 100644
--- a/arch/s390/kernel/Makefile
+++ b/arch/s390/kernel/Makefile
@@ -23,7 +23,7 @@ CFLAGS_sysinfo.o += -Iinclude/math-emu -Iarch/s390/math-emu -w
 obj-y   :=  bitmap.o traps.o time.o process.o base.o early.o setup.o vtime.o \
             processor.o sys_s390.o ptrace.o signal.o cpcmd.o ebcdic.o nmi.o \
             debug.o irq.o ipl.o dis.o diag.o mem_detect.o sclp.o vdso.o \
-            sysinfo.o jump_label.o
+            sysinfo.o jump_label.o lgr.o os_info.o
 
 obj-y   += $(if $(CONFIG_64BIT),entry64.o,entry.o)
 obj-y   += $(if $(CONFIG_64BIT),reipl64.o,reipl.o)
@@ -34,8 +34,6 @@ extra-y				+= $(if $(CONFIG_64BIT),head64.o,head31.o)
 obj-$(CONFIG_MODULES)           += s390_ksyms.o module.o
 obj-$(CONFIG_SMP)               += smp.o
 obj-$(CONFIG_SCHED_BOOK)        += topology.o
-obj-$(CONFIG_SMP)               += $(if $(CONFIG_64BIT),switch_cpu64.o, \
-                                                        switch_cpu.o)
 obj-$(CONFIG_HIBERNATION)       += suspend.o swsusp_asm64.o
 obj-$(CONFIG_AUDIT)             += audit.o
 compat-obj-$(CONFIG_AUDIT)      += compat_audit.o
diff --git a/arch/s390/kernel/asm-offsets.c b/arch/s390/kernel/asm-offsets.c
index 6e6a72e66d6..ed8c913db79 100644
--- a/arch/s390/kernel/asm-offsets.c
+++ b/arch/s390/kernel/asm-offsets.c
@@ -8,9 +8,11 @@
 
 #include <linux/kbuild.h>
 #include <linux/sched.h>
+#include <asm/cputime.h>
+#include <asm/timer.h>
 #include <asm/vdso.h>
-#include <asm/sigp.h>
 #include <asm/pgtable.h>
+#include <asm/system.h>
 
 /*
  * Make sure that the compiler is new enough. We want a compiler that
@@ -70,15 +72,15 @@ int main(void)
         DEFINE(__CLOCK_MONOTONIC, CLOCK_MONOTONIC);
         DEFINE(__CLOCK_REALTIME_RES, MONOTONIC_RES_NSEC);
         BLANK();
-        /* constants for SIGP */
-        DEFINE(__SIGP_STOP, sigp_stop);
-        DEFINE(__SIGP_RESTART, sigp_restart);
-        DEFINE(__SIGP_SENSE, sigp_sense);
-        DEFINE(__SIGP_INITIAL_CPU_RESET, sigp_initial_cpu_reset);
-        BLANK();
+        /* idle data offsets */
+        DEFINE(__IDLE_ENTER, offsetof(struct s390_idle_data, idle_enter));
+        DEFINE(__IDLE_EXIT, offsetof(struct s390_idle_data, idle_exit));
+        /* vtimer queue offsets */
+        DEFINE(__VQ_IDLE_ENTER, offsetof(struct vtimer_queue, idle_enter));
+        DEFINE(__VQ_IDLE_EXIT, offsetof(struct vtimer_queue, idle_exit));
         /* lowcore offsets */
         DEFINE(__LC_EXT_PARAMS, offsetof(struct _lowcore, ext_params));
-        DEFINE(__LC_CPU_ADDRESS, offsetof(struct _lowcore, cpu_addr));
+        DEFINE(__LC_EXT_CPU_ADDR, offsetof(struct _lowcore, ext_cpu_addr));
         DEFINE(__LC_EXT_INT_CODE, offsetof(struct _lowcore, ext_int_code));
         DEFINE(__LC_SVC_ILC, offsetof(struct _lowcore, svc_ilc));
         DEFINE(__LC_SVC_INT_CODE, offsetof(struct _lowcore, svc_code));
@@ -95,20 +97,19 @@ int main(void)
         DEFINE(__LC_IO_INT_WORD, offsetof(struct _lowcore, io_int_word));
         DEFINE(__LC_STFL_FAC_LIST, offsetof(struct _lowcore, stfl_fac_list));
         DEFINE(__LC_MCCK_CODE, offsetof(struct _lowcore, mcck_interruption_code));
-        DEFINE(__LC_DUMP_REIPL, offsetof(struct _lowcore, ipib));
-        BLANK();
-        DEFINE(__LC_RST_NEW_PSW, offsetof(struct _lowcore, restart_psw));
         DEFINE(__LC_RST_OLD_PSW, offsetof(struct _lowcore, restart_old_psw));
         DEFINE(__LC_EXT_OLD_PSW, offsetof(struct _lowcore, external_old_psw));
         DEFINE(__LC_SVC_OLD_PSW, offsetof(struct _lowcore, svc_old_psw));
         DEFINE(__LC_PGM_OLD_PSW, offsetof(struct _lowcore, program_old_psw));
         DEFINE(__LC_MCK_OLD_PSW, offsetof(struct _lowcore, mcck_old_psw));
         DEFINE(__LC_IO_OLD_PSW, offsetof(struct _lowcore, io_old_psw));
+        DEFINE(__LC_RST_NEW_PSW, offsetof(struct _lowcore, restart_psw));
         DEFINE(__LC_EXT_NEW_PSW, offsetof(struct _lowcore, external_new_psw));
         DEFINE(__LC_SVC_NEW_PSW, offsetof(struct _lowcore, svc_new_psw));
         DEFINE(__LC_PGM_NEW_PSW, offsetof(struct _lowcore, program_new_psw));
         DEFINE(__LC_MCK_NEW_PSW, offsetof(struct _lowcore, mcck_new_psw));
         DEFINE(__LC_IO_NEW_PSW, offsetof(struct _lowcore, io_new_psw));
+        BLANK();
         DEFINE(__LC_SAVE_AREA_SYNC, offsetof(struct _lowcore, save_area_sync));
         DEFINE(__LC_SAVE_AREA_ASYNC, offsetof(struct _lowcore, save_area_async));
         DEFINE(__LC_SAVE_AREA_RESTART, offsetof(struct _lowcore, save_area_restart));
@@ -129,12 +130,16 @@ int main(void)
         DEFINE(__LC_KERNEL_STACK, offsetof(struct _lowcore, kernel_stack));
         DEFINE(__LC_ASYNC_STACK, offsetof(struct _lowcore, async_stack));
         DEFINE(__LC_PANIC_STACK, offsetof(struct _lowcore, panic_stack));
+        DEFINE(__LC_RESTART_STACK, offsetof(struct _lowcore, restart_stack));
+        DEFINE(__LC_RESTART_FN, offsetof(struct _lowcore, restart_fn));
         DEFINE(__LC_USER_ASCE, offsetof(struct _lowcore, user_asce));
         DEFINE(__LC_INT_CLOCK, offsetof(struct _lowcore, int_clock));
         DEFINE(__LC_MCCK_CLOCK, offsetof(struct _lowcore, mcck_clock));
         DEFINE(__LC_MACHINE_FLAGS, offsetof(struct _lowcore, machine_flags));
         DEFINE(__LC_FTRACE_FUNC, offsetof(struct _lowcore, ftrace_func));
         DEFINE(__LC_IRB, offsetof(struct _lowcore, irb));
+        DEFINE(__LC_DUMP_REIPL, offsetof(struct _lowcore, ipib));
+        BLANK();
         DEFINE(__LC_CPU_TIMER_SAVE_AREA, offsetof(struct _lowcore, cpu_timer_save_area));
         DEFINE(__LC_CLOCK_COMP_SAVE_AREA, offsetof(struct _lowcore, clock_comp_save_area));
         DEFINE(__LC_PSW_SAVE_AREA, offsetof(struct _lowcore, psw_save_area));
diff --git a/arch/s390/kernel/compat_signal.c b/arch/s390/kernel/compat_signal.c
index 6fe78c2f95d..53a82c8d50e 100644
--- a/arch/s390/kernel/compat_signal.c
+++ b/arch/s390/kernel/compat_signal.c
@@ -581,7 +581,6 @@ give_sigsegv:
 int handle_signal32(unsigned long sig, struct k_sigaction *ka,
                     siginfo_t *info, sigset_t *oldset, struct pt_regs *regs)
 {
-        sigset_t blocked;
         int ret;
 
         /* Set up the stack frame */
@@ -591,10 +590,7 @@ int handle_signal32(unsigned long sig, struct k_sigaction *ka,
                 ret = setup_frame32(sig, ka, oldset, regs);
         if (ret)
                 return ret;
-        sigorsets(&blocked, &current->blocked, &ka->sa.sa_mask);
-        if (!(ka->sa.sa_flags & SA_NODEFER))
-                sigaddset(&blocked, sig);
-        set_current_blocked(&blocked);
+        block_sigmask(ka, sig);
         return 0;
 }
 
diff --git a/arch/s390/kernel/crash_dump.c b/arch/s390/kernel/crash_dump.c
index c383ce440d9..cc1172b2687 100644
--- a/arch/s390/kernel/crash_dump.c
+++ b/arch/s390/kernel/crash_dump.c
@@ -14,6 +14,7 @@
 #include <linux/bootmem.h>
 #include <linux/elf.h>
 #include <asm/ipl.h>
+#include <asm/os_info.h>
 
 #define PTR_ADD(x, y) (((char *) (x)) + ((unsigned long) (y)))
 #define PTR_SUB(x, y) (((char *) (x)) - ((unsigned long) (y)))
@@ -51,7 +52,7 @@ ssize_t copy_oldmem_page(unsigned long pfn, char *buf,
 /*
  * Copy memory from old kernel
  */
-static int copy_from_oldmem(void *dest, void *src, size_t count)
+int copy_from_oldmem(void *dest, void *src, size_t count)
 {
         unsigned long copied = 0;
         int rc;
@@ -224,28 +225,44 @@ static void *nt_prpsinfo(void *ptr)
 }
 
 /*
- * Initialize vmcoreinfo note (new kernel)
+ * Get vmcoreinfo using lowcore->vmcore_info (new kernel)
  */
-static void *nt_vmcoreinfo(void *ptr)
+static void *get_vmcoreinfo_old(unsigned long *size)
 {
         char nt_name[11], *vmcoreinfo;
         Elf64_Nhdr note;
         void *addr;
 
         if (copy_from_oldmem(&addr, &S390_lowcore.vmcore_info, sizeof(addr)))
-                return ptr;
+                return NULL;
         memset(nt_name, 0, sizeof(nt_name));
         if (copy_from_oldmem(&note, addr, sizeof(note)))
-                return ptr;
+                return NULL;
         if (copy_from_oldmem(nt_name, addr + sizeof(note), sizeof(nt_name) - 1))
-                return ptr;
+                return NULL;
         if (strcmp(nt_name, "VMCOREINFO") != 0)
-                return ptr;
-        vmcoreinfo = kzalloc_panic(note.n_descsz + 1);
+                return NULL;
+        vmcoreinfo = kzalloc_panic(note.n_descsz);
         if (copy_from_oldmem(vmcoreinfo, addr + 24, note.n_descsz))
+                return NULL;
+        *size = note.n_descsz;
+        return vmcoreinfo;
+}
+
+/*
+ * Initialize vmcoreinfo note (new kernel)
+ */
+static void *nt_vmcoreinfo(void *ptr)
+{
+        unsigned long size;
+        void *vmcoreinfo;
+
+        vmcoreinfo = os_info_old_entry(OS_INFO_VMCOREINFO, &size);
+        if (!vmcoreinfo)
+                vmcoreinfo = get_vmcoreinfo_old(&size);
+        if (!vmcoreinfo)
                 return ptr;
-        vmcoreinfo[note.n_descsz + 1] = 0;
-        return nt_init(ptr, 0, vmcoreinfo, note.n_descsz, "VMCOREINFO");
+        return nt_init(ptr, 0, vmcoreinfo, size, "VMCOREINFO");
 }
 
 /*
diff --git a/arch/s390/kernel/debug.c b/arch/s390/kernel/debug.c
index 6848828b962..19e5e9eba54 100644
--- a/arch/s390/kernel/debug.c
+++ b/arch/s390/kernel/debug.c
@@ -2,8 +2,8 @@
  *  arch/s390/kernel/debug.c
  *   S/390 debug facility
  *
- *    Copyright (C) 1999, 2000 IBM Deutschland Entwicklung GmbH,
- *                             IBM Corporation
+ *    Copyright IBM Corp. 1999, 2012
+ *
  *    Author(s): Michael Holzheu (holzheu@de.ibm.com),
  *               Holger Smolinski (Holger.Smolinski@de.ibm.com)
  *
@@ -167,6 +167,7 @@ static debug_info_t *debug_area_last = NULL;
 static DEFINE_MUTEX(debug_mutex);
 
 static int initialized;
+static int debug_critical;
 
 static const struct file_operations debug_file_ops = {
         .owner   = THIS_MODULE,
@@ -932,6 +933,11 @@ debug_stop_all(void)
 }
 
 
+void debug_set_critical(void)
+{
+        debug_critical = 1;
+}
+
 /*
  * debug_event_common:
  * - write debug entry with given size
@@ -945,7 +951,11 @@ debug_event_common(debug_info_t * id, int level, const void *buf, int len)
 
         if (!debug_active || !id->areas)
                 return NULL;
-        spin_lock_irqsave(&id->lock, flags);
+        if (debug_critical) {
+                if (!spin_trylock_irqsave(&id->lock, flags))
+                        return NULL;
+        } else
+                spin_lock_irqsave(&id->lock, flags);
         active = get_active_entry(id);
         memset(DEBUG_DATA(active), 0, id->buf_size);
         memcpy(DEBUG_DATA(active), buf, min(len, id->buf_size));
@@ -968,7 +978,11 @@ debug_entry_t
 
         if (!debug_active || !id->areas)
                 return NULL;
-        spin_lock_irqsave(&id->lock, flags);
+        if (debug_critical) {
+                if (!spin_trylock_irqsave(&id->lock, flags))
+                        return NULL;
+        } else
+                spin_lock_irqsave(&id->lock, flags);
         active = get_active_entry(id);
         memset(DEBUG_DATA(active), 0, id->buf_size);
         memcpy(DEBUG_DATA(active), buf, min(len, id->buf_size));
@@ -1013,7 +1027,11 @@ debug_sprintf_event(debug_info_t* id, int level,char *string,...)
                 return NULL;
         numargs=debug_count_numargs(string);
 
-        spin_lock_irqsave(&id->lock, flags);
+        if (debug_critical) {
+                if (!spin_trylock_irqsave(&id->lock, flags))
+                        return NULL;
+        } else
+                spin_lock_irqsave(&id->lock, flags);
         active = get_active_entry(id);
         curr_event=(debug_sprintf_entry_t *) DEBUG_DATA(active);
         va_start(ap,string);
@@ -1047,7 +1065,11 @@ debug_sprintf_exception(debug_info_t* id, int level,char *string,...)
 
         numargs=debug_count_numargs(string);
 
-        spin_lock_irqsave(&id->lock, flags);
+        if (debug_critical) {
+                if (!spin_trylock_irqsave(&id->lock, flags))
+                        return NULL;
+        } else
+                spin_lock_irqsave(&id->lock, flags);
         active = get_active_entry(id);
         curr_event=(debug_sprintf_entry_t *)DEBUG_DATA(active);
         va_start(ap,string);
@@ -1428,10 +1450,10 @@ debug_hex_ascii_format_fn(debug_info_t * id, struct debug_view *view,
         rc += sprintf(out_buf + rc, "| ");
         for (i = 0; i < id->buf_size; i++) {
                 unsigned char c = in_buf[i];
-                if (!isprint(c))
-                        rc += sprintf(out_buf + rc, ".");
-                else
+                if (isascii(c) && isprint(c))
                         rc += sprintf(out_buf + rc, "%c", c);
+                else
+                        rc += sprintf(out_buf + rc, ".");
         }
         rc += sprintf(out_buf + rc, "\n");
         return rc;
diff --git a/arch/s390/kernel/early.c b/arch/s390/kernel/early.c
index 52098d6dfaa..578eb4e6d15 100644
--- a/arch/s390/kernel/early.c
+++ b/arch/s390/kernel/early.c
@@ -29,6 +29,7 @@
 #include <asm/sysinfo.h>
 #include <asm/cpcmd.h>
 #include <asm/sclp.h>
+#include <asm/system.h>
 #include "entry.h"
 
 /*
@@ -262,25 +263,8 @@ static noinline __init void setup_lowcore_early(void)
 
 static noinline __init void setup_facility_list(void)
 {
-        unsigned long nr;
-
-        S390_lowcore.stfl_fac_list = 0;
-        asm volatile(
-                "       .insn   s,0xb2b10000,0(0)\n" /* stfl */
-                "0:\n"
-                EX_TABLE(0b,0b) : "=m" (S390_lowcore.stfl_fac_list));
-        memcpy(&S390_lowcore.stfle_fac_list, &S390_lowcore.stfl_fac_list, 4);
-        nr = 4;                         /* # bytes stored by stfl */
-        if (test_facility(7)) {
-                /* More facility bits available with stfle */
-                register unsigned long reg0 asm("0") = MAX_FACILITY_BIT/64 - 1;
-                asm volatile(".insn s,0xb2b00000,%0" /* stfle */
-                             : "=m" (S390_lowcore.stfle_fac_list), "+d" (reg0)
-                             : : "cc");
-                nr = (reg0 + 1) * 8;    /* # bytes stored by stfle */
-        }
-        memset((char *) S390_lowcore.stfle_fac_list + nr, 0,
-               MAX_FACILITY_BIT/8 - nr);
+        stfle(S390_lowcore.stfle_fac_list,
+              ARRAY_SIZE(S390_lowcore.stfle_fac_list));
 }
 
 static noinline __init void setup_hpage(void)
diff --git a/arch/s390/kernel/entry.S b/arch/s390/kernel/entry.S
index 3705700ed37..74ee563fe62 100644
--- a/arch/s390/kernel/entry.S
+++ b/arch/s390/kernel/entry.S
@@ -2,7 +2,7 @@
  *  arch/s390/kernel/entry.S
  *    S390 low-level entry points.
  *
- *    Copyright (C) IBM Corp. 1999,2006
+ *    Copyright (C) IBM Corp. 1999,2012
  *    Author(s): Martin Schwidefsky (schwidefsky@de.ibm.com),
  *               Hartmut Penner (hp@de.ibm.com),
  *               Denis Joseph Barrow (djbarrow@de.ibm.com,barrow_dj@yahoo.com),
@@ -105,14 +105,14 @@ STACK_SIZE  = 1 << STACK_SHIFT
 
         .macro  ADD64 high,low,timer
         al      \high,\timer
-        al      \low,\timer+4
+        al      \low,4+\timer
         brc     12,.+8
         ahi     \high,1
         .endm
 
         .macro  SUB64 high,low,timer
         sl      \high,\timer
-        sl      \low,\timer+4
+        sl      \low,4+\timer
         brc     3,.+8
         ahi     \high,-1
         .endm
@@ -471,7 +471,6 @@ io_tif:
         jnz     io_work                 # there is work to do (signals etc.)
 io_restore:
         mvc     __LC_RETURN_PSW(8),__PT_PSW(%r11)
-        ni      __LC_RETURN_PSW+1,0xfd  # clean wait state bit
         stpt    __LC_EXIT_TIMER
         lm      %r0,%r15,__PT_R0(%r11)
         lpsw    __LC_RETURN_PSW
@@ -606,12 +605,32 @@ ext_skip:
         stm     %r8,%r9,__PT_PSW(%r11)
         TRACE_IRQS_OFF
         lr      %r2,%r11                # pass pointer to pt_regs
-        l       %r3,__LC_CPU_ADDRESS    # get cpu address + interruption code
+        l       %r3,__LC_EXT_CPU_ADDR   # get cpu address + interruption code
         l       %r4,__LC_EXT_PARAMS     # get external parameters
         l       %r1,BASED(.Ldo_extint)
         basr    %r14,%r1                # call do_extint
         j       io_return
 
+/*
+ * Load idle PSW. The second "half" of this function is in cleanup_idle.
+ */
+ENTRY(psw_idle)
+        st      %r4,__SF_EMPTY(%r15)
+        basr    %r1,0
+        la      %r1,psw_idle_lpsw+4-.(%r1)
+        st      %r1,__SF_EMPTY+4(%r15)
+        oi      __SF_EMPTY+4(%r15),0x80
+        la      %r1,.Lvtimer_max-psw_idle_lpsw-4(%r1)
+        stck    __IDLE_ENTER(%r2)
+        ltr     %r5,%r5
+        stpt    __VQ_IDLE_ENTER(%r3)
+        jz      psw_idle_lpsw
+        spt     0(%r1)
+psw_idle_lpsw:
+        lpsw    __SF_EMPTY(%r15)
+        br      %r14
+psw_idle_end:
+
 __critical_end:
 
 /*
@@ -673,7 +692,6 @@ mcck_skip:
         TRACE_IRQS_ON
 mcck_return:
         mvc     __LC_RETURN_MCCK_PSW(8),__PT_PSW(%r11) # move return PSW
-        ni      __LC_RETURN_MCCK_PSW+1,0xfd # clear wait state bit
         tm      __LC_RETURN_MCCK_PSW+1,0x01 # returning to user ?
         jno     0f
         lm      %r0,%r15,__PT_R0(%r11)
@@ -691,77 +709,30 @@ mcck_panic:
 0:      ahi     %r15,-(STACK_FRAME_OVERHEAD + __PT_SIZE)
         j       mcck_skip
 
-/*
- * Restart interruption handler, kick starter for additional CPUs
- */
-#ifdef CONFIG_SMP
-        __CPUINIT
-ENTRY(restart_int_handler)
-        basr    %r1,0
-restart_base:
-        spt     restart_vtime-restart_base(%r1)
-        stck    __LC_LAST_UPDATE_CLOCK
-        mvc     __LC_LAST_UPDATE_TIMER(8),restart_vtime-restart_base(%r1)
-        mvc     __LC_EXIT_TIMER(8),restart_vtime-restart_base(%r1)
-        l       %r15,__LC_GPREGS_SAVE_AREA+60 # load ksp
-        lctl    %c0,%c15,__LC_CREGS_SAVE_AREA # get new ctl regs
-        lam     %a0,%a15,__LC_AREGS_SAVE_AREA
-        lm      %r6,%r15,__SF_GPRS(%r15)# load registers from clone
-        l       %r1,__LC_THREAD_INFO
-        mvc     __LC_USER_TIMER(8),__TI_user_timer(%r1)
-        mvc     __LC_SYSTEM_TIMER(8),__TI_system_timer(%r1)
-        xc      __LC_STEAL_TIMER(8),__LC_STEAL_TIMER
-        ssm     __LC_PGM_NEW_PSW        # turn dat on, keep irqs off
-        basr    %r14,0
-        l       %r14,restart_addr-.(%r14)
-        basr    %r14,%r14               # call start_secondary
-restart_addr:
-        .long   start_secondary
-        .align  8
-restart_vtime:
-        .long   0x7fffffff,0xffffffff
-        .previous
-#else
-/*
- * If we do not run with SMP enabled, let the new CPU crash ...
- */
-ENTRY(restart_int_handler)
-        basr    %r1,0
-restart_base:
-        lpsw    restart_crash-restart_base(%r1)
-        .align  8
-restart_crash:
-        .long   0x000a0000,0x00000000
-restart_go:
-#endif
-
 #
 # PSW restart interrupt handler
 #
-ENTRY(psw_restart_int_handler)
+ENTRY(restart_int_handler)
         st      %r15,__LC_SAVE_AREA_RESTART
-        basr    %r15,0
-0:      l       %r15,.Lrestart_stack-0b(%r15)   # load restart stack
-        l       %r15,0(%r15)
+        l       %r15,__LC_RESTART_STACK
         ahi     %r15,-__PT_SIZE                 # create pt_regs on stack
+        xc      0(__PT_SIZE,%r15),0(%r15)
         stm     %r0,%r14,__PT_R0(%r15)
         mvc     __PT_R15(4,%r15),__LC_SAVE_AREA_RESTART
         mvc     __PT_PSW(8,%r15),__LC_RST_OLD_PSW # store restart old psw
-        ahi     %r15,-STACK_FRAME_OVERHEAD
-        xc      __SF_BACKCHAIN(4,%r15),__SF_BACKCHAIN(%r15)
-        basr    %r14,0
-1:      l       %r14,.Ldo_restart-1b(%r14)
-        basr    %r14,%r14
-        basr    %r14,0                          # load disabled wait PSW if
-2:      lpsw    restart_psw_crash-2b(%r14)      # do_restart returns
-        .align 4
-.Ldo_restart:
-        .long   do_restart
-.Lrestart_stack:
-        .long   restart_stack
-        .align 8
-restart_psw_crash:
-        .long   0x000a0000,0x00000000 + restart_psw_crash
+        ahi     %r15,-STACK_FRAME_OVERHEAD      # create stack frame on stack
+        xc      0(STACK_FRAME_OVERHEAD,%r15),0(%r15)
+        lm      %r1,%r3,__LC_RESTART_FN         # load fn, parm & source cpu
+        ltr     %r3,%r3                         # test source cpu address
+        jm      1f                              # negative -> skip source stop
+0:      sigp    %r4,%r3,1                       # sigp sense to source cpu
+        brc     10,0b                           # wait for status stored
+1:      basr    %r14,%r1                        # call function
+        stap    __SF_EMPTY(%r15)                # store cpu address
+        lh      %r3,__SF_EMPTY(%r15)
+2:      sigp    %r4,%r3,5                       # sigp stop to current cpu
+        brc     2,2b
+3:      j       3b
 
         .section .kprobes.text, "ax"
 
@@ -795,6 +766,8 @@ cleanup_table:
         .long   io_tif + 0x80000000
         .long   io_restore + 0x80000000
         .long   io_done + 0x80000000
+        .long   psw_idle + 0x80000000
+        .long   psw_idle_end + 0x80000000
 
 cleanup_critical:
         cl      %r9,BASED(cleanup_table)        # system_call
@@ -813,6 +786,10 @@ cleanup_critical:
         jl      cleanup_io_tif
         cl      %r9,BASED(cleanup_table+28)     # io_done
         jl      cleanup_io_restore
+        cl      %r9,BASED(cleanup_table+32)     # psw_idle
+        jl      0f
+        cl      %r9,BASED(cleanup_table+36)     # psw_idle_end
+        jl      cleanup_idle
 0:      br      %r14
 
 cleanup_system_call:
@@ -896,7 +873,6 @@ cleanup_io_restore:
         jhe     0f
         l       %r9,12(%r11)            # get saved r11 pointer to pt_regs
         mvc     __LC_RETURN_PSW(8),__PT_PSW(%r9)
-        ni      __LC_RETURN_PSW+1,0xfd  # clear wait state bit
         mvc     0(32,%r11),__PT_R8(%r9)
         lm      %r0,%r7,__PT_R0(%r9)
 0:      lm      %r8,%r9,__LC_RETURN_PSW
@@ -904,11 +880,52 @@ cleanup_io_restore:
 cleanup_io_restore_insn:
         .long   io_done - 4 + 0x80000000
 
+cleanup_idle:
+        # copy interrupt clock & cpu timer
+        mvc     __IDLE_EXIT(8,%r2),__LC_INT_CLOCK
+        mvc     __VQ_IDLE_EXIT(8,%r3),__LC_ASYNC_ENTER_TIMER
+        chi     %r11,__LC_SAVE_AREA_ASYNC
+        je      0f
+        mvc     __IDLE_EXIT(8,%r2),__LC_MCCK_CLOCK
+        mvc     __VQ_IDLE_EXIT(8,%r3),__LC_MCCK_ENTER_TIMER
+0:      # check if stck has been executed
+        cl      %r9,BASED(cleanup_idle_insn)
+        jhe     1f
+        mvc     __IDLE_ENTER(8,%r2),__IDLE_EXIT(%r2)
+        mvc     __VQ_IDLE_ENTER(8,%r3),__VQ_IDLE_EXIT(%r3)
+        j       2f
+1:      # check if the cpu timer has been reprogrammed
+        ltr     %r5,%r5
+        jz      2f
+        spt     __VQ_IDLE_ENTER(%r3)
+2:      # account system time going idle
+        lm      %r9,%r10,__LC_STEAL_TIMER
+        ADD64   %r9,%r10,__IDLE_ENTER(%r2)
+        SUB64   %r9,%r10,__LC_LAST_UPDATE_CLOCK
+        stm     %r9,%r10,__LC_STEAL_TIMER
+        mvc     __LC_LAST_UPDATE_CLOCK(8),__IDLE_EXIT(%r2)
+        lm      %r9,%r10,__LC_SYSTEM_TIMER
+        ADD64   %r9,%r10,__LC_LAST_UPDATE_TIMER
+        SUB64   %r9,%r10,__VQ_IDLE_ENTER(%r3)
+        stm     %r9,%r10,__LC_SYSTEM_TIMER
+        mvc     __LC_LAST_UPDATE_TIMER(8),__VQ_IDLE_EXIT(%r3)
+        # prepare return psw
+        n       %r8,BASED(cleanup_idle_wait)    # clear wait state bit
+        l       %r9,24(%r11)                    # return from psw_idle
+        br      %r14
+cleanup_idle_insn:
+        .long   psw_idle_lpsw + 0x80000000
+cleanup_idle_wait:
+        .long   0xfffdffff
+
 /*
  * Integer constants
  */
         .align  4
-.Lnr_syscalls:          .long   NR_syscalls
+.Lnr_syscalls:
+        .long   NR_syscalls
+.Lvtimer_max:
+        .quad   0x7fffffffffffffff
 
 /*
  * Symbol constants
diff --git a/arch/s390/kernel/entry.h b/arch/s390/kernel/entry.h
index bf538aaf407..6cdddac93a2 100644
--- a/arch/s390/kernel/entry.h
+++ b/arch/s390/kernel/entry.h
@@ -4,11 +4,22 @@
 #include <linux/types.h>
 #include <linux/signal.h>
 #include <asm/ptrace.h>
-
+#include <asm/cputime.h>
+#include <asm/timer.h>
 
 extern void (*pgm_check_table[128])(struct pt_regs *);
 extern void *restart_stack;
 
+void system_call(void);
+void pgm_check_handler(void);
+void ext_int_handler(void);
+void io_int_handler(void);
+void mcck_int_handler(void);
+void restart_int_handler(void);
+void restart_call_handler(void);
+void psw_idle(struct s390_idle_data *, struct vtimer_queue *,
+              unsigned long, int);
+
 asmlinkage long do_syscall_trace_enter(struct pt_regs *regs);
 asmlinkage void do_syscall_trace_exit(struct pt_regs *regs);
 
@@ -24,9 +35,9 @@ int handle_signal32(unsigned long sig, struct k_sigaction *ka,
                     siginfo_t *info, sigset_t *oldset, struct pt_regs *regs);
 void do_notify_resume(struct pt_regs *regs);
 
-void do_extint(struct pt_regs *regs, unsigned int, unsigned int, unsigned long);
+struct ext_code;
+void do_extint(struct pt_regs *regs, struct ext_code, unsigned int, unsigned long);
 void do_restart(void);
-int __cpuinit start_secondary(void *cpuvoid);
 void __init startup_init(void);
 void die(struct pt_regs *regs, const char *str);
 
diff --git a/arch/s390/kernel/entry64.S b/arch/s390/kernel/entry64.S
index 412a7b8783d..4e1c292fa7e 100644
--- a/arch/s390/kernel/entry64.S
+++ b/arch/s390/kernel/entry64.S
@@ -2,7 +2,7 @@
  *  arch/s390/kernel/entry64.S
  *    S390 low-level entry points.
  *
- *    Copyright (C) IBM Corp. 1999,2010
+ *    Copyright (C) IBM Corp. 1999,2012
  *    Author(s): Martin Schwidefsky (schwidefsky@de.ibm.com),
  *               Hartmut Penner (hp@de.ibm.com),
  *               Denis Joseph Barrow (djbarrow@de.ibm.com,barrow_dj@yahoo.com),
@@ -489,7 +489,6 @@ io_restore:
         lg      %r14,__LC_VDSO_PER_CPU
         lmg     %r0,%r10,__PT_R0(%r11)
         mvc     __LC_RETURN_PSW(16),__PT_PSW(%r11)
-        ni      __LC_RETURN_PSW+1,0xfd  # clear wait state bit
         stpt    __LC_EXIT_TIMER
         mvc     __VDSO_ECTG_BASE(16,%r14),__LC_EXIT_TIMER
         lmg     %r11,%r15,__PT_R11(%r11)
@@ -625,12 +624,30 @@ ext_skip:
         TRACE_IRQS_OFF
         lghi    %r1,4096
         lgr     %r2,%r11                # pass pointer to pt_regs
-        llgf    %r3,__LC_CPU_ADDRESS    # get cpu address + interruption code
+        llgf    %r3,__LC_EXT_CPU_ADDR   # get cpu address + interruption code
         llgf    %r4,__LC_EXT_PARAMS     # get external parameter
         lg      %r5,__LC_EXT_PARAMS2-4096(%r1)  # get 64 bit external parameter
         brasl   %r14,do_extint
         j       io_return
 
+/*
+ * Load idle PSW. The second "half" of this function is in cleanup_idle.
+ */
+ENTRY(psw_idle)
+        stg     %r4,__SF_EMPTY(%r15)
+        larl    %r1,psw_idle_lpsw+4
+        stg     %r1,__SF_EMPTY+8(%r15)
+        larl    %r1,.Lvtimer_max
+        stck    __IDLE_ENTER(%r2)
+        ltr     %r5,%r5
+        stpt    __VQ_IDLE_ENTER(%r3)
+        jz      psw_idle_lpsw
+        spt     0(%r1)
+psw_idle_lpsw:
+        lpswe   __SF_EMPTY(%r15)
+        br      %r14
+psw_idle_end:
+
 __critical_end:
 
 /*
@@ -696,7 +713,6 @@ mcck_return:
         lg      %r14,__LC_VDSO_PER_CPU
         lmg     %r0,%r10,__PT_R0(%r11)
         mvc     __LC_RETURN_MCCK_PSW(16),__PT_PSW(%r11) # move return PSW
-        ni      __LC_RETURN_MCCK_PSW+1,0xfd # clear wait state bit
         tm      __LC_RETURN_MCCK_PSW+1,0x01 # returning to user ?
         jno     0f
         stpt    __LC_EXIT_TIMER
@@ -713,68 +729,30 @@ mcck_panic:
 0:      aghi    %r15,-(STACK_FRAME_OVERHEAD + __PT_SIZE)
         j       mcck_skip
 
-/*
- * Restart interruption handler, kick starter for additional CPUs
- */
-#ifdef CONFIG_SMP
-        __CPUINIT
-ENTRY(restart_int_handler)
-        basr    %r1,0
-restart_base:
-        spt     restart_vtime-restart_base(%r1)
-        stck    __LC_LAST_UPDATE_CLOCK
-        mvc     __LC_LAST_UPDATE_TIMER(8),restart_vtime-restart_base(%r1)
-        mvc     __LC_EXIT_TIMER(8),restart_vtime-restart_base(%r1)
-        lghi    %r10,__LC_GPREGS_SAVE_AREA
-        lg      %r15,120(%r10)          # load ksp
-        lghi    %r10,__LC_CREGS_SAVE_AREA
-        lctlg   %c0,%c15,0(%r10)        # get new ctl regs
-        lghi    %r10,__LC_AREGS_SAVE_AREA
-        lam     %a0,%a15,0(%r10)
-        lmg     %r6,%r15,__SF_GPRS(%r15)# load registers from clone
-        lg      %r1,__LC_THREAD_INFO
-        mvc     __LC_USER_TIMER(8),__TI_user_timer(%r1)
-        mvc     __LC_SYSTEM_TIMER(8),__TI_system_timer(%r1)
-        xc      __LC_STEAL_TIMER(8),__LC_STEAL_TIMER
-        ssm     __LC_PGM_NEW_PSW        # turn dat on, keep irqs off
-        brasl   %r14,start_secondary
-        .align  8
-restart_vtime:
-        .long   0x7fffffff,0xffffffff
-        .previous
-#else
-/*
- * If we do not run with SMP enabled, let the new CPU crash ...
- */
-ENTRY(restart_int_handler)
-        basr    %r1,0
-restart_base:
-        lpswe   restart_crash-restart_base(%r1)
-        .align 8
-restart_crash:
-        .long  0x000a0000,0x00000000,0x00000000,0x00000000
-restart_go:
-#endif
-
 #
 # PSW restart interrupt handler
 #
-ENTRY(psw_restart_int_handler)
+ENTRY(restart_int_handler)
         stg     %r15,__LC_SAVE_AREA_RESTART
-        larl    %r15,restart_stack              # load restart stack
-        lg      %r15,0(%r15)
+        lg      %r15,__LC_RESTART_STACK
         aghi    %r15,-__PT_SIZE                 # create pt_regs on stack
+        xc      0(__PT_SIZE,%r15),0(%r15)
         stmg    %r0,%r14,__PT_R0(%r15)
         mvc     __PT_R15(8,%r15),__LC_SAVE_AREA_RESTART
         mvc     __PT_PSW(16,%r15),__LC_RST_OLD_PSW # store restart old psw
-        aghi    %r15,-STACK_FRAME_OVERHEAD
-        xc      __SF_BACKCHAIN(8,%r15),__SF_BACKCHAIN(%r15)
-        brasl   %r14,do_restart
-        larl    %r14,restart_psw_crash          # load disabled wait PSW if
-        lpswe   0(%r14)                         # do_restart returns
-        .align 8
-restart_psw_crash:
-        .quad   0x0002000080000000,0x0000000000000000 + restart_psw_crash
+        aghi    %r15,-STACK_FRAME_OVERHEAD      # create stack frame on stack
+        xc      0(STACK_FRAME_OVERHEAD,%r15),0(%r15)
+        lmg     %r1,%r3,__LC_RESTART_FN         # load fn, parm & source cpu
+        ltgr    %r3,%r3                         # test source cpu address
+        jm      1f                              # negative -> skip source stop
+0:      sigp    %r4,%r3,1                       # sigp sense to source cpu
+        brc     10,0b                           # wait for status stored
+1:      basr    %r14,%r1                        # call function
+        stap    __SF_EMPTY(%r15)                # store cpu address
+        llgh    %r3,__SF_EMPTY(%r15)
+2:      sigp    %r4,%r3,5                       # sigp stop to current cpu
+        brc     2,2b
+3:      j       3b
 
         .section .kprobes.text, "ax"
 
@@ -808,6 +786,8 @@ cleanup_table:
         .quad   io_tif
         .quad   io_restore
         .quad   io_done
+        .quad   psw_idle
+        .quad   psw_idle_end
 
 cleanup_critical:
         clg     %r9,BASED(cleanup_table)        # system_call
@@ -826,6 +806,10 @@ cleanup_critical:
         jl      cleanup_io_tif
         clg     %r9,BASED(cleanup_table+56)     # io_done
         jl      cleanup_io_restore
+        clg     %r9,BASED(cleanup_table+64)     # psw_idle
+        jl      0f
+        clg     %r9,BASED(cleanup_table+72)     # psw_idle_end
+        jl      cleanup_idle
 0:      br      %r14
 
 
@@ -915,7 +899,6 @@ cleanup_io_restore:
         je      0f
         lg      %r9,24(%r11)            # get saved r11 pointer to pt_regs
         mvc     __LC_RETURN_PSW(16),__PT_PSW(%r9)
-        ni      __LC_RETURN_PSW+1,0xfd  # clear wait state bit
         mvc     0(64,%r11),__PT_R8(%r9)
         lmg     %r0,%r7,__PT_R0(%r9)
 0:      lmg     %r8,%r9,__LC_RETURN_PSW
@@ -923,6 +906,42 @@ cleanup_io_restore:
 cleanup_io_restore_insn:
         .quad   io_done - 4
 
+cleanup_idle:
+        # copy interrupt clock & cpu timer
+        mvc     __IDLE_EXIT(8,%r2),__LC_INT_CLOCK
+        mvc     __VQ_IDLE_EXIT(8,%r3),__LC_ASYNC_ENTER_TIMER
+        cghi    %r11,__LC_SAVE_AREA_ASYNC
+        je      0f
+        mvc     __IDLE_EXIT(8,%r2),__LC_MCCK_CLOCK
+        mvc     __VQ_IDLE_EXIT(8,%r3),__LC_MCCK_ENTER_TIMER
+0:      # check if stck & stpt have been executed
+        clg     %r9,BASED(cleanup_idle_insn)
+        jhe     1f
+        mvc     __IDLE_ENTER(8,%r2),__IDLE_EXIT(%r2)
+        mvc     __VQ_IDLE_ENTER(8,%r3),__VQ_IDLE_EXIT(%r3)
+        j       2f
+1:      # check if the cpu timer has been reprogrammed
+        ltr     %r5,%r5
+        jz      2f
+        spt     __VQ_IDLE_ENTER(%r3)
+2:      # account system time going idle
+        lg      %r9,__LC_STEAL_TIMER
+        alg     %r9,__IDLE_ENTER(%r2)
+        slg     %r9,__LC_LAST_UPDATE_CLOCK
+        stg     %r9,__LC_STEAL_TIMER
+        mvc     __LC_LAST_UPDATE_CLOCK(8),__IDLE_EXIT(%r2)
+        lg      %r9,__LC_SYSTEM_TIMER
+        alg     %r9,__LC_LAST_UPDATE_TIMER
+        slg     %r9,__VQ_IDLE_ENTER(%r3)
+        stg     %r9,__LC_SYSTEM_TIMER
+        mvc     __LC_LAST_UPDATE_TIMER(8),__VQ_IDLE_EXIT(%r3)
+        # prepare return psw
+        nihh    %r8,0xfffd              # clear wait state bit
+        lg      %r9,48(%r11)            # return from psw_idle
+        br      %r14
+cleanup_idle_insn:
+        .quad   psw_idle_lpsw
+
 /*
  * Integer constants
  */
@@ -931,6 +950,8 @@ cleanup_io_restore_insn:
         .quad   __critical_start
 .Lcritical_length:
         .quad   __critical_end - __critical_start
+.Lvtimer_max:
+        .quad   0x7fffffffffffffff
 
 
 #if defined(CONFIG_KVM) || defined(CONFIG_KVM_MODULE)
diff --git a/arch/s390/kernel/ipl.c b/arch/s390/kernel/ipl.c
index affa8e68124..8342e65a140 100644
--- a/arch/s390/kernel/ipl.c
+++ b/arch/s390/kernel/ipl.c
@@ -2,7 +2,7 @@
  *  arch/s390/kernel/ipl.c
  *    ipl/reipl/dump support for Linux on s390.
  *
- *    Copyright IBM Corp. 2005,2007
+ *    Copyright IBM Corp. 2005,2012
  *    Author(s): Michael Holzheu <holzheu@de.ibm.com>
  *               Heiko Carstens <heiko.carstens@de.ibm.com>
  *               Volker Sameske <sameske@de.ibm.com>
@@ -17,6 +17,7 @@
 #include <linux/fs.h>
 #include <linux/gfp.h>
 #include <linux/crash_dump.h>
+#include <linux/debug_locks.h>
 #include <asm/ipl.h>
 #include <asm/smp.h>
 #include <asm/setup.h>
@@ -25,8 +26,9 @@
 #include <asm/ebcdic.h>
 #include <asm/reset.h>
 #include <asm/sclp.h>
-#include <asm/sigp.h>
 #include <asm/checksum.h>
+#include <asm/debug.h>
+#include <asm/os_info.h>
 #include "entry.h"
 
 #define IPL_PARM_BLOCK_VERSION 0
@@ -571,7 +573,7 @@ static void __ipl_run(void *unused)
 
 static void ipl_run(struct shutdown_trigger *trigger)
 {
-        smp_switch_to_ipl_cpu(__ipl_run, NULL);
+        smp_call_ipl_cpu(__ipl_run, NULL);
 }
 
 static int __init ipl_init(void)
@@ -950,6 +952,13 @@ static struct attribute_group reipl_nss_attr_group = {
         .attrs = reipl_nss_attrs,
 };
 
+static void set_reipl_block_actual(struct ipl_parameter_block *reipl_block)
+{
+        reipl_block_actual = reipl_block;
+        os_info_entry_add(OS_INFO_REIPL_BLOCK, reipl_block_actual,
+                          reipl_block->hdr.len);
+}
+
 /* reipl type */
 
 static int reipl_set_type(enum ipl_type type)
@@ -965,7 +974,7 @@ static int reipl_set_type(enum ipl_type type)
                         reipl_method = REIPL_METHOD_CCW_VM;
                 else
                         reipl_method = REIPL_METHOD_CCW_CIO;
-                reipl_block_actual = reipl_block_ccw;
+                set_reipl_block_actual(reipl_block_ccw);
                 break;
         case IPL_TYPE_FCP:
                 if (diag308_set_works)
@@ -974,7 +983,7 @@ static int reipl_set_type(enum ipl_type type)
                         reipl_method = REIPL_METHOD_FCP_RO_VM;
                 else
                         reipl_method = REIPL_METHOD_FCP_RO_DIAG;
-                reipl_block_actual = reipl_block_fcp;
+                set_reipl_block_actual(reipl_block_fcp);
                 break;
         case IPL_TYPE_FCP_DUMP:
                 reipl_method = REIPL_METHOD_FCP_DUMP;
@@ -984,7 +993,7 @@ static int reipl_set_type(enum ipl_type type)
                         reipl_method = REIPL_METHOD_NSS_DIAG;
                 else
                         reipl_method = REIPL_METHOD_NSS;
-                reipl_block_actual = reipl_block_nss;
+                set_reipl_block_actual(reipl_block_nss);
                 break;
         case IPL_TYPE_UNKNOWN:
                 reipl_method = REIPL_METHOD_DEFAULT;
@@ -1101,7 +1110,7 @@ static void __reipl_run(void *unused)
 
 static void reipl_run(struct shutdown_trigger *trigger)
 {
-        smp_switch_to_ipl_cpu(__reipl_run, NULL);
+        smp_call_ipl_cpu(__reipl_run, NULL);
 }
 
 static void reipl_block_ccw_init(struct ipl_parameter_block *ipb)
@@ -1256,6 +1265,29 @@ static int __init reipl_fcp_init(void)
         return 0;
 }
 
+static int __init reipl_type_init(void)
+{
+        enum ipl_type reipl_type = ipl_info.type;
+        struct ipl_parameter_block *reipl_block;
+        unsigned long size;
+
+        reipl_block = os_info_old_entry(OS_INFO_REIPL_BLOCK, &size);
+        if (!reipl_block)
+                goto out;
+        /*
+         * If we have an OS info reipl block, this will be used
+         */
+        if (reipl_block->hdr.pbt == DIAG308_IPL_TYPE_FCP) {
+                memcpy(reipl_block_fcp, reipl_block, size);
+                reipl_type = IPL_TYPE_FCP;
+        } else if (reipl_block->hdr.pbt == DIAG308_IPL_TYPE_CCW) {
+                memcpy(reipl_block_ccw, reipl_block, size);
+                reipl_type = IPL_TYPE_CCW;
+        }
+out:
+        return reipl_set_type(reipl_type);
+}
+
 static int __init reipl_init(void)
 {
         int rc;
@@ -1277,10 +1309,7 @@ static int __init reipl_init(void)
         rc = reipl_nss_init();
         if (rc)
                 return rc;
-        rc = reipl_set_type(ipl_info.type);
-        if (rc)
-                return rc;
-        return 0;
+        return reipl_type_init();
 }
 
 static struct shutdown_action __refdata reipl_action = {
@@ -1421,7 +1450,7 @@ static void dump_run(struct shutdown_trigger *trigger)
         if (dump_method == DUMP_METHOD_NONE)
                 return;
         smp_send_stop();
-        smp_switch_to_ipl_cpu(__dump_run, NULL);
+        smp_call_ipl_cpu(__dump_run, NULL);
 }
 
 static int __init dump_ccw_init(void)
@@ -1499,30 +1528,12 @@ static struct shutdown_action __refdata dump_action = {
 
 static void dump_reipl_run(struct shutdown_trigger *trigger)
 {
-        preempt_disable();
-        /*
-         * Bypass dynamic address translation (DAT) when storing IPL parameter
-         * information block address and checksum into the prefix area
-         * (corresponding to absolute addresses 0-8191).
-         * When enhanced DAT applies and the STE format control in one,
-         * the absolute address is formed without prefixing. In this case a
-         * normal store (stg/st) into the prefix area would no more match to
-         * absolute addresses 0-8191.
-         */
-#ifdef CONFIG_64BIT
-        asm volatile("sturg %0,%1"
-                :: "a" ((unsigned long) reipl_block_actual),
-                "a" (&lowcore_ptr[smp_processor_id()]->ipib));
-#else
-        asm volatile("stura %0,%1"
-                :: "a" ((unsigned long) reipl_block_actual),
-                "a" (&lowcore_ptr[smp_processor_id()]->ipib));
-#endif
-        asm volatile("stura %0,%1"
-                :: "a" (csum_partial(reipl_block_actual,
-                                     reipl_block_actual->hdr.len, 0)),
-                "a" (&lowcore_ptr[smp_processor_id()]->ipib_checksum));
-        preempt_enable();
+        u32 csum;
+
+        csum = csum_partial(reipl_block_actual, reipl_block_actual->hdr.len, 0);
+        copy_to_absolute_zero(&S390_lowcore.ipib_checksum, &csum, sizeof(csum));
+        copy_to_absolute_zero(&S390_lowcore.ipib, &reipl_block_actual,
+                              sizeof(reipl_block_actual));
         dump_run(trigger);
 }
 
@@ -1623,9 +1634,7 @@ static void stop_run(struct shutdown_trigger *trigger)
         if (strcmp(trigger->name, ON_PANIC_STR) == 0 ||
             strcmp(trigger->name, ON_RESTART_STR) == 0)
                 disabled_wait((unsigned long) __builtin_return_address(0));
-        while (sigp(smp_processor_id(), sigp_stop) == sigp_busy)
-                cpu_relax();
-        for (;;);
+        smp_stop_cpu();
 }
 
 static struct shutdown_action stop_action = {SHUTDOWN_ACTION_STOP_STR,
@@ -1713,6 +1722,7 @@ static struct kobj_attribute on_panic_attr =
 
 static void do_panic(void)
 {
+        lgr_info_log();
         on_panic_trigger.action->fn(&on_panic_trigger);
         stop_run(&on_panic_trigger);
 }
@@ -1738,9 +1748,8 @@ static ssize_t on_restart_store(struct kobject *kobj,
 static struct kobj_attribute on_restart_attr =
         __ATTR(on_restart, 0644, on_restart_show, on_restart_store);
 
-void do_restart(void)
+static void __do_restart(void *ignore)
 {
-        smp_restart_with_online_cpu();
         smp_send_stop();
 #ifdef CONFIG_CRASH_DUMP
         crash_kexec(NULL);
@@ -1749,6 +1758,14 @@ void do_restart(void)
         stop_run(&on_restart_trigger);
 }
 
+void do_restart(void)
+{
+        tracing_off();
+        debug_locks_off();
+        lgr_info_log();
+        smp_call_online_cpu(__do_restart, NULL);
+}
+
 /* on halt */
 
 static struct shutdown_trigger on_halt_trigger = {ON_HALT_STR, &stop_action};
diff --git a/arch/s390/kernel/irq.c b/arch/s390/kernel/irq.c
index e30b2dfa8ba..2429ecd6887 100644
--- a/arch/s390/kernel/irq.c
+++ b/arch/s390/kernel/irq.c
@@ -202,31 +202,27 @@ int unregister_external_interrupt(u16 code, ext_int_handler_t handler)
 }
 EXPORT_SYMBOL(unregister_external_interrupt);
 
-void __irq_entry do_extint(struct pt_regs *regs, unsigned int ext_int_code,
+void __irq_entry do_extint(struct pt_regs *regs, struct ext_code ext_code,
                            unsigned int param32, unsigned long param64)
 {
         struct pt_regs *old_regs;
-        unsigned short code;
         struct ext_int_info *p;
         int index;
 
-        code = (unsigned short) ext_int_code;
         old_regs = set_irq_regs(regs);
-        s390_idle_check(regs, S390_lowcore.int_clock,
-                        S390_lowcore.async_enter_timer);
         irq_enter();
         if (S390_lowcore.int_clock >= S390_lowcore.clock_comparator)
                 /* Serve timer interrupts first. */
                 clock_comparator_work();
         kstat_cpu(smp_processor_id()).irqs[EXTERNAL_INTERRUPT]++;
-        if (code != 0x1004)
+        if (ext_code.code != 0x1004)
                 __get_cpu_var(s390_idle).nohz_delay = 1;
 
-        index = ext_hash(code);
+        index = ext_hash(ext_code.code);
         rcu_read_lock();
         list_for_each_entry_rcu(p, &ext_int_hash[index], entry)
-                if (likely(p->code == code))
-                        p->handler(ext_int_code, param32, param64);
+                if (likely(p->code == ext_code.code))
+                        p->handler(ext_code, param32, param64);
         rcu_read_unlock();
         irq_exit();
         set_irq_regs(old_regs);
diff --git a/arch/s390/kernel/lgr.c b/arch/s390/kernel/lgr.c
new file mode 100644
index 00000000000..8431b92ca3a
--- /dev/null
+++ b/arch/s390/kernel/lgr.c
@@ -0,0 +1,200 @@
+/*
+ * Linux Guest Relocation (LGR) detection
+ *
+ * Copyright IBM Corp. 2012
+ * Author(s): Michael Holzheu <holzheu@linux.vnet.ibm.com>
+ */
+
+#include <linux/module.h>
+#include <linux/timer.h>
+#include <linux/slab.h>
+#include <asm/sysinfo.h>
+#include <asm/ebcdic.h>
+#include <asm/system.h>
+#include <asm/debug.h>
+#include <asm/ipl.h>
+
+#define LGR_TIMER_INTERVAL_SECS (30 * 60)
+#define VM_LEVEL_MAX 2 /* Maximum is 8, but we only record two levels */
+
+/*
+ * LGR info: Contains stfle and stsi data
+ */
+struct lgr_info {
+        /* Bit field with facility information: 4 DWORDs are stored */
+        u64 stfle_fac_list[4];
+        /* Level of system (1 = CEC, 2 = LPAR, 3 = z/VM */
+        u32 level;
+        /* Level 1: CEC info (stsi 1.1.1) */
+        char manufacturer[16];
+        char type[4];
+        char sequence[16];
+        char plant[4];
+        char model[16];
+        /* Level 2: LPAR info (stsi 2.2.2) */
+        u16 lpar_number;
+        char name[8];
+        /* Level 3: VM info (stsi 3.2.2) */
+        u8 vm_count;
+        struct {
+                char name[8];
+                char cpi[16];
+        } vm[VM_LEVEL_MAX];
+} __packed __aligned(8);
+
+/*
+ * LGR globals
+ */
+static void *lgr_page;
+static struct lgr_info lgr_info_last;
+static struct lgr_info lgr_info_cur;
+static struct debug_info *lgr_dbf;
+
+/*
+ * Return number of valid stsi levels
+ */
+static inline int stsi_0(void)
+{
+        int rc = stsi(NULL, 0, 0, 0);
+
+        return rc == -ENOSYS ? rc : (((unsigned int) rc) >> 28);
+}
+
+/*
+ * Copy buffer and then convert it to ASCII
+ */
+static void cpascii(char *dst, char *src, int size)
+{
+        memcpy(dst, src, size);
+        EBCASC(dst, size);
+}
+
+/*
+ * Fill LGR info with 1.1.1 stsi data
+ */
+static void lgr_stsi_1_1_1(struct lgr_info *lgr_info)
+{
+        struct sysinfo_1_1_1 *si = lgr_page;
+
+        if (stsi(si, 1, 1, 1) == -ENOSYS)
+                return;
+        cpascii(lgr_info->manufacturer, si->manufacturer,
+                sizeof(si->manufacturer));
+        cpascii(lgr_info->type, si->type, sizeof(si->type));
+        cpascii(lgr_info->model, si->model, sizeof(si->model));
+        cpascii(lgr_info->sequence, si->sequence, sizeof(si->sequence));
+        cpascii(lgr_info->plant, si->plant, sizeof(si->plant));
+}
+
+/*
+ * Fill LGR info with 2.2.2 stsi data
+ */
+static void lgr_stsi_2_2_2(struct lgr_info *lgr_info)
+{
+        struct sysinfo_2_2_2 *si = lgr_page;
+
+        if (stsi(si, 2, 2, 2) == -ENOSYS)
+                return;
+        cpascii(lgr_info->name, si->name, sizeof(si->name));
+        memcpy(&lgr_info->lpar_number, &si->lpar_number,
+               sizeof(lgr_info->lpar_number));
+}
+
+/*
+ * Fill LGR info with 3.2.2 stsi data
+ */
+static void lgr_stsi_3_2_2(struct lgr_info *lgr_info)
+{
+        struct sysinfo_3_2_2 *si = lgr_page;
+        int i;
+
+        if (stsi(si, 3, 2, 2) == -ENOSYS)
+                return;
+        for (i = 0; i < min_t(u8, si->count, VM_LEVEL_MAX); i++) {
+                cpascii(lgr_info->vm[i].name, si->vm[i].name,
+                        sizeof(si->vm[i].name));
+                cpascii(lgr_info->vm[i].cpi, si->vm[i].cpi,
+                        sizeof(si->vm[i].cpi));
+        }
+        lgr_info->vm_count = si->count;
+}
+
+/*
+ * Fill LGR info with current data
+ */
+static void lgr_info_get(struct lgr_info *lgr_info)
+{
+        memset(lgr_info, 0, sizeof(*lgr_info));
+        stfle(lgr_info->stfle_fac_list, ARRAY_SIZE(lgr_info->stfle_fac_list));
+        lgr_info->level = stsi_0();
+        if (lgr_info->level == -ENOSYS)
+                return;
+        if (lgr_info->level >= 1)
+                lgr_stsi_1_1_1(lgr_info);
+        if (lgr_info->level >= 2)
+                lgr_stsi_2_2_2(lgr_info);
+        if (lgr_info->level >= 3)
+                lgr_stsi_3_2_2(lgr_info);
+}
+
+/*
+ * Check if LGR info has changed and if yes log new LGR info to s390dbf
+ */
+void lgr_info_log(void)
+{
+        static DEFINE_SPINLOCK(lgr_info_lock);
+        unsigned long flags;
+
+        if (!spin_trylock_irqsave(&lgr_info_lock, flags))
+                return;
+        lgr_info_get(&lgr_info_cur);
+        if (memcmp(&lgr_info_last, &lgr_info_cur, sizeof(lgr_info_cur)) != 0) {
+                debug_event(lgr_dbf, 1, &lgr_info_cur, sizeof(lgr_info_cur));
+                lgr_info_last = lgr_info_cur;
+        }
+        spin_unlock_irqrestore(&lgr_info_lock, flags);
+}
+EXPORT_SYMBOL_GPL(lgr_info_log);
+
+static void lgr_timer_set(void);
+
+/*
+ * LGR timer callback
+ */
+static void lgr_timer_fn(unsigned long ignored)
+{
+        lgr_info_log();
+        lgr_timer_set();
+}
+
+static struct timer_list lgr_timer =
+        TIMER_DEFERRED_INITIALIZER(lgr_timer_fn, 0, 0);
+
+/*
+ * Setup next LGR timer
+ */
+static void lgr_timer_set(void)
+{
+        mod_timer(&lgr_timer, jiffies + LGR_TIMER_INTERVAL_SECS * HZ);
+}
+
+/*
+ * Initialize LGR: Add s390dbf, write initial lgr_info and setup timer
+ */
+static int __init lgr_init(void)
+{
+        lgr_page = (void *) __get_free_pages(GFP_KERNEL, 0);
+        if (!lgr_page)
+                return -ENOMEM;
+        lgr_dbf = debug_register("lgr", 1, 1, sizeof(struct lgr_info));
+        if (!lgr_dbf) {
+                free_page((unsigned long) lgr_page);
+                return -ENOMEM;
+        }
+        debug_register_view(lgr_dbf, &debug_hex_ascii_view);
+        lgr_info_get(&lgr_info_last);
+        debug_event(lgr_dbf, 1, &lgr_info_last, sizeof(lgr_info_last));
+        lgr_timer_set();
+        return 0;
+}
+module_init(lgr_init);
diff --git a/arch/s390/kernel/machine_kexec.c b/arch/s390/kernel/machine_kexec.c
index 47b168fb29c..0f8cdf1268d 100644
--- a/arch/s390/kernel/machine_kexec.c
+++ b/arch/s390/kernel/machine_kexec.c
@@ -14,6 +14,7 @@
 #include <linux/delay.h>
 #include <linux/reboot.h>
 #include <linux/ftrace.h>
+#include <linux/debug_locks.h>
 #include <asm/cio.h>
 #include <asm/setup.h>
 #include <asm/pgtable.h>
@@ -49,50 +50,21 @@ static void add_elf_notes(int cpu)
 }
 
 /*
- * Store status of next available physical CPU
- */
-static int store_status_next(int start_cpu, int this_cpu)
-{
-        struct save_area *sa = (void *) 4608 + store_prefix();
-        int cpu, rc;
-
-        for (cpu = start_cpu; cpu < 65536; cpu++) {
-                if (cpu == this_cpu)
-                        continue;
-                do {
-                        rc = raw_sigp(cpu, sigp_stop_and_store_status);
-                } while (rc == sigp_busy);
-                if (rc != sigp_order_code_accepted)
-                        continue;
-                if (sa->pref_reg)
-                        return cpu;
-        }
-        return -1;
-}
-
-/*
  * Initialize CPU ELF notes
  */
 void setup_regs(void)
 {
         unsigned long sa = S390_lowcore.prefixreg_save_area + SAVE_AREA_BASE;
-        int cpu, this_cpu, phys_cpu = 0, first = 1;
+        int cpu, this_cpu;
 
-        this_cpu = stap();
-
-        if (!S390_lowcore.prefixreg_save_area)
-                first = 0;
+        this_cpu = smp_find_processor_id(stap());
+        add_elf_notes(this_cpu);
         for_each_online_cpu(cpu) {
-                if (first) {
-                        add_elf_notes(cpu);
-                        first = 0;
+                if (cpu == this_cpu)
+                        continue;
+                if (smp_store_status(cpu))
                         continue;
-                }
-                phys_cpu = store_status_next(phys_cpu, this_cpu);
-                if (phys_cpu == -1)
-                        break;
                 add_elf_notes(cpu);
-                phys_cpu++;
         }
         /* Copy dump CPU store status info to absolute zero */
         memcpy((void *) SAVE_AREA_BASE, (void *) sa, sizeof(struct save_area));
@@ -238,10 +210,14 @@ static void __machine_kexec(void *data)
         struct kimage *image = data;
 
         pfault_fini();
-        if (image->type == KEXEC_TYPE_CRASH)
+        tracing_off();
+        debug_locks_off();
+        if (image->type == KEXEC_TYPE_CRASH) {
+                lgr_info_log();
                 s390_reset_system(__do_machine_kdump, data);
-        else
+        } else {
                 s390_reset_system(__do_machine_kexec, data);
+        }
         disabled_wait((unsigned long) __builtin_return_address(0));
 }
 
@@ -255,5 +231,5 @@ void machine_kexec(struct kimage *image)
                 return;
         tracer_disable();
         smp_send_stop();
-        smp_switch_to_ipl_cpu(__machine_kexec, image);
+        smp_call_ipl_cpu(__machine_kexec, image);
 }
diff --git a/arch/s390/kernel/nmi.c b/arch/s390/kernel/nmi.c
index 0fd2e863e11..8c372ca6135 100644
--- a/arch/s390/kernel/nmi.c
+++ b/arch/s390/kernel/nmi.c
@@ -254,8 +254,6 @@ void notrace s390_do_machine_check(struct pt_regs *regs)
         int umode;
 
         nmi_enter();
-        s390_idle_check(regs, S390_lowcore.mcck_clock,
-                        S390_lowcore.mcck_enter_timer);
         kstat_cpu(smp_processor_id()).irqs[NMI_NMI]++;
         mci = (struct mci *) &S390_lowcore.mcck_interruption_code;
         mcck = &__get_cpu_var(cpu_mcck);
diff --git a/arch/s390/kernel/os_info.c b/arch/s390/kernel/os_info.c
new file mode 100644
index 00000000000..bbe522672e0
--- /dev/null
+++ b/arch/s390/kernel/os_info.c
@@ -0,0 +1,169 @@
+/*
+ * OS info memory interface
+ *
+ * Copyright IBM Corp. 2012
+ * Author(s): Michael Holzheu <holzheu@linux.vnet.ibm.com>
+ */
+
+#define KMSG_COMPONENT "os_info"
+#define pr_fmt(fmt) KMSG_COMPONENT ": " fmt
+
+#include <linux/crash_dump.h>
+#include <linux/kernel.h>
+#include <asm/checksum.h>
+#include <asm/lowcore.h>
+#include <asm/system.h>
+#include <asm/os_info.h>
+
+/*
+ * OS info structure has to be page aligned
+ */
+static struct os_info os_info __page_aligned_data;
+
+/*
+ * Compute checksum over OS info structure
+ */
+u32 os_info_csum(struct os_info *os_info)
+{
+        int size = sizeof(*os_info) - offsetof(struct os_info, version_major);
+        return csum_partial(&os_info->version_major, size, 0);
+}
+
+/*
+ * Add crashkernel info to OS info and update checksum
+ */
+void os_info_crashkernel_add(unsigned long base, unsigned long size)
+{
+        os_info.crashkernel_addr = (u64)(unsigned long)base;
+        os_info.crashkernel_size = (u64)(unsigned long)size;
+        os_info.csum = os_info_csum(&os_info);
+}
+
+/*
+ * Add OS info entry and update checksum
+ */
+void os_info_entry_add(int nr, void *ptr, u64 size)
+{
+        os_info.entry[nr].addr = (u64)(unsigned long)ptr;
+        os_info.entry[nr].size = size;
+        os_info.entry[nr].csum = csum_partial(ptr, size, 0);
+        os_info.csum = os_info_csum(&os_info);
+}
+
+/*
+ * Initialize OS info struture and set lowcore pointer
+ */
+void __init os_info_init(void)
+{
+        void *ptr = &os_info;
+
+        os_info.version_major = OS_INFO_VERSION_MAJOR;
+        os_info.version_minor = OS_INFO_VERSION_MINOR;
+        os_info.magic = OS_INFO_MAGIC;
+        os_info.csum = os_info_csum(&os_info);
+        copy_to_absolute_zero(&S390_lowcore.os_info, &ptr, sizeof(ptr));
+}
+
+#ifdef CONFIG_CRASH_DUMP
+
+static struct os_info *os_info_old;
+
+/*
+ * Allocate and copy OS info entry from oldmem
+ */
+static void os_info_old_alloc(int nr, int align)
+{
+        unsigned long addr, size = 0;
+        char *buf, *buf_align, *msg;
+        u32 csum;
+
+        addr = os_info_old->entry[nr].addr;
+        if (!addr) {
+                msg = "not available";
+                goto fail;
+        }
+        size = os_info_old->entry[nr].size;
+        buf = kmalloc(size + align - 1, GFP_KERNEL);
+        if (!buf) {
+                msg = "alloc failed";
+                goto fail;
+        }
+        buf_align = PTR_ALIGN(buf, align);
+        if (copy_from_oldmem(buf_align, (void *) addr, size)) {
+                msg = "copy failed";
+                goto fail_free;
+        }
+        csum = csum_partial(buf_align, size, 0);
+        if (csum != os_info_old->entry[nr].csum) {
+                msg = "checksum failed";
+                goto fail_free;
+        }
+        os_info_old->entry[nr].addr = (u64)(unsigned long)buf_align;
+        msg = "copied";
+        goto out;
+fail_free:
+        kfree(buf);
+fail:
+        os_info_old->entry[nr].addr = 0;
+out:
+        pr_info("entry %i: %s (addr=0x%lx size=%lu)\n",
+                nr, msg, addr, size);
+}
+
+/*
+ * Initialize os info and os info entries from oldmem
+ */
+static void os_info_old_init(void)
+{
+        static int os_info_init;
+        unsigned long addr;
+
+        if (os_info_init)
+                return;
+        if (!OLDMEM_BASE)
+                goto fail;
+        if (copy_from_oldmem(&addr, &S390_lowcore.os_info, sizeof(addr)))
+                goto fail;
+        if (addr == 0 || addr % PAGE_SIZE)
+                goto fail;
+        os_info_old = kzalloc(sizeof(*os_info_old), GFP_KERNEL);
+        if (!os_info_old)
+                goto fail;
+        if (copy_from_oldmem(os_info_old, (void *) addr, sizeof(*os_info_old)))
+                goto fail_free;
+        if (os_info_old->magic != OS_INFO_MAGIC)
+                goto fail_free;
+        if (os_info_old->csum != os_info_csum(os_info_old))
+                goto fail_free;
+        if (os_info_old->version_major > OS_INFO_VERSION_MAJOR)
+                goto fail_free;
+        os_info_old_alloc(OS_INFO_VMCOREINFO, 1);
+        os_info_old_alloc(OS_INFO_REIPL_BLOCK, 1);
+        os_info_old_alloc(OS_INFO_INIT_FN, PAGE_SIZE);
+        pr_info("crashkernel: addr=0x%lx size=%lu\n",
+                (unsigned long) os_info_old->crashkernel_addr,
+                (unsigned long) os_info_old->crashkernel_size);
+        os_info_init = 1;
+        return;
+fail_free:
+        kfree(os_info_old);
+fail:
+        os_info_init = 1;
+        os_info_old = NULL;
+}
+
+/*
+ * Return pointer to os infor entry and its size
+ */
+void *os_info_old_entry(int nr, unsigned long *size)
+{
+        os_info_old_init();
+
+        if (!os_info_old)
+                return NULL;
+        if (!os_info_old->entry[nr].addr)
+                return NULL;
+        *size = (unsigned long) os_info_old->entry[nr].size;
+        return (void *)(unsigned long)os_info_old->entry[nr].addr;
+}
+#endif
diff --git a/arch/s390/kernel/process.c b/arch/s390/kernel/process.c
index 7618085b416..3732e4c09cb 100644
--- a/arch/s390/kernel/process.c
+++ b/arch/s390/kernel/process.c
@@ -77,13 +77,8 @@ static void default_idle(void)
                 local_irq_enable();
                 return;
         }
-        trace_hardirqs_on();
-        /* Don't trace preempt off for idle. */
-        stop_critical_timings();
-        /* Stop virtual timer and halt the cpu. */
+        /* Halt the cpu and keep track of cpu time accounting. */
         vtime_stop_cpu();
-        /* Reenable preemption tracer. */
-        start_critical_timings();
 }
 
 void cpu_idle(void)
diff --git a/arch/s390/kernel/setup.c b/arch/s390/kernel/setup.c
index 3b2efc81f34..38e751278bf 100644
--- a/arch/s390/kernel/setup.c
+++ b/arch/s390/kernel/setup.c
@@ -2,7 +2,7 @@
  *  arch/s390/kernel/setup.c
  *
  *  S390 version
- *    Copyright (C) IBM Corp. 1999,2010
+ *    Copyright (C) IBM Corp. 1999,2012
  *    Author(s): Hartmut Penner (hp@de.ibm.com),
  *               Martin Schwidefsky (schwidefsky@de.ibm.com)
  *
@@ -62,6 +62,8 @@
 #include <asm/ebcdic.h>
 #include <asm/kvm_virtio.h>
 #include <asm/diag.h>
+#include <asm/os_info.h>
+#include "entry.h"
 
 long psw_kernel_bits    = PSW_DEFAULT_KEY | PSW_MASK_BASE | PSW_ASC_PRIMARY |
                           PSW_MASK_EA | PSW_MASK_BA;
@@ -351,8 +353,9 @@ static void setup_addressing_mode(void)
         }
 }
 
-static void __init
-setup_lowcore(void)
+void *restart_stack __attribute__((__section__(".data")));
+
+static void __init setup_lowcore(void)
 {
         struct _lowcore *lc;
 
@@ -363,7 +366,7 @@ setup_lowcore(void)
         lc = __alloc_bootmem_low(LC_PAGES * PAGE_SIZE, LC_PAGES * PAGE_SIZE, 0);
         lc->restart_psw.mask = psw_kernel_bits;
         lc->restart_psw.addr =
-                PSW_ADDR_AMODE | (unsigned long) psw_restart_int_handler;
+                PSW_ADDR_AMODE | (unsigned long) restart_int_handler;
         lc->external_new_psw.mask = psw_kernel_bits |
                 PSW_MASK_DAT | PSW_MASK_MCHECK;
         lc->external_new_psw.addr =
@@ -412,6 +415,24 @@ setup_lowcore(void)
         lc->last_update_timer = S390_lowcore.last_update_timer;
         lc->last_update_clock = S390_lowcore.last_update_clock;
         lc->ftrace_func = S390_lowcore.ftrace_func;
+
+        restart_stack = __alloc_bootmem(ASYNC_SIZE, ASYNC_SIZE, 0);
+        restart_stack += ASYNC_SIZE;
+
+        /*
+         * Set up PSW restart to call ipl.c:do_restart(). Copy the relevant
+         * restart data to the absolute zero lowcore. This is necesary if
+         * PSW restart is done on an offline CPU that has lowcore zero.
+         */
+        lc->restart_stack = (unsigned long) restart_stack;
+        lc->restart_fn = (unsigned long) do_restart;
+        lc->restart_data = 0;
+        lc->restart_source = -1UL;
+        memcpy(&S390_lowcore.restart_stack, &lc->restart_stack,
+               4*sizeof(unsigned long));
+        copy_to_absolute_zero(&S390_lowcore.restart_psw,
+                              &lc->restart_psw, sizeof(psw_t));
+
         set_prefix((u32)(unsigned long) lc);
         lowcore_ptr[0] = lc;
 }
@@ -572,27 +593,6 @@ static void __init setup_memory_end(void)
         }
 }
 
-void *restart_stack __attribute__((__section__(".data")));
-
-/*
- * Setup new PSW and allocate stack for PSW restart interrupt
- */
-static void __init setup_restart_psw(void)
-{
-        psw_t psw;
-
-        restart_stack = __alloc_bootmem(ASYNC_SIZE, ASYNC_SIZE, 0);
-        restart_stack += ASYNC_SIZE;
-
-        /*
-         * Setup restart PSW for absolute zero lowcore. This is necesary
-         * if PSW restart is done on an offline CPU that has lowcore zero
-         */
-        psw.mask = PSW_DEFAULT_KEY | PSW_MASK_BASE | PSW_MASK_EA | PSW_MASK_BA;
-        psw.addr = PSW_ADDR_AMODE | (unsigned long) psw_restart_int_handler;
-        copy_to_absolute_zero(&S390_lowcore.restart_psw, &psw, sizeof(psw));
-}
-
 static void __init setup_vmcoreinfo(void)
 {
 #ifdef CONFIG_KEXEC
@@ -747,7 +747,7 @@ static void __init reserve_crashkernel(void)
 {
 #ifdef CONFIG_CRASH_DUMP
         unsigned long long crash_base, crash_size;
-        char *msg;
+        char *msg = NULL;
         int rc;
 
         rc = parse_crashkernel(boot_command_line, memory_end, &crash_size,
@@ -779,11 +779,11 @@ static void __init reserve_crashkernel(void)
         pr_info("Reserving %lluMB of memory at %lluMB "
                 "for crashkernel (System RAM: %luMB)\n",
                 crash_size >> 20, crash_base >> 20, memory_end >> 20);
+        os_info_crashkernel_add(crash_base, crash_size);
 #endif
 }
 
-static void __init
-setup_memory(void)
+static void __init setup_memory(void)
 {
         unsigned long bootmap_size;
         unsigned long start_pfn, end_pfn;
@@ -1014,8 +1014,7 @@ static void __init setup_hwcaps(void)
  * was printed.
  */
 
-void __init
-setup_arch(char **cmdline_p)
+void __init setup_arch(char **cmdline_p)
 {
         /*
          * print what head.S has found out about the machine
@@ -1060,6 +1059,7 @@ setup_arch(char **cmdline_p)
 
         parse_early_param();
 
+        os_info_init();
         setup_ipl();
         setup_memory_end();
         setup_addressing_mode();
@@ -1068,7 +1068,6 @@ setup_arch(char **cmdline_p)
         setup_memory();
         setup_resources();
         setup_vmcoreinfo();
-        setup_restart_psw();
         setup_lowcore();
 
         cpu_init();
diff --git a/arch/s390/kernel/signal.c b/arch/s390/kernel/signal.c
index 2d421d90fad..f29f5ef400e 100644
--- a/arch/s390/kernel/signal.c
+++ b/arch/s390/kernel/signal.c
@@ -384,7 +384,6 @@ static int handle_signal(unsigned long sig, struct k_sigaction *ka,
                          siginfo_t *info, sigset_t *oldset,
                          struct pt_regs *regs)
 {
-        sigset_t blocked;
         int ret;
 
         /* Set up the stack frame */
@@ -394,10 +393,7 @@ static int handle_signal(unsigned long sig, struct k_sigaction *ka,
                 ret = setup_frame(sig, ka, oldset, regs);
         if (ret)
                 return ret;
-        sigorsets(&blocked, &current->blocked, &ka->sa.sa_mask);
-        if (!(ka->sa.sa_flags & SA_NODEFER))
-                sigaddset(&blocked, sig);
-        set_current_blocked(&blocked);
+        block_sigmask(ka, sig);
         return 0;
 }
 
diff --git a/arch/s390/kernel/smp.c b/arch/s390/kernel/smp.c
index b0e28c47ab8..a8bf9994b08 100644
--- a/arch/s390/kernel/smp.c
+++ b/arch/s390/kernel/smp.c
@@ -1,23 +1,18 @@
 /*
- *  arch/s390/kernel/smp.c
+ *  SMP related functions
  *
- *    Copyright IBM Corp. 1999, 2009
- *    Author(s): Denis Joseph Barrow (djbarrow@de.ibm.com,barrow_dj@yahoo.com),
- *               Martin Schwidefsky (schwidefsky@de.ibm.com)
- *               Heiko Carstens (heiko.carstens@de.ibm.com)
+ *    Copyright IBM Corp. 1999,2012
+ *    Author(s): Denis Joseph Barrow,
+ *               Martin Schwidefsky <schwidefsky@de.ibm.com>,
+ *               Heiko Carstens <heiko.carstens@de.ibm.com>,
  *
  *  based on other smp stuff by
  *    (c) 1995 Alan Cox, CymruNET Ltd  <alan@cymru.net>
  *    (c) 1998 Ingo Molnar
  *
- * We work with logical cpu numbering everywhere we can. The only
- * functions using the real cpu address (got from STAP) are the sigp
- * functions. For all other functions we use the identity mapping.
- * That means that cpu_number_map[i] == i for every cpu. cpu_number_map is
- * used e.g. to find the idle task belonging to a logical cpu. Every array
- * in the kernel is sorted by the logical cpu number and not by the physical
- * one which is causing all the confusion with __cpu_logical_map and
- * cpu_number_map in other architectures.
+ * The code outside of smp.c uses logical cpu numbers, only smp.c does
+ * the translation of logical to physical cpu ids. All new code that
+ * operates on physical cpu numbers needs to go into smp.c.
  */
 
 #define KMSG_COMPONENT "cpu"
@@ -31,198 +26,433 @@
 #include <linux/spinlock.h>
 #include <linux/kernel_stat.h>
 #include <linux/delay.h>
-#include <linux/cache.h>
 #include <linux/interrupt.h>
 #include <linux/irqflags.h>
 #include <linux/cpu.h>
-#include <linux/timex.h>
-#include <linux/bootmem.h>
 #include <linux/slab.h>
 #include <linux/crash_dump.h>
 #include <asm/asm-offsets.h>
 #include <asm/ipl.h>
 #include <asm/setup.h>
-#include <asm/sigp.h>
-#include <asm/pgalloc.h>
 #include <asm/irq.h>
-#include <asm/cpcmd.h>
 #include <asm/tlbflush.h>
 #include <asm/timer.h>
 #include <asm/lowcore.h>
 #include <asm/sclp.h>
-#include <asm/cputime.h>
 #include <asm/vdso.h>
-#include <asm/cpu.h>
+#include <asm/debug.h>
+#include <asm/os_info.h>
 #include "entry.h"
 
-/* logical cpu to cpu address */
-unsigned short __cpu_logical_map[NR_CPUS];
+enum {
+        sigp_sense = 1,
+        sigp_external_call = 2,
+        sigp_emergency_signal = 3,
+        sigp_start = 4,
+        sigp_stop = 5,
+        sigp_restart = 6,
+        sigp_stop_and_store_status = 9,
+        sigp_initial_cpu_reset = 11,
+        sigp_cpu_reset = 12,
+        sigp_set_prefix = 13,
+        sigp_store_status_at_address = 14,
+        sigp_store_extended_status_at_address = 15,
+        sigp_set_architecture = 18,
+        sigp_conditional_emergency_signal = 19,
+        sigp_sense_running = 21,
+};
 
-static struct task_struct *current_set[NR_CPUS];
+enum {
+        sigp_order_code_accepted = 0,
+        sigp_status_stored = 1,
+        sigp_busy = 2,
+        sigp_not_operational = 3,
+};
 
-static u8 smp_cpu_type;
-static int smp_use_sigp_detection;
+enum {
+        ec_schedule = 0,
+        ec_call_function,
+        ec_call_function_single,
+        ec_stop_cpu,
+};
 
-enum s390_cpu_state {
+enum {
         CPU_STATE_STANDBY,
         CPU_STATE_CONFIGURED,
 };
 
+struct pcpu {
+        struct cpu cpu;
+        struct task_struct *idle;       /* idle process for the cpu */
+        struct _lowcore *lowcore;       /* lowcore page(s) for the cpu */
+        unsigned long async_stack;      /* async stack for the cpu */
+        unsigned long panic_stack;      /* panic stack for the cpu */
+        unsigned long ec_mask;          /* bit mask for ec_xxx functions */
+        int state;                      /* physical cpu state */
+        u32 status;                     /* last status received via sigp */
+        u16 address;                    /* physical cpu address */
+};
+
+static u8 boot_cpu_type;
+static u16 boot_cpu_address;
+static struct pcpu pcpu_devices[NR_CPUS];
+
 DEFINE_MUTEX(smp_cpu_state_mutex);
-static int smp_cpu_state[NR_CPUS];
 
-static DEFINE_PER_CPU(struct cpu, cpu_devices);
+/*
+ * Signal processor helper functions.
+ */
+static inline int __pcpu_sigp(u16 addr, u8 order, u32 parm, u32 *status)
+{
+        register unsigned int reg1 asm ("1") = parm;
+        int cc;
 
-static void smp_ext_bitcall(int, int);
+        asm volatile(
+                "       sigp    %1,%2,0(%3)\n"
+                "       ipm     %0\n"
+                "       srl     %0,28\n"
+                : "=d" (cc), "+d" (reg1) : "d" (addr), "a" (order) : "cc");
+        if (status && cc == 1)
+                *status = reg1;
+        return cc;
+}
 
-static int raw_cpu_stopped(int cpu)
+static inline int __pcpu_sigp_relax(u16 addr, u8 order, u32 parm, u32 *status)
 {
-        u32 status;
+        int cc;
 
-        switch (raw_sigp_ps(&status, 0, cpu, sigp_sense)) {
-        case sigp_status_stored:
-                /* Check for stopped and check stop state */
-                if (status & 0x50)
-                        return 1;
-                break;
-        default:
-                break;
+        while (1) {
+                cc = __pcpu_sigp(addr, order, parm, status);
+                if (cc != sigp_busy)
+                        return cc;
+                cpu_relax();
         }
-        return 0;
 }
 
-static inline int cpu_stopped(int cpu)
+static int pcpu_sigp_retry(struct pcpu *pcpu, u8 order, u32 parm)
+{
+        int cc, retry;
+
+        for (retry = 0; ; retry++) {
+                cc = __pcpu_sigp(pcpu->address, order, parm, &pcpu->status);
+                if (cc != sigp_busy)
+                        break;
+                if (retry >= 3)
+                        udelay(10);
+        }
+        return cc;
+}
+
+static inline int pcpu_stopped(struct pcpu *pcpu)
+{
+        if (__pcpu_sigp(pcpu->address, sigp_sense,
+                        0, &pcpu->status) != sigp_status_stored)
+                return 0;
+        /* Check for stopped and check stop state */
+        return !!(pcpu->status & 0x50);
+}
+
+static inline int pcpu_running(struct pcpu *pcpu)
 {
-        return raw_cpu_stopped(cpu_logical_map(cpu));
+        if (__pcpu_sigp(pcpu->address, sigp_sense_running,
+                        0, &pcpu->status) != sigp_status_stored)
+                return 1;
+        /* Check for running status */
+        return !(pcpu->status & 0x400);
 }
 
 /*
- * Ensure that PSW restart is done on an online CPU
+ * Find struct pcpu by cpu address.
  */
-void smp_restart_with_online_cpu(void)
+static struct pcpu *pcpu_find_address(const struct cpumask *mask, int address)
 {
         int cpu;
 
-        for_each_online_cpu(cpu) {
-                if (stap() == __cpu_logical_map[cpu]) {
-                        /* We are online: Enable DAT again and return */
-                        __load_psw_mask(psw_kernel_bits | PSW_MASK_DAT);
-                        return;
-                }
+        for_each_cpu(cpu, mask)
+                if (pcpu_devices[cpu].address == address)
+                        return pcpu_devices + cpu;
+        return NULL;
+}
+
+static void pcpu_ec_call(struct pcpu *pcpu, int ec_bit)
+{
+        int order;
+
+        set_bit(ec_bit, &pcpu->ec_mask);
+        order = pcpu_running(pcpu) ?
+                sigp_external_call : sigp_emergency_signal;
+        pcpu_sigp_retry(pcpu, order, 0);
+}
+
+static int __cpuinit pcpu_alloc_lowcore(struct pcpu *pcpu, int cpu)
+{
+        struct _lowcore *lc;
+
+        if (pcpu != &pcpu_devices[0]) {
+                pcpu->lowcore = (struct _lowcore *)
+                        __get_free_pages(GFP_KERNEL | GFP_DMA, LC_ORDER);
+                pcpu->async_stack = __get_free_pages(GFP_KERNEL, ASYNC_ORDER);
+                pcpu->panic_stack = __get_free_page(GFP_KERNEL);
+                if (!pcpu->lowcore || !pcpu->panic_stack || !pcpu->async_stack)
+                        goto out;
         }
-        /* We are not online: Do PSW restart on an online CPU */
-        while (sigp(cpu, sigp_restart) == sigp_busy)
-                cpu_relax();
-        /* And stop ourself */
-        while (raw_sigp(stap(), sigp_stop) == sigp_busy)
-                cpu_relax();
-        for (;;);
+        lc = pcpu->lowcore;
+        memcpy(lc, &S390_lowcore, 512);
+        memset((char *) lc + 512, 0, sizeof(*lc) - 512);
+        lc->async_stack = pcpu->async_stack + ASYNC_SIZE;
+        lc->panic_stack = pcpu->panic_stack + PAGE_SIZE;
+        lc->cpu_nr = cpu;
+#ifndef CONFIG_64BIT
+        if (MACHINE_HAS_IEEE) {
+                lc->extended_save_area_addr = get_zeroed_page(GFP_KERNEL);
+                if (!lc->extended_save_area_addr)
+                        goto out;
+        }
+#else
+        if (vdso_alloc_per_cpu(lc))
+                goto out;
+#endif
+        lowcore_ptr[cpu] = lc;
+        pcpu_sigp_retry(pcpu, sigp_set_prefix, (u32)(unsigned long) lc);
+        return 0;
+out:
+        if (pcpu != &pcpu_devices[0]) {
+                free_page(pcpu->panic_stack);
+                free_pages(pcpu->async_stack, ASYNC_ORDER);
+                free_pages((unsigned long) pcpu->lowcore, LC_ORDER);
+        }
+        return -ENOMEM;
 }
 
-void smp_switch_to_ipl_cpu(void (*func)(void *), void *data)
+static void pcpu_free_lowcore(struct pcpu *pcpu)
 {
-        struct _lowcore *lc, *current_lc;
-        struct stack_frame *sf;
-        struct pt_regs *regs;
-        unsigned long sp;
-
-        if (smp_processor_id() == 0)
-                func(data);
-        __load_psw_mask(PSW_DEFAULT_KEY | PSW_MASK_BASE |
-                        PSW_MASK_EA | PSW_MASK_BA);
-        /* Disable lowcore protection */
-        __ctl_clear_bit(0, 28);
-        current_lc = lowcore_ptr[smp_processor_id()];
-        lc = lowcore_ptr[0];
-        if (!lc)
-                lc = current_lc;
-        lc->restart_psw.mask =
-                PSW_DEFAULT_KEY | PSW_MASK_BASE | PSW_MASK_EA | PSW_MASK_BA;
-        lc->restart_psw.addr = PSW_ADDR_AMODE | (unsigned long) smp_restart_cpu;
-        if (!cpu_online(0))
-                smp_switch_to_cpu(func, data, 0, stap(), __cpu_logical_map[0]);
-        while (sigp(0, sigp_stop_and_store_status) == sigp_busy)
-                cpu_relax();
-        sp = lc->panic_stack;
-        sp -= sizeof(struct pt_regs);
-        regs = (struct pt_regs *) sp;
-        memcpy(&regs->gprs, &current_lc->gpregs_save_area, sizeof(regs->gprs));
-        regs->psw = current_lc->psw_save_area;
-        sp -= STACK_FRAME_OVERHEAD;
-        sf = (struct stack_frame *) sp;
-        sf->back_chain = 0;
-        smp_switch_to_cpu(func, data, sp, stap(), __cpu_logical_map[0]);
+        pcpu_sigp_retry(pcpu, sigp_set_prefix, 0);
+        lowcore_ptr[pcpu - pcpu_devices] = NULL;
+#ifndef CONFIG_64BIT
+        if (MACHINE_HAS_IEEE) {
+                struct _lowcore *lc = pcpu->lowcore;
+
+                free_page((unsigned long) lc->extended_save_area_addr);
+                lc->extended_save_area_addr = 0;
+        }
+#else
+        vdso_free_per_cpu(pcpu->lowcore);
+#endif
+        if (pcpu != &pcpu_devices[0]) {
+                free_page(pcpu->panic_stack);
+                free_pages(pcpu->async_stack, ASYNC_ORDER);
+                free_pages((unsigned long) pcpu->lowcore, LC_ORDER);
+        }
+}
+
+static void pcpu_prepare_secondary(struct pcpu *pcpu, int cpu)
+{
+        struct _lowcore *lc = pcpu->lowcore;
+
+        atomic_inc(&init_mm.context.attach_count);
+        lc->cpu_nr = cpu;
+        lc->percpu_offset = __per_cpu_offset[cpu];
+        lc->kernel_asce = S390_lowcore.kernel_asce;
+        lc->machine_flags = S390_lowcore.machine_flags;
+        lc->ftrace_func = S390_lowcore.ftrace_func;
+        lc->user_timer = lc->system_timer = lc->steal_timer = 0;
+        __ctl_store(lc->cregs_save_area, 0, 15);
+        save_access_regs((unsigned int *) lc->access_regs_save_area);
+        memcpy(lc->stfle_fac_list, S390_lowcore.stfle_fac_list,
+               MAX_FACILITY_BIT/8);
+}
+
+static void pcpu_attach_task(struct pcpu *pcpu, struct task_struct *tsk)
+{
+        struct _lowcore *lc = pcpu->lowcore;
+        struct thread_info *ti = task_thread_info(tsk);
+
+        lc->kernel_stack = (unsigned long) task_stack_page(tsk) + THREAD_SIZE;
+        lc->thread_info = (unsigned long) task_thread_info(tsk);
+        lc->current_task = (unsigned long) tsk;
+        lc->user_timer = ti->user_timer;
+        lc->system_timer = ti->system_timer;
+        lc->steal_timer = 0;
+}
+
+static void pcpu_start_fn(struct pcpu *pcpu, void (*func)(void *), void *data)
+{
+        struct _lowcore *lc = pcpu->lowcore;
+
+        lc->restart_stack = lc->kernel_stack;
+        lc->restart_fn = (unsigned long) func;
+        lc->restart_data = (unsigned long) data;
+        lc->restart_source = -1UL;
+        pcpu_sigp_retry(pcpu, sigp_restart, 0);
+}
+
+/*
+ * Call function via PSW restart on pcpu and stop the current cpu.
+ */
+static void pcpu_delegate(struct pcpu *pcpu, void (*func)(void *),
+                          void *data, unsigned long stack)
+{
+        struct _lowcore *lc = pcpu->lowcore;
+        unsigned short this_cpu;
+
+        __load_psw_mask(psw_kernel_bits);
+        this_cpu = stap();
+        if (pcpu->address == this_cpu)
+                func(data);     /* should not return */
+        /* Stop target cpu (if func returns this stops the current cpu). */
+        pcpu_sigp_retry(pcpu, sigp_stop, 0);
+        /* Restart func on the target cpu and stop the current cpu. */
+        lc->restart_stack = stack;
+        lc->restart_fn = (unsigned long) func;
+        lc->restart_data = (unsigned long) data;
+        lc->restart_source = (unsigned long) this_cpu;
+        asm volatile(
+                "0:     sigp    0,%0,6  # sigp restart to target cpu\n"
+                "       brc     2,0b    # busy, try again\n"
+                "1:     sigp    0,%1,5  # sigp stop to current cpu\n"
+                "       brc     2,1b    # busy, try again\n"
+                : : "d" (pcpu->address), "d" (this_cpu) : "0", "1", "cc");
+        for (;;) ;
+}
+
+/*
+ * Call function on an online CPU.
+ */
+void smp_call_online_cpu(void (*func)(void *), void *data)
+{
+        struct pcpu *pcpu;
+
+        /* Use the current cpu if it is online. */
+        pcpu = pcpu_find_address(cpu_online_mask, stap());
+        if (!pcpu)
+                /* Use the first online cpu. */
+                pcpu = pcpu_devices + cpumask_first(cpu_online_mask);
+        pcpu_delegate(pcpu, func, data, (unsigned long) restart_stack);
+}
+
+/*
+ * Call function on the ipl CPU.
+ */
+void smp_call_ipl_cpu(void (*func)(void *), void *data)
+{
+        pcpu_delegate(&pcpu_devices[0], func, data,
+                      pcpu_devices->panic_stack + PAGE_SIZE);
+}
+
+int smp_find_processor_id(u16 address)
+{
+        int cpu;
+
+        for_each_present_cpu(cpu)
+                if (pcpu_devices[cpu].address == address)
+                        return cpu;
+        return -1;
+}
+
+int smp_vcpu_scheduled(int cpu)
+{
+        return pcpu_running(pcpu_devices + cpu);
+}
+
+void smp_yield(void)
+{
+        if (MACHINE_HAS_DIAG44)
+                asm volatile("diag 0,0,0x44");
 }
 
-static void smp_stop_cpu(void)
+void smp_yield_cpu(int cpu)
 {
-        while (sigp(smp_processor_id(), sigp_stop) == sigp_busy)
+        if (MACHINE_HAS_DIAG9C)
+                asm volatile("diag %0,0,0x9c"
+                             : : "d" (pcpu_devices[cpu].address));
+        else if (MACHINE_HAS_DIAG44)
+                asm volatile("diag 0,0,0x44");
+}
+
+/*
+ * Send cpus emergency shutdown signal. This gives the cpus the
+ * opportunity to complete outstanding interrupts.
+ */
+void smp_emergency_stop(cpumask_t *cpumask)
+{
+        u64 end;
+        int cpu;
+
+        end = get_clock() + (1000000UL << 12);
+        for_each_cpu(cpu, cpumask) {
+                struct pcpu *pcpu = pcpu_devices + cpu;
+                set_bit(ec_stop_cpu, &pcpu->ec_mask);
+                while (__pcpu_sigp(pcpu->address, sigp_emergency_signal,
+                                   0, NULL) == sigp_busy &&
+                       get_clock() < end)
+                        cpu_relax();
+        }
+        while (get_clock() < end) {
+                for_each_cpu(cpu, cpumask)
+                        if (pcpu_stopped(pcpu_devices + cpu))
+                                cpumask_clear_cpu(cpu, cpumask);
+                if (cpumask_empty(cpumask))
+                        break;
                 cpu_relax();
+        }
 }
 
+/*
+ * Stop all cpus but the current one.
+ */
 void smp_send_stop(void)
 {
         cpumask_t cpumask;
         int cpu;
-        u64 end;
 
         /* Disable all interrupts/machine checks */
         __load_psw_mask(psw_kernel_bits | PSW_MASK_DAT);
         trace_hardirqs_off();
 
+        debug_set_critical();
         cpumask_copy(&cpumask, cpu_online_mask);
         cpumask_clear_cpu(smp_processor_id(), &cpumask);
 
-        if (oops_in_progress) {
-                /*
-                 * Give the other cpus the opportunity to complete
-                 * outstanding interrupts before stopping them.
-                 */
-                end = get_clock() + (1000000UL << 12);
-                for_each_cpu(cpu, &cpumask) {
-                        set_bit(ec_stop_cpu, (unsigned long *)
-                                &lowcore_ptr[cpu]->ext_call_fast);
-                        while (sigp(cpu, sigp_emergency_signal) == sigp_busy &&
-                               get_clock() < end)
-                                cpu_relax();
-                }
-                while (get_clock() < end) {
-                        for_each_cpu(cpu, &cpumask)
-                                if (cpu_stopped(cpu))
-                                        cpumask_clear_cpu(cpu, &cpumask);
-                        if (cpumask_empty(&cpumask))
-                                break;
-                        cpu_relax();
-                }
-        }
+        if (oops_in_progress)
+                smp_emergency_stop(&cpumask);
 
         /* stop all processors */
         for_each_cpu(cpu, &cpumask) {
-                while (sigp(cpu, sigp_stop) == sigp_busy)
-                        cpu_relax();
-                while (!cpu_stopped(cpu))
+                struct pcpu *pcpu = pcpu_devices + cpu;
+                pcpu_sigp_retry(pcpu, sigp_stop, 0);
+                while (!pcpu_stopped(pcpu))
                         cpu_relax();
         }
 }
 
 /*
+ * Stop the current cpu.
+ */
+void smp_stop_cpu(void)
+{
+        pcpu_sigp_retry(pcpu_devices + smp_processor_id(), sigp_stop, 0);
+        for (;;) ;
+}
+
+/*
  * This is the main routine where commands issued by other
  * cpus are handled.
  */
-
-static void do_ext_call_interrupt(unsigned int ext_int_code,
+static void do_ext_call_interrupt(struct ext_code ext_code,
                                   unsigned int param32, unsigned long param64)
 {
         unsigned long bits;
+        int cpu;
 
-        if ((ext_int_code & 0xffff) == 0x1202)
-                kstat_cpu(smp_processor_id()).irqs[EXTINT_EXC]++;
+        cpu = smp_processor_id();
+        if (ext_code.code == 0x1202)
+                kstat_cpu(cpu).irqs[EXTINT_EXC]++;
         else
-                kstat_cpu(smp_processor_id()).irqs[EXTINT_EMS]++;
+                kstat_cpu(cpu).irqs[EXTINT_EMS]++;
         /*
          * handle bit signal external calls
          */
-        bits = xchg(&S390_lowcore.ext_call_fast, 0);
+        bits = xchg(&pcpu_devices[cpu].ec_mask, 0);
 
         if (test_bit(ec_stop_cpu, &bits))
                 smp_stop_cpu();
@@ -238,38 +468,17 @@ static void do_ext_call_interrupt(unsigned int ext_int_code,
 
 }
 
-/*
- * Send an external call sigp to another cpu and return without waiting
- * for its completion.
- */
-static void smp_ext_bitcall(int cpu, int sig)
-{
-        int order;
-
-        /*
-         * Set signaling bit in lowcore of target cpu and kick it
-         */
-        set_bit(sig, (unsigned long *) &lowcore_ptr[cpu]->ext_call_fast);
-        while (1) {
-                order = smp_vcpu_scheduled(cpu) ?
-                        sigp_external_call : sigp_emergency_signal;
-                if (sigp(cpu, order) != sigp_busy)
-                        break;
-                udelay(10);
-        }
-}
-
 void arch_send_call_function_ipi_mask(const struct cpumask *mask)
 {
         int cpu;
 
         for_each_cpu(cpu, mask)
-                smp_ext_bitcall(cpu, ec_call_function);
+                pcpu_ec_call(pcpu_devices + cpu, ec_call_function);
 }
 
 void arch_send_call_function_single_ipi(int cpu)
 {
-        smp_ext_bitcall(cpu, ec_call_function_single);
+        pcpu_ec_call(pcpu_devices + cpu, ec_call_function_single);
 }
 
 #ifndef CONFIG_64BIT
@@ -295,15 +504,16 @@ EXPORT_SYMBOL(smp_ptlb_all);
  */
 void smp_send_reschedule(int cpu)
 {
-        smp_ext_bitcall(cpu, ec_schedule);
+        pcpu_ec_call(pcpu_devices + cpu, ec_schedule);
 }
 
 /*
  * parameter area for the set/clear control bit callbacks
  */
 struct ec_creg_mask_parms {
-        unsigned long orvals[16];
-        unsigned long andvals[16];
+        unsigned long orval;
+        unsigned long andval;
+        int cr;
 };
 
 /*
@@ -313,11 +523,9 @@ static void smp_ctl_bit_callback(void *info)
 {
         struct ec_creg_mask_parms *pp = info;
         unsigned long cregs[16];
-        int i;
 
         __ctl_store(cregs, 0, 15);
-        for (i = 0; i <= 15; i++)
-                cregs[i] = (cregs[i] & pp->andvals[i]) | pp->orvals[i];
+        cregs[pp->cr] = (cregs[pp->cr] & pp->andval) | pp->orval;
         __ctl_load(cregs, 0, 15);
 }
 
@@ -326,11 +534,8 @@ static void smp_ctl_bit_callback(void *info)
  */
 void smp_ctl_set_bit(int cr, int bit)
 {
-        struct ec_creg_mask_parms parms;
+        struct ec_creg_mask_parms parms = { 1UL << bit, -1UL, cr };
 
-        memset(&parms.orvals, 0, sizeof(parms.orvals));
-        memset(&parms.andvals, 0xff, sizeof(parms.andvals));
-        parms.orvals[cr] = 1UL << bit;
         on_each_cpu(smp_ctl_bit_callback, &parms, 1);
 }
 EXPORT_SYMBOL(smp_ctl_set_bit);
@@ -340,220 +545,178 @@ EXPORT_SYMBOL(smp_ctl_set_bit);
  */
 void smp_ctl_clear_bit(int cr, int bit)
 {
-        struct ec_creg_mask_parms parms;
+        struct ec_creg_mask_parms parms = { 0, ~(1UL << bit), cr };
 
-        memset(&parms.orvals, 0, sizeof(parms.orvals));
-        memset(&parms.andvals, 0xff, sizeof(parms.andvals));
-        parms.andvals[cr] = ~(1UL << bit);
         on_each_cpu(smp_ctl_bit_callback, &parms, 1);
 }
 EXPORT_SYMBOL(smp_ctl_clear_bit);
 
 #if defined(CONFIG_ZFCPDUMP) || defined(CONFIG_CRASH_DUMP)
 
-static void __init smp_get_save_area(unsigned int cpu, unsigned int phy_cpu)
+struct save_area *zfcpdump_save_areas[NR_CPUS + 1];
+EXPORT_SYMBOL_GPL(zfcpdump_save_areas);
+
+static void __init smp_get_save_area(int cpu, u16 address)
 {
-        if (ipl_info.type != IPL_TYPE_FCP_DUMP && !OLDMEM_BASE)
-                return;
+        void *lc = pcpu_devices[0].lowcore;
+        struct save_area *save_area;
+
         if (is_kdump_kernel())
                 return;
+        if (!OLDMEM_BASE && (address == boot_cpu_address ||
+                             ipl_info.type != IPL_TYPE_FCP_DUMP))
+                return;
         if (cpu >= NR_CPUS) {
-                pr_warning("CPU %i exceeds the maximum %i and is excluded from "
-                           "the dump\n", cpu, NR_CPUS - 1);
+                pr_warning("CPU %i exceeds the maximum %i and is excluded "
+                           "from the dump\n", cpu, NR_CPUS - 1);
                 return;
         }
-        zfcpdump_save_areas[cpu] = kmalloc(sizeof(struct save_area), GFP_KERNEL);
-        while (raw_sigp(phy_cpu, sigp_stop_and_store_status) == sigp_busy)
-                cpu_relax();
-        memcpy_real(zfcpdump_save_areas[cpu],
-                    (void *)(unsigned long) store_prefix() + SAVE_AREA_BASE,
-                    sizeof(struct save_area));
+        save_area = kmalloc(sizeof(struct save_area), GFP_KERNEL);
+        if (!save_area)
+                panic("could not allocate memory for save area\n");
+        zfcpdump_save_areas[cpu] = save_area;
+#ifdef CONFIG_CRASH_DUMP
+        if (address == boot_cpu_address) {
+                /* Copy the registers of the boot cpu. */
+                copy_oldmem_page(1, (void *) save_area, sizeof(*save_area),
+                                 SAVE_AREA_BASE - PAGE_SIZE, 0);
+                return;
+        }
+#endif
+        /* Get the registers of a non-boot cpu. */
+        __pcpu_sigp_relax(address, sigp_stop_and_store_status, 0, NULL);
+        memcpy_real(save_area, lc + SAVE_AREA_BASE, sizeof(*save_area));
 }
 
-struct save_area *zfcpdump_save_areas[NR_CPUS + 1];
-EXPORT_SYMBOL_GPL(zfcpdump_save_areas);
-
-#else
-
-static inline void smp_get_save_area(unsigned int cpu, unsigned int phy_cpu) { }
-
-#endif /* CONFIG_ZFCPDUMP */
-
-static int cpu_known(int cpu_id)
+int smp_store_status(int cpu)
 {
-        int cpu;
+        struct pcpu *pcpu;
 
-        for_each_present_cpu(cpu) {
-                if (__cpu_logical_map[cpu] == cpu_id)
-                        return 1;
-        }
+        pcpu = pcpu_devices + cpu;
+        if (__pcpu_sigp_relax(pcpu->address, sigp_stop_and_store_status,
+                              0, NULL) != sigp_order_code_accepted)
+                return -EIO;
         return 0;
 }
 
-static int smp_rescan_cpus_sigp(cpumask_t avail)
-{
-        int cpu_id, logical_cpu;
+#else /* CONFIG_ZFCPDUMP || CONFIG_CRASH_DUMP */
 
-        logical_cpu = cpumask_first(&avail);
-        if (logical_cpu >= nr_cpu_ids)
-                return 0;
-        for (cpu_id = 0; cpu_id <= MAX_CPU_ADDRESS; cpu_id++) {
-                if (cpu_known(cpu_id))
-                        continue;
-                __cpu_logical_map[logical_cpu] = cpu_id;
-                cpu_set_polarization(logical_cpu, POLARIZATION_UNKNOWN);
-                if (!cpu_stopped(logical_cpu))
-                        continue;
-                set_cpu_present(logical_cpu, true);
-                smp_cpu_state[logical_cpu] = CPU_STATE_CONFIGURED;
-                logical_cpu = cpumask_next(logical_cpu, &avail);
-                if (logical_cpu >= nr_cpu_ids)
-                        break;
-        }
-        return 0;
-}
+static inline void smp_get_save_area(int cpu, u16 address) { }
 
-static int smp_rescan_cpus_sclp(cpumask_t avail)
+#endif /* CONFIG_ZFCPDUMP || CONFIG_CRASH_DUMP */
+
+static struct sclp_cpu_info *smp_get_cpu_info(void)
 {
+        static int use_sigp_detection;
         struct sclp_cpu_info *info;
-        int cpu_id, logical_cpu, cpu;
-        int rc;
-
-        logical_cpu = cpumask_first(&avail);
-        if (logical_cpu >= nr_cpu_ids)
-                return 0;
-        info = kmalloc(sizeof(*info), GFP_KERNEL);
-        if (!info)
-                return -ENOMEM;
-        rc = sclp_get_cpu_info(info);
-        if (rc)
-                goto out;
-        for (cpu = 0; cpu < info->combined; cpu++) {
-                if (info->has_cpu_type && info->cpu[cpu].type != smp_cpu_type)
-                        continue;
-                cpu_id = info->cpu[cpu].address;
-                if (cpu_known(cpu_id))
-                        continue;
-                __cpu_logical_map[logical_cpu] = cpu_id;
-                cpu_set_polarization(logical_cpu, POLARIZATION_UNKNOWN);
-                set_cpu_present(logical_cpu, true);
-                if (cpu >= info->configured)
-                        smp_cpu_state[logical_cpu] = CPU_STATE_STANDBY;
-                else
-                        smp_cpu_state[logical_cpu] = CPU_STATE_CONFIGURED;
-                logical_cpu = cpumask_next(logical_cpu, &avail);
-                if (logical_cpu >= nr_cpu_ids)
-                        break;
+        int address;
+
+        info = kzalloc(sizeof(*info), GFP_KERNEL);
+        if (info && (use_sigp_detection || sclp_get_cpu_info(info))) {
+                use_sigp_detection = 1;
+                for (address = 0; address <= MAX_CPU_ADDRESS; address++) {
+                        if (__pcpu_sigp_relax(address, sigp_sense, 0, NULL) ==
+                            sigp_not_operational)
+                                continue;
+                        info->cpu[info->configured].address = address;
+                        info->configured++;
+                }
+                info->combined = info->configured;
         }
-out:
-        kfree(info);
-        return rc;
+        return info;
 }
 
-static int __smp_rescan_cpus(void)
+static int __devinit smp_add_present_cpu(int cpu);
+
+static int __devinit __smp_rescan_cpus(struct sclp_cpu_info *info,
+                                       int sysfs_add)
 {
+        struct pcpu *pcpu;
         cpumask_t avail;
+        int cpu, nr, i;
 
+        nr = 0;
         cpumask_xor(&avail, cpu_possible_mask, cpu_present_mask);
-        if (smp_use_sigp_detection)
-                return smp_rescan_cpus_sigp(avail);
-        else
-                return smp_rescan_cpus_sclp(avail);
+        cpu = cpumask_first(&avail);
+        for (i = 0; (i < info->combined) && (cpu < nr_cpu_ids); i++) {
+                if (info->has_cpu_type && info->cpu[i].type != boot_cpu_type)
+                        continue;
+                if (pcpu_find_address(cpu_present_mask, info->cpu[i].address))
+                        continue;
+                pcpu = pcpu_devices + cpu;
+                pcpu->address = info->cpu[i].address;
+                pcpu->state = (cpu >= info->configured) ?
+                        CPU_STATE_STANDBY : CPU_STATE_CONFIGURED;
+                cpu_set_polarization(cpu, POLARIZATION_UNKNOWN);
+                set_cpu_present(cpu, true);
+                if (sysfs_add && smp_add_present_cpu(cpu) != 0)
+                        set_cpu_present(cpu, false);
+                else
+                        nr++;
+                cpu = cpumask_next(cpu, &avail);
+        }
+        return nr;
 }
 
 static void __init smp_detect_cpus(void)
 {
         unsigned int cpu, c_cpus, s_cpus;
         struct sclp_cpu_info *info;
-        u16 boot_cpu_addr, cpu_addr;
 
-        c_cpus = 1;
-        s_cpus = 0;
-        boot_cpu_addr = __cpu_logical_map[0];
-        info = kmalloc(sizeof(*info), GFP_KERNEL);
+        info = smp_get_cpu_info();
         if (!info)
                 panic("smp_detect_cpus failed to allocate memory\n");
-#ifdef CONFIG_CRASH_DUMP
-        if (OLDMEM_BASE && !is_kdump_kernel()) {
-                struct save_area *save_area;
-
-                save_area = kmalloc(sizeof(*save_area), GFP_KERNEL);
-                if (!save_area)
-                        panic("could not allocate memory for save area\n");
-                copy_oldmem_page(1, (void *) save_area, sizeof(*save_area),
-                                 0x200, 0);
-                zfcpdump_save_areas[0] = save_area;
-        }
-#endif
-        /* Use sigp detection algorithm if sclp doesn't work. */
-        if (sclp_get_cpu_info(info)) {
-                smp_use_sigp_detection = 1;
-                for (cpu = 0; cpu <= MAX_CPU_ADDRESS; cpu++) {
-                        if (cpu == boot_cpu_addr)
-                                continue;
-                        if (!raw_cpu_stopped(cpu))
-                                continue;
-                        smp_get_save_area(c_cpus, cpu);
-                        c_cpus++;
-                }
-                goto out;
-        }
-
         if (info->has_cpu_type) {
                 for (cpu = 0; cpu < info->combined; cpu++) {
-                        if (info->cpu[cpu].address == boot_cpu_addr) {
-                                smp_cpu_type = info->cpu[cpu].type;
-                                break;
-                        }
+                        if (info->cpu[cpu].address != boot_cpu_address)
+                                continue;
+                        /* The boot cpu dictates the cpu type. */
+                        boot_cpu_type = info->cpu[cpu].type;
+                        break;
                 }
         }
-
+        c_cpus = s_cpus = 0;
         for (cpu = 0; cpu < info->combined; cpu++) {
-                if (info->has_cpu_type && info->cpu[cpu].type != smp_cpu_type)
+                if (info->has_cpu_type && info->cpu[cpu].type != boot_cpu_type)
                         continue;
-                cpu_addr = info->cpu[cpu].address;
-                if (cpu_addr == boot_cpu_addr)
-                        continue;
-                if (!raw_cpu_stopped(cpu_addr)) {
+                if (cpu < info->configured) {
+                        smp_get_save_area(c_cpus, info->cpu[cpu].address);
+                        c_cpus++;
+                } else
                         s_cpus++;
-                        continue;
-                }
-                smp_get_save_area(c_cpus, cpu_addr);
-                c_cpus++;
         }
-out:
-        kfree(info);
         pr_info("%d configured CPUs, %d standby CPUs\n", c_cpus, s_cpus);
         get_online_cpus();
-        __smp_rescan_cpus();
+        __smp_rescan_cpus(info, 0);
         put_online_cpus();
+        kfree(info);
 }
 
 /*
  *      Activate a secondary processor.
  */
-int __cpuinit start_secondary(void *cpuvoid)
+static void __cpuinit smp_start_secondary(void *cpuvoid)
 {
+        S390_lowcore.last_update_clock = get_clock();
+        S390_lowcore.restart_stack = (unsigned long) restart_stack;
+        S390_lowcore.restart_fn = (unsigned long) do_restart;
+        S390_lowcore.restart_data = 0;
+        S390_lowcore.restart_source = -1UL;
+        restore_access_regs(S390_lowcore.access_regs_save_area);
+        __ctl_load(S390_lowcore.cregs_save_area, 0, 15);
+        __load_psw_mask(psw_kernel_bits | PSW_MASK_DAT);
         cpu_init();
         preempt_disable();
         init_cpu_timer();
         init_cpu_vtimer();
         pfault_init();
-
         notify_cpu_starting(smp_processor_id());
         ipi_call_lock();
         set_cpu_online(smp_processor_id(), true);
         ipi_call_unlock();
-        __ctl_clear_bit(0, 28); /* Disable lowcore protection */
-        S390_lowcore.restart_psw.mask =
-                PSW_DEFAULT_KEY | PSW_MASK_BASE | PSW_MASK_EA | PSW_MASK_BA;
-        S390_lowcore.restart_psw.addr =
-                PSW_ADDR_AMODE | (unsigned long) psw_restart_int_handler;
-        __ctl_set_bit(0, 28); /* Enable lowcore protection */
         local_irq_enable();
         /* cpu_idle will call schedule for us */
         cpu_idle();
-        return 0;
 }
 
 struct create_idle {
@@ -572,82 +735,20 @@ static void __cpuinit smp_fork_idle(struct work_struct *work)
         complete(&c_idle->done);
 }
 
-static int __cpuinit smp_alloc_lowcore(int cpu)
-{
-        unsigned long async_stack, panic_stack;
-        struct _lowcore *lowcore;
-
-        lowcore = (void *) __get_free_pages(GFP_KERNEL | GFP_DMA, LC_ORDER);
-        if (!lowcore)
-                return -ENOMEM;
-        async_stack = __get_free_pages(GFP_KERNEL, ASYNC_ORDER);
-        panic_stack = __get_free_page(GFP_KERNEL);
-        if (!panic_stack || !async_stack)
-                goto out;
-        memcpy(lowcore, &S390_lowcore, 512);
-        memset((char *)lowcore + 512, 0, sizeof(*lowcore) - 512);
-        lowcore->async_stack = async_stack + ASYNC_SIZE;
-        lowcore->panic_stack = panic_stack + PAGE_SIZE;
-        lowcore->restart_psw.mask =
-                PSW_DEFAULT_KEY | PSW_MASK_BASE | PSW_MASK_EA | PSW_MASK_BA;
-        lowcore->restart_psw.addr =
-                PSW_ADDR_AMODE | (unsigned long) restart_int_handler;
-        if (user_mode != HOME_SPACE_MODE)
-                lowcore->restart_psw.mask |= PSW_ASC_HOME;
-#ifndef CONFIG_64BIT
-        if (MACHINE_HAS_IEEE) {
-                unsigned long save_area;
-
-                save_area = get_zeroed_page(GFP_KERNEL);
-                if (!save_area)
-                        goto out;
-                lowcore->extended_save_area_addr = (u32) save_area;
-        }
-#else
-        if (vdso_alloc_per_cpu(cpu, lowcore))
-                goto out;
-#endif
-        lowcore_ptr[cpu] = lowcore;
-        return 0;
-
-out:
-        free_page(panic_stack);
-        free_pages(async_stack, ASYNC_ORDER);
-        free_pages((unsigned long) lowcore, LC_ORDER);
-        return -ENOMEM;
-}
-
-static void smp_free_lowcore(int cpu)
-{
-        struct _lowcore *lowcore;
-
-        lowcore = lowcore_ptr[cpu];
-#ifndef CONFIG_64BIT
-        if (MACHINE_HAS_IEEE)
-                free_page((unsigned long) lowcore->extended_save_area_addr);
-#else
-        vdso_free_per_cpu(cpu, lowcore);
-#endif
-        free_page(lowcore->panic_stack - PAGE_SIZE);
-        free_pages(lowcore->async_stack - ASYNC_SIZE, ASYNC_ORDER);
-        free_pages((unsigned long) lowcore, LC_ORDER);
-        lowcore_ptr[cpu] = NULL;
-}
-
 /* Upping and downing of CPUs */
 int __cpuinit __cpu_up(unsigned int cpu)
 {
-        struct _lowcore *cpu_lowcore;
         struct create_idle c_idle;
-        struct task_struct *idle;
-        struct stack_frame *sf;
-        u32 lowcore;
-        int ccode;
+        struct pcpu *pcpu;
+        int rc;
 
-        if (smp_cpu_state[cpu] != CPU_STATE_CONFIGURED)
+        pcpu = pcpu_devices + cpu;
+        if (pcpu->state != CPU_STATE_CONFIGURED)
+                return -EIO;
+        if (pcpu_sigp_retry(pcpu, sigp_initial_cpu_reset, 0) !=
+            sigp_order_code_accepted)
                 return -EIO;
-        idle = current_set[cpu];
-        if (!idle) {
+        if (!pcpu->idle) {
                 c_idle.done = COMPLETION_INITIALIZER_ONSTACK(c_idle.done);
                 INIT_WORK_ONSTACK(&c_idle.work, smp_fork_idle);
                 c_idle.cpu = cpu;
@@ -655,68 +756,28 @@ int __cpuinit __cpu_up(unsigned int cpu)
                 wait_for_completion(&c_idle.done);
                 if (IS_ERR(c_idle.idle))
                         return PTR_ERR(c_idle.idle);
-                idle = c_idle.idle;
-                current_set[cpu] = c_idle.idle;
+                pcpu->idle = c_idle.idle;
         }
-        init_idle(idle, cpu);
-        if (smp_alloc_lowcore(cpu))
-                return -ENOMEM;
-        do {
-                ccode = sigp(cpu, sigp_initial_cpu_reset);
-                if (ccode == sigp_busy)
-                        udelay(10);
-                if (ccode == sigp_not_operational)
-                        goto err_out;
-        } while (ccode == sigp_busy);
-
-        lowcore = (u32)(unsigned long)lowcore_ptr[cpu];
-        while (sigp_p(lowcore, cpu, sigp_set_prefix) == sigp_busy)
-                udelay(10);
-
-        cpu_lowcore = lowcore_ptr[cpu];
-        cpu_lowcore->kernel_stack = (unsigned long)
-                task_stack_page(idle) + THREAD_SIZE;
-        cpu_lowcore->thread_info = (unsigned long) task_thread_info(idle);
-        sf = (struct stack_frame *) (cpu_lowcore->kernel_stack
-                                     - sizeof(struct pt_regs)
-                                     - sizeof(struct stack_frame));
-        memset(sf, 0, sizeof(struct stack_frame));
-        sf->gprs[9] = (unsigned long) sf;
-        cpu_lowcore->gpregs_save_area[15] = (unsigned long) sf;
-        __ctl_store(cpu_lowcore->cregs_save_area, 0, 15);
-        atomic_inc(&init_mm.context.attach_count);
-        asm volatile(
-                "       stam    0,15,0(%0)"
-                : : "a" (&cpu_lowcore->access_regs_save_area) : "memory");
-        cpu_lowcore->percpu_offset = __per_cpu_offset[cpu];
-        cpu_lowcore->current_task = (unsigned long) idle;
-        cpu_lowcore->cpu_nr = cpu;
-        cpu_lowcore->kernel_asce = S390_lowcore.kernel_asce;
-        cpu_lowcore->machine_flags = S390_lowcore.machine_flags;
-        cpu_lowcore->ftrace_func = S390_lowcore.ftrace_func;
-        memcpy(cpu_lowcore->stfle_fac_list, S390_lowcore.stfle_fac_list,
-               MAX_FACILITY_BIT/8);
-        eieio();
-
-        while (sigp(cpu, sigp_restart) == sigp_busy)
-                udelay(10);
-
+        init_idle(pcpu->idle, cpu);
+        rc = pcpu_alloc_lowcore(pcpu, cpu);
+        if (rc)
+                return rc;
+        pcpu_prepare_secondary(pcpu, cpu);
+        pcpu_attach_task(pcpu, pcpu->idle);
+        pcpu_start_fn(pcpu, smp_start_secondary, NULL);
         while (!cpu_online(cpu))
                 cpu_relax();
         return 0;
-
-err_out:
-        smp_free_lowcore(cpu);
-        return -EIO;
 }
 
 static int __init setup_possible_cpus(char *s)
 {
-        int pcpus, cpu;
+        int max, cpu;
 
-        pcpus = simple_strtoul(s, NULL, 0);
+        if (kstrtoint(s, 0, &max) < 0)
+                return 0;
         init_cpu_possible(cpumask_of(0));
-        for (cpu = 1; cpu < pcpus && cpu < nr_cpu_ids; cpu++)
+        for (cpu = 1; cpu < max && cpu < nr_cpu_ids; cpu++)
                 set_cpu_possible(cpu, true);
         return 0;
 }
@@ -726,113 +787,79 @@ early_param("possible_cpus", setup_possible_cpus);
 
 int __cpu_disable(void)
 {
-        struct ec_creg_mask_parms cr_parms;
-        int cpu = smp_processor_id();
-
-        set_cpu_online(cpu, false);
+        unsigned long cregs[16];
 
-        /* Disable pfault pseudo page faults on this cpu. */
+        set_cpu_online(smp_processor_id(), false);
+        /* Disable pseudo page faults on this cpu. */
         pfault_fini();
-
-        memset(&cr_parms.orvals, 0, sizeof(cr_parms.orvals));
-        memset(&cr_parms.andvals, 0xff, sizeof(cr_parms.andvals));
-
-        /* disable all external interrupts */
-        cr_parms.orvals[0] = 0;
-        cr_parms.andvals[0] = ~(1 << 15 | 1 << 14 | 1 << 13 | 1 << 11 |
-                                1 << 10 | 1 <<  9 | 1 <<  6 | 1 <<  5 |
-                                1 <<  4);
-        /* disable all I/O interrupts */
-        cr_parms.orvals[6] = 0;
-        cr_parms.andvals[6] = ~(1 << 31 | 1 << 30 | 1 << 29 | 1 << 28 |
-                                1 << 27 | 1 << 26 | 1 << 25 | 1 << 24);
-        /* disable most machine checks */
-        cr_parms.orvals[14] = 0;
-        cr_parms.andvals[14] = ~(1 << 28 | 1 << 27 | 1 << 26 |
-                                 1 << 25 | 1 << 24);
-
-        smp_ctl_bit_callback(&cr_parms);
-
+        /* Disable interrupt sources via control register. */
+        __ctl_store(cregs, 0, 15);
+        cregs[0]  &= ~0x0000ee70UL;     /* disable all external interrupts */
+        cregs[6]  &= ~0xff000000UL;     /* disable all I/O interrupts */
+        cregs[14] &= ~0x1f000000UL;     /* disable most machine checks */
+        __ctl_load(cregs, 0, 15);
         return 0;
 }
 
 void __cpu_die(unsigned int cpu)
 {
+        struct pcpu *pcpu;
+
         /* Wait until target cpu is down */
-        while (!cpu_stopped(cpu))
+        pcpu = pcpu_devices + cpu;
+        while (!pcpu_stopped(pcpu))
                 cpu_relax();
-        while (sigp_p(0, cpu, sigp_set_prefix) == sigp_busy)
-                udelay(10);
-        smp_free_lowcore(cpu);
+        pcpu_free_lowcore(pcpu);
         atomic_dec(&init_mm.context.attach_count);
 }
 
 void __noreturn cpu_die(void)
 {
         idle_task_exit();
-        while (sigp(smp_processor_id(), sigp_stop) == sigp_busy)
-                cpu_relax();
-        for (;;);
+        pcpu_sigp_retry(pcpu_devices + smp_processor_id(), sigp_stop, 0);
+        for (;;) ;
 }
 
 #endif /* CONFIG_HOTPLUG_CPU */
 
-void __init smp_prepare_cpus(unsigned int max_cpus)
+static void smp_call_os_info_init_fn(void)
 {
-#ifndef CONFIG_64BIT
-        unsigned long save_area = 0;
-#endif
-        unsigned long async_stack, panic_stack;
-        struct _lowcore *lowcore;
+        int (*init_fn)(void);
+        unsigned long size;
 
-        smp_detect_cpus();
+        init_fn = os_info_old_entry(OS_INFO_INIT_FN, &size);
+        if (!init_fn)
+                return;
+        init_fn();
+}
 
+void __init smp_prepare_cpus(unsigned int max_cpus)
+{
         /* request the 0x1201 emergency signal external interrupt */
         if (register_external_interrupt(0x1201, do_ext_call_interrupt) != 0)
                 panic("Couldn't request external interrupt 0x1201");
         /* request the 0x1202 external call external interrupt */
         if (register_external_interrupt(0x1202, do_ext_call_interrupt) != 0)
                 panic("Couldn't request external interrupt 0x1202");
-
-        /* Reallocate current lowcore, but keep its contents. */
-        lowcore = (void *) __get_free_pages(GFP_KERNEL | GFP_DMA, LC_ORDER);
-        panic_stack = __get_free_page(GFP_KERNEL);
-        async_stack = __get_free_pages(GFP_KERNEL, ASYNC_ORDER);
-        BUG_ON(!lowcore || !panic_stack || !async_stack);
-#ifndef CONFIG_64BIT
-        if (MACHINE_HAS_IEEE)
-                save_area = get_zeroed_page(GFP_KERNEL);
-#endif
-        local_irq_disable();
-        local_mcck_disable();
-        lowcore_ptr[smp_processor_id()] = lowcore;
-        *lowcore = S390_lowcore;
-        lowcore->panic_stack = panic_stack + PAGE_SIZE;
-        lowcore->async_stack = async_stack + ASYNC_SIZE;
-#ifndef CONFIG_64BIT
-        if (MACHINE_HAS_IEEE)
-                lowcore->extended_save_area_addr = (u32) save_area;
-#endif
-        set_prefix((u32)(unsigned long) lowcore);
-        local_mcck_enable();
-        local_irq_enable();
-#ifdef CONFIG_64BIT
-        if (vdso_alloc_per_cpu(smp_processor_id(), &S390_lowcore))
-                BUG();
-#endif
+        smp_call_os_info_init_fn();
+        smp_detect_cpus();
 }
 
 void __init smp_prepare_boot_cpu(void)
 {
-        BUG_ON(smp_processor_id() != 0);
-
-        current_thread_info()->cpu = 0;
-        set_cpu_present(0, true);
-        set_cpu_online(0, true);
+        struct pcpu *pcpu = pcpu_devices;
+
+        boot_cpu_address = stap();
+        pcpu->idle = current;
+        pcpu->state = CPU_STATE_CONFIGURED;
+        pcpu->address = boot_cpu_address;
+        pcpu->lowcore = (struct _lowcore *)(unsigned long) store_prefix();
+        pcpu->async_stack = S390_lowcore.async_stack - ASYNC_SIZE;
+        pcpu->panic_stack = S390_lowcore.panic_stack - PAGE_SIZE;
         S390_lowcore.percpu_offset = __per_cpu_offset[0];
-        current_set[0] = current;
-        smp_cpu_state[0] = CPU_STATE_CONFIGURED;
         cpu_set_polarization(0, POLARIZATION_UNKNOWN);
+        set_cpu_present(0, true);
+        set_cpu_online(0, true);
 }
 
 void __init smp_cpus_done(unsigned int max_cpus)
@@ -842,7 +869,6 @@ void __init smp_cpus_done(unsigned int max_cpus)
 void __init smp_setup_processor_id(void)
 {
         S390_lowcore.cpu_nr = 0;
-        __cpu_logical_map[0] = stap();
 }
 
 /*
@@ -858,56 +884,57 @@ int setup_profiling_timer(unsigned int multiplier)
 
 #ifdef CONFIG_HOTPLUG_CPU
 static ssize_t cpu_configure_show(struct device *dev,
-                                struct device_attribute *attr, char *buf)
+                                  struct device_attribute *attr, char *buf)
 {
         ssize_t count;
 
         mutex_lock(&smp_cpu_state_mutex);
-        count = sprintf(buf, "%d\n", smp_cpu_state[dev->id]);
+        count = sprintf(buf, "%d\n", pcpu_devices[dev->id].state);
         mutex_unlock(&smp_cpu_state_mutex);
         return count;
 }
 
 static ssize_t cpu_configure_store(struct device *dev,
-                                  struct device_attribute *attr,
-                                  const char *buf, size_t count)
+                                   struct device_attribute *attr,
+                                   const char *buf, size_t count)
 {
-        int cpu = dev->id;
-        int val, rc;
+        struct pcpu *pcpu;
+        int cpu, val, rc;
         char delim;
 
         if (sscanf(buf, "%d %c", &val, &delim) != 1)
                 return -EINVAL;
         if (val != 0 && val != 1)
                 return -EINVAL;
-
         get_online_cpus();
         mutex_lock(&smp_cpu_state_mutex);
         rc = -EBUSY;
         /* disallow configuration changes of online cpus and cpu 0 */
+        cpu = dev->id;
         if (cpu_online(cpu) || cpu == 0)
                 goto out;
+        pcpu = pcpu_devices + cpu;
         rc = 0;
         switch (val) {
         case 0:
-                if (smp_cpu_state[cpu] == CPU_STATE_CONFIGURED) {
-                        rc = sclp_cpu_deconfigure(__cpu_logical_map[cpu]);
-                        if (!rc) {
-                                smp_cpu_state[cpu] = CPU_STATE_STANDBY;
-                                cpu_set_polarization(cpu, POLARIZATION_UNKNOWN);
-                                topology_expect_change();
-                        }
-                }
+                if (pcpu->state != CPU_STATE_CONFIGURED)
+                        break;
+                rc = sclp_cpu_deconfigure(pcpu->address);
+                if (rc)
+                        break;
+                pcpu->state = CPU_STATE_STANDBY;
+                cpu_set_polarization(cpu, POLARIZATION_UNKNOWN);
+                topology_expect_change();
                 break;
         case 1:
-                if (smp_cpu_state[cpu] == CPU_STATE_STANDBY) {
-                        rc = sclp_cpu_configure(__cpu_logical_map[cpu]);
-                        if (!rc) {
-                                smp_cpu_state[cpu] = CPU_STATE_CONFIGURED;
-                                cpu_set_polarization(cpu, POLARIZATION_UNKNOWN);
-                                topology_expect_change();
-                        }
-                }
+                if (pcpu->state != CPU_STATE_STANDBY)
+                        break;
+                rc = sclp_cpu_configure(pcpu->address);
+                if (rc)
+                        break;
+                pcpu->state = CPU_STATE_CONFIGURED;
+                cpu_set_polarization(cpu, POLARIZATION_UNKNOWN);
+                topology_expect_change();
                 break;
         default:
                 break;
@@ -923,7 +950,7 @@ static DEVICE_ATTR(configure, 0644, cpu_configure_show, cpu_configure_store);
 static ssize_t show_cpu_address(struct device *dev,
                                 struct device_attribute *attr, char *buf)
 {
-        return sprintf(buf, "%d\n", __cpu_logical_map[dev->id]);
+        return sprintf(buf, "%d\n", pcpu_devices[dev->id].address);
 }
 static DEVICE_ATTR(address, 0444, show_cpu_address, NULL);
 
@@ -955,22 +982,16 @@ static DEVICE_ATTR(capability, 0444, show_capability, NULL);
 static ssize_t show_idle_count(struct device *dev,
                                 struct device_attribute *attr, char *buf)
 {
-        struct s390_idle_data *idle;
+        struct s390_idle_data *idle = &per_cpu(s390_idle, dev->id);
         unsigned long long idle_count;
         unsigned int sequence;
 
-        idle = &per_cpu(s390_idle, dev->id);
-repeat:
-        sequence = idle->sequence;
-        smp_rmb();
-        if (sequence & 1)
-                goto repeat;
-        idle_count = idle->idle_count;
-        if (idle->idle_enter)
-                idle_count++;
-        smp_rmb();
-        if (idle->sequence != sequence)
-                goto repeat;
+        do {
+                sequence = ACCESS_ONCE(idle->sequence);
+                idle_count = ACCESS_ONCE(idle->idle_count);
+                if (ACCESS_ONCE(idle->idle_enter))
+                        idle_count++;
+        } while ((sequence & 1) || (idle->sequence != sequence));
         return sprintf(buf, "%llu\n", idle_count);
 }
 static DEVICE_ATTR(idle_count, 0444, show_idle_count, NULL);
@@ -978,24 +999,18 @@ static DEVICE_ATTR(idle_count, 0444, show_idle_count, NULL);
 static ssize_t show_idle_time(struct device *dev,
                                 struct device_attribute *attr, char *buf)
 {
-        struct s390_idle_data *idle;
-        unsigned long long now, idle_time, idle_enter;
+        struct s390_idle_data *idle = &per_cpu(s390_idle, dev->id);
+        unsigned long long now, idle_time, idle_enter, idle_exit;
         unsigned int sequence;
 
-        idle = &per_cpu(s390_idle, dev->id);
-        now = get_clock();
-repeat:
-        sequence = idle->sequence;
-        smp_rmb();
-        if (sequence & 1)
-                goto repeat;
-        idle_time = idle->idle_time;
-        idle_enter = idle->idle_enter;
-        if (idle_enter != 0ULL && idle_enter < now)
-                idle_time += now - idle_enter;
-        smp_rmb();
-        if (idle->sequence != sequence)
-                goto repeat;
+        do {
+                now = get_clock();
+                sequence = ACCESS_ONCE(idle->sequence);
+                idle_time = ACCESS_ONCE(idle->idle_time);
+                idle_enter = ACCESS_ONCE(idle->idle_enter);
+                idle_exit = ACCESS_ONCE(idle->idle_exit);
+        } while ((sequence & 1) || (idle->sequence != sequence));
+        idle_time += idle_enter ? ((idle_exit ? : now) - idle_enter) : 0;
         return sprintf(buf, "%llu\n", idle_time >> 12);
 }
 static DEVICE_ATTR(idle_time_us, 0444, show_idle_time, NULL);
@@ -1015,7 +1030,7 @@ static int __cpuinit smp_cpu_notify(struct notifier_block *self,
                                     unsigned long action, void *hcpu)
 {
         unsigned int cpu = (unsigned int)(long)hcpu;
-        struct cpu *c = &per_cpu(cpu_devices, cpu);
+        struct cpu *c = &pcpu_devices[cpu].cpu;
         struct device *s = &c->dev;
         struct s390_idle_data *idle;
         int err = 0;
@@ -1041,7 +1056,7 @@ static struct notifier_block __cpuinitdata smp_cpu_nb = {
 
 static int __devinit smp_add_present_cpu(int cpu)
 {
-        struct cpu *c = &per_cpu(cpu_devices, cpu);
+        struct cpu *c = &pcpu_devices[cpu].cpu;
         struct device *s = &c->dev;
         int rc;
 
@@ -1079,29 +1094,21 @@ out:
 
 int __ref smp_rescan_cpus(void)
 {
-        cpumask_t newcpus;
-        int cpu;
-        int rc;
+        struct sclp_cpu_info *info;
+        int nr;
 
+        info = smp_get_cpu_info();
+        if (!info)
+                return -ENOMEM;
         get_online_cpus();
         mutex_lock(&smp_cpu_state_mutex);
-        cpumask_copy(&newcpus, cpu_present_mask);
-        rc = __smp_rescan_cpus();
-        if (rc)
-                goto out;
-        cpumask_andnot(&newcpus, cpu_present_mask, &newcpus);
-        for_each_cpu(cpu, &newcpus) {
-                rc = smp_add_present_cpu(cpu);
-                if (rc)
-                        set_cpu_present(cpu, false);
-        }
-        rc = 0;
-out:
+        nr = __smp_rescan_cpus(info, 1);
         mutex_unlock(&smp_cpu_state_mutex);
         put_online_cpus();
-        if (!cpumask_empty(&newcpus))
+        kfree(info);
+        if (nr)
                 topology_schedule_update();
-        return rc;
+        return 0;
 }
 
 static ssize_t __ref rescan_store(struct device *dev,
diff --git a/arch/s390/kernel/switch_cpu.S b/arch/s390/kernel/switch_cpu.S
deleted file mode 100644
index bfe070bc765..00000000000
--- a/arch/s390/kernel/switch_cpu.S
+++ /dev/null
@@ -1,58 +0,0 @@
-/*
- * 31-bit switch cpu code
- *
- * Copyright IBM Corp. 2009
- *
- */
-
-#include <linux/linkage.h>
-#include <asm/asm-offsets.h>
-#include <asm/ptrace.h>
-
-# smp_switch_to_cpu switches to destination cpu and executes the passed function
-# Parameter: %r2 - function to call
-#            %r3 - function parameter
-#            %r4 - stack poiner
-#            %r5 - current cpu
-#            %r6 - destination cpu
-
-        .section .text
-ENTRY(smp_switch_to_cpu)
-        stm     %r6,%r15,__SF_GPRS(%r15)
-        lr      %r1,%r15
-        ahi     %r15,-STACK_FRAME_OVERHEAD
-        st      %r1,__SF_BACKCHAIN(%r15)
-        basr    %r13,0
-0:      la      %r1,.gprregs_addr-0b(%r13)
-        l       %r1,0(%r1)
-        stm     %r0,%r15,0(%r1)
-1:      sigp    %r0,%r6,__SIGP_RESTART  /* start destination CPU */
-        brc     2,1b                    /* busy, try again */
-2:      sigp    %r0,%r5,__SIGP_STOP     /* stop current CPU */
-        brc     2,2b                    /* busy, try again */
-3:      j       3b
-
-ENTRY(smp_restart_cpu)
-        basr    %r13,0
-0:      la      %r1,.gprregs_addr-0b(%r13)
-        l       %r1,0(%r1)
-        lm      %r0,%r15,0(%r1)
-1:      sigp    %r0,%r5,__SIGP_SENSE    /* Wait for calling CPU */
-        brc     10,1b                   /* busy, accepted (status 0), running */
-        tmll    %r0,0x40                /* Test if calling CPU is stopped */
-        jz      1b
-        ltr     %r4,%r4                 /* New stack ? */
-        jz      1f
-        lr      %r15,%r4
-1:      lr      %r14,%r2                /* r14: Function to call */
-        lr      %r2,%r3                 /* r2 : Parameter for function*/
-        basr    %r14,%r14               /* Call function */
-
-.gprregs_addr:
-        .long   .gprregs
-
-        .section .data,"aw",@progbits
-.gprregs:
-        .rept   16
-        .long   0
-        .endr
diff --git a/arch/s390/kernel/switch_cpu64.S b/arch/s390/kernel/switch_cpu64.S
deleted file mode 100644
index fcc42d799e4..00000000000
--- a/arch/s390/kernel/switch_cpu64.S
+++ /dev/null
@@ -1,51 +0,0 @@
-/*
- * 64-bit switch cpu code
- *
- * Copyright IBM Corp. 2009
- *
- */
-
-#include <linux/linkage.h>
-#include <asm/asm-offsets.h>
-#include <asm/ptrace.h>
-
-# smp_switch_to_cpu switches to destination cpu and executes the passed function
-# Parameter: %r2 - function to call
-#            %r3 - function parameter
-#            %r4 - stack poiner
-#            %r5 - current cpu
-#            %r6 - destination cpu
-
-        .section .text
-ENTRY(smp_switch_to_cpu)
-        stmg    %r6,%r15,__SF_GPRS(%r15)
-        lgr     %r1,%r15
-        aghi    %r15,-STACK_FRAME_OVERHEAD
-        stg     %r1,__SF_BACKCHAIN(%r15)
-        larl    %r1,.gprregs
-        stmg    %r0,%r15,0(%r1)
-1:      sigp    %r0,%r6,__SIGP_RESTART  /* start destination CPU */
-        brc     2,1b                    /* busy, try again */
-2:      sigp    %r0,%r5,__SIGP_STOP     /* stop current CPU */
-        brc     2,2b                    /* busy, try again */
-3:      j       3b
-
-ENTRY(smp_restart_cpu)
-        larl    %r1,.gprregs
-        lmg     %r0,%r15,0(%r1)
-1:      sigp    %r0,%r5,__SIGP_SENSE    /* Wait for calling CPU */
-        brc     10,1b                   /* busy, accepted (status 0), running */
-        tmll    %r0,0x40                /* Test if calling CPU is stopped */
-        jz      1b
-        ltgr    %r4,%r4                 /* New stack ? */
-        jz      1f
-        lgr     %r15,%r4
-1:      lgr     %r14,%r2                /* r14: Function to call */
-        lgr     %r2,%r3                 /* r2 : Parameter for function*/
-        basr    %r14,%r14               /* Call function */
-
-        .section .data,"aw",@progbits
-.gprregs:
-        .rept   16
-        .quad   0
-        .endr
diff --git a/arch/s390/kernel/swsusp_asm64.S b/arch/s390/kernel/swsusp_asm64.S
index acb78cdee89..dd70ef04605 100644
--- a/arch/s390/kernel/swsusp_asm64.S
+++ b/arch/s390/kernel/swsusp_asm64.S
@@ -42,7 +42,7 @@ ENTRY(swsusp_arch_suspend)
         lghi    %r1,0x1000
 
         /* Save CPU address */
-        stap    __LC_CPU_ADDRESS(%r0)
+        stap    __LC_EXT_CPU_ADDR(%r0)
 
         /* Store registers */
         mvc     0x318(4,%r1),__SF_EMPTY(%r15)   /* move prefix to lowcore */
@@ -173,15 +173,15 @@ pgm_check_entry:
         larl    %r1,.Lresume_cpu                /* Resume CPU address: r2 */
         stap    0(%r1)
         llgh    %r2,0(%r1)
-        llgh    %r1,__LC_CPU_ADDRESS(%r0)       /* Suspend CPU address: r1 */
+        llgh    %r1,__LC_EXT_CPU_ADDR(%r0)      /* Suspend CPU address: r1 */
         cgr     %r1,%r2
         je      restore_registers               /* r1 = r2 -> nothing to do */
         larl    %r4,.Lrestart_suspend_psw       /* Set new restart PSW */
         mvc     __LC_RST_NEW_PSW(16,%r0),0(%r4)
 3:
-        sigp    %r9,%r1,__SIGP_INITIAL_CPU_RESET
-        brc     8,4f    /* accepted */
-        brc     2,3b    /* busy, try again */
+        sigp    %r9,%r1,11                      /* sigp initial cpu reset */
+        brc     8,4f                            /* accepted */
+        brc     2,3b                            /* busy, try again */
 
         /* Suspend CPU not available -> panic */
         larl    %r15,init_thread_union
@@ -196,10 +196,10 @@ pgm_check_entry:
         lpsw    0(%r3)
 4:
         /* Switch to suspend CPU */
-        sigp    %r9,%r1,__SIGP_RESTART  /* start suspend CPU */
+        sigp    %r9,%r1,6               /* sigp restart to suspend CPU */
         brc     2,4b                    /* busy, try again */
 5:
-        sigp    %r9,%r2,__SIGP_STOP     /* stop resume (current) CPU */
+        sigp    %r9,%r2,5               /* sigp stop to current resume CPU */
         brc     2,5b                    /* busy, try again */
 6:      j       6b
 
@@ -207,7 +207,7 @@ restart_suspend:
         larl    %r1,.Lresume_cpu
         llgh    %r2,0(%r1)
 7:
-        sigp    %r9,%r2,__SIGP_SENSE    /* Wait for resume CPU */
+        sigp    %r9,%r2,1               /* sigp sense, wait for resume CPU */
         brc     8,7b                    /* accepted, status 0, still running */
         brc     2,7b                    /* busy, try again */
         tmll    %r9,0x40                /* Test if resume CPU is stopped */
@@ -257,6 +257,9 @@ restore_registers:
         lghi    %r2,0
         brasl   %r14,arch_set_page_states
 
+        /* Log potential guest relocation */
+        brasl   %r14,lgr_info_log
+
         /* Reinitialize the channel subsystem */
         brasl   %r14,channel_subsystem_reinit
 
diff --git a/arch/s390/kernel/time.c b/arch/s390/kernel/time.c
index 14da278febb..d4e1cb1dbcd 100644
--- a/arch/s390/kernel/time.c
+++ b/arch/s390/kernel/time.c
@@ -165,7 +165,7 @@ void init_cpu_timer(void)
         __ctl_set_bit(0, 4);
 }
 
-static void clock_comparator_interrupt(unsigned int ext_int_code,
+static void clock_comparator_interrupt(struct ext_code ext_code,
                                        unsigned int param32,
                                        unsigned long param64)
 {
@@ -177,7 +177,7 @@ static void clock_comparator_interrupt(unsigned int ext_int_code,
 static void etr_timing_alert(struct etr_irq_parm *);
 static void stp_timing_alert(struct stp_irq_parm *);
 
-static void timing_alert_interrupt(unsigned int ext_int_code,
+static void timing_alert_interrupt(struct ext_code ext_code,
                                    unsigned int param32, unsigned long param64)
 {
         kstat_cpu(smp_processor_id()).irqs[EXTINT_TLA]++;
diff --git a/arch/s390/kernel/topology.c b/arch/s390/kernel/topology.c
index 7370a41948c..4f8dc942257 100644
--- a/arch/s390/kernel/topology.c
+++ b/arch/s390/kernel/topology.c
@@ -79,12 +79,12 @@ static struct mask_info *add_cpus_to_mask(struct topology_cpu *tl_cpu,
              cpu < TOPOLOGY_CPU_BITS;
              cpu = find_next_bit(&tl_cpu->mask[0], TOPOLOGY_CPU_BITS, cpu + 1))
         {
-                unsigned int rcpu, lcpu;
+                unsigned int rcpu;
+                int lcpu;
 
                 rcpu = TOPOLOGY_CPU_BITS - 1 - cpu + tl_cpu->origin;
-                for_each_present_cpu(lcpu) {
-                        if (cpu_logical_map(lcpu) != rcpu)
-                                continue;
+                lcpu = smp_find_processor_id(rcpu);
+                if (lcpu >= 0) {
                         cpumask_set_cpu(lcpu, &book->mask);
                         cpu_book_id[lcpu] = book->id;
                         cpumask_set_cpu(lcpu, &core->mask);
diff --git a/arch/s390/kernel/traps.c b/arch/s390/kernel/traps.c
index 5ce3750b181..cd6ebe12c48 100644
--- a/arch/s390/kernel/traps.c
+++ b/arch/s390/kernel/traps.c
@@ -41,6 +41,7 @@
 #include <asm/cpcmd.h>
 #include <asm/lowcore.h>
 #include <asm/debug.h>
+#include <asm/ipl.h>
 #include "entry.h"
 
 void (*pgm_check_table[128])(struct pt_regs *regs);
@@ -144,8 +145,8 @@ void show_stack(struct task_struct *task, unsigned long *sp)
         for (i = 0; i < kstack_depth_to_print; i++) {
                 if (((addr_t) stack & (THREAD_SIZE-1)) == 0)
                         break;
-                if (i && ((i * sizeof (long) % 32) == 0))
-                        printk("\n       ");
+                if ((i * sizeof(long) % 32) == 0)
+                        printk("%s       ", i == 0 ? "" : "\n");
                 printk(LONG, *stack++);
         }
         printk("\n");
@@ -239,6 +240,7 @@ void die(struct pt_regs *regs, const char *str)
         static int die_counter;
 
         oops_enter();
+        lgr_info_log();
         debug_stop_all();
         console_verbose();
         spin_lock_irq(&die_lock);
diff --git a/arch/s390/kernel/vdso.c b/arch/s390/kernel/vdso.c
index d73630b4fe1..9c80138206b 100644
--- a/arch/s390/kernel/vdso.c
+++ b/arch/s390/kernel/vdso.c
@@ -89,18 +89,11 @@ static void vdso_init_data(struct vdso_data *vd)
 
 #ifdef CONFIG_64BIT
 /*
- * Setup per cpu vdso data page.
- */
-static void vdso_init_per_cpu_data(int cpu, struct vdso_per_cpu_data *vpcd)
-{
-}
-
-/*
  * Allocate/free per cpu vdso data.
  */
 #define SEGMENT_ORDER   2
 
-int vdso_alloc_per_cpu(int cpu, struct _lowcore *lowcore)
+int vdso_alloc_per_cpu(struct _lowcore *lowcore)
 {
         unsigned long segment_table, page_table, page_frame;
         u32 *psal, *aste;
@@ -139,7 +132,6 @@ int vdso_alloc_per_cpu(int cpu, struct _lowcore *lowcore)
         aste[4] = (u32)(addr_t) psal;
         lowcore->vdso_per_cpu_data = page_frame;
 
-        vdso_init_per_cpu_data(cpu, (struct vdso_per_cpu_data *) page_frame);
         return 0;
 
 out:
@@ -149,7 +141,7 @@ out:
         return -ENOMEM;
 }
 
-void vdso_free_per_cpu(int cpu, struct _lowcore *lowcore)
+void vdso_free_per_cpu(struct _lowcore *lowcore)
 {
         unsigned long segment_table, page_table, page_frame;
         u32 *psal, *aste;
@@ -168,19 +160,15 @@ void vdso_free_per_cpu(int cpu, struct _lowcore *lowcore)
         free_pages(segment_table, SEGMENT_ORDER);
 }
 
-static void __vdso_init_cr5(void *dummy)
+static void vdso_init_cr5(void)
 {
         unsigned long cr5;
 
+        if (user_mode == HOME_SPACE_MODE || !vdso_enabled)
+                return;
         cr5 = offsetof(struct _lowcore, paste);
         __ctl_load(cr5, 5, 5);
 }
-
-static void vdso_init_cr5(void)
-{
-        if (user_mode != HOME_SPACE_MODE && vdso_enabled)
-                on_each_cpu(__vdso_init_cr5, NULL, 1);
-}
 #endif /* CONFIG_64BIT */
 
 /*
@@ -253,17 +241,11 @@ int arch_setup_additional_pages(struct linux_binprm *bprm, int uses_interp)
          * on the "data" page of the vDSO or you'll stop getting kernel
          * updates and your nice userland gettimeofday will be totally dead.
          * It's fine to use that for setting breakpoints in the vDSO code
-         * pages though
-         *
-         * Make sure the vDSO gets into every core dump.
-         * Dumping its contents makes post-mortem fully interpretable later
-         * without matching up the same kernel and hardware config to see
-         * what PC values meant.
+         * pages though.
          */
         rc = install_special_mapping(mm, vdso_base, vdso_pages << PAGE_SHIFT,
                                      VM_READ|VM_EXEC|
-                                     VM_MAYREAD|VM_MAYWRITE|VM_MAYEXEC|
-                                     VM_ALWAYSDUMP,
+                                     VM_MAYREAD|VM_MAYWRITE|VM_MAYEXEC,
                                      vdso_pagelist);
         if (rc)
                 current->mm->context.vdso_base = 0;
@@ -322,10 +304,8 @@ static int __init vdso_init(void)
         }
         vdso64_pagelist[vdso64_pages - 1] = virt_to_page(vdso_data);
         vdso64_pagelist[vdso64_pages] = NULL;
-#ifndef CONFIG_SMP
-        if (vdso_alloc_per_cpu(0, &S390_lowcore))
+        if (vdso_alloc_per_cpu(&S390_lowcore))
                 BUG();
-#endif
         vdso_init_cr5();
 #endif /* CONFIG_64BIT */
 
@@ -335,7 +315,7 @@ static int __init vdso_init(void)
 
         return 0;
 }
-arch_initcall(vdso_init);
+early_initcall(vdso_init);
 
 int in_gate_area_no_mm(unsigned long addr)
 {
diff --git a/arch/s390/kernel/vtime.c b/arch/s390/kernel/vtime.c
index bb48977f546..39ebff50694 100644
--- a/arch/s390/kernel/vtime.c
+++ b/arch/s390/kernel/vtime.c
@@ -26,6 +26,7 @@
 #include <asm/irq_regs.h>
 #include <asm/cputime.h>
 #include <asm/irq.h>
+#include "entry.h"
 
 static DEFINE_PER_CPU(struct vtimer_queue, virt_cpu_timer);
 
@@ -123,153 +124,53 @@ void account_system_vtime(struct task_struct *tsk)
 }
 EXPORT_SYMBOL_GPL(account_system_vtime);
 
-void __kprobes vtime_start_cpu(__u64 int_clock, __u64 enter_timer)
+void __kprobes vtime_stop_cpu(void)
 {
         struct s390_idle_data *idle = &__get_cpu_var(s390_idle);
         struct vtimer_queue *vq = &__get_cpu_var(virt_cpu_timer);
-        __u64 idle_time, expires;
+        unsigned long long idle_time;
+        unsigned long psw_mask;
 
-        if (idle->idle_enter == 0ULL)
-                return;
+        trace_hardirqs_on();
+        /* Don't trace preempt off for idle. */
+        stop_critical_timings();
 
-        /* Account time spent with enabled wait psw loaded as idle time. */
-        idle_time = int_clock - idle->idle_enter;
-        account_idle_time(idle_time);
-        S390_lowcore.steal_timer +=
-                idle->idle_enter - S390_lowcore.last_update_clock;
-        S390_lowcore.last_update_clock = int_clock;
-
-        /* Account system time spent going idle. */
-        S390_lowcore.system_timer += S390_lowcore.last_update_timer - vq->idle;
-        S390_lowcore.last_update_timer = enter_timer;
-
-        /* Restart vtime CPU timer */
-        if (vq->do_spt) {
-                /* Program old expire value but first save progress. */
-                expires = vq->idle - enter_timer;
-                expires += get_vtimer();
-                set_vtimer(expires);
-        } else {
-                /* Don't account the CPU timer delta while the cpu was idle. */
-                vq->elapsed -= vq->idle - enter_timer;
-        }
+        /* Wait for external, I/O or machine check interrupt. */
+        psw_mask = psw_kernel_bits | PSW_MASK_WAIT | PSW_MASK_DAT |
+                PSW_MASK_IO | PSW_MASK_EXT | PSW_MASK_MCHECK;
+        idle->nohz_delay = 0;
 
+        /* Call the assembler magic in entry.S */
+        psw_idle(idle, vq, psw_mask, !list_empty(&vq->list));
+
+        /* Reenable preemption tracer. */
+        start_critical_timings();
+
+        /* Account time spent with enabled wait psw loaded as idle time. */
         idle->sequence++;
         smp_wmb();
+        idle_time = idle->idle_exit - idle->idle_enter;
         idle->idle_time += idle_time;
-        idle->idle_enter = 0ULL;
+        idle->idle_enter = idle->idle_exit = 0ULL;
         idle->idle_count++;
+        account_idle_time(idle_time);
         smp_wmb();
         idle->sequence++;
 }
 
-void __kprobes vtime_stop_cpu(void)
-{
-        struct s390_idle_data *idle = &__get_cpu_var(s390_idle);
-        struct vtimer_queue *vq = &__get_cpu_var(virt_cpu_timer);
-        psw_t psw;
-
-        /* Wait for external, I/O or machine check interrupt. */
-        psw.mask = psw_kernel_bits | PSW_MASK_WAIT |
-                PSW_MASK_DAT | PSW_MASK_IO | PSW_MASK_EXT | PSW_MASK_MCHECK;
-
-        idle->nohz_delay = 0;
-
-        /* Check if the CPU timer needs to be reprogrammed. */
-        if (vq->do_spt) {
-                __u64 vmax = VTIMER_MAX_SLICE;
-                /*
-                 * The inline assembly is equivalent to
-                 *      vq->idle = get_cpu_timer();
-                 *      set_cpu_timer(VTIMER_MAX_SLICE);
-                 *      idle->idle_enter = get_clock();
-                 *      __load_psw_mask(psw_kernel_bits | PSW_MASK_WAIT |
-                 *                         PSW_MASK_DAT | PSW_MASK_IO |
-                 *                         PSW_MASK_EXT | PSW_MASK_MCHECK);
-                 * The difference is that the inline assembly makes sure that
-                 * the last three instruction are stpt, stck and lpsw in that
-                 * order. This is done to increase the precision.
-                 */
-                asm volatile(
-#ifndef CONFIG_64BIT
-                        "       basr    1,0\n"
-                        "0:     ahi     1,1f-0b\n"
-                        "       st      1,4(%2)\n"
-#else /* CONFIG_64BIT */
-                        "       larl    1,1f\n"
-                        "       stg     1,8(%2)\n"
-#endif /* CONFIG_64BIT */
-                        "       stpt    0(%4)\n"
-                        "       spt     0(%5)\n"
-                        "       stck    0(%3)\n"
-#ifndef CONFIG_64BIT
-                        "       lpsw    0(%2)\n"
-#else /* CONFIG_64BIT */
-                        "       lpswe   0(%2)\n"
-#endif /* CONFIG_64BIT */
-                        "1:"
-                        : "=m" (idle->idle_enter), "=m" (vq->idle)
-                        : "a" (&psw), "a" (&idle->idle_enter),
-                          "a" (&vq->idle), "a" (&vmax), "m" (vmax), "m" (psw)
-                        : "memory", "cc", "1");
-        } else {
-                /*
-                 * The inline assembly is equivalent to
-                 *      vq->idle = get_cpu_timer();
-                 *      idle->idle_enter = get_clock();
-                 *      __load_psw_mask(psw_kernel_bits | PSW_MASK_WAIT |
-                 *                         PSW_MASK_DAT | PSW_MASK_IO |
-                 *                         PSW_MASK_EXT | PSW_MASK_MCHECK);
-                 * The difference is that the inline assembly makes sure that
-                 * the last three instruction are stpt, stck and lpsw in that
-                 * order. This is done to increase the precision.
-                 */
-                asm volatile(
-#ifndef CONFIG_64BIT
-                        "       basr    1,0\n"
-                        "0:     ahi     1,1f-0b\n"
-                        "       st      1,4(%2)\n"
-#else /* CONFIG_64BIT */
-                        "       larl    1,1f\n"
-                        "       stg     1,8(%2)\n"
-#endif /* CONFIG_64BIT */
-                        "       stpt    0(%4)\n"
-                        "       stck    0(%3)\n"
-#ifndef CONFIG_64BIT
-                        "       lpsw    0(%2)\n"
-#else /* CONFIG_64BIT */
-                        "       lpswe   0(%2)\n"
-#endif /* CONFIG_64BIT */
-                        "1:"
-                        : "=m" (idle->idle_enter), "=m" (vq->idle)
-                        : "a" (&psw), "a" (&idle->idle_enter),
-                          "a" (&vq->idle), "m" (psw)
-                        : "memory", "cc", "1");
-        }
-}
-
 cputime64_t s390_get_idle_time(int cpu)
 {
-        struct s390_idle_data *idle;
-        unsigned long long now, idle_time, idle_enter;
+        struct s390_idle_data *idle = &per_cpu(s390_idle, cpu);
+        unsigned long long now, idle_enter, idle_exit;
         unsigned int sequence;
 
-        idle = &per_cpu(s390_idle, cpu);
-
-        now = get_clock();
-repeat:
-        sequence = idle->sequence;
-        smp_rmb();
-        if (sequence & 1)
-                goto repeat;
-        idle_time = 0;
-        idle_enter = idle->idle_enter;
-        if (idle_enter != 0ULL && idle_enter < now)
-                idle_time = now - idle_enter;
-        smp_rmb();
-        if (idle->sequence != sequence)
-                goto repeat;
-        return idle_time;
+        do {
+                now = get_clock();
+                sequence = ACCESS_ONCE(idle->sequence);
+                idle_enter = ACCESS_ONCE(idle->idle_enter);
+                idle_exit = ACCESS_ONCE(idle->idle_exit);
+        } while ((sequence & 1) || (idle->sequence != sequence));
+        return idle_enter ? ((idle_exit ? : now) - idle_enter) : 0;
 }
 
 /*
@@ -319,7 +220,7 @@ static void do_callbacks(struct list_head *cb_list)
 /*
  * Handler for the virtual CPU timer.
  */
-static void do_cpu_timer_interrupt(unsigned int ext_int_code,
+static void do_cpu_timer_interrupt(struct ext_code ext_code,
                                    unsigned int param32, unsigned long param64)
 {
         struct vtimer_queue *vq;
@@ -346,7 +247,6 @@ static void do_cpu_timer_interrupt(unsigned int ext_int_code,
         }
         spin_unlock(&vq->lock);
 
-        vq->do_spt = list_empty(&cb_list);
         do_callbacks(&cb_list);
 
         /* next event is first in list */
@@ -355,8 +255,7 @@ static void do_cpu_timer_interrupt(unsigned int ext_int_code,
         if (!list_empty(&vq->list)) {
                 event = list_first_entry(&vq->list, struct vtimer_list, entry);
                 next = event->expires;
-        } else
-                vq->do_spt = 0;
+        }
         spin_unlock(&vq->lock);
         /*
          * To improve precision add the time spent by the
@@ -570,6 +469,9 @@ void init_cpu_vtimer(void)
 
         /* enable cpu timer interrupts */
         __ctl_set_bit(0,10);
+
+        /* set initial cpu timer */
+        set_vtimer(0x7fffffffffffffffULL);
 }
 
 static int __cpuinit s390_nohz_notify(struct notifier_block *self,
diff --git a/arch/s390/kvm/interrupt.c b/arch/s390/kvm/interrupt.c
index 278ee009ce6..f0647ce6da2 100644
--- a/arch/s390/kvm/interrupt.c
+++ b/arch/s390/kvm/interrupt.c
@@ -134,7 +134,7 @@ static void __do_deliver_interrupt(struct kvm_vcpu *vcpu,
                 if (rc == -EFAULT)
                         exception = 1;
 
-                rc = put_guest_u16(vcpu, __LC_CPU_ADDRESS, inti->emerg.code);
+                rc = put_guest_u16(vcpu, __LC_EXT_CPU_ADDR, inti->emerg.code);
                 if (rc == -EFAULT)
                         exception = 1;
 
@@ -156,7 +156,7 @@ static void __do_deliver_interrupt(struct kvm_vcpu *vcpu,
                 if (rc == -EFAULT)
                         exception = 1;
 
-                rc = put_guest_u16(vcpu, __LC_CPU_ADDRESS, inti->extcall.code);
+                rc = put_guest_u16(vcpu, __LC_EXT_CPU_ADDR, inti->extcall.code);
                 if (rc == -EFAULT)
                         exception = 1;
 
@@ -202,7 +202,7 @@ static void __do_deliver_interrupt(struct kvm_vcpu *vcpu,
                 if (rc == -EFAULT)
                         exception = 1;
 
-                rc = put_guest_u16(vcpu, __LC_CPU_ADDRESS, 0x0d00);
+                rc = put_guest_u16(vcpu, __LC_EXT_CPU_ADDR, 0x0d00);
                 if (rc == -EFAULT)
                         exception = 1;
 
diff --git a/arch/s390/lib/delay.c b/arch/s390/lib/delay.c
index db92f044024..9f1f71e8577 100644
--- a/arch/s390/lib/delay.c
+++ b/arch/s390/lib/delay.c
@@ -13,6 +13,7 @@
 #include <linux/irqflags.h>
 #include <linux/interrupt.h>
 #include <asm/div64.h>
+#include <asm/timer.h>
 
 void __delay(unsigned long loops)
 {
@@ -28,36 +29,33 @@ void __delay(unsigned long loops)
 
 static void __udelay_disabled(unsigned long long usecs)
 {
-        unsigned long mask, cr0, cr0_saved;
-        u64 clock_saved;
-        u64 end;
+        unsigned long cr0, cr6, new;
+        u64 clock_saved, end;
 
-        mask = psw_kernel_bits | PSW_MASK_DAT | PSW_MASK_WAIT |
-                PSW_MASK_EXT | PSW_MASK_MCHECK;
         end = get_clock() + (usecs << 12);
         clock_saved = local_tick_disable();
-        __ctl_store(cr0_saved, 0, 0);
-        cr0 = (cr0_saved & 0xffff00e0) | 0x00000800;
-        __ctl_load(cr0 , 0, 0);
+        __ctl_store(cr0, 0, 0);
+        __ctl_store(cr6, 6, 6);
+        new = (cr0 &  0xffff00e0) | 0x00000800;
+        __ctl_load(new , 0, 0);
+        new = 0;
+        __ctl_load(new, 6, 6);
         lockdep_off();
         do {
                 set_clock_comparator(end);
-                trace_hardirqs_on();
-                __load_psw_mask(mask);
+                vtime_stop_cpu();
                 local_irq_disable();
         } while (get_clock() < end);
         lockdep_on();
-        __ctl_load(cr0_saved, 0, 0);
+        __ctl_load(cr0, 0, 0);
+        __ctl_load(cr6, 6, 6);
         local_tick_enable(clock_saved);
 }
 
 static void __udelay_enabled(unsigned long long usecs)
 {
-        unsigned long mask;
-        u64 clock_saved;
-        u64 end;
+        u64 clock_saved, end;
 
-        mask = psw_kernel_bits | PSW_MASK_WAIT | PSW_MASK_EXT | PSW_MASK_IO;
         end = get_clock() + (usecs << 12);
         do {
                 clock_saved = 0;
@@ -65,8 +63,7 @@ static void __udelay_enabled(unsigned long long usecs)
                         clock_saved = local_tick_disable();
                         set_clock_comparator(end);
                 }
-                trace_hardirqs_on();
-                __load_psw_mask(mask);
+                vtime_stop_cpu();
                 local_irq_disable();
                 if (clock_saved)
                         local_tick_enable(clock_saved);
diff --git a/arch/s390/lib/spinlock.c b/arch/s390/lib/spinlock.c
index 91754ffb920..093eb694d9c 100644
--- a/arch/s390/lib/spinlock.c
+++ b/arch/s390/lib/spinlock.c
@@ -10,6 +10,7 @@
 #include <linux/module.h>
 #include <linux/spinlock.h>
 #include <linux/init.h>
+#include <linux/smp.h>
 #include <asm/io.h>
 
 int spin_retry = 1000;
@@ -24,21 +25,6 @@ static int __init spin_retry_setup(char *str)
 }
 __setup("spin_retry=", spin_retry_setup);
 
-static inline void _raw_yield(void)
-{
-        if (MACHINE_HAS_DIAG44)
-                asm volatile("diag 0,0,0x44");
-}
-
-static inline void _raw_yield_cpu(int cpu)
-{
-        if (MACHINE_HAS_DIAG9C)
-                asm volatile("diag %0,0,0x9c"
-                             : : "d" (cpu_logical_map(cpu)));
-        else
-                _raw_yield();
-}
-
 void arch_spin_lock_wait(arch_spinlock_t *lp)
 {
         int count = spin_retry;
@@ -60,7 +46,7 @@ void arch_spin_lock_wait(arch_spinlock_t *lp)
                 }
                 owner = lp->owner_cpu;
                 if (owner)
-                        _raw_yield_cpu(~owner);
+                        smp_yield_cpu(~owner);
                 if (_raw_compare_and_swap(&lp->owner_cpu, 0, cpu) == 0)
                         return;
         }
@@ -91,7 +77,7 @@ void arch_spin_lock_wait_flags(arch_spinlock_t *lp, unsigned long flags)
                 }
                 owner = lp->owner_cpu;
                 if (owner)
-                        _raw_yield_cpu(~owner);
+                        smp_yield_cpu(~owner);
                 local_irq_disable();
                 if (_raw_compare_and_swap(&lp->owner_cpu, 0, cpu) == 0)
                         return;
@@ -121,7 +107,7 @@ void arch_spin_relax(arch_spinlock_t *lock)
         if (cpu != 0) {
                 if (MACHINE_IS_VM || MACHINE_IS_KVM ||
                     !smp_vcpu_scheduled(~cpu))
-                        _raw_yield_cpu(~cpu);
+                        smp_yield_cpu(~cpu);
         }
 }
 EXPORT_SYMBOL(arch_spin_relax);
@@ -133,7 +119,7 @@ void _raw_read_lock_wait(arch_rwlock_t *rw)
 
         while (1) {
                 if (count-- <= 0) {
-                        _raw_yield();
+                        smp_yield();
                         count = spin_retry;
                 }
                 if (!arch_read_can_lock(rw))
@@ -153,7 +139,7 @@ void _raw_read_lock_wait_flags(arch_rwlock_t *rw, unsigned long flags)
         local_irq_restore(flags);
         while (1) {
                 if (count-- <= 0) {
-                        _raw_yield();
+                        smp_yield();
                         count = spin_retry;
                 }
                 if (!arch_read_can_lock(rw))
@@ -188,7 +174,7 @@ void _raw_write_lock_wait(arch_rwlock_t *rw)
 
         while (1) {
                 if (count-- <= 0) {
-                        _raw_yield();
+                        smp_yield();
                         count = spin_retry;
                 }
                 if (!arch_write_can_lock(rw))
@@ -206,7 +192,7 @@ void _raw_write_lock_wait_flags(arch_rwlock_t *rw, unsigned long flags)
         local_irq_restore(flags);
         while (1) {
                 if (count-- <= 0) {
-                        _raw_yield();
+                        smp_yield();
                         count = spin_retry;
                 }
                 if (!arch_write_can_lock(rw))
diff --git a/arch/s390/mm/fault.c b/arch/s390/mm/fault.c
index e8fcd928dc7..b17c42df61c 100644
--- a/arch/s390/mm/fault.c
+++ b/arch/s390/mm/fault.c
@@ -532,7 +532,7 @@ void pfault_fini(void)
 static DEFINE_SPINLOCK(pfault_lock);
 static LIST_HEAD(pfault_list);
 
-static void pfault_interrupt(unsigned int ext_int_code,
+static void pfault_interrupt(struct ext_code ext_code,
                              unsigned int param32, unsigned long param64)
 {
         struct task_struct *tsk;
@@ -545,7 +545,7 @@ static void pfault_interrupt(unsigned int ext_int_code,
          * in the 'cpu address' field associated with the
          * external interrupt. 
          */
-        subcode = ext_int_code >> 16;
+        subcode = ext_code.subcode;
         if ((subcode & 0xff00) != __SUBCODE_MASK)
                 return;
         kstat_cpu(smp_processor_id()).irqs[EXTINT_PFL]++;
diff --git a/arch/s390/oprofile/hwsampler.c b/arch/s390/oprofile/hwsampler.c
index 9daee91e6c3..12bea05a0fc 100644
--- a/arch/s390/oprofile/hwsampler.c
+++ b/arch/s390/oprofile/hwsampler.c
@@ -233,8 +233,8 @@ static inline unsigned long *trailer_entry_ptr(unsigned long v)
 }
 
 /* prototypes for external interrupt handler and worker */
-static void hws_ext_handler(unsigned int ext_int_code,
-                                unsigned int param32, unsigned long param64);
+static void hws_ext_handler(struct ext_code ext_code,
+                            unsigned int param32, unsigned long param64);
 
 static void worker(struct work_struct *work);
 
@@ -673,7 +673,7 @@ int hwsampler_activate(unsigned int cpu)
         return rc;
 }
 
-static void hws_ext_handler(unsigned int ext_int_code,
+static void hws_ext_handler(struct ext_code ext_code,
                             unsigned int param32, unsigned long param64)
 {
         struct hws_cpu_buffer *cb;
diff --git a/arch/sh/boards/mach-ap325rxa/setup.c b/arch/sh/boards/mach-ap325rxa/setup.c
index ebd0f818a25..8cf02e34333 100644
--- a/arch/sh/boards/mach-ap325rxa/setup.c
+++ b/arch/sh/boards/mach-ap325rxa/setup.c
@@ -157,7 +157,7 @@ static struct platform_device nand_flash_device = {
 #define PORT_DRVCRA     0xA405018A
 #define PORT_DRVCRB     0xA405018C
 
-static int ap320_wvga_set_brightness(void *board_data, int brightness)
+static int ap320_wvga_set_brightness(int brightness)
 {
         if (brightness) {
                 gpio_set_value(GPIO_PTS3, 0);
@@ -170,12 +170,12 @@ static int ap320_wvga_set_brightness(void *board_data, int brightness)
         return 0;
 }
 
-static int ap320_wvga_get_brightness(void *board_data)
+static int ap320_wvga_get_brightness(void)
 {
         return gpio_get_value(GPIO_PTS3);
 }
 
-static void ap320_wvga_power_on(void *board_data, struct fb_info *info)
+static void ap320_wvga_power_on(void)
 {
         msleep(100);
 
@@ -183,7 +183,7 @@ static void ap320_wvga_power_on(void *board_data, struct fb_info *info)
         __raw_writew(FPGA_LCDREG_VAL, FPGA_LCDREG);
 }
 
-static void ap320_wvga_power_off(void *board_data)
+static void ap320_wvga_power_off(void)
 {
         /* ASD AP-320/325 LCD OFF */
         __raw_writew(0, FPGA_LCDREG);
@@ -211,21 +211,19 @@ static struct sh_mobile_lcdc_info lcdc_info = {
                 .fourcc = V4L2_PIX_FMT_RGB565,
                 .interface_type = RGB18,
                 .clock_divider = 1,
-                .lcd_cfg = ap325rxa_lcdc_modes,
-                .num_cfg = ARRAY_SIZE(ap325rxa_lcdc_modes),
-                .lcd_size_cfg = { /* 7.0 inch */
-                        .width = 152,
+                .lcd_modes = ap325rxa_lcdc_modes,
+                .num_modes = ARRAY_SIZE(ap325rxa_lcdc_modes),
+                .panel_cfg = {
+                        .width = 152,   /* 7.0 inch */
                         .height = 91,
-                },
-                .board_cfg = {
                         .display_on = ap320_wvga_power_on,
                         .display_off = ap320_wvga_power_off,
-                        .set_brightness = ap320_wvga_set_brightness,
-                        .get_brightness = ap320_wvga_get_brightness,
                 },
                 .bl_info = {
                         .name = "sh_mobile_lcdc_bl",
                         .max_brightness = 1,
+                        .set_brightness = ap320_wvga_set_brightness,
+                        .get_brightness = ap320_wvga_get_brightness,
                 },
         }
 };
diff --git a/arch/sh/boards/mach-ecovec24/setup.c b/arch/sh/boards/mach-ecovec24/setup.c
index cde7c0085ce..e5ac12b2ce6 100644
--- a/arch/sh/boards/mach-ecovec24/setup.c
+++ b/arch/sh/boards/mach-ecovec24/setup.c
@@ -310,14 +310,14 @@ static const struct fb_videomode ecovec_dvi_modes[] = {
         },
 };
 
-static int ecovec24_set_brightness(void *board_data, int brightness)
+static int ecovec24_set_brightness(int brightness)
 {
         gpio_set_value(GPIO_PTR1, brightness);
 
         return 0;
 }
 
-static int ecovec24_get_brightness(void *board_data)
+static int ecovec24_get_brightness(void)
 {
         return gpio_get_value(GPIO_PTR1);
 }
@@ -327,17 +327,15 @@ static struct sh_mobile_lcdc_info lcdc_info = {
                 .interface_type = RGB18,
                 .chan = LCDC_CHAN_MAINLCD,
                 .fourcc = V4L2_PIX_FMT_RGB565,
-                .lcd_size_cfg = { /* 7.0 inch */
+                .panel_cfg = { /* 7.0 inch */
                         .width = 152,
                         .height = 91,
                 },
-                .board_cfg = {
-                        .set_brightness = ecovec24_set_brightness,
-                        .get_brightness = ecovec24_get_brightness,
-                },
                 .bl_info = {
                         .name = "sh_mobile_lcdc_bl",
                         .max_brightness = 1,
+                        .set_brightness = ecovec24_set_brightness,
+                        .get_brightness = ecovec24_get_brightness,
                 },
         }
 };
@@ -769,7 +767,9 @@ static struct platform_device camera_devices[] = {
 
 /* FSI */
 static struct sh_fsi_platform_info fsi_info = {
-        .portb_flags = SH_FSI_BRS_INV,
+        .port_b = {
+                .flags = SH_FSI_BRS_INV,
+        },
 };
 
 static struct resource fsi_resources[] = {
@@ -1116,8 +1116,8 @@ static int __init arch_setup(void)
                 /* DVI */
                 lcdc_info.clock_source                  = LCDC_CLK_EXTERNAL;
                 lcdc_info.ch[0].clock_divider           = 1;
-                lcdc_info.ch[0].lcd_cfg                 = ecovec_dvi_modes;
-                lcdc_info.ch[0].num_cfg                 = ARRAY_SIZE(ecovec_dvi_modes);
+                lcdc_info.ch[0].lcd_modes               = ecovec_dvi_modes;
+                lcdc_info.ch[0].num_modes               = ARRAY_SIZE(ecovec_dvi_modes);
 
                 gpio_set_value(GPIO_PTA2, 1);
                 gpio_set_value(GPIO_PTU1, 1);
@@ -1125,8 +1125,8 @@ static int __init arch_setup(void)
                 /* Panel */
                 lcdc_info.clock_source                  = LCDC_CLK_PERIPHERAL;
                 lcdc_info.ch[0].clock_divider           = 2;
-                lcdc_info.ch[0].lcd_cfg                 = ecovec_lcd_modes;
-                lcdc_info.ch[0].num_cfg                 = ARRAY_SIZE(ecovec_lcd_modes);
+                lcdc_info.ch[0].lcd_modes               = ecovec_lcd_modes;
+                lcdc_info.ch[0].num_modes               = ARRAY_SIZE(ecovec_lcd_modes);
 
                 gpio_set_value(GPIO_PTR1, 1);
 
diff --git a/arch/sh/boards/mach-highlander/setup.c b/arch/sh/boards/mach-highlander/setup.c
index 74b8db1b74a..4a52590fe3d 100644
--- a/arch/sh/boards/mach-highlander/setup.c
+++ b/arch/sh/boards/mach-highlander/setup.c
@@ -322,7 +322,7 @@ static void ivdr_clk_disable(struct clk *clk)
         __raw_writew(__raw_readw(PA_IVDRCTL) & ~(1 << IVDR_CK_ON), PA_IVDRCTL);
 }
 
-static struct clk_ops ivdr_clk_ops = {
+static struct sh_clk_ops ivdr_clk_ops = {
         .enable         = ivdr_clk_enable,
         .disable        = ivdr_clk_disable,
 };
diff --git a/arch/sh/boards/mach-kfr2r09/lcd_wqvga.c b/arch/sh/boards/mach-kfr2r09/lcd_wqvga.c
index 25e145fb708..c148b36ecb6 100644
--- a/arch/sh/boards/mach-kfr2r09/lcd_wqvga.c
+++ b/arch/sh/boards/mach-kfr2r09/lcd_wqvga.c
@@ -251,8 +251,7 @@ static void display_on(void *sohandle,
         write_memory_start(sohandle, so);
 }
 
-int kfr2r09_lcd_setup(void *board_data, void *sohandle,
-                      struct sh_mobile_lcdc_sys_bus_ops *so)
+int kfr2r09_lcd_setup(void *sohandle, struct sh_mobile_lcdc_sys_bus_ops *so)
 {
         /* power on */
         gpio_set_value(GPIO_PTF4, 0);  /* PROTECT/ -> L */
@@ -273,8 +272,7 @@ int kfr2r09_lcd_setup(void *board_data, void *sohandle,
         return 0;
 }
 
-void kfr2r09_lcd_start(void *board_data, void *sohandle,
-                       struct sh_mobile_lcdc_sys_bus_ops *so)
+void kfr2r09_lcd_start(void *sohandle, struct sh_mobile_lcdc_sys_bus_ops *so)
 {
         write_memory_start(sohandle, so);
 }
@@ -327,12 +325,12 @@ static int kfr2r09_lcd_backlight(int on)
         return 0;
 }
 
-void kfr2r09_lcd_on(void *board_data, struct fb_info *info)
+void kfr2r09_lcd_on(void)
 {
         kfr2r09_lcd_backlight(1);
 }
 
-void kfr2r09_lcd_off(void *board_data)
+void kfr2r09_lcd_off(void)
 {
         kfr2r09_lcd_backlight(0);
 }
diff --git a/arch/sh/boards/mach-kfr2r09/setup.c b/arch/sh/boards/mach-kfr2r09/setup.c
index 5b382e1afae..d04a55d3b87 100644
--- a/arch/sh/boards/mach-kfr2r09/setup.c
+++ b/arch/sh/boards/mach-kfr2r09/setup.c
@@ -148,13 +148,11 @@ static struct sh_mobile_lcdc_info kfr2r09_sh_lcdc_info = {
                 .interface_type = SYS18,
                 .clock_divider = 6,
                 .flags = LCDC_FLAGS_DWPOL,
-                .lcd_cfg = kfr2r09_lcdc_modes,
-                .num_cfg = ARRAY_SIZE(kfr2r09_lcdc_modes),
-                .lcd_size_cfg = {
+                .lcd_modes = kfr2r09_lcdc_modes,
+                .num_modes = ARRAY_SIZE(kfr2r09_lcdc_modes),
+                .panel_cfg = {
                         .width = 35,
                         .height = 58,
-                },
-                .board_cfg = {
                         .setup_sys = kfr2r09_lcd_setup,
                         .start_transfer = kfr2r09_lcd_start,
                         .display_on = kfr2r09_lcd_on,
diff --git a/arch/sh/boards/mach-migor/lcd_qvga.c b/arch/sh/boards/mach-migor/lcd_qvga.c
index de9014a8a93..8bccd345b69 100644
--- a/arch/sh/boards/mach-migor/lcd_qvga.c
+++ b/arch/sh/boards/mach-migor/lcd_qvga.c
@@ -113,8 +113,7 @@ static const unsigned short magic3_data[] = {
         0x0010, 0x16B0, 0x0011, 0x0111, 0x0007, 0x0061,
 };
 
-int migor_lcd_qvga_setup(void *board_data, void *sohandle,
-                         struct sh_mobile_lcdc_sys_bus_ops *so)
+int migor_lcd_qvga_setup(void *sohandle, struct sh_mobile_lcdc_sys_bus_ops *so)
 {
         unsigned long xres = 320;
         unsigned long yres = 240;
diff --git a/arch/sh/boards/mach-migor/setup.c b/arch/sh/boards/mach-migor/setup.c
index d37ba272052..ff6f69c6906 100644
--- a/arch/sh/boards/mach-migor/setup.c
+++ b/arch/sh/boards/mach-migor/setup.c
@@ -246,9 +246,9 @@ static struct sh_mobile_lcdc_info sh_mobile_lcdc_info = {
                 .fourcc = V4L2_PIX_FMT_RGB565,
                 .interface_type = RGB16,
                 .clock_divider = 2,
-                .lcd_cfg = migor_lcd_modes,
-                .num_cfg = ARRAY_SIZE(migor_lcd_modes),
-                .lcd_size_cfg = { /* 7.0 inch */
+                .lcd_modes = migor_lcd_modes,
+                .num_modes = ARRAY_SIZE(migor_lcd_modes),
+                .panel_cfg = { /* 7.0 inch */
                         .width = 152,
                         .height = 91,
                 },
@@ -260,13 +260,11 @@ static struct sh_mobile_lcdc_info sh_mobile_lcdc_info = {
                 .fourcc = V4L2_PIX_FMT_RGB565,
                 .interface_type = SYS16A,
                 .clock_divider = 10,
-                .lcd_cfg = migor_lcd_modes,
-                .num_cfg = ARRAY_SIZE(migor_lcd_modes),
-                .lcd_size_cfg = { /* 2.4 inch */
-                        .width = 49,
+                .lcd_modes = migor_lcd_modes,
+                .num_modes = ARRAY_SIZE(migor_lcd_modes),
+                .panel_cfg = {
+                        .width = 49,    /* 2.4 inch */
                         .height = 37,
-                },
-                .board_cfg = {
                         .setup_sys = migor_lcd_qvga_setup,
                 },
                 .sys_bus_cfg = {
diff --git a/arch/sh/boards/mach-sdk7786/setup.c b/arch/sh/boards/mach-sdk7786/setup.c
index 486d1ac3694..27a2314f50a 100644
--- a/arch/sh/boards/mach-sdk7786/setup.c
+++ b/arch/sh/boards/mach-sdk7786/setup.c
@@ -167,7 +167,7 @@ static void sdk7786_pcie_clk_disable(struct clk *clk)
         fpga_write_reg(fpga_read_reg(PCIECR) & ~PCIECR_CLKEN, PCIECR);
 }
 
-static struct clk_ops sdk7786_pcie_clk_ops = {
+static struct sh_clk_ops sdk7786_pcie_clk_ops = {
         .enable         = sdk7786_pcie_clk_enable,
         .disable        = sdk7786_pcie_clk_disable,
 };
diff --git a/arch/sh/boards/mach-se/7724/setup.c b/arch/sh/boards/mach-se/7724/setup.c
index 2b07fc01695..c540b16547c 100644
--- a/arch/sh/boards/mach-se/7724/setup.c
+++ b/arch/sh/boards/mach-se/7724/setup.c
@@ -182,12 +182,10 @@ static struct sh_mobile_lcdc_info lcdc_info = {
                 .chan = LCDC_CHAN_MAINLCD,
                 .fourcc = V4L2_PIX_FMT_RGB565,
                 .clock_divider = 1,
-                .lcd_size_cfg = { /* 7.0 inch */
+                .panel_cfg = { /* 7.0 inch */
                         .width = 152,
                         .height = 91,
                 },
-                .board_cfg = {
-                },
         }
 };
 
@@ -278,7 +276,9 @@ static struct platform_device ceu1_device = {
 /* FSI */
 /* change J20, J21, J22 pin to 1-2 connection to use slave mode */
 static struct sh_fsi_platform_info fsi_info = {
-        .porta_flags = SH_FSI_BRS_INV,
+        .port_a = {
+                .flags = SH_FSI_BRS_INV,
+        },
 };
 
 static struct resource fsi_resources[] = {
@@ -888,12 +888,12 @@ static int __init devices_setup(void)
 
         if (sw & SW41_B) {
                 /* 720p */
-                lcdc_info.ch[0].lcd_cfg = lcdc_720p_modes;
-                lcdc_info.ch[0].num_cfg = ARRAY_SIZE(lcdc_720p_modes);
+                lcdc_info.ch[0].lcd_modes = lcdc_720p_modes;
+                lcdc_info.ch[0].num_modes = ARRAY_SIZE(lcdc_720p_modes);
         } else {
                 /* VGA */
-                lcdc_info.ch[0].lcd_cfg = lcdc_vga_modes;
-                lcdc_info.ch[0].num_cfg = ARRAY_SIZE(lcdc_vga_modes);
+                lcdc_info.ch[0].lcd_modes = lcdc_vga_modes;
+                lcdc_info.ch[0].num_modes = ARRAY_SIZE(lcdc_vga_modes);
         }
 
         if (sw & SW41_A) {
diff --git a/arch/sh/drivers/pci/pci.c b/arch/sh/drivers/pci/pci.c
index 1e7b0e2e764..9d10a3cb879 100644
--- a/arch/sh/drivers/pci/pci.c
+++ b/arch/sh/drivers/pci/pci.c
@@ -37,11 +37,20 @@ static void __devinit pcibios_scanbus(struct pci_channel *hose)
         static int next_busno;
         static int need_domain_info;
         LIST_HEAD(resources);
+        struct resource *res;
+        resource_size_t offset;
         int i;
         struct pci_bus *bus;
 
-        for (i = 0; i < hose->nr_resources; i++)
-                pci_add_resource(&resources, hose->resources + i);
+        for (i = 0; i < hose->nr_resources; i++) {
+                res = hose->resources + i;
+                offset = 0;
+                if (res->flags & IORESOURCE_IO)
+                        offset = hose->io_offset;
+                else if (res->flags & IORESOURCE_MEM)
+                        offset = hose->mem_offset;
+                pci_add_resource_offset(&resources, res, offset);
+        }
 
         bus = pci_scan_root_bus(NULL, next_busno, hose->pci_ops, hose,
                                 &resources);
@@ -143,42 +152,12 @@ static int __init pcibios_init(void)
 }
 subsys_initcall(pcibios_init);
 
-static void pcibios_fixup_device_resources(struct pci_dev *dev,
-        struct pci_bus *bus)
-{
-        /* Update device resources.  */
-        struct pci_channel *hose = bus->sysdata;
-        unsigned long offset = 0;
-        int i;
-
-        for (i = 0; i < PCI_NUM_RESOURCES; i++) {
-                if (!dev->resource[i].start)
-                        continue;
-                if (dev->resource[i].flags & IORESOURCE_IO)
-                        offset = hose->io_offset;
-                else if (dev->resource[i].flags & IORESOURCE_MEM)
-                        offset = hose->mem_offset;
-
-                dev->resource[i].start += offset;
-                dev->resource[i].end += offset;
-        }
-}
-
 /*
  *  Called after each bus is probed, but before its children
  *  are examined.
  */
 void __devinit pcibios_fixup_bus(struct pci_bus *bus)
 {
-        struct pci_dev *dev;
-        struct list_head *ln;
-
-        for (ln = bus->devices.next; ln != &bus->devices; ln = ln->next) {
-                dev = pci_dev_b(ln);
-
-                if ((dev->class >> 8) != PCI_CLASS_BRIDGE_PCI)
-                        pcibios_fixup_device_resources(dev, bus);
-        }
 }
 
 /*
@@ -208,36 +187,6 @@ resource_size_t pcibios_align_resource(void *data, const struct resource *res,
         return start;
 }
 
-void pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
-                             struct resource *res)
-{
-        struct pci_channel *hose = dev->sysdata;
-        unsigned long offset = 0;
-
-        if (res->flags & IORESOURCE_IO)
-                offset = hose->io_offset;
-        else if (res->flags & IORESOURCE_MEM)
-                offset = hose->mem_offset;
-
-        region->start = res->start - offset;
-        region->end = res->end - offset;
-}
-
-void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
-                             struct pci_bus_region *region)
-{
-        struct pci_channel *hose = dev->sysdata;
-        unsigned long offset = 0;
-
-        if (res->flags & IORESOURCE_IO)
-                offset = hose->io_offset;
-        else if (res->flags & IORESOURCE_MEM)
-                offset = hose->mem_offset;
-
-        res->start = region->start + offset;
-        res->end = region->end + offset;
-}
-
 int pcibios_enable_device(struct pci_dev *dev, int mask)
 {
         return pci_enable_resources(dev, mask);
@@ -381,8 +330,6 @@ EXPORT_SYMBOL(pci_iounmap);
 #endif /* CONFIG_GENERIC_IOMAP */
 
 #ifdef CONFIG_HOTPLUG
-EXPORT_SYMBOL(pcibios_resource_to_bus);
-EXPORT_SYMBOL(pcibios_bus_to_resource);
 EXPORT_SYMBOL(PCIBIOS_MIN_IO);
 EXPORT_SYMBOL(PCIBIOS_MIN_MEM);
 #endif
diff --git a/arch/sh/include/asm/clock.h b/arch/sh/include/asm/clock.h
index 803d4c7f09d..0390a07e7e3 100644
--- a/arch/sh/include/asm/clock.h
+++ b/arch/sh/include/asm/clock.h
@@ -4,7 +4,7 @@
 #include <linux/sh_clk.h>
 
 /* Should be defined by processor-specific code */
-void __deprecated arch_init_clk_ops(struct clk_ops **, int type);
+void __deprecated arch_init_clk_ops(struct sh_clk_ops **, int type);
 int __init arch_clk_init(void);
 
 /* arch/sh/kernel/cpu/clock-cpg.c */
diff --git a/arch/sh/include/asm/pci.h b/arch/sh/include/asm/pci.h
index cb21e2399dc..bff96c2e7d2 100644
--- a/arch/sh/include/asm/pci.h
+++ b/arch/sh/include/asm/pci.h
@@ -114,12 +114,6 @@ static inline void pci_dma_burst_advice(struct pci_dev *pdev,
 /* Board-specific fixup routines. */
 int pcibios_map_platform_irq(const struct pci_dev *dev, u8 slot, u8 pin);
 
-extern void pcibios_resource_to_bus(struct pci_dev *dev,
-        struct pci_bus_region *region, struct resource *res);
-
-extern void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
-                                    struct pci_bus_region *region);
-
 #define pci_domain_nr(bus) ((struct pci_channel *)(bus)->sysdata)->index
 
 static inline int pci_proc_domain(struct pci_bus *bus)
diff --git a/arch/sh/include/mach-kfr2r09/mach/kfr2r09.h b/arch/sh/include/mach-kfr2r09/mach/kfr2r09.h
index 07e635b0e04..ba3d93d333f 100644
--- a/arch/sh/include/mach-kfr2r09/mach/kfr2r09.h
+++ b/arch/sh/include/mach-kfr2r09/mach/kfr2r09.h
@@ -4,21 +4,21 @@
 #include <video/sh_mobile_lcdc.h>
 
 #if defined(CONFIG_FB_SH_MOBILE_LCDC) || defined(CONFIG_FB_SH_MOBILE_LCDC_MODULE)
-void kfr2r09_lcd_on(void *board_data, struct fb_info *info);
-void kfr2r09_lcd_off(void *board_data);
-int kfr2r09_lcd_setup(void *board_data, void *sys_ops_handle,
+void kfr2r09_lcd_on(void);
+void kfr2r09_lcd_off(void);
+int kfr2r09_lcd_setup(void *sys_ops_handle,
                       struct sh_mobile_lcdc_sys_bus_ops *sys_ops);
-void kfr2r09_lcd_start(void *board_data, void *sys_ops_handle,
+void kfr2r09_lcd_start(void *sys_ops_handle,
                        struct sh_mobile_lcdc_sys_bus_ops *sys_ops);
 #else
-static void kfr2r09_lcd_on(void *board_data) {}
-static void kfr2r09_lcd_off(void *board_data) {}
-static int kfr2r09_lcd_setup(void *board_data, void *sys_ops_handle,
+static void kfr2r09_lcd_on(void) {}
+static void kfr2r09_lcd_off(void) {}
+static int kfr2r09_lcd_setup(void *sys_ops_handle,
                                 struct sh_mobile_lcdc_sys_bus_ops *sys_ops)
 {
         return -ENODEV;
 }
-static void kfr2r09_lcd_start(void *board_data, void *sys_ops_handle,
+static void kfr2r09_lcd_start(void *sys_ops_handle,
                                 struct sh_mobile_lcdc_sys_bus_ops *sys_ops)
 {
 }
diff --git a/arch/sh/include/mach-migor/mach/migor.h b/arch/sh/include/mach-migor/mach/migor.h
index 42fccf93412..7de7bb74c29 100644
--- a/arch/sh/include/mach-migor/mach/migor.h
+++ b/arch/sh/include/mach-migor/mach/migor.h
@@ -9,7 +9,7 @@
 
 #include <video/sh_mobile_lcdc.h>
 
-int migor_lcd_qvga_setup(void *board_data, void *sys_ops_handle,
+int migor_lcd_qvga_setup(void *sys_ops_handle,
                          struct sh_mobile_lcdc_sys_bus_ops *sys_ops);
 
 #endif /* __ASM_SH_MIGOR_H */
diff --git a/arch/sh/kernel/cpu/sh2/clock-sh7619.c b/arch/sh/kernel/cpu/sh2/clock-sh7619.c
index 5b7f12e58a8..e80252ae5bc 100644
--- a/arch/sh/kernel/cpu/sh2/clock-sh7619.c
+++ b/arch/sh/kernel/cpu/sh2/clock-sh7619.c
@@ -28,7 +28,7 @@ static void master_clk_init(struct clk *clk)
         clk->rate *= pll2_mult * pll1rate[(__raw_readw(FREQCR) >> 8) & 7];
 }
 
-static struct clk_ops sh7619_master_clk_ops = {
+static struct sh_clk_ops sh7619_master_clk_ops = {
         .init           = master_clk_init,
 };
 
@@ -38,7 +38,7 @@ static unsigned long module_clk_recalc(struct clk *clk)
         return clk->parent->rate / pfc_divisors[idx];
 }
 
-static struct clk_ops sh7619_module_clk_ops = {
+static struct sh_clk_ops sh7619_module_clk_ops = {
         .recalc         = module_clk_recalc,
 };
 
@@ -47,22 +47,22 @@ static unsigned long bus_clk_recalc(struct clk *clk)
         return clk->parent->rate / pll1rate[(__raw_readw(FREQCR) >> 8) & 7];
 }
 
-static struct clk_ops sh7619_bus_clk_ops = {
+static struct sh_clk_ops sh7619_bus_clk_ops = {
         .recalc         = bus_clk_recalc,
 };
 
-static struct clk_ops sh7619_cpu_clk_ops = {
+static struct sh_clk_ops sh7619_cpu_clk_ops = {
         .recalc         = followparent_recalc,
 };
 
-static struct clk_ops *sh7619_clk_ops[] = {
+static struct sh_clk_ops *sh7619_clk_ops[] = {
         &sh7619_master_clk_ops,
         &sh7619_module_clk_ops,
         &sh7619_bus_clk_ops,
         &sh7619_cpu_clk_ops,
 };
 
-void __init arch_init_clk_ops(struct clk_ops **ops, int idx)
+void __init arch_init_clk_ops(struct sh_clk_ops **ops, int idx)
 {
         if (test_mode_pin(MODE_PIN2 | MODE_PIN0) ||
             test_mode_pin(MODE_PIN2 | MODE_PIN1))
diff --git a/arch/sh/kernel/cpu/sh2a/clock-sh7201.c b/arch/sh/kernel/cpu/sh2a/clock-sh7201.c
index 1174e2d96c0..532a36c7232 100644
--- a/arch/sh/kernel/cpu/sh2a/clock-sh7201.c
+++ b/arch/sh/kernel/cpu/sh2a/clock-sh7201.c
@@ -30,7 +30,7 @@ static void master_clk_init(struct clk *clk)
                pll1rate[(__raw_readw(FREQCR) >> 8) & 0x0007];
 }
 
-static struct clk_ops sh7201_master_clk_ops = {
+static struct sh_clk_ops sh7201_master_clk_ops = {
         .init           = master_clk_init,
 };
 
@@ -40,7 +40,7 @@ static unsigned long module_clk_recalc(struct clk *clk)
         return clk->parent->rate / pfc_divisors[idx];
 }
 
-static struct clk_ops sh7201_module_clk_ops = {
+static struct sh_clk_ops sh7201_module_clk_ops = {
         .recalc         = module_clk_recalc,
 };
 
@@ -50,7 +50,7 @@ static unsigned long bus_clk_recalc(struct clk *clk)
         return clk->parent->rate / pfc_divisors[idx];
 }
 
-static struct clk_ops sh7201_bus_clk_ops = {
+static struct sh_clk_ops sh7201_bus_clk_ops = {
         .recalc         = bus_clk_recalc,
 };
 
@@ -60,18 +60,18 @@ static unsigned long cpu_clk_recalc(struct clk *clk)
         return clk->parent->rate / ifc_divisors[idx];
 }
 
-static struct clk_ops sh7201_cpu_clk_ops = {
+static struct sh_clk_ops sh7201_cpu_clk_ops = {
         .recalc         = cpu_clk_recalc,
 };
 
-static struct clk_ops *sh7201_clk_ops[] = {
+static struct sh_clk_ops *sh7201_clk_ops[] = {
         &sh7201_master_clk_ops,
         &sh7201_module_clk_ops,
         &sh7201_bus_clk_ops,
         &sh7201_cpu_clk_ops,
 };
 
-void __init arch_init_clk_ops(struct clk_ops **ops, int idx)
+void __init arch_init_clk_ops(struct sh_clk_ops **ops, int idx)
 {
         if (test_mode_pin(MODE_PIN1 | MODE_PIN0))
                 pll2_mult = 1;
diff --git a/arch/sh/kernel/cpu/sh2a/clock-sh7203.c b/arch/sh/kernel/cpu/sh2a/clock-sh7203.c
index 95a008e8b73..529f719b6e3 100644
--- a/arch/sh/kernel/cpu/sh2a/clock-sh7203.c
+++ b/arch/sh/kernel/cpu/sh2a/clock-sh7203.c
@@ -32,7 +32,7 @@ static void master_clk_init(struct clk *clk)
         clk->rate *= pll1rate[(__raw_readw(FREQCR) >> 8) & 0x0003] * pll2_mult;
 }
 
-static struct clk_ops sh7203_master_clk_ops = {
+static struct sh_clk_ops sh7203_master_clk_ops = {
         .init           = master_clk_init,
 };
 
@@ -42,7 +42,7 @@ static unsigned long module_clk_recalc(struct clk *clk)
         return clk->parent->rate / pfc_divisors[idx];
 }
 
-static struct clk_ops sh7203_module_clk_ops = {
+static struct sh_clk_ops sh7203_module_clk_ops = {
         .recalc         = module_clk_recalc,
 };
 
@@ -52,22 +52,22 @@ static unsigned long bus_clk_recalc(struct clk *clk)
         return clk->parent->rate / pfc_divisors[idx-2];
 }
 
-static struct clk_ops sh7203_bus_clk_ops = {
+static struct sh_clk_ops sh7203_bus_clk_ops = {
         .recalc         = bus_clk_recalc,
 };
 
-static struct clk_ops sh7203_cpu_clk_ops = {
+static struct sh_clk_ops sh7203_cpu_clk_ops = {
         .recalc         = followparent_recalc,
 };
 
-static struct clk_ops *sh7203_clk_ops[] = {
+static struct sh_clk_ops *sh7203_clk_ops[] = {
         &sh7203_master_clk_ops,
         &sh7203_module_clk_ops,
         &sh7203_bus_clk_ops,
         &sh7203_cpu_clk_ops,
 };
 
-void __init arch_init_clk_ops(struct clk_ops **ops, int idx)
+void __init arch_init_clk_ops(struct sh_clk_ops **ops, int idx)
 {
         if (test_mode_pin(MODE_PIN1))
                 pll2_mult = 4;
diff --git a/arch/sh/kernel/cpu/sh2a/clock-sh7206.c b/arch/sh/kernel/cpu/sh2a/clock-sh7206.c
index 3c314d7cd6e..17778983467 100644
--- a/arch/sh/kernel/cpu/sh2a/clock-sh7206.c
+++ b/arch/sh/kernel/cpu/sh2a/clock-sh7206.c
@@ -29,7 +29,7 @@ static void master_clk_init(struct clk *clk)
         clk->rate *= pll2_mult * pll1rate[(__raw_readw(FREQCR) >> 8) & 0x0007];
 }
 
-static struct clk_ops sh7206_master_clk_ops = {
+static struct sh_clk_ops sh7206_master_clk_ops = {
         .init           = master_clk_init,
 };
 
@@ -39,7 +39,7 @@ static unsigned long module_clk_recalc(struct clk *clk)
         return clk->parent->rate / pfc_divisors[idx];
 }
 
-static struct clk_ops sh7206_module_clk_ops = {
+static struct sh_clk_ops sh7206_module_clk_ops = {
         .recalc         = module_clk_recalc,
 };
 
@@ -48,7 +48,7 @@ static unsigned long bus_clk_recalc(struct clk *clk)
         return clk->parent->rate / pll1rate[(__raw_readw(FREQCR) >> 8) & 0x0007];
 }
 
-static struct clk_ops sh7206_bus_clk_ops = {
+static struct sh_clk_ops sh7206_bus_clk_ops = {
         .recalc         = bus_clk_recalc,
 };
 
@@ -58,18 +58,18 @@ static unsigned long cpu_clk_recalc(struct clk *clk)
         return clk->parent->rate / ifc_divisors[idx];
 }
 
-static struct clk_ops sh7206_cpu_clk_ops = {
+static struct sh_clk_ops sh7206_cpu_clk_ops = {
         .recalc         = cpu_clk_recalc,
 };
 
-static struct clk_ops *sh7206_clk_ops[] = {
+static struct sh_clk_ops *sh7206_clk_ops[] = {
         &sh7206_master_clk_ops,
         &sh7206_module_clk_ops,
         &sh7206_bus_clk_ops,
         &sh7206_cpu_clk_ops,
 };
 
-void __init arch_init_clk_ops(struct clk_ops **ops, int idx)
+void __init arch_init_clk_ops(struct sh_clk_ops **ops, int idx)
 {
         if (test_mode_pin(MODE_PIN2 | MODE_PIN1 | MODE_PIN0))
                 pll2_mult = 1;
diff --git a/arch/sh/kernel/cpu/sh3/clock-sh3.c b/arch/sh/kernel/cpu/sh3/clock-sh3.c
index b78384afac0..90faa44ca94 100644
--- a/arch/sh/kernel/cpu/sh3/clock-sh3.c
+++ b/arch/sh/kernel/cpu/sh3/clock-sh3.c
@@ -34,7 +34,7 @@ static void master_clk_init(struct clk *clk)
         clk->rate *= pfc_divisors[idx];
 }
 
-static struct clk_ops sh3_master_clk_ops = {
+static struct sh_clk_ops sh3_master_clk_ops = {
         .init           = master_clk_init,
 };
 
@@ -46,7 +46,7 @@ static unsigned long module_clk_recalc(struct clk *clk)
         return clk->parent->rate / pfc_divisors[idx];
 }
 
-static struct clk_ops sh3_module_clk_ops = {
+static struct sh_clk_ops sh3_module_clk_ops = {
         .recalc         = module_clk_recalc,
 };
 
@@ -58,7 +58,7 @@ static unsigned long bus_clk_recalc(struct clk *clk)
         return clk->parent->rate / stc_multipliers[idx];
 }
 
-static struct clk_ops sh3_bus_clk_ops = {
+static struct sh_clk_ops sh3_bus_clk_ops = {
         .recalc         = bus_clk_recalc,
 };
 
@@ -70,18 +70,18 @@ static unsigned long cpu_clk_recalc(struct clk *clk)
         return clk->parent->rate / ifc_divisors[idx];
 }
 
-static struct clk_ops sh3_cpu_clk_ops = {
+static struct sh_clk_ops sh3_cpu_clk_ops = {
         .recalc         = cpu_clk_recalc,
 };
 
-static struct clk_ops *sh3_clk_ops[] = {
+static struct sh_clk_ops *sh3_clk_ops[] = {
         &sh3_master_clk_ops,
         &sh3_module_clk_ops,
         &sh3_bus_clk_ops,
         &sh3_cpu_clk_ops,
 };
 
-void __init arch_init_clk_ops(struct clk_ops **ops, int idx)
+void __init arch_init_clk_ops(struct sh_clk_ops **ops, int idx)
 {
         if (idx < ARRAY_SIZE(sh3_clk_ops))
                 *ops = sh3_clk_ops[idx];
diff --git a/arch/sh/kernel/cpu/sh3/clock-sh7705.c b/arch/sh/kernel/cpu/sh3/clock-sh7705.c
index 0ecea1451c6..a8da4a9986b 100644
--- a/arch/sh/kernel/cpu/sh3/clock-sh7705.c
+++ b/arch/sh/kernel/cpu/sh3/clock-sh7705.c
@@ -35,7 +35,7 @@ static void master_clk_init(struct clk *clk)
         clk->rate *= pfc_divisors[__raw_readw(FRQCR) & 0x0003];
 }
 
-static struct clk_ops sh7705_master_clk_ops = {
+static struct sh_clk_ops sh7705_master_clk_ops = {
         .init           = master_clk_init,
 };
 
@@ -45,7 +45,7 @@ static unsigned long module_clk_recalc(struct clk *clk)
         return clk->parent->rate / pfc_divisors[idx];
 }
 
-static struct clk_ops sh7705_module_clk_ops = {
+static struct sh_clk_ops sh7705_module_clk_ops = {
         .recalc         = module_clk_recalc,
 };
 
@@ -55,7 +55,7 @@ static unsigned long bus_clk_recalc(struct clk *clk)
         return clk->parent->rate / stc_multipliers[idx];
 }
 
-static struct clk_ops sh7705_bus_clk_ops = {
+static struct sh_clk_ops sh7705_bus_clk_ops = {
         .recalc         = bus_clk_recalc,
 };
 
@@ -65,18 +65,18 @@ static unsigned long cpu_clk_recalc(struct clk *clk)
         return clk->parent->rate / ifc_divisors[idx];
 }
 
-static struct clk_ops sh7705_cpu_clk_ops = {
+static struct sh_clk_ops sh7705_cpu_clk_ops = {
         .recalc         = cpu_clk_recalc,
 };
 
-static struct clk_ops *sh7705_clk_ops[] = {
+static struct sh_clk_ops *sh7705_clk_ops[] = {
         &sh7705_master_clk_ops,
         &sh7705_module_clk_ops,
         &sh7705_bus_clk_ops,
         &sh7705_cpu_clk_ops,
 };
 
-void __init arch_init_clk_ops(struct clk_ops **ops, int idx)
+void __init arch_init_clk_ops(struct sh_clk_ops **ops, int idx)
 {
         if (idx < ARRAY_SIZE(sh7705_clk_ops))
                 *ops = sh7705_clk_ops[idx];
diff --git a/arch/sh/kernel/cpu/sh3/clock-sh7706.c b/arch/sh/kernel/cpu/sh3/clock-sh7706.c
index 6f9ff8b57dd..a4088e5b220 100644
--- a/arch/sh/kernel/cpu/sh3/clock-sh7706.c
+++ b/arch/sh/kernel/cpu/sh3/clock-sh7706.c
@@ -30,7 +30,7 @@ static void master_clk_init(struct clk *clk)
         clk->rate *= pfc_divisors[idx];
 }
 
-static struct clk_ops sh7706_master_clk_ops = {
+static struct sh_clk_ops sh7706_master_clk_ops = {
         .init           = master_clk_init,
 };
 
@@ -42,7 +42,7 @@ static unsigned long module_clk_recalc(struct clk *clk)
         return clk->parent->rate / pfc_divisors[idx];
 }
 
-static struct clk_ops sh7706_module_clk_ops = {
+static struct sh_clk_ops sh7706_module_clk_ops = {
         .recalc         = module_clk_recalc,
 };
 
@@ -54,7 +54,7 @@ static unsigned long bus_clk_recalc(struct clk *clk)
         return clk->parent->rate / stc_multipliers[idx];
 }
 
-static struct clk_ops sh7706_bus_clk_ops = {
+static struct sh_clk_ops sh7706_bus_clk_ops = {
         .recalc         = bus_clk_recalc,
 };
 
@@ -66,18 +66,18 @@ static unsigned long cpu_clk_recalc(struct clk *clk)
         return clk->parent->rate / ifc_divisors[idx];
 }
 
-static struct clk_ops sh7706_cpu_clk_ops = {
+static struct sh_clk_ops sh7706_cpu_clk_ops = {
         .recalc         = cpu_clk_recalc,
 };
 
-static struct clk_ops *sh7706_clk_ops[] = {
+static struct sh_clk_ops *sh7706_clk_ops[] = {
         &sh7706_master_clk_ops,
         &sh7706_module_clk_ops,
         &sh7706_bus_clk_ops,
         &sh7706_cpu_clk_ops,
 };
 
-void __init arch_init_clk_ops(struct clk_ops **ops, int idx)
+void __init arch_init_clk_ops(struct sh_clk_ops **ops, int idx)
 {
         if (idx < ARRAY_SIZE(sh7706_clk_ops))
                 *ops = sh7706_clk_ops[idx];
diff --git a/arch/sh/kernel/cpu/sh3/clock-sh7709.c b/arch/sh/kernel/cpu/sh3/clock-sh7709.c
index f302ba09e68..54a6d4bcc0d 100644
--- a/arch/sh/kernel/cpu/sh3/clock-sh7709.c
+++ b/arch/sh/kernel/cpu/sh3/clock-sh7709.c
@@ -30,7 +30,7 @@ static void master_clk_init(struct clk *clk)
         clk->rate *= pfc_divisors[idx];
 }
 
-static struct clk_ops sh7709_master_clk_ops = {
+static struct sh_clk_ops sh7709_master_clk_ops = {
         .init           = master_clk_init,
 };
 
@@ -42,7 +42,7 @@ static unsigned long module_clk_recalc(struct clk *clk)
         return clk->parent->rate / pfc_divisors[idx];
 }
 
-static struct clk_ops sh7709_module_clk_ops = {
+static struct sh_clk_ops sh7709_module_clk_ops = {
         .recalc         = module_clk_recalc,
 };
 
@@ -55,7 +55,7 @@ static unsigned long bus_clk_recalc(struct clk *clk)
         return clk->parent->rate * stc_multipliers[idx];
 }
 
-static struct clk_ops sh7709_bus_clk_ops = {
+static struct sh_clk_ops sh7709_bus_clk_ops = {
         .recalc         = bus_clk_recalc,
 };
 
@@ -67,18 +67,18 @@ static unsigned long cpu_clk_recalc(struct clk *clk)
         return clk->parent->rate / ifc_divisors[idx];
 }
 
-static struct clk_ops sh7709_cpu_clk_ops = {
+static struct sh_clk_ops sh7709_cpu_clk_ops = {
         .recalc         = cpu_clk_recalc,
 };
 
-static struct clk_ops *sh7709_clk_ops[] = {
+static struct sh_clk_ops *sh7709_clk_ops[] = {
         &sh7709_master_clk_ops,
         &sh7709_module_clk_ops,
         &sh7709_bus_clk_ops,
         &sh7709_cpu_clk_ops,
 };
 
-void __init arch_init_clk_ops(struct clk_ops **ops, int idx)
+void __init arch_init_clk_ops(struct sh_clk_ops **ops, int idx)
 {
         if (idx < ARRAY_SIZE(sh7709_clk_ops))
                 *ops = sh7709_clk_ops[idx];
diff --git a/arch/sh/kernel/cpu/sh3/clock-sh7710.c b/arch/sh/kernel/cpu/sh3/clock-sh7710.c
index 29a87d8946a..ce601b2e397 100644
--- a/arch/sh/kernel/cpu/sh3/clock-sh7710.c
+++ b/arch/sh/kernel/cpu/sh3/clock-sh7710.c
@@ -29,7 +29,7 @@ static void master_clk_init(struct clk *clk)
         clk->rate *= md_table[__raw_readw(FRQCR) & 0x0007];
 }
 
-static struct clk_ops sh7710_master_clk_ops = {
+static struct sh_clk_ops sh7710_master_clk_ops = {
         .init           = master_clk_init,
 };
 
@@ -39,7 +39,7 @@ static unsigned long module_clk_recalc(struct clk *clk)
         return clk->parent->rate / md_table[idx];
 }
 
-static struct clk_ops sh7710_module_clk_ops = {
+static struct sh_clk_ops sh7710_module_clk_ops = {
         .recalc         = module_clk_recalc,
 };
 
@@ -49,7 +49,7 @@ static unsigned long bus_clk_recalc(struct clk *clk)
         return clk->parent->rate / md_table[idx];
 }
 
-static struct clk_ops sh7710_bus_clk_ops = {
+static struct sh_clk_ops sh7710_bus_clk_ops = {
         .recalc         = bus_clk_recalc,
 };
 
@@ -59,18 +59,18 @@ static unsigned long cpu_clk_recalc(struct clk *clk)
         return clk->parent->rate / md_table[idx];
 }
 
-static struct clk_ops sh7710_cpu_clk_ops = {
+static struct sh_clk_ops sh7710_cpu_clk_ops = {
         .recalc         = cpu_clk_recalc,
 };
 
-static struct clk_ops *sh7710_clk_ops[] = {
+static struct sh_clk_ops *sh7710_clk_ops[] = {
         &sh7710_master_clk_ops,
         &sh7710_module_clk_ops,
         &sh7710_bus_clk_ops,
         &sh7710_cpu_clk_ops,
 };
 
-void __init arch_init_clk_ops(struct clk_ops **ops, int idx)
+void __init arch_init_clk_ops(struct sh_clk_ops **ops, int idx)
 {
         if (idx < ARRAY_SIZE(sh7710_clk_ops))
                 *ops = sh7710_clk_ops[idx];
diff --git a/arch/sh/kernel/cpu/sh3/clock-sh7712.c b/arch/sh/kernel/cpu/sh3/clock-sh7712.c
index b0d0c520399..21438a9a1ae 100644
--- a/arch/sh/kernel/cpu/sh3/clock-sh7712.c
+++ b/arch/sh/kernel/cpu/sh3/clock-sh7712.c
@@ -29,7 +29,7 @@ static void master_clk_init(struct clk *clk)
         clk->rate *= multipliers[idx];
 }
 
-static struct clk_ops sh7712_master_clk_ops = {
+static struct sh_clk_ops sh7712_master_clk_ops = {
         .init           = master_clk_init,
 };
 
@@ -41,7 +41,7 @@ static unsigned long module_clk_recalc(struct clk *clk)
         return clk->parent->rate / divisors[idx];
 }
 
-static struct clk_ops sh7712_module_clk_ops = {
+static struct sh_clk_ops sh7712_module_clk_ops = {
         .recalc         = module_clk_recalc,
 };
 
@@ -53,17 +53,17 @@ static unsigned long cpu_clk_recalc(struct clk *clk)
         return clk->parent->rate / divisors[idx];
 }
 
-static struct clk_ops sh7712_cpu_clk_ops = {
+static struct sh_clk_ops sh7712_cpu_clk_ops = {
         .recalc         = cpu_clk_recalc,
 };
 
-static struct clk_ops *sh7712_clk_ops[] = {
+static struct sh_clk_ops *sh7712_clk_ops[] = {
         &sh7712_master_clk_ops,
         &sh7712_module_clk_ops,
         &sh7712_cpu_clk_ops,
 };
 
-void __init arch_init_clk_ops(struct clk_ops **ops, int idx)
+void __init arch_init_clk_ops(struct sh_clk_ops **ops, int idx)
 {
         if (idx < ARRAY_SIZE(sh7712_clk_ops))
                 *ops = sh7712_clk_ops[idx];
diff --git a/arch/sh/kernel/cpu/sh4/clock-sh4-202.c b/arch/sh/kernel/cpu/sh4/clock-sh4-202.c
index f4e262adb39..4b5bab5f875 100644
--- a/arch/sh/kernel/cpu/sh4/clock-sh4-202.c
+++ b/arch/sh/kernel/cpu/sh4/clock-sh4-202.c
@@ -41,7 +41,7 @@ static inline int frqcr3_lookup(struct clk *clk, unsigned long rate)
         return 5;
 }
 
-static struct clk_ops sh4202_emi_clk_ops = {
+static struct sh_clk_ops sh4202_emi_clk_ops = {
         .recalc         = emi_clk_recalc,
 };
 
@@ -56,7 +56,7 @@ static unsigned long femi_clk_recalc(struct clk *clk)
         return clk->parent->rate / frqcr3_divisors[idx];
 }
 
-static struct clk_ops sh4202_femi_clk_ops = {
+static struct sh_clk_ops sh4202_femi_clk_ops = {
         .recalc         = femi_clk_recalc,
 };
 
@@ -130,7 +130,7 @@ static int shoc_clk_set_rate(struct clk *clk, unsigned long rate)
         return 0;
 }
 
-static struct clk_ops sh4202_shoc_clk_ops = {
+static struct sh_clk_ops sh4202_shoc_clk_ops = {
         .init           = shoc_clk_init,
         .recalc         = shoc_clk_recalc,
         .set_rate       = shoc_clk_set_rate,
diff --git a/arch/sh/kernel/cpu/sh4/clock-sh4.c b/arch/sh/kernel/cpu/sh4/clock-sh4.c
index 5add75c1f53..99e5ec8b483 100644
--- a/arch/sh/kernel/cpu/sh4/clock-sh4.c
+++ b/arch/sh/kernel/cpu/sh4/clock-sh4.c
@@ -31,7 +31,7 @@ static void master_clk_init(struct clk *clk)
         clk->rate *= pfc_divisors[__raw_readw(FRQCR) & 0x0007];
 }
 
-static struct clk_ops sh4_master_clk_ops = {
+static struct sh_clk_ops sh4_master_clk_ops = {
         .init           = master_clk_init,
 };
 
@@ -41,7 +41,7 @@ static unsigned long module_clk_recalc(struct clk *clk)
         return clk->parent->rate / pfc_divisors[idx];
 }
 
-static struct clk_ops sh4_module_clk_ops = {
+static struct sh_clk_ops sh4_module_clk_ops = {
         .recalc         = module_clk_recalc,
 };
 
@@ -51,7 +51,7 @@ static unsigned long bus_clk_recalc(struct clk *clk)
         return clk->parent->rate / bfc_divisors[idx];
 }
 
-static struct clk_ops sh4_bus_clk_ops = {
+static struct sh_clk_ops sh4_bus_clk_ops = {
         .recalc         = bus_clk_recalc,
 };
 
@@ -61,18 +61,18 @@ static unsigned long cpu_clk_recalc(struct clk *clk)
         return clk->parent->rate / ifc_divisors[idx];
 }
 
-static struct clk_ops sh4_cpu_clk_ops = {
+static struct sh_clk_ops sh4_cpu_clk_ops = {
         .recalc         = cpu_clk_recalc,
 };
 
-static struct clk_ops *sh4_clk_ops[] = {
+static struct sh_clk_ops *sh4_clk_ops[] = {
         &sh4_master_clk_ops,
         &sh4_module_clk_ops,
         &sh4_bus_clk_ops,
         &sh4_cpu_clk_ops,
 };
 
-void __init arch_init_clk_ops(struct clk_ops **ops, int idx)
+void __init arch_init_clk_ops(struct sh_clk_ops **ops, int idx)
 {
         if (idx < ARRAY_SIZE(sh4_clk_ops))
                 *ops = sh4_clk_ops[idx];
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7343.c b/arch/sh/kernel/cpu/sh4a/clock-sh7343.c
index 70e45bdaadc..ea01a72f1b9 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7343.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7343.c
@@ -61,7 +61,7 @@ static unsigned long dll_recalc(struct clk *clk)
         return clk->parent->rate * mult;
 }
 
-static struct clk_ops dll_clk_ops = {
+static struct sh_clk_ops dll_clk_ops = {
         .recalc         = dll_recalc,
 };
 
@@ -81,7 +81,7 @@ static unsigned long pll_recalc(struct clk *clk)
         return clk->parent->rate * mult;
 }
 
-static struct clk_ops pll_clk_ops = {
+static struct sh_clk_ops pll_clk_ops = {
         .recalc         = pll_recalc,
 };
 
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7366.c b/arch/sh/kernel/cpu/sh4a/clock-sh7366.c
index 3c3165000c5..7ac07b4f75d 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7366.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7366.c
@@ -61,7 +61,7 @@ static unsigned long dll_recalc(struct clk *clk)
         return clk->parent->rate * mult;
 }
 
-static struct clk_ops dll_clk_ops = {
+static struct sh_clk_ops dll_clk_ops = {
         .recalc         = dll_recalc,
 };
 
@@ -84,7 +84,7 @@ static unsigned long pll_recalc(struct clk *clk)
         return (clk->parent->rate * mult) / div;
 }
 
-static struct clk_ops pll_clk_ops = {
+static struct sh_clk_ops pll_clk_ops = {
         .recalc         = pll_recalc,
 };
 
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7722.c b/arch/sh/kernel/cpu/sh4a/clock-sh7722.c
index 212c72ef959..8e1f97010c0 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7722.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7722.c
@@ -64,7 +64,7 @@ static unsigned long dll_recalc(struct clk *clk)
         return clk->parent->rate * mult;
 }
 
-static struct clk_ops dll_clk_ops = {
+static struct sh_clk_ops dll_clk_ops = {
         .recalc         = dll_recalc,
 };
 
@@ -87,7 +87,7 @@ static unsigned long pll_recalc(struct clk *clk)
         return (clk->parent->rate * mult) / div;
 }
 
-static struct clk_ops pll_clk_ops = {
+static struct sh_clk_ops pll_clk_ops = {
         .recalc         = pll_recalc,
 };
 
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7723.c b/arch/sh/kernel/cpu/sh4a/clock-sh7723.c
index 2f8c9179da4..35f75cf0c7e 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7723.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7723.c
@@ -65,7 +65,7 @@ static unsigned long dll_recalc(struct clk *clk)
         return clk->parent->rate * mult;
 }
 
-static struct clk_ops dll_clk_ops = {
+static struct sh_clk_ops dll_clk_ops = {
         .recalc         = dll_recalc,
 };
 
@@ -88,7 +88,7 @@ static unsigned long pll_recalc(struct clk *clk)
         return (clk->parent->rate * mult) / div;
 }
 
-static struct clk_ops pll_clk_ops = {
+static struct sh_clk_ops pll_clk_ops = {
         .recalc         = pll_recalc,
 };
 
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7724.c b/arch/sh/kernel/cpu/sh4a/clock-sh7724.c
index 70bd96646f4..2a87901673f 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7724.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7724.c
@@ -70,7 +70,7 @@ static unsigned long fll_recalc(struct clk *clk)
         return (clk->parent->rate * mult) / div;
 }
 
-static struct clk_ops fll_clk_ops = {
+static struct sh_clk_ops fll_clk_ops = {
         .recalc         = fll_recalc,
 };
 
@@ -90,7 +90,7 @@ static unsigned long pll_recalc(struct clk *clk)
         return clk->parent->rate * mult;
 }
 
-static struct clk_ops pll_clk_ops = {
+static struct sh_clk_ops pll_clk_ops = {
         .recalc         = pll_recalc,
 };
 
@@ -105,7 +105,7 @@ static unsigned long div3_recalc(struct clk *clk)
         return clk->parent->rate / 3;
 }
 
-static struct clk_ops div3_clk_ops = {
+static struct sh_clk_ops div3_clk_ops = {
         .recalc         = div3_recalc,
 };
 
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7757.c b/arch/sh/kernel/cpu/sh4a/clock-sh7757.c
index 0bd21c82151..5853989586e 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7757.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7757.c
@@ -33,7 +33,7 @@ static unsigned long pll_recalc(struct clk *clk)
         return clk->parent->rate * multiplier;
 }
 
-static struct clk_ops pll_clk_ops = {
+static struct sh_clk_ops pll_clk_ops = {
         .recalc         = pll_recalc,
 };
 
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7763.c b/arch/sh/kernel/cpu/sh4a/clock-sh7763.c
index 2d4c7fd79c0..7707e35aea4 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7763.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7763.c
@@ -27,7 +27,7 @@ static void master_clk_init(struct clk *clk)
         clk->rate *= p0fc_divisors[(__raw_readl(FRQCR) >> 4) & 0x07];
 }
 
-static struct clk_ops sh7763_master_clk_ops = {
+static struct sh_clk_ops sh7763_master_clk_ops = {
         .init           = master_clk_init,
 };
 
@@ -37,7 +37,7 @@ static unsigned long module_clk_recalc(struct clk *clk)
         return clk->parent->rate / p0fc_divisors[idx];
 }
 
-static struct clk_ops sh7763_module_clk_ops = {
+static struct sh_clk_ops sh7763_module_clk_ops = {
         .recalc         = module_clk_recalc,
 };
 
@@ -47,22 +47,22 @@ static unsigned long bus_clk_recalc(struct clk *clk)
         return clk->parent->rate / bfc_divisors[idx];
 }
 
-static struct clk_ops sh7763_bus_clk_ops = {
+static struct sh_clk_ops sh7763_bus_clk_ops = {
         .recalc         = bus_clk_recalc,
 };
 
-static struct clk_ops sh7763_cpu_clk_ops = {
+static struct sh_clk_ops sh7763_cpu_clk_ops = {
         .recalc         = followparent_recalc,
 };
 
-static struct clk_ops *sh7763_clk_ops[] = {
+static struct sh_clk_ops *sh7763_clk_ops[] = {
         &sh7763_master_clk_ops,
         &sh7763_module_clk_ops,
         &sh7763_bus_clk_ops,
         &sh7763_cpu_clk_ops,
 };
 
-void __init arch_init_clk_ops(struct clk_ops **ops, int idx)
+void __init arch_init_clk_ops(struct sh_clk_ops **ops, int idx)
 {
         if (idx < ARRAY_SIZE(sh7763_clk_ops))
                 *ops = sh7763_clk_ops[idx];
@@ -74,7 +74,7 @@ static unsigned long shyway_clk_recalc(struct clk *clk)
         return clk->parent->rate / cfc_divisors[idx];
 }
 
-static struct clk_ops sh7763_shyway_clk_ops = {
+static struct sh_clk_ops sh7763_shyway_clk_ops = {
         .recalc         = shyway_clk_recalc,
 };
 
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7770.c b/arch/sh/kernel/cpu/sh4a/clock-sh7770.c
index 9e3354365d4..5d36f334bb0 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7770.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7770.c
@@ -24,7 +24,7 @@ static void master_clk_init(struct clk *clk)
         clk->rate *= pfc_divisors[(__raw_readl(FRQCR) >> 28) & 0x000f];
 }
 
-static struct clk_ops sh7770_master_clk_ops = {
+static struct sh_clk_ops sh7770_master_clk_ops = {
         .init           = master_clk_init,
 };
 
@@ -34,7 +34,7 @@ static unsigned long module_clk_recalc(struct clk *clk)
         return clk->parent->rate / pfc_divisors[idx];
 }
 
-static struct clk_ops sh7770_module_clk_ops = {
+static struct sh_clk_ops sh7770_module_clk_ops = {
         .recalc         = module_clk_recalc,
 };
 
@@ -44,7 +44,7 @@ static unsigned long bus_clk_recalc(struct clk *clk)
         return clk->parent->rate / bfc_divisors[idx];
 }
 
-static struct clk_ops sh7770_bus_clk_ops = {
+static struct sh_clk_ops sh7770_bus_clk_ops = {
         .recalc         = bus_clk_recalc,
 };
 
@@ -54,18 +54,18 @@ static unsigned long cpu_clk_recalc(struct clk *clk)
         return clk->parent->rate / ifc_divisors[idx];
 }
 
-static struct clk_ops sh7770_cpu_clk_ops = {
+static struct sh_clk_ops sh7770_cpu_clk_ops = {
         .recalc         = cpu_clk_recalc,
 };
 
-static struct clk_ops *sh7770_clk_ops[] = {
+static struct sh_clk_ops *sh7770_clk_ops[] = {
         &sh7770_master_clk_ops,
         &sh7770_module_clk_ops,
         &sh7770_bus_clk_ops,
         &sh7770_cpu_clk_ops,
 };
 
-void __init arch_init_clk_ops(struct clk_ops **ops, int idx)
+void __init arch_init_clk_ops(struct sh_clk_ops **ops, int idx)
 {
         if (idx < ARRAY_SIZE(sh7770_clk_ops))
                 *ops = sh7770_clk_ops[idx];
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7780.c b/arch/sh/kernel/cpu/sh4a/clock-sh7780.c
index 3b53348fe2f..793dae42a2f 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7780.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7780.c
@@ -27,7 +27,7 @@ static void master_clk_init(struct clk *clk)
         clk->rate *= pfc_divisors[__raw_readl(FRQCR) & 0x0003];
 }
 
-static struct clk_ops sh7780_master_clk_ops = {
+static struct sh_clk_ops sh7780_master_clk_ops = {
         .init           = master_clk_init,
 };
 
@@ -37,7 +37,7 @@ static unsigned long module_clk_recalc(struct clk *clk)
         return clk->parent->rate / pfc_divisors[idx];
 }
 
-static struct clk_ops sh7780_module_clk_ops = {
+static struct sh_clk_ops sh7780_module_clk_ops = {
         .recalc         = module_clk_recalc,
 };
 
@@ -47,7 +47,7 @@ static unsigned long bus_clk_recalc(struct clk *clk)
         return clk->parent->rate / bfc_divisors[idx];
 }
 
-static struct clk_ops sh7780_bus_clk_ops = {
+static struct sh_clk_ops sh7780_bus_clk_ops = {
         .recalc         = bus_clk_recalc,
 };
 
@@ -57,18 +57,18 @@ static unsigned long cpu_clk_recalc(struct clk *clk)
         return clk->parent->rate / ifc_divisors[idx];
 }
 
-static struct clk_ops sh7780_cpu_clk_ops = {
+static struct sh_clk_ops sh7780_cpu_clk_ops = {
         .recalc         = cpu_clk_recalc,
 };
 
-static struct clk_ops *sh7780_clk_ops[] = {
+static struct sh_clk_ops *sh7780_clk_ops[] = {
         &sh7780_master_clk_ops,
         &sh7780_module_clk_ops,
         &sh7780_bus_clk_ops,
         &sh7780_cpu_clk_ops,
 };
 
-void __init arch_init_clk_ops(struct clk_ops **ops, int idx)
+void __init arch_init_clk_ops(struct sh_clk_ops **ops, int idx)
 {
         if (idx < ARRAY_SIZE(sh7780_clk_ops))
                 *ops = sh7780_clk_ops[idx];
@@ -80,7 +80,7 @@ static unsigned long shyway_clk_recalc(struct clk *clk)
         return clk->parent->rate / cfc_divisors[idx];
 }
 
-static struct clk_ops sh7780_shyway_clk_ops = {
+static struct sh_clk_ops sh7780_shyway_clk_ops = {
         .recalc         = shyway_clk_recalc,
 };
 
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7785.c b/arch/sh/kernel/cpu/sh4a/clock-sh7785.c
index 2b314439d35..ab1c58f2d10 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7785.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7785.c
@@ -36,7 +36,7 @@ static unsigned long pll_recalc(struct clk *clk)
         return clk->parent->rate * multiplier;
 }
 
-static struct clk_ops pll_clk_ops = {
+static struct sh_clk_ops pll_clk_ops = {
         .recalc         = pll_recalc,
 };
 
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7786.c b/arch/sh/kernel/cpu/sh4a/clock-sh7786.c
index f6c0c3d5599..491709483e1 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7786.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7786.c
@@ -38,7 +38,7 @@ static unsigned long pll_recalc(struct clk *clk)
         return clk->parent->rate * multiplier;
 }
 
-static struct clk_ops pll_clk_ops = {
+static struct sh_clk_ops pll_clk_ops = {
         .recalc         = pll_recalc,
 };
 
diff --git a/arch/sh/kernel/cpu/sh4a/clock-shx3.c b/arch/sh/kernel/cpu/sh4a/clock-shx3.c
index bf2d00b8b90..0f11b392bf4 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-shx3.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-shx3.c
@@ -32,7 +32,7 @@ static unsigned long pll_recalc(struct clk *clk)
         return clk->parent->rate * 72;
 }
 
-static struct clk_ops pll_clk_ops = {
+static struct sh_clk_ops pll_clk_ops = {
         .recalc         = pll_recalc,
 };
 
diff --git a/arch/sh/kernel/cpu/sh5/clock-sh5.c b/arch/sh/kernel/cpu/sh5/clock-sh5.c
index 9cfc19b8dbe..c48b93d4c08 100644
--- a/arch/sh/kernel/cpu/sh5/clock-sh5.c
+++ b/arch/sh/kernel/cpu/sh5/clock-sh5.c
@@ -28,7 +28,7 @@ static void master_clk_init(struct clk *clk)
         clk->rate *= ifc_table[idx];
 }
 
-static struct clk_ops sh5_master_clk_ops = {
+static struct sh_clk_ops sh5_master_clk_ops = {
         .init           = master_clk_init,
 };
 
@@ -38,7 +38,7 @@ static unsigned long module_clk_recalc(struct clk *clk)
         return clk->parent->rate / ifc_table[idx];
 }
 
-static struct clk_ops sh5_module_clk_ops = {
+static struct sh_clk_ops sh5_module_clk_ops = {
         .recalc         = module_clk_recalc,
 };
 
@@ -48,7 +48,7 @@ static unsigned long bus_clk_recalc(struct clk *clk)
         return clk->parent->rate / ifc_table[idx];
 }
 
-static struct clk_ops sh5_bus_clk_ops = {
+static struct sh_clk_ops sh5_bus_clk_ops = {
         .recalc         = bus_clk_recalc,
 };
 
@@ -58,18 +58,18 @@ static unsigned long cpu_clk_recalc(struct clk *clk)
         return clk->parent->rate / ifc_table[idx];
 }
 
-static struct clk_ops sh5_cpu_clk_ops = {
+static struct sh_clk_ops sh5_cpu_clk_ops = {
         .recalc         = cpu_clk_recalc,
 };
 
-static struct clk_ops *sh5_clk_ops[] = {
+static struct sh_clk_ops *sh5_clk_ops[] = {
         &sh5_master_clk_ops,
         &sh5_module_clk_ops,
         &sh5_bus_clk_ops,
         &sh5_cpu_clk_ops,
 };
 
-void __init arch_init_clk_ops(struct clk_ops **ops, int idx)
+void __init arch_init_clk_ops(struct sh_clk_ops **ops, int idx)
 {
         cprc_base = (unsigned long)ioremap_nocache(CPRC_BASE, 1024);
         BUG_ON(!cprc_base);
diff --git a/arch/sh/kernel/vsyscall/vsyscall.c b/arch/sh/kernel/vsyscall/vsyscall.c
index 1d6d51a1ce7..5ca579720a0 100644
--- a/arch/sh/kernel/vsyscall/vsyscall.c
+++ b/arch/sh/kernel/vsyscall/vsyscall.c
@@ -73,8 +73,7 @@ int arch_setup_additional_pages(struct linux_binprm *bprm, int uses_interp)
 
         ret = install_special_mapping(mm, addr, PAGE_SIZE,
                                       VM_READ | VM_EXEC |
-                                      VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC |
-                                      VM_ALWAYSDUMP,
+                                      VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC,
                                       syscall_pages);
         if (unlikely(ret))
                 goto up_fail;
diff --git a/arch/sparc/Kconfig b/arch/sparc/Kconfig
index ca5580e4d81..1666de84d47 100644
--- a/arch/sparc/Kconfig
+++ b/arch/sparc/Kconfig
@@ -29,6 +29,7 @@ config SPARC
         select GENERIC_IRQ_SHOW
         select USE_GENERIC_SMP_HELPERS if SMP
         select GENERIC_PCI_IOMAP
+        select HAVE_NMI_WATCHDOG if SPARC64
 
 config SPARC32
         def_bool !64BIT
diff --git a/arch/sparc/include/asm/irq_64.h b/arch/sparc/include/asm/irq_64.h
index 16dcae6d56e..abf6afe82ca 100644
--- a/arch/sparc/include/asm/irq_64.h
+++ b/arch/sparc/include/asm/irq_64.h
@@ -95,7 +95,6 @@ void arch_trigger_all_cpu_backtrace(void);
 extern void *hardirq_stack[NR_CPUS];
 extern void *softirq_stack[NR_CPUS];
 #define __ARCH_HAS_DO_SOFTIRQ
-#define ARCH_HAS_NMI_WATCHDOG
 
 #define NO_IRQ          0xffffffff
 
diff --git a/arch/sparc/include/asm/pci_32.h b/arch/sparc/include/asm/pci_32.h
index 6de7f7bf956..dc503297481 100644
--- a/arch/sparc/include/asm/pci_32.h
+++ b/arch/sparc/include/asm/pci_32.h
@@ -52,14 +52,6 @@ static inline void pci_dma_burst_advice(struct pci_dev *pdev,
  * 64Kbytes by the Host controller.
  */
 
-extern void
-pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
-                        struct resource *res);
-
-extern void
-pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
-                        struct pci_bus_region *region);
-
 static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel)
 {
         return PCI_IRQ_NONE;
diff --git a/arch/sparc/include/asm/pci_64.h b/arch/sparc/include/asm/pci_64.h
index 755a4bb6bcd..1633b718d3b 100644
--- a/arch/sparc/include/asm/pci_64.h
+++ b/arch/sparc/include/asm/pci_64.h
@@ -73,14 +73,6 @@ extern int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
                                enum pci_mmap_state mmap_state,
                                int write_combine);
 
-extern void
-pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
-                        struct resource *res);
-
-extern void
-pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
-                        struct pci_bus_region *region);
-
 static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel)
 {
         return PCI_IRQ_NONE;
diff --git a/arch/sparc/include/asm/vga.h b/arch/sparc/include/asm/vga.h
index c69d5b2ba19..ec0e9967d93 100644
--- a/arch/sparc/include/asm/vga.h
+++ b/arch/sparc/include/asm/vga.h
@@ -7,6 +7,7 @@
 #ifndef _LINUX_ASM_VGA_H_
 #define _LINUX_ASM_VGA_H_
 
+#include <linux/bug.h>
 #include <asm/types.h>
 
 #define VT_BUF_HAVE_RW
diff --git a/arch/sparc/kernel/leon_pci.c b/arch/sparc/kernel/leon_pci.c
index c7bec25fdb1..aba6b958b2a 100644
--- a/arch/sparc/kernel/leon_pci.c
+++ b/arch/sparc/kernel/leon_pci.c
@@ -15,14 +15,19 @@
 
 /* The LEON architecture does not rely on a BIOS or bootloader to setup
  * PCI for us. The Linux generic routines are used to setup resources,
- * reset values of confuration-space registers settings ae preseved.
+ * reset values of configuration-space register settings are preserved.
+ *
+ * PCI Memory and Prefetchable Memory is direct-mapped. However I/O Space is
+ * accessed through a Window which is translated to low 64KB in PCI space, the
+ * first 4KB is not used so 60KB is available.
  */
 void leon_pci_init(struct platform_device *ofdev, struct leon_pci_info *info)
 {
         LIST_HEAD(resources);
         struct pci_bus *root_bus;
 
-        pci_add_resource(&resources, &info->io_space);
+        pci_add_resource_offset(&resources, &info->io_space,
+                                info->io_space.start - 0x1000);
         pci_add_resource(&resources, &info->mem_space);
 
         root_bus = pci_scan_root_bus(&ofdev->dev, 0, info->ops, info,
@@ -38,44 +43,6 @@ void leon_pci_init(struct platform_device *ofdev, struct leon_pci_info *info)
         }
 }
 
-/* PCI Memory and Prefetchable Memory is direct-mapped. However I/O Space is
- * accessed through a Window which is translated to low 64KB in PCI space, the
- * first 4KB is not used so 60KB is available.
- *
- * This function is used by generic code to translate resource addresses into
- * PCI addresses.
- */
-void pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
-                             struct resource *res)
-{
-        struct leon_pci_info *info = dev->bus->sysdata;
-
-        region->start = res->start;
-        region->end = res->end;
-
-        if (res->flags & IORESOURCE_IO) {
-                region->start -= (info->io_space.start - 0x1000);
-                region->end -= (info->io_space.start - 0x1000);
-        }
-}
-EXPORT_SYMBOL(pcibios_resource_to_bus);
-
-/* see pcibios_resource_to_bus() comment */
-void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
-                             struct pci_bus_region *region)
-{
-        struct leon_pci_info *info = dev->bus->sysdata;
-
-        res->start = region->start;
-        res->end = region->end;
-
-        if (res->flags & IORESOURCE_IO) {
-                res->start += (info->io_space.start - 0x1000);
-                res->end += (info->io_space.start - 0x1000);
-        }
-}
-EXPORT_SYMBOL(pcibios_bus_to_resource);
-
 void __devinit pcibios_fixup_bus(struct pci_bus *pbus)
 {
         struct leon_pci_info *info = pbus->sysdata;
diff --git a/arch/sparc/kernel/pci.c b/arch/sparc/kernel/pci.c
index bb8bc2e519a..fdaf2181167 100644
--- a/arch/sparc/kernel/pci.c
+++ b/arch/sparc/kernel/pci.c
@@ -375,13 +375,6 @@ static void __devinit apb_calc_first_last(u8 map, u32 *first_p, u32 *last_p)
         *last_p = last;
 }
 
-static void pci_resource_adjust(struct resource *res,
-                                struct resource *root)
-{
-        res->start += root->start;
-        res->end += root->start;
-}
-
 /* For PCI bus devices which lack a 'ranges' property we interrogate
  * the config space values to set the resources, just like the generic
  * Linux PCI probing code does.
@@ -390,7 +383,8 @@ static void __devinit pci_cfg_fake_ranges(struct pci_dev *dev,
                                           struct pci_bus *bus,
                                           struct pci_pbm_info *pbm)
 {
-        struct resource *res;
+        struct pci_bus_region region;
+        struct resource *res, res2;
         u8 io_base_lo, io_limit_lo;
         u16 mem_base_lo, mem_limit_lo;
         unsigned long base, limit;
@@ -412,11 +406,14 @@ static void __devinit pci_cfg_fake_ranges(struct pci_dev *dev,
         res = bus->resource[0];
         if (base <= limit) {
                 res->flags = (io_base_lo & PCI_IO_RANGE_TYPE_MASK) | IORESOURCE_IO;
+                res2.flags = res->flags;
+                region.start = base;
+                region.end = limit + 0xfff;
+                pcibios_bus_to_resource(dev, &res2, &region);
                 if (!res->start)
-                        res->start = base;
+                        res->start = res2.start;
                 if (!res->end)
-                        res->end = limit + 0xfff;
-                pci_resource_adjust(res, &pbm->io_space);
+                        res->end = res2.end;
         }
 
         pci_read_config_word(dev, PCI_MEMORY_BASE, &mem_base_lo);
@@ -428,9 +425,9 @@ static void __devinit pci_cfg_fake_ranges(struct pci_dev *dev,
         if (base <= limit) {
                 res->flags = ((mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) |
                               IORESOURCE_MEM);
-                res->start = base;
-                res->end = limit + 0xfffff;
-                pci_resource_adjust(res, &pbm->mem_space);
+                region.start = base;
+                region.end = limit + 0xfffff;
+                pcibios_bus_to_resource(dev, res, &region);
         }
 
         pci_read_config_word(dev, PCI_PREF_MEMORY_BASE, &mem_base_lo);
@@ -459,9 +456,9 @@ static void __devinit pci_cfg_fake_ranges(struct pci_dev *dev,
         if (base <= limit) {
                 res->flags = ((mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) |
                               IORESOURCE_MEM | IORESOURCE_PREFETCH);
-                res->start = base;
-                res->end = limit + 0xfffff;
-                pci_resource_adjust(res, &pbm->mem_space);
+                region.start = base;
+                region.end = limit + 0xfffff;
+                pcibios_bus_to_resource(dev, res, &region);
         }
 }
 
@@ -472,6 +469,7 @@ static void __devinit apb_fake_ranges(struct pci_dev *dev,
                                       struct pci_bus *bus,
                                       struct pci_pbm_info *pbm)
 {
+        struct pci_bus_region region;
         struct resource *res;
         u32 first, last;
         u8 map;
@@ -479,18 +477,18 @@ static void __devinit apb_fake_ranges(struct pci_dev *dev,
         pci_read_config_byte(dev, APB_IO_ADDRESS_MAP, &map);
         apb_calc_first_last(map, &first, &last);
         res = bus->resource[0];
-        res->start = (first << 21);
-        res->end = (last << 21) + ((1 << 21) - 1);
         res->flags = IORESOURCE_IO;
-        pci_resource_adjust(res, &pbm->io_space);
+        region.start = (first << 21);
+        region.end = (last << 21) + ((1 << 21) - 1);
+        pcibios_bus_to_resource(dev, res, &region);
 
         pci_read_config_byte(dev, APB_MEM_ADDRESS_MAP, &map);
         apb_calc_first_last(map, &first, &last);
         res = bus->resource[1];
-        res->start = (first << 21);
-        res->end = (last << 21) + ((1 << 21) - 1);
         res->flags = IORESOURCE_MEM;
-        pci_resource_adjust(res, &pbm->mem_space);
+        region.start = (first << 21);
+        region.end = (last << 21) + ((1 << 21) - 1);
+        pcibios_bus_to_resource(dev, res, &region);
 }
 
 static void __devinit pci_of_scan_bus(struct pci_pbm_info *pbm,
@@ -506,6 +504,7 @@ static void __devinit of_scan_pci_bridge(struct pci_pbm_info *pbm,
         struct pci_bus *bus;
         const u32 *busrange, *ranges;
         int len, i, simba;
+        struct pci_bus_region region;
         struct resource *res;
         unsigned int flags;
         u64 size;
@@ -556,8 +555,6 @@ static void __devinit of_scan_pci_bridge(struct pci_pbm_info *pbm,
         }
         i = 1;
         for (; len >= 32; len -= 32, ranges += 8) {
-                struct resource *root;
-
                 flags = pci_parse_of_flags(ranges[0]);
                 size = GET_64BIT(ranges, 6);
                 if (flags == 0 || size == 0)
@@ -569,7 +566,6 @@ static void __devinit of_scan_pci_bridge(struct pci_pbm_info *pbm,
                                        " for bridge %s\n", node->full_name);
                                 continue;
                         }
-                        root = &pbm->io_space;
                 } else {
                         if (i >= PCI_NUM_RESOURCES - PCI_BRIDGE_RESOURCES) {
                                 printk(KERN_ERR "PCI: too many memory ranges"
@@ -578,18 +574,12 @@ static void __devinit of_scan_pci_bridge(struct pci_pbm_info *pbm,
                         }
                         res = bus->resource[i];
                         ++i;
-                        root = &pbm->mem_space;
                 }
 
-                res->start = GET_64BIT(ranges, 1);
-                res->end = res->start + size - 1;
                 res->flags = flags;
-
-                /* Another way to implement this would be to add an of_device
-                 * layer routine that can calculate a resource for a given
-                 * range property value in a PCI device.
-                 */
-                pci_resource_adjust(res, root);
+                region.start = GET_64BIT(ranges, 1);
+                region.end = region.start + size - 1;
+                pcibios_bus_to_resource(dev, res, &region);
         }
 after_ranges:
         sprintf(bus->name, "PCI Bus %04x:%02x", pci_domain_nr(bus),
@@ -691,8 +681,10 @@ struct pci_bus * __devinit pci_scan_one_pbm(struct pci_pbm_info *pbm,
 
         printk("PCI: Scanning PBM %s\n", node->full_name);
 
-        pci_add_resource(&resources, &pbm->io_space);
-        pci_add_resource(&resources, &pbm->mem_space);
+        pci_add_resource_offset(&resources, &pbm->io_space,
+                                pbm->io_space.start);
+        pci_add_resource_offset(&resources, &pbm->mem_space,
+                                pbm->mem_space.start);
         bus = pci_create_root_bus(parent, pbm->pci_first_busno, pbm->pci_ops,
                                   pbm, &resources);
         if (!bus) {
@@ -755,46 +747,6 @@ int pcibios_enable_device(struct pci_dev *dev, int mask)
         return 0;
 }
 
-void pcibios_resource_to_bus(struct pci_dev *pdev, struct pci_bus_region *region,
-                             struct resource *res)
-{
-        struct pci_pbm_info *pbm = pdev->bus->sysdata;
-        struct resource zero_res, *root;
-
-        zero_res.start = 0;
-        zero_res.end = 0;
-        zero_res.flags = res->flags;
-
-        if (res->flags & IORESOURCE_IO)
-                root = &pbm->io_space;
-        else
-                root = &pbm->mem_space;
-
-        pci_resource_adjust(&zero_res, root);
-
-        region->start = res->start - zero_res.start;
-        region->end = res->end - zero_res.start;
-}
-EXPORT_SYMBOL(pcibios_resource_to_bus);
-
-void pcibios_bus_to_resource(struct pci_dev *pdev, struct resource *res,
-                             struct pci_bus_region *region)
-{
-        struct pci_pbm_info *pbm = pdev->bus->sysdata;
-        struct resource *root;
-
-        res->start = region->start;
-        res->end = region->end;
-
-        if (res->flags & IORESOURCE_IO)
-                root = &pbm->io_space;
-        else
-                root = &pbm->mem_space;
-
-        pci_resource_adjust(res, root);
-}
-EXPORT_SYMBOL(pcibios_bus_to_resource);
-
 char * __devinit pcibios_setup(char *str)
 {
         return str;
diff --git a/arch/sparc/kernel/signal32.c b/arch/sparc/kernel/signal32.c
index 023b8860dc9..c8f5b50db89 100644
--- a/arch/sparc/kernel/signal32.c
+++ b/arch/sparc/kernel/signal32.c
@@ -776,7 +776,6 @@ static inline int handle_signal32(unsigned long signr, struct k_sigaction *ka,
                                   siginfo_t *info,
                                   sigset_t *oldset, struct pt_regs *regs)
 {
-        sigset_t blocked;
         int err;
 
         if (ka->sa.sa_flags & SA_SIGINFO)
@@ -787,11 +786,7 @@ static inline int handle_signal32(unsigned long signr, struct k_sigaction *ka,
         if (err)
                 return err;
 
-        sigorsets(&blocked, &current->blocked, &ka->sa.sa_mask);
-        if (!(ka->sa.sa_flags & SA_NOMASK))
-                sigaddset(&blocked, signr);
-        set_current_blocked(&blocked);
-
+        block_sigmask(ka, signr);
         tracehook_signal_handler(signr, info, ka, regs, 0);
 
         return 0;
diff --git a/arch/sparc/kernel/signal_32.c b/arch/sparc/kernel/signal_32.c
index d54c6e53aba..7bb71b6fbd2 100644
--- a/arch/sparc/kernel/signal_32.c
+++ b/arch/sparc/kernel/signal_32.c
@@ -465,7 +465,6 @@ static inline int
 handle_signal(unsigned long signr, struct k_sigaction *ka,
               siginfo_t *info, sigset_t *oldset, struct pt_regs *regs)
 {
-        sigset_t blocked;
         int err;
 
         if (ka->sa.sa_flags & SA_SIGINFO)
@@ -476,11 +475,7 @@ handle_signal(unsigned long signr, struct k_sigaction *ka,
         if (err)
                 return err;
 
-        sigorsets(&blocked, &current->blocked, &ka->sa.sa_mask);
-        if (!(ka->sa.sa_flags & SA_NOMASK))
-                sigaddset(&blocked, signr);
-        set_current_blocked(&blocked);
-
+        block_sigmask(ka, signr);
         tracehook_signal_handler(signr, info, ka, regs, 0);
 
         return 0;
diff --git a/arch/sparc/kernel/signal_64.c b/arch/sparc/kernel/signal_64.c
index f0836cd0e2f..d8a67e60be8 100644
--- a/arch/sparc/kernel/signal_64.c
+++ b/arch/sparc/kernel/signal_64.c
@@ -479,18 +479,14 @@ static inline int handle_signal(unsigned long signr, struct k_sigaction *ka,
                                 siginfo_t *info,
                                 sigset_t *oldset, struct pt_regs *regs)
 {
-        sigset_t blocked;
         int err;
 
         err = setup_rt_frame(ka, regs, signr, oldset,
                              (ka->sa.sa_flags & SA_SIGINFO) ? info : NULL);
         if (err)
                 return err;
-        sigorsets(&blocked, &current->blocked, &ka->sa.sa_mask);
-        if (!(ka->sa.sa_flags & SA_NOMASK))
-                sigaddset(&blocked, signr);
-        set_current_blocked(&blocked);
 
+        block_sigmask(ka, signr);
         tracehook_signal_handler(signr, info, ka, regs, 0);
 
         return 0;
diff --git a/arch/tile/mm/elf.c b/arch/tile/mm/elf.c
index 55e58e93bfc..1a00fb64fc8 100644
--- a/arch/tile/mm/elf.c
+++ b/arch/tile/mm/elf.c
@@ -117,17 +117,11 @@ int arch_setup_additional_pages(struct linux_binprm *bprm,
 
         /*
          * MAYWRITE to allow gdb to COW and set breakpoints
-         *
-         * Make sure the vDSO gets into every core dump.  Dumping its
-         * contents makes post-mortem fully interpretable later
-         * without matching up the same kernel and hardware config to
-         * see what PC values meant.
          */
         vdso_base = VDSO_BASE;
         retval = install_special_mapping(mm, vdso_base, PAGE_SIZE,
                                          VM_READ|VM_EXEC|
-                                         VM_MAYREAD|VM_MAYWRITE|VM_MAYEXEC|
-                                         VM_ALWAYSDUMP,
+                                         VM_MAYREAD|VM_MAYWRITE|VM_MAYEXEC,
                                          vdso_pages);
 
 #ifndef __tilegx__
diff --git a/arch/um/include/asm/mmu.h b/arch/um/include/asm/mmu.h
index 30509b9f37f..53e8b498ebb 100644
--- a/arch/um/include/asm/mmu.h
+++ b/arch/um/include/asm/mmu.h
@@ -12,7 +12,7 @@
 typedef struct mm_context {
         struct mm_id id;
         struct uml_arch_mm_context arch;
-        struct page **stub_pages;
+        struct page *stub_pages[2];
 } mm_context_t;
 
 extern void __switch_mm(struct mm_id * mm_idp);
diff --git a/arch/um/include/asm/mmu_context.h b/arch/um/include/asm/mmu_context.h
index 591b3d8d761..aa4a743dc4a 100644
--- a/arch/um/include/asm/mmu_context.h
+++ b/arch/um/include/asm/mmu_context.h
@@ -9,7 +9,7 @@
 #include <linux/sched.h>
 #include <asm/mmu.h>
 
-extern void arch_dup_mmap(struct mm_struct *oldmm, struct mm_struct *mm);
+extern void uml_setup_stubs(struct mm_struct *mm);
 extern void arch_exit_mmap(struct mm_struct *mm);
 
 #define deactivate_mm(tsk,mm)   do { } while (0)
@@ -23,7 +23,9 @@ static inline void activate_mm(struct mm_struct *old, struct mm_struct *new)
          * when the new ->mm is used for the first time.
          */
         __switch_mm(&new->context.id);
-        arch_dup_mmap(old, new);
+        down_write(&new->mmap_sem);
+        uml_setup_stubs(new);
+        up_write(&new->mmap_sem);
 }
 
 static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next, 
@@ -39,6 +41,11 @@ static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next,
         }
 }
 
+static inline void arch_dup_mmap(struct mm_struct *oldmm, struct mm_struct *mm)
+{
+        uml_setup_stubs(mm);
+}
+
 static inline void enter_lazy_tlb(struct mm_struct *mm, 
                                   struct task_struct *tsk)
 {
diff --git a/arch/um/kernel/signal.c b/arch/um/kernel/signal.c
index e8b889d3bce..fb12f4c5e64 100644
--- a/arch/um/kernel/signal.c
+++ b/arch/um/kernel/signal.c
@@ -65,21 +65,10 @@ static int handle_signal(struct pt_regs *regs, unsigned long signr,
 #endif
                 err = setup_signal_stack_si(sp, signr, ka, regs, info, oldset);
 
-        if (err) {
-                spin_lock_irq(&current->sighand->siglock);
-                current->blocked = *oldset;
-                recalc_sigpending();
-                spin_unlock_irq(&current->sighand->siglock);
+        if (err)
                 force_sigsegv(signr, current);
-        } else {
-                spin_lock_irq(&current->sighand->siglock);
-                sigorsets(&current->blocked, &current->blocked,
-                          &ka->sa.sa_mask);
-                if (!(ka->sa.sa_flags & SA_NODEFER))
-                        sigaddset(&current->blocked, signr);
-                recalc_sigpending();
-                spin_unlock_irq(&current->sighand->siglock);
-        }
+        else
+                block_sigmask(ka, signr);
 
         return err;
 }
@@ -162,12 +151,11 @@ int do_signal(void)
  */
 long sys_sigsuspend(int history0, int history1, old_sigset_t mask)
 {
+        sigset_t blocked;
+
         mask &= _BLOCKABLE;
-        spin_lock_irq(&current->sighand->siglock);
-        current->saved_sigmask = current->blocked;
-        siginitset(&current->blocked, mask);
-        recalc_sigpending();
-        spin_unlock_irq(&current->sighand->siglock);
+        siginitset(&blocked, mask);
+        set_current_blocked(&blocked);
 
         current->state = TASK_INTERRUPTIBLE;
         schedule();
diff --git a/arch/um/kernel/skas/mmu.c b/arch/um/kernel/skas/mmu.c
index 1aee587e9c5..4947b319f53 100644
--- a/arch/um/kernel/skas/mmu.c
+++ b/arch/um/kernel/skas/mmu.c
@@ -92,8 +92,6 @@ int init_new_context(struct task_struct *task, struct mm_struct *mm)
                 goto out_free;
         }
 
-        to_mm->stub_pages = NULL;
-
         return 0;
 
  out_free:
@@ -103,7 +101,7 @@ int init_new_context(struct task_struct *task, struct mm_struct *mm)
         return ret;
 }
 
-void arch_dup_mmap(struct mm_struct *oldmm, struct mm_struct *mm)
+void uml_setup_stubs(struct mm_struct *mm)
 {
         struct page **pages;
         int err, ret;
@@ -120,29 +118,20 @@ void arch_dup_mmap(struct mm_struct *oldmm, struct mm_struct *mm)
         if (ret)
                 goto out;
 
-        pages = kmalloc(2 * sizeof(struct page *), GFP_KERNEL);
-        if (pages == NULL) {
-                printk(KERN_ERR "arch_dup_mmap failed to allocate 2 page "
-                       "pointers\n");
-                goto out;
-        }
-
-        pages[0] = virt_to_page(&__syscall_stub_start);
-        pages[1] = virt_to_page(mm->context.id.stack);
-        mm->context.stub_pages = pages;
+        mm->context.stub_pages[0] = virt_to_page(&__syscall_stub_start);
+        mm->context.stub_pages[1] = virt_to_page(mm->context.id.stack);
 
         /* dup_mmap already holds mmap_sem */
         err = install_special_mapping(mm, STUB_START, STUB_END - STUB_START,
                                       VM_READ | VM_MAYREAD | VM_EXEC |
-                                      VM_MAYEXEC | VM_DONTCOPY, pages);
+                                      VM_MAYEXEC | VM_DONTCOPY,
+                                      mm->context.stub_pages);
         if (err) {
                 printk(KERN_ERR "install_special_mapping returned %d\n", err);
-                goto out_free;
+                goto out;
         }
         return;
 
-out_free:
-        kfree(pages);
 out:
         force_sigsegv(SIGSEGV, current);
 }
@@ -151,8 +140,6 @@ void arch_exit_mmap(struct mm_struct *mm)
 {
         pte_t *pte;
 
-        if (mm->context.stub_pages != NULL)
-                kfree(mm->context.stub_pages);
         pte = virt_to_pte(mm, STUB_CODE);
         if (pte != NULL)
                 pte_clear(mm, STUB_CODE, pte);
diff --git a/arch/unicore32/include/asm/pci.h b/arch/unicore32/include/asm/pci.h
index dd3867727c3..f5e108f4a15 100644
--- a/arch/unicore32/include/asm/pci.h
+++ b/arch/unicore32/include/asm/pci.h
@@ -14,6 +14,7 @@
 
 #ifdef __KERNEL__
 #include <asm-generic/pci-dma-compat.h>
+#include <asm-generic/pci-bridge.h>
 #include <asm-generic/pci.h>
 #include <mach/hardware.h> /* for PCIBIOS_MIN_* */
 
diff --git a/arch/unicore32/kernel/pci.c b/arch/unicore32/kernel/pci.c
index a8f07fe10ca..2fc2b1ba825 100644
--- a/arch/unicore32/kernel/pci.c
+++ b/arch/unicore32/kernel/pci.c
@@ -21,7 +21,6 @@
 #include <linux/io.h>
 
 static int debug_pci;
-static int use_firmware;
 
 #define CONFIG_CMD(bus, devfn, where)   \
         (0x80000000 | (bus->number << 16) | (devfn << 8) | (where & ~3))
@@ -276,7 +275,7 @@ static int __init pci_common_init(void)
 
         pci_fixup_irqs(pci_common_swizzle, pci_puv3_map_irq);
 
-        if (!use_firmware) {
+        if (!pci_has_flag(PCI_PROBE_ONLY)) {
                 /*
                  * Size the bridge windows.
                  */
@@ -303,7 +302,7 @@ char * __devinit pcibios_setup(char *str)
                 debug_pci = 1;
                 return NULL;
         } else if (!strcmp(str, "firmware")) {
-                use_firmware = 1;
+                pci_add_flags(PCI_PROBE_ONLY);
                 return NULL;
         }
         return str;
diff --git a/arch/unicore32/kernel/process.c b/arch/unicore32/kernel/process.c
index 52edc2b6287..432b4291f37 100644
--- a/arch/unicore32/kernel/process.c
+++ b/arch/unicore32/kernel/process.c
@@ -381,7 +381,7 @@ int vectors_user_mapping(void)
         return install_special_mapping(mm, 0xffff0000, PAGE_SIZE,
                                        VM_READ | VM_EXEC |
                                        VM_MAYREAD | VM_MAYEXEC |
-                                       VM_ALWAYSDUMP | VM_RESERVED,
+                                       VM_RESERVED,
                                        NULL);
 }
 
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index 6c29256a71a..90195235596 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -422,27 +422,6 @@ if X86_WANT_INTEL_MID
 config X86_INTEL_MID
         bool
 
-config X86_MRST
-       bool "Moorestown MID platform"
-        depends on PCI
-        depends on PCI_GOANY
-        depends on X86_IO_APIC
-        select X86_INTEL_MID
-        select SFI
-        select DW_APB_TIMER
-        select APB_TIMER
-        select I2C
-        select SPI
-        select INTEL_SCU_IPC
-        select X86_PLATFORM_DEVICES
-        ---help---
-          Moorestown is Intel's Low Power Intel Architecture (LPIA) based Moblin
-          Internet Device(MID) platform. Moorestown consists of two chips:
-          Lincroft (CPU core, graphics, and memory controller) and Langwell IOH.
-          Unlike standard x86 PCs, Moorestown does not have many legacy devices
-          nor standard legacy replacement devices/features. e.g. Moorestown does
-          not contain i8259, i8254, HPET, legacy BIOS, most of the io ports.
-
 config X86_MDFLD
        bool "Medfield MID platform"
         depends on PCI
@@ -456,6 +435,7 @@ config X86_MDFLD
         select SPI
         select INTEL_SCU_IPC
         select X86_PLATFORM_DEVICES
+        select MFD_INTEL_MSIC
         ---help---
           Medfield is Intel's Low Power Intel Architecture (LPIA) based Moblin
           Internet Device(MID) platform. 
@@ -2139,6 +2119,12 @@ config ALIX
 
           Note: You have to set alix.force=1 for boards with Award BIOS.
 
+config NET5501
+        bool "Soekris Engineering net5501 System Support (LEDS, GPIO, etc)"
+        select GPIOLIB
+        ---help---
+          This option enables system support for the Soekris Engineering net5501.
+
 endif # X86_32
 
 config AMD_NB
diff --git a/arch/x86/Kconfig.cpu b/arch/x86/Kconfig.cpu
index 3c57033e221..706e12e9984 100644
--- a/arch/x86/Kconfig.cpu
+++ b/arch/x86/Kconfig.cpu
@@ -303,7 +303,6 @@ config X86_GENERIC
 config X86_INTERNODE_CACHE_SHIFT
         int
         default "12" if X86_VSMP
-        default "7" if NUMA
         default X86_L1_CACHE_SHIFT
 
 config X86_CMPXCHG
@@ -441,7 +440,7 @@ config CPU_SUP_INTEL
 config CPU_SUP_CYRIX_32
         default y
         bool "Support Cyrix processors" if PROCESSOR_SELECT
-        depends on !64BIT
+        depends on M386 || M486 || M586 || M586TSC || M586MMX || (EXPERT && !64BIT)
         ---help---
           This enables detection, tunings and quirks for Cyrix processors
 
@@ -495,7 +494,7 @@ config CPU_SUP_TRANSMETA_32
 config CPU_SUP_UMC_32
         default y
         bool "Support UMC processors" if PROCESSOR_SELECT
-        depends on !64BIT
+        depends on M386 || M486 || (EXPERT && !64BIT)
         ---help---
           This enables detection, tunings and quirks for UMC processors
 
diff --git a/arch/x86/boot/Makefile b/arch/x86/boot/Makefile
index 95365a82b6a..5a747dd884d 100644
--- a/arch/x86/boot/Makefile
+++ b/arch/x86/boot/Makefile
@@ -37,7 +37,8 @@ setup-y		+= video-bios.o
 targets         += $(setup-y)
 hostprogs-y     := mkcpustr tools/build
 
-HOST_EXTRACFLAGS += $(LINUXINCLUDE)
+HOST_EXTRACFLAGS += -I$(srctree)/tools/include $(LINUXINCLUDE) \
+                    -D__EXPORTED_HEADERS__
 
 $(obj)/cpu.o: $(obj)/cpustr.h
 
diff --git a/arch/x86/boot/boot.h b/arch/x86/boot/boot.h
index c7093bd9f2d..18997e5a105 100644
--- a/arch/x86/boot/boot.h
+++ b/arch/x86/boot/boot.h
@@ -67,7 +67,7 @@ static inline void outl(u32 v, u16 port)
 {
         asm volatile("outl %0,%1" : : "a" (v), "dN" (port));
 }
-static inline u32 inl(u32 port)
+static inline u32 inl(u16 port)
 {
         u32 v;
         asm volatile("inl %1,%0" : "=a" (v) : "dN" (port));
diff --git a/arch/x86/boot/compressed/Makefile b/arch/x86/boot/compressed/Makefile
index b123b9a8f5b..fd55a2ff3ad 100644
--- a/arch/x86/boot/compressed/Makefile
+++ b/arch/x86/boot/compressed/Makefile
@@ -22,6 +22,7 @@ LDFLAGS := -m elf_$(UTS_MACHINE)
 LDFLAGS_vmlinux := -T
 
 hostprogs-y     := mkpiggy
+HOST_EXTRACFLAGS += -I$(srctree)/tools/include
 
 VMLINUX_OBJS = $(obj)/vmlinux.lds $(obj)/head_$(BITS).o $(obj)/misc.o \
         $(obj)/string.o $(obj)/cmdline.o $(obj)/early_serial_console.o \
diff --git a/arch/x86/boot/compressed/eboot.c b/arch/x86/boot/compressed/eboot.c
index fec216f4fbc..0cdfc0d2315 100644
--- a/arch/x86/boot/compressed/eboot.c
+++ b/arch/x86/boot/compressed/eboot.c
@@ -539,7 +539,7 @@ static efi_status_t handle_ramdisks(efi_loaded_image_t *image,
                 struct initrd *initrd;
                 efi_file_handle_t *h;
                 efi_file_info_t *info;
-                efi_char16_t filename[256];
+                efi_char16_t filename_16[256];
                 unsigned long info_sz;
                 efi_guid_t info_guid = EFI_FILE_INFO_ID;
                 efi_char16_t *p;
@@ -552,14 +552,14 @@ static efi_status_t handle_ramdisks(efi_loaded_image_t *image,
                 str += 7;
 
                 initrd = &initrds[i];
-                p = filename;
+                p = filename_16;
 
                 /* Skip any leading slashes */
                 while (*str == '/' || *str == '\\')
                         str++;
 
                 while (*str && *str != ' ' && *str != '\n') {
-                        if (p >= filename + sizeof(filename))
+                        if ((u8 *)p >= (u8 *)filename_16 + sizeof(filename_16))
                                 break;
 
                         *p++ = *str++;
@@ -583,7 +583,7 @@ static efi_status_t handle_ramdisks(efi_loaded_image_t *image,
                                 goto free_initrds;
                 }
 
-                status = efi_call_phys5(fh->open, fh, &h, filename,
+                status = efi_call_phys5(fh->open, fh, &h, filename_16,
                                         EFI_FILE_MODE_READ, (u64)0);
                 if (status != EFI_SUCCESS)
                         goto close_handles;
diff --git a/arch/x86/boot/compressed/mkpiggy.c b/arch/x86/boot/compressed/mkpiggy.c
index 46a82388243..958a641483d 100644
--- a/arch/x86/boot/compressed/mkpiggy.c
+++ b/arch/x86/boot/compressed/mkpiggy.c
@@ -29,14 +29,7 @@
 #include <stdio.h>
 #include <string.h>
 #include <inttypes.h>
-
-static uint32_t getle32(const void *p)
-{
-        const uint8_t *cp = p;
-
-        return (uint32_t)cp[0] + ((uint32_t)cp[1] << 8) +
-                ((uint32_t)cp[2] << 16) + ((uint32_t)cp[3] << 24);
-}
+#include <tools/le_byteshift.h>
 
 int main(int argc, char *argv[])
 {
@@ -69,7 +62,7 @@ int main(int argc, char *argv[])
         }
 
         ilen = ftell(f);
-        olen = getle32(&olen);
+        olen = get_unaligned_le32(&olen);
         fclose(f);
 
         /*
diff --git a/arch/x86/boot/compressed/relocs.c b/arch/x86/boot/compressed/relocs.c
index 89bbf4e4d05..d3c0b027766 100644
--- a/arch/x86/boot/compressed/relocs.c
+++ b/arch/x86/boot/compressed/relocs.c
@@ -10,6 +10,7 @@
 #define USE_BSD
 #include <endian.h>
 #include <regex.h>
+#include <tools/le_byteshift.h>
 
 static void die(char *fmt, ...);
 
@@ -605,10 +606,7 @@ static void emit_relocs(int as_text)
                 fwrite("\0\0\0\0", 4, 1, stdout);
                 /* Now print each relocation */
                 for (i = 0; i < reloc_count; i++) {
-                        buf[0] = (relocs[i] >>  0) & 0xff;
-                        buf[1] = (relocs[i] >>  8) & 0xff;
-                        buf[2] = (relocs[i] >> 16) & 0xff;
-                        buf[3] = (relocs[i] >> 24) & 0xff;
+                        put_unaligned_le32(relocs[i], buf);
                         fwrite(buf, 4, 1, stdout);
                 }
         }
diff --git a/arch/x86/boot/tools/build.c b/arch/x86/boot/tools/build.c
index 4e9bd6bcafa..ed549767a23 100644
--- a/arch/x86/boot/tools/build.c
+++ b/arch/x86/boot/tools/build.c
@@ -29,18 +29,18 @@
 #include <stdarg.h>
 #include <sys/types.h>
 #include <sys/stat.h>
-#include <sys/sysmacros.h>
 #include <unistd.h>
 #include <fcntl.h>
 #include <sys/mman.h>
-#include <asm/boot.h>
+#include <tools/le_byteshift.h>
 
 typedef unsigned char  u8;
 typedef unsigned short u16;
-typedef unsigned long  u32;
+typedef unsigned int   u32;
 
 #define DEFAULT_MAJOR_ROOT 0
 #define DEFAULT_MINOR_ROOT 0
+#define DEFAULT_ROOT_DEV (DEFAULT_MAJOR_ROOT << 8 | DEFAULT_MINOR_ROOT)
 
 /* Minimal number of setup sectors */
 #define SETUP_SECT_MIN 5
@@ -159,7 +159,7 @@ int main(int argc, char ** argv)
                 die("read-error on `setup'");
         if (c < 1024)
                 die("The setup must be at least 1024 bytes");
-        if (buf[510] != 0x55 || buf[511] != 0xaa)
+        if (get_unaligned_le16(&buf[510]) != 0xAA55)
                 die("Boot block hasn't got boot flag (0xAA55)");
         fclose(file);
 
@@ -171,8 +171,7 @@ int main(int argc, char ** argv)
         memset(buf+c, 0, i-c);
 
         /* Set the default root device */
-        buf[508] = DEFAULT_MINOR_ROOT;
-        buf[509] = DEFAULT_MAJOR_ROOT;
+        put_unaligned_le16(DEFAULT_ROOT_DEV, &buf[508]);
 
         fprintf(stderr, "Setup is %d bytes (padded to %d bytes).\n", c, i);
 
@@ -192,44 +191,42 @@ int main(int argc, char ** argv)
 
         /* Patch the setup code with the appropriate size parameters */
         buf[0x1f1] = setup_sectors-1;
-        buf[0x1f4] = sys_size;
-        buf[0x1f5] = sys_size >> 8;
-        buf[0x1f6] = sys_size >> 16;
-        buf[0x1f7] = sys_size >> 24;
+        put_unaligned_le32(sys_size, &buf[0x1f4]);
 
 #ifdef CONFIG_EFI_STUB
         file_sz = sz + i + ((sys_size * 16) - sz);
 
-        pe_header = *(unsigned int *)&buf[0x3c];
+        pe_header = get_unaligned_le32(&buf[0x3c]);
 
         /* Size of code */
-        *(unsigned int *)&buf[pe_header + 0x1c] = file_sz;
+        put_unaligned_le32(file_sz, &buf[pe_header + 0x1c]);
 
         /* Size of image */
-        *(unsigned int *)&buf[pe_header + 0x50] = file_sz;
+        put_unaligned_le32(file_sz, &buf[pe_header + 0x50]);
 
 #ifdef CONFIG_X86_32
         /* Address of entry point */
-        *(unsigned int *)&buf[pe_header + 0x28] = i;
+        put_unaligned_le32(i, &buf[pe_header + 0x28]);
 
         /* .text size */
-        *(unsigned int *)&buf[pe_header + 0xb0] = file_sz;
+        put_unaligned_le32(file_sz, &buf[pe_header + 0xb0]);
 
         /* .text size of initialised data */
-        *(unsigned int *)&buf[pe_header + 0xb8] = file_sz;
+        put_unaligned_le32(file_sz, &buf[pe_header + 0xb8]);
 #else
         /*
          * Address of entry point. startup_32 is at the beginning and
          * the 64-bit entry point (startup_64) is always 512 bytes
          * after.
          */
-        *(unsigned int *)&buf[pe_header + 0x28] = i + 512;
+        put_unaligned_le32(i + 512, &buf[pe_header + 0x28]);
 
         /* .text size */
-        *(unsigned int *)&buf[pe_header + 0xc0] = file_sz;
+        put_unaligned_le32(file_sz, &buf[pe_header + 0xc0]);
 
         /* .text size of initialised data */
-        *(unsigned int *)&buf[pe_header + 0xc8] = file_sz;
+        put_unaligned_le32(file_sz, &buf[pe_header + 0xc8]);
+
 #endif /* CONFIG_X86_32 */
 #endif /* CONFIG_EFI_STUB */
 
@@ -250,8 +247,9 @@ int main(int argc, char ** argv)
         }
 
         /* Write the CRC */
-        fprintf(stderr, "CRC %lx\n", crc);
-        if (fwrite(&crc, 1, 4, stdout) != 4)
+        fprintf(stderr, "CRC %x\n", crc);
+        put_unaligned_le32(crc, buf);
+        if (fwrite(buf, 1, 4, stdout) != 4)
                 die("Writing CRC failed");
 
         close(fd);
diff --git a/arch/x86/crypto/camellia_glue.c b/arch/x86/crypto/camellia_glue.c
index 1ca36a93fd2..3306dc0b139 100644
--- a/arch/x86/crypto/camellia_glue.c
+++ b/arch/x86/crypto/camellia_glue.c
@@ -1925,7 +1925,7 @@ static int force;
 module_param(force, int, 0);
 MODULE_PARM_DESC(force, "Force module load, ignore CPU blacklist");
 
-int __init init(void)
+static int __init init(void)
 {
         if (!force && is_blacklisted_cpu()) {
                 printk(KERN_INFO
@@ -1938,7 +1938,7 @@ int __init init(void)
         return crypto_register_algs(camellia_algs, ARRAY_SIZE(camellia_algs));
 }
 
-void __exit fini(void)
+static void __exit fini(void)
 {
         crypto_unregister_algs(camellia_algs, ARRAY_SIZE(camellia_algs));
 }
diff --git a/arch/x86/crypto/twofish_glue_3way.c b/arch/x86/crypto/twofish_glue_3way.c
index 408fc0c5814..922ab24cce3 100644
--- a/arch/x86/crypto/twofish_glue_3way.c
+++ b/arch/x86/crypto/twofish_glue_3way.c
@@ -668,7 +668,7 @@ static int force;
 module_param(force, int, 0);
 MODULE_PARM_DESC(force, "Force module load, ignore CPU blacklist");
 
-int __init init(void)
+static int __init init(void)
 {
         if (!force && is_blacklisted_cpu()) {
                 printk(KERN_INFO
@@ -681,7 +681,7 @@ int __init init(void)
         return crypto_register_algs(tf_algs, ARRAY_SIZE(tf_algs));
 }
 
-void __exit fini(void)
+static void __exit fini(void)
 {
         crypto_unregister_algs(tf_algs, ARRAY_SIZE(tf_algs));
 }
diff --git a/arch/x86/ia32/ia32_aout.c b/arch/x86/ia32/ia32_aout.c
index 39e49091f64..4c2e59a420b 100644
--- a/arch/x86/ia32/ia32_aout.c
+++ b/arch/x86/ia32/ia32_aout.c
@@ -323,7 +323,6 @@ static int load_aout_binary(struct linux_binprm *bprm, struct pt_regs *regs)
         }
 
         install_exec_creds(bprm);
-        current->flags &= ~PF_FORKNOEXEC;
 
         if (N_MAGIC(ex) == OMAGIC) {
                 unsigned long text_addr, map_size;
@@ -519,7 +518,8 @@ out:
 
 static int __init init_aout_binfmt(void)
 {
-        return register_binfmt(&aout_format);
+        register_binfmt(&aout_format);
+        return 0;
 }
 
 static void __exit exit_aout_binfmt(void)
diff --git a/arch/x86/ia32/ia32_signal.c b/arch/x86/ia32/ia32_signal.c
index 65577698cab..5563ba1cf51 100644
--- a/arch/x86/ia32/ia32_signal.c
+++ b/arch/x86/ia32/ia32_signal.c
@@ -24,6 +24,7 @@
 #include <asm/ucontext.h>
 #include <asm/uaccess.h>
 #include <asm/i387.h>
+#include <asm/fpu-internal.h>
 #include <asm/ptrace.h>
 #include <asm/ia32_unistd.h>
 #include <asm/user32.h>
diff --git a/arch/x86/include/asm/alternative.h b/arch/x86/include/asm/alternative.h
index 37ad100a221..49331bedc15 100644
--- a/arch/x86/include/asm/alternative.h
+++ b/arch/x86/include/asm/alternative.h
@@ -145,6 +145,12 @@ static inline int alternatives_text_reserved(void *start, void *end)
  */
 #define ASM_OUTPUT2(a...) a
 
+/*
+ * use this macro if you need clobbers but no inputs in
+ * alternative_{input,io,call}()
+ */
+#define ASM_NO_INPUT_CLOBBER(clbr...) "i" (0) : clbr
+
 struct paravirt_patch_site;
 #ifdef CONFIG_PARAVIRT
 void apply_paravirt(struct paravirt_patch_site *start,
diff --git a/arch/x86/include/asm/apic.h b/arch/x86/include/asm/apic.h
index 3ab9bdd87e7..a9371c91718 100644
--- a/arch/x86/include/asm/apic.h
+++ b/arch/x86/include/asm/apic.h
@@ -288,6 +288,7 @@ struct apic {
 
         int (*probe)(void);
         int (*acpi_madt_oem_check)(char *oem_id, char *oem_table_id);
+        int (*apic_id_valid)(int apicid);
         int (*apic_id_registered)(void);
 
         u32 irq_delivery_mode;
@@ -532,6 +533,11 @@ static inline unsigned int read_apic_id(void)
         return apic->get_apic_id(reg);
 }
 
+static inline int default_apic_id_valid(int apicid)
+{
+        return x2apic_mode || (apicid < 255);
+}
+
 extern void default_setup_apic_routing(void);
 
 extern struct apic apic_noop;
diff --git a/arch/x86/include/asm/atomic64_32.h b/arch/x86/include/asm/atomic64_32.h
index fa13f0ec287..198119910da 100644
--- a/arch/x86/include/asm/atomic64_32.h
+++ b/arch/x86/include/asm/atomic64_32.h
@@ -14,13 +14,52 @@ typedef struct {
 
 #define ATOMIC64_INIT(val)      { (val) }
 
+#define __ATOMIC64_DECL(sym) void atomic64_##sym(atomic64_t *, ...)
+#ifndef ATOMIC64_EXPORT
+#define ATOMIC64_DECL_ONE __ATOMIC64_DECL
+#else
+#define ATOMIC64_DECL_ONE(sym) __ATOMIC64_DECL(sym); \
+        ATOMIC64_EXPORT(atomic64_##sym)
+#endif
+
 #ifdef CONFIG_X86_CMPXCHG64
-#define ATOMIC64_ALTERNATIVE_(f, g) "call atomic64_" #g "_cx8"
+#define __alternative_atomic64(f, g, out, in...) \
+        asm volatile("call %P[func]" \
+                     : out : [func] "i" (atomic64_##g##_cx8), ## in)
+
+#define ATOMIC64_DECL(sym) ATOMIC64_DECL_ONE(sym##_cx8)
 #else
-#define ATOMIC64_ALTERNATIVE_(f, g) ALTERNATIVE("call atomic64_" #f "_386", "call atomic64_" #g "_cx8", X86_FEATURE_CX8)
+#define __alternative_atomic64(f, g, out, in...) \
+        alternative_call(atomic64_##f##_386, atomic64_##g##_cx8, \
+                         X86_FEATURE_CX8, ASM_OUTPUT2(out), ## in)
+
+#define ATOMIC64_DECL(sym) ATOMIC64_DECL_ONE(sym##_cx8); \
+        ATOMIC64_DECL_ONE(sym##_386)
+
+ATOMIC64_DECL_ONE(add_386);
+ATOMIC64_DECL_ONE(sub_386);
+ATOMIC64_DECL_ONE(inc_386);
+ATOMIC64_DECL_ONE(dec_386);
 #endif
 
-#define ATOMIC64_ALTERNATIVE(f) ATOMIC64_ALTERNATIVE_(f, f)
+#define alternative_atomic64(f, out, in...) \
+        __alternative_atomic64(f, f, ASM_OUTPUT2(out), ## in)
+
+ATOMIC64_DECL(read);
+ATOMIC64_DECL(set);
+ATOMIC64_DECL(xchg);
+ATOMIC64_DECL(add_return);
+ATOMIC64_DECL(sub_return);
+ATOMIC64_DECL(inc_return);
+ATOMIC64_DECL(dec_return);
+ATOMIC64_DECL(dec_if_positive);
+ATOMIC64_DECL(inc_not_zero);
+ATOMIC64_DECL(add_unless);
+
+#undef ATOMIC64_DECL
+#undef ATOMIC64_DECL_ONE
+#undef __ATOMIC64_DECL
+#undef ATOMIC64_EXPORT
 
 /**
  * atomic64_cmpxchg - cmpxchg atomic64 variable
@@ -50,11 +89,9 @@ static inline long long atomic64_xchg(atomic64_t *v, long long n)
         long long o;
         unsigned high = (unsigned)(n >> 32);
         unsigned low = (unsigned)n;
-        asm volatile(ATOMIC64_ALTERNATIVE(xchg)
-                     : "=A" (o), "+b" (low), "+c" (high)
-                     : "S" (v)
-                     : "memory"
-                     );
+        alternative_atomic64(xchg, "=&A" (o),
+                             "S" (v), "b" (low), "c" (high)
+                             : "memory");
         return o;
 }
 
@@ -69,11 +106,9 @@ static inline void atomic64_set(atomic64_t *v, long long i)
 {
         unsigned high = (unsigned)(i >> 32);
         unsigned low = (unsigned)i;
-        asm volatile(ATOMIC64_ALTERNATIVE(set)
-                     : "+b" (low), "+c" (high)
-                     : "S" (v)
-                     : "eax", "edx", "memory"
-                     );
+        alternative_atomic64(set, /* no output */,
+                             "S" (v), "b" (low), "c" (high)
+                             : "eax", "edx", "memory");
 }
 
 /**
@@ -85,10 +120,7 @@ static inline void atomic64_set(atomic64_t *v, long long i)
 static inline long long atomic64_read(const atomic64_t *v)
 {
         long long r;
-        asm volatile(ATOMIC64_ALTERNATIVE(read)
-                     : "=A" (r), "+c" (v)
-                     : : "memory"
-                     );
+        alternative_atomic64(read, "=&A" (r), "c" (v) : "memory");
         return r;
  }
 
@@ -101,10 +133,9 @@ static inline long long atomic64_read(const atomic64_t *v)
  */
 static inline long long atomic64_add_return(long long i, atomic64_t *v)
 {
-        asm volatile(ATOMIC64_ALTERNATIVE(add_return)
-                     : "+A" (i), "+c" (v)
-                     : : "memory"
-                     );
+        alternative_atomic64(add_return,
+                             ASM_OUTPUT2("+A" (i), "+c" (v)),
+                             ASM_NO_INPUT_CLOBBER("memory"));
         return i;
 }
 
@@ -113,32 +144,25 @@ static inline long long atomic64_add_return(long long i, atomic64_t *v)
  */
 static inline long long atomic64_sub_return(long long i, atomic64_t *v)
 {
-        asm volatile(ATOMIC64_ALTERNATIVE(sub_return)
-                     : "+A" (i), "+c" (v)
-                     : : "memory"
-                     );
+        alternative_atomic64(sub_return,
+                             ASM_OUTPUT2("+A" (i), "+c" (v)),
+                             ASM_NO_INPUT_CLOBBER("memory"));
         return i;
 }
 
 static inline long long atomic64_inc_return(atomic64_t *v)
 {
         long long a;
-        asm volatile(ATOMIC64_ALTERNATIVE(inc_return)
-                     : "=A" (a)
-                     : "S" (v)
-                     : "memory", "ecx"
-                     );
+        alternative_atomic64(inc_return, "=&A" (a),
+                             "S" (v) : "memory", "ecx");
         return a;
 }
 
 static inline long long atomic64_dec_return(atomic64_t *v)
 {
         long long a;
-        asm volatile(ATOMIC64_ALTERNATIVE(dec_return)
-                     : "=A" (a)
-                     : "S" (v)
-                     : "memory", "ecx"
-                     );
+        alternative_atomic64(dec_return, "=&A" (a),
+                             "S" (v) : "memory", "ecx");
         return a;
 }
 
@@ -151,10 +175,9 @@ static inline long long atomic64_dec_return(atomic64_t *v)
  */
 static inline long long atomic64_add(long long i, atomic64_t *v)
 {
-        asm volatile(ATOMIC64_ALTERNATIVE_(add, add_return)
-                     : "+A" (i), "+c" (v)
-                     : : "memory"
-                     );
+        __alternative_atomic64(add, add_return,
+                               ASM_OUTPUT2("+A" (i), "+c" (v)),
+                               ASM_NO_INPUT_CLOBBER("memory"));
         return i;
 }
 
@@ -167,10 +190,9 @@ static inline long long atomic64_add(long long i, atomic64_t *v)
  */
 static inline long long atomic64_sub(long long i, atomic64_t *v)
 {
-        asm volatile(ATOMIC64_ALTERNATIVE_(sub, sub_return)
-                     : "+A" (i), "+c" (v)
-                     : : "memory"
-                     );
+        __alternative_atomic64(sub, sub_return,
+                               ASM_OUTPUT2("+A" (i), "+c" (v)),
+                               ASM_NO_INPUT_CLOBBER("memory"));
         return i;
 }
 
@@ -196,10 +218,8 @@ static inline int atomic64_sub_and_test(long long i, atomic64_t *v)
  */
 static inline void atomic64_inc(atomic64_t *v)
 {
-        asm volatile(ATOMIC64_ALTERNATIVE_(inc, inc_return)
-                     : : "S" (v)
-                     : "memory", "eax", "ecx", "edx"
-                     );
+        __alternative_atomic64(inc, inc_return, /* no output */,
+                               "S" (v) : "memory", "eax", "ecx", "edx");
 }
 
 /**
@@ -210,10 +230,8 @@ static inline void atomic64_inc(atomic64_t *v)
  */
 static inline void atomic64_dec(atomic64_t *v)
 {
-        asm volatile(ATOMIC64_ALTERNATIVE_(dec, dec_return)
-                     : : "S" (v)
-                     : "memory", "eax", "ecx", "edx"
-                     );
+        __alternative_atomic64(dec, dec_return, /* no output */,
+                               "S" (v) : "memory", "eax", "ecx", "edx");
 }
 
 /**
@@ -263,15 +281,15 @@ static inline int atomic64_add_negative(long long i, atomic64_t *v)
  * @u: ...unless v is equal to u.
  *
  * Atomically adds @a to @v, so long as it was not @u.
- * Returns the old value of @v.
+ * Returns non-zero if the add was done, zero otherwise.
  */
 static inline int atomic64_add_unless(atomic64_t *v, long long a, long long u)
 {
         unsigned low = (unsigned)u;
         unsigned high = (unsigned)(u >> 32);
-        asm volatile(ATOMIC64_ALTERNATIVE(add_unless) "\n\t"
-                     : "+A" (a), "+c" (v), "+S" (low), "+D" (high)
-                     : : "memory");
+        alternative_atomic64(add_unless,
+                             ASM_OUTPUT2("+A" (a), "+c" (low), "+D" (high)),
+                             "S" (v) : "memory");
         return (int)a;
 }
 
@@ -279,26 +297,20 @@ static inline int atomic64_add_unless(atomic64_t *v, long long a, long long u)
 static inline int atomic64_inc_not_zero(atomic64_t *v)
 {
         int r;
-        asm volatile(ATOMIC64_ALTERNATIVE(inc_not_zero)
-                     : "=a" (r)
-                     : "S" (v)
-                     : "ecx", "edx", "memory"
-                     );
+        alternative_atomic64(inc_not_zero, "=&a" (r),
+                             "S" (v) : "ecx", "edx", "memory");
         return r;
 }
 
 static inline long long atomic64_dec_if_positive(atomic64_t *v)
 {
         long long r;
-        asm volatile(ATOMIC64_ALTERNATIVE(dec_if_positive)
-                     : "=A" (r)
-                     : "S" (v)
-                     : "ecx", "memory"
-                     );
+        alternative_atomic64(dec_if_positive, "=&A" (r),
+                             "S" (v) : "ecx", "memory");
         return r;
 }
 
-#undef ATOMIC64_ALTERNATIVE
-#undef ATOMIC64_ALTERNATIVE_
+#undef alternative_atomic64
+#undef __alternative_atomic64
 
 #endif /* _ASM_X86_ATOMIC64_32_H */
diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufeature.h
index dcb839eebc7..340ee49961a 100644
--- a/arch/x86/include/asm/cpufeature.h
+++ b/arch/x86/include/asm/cpufeature.h
@@ -200,10 +200,13 @@
 /* Intel-defined CPU features, CPUID level 0x00000007:0 (ebx), word 9 */
 #define X86_FEATURE_FSGSBASE    (9*32+ 0) /* {RD/WR}{FS/GS}BASE instructions*/
 #define X86_FEATURE_BMI1        (9*32+ 3) /* 1st group bit manipulation extensions */
+#define X86_FEATURE_HLE         (9*32+ 4) /* Hardware Lock Elision */
 #define X86_FEATURE_AVX2        (9*32+ 5) /* AVX2 instructions */
 #define X86_FEATURE_SMEP        (9*32+ 7) /* Supervisor Mode Execution Protection */
 #define X86_FEATURE_BMI2        (9*32+ 8) /* 2nd group bit manipulation extensions */
 #define X86_FEATURE_ERMS        (9*32+ 9) /* Enhanced REP MOVSB/STOSB */
+#define X86_FEATURE_INVPCID     (9*32+10) /* Invalidate Processor Context ID */
+#define X86_FEATURE_RTM         (9*32+11) /* Restricted Transactional Memory */
 
 #if defined(__KERNEL__) && !defined(__ASSEMBLY__)
 
diff --git a/arch/x86/include/asm/debugreg.h b/arch/x86/include/asm/debugreg.h
index b903d5ea394..2d91580bf22 100644
--- a/arch/x86/include/asm/debugreg.h
+++ b/arch/x86/include/asm/debugreg.h
@@ -78,8 +78,75 @@
  */
 #ifdef __KERNEL__
 
+#include <linux/bug.h>
+
 DECLARE_PER_CPU(unsigned long, cpu_dr7);
 
+#ifndef CONFIG_PARAVIRT
+/*
+ * These special macros can be used to get or set a debugging register
+ */
+#define get_debugreg(var, register)                             \
+        (var) = native_get_debugreg(register)
+#define set_debugreg(value, register)                           \
+        native_set_debugreg(register, value)
+#endif
+
+static inline unsigned long native_get_debugreg(int regno)
+{
+        unsigned long val = 0;  /* Damn you, gcc! */
+
+        switch (regno) {
+        case 0:
+                asm("mov %%db0, %0" :"=r" (val));
+                break;
+        case 1:
+                asm("mov %%db1, %0" :"=r" (val));
+                break;
+        case 2:
+                asm("mov %%db2, %0" :"=r" (val));
+                break;
+        case 3:
+                asm("mov %%db3, %0" :"=r" (val));
+                break;
+        case 6:
+                asm("mov %%db6, %0" :"=r" (val));
+                break;
+        case 7:
+                asm("mov %%db7, %0" :"=r" (val));
+                break;
+        default:
+                BUG();
+        }
+        return val;
+}
+
+static inline void native_set_debugreg(int regno, unsigned long value)
+{
+        switch (regno) {
+        case 0:
+                asm("mov %0, %%db0"     ::"r" (value));
+                break;
+        case 1:
+                asm("mov %0, %%db1"     ::"r" (value));
+                break;
+        case 2:
+                asm("mov %0, %%db2"     ::"r" (value));
+                break;
+        case 3:
+                asm("mov %0, %%db3"     ::"r" (value));
+                break;
+        case 6:
+                asm("mov %0, %%db6"     ::"r" (value));
+                break;
+        case 7:
+                asm("mov %0, %%db7"     ::"r" (value));
+                break;
+        default:
+                BUG();
+        }
+}
+
 static inline void hw_breakpoint_disable(void)
 {
         /* Zero the control register for HW Breakpoint */
diff --git a/arch/x86/include/asm/efi.h b/arch/x86/include/asm/efi.h
index 844f735fd63..c9dcc181d4d 100644
--- a/arch/x86/include/asm/efi.h
+++ b/arch/x86/include/asm/efi.h
@@ -95,7 +95,7 @@ extern void __iomem *efi_ioremap(unsigned long addr, unsigned long size,
 
 extern int add_efi_memmap;
 extern void efi_set_executable(efi_memory_desc_t *md, bool executable);
-extern void efi_memblock_x86_reserve_range(void);
+extern int efi_memblock_x86_reserve_range(void);
 extern void efi_call_phys_prelog(void);
 extern void efi_call_phys_epilog(void);
 
diff --git a/arch/x86/include/asm/fpu-internal.h b/arch/x86/include/asm/fpu-internal.h
new file mode 100644
index 00000000000..4fa88154e4d
--- /dev/null
+++ b/arch/x86/include/asm/fpu-internal.h
@@ -0,0 +1,520 @@
+/*
+ * Copyright (C) 1994 Linus Torvalds
+ *
+ * Pentium III FXSR, SSE support
+ * General FPU state handling cleanups
+ *      Gareth Hughes <gareth@valinux.com>, May 2000
+ * x86-64 work by Andi Kleen 2002
+ */
+
+#ifndef _FPU_INTERNAL_H
+#define _FPU_INTERNAL_H
+
+#include <linux/kernel_stat.h>
+#include <linux/regset.h>
+#include <linux/slab.h>
+#include <asm/asm.h>
+#include <asm/cpufeature.h>
+#include <asm/processor.h>
+#include <asm/sigcontext.h>
+#include <asm/user.h>
+#include <asm/uaccess.h>
+#include <asm/xsave.h>
+
+extern unsigned int sig_xstate_size;
+extern void fpu_init(void);
+
+DECLARE_PER_CPU(struct task_struct *, fpu_owner_task);
+
+extern user_regset_active_fn fpregs_active, xfpregs_active;
+extern user_regset_get_fn fpregs_get, xfpregs_get, fpregs_soft_get,
+                                xstateregs_get;
+extern user_regset_set_fn fpregs_set, xfpregs_set, fpregs_soft_set,
+                                 xstateregs_set;
+
+
+/*
+ * xstateregs_active == fpregs_active. Please refer to the comment
+ * at the definition of fpregs_active.
+ */
+#define xstateregs_active       fpregs_active
+
+extern struct _fpx_sw_bytes fx_sw_reserved;
+#ifdef CONFIG_IA32_EMULATION
+extern unsigned int sig_xstate_ia32_size;
+extern struct _fpx_sw_bytes fx_sw_reserved_ia32;
+struct _fpstate_ia32;
+struct _xstate_ia32;
+extern int save_i387_xstate_ia32(void __user *buf);
+extern int restore_i387_xstate_ia32(void __user *buf);
+#endif
+
+#ifdef CONFIG_MATH_EMULATION
+extern void finit_soft_fpu(struct i387_soft_struct *soft);
+#else
+static inline void finit_soft_fpu(struct i387_soft_struct *soft) {}
+#endif
+
+#define X87_FSW_ES (1 << 7)     /* Exception Summary */
+
+static __always_inline __pure bool use_xsaveopt(void)
+{
+        return static_cpu_has(X86_FEATURE_XSAVEOPT);
+}
+
+static __always_inline __pure bool use_xsave(void)
+{
+        return static_cpu_has(X86_FEATURE_XSAVE);
+}
+
+static __always_inline __pure bool use_fxsr(void)
+{
+        return static_cpu_has(X86_FEATURE_FXSR);
+}
+
+extern void __sanitize_i387_state(struct task_struct *);
+
+static inline void sanitize_i387_state(struct task_struct *tsk)
+{
+        if (!use_xsaveopt())
+                return;
+        __sanitize_i387_state(tsk);
+}
+
+#ifdef CONFIG_X86_64
+static inline int fxrstor_checking(struct i387_fxsave_struct *fx)
+{
+        int err;
+
+        /* See comment in fxsave() below. */
+#ifdef CONFIG_AS_FXSAVEQ
+        asm volatile("1:  fxrstorq %[fx]\n\t"
+                     "2:\n"
+                     ".section .fixup,\"ax\"\n"
+                     "3:  movl $-1,%[err]\n"
+                     "    jmp  2b\n"
+                     ".previous\n"
+                     _ASM_EXTABLE(1b, 3b)
+                     : [err] "=r" (err)
+                     : [fx] "m" (*fx), "0" (0));
+#else
+        asm volatile("1:  rex64/fxrstor (%[fx])\n\t"
+                     "2:\n"
+                     ".section .fixup,\"ax\"\n"
+                     "3:  movl $-1,%[err]\n"
+                     "    jmp  2b\n"
+                     ".previous\n"
+                     _ASM_EXTABLE(1b, 3b)
+                     : [err] "=r" (err)
+                     : [fx] "R" (fx), "m" (*fx), "0" (0));
+#endif
+        return err;
+}
+
+static inline int fxsave_user(struct i387_fxsave_struct __user *fx)
+{
+        int err;
+
+        /*
+         * Clear the bytes not touched by the fxsave and reserved
+         * for the SW usage.
+         */
+        err = __clear_user(&fx->sw_reserved,
+                           sizeof(struct _fpx_sw_bytes));
+        if (unlikely(err))
+                return -EFAULT;
+
+        /* See comment in fxsave() below. */
+#ifdef CONFIG_AS_FXSAVEQ
+        asm volatile("1:  fxsaveq %[fx]\n\t"
+                     "2:\n"
+                     ".section .fixup,\"ax\"\n"
+                     "3:  movl $-1,%[err]\n"
+                     "    jmp  2b\n"
+                     ".previous\n"
+                     _ASM_EXTABLE(1b, 3b)
+                     : [err] "=r" (err), [fx] "=m" (*fx)
+                     : "0" (0));
+#else
+        asm volatile("1:  rex64/fxsave (%[fx])\n\t"
+                     "2:\n"
+                     ".section .fixup,\"ax\"\n"
+                     "3:  movl $-1,%[err]\n"
+                     "    jmp  2b\n"
+                     ".previous\n"
+                     _ASM_EXTABLE(1b, 3b)
+                     : [err] "=r" (err), "=m" (*fx)
+                     : [fx] "R" (fx), "0" (0));
+#endif
+        if (unlikely(err) &&
+            __clear_user(fx, sizeof(struct i387_fxsave_struct)))
+                err = -EFAULT;
+        /* No need to clear here because the caller clears USED_MATH */
+        return err;
+}
+
+static inline void fpu_fxsave(struct fpu *fpu)
+{
+        /* Using "rex64; fxsave %0" is broken because, if the memory operand
+           uses any extended registers for addressing, a second REX prefix
+           will be generated (to the assembler, rex64 followed by semicolon
+           is a separate instruction), and hence the 64-bitness is lost. */
+
+#ifdef CONFIG_AS_FXSAVEQ
+        /* Using "fxsaveq %0" would be the ideal choice, but is only supported
+           starting with gas 2.16. */
+        __asm__ __volatile__("fxsaveq %0"
+                             : "=m" (fpu->state->fxsave));
+#else
+        /* Using, as a workaround, the properly prefixed form below isn't
+           accepted by any binutils version so far released, complaining that
+           the same type of prefix is used twice if an extended register is
+           needed for addressing (fix submitted to mainline 2005-11-21).
+        asm volatile("rex64/fxsave %0"
+                     : "=m" (fpu->state->fxsave));
+           This, however, we can work around by forcing the compiler to select
+           an addressing mode that doesn't require extended registers. */
+        asm volatile("rex64/fxsave (%[fx])"
+                     : "=m" (fpu->state->fxsave)
+                     : [fx] "R" (&fpu->state->fxsave));
+#endif
+}
+
+#else  /* CONFIG_X86_32 */
+
+/* perform fxrstor iff the processor has extended states, otherwise frstor */
+static inline int fxrstor_checking(struct i387_fxsave_struct *fx)
+{
+        /*
+         * The "nop" is needed to make the instructions the same
+         * length.
+         */
+        alternative_input(
+                "nop ; frstor %1",
+                "fxrstor %1",
+                X86_FEATURE_FXSR,
+                "m" (*fx));
+
+        return 0;
+}
+
+static inline void fpu_fxsave(struct fpu *fpu)
+{
+        asm volatile("fxsave %[fx]"
+                     : [fx] "=m" (fpu->state->fxsave));
+}
+
+#endif  /* CONFIG_X86_64 */
+
+/*
+ * These must be called with preempt disabled. Returns
+ * 'true' if the FPU state is still intact.
+ */
+static inline int fpu_save_init(struct fpu *fpu)
+{
+        if (use_xsave()) {
+                fpu_xsave(fpu);
+
+                /*
+                 * xsave header may indicate the init state of the FP.
+                 */
+                if (!(fpu->state->xsave.xsave_hdr.xstate_bv & XSTATE_FP))
+                        return 1;
+        } else if (use_fxsr()) {
+                fpu_fxsave(fpu);
+        } else {
+                asm volatile("fnsave %[fx]; fwait"
+                             : [fx] "=m" (fpu->state->fsave));
+                return 0;
+        }
+
+        /*
+         * If exceptions are pending, we need to clear them so
+         * that we don't randomly get exceptions later.
+         *
+         * FIXME! Is this perhaps only true for the old-style
+         * irq13 case? Maybe we could leave the x87 state
+         * intact otherwise?
+         */
+        if (unlikely(fpu->state->fxsave.swd & X87_FSW_ES)) {
+                asm volatile("fnclex");
+                return 0;
+        }
+        return 1;
+}
+
+static inline int __save_init_fpu(struct task_struct *tsk)
+{
+        return fpu_save_init(&tsk->thread.fpu);
+}
+
+static inline int fpu_fxrstor_checking(struct fpu *fpu)
+{
+        return fxrstor_checking(&fpu->state->fxsave);
+}
+
+static inline int fpu_restore_checking(struct fpu *fpu)
+{
+        if (use_xsave())
+                return fpu_xrstor_checking(fpu);
+        else
+                return fpu_fxrstor_checking(fpu);
+}
+
+static inline int restore_fpu_checking(struct task_struct *tsk)
+{
+        /* AMD K7/K8 CPUs don't save/restore FDP/FIP/FOP unless an exception
+           is pending.  Clear the x87 state here by setting it to fixed
+           values. "m" is a random variable that should be in L1 */
+        alternative_input(
+                ASM_NOP8 ASM_NOP2,
+                "emms\n\t"              /* clear stack tags */
+                "fildl %P[addr]",       /* set F?P to defined value */
+                X86_FEATURE_FXSAVE_LEAK,
+                [addr] "m" (tsk->thread.fpu.has_fpu));
+
+        return fpu_restore_checking(&tsk->thread.fpu);
+}
+
+/*
+ * Software FPU state helpers. Careful: these need to
+ * be preemption protection *and* they need to be
+ * properly paired with the CR0.TS changes!
+ */
+static inline int __thread_has_fpu(struct task_struct *tsk)
+{
+        return tsk->thread.fpu.has_fpu;
+}
+
+/* Must be paired with an 'stts' after! */
+static inline void __thread_clear_has_fpu(struct task_struct *tsk)
+{
+        tsk->thread.fpu.has_fpu = 0;
+        percpu_write(fpu_owner_task, NULL);
+}
+
+/* Must be paired with a 'clts' before! */
+static inline void __thread_set_has_fpu(struct task_struct *tsk)
+{
+        tsk->thread.fpu.has_fpu = 1;
+        percpu_write(fpu_owner_task, tsk);
+}
+
+/*
+ * Encapsulate the CR0.TS handling together with the
+ * software flag.
+ *
+ * These generally need preemption protection to work,
+ * do try to avoid using these on their own.
+ */
+static inline void __thread_fpu_end(struct task_struct *tsk)
+{
+        __thread_clear_has_fpu(tsk);
+        stts();
+}
+
+static inline void __thread_fpu_begin(struct task_struct *tsk)
+{
+        clts();
+        __thread_set_has_fpu(tsk);
+}
+
+/*
+ * FPU state switching for scheduling.
+ *
+ * This is a two-stage process:
+ *
+ *  - switch_fpu_prepare() saves the old state and
+ *    sets the new state of the CR0.TS bit. This is
+ *    done within the context of the old process.
+ *
+ *  - switch_fpu_finish() restores the new state as
+ *    necessary.
+ */
+typedef struct { int preload; } fpu_switch_t;
+
+/*
+ * FIXME! We could do a totally lazy restore, but we need to
+ * add a per-cpu "this was the task that last touched the FPU
+ * on this CPU" variable, and the task needs to have a "I last
+ * touched the FPU on this CPU" and check them.
+ *
+ * We don't do that yet, so "fpu_lazy_restore()" always returns
+ * false, but some day..
+ */
+static inline int fpu_lazy_restore(struct task_struct *new, unsigned int cpu)
+{
+        return new == percpu_read_stable(fpu_owner_task) &&
+                cpu == new->thread.fpu.last_cpu;
+}
+
+static inline fpu_switch_t switch_fpu_prepare(struct task_struct *old, struct task_struct *new, int cpu)
+{
+        fpu_switch_t fpu;
+
+        fpu.preload = tsk_used_math(new) && new->fpu_counter > 5;
+        if (__thread_has_fpu(old)) {
+                if (!__save_init_fpu(old))
+                        cpu = ~0;
+                old->thread.fpu.last_cpu = cpu;
+                old->thread.fpu.has_fpu = 0;    /* But leave fpu_owner_task! */
+
+                /* Don't change CR0.TS if we just switch! */
+                if (fpu.preload) {
+                        new->fpu_counter++;
+                        __thread_set_has_fpu(new);
+                        prefetch(new->thread.fpu.state);
+                } else
+                        stts();
+        } else {
+                old->fpu_counter = 0;
+                old->thread.fpu.last_cpu = ~0;
+                if (fpu.preload) {
+                        new->fpu_counter++;
+                        if (fpu_lazy_restore(new, cpu))
+                                fpu.preload = 0;
+                        else
+                                prefetch(new->thread.fpu.state);
+                        __thread_fpu_begin(new);
+                }
+        }
+        return fpu;
+}
+
+/*
+ * By the time this gets called, we've already cleared CR0.TS and
+ * given the process the FPU if we are going to preload the FPU
+ * state - all we need to do is to conditionally restore the register
+ * state itself.
+ */
+static inline void switch_fpu_finish(struct task_struct *new, fpu_switch_t fpu)
+{
+        if (fpu.preload) {
+                if (unlikely(restore_fpu_checking(new)))
+                        __thread_fpu_end(new);
+        }
+}
+
+/*
+ * Signal frame handlers...
+ */
+extern int save_i387_xstate(void __user *buf);
+extern int restore_i387_xstate(void __user *buf);
+
+static inline void __clear_fpu(struct task_struct *tsk)
+{
+        if (__thread_has_fpu(tsk)) {
+                /* Ignore delayed exceptions from user space */
+                asm volatile("1: fwait\n"
+                             "2:\n"
+                             _ASM_EXTABLE(1b, 2b));
+                __thread_fpu_end(tsk);
+        }
+}
+
+/*
+ * The actual user_fpu_begin/end() functions
+ * need to be preemption-safe.
+ *
+ * NOTE! user_fpu_end() must be used only after you
+ * have saved the FP state, and user_fpu_begin() must
+ * be used only immediately before restoring it.
+ * These functions do not do any save/restore on
+ * their own.
+ */
+static inline void user_fpu_end(void)
+{
+        preempt_disable();
+        __thread_fpu_end(current);
+        preempt_enable();
+}
+
+static inline void user_fpu_begin(void)
+{
+        preempt_disable();
+        if (!user_has_fpu())
+                __thread_fpu_begin(current);
+        preempt_enable();
+}
+
+/*
+ * These disable preemption on their own and are safe
+ */
+static inline void save_init_fpu(struct task_struct *tsk)
+{
+        WARN_ON_ONCE(!__thread_has_fpu(tsk));
+        preempt_disable();
+        __save_init_fpu(tsk);
+        __thread_fpu_end(tsk);
+        preempt_enable();
+}
+
+static inline void clear_fpu(struct task_struct *tsk)
+{
+        preempt_disable();
+        __clear_fpu(tsk);
+        preempt_enable();
+}
+
+/*
+ * i387 state interaction
+ */
+static inline unsigned short get_fpu_cwd(struct task_struct *tsk)
+{
+        if (cpu_has_fxsr) {
+                return tsk->thread.fpu.state->fxsave.cwd;
+        } else {
+                return (unsigned short)tsk->thread.fpu.state->fsave.cwd;
+        }
+}
+
+static inline unsigned short get_fpu_swd(struct task_struct *tsk)
+{
+        if (cpu_has_fxsr) {
+                return tsk->thread.fpu.state->fxsave.swd;
+        } else {
+                return (unsigned short)tsk->thread.fpu.state->fsave.swd;
+        }
+}
+
+static inline unsigned short get_fpu_mxcsr(struct task_struct *tsk)
+{
+        if (cpu_has_xmm) {
+                return tsk->thread.fpu.state->fxsave.mxcsr;
+        } else {
+                return MXCSR_DEFAULT;
+        }
+}
+
+static bool fpu_allocated(struct fpu *fpu)
+{
+        return fpu->state != NULL;
+}
+
+static inline int fpu_alloc(struct fpu *fpu)
+{
+        if (fpu_allocated(fpu))
+                return 0;
+        fpu->state = kmem_cache_alloc(task_xstate_cachep, GFP_KERNEL);
+        if (!fpu->state)
+                return -ENOMEM;
+        WARN_ON((unsigned long)fpu->state & 15);
+        return 0;
+}
+
+static inline void fpu_free(struct fpu *fpu)
+{
+        if (fpu->state) {
+                kmem_cache_free(task_xstate_cachep, fpu->state);
+                fpu->state = NULL;
+        }
+}
+
+static inline void fpu_copy(struct fpu *dst, struct fpu *src)
+{
+        memcpy(dst->state, src->state, xstate_size);
+}
+
+extern void fpu_finit(struct fpu *fpu);
+
+#endif
diff --git a/arch/x86/include/asm/i387.h b/arch/x86/include/asm/i387.h
index 247904945d3..7ce0798b1b2 100644
--- a/arch/x86/include/asm/i387.h
+++ b/arch/x86/include/asm/i387.h
@@ -13,476 +13,19 @@
 #ifndef __ASSEMBLY__
 
 #include <linux/sched.h>
-#include <linux/kernel_stat.h>
-#include <linux/regset.h>
 #include <linux/hardirq.h>
-#include <linux/slab.h>
-#include <asm/asm.h>
-#include <asm/cpufeature.h>
-#include <asm/processor.h>
-#include <asm/sigcontext.h>
-#include <asm/user.h>
-#include <asm/uaccess.h>
-#include <asm/xsave.h>
+#include <asm/system.h>
+
+struct pt_regs;
+struct user_i387_struct;
 
-extern unsigned int sig_xstate_size;
-extern void fpu_init(void);
-extern void mxcsr_feature_mask_init(void);
 extern int init_fpu(struct task_struct *child);
-extern void math_state_restore(void);
 extern int dump_fpu(struct pt_regs *, struct user_i387_struct *);
+extern void math_state_restore(void);
 
-DECLARE_PER_CPU(struct task_struct *, fpu_owner_task);
-
-extern user_regset_active_fn fpregs_active, xfpregs_active;
-extern user_regset_get_fn fpregs_get, xfpregs_get, fpregs_soft_get,
-                                xstateregs_get;
-extern user_regset_set_fn fpregs_set, xfpregs_set, fpregs_soft_set,
-                                 xstateregs_set;
-
-/*
- * xstateregs_active == fpregs_active. Please refer to the comment
- * at the definition of fpregs_active.
- */
-#define xstateregs_active       fpregs_active
-
-extern struct _fpx_sw_bytes fx_sw_reserved;
-#ifdef CONFIG_IA32_EMULATION
-extern unsigned int sig_xstate_ia32_size;
-extern struct _fpx_sw_bytes fx_sw_reserved_ia32;
-struct _fpstate_ia32;
-struct _xstate_ia32;
-extern int save_i387_xstate_ia32(void __user *buf);
-extern int restore_i387_xstate_ia32(void __user *buf);
-#endif
-
-#ifdef CONFIG_MATH_EMULATION
-extern void finit_soft_fpu(struct i387_soft_struct *soft);
-#else
-static inline void finit_soft_fpu(struct i387_soft_struct *soft) {}
-#endif
-
-#define X87_FSW_ES (1 << 7)     /* Exception Summary */
-
-static __always_inline __pure bool use_xsaveopt(void)
-{
-        return static_cpu_has(X86_FEATURE_XSAVEOPT);
-}
-
-static __always_inline __pure bool use_xsave(void)
-{
-        return static_cpu_has(X86_FEATURE_XSAVE);
-}
-
-static __always_inline __pure bool use_fxsr(void)
-{
-        return static_cpu_has(X86_FEATURE_FXSR);
-}
-
-extern void __sanitize_i387_state(struct task_struct *);
-
-static inline void sanitize_i387_state(struct task_struct *tsk)
-{
-        if (!use_xsaveopt())
-                return;
-        __sanitize_i387_state(tsk);
-}
-
-#ifdef CONFIG_X86_64
-static inline int fxrstor_checking(struct i387_fxsave_struct *fx)
-{
-        int err;
-
-        /* See comment in fxsave() below. */
-#ifdef CONFIG_AS_FXSAVEQ
-        asm volatile("1:  fxrstorq %[fx]\n\t"
-                     "2:\n"
-                     ".section .fixup,\"ax\"\n"
-                     "3:  movl $-1,%[err]\n"
-                     "    jmp  2b\n"
-                     ".previous\n"
-                     _ASM_EXTABLE(1b, 3b)
-                     : [err] "=r" (err)
-                     : [fx] "m" (*fx), "0" (0));
-#else
-        asm volatile("1:  rex64/fxrstor (%[fx])\n\t"
-                     "2:\n"
-                     ".section .fixup,\"ax\"\n"
-                     "3:  movl $-1,%[err]\n"
-                     "    jmp  2b\n"
-                     ".previous\n"
-                     _ASM_EXTABLE(1b, 3b)
-                     : [err] "=r" (err)
-                     : [fx] "R" (fx), "m" (*fx), "0" (0));
-#endif
-        return err;
-}
-
-static inline int fxsave_user(struct i387_fxsave_struct __user *fx)
-{
-        int err;
-
-        /*
-         * Clear the bytes not touched by the fxsave and reserved
-         * for the SW usage.
-         */
-        err = __clear_user(&fx->sw_reserved,
-                           sizeof(struct _fpx_sw_bytes));
-        if (unlikely(err))
-                return -EFAULT;
-
-        /* See comment in fxsave() below. */
-#ifdef CONFIG_AS_FXSAVEQ
-        asm volatile("1:  fxsaveq %[fx]\n\t"
-                     "2:\n"
-                     ".section .fixup,\"ax\"\n"
-                     "3:  movl $-1,%[err]\n"
-                     "    jmp  2b\n"
-                     ".previous\n"
-                     _ASM_EXTABLE(1b, 3b)
-                     : [err] "=r" (err), [fx] "=m" (*fx)
-                     : "0" (0));
-#else
-        asm volatile("1:  rex64/fxsave (%[fx])\n\t"
-                     "2:\n"
-                     ".section .fixup,\"ax\"\n"
-                     "3:  movl $-1,%[err]\n"
-                     "    jmp  2b\n"
-                     ".previous\n"
-                     _ASM_EXTABLE(1b, 3b)
-                     : [err] "=r" (err), "=m" (*fx)
-                     : [fx] "R" (fx), "0" (0));
-#endif
-        if (unlikely(err) &&
-            __clear_user(fx, sizeof(struct i387_fxsave_struct)))
-                err = -EFAULT;
-        /* No need to clear here because the caller clears USED_MATH */
-        return err;
-}
-
-static inline void fpu_fxsave(struct fpu *fpu)
-{
-        /* Using "rex64; fxsave %0" is broken because, if the memory operand
-           uses any extended registers for addressing, a second REX prefix
-           will be generated (to the assembler, rex64 followed by semicolon
-           is a separate instruction), and hence the 64-bitness is lost. */
-
-#ifdef CONFIG_AS_FXSAVEQ
-        /* Using "fxsaveq %0" would be the ideal choice, but is only supported
-           starting with gas 2.16. */
-        __asm__ __volatile__("fxsaveq %0"
-                             : "=m" (fpu->state->fxsave));
-#else
-        /* Using, as a workaround, the properly prefixed form below isn't
-           accepted by any binutils version so far released, complaining that
-           the same type of prefix is used twice if an extended register is
-           needed for addressing (fix submitted to mainline 2005-11-21).
-        asm volatile("rex64/fxsave %0"
-                     : "=m" (fpu->state->fxsave));
-           This, however, we can work around by forcing the compiler to select
-           an addressing mode that doesn't require extended registers. */
-        asm volatile("rex64/fxsave (%[fx])"
-                     : "=m" (fpu->state->fxsave)
-                     : [fx] "R" (&fpu->state->fxsave));
-#endif
-}
-
-#else  /* CONFIG_X86_32 */
-
-/* perform fxrstor iff the processor has extended states, otherwise frstor */
-static inline int fxrstor_checking(struct i387_fxsave_struct *fx)
-{
-        /*
-         * The "nop" is needed to make the instructions the same
-         * length.
-         */
-        alternative_input(
-                "nop ; frstor %1",
-                "fxrstor %1",
-                X86_FEATURE_FXSR,
-                "m" (*fx));
-
-        return 0;
-}
-
-static inline void fpu_fxsave(struct fpu *fpu)
-{
-        asm volatile("fxsave %[fx]"
-                     : [fx] "=m" (fpu->state->fxsave));
-}
-
-#endif  /* CONFIG_X86_64 */
-
-/*
- * These must be called with preempt disabled. Returns
- * 'true' if the FPU state is still intact.
- */
-static inline int fpu_save_init(struct fpu *fpu)
-{
-        if (use_xsave()) {
-                fpu_xsave(fpu);
-
-                /*
-                 * xsave header may indicate the init state of the FP.
-                 */
-                if (!(fpu->state->xsave.xsave_hdr.xstate_bv & XSTATE_FP))
-                        return 1;
-        } else if (use_fxsr()) {
-                fpu_fxsave(fpu);
-        } else {
-                asm volatile("fnsave %[fx]; fwait"
-                             : [fx] "=m" (fpu->state->fsave));
-                return 0;
-        }
-
-        /*
-         * If exceptions are pending, we need to clear them so
-         * that we don't randomly get exceptions later.
-         *
-         * FIXME! Is this perhaps only true for the old-style
-         * irq13 case? Maybe we could leave the x87 state
-         * intact otherwise?
-         */
-        if (unlikely(fpu->state->fxsave.swd & X87_FSW_ES)) {
-                asm volatile("fnclex");
-                return 0;
-        }
-        return 1;
-}
-
-static inline int __save_init_fpu(struct task_struct *tsk)
-{
-        return fpu_save_init(&tsk->thread.fpu);
-}
-
-static inline int fpu_fxrstor_checking(struct fpu *fpu)
-{
-        return fxrstor_checking(&fpu->state->fxsave);
-}
-
-static inline int fpu_restore_checking(struct fpu *fpu)
-{
-        if (use_xsave())
-                return fpu_xrstor_checking(fpu);
-        else
-                return fpu_fxrstor_checking(fpu);
-}
-
-static inline int restore_fpu_checking(struct task_struct *tsk)
-{
-        /* AMD K7/K8 CPUs don't save/restore FDP/FIP/FOP unless an exception
-           is pending.  Clear the x87 state here by setting it to fixed
-           values. "m" is a random variable that should be in L1 */
-        alternative_input(
-                ASM_NOP8 ASM_NOP2,
-                "emms\n\t"              /* clear stack tags */
-                "fildl %P[addr]",       /* set F?P to defined value */
-                X86_FEATURE_FXSAVE_LEAK,
-                [addr] "m" (tsk->thread.fpu.has_fpu));
-
-        return fpu_restore_checking(&tsk->thread.fpu);
-}
-
-/*
- * Software FPU state helpers. Careful: these need to
- * be preemption protection *and* they need to be
- * properly paired with the CR0.TS changes!
- */
-static inline int __thread_has_fpu(struct task_struct *tsk)
-{
-        return tsk->thread.fpu.has_fpu;
-}
-
-/* Must be paired with an 'stts' after! */
-static inline void __thread_clear_has_fpu(struct task_struct *tsk)
-{
-        tsk->thread.fpu.has_fpu = 0;
-        percpu_write(fpu_owner_task, NULL);
-}
-
-/* Must be paired with a 'clts' before! */
-static inline void __thread_set_has_fpu(struct task_struct *tsk)
-{
-        tsk->thread.fpu.has_fpu = 1;
-        percpu_write(fpu_owner_task, tsk);
-}
-
-/*
- * Encapsulate the CR0.TS handling together with the
- * software flag.
- *
- * These generally need preemption protection to work,
- * do try to avoid using these on their own.
- */
-static inline void __thread_fpu_end(struct task_struct *tsk)
-{
-        __thread_clear_has_fpu(tsk);
-        stts();
-}
-
-static inline void __thread_fpu_begin(struct task_struct *tsk)
-{
-        clts();
-        __thread_set_has_fpu(tsk);
-}
-
-/*
- * FPU state switching for scheduling.
- *
- * This is a two-stage process:
- *
- *  - switch_fpu_prepare() saves the old state and
- *    sets the new state of the CR0.TS bit. This is
- *    done within the context of the old process.
- *
- *  - switch_fpu_finish() restores the new state as
- *    necessary.
- */
-typedef struct { int preload; } fpu_switch_t;
-
-/*
- * FIXME! We could do a totally lazy restore, but we need to
- * add a per-cpu "this was the task that last touched the FPU
- * on this CPU" variable, and the task needs to have a "I last
- * touched the FPU on this CPU" and check them.
- *
- * We don't do that yet, so "fpu_lazy_restore()" always returns
- * false, but some day..
- */
-static inline int fpu_lazy_restore(struct task_struct *new, unsigned int cpu)
-{
-        return new == percpu_read_stable(fpu_owner_task) &&
-                cpu == new->thread.fpu.last_cpu;
-}
-
-static inline fpu_switch_t switch_fpu_prepare(struct task_struct *old, struct task_struct *new, int cpu)
-{
-        fpu_switch_t fpu;
-
-        fpu.preload = tsk_used_math(new) && new->fpu_counter > 5;
-        if (__thread_has_fpu(old)) {
-                if (!__save_init_fpu(old))
-                        cpu = ~0;
-                old->thread.fpu.last_cpu = cpu;
-                old->thread.fpu.has_fpu = 0;    /* But leave fpu_owner_task! */
-
-                /* Don't change CR0.TS if we just switch! */
-                if (fpu.preload) {
-                        new->fpu_counter++;
-                        __thread_set_has_fpu(new);
-                        prefetch(new->thread.fpu.state);
-                } else
-                        stts();
-        } else {
-                old->fpu_counter = 0;
-                old->thread.fpu.last_cpu = ~0;
-                if (fpu.preload) {
-                        new->fpu_counter++;
-                        if (fpu_lazy_restore(new, cpu))
-                                fpu.preload = 0;
-                        else
-                                prefetch(new->thread.fpu.state);
-                        __thread_fpu_begin(new);
-                }
-        }
-        return fpu;
-}
-
-/*
- * By the time this gets called, we've already cleared CR0.TS and
- * given the process the FPU if we are going to preload the FPU
- * state - all we need to do is to conditionally restore the register
- * state itself.
- */
-static inline void switch_fpu_finish(struct task_struct *new, fpu_switch_t fpu)
-{
-        if (fpu.preload) {
-                if (unlikely(restore_fpu_checking(new)))
-                        __thread_fpu_end(new);
-        }
-}
-
-/*
- * Signal frame handlers...
- */
-extern int save_i387_xstate(void __user *buf);
-extern int restore_i387_xstate(void __user *buf);
-
-static inline void __clear_fpu(struct task_struct *tsk)
-{
-        if (__thread_has_fpu(tsk)) {
-                /* Ignore delayed exceptions from user space */
-                asm volatile("1: fwait\n"
-                             "2:\n"
-                             _ASM_EXTABLE(1b, 2b));
-                __thread_fpu_end(tsk);
-        }
-}
-
-/*
- * Were we in an interrupt that interrupted kernel mode?
- *
- * We can do a kernel_fpu_begin/end() pair *ONLY* if that
- * pair does nothing at all: the thread must not have fpu (so
- * that we don't try to save the FPU state), and TS must
- * be set (so that the clts/stts pair does nothing that is
- * visible in the interrupted kernel thread).
- */
-static inline bool interrupted_kernel_fpu_idle(void)
-{
-        return !__thread_has_fpu(current) &&
-                (read_cr0() & X86_CR0_TS);
-}
-
-/*
- * Were we in user mode (or vm86 mode) when we were
- * interrupted?
- *
- * Doing kernel_fpu_begin/end() is ok if we are running
- * in an interrupt context from user mode - we'll just
- * save the FPU state as required.
- */
-static inline bool interrupted_user_mode(void)
-{
-        struct pt_regs *regs = get_irq_regs();
-        return regs && user_mode_vm(regs);
-}
-
-/*
- * Can we use the FPU in kernel mode with the
- * whole "kernel_fpu_begin/end()" sequence?
- *
- * It's always ok in process context (ie "not interrupt")
- * but it is sometimes ok even from an irq.
- */
-static inline bool irq_fpu_usable(void)
-{
-        return !in_interrupt() ||
-                interrupted_user_mode() ||
-                interrupted_kernel_fpu_idle();
-}
-
-static inline void kernel_fpu_begin(void)
-{
-        struct task_struct *me = current;
-
-        WARN_ON_ONCE(!irq_fpu_usable());
-        preempt_disable();
-        if (__thread_has_fpu(me)) {
-                __save_init_fpu(me);
-                __thread_clear_has_fpu(me);
-                /* We do 'stts()' in kernel_fpu_end() */
-        } else {
-                percpu_write(fpu_owner_task, NULL);
-                clts();
-        }
-}
-
-static inline void kernel_fpu_end(void)
-{
-        stts();
-        preempt_enable();
-}
+extern bool irq_fpu_usable(void);
+extern void kernel_fpu_begin(void);
+extern void kernel_fpu_end(void);
 
 /*
  * Some instructions like VIA's padlock instructions generate a spurious
@@ -524,126 +67,13 @@ static inline void irq_ts_restore(int TS_state)
  * we can just assume we have FPU access - typically
  * to save the FP state - we'll just take a #NM
  * fault and get the FPU access back.
- *
- * The actual user_fpu_begin/end() functions
- * need to be preemption-safe, though.
- *
- * NOTE! user_fpu_end() must be used only after you
- * have saved the FP state, and user_fpu_begin() must
- * be used only immediately before restoring it.
- * These functions do not do any save/restore on
- * their own.
  */
 static inline int user_has_fpu(void)
 {
-        return __thread_has_fpu(current);
-}
-
-static inline void user_fpu_end(void)
-{
-        preempt_disable();
-        __thread_fpu_end(current);
-        preempt_enable();
-}
-
-static inline void user_fpu_begin(void)
-{
-        preempt_disable();
-        if (!user_has_fpu())
-                __thread_fpu_begin(current);
-        preempt_enable();
-}
-
-/*
- * These disable preemption on their own and are safe
- */
-static inline void save_init_fpu(struct task_struct *tsk)
-{
-        WARN_ON_ONCE(!__thread_has_fpu(tsk));
-        preempt_disable();
-        __save_init_fpu(tsk);
-        __thread_fpu_end(tsk);
-        preempt_enable();
-}
-
-static inline void unlazy_fpu(struct task_struct *tsk)
-{
-        preempt_disable();
-        if (__thread_has_fpu(tsk)) {
-                __save_init_fpu(tsk);
-                __thread_fpu_end(tsk);
-        } else
-                tsk->fpu_counter = 0;
-        preempt_enable();
-}
-
-static inline void clear_fpu(struct task_struct *tsk)
-{
-        preempt_disable();
-        __clear_fpu(tsk);
-        preempt_enable();
-}
-
-/*
- * i387 state interaction
- */
-static inline unsigned short get_fpu_cwd(struct task_struct *tsk)
-{
-        if (cpu_has_fxsr) {
-                return tsk->thread.fpu.state->fxsave.cwd;
-        } else {
-                return (unsigned short)tsk->thread.fpu.state->fsave.cwd;
-        }
-}
-
-static inline unsigned short get_fpu_swd(struct task_struct *tsk)
-{
-        if (cpu_has_fxsr) {
-                return tsk->thread.fpu.state->fxsave.swd;
-        } else {
-                return (unsigned short)tsk->thread.fpu.state->fsave.swd;
-        }
-}
-
-static inline unsigned short get_fpu_mxcsr(struct task_struct *tsk)
-{
-        if (cpu_has_xmm) {
-                return tsk->thread.fpu.state->fxsave.mxcsr;
-        } else {
-                return MXCSR_DEFAULT;
-        }
-}
-
-static bool fpu_allocated(struct fpu *fpu)
-{
-        return fpu->state != NULL;
-}
-
-static inline int fpu_alloc(struct fpu *fpu)
-{
-        if (fpu_allocated(fpu))
-                return 0;
-        fpu->state = kmem_cache_alloc(task_xstate_cachep, GFP_KERNEL);
-        if (!fpu->state)
-                return -ENOMEM;
-        WARN_ON((unsigned long)fpu->state & 15);
-        return 0;
-}
-
-static inline void fpu_free(struct fpu *fpu)
-{
-        if (fpu->state) {
-                kmem_cache_free(task_xstate_cachep, fpu->state);
-                fpu->state = NULL;
-        }
-}
-
-static inline void fpu_copy(struct fpu *dst, struct fpu *src)
-{
-        memcpy(dst->state, src->state, xstate_size);
+        return current->thread.fpu.has_fpu;
 }
 
-extern void fpu_finit(struct fpu *fpu);
+extern void unlazy_fpu(struct task_struct *tsk);
 
 #endif /* __ASSEMBLY__ */
 
diff --git a/arch/x86/include/asm/kgdb.h b/arch/x86/include/asm/kgdb.h
index 77e95f54570..332f98c9111 100644
--- a/arch/x86/include/asm/kgdb.h
+++ b/arch/x86/include/asm/kgdb.h
@@ -64,11 +64,15 @@ enum regnames {
         GDB_PS,                 /* 17 */
         GDB_CS,                 /* 18 */
         GDB_SS,                 /* 19 */
+        GDB_DS,                 /* 20 */
+        GDB_ES,                 /* 21 */
+        GDB_FS,                 /* 22 */
+        GDB_GS,                 /* 23 */
 };
 #define GDB_ORIG_AX             57
-#define DBG_MAX_REG_NUM         20
-/* 17 64 bit regs and 3 32 bit regs */
-#define NUMREGBYTES             ((17 * 8) + (3 * 4))
+#define DBG_MAX_REG_NUM         24
+/* 17 64 bit regs and 5 32 bit regs */
+#define NUMREGBYTES             ((17 * 8) + (5 * 4))
 #endif /* ! CONFIG_X86_32 */
 
 static inline void arch_kgdb_breakpoint(void)
diff --git a/arch/x86/include/asm/mce.h b/arch/x86/include/asm/mce.h
index 6aefb14cbbc..441520e4174 100644
--- a/arch/x86/include/asm/mce.h
+++ b/arch/x86/include/asm/mce.h
@@ -151,7 +151,7 @@ static inline void enable_p5_mce(void) {}
 
 void mce_setup(struct mce *m);
 void mce_log(struct mce *m);
-extern struct device *mce_device[CONFIG_NR_CPUS];
+DECLARE_PER_CPU(struct device *, mce_device);
 
 /*
  * Maximum banks number.
diff --git a/arch/x86/include/asm/mrst.h b/arch/x86/include/asm/mrst.h
index 0a0a9546043..fc18bf3ce7c 100644
--- a/arch/x86/include/asm/mrst.h
+++ b/arch/x86/include/asm/mrst.h
@@ -26,8 +26,8 @@ extern struct sfi_rtc_table_entry sfi_mrtc_array[];
  * identified via MSRs.
  */
 enum mrst_cpu_type {
-        MRST_CPU_CHIP_LINCROFT = 1,
-        MRST_CPU_CHIP_PENWELL,
+        /* 1 was Moorestown */
+        MRST_CPU_CHIP_PENWELL = 2,
 };
 
 extern enum mrst_cpu_type __mrst_cpu_chip;
diff --git a/arch/x86/include/asm/paravirt.h b/arch/x86/include/asm/paravirt.h
index c0180fd372d..aa0f9130836 100644
--- a/arch/x86/include/asm/paravirt.h
+++ b/arch/x86/include/asm/paravirt.h
@@ -10,6 +10,7 @@
 #include <asm/paravirt_types.h>
 
 #ifndef __ASSEMBLY__
+#include <linux/bug.h>
 #include <linux/types.h>
 #include <linux/cpumask.h>
 
diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/processor.h
index 58545c97d07..5533b30cac0 100644
--- a/arch/x86/include/asm/processor.h
+++ b/arch/x86/include/asm/processor.h
@@ -162,6 +162,7 @@ extern void early_cpu_init(void);
 extern void identify_boot_cpu(void);
 extern void identify_secondary_cpu(struct cpuinfo_x86 *);
 extern void print_cpu_info(struct cpuinfo_x86 *);
+void print_cpu_msr(struct cpuinfo_x86 *);
 extern void init_scattered_cpuid_features(struct cpuinfo_x86 *c);
 extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c);
 extern unsigned short num_cache_leaves;
@@ -474,61 +475,6 @@ struct thread_struct {
         unsigned                io_bitmap_max;
 };
 
-static inline unsigned long native_get_debugreg(int regno)
-{
-        unsigned long val = 0;  /* Damn you, gcc! */
-
-        switch (regno) {
-        case 0:
-                asm("mov %%db0, %0" :"=r" (val));
-                break;
-        case 1:
-                asm("mov %%db1, %0" :"=r" (val));
-                break;
-        case 2:
-                asm("mov %%db2, %0" :"=r" (val));
-                break;
-        case 3:
-                asm("mov %%db3, %0" :"=r" (val));
-                break;
-        case 6:
-                asm("mov %%db6, %0" :"=r" (val));
-                break;
-        case 7:
-                asm("mov %%db7, %0" :"=r" (val));
-                break;
-        default:
-                BUG();
-        }
-        return val;
-}
-
-static inline void native_set_debugreg(int regno, unsigned long value)
-{
-        switch (regno) {
-        case 0:
-                asm("mov %0, %%db0"     ::"r" (value));
-                break;
-        case 1:
-                asm("mov %0, %%db1"     ::"r" (value));
-                break;
-        case 2:
-                asm("mov %0, %%db2"     ::"r" (value));
-                break;
-        case 3:
-                asm("mov %0, %%db3"     ::"r" (value));
-                break;
-        case 6:
-                asm("mov %0, %%db6"     ::"r" (value));
-                break;
-        case 7:
-                asm("mov %0, %%db7"     ::"r" (value));
-                break;
-        default:
-                BUG();
-        }
-}
-
 /*
  * Set IOPL bits in EFLAGS from given mask
  */
@@ -574,14 +520,6 @@ static inline void native_swapgs(void)
 #define __cpuid                 native_cpuid
 #define paravirt_enabled()      0
 
-/*
- * These special macros can be used to get or set a debugging register
- */
-#define get_debugreg(var, register)                             \
-        (var) = native_get_debugreg(register)
-#define set_debugreg(value, register)                           \
-        native_set_debugreg(register, value)
-
 static inline void load_sp0(struct tss_struct *tss,
                             struct thread_struct *thread)
 {
diff --git a/arch/x86/include/asm/spinlock.h b/arch/x86/include/asm/spinlock.h
index a82c2bf504b..76bfa2cf301 100644
--- a/arch/x86/include/asm/spinlock.h
+++ b/arch/x86/include/asm/spinlock.h
@@ -88,14 +88,14 @@ static inline int __ticket_spin_is_locked(arch_spinlock_t *lock)
 {
         struct __raw_tickets tmp = ACCESS_ONCE(lock->tickets);
 
-        return !!(tmp.tail ^ tmp.head);
+        return tmp.tail != tmp.head;
 }
 
 static inline int __ticket_spin_is_contended(arch_spinlock_t *lock)
 {
         struct __raw_tickets tmp = ACCESS_ONCE(lock->tickets);
 
-        return ((tmp.tail - tmp.head) & TICKET_MASK) > 1;
+        return (__ticket_t)(tmp.tail - tmp.head) > 1;
 }
 
 #ifndef CONFIG_PARAVIRT_SPINLOCKS
diff --git a/arch/x86/include/asm/spinlock_types.h b/arch/x86/include/asm/spinlock_types.h
index 8ebd5df7451..ad0ad07fc00 100644
--- a/arch/x86/include/asm/spinlock_types.h
+++ b/arch/x86/include/asm/spinlock_types.h
@@ -16,7 +16,6 @@ typedef u32 __ticketpair_t;
 #endif
 
 #define TICKET_SHIFT    (sizeof(__ticket_t) * 8)
-#define TICKET_MASK     ((__ticket_t)((1 << TICKET_SHIFT) - 1))
 
 typedef struct arch_spinlock {
         union {
diff --git a/arch/x86/include/asm/xen/interface.h b/arch/x86/include/asm/xen/interface.h
index a1f2db5f117..cbf0c9d50b9 100644
--- a/arch/x86/include/asm/xen/interface.h
+++ b/arch/x86/include/asm/xen/interface.h
@@ -56,6 +56,7 @@ DEFINE_GUEST_HANDLE(int);
 DEFINE_GUEST_HANDLE(long);
 DEFINE_GUEST_HANDLE(void);
 DEFINE_GUEST_HANDLE(uint64_t);
+DEFINE_GUEST_HANDLE(uint32_t);
 #endif
 
 #ifndef HYPERVISOR_VIRT_START
diff --git a/arch/x86/kernel/acpi/boot.c b/arch/x86/kernel/acpi/boot.c
index ce664f33ea8..406ed77216d 100644
--- a/arch/x86/kernel/acpi/boot.c
+++ b/arch/x86/kernel/acpi/boot.c
@@ -593,7 +593,7 @@ void __init acpi_set_irq_model_ioapic(void)
 #ifdef CONFIG_ACPI_HOTPLUG_CPU
 #include <acpi/processor.h>
 
-static void acpi_map_cpu2node(acpi_handle handle, int cpu, int physid)
+static void __cpuinitdata acpi_map_cpu2node(acpi_handle handle, int cpu, int physid)
 {
 #ifdef CONFIG_ACPI_NUMA
         int nid;
diff --git a/arch/x86/kernel/apic/apic_flat_64.c b/arch/x86/kernel/apic/apic_flat_64.c
index 8c3cdded6f2..359b6899a36 100644
--- a/arch/x86/kernel/apic/apic_flat_64.c
+++ b/arch/x86/kernel/apic/apic_flat_64.c
@@ -180,6 +180,7 @@ static struct apic apic_flat =  {
         .name                           = "flat",
         .probe                          = flat_probe,
         .acpi_madt_oem_check            = flat_acpi_madt_oem_check,
+        .apic_id_valid                  = default_apic_id_valid,
         .apic_id_registered             = flat_apic_id_registered,
 
         .irq_delivery_mode              = dest_LowestPrio,
@@ -337,6 +338,7 @@ static struct apic apic_physflat =  {
         .name                           = "physical flat",
         .probe                          = physflat_probe,
         .acpi_madt_oem_check            = physflat_acpi_madt_oem_check,
+        .apic_id_valid                  = default_apic_id_valid,
         .apic_id_registered             = flat_apic_id_registered,
 
         .irq_delivery_mode              = dest_Fixed,
diff --git a/arch/x86/kernel/apic/apic_noop.c b/arch/x86/kernel/apic/apic_noop.c
index 775b82bc655..634ae6cdd5c 100644
--- a/arch/x86/kernel/apic/apic_noop.c
+++ b/arch/x86/kernel/apic/apic_noop.c
@@ -124,6 +124,7 @@ struct apic apic_noop = {
         .probe                          = noop_probe,
         .acpi_madt_oem_check            = NULL,
 
+        .apic_id_valid                  = default_apic_id_valid,
         .apic_id_registered             = noop_apic_id_registered,
 
         .irq_delivery_mode              = dest_LowestPrio,
diff --git a/arch/x86/kernel/apic/apic_numachip.c b/arch/x86/kernel/apic/apic_numachip.c
index 09d3d8c1cd9..d9ea5f331ac 100644
--- a/arch/x86/kernel/apic/apic_numachip.c
+++ b/arch/x86/kernel/apic/apic_numachip.c
@@ -56,6 +56,12 @@ static unsigned int read_xapic_id(void)
         return get_apic_id(apic_read(APIC_ID));
 }
 
+static int numachip_apic_id_valid(int apicid)
+{
+        /* Trust what bootloader passes in MADT */
+        return 1;
+}
+
 static int numachip_apic_id_registered(void)
 {
         return physid_isset(read_xapic_id(), phys_cpu_present_map);
@@ -223,10 +229,11 @@ static int __init numachip_system_init(void)
 }
 early_initcall(numachip_system_init);
 
-static int numachip_acpi_madt_oem_check(char *oem_id, char *oem_table_id)
+static int __cpuinit numachip_acpi_madt_oem_check(char *oem_id, char *oem_table_id)
 {
         if (!strncmp(oem_id, "NUMASC", 6)) {
                 numachip_system = 1;
+                setup_force_cpu_cap(X86_FEATURE_X2APIC);
                 return 1;
         }
 
@@ -238,6 +245,7 @@ static struct apic apic_numachip __refconst = {
         .name                           = "NumaConnect system",
         .probe                          = numachip_probe,
         .acpi_madt_oem_check            = numachip_acpi_madt_oem_check,
+        .apic_id_valid                  = numachip_apic_id_valid,
         .apic_id_registered             = numachip_apic_id_registered,
 
         .irq_delivery_mode              = dest_Fixed,
diff --git a/arch/x86/kernel/apic/bigsmp_32.c b/arch/x86/kernel/apic/bigsmp_32.c
index 521bead0113..0cdec7065af 100644
--- a/arch/x86/kernel/apic/bigsmp_32.c
+++ b/arch/x86/kernel/apic/bigsmp_32.c
@@ -198,6 +198,7 @@ static struct apic apic_bigsmp = {
         .name                           = "bigsmp",
         .probe                          = probe_bigsmp,
         .acpi_madt_oem_check            = NULL,
+        .apic_id_valid                  = default_apic_id_valid,
         .apic_id_registered             = bigsmp_apic_id_registered,
 
         .irq_delivery_mode              = dest_Fixed,
diff --git a/arch/x86/kernel/apic/es7000_32.c b/arch/x86/kernel/apic/es7000_32.c
index 5d513bc47b6..e42d1d3b913 100644
--- a/arch/x86/kernel/apic/es7000_32.c
+++ b/arch/x86/kernel/apic/es7000_32.c
@@ -625,6 +625,7 @@ static struct apic __refdata apic_es7000_cluster = {
         .name                           = "es7000",
         .probe                          = probe_es7000,
         .acpi_madt_oem_check            = es7000_acpi_madt_oem_check_cluster,
+        .apic_id_valid                  = default_apic_id_valid,
         .apic_id_registered             = es7000_apic_id_registered,
 
         .irq_delivery_mode              = dest_LowestPrio,
@@ -690,6 +691,7 @@ static struct apic __refdata apic_es7000 = {
         .name                           = "es7000",
         .probe                          = probe_es7000,
         .acpi_madt_oem_check            = es7000_acpi_madt_oem_check,
+        .apic_id_valid                  = default_apic_id_valid,
         .apic_id_registered             = es7000_apic_id_registered,
 
         .irq_delivery_mode              = dest_Fixed,
diff --git a/arch/x86/kernel/apic/io_apic.c b/arch/x86/kernel/apic/io_apic.c
index fb072754bc1..6d10a66fc5a 100644
--- a/arch/x86/kernel/apic/io_apic.c
+++ b/arch/x86/kernel/apic/io_apic.c
@@ -3967,18 +3967,36 @@ int mp_find_ioapic_pin(int ioapic, u32 gsi)
 static __init int bad_ioapic(unsigned long address)
 {
         if (nr_ioapics >= MAX_IO_APICS) {
-                printk(KERN_WARNING "WARNING: Max # of I/O APICs (%d) exceeded "
-                       "(found %d), skipping\n", MAX_IO_APICS, nr_ioapics);
+                pr_warn("WARNING: Max # of I/O APICs (%d) exceeded (found %d), skipping\n",
+                        MAX_IO_APICS, nr_ioapics);
                 return 1;
         }
         if (!address) {
-                printk(KERN_WARNING "WARNING: Bogus (zero) I/O APIC address"
-                       " found in table, skipping!\n");
+                pr_warn("WARNING: Bogus (zero) I/O APIC address found in table, skipping!\n");
                 return 1;
         }
         return 0;
 }
 
+static __init int bad_ioapic_register(int idx)
+{
+        union IO_APIC_reg_00 reg_00;
+        union IO_APIC_reg_01 reg_01;
+        union IO_APIC_reg_02 reg_02;
+
+        reg_00.raw = io_apic_read(idx, 0);
+        reg_01.raw = io_apic_read(idx, 1);
+        reg_02.raw = io_apic_read(idx, 2);
+
+        if (reg_00.raw == -1 && reg_01.raw == -1 && reg_02.raw == -1) {
+                pr_warn("I/O APIC 0x%x registers return all ones, skipping!\n",
+                        mpc_ioapic_addr(idx));
+                return 1;
+        }
+
+        return 0;
+}
+
 void __init mp_register_ioapic(int id, u32 address, u32 gsi_base)
 {
         int idx = 0;
@@ -3995,6 +4013,12 @@ void __init mp_register_ioapic(int id, u32 address, u32 gsi_base)
         ioapics[idx].mp_config.apicaddr = address;
 
         set_fixmap_nocache(FIX_IO_APIC_BASE_0 + idx, address);
+
+        if (bad_ioapic_register(idx)) {
+                clear_fixmap(FIX_IO_APIC_BASE_0 + idx);
+                return;
+        }
+
         ioapics[idx].mp_config.apicid = io_apic_unique_id(id);
         ioapics[idx].mp_config.apicver = io_apic_get_version(idx);
 
@@ -4015,10 +4039,10 @@ void __init mp_register_ioapic(int id, u32 address, u32 gsi_base)
         if (gsi_cfg->gsi_end >= gsi_top)
                 gsi_top = gsi_cfg->gsi_end + 1;
 
-        printk(KERN_INFO "IOAPIC[%d]: apic_id %d, version %d, address 0x%x, "
-               "GSI %d-%d\n", idx, mpc_ioapic_id(idx),
-               mpc_ioapic_ver(idx), mpc_ioapic_addr(idx),
-               gsi_cfg->gsi_base, gsi_cfg->gsi_end);
+        pr_info("IOAPIC[%d]: apic_id %d, version %d, address 0x%x, GSI %d-%d\n",
+                idx, mpc_ioapic_id(idx),
+                mpc_ioapic_ver(idx), mpc_ioapic_addr(idx),
+                gsi_cfg->gsi_base, gsi_cfg->gsi_end);
 
         nr_ioapics++;
 }
diff --git a/arch/x86/kernel/apic/numaq_32.c b/arch/x86/kernel/apic/numaq_32.c
index c4a61ca1349..00d2422ca7c 100644
--- a/arch/x86/kernel/apic/numaq_32.c
+++ b/arch/x86/kernel/apic/numaq_32.c
@@ -478,6 +478,7 @@ static struct apic __refdata apic_numaq = {
         .name                           = "NUMAQ",
         .probe                          = probe_numaq,
         .acpi_madt_oem_check            = NULL,
+        .apic_id_valid                  = default_apic_id_valid,
         .apic_id_registered             = numaq_apic_id_registered,
 
         .irq_delivery_mode              = dest_LowestPrio,
diff --git a/arch/x86/kernel/apic/probe_32.c b/arch/x86/kernel/apic/probe_32.c
index 0787bb3412f..ff2c1b9aac4 100644
--- a/arch/x86/kernel/apic/probe_32.c
+++ b/arch/x86/kernel/apic/probe_32.c
@@ -92,6 +92,7 @@ static struct apic apic_default = {
         .name                           = "default",
         .probe                          = probe_default,
         .acpi_madt_oem_check            = NULL,
+        .apic_id_valid                  = default_apic_id_valid,
         .apic_id_registered             = default_apic_id_registered,
 
         .irq_delivery_mode              = dest_LowestPrio,
diff --git a/arch/x86/kernel/apic/summit_32.c b/arch/x86/kernel/apic/summit_32.c
index 19114423c58..fea000b27f0 100644
--- a/arch/x86/kernel/apic/summit_32.c
+++ b/arch/x86/kernel/apic/summit_32.c
@@ -496,6 +496,7 @@ static struct apic apic_summit = {
         .name                           = "summit",
         .probe                          = probe_summit,
         .acpi_madt_oem_check            = summit_acpi_madt_oem_check,
+        .apic_id_valid                  = default_apic_id_valid,
         .apic_id_registered             = summit_apic_id_registered,
 
         .irq_delivery_mode              = dest_LowestPrio,
diff --git a/arch/x86/kernel/apic/x2apic_cluster.c b/arch/x86/kernel/apic/x2apic_cluster.c
index 50079587582..9193713060a 100644
--- a/arch/x86/kernel/apic/x2apic_cluster.c
+++ b/arch/x86/kernel/apic/x2apic_cluster.c
@@ -213,6 +213,7 @@ static struct apic apic_x2apic_cluster = {
         .name                           = "cluster x2apic",
         .probe                          = x2apic_cluster_probe,
         .acpi_madt_oem_check            = x2apic_acpi_madt_oem_check,
+        .apic_id_valid                  = default_apic_id_valid,
         .apic_id_registered             = x2apic_apic_id_registered,
 
         .irq_delivery_mode              = dest_LowestPrio,
diff --git a/arch/x86/kernel/apic/x2apic_phys.c b/arch/x86/kernel/apic/x2apic_phys.c
index f5373dfde21..bcd1db6eaca 100644
--- a/arch/x86/kernel/apic/x2apic_phys.c
+++ b/arch/x86/kernel/apic/x2apic_phys.c
@@ -119,6 +119,7 @@ static struct apic apic_x2apic_phys = {
         .name                           = "physical x2apic",
         .probe                          = x2apic_phys_probe,
         .acpi_madt_oem_check            = x2apic_acpi_madt_oem_check,
+        .apic_id_valid                  = default_apic_id_valid,
         .apic_id_registered             = x2apic_apic_id_registered,
 
         .irq_delivery_mode              = dest_Fixed,
diff --git a/arch/x86/kernel/apic/x2apic_uv_x.c b/arch/x86/kernel/apic/x2apic_uv_x.c
index 79b05b88aa1..fc477142585 100644
--- a/arch/x86/kernel/apic/x2apic_uv_x.c
+++ b/arch/x86/kernel/apic/x2apic_uv_x.c
@@ -351,6 +351,7 @@ static struct apic __refdata apic_x2apic_uv_x = {
         .name                           = "UV large system",
         .probe                          = uv_probe,
         .acpi_madt_oem_check            = uv_acpi_madt_oem_check,
+        .apic_id_valid                  = default_apic_id_valid,
         .apic_id_registered             = uv_apic_id_registered,
 
         .irq_delivery_mode              = dest_Fixed,
diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c
index c0f7d68d318..e49477444ff 100644
--- a/arch/x86/kernel/cpu/common.c
+++ b/arch/x86/kernel/cpu/common.c
@@ -18,6 +18,7 @@
 #include <asm/archrandom.h>
 #include <asm/hypervisor.h>
 #include <asm/processor.h>
+#include <asm/debugreg.h>
 #include <asm/sections.h>
 #include <linux/topology.h>
 #include <linux/cpumask.h>
@@ -28,6 +29,7 @@
 #include <asm/apic.h>
 #include <asm/desc.h>
 #include <asm/i387.h>
+#include <asm/fpu-internal.h>
 #include <asm/mtrr.h>
 #include <linux/numa.h>
 #include <asm/asm.h>
@@ -933,7 +935,7 @@ static const struct msr_range msr_range_array[] __cpuinitconst = {
         { 0xc0011000, 0xc001103b},
 };
 
-static void __cpuinit print_cpu_msr(void)
+static void __cpuinit __print_cpu_msr(void)
 {
         unsigned index_min, index_max;
         unsigned index;
@@ -997,13 +999,13 @@ void __cpuinit print_cpu_info(struct cpuinfo_x86 *c)
         else
                 printk(KERN_CONT "\n");
 
-#ifdef CONFIG_SMP
+        __print_cpu_msr();
+}
+
+void __cpuinit print_cpu_msr(struct cpuinfo_x86 *c)
+{
         if (c->cpu_index < show_msr)
-                print_cpu_msr();
-#else
-        if (show_msr)
-                print_cpu_msr();
-#endif
+                __print_cpu_msr();
 }
 
 static __init int setup_disablecpuid(char *arg)
@@ -1045,7 +1047,6 @@ DEFINE_PER_CPU(char *, irq_stack_ptr) =
 DEFINE_PER_CPU(unsigned int, irq_count) = -1;
 
 DEFINE_PER_CPU(struct task_struct *, fpu_owner_task);
-EXPORT_PER_CPU_SYMBOL(fpu_owner_task);
 
 /*
  * Special IST stacks which the CPU switches to when it calls
@@ -1115,7 +1116,6 @@ void debug_stack_reset(void)
 DEFINE_PER_CPU(struct task_struct *, current_task) = &init_task;
 EXPORT_PER_CPU_SYMBOL(current_task);
 DEFINE_PER_CPU(struct task_struct *, fpu_owner_task);
-EXPORT_PER_CPU_SYMBOL(fpu_owner_task);
 
 #ifdef CONFIG_CC_STACKPROTECTOR
 DEFINE_PER_CPU_ALIGNED(struct stack_canary, stack_canary);
diff --git a/arch/x86/kernel/cpu/mcheck/mce-severity.c b/arch/x86/kernel/cpu/mcheck/mce-severity.c
index 7395d5f4272..0c82091b165 100644
--- a/arch/x86/kernel/cpu/mcheck/mce-severity.c
+++ b/arch/x86/kernel/cpu/mcheck/mce-severity.c
@@ -54,7 +54,14 @@ static struct severity {
 #define  MASK(x, y)     .mask = x, .result = y
 #define MCI_UC_S (MCI_STATUS_UC|MCI_STATUS_S)
 #define MCI_UC_SAR (MCI_STATUS_UC|MCI_STATUS_S|MCI_STATUS_AR)
+#define MCI_ADDR (MCI_STATUS_ADDRV|MCI_STATUS_MISCV)
 #define MCACOD 0xffff
+/* Architecturally defined codes from SDM Vol. 3B Chapter 15 */
+#define MCACOD_SCRUB    0x00C0  /* 0xC0-0xCF Memory Scrubbing */
+#define MCACOD_SCRUBMSK 0xfff0
+#define MCACOD_L3WB     0x017A  /* L3 Explicit Writeback */
+#define MCACOD_DATA     0x0134  /* Data Load */
+#define MCACOD_INSTR    0x0150  /* Instruction Fetch */
 
         MCESEV(
                 NO, "Invalid",
@@ -102,11 +109,24 @@ static struct severity {
                 SER, BITCLR(MCI_STATUS_S)
                 ),
 
-        /* AR add known MCACODs here */
         MCESEV(
                 PANIC, "Action required with lost events",
                 SER, BITSET(MCI_STATUS_OVER|MCI_UC_SAR)
                 ),
+
+        /* known AR MCACODs: */
+#ifdef  CONFIG_MEMORY_FAILURE
+        MCESEV(
+                KEEP, "HT thread notices Action required: data load error",
+                SER, MASK(MCI_STATUS_OVER|MCI_UC_SAR|MCI_ADDR|MCACOD, MCI_UC_SAR|MCI_ADDR|MCACOD_DATA),
+                MCGMASK(MCG_STATUS_EIPV, 0)
+                ),
+        MCESEV(
+                AR, "Action required: data load error",
+                SER, MASK(MCI_STATUS_OVER|MCI_UC_SAR|MCI_ADDR|MCACOD, MCI_UC_SAR|MCI_ADDR|MCACOD_DATA),
+                USER
+                ),
+#endif
         MCESEV(
                 PANIC, "Action required: unknown MCACOD",
                 SER, MASK(MCI_STATUS_OVER|MCI_UC_SAR, MCI_UC_SAR)
@@ -115,11 +135,11 @@ static struct severity {
         /* known AO MCACODs: */
         MCESEV(
                 AO, "Action optional: memory scrubbing error",
-                SER, MASK(MCI_STATUS_OVER|MCI_UC_SAR|0xfff0, MCI_UC_S|0x00c0)
+                SER, MASK(MCI_STATUS_OVER|MCI_UC_SAR|MCACOD_SCRUBMSK, MCI_UC_S|MCACOD_SCRUB)
                 ),
         MCESEV(
                 AO, "Action optional: last level cache writeback error",
-                SER, MASK(MCI_STATUS_OVER|MCI_UC_SAR|MCACOD, MCI_UC_S|0x017a)
+                SER, MASK(MCI_STATUS_OVER|MCI_UC_SAR|MCACOD, MCI_UC_S|MCACOD_L3WB)
                 ),
         MCESEV(
                 SOME, "Action optional: unknown MCACOD",
diff --git a/arch/x86/kernel/cpu/mcheck/mce.c b/arch/x86/kernel/cpu/mcheck/mce.c
index 5a11ae2e9e9..d086a09c087 100644
--- a/arch/x86/kernel/cpu/mcheck/mce.c
+++ b/arch/x86/kernel/cpu/mcheck/mce.c
@@ -191,7 +191,7 @@ static void drain_mcelog_buffer(void)
 {
         unsigned int next, i, prev = 0;
 
-        next = rcu_dereference_check_mce(mcelog.next);
+        next = ACCESS_ONCE(mcelog.next);
 
         do {
                 struct mce *m;
@@ -540,6 +540,27 @@ static void mce_report_event(struct pt_regs *regs)
         irq_work_queue(&__get_cpu_var(mce_irq_work));
 }
 
+/*
+ * Read ADDR and MISC registers.
+ */
+static void mce_read_aux(struct mce *m, int i)
+{
+        if (m->status & MCI_STATUS_MISCV)
+                m->misc = mce_rdmsrl(MSR_IA32_MCx_MISC(i));
+        if (m->status & MCI_STATUS_ADDRV) {
+                m->addr = mce_rdmsrl(MSR_IA32_MCx_ADDR(i));
+
+                /*
+                 * Mask the reported address by the reported granularity.
+                 */
+                if (mce_ser && (m->status & MCI_STATUS_MISCV)) {
+                        u8 shift = MCI_MISC_ADDR_LSB(m->misc);
+                        m->addr >>= shift;
+                        m->addr <<= shift;
+                }
+        }
+}
+
 DEFINE_PER_CPU(unsigned, mce_poll_count);
 
 /*
@@ -590,10 +611,7 @@ void machine_check_poll(enum mcp_flags flags, mce_banks_t *b)
                     (m.status & (mce_ser ? MCI_STATUS_S : MCI_STATUS_UC)))
                         continue;
 
-                if (m.status & MCI_STATUS_MISCV)
-                        m.misc = mce_rdmsrl(MSR_IA32_MCx_MISC(i));
-                if (m.status & MCI_STATUS_ADDRV)
-                        m.addr = mce_rdmsrl(MSR_IA32_MCx_ADDR(i));
+                mce_read_aux(&m, i);
 
                 if (!(flags & MCP_TIMESTAMP))
                         m.tsc = 0;
@@ -917,6 +935,49 @@ static void mce_clear_state(unsigned long *toclear)
 }
 
 /*
+ * Need to save faulting physical address associated with a process
+ * in the machine check handler some place where we can grab it back
+ * later in mce_notify_process()
+ */
+#define MCE_INFO_MAX    16
+
+struct mce_info {
+        atomic_t                inuse;
+        struct task_struct      *t;
+        __u64                   paddr;
+} mce_info[MCE_INFO_MAX];
+
+static void mce_save_info(__u64 addr)
+{
+        struct mce_info *mi;
+
+        for (mi = mce_info; mi < &mce_info[MCE_INFO_MAX]; mi++) {
+                if (atomic_cmpxchg(&mi->inuse, 0, 1) == 0) {
+                        mi->t = current;
+                        mi->paddr = addr;
+                        return;
+                }
+        }
+
+        mce_panic("Too many concurrent recoverable errors", NULL, NULL);
+}
+
+static struct mce_info *mce_find_info(void)
+{
+        struct mce_info *mi;
+
+        for (mi = mce_info; mi < &mce_info[MCE_INFO_MAX]; mi++)
+                if (atomic_read(&mi->inuse) && mi->t == current)
+                        return mi;
+        return NULL;
+}
+
+static void mce_clear_info(struct mce_info *mi)
+{
+        atomic_set(&mi->inuse, 0);
+}
+
+/*
  * The actual machine check handler. This only handles real
  * exceptions when something got corrupted coming in through int 18.
  *
@@ -969,7 +1030,9 @@ void do_machine_check(struct pt_regs *regs, long error_code)
         barrier();
 
         /*
-         * When no restart IP must always kill or panic.
+         * When no restart IP might need to kill or panic.
+         * Assume the worst for now, but if we find the
+         * severity is MCE_AR_SEVERITY we have other options.
          */
         if (!(m.mcgstatus & MCG_STATUS_RIPV))
                 kill_it = 1;
@@ -1023,16 +1086,7 @@ void do_machine_check(struct pt_regs *regs, long error_code)
                         continue;
                 }
 
-                /*
-                 * Kill on action required.
-                 */
-                if (severity == MCE_AR_SEVERITY)
-                        kill_it = 1;
-
-                if (m.status & MCI_STATUS_MISCV)
-                        m.misc = mce_rdmsrl(MSR_IA32_MCx_MISC(i));
-                if (m.status & MCI_STATUS_ADDRV)
-                        m.addr = mce_rdmsrl(MSR_IA32_MCx_ADDR(i));
+                mce_read_aux(&m, i);
 
                 /*
                  * Action optional error. Queue address for later processing.
@@ -1052,6 +1106,9 @@ void do_machine_check(struct pt_regs *regs, long error_code)
                 }
         }
 
+        /* mce_clear_state will clear *final, save locally for use later */
+        m = *final;
+
         if (!no_way_out)
                 mce_clear_state(toclear);
 
@@ -1063,27 +1120,22 @@ void do_machine_check(struct pt_regs *regs, long error_code)
                 no_way_out = worst >= MCE_PANIC_SEVERITY;
 
         /*
-         * If we have decided that we just CAN'T continue, and the user
-         * has not set tolerant to an insane level, give up and die.
-         *
-         * This is mainly used in the case when the system doesn't
-         * support MCE broadcasting or it has been disabled.
-         */
-        if (no_way_out && tolerant < 3)
-                mce_panic("Fatal machine check on current CPU", final, msg);
-
-        /*
-         * If the error seems to be unrecoverable, something should be
-         * done.  Try to kill as little as possible.  If we can kill just
-         * one task, do that.  If the user has set the tolerance very
-         * high, don't try to do anything at all.
+         * At insane "tolerant" levels we take no action. Otherwise
+         * we only die if we have no other choice. For less serious
+         * issues we try to recover, or limit damage to the current
+         * process.
          */
-
-        if (kill_it && tolerant < 3)
-                force_sig(SIGBUS, current);
-
-        /* notify userspace ASAP */
-        set_thread_flag(TIF_MCE_NOTIFY);
+        if (tolerant < 3) {
+                if (no_way_out)
+                        mce_panic("Fatal machine check on current CPU", &m, msg);
+                if (worst == MCE_AR_SEVERITY) {
+                        /* schedule action before return to userland */
+                        mce_save_info(m.addr);
+                        set_thread_flag(TIF_MCE_NOTIFY);
+                } else if (kill_it) {
+                        force_sig(SIGBUS, current);
+                }
+        }
 
         if (worst > 0)
                 mce_report_event(regs);
@@ -1094,34 +1146,57 @@ out:
 }
 EXPORT_SYMBOL_GPL(do_machine_check);
 
-/* dummy to break dependency. actual code is in mm/memory-failure.c */
-void __attribute__((weak)) memory_failure(unsigned long pfn, int vector)
+#ifndef CONFIG_MEMORY_FAILURE
+int memory_failure(unsigned long pfn, int vector, int flags)
 {
-        printk(KERN_ERR "Action optional memory failure at %lx ignored\n", pfn);
+        /* mce_severity() should not hand us an ACTION_REQUIRED error */
+        BUG_ON(flags & MF_ACTION_REQUIRED);
+        printk(KERN_ERR "Uncorrected memory error in page 0x%lx ignored\n"
+                "Rebuild kernel with CONFIG_MEMORY_FAILURE=y for smarter handling\n", pfn);
+
+        return 0;
 }
+#endif
 
 /*
- * Called after mce notification in process context. This code
- * is allowed to sleep. Call the high level VM handler to process
- * any corrupted pages.
- * Assume that the work queue code only calls this one at a time
- * per CPU.
- * Note we don't disable preemption, so this code might run on the wrong
- * CPU. In this case the event is picked up by the scheduled work queue.
- * This is merely a fast path to expedite processing in some common
- * cases.
+ * Called in process context that interrupted by MCE and marked with
+ * TIF_MCE_NOTIFY, just before returning to erroneous userland.
+ * This code is allowed to sleep.
+ * Attempt possible recovery such as calling the high level VM handler to
+ * process any corrupted pages, and kill/signal current process if required.
+ * Action required errors are handled here.
  */
 void mce_notify_process(void)
 {
         unsigned long pfn;
-        mce_notify_irq();
-        while (mce_ring_get(&pfn))
-                memory_failure(pfn, MCE_VECTOR);
+        struct mce_info *mi = mce_find_info();
+
+        if (!mi)
+                mce_panic("Lost physical address for unconsumed uncorrectable error", NULL, NULL);
+        pfn = mi->paddr >> PAGE_SHIFT;
+
+        clear_thread_flag(TIF_MCE_NOTIFY);
+
+        pr_err("Uncorrected hardware memory error in user-access at %llx",
+                 mi->paddr);
+        if (memory_failure(pfn, MCE_VECTOR, MF_ACTION_REQUIRED) < 0) {
+                pr_err("Memory error not recovered");
+                force_sig(SIGBUS, current);
+        }
+        mce_clear_info(mi);
 }
 
+/*
+ * Action optional processing happens here (picking up
+ * from the list of faulting pages that do_machine_check()
+ * placed into the "ring").
+ */
 static void mce_process_work(struct work_struct *dummy)
 {
-        mce_notify_process();
+        unsigned long pfn;
+
+        while (mce_ring_get(&pfn))
+                memory_failure(pfn, MCE_VECTOR, 0);
 }
 
 #ifdef CONFIG_X86_MCE_INTEL
@@ -1211,8 +1286,6 @@ int mce_notify_irq(void)
         /* Not more than two messages every minute */
         static DEFINE_RATELIMIT_STATE(ratelimit, 60*HZ, 2);
 
-        clear_thread_flag(TIF_MCE_NOTIFY);
-
         if (test_and_clear_bit(0, &mce_need_notify)) {
                 /* wake processes polling /dev/mcelog */
                 wake_up_interruptible(&mce_chrdev_wait);
@@ -1541,6 +1614,12 @@ static int __mce_read_apei(char __user **ubuf, size_t usize)
         /* Error or no more MCE record */
         if (rc <= 0) {
                 mce_apei_read_done = 1;
+                /*
+                 * When ERST is disabled, mce_chrdev_read() should return
+                 * "no record" instead of "no device."
+                 */
+                if (rc == -ENODEV)
+                        return 0;
                 return rc;
         }
         rc = -EFAULT;
@@ -1859,7 +1938,7 @@ static struct bus_type mce_subsys = {
         .dev_name       = "machinecheck",
 };
 
-struct device *mce_device[CONFIG_NR_CPUS];
+DEFINE_PER_CPU(struct device *, mce_device);
 
 __cpuinitdata
 void (*threshold_cpu_callback)(unsigned long action, unsigned int cpu);
@@ -2038,7 +2117,7 @@ static __cpuinit int mce_device_create(unsigned int cpu)
                         goto error2;
         }
         cpumask_set_cpu(cpu, mce_device_initialized);
-        mce_device[cpu] = dev;
+        per_cpu(mce_device, cpu) = dev;
 
         return 0;
 error2:
@@ -2055,7 +2134,7 @@ error:
 
 static __cpuinit void mce_device_remove(unsigned int cpu)
 {
-        struct device *dev = mce_device[cpu];
+        struct device *dev = per_cpu(mce_device, cpu);
         int i;
 
         if (!cpumask_test_cpu(cpu, mce_device_initialized))
@@ -2069,7 +2148,7 @@ static __cpuinit void mce_device_remove(unsigned int cpu)
 
         device_unregister(dev);
         cpumask_clear_cpu(cpu, mce_device_initialized);
-        mce_device[cpu] = NULL;
+        per_cpu(mce_device, cpu) = NULL;
 }
 
 /* Make sure there are no machine checks on offlined CPUs. */
diff --git a/arch/x86/kernel/cpu/mcheck/mce_amd.c b/arch/x86/kernel/cpu/mcheck/mce_amd.c
index e4eeaaf58a4..99b57179f91 100644
--- a/arch/x86/kernel/cpu/mcheck/mce_amd.c
+++ b/arch/x86/kernel/cpu/mcheck/mce_amd.c
@@ -523,7 +523,7 @@ static __cpuinit int threshold_create_bank(unsigned int cpu, unsigned int bank)
 {
         int i, err = 0;
         struct threshold_bank *b = NULL;
-        struct device *dev = mce_device[cpu];
+        struct device *dev = per_cpu(mce_device, cpu);
         char name[32];
 
         sprintf(name, "threshold_bank%i", bank);
@@ -587,7 +587,7 @@ static __cpuinit int threshold_create_bank(unsigned int cpu, unsigned int bank)
                 if (i == cpu)
                         continue;
 
-                dev = mce_device[i];
+                dev = per_cpu(mce_device, i);
                 if (dev)
                         err = sysfs_create_link(&dev->kobj,b->kobj, name);
                 if (err)
@@ -667,7 +667,8 @@ static void threshold_remove_bank(unsigned int cpu, int bank)
 #ifdef CONFIG_SMP
         /* sibling symlink */
         if (shared_bank[bank] && b->blocks->cpu != cpu) {
-                sysfs_remove_link(&mce_device[cpu]->kobj, name);
+                dev = per_cpu(mce_device, cpu);
+                sysfs_remove_link(&dev->kobj, name);
                 per_cpu(threshold_banks, cpu)[bank] = NULL;
 
                 return;
@@ -679,7 +680,7 @@ static void threshold_remove_bank(unsigned int cpu, int bank)
                 if (i == cpu)
                         continue;
 
-                dev = mce_device[i];
+                dev = per_cpu(mce_device, i);
                 if (dev)
                         sysfs_remove_link(&dev->kobj, name);
                 per_cpu(threshold_banks, i)[bank] = NULL;
diff --git a/arch/x86/kernel/cpu/perf_event.c b/arch/x86/kernel/cpu/perf_event.c
index 0a18d16cb58..fa2900c0e39 100644
--- a/arch/x86/kernel/cpu/perf_event.c
+++ b/arch/x86/kernel/cpu/perf_event.c
@@ -643,14 +643,14 @@ static bool __perf_sched_find_counter(struct perf_sched *sched)
         /* Prefer fixed purpose counters */
         if (x86_pmu.num_counters_fixed) {
                 idx = X86_PMC_IDX_FIXED;
-                for_each_set_bit_cont(idx, c->idxmsk, X86_PMC_IDX_MAX) {
+                for_each_set_bit_from(idx, c->idxmsk, X86_PMC_IDX_MAX) {
                         if (!__test_and_set_bit(idx, sched->state.used))
                                 goto done;
                 }
         }
         /* Grab the first unused counter starting with idx */
         idx = sched->state.counter;
-        for_each_set_bit_cont(idx, c->idxmsk, X86_PMC_IDX_FIXED) {
+        for_each_set_bit_from(idx, c->idxmsk, X86_PMC_IDX_FIXED) {
                 if (!__test_and_set_bit(idx, sched->state.used))
                         goto done;
         }
diff --git a/arch/x86/kernel/dumpstack_32.c b/arch/x86/kernel/dumpstack_32.c
index c99f9ed013d..88ec9129271 100644
--- a/arch/x86/kernel/dumpstack_32.c
+++ b/arch/x86/kernel/dumpstack_32.c
@@ -87,7 +87,7 @@ void show_registers(struct pt_regs *regs)
         int i;
 
         print_modules();
-        __show_regs(regs, 0);
+        __show_regs(regs, !user_mode_vm(regs));
 
         printk(KERN_EMERG "Process %.*s (pid: %d, ti=%p task=%p task.ti=%p)\n",
                 TASK_COMM_LEN, current->comm, task_pid_nr(current),
diff --git a/arch/x86/kernel/entry_32.S b/arch/x86/kernel/entry_32.S
index 79d97e68f04..7b784f4ef1e 100644
--- a/arch/x86/kernel/entry_32.S
+++ b/arch/x86/kernel/entry_32.S
@@ -98,12 +98,6 @@
 #endif
 .endm
 
-#ifdef CONFIG_VM86
-#define resume_userspace_sig    check_userspace
-#else
-#define resume_userspace_sig    resume_userspace
-#endif
-
 /*
  * User gs save/restore
  *
@@ -327,10 +321,19 @@ ret_from_exception:
         preempt_stop(CLBR_ANY)
 ret_from_intr:
         GET_THREAD_INFO(%ebp)
-check_userspace:
+resume_userspace_sig:
+#ifdef CONFIG_VM86
         movl PT_EFLAGS(%esp), %eax      # mix EFLAGS and CS
         movb PT_CS(%esp), %al
         andl $(X86_EFLAGS_VM | SEGMENT_RPL_MASK), %eax
+#else
+        /*
+         * We can be coming here from a syscall done in the kernel space,
+         * e.g. a failed kernel_execve().
+         */
+        movl PT_CS(%esp), %eax
+        andl $SEGMENT_RPL_MASK, %eax
+#endif
         cmpl $USER_RPL, %eax
         jb resume_kernel                # not returning to v8086 or userspace
 
diff --git a/arch/x86/kernel/entry_64.S b/arch/x86/kernel/entry_64.S
index 1333d985177..734ebd1d3ca 100644
--- a/arch/x86/kernel/entry_64.S
+++ b/arch/x86/kernel/entry_64.S
@@ -320,7 +320,7 @@ ENDPROC(native_usergs_sysret64)
         movq %rsp, %rsi
 
         leaq -RBP(%rsp),%rdi    /* arg1 for handler */
-        testl $3, CS(%rdi)
+        testl $3, CS-RBP(%rsi)
         je 1f
         SWAPGS
         /*
@@ -330,11 +330,10 @@ ENDPROC(native_usergs_sysret64)
          * moving irq_enter into assembly, which would be too much work)
          */
 1:      incl PER_CPU_VAR(irq_count)
-        jne 2f
-        mov PER_CPU_VAR(irq_stack_ptr),%rsp
+        cmovzq PER_CPU_VAR(irq_stack_ptr),%rsp
         CFI_DEF_CFA_REGISTER    rsi
 
-2:      /* Store previous stack value */
+        /* Store previous stack value */
         pushq %rsi
         CFI_ESCAPE      0x0f /* DW_CFA_def_cfa_expression */, 6, \
                         0x77 /* DW_OP_breg7 */, 0, \
@@ -813,7 +812,7 @@ ret_from_intr:
 
         /* Restore saved previous stack */
         popq %rsi
-        CFI_DEF_CFA_REGISTER    rsi
+        CFI_DEF_CFA rsi,SS+8-RBP        /* reg/off reset after def_cfa_expr */
         leaq ARGOFFSET-RBP(%rsi), %rsp
         CFI_DEF_CFA_REGISTER    rsp
         CFI_ADJUST_CFA_OFFSET   RBP-ARGOFFSET
@@ -1530,6 +1529,7 @@ ENTRY(nmi)
 
         /* Use %rdx as out temp variable throughout */
         pushq_cfi %rdx
+        CFI_REL_OFFSET rdx, 0
 
         /*
          * If %cs was not the kernel segment, then the NMI triggered in user
@@ -1554,6 +1554,7 @@ ENTRY(nmi)
          */
         lea 6*8(%rsp), %rdx
         test_in_nmi rdx, 4*8(%rsp), nested_nmi, first_nmi
+        CFI_REMEMBER_STATE
 
 nested_nmi:
         /*
@@ -1585,10 +1586,12 @@ nested_nmi:
 
 nested_nmi_out:
         popq_cfi %rdx
+        CFI_RESTORE rdx
 
         /* No need to check faults here */
         INTERRUPT_RETURN
 
+        CFI_RESTORE_STATE
 first_nmi:
         /*
          * Because nested NMIs will use the pushed location that we
@@ -1620,10 +1623,15 @@ first_nmi:
          * | pt_regs                 |
          * +-------------------------+
          *
-         * The saved RIP is used to fix up the copied RIP that a nested
-         * NMI may zero out. The original stack frame and the temp storage
+         * The saved stack frame is used to fix up the copied stack frame
+         * that a nested NMI may change to make the interrupted NMI iret jump
+         * to the repeat_nmi. The original stack frame and the temp storage
          * is also used by nested NMIs and can not be trusted on exit.
          */
+        /* Do not pop rdx, nested NMIs will corrupt that part of the stack */
+        movq (%rsp), %rdx
+        CFI_RESTORE rdx
+
         /* Set the NMI executing variable on the stack. */
         pushq_cfi $1
 
@@ -1631,22 +1639,39 @@ first_nmi:
         .rept 5
         pushq_cfi 6*8(%rsp)
         .endr
+        CFI_DEF_CFA_OFFSET SS+8-RIP
+
+        /* Everything up to here is safe from nested NMIs */
+
+        /*
+         * If there was a nested NMI, the first NMI's iret will return
+         * here. But NMIs are still enabled and we can take another
+         * nested NMI. The nested NMI checks the interrupted RIP to see
+         * if it is between repeat_nmi and end_repeat_nmi, and if so
+         * it will just return, as we are about to repeat an NMI anyway.
+         * This makes it safe to copy to the stack frame that a nested
+         * NMI will update.
+         */
+repeat_nmi:
+        /*
+         * Update the stack variable to say we are still in NMI (the update
+         * is benign for the non-repeat case, where 1 was pushed just above
+         * to this very stack slot).
+         */
+        movq $1, 5*8(%rsp)
 
         /* Make another copy, this one may be modified by nested NMIs */
         .rept 5
         pushq_cfi 4*8(%rsp)
         .endr
-
-        /* Do not pop rdx, nested NMIs will corrupt it */
-        movq 11*8(%rsp), %rdx
+        CFI_DEF_CFA_OFFSET SS+8-RIP
+end_repeat_nmi:
 
         /*
          * Everything below this point can be preempted by a nested
-         * NMI if the first NMI took an exception. Repeated NMIs
-         * caused by an exception and nested NMI will start here, and
-         * can still be preempted by another NMI.
+         * NMI if the first NMI took an exception and reset our iret stack
+         * so that we repeat another NMI.
          */
-restart_nmi:
         pushq_cfi $-1           /* ORIG_RAX: no syscall to restart */
         subq $ORIG_RAX-R15, %rsp
         CFI_ADJUST_CFA_OFFSET ORIG_RAX-R15
@@ -1675,26 +1700,6 @@ nmi_restore:
         CFI_ENDPROC
 END(nmi)
 
-        /*
-         * If an NMI hit an iret because of an exception or breakpoint,
-         * it can lose its NMI context, and a nested NMI may come in.
-         * In that case, the nested NMI will change the preempted NMI's
-         * stack to jump to here when it does the final iret.
-         */
-repeat_nmi:
-        INTR_FRAME
-        /* Update the stack variable to say we are still in NMI */
-        movq $1, 5*8(%rsp)
-
-        /* copy the saved stack back to copy stack */
-        .rept 5
-        pushq_cfi 4*8(%rsp)
-        .endr
-
-        jmp restart_nmi
-        CFI_ENDPROC
-end_repeat_nmi:
-
 ENTRY(ignore_sysret)
         CFI_STARTPROC
         mov $-ENOSYS,%eax
diff --git a/arch/x86/kernel/i387.c b/arch/x86/kernel/i387.c
index 739d8598f78..7734bcbb5a3 100644
--- a/arch/x86/kernel/i387.c
+++ b/arch/x86/kernel/i387.c
@@ -16,6 +16,7 @@
 #include <asm/uaccess.h>
 #include <asm/ptrace.h>
 #include <asm/i387.h>
+#include <asm/fpu-internal.h>
 #include <asm/user.h>
 
 #ifdef CONFIG_X86_64
@@ -32,6 +33,86 @@
 # define user32_fxsr_struct     user_fxsr_struct
 #endif
 
+/*
+ * Were we in an interrupt that interrupted kernel mode?
+ *
+ * We can do a kernel_fpu_begin/end() pair *ONLY* if that
+ * pair does nothing at all: the thread must not have fpu (so
+ * that we don't try to save the FPU state), and TS must
+ * be set (so that the clts/stts pair does nothing that is
+ * visible in the interrupted kernel thread).
+ */
+static inline bool interrupted_kernel_fpu_idle(void)
+{
+        return !__thread_has_fpu(current) &&
+                (read_cr0() & X86_CR0_TS);
+}
+
+/*
+ * Were we in user mode (or vm86 mode) when we were
+ * interrupted?
+ *
+ * Doing kernel_fpu_begin/end() is ok if we are running
+ * in an interrupt context from user mode - we'll just
+ * save the FPU state as required.
+ */
+static inline bool interrupted_user_mode(void)
+{
+        struct pt_regs *regs = get_irq_regs();
+        return regs && user_mode_vm(regs);
+}
+
+/*
+ * Can we use the FPU in kernel mode with the
+ * whole "kernel_fpu_begin/end()" sequence?
+ *
+ * It's always ok in process context (ie "not interrupt")
+ * but it is sometimes ok even from an irq.
+ */
+bool irq_fpu_usable(void)
+{
+        return !in_interrupt() ||
+                interrupted_user_mode() ||
+                interrupted_kernel_fpu_idle();
+}
+EXPORT_SYMBOL(irq_fpu_usable);
+
+void kernel_fpu_begin(void)
+{
+        struct task_struct *me = current;
+
+        WARN_ON_ONCE(!irq_fpu_usable());
+        preempt_disable();
+        if (__thread_has_fpu(me)) {
+                __save_init_fpu(me);
+                __thread_clear_has_fpu(me);
+                /* We do 'stts()' in kernel_fpu_end() */
+        } else {
+                percpu_write(fpu_owner_task, NULL);
+                clts();
+        }
+}
+EXPORT_SYMBOL(kernel_fpu_begin);
+
+void kernel_fpu_end(void)
+{
+        stts();
+        preempt_enable();
+}
+EXPORT_SYMBOL(kernel_fpu_end);
+
+void unlazy_fpu(struct task_struct *tsk)
+{
+        preempt_disable();
+        if (__thread_has_fpu(tsk)) {
+                __save_init_fpu(tsk);
+                __thread_fpu_end(tsk);
+        } else
+                tsk->fpu_counter = 0;
+        preempt_enable();
+}
+EXPORT_SYMBOL(unlazy_fpu);
+
 #ifdef CONFIG_MATH_EMULATION
 # define HAVE_HWFP              (boot_cpu_data.hard_math)
 #else
@@ -44,7 +125,7 @@ EXPORT_SYMBOL_GPL(xstate_size);
 unsigned int sig_xstate_ia32_size = sizeof(struct _fpstate_ia32);
 static struct i387_fxsave_struct fx_scratch __cpuinitdata;
 
-void __cpuinit mxcsr_feature_mask_init(void)
+static void __cpuinit mxcsr_feature_mask_init(void)
 {
         unsigned long mask = 0;
 
diff --git a/arch/x86/kernel/irqinit.c b/arch/x86/kernel/irqinit.c
index 313fb5cddbc..43e2b1cff0a 100644
--- a/arch/x86/kernel/irqinit.c
+++ b/arch/x86/kernel/irqinit.c
@@ -306,10 +306,10 @@ void __init native_init_IRQ(void)
          * us. (some of these will be overridden and become
          * 'special' SMP interrupts)
          */
-        for (i = FIRST_EXTERNAL_VECTOR; i < NR_VECTORS; i++) {
+        i = FIRST_EXTERNAL_VECTOR;
+        for_each_clear_bit_from(i, used_vectors, NR_VECTORS) {
                 /* IA32_SYSCALL_VECTOR could be used in trap_init already. */
-                if (!test_bit(i, used_vectors))
-                        set_intr_gate(i, interrupt[i-FIRST_EXTERNAL_VECTOR]);
+                set_intr_gate(i, interrupt[i - FIRST_EXTERNAL_VECTOR]);
         }
 
         if (!acpi_ioapic && !of_ioapic)
diff --git a/arch/x86/kernel/kgdb.c b/arch/x86/kernel/kgdb.c
index faba5771aca..fdc37b3d0ce 100644
--- a/arch/x86/kernel/kgdb.c
+++ b/arch/x86/kernel/kgdb.c
@@ -67,8 +67,6 @@ struct dbg_reg_def_t dbg_reg_def[DBG_MAX_REG_NUM] =
         { "ss", 4, offsetof(struct pt_regs, ss) },
         { "ds", 4, offsetof(struct pt_regs, ds) },
         { "es", 4, offsetof(struct pt_regs, es) },
-        { "fs", 4, -1 },
-        { "gs", 4, -1 },
 #else
         { "ax", 8, offsetof(struct pt_regs, ax) },
         { "bx", 8, offsetof(struct pt_regs, bx) },
@@ -90,7 +88,11 @@ struct dbg_reg_def_t dbg_reg_def[DBG_MAX_REG_NUM] =
         { "flags", 4, offsetof(struct pt_regs, flags) },
         { "cs", 4, offsetof(struct pt_regs, cs) },
         { "ss", 4, offsetof(struct pt_regs, ss) },
+        { "ds", 4, -1 },
+        { "es", 4, -1 },
 #endif
+        { "fs", 4, -1 },
+        { "gs", 4, -1 },
 };
 
 int dbg_set_reg(int regno, void *mem, struct pt_regs *regs)
diff --git a/arch/x86/kernel/nmi_selftest.c b/arch/x86/kernel/nmi_selftest.c
index 0d01a8ea4e1..2c39dcd510f 100644
--- a/arch/x86/kernel/nmi_selftest.c
+++ b/arch/x86/kernel/nmi_selftest.c
@@ -12,6 +12,7 @@
 #include <linux/smp.h>
 #include <linux/cpumask.h>
 #include <linux/delay.h>
+#include <linux/init.h>
 
 #include <asm/apic.h>
 #include <asm/nmi.h>
@@ -20,35 +21,35 @@
 #define FAILURE         1
 #define TIMEOUT         2
 
-static int nmi_fail;
+static int __initdata nmi_fail;
 
 /* check to see if NMI IPIs work on this machine */
-static DECLARE_BITMAP(nmi_ipi_mask, NR_CPUS) __read_mostly;
+static DECLARE_BITMAP(nmi_ipi_mask, NR_CPUS) __initdata;
 
-static int testcase_total;
-static int testcase_successes;
-static int expected_testcase_failures;
-static int unexpected_testcase_failures;
-static int unexpected_testcase_unknowns;
+static int __initdata testcase_total;
+static int __initdata testcase_successes;
+static int __initdata expected_testcase_failures;
+static int __initdata unexpected_testcase_failures;
+static int __initdata unexpected_testcase_unknowns;
 
-static int nmi_unk_cb(unsigned int val, struct pt_regs *regs)
+static int __init nmi_unk_cb(unsigned int val, struct pt_regs *regs)
 {
         unexpected_testcase_unknowns++;
         return NMI_HANDLED;
 }
 
-static void init_nmi_testsuite(void)
+static void __init init_nmi_testsuite(void)
 {
         /* trap all the unknown NMIs we may generate */
         register_nmi_handler(NMI_UNKNOWN, nmi_unk_cb, 0, "nmi_selftest_unk");
 }
 
-static void cleanup_nmi_testsuite(void)
+static void __init cleanup_nmi_testsuite(void)
 {
         unregister_nmi_handler(NMI_UNKNOWN, "nmi_selftest_unk");
 }
 
-static int test_nmi_ipi_callback(unsigned int val, struct pt_regs *regs)
+static int __init test_nmi_ipi_callback(unsigned int val, struct pt_regs *regs)
 {
         int cpu = raw_smp_processor_id();
 
@@ -58,7 +59,7 @@ static int test_nmi_ipi_callback(unsigned int val, struct pt_regs *regs)
         return NMI_DONE;
 }
 
-static void test_nmi_ipi(struct cpumask *mask)
+static void __init test_nmi_ipi(struct cpumask *mask)
 {
         unsigned long timeout;
 
@@ -86,7 +87,7 @@ static void test_nmi_ipi(struct cpumask *mask)
         return;
 }
 
-static void remote_ipi(void)
+static void __init remote_ipi(void)
 {
         cpumask_copy(to_cpumask(nmi_ipi_mask), cpu_online_mask);
         cpumask_clear_cpu(smp_processor_id(), to_cpumask(nmi_ipi_mask));
@@ -94,19 +95,19 @@ static void remote_ipi(void)
                 test_nmi_ipi(to_cpumask(nmi_ipi_mask));
 }
 
-static void local_ipi(void)
+static void __init local_ipi(void)
 {
         cpumask_clear(to_cpumask(nmi_ipi_mask));
         cpumask_set_cpu(smp_processor_id(), to_cpumask(nmi_ipi_mask));
         test_nmi_ipi(to_cpumask(nmi_ipi_mask));
 }
 
-static void reset_nmi(void)
+static void __init reset_nmi(void)
 {
         nmi_fail = 0;
 }
 
-static void dotest(void (*testcase_fn)(void), int expected)
+static void __init dotest(void (*testcase_fn)(void), int expected)
 {
         testcase_fn();
         /*
@@ -131,12 +132,12 @@ static void dotest(void (*testcase_fn)(void), int expected)
         reset_nmi();
 }
 
-static inline void print_testname(const char *testname)
+static inline void __init print_testname(const char *testname)
 {
         printk("%12s:", testname);
 }
 
-void nmi_selftest(void)
+void __init nmi_selftest(void)
 {
         init_nmi_testsuite();
 
diff --git a/arch/x86/kernel/paravirt.c b/arch/x86/kernel/paravirt.c
index ada2f99388d..9c57c02e54f 100644
--- a/arch/x86/kernel/paravirt.c
+++ b/arch/x86/kernel/paravirt.c
@@ -26,6 +26,7 @@
 
 #include <asm/bug.h>
 #include <asm/paravirt.h>
+#include <asm/debugreg.h>
 #include <asm/desc.h>
 #include <asm/setup.h>
 #include <asm/pgtable.h>
diff --git a/arch/x86/kernel/pci-dma.c b/arch/x86/kernel/pci-dma.c
index 1c4d769e21e..28e5e06fcba 100644
--- a/arch/x86/kernel/pci-dma.c
+++ b/arch/x86/kernel/pci-dma.c
@@ -262,10 +262,11 @@ rootfs_initcall(pci_iommu_init);
 
 static __devinit void via_no_dac(struct pci_dev *dev)
 {
-        if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI && forbid_dac == 0) {
+        if (forbid_dac == 0) {
                 dev_info(&dev->dev, "disabling DAC on VIA PCI bridge\n");
                 forbid_dac = 1;
         }
 }
-DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_ANY_ID, via_no_dac);
+DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_VIA, PCI_ANY_ID,
+                                PCI_CLASS_BRIDGE_PCI, 8, via_no_dac);
 #endif
diff --git a/arch/x86/kernel/probe_roms.c b/arch/x86/kernel/probe_roms.c
index 34e06e84ce3..0bc72e2069e 100644
--- a/arch/x86/kernel/probe_roms.c
+++ b/arch/x86/kernel/probe_roms.c
@@ -12,6 +12,7 @@
 #include <linux/pci.h>
 #include <linux/export.h>
 
+#include <asm/probe_roms.h>
 #include <asm/pci-direct.h>
 #include <asm/e820.h>
 #include <asm/mmzone.h>
diff --git a/arch/x86/kernel/process.c b/arch/x86/kernel/process.c
index 44eefde9210..14baf78d5a1 100644
--- a/arch/x86/kernel/process.c
+++ b/arch/x86/kernel/process.c
@@ -21,6 +21,7 @@
 #include <asm/idle.h>
 #include <asm/uaccess.h>
 #include <asm/i387.h>
+#include <asm/fpu-internal.h>
 #include <asm/debugreg.h>
 
 struct kmem_cache *task_xstate_cachep;
diff --git a/arch/x86/kernel/process_32.c b/arch/x86/kernel/process_32.c
index 49888fefe79..9d7d4842bfa 100644
--- a/arch/x86/kernel/process_32.c
+++ b/arch/x86/kernel/process_32.c
@@ -45,6 +45,7 @@
 #include <asm/ldt.h>
 #include <asm/processor.h>
 #include <asm/i387.h>
+#include <asm/fpu-internal.h>
 #include <asm/desc.h>
 #ifdef CONFIG_MATH_EMULATION
 #include <asm/math_emu.h>
diff --git a/arch/x86/kernel/process_64.c b/arch/x86/kernel/process_64.c
index e34257c70c2..292da13fc5a 100644
--- a/arch/x86/kernel/process_64.c
+++ b/arch/x86/kernel/process_64.c
@@ -43,6 +43,7 @@
 #include <asm/system.h>
 #include <asm/processor.h>
 #include <asm/i387.h>
+#include <asm/fpu-internal.h>
 #include <asm/mmu_context.h>
 #include <asm/prctl.h>
 #include <asm/desc.h>
@@ -340,6 +341,7 @@ start_thread_common(struct pt_regs *regs, unsigned long new_ip,
         loadsegment(es, _ds);
         loadsegment(ds, _ds);
         load_gs_index(0);
+        current->thread.usersp  = new_sp;
         regs->ip                = new_ip;
         regs->sp                = new_sp;
         percpu_write(old_rsp, new_sp);
diff --git a/arch/x86/kernel/ptrace.c b/arch/x86/kernel/ptrace.c
index 50267386b76..78f05e438be 100644
--- a/arch/x86/kernel/ptrace.c
+++ b/arch/x86/kernel/ptrace.c
@@ -27,6 +27,7 @@
 #include <asm/system.h>
 #include <asm/processor.h>
 #include <asm/i387.h>
+#include <asm/fpu-internal.h>
 #include <asm/debugreg.h>
 #include <asm/ldt.h>
 #include <asm/desc.h>
diff --git a/arch/x86/kernel/setup.c b/arch/x86/kernel/setup.c
index d7d5099fe87..88638883176 100644
--- a/arch/x86/kernel/setup.c
+++ b/arch/x86/kernel/setup.c
@@ -749,10 +749,16 @@ void __init setup_arch(char **cmdline_p)
 #endif
 #ifdef CONFIG_EFI
         if (!strncmp((char *)&boot_params.efi_info.efi_loader_signature,
-                     EFI_LOADER_SIGNATURE, 4)) {
+                     "EL32", 4)) {
                 efi_enabled = 1;
-                efi_memblock_x86_reserve_range();
+                efi_64bit = false;
+        } else if (!strncmp((char *)&boot_params.efi_info.efi_loader_signature,
+                     "EL64", 4)) {
+                efi_enabled = 1;
+                efi_64bit = true;
         }
+        if (efi_enabled && efi_memblock_x86_reserve_range())
+                efi_enabled = 0;
 #endif
 
         x86_init.oem.arch_setup();
diff --git a/arch/x86/kernel/signal.c b/arch/x86/kernel/signal.c
index 46a01bdc27e..25edcfc9ba5 100644
--- a/arch/x86/kernel/signal.c
+++ b/arch/x86/kernel/signal.c
@@ -24,6 +24,7 @@
 #include <asm/processor.h>
 #include <asm/ucontext.h>
 #include <asm/i387.h>
+#include <asm/fpu-internal.h>
 #include <asm/vdso.h>
 #include <asm/mce.h>
 
diff --git a/arch/x86/kernel/smpboot.c b/arch/x86/kernel/smpboot.c
index 58f78165d30..e578a79a309 100644
--- a/arch/x86/kernel/smpboot.c
+++ b/arch/x86/kernel/smpboot.c
@@ -727,8 +727,6 @@ do_rest:
          * the targeted processor.
          */
 
-        printk(KERN_DEBUG "smpboot cpu %d: start_ip = %lx\n", cpu, start_ip);
-
         atomic_set(&init_deasserted, 0);
 
         if (get_uv_system_type() != UV_NON_UNIQUE_APIC) {
@@ -778,9 +776,10 @@ do_rest:
                         schedule();
                 }
 
-                if (cpumask_test_cpu(cpu, cpu_callin_mask))
+                if (cpumask_test_cpu(cpu, cpu_callin_mask)) {
+                        print_cpu_msr(&cpu_data(cpu));
                         pr_debug("CPU%d: has booted.\n", cpu);
-                else {
+                } else {
                         boot_error = 1;
                         if (*(volatile u32 *)TRAMPOLINE_SYM(trampoline_status)
                             == 0xA5A5A5A5)
@@ -834,7 +833,7 @@ int __cpuinit native_cpu_up(unsigned int cpu)
 
         if (apicid == BAD_APICID || apicid == boot_cpu_physical_apicid ||
             !physid_isset(apicid, phys_cpu_present_map) ||
-            (!x2apic_mode && apicid >= 255)) {
+            !apic->apic_id_valid(apicid)) {
                 printk(KERN_ERR "%s: bad cpu %d\n", __func__, cpu);
                 return -EINVAL;
         }
diff --git a/arch/x86/kernel/sys_x86_64.c b/arch/x86/kernel/sys_x86_64.c
index 051489082d5..ef59642ff1b 100644
--- a/arch/x86/kernel/sys_x86_64.c
+++ b/arch/x86/kernel/sys_x86_64.c
@@ -195,7 +195,7 @@ arch_get_unmapped_area_topdown(struct file *filp, const unsigned long addr0,
 {
         struct vm_area_struct *vma;
         struct mm_struct *mm = current->mm;
-        unsigned long addr = addr0;
+        unsigned long addr = addr0, start_addr;
 
         /* requested length too big for entire address space */
         if (len > TASK_SIZE)
@@ -223,25 +223,14 @@ arch_get_unmapped_area_topdown(struct file *filp, const unsigned long addr0,
                 mm->free_area_cache = mm->mmap_base;
         }
 
+try_again:
         /* either no address requested or can't fit in requested address hole */
-        addr = mm->free_area_cache;
-
-        /* make sure it can fit in the remaining address space */
-        if (addr > len) {
-                unsigned long tmp_addr = align_addr(addr - len, filp,
-                                                    ALIGN_TOPDOWN);
-
-                vma = find_vma(mm, tmp_addr);
-                if (!vma || tmp_addr + len <= vma->vm_start)
-                        /* remember the address as a hint for next time */
-                        return mm->free_area_cache = tmp_addr;
-        }
-
-        if (mm->mmap_base < len)
-                goto bottomup;
+        start_addr = addr = mm->free_area_cache;
 
-        addr = mm->mmap_base-len;
+        if (addr < len)
+                goto fail;
 
+        addr -= len;
         do {
                 addr = align_addr(addr, filp, ALIGN_TOPDOWN);
 
@@ -263,6 +252,17 @@ arch_get_unmapped_area_topdown(struct file *filp, const unsigned long addr0,
                 addr = vma->vm_start-len;
         } while (len < vma->vm_start);
 
+fail:
+        /*
+         * if hint left us with no space for the requested
+         * mapping then try again:
+         */
+        if (start_addr != mm->mmap_base) {
+                mm->free_area_cache = mm->mmap_base;
+                mm->cached_hole_size = 0;
+                goto try_again;
+        }
+
 bottomup:
         /*
          * A failed mmap() very likely causes application failure,
diff --git a/arch/x86/kernel/traps.c b/arch/x86/kernel/traps.c
index 4bbe04d9674..ec61d4c1b93 100644
--- a/arch/x86/kernel/traps.c
+++ b/arch/x86/kernel/traps.c
@@ -54,6 +54,7 @@
 #include <asm/traps.h>
 #include <asm/desc.h>
 #include <asm/i387.h>
+#include <asm/fpu-internal.h>
 #include <asm/mce.h>
 
 #include <asm/mach_traps.h>
diff --git a/arch/x86/kernel/vm86_32.c b/arch/x86/kernel/vm86_32.c
index b466cab5ba1..328cb37bb82 100644
--- a/arch/x86/kernel/vm86_32.c
+++ b/arch/x86/kernel/vm86_32.c
@@ -172,6 +172,7 @@ static void mark_screen_rdonly(struct mm_struct *mm)
         spinlock_t *ptl;
         int i;
 
+        down_write(&mm->mmap_sem);
         pgd = pgd_offset(mm, 0xA0000);
         if (pgd_none_or_clear_bad(pgd))
                 goto out;
@@ -190,6 +191,7 @@ static void mark_screen_rdonly(struct mm_struct *mm)
         }
         pte_unmap_unlock(pte, ptl);
 out:
+        up_write(&mm->mmap_sem);
         flush_tlb();
 }
 
diff --git a/arch/x86/kernel/xsave.c b/arch/x86/kernel/xsave.c
index 71109111411..e62728e30b0 100644
--- a/arch/x86/kernel/xsave.c
+++ b/arch/x86/kernel/xsave.c
@@ -6,6 +6,7 @@
 #include <linux/bootmem.h>
 #include <linux/compat.h>
 #include <asm/i387.h>
+#include <asm/fpu-internal.h>
 #ifdef CONFIG_IA32_EMULATION
 #include <asm/sigcontext32.h>
 #endif
diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c
index 3b4c8d8ad90..246490f643b 100644
--- a/arch/x86/kvm/vmx.c
+++ b/arch/x86/kvm/vmx.c
@@ -1457,7 +1457,7 @@ static void __vmx_load_host_state(struct vcpu_vmx *vmx)
 #ifdef CONFIG_X86_64
         wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
 #endif
-        if (__thread_has_fpu(current))
+        if (user_has_fpu())
                 clts();
         load_gdt(&__get_cpu_var(host_gdt));
 }
diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c
index bb4fd2636bc..54696b5f844 100644
--- a/arch/x86/kvm/x86.c
+++ b/arch/x86/kvm/x86.c
@@ -57,6 +57,7 @@
 #include <asm/mtrr.h>
 #include <asm/mce.h>
 #include <asm/i387.h>
+#include <asm/fpu-internal.h> /* Ugh! */
 #include <asm/xcr.h>
 #include <asm/pvclock.h>
 #include <asm/div64.h>
diff --git a/arch/x86/lib/atomic64_32.c b/arch/x86/lib/atomic64_32.c
index 042f6826bf5..a0b4a350daa 100644
--- a/arch/x86/lib/atomic64_32.c
+++ b/arch/x86/lib/atomic64_32.c
@@ -1,59 +1,4 @@
-#include <linux/compiler.h>
-#include <linux/module.h>
-#include <linux/types.h>
+#define ATOMIC64_EXPORT EXPORT_SYMBOL
 
-#include <asm/processor.h>
-#include <asm/cmpxchg.h>
+#include <linux/export.h>
 #include <linux/atomic.h>
-
-long long atomic64_read_cx8(long long, const atomic64_t *v);
-EXPORT_SYMBOL(atomic64_read_cx8);
-long long atomic64_set_cx8(long long, const atomic64_t *v);
-EXPORT_SYMBOL(atomic64_set_cx8);
-long long atomic64_xchg_cx8(long long, unsigned high);
-EXPORT_SYMBOL(atomic64_xchg_cx8);
-long long atomic64_add_return_cx8(long long a, atomic64_t *v);
-EXPORT_SYMBOL(atomic64_add_return_cx8);
-long long atomic64_sub_return_cx8(long long a, atomic64_t *v);
-EXPORT_SYMBOL(atomic64_sub_return_cx8);
-long long atomic64_inc_return_cx8(long long a, atomic64_t *v);
-EXPORT_SYMBOL(atomic64_inc_return_cx8);
-long long atomic64_dec_return_cx8(long long a, atomic64_t *v);
-EXPORT_SYMBOL(atomic64_dec_return_cx8);
-long long atomic64_dec_if_positive_cx8(atomic64_t *v);
-EXPORT_SYMBOL(atomic64_dec_if_positive_cx8);
-int atomic64_inc_not_zero_cx8(atomic64_t *v);
-EXPORT_SYMBOL(atomic64_inc_not_zero_cx8);
-int atomic64_add_unless_cx8(atomic64_t *v, long long a, long long u);
-EXPORT_SYMBOL(atomic64_add_unless_cx8);
-
-#ifndef CONFIG_X86_CMPXCHG64
-long long atomic64_read_386(long long, const atomic64_t *v);
-EXPORT_SYMBOL(atomic64_read_386);
-long long atomic64_set_386(long long, const atomic64_t *v);
-EXPORT_SYMBOL(atomic64_set_386);
-long long atomic64_xchg_386(long long, unsigned high);
-EXPORT_SYMBOL(atomic64_xchg_386);
-long long atomic64_add_return_386(long long a, atomic64_t *v);
-EXPORT_SYMBOL(atomic64_add_return_386);
-long long atomic64_sub_return_386(long long a, atomic64_t *v);
-EXPORT_SYMBOL(atomic64_sub_return_386);
-long long atomic64_inc_return_386(long long a, atomic64_t *v);
-EXPORT_SYMBOL(atomic64_inc_return_386);
-long long atomic64_dec_return_386(long long a, atomic64_t *v);
-EXPORT_SYMBOL(atomic64_dec_return_386);
-long long atomic64_add_386(long long a, atomic64_t *v);
-EXPORT_SYMBOL(atomic64_add_386);
-long long atomic64_sub_386(long long a, atomic64_t *v);
-EXPORT_SYMBOL(atomic64_sub_386);
-long long atomic64_inc_386(long long a, atomic64_t *v);
-EXPORT_SYMBOL(atomic64_inc_386);
-long long atomic64_dec_386(long long a, atomic64_t *v);
-EXPORT_SYMBOL(atomic64_dec_386);
-long long atomic64_dec_if_positive_386(atomic64_t *v);
-EXPORT_SYMBOL(atomic64_dec_if_positive_386);
-int atomic64_inc_not_zero_386(atomic64_t *v);
-EXPORT_SYMBOL(atomic64_inc_not_zero_386);
-int atomic64_add_unless_386(atomic64_t *v, long long a, long long u);
-EXPORT_SYMBOL(atomic64_add_unless_386);
-#endif
diff --git a/arch/x86/lib/atomic64_386_32.S b/arch/x86/lib/atomic64_386_32.S
index e8e7e0d06f4..00933d5e992 100644
--- a/arch/x86/lib/atomic64_386_32.S
+++ b/arch/x86/lib/atomic64_386_32.S
@@ -137,13 +137,13 @@ BEGIN(dec_return)
 RET_ENDP
 #undef v
 
-#define v %ecx
+#define v %esi
 BEGIN(add_unless)
-        addl %eax, %esi
+        addl %eax, %ecx
         adcl %edx, %edi
         addl  (v), %eax
         adcl 4(v), %edx
-        cmpl %eax, %esi
+        cmpl %eax, %ecx
         je 3f
 1:
         movl %eax,  (v)
diff --git a/arch/x86/lib/atomic64_cx8_32.S b/arch/x86/lib/atomic64_cx8_32.S
index 391a083674b..f5cc9eb1d51 100644
--- a/arch/x86/lib/atomic64_cx8_32.S
+++ b/arch/x86/lib/atomic64_cx8_32.S
@@ -55,8 +55,6 @@ ENDPROC(atomic64_set_cx8)
 ENTRY(atomic64_xchg_cx8)
         CFI_STARTPROC
 
-        movl %ebx, %eax
-        movl %ecx, %edx
 1:
         LOCK_PREFIX
         cmpxchg8b (%esi)
@@ -78,7 +76,7 @@ ENTRY(atomic64_\func\()_return_cx8)
         movl %edx, %edi
         movl %ecx, %ebp
 
-        read64 %ebp
+        read64 %ecx
 1:
         movl %eax, %ebx
         movl %edx, %ecx
@@ -159,23 +157,22 @@ ENTRY(atomic64_add_unless_cx8)
         SAVE ebx
 /* these just push these two parameters on the stack */
         SAVE edi
-        SAVE esi
+        SAVE ecx
 
-        movl %ecx, %ebp
-        movl %eax, %esi
+        movl %eax, %ebp
         movl %edx, %edi
 
-        read64 %ebp
+        read64 %esi
 1:
         cmpl %eax, 0(%esp)
         je 4f
 2:
         movl %eax, %ebx
         movl %edx, %ecx
-        addl %esi, %ebx
+        addl %ebp, %ebx
         adcl %edi, %ecx
         LOCK_PREFIX
-        cmpxchg8b (%ebp)
+        cmpxchg8b (%esi)
         jne 1b
 
         movl $1, %eax
@@ -199,13 +196,13 @@ ENTRY(atomic64_inc_not_zero_cx8)
 
         read64 %esi
 1:
-        testl %eax, %eax
-        je 4f
-2:
+        movl %eax, %ecx
+        orl %edx, %ecx
+        jz 3f
         movl %eax, %ebx
-        movl %edx, %ecx
+        xorl %ecx, %ecx
         addl $1, %ebx
-        adcl $0, %ecx
+        adcl %edx, %ecx
         LOCK_PREFIX
         cmpxchg8b (%esi)
         jne 1b
@@ -214,9 +211,5 @@ ENTRY(atomic64_inc_not_zero_cx8)
 3:
         RESTORE ebx
         ret
-4:
-        testl %edx, %edx
-        jne 2b
-        jmp 3b
         CFI_ENDPROC
 ENDPROC(atomic64_inc_not_zero_cx8)
diff --git a/arch/x86/lib/copy_page_64.S b/arch/x86/lib/copy_page_64.S
index 01c805ba535..6b34d04d096 100644
--- a/arch/x86/lib/copy_page_64.S
+++ b/arch/x86/lib/copy_page_64.S
@@ -20,14 +20,12 @@ ENDPROC(copy_page_c)
 
 ENTRY(copy_page)
         CFI_STARTPROC
-        subq    $3*8,%rsp
-        CFI_ADJUST_CFA_OFFSET 3*8
+        subq    $2*8,%rsp
+        CFI_ADJUST_CFA_OFFSET 2*8
         movq    %rbx,(%rsp)
         CFI_REL_OFFSET rbx, 0
         movq    %r12,1*8(%rsp)
         CFI_REL_OFFSET r12, 1*8
-        movq    %r13,2*8(%rsp)
-        CFI_REL_OFFSET r13, 2*8
 
         movl    $(4096/64)-5,%ecx
         .p2align 4
@@ -91,10 +89,8 @@ ENTRY(copy_page)
         CFI_RESTORE rbx
         movq    1*8(%rsp),%r12
         CFI_RESTORE r12
-        movq    2*8(%rsp),%r13
-        CFI_RESTORE r13
-        addq    $3*8,%rsp
-        CFI_ADJUST_CFA_OFFSET -3*8
+        addq    $2*8,%rsp
+        CFI_ADJUST_CFA_OFFSET -2*8
         ret
 .Lcopy_page_end:
         CFI_ENDPROC
diff --git a/arch/x86/lib/memcpy_64.S b/arch/x86/lib/memcpy_64.S
index efbf2a0ecde..1c273be7c97 100644
--- a/arch/x86/lib/memcpy_64.S
+++ b/arch/x86/lib/memcpy_64.S
@@ -27,9 +27,8 @@
         .section .altinstr_replacement, "ax", @progbits
 .Lmemcpy_c:
         movq %rdi, %rax
-
-        movl %edx, %ecx
-        shrl $3, %ecx
+        movq %rdx, %rcx
+        shrq $3, %rcx
         andl $7, %edx
         rep movsq
         movl %edx, %ecx
@@ -48,8 +47,7 @@
         .section .altinstr_replacement, "ax", @progbits
 .Lmemcpy_c_e:
         movq %rdi, %rax
-
-        movl %edx, %ecx
+        movq %rdx, %rcx
         rep movsb
         ret
 .Lmemcpy_e_e:
@@ -60,10 +58,7 @@ ENTRY(memcpy)
         CFI_STARTPROC
         movq %rdi, %rax
 
-        /*
-         * Use 32bit CMP here to avoid long NOP padding.
-         */
-        cmp  $0x20, %edx
+        cmpq $0x20, %rdx
         jb .Lhandle_tail
 
         /*
@@ -72,7 +67,7 @@ ENTRY(memcpy)
          */
         cmp  %dil, %sil
         jl .Lcopy_backward
-        subl $0x20, %edx
+        subq $0x20, %rdx
 .Lcopy_forward_loop:
         subq $0x20,     %rdx
 
@@ -91,7 +86,7 @@ ENTRY(memcpy)
         movq %r11,      3*8(%rdi)
         leaq 4*8(%rdi), %rdi
         jae  .Lcopy_forward_loop
-        addq $0x20,     %rdx
+        addl $0x20,     %edx
         jmp  .Lhandle_tail
 
 .Lcopy_backward:
@@ -123,11 +118,11 @@ ENTRY(memcpy)
         /*
          * Calculate copy position to head.
          */
-        addq $0x20,     %rdx
+        addl $0x20,     %edx
         subq %rdx,      %rsi
         subq %rdx,      %rdi
 .Lhandle_tail:
-        cmpq $16,       %rdx
+        cmpl $16,       %edx
         jb   .Lless_16bytes
 
         /*
@@ -144,7 +139,7 @@ ENTRY(memcpy)
         retq
         .p2align 4
 .Lless_16bytes:
-        cmpq $8,        %rdx
+        cmpl $8,        %edx
         jb   .Lless_8bytes
         /*
          * Move data from 8 bytes to 15 bytes.
@@ -156,7 +151,7 @@ ENTRY(memcpy)
         retq
         .p2align 4
 .Lless_8bytes:
-        cmpq $4,        %rdx
+        cmpl $4,        %edx
         jb   .Lless_3bytes
 
         /*
@@ -169,18 +164,19 @@ ENTRY(memcpy)
         retq
         .p2align 4
 .Lless_3bytes:
-        cmpl $0, %edx
-        je .Lend
+        subl $1, %edx
+        jb .Lend
         /*
          * Move data from 1 bytes to 3 bytes.
          */
-.Lloop_1:
-        movb (%rsi), %r8b
-        movb %r8b, (%rdi)
-        incq %rdi
-        incq %rsi
-        decl %edx
-        jnz .Lloop_1
+        movzbl (%rsi), %ecx
+        jz .Lstore_1byte
+        movzbq 1(%rsi), %r8
+        movzbq (%rsi, %rdx), %r9
+        movb %r8b, 1(%rdi)
+        movb %r9b, (%rdi, %rdx)
+.Lstore_1byte:
+        movb %cl, (%rdi)
 
 .Lend:
         retq
diff --git a/arch/x86/lib/memset_64.S b/arch/x86/lib/memset_64.S
index 79bd454b78a..2dcb3808cbd 100644
--- a/arch/x86/lib/memset_64.S
+++ b/arch/x86/lib/memset_64.S
@@ -19,16 +19,15 @@
         .section .altinstr_replacement, "ax", @progbits
 .Lmemset_c:
         movq %rdi,%r9
-        movl %edx,%r8d
-        andl $7,%r8d
-        movl %edx,%ecx
-        shrl $3,%ecx
+        movq %rdx,%rcx
+        andl $7,%edx
+        shrq $3,%rcx
         /* expand byte value  */
         movzbl %sil,%esi
         movabs $0x0101010101010101,%rax
-        mulq %rsi               /* with rax, clobbers rdx */
+        imulq %rsi,%rax
         rep stosq
-        movl %r8d,%ecx
+        movl %edx,%ecx
         rep stosb
         movq %r9,%rax
         ret
@@ -50,7 +49,7 @@
 .Lmemset_c_e:
         movq %rdi,%r9
         movb %sil,%al
-        movl %edx,%ecx
+        movq %rdx,%rcx
         rep stosb
         movq %r9,%rax
         ret
@@ -61,12 +60,11 @@ ENTRY(memset)
 ENTRY(__memset)
         CFI_STARTPROC
         movq %rdi,%r10
-        movq %rdx,%r11
 
         /* expand byte value  */
         movzbl %sil,%ecx
         movabs $0x0101010101010101,%rax
-        mul    %rcx             /* with rax, clobbers rdx */
+        imulq  %rcx,%rax
 
         /* align dst */
         movl  %edi,%r9d
@@ -75,13 +73,13 @@ ENTRY(__memset)
         CFI_REMEMBER_STATE
 .Lafter_bad_alignment:
 
-        movl %r11d,%ecx
-        shrl $6,%ecx
+        movq  %rdx,%rcx
+        shrq  $6,%rcx
         jz       .Lhandle_tail
 
         .p2align 4
 .Lloop_64:
-        decl   %ecx
+        decq  %rcx
         movq  %rax,(%rdi)
         movq  %rax,8(%rdi)
         movq  %rax,16(%rdi)
@@ -97,7 +95,7 @@ ENTRY(__memset)
            to predict jump tables. */
         .p2align 4
 .Lhandle_tail:
-        movl    %r11d,%ecx
+        movl    %edx,%ecx
         andl    $63&(~7),%ecx
         jz              .Lhandle_7
         shrl    $3,%ecx
@@ -109,12 +107,11 @@ ENTRY(__memset)
         jnz    .Lloop_8
 
 .Lhandle_7:
-        movl    %r11d,%ecx
-        andl    $7,%ecx
+        andl    $7,%edx
         jz      .Lende
         .p2align 4
 .Lloop_1:
-        decl    %ecx
+        decl    %edx
         movb    %al,(%rdi)
         leaq    1(%rdi),%rdi
         jnz     .Lloop_1
@@ -125,13 +122,13 @@ ENTRY(__memset)
 
         CFI_RESTORE_STATE
 .Lbad_alignment:
-        cmpq $7,%r11
+        cmpq $7,%rdx
         jbe     .Lhandle_7
         movq %rax,(%rdi)        /* unaligned store */
         movq $8,%r8
         subq %r9,%r8
         addq %r8,%rdi
-        subq %r8,%r11
+        subq %r8,%rdx
         jmp .Lafter_bad_alignment
 .Lfinal:
         CFI_ENDPROC
diff --git a/arch/x86/mm/hugetlbpage.c b/arch/x86/mm/hugetlbpage.c
index 8ecbb4bba4b..f6679a7fb8c 100644
--- a/arch/x86/mm/hugetlbpage.c
+++ b/arch/x86/mm/hugetlbpage.c
@@ -308,10 +308,11 @@ static unsigned long hugetlb_get_unmapped_area_topdown(struct file *file,
 {
         struct hstate *h = hstate_file(file);
         struct mm_struct *mm = current->mm;
-        struct vm_area_struct *vma, *prev_vma;
-        unsigned long base = mm->mmap_base, addr = addr0;
+        struct vm_area_struct *vma;
+        unsigned long base = mm->mmap_base;
+        unsigned long addr = addr0;
         unsigned long largest_hole = mm->cached_hole_size;
-        int first_time = 1;
+        unsigned long start_addr;
 
         /* don't allow allocations above current base */
         if (mm->free_area_cache > base)
@@ -322,6 +323,8 @@ static unsigned long hugetlb_get_unmapped_area_topdown(struct file *file,
                 mm->free_area_cache  = base;
         }
 try_again:
+        start_addr = mm->free_area_cache;
+
         /* make sure it can fit in the remaining address space */
         if (mm->free_area_cache < len)
                 goto fail;
@@ -337,22 +340,14 @@ try_again:
                 if (!vma)
                         return addr;
 
-                /*
-                 * new region fits between prev_vma->vm_end and
-                 * vma->vm_start, use it:
-                 */
-                prev_vma = vma->vm_prev;
-                if (addr + len <= vma->vm_start &&
-                            (!prev_vma || (addr >= prev_vma->vm_end))) {
+                if (addr + len <= vma->vm_start) {
                         /* remember the address as a hint for next time */
                         mm->cached_hole_size = largest_hole;
                         return (mm->free_area_cache = addr);
-                } else {
+                } else if (mm->free_area_cache == vma->vm_end) {
                         /* pull free_area_cache down to the first hole */
-                        if (mm->free_area_cache == vma->vm_end) {
-                                mm->free_area_cache = vma->vm_start;
-                                mm->cached_hole_size = largest_hole;
-                        }
+                        mm->free_area_cache = vma->vm_start;
+                        mm->cached_hole_size = largest_hole;
                 }
 
                 /* remember the largest hole we saw so far */
@@ -368,10 +363,9 @@ fail:
          * if hint left us with no space for the requested
          * mapping then try again:
          */
-        if (first_time) {
+        if (start_addr != base) {
                 mm->free_area_cache = base;
                 largest_hole = 0;
-                first_time = 0;
                 goto try_again;
         }
         /*
diff --git a/arch/x86/mm/kmemcheck/selftest.c b/arch/x86/mm/kmemcheck/selftest.c
index 036efbea8b2..aef7140c006 100644
--- a/arch/x86/mm/kmemcheck/selftest.c
+++ b/arch/x86/mm/kmemcheck/selftest.c
@@ -1,3 +1,4 @@
+#include <linux/bug.h>
 #include <linux/kernel.h>
 
 #include "opcode.h"
diff --git a/arch/x86/mm/numa_emulation.c b/arch/x86/mm/numa_emulation.c
index 46db56845f1..53489ff6bf8 100644
--- a/arch/x86/mm/numa_emulation.c
+++ b/arch/x86/mm/numa_emulation.c
@@ -28,7 +28,7 @@ static int __init emu_find_memblk_by_nid(int nid, const struct numa_meminfo *mi)
         return -ENOENT;
 }
 
-static u64 mem_hole_size(u64 start, u64 end)
+static u64 __init mem_hole_size(u64 start, u64 end)
 {
         unsigned long start_pfn = PFN_UP(start);
         unsigned long end_pfn = PFN_DOWN(end);
@@ -60,7 +60,7 @@ static int __init emu_setup_memblk(struct numa_meminfo *ei,
         eb->nid = nid;
 
         if (emu_nid_to_phys[nid] == NUMA_NO_NODE)
-                emu_nid_to_phys[nid] = pb->nid;
+                emu_nid_to_phys[nid] = nid;
 
         pb->start += size;
         if (pb->start >= pb->end) {
diff --git a/arch/x86/pci/acpi.c b/arch/x86/pci/acpi.c
index 49a5cb55429..ed2835e148b 100644
--- a/arch/x86/pci/acpi.c
+++ b/arch/x86/pci/acpi.c
@@ -416,7 +416,12 @@ struct pci_bus * __devinit pci_acpi_scan_root(struct acpi_pci_root *root)
                 kfree(sd);
         } else {
                 get_current_resources(device, busnum, domain, &resources);
-                if (list_empty(&resources))
+
+                /*
+                 * _CRS with no apertures is normal, so only fall back to
+                 * defaults or native bridge info if we're ignoring _CRS.
+                 */
+                if (!pci_use_crs)
                         x86_pci_root_bus_resources(busnum, &resources);
                 bus = pci_create_root_bus(NULL, busnum, &pci_root_ops, sd,
                                           &resources);
diff --git a/arch/x86/pci/fixup.c b/arch/x86/pci/fixup.c
index 6dd89555fbf..d0e6e403b4f 100644
--- a/arch/x86/pci/fixup.c
+++ b/arch/x86/pci/fixup.c
@@ -164,11 +164,11 @@ DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8367_0, pci_fixup_
  */
 static void __devinit pci_fixup_transparent_bridge(struct pci_dev *dev)
 {
-        if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI &&
-            (dev->device & 0xff00) == 0x2400)
+        if ((dev->device & 0xff00) == 0x2400)
                 dev->transparent = 1;
 }
-DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_fixup_transparent_bridge);
+DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_INTEL, PCI_ANY_ID,
+                         PCI_CLASS_BRIDGE_PCI, 8, pci_fixup_transparent_bridge);
 
 /*
  * Fixup for C1 Halt Disconnect problem on nForce2 systems.
@@ -322,9 +322,6 @@ static void __devinit pci_fixup_video(struct pci_dev *pdev)
         struct pci_bus *bus;
         u16 config;
 
-        if ((pdev->class >> 8) != PCI_CLASS_DISPLAY_VGA)
-                return;
-
         /* Is VGA routed to us? */
         bus = pdev->bus;
         while (bus) {
@@ -353,7 +350,8 @@ static void __devinit pci_fixup_video(struct pci_dev *pdev)
                 dev_printk(KERN_DEBUG, &pdev->dev, "Boot video device\n");
         }
 }
-DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, pci_fixup_video);
+DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_ANY_ID, PCI_ANY_ID,
+                                PCI_CLASS_DISPLAY_VGA, 8, pci_fixup_video);
 
 
 static const struct dmi_system_id __devinitconst msi_k8t_dmi_table[] = {
diff --git a/arch/x86/pci/i386.c b/arch/x86/pci/i386.c
index 91821a1a0c3..831971e731f 100644
--- a/arch/x86/pci/i386.c
+++ b/arch/x86/pci/i386.c
@@ -39,6 +39,87 @@
 #include <asm/io_apic.h>
 
 
+/*
+ * This list of dynamic mappings is for temporarily maintaining
+ * original BIOS BAR addresses for possible reinstatement.
+ */
+struct pcibios_fwaddrmap {
+        struct list_head list;
+        struct pci_dev *dev;
+        resource_size_t fw_addr[DEVICE_COUNT_RESOURCE];
+};
+
+static LIST_HEAD(pcibios_fwaddrmappings);
+static DEFINE_SPINLOCK(pcibios_fwaddrmap_lock);
+
+/* Must be called with 'pcibios_fwaddrmap_lock' lock held. */
+static struct pcibios_fwaddrmap *pcibios_fwaddrmap_lookup(struct pci_dev *dev)
+{
+        struct pcibios_fwaddrmap *map;
+
+        WARN_ON(!spin_is_locked(&pcibios_fwaddrmap_lock));
+
+        list_for_each_entry(map, &pcibios_fwaddrmappings, list)
+                if (map->dev == dev)
+                        return map;
+
+        return NULL;
+}
+
+static void
+pcibios_save_fw_addr(struct pci_dev *dev, int idx, resource_size_t fw_addr)
+{
+        unsigned long flags;
+        struct pcibios_fwaddrmap *map;
+
+        spin_lock_irqsave(&pcibios_fwaddrmap_lock, flags);
+        map = pcibios_fwaddrmap_lookup(dev);
+        if (!map) {
+                spin_unlock_irqrestore(&pcibios_fwaddrmap_lock, flags);
+                map = kzalloc(sizeof(*map), GFP_KERNEL);
+                if (!map)
+                        return;
+
+                map->dev = pci_dev_get(dev);
+                map->fw_addr[idx] = fw_addr;
+                INIT_LIST_HEAD(&map->list);
+
+                spin_lock_irqsave(&pcibios_fwaddrmap_lock, flags);
+                list_add_tail(&map->list, &pcibios_fwaddrmappings);
+        } else
+                map->fw_addr[idx] = fw_addr;
+        spin_unlock_irqrestore(&pcibios_fwaddrmap_lock, flags);
+}
+
+resource_size_t pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx)
+{
+        unsigned long flags;
+        struct pcibios_fwaddrmap *map;
+        resource_size_t fw_addr = 0;
+
+        spin_lock_irqsave(&pcibios_fwaddrmap_lock, flags);
+        map = pcibios_fwaddrmap_lookup(dev);
+        if (map)
+                fw_addr = map->fw_addr[idx];
+        spin_unlock_irqrestore(&pcibios_fwaddrmap_lock, flags);
+
+        return fw_addr;
+}
+
+static void pcibios_fw_addr_list_del(void)
+{
+        unsigned long flags;
+        struct pcibios_fwaddrmap *entry, *next;
+
+        spin_lock_irqsave(&pcibios_fwaddrmap_lock, flags);
+        list_for_each_entry_safe(entry, next, &pcibios_fwaddrmappings, list) {
+                list_del(&entry->list);
+                pci_dev_put(entry->dev);
+                kfree(entry);
+        }
+        spin_unlock_irqrestore(&pcibios_fwaddrmap_lock, flags);
+}
+
 static int
 skip_isa_ioresource_align(struct pci_dev *dev) {
 
@@ -182,7 +263,8 @@ static void __init pcibios_allocate_resources(int pass)
                                         idx, r, disabled, pass);
                                 if (pci_claim_resource(dev, idx) < 0) {
                                         /* We'll assign a new address later */
-                                        dev->fw_addr[idx] = r->start;
+                                        pcibios_save_fw_addr(dev,
+                                                        idx, r->start);
                                         r->end -= r->start;
                                         r->start = 0;
                                 }
@@ -228,6 +310,7 @@ static int __init pcibios_assign_resources(void)
         }
 
         pci_assign_unassigned_resources();
+        pcibios_fw_addr_list_del();
 
         return 0;
 }
diff --git a/arch/x86/pci/mrst.c b/arch/x86/pci/mrst.c
index cb29191cee5..140942f66b3 100644
--- a/arch/x86/pci/mrst.c
+++ b/arch/x86/pci/mrst.c
@@ -43,6 +43,8 @@
 #define PCI_FIXED_BAR_4_SIZE    0x14
 #define PCI_FIXED_BAR_5_SIZE    0x1c
 
+static int pci_soc_mode = 0;
+
 /**
  * fixed_bar_cap - return the offset of the fixed BAR cap if found
  * @bus: PCI bus
@@ -148,7 +150,9 @@ static bool type1_access_ok(unsigned int bus, unsigned int devfn, int reg)
          */
         if (reg >= 0x100 || reg == PCI_STATUS || reg == PCI_HEADER_TYPE)
                 return 0;
-        if (bus == 0 && (devfn == PCI_DEVFN(2, 0) || devfn == PCI_DEVFN(0, 0)))
+        if (bus == 0 && (devfn == PCI_DEVFN(2, 0)
+                                || devfn == PCI_DEVFN(0, 0)
+                                || devfn == PCI_DEVFN(3, 0)))
                 return 1;
         return 0; /* langwell on others */
 }
@@ -231,14 +235,43 @@ struct pci_ops pci_mrst_ops = {
  */
 int __init pci_mrst_init(void)
 {
-        printk(KERN_INFO "Moorestown platform detected, using MRST PCI ops\n");
+        printk(KERN_INFO "Intel MID platform detected, using MID PCI ops\n");
         pci_mmcfg_late_init();
         pcibios_enable_irq = mrst_pci_irq_enable;
         pci_root_ops = pci_mrst_ops;
+        pci_soc_mode = 1;
         /* Continue with standard init */
         return 1;
 }
 
+/* Langwell devices are not true pci devices, they are not subject to 10 ms
+ * d3 to d0 delay required by pci spec.
+ */
+static void __devinit pci_d3delay_fixup(struct pci_dev *dev)
+{
+        /* PCI fixups are effectively decided compile time. If we have a dual
+           SoC/non-SoC kernel we don't want to mangle d3 on non SoC devices */
+        if (!pci_soc_mode)
+            return;
+        /* true pci devices in lincroft should allow type 1 access, the rest
+         * are langwell fake pci devices.
+         */
+        if (type1_access_ok(dev->bus->number, dev->devfn, PCI_DEVICE_ID))
+                return;
+        dev->d3_delay = 0;
+}
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_d3delay_fixup);
+
+static void __devinit mrst_power_off_unused_dev(struct pci_dev *dev)
+{
+        pci_set_power_state(dev, PCI_D3cold);
+}
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0801, mrst_power_off_unused_dev);
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0809, mrst_power_off_unused_dev);
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x080C, mrst_power_off_unused_dev);
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0812, mrst_power_off_unused_dev);
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0815, mrst_power_off_unused_dev);
+
 /*
  * Langwell devices reside at fixed offsets, don't try to move them.
  */
@@ -248,6 +281,9 @@ static void __devinit pci_fixed_bar_fixup(struct pci_dev *dev)
         u32 size;
         int i;
 
+        if (!pci_soc_mode)
+                return;
+
         /* Must have extended configuration space */
         if (dev->cfg_size < PCIE_CAP_OFFSET + 4)
                 return;
diff --git a/arch/x86/pci/xen.c b/arch/x86/pci/xen.c
index d99346ea8fd..7415aa92791 100644
--- a/arch/x86/pci/xen.c
+++ b/arch/x86/pci/xen.c
@@ -324,6 +324,32 @@ static int xen_initdom_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
 out:
         return ret;
 }
+
+static void xen_initdom_restore_msi_irqs(struct pci_dev *dev, int irq)
+{
+        int ret = 0;
+
+        if (pci_seg_supported) {
+                struct physdev_pci_device restore_ext;
+
+                restore_ext.seg = pci_domain_nr(dev->bus);
+                restore_ext.bus = dev->bus->number;
+                restore_ext.devfn = dev->devfn;
+                ret = HYPERVISOR_physdev_op(PHYSDEVOP_restore_msi_ext,
+                                        &restore_ext);
+                if (ret == -ENOSYS)
+                        pci_seg_supported = false;
+                WARN(ret && ret != -ENOSYS, "restore_msi_ext -> %d\n", ret);
+        }
+        if (!pci_seg_supported) {
+                struct physdev_restore_msi restore;
+
+                restore.bus = dev->bus->number;
+                restore.devfn = dev->devfn;
+                ret = HYPERVISOR_physdev_op(PHYSDEVOP_restore_msi, &restore);
+                WARN(ret && ret != -ENOSYS, "restore_msi -> %d\n", ret);
+        }
+}
 #endif
 
 static void xen_teardown_msi_irqs(struct pci_dev *dev)
@@ -446,6 +472,7 @@ int __init pci_xen_initial_domain(void)
 #ifdef CONFIG_PCI_MSI
         x86_msi.setup_msi_irqs = xen_initdom_setup_msi_irqs;
         x86_msi.teardown_msi_irq = xen_teardown_msi_irq;
+        x86_msi.restore_msi_irqs = xen_initdom_restore_msi_irqs;
 #endif
         xen_setup_acpi_sci();
         __acpi_register_gsi = acpi_register_gsi_xen;
diff --git a/arch/x86/platform/efi/efi.c b/arch/x86/platform/efi/efi.c
index 4cf9bd0a165..92660edaa1e 100644
--- a/arch/x86/platform/efi/efi.c
+++ b/arch/x86/platform/efi/efi.c
@@ -26,6 +26,8 @@
  *      Skip non-WB memory and ignore empty memory ranges.
  */
 
+#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
+
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/efi.h>
@@ -47,7 +49,6 @@
 #include <asm/x86_init.h>
 
 #define EFI_DEBUG       1
-#define PFX             "EFI: "
 
 int efi_enabled;
 EXPORT_SYMBOL(efi_enabled);
@@ -67,6 +68,9 @@ EXPORT_SYMBOL(efi);
 
 struct efi_memory_map memmap;
 
+bool efi_64bit;
+static bool efi_native;
+
 static struct efi efi_phys __initdata;
 static efi_system_table_t efi_systab __initdata;
 
@@ -254,7 +258,7 @@ int efi_set_rtc_mmss(unsigned long nowtime)
 
         status = efi.get_time(&eft, &cap);
         if (status != EFI_SUCCESS) {
-                printk(KERN_ERR "Oops: efitime: can't read time!\n");
+                pr_err("Oops: efitime: can't read time!\n");
                 return -1;
         }
 
@@ -268,7 +272,7 @@ int efi_set_rtc_mmss(unsigned long nowtime)
 
         status = efi.set_time(&eft);
         if (status != EFI_SUCCESS) {
-                printk(KERN_ERR "Oops: efitime: can't write time!\n");
+                pr_err("Oops: efitime: can't write time!\n");
                 return -1;
         }
         return 0;
@@ -282,7 +286,7 @@ unsigned long efi_get_time(void)
 
         status = efi.get_time(&eft, &cap);
         if (status != EFI_SUCCESS)
-                printk(KERN_ERR "Oops: efitime: can't read time!\n");
+                pr_err("Oops: efitime: can't read time!\n");
 
         return mktime(eft.year, eft.month, eft.day, eft.hour,
                       eft.minute, eft.second);
@@ -338,11 +342,16 @@ static void __init do_add_efi_memmap(void)
         sanitize_e820_map(e820.map, ARRAY_SIZE(e820.map), &e820.nr_map);
 }
 
-void __init efi_memblock_x86_reserve_range(void)
+int __init efi_memblock_x86_reserve_range(void)
 {
         unsigned long pmap;
 
 #ifdef CONFIG_X86_32
+        /* Can't handle data above 4GB at this time */
+        if (boot_params.efi_info.efi_memmap_hi) {
+                pr_err("Memory map is above 4GB, disabling EFI.\n");
+                return -EINVAL;
+        }
         pmap = boot_params.efi_info.efi_memmap;
 #else
         pmap = (boot_params.efi_info.efi_memmap |
@@ -354,6 +363,8 @@ void __init efi_memblock_x86_reserve_range(void)
         memmap.desc_version = boot_params.efi_info.efi_memdesc_version;
         memmap.desc_size = boot_params.efi_info.efi_memdesc_size;
         memblock_reserve(pmap, memmap.nr_map * memmap.desc_size);
+
+        return 0;
 }
 
 #if EFI_DEBUG
@@ -367,7 +378,7 @@ static void __init print_efi_memmap(void)
              p < memmap.map_end;
              p += memmap.desc_size, i++) {
                 md = p;
-                printk(KERN_INFO PFX "mem%02u: type=%u, attr=0x%llx, "
+                pr_info("mem%02u: type=%u, attr=0x%llx, "
                         "range=[0x%016llx-0x%016llx) (%lluMB)\n",
                         i, md->type, md->attribute, md->phys_addr,
                         md->phys_addr + (md->num_pages << EFI_PAGE_SHIFT),
@@ -400,7 +411,7 @@ void __init efi_reserve_boot_services(void)
                         memblock_is_region_reserved(start, size)) {
                         /* Could not reserve, skip it */
                         md->num_pages = 0;
-                        memblock_dbg(PFX "Could not reserve boot range "
+                        memblock_dbg("Could not reserve boot range "
                                         "[0x%010llx-0x%010llx]\n",
                                                 start, start+size-1);
                 } else
@@ -429,103 +440,172 @@ static void __init efi_free_boot_services(void)
         }
 }
 
-void __init efi_init(void)
+static int __init efi_systab_init(void *phys)
 {
-        efi_config_table_t *config_tables;
-        efi_runtime_services_t *runtime;
-        efi_char16_t *c16;
-        char vendor[100] = "unknown";
-        int i = 0;
-        void *tmp;
+        if (efi_64bit) {
+                efi_system_table_64_t *systab64;
+                u64 tmp = 0;
+
+                systab64 = early_ioremap((unsigned long)phys,
+                                         sizeof(*systab64));
+                if (systab64 == NULL) {
+                        pr_err("Couldn't map the system table!\n");
+                        return -ENOMEM;
+                }
 
+                efi_systab.hdr = systab64->hdr;
+                efi_systab.fw_vendor = systab64->fw_vendor;
+                tmp |= systab64->fw_vendor;
+                efi_systab.fw_revision = systab64->fw_revision;
+                efi_systab.con_in_handle = systab64->con_in_handle;
+                tmp |= systab64->con_in_handle;
+                efi_systab.con_in = systab64->con_in;
+                tmp |= systab64->con_in;
+                efi_systab.con_out_handle = systab64->con_out_handle;
+                tmp |= systab64->con_out_handle;
+                efi_systab.con_out = systab64->con_out;
+                tmp |= systab64->con_out;
+                efi_systab.stderr_handle = systab64->stderr_handle;
+                tmp |= systab64->stderr_handle;
+                efi_systab.stderr = systab64->stderr;
+                tmp |= systab64->stderr;
+                efi_systab.runtime = (void *)(unsigned long)systab64->runtime;
+                tmp |= systab64->runtime;
+                efi_systab.boottime = (void *)(unsigned long)systab64->boottime;
+                tmp |= systab64->boottime;
+                efi_systab.nr_tables = systab64->nr_tables;
+                efi_systab.tables = systab64->tables;
+                tmp |= systab64->tables;
+
+                early_iounmap(systab64, sizeof(*systab64));
 #ifdef CONFIG_X86_32
-        efi_phys.systab = (efi_system_table_t *)boot_params.efi_info.efi_systab;
-#else
-        efi_phys.systab = (efi_system_table_t *)
-                (boot_params.efi_info.efi_systab |
-                 ((__u64)boot_params.efi_info.efi_systab_hi<<32));
+                if (tmp >> 32) {
+                        pr_err("EFI data located above 4GB, disabling EFI.\n");
+                        return -EINVAL;
+                }
 #endif
+        } else {
+                efi_system_table_32_t *systab32;
+
+                systab32 = early_ioremap((unsigned long)phys,
+                                         sizeof(*systab32));
+                if (systab32 == NULL) {
+                        pr_err("Couldn't map the system table!\n");
+                        return -ENOMEM;
+                }
+
+                efi_systab.hdr = systab32->hdr;
+                efi_systab.fw_vendor = systab32->fw_vendor;
+                efi_systab.fw_revision = systab32->fw_revision;
+                efi_systab.con_in_handle = systab32->con_in_handle;
+                efi_systab.con_in = systab32->con_in;
+                efi_systab.con_out_handle = systab32->con_out_handle;
+                efi_systab.con_out = systab32->con_out;
+                efi_systab.stderr_handle = systab32->stderr_handle;
+                efi_systab.stderr = systab32->stderr;
+                efi_systab.runtime = (void *)(unsigned long)systab32->runtime;
+                efi_systab.boottime = (void *)(unsigned long)systab32->boottime;
+                efi_systab.nr_tables = systab32->nr_tables;
+                efi_systab.tables = systab32->tables;
+
+                early_iounmap(systab32, sizeof(*systab32));
+        }
 
-        efi.systab = early_ioremap((unsigned long)efi_phys.systab,
-                                   sizeof(efi_system_table_t));
-        if (efi.systab == NULL)
-                printk(KERN_ERR "Couldn't map the EFI system table!\n");
-        memcpy(&efi_systab, efi.systab, sizeof(efi_system_table_t));
-        early_iounmap(efi.systab, sizeof(efi_system_table_t));
         efi.systab = &efi_systab;
 
         /*
          * Verify the EFI Table
          */
-        if (efi.systab->hdr.signature != EFI_SYSTEM_TABLE_SIGNATURE)
-                printk(KERN_ERR "EFI system table signature incorrect!\n");
+        if (efi.systab->hdr.signature != EFI_SYSTEM_TABLE_SIGNATURE) {
+                pr_err("System table signature incorrect!\n");
+                return -EINVAL;
+        }
         if ((efi.systab->hdr.revision >> 16) == 0)
-                printk(KERN_ERR "Warning: EFI system table version "
+                pr_err("Warning: System table version "
                        "%d.%02d, expected 1.00 or greater!\n",
                        efi.systab->hdr.revision >> 16,
                        efi.systab->hdr.revision & 0xffff);
 
-        /*
-         * Show what we know for posterity
-         */
-        c16 = tmp = early_ioremap(efi.systab->fw_vendor, 2);
-        if (c16) {
-                for (i = 0; i < sizeof(vendor) - 1 && *c16; ++i)
-                        vendor[i] = *c16++;
-                vendor[i] = '\0';
-        } else
-                printk(KERN_ERR PFX "Could not map the firmware vendor!\n");
-        early_iounmap(tmp, 2);
+        return 0;
+}
 
-        printk(KERN_INFO "EFI v%u.%.02u by %s\n",
-               efi.systab->hdr.revision >> 16,
-               efi.systab->hdr.revision & 0xffff, vendor);
+static int __init efi_config_init(u64 tables, int nr_tables)
+{
+        void *config_tables, *tablep;
+        int i, sz;
+
+        if (efi_64bit)
+                sz = sizeof(efi_config_table_64_t);
+        else
+                sz = sizeof(efi_config_table_32_t);
 
         /*
          * Let's see what config tables the firmware passed to us.
          */
-        config_tables = early_ioremap(
-                efi.systab->tables,
-                efi.systab->nr_tables * sizeof(efi_config_table_t));
-        if (config_tables == NULL)
-                printk(KERN_ERR "Could not map EFI Configuration Table!\n");
+        config_tables = early_ioremap(tables, nr_tables * sz);
+        if (config_tables == NULL) {
+                pr_err("Could not map Configuration table!\n");
+                return -ENOMEM;
+        }
 
-        printk(KERN_INFO);
+        tablep = config_tables;
+        pr_info("");
         for (i = 0; i < efi.systab->nr_tables; i++) {
-                if (!efi_guidcmp(config_tables[i].guid, MPS_TABLE_GUID)) {
-                        efi.mps = config_tables[i].table;
-                        printk(" MPS=0x%lx ", config_tables[i].table);
-                } else if (!efi_guidcmp(config_tables[i].guid,
-                                        ACPI_20_TABLE_GUID)) {
-                        efi.acpi20 = config_tables[i].table;
-                        printk(" ACPI 2.0=0x%lx ", config_tables[i].table);
-                } else if (!efi_guidcmp(config_tables[i].guid,
-                                        ACPI_TABLE_GUID)) {
-                        efi.acpi = config_tables[i].table;
-                        printk(" ACPI=0x%lx ", config_tables[i].table);
-                } else if (!efi_guidcmp(config_tables[i].guid,
-                                        SMBIOS_TABLE_GUID)) {
-                        efi.smbios = config_tables[i].table;
-                        printk(" SMBIOS=0x%lx ", config_tables[i].table);
+                efi_guid_t guid;
+                unsigned long table;
+
+                if (efi_64bit) {
+                        u64 table64;
+                        guid = ((efi_config_table_64_t *)tablep)->guid;
+                        table64 = ((efi_config_table_64_t *)tablep)->table;
+                        table = table64;
+#ifdef CONFIG_X86_32
+                        if (table64 >> 32) {
+                                pr_cont("\n");
+                                pr_err("Table located above 4GB, disabling EFI.\n");
+                                early_iounmap(config_tables,
+                                              efi.systab->nr_tables * sz);
+                                return -EINVAL;
+                        }
+#endif
+                } else {
+                        guid = ((efi_config_table_32_t *)tablep)->guid;
+                        table = ((efi_config_table_32_t *)tablep)->table;
+                }
+                if (!efi_guidcmp(guid, MPS_TABLE_GUID)) {
+                        efi.mps = table;
+                        pr_cont(" MPS=0x%lx ", table);
+                } else if (!efi_guidcmp(guid, ACPI_20_TABLE_GUID)) {
+                        efi.acpi20 = table;
+                        pr_cont(" ACPI 2.0=0x%lx ", table);
+                } else if (!efi_guidcmp(guid, ACPI_TABLE_GUID)) {
+                        efi.acpi = table;
+                        pr_cont(" ACPI=0x%lx ", table);
+                } else if (!efi_guidcmp(guid, SMBIOS_TABLE_GUID)) {
+                        efi.smbios = table;
+                        pr_cont(" SMBIOS=0x%lx ", table);
 #ifdef CONFIG_X86_UV
-                } else if (!efi_guidcmp(config_tables[i].guid,
-                                        UV_SYSTEM_TABLE_GUID)) {
-                        efi.uv_systab = config_tables[i].table;
-                        printk(" UVsystab=0x%lx ", config_tables[i].table);
+                } else if (!efi_guidcmp(guid, UV_SYSTEM_TABLE_GUID)) {
+                        efi.uv_systab = table;
+                        pr_cont(" UVsystab=0x%lx ", table);
 #endif
-                } else if (!efi_guidcmp(config_tables[i].guid,
-                                        HCDP_TABLE_GUID)) {
-                        efi.hcdp = config_tables[i].table;
-                        printk(" HCDP=0x%lx ", config_tables[i].table);
-                } else if (!efi_guidcmp(config_tables[i].guid,
-                                        UGA_IO_PROTOCOL_GUID)) {
-                        efi.uga = config_tables[i].table;
-                        printk(" UGA=0x%lx ", config_tables[i].table);
+                } else if (!efi_guidcmp(guid, HCDP_TABLE_GUID)) {
+                        efi.hcdp = table;
+                        pr_cont(" HCDP=0x%lx ", table);
+                } else if (!efi_guidcmp(guid, UGA_IO_PROTOCOL_GUID)) {
+                        efi.uga = table;
+                        pr_cont(" UGA=0x%lx ", table);
                 }
+                tablep += sz;
         }
-        printk("\n");
-        early_iounmap(config_tables,
-                          efi.systab->nr_tables * sizeof(efi_config_table_t));
+        pr_cont("\n");
+        early_iounmap(config_tables, efi.systab->nr_tables * sz);
+        return 0;
+}
+
+static int __init efi_runtime_init(void)
+{
+        efi_runtime_services_t *runtime;
 
         /*
          * Check out the runtime services table. We need to map
@@ -535,43 +615,116 @@ void __init efi_init(void)
          */
         runtime = early_ioremap((unsigned long)efi.systab->runtime,
                                 sizeof(efi_runtime_services_t));
-        if (runtime != NULL) {
-                /*
-                 * We will only need *early* access to the following
-                 * two EFI runtime services before set_virtual_address_map
-                 * is invoked.
-                 */
-                efi_phys.get_time = (efi_get_time_t *)runtime->get_time;
-                efi_phys.set_virtual_address_map =
-                        (efi_set_virtual_address_map_t *)
-                        runtime->set_virtual_address_map;
-                /*
-                 * Make efi_get_time can be called before entering
-                 * virtual mode.
-                 */
-                efi.get_time = phys_efi_get_time;
-        } else
-                printk(KERN_ERR "Could not map the EFI runtime service "
-                       "table!\n");
+        if (!runtime) {
+                pr_err("Could not map the runtime service table!\n");
+                return -ENOMEM;
+        }
+        /*
+         * We will only need *early* access to the following
+         * two EFI runtime services before set_virtual_address_map
+         * is invoked.
+         */
+        efi_phys.get_time = (efi_get_time_t *)runtime->get_time;
+        efi_phys.set_virtual_address_map =
+                (efi_set_virtual_address_map_t *)
+                runtime->set_virtual_address_map;
+        /*
+         * Make efi_get_time can be called before entering
+         * virtual mode.
+         */
+        efi.get_time = phys_efi_get_time;
         early_iounmap(runtime, sizeof(efi_runtime_services_t));
 
+        return 0;
+}
+
+static int __init efi_memmap_init(void)
+{
         /* Map the EFI memory map */
         memmap.map = early_ioremap((unsigned long)memmap.phys_map,
                                    memmap.nr_map * memmap.desc_size);
-        if (memmap.map == NULL)
-                printk(KERN_ERR "Could not map the EFI memory map!\n");
+        if (memmap.map == NULL) {
+                pr_err("Could not map the memory map!\n");
+                return -ENOMEM;
+        }
         memmap.map_end = memmap.map + (memmap.nr_map * memmap.desc_size);
 
-        if (memmap.desc_size != sizeof(efi_memory_desc_t))
-                printk(KERN_WARNING
-                  "Kernel-defined memdesc doesn't match the one from EFI!\n");
-
         if (add_efi_memmap)
                 do_add_efi_memmap();
 
+        return 0;
+}
+
+void __init efi_init(void)
+{
+        efi_char16_t *c16;
+        char vendor[100] = "unknown";
+        int i = 0;
+        void *tmp;
+
+#ifdef CONFIG_X86_32
+        if (boot_params.efi_info.efi_systab_hi ||
+            boot_params.efi_info.efi_memmap_hi) {
+                pr_info("Table located above 4GB, disabling EFI.\n");
+                efi_enabled = 0;
+                return;
+        }
+        efi_phys.systab = (efi_system_table_t *)boot_params.efi_info.efi_systab;
+        efi_native = !efi_64bit;
+#else
+        efi_phys.systab = (efi_system_table_t *)
+                          (boot_params.efi_info.efi_systab |
+                          ((__u64)boot_params.efi_info.efi_systab_hi<<32));
+        efi_native = efi_64bit;
+#endif
+
+        if (efi_systab_init(efi_phys.systab)) {
+                efi_enabled = 0;
+                return;
+        }
+
+        /*
+         * Show what we know for posterity
+         */
+        c16 = tmp = early_ioremap(efi.systab->fw_vendor, 2);
+        if (c16) {
+                for (i = 0; i < sizeof(vendor) - 1 && *c16; ++i)
+                        vendor[i] = *c16++;
+                vendor[i] = '\0';
+        } else
+                pr_err("Could not map the firmware vendor!\n");
+        early_iounmap(tmp, 2);
+
+        pr_info("EFI v%u.%.02u by %s\n",
+                efi.systab->hdr.revision >> 16,
+                efi.systab->hdr.revision & 0xffff, vendor);
+
+        if (efi_config_init(efi.systab->tables, efi.systab->nr_tables)) {
+                efi_enabled = 0;
+                return;
+        }
+
+        /*
+         * Note: We currently don't support runtime services on an EFI
+         * that doesn't match the kernel 32/64-bit mode.
+         */
+
+        if (!efi_native)
+                pr_info("No EFI runtime due to 32/64-bit mismatch with kernel\n");
+        else if (efi_runtime_init()) {
+                efi_enabled = 0;
+                return;
+        }
+
+        if (efi_memmap_init()) {
+                efi_enabled = 0;
+                return;
+        }
 #ifdef CONFIG_X86_32
-        x86_platform.get_wallclock = efi_get_time;
-        x86_platform.set_wallclock = efi_set_rtc_mmss;
+        if (efi_native) {
+                x86_platform.get_wallclock = efi_get_time;
+                x86_platform.set_wallclock = efi_set_rtc_mmss;
+        }
 #endif
 
 #if EFI_DEBUG
@@ -629,6 +782,14 @@ void __init efi_enter_virtual_mode(void)
 
         efi.systab = NULL;
 
+        /*
+         * We don't do virtual mode, since we don't do runtime services, on
+         * non-native EFI
+         */
+
+        if (!efi_native)
+                goto out;
+
         /* Merge contiguous regions of the same type and attribute */
         for (p = memmap.map; p < memmap.map_end; p += memmap.desc_size) {
                 u64 prev_size;
@@ -677,7 +838,7 @@ void __init efi_enter_virtual_mode(void)
                 md->virt_addr = (u64) (unsigned long) va;
 
                 if (!va) {
-                        printk(KERN_ERR PFX "ioremap of 0x%llX failed!\n",
+                        pr_err("ioremap of 0x%llX failed!\n",
                                (unsigned long long)md->phys_addr);
                         continue;
                 }
@@ -711,8 +872,8 @@ void __init efi_enter_virtual_mode(void)
                 (efi_memory_desc_t *)__pa(new_memmap));
 
         if (status != EFI_SUCCESS) {
-                printk(KERN_ALERT "Unable to switch EFI into virtual mode "
-                       "(status=%lx)!\n", status);
+                pr_alert("Unable to switch EFI into virtual mode "
+                         "(status=%lx)!\n", status);
                 panic("EFI call to SetVirtualAddressMap() failed!");
         }
 
@@ -744,6 +905,8 @@ void __init efi_enter_virtual_mode(void)
         efi.query_capsule_caps = virt_efi_query_capsule_caps;
         if (__supported_pte_mask & _PAGE_NX)
                 runtime_code_page_mkexec();
+
+out:
         early_iounmap(memmap.map, memmap.nr_map * memmap.desc_size);
         memmap.map = NULL;
         kfree(new_memmap);
diff --git a/arch/x86/platform/geode/Makefile b/arch/x86/platform/geode/Makefile
index 07c9cd05021..246b788847f 100644
--- a/arch/x86/platform/geode/Makefile
+++ b/arch/x86/platform/geode/Makefile
@@ -1 +1,2 @@
 obj-$(CONFIG_ALIX)              += alix.o
+obj-$(CONFIG_NET5501)           += net5501.o
diff --git a/arch/x86/platform/geode/alix.c b/arch/x86/platform/geode/alix.c
index dc5f1d32ace..90e23e7679a 100644
--- a/arch/x86/platform/geode/alix.c
+++ b/arch/x86/platform/geode/alix.c
@@ -6,6 +6,7 @@
  *
  * Copyright (C) 2008 Constantin Baranov <const@mimas.ru>
  * Copyright (C) 2011 Ed Wildgoose <kernel@wildgooses.com>
+ *                and Philip Prindeville <philipp@redfish-solutions.com>
  *
  * TODO: There are large similarities with leds-net5501.c
  * by Alessandro Zummo <a.zummo@towertech.it>
@@ -24,14 +25,47 @@
 #include <linux/leds.h>
 #include <linux/platform_device.h>
 #include <linux/gpio.h>
+#include <linux/input.h>
+#include <linux/gpio_keys.h>
+#include <linux/dmi.h>
 
 #include <asm/geode.h>
 
+#define BIOS_SIGNATURE_TINYBIOS         0xf0000
+#define BIOS_SIGNATURE_COREBOOT         0x500
+#define BIOS_REGION_SIZE                0x10000
+
 static bool force = 0;
 module_param(force, bool, 0444);
 /* FIXME: Award bios is not automatically detected as Alix platform */
 MODULE_PARM_DESC(force, "Force detection as ALIX.2/ALIX.3 platform");
 
+static struct gpio_keys_button alix_gpio_buttons[] = {
+        {
+                .code                   = KEY_RESTART,
+                .gpio                   = 24,
+                .active_low             = 1,
+                .desc                   = "Reset button",
+                .type                   = EV_KEY,
+                .wakeup                 = 0,
+                .debounce_interval      = 100,
+                .can_disable            = 0,
+        }
+};
+static struct gpio_keys_platform_data alix_buttons_data = {
+        .buttons                        = alix_gpio_buttons,
+        .nbuttons                       = ARRAY_SIZE(alix_gpio_buttons),
+        .poll_interval                  = 20,
+};
+
+static struct platform_device alix_buttons_dev = {
+        .name                           = "gpio-keys-polled",
+        .id                             = 1,
+        .dev = {
+                .platform_data          = &alix_buttons_data,
+        }
+};
+
 static struct gpio_led alix_leds[] = {
         {
                 .name = "alix:1",
@@ -64,17 +98,22 @@ static struct platform_device alix_leds_dev = {
         .dev.platform_data = &alix_leds_data,
 };
 
+static struct __initdata platform_device *alix_devs[] = {
+        &alix_buttons_dev,
+        &alix_leds_dev,
+};
+
 static void __init register_alix(void)
 {
         /* Setup LED control through leds-gpio driver */
-        platform_device_register(&alix_leds_dev);
+        platform_add_devices(alix_devs, ARRAY_SIZE(alix_devs));
 }
 
-static int __init alix_present(unsigned long bios_phys,
+static bool __init alix_present(unsigned long bios_phys,
                                 const char *alix_sig,
                                 size_t alix_sig_len)
 {
-        const size_t bios_len = 0x00010000;
+        const size_t bios_len = BIOS_REGION_SIZE;
         const char *bios_virt;
         const char *scan_end;
         const char *p;
@@ -84,7 +123,7 @@ static int __init alix_present(unsigned long bios_phys,
                 printk(KERN_NOTICE "%s: forced to skip BIOS test, "
                        "assume system is ALIX.2/ALIX.3\n",
                        KBUILD_MODNAME);
-                return 1;
+                return true;
         }
 
         bios_virt = phys_to_virt(bios_phys);
@@ -109,15 +148,33 @@ static int __init alix_present(unsigned long bios_phys,
                         *a = '\0';
 
                 tail = p + alix_sig_len;
-                if ((tail[0] == '2' || tail[0] == '3')) {
+                if ((tail[0] == '2' || tail[0] == '3' || tail[0] == '6')) {
                         printk(KERN_INFO
                                "%s: system is recognized as \"%s\"\n",
                                KBUILD_MODNAME, name);
-                        return 1;
+                        return true;
                 }
         }
 
-        return 0;
+        return false;
+}
+
+static bool __init alix_present_dmi(void)
+{
+        const char *vendor, *product;
+
+        vendor = dmi_get_system_info(DMI_SYS_VENDOR);
+        if (!vendor || strcmp(vendor, "PC Engines"))
+                return false;
+
+        product = dmi_get_system_info(DMI_PRODUCT_NAME);
+        if (!product || (strcmp(product, "ALIX.2D") && strcmp(product, "ALIX.6")))
+                return false;
+
+        printk(KERN_INFO "%s: system is recognized as \"%s %s\"\n",
+               KBUILD_MODNAME, vendor, product);
+
+        return true;
 }
 
 static int __init alix_init(void)
@@ -128,8 +185,9 @@ static int __init alix_init(void)
         if (!is_geode())
                 return 0;
 
-        if (alix_present(0xf0000, tinybios_sig, sizeof(tinybios_sig) - 1) ||
-            alix_present(0x500, coreboot_sig, sizeof(coreboot_sig) - 1))
+        if (alix_present(BIOS_SIGNATURE_TINYBIOS, tinybios_sig, sizeof(tinybios_sig) - 1) ||
+            alix_present(BIOS_SIGNATURE_COREBOOT, coreboot_sig, sizeof(coreboot_sig) - 1) ||
+            alix_present_dmi())
                 register_alix();
 
         return 0;
diff --git a/arch/x86/platform/geode/net5501.c b/arch/x86/platform/geode/net5501.c
new file mode 100644
index 00000000000..66d377e334f
--- /dev/null
+++ b/arch/x86/platform/geode/net5501.c
@@ -0,0 +1,154 @@
+/*
+ * System Specific setup for Soekris net5501
+ * At the moment this means setup of GPIO control of LEDs and buttons
+ * on net5501 boards.
+ *
+ *
+ * Copyright (C) 2008-2009 Tower Technologies
+ * Written by Alessandro Zummo <a.zummo@towertech.it>
+ *
+ * Copyright (C) 2008 Constantin Baranov <const@mimas.ru>
+ * Copyright (C) 2011 Ed Wildgoose <kernel@wildgooses.com>
+ *                and Philip Prindeville <philipp@redfish-solutions.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/string.h>
+#include <linux/module.h>
+#include <linux/leds.h>
+#include <linux/platform_device.h>
+#include <linux/gpio.h>
+#include <linux/input.h>
+#include <linux/gpio_keys.h>
+
+#include <asm/geode.h>
+
+#define BIOS_REGION_BASE                0xffff0000
+#define BIOS_REGION_SIZE                0x00010000
+
+static struct gpio_keys_button net5501_gpio_buttons[] = {
+        {
+                .code = KEY_RESTART,
+                .gpio = 24,
+                .active_low = 1,
+                .desc = "Reset button",
+                .type = EV_KEY,
+                .wakeup = 0,
+                .debounce_interval = 100,
+                .can_disable = 0,
+        }
+};
+static struct gpio_keys_platform_data net5501_buttons_data = {
+        .buttons = net5501_gpio_buttons,
+        .nbuttons = ARRAY_SIZE(net5501_gpio_buttons),
+        .poll_interval = 20,
+};
+
+static struct platform_device net5501_buttons_dev = {
+        .name = "gpio-keys-polled",
+        .id = 1,
+        .dev = {
+                .platform_data = &net5501_buttons_data,
+        }
+};
+
+static struct gpio_led net5501_leds[] = {
+        {
+                .name = "net5501:1",
+                .gpio = 6,
+                .default_trigger = "default-on",
+                .active_low = 1,
+        },
+};
+
+static struct gpio_led_platform_data net5501_leds_data = {
+        .num_leds = ARRAY_SIZE(net5501_leds),
+        .leds = net5501_leds,
+};
+
+static struct platform_device net5501_leds_dev = {
+        .name = "leds-gpio",
+        .id = -1,
+        .dev.platform_data = &net5501_leds_data,
+};
+
+static struct __initdata platform_device *net5501_devs[] = {
+        &net5501_buttons_dev,
+        &net5501_leds_dev,
+};
+
+static void __init register_net5501(void)
+{
+        /* Setup LED control through leds-gpio driver */
+        platform_add_devices(net5501_devs, ARRAY_SIZE(net5501_devs));
+}
+
+struct net5501_board {
+        u16     offset;
+        u16     len;
+        char    *sig;
+};
+
+static struct net5501_board __initdata boards[] = {
+        { 0xb7b, 7, "net5501" },        /* net5501 v1.33/1.33c */
+        { 0xb1f, 7, "net5501" },        /* net5501 v1.32i */
+};
+
+static bool __init net5501_present(void)
+{
+        int i;
+        unsigned char *rombase, *bios;
+        bool found = false;
+
+        rombase = ioremap(BIOS_REGION_BASE, BIOS_REGION_SIZE - 1);
+        if (!rombase) {
+                printk(KERN_ERR "%s: failed to get rombase\n", KBUILD_MODNAME);
+                return found;
+        }
+
+        bios = rombase + 0x20;  /* null terminated */
+
+        if (memcmp(bios, "comBIOS", 7))
+                goto unmap;
+
+        for (i = 0; i < ARRAY_SIZE(boards); i++) {
+                unsigned char *model = rombase + boards[i].offset;
+
+                if (!memcmp(model, boards[i].sig, boards[i].len)) {
+                        printk(KERN_INFO "%s: system is recognized as \"%s\"\n",
+                               KBUILD_MODNAME, model);
+
+                        found = true;
+                        break;
+                }
+        }
+
+unmap:
+        iounmap(rombase);
+        return found;
+}
+
+static int __init net5501_init(void)
+{
+        if (!is_geode())
+                return 0;
+
+        if (!net5501_present())
+                return 0;
+
+        register_net5501();
+
+        return 0;
+}
+
+module_init(net5501_init);
+
+MODULE_AUTHOR("Philip Prindeville <philipp@redfish-solutions.com>");
+MODULE_DESCRIPTION("Soekris net5501 System Setup");
+MODULE_LICENSE("GPL");
diff --git a/arch/x86/platform/mrst/Makefile b/arch/x86/platform/mrst/Makefile
index 7baed5135e0..af1da7e623f 100644
--- a/arch/x86/platform/mrst/Makefile
+++ b/arch/x86/platform/mrst/Makefile
@@ -1,4 +1,3 @@
 obj-$(CONFIG_X86_INTEL_MID)     += mrst.o
 obj-$(CONFIG_X86_INTEL_MID)     += vrtc.o
 obj-$(CONFIG_EARLY_PRINTK_INTEL_MID)    += early_printk_mrst.o
-obj-$(CONFIG_X86_MRST)          += pmu.o
diff --git a/arch/x86/platform/mrst/mrst.c b/arch/x86/platform/mrst/mrst.c
index 475e2cd0f3c..e0a37233c0a 100644
--- a/arch/x86/platform/mrst/mrst.c
+++ b/arch/x86/platform/mrst/mrst.c
@@ -28,6 +28,8 @@
 #include <linux/module.h>
 #include <linux/notifier.h>
 #include <linux/mfd/intel_msic.h>
+#include <linux/gpio.h>
+#include <linux/i2c/tc35876x.h>
 
 #include <asm/setup.h>
 #include <asm/mpspec_def.h>
@@ -78,16 +80,11 @@ int sfi_mrtc_num;
 
 static void mrst_power_off(void)
 {
-        if (__mrst_cpu_chip == MRST_CPU_CHIP_LINCROFT)
-                intel_scu_ipc_simple_command(IPCMSG_COLD_RESET, 1);
 }
 
 static void mrst_reboot(void)
 {
-        if (__mrst_cpu_chip == MRST_CPU_CHIP_LINCROFT)
-                intel_scu_ipc_simple_command(IPCMSG_COLD_RESET, 0);
-        else
-                intel_scu_ipc_simple_command(IPCMSG_COLD_BOOT, 0);
+        intel_scu_ipc_simple_command(IPCMSG_COLD_BOOT, 0);
 }
 
 /* parse all the mtimer info to a static mtimer array */
@@ -200,34 +197,28 @@ int __init sfi_parse_mrtc(struct sfi_table_header *table)
 
 static unsigned long __init mrst_calibrate_tsc(void)
 {
-        unsigned long flags, fast_calibrate;
-        if (__mrst_cpu_chip == MRST_CPU_CHIP_PENWELL) {
-                u32 lo, hi, ratio, fsb;
-
-                rdmsr(MSR_IA32_PERF_STATUS, lo, hi);
-                pr_debug("IA32 perf status is 0x%x, 0x%0x\n", lo, hi);
-                ratio = (hi >> 8) & 0x1f;
-                pr_debug("ratio is %d\n", ratio);
-                if (!ratio) {
-                        pr_err("read a zero ratio, should be incorrect!\n");
-                        pr_err("force tsc ratio to 16 ...\n");
-                        ratio = 16;
-                }
-                rdmsr(MSR_FSB_FREQ, lo, hi);
-                if ((lo & 0x7) == 0x7)
-                        fsb = PENWELL_FSB_FREQ_83SKU;
-                else
-                        fsb = PENWELL_FSB_FREQ_100SKU;
-                fast_calibrate = ratio * fsb;
-                pr_debug("read penwell tsc %lu khz\n", fast_calibrate);
-                lapic_timer_frequency = fsb * 1000 / HZ;
-                /* mark tsc clocksource as reliable */
-                set_cpu_cap(&boot_cpu_data, X86_FEATURE_TSC_RELIABLE);
-        } else {
-                local_irq_save(flags);
-                fast_calibrate = apbt_quick_calibrate();
-                local_irq_restore(flags);
+        unsigned long fast_calibrate;
+        u32 lo, hi, ratio, fsb;
+
+        rdmsr(MSR_IA32_PERF_STATUS, lo, hi);
+        pr_debug("IA32 perf status is 0x%x, 0x%0x\n", lo, hi);
+        ratio = (hi >> 8) & 0x1f;
+        pr_debug("ratio is %d\n", ratio);
+        if (!ratio) {
+                pr_err("read a zero ratio, should be incorrect!\n");
+                pr_err("force tsc ratio to 16 ...\n");
+                ratio = 16;
         }
+        rdmsr(MSR_FSB_FREQ, lo, hi);
+        if ((lo & 0x7) == 0x7)
+                fsb = PENWELL_FSB_FREQ_83SKU;
+        else
+                fsb = PENWELL_FSB_FREQ_100SKU;
+        fast_calibrate = ratio * fsb;
+        pr_debug("read penwell tsc %lu khz\n", fast_calibrate);
+        lapic_timer_frequency = fsb * 1000 / HZ;
+        /* mark tsc clocksource as reliable */
+        set_cpu_cap(&boot_cpu_data, X86_FEATURE_TSC_RELIABLE);
         
         if (fast_calibrate)
                 return fast_calibrate;
@@ -261,16 +252,11 @@ static void __cpuinit mrst_arch_setup(void)
 {
         if (boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model == 0x27)
                 __mrst_cpu_chip = MRST_CPU_CHIP_PENWELL;
-        else if (boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model == 0x26)
-                __mrst_cpu_chip = MRST_CPU_CHIP_LINCROFT;
         else {
-                pr_err("Unknown Moorestown CPU (%d:%d), default to Lincroft\n",
+                pr_err("Unknown Intel MID CPU (%d:%d), default to Penwell\n",
                         boot_cpu_data.x86, boot_cpu_data.x86_model);
-                __mrst_cpu_chip = MRST_CPU_CHIP_LINCROFT;
+                __mrst_cpu_chip = MRST_CPU_CHIP_PENWELL;
         }
-        pr_debug("Moorestown CPU %s identified\n",
-                (__mrst_cpu_chip == MRST_CPU_CHIP_LINCROFT) ?
-                "Lincroft" : "Penwell");
 }
 
 /* MID systems don't have i8042 controller */
@@ -686,6 +672,24 @@ static void *msic_ocd_platform_data(void *info)
         return msic_generic_platform_data(info, INTEL_MSIC_BLOCK_OCD);
 }
 
+static void *msic_thermal_platform_data(void *info)
+{
+        return msic_generic_platform_data(info, INTEL_MSIC_BLOCK_THERMAL);
+}
+
+/* tc35876x DSI-LVDS bridge chip and panel platform data */
+static void *tc35876x_platform_data(void *data)
+{
+       static struct tc35876x_platform_data pdata;
+
+       /* gpio pins set to -1 will not be used by the driver */
+       pdata.gpio_bridge_reset = get_gpio_by_name("LCMB_RXEN");
+       pdata.gpio_panel_bl_en = get_gpio_by_name("6S6P_BL_EN");
+       pdata.gpio_panel_vadd = get_gpio_by_name("EN_VREG_LCD_V3P3");
+
+       return &pdata;
+}
+
 static const struct devs_id __initconst device_ids[] = {
         {"bma023", SFI_DEV_TYPE_I2C, 1, &no_platform_data},
         {"pmic_gpio", SFI_DEV_TYPE_SPI, 1, &pmic_gpio_platform_data},
@@ -698,6 +702,7 @@ static const struct devs_id __initconst device_ids[] = {
         {"i2c_accel", SFI_DEV_TYPE_I2C, 0, &lis331dl_platform_data},
         {"pmic_audio", SFI_DEV_TYPE_IPC, 1, &no_platform_data},
         {"mpu3050", SFI_DEV_TYPE_I2C, 1, &mpu3050_platform_data},
+        {"i2c_disp_brig", SFI_DEV_TYPE_I2C, 0, &tc35876x_platform_data},
 
         /* MSIC subdevices */
         {"msic_battery", SFI_DEV_TYPE_IPC, 1, &msic_battery_platform_data},
@@ -705,6 +710,7 @@ static const struct devs_id __initconst device_ids[] = {
         {"msic_audio", SFI_DEV_TYPE_IPC, 1, &msic_audio_platform_data},
         {"msic_power_btn", SFI_DEV_TYPE_IPC, 1, &msic_power_btn_platform_data},
         {"msic_ocd", SFI_DEV_TYPE_IPC, 1, &msic_ocd_platform_data},
+        {"msic_thermal", SFI_DEV_TYPE_IPC, 1, &msic_thermal_platform_data},
 
         {},
 };
diff --git a/arch/x86/platform/mrst/pmu.c b/arch/x86/platform/mrst/pmu.c
deleted file mode 100644
index c0ac06da57a..00000000000
--- a/arch/x86/platform/mrst/pmu.c
+++ /dev/null
@@ -1,817 +0,0 @@
-/*
- * mrst/pmu.c - driver for MRST Power Management Unit
- *
- * Copyright (c) 2011, Intel Corporation.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
- */
-
-#include <linux/cpuidle.h>
-#include <linux/debugfs.h>
-#include <linux/delay.h>
-#include <linux/interrupt.h>
-#include <linux/module.h>
-#include <linux/pci.h>
-#include <linux/seq_file.h>
-#include <linux/sfi.h>
-#include <asm/intel_scu_ipc.h>
-#include "pmu.h"
-
-#define IPCMSG_FW_REVISION      0xF4
-
-struct mrst_device {
-        u16 pci_dev_num;        /* DEBUG only */
-        u16 lss;
-        u16 latest_request;
-        unsigned int pci_state_counts[PCI_D3cold + 1]; /* DEBUG only */
-};
-
-/*
- * comlete list of MRST PCI devices
- */
-static struct mrst_device mrst_devs[] = {
-/*  0 */ { 0x0800, LSS_SPI0 },          /* Moorestown SPI Ctrl 0 */
-/*  1 */ { 0x0801, LSS_SPI1 },          /* Moorestown SPI Ctrl 1 */
-/*  2 */ { 0x0802, LSS_I2C0 },          /* Moorestown I2C 0 */
-/*  3 */ { 0x0803, LSS_I2C1 },          /* Moorestown I2C 1 */
-/*  4 */ { 0x0804, LSS_I2C2 },          /* Moorestown I2C 2 */
-/*  5 */ { 0x0805, LSS_KBD },           /* Moorestown Keyboard Ctrl */
-/*  6 */ { 0x0806, LSS_USB_HC },        /* Moorestown USB Ctrl */
-/*  7 */ { 0x0807, LSS_SD_HC0 },        /* Moorestown SD Host Ctrl 0 */
-/*  8 */ { 0x0808, LSS_SD_HC1 },        /* Moorestown SD Host Ctrl 1 */
-/*  9 */ { 0x0809, LSS_NAND },          /* Moorestown NAND Ctrl */
-/* 10 */ { 0x080a, LSS_AUDIO },         /* Moorestown Audio Ctrl */
-/* 11 */ { 0x080b, LSS_IMAGING },       /* Moorestown ISP */
-/* 12 */ { 0x080c, LSS_SECURITY },      /* Moorestown Security Controller */
-/* 13 */ { 0x080d, LSS_DISPLAY },       /* Moorestown External Displays */
-/* 14 */ { 0x080e, 0 },                 /* Moorestown SCU IPC */
-/* 15 */ { 0x080f, LSS_GPIO },          /* Moorestown GPIO Controller */
-/* 16 */ { 0x0810, 0 },                 /* Moorestown Power Management Unit */
-/* 17 */ { 0x0811, LSS_USB_OTG },       /* Moorestown OTG Ctrl */
-/* 18 */ { 0x0812, LSS_SPI2 },          /* Moorestown SPI Ctrl 2 */
-/* 19 */ { 0x0813, 0 },                 /* Moorestown SC DMA */
-/* 20 */ { 0x0814, LSS_AUDIO_LPE },     /* Moorestown LPE DMA */
-/* 21 */ { 0x0815, LSS_AUDIO_SSP },     /* Moorestown SSP0 */
-
-/* 22 */ { 0x084F, LSS_SD_HC2 },        /* Moorestown SD Host Ctrl 2 */
-
-/* 23 */ { 0x4102, 0 },                 /* Lincroft */
-/* 24 */ { 0x4110, 0 },                 /* Lincroft */
-};
-
-/* n.b. We ignore PCI-id 0x815 in LSS9 b/c Linux has no driver for it */
-static u16 mrst_lss9_pci_ids[] = {0x080a, 0x0814, 0};
-static u16 mrst_lss10_pci_ids[] = {0x0800, 0x0801, 0x0802, 0x0803,
-                                        0x0804, 0x0805, 0x080f, 0};
-
-/* handle concurrent SMP invokations of pmu_pci_set_power_state() */
-static spinlock_t mrst_pmu_power_state_lock;
-
-static unsigned int wake_counters[MRST_NUM_LSS];        /* DEBUG only */
-static unsigned int pmu_irq_stats[INT_INVALID + 1];     /* DEBUG only */
-
-static int graphics_is_off;
-static int lss_s0i3_enabled;
-static bool mrst_pmu_s0i3_enable;
-
-/*  debug counters */
-static u32 pmu_wait_ready_calls;
-static u32 pmu_wait_ready_udelays;
-static u32 pmu_wait_ready_udelays_max;
-static u32 pmu_wait_done_calls;
-static u32 pmu_wait_done_udelays;
-static u32 pmu_wait_done_udelays_max;
-static u32 pmu_set_power_state_entry;
-static u32 pmu_set_power_state_send_cmd;
-
-static struct mrst_device *pci_id_2_mrst_dev(u16 pci_dev_num)
-{
-        int index = 0;
-
-        if ((pci_dev_num >= 0x0800) && (pci_dev_num <= 0x815))
-                index = pci_dev_num - 0x800;
-        else if (pci_dev_num == 0x084F)
-                index = 22;
-        else if (pci_dev_num == 0x4102)
-                index = 23;
-        else if (pci_dev_num == 0x4110)
-                index = 24;
-
-        if (pci_dev_num != mrst_devs[index].pci_dev_num) {
-                WARN_ONCE(1, FW_BUG "Unknown PCI device 0x%04X\n", pci_dev_num);
-                return 0;
-        }
-
-        return &mrst_devs[index];
-}
-
-/**
- * mrst_pmu_validate_cstates
- * @dev: cpuidle_device
- *
- * Certain states are not appropriate for governor to pick in some cases.
- * This function will be called as cpuidle_device's prepare callback and
- * thus tells governor to ignore such states when selecting the next state
- * to enter.
- */
-
-#define IDLE_STATE4_IS_C6       4
-#define IDLE_STATE5_IS_S0I3     5
-
-int mrst_pmu_invalid_cstates(void)
-{
-        int cpu = smp_processor_id();
-
-        /*
-         * Demote to C4 if the PMU is busy.
-         * Since LSS changes leave the busy bit clear...
-         * busy means either the PMU is waiting for an ACK-C6 that
-         * isn't coming due to an MWAIT that returned immediately;
-         * or we returned from S0i3 successfully, and the PMU
-         * is not done sending us interrupts.
-         */
-        if (pmu_read_busy_status())
-                return 1 << IDLE_STATE4_IS_C6 | 1 << IDLE_STATE5_IS_S0I3;
-
-        /*
-         * Disallow S0i3 if: PMU is not initialized, or CPU1 is active,
-         * or if device LSS is insufficient, or the GPU is active,
-         * or if it has been explicitly disabled.
-         */
-        if (!pmu_reg || !cpumask_equal(cpu_online_mask, cpumask_of(cpu)) ||
-            !lss_s0i3_enabled || !graphics_is_off || !mrst_pmu_s0i3_enable)
-                return 1 << IDLE_STATE5_IS_S0I3;
-        else
-                return 0;
-}
-
-/*
- * pmu_update_wake_counters(): read PM_WKS, update wake_counters[]
- * DEBUG only.
- */
-static void pmu_update_wake_counters(void)
-{
-        int lss;
-        u32 wake_status;
-
-        wake_status = pmu_read_wks();
-
-        for (lss = 0; lss < MRST_NUM_LSS; ++lss) {
-                if (wake_status & (1 << lss))
-                        wake_counters[lss]++;
-        }
-}
-
-int mrst_pmu_s0i3_entry(void)
-{
-        int status;
-
-        /* Clear any possible error conditions */
-        pmu_write_ics(0x300);
-
-        /* set wake control to current D-states */
-        pmu_write_wssc(S0I3_SSS_TARGET);
-
-        status = mrst_s0i3_entry(PM_S0I3_COMMAND, &pmu_reg->pm_cmd);
-        pmu_update_wake_counters();
-        return status;
-}
-
-/* poll for maximum of 5ms for busy bit to clear */
-static int pmu_wait_ready(void)
-{
-        int udelays;
-
-        pmu_wait_ready_calls++;
-
-        for (udelays = 0; udelays < 500; ++udelays) {
-                if (udelays > pmu_wait_ready_udelays_max)
-                        pmu_wait_ready_udelays_max = udelays;
-
-                if (pmu_read_busy_status() == 0)
-                        return 0;
-
-                udelay(10);
-                pmu_wait_ready_udelays++;
-        }
-
-        /*
-         * if this fires, observe
-         * /sys/kernel/debug/mrst_pmu_wait_ready_calls
-         * /sys/kernel/debug/mrst_pmu_wait_ready_udelays
-         */
-        WARN_ONCE(1, "SCU not ready for 5ms");
-        return -EBUSY;
-}
-/* poll for maximum of 50ms us for busy bit to clear */
-static int pmu_wait_done(void)
-{
-        int udelays;
-
-        pmu_wait_done_calls++;
-
-        for (udelays = 0; udelays < 500; ++udelays) {
-                if (udelays > pmu_wait_done_udelays_max)
-                        pmu_wait_done_udelays_max = udelays;
-
-                if (pmu_read_busy_status() == 0)
-                        return 0;
-
-                udelay(100);
-                pmu_wait_done_udelays++;
-        }
-
-        /*
-         * if this fires, observe
-         * /sys/kernel/debug/mrst_pmu_wait_done_calls
-         * /sys/kernel/debug/mrst_pmu_wait_done_udelays
-         */
-        WARN_ONCE(1, "SCU not done for 50ms");
-        return -EBUSY;
-}
-
-u32 mrst_pmu_msi_is_disabled(void)
-{
-        return pmu_msi_is_disabled();
-}
-
-void mrst_pmu_enable_msi(void)
-{
-        pmu_msi_enable();
-}
-
-/**
- * pmu_irq - pmu driver interrupt handler
- * Context: interrupt context
- */
-static irqreturn_t pmu_irq(int irq, void *dummy)
-{
-        union pmu_pm_ics pmu_ics;
-
-        pmu_ics.value = pmu_read_ics();
-
-        if (!pmu_ics.bits.pending)
-                return IRQ_NONE;
-
-        switch (pmu_ics.bits.cause) {
-        case INT_SPURIOUS:
-        case INT_CMD_DONE:
-        case INT_CMD_ERR:
-        case INT_WAKE_RX:
-        case INT_SS_ERROR:
-        case INT_S0IX_MISS:
-        case INT_NO_ACKC6:
-                pmu_irq_stats[pmu_ics.bits.cause]++;
-                break;
-        default:
-                pmu_irq_stats[INT_INVALID]++;
-        }
-
-        pmu_write_ics(pmu_ics.value); /* Clear pending interrupt */
-
-        return IRQ_HANDLED;
-}
-
-/*
- * Translate PCI power management to MRST LSS D-states
- */
-static int pci_2_mrst_state(int lss, pci_power_t pci_state)
-{
-        switch (pci_state) {
-        case PCI_D0:
-                if (SSMSK(D0i1, lss) & D0I1_ACG_SSS_TARGET)
-                        return D0i1;
-                else
-                        return D0;
-        case PCI_D1:
-                return D0i1;
-        case PCI_D2:
-                return D0i2;
-        case PCI_D3hot:
-        case PCI_D3cold:
-                return D0i3;
-        default:
-                WARN(1, "pci_state %d\n", pci_state);
-                return 0;
-        }
-}
-
-static int pmu_issue_command(u32 pm_ssc)
-{
-        union pmu_pm_set_cfg_cmd_t command;
-
-        if (pmu_read_busy_status()) {
-                pr_debug("pmu is busy, Operation not permitted\n");
-                return -1;
-        }
-
-        /*
-         * enable interrupts in PMU so that interrupts are
-         * propagated when ioc bit for a particular set
-         * command is set
-         */
-
-        pmu_irq_enable();
-
-        /* Configure the sub systems for pmu2 */
-
-        pmu_write_ssc(pm_ssc);
-
-        /*
-         * Send the set config command for pmu its configured
-         * for mode CM_IMMEDIATE & hence with No Trigger
-         */
-
-        command.pmu2_params.d_param.cfg_mode = CM_IMMEDIATE;
-        command.pmu2_params.d_param.cfg_delay = 0;
-        command.pmu2_params.d_param.rsvd = 0;
-
-        /* construct the command to send SET_CFG to particular PMU */
-        command.pmu2_params.d_param.cmd = SET_CFG_CMD;
-        command.pmu2_params.d_param.ioc = 0;
-        command.pmu2_params.d_param.mode_id = 0;
-        command.pmu2_params.d_param.sys_state = SYS_STATE_S0I0;
-
-        /* write the value of PM_CMD into particular PMU */
-        pr_debug("pmu command being written %x\n",
-                        command.pmu_pm_set_cfg_cmd_value);
-
-        pmu_write_cmd(command.pmu_pm_set_cfg_cmd_value);
-
-        return 0;
-}
-
-static u16 pmu_min_lss_pci_req(u16 *ids, u16 pci_state)
-{
-        u16 existing_request;
-        int i;
-
-        for (i = 0; ids[i]; ++i) {
-                struct mrst_device *mrst_dev;
-
-                mrst_dev = pci_id_2_mrst_dev(ids[i]);
-                if (unlikely(!mrst_dev))
-                        continue;
-
-                existing_request = mrst_dev->latest_request;
-                if (existing_request < pci_state)
-                        pci_state = existing_request;
-        }
-        return pci_state;
-}
-
-/**
- * pmu_pci_set_power_state - Callback function is used by all the PCI devices
- *                      for a platform  specific device power on/shutdown.
- */
-
-int pmu_pci_set_power_state(struct pci_dev *pdev, pci_power_t pci_state)
-{
-        u32 old_sss, new_sss;
-        int status = 0;
-        struct mrst_device *mrst_dev;
-
-        pmu_set_power_state_entry++;
-
-        BUG_ON(pdev->vendor != PCI_VENDOR_ID_INTEL);
-        BUG_ON(pci_state < PCI_D0 || pci_state > PCI_D3cold);
-
-        mrst_dev = pci_id_2_mrst_dev(pdev->device);
-        if (unlikely(!mrst_dev))
-                return -ENODEV;
-
-        mrst_dev->pci_state_counts[pci_state]++;        /* count invocations */
-
-        /* PMU driver calls self as part of PCI initialization, ignore */
-        if (pdev->device == PCI_DEV_ID_MRST_PMU)
-                return 0;
-
-        BUG_ON(!pmu_reg); /* SW bug if called before initialized */
-
-        spin_lock(&mrst_pmu_power_state_lock);
-
-        if (pdev->d3_delay) {
-                dev_dbg(&pdev->dev, "d3_delay %d, should be 0\n",
-                        pdev->d3_delay);
-                pdev->d3_delay = 0;
-        }
-        /*
-         * If Lincroft graphics, simply remember state
-         */
-        if ((pdev->class >> 16) == PCI_BASE_CLASS_DISPLAY
-                && !((pdev->class & PCI_SUB_CLASS_MASK) >> 8)) {
-                if (pci_state == PCI_D0)
-                        graphics_is_off = 0;
-                else
-                        graphics_is_off = 1;
-                goto ret;
-        }
-
-        if (!mrst_dev->lss)
-                goto ret;       /* device with no LSS */
-
-        if (mrst_dev->latest_request == pci_state)
-                goto ret;       /* no change */
-
-        mrst_dev->latest_request = pci_state;   /* record latest request */
-
-        /*
-         * LSS9 and LSS10 contain multiple PCI devices.
-         * Use the lowest numbered (highest power) state in the LSS
-         */
-        if (mrst_dev->lss == 9)
-                pci_state = pmu_min_lss_pci_req(mrst_lss9_pci_ids, pci_state);
-        else if (mrst_dev->lss == 10)
-                pci_state = pmu_min_lss_pci_req(mrst_lss10_pci_ids, pci_state);
-
-        status = pmu_wait_ready();
-        if (status)
-                goto ret;
-
-        old_sss = pmu_read_sss();
-        new_sss = old_sss & ~SSMSK(3, mrst_dev->lss);
-        new_sss |= SSMSK(pci_2_mrst_state(mrst_dev->lss, pci_state),
-                        mrst_dev->lss);
-
-        if (new_sss == old_sss)
-                goto ret;       /* nothing to do */
-
-        pmu_set_power_state_send_cmd++;
-
-        status = pmu_issue_command(new_sss);
-
-        if (unlikely(status != 0)) {
-                dev_err(&pdev->dev, "Failed to Issue a PM command\n");
-                goto ret;
-        }
-
-        if (pmu_wait_done())
-                goto ret;
-
-        lss_s0i3_enabled =
-        ((pmu_read_sss() & S0I3_SSS_TARGET) == S0I3_SSS_TARGET);
-ret:
-        spin_unlock(&mrst_pmu_power_state_lock);
-        return status;
-}
-
-#ifdef CONFIG_DEBUG_FS
-static char *d0ix_names[] = {"D0", "D0i1", "D0i2", "D0i3"};
-
-static inline const char *d0ix_name(int state)
-{
-        return d0ix_names[(int) state];
-}
-
-static int debug_mrst_pmu_show(struct seq_file *s, void *unused)
-{
-        struct pci_dev *pdev = NULL;
-        u32 cur_pmsss;
-        int lss;
-
-        seq_printf(s, "0x%08X D0I1_ACG_SSS_TARGET\n", D0I1_ACG_SSS_TARGET);
-
-        cur_pmsss = pmu_read_sss();
-
-        seq_printf(s, "0x%08X S0I3_SSS_TARGET\n", S0I3_SSS_TARGET);
-
-        seq_printf(s, "0x%08X Current SSS ", cur_pmsss);
-        seq_printf(s, lss_s0i3_enabled ? "\n" : "[BLOCKS s0i3]\n");
-
-        if (cpumask_equal(cpu_online_mask, cpumask_of(0)))
-                seq_printf(s, "cpu0 is only cpu online\n");
-        else
-                seq_printf(s, "cpu0 is NOT only cpu online [BLOCKS S0i3]\n");
-
-        seq_printf(s, "GFX: %s\n", graphics_is_off ? "" : "[BLOCKS s0i3]");
-
-
-        for_each_pci_dev(pdev) {
-                int pos;
-                u16 pmcsr;
-                struct mrst_device *mrst_dev;
-                int i;
-
-                mrst_dev = pci_id_2_mrst_dev(pdev->device);
-
-                seq_printf(s, "%s %04x/%04X %-16.16s ",
-                        dev_name(&pdev->dev),
-                        pdev->vendor, pdev->device,
-                        dev_driver_string(&pdev->dev));
-
-                if (unlikely (!mrst_dev)) {
-                        seq_printf(s, " UNKNOWN\n");
-                        continue;
-                }
-
-                if (mrst_dev->lss)
-                        seq_printf(s, "LSS %2d %-4s ", mrst_dev->lss,
-                                d0ix_name(((cur_pmsss >>
-                                        (mrst_dev->lss * 2)) & 0x3)));
-                else
-                        seq_printf(s, "            ");
-
-                /* PCI PM config space setting */
-                pos = pci_find_capability(pdev, PCI_CAP_ID_PM);
-                if (pos != 0) {
-                        pci_read_config_word(pdev, pos + PCI_PM_CTRL, &pmcsr);
-                seq_printf(s, "PCI-%-4s",
-                        pci_power_name(pmcsr & PCI_PM_CTRL_STATE_MASK));
-                } else {
-                        seq_printf(s, "        ");
-                }
-
-                seq_printf(s, " %s ", pci_power_name(mrst_dev->latest_request));
-                for (i = 0; i <= PCI_D3cold; ++i)
-                        seq_printf(s, "%d ", mrst_dev->pci_state_counts[i]);
-
-                if (mrst_dev->lss) {
-                        unsigned int lssmask;
-
-                        lssmask = SSMSK(D0i3, mrst_dev->lss);
-
-                        if ((lssmask & S0I3_SSS_TARGET) &&
-                                ((lssmask & cur_pmsss) !=
-                                        (lssmask & S0I3_SSS_TARGET)))
-                                                seq_printf(s , "[BLOCKS s0i3]");
-                }
-
-                seq_printf(s, "\n");
-        }
-        seq_printf(s, "Wake Counters:\n");
-        for (lss = 0; lss < MRST_NUM_LSS; ++lss)
-                seq_printf(s, "LSS%d %d\n", lss, wake_counters[lss]);
-
-        seq_printf(s, "Interrupt Counters:\n");
-        seq_printf(s,
-                "INT_SPURIOUS \t%8u\n" "INT_CMD_DONE \t%8u\n"
-                "INT_CMD_ERR  \t%8u\n" "INT_WAKE_RX  \t%8u\n"
-                "INT_SS_ERROR \t%8u\n" "INT_S0IX_MISS\t%8u\n"
-                "INT_NO_ACKC6 \t%8u\n" "INT_INVALID  \t%8u\n",
-                pmu_irq_stats[INT_SPURIOUS], pmu_irq_stats[INT_CMD_DONE],
-                pmu_irq_stats[INT_CMD_ERR], pmu_irq_stats[INT_WAKE_RX],
-                pmu_irq_stats[INT_SS_ERROR], pmu_irq_stats[INT_S0IX_MISS],
-                pmu_irq_stats[INT_NO_ACKC6], pmu_irq_stats[INT_INVALID]);
-
-        seq_printf(s, "mrst_pmu_wait_ready_calls          %8d\n",
-                        pmu_wait_ready_calls);
-        seq_printf(s, "mrst_pmu_wait_ready_udelays        %8d\n",
-                        pmu_wait_ready_udelays);
-        seq_printf(s, "mrst_pmu_wait_ready_udelays_max    %8d\n",
-                        pmu_wait_ready_udelays_max);
-        seq_printf(s, "mrst_pmu_wait_done_calls           %8d\n",
-                        pmu_wait_done_calls);
-        seq_printf(s, "mrst_pmu_wait_done_udelays         %8d\n",
-                        pmu_wait_done_udelays);
-        seq_printf(s, "mrst_pmu_wait_done_udelays_max     %8d\n",
-                        pmu_wait_done_udelays_max);
-        seq_printf(s, "mrst_pmu_set_power_state_entry     %8d\n",
-                        pmu_set_power_state_entry);
-        seq_printf(s, "mrst_pmu_set_power_state_send_cmd  %8d\n",
-                        pmu_set_power_state_send_cmd);
-        seq_printf(s, "SCU busy: %d\n", pmu_read_busy_status());
-
-        return 0;
-}
-
-static int debug_mrst_pmu_open(struct inode *inode, struct file *file)
-{
-        return single_open(file, debug_mrst_pmu_show, NULL);
-}
-
-static const struct file_operations devices_state_operations = {
-        .open           = debug_mrst_pmu_open,
-        .read           = seq_read,
-        .llseek         = seq_lseek,
-        .release        = single_release,
-};
-#endif  /* DEBUG_FS */
-
-/*
- * Validate SCU PCI shim PCI vendor capability byte
- * against LSS hard-coded in mrst_devs[] above.
- * DEBUG only.
- */
-static void pmu_scu_firmware_debug(void)
-{
-        struct pci_dev *pdev = NULL;
-
-        for_each_pci_dev(pdev) {
-                struct mrst_device *mrst_dev;
-                u8 pci_config_lss;
-                int pos;
-
-                mrst_dev = pci_id_2_mrst_dev(pdev->device);
-                if (unlikely(!mrst_dev)) {
-                        printk(KERN_ERR FW_BUG "pmu: Unknown "
-                                "PCI device 0x%04X\n", pdev->device);
-                        continue;
-                }
-
-                if (mrst_dev->lss == 0)
-                        continue;        /* no LSS in our table */
-
-                pos = pci_find_capability(pdev, PCI_CAP_ID_VNDR);
-                if (!pos != 0) {
-                        printk(KERN_ERR FW_BUG "pmu: 0x%04X "
-                                "missing PCI Vendor Capability\n",
-                                pdev->device);
-                        continue;
-                }
-                pci_read_config_byte(pdev, pos + 4, &pci_config_lss);
-                if (!(pci_config_lss & PCI_VENDOR_CAP_LOG_SS_MASK)) {
-                        printk(KERN_ERR FW_BUG "pmu: 0x%04X "
-                                "invalid PCI Vendor Capability 0x%x "
-                                " expected LSS 0x%X\n",
-                                pdev->device, pci_config_lss, mrst_dev->lss);
-                        continue;
-                }
-                pci_config_lss &= PCI_VENDOR_CAP_LOG_ID_MASK;
-
-                if (mrst_dev->lss == pci_config_lss)
-                        continue;
-
-                printk(KERN_ERR FW_BUG "pmu: 0x%04X LSS = %d, expected %d\n",
-                        pdev->device, pci_config_lss, mrst_dev->lss);
-        }
-}
-
-/**
- * pmu_probe
- */
-static int __devinit pmu_probe(struct pci_dev *pdev,
-                                   const struct pci_device_id *pci_id)
-{
-        int ret;
-        struct mrst_pmu_reg *pmu;
-
-        /* Init the device */
-        ret = pci_enable_device(pdev);
-        if (ret) {
-                dev_err(&pdev->dev, "Unable to Enable PCI device\n");
-                return ret;
-        }
-
-        ret = pci_request_regions(pdev, MRST_PMU_DRV_NAME);
-        if (ret < 0) {
-                dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
-                goto out_err1;
-        }
-
-        /* Map the memory of PMU reg base */
-        pmu = pci_iomap(pdev, 0, 0);
-        if (!pmu) {
-                dev_err(&pdev->dev, "Unable to map the PMU address space\n");
-                ret = -ENOMEM;
-                goto out_err2;
-        }
-
-#ifdef CONFIG_DEBUG_FS
-        /* /sys/kernel/debug/mrst_pmu */
-        (void) debugfs_create_file("mrst_pmu", S_IFREG | S_IRUGO,
-                                NULL, NULL, &devices_state_operations);
-#endif
-        pmu_reg = pmu;  /* success */
-
-        if (request_irq(pdev->irq, pmu_irq, 0, MRST_PMU_DRV_NAME, NULL)) {
-                dev_err(&pdev->dev, "Registering isr has failed\n");
-                ret = -1;
-                goto out_err3;
-        }
-
-        pmu_scu_firmware_debug();
-
-        pmu_write_wkc(S0I3_WAKE_SOURCES);       /* Enable S0i3 wakeup sources */
-
-        pmu_wait_ready();
-
-        pmu_write_ssc(D0I1_ACG_SSS_TARGET);     /* Enable Auto-Clock_Gating */
-        pmu_write_cmd(0x201);
-
-        spin_lock_init(&mrst_pmu_power_state_lock);
-
-        /* Enable the hardware interrupt */
-        pmu_irq_enable();
-        return 0;
-
-out_err3:
-        free_irq(pdev->irq, NULL);
-        pci_iounmap(pdev, pmu_reg);
-        pmu_reg = NULL;
-out_err2:
-        pci_release_region(pdev, 0);
-out_err1:
-        pci_disable_device(pdev);
-        return ret;
-}
-
-static void __devexit pmu_remove(struct pci_dev *pdev)
-{
-        dev_err(&pdev->dev, "Mid PM pmu_remove called\n");
-
-        /* Freeing up the irq */
-        free_irq(pdev->irq, NULL);
-
-        pci_iounmap(pdev, pmu_reg);
-        pmu_reg = NULL;
-
-        /* disable the current PCI device */
-        pci_release_region(pdev, 0);
-        pci_disable_device(pdev);
-}
-
-static DEFINE_PCI_DEVICE_TABLE(pmu_pci_ids) = {
-        { PCI_VDEVICE(INTEL, PCI_DEV_ID_MRST_PMU), 0 },
-        { }
-};
-
-MODULE_DEVICE_TABLE(pci, pmu_pci_ids);
-
-static struct pci_driver driver = {
-        .name = MRST_PMU_DRV_NAME,
-        .id_table = pmu_pci_ids,
-        .probe = pmu_probe,
-        .remove = __devexit_p(pmu_remove),
-};
-
-/**
- * pmu_pci_register - register the PMU driver as PCI device
- */
-static int __init pmu_pci_register(void)
-{
-        return pci_register_driver(&driver);
-}
-
-/* Register and probe via fs_initcall() to preceed device_initcall() */
-fs_initcall(pmu_pci_register);
-
-static void __exit mid_pci_cleanup(void)
-{
-        pci_unregister_driver(&driver);
-}
-
-static int ia_major;
-static int ia_minor;
-
-static int pmu_sfi_parse_oem(struct sfi_table_header *table)
-{
-        struct sfi_table_simple *sb;
-
-        sb = (struct sfi_table_simple *)table;
-        ia_major = (sb->pentry[1] >> 0) & 0xFFFF;
-        ia_minor = (sb->pentry[1] >> 16) & 0xFFFF;
-        printk(KERN_INFO "mrst_pmu: IA FW version v%x.%x\n",
-                ia_major, ia_minor);
-
-        return 0;
-}
-
-static int __init scu_fw_check(void)
-{
-        int ret;
-        u32 fw_version;
-
-        if (!pmu_reg)
-                return 0;       /* this driver didn't probe-out */
-
-        sfi_table_parse("OEMB", NULL, NULL, pmu_sfi_parse_oem);
-
-        if (ia_major < 0x6005 || ia_minor < 0x1525) {
-                WARN(1, "mrst_pmu: IA FW version too old\n");
-                return -1;
-        }
-
-        ret = intel_scu_ipc_command(IPCMSG_FW_REVISION, 0, NULL, 0,
-                                        &fw_version, 1);
-
-        if (ret) {
-                WARN(1, "mrst_pmu: IPC FW version? %d\n", ret);
-        } else {
-                int scu_major = (fw_version >> 8) & 0xFF;
-                int scu_minor = (fw_version >> 0) & 0xFF;
-
-                printk(KERN_INFO "mrst_pmu: firmware v%x\n", fw_version);
-
-                if ((scu_major >= 0xC0) && (scu_minor >= 0x49)) {
-                        printk(KERN_INFO "mrst_pmu: enabling S0i3\n");
-                        mrst_pmu_s0i3_enable = true;
-                } else {
-                        WARN(1, "mrst_pmu: S0i3 disabled, old firmware %X.%X",
-                                        scu_major, scu_minor);
-                }
-        }
-        return 0;
-}
-late_initcall(scu_fw_check);
-module_exit(mid_pci_cleanup);
diff --git a/arch/x86/platform/mrst/pmu.h b/arch/x86/platform/mrst/pmu.h
deleted file mode 100644
index bfbfe64b167..00000000000
--- a/arch/x86/platform/mrst/pmu.h
+++ /dev/null
@@ -1,234 +0,0 @@
-/*
- * mrst/pmu.h - private definitions for MRST Power Management Unit mrst/pmu.c
- *
- * Copyright (c) 2011, Intel Corporation.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
- */
-
-#ifndef _MRST_PMU_H_
-#define _MRST_PMU_H_
-
-#define PCI_DEV_ID_MRST_PMU             0x0810
-#define MRST_PMU_DRV_NAME               "mrst_pmu"
-#define PCI_SUB_CLASS_MASK              0xFF00
-
-#define PCI_VENDOR_CAP_LOG_ID_MASK      0x7F
-#define PCI_VENDOR_CAP_LOG_SS_MASK      0x80
-
-#define SUB_SYS_ALL_D0I1        0x01155555
-#define S0I3_WAKE_SOURCES       0x00001FFF
-
-#define PM_S0I3_COMMAND                                 \
-        ((0 << 31) |    /* Reserved */                  \
-        (0 << 30) |     /* Core must be idle */         \
-        (0xc2 << 22) |  /* ACK C6 trigger */            \
-        (3 << 19) |     /* Trigger on DMI message */    \
-        (3 << 16) |     /* Enter S0i3 */                \
-        (0 << 13) |     /* Numeric mode ID (sw) */      \
-        (3 << 9) |      /* Trigger mode */              \
-        (0 << 8) |      /* Do not interrupt */          \
-        (1 << 0))       /* Set configuration */
-
-#define LSS_DMI         0
-#define LSS_SD_HC0      1
-#define LSS_SD_HC1      2
-#define LSS_NAND        3
-#define LSS_IMAGING     4
-#define LSS_SECURITY    5
-#define LSS_DISPLAY     6
-#define LSS_USB_HC      7
-#define LSS_USB_OTG     8
-#define LSS_AUDIO       9
-#define LSS_AUDIO_LPE   9
-#define LSS_AUDIO_SSP   9
-#define LSS_I2C0        10
-#define LSS_I2C1        10
-#define LSS_I2C2        10
-#define LSS_KBD         10
-#define LSS_SPI0        10
-#define LSS_SPI1        10
-#define LSS_SPI2        10
-#define LSS_GPIO        10
-#define LSS_SRAM        11      /* used by SCU, do not touch */
-#define LSS_SD_HC2      12
-/* LSS hardware bits 15,14,13 are hardwired to 0, thus unusable */
-#define MRST_NUM_LSS    13
-
-#define MIN(a, b) (((a) < (b)) ? (a) : (b))
-
-#define SSMSK(mask, lss) ((mask) << ((lss) * 2))
-#define D0      0
-#define D0i1    1
-#define D0i2    2
-#define D0i3    3
-
-#define S0I3_SSS_TARGET (               \
-        SSMSK(D0i1, LSS_DMI) |          \
-        SSMSK(D0i3, LSS_SD_HC0) |       \
-        SSMSK(D0i3, LSS_SD_HC1) |       \
-        SSMSK(D0i3, LSS_NAND) |         \
-        SSMSK(D0i3, LSS_SD_HC2) |       \
-        SSMSK(D0i3, LSS_IMAGING) |      \
-        SSMSK(D0i3, LSS_SECURITY) |     \
-        SSMSK(D0i3, LSS_DISPLAY) |      \
-        SSMSK(D0i3, LSS_USB_HC) |       \
-        SSMSK(D0i3, LSS_USB_OTG) |      \
-        SSMSK(D0i3, LSS_AUDIO) |        \
-        SSMSK(D0i1, LSS_I2C0))
-
-/*
- * D0i1 on Langwell is Autonomous Clock Gating (ACG).
- * Enable ACG on every LSS except camera and audio
- */
-#define D0I1_ACG_SSS_TARGET      \
-        (SUB_SYS_ALL_D0I1 & ~SSMSK(D0i1, LSS_IMAGING) & ~SSMSK(D0i1, LSS_AUDIO))
-
-enum cm_mode {
-        CM_NOP,                 /* ignore the config mode value */
-        CM_IMMEDIATE,
-        CM_DELAY,
-        CM_TRIGGER,
-        CM_INVALID
-};
-
-enum sys_state {
-        SYS_STATE_S0I0,
-        SYS_STATE_S0I1,
-        SYS_STATE_S0I2,
-        SYS_STATE_S0I3,
-        SYS_STATE_S3,
-        SYS_STATE_S5
-};
-
-#define SET_CFG_CMD     1
-
-enum int_status {
-        INT_SPURIOUS = 0,
-        INT_CMD_DONE = 1,
-        INT_CMD_ERR = 2,
-        INT_WAKE_RX = 3,
-        INT_SS_ERROR = 4,
-        INT_S0IX_MISS = 5,
-        INT_NO_ACKC6 = 6,
-        INT_INVALID = 7,
-};
-
-/* PMU register interface */
-static struct mrst_pmu_reg {
-        u32 pm_sts;             /* 0x00 */
-        u32 pm_cmd;             /* 0x04 */
-        u32 pm_ics;             /* 0x08 */
-        u32 _resv1;             /* 0x0C */
-        u32 pm_wkc[2];          /* 0x10 */
-        u32 pm_wks[2];          /* 0x18 */
-        u32 pm_ssc[4];          /* 0x20 */
-        u32 pm_sss[4];          /* 0x30 */
-        u32 pm_wssc[4];         /* 0x40 */
-        u32 pm_c3c4;            /* 0x50 */
-        u32 pm_c5c6;            /* 0x54 */
-        u32 pm_msi_disable;     /* 0x58 */
-} *pmu_reg;
-
-static inline u32 pmu_read_sts(void) { return readl(&pmu_reg->pm_sts); }
-static inline u32 pmu_read_ics(void) { return readl(&pmu_reg->pm_ics); }
-static inline u32 pmu_read_wks(void) { return readl(&pmu_reg->pm_wks[0]); }
-static inline u32 pmu_read_sss(void) { return readl(&pmu_reg->pm_sss[0]); }
-
-static inline void pmu_write_cmd(u32 arg) { writel(arg, &pmu_reg->pm_cmd); }
-static inline void pmu_write_ics(u32 arg) { writel(arg, &pmu_reg->pm_ics); }
-static inline void pmu_write_wkc(u32 arg) { writel(arg, &pmu_reg->pm_wkc[0]); }
-static inline void pmu_write_ssc(u32 arg) { writel(arg, &pmu_reg->pm_ssc[0]); }
-static inline void pmu_write_wssc(u32 arg)
-                                        { writel(arg, &pmu_reg->pm_wssc[0]); }
-
-static inline void pmu_msi_enable(void) { writel(0, &pmu_reg->pm_msi_disable); }
-static inline u32 pmu_msi_is_disabled(void)
-                                { return readl(&pmu_reg->pm_msi_disable); }
-
-union pmu_pm_ics {
-        struct {
-                u32 cause:8;
-                u32 enable:1;
-                u32 pending:1;
-                u32 reserved:22;
-        } bits;
-        u32 value;
-};
-
-static inline void pmu_irq_enable(void)
-{
-        union pmu_pm_ics pmu_ics;
-
-        pmu_ics.value = pmu_read_ics();
-        pmu_ics.bits.enable = 1;
-        pmu_write_ics(pmu_ics.value);
-}
-
-union pmu_pm_status {
-        struct {
-                u32 pmu_rev:8;
-                u32 pmu_busy:1;
-                u32 mode_id:4;
-                u32 Reserved:19;
-        } pmu_status_parts;
-        u32 pmu_status_value;
-};
-
-static inline int pmu_read_busy_status(void)
-{
-        union pmu_pm_status result;
-
-        result.pmu_status_value = pmu_read_sts();
-
-        return result.pmu_status_parts.pmu_busy;
-}
-
-/* pmu set config parameters */
-struct cfg_delay_param_t {
-        u32 cmd:8;
-        u32 ioc:1;
-        u32 cfg_mode:4;
-        u32 mode_id:3;
-        u32 sys_state:3;
-        u32 cfg_delay:8;
-        u32 rsvd:5;
-};
-
-struct cfg_trig_param_t {
-        u32 cmd:8;
-        u32 ioc:1;
-        u32 cfg_mode:4;
-        u32 mode_id:3;
-        u32 sys_state:3;
-        u32 cfg_trig_type:3;
-        u32 cfg_trig_val:8;
-        u32 cmbi:1;
-        u32 rsvd1:1;
-};
-
-union pmu_pm_set_cfg_cmd_t {
-        union {
-                struct cfg_delay_param_t d_param;
-                struct cfg_trig_param_t t_param;
-        } pmu2_params;
-        u32 pmu_pm_set_cfg_cmd_value;
-};
-
-#ifdef FUTURE_PATCH
-extern int mrst_s0i3_entry(u32 regval, u32 *regaddr);
-#else
-static inline int mrst_s0i3_entry(u32 regval, u32 *regaddr) { return -1; }
-#endif
-#endif
diff --git a/arch/x86/platform/olpc/olpc-xo15-sci.c b/arch/x86/platform/olpc/olpc-xo15-sci.c
index 2b235b77d9a..23e5b9d7977 100644
--- a/arch/x86/platform/olpc/olpc-xo15-sci.c
+++ b/arch/x86/platform/olpc/olpc-xo15-sci.c
@@ -23,7 +23,66 @@
 #define XO15_SCI_CLASS                  DRV_NAME
 #define XO15_SCI_DEVICE_NAME            "OLPC XO-1.5 SCI"
 
-static unsigned long xo15_sci_gpe;
+static unsigned long                    xo15_sci_gpe;
+static bool                             lid_wake_on_close;
+
+/*
+ * The normal ACPI LID wakeup behavior is wake-on-open, but not
+ * wake-on-close. This is implemented as standard by the XO-1.5 DSDT.
+ *
+ * We provide here a sysfs attribute that will additionally enable
+ * wake-on-close behavior. This is useful (e.g.) when we oportunistically
+ * suspend with the display running; if the lid is then closed, we want to
+ * wake up to turn the display off.
+ *
+ * This is controlled through a custom method in the XO-1.5 DSDT.
+ */
+static int set_lid_wake_behavior(bool wake_on_close)
+{
+        struct acpi_object_list arg_list;
+        union acpi_object arg;
+        acpi_status status;
+
+        arg_list.count          = 1;
+        arg_list.pointer        = &arg;
+        arg.type                = ACPI_TYPE_INTEGER;
+        arg.integer.value       = wake_on_close;
+
+        status = acpi_evaluate_object(NULL, "\\_SB.PCI0.LID.LIDW", &arg_list, NULL);
+        if (ACPI_FAILURE(status)) {
+                pr_warning(PFX "failed to set lid behavior\n");
+                return 1;
+        }
+
+        lid_wake_on_close = wake_on_close;
+
+        return 0;
+}
+
+static ssize_t
+lid_wake_on_close_show(struct kobject *s, struct kobj_attribute *attr, char *buf)
+{
+        return sprintf(buf, "%u\n", lid_wake_on_close);
+}
+
+static ssize_t lid_wake_on_close_store(struct kobject *s,
+                                       struct kobj_attribute *attr,
+                                       const char *buf, size_t n)
+{
+        unsigned int val;
+
+        if (sscanf(buf, "%u", &val) != 1)
+                return -EINVAL;
+
+        set_lid_wake_behavior(!!val);
+
+        return n;
+}
+
+static struct kobj_attribute lid_wake_on_close_attr =
+        __ATTR(lid_wake_on_close, 0644,
+               lid_wake_on_close_show,
+               lid_wake_on_close_store);
 
 static void battery_status_changed(void)
 {
@@ -91,6 +150,7 @@ static int xo15_sci_add(struct acpi_device *device)
 {
         unsigned long long tmp;
         acpi_status status;
+        int r;
 
         if (!device)
                 return -EINVAL;
@@ -112,6 +172,10 @@ static int xo15_sci_add(struct acpi_device *device)
 
         dev_info(&device->dev, "Initialized, GPE = 0x%lx\n", xo15_sci_gpe);
 
+        r = sysfs_create_file(&device->dev.kobj, &lid_wake_on_close_attr.attr);
+        if (r)
+                goto err_sysfs;
+
         /* Flush queue, and enable all SCI events */
         process_sci_queue();
         olpc_ec_mask_write(EC_SCI_SRC_ALL);
@@ -123,6 +187,11 @@ static int xo15_sci_add(struct acpi_device *device)
                 device_init_wakeup(&device->dev, true);
 
         return 0;
+
+err_sysfs:
+        acpi_remove_gpe_handler(NULL, xo15_sci_gpe, xo15_sci_gpe_handler);
+        cancel_work_sync(&sci_work);
+        return r;
 }
 
 static int xo15_sci_remove(struct acpi_device *device, int type)
@@ -130,6 +199,7 @@ static int xo15_sci_remove(struct acpi_device *device, int type)
         acpi_disable_gpe(NULL, xo15_sci_gpe);
         acpi_remove_gpe_handler(NULL, xo15_sci_gpe, xo15_sci_gpe_handler);
         cancel_work_sync(&sci_work);
+        sysfs_remove_file(&device->dev.kobj, &lid_wake_on_close_attr.attr);
         return 0;
 }
 
diff --git a/arch/x86/platform/uv/uv_time.c b/arch/x86/platform/uv/uv_time.c
index 9f29a01ee1b..5032e0d19b8 100644
--- a/arch/x86/platform/uv/uv_time.c
+++ b/arch/x86/platform/uv/uv_time.c
@@ -37,7 +37,7 @@ static void uv_rtc_timer_setup(enum clock_event_mode,
 
 static struct clocksource clocksource_uv = {
         .name           = RTC_NAME,
-        .rating         = 400,
+        .rating         = 299,
         .read           = uv_read_rtc,
         .mask           = (cycle_t)UVH_RTC_REAL_TIME_CLOCK_MASK,
         .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
@@ -379,10 +379,6 @@ static __init int uv_rtc_setup_clock(void)
         if (!is_uv_system())
                 return -ENODEV;
 
-        /* If single blade, prefer tsc */
-        if (uv_num_possible_blades() == 1)
-                clocksource_uv.rating = 250;
-
         rc = clocksource_register_hz(&clocksource_uv, sn_rtc_cycles_per_second);
         if (rc)
                 printk(KERN_INFO "UV RTC clocksource failed rc %d\n", rc);
diff --git a/arch/x86/power/cpu.c b/arch/x86/power/cpu.c
index f10c0afa1cb..4889655ba78 100644
--- a/arch/x86/power/cpu.c
+++ b/arch/x86/power/cpu.c
@@ -20,6 +20,7 @@
 #include <asm/xcr.h>
 #include <asm/suspend.h>
 #include <asm/debugreg.h>
+#include <asm/fpu-internal.h> /* pcntxt_mask */
 
 #ifdef CONFIG_X86_32
 static struct saved_context saved_context;
diff --git a/arch/x86/syscalls/syscall_32.tbl b/arch/x86/syscalls/syscall_32.tbl
index ce98e287c06..e7e67cc3c14 100644
--- a/arch/x86/syscalls/syscall_32.tbl
+++ b/arch/x86/syscalls/syscall_32.tbl
@@ -288,7 +288,7 @@
 279     i386    mq_timedsend            sys_mq_timedsend                compat_sys_mq_timedsend
 280     i386    mq_timedreceive         sys_mq_timedreceive             compat_sys_mq_timedreceive
 281     i386    mq_notify               sys_mq_notify                   compat_sys_mq_notify
-282     i386    mq_getsetaddr           sys_mq_getsetattr               compat_sys_mq_getsetattr
+282     i386    mq_getsetattr           sys_mq_getsetattr               compat_sys_mq_getsetattr
 283     i386    kexec_load              sys_kexec_load                  compat_sys_kexec_load
 284     i386    waitid                  sys_waitid                      compat_sys_waitid
 # 285 sys_setaltroot
diff --git a/arch/x86/um/mem_32.c b/arch/x86/um/mem_32.c
index 639900a6fde..f40281e5d6a 100644
--- a/arch/x86/um/mem_32.c
+++ b/arch/x86/um/mem_32.c
@@ -23,14 +23,6 @@ static int __init gate_vma_init(void)
         gate_vma.vm_flags = VM_READ | VM_MAYREAD | VM_EXEC | VM_MAYEXEC;
         gate_vma.vm_page_prot = __P101;
 
-        /*
-         * Make sure the vDSO gets into every core dump.
-         * Dumping its contents makes post-mortem fully interpretable later
-         * without matching up the same kernel and hardware config to see
-         * what PC values meant.
-         */
-        gate_vma.vm_flags |= VM_ALWAYSDUMP;
-
         return 0;
 }
 __initcall(gate_vma_init);
diff --git a/arch/x86/um/vdso/vma.c b/arch/x86/um/vdso/vma.c
index 91f4ec9a0a5..af91901babb 100644
--- a/arch/x86/um/vdso/vma.c
+++ b/arch/x86/um/vdso/vma.c
@@ -64,8 +64,7 @@ int arch_setup_additional_pages(struct linux_binprm *bprm, int uses_interp)
 
         err = install_special_mapping(mm, um_vdso_addr, PAGE_SIZE,
                 VM_READ|VM_EXEC|
-                VM_MAYREAD|VM_MAYWRITE|VM_MAYEXEC|
-                VM_ALWAYSDUMP,
+                VM_MAYREAD|VM_MAYWRITE|VM_MAYEXEC,
                 vdsop);
 
         up_write(&mm->mmap_sem);
diff --git a/arch/x86/vdso/vdso32-setup.c b/arch/x86/vdso/vdso32-setup.c
index 468d591dde3..a944020fa85 100644
--- a/arch/x86/vdso/vdso32-setup.c
+++ b/arch/x86/vdso/vdso32-setup.c
@@ -250,13 +250,7 @@ static int __init gate_vma_init(void)
         gate_vma.vm_end = FIXADDR_USER_END;
         gate_vma.vm_flags = VM_READ | VM_MAYREAD | VM_EXEC | VM_MAYEXEC;
         gate_vma.vm_page_prot = __P101;
-        /*
-         * Make sure the vDSO gets into every core dump.
-         * Dumping its contents makes post-mortem fully interpretable later
-         * without matching up the same kernel and hardware config to see
-         * what PC values meant.
-         */
-        gate_vma.vm_flags |= VM_ALWAYSDUMP;
+
         return 0;
 }
 
@@ -343,17 +337,10 @@ int arch_setup_additional_pages(struct linux_binprm *bprm, int uses_interp)
         if (compat_uses_vma || !compat) {
                 /*
                  * MAYWRITE to allow gdb to COW and set breakpoints
-                 *
-                 * Make sure the vDSO gets into every core dump.
-                 * Dumping its contents makes post-mortem fully
-                 * interpretable later without matching up the same
-                 * kernel and hardware config to see what PC values
-                 * meant.
                  */
                 ret = install_special_mapping(mm, addr, PAGE_SIZE,
                                               VM_READ|VM_EXEC|
-                                              VM_MAYREAD|VM_MAYWRITE|VM_MAYEXEC|
-                                              VM_ALWAYSDUMP,
+                                              VM_MAYREAD|VM_MAYWRITE|VM_MAYEXEC,
                                               vdso32_pages);
 
                 if (ret)
diff --git a/arch/x86/vdso/vma.c b/arch/x86/vdso/vma.c
index 153407c35b7..17e18279649 100644
--- a/arch/x86/vdso/vma.c
+++ b/arch/x86/vdso/vma.c
@@ -124,8 +124,7 @@ int arch_setup_additional_pages(struct linux_binprm *bprm, int uses_interp)
 
         ret = install_special_mapping(mm, addr, vdso_size,
                                       VM_READ|VM_EXEC|
-                                      VM_MAYREAD|VM_MAYWRITE|VM_MAYEXEC|
-                                      VM_ALWAYSDUMP,
+                                      VM_MAYREAD|VM_MAYWRITE|VM_MAYEXEC,
                                       vdso_pages);
         if (ret) {
                 current->mm->context.vdso = NULL;
diff --git a/arch/x86/xen/enlighten.c b/arch/x86/xen/enlighten.c
index 4172af8ceeb..b132ade26f7 100644
--- a/arch/x86/xen/enlighten.c
+++ b/arch/x86/xen/enlighten.c
@@ -62,6 +62,15 @@
 #include <asm/reboot.h>
 #include <asm/stackprotector.h>
 #include <asm/hypervisor.h>
+#include <asm/mwait.h>
+
+#ifdef CONFIG_ACPI
+#include <linux/acpi.h>
+#include <asm/acpi.h>
+#include <acpi/pdc_intel.h>
+#include <acpi/processor.h>
+#include <xen/interface/platform.h>
+#endif
 
 #include "xen-ops.h"
 #include "mmu.h"
@@ -200,13 +209,17 @@ static void __init xen_banner(void)
 static __read_mostly unsigned int cpuid_leaf1_edx_mask = ~0;
 static __read_mostly unsigned int cpuid_leaf1_ecx_mask = ~0;
 
+static __read_mostly unsigned int cpuid_leaf1_ecx_set_mask;
+static __read_mostly unsigned int cpuid_leaf5_ecx_val;
+static __read_mostly unsigned int cpuid_leaf5_edx_val;
+
 static void xen_cpuid(unsigned int *ax, unsigned int *bx,
                       unsigned int *cx, unsigned int *dx)
 {
         unsigned maskebx = ~0;
         unsigned maskecx = ~0;
         unsigned maskedx = ~0;
-
+        unsigned setecx = 0;
         /*
          * Mask out inconvenient features, to try and disable as many
          * unsupported kernel subsystems as possible.
@@ -214,9 +227,18 @@ static void xen_cpuid(unsigned int *ax, unsigned int *bx,
         switch (*ax) {
         case 1:
                 maskecx = cpuid_leaf1_ecx_mask;
+                setecx = cpuid_leaf1_ecx_set_mask;
                 maskedx = cpuid_leaf1_edx_mask;
                 break;
 
+        case CPUID_MWAIT_LEAF:
+                /* Synthesize the values.. */
+                *ax = 0;
+                *bx = 0;
+                *cx = cpuid_leaf5_ecx_val;
+                *dx = cpuid_leaf5_edx_val;
+                return;
+
         case 0xb:
                 /* Suppress extended topology stuff */
                 maskebx = 0;
@@ -232,9 +254,75 @@ static void xen_cpuid(unsigned int *ax, unsigned int *bx,
 
         *bx &= maskebx;
         *cx &= maskecx;
+        *cx |= setecx;
         *dx &= maskedx;
+
 }
 
+static bool __init xen_check_mwait(void)
+{
+#ifdef CONFIG_ACPI
+        struct xen_platform_op op = {
+                .cmd                    = XENPF_set_processor_pminfo,
+                .u.set_pminfo.id        = -1,
+                .u.set_pminfo.type      = XEN_PM_PDC,
+        };
+        uint32_t buf[3];
+        unsigned int ax, bx, cx, dx;
+        unsigned int mwait_mask;
+
+        /* We need to determine whether it is OK to expose the MWAIT
+         * capability to the kernel to harvest deeper than C3 states from ACPI
+         * _CST using the processor_harvest_xen.c module. For this to work, we
+         * need to gather the MWAIT_LEAF values (which the cstate.c code
+         * checks against). The hypervisor won't expose the MWAIT flag because
+         * it would break backwards compatibility; so we will find out directly
+         * from the hardware and hypercall.
+         */
+        if (!xen_initial_domain())
+                return false;
+
+        ax = 1;
+        cx = 0;
+
+        native_cpuid(&ax, &bx, &cx, &dx);
+
+        mwait_mask = (1 << (X86_FEATURE_EST % 32)) |
+                     (1 << (X86_FEATURE_MWAIT % 32));
+
+        if ((cx & mwait_mask) != mwait_mask)
+                return false;
+
+        /* We need to emulate the MWAIT_LEAF and for that we need both
+         * ecx and edx. The hypercall provides only partial information.
+         */
+
+        ax = CPUID_MWAIT_LEAF;
+        bx = 0;
+        cx = 0;
+        dx = 0;
+
+        native_cpuid(&ax, &bx, &cx, &dx);
+
+        /* Ask the Hypervisor whether to clear ACPI_PDC_C_C2C3_FFH. If so,
+         * don't expose MWAIT_LEAF and let ACPI pick the IOPORT version of C3.
+         */
+        buf[0] = ACPI_PDC_REVISION_ID;
+        buf[1] = 1;
+        buf[2] = (ACPI_PDC_C_CAPABILITY_SMP | ACPI_PDC_EST_CAPABILITY_SWSMP);
+
+        set_xen_guest_handle(op.u.set_pminfo.pdc, buf);
+
+        if ((HYPERVISOR_dom0_op(&op) == 0) &&
+            (buf[2] & (ACPI_PDC_C_C1_FFH | ACPI_PDC_C_C2C3_FFH))) {
+                cpuid_leaf5_ecx_val = cx;
+                cpuid_leaf5_edx_val = dx;
+        }
+        return true;
+#else
+        return false;
+#endif
+}
 static void __init xen_init_cpuid_mask(void)
 {
         unsigned int ax, bx, cx, dx;
@@ -261,6 +349,9 @@ static void __init xen_init_cpuid_mask(void)
         /* Xen will set CR4.OSXSAVE if supported and not disabled by force */
         if ((cx & xsave_mask) != xsave_mask)
                 cpuid_leaf1_ecx_mask &= ~xsave_mask; /* disable XSAVE & OSXSAVE */
+
+        if (xen_check_mwait())
+                cpuid_leaf1_ecx_set_mask = (1 << (X86_FEATURE_MWAIT % 32));
 }
 
 static void xen_set_debugreg(int reg, unsigned long val)
@@ -777,11 +868,11 @@ static DEFINE_PER_CPU(unsigned long, xen_cr0_value);
 
 static unsigned long xen_read_cr0(void)
 {
-        unsigned long cr0 = percpu_read(xen_cr0_value);
+        unsigned long cr0 = this_cpu_read(xen_cr0_value);
 
         if (unlikely(cr0 == 0)) {
                 cr0 = native_read_cr0();
-                percpu_write(xen_cr0_value, cr0);
+                this_cpu_write(xen_cr0_value, cr0);
         }
 
         return cr0;
@@ -791,7 +882,7 @@ static void xen_write_cr0(unsigned long cr0)
 {
         struct multicall_space mcs;
 
-        percpu_write(xen_cr0_value, cr0);
+        this_cpu_write(xen_cr0_value, cr0);
 
         /* Only pay attention to cr0.TS; everything else is
            ignored. */
diff --git a/arch/x86/xen/irq.c b/arch/x86/xen/irq.c
index 8bbb465b6f0..15733765797 100644
--- a/arch/x86/xen/irq.c
+++ b/arch/x86/xen/irq.c
@@ -26,7 +26,7 @@ static unsigned long xen_save_fl(void)
         struct vcpu_info *vcpu;
         unsigned long flags;
 
-        vcpu = percpu_read(xen_vcpu);
+        vcpu = this_cpu_read(xen_vcpu);
 
         /* flag has opposite sense of mask */
         flags = !vcpu->evtchn_upcall_mask;
@@ -50,7 +50,7 @@ static void xen_restore_fl(unsigned long flags)
            make sure we're don't switch CPUs between getting the vcpu
            pointer and updating the mask. */
         preempt_disable();
-        vcpu = percpu_read(xen_vcpu);
+        vcpu = this_cpu_read(xen_vcpu);
         vcpu->evtchn_upcall_mask = flags;
         preempt_enable_no_resched();
 
@@ -72,7 +72,7 @@ static void xen_irq_disable(void)
            make sure we're don't switch CPUs between getting the vcpu
            pointer and updating the mask. */
         preempt_disable();
-        percpu_read(xen_vcpu)->evtchn_upcall_mask = 1;
+        this_cpu_read(xen_vcpu)->evtchn_upcall_mask = 1;
         preempt_enable_no_resched();
 }
 PV_CALLEE_SAVE_REGS_THUNK(xen_irq_disable);
@@ -86,7 +86,7 @@ static void xen_irq_enable(void)
            the caller is confused and is trying to re-enable interrupts
            on an indeterminate processor. */
 
-        vcpu = percpu_read(xen_vcpu);
+        vcpu = this_cpu_read(xen_vcpu);
         vcpu->evtchn_upcall_mask = 0;
 
         /* Doesn't matter if we get preempted here, because any
diff --git a/arch/x86/xen/mmu.c b/arch/x86/xen/mmu.c
index 95c1cf60c66..988828b479e 100644
--- a/arch/x86/xen/mmu.c
+++ b/arch/x86/xen/mmu.c
@@ -1071,14 +1071,14 @@ static void drop_other_mm_ref(void *info)
         struct mm_struct *mm = info;
         struct mm_struct *active_mm;
 
-        active_mm = percpu_read(cpu_tlbstate.active_mm);
+        active_mm = this_cpu_read(cpu_tlbstate.active_mm);
 
-        if (active_mm == mm && percpu_read(cpu_tlbstate.state) != TLBSTATE_OK)
+        if (active_mm == mm && this_cpu_read(cpu_tlbstate.state) != TLBSTATE_OK)
                 leave_mm(smp_processor_id());
 
         /* If this cpu still has a stale cr3 reference, then make sure
            it has been flushed. */
-        if (percpu_read(xen_current_cr3) == __pa(mm->pgd))
+        if (this_cpu_read(xen_current_cr3) == __pa(mm->pgd))
                 load_cr3(swapper_pg_dir);
 }
 
@@ -1185,17 +1185,17 @@ static void __init xen_pagetable_setup_done(pgd_t *base)
 
 static void xen_write_cr2(unsigned long cr2)
 {
-        percpu_read(xen_vcpu)->arch.cr2 = cr2;
+        this_cpu_read(xen_vcpu)->arch.cr2 = cr2;
 }
 
 static unsigned long xen_read_cr2(void)
 {
-        return percpu_read(xen_vcpu)->arch.cr2;
+        return this_cpu_read(xen_vcpu)->arch.cr2;
 }
 
 unsigned long xen_read_cr2_direct(void)
 {
-        return percpu_read(xen_vcpu_info.arch.cr2);
+        return this_cpu_read(xen_vcpu_info.arch.cr2);
 }
 
 static void xen_flush_tlb(void)
@@ -1278,12 +1278,12 @@ static void xen_flush_tlb_others(const struct cpumask *cpus,
 
 static unsigned long xen_read_cr3(void)
 {
-        return percpu_read(xen_cr3);
+        return this_cpu_read(xen_cr3);
 }
 
 static void set_current_cr3(void *v)
 {
-        percpu_write(xen_current_cr3, (unsigned long)v);
+        this_cpu_write(xen_current_cr3, (unsigned long)v);
 }
 
 static void __xen_write_cr3(bool kernel, unsigned long cr3)
@@ -1306,7 +1306,7 @@ static void __xen_write_cr3(bool kernel, unsigned long cr3)
         xen_extend_mmuext_op(&op);
 
         if (kernel) {
-                percpu_write(xen_cr3, cr3);
+                this_cpu_write(xen_cr3, cr3);
 
                 /* Update xen_current_cr3 once the batch has actually
                    been submitted. */
@@ -1322,7 +1322,7 @@ static void xen_write_cr3(unsigned long cr3)
 
         /* Update while interrupts are disabled, so its atomic with
            respect to ipis */
-        percpu_write(xen_cr3, cr3);
+        this_cpu_write(xen_cr3, cr3);
 
         __xen_write_cr3(true, cr3);
 
diff --git a/arch/x86/xen/multicalls.h b/arch/x86/xen/multicalls.h
index dee79b78a90..9c2e74f9096 100644
--- a/arch/x86/xen/multicalls.h
+++ b/arch/x86/xen/multicalls.h
@@ -47,7 +47,7 @@ static inline void xen_mc_issue(unsigned mode)
                 xen_mc_flush();
 
         /* restore flags saved in xen_mc_batch */
-        local_irq_restore(percpu_read(xen_mc_irq_flags));
+        local_irq_restore(this_cpu_read(xen_mc_irq_flags));
 }
 
 /* Set up a callback to be called when the current batch is flushed */
diff --git a/arch/x86/xen/setup.c b/arch/x86/xen/setup.c
index e03c6369217..1ba8dff2675 100644
--- a/arch/x86/xen/setup.c
+++ b/arch/x86/xen/setup.c
@@ -10,6 +10,7 @@
 #include <linux/pm.h>
 #include <linux/memblock.h>
 #include <linux/cpuidle.h>
+#include <linux/cpufreq.h>
 
 #include <asm/elf.h>
 #include <asm/vdso.h>
@@ -420,7 +421,7 @@ void __init xen_arch_setup(void)
         boot_cpu_data.hlt_works_ok = 1;
 #endif
         disable_cpuidle();
-        boot_option_idle_override = IDLE_HALT;
+        disable_cpufreq();
         WARN_ON(set_pm_idle_to_default());
         fiddle_vdso();
 }
diff --git a/arch/x86/xen/smp.c b/arch/x86/xen/smp.c
index 501d4e0244b..02900e8ce26 100644
--- a/arch/x86/xen/smp.c
+++ b/arch/x86/xen/smp.c
@@ -75,8 +75,14 @@ static void __cpuinit cpu_bringup(void)
 
         xen_setup_cpu_clockevents();
 
+        notify_cpu_starting(cpu);
+
+        ipi_call_lock();
         set_cpu_online(cpu, true);
-        percpu_write(cpu_state, CPU_ONLINE);
+        ipi_call_unlock();
+
+        this_cpu_write(cpu_state, CPU_ONLINE);
+
         wmb();
 
         /* We can take interrupts now: we're officially "up". */
diff --git a/arch/xtensa/include/asm/mman.h b/arch/xtensa/include/asm/mman.h
index 30789010733..25bc6c1309c 100644
--- a/arch/xtensa/include/asm/mman.h
+++ b/arch/xtensa/include/asm/mman.h
@@ -86,6 +86,10 @@
 #define MADV_HUGEPAGE   14              /* Worth backing with hugepages */
 #define MADV_NOHUGEPAGE 15              /* Not worth backing with hugepages */
 
+#define MADV_DONTDUMP   16              /* Explicity exclude from the core dump,
+                                           overrides the coredump filter bits */
+#define MADV_DODUMP     17              /* Clear the MADV_NODUMP flag */
+
 /* compatibility flags */
 #define MAP_FILE        0
 
diff --git a/arch/xtensa/kernel/pci.c b/arch/xtensa/kernel/pci.c
index 61045c192e8..eb30e356f5b 100644
--- a/arch/xtensa/kernel/pci.c
+++ b/arch/xtensa/kernel/pci.c
@@ -153,7 +153,7 @@ static void __init pci_controller_apertures(struct pci_controller *pci_ctrl,
         }
         res->start += io_offset;
         res->end += io_offset;
-        pci_add_resource(resources, res);
+        pci_add_resource_offset(resources, res, io_offset);
 
         for (i = 0; i < 3; i++) {
                 res = &pci_ctrl->mem_resources[i];
@@ -200,24 +200,9 @@ subsys_initcall(pcibios_init);
 
 void __init pcibios_fixup_bus(struct pci_bus *bus)
 {
-        struct pci_controller *pci_ctrl = bus->sysdata;
-        struct resource *res;
-        unsigned long io_offset;
-        int i;
-
-        io_offset = (unsigned long)pci_ctrl->io_space.base;
         if (bus->parent) {
                 /* This is a subordinate bridge */
                 pci_read_bridge_bases(bus);
-
-                for (i = 0; i < 4; i++) {
-                        if ((res = bus->resource[i]) == NULL || !res->flags)
-                                continue;
-                        if (io_offset && (res->flags & IORESOURCE_IO)) {
-                                res->start += io_offset;
-                                res->end += io_offset;
-                        }
-                }
         }
 }
 
diff --git a/arch/xtensa/kernel/signal.c b/arch/xtensa/kernel/signal.c
index f2220b5bdce..b69b000349f 100644
--- a/arch/xtensa/kernel/signal.c
+++ b/arch/xtensa/kernel/signal.c
@@ -260,10 +260,7 @@ asmlinkage long xtensa_rt_sigreturn(long a0, long a1, long a2, long a3,
                 goto badframe;
 
         sigdelsetmask(&set, ~_BLOCKABLE);
-        spin_lock_irq(&current->sighand->siglock);
-        current->blocked = set;
-        recalc_sigpending();
-        spin_unlock_irq(&current->sighand->siglock);
+        set_current_blocked(&set);
 
         if (restore_sigcontext(regs, frame))
                 goto badframe;
@@ -336,8 +333,8 @@ gen_return_code(unsigned char *codemem)
 }
 
 
-static void setup_frame(int sig, struct k_sigaction *ka, siginfo_t *info,
-                        sigset_t *set, struct pt_regs *regs)
+static int setup_frame(int sig, struct k_sigaction *ka, siginfo_t *info,
+                       sigset_t *set, struct pt_regs *regs)
 {
         struct rt_sigframe *frame;
         int err = 0;
@@ -422,12 +419,11 @@ static void setup_frame(int sig, struct k_sigaction *ka, siginfo_t *info,
                 current->comm, current->pid, signal, frame, regs->pc);
 #endif
 
-        return;
+        return 0;
 
 give_sigsegv:
-        if (sig == SIGSEGV)
-                ka->sa.sa_handler = SIG_DFL;
-        force_sig(SIGSEGV, current);
+        force_sigsegv(sig, current);
+        return -EFAULT;
 }
 
 /*
@@ -449,11 +445,8 @@ asmlinkage long xtensa_rt_sigsuspend(sigset_t __user *unewset,
                 return -EFAULT;
 
         sigdelsetmask(&newset, ~_BLOCKABLE);
-        spin_lock_irq(&current->sighand->siglock);
         saveset = current->blocked;
-        current->blocked = newset;
-        recalc_sigpending();
-        spin_unlock_irq(&current->sighand->siglock);
+        set_current_blocked(&newset);
 
         regs->areg[2] = -EINTR;
         while (1) {
@@ -536,17 +529,11 @@ int do_signal(struct pt_regs *regs, sigset_t *oldset)
 
                 /* Whee!  Actually deliver the signal.  */
                 /* Set up the stack frame */
-                setup_frame(signr, &ka, &info, oldset, regs);
-
-                if (ka.sa.sa_flags & SA_ONESHOT)
-                        ka.sa.sa_handler = SIG_DFL;
+                ret = setup_frame(signr, &ka, &info, oldset, regs);
+                if (ret)
+                        return ret;
 
-                spin_lock_irq(&current->sighand->siglock);
-                sigorsets(&current->blocked, &current->blocked, &ka.sa.sa_mask);
-                if (!(ka.sa.sa_flags & SA_NODEFER))
-                        sigaddset(&current->blocked, signr);
-                recalc_sigpending();
-                spin_unlock_irq(&current->sighand->siglock);
+                block_sigmask(&ka, signr);
                 if (current->ptrace & PT_SINGLESTEP)
                         task_pt_regs(current)->icountlevel = 1;