210 files changed, 3892 insertions, 7724 deletions

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 43449305961..7275009686e 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -469,7 +469,7 @@ config ARCH_IXP4XX
 
 config ARCH_DOVE
         bool "Marvell Dove"
-        select CPU_V6K
+        select CPU_V7
         select PCI
         select ARCH_REQUIRE_GPIOLIB
         select GENERIC_CLOCKEVENTS
@@ -850,6 +850,7 @@ config ARCH_DAVINCI
         select HAVE_IDE
         select CLKDEV_LOOKUP
         select GENERIC_ALLOCATOR
+        select GENERIC_IRQ_CHIP
         select ARCH_HAS_HOLES_MEMORYMODEL
         help
           Support for TI's DaVinci platform.
@@ -1027,6 +1028,7 @@ config PLAT_IOP
 config PLAT_ORION
         bool
         select CLKSRC_MMIO
+        select GENERIC_IRQ_CHIP
         select HAVE_SCHED_CLOCK
 
 config PLAT_PXA
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 458a0151667..25750bcb339 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -158,9 +158,8 @@ machine-$(CONFIG_ARCH_MV78XX0)		:= mv78xx0
 machine-$(CONFIG_ARCH_MX1)              := imx
 machine-$(CONFIG_ARCH_MX2)              := imx
 machine-$(CONFIG_ARCH_MX25)             := imx
-machine-$(CONFIG_ARCH_MX3)              := mx3
+machine-$(CONFIG_ARCH_MX3)              := imx
 machine-$(CONFIG_ARCH_MX5)              := mx5
-machine-$(CONFIG_ARCH_MXC91231)         := mxc91231
 machine-$(CONFIG_ARCH_MXS)              := mxs
 machine-$(CONFIG_ARCH_NETX)             := netx
 machine-$(CONFIG_ARCH_NOMADIK)          := nomadik
diff --git a/arch/arm/boot/compressed/Makefile b/arch/arm/boot/compressed/Makefile
index 0c6852d9350..23aad072230 100644
--- a/arch/arm/boot/compressed/Makefile
+++ b/arch/arm/boot/compressed/Makefile
@@ -98,8 +98,6 @@ endif
 ccflags-y := -fpic -fno-builtin
 asflags-y := -Wa,-march=all
 
-# Provide size of uncompressed kernel to the decompressor via a linker symbol.
-LDFLAGS_vmlinux = --defsym _image_size=$(shell stat -c "%s" $(obj)/../Image)
 # Supply ZRELADDR to the decompressor via a linker symbol.
 ifneq ($(CONFIG_AUTO_ZRELADDR),y)
 LDFLAGS_vmlinux += --defsym zreladdr=$(ZRELADDR)
@@ -122,10 +120,23 @@ lib1funcs = $(obj)/lib1funcs.o
 $(obj)/lib1funcs.S: $(srctree)/arch/$(SRCARCH)/lib/lib1funcs.S FORCE
         $(call cmd,shipped)
 
+# We need to prevent any GOTOFF relocs being used with references
+# to symbols in the .bss section since we cannot relocate them
+# independently from the rest at run time.  This can be achieved by
+# ensuring that no private .bss symbols exist, as global symbols
+# always have a GOT entry which is what we need.
+# The .data section is already discarded by the linker script so no need
+# to bother about it here.
+check_for_bad_syms = \
+bad_syms=$$($(CROSS_COMPILE)nm $@ | sed -n 's/^.\{8\} [bc] \(.*\)/\1/p') && \
+[ -z "$$bad_syms" ] || \
+  ( echo "following symbols must have non local/private scope:" >&2; \
+    echo "$$bad_syms" >&2; rm -f $@; false )
+
 $(obj)/vmlinux: $(obj)/vmlinux.lds $(obj)/$(HEAD) $(obj)/piggy.$(suffix_y).o \
                 $(addprefix $(obj)/, $(OBJS)) $(lib1funcs) FORCE
         $(call if_changed,ld)
-        @:
+        @$(check_for_bad_syms)
 
 $(obj)/piggy.$(suffix_y): $(obj)/../Image FORCE
         $(call if_changed,$(suffix_y))
diff --git a/arch/arm/boot/compressed/decompress.c b/arch/arm/boot/compressed/decompress.c
index 4c72a97bc3e..07be5a2f830 100644
--- a/arch/arm/boot/compressed/decompress.c
+++ b/arch/arm/boot/compressed/decompress.c
@@ -44,7 +44,7 @@ extern void error(char *);
 #include "../../../../lib/decompress_unlzma.c"
 #endif
 
-void do_decompress(u8 *input, int len, u8 *output, void (*error)(char *x))
+int do_decompress(u8 *input, int len, u8 *output, void (*error)(char *x))
 {
-        decompress(input, len, NULL, NULL, output, NULL, error);
+        return decompress(input, len, NULL, NULL, output, NULL, error);
 }
diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S
index 6fdf4abb718..f9da41921c5 100644
--- a/arch/arm/boot/compressed/head.S
+++ b/arch/arm/boot/compressed/head.S
@@ -179,7 +179,7 @@ not_angel:
                 bl      cache_on
 
 restart:        adr     r0, LC0
-                ldmia   r0, {r1, r2, r3, r6, r9, r11, r12}
+                ldmia   r0, {r1, r2, r3, r6, r10, r11, r12}
                 ldr     sp, [r0, #28]
 
                 /*
@@ -188,6 +188,20 @@ restart:	adr	r0, LC0
                  */
                 sub     r0, r0, r1              @ calculate the delta offset
                 add     r6, r6, r0              @ _edata
+                add     r10, r10, r0            @ inflated kernel size location
+
+                /*
+                 * The kernel build system appends the size of the
+                 * decompressed kernel at the end of the compressed data
+                 * in little-endian form.
+                 */
+                ldrb    r9, [r10, #0]
+                ldrb    lr, [r10, #1]
+                orr     r9, r9, lr, lsl #8
+                ldrb    lr, [r10, #2]
+                ldrb    r10, [r10, #3]
+                orr     r9, r9, lr, lsl #16
+                orr     r9, r9, r10, lsl #24
 
 #ifndef CONFIG_ZBOOT_ROM
                 /* malloc space is above the relocated stack (64k max) */
@@ -347,10 +361,10 @@ LC0:		.word	LC0			@ r1
                 .word   __bss_start             @ r2
                 .word   _end                    @ r3
                 .word   _edata                  @ r6
-                .word   _image_size             @ r9
+                .word   input_data_end - 4      @ r10 (inflated size location)
                 .word   _got_start              @ r11
                 .word   _got_end                @ ip
-                .word   user_stack_end          @ sp
+                .word   .L_user_stack_end       @ sp
                 .size   LC0, . - LC0
 
 #ifdef CONFIG_ARCH_RPC
@@ -763,12 +777,6 @@ proc_types:
                 W(b)    __armv4_mmu_cache_off
                 W(b)    __armv6_mmu_cache_flush
 
-                .word   0x560f5810              @ Marvell PJ4 ARMv6
-                .word   0xff0ffff0
-                W(b)    __armv4_mmu_cache_on
-                W(b)    __armv4_mmu_cache_off
-                W(b)    __armv6_mmu_cache_flush
-
                 .word   0x000f0000              @ new CPU Id
                 .word   0x000f0000
                 W(b)    __armv7_mmu_cache_on
@@ -1094,5 +1102,5 @@ reloc_code_end:
 
                 .align
                 .section ".stack", "aw", %nobits
-user_stack:     .space  4096
-user_stack_end:
+.L_user_stack:  .space  4096
+.L_user_stack_end:
diff --git a/arch/arm/boot/compressed/misc.c b/arch/arm/boot/compressed/misc.c
index 2df38263124..832d37236c5 100644
--- a/arch/arm/boot/compressed/misc.c
+++ b/arch/arm/boot/compressed/misc.c
@@ -26,8 +26,6 @@ unsigned int __machine_arch_type;
 #include <linux/linkage.h>
 #include <asm/string.h>
 
-#include <asm/unaligned.h>
-
 
 static void putstr(const char *ptr);
 extern void error(char *x);
@@ -139,13 +137,12 @@ void *memcpy(void *__dest, __const void *__src, size_t __n)
 }
 
 /*
- * gzip delarations
+ * gzip declarations
  */
 extern char input_data[];
 extern char input_data_end[];
 
 unsigned char *output_data;
-unsigned long output_ptr;
 
 unsigned long free_mem_ptr;
 unsigned long free_mem_end_ptr;
@@ -170,15 +167,15 @@ asmlinkage void __div0(void)
         error("Attempting division by 0!");
 }
 
-extern void do_decompress(u8 *input, int len, u8 *output, void (*error)(char *x));
+extern int do_decompress(u8 *input, int len, u8 *output, void (*error)(char *x));
 
 
-unsigned long
+void
 decompress_kernel(unsigned long output_start, unsigned long free_mem_ptr_p,
                 unsigned long free_mem_ptr_end_p,
                 int arch_id)
 {
-        unsigned char *tmp;
+        int ret;
 
         output_data             = (unsigned char *)output_start;
         free_mem_ptr            = free_mem_ptr_p;
@@ -187,12 +184,11 @@ decompress_kernel(unsigned long output_start, unsigned long free_mem_ptr_p,
 
         arch_decomp_setup();
 
-        tmp = (unsigned char *) (((unsigned long)input_data_end) - 4);
-        output_ptr = get_unaligned_le32(tmp);
-
         putstr("Uncompressing Linux...");
-        do_decompress(input_data, input_data_end - input_data,
-                        output_data, error);
-        putstr(" done, booting the kernel.\n");
-        return output_ptr;
+        ret = do_decompress(input_data, input_data_end - input_data,
+                            output_data, error);
+        if (ret)
+                error("decompressor returned an error");
+        else
+                putstr(" done, booting the kernel.\n");
 }
diff --git a/arch/arm/common/gic.c b/arch/arm/common/gic.c
index f70ec7dadeb..4ddd0a6ac7f 100644
--- a/arch/arm/common/gic.c
+++ b/arch/arm/common/gic.c
@@ -49,7 +49,7 @@ struct gic_chip_data {
  * Default make them NULL.
  */
 struct irq_chip gic_arch_extn = {
-        .irq_ack        = NULL,
+        .irq_eoi        = NULL,
         .irq_mask       = NULL,
         .irq_unmask     = NULL,
         .irq_retrigger  = NULL,
@@ -84,21 +84,12 @@ static inline unsigned int gic_irq(struct irq_data *d)
 /*
  * Routines to acknowledge, disable and enable interrupts
  */
-static void gic_ack_irq(struct irq_data *d)
-{
-        spin_lock(&irq_controller_lock);
-        if (gic_arch_extn.irq_ack)
-                gic_arch_extn.irq_ack(d);
-        writel(gic_irq(d), gic_cpu_base(d) + GIC_CPU_EOI);
-        spin_unlock(&irq_controller_lock);
-}
-
 static void gic_mask_irq(struct irq_data *d)
 {
         u32 mask = 1 << (d->irq % 32);
 
         spin_lock(&irq_controller_lock);
-        writel(mask, gic_dist_base(d) + GIC_DIST_ENABLE_CLEAR + (gic_irq(d) / 32) * 4);
+        writel_relaxed(mask, gic_dist_base(d) + GIC_DIST_ENABLE_CLEAR + (gic_irq(d) / 32) * 4);
         if (gic_arch_extn.irq_mask)
                 gic_arch_extn.irq_mask(d);
         spin_unlock(&irq_controller_lock);
@@ -111,10 +102,21 @@ static void gic_unmask_irq(struct irq_data *d)
         spin_lock(&irq_controller_lock);
         if (gic_arch_extn.irq_unmask)
                 gic_arch_extn.irq_unmask(d);
-        writel(mask, gic_dist_base(d) + GIC_DIST_ENABLE_SET + (gic_irq(d) / 32) * 4);
+        writel_relaxed(mask, gic_dist_base(d) + GIC_DIST_ENABLE_SET + (gic_irq(d) / 32) * 4);
         spin_unlock(&irq_controller_lock);
 }
 
+static void gic_eoi_irq(struct irq_data *d)
+{
+        if (gic_arch_extn.irq_eoi) {
+                spin_lock(&irq_controller_lock);
+                gic_arch_extn.irq_eoi(d);
+                spin_unlock(&irq_controller_lock);
+        }
+
+        writel_relaxed(gic_irq(d), gic_cpu_base(d) + GIC_CPU_EOI);
+}
+
 static int gic_set_type(struct irq_data *d, unsigned int type)
 {
         void __iomem *base = gic_dist_base(d);
@@ -138,7 +140,7 @@ static int gic_set_type(struct irq_data *d, unsigned int type)
         if (gic_arch_extn.irq_set_type)
                 gic_arch_extn.irq_set_type(d, type);
 
-        val = readl(base + GIC_DIST_CONFIG + confoff);
+        val = readl_relaxed(base + GIC_DIST_CONFIG + confoff);
         if (type == IRQ_TYPE_LEVEL_HIGH)
                 val &= ~confmask;
         else if (type == IRQ_TYPE_EDGE_RISING)
@@ -148,15 +150,15 @@ static int gic_set_type(struct irq_data *d, unsigned int type)
          * As recommended by the spec, disable the interrupt before changing
          * the configuration
          */
-        if (readl(base + GIC_DIST_ENABLE_SET + enableoff) & enablemask) {
-                writel(enablemask, base + GIC_DIST_ENABLE_CLEAR + enableoff);
+        if (readl_relaxed(base + GIC_DIST_ENABLE_SET + enableoff) & enablemask) {
+                writel_relaxed(enablemask, base + GIC_DIST_ENABLE_CLEAR + enableoff);
                 enabled = true;
         }
 
-        writel(val, base + GIC_DIST_CONFIG + confoff);
+        writel_relaxed(val, base + GIC_DIST_CONFIG + confoff);
 
         if (enabled)
-                writel(enablemask, base + GIC_DIST_ENABLE_SET + enableoff);
+                writel_relaxed(enablemask, base + GIC_DIST_ENABLE_SET + enableoff);
 
         spin_unlock(&irq_controller_lock);
 
@@ -188,8 +190,8 @@ static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val,
 
         spin_lock(&irq_controller_lock);
         d->node = cpu;
-        val = readl(reg) & ~mask;
-        writel(val | bit, reg);
+        val = readl_relaxed(reg) & ~mask;
+        writel_relaxed(val | bit, reg);
         spin_unlock(&irq_controller_lock);
 
         return 0;
@@ -218,11 +220,10 @@ static void gic_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
         unsigned int cascade_irq, gic_irq;
         unsigned long status;
 
-        /* primary controller ack'ing */
-        chip->irq_ack(&desc->irq_data);
+        chained_irq_enter(chip, desc);
 
         spin_lock(&irq_controller_lock);
-        status = readl(chip_data->cpu_base + GIC_CPU_INTACK);
+        status = readl_relaxed(chip_data->cpu_base + GIC_CPU_INTACK);
         spin_unlock(&irq_controller_lock);
 
         gic_irq = (status & 0x3ff);
@@ -236,15 +237,14 @@ static void gic_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
                 generic_handle_irq(cascade_irq);
 
  out:
-        /* primary controller unmasking */
-        chip->irq_unmask(&desc->irq_data);
+        chained_irq_exit(chip, desc);
 }
 
 static struct irq_chip gic_chip = {
         .name                   = "GIC",
-        .irq_ack                = gic_ack_irq,
         .irq_mask               = gic_mask_irq,
         .irq_unmask             = gic_unmask_irq,
+        .irq_eoi                = gic_eoi_irq,
         .irq_set_type           = gic_set_type,
         .irq_retrigger          = gic_retrigger,
 #ifdef CONFIG_SMP
@@ -272,13 +272,13 @@ static void __init gic_dist_init(struct gic_chip_data *gic,
         cpumask |= cpumask << 8;
         cpumask |= cpumask << 16;
 
-        writel(0, base + GIC_DIST_CTRL);
+        writel_relaxed(0, base + GIC_DIST_CTRL);
 
         /*
          * Find out how many interrupts are supported.
          * The GIC only supports up to 1020 interrupt sources.
          */
-        gic_irqs = readl(base + GIC_DIST_CTR) & 0x1f;
+        gic_irqs = readl_relaxed(base + GIC_DIST_CTR) & 0x1f;
         gic_irqs = (gic_irqs + 1) * 32;
         if (gic_irqs > 1020)
                 gic_irqs = 1020;
@@ -287,26 +287,26 @@ static void __init gic_dist_init(struct gic_chip_data *gic,
          * Set all global interrupts to be level triggered, active low.
          */
         for (i = 32; i < gic_irqs; i += 16)
-                writel(0, base + GIC_DIST_CONFIG + i * 4 / 16);
+                writel_relaxed(0, base + GIC_DIST_CONFIG + i * 4 / 16);
 
         /*
          * Set all global interrupts to this CPU only.
          */
         for (i = 32; i < gic_irqs; i += 4)
-                writel(cpumask, base + GIC_DIST_TARGET + i * 4 / 4);
+                writel_relaxed(cpumask, base + GIC_DIST_TARGET + i * 4 / 4);
 
         /*
          * Set priority on all global interrupts.
          */
         for (i = 32; i < gic_irqs; i += 4)
-                writel(0xa0a0a0a0, base + GIC_DIST_PRI + i * 4 / 4);
+                writel_relaxed(0xa0a0a0a0, base + GIC_DIST_PRI + i * 4 / 4);
 
         /*
          * Disable all interrupts.  Leave the PPI and SGIs alone
          * as these enables are banked registers.
          */
         for (i = 32; i < gic_irqs; i += 32)
-                writel(0xffffffff, base + GIC_DIST_ENABLE_CLEAR + i * 4 / 32);
+                writel_relaxed(0xffffffff, base + GIC_DIST_ENABLE_CLEAR + i * 4 / 32);
 
         /*
          * Limit number of interrupts registered to the platform maximum
@@ -319,12 +319,12 @@ static void __init gic_dist_init(struct gic_chip_data *gic,
          * Setup the Linux IRQ subsystem.
          */
         for (i = irq_start; i < irq_limit; i++) {
-                irq_set_chip_and_handler(i, &gic_chip, handle_level_irq);
+                irq_set_chip_and_handler(i, &gic_chip, handle_fasteoi_irq);
                 irq_set_chip_data(i, gic);
                 set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
         }
 
-        writel(1, base + GIC_DIST_CTRL);
+        writel_relaxed(1, base + GIC_DIST_CTRL);
 }
 
 static void __cpuinit gic_cpu_init(struct gic_chip_data *gic)
@@ -337,17 +337,17 @@ static void __cpuinit gic_cpu_init(struct gic_chip_data *gic)
          * Deal with the banked PPI and SGI interrupts - disable all
          * PPI interrupts, ensure all SGI interrupts are enabled.
          */
-        writel(0xffff0000, dist_base + GIC_DIST_ENABLE_CLEAR);
-        writel(0x0000ffff, dist_base + GIC_DIST_ENABLE_SET);
+        writel_relaxed(0xffff0000, dist_base + GIC_DIST_ENABLE_CLEAR);
+        writel_relaxed(0x0000ffff, dist_base + GIC_DIST_ENABLE_SET);
 
         /*
          * Set priority on PPI and SGI interrupts
          */
         for (i = 0; i < 32; i += 4)
-                writel(0xa0a0a0a0, dist_base + GIC_DIST_PRI + i * 4 / 4);
+                writel_relaxed(0xa0a0a0a0, dist_base + GIC_DIST_PRI + i * 4 / 4);
 
-        writel(0xf0, base + GIC_CPU_PRIMASK);
-        writel(1, base + GIC_CPU_CTRL);
+        writel_relaxed(0xf0, base + GIC_CPU_PRIMASK);
+        writel_relaxed(1, base + GIC_CPU_CTRL);
 }
 
 void __init gic_init(unsigned int gic_nr, unsigned int irq_start,
@@ -391,7 +391,13 @@ void gic_raise_softirq(const struct cpumask *mask, unsigned int irq)
 {
         unsigned long map = *cpus_addr(*mask);
 
+        /*
+         * Ensure that stores to Normal memory are visible to the
+         * other CPUs before issuing the IPI.
+         */
+        dsb();
+
         /* this always happens on GIC0 */
-        writel(map << 16 | irq, gic_data[0].dist_base + GIC_DIST_SOFTINT);
+        writel_relaxed(map << 16 | irq, gic_data[0].dist_base + GIC_DIST_SOFTINT);
 }
 #endif
diff --git a/arch/arm/configs/dove_defconfig b/arch/arm/configs/dove_defconfig
index 54bf5eec801..40db34cf277 100644
--- a/arch/arm/configs/dove_defconfig
+++ b/arch/arm/configs/dove_defconfig
@@ -8,8 +8,6 @@ CONFIG_MODULE_UNLOAD=y
 # CONFIG_BLK_DEV_BSG is not set
 CONFIG_ARCH_DOVE=y
 CONFIG_MACH_DOVE_DB=y
-CONFIG_CPU_V6=y
-CONFIG_CPU_32v6K=y
 CONFIG_NO_HZ=y
 CONFIG_HIGH_RES_TIMERS=y
 CONFIG_AEABI=y
@@ -44,7 +42,6 @@ CONFIG_MTD_UBI=y
 CONFIG_BLK_DEV_LOOP=y
 CONFIG_BLK_DEV_RAM=y
 CONFIG_BLK_DEV_RAM_COUNT=1
-# CONFIG_MISC_DEVICES is not set
 # CONFIG_SCSI_PROC_FS is not set
 CONFIG_BLK_DEV_SD=y
 # CONFIG_SCSI_LOWLEVEL is not set
@@ -59,12 +56,12 @@ CONFIG_INPUT_EVDEV=y
 # CONFIG_KEYBOARD_ATKBD is not set
 # CONFIG_MOUSE_PS2 is not set
 # CONFIG_SERIO is not set
+CONFIG_LEGACY_PTY_COUNT=16
 # CONFIG_DEVKMEM is not set
 CONFIG_SERIAL_8250=y
 CONFIG_SERIAL_8250_CONSOLE=y
 # CONFIG_SERIAL_8250_PCI is not set
 CONFIG_SERIAL_8250_RUNTIME_UARTS=2
-CONFIG_LEGACY_PTY_COUNT=16
 # CONFIG_HW_RANDOM is not set
 CONFIG_I2C=y
 CONFIG_I2C_CHARDEV=y
@@ -72,12 +69,10 @@ CONFIG_I2C_MV64XXX=y
 CONFIG_SPI=y
 CONFIG_SPI_ORION=y
 # CONFIG_HWMON is not set
-# CONFIG_VGA_CONSOLE is not set
 CONFIG_USB=y
 CONFIG_USB_DEVICEFS=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_EHCI_ROOT_HUB_TT=y
-CONFIG_USB_EHCI_TT_NEWSCHED=y
 CONFIG_USB_STORAGE=y
 CONFIG_RTC_CLASS=y
 CONFIG_RTC_DRV_MV=y
@@ -86,7 +81,6 @@ CONFIG_MV_XOR=y
 CONFIG_EXT2_FS=y
 CONFIG_EXT3_FS=y
 # CONFIG_EXT3_FS_XATTR is not set
-CONFIG_INOTIFY=y
 CONFIG_ISO9660_FS=y
 CONFIG_JOLIET=y
 CONFIG_UDF_FS=m
@@ -110,23 +104,19 @@ CONFIG_DEBUG_KERNEL=y
 CONFIG_TIMER_STATS=y
 # CONFIG_DEBUG_BUGVERBOSE is not set
 CONFIG_DEBUG_INFO=y
-# CONFIG_RCU_CPU_STALL_DETECTOR is not set
 CONFIG_SYSCTL_SYSCALL_CHECK=y
 CONFIG_DEBUG_USER=y
 CONFIG_DEBUG_ERRORS=y
 CONFIG_CRYPTO_NULL=y
-CONFIG_CRYPTO_CBC=y
 CONFIG_CRYPTO_ECB=m
 CONFIG_CRYPTO_PCBC=m
 CONFIG_CRYPTO_HMAC=y
 CONFIG_CRYPTO_MD4=y
-CONFIG_CRYPTO_MD5=y
 CONFIG_CRYPTO_SHA1=y
 CONFIG_CRYPTO_SHA256=y
 CONFIG_CRYPTO_SHA512=y
 CONFIG_CRYPTO_AES=y
 CONFIG_CRYPTO_BLOWFISH=y
-CONFIG_CRYPTO_DES=y
 CONFIG_CRYPTO_TEA=y
 CONFIG_CRYPTO_TWOFISH=y
 CONFIG_CRYPTO_DEFLATE=y
diff --git a/arch/arm/configs/mx1_defconfig b/arch/arm/configs/mx1_defconfig
index b39b5ced8a1..c9436d0bf59 100644
--- a/arch/arm/configs/mx1_defconfig
+++ b/arch/arm/configs/mx1_defconfig
@@ -15,6 +15,7 @@ CONFIG_ARCH_MXC=y
 CONFIG_ARCH_MX1=y
 CONFIG_ARCH_MX1ADS=y
 CONFIG_MACH_SCB9328=y
+CONFIG_MACH_APF9328=y
 CONFIG_MXC_IRQ_PRIOR=y
 CONFIG_NO_HZ=y
 CONFIG_HIGH_RES_TIMERS=y
diff --git a/arch/arm/configs/mx51_defconfig b/arch/arm/configs/mx51_defconfig
index e3c903281f7..0ace16cba9b 100644
--- a/arch/arm/configs/mx51_defconfig
+++ b/arch/arm/configs/mx51_defconfig
@@ -13,7 +13,7 @@ CONFIG_MODULE_SRCVERSION_ALL=y
 # CONFIG_LBDAF is not set
 # CONFIG_BLK_DEV_BSG is not set
 CONFIG_ARCH_MXC=y
-CONFIG_ARCH_MX5=y
+CONFIG_ARCH_MX51=y
 CONFIG_MACH_MX51_BABBAGE=y
 CONFIG_MACH_MX51_3DS=y
 CONFIG_MACH_EUKREA_CPUIMX51=y
diff --git a/arch/arm/mach-davinci/include/mach/uncompress.h b/arch/arm/mach-davinci/include/mach/uncompress.h
index 47723e8d75a..78d80683cdc 100644
--- a/arch/arm/mach-davinci/include/mach/uncompress.h
+++ b/arch/arm/mach-davinci/include/mach/uncompress.h
@@ -25,8 +25,7 @@
 
 #include <mach/serial.h>
 
-static u32 *uart;
-static u32 *uart_info = (u32 *)(DAVINCI_UART_INFO);
+u32 *uart;
 
 /* PORT_16C550A, in polled non-fifo mode */
 static void putc(char c)
@@ -44,6 +43,8 @@ static inline void flush(void)
 
 static inline void set_uart_info(u32 phys, void * __iomem virt)
 {
+        u32 *uart_info = (u32 *)(DAVINCI_UART_INFO);
+
         uart = (u32 *)phys;
         uart_info[0] = phys;
         uart_info[1] = (u32)virt;
diff --git a/arch/arm/mach-davinci/irq.c b/arch/arm/mach-davinci/irq.c
index e6269a6e001..bfe68ec4e1a 100644
--- a/arch/arm/mach-davinci/irq.c
+++ b/arch/arm/mach-davinci/irq.c
@@ -29,8 +29,6 @@
 #include <mach/common.h>
 #include <asm/mach/irq.h>
 
-#define IRQ_BIT(irq)            ((irq) & 0x1f)
-
 #define FIQ_REG0_OFFSET         0x0000
 #define FIQ_REG1_OFFSET         0x0004
 #define IRQ_REG0_OFFSET         0x0008
@@ -42,78 +40,33 @@
 #define IRQ_INTPRI0_REG_OFFSET  0x0030
 #define IRQ_INTPRI7_REG_OFFSET  0x004C
 
-static inline unsigned int davinci_irq_readl(int offset)
-{
-        return __raw_readl(davinci_intc_base + offset);
-}
-
 static inline void davinci_irq_writel(unsigned long value, int offset)
 {
         __raw_writel(value, davinci_intc_base + offset);
 }
 
-/* Disable interrupt */
-static void davinci_mask_irq(struct irq_data *d)
+static __init void
+davinci_alloc_gc(void __iomem *base, unsigned int irq_start, unsigned int num)
 {
-        unsigned int mask;
-        u32 l;
-
-        mask = 1 << IRQ_BIT(d->irq);
-
-        if (d->irq > 31) {
-                l = davinci_irq_readl(IRQ_ENT_REG1_OFFSET);
-                l &= ~mask;
-                davinci_irq_writel(l, IRQ_ENT_REG1_OFFSET);
-        } else {
-                l = davinci_irq_readl(IRQ_ENT_REG0_OFFSET);
-                l &= ~mask;
-                davinci_irq_writel(l, IRQ_ENT_REG0_OFFSET);
-        }
-}
-
-/* Enable interrupt */
-static void davinci_unmask_irq(struct irq_data *d)
-{
-        unsigned int mask;
-        u32 l;
-
-        mask = 1 << IRQ_BIT(d->irq);
-
-        if (d->irq > 31) {
-                l = davinci_irq_readl(IRQ_ENT_REG1_OFFSET);
-                l |= mask;
-                davinci_irq_writel(l, IRQ_ENT_REG1_OFFSET);
-        } else {
-                l = davinci_irq_readl(IRQ_ENT_REG0_OFFSET);
-                l |= mask;
-                davinci_irq_writel(l, IRQ_ENT_REG0_OFFSET);
-        }
+        struct irq_chip_generic *gc;
+        struct irq_chip_type *ct;
+
+        gc = irq_alloc_generic_chip("AINTC", 1, irq_start, base, handle_edge_irq);
+        ct = gc->chip_types;
+        ct->chip.irq_ack = irq_gc_ack;
+        ct->chip.irq_mask = irq_gc_mask_clr_bit;
+        ct->chip.irq_unmask = irq_gc_mask_set_bit;
+
+        ct->regs.ack = IRQ_REG0_OFFSET;
+        ct->regs.mask = IRQ_ENT_REG0_OFFSET;
+        irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE,
+                               IRQ_NOREQUEST | IRQ_NOPROBE, 0);
 }
 
-/* EOI interrupt */
-static void davinci_ack_irq(struct irq_data *d)
-{
-        unsigned int mask;
-
-        mask = 1 << IRQ_BIT(d->irq);
-
-        if (d->irq > 31)
-                davinci_irq_writel(mask, IRQ_REG1_OFFSET);
-        else
-                davinci_irq_writel(mask, IRQ_REG0_OFFSET);
-}
-
-static struct irq_chip davinci_irq_chip_0 = {
-        .name           = "AINTC",
-        .irq_ack        = davinci_ack_irq,
-        .irq_mask       = davinci_mask_irq,
-        .irq_unmask     = davinci_unmask_irq,
-};
-
 /* ARM Interrupt Controller Initialization */
 void __init davinci_irq_init(void)
 {
-        unsigned i;
+        unsigned i, j;
         const u8 *davinci_def_priorities = davinci_soc_info.intc_irq_prios;
 
         davinci_intc_type = DAVINCI_INTC_TYPE_AINTC;
@@ -144,7 +97,6 @@ void __init davinci_irq_init(void)
         davinci_irq_writel(~0x0, IRQ_REG1_OFFSET);
 
         for (i = IRQ_INTPRI0_REG_OFFSET; i <= IRQ_INTPRI7_REG_OFFSET; i += 4) {
-                unsigned        j;
                 u32             pri;
 
                 for (j = 0, pri = 0; j < 32; j += 4, davinci_def_priorities++)
@@ -152,13 +104,8 @@ void __init davinci_irq_init(void)
                 davinci_irq_writel(pri, i);
         }
 
-        /* set up genirq dispatch for ARM INTC */
-        for (i = 0; i < davinci_soc_info.intc_irq_num; i++) {
-                irq_set_chip(i, &davinci_irq_chip_0);
-                set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
-                if (i != IRQ_TINT1_TINT34)
-                        irq_set_handler(i, handle_edge_irq);
-                else
-                        irq_set_handler(i, handle_level_irq);
-        }
+        for (i = 0, j = 0; i < davinci_soc_info.intc_irq_num; i += 32, j += 0x04)
+                davinci_alloc_gc(davinci_intc_base + j, i, 32);
+
+        irq_set_handler(IRQ_TINT1_TINT34, handle_level_irq);
 }
diff --git a/arch/arm/mach-dove/common.c b/arch/arm/mach-dove/common.c
index e06a88f1f81..5ed51b84c1b 100644
--- a/arch/arm/mach-dove/common.c
+++ b/arch/arm/mach-dove/common.c
@@ -16,10 +16,8 @@
 #include <linux/serial_8250.h>
 #include <linux/clk.h>
 #include <linux/mbus.h>
-#include <linux/mv643xx_eth.h>
-#include <linux/mv643xx_i2c.h>
 #include <linux/ata_platform.h>
-#include <linux/spi/orion_spi.h>
+#include <linux/serial_8250.h>
 #include <linux/gpio.h>
 #include <asm/page.h>
 #include <asm/setup.h>
@@ -32,11 +30,12 @@
 #include <mach/bridge-regs.h>
 #include <asm/mach/arch.h>
 #include <linux/irq.h>
-#include <plat/mv_xor.h>
-#include <plat/ehci-orion.h>
 #include <plat/time.h>
+#include <plat/common.h>
 #include "common.h"
 
+static int get_tclk(void);
+
 /*****************************************************************************
  * I/O Address Mapping
  ****************************************************************************/
@@ -70,463 +69,106 @@ void __init dove_map_io(void)
 }
 
 /*****************************************************************************
- * EHCI
- ****************************************************************************/
-static struct orion_ehci_data dove_ehci_data = {
-        .dram           = &dove_mbus_dram_info,
-        .phy_version    = EHCI_PHY_NA,
-};
-
-static u64 ehci_dmamask = DMA_BIT_MASK(32);
-
-/*****************************************************************************
  * EHCI0
  ****************************************************************************/
-static struct resource dove_ehci0_resources[] = {
-        {
-                .start  = DOVE_USB0_PHYS_BASE,
-                .end    = DOVE_USB0_PHYS_BASE + SZ_4K - 1,
-                .flags  = IORESOURCE_MEM,
-        }, {
-                .start  = IRQ_DOVE_USB0,
-                .end    = IRQ_DOVE_USB0,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device dove_ehci0 = {
-        .name           = "orion-ehci",
-        .id             = 0,
-        .dev            = {
-                .dma_mask               = &ehci_dmamask,
-                .coherent_dma_mask      = DMA_BIT_MASK(32),
-                .platform_data          = &dove_ehci_data,
-        },
-        .resource       = dove_ehci0_resources,
-        .num_resources  = ARRAY_SIZE(dove_ehci0_resources),
-};
-
 void __init dove_ehci0_init(void)
 {
-        platform_device_register(&dove_ehci0);
+        orion_ehci_init(&dove_mbus_dram_info,
+                        DOVE_USB0_PHYS_BASE, IRQ_DOVE_USB0);
 }
 
 /*****************************************************************************
  * EHCI1
  ****************************************************************************/
-static struct resource dove_ehci1_resources[] = {
-        {
-                .start  = DOVE_USB1_PHYS_BASE,
-                .end    = DOVE_USB1_PHYS_BASE + SZ_4K - 1,
-                .flags  = IORESOURCE_MEM,
-        }, {
-                .start  = IRQ_DOVE_USB1,
-                .end    = IRQ_DOVE_USB1,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device dove_ehci1 = {
-        .name           = "orion-ehci",
-        .id             = 1,
-        .dev            = {
-                .dma_mask               = &ehci_dmamask,
-                .coherent_dma_mask      = DMA_BIT_MASK(32),
-                .platform_data          = &dove_ehci_data,
-        },
-        .resource       = dove_ehci1_resources,
-        .num_resources  = ARRAY_SIZE(dove_ehci1_resources),
-};
-
 void __init dove_ehci1_init(void)
 {
-        platform_device_register(&dove_ehci1);
+        orion_ehci_1_init(&dove_mbus_dram_info,
+                          DOVE_USB1_PHYS_BASE, IRQ_DOVE_USB1);
 }
 
 /*****************************************************************************
  * GE00
  ****************************************************************************/
-struct mv643xx_eth_shared_platform_data dove_ge00_shared_data = {
-        .t_clk          = 0,
-        .dram           = &dove_mbus_dram_info,
-};
-
-static struct resource dove_ge00_shared_resources[] = {
-        {
-                .name   = "ge00 base",
-                .start  = DOVE_GE00_PHYS_BASE + 0x2000,
-                .end    = DOVE_GE00_PHYS_BASE + SZ_16K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-};
-
-static struct platform_device dove_ge00_shared = {
-        .name           = MV643XX_ETH_SHARED_NAME,
-        .id             = 0,
-        .dev            = {
-                .platform_data  = &dove_ge00_shared_data,
-        },
-        .num_resources  = 1,
-        .resource       = dove_ge00_shared_resources,
-};
-
-static struct resource dove_ge00_resources[] = {
-        {
-                .name   = "ge00 irq",
-                .start  = IRQ_DOVE_GE00_SUM,
-                .end    = IRQ_DOVE_GE00_SUM,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device dove_ge00 = {
-        .name           = MV643XX_ETH_NAME,
-        .id             = 0,
-        .num_resources  = 1,
-        .resource       = dove_ge00_resources,
-        .dev            = {
-                .coherent_dma_mask      = 0xffffffff,
-        },
-};
-
 void __init dove_ge00_init(struct mv643xx_eth_platform_data *eth_data)
 {
-        eth_data->shared = &dove_ge00_shared;
-        dove_ge00.dev.platform_data = eth_data;
-
-        platform_device_register(&dove_ge00_shared);
-        platform_device_register(&dove_ge00);
+        orion_ge00_init(eth_data, &dove_mbus_dram_info,
+                        DOVE_GE00_PHYS_BASE, IRQ_DOVE_GE00_SUM,
+                        0, get_tclk());
 }
 
 /*****************************************************************************
  * SoC RTC
  ****************************************************************************/
-static struct resource dove_rtc_resource[] = {
-        {
-                .start  = DOVE_RTC_PHYS_BASE,
-                .end    = DOVE_RTC_PHYS_BASE + 32 - 1,
-                .flags  = IORESOURCE_MEM,
-        }, {
-                .start  = IRQ_DOVE_RTC,
-                .flags  = IORESOURCE_IRQ,
-        }
-};
-
 void __init dove_rtc_init(void)
 {
-        platform_device_register_simple("rtc-mv", -1, dove_rtc_resource, 2);
+        orion_rtc_init(DOVE_RTC_PHYS_BASE, IRQ_DOVE_RTC);
 }
 
 /*****************************************************************************
  * SATA
  ****************************************************************************/
-static struct resource dove_sata_resources[] = {
-        {
-                .name   = "sata base",
-                .start  = DOVE_SATA_PHYS_BASE,
-                .end    = DOVE_SATA_PHYS_BASE + 0x5000 - 1,
-                .flags  = IORESOURCE_MEM,
-        }, {
-                .name   = "sata irq",
-                .start  = IRQ_DOVE_SATA,
-                .end    = IRQ_DOVE_SATA,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device dove_sata = {
-        .name           = "sata_mv",
-        .id             = 0,
-        .dev            = {
-                .coherent_dma_mask      = DMA_BIT_MASK(32),
-        },
-        .num_resources  = ARRAY_SIZE(dove_sata_resources),
-        .resource       = dove_sata_resources,
-};
-
 void __init dove_sata_init(struct mv_sata_platform_data *sata_data)
 {
-        sata_data->dram = &dove_mbus_dram_info;
-        dove_sata.dev.platform_data = sata_data;
-        platform_device_register(&dove_sata);
+        orion_sata_init(sata_data, &dove_mbus_dram_info,
+                        DOVE_SATA_PHYS_BASE, IRQ_DOVE_SATA);
+
 }
 
 /*****************************************************************************
  * UART0
  ****************************************************************************/
-static struct plat_serial8250_port dove_uart0_data[] = {
-        {
-                .mapbase        = DOVE_UART0_PHYS_BASE,
-                .membase        = (char *)DOVE_UART0_VIRT_BASE,
-                .irq            = IRQ_DOVE_UART_0,
-                .flags          = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
-                .iotype         = UPIO_MEM,
-                .regshift       = 2,
-                .uartclk        = 0,
-        }, {
-        },
-};
-
-static struct resource dove_uart0_resources[] = {
-        {
-                .start          = DOVE_UART0_PHYS_BASE,
-                .end            = DOVE_UART0_PHYS_BASE + SZ_256 - 1,
-                .flags          = IORESOURCE_MEM,
-        }, {
-                .start          = IRQ_DOVE_UART_0,
-                .end            = IRQ_DOVE_UART_0,
-                .flags          = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device dove_uart0 = {
-        .name                   = "serial8250",
-        .id                     = 0,
-        .dev                    = {
-                .platform_data  = dove_uart0_data,
-        },
-        .resource               = dove_uart0_resources,
-        .num_resources          = ARRAY_SIZE(dove_uart0_resources),
-};
-
 void __init dove_uart0_init(void)
 {
-        platform_device_register(&dove_uart0);
+        orion_uart0_init(DOVE_UART0_VIRT_BASE, DOVE_UART0_PHYS_BASE,
+                         IRQ_DOVE_UART_0, get_tclk());
 }
 
 /*****************************************************************************
  * UART1
  ****************************************************************************/
-static struct plat_serial8250_port dove_uart1_data[] = {
-        {
-                .mapbase        = DOVE_UART1_PHYS_BASE,
-                .membase        = (char *)DOVE_UART1_VIRT_BASE,
-                .irq            = IRQ_DOVE_UART_1,
-                .flags          = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
-                .iotype         = UPIO_MEM,
-                .regshift       = 2,
-                .uartclk        = 0,
-        }, {
-        },
-};
-
-static struct resource dove_uart1_resources[] = {
-        {
-                .start          = DOVE_UART1_PHYS_BASE,
-                .end            = DOVE_UART1_PHYS_BASE + SZ_256 - 1,
-                .flags          = IORESOURCE_MEM,
-        }, {
-                .start          = IRQ_DOVE_UART_1,
-                .end            = IRQ_DOVE_UART_1,
-                .flags          = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device dove_uart1 = {
-        .name                   = "serial8250",
-        .id                     = 1,
-        .dev                    = {
-                .platform_data  = dove_uart1_data,
-        },
-        .resource               = dove_uart1_resources,
-        .num_resources          = ARRAY_SIZE(dove_uart1_resources),
-};
-
 void __init dove_uart1_init(void)
 {
-        platform_device_register(&dove_uart1);
+        orion_uart1_init(DOVE_UART1_VIRT_BASE, DOVE_UART1_PHYS_BASE,
+                         IRQ_DOVE_UART_1, get_tclk());
 }
 
 /*****************************************************************************
  * UART2
  ****************************************************************************/
-static struct plat_serial8250_port dove_uart2_data[] = {
-        {
-                .mapbase        = DOVE_UART2_PHYS_BASE,
-                .membase        = (char *)DOVE_UART2_VIRT_BASE,
-                .irq            = IRQ_DOVE_UART_2,
-                .flags          = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
-                .iotype         = UPIO_MEM,
-                .regshift       = 2,
-                .uartclk        = 0,
-        }, {
-        },
-};
-
-static struct resource dove_uart2_resources[] = {
-        {
-                .start          = DOVE_UART2_PHYS_BASE,
-                .end            = DOVE_UART2_PHYS_BASE + SZ_256 - 1,
-                .flags          = IORESOURCE_MEM,
-        }, {
-                .start          = IRQ_DOVE_UART_2,
-                .end            = IRQ_DOVE_UART_2,
-                .flags          = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device dove_uart2 = {
-        .name                   = "serial8250",
-        .id                     = 2,
-        .dev                    = {
-                .platform_data  = dove_uart2_data,
-        },
-        .resource               = dove_uart2_resources,
-        .num_resources          = ARRAY_SIZE(dove_uart2_resources),
-};
-
 void __init dove_uart2_init(void)
 {
-        platform_device_register(&dove_uart2);
+        orion_uart2_init(DOVE_UART2_VIRT_BASE, DOVE_UART2_PHYS_BASE,
+                         IRQ_DOVE_UART_2, get_tclk());
 }
 
 /*****************************************************************************
  * UART3
  ****************************************************************************/
-static struct plat_serial8250_port dove_uart3_data[] = {
-        {
-                .mapbase        = DOVE_UART3_PHYS_BASE,
-                .membase        = (char *)DOVE_UART3_VIRT_BASE,
-                .irq            = IRQ_DOVE_UART_3,
-                .flags          = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
-                .iotype         = UPIO_MEM,
-                .regshift       = 2,
-                .uartclk        = 0,
-        }, {
-        },
-};
-
-static struct resource dove_uart3_resources[] = {
-        {
-                .start          = DOVE_UART3_PHYS_BASE,
-                .end            = DOVE_UART3_PHYS_BASE + SZ_256 - 1,
-                .flags          = IORESOURCE_MEM,
-        }, {
-                .start          = IRQ_DOVE_UART_3,
-                .end            = IRQ_DOVE_UART_3,
-                .flags          = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device dove_uart3 = {
-        .name                   = "serial8250",
-        .id                     = 3,
-        .dev                    = {
-                .platform_data  = dove_uart3_data,
-        },
-        .resource               = dove_uart3_resources,
-        .num_resources          = ARRAY_SIZE(dove_uart3_resources),
-};
-
 void __init dove_uart3_init(void)
 {
-        platform_device_register(&dove_uart3);
+        orion_uart3_init(DOVE_UART3_VIRT_BASE, DOVE_UART3_PHYS_BASE,
+                         IRQ_DOVE_UART_3, get_tclk());
 }
 
 /*****************************************************************************
- * SPI0
+ * SPI
  ****************************************************************************/
-static struct orion_spi_info dove_spi0_data = {
-        .tclk           = 0,
-};
-
-static struct resource dove_spi0_resources[] = {
-        {
-                .start  = DOVE_SPI0_PHYS_BASE,
-                .end    = DOVE_SPI0_PHYS_BASE + SZ_512 - 1,
-                .flags  = IORESOURCE_MEM,
-        }, {
-                .start  = IRQ_DOVE_SPI0,
-                .end    = IRQ_DOVE_SPI0,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device dove_spi0 = {
-        .name           = "orion_spi",
-        .id             = 0,
-        .resource       = dove_spi0_resources,
-        .dev            = {
-                .platform_data  = &dove_spi0_data,
-        },
-        .num_resources  = ARRAY_SIZE(dove_spi0_resources),
-};
-
 void __init dove_spi0_init(void)
 {
-        platform_device_register(&dove_spi0);
+        orion_spi_init(DOVE_SPI0_PHYS_BASE, get_tclk());
 }
 
-/*****************************************************************************
- * SPI1
- ****************************************************************************/
-static struct orion_spi_info dove_spi1_data = {
-        .tclk           = 0,
-};
-
-static struct resource dove_spi1_resources[] = {
-        {
-                .start  = DOVE_SPI1_PHYS_BASE,
-                .end    = DOVE_SPI1_PHYS_BASE + SZ_512 - 1,
-                .flags  = IORESOURCE_MEM,
-        }, {
-                .start  = IRQ_DOVE_SPI1,
-                .end    = IRQ_DOVE_SPI1,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device dove_spi1 = {
-        .name           = "orion_spi",
-        .id             = 1,
-        .resource       = dove_spi1_resources,
-        .dev            = {
-                .platform_data  = &dove_spi1_data,
-        },
-        .num_resources  = ARRAY_SIZE(dove_spi1_resources),
-};
-
 void __init dove_spi1_init(void)
 {
-        platform_device_register(&dove_spi1);
+        orion_spi_init(DOVE_SPI1_PHYS_BASE, get_tclk());
 }
 
 /*****************************************************************************
  * I2C
  ****************************************************************************/
-static struct mv64xxx_i2c_pdata dove_i2c_data = {
-        .freq_m         = 10, /* assumes 166 MHz TCLK gets 94.3kHz */
-        .freq_n         = 3,
-        .timeout        = 1000, /* Default timeout of 1 second */
-};
-
-static struct resource dove_i2c_resources[] = {
-        {
-                .name   = "i2c base",
-                .start  = DOVE_I2C_PHYS_BASE,
-                .end    = DOVE_I2C_PHYS_BASE + 0x20 - 1,
-                .flags  = IORESOURCE_MEM,
-        }, {
-                .name   = "i2c irq",
-                .start  = IRQ_DOVE_I2C,
-                .end    = IRQ_DOVE_I2C,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device dove_i2c = {
-        .name           = MV64XXX_I2C_CTLR_NAME,
-        .id             = 0,
-        .num_resources  = ARRAY_SIZE(dove_i2c_resources),
-        .resource       = dove_i2c_resources,
-        .dev            = {
-                .platform_data = &dove_i2c_data,
-        },
-};
-
 void __init dove_i2c_init(void)
 {
-        platform_device_register(&dove_i2c);
+        orion_i2c_init(DOVE_I2C_PHYS_BASE, IRQ_DOVE_I2C, 10);
 }
 
 /*****************************************************************************
@@ -554,208 +196,22 @@ struct sys_timer dove_timer = {
 };
 
 /*****************************************************************************
- * XOR
- ****************************************************************************/
-static struct mv_xor_platform_shared_data dove_xor_shared_data = {
-        .dram           = &dove_mbus_dram_info,
-};
-
-/*****************************************************************************
  * XOR 0
  ****************************************************************************/
-static u64 dove_xor0_dmamask = DMA_BIT_MASK(32);
-
-static struct resource dove_xor0_shared_resources[] = {
-        {
-                .name   = "xor 0 low",
-                .start  = DOVE_XOR0_PHYS_BASE,
-                .end    = DOVE_XOR0_PHYS_BASE + 0xff,
-                .flags  = IORESOURCE_MEM,
-        }, {
-                .name   = "xor 0 high",
-                .start  = DOVE_XOR0_HIGH_PHYS_BASE,
-                .end    = DOVE_XOR0_HIGH_PHYS_BASE + 0xff,
-                .flags  = IORESOURCE_MEM,
-        },
-};
-
-static struct platform_device dove_xor0_shared = {
-        .name           = MV_XOR_SHARED_NAME,
-        .id             = 0,
-        .dev            = {
-                .platform_data = &dove_xor_shared_data,
-        },
-        .num_resources  = ARRAY_SIZE(dove_xor0_shared_resources),
-        .resource       = dove_xor0_shared_resources,
-};
-
-static struct resource dove_xor00_resources[] = {
-        [0] = {
-                .start  = IRQ_DOVE_XOR_00,
-                .end    = IRQ_DOVE_XOR_00,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct mv_xor_platform_data dove_xor00_data = {
-        .shared         = &dove_xor0_shared,
-        .hw_id          = 0,
-        .pool_size      = PAGE_SIZE,
-};
-
-static struct platform_device dove_xor00_channel = {
-        .name           = MV_XOR_NAME,
-        .id             = 0,
-        .num_resources  = ARRAY_SIZE(dove_xor00_resources),
-        .resource       = dove_xor00_resources,
-        .dev            = {
-                .dma_mask               = &dove_xor0_dmamask,
-                .coherent_dma_mask      = DMA_BIT_MASK(64),
-                .platform_data          = &dove_xor00_data,
-        },
-};
-
-static struct resource dove_xor01_resources[] = {
-        [0] = {
-                .start  = IRQ_DOVE_XOR_01,
-                .end    = IRQ_DOVE_XOR_01,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct mv_xor_platform_data dove_xor01_data = {
-        .shared         = &dove_xor0_shared,
-        .hw_id          = 1,
-        .pool_size      = PAGE_SIZE,
-};
-
-static struct platform_device dove_xor01_channel = {
-        .name           = MV_XOR_NAME,
-        .id             = 1,
-        .num_resources  = ARRAY_SIZE(dove_xor01_resources),
-        .resource       = dove_xor01_resources,
-        .dev            = {
-                .dma_mask               = &dove_xor0_dmamask,
-                .coherent_dma_mask      = DMA_BIT_MASK(64),
-                .platform_data          = &dove_xor01_data,
-        },
-};
-
 void __init dove_xor0_init(void)
 {
-        platform_device_register(&dove_xor0_shared);
-
-        /*
-         * two engines can't do memset simultaneously, this limitation
-         * satisfied by removing memset support from one of the engines.
-         */
-        dma_cap_set(DMA_MEMCPY, dove_xor00_data.cap_mask);
-        dma_cap_set(DMA_XOR, dove_xor00_data.cap_mask);
-        platform_device_register(&dove_xor00_channel);
-
-        dma_cap_set(DMA_MEMCPY, dove_xor01_data.cap_mask);
-        dma_cap_set(DMA_MEMSET, dove_xor01_data.cap_mask);
-        dma_cap_set(DMA_XOR, dove_xor01_data.cap_mask);
-        platform_device_register(&dove_xor01_channel);
+        orion_xor0_init(&dove_mbus_dram_info,
+                        DOVE_XOR0_PHYS_BASE, DOVE_XOR0_HIGH_PHYS_BASE,
+                        IRQ_DOVE_XOR_00, IRQ_DOVE_XOR_01);
 }
 
 /*****************************************************************************
  * XOR 1
  ****************************************************************************/
-static u64 dove_xor1_dmamask = DMA_BIT_MASK(32);
-
-static struct resource dove_xor1_shared_resources[] = {
-        {
-                .name   = "xor 0 low",
-                .start  = DOVE_XOR1_PHYS_BASE,
-                .end    = DOVE_XOR1_PHYS_BASE + 0xff,
-                .flags  = IORESOURCE_MEM,
-        }, {
-                .name   = "xor 0 high",
-                .start  = DOVE_XOR1_HIGH_PHYS_BASE,
-                .end    = DOVE_XOR1_HIGH_PHYS_BASE + 0xff,
-                .flags  = IORESOURCE_MEM,
-        },
-};
-
-static struct platform_device dove_xor1_shared = {
-        .name           = MV_XOR_SHARED_NAME,
-        .id             = 1,
-        .dev            = {
-                .platform_data = &dove_xor_shared_data,
-        },
-        .num_resources  = ARRAY_SIZE(dove_xor1_shared_resources),
-        .resource       = dove_xor1_shared_resources,
-};
-
-static struct resource dove_xor10_resources[] = {
-        [0] = {
-                .start  = IRQ_DOVE_XOR_10,
-                .end    = IRQ_DOVE_XOR_10,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct mv_xor_platform_data dove_xor10_data = {
-        .shared         = &dove_xor1_shared,
-        .hw_id          = 0,
-        .pool_size      = PAGE_SIZE,
-};
-
-static struct platform_device dove_xor10_channel = {
-        .name           = MV_XOR_NAME,
-        .id             = 2,
-        .num_resources  = ARRAY_SIZE(dove_xor10_resources),
-        .resource       = dove_xor10_resources,
-        .dev            = {
-                .dma_mask               = &dove_xor1_dmamask,
-                .coherent_dma_mask      = DMA_BIT_MASK(64),
-                .platform_data          = &dove_xor10_data,
-        },
-};
-
-static struct resource dove_xor11_resources[] = {
-        [0] = {
-                .start  = IRQ_DOVE_XOR_11,
-                .end    = IRQ_DOVE_XOR_11,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct mv_xor_platform_data dove_xor11_data = {
-        .shared         = &dove_xor1_shared,
-        .hw_id          = 1,
-        .pool_size      = PAGE_SIZE,
-};
-
-static struct platform_device dove_xor11_channel = {
-        .name           = MV_XOR_NAME,
-        .id             = 3,
-        .num_resources  = ARRAY_SIZE(dove_xor11_resources),
-        .resource       = dove_xor11_resources,
-        .dev            = {
-                .dma_mask               = &dove_xor1_dmamask,
-                .coherent_dma_mask      = DMA_BIT_MASK(64),
-                .platform_data          = &dove_xor11_data,
-        },
-};
-
 void __init dove_xor1_init(void)
 {
-        platform_device_register(&dove_xor1_shared);
-
-        /*
-         * two engines can't do memset simultaneously, this limitation
-         * satisfied by removing memset support from one of the engines.
-         */
-        dma_cap_set(DMA_MEMCPY, dove_xor10_data.cap_mask);
-        dma_cap_set(DMA_XOR, dove_xor10_data.cap_mask);
-        platform_device_register(&dove_xor10_channel);
-
-        dma_cap_set(DMA_MEMCPY, dove_xor11_data.cap_mask);
-        dma_cap_set(DMA_MEMSET, dove_xor11_data.cap_mask);
-        dma_cap_set(DMA_XOR, dove_xor11_data.cap_mask);
-        platform_device_register(&dove_xor11_channel);
+        orion_xor1_init(DOVE_XOR1_PHYS_BASE, DOVE_XOR1_HIGH_PHYS_BASE,
+                        IRQ_DOVE_XOR_10, IRQ_DOVE_XOR_11);
 }
 
 /*****************************************************************************
@@ -833,14 +289,6 @@ void __init dove_init(void)
 #endif
         dove_setup_cpu_mbus();
 
-        dove_ge00_shared_data.t_clk = tclk;
-        dove_uart0_data[0].uartclk = tclk;
-        dove_uart1_data[0].uartclk = tclk;
-        dove_uart2_data[0].uartclk = tclk;
-        dove_uart3_data[0].uartclk = tclk;
-        dove_spi0_data.tclk = tclk;
-        dove_spi1_data.tclk = tclk;
-
         /* internal devices that every board has */
         dove_rtc_init();
         dove_xor0_init();
diff --git a/arch/arm/mach-dove/mpp.c b/arch/arm/mach-dove/mpp.c
index c66c7634690..51e0e411c9c 100644
--- a/arch/arm/mach-dove/mpp.c
+++ b/arch/arm/mach-dove/mpp.c
@@ -11,24 +11,17 @@
 #include <linux/kernel.h>
 #include <linux/gpio.h>
 #include <linux/io.h>
-
+#include <plat/mpp.h>
 #include <mach/dove.h>
-
 #include "mpp.h"
 
-#define MPP_NR_REGS 4
-#define MPP_CTRL(i)     ((i) == 3 ?                             \
-                         DOVE_MPP_CTRL4_VIRT_BASE :             \
-                         DOVE_MPP_VIRT_BASE + (i) * 4)
-#define PMU_SIG_REGS 2
-#define PMU_SIG_CTRL(i) (DOVE_PMU_SIG_CTRL + (i) * 4)
-
 struct dove_mpp_grp {
         int start;
         int end;
 };
 
-static struct dove_mpp_grp dove_mpp_grp[] = {
+/* Map a group to a range of GPIO pins in that group */
+static const struct dove_mpp_grp dove_mpp_grp[] = {
         [MPP_24_39] = {
                 .start  = 24,
                 .end    = 39,
@@ -38,8 +31,8 @@ static struct dove_mpp_grp dove_mpp_grp[] = {
                 .end    = 45,
         },
         [MPP_46_51] = {
-                .start  = 40,
-                .end    = 45,
+                .start  = 46,
+                .end    = 51,
         },
         [MPP_58_61] = {
                 .start  = 58,
@@ -51,6 +44,8 @@ static struct dove_mpp_grp dove_mpp_grp[] = {
         },
 };
 
+/* Enable gpio for a range of pins. mode should be a combination of
+   GPIO_OUTPUT_OK | GPIO_INPUT_OK */
 static void dove_mpp_gpio_mode(int start, int end, int gpio_mode)
 {
         int i;
@@ -59,24 +54,17 @@ static void dove_mpp_gpio_mode(int start, int end, int gpio_mode)
                 orion_gpio_set_valid(i, gpio_mode);
 }
 
+/* Dump all the extra MPP registers. The platform code will dump the
+   registers for pins 0-23. */
 static void dove_mpp_dump_regs(void)
 {
-#ifdef DEBUG
-        int i;
+        pr_debug("PMU_CTRL4_CTRL: %08x\n",
+                 readl(DOVE_MPP_CTRL4_VIRT_BASE));
 
-        pr_debug("MPP_CTRL regs:");
-        for (i = 0; i < MPP_NR_REGS; i++)
-                printk(" %08x", readl(MPP_CTRL(i)));
-        printk("\n");
+        pr_debug("PMU_MPP_GENERAL_CTRL: %08x\n",
+                 readl(DOVE_PMU_MPP_GENERAL_CTRL));
 
-        pr_debug("PMU_SIG_CTRL regs:");
-        for (i = 0; i < PMU_SIG_REGS; i++)
-                printk(" %08x", readl(PMU_SIG_CTRL(i)));
-        printk("\n");
-
-        pr_debug("PMU_MPP_GENERAL_CTRL: %08x\n", readl(DOVE_PMU_MPP_GENERAL_CTRL));
         pr_debug("MPP_GENERAL: %08x\n", readl(DOVE_MPP_GENERAL_VIRT_BASE));
-#endif
 }
 
 static void dove_mpp_cfg_nfc(int sel)
@@ -92,7 +80,7 @@ static void dove_mpp_cfg_nfc(int sel)
 
 static void dove_mpp_cfg_au1(int sel)
 {
-        u32 mpp_ctrl4           = readl(DOVE_MPP_CTRL4_VIRT_BASE);
+        u32 mpp_ctrl4 = readl(DOVE_MPP_CTRL4_VIRT_BASE);
         u32 ssp_ctrl1 = readl(DOVE_SSP_CTRL_STATUS_1);
         u32 mpp_gen_ctrl = readl(DOVE_MPP_GENERAL_VIRT_BASE);
         u32 global_cfg_2 = readl(DOVE_GLOBAL_CONFIG_2);
@@ -128,82 +116,46 @@ static void dove_mpp_cfg_au1(int sel)
         writel(global_cfg_2, DOVE_GLOBAL_CONFIG_2);
 }
 
-static void dove_mpp_conf_grp(int num, int sel, u32 *mpp_ctrl)
-{
-        int start = dove_mpp_grp[num].start;
-        int end = dove_mpp_grp[num].end;
-        int gpio_mode = sel ? GPIO_OUTPUT_OK | GPIO_INPUT_OK : 0;
-
-        *mpp_ctrl &= ~(0x1 << num);
-        *mpp_ctrl |= sel << num;
-
-        dove_mpp_gpio_mode(start, end, gpio_mode);
-}
-
-void __init dove_mpp_conf(unsigned int *mpp_list)
+/* Configure the group registers, enabling GPIO if sel indicates the
+   pin is to be used for GPIO */
+static void dove_mpp_conf_grp(unsigned int *mpp_grp_list)
 {
-        u32 mpp_ctrl[MPP_NR_REGS];
-        u32 pmu_mpp_ctrl = 0;
-        u32 pmu_sig_ctrl[PMU_SIG_REGS];
-        int i;
-
-        for (i = 0; i < MPP_NR_REGS; i++)
-                mpp_ctrl[i] = readl(MPP_CTRL(i));
-
-        for (i = 0; i < PMU_SIG_REGS; i++)
-                pmu_sig_ctrl[i] = readl(PMU_SIG_CTRL(i));
-
-        pmu_mpp_ctrl = readl(DOVE_PMU_MPP_GENERAL_CTRL);
+        u32 mpp_ctrl4 = readl(DOVE_MPP_CTRL4_VIRT_BASE);
+        int gpio_mode;
 
-        dove_mpp_dump_regs();
-
-        for ( ; *mpp_list != MPP_END; mpp_list++) {
-                unsigned int num = MPP_NUM(*mpp_list);
-                unsigned int sel = MPP_SEL(*mpp_list);
-                int shift, gpio_mode;
-
-                if (num > MPP_MAX) {
-                        pr_err("dove: invalid MPP number (%u)\n", num);
-                        continue;
-                }
-
-                if (*mpp_list & MPP_NFC_MASK) {
-                        dove_mpp_cfg_nfc(sel);
-                        continue;
-                }
+        for ( ; *mpp_grp_list; mpp_grp_list++) {
+                unsigned int num = MPP_NUM(*mpp_grp_list);
+                unsigned int sel = MPP_SEL(*mpp_grp_list);
 
-                if (*mpp_list & MPP_AU1_MASK) {
-                        dove_mpp_cfg_au1(sel);
+                if (num > MPP_GRP_MAX) {
+                        pr_err("dove: invalid MPP GRP number (%u)\n", num);
                         continue;
                 }
 
-                if (*mpp_list & MPP_GRP_MASK) {
-                        dove_mpp_conf_grp(num, sel, &mpp_ctrl[3]);
-                        continue;
-                }
-
-                shift = (num & 7) << 2;
-                if (*mpp_list & MPP_PMU_MASK) {
-                        pmu_mpp_ctrl |= (0x1 << num);
-                        pmu_sig_ctrl[num / 8] &= ~(0xf << shift);
-                        pmu_sig_ctrl[num / 8] |= 0xf << shift;
-                        gpio_mode = 0;
-                } else {
-                        mpp_ctrl[num / 8] &= ~(0xf << shift);
-                        mpp_ctrl[num / 8] |= sel << shift;
-                        gpio_mode = GPIO_OUTPUT_OK | GPIO_INPUT_OK;
-                }
+                mpp_ctrl4 &= ~(0x1 << num);
+                mpp_ctrl4 |= sel << num;
 
-                orion_gpio_set_valid(num, gpio_mode);
+                gpio_mode = sel ? GPIO_OUTPUT_OK | GPIO_INPUT_OK : 0;
+                dove_mpp_gpio_mode(dove_mpp_grp[num].start,
+                                   dove_mpp_grp[num].end, gpio_mode);
         }
+        writel(mpp_ctrl4, DOVE_MPP_CTRL4_VIRT_BASE);
+}
 
-        for (i = 0; i < MPP_NR_REGS; i++)
-                writel(mpp_ctrl[i], MPP_CTRL(i));
+/* Configure the various MPP pins on Dove */
+void __init dove_mpp_conf(unsigned int *mpp_list,
+                          unsigned int *mpp_grp_list,
+                          unsigned int grp_au1_52_57,
+                          unsigned int grp_nfc_64_71)
+{
+        dove_mpp_dump_regs();
 
-        for (i = 0; i < PMU_SIG_REGS; i++)
-                writel(pmu_sig_ctrl[i], PMU_SIG_CTRL(i));
+        /* Use platform code for pins 0-23 */
+        orion_mpp_conf(mpp_list, 0, MPP_MAX, DOVE_MPP_VIRT_BASE);
 
-        writel(pmu_mpp_ctrl, DOVE_PMU_MPP_GENERAL_CTRL);
+        dove_mpp_conf_grp(mpp_grp_list);
+        dove_mpp_cfg_au1(grp_au1_52_57);
+        dove_mpp_cfg_nfc(grp_nfc_64_71);
 
         dove_mpp_dump_regs();
 }
diff --git a/arch/arm/mach-dove/mpp.h b/arch/arm/mach-dove/mpp.h
index 2a43ce413b1..fbec7c52bfa 100644
--- a/arch/arm/mach-dove/mpp.h
+++ b/arch/arm/mach-dove/mpp.h
@@ -1,178 +1,150 @@
 #ifndef __ARCH_DOVE_MPP_CODED_H
 #define __ARCH_DOVE_MPP_CODED_H
 
-#define MPP(_num, _mode, _pmu, _grp, _au1, _nfc) (      \
-/* MPP/group number */          ((_num) & 0xff) |               \
-/* MPP select value */          (((_mode) & 0xf) << 8) |        \
-/* MPP PMU */                   ((!!(_pmu)) << 12) |            \
-/* group flag */                ((!!(_grp)) << 13) |            \
-/* AU1 flag */                  ((!!(_au1)) << 14) |            \
-/* NFCE flag */                 ((!!(_nfc)) << 15))
-
-#define MPP_MAX 71
-
-#define MPP_NUM(x)    ((x) & 0xff)
-#define MPP_SEL(x)    (((x) >> 8) & 0xf)
-
-#define MPP_PMU_MASK            MPP(0, 0x0, 1, 0, 0, 0)
-#define MPP_GRP_MASK            MPP(0, 0x0, 0, 1, 0, 0)
-#define MPP_AU1_MASK            MPP(0, 0x0, 0, 0, 1, 0)
-#define MPP_NFC_MASK            MPP(0, 0x0, 0, 0, 0, 1)
-
-#define MPP_END                 MPP(0xff, 0xf, 1, 1, 1, 1)
-
-#define MPP_PMU_DRIVE_0         0x1
-#define MPP_PMU_DRIVE_1         0x2
-#define MPP_PMU_SDI             0x3
-#define MPP_PMU_CPU_PWRDWN      0x4
-#define MPP_PMU_STBY_PWRDWN     0x5
-#define MPP_PMU_CORE_PWR_GOOD   0x8
-#define MPP_PMU_BAT_FAULT       0xa
-#define MPP_PMU_EXT0_WU         0xb
-#define MPP_PMU_EXT1_WU         0xc
-#define MPP_PMU_EXT2_WU         0xd
-#define MPP_PMU_BLINK           0xe
-#define MPP_PMU(_num, _mode)    MPP((_num), MPP_PMU_##_mode, 1, 0, 0, 0)
-
-#define MPP_PIN(_num, _mode)    MPP((_num), (_mode), 0, 0, 0, 0)
-#define MPP_GRP(_grp, _mode)    MPP((_grp), (_mode), 0, 1, 0, 0)
-#define MPP_GRP_AU1(_mode)      MPP(0, (_mode), 0, 0, 1, 0)
-#define MPP_GRP_NFC(_mode)      MPP(0, (_mode), 0, 0, 0, 1)
-
-#define MPP0_GPIO0              MPP_PIN(0, 0x0)
-#define MPP0_UA2_RTSn           MPP_PIN(0, 0x2)
-#define MPP0_SDIO0_CD           MPP_PIN(0, 0x3)
-#define MPP0_LCD0_PWM           MPP_PIN(0, 0xf)
-
-#define MPP1_GPIO1              MPP_PIN(1, 0x0)
-#define MPP1_UA2_CTSn           MPP_PIN(1, 0x2)
-#define MPP1_SDIO0_WP           MPP_PIN(1, 0x3)
-#define MPP1_LCD1_PWM           MPP_PIN(1, 0xf)
-
-#define MPP2_GPIO2              MPP_PIN(2, 0x0)
-#define MPP2_SATA_PRESENT       MPP_PIN(2, 0x1)
-#define MPP2_UA2_TXD            MPP_PIN(2, 0x2)
-#define MPP2_SDIO0_BUS_POWER    MPP_PIN(2, 0x3)
-#define MPP2_UA_RTSn1           MPP_PIN(2, 0x4)
-
-#define MPP3_GPIO3              MPP_PIN(3, 0x0)
-#define MPP3_SATA_ACT           MPP_PIN(3, 0x1)
-#define MPP3_UA2_RXD            MPP_PIN(3, 0x2)
-#define MPP3_SDIO0_LED_CTRL     MPP_PIN(3, 0x3)
-#define MPP3_UA_CTSn1           MPP_PIN(3, 0x4)
-#define MPP3_SPI_LCD_CS1        MPP_PIN(3, 0xf)
-
-#define MPP4_GPIO4              MPP_PIN(4, 0x0)
-#define MPP4_UA3_RTSn           MPP_PIN(4, 0x2)
-#define MPP4_SDIO1_CD           MPP_PIN(4, 0x3)
-#define MPP4_SPI_1_MISO         MPP_PIN(4, 0x4)
-
-#define MPP5_GPIO5              MPP_PIN(5, 0x0)
-#define MPP5_UA3_CTSn           MPP_PIN(5, 0x2)
-#define MPP5_SDIO1_WP           MPP_PIN(5, 0x3)
-#define MPP5_SPI_1_CS           MPP_PIN(5, 0x4)
-
-#define MPP6_GPIO6              MPP_PIN(6, 0x0)
-#define MPP6_UA3_TXD            MPP_PIN(6, 0x2)
-#define MPP6_SDIO1_BUS_POWER    MPP_PIN(6, 0x3)
-#define MPP6_SPI_1_MOSI         MPP_PIN(6, 0x4)
-
-#define MPP7_GPIO7              MPP_PIN(7, 0x0)
-#define MPP7_UA3_RXD            MPP_PIN(7, 0x2)
-#define MPP7_SDIO1_LED_CTRL     MPP_PIN(7, 0x3)
-#define MPP7_SPI_1_SCK          MPP_PIN(7, 0x4)
-
-#define MPP8_GPIO8              MPP_PIN(8, 0x0)
-#define MPP8_WD_RST_OUT         MPP_PIN(8, 0x1)
-
-#define MPP9_GPIO9              MPP_PIN(9, 0x0)
-#define MPP9_PEX1_CLKREQn       MPP_PIN(9, 0x5)
-
-#define MPP10_GPIO10            MPP_PIN(10, 0x0)
-#define MPP10_SSP_SCLK          MPP_PIN(10, 0x5)
-
-#define MPP11_GPIO11            MPP_PIN(11, 0x0)
-#define MPP11_SATA_PRESENT      MPP_PIN(11, 0x1)
-#define MPP11_SATA_ACT          MPP_PIN(11, 0x2)
-#define MPP11_SDIO0_LED_CTRL    MPP_PIN(11, 0x3)
-#define MPP11_SDIO1_LED_CTRL    MPP_PIN(11, 0x4)
-#define MPP11_PEX0_CLKREQn      MPP_PIN(11, 0x5)
-
-#define MPP12_GPIO12            MPP_PIN(12, 0x0)
-#define MPP12_SATA_ACT          MPP_PIN(12, 0x1)
-#define MPP12_UA2_RTSn          MPP_PIN(12, 0x2)
-#define MPP12_AD0_I2S_EXT_MCLK  MPP_PIN(12, 0x3)
-#define MPP12_SDIO1_CD          MPP_PIN(12, 0x4)
-
-#define MPP13_GPIO13            MPP_PIN(13, 0x0)
-#define MPP13_UA2_CTSn          MPP_PIN(13, 0x2)
-#define MPP13_AD1_I2S_EXT_MCLK  MPP_PIN(13, 0x3)
-#define MPP13_SDIO1WP           MPP_PIN(13, 0x4)
-#define MPP13_SSP_EXTCLK        MPP_PIN(13, 0x5)
-
-#define MPP14_GPIO14            MPP_PIN(14, 0x0)
-#define MPP14_UA2_TXD           MPP_PIN(14, 0x2)
-#define MPP14_SDIO1_BUS_POWER   MPP_PIN(14, 0x4)
-#define MPP14_SSP_RXD           MPP_PIN(14, 0x5)
-
-#define MPP15_GPIO15            MPP_PIN(15, 0x0)
-#define MPP15_UA2_RXD           MPP_PIN(15, 0x2)
-#define MPP15_SDIO1_LED_CTRL    MPP_PIN(15, 0x4)
-#define MPP15_SSP_SFRM          MPP_PIN(15, 0x5)
-
-#define MPP16_GPIO16            MPP_PIN(16, 0x0)
-#define MPP16_UA3_RTSn          MPP_PIN(16, 0x2)
-#define MPP16_SDIO0_CD          MPP_PIN(16, 0x3)
-#define MPP16_SPI_LCD_CS1       MPP_PIN(16, 0x4)
-#define MPP16_AC97_SDATA_IN1    MPP_PIN(16, 0x5)
-
-#define MPP17_GPIO17            MPP_PIN(17, 0x0)
-#define MPP17_AC97_SYSCLK_OUT   MPP_PIN(17, 0x1)
-#define MPP17_UA3_CTSn          MPP_PIN(17, 0x2)
-#define MPP17_SDIO0_WP          MPP_PIN(17, 0x3)
-#define MPP17_TW_SDA2           MPP_PIN(17, 0x4)
-#define MPP17_AC97_SDATA_IN2    MPP_PIN(17, 0x5)
-
-#define MPP18_GPIO18            MPP_PIN(18, 0x0)
-#define MPP18_UA3_TXD           MPP_PIN(18, 0x2)
-#define MPP18_SDIO0_BUS_POWER   MPP_PIN(18, 0x3)
-#define MPP18_LCD0_PWM          MPP_PIN(18, 0x4)
-#define MPP18_AC_SDATA_IN3      MPP_PIN(18, 0x5)
-
-#define MPP19_GPIO19            MPP_PIN(19, 0x0)
-#define MPP19_UA3_RXD           MPP_PIN(19, 0x2)
-#define MPP19_SDIO0_LED_CTRL    MPP_PIN(19, 0x3)
-#define MPP19_TW_SCK2           MPP_PIN(19, 0x4)
-
-#define MPP20_GPIO20            MPP_PIN(20, 0x0)
-#define MPP20_AC97_SYSCLK_OUT   MPP_PIN(20, 0x1)
-#define MPP20_SPI_LCD_MISO      MPP_PIN(20, 0x2)
-#define MPP20_SDIO1_CD          MPP_PIN(20, 0x3)
-#define MPP20_SDIO0_CD          MPP_PIN(20, 0x5)
-#define MPP20_SPI_1_MISO        MPP_PIN(20, 0x6)
-
-#define MPP21_GPIO21            MPP_PIN(21, 0x0)
-#define MPP21_UA1_RTSn          MPP_PIN(21, 0x1)
-#define MPP21_SPI_LCD_CS0       MPP_PIN(21, 0x2)
-#define MPP21_SDIO1_WP          MPP_PIN(21, 0x3)
-#define MPP21_SSP_SFRM          MPP_PIN(21, 0x4)
-#define MPP21_SDIO0_WP          MPP_PIN(21, 0x5)
-#define MPP21_SPI_1_CS          MPP_PIN(21, 0x6)
-
-#define MPP22_GPIO22            MPP_PIN(22, 0x0)
-#define MPP22_UA1_CTSn          MPP_PIN(22, 0x1)
-#define MPP22_SPI_LCD_MOSI      MPP_PIN(22, 0x2)
-#define MPP22_SDIO1_BUS_POWER   MPP_PIN(22, 0x3)
-#define MPP22_SSP_TXD           MPP_PIN(22, 0x4)
-#define MPP22_SDIO0_BUS_POWER   MPP_PIN(22, 0x5)
-#define MPP22_SPI_1_MOSI        MPP_PIN(22, 0x6)
-
-#define MPP23_GPIO23            MPP_PIN(23, 0x0)
-#define MPP23_SPI_LCD_SCK       MPP_PIN(23, 0x2)
-#define MPP23_SDIO1_LED_CTRL    MPP_PIN(23, 0x3)
-#define MPP23_SSP_SCLK          MPP_PIN(23, 0x4)
-#define MPP23_SDIO0_LED_CTRL    MPP_PIN(23, 0x5)
-#define MPP23_SPI_1_SCK         MPP_PIN(23, 0x6)
+#define MPP(_num, _sel, _in, _out) ( \
+        /* MPP number */                ((_num) & 0xff) | \
+        /* MPP select value */          (((_sel) & 0xf) << 8) | \
+        /* may be input signal */       ((!!(_in)) << 12) | \
+        /* may be output signal */      ((!!(_out)) << 13))
+
+#define MPP0_GPIO0              MPP(0, 0x0, 1, 1)
+#define MPP0_UA2_RTSn           MPP(0, 0x2, 0, 0)
+#define MPP0_SDIO0_CD           MPP(0, 0x3, 0, 0)
+#define MPP0_LCD0_PWM           MPP(0, 0xf, 0, 0)
+
+#define MPP1_GPIO1              MPP(1, 0x0, 1, 1)
+#define MPP1_UA2_CTSn           MPP(1, 0x2, 0, 0)
+#define MPP1_SDIO0_WP           MPP(1, 0x3, 0, 0)
+#define MPP1_LCD1_PWM           MPP(1, 0xf, 0, 0)
+
+#define MPP2_GPIO2              MPP(2, 0x0, 1, 1)
+#define MPP2_SATA_PRESENT       MPP(2, 0x1, 0, 0)
+#define MPP2_UA2_TXD            MPP(2, 0x2, 0, 0)
+#define MPP2_SDIO0_BUS_POWER    MPP(2, 0x3, 0, 0)
+#define MPP2_UA_RTSn1           MPP(2, 0x4, 0, 0)
+
+#define MPP3_GPIO3              MPP(3, 0x0, 1, 1)
+#define MPP3_SATA_ACT           MPP(3, 0x1, 0, 0)
+#define MPP3_UA2_RXD            MPP(3, 0x2, 0, 0)
+#define MPP3_SDIO0_LED_CTRL     MPP(3, 0x3, 0, 0)
+#define MPP3_UA_CTSn1           MPP(3, 0x4, 0, 0)
+#define MPP3_SPI_LCD_CS1        MPP(3, 0xf, 0, 0)
+
+#define MPP4_GPIO4              MPP(4, 0x0, 1, 1)
+#define MPP4_UA3_RTSn           MPP(4, 0x2, 0, 0)
+#define MPP4_SDIO1_CD           MPP(4, 0x3, 0, 0)
+#define MPP4_SPI_1_MISO         MPP(4, 0x4, 0, 0)
+
+#define MPP5_GPIO5              MPP(5, 0x0, 1, 1)
+#define MPP5_UA3_CTSn           MPP(5, 0x2, 0, 0)
+#define MPP5_SDIO1_WP           MPP(5, 0x3, 0, 0)
+#define MPP5_SPI_1_CS           MPP(5, 0x4, 0, 0)
+
+#define MPP6_GPIO6              MPP(6, 0x0, 1, 1)
+#define MPP6_UA3_TXD            MPP(6, 0x2, 0, 0)
+#define MPP6_SDIO1_BUS_POWER    MPP(6, 0x3, 0, 0)
+#define MPP6_SPI_1_MOSI         MPP(6, 0x4, 0, 0)
+
+#define MPP7_GPIO7              MPP(7, 0x0, 1, 1)
+#define MPP7_UA3_RXD            MPP(7, 0x2, 0, 0)
+#define MPP7_SDIO1_LED_CTRL     MPP(7, 0x3, 0, 0)
+#define MPP7_SPI_1_SCK          MPP(7, 0x4, 0, 0)
+
+#define MPP8_GPIO8              MPP(8, 0x0, 1, 1)
+#define MPP8_WD_RST_OUT         MPP(8, 0x1, 0, 0)
+
+#define MPP9_GPIO9              MPP(9, 0x0, 1, 1)
+#define MPP9_PEX1_CLKREQn       MPP(9, 0x5, 0, 0)
+
+#define MPP10_GPIO10            MPP(10, 0x0, 1, 1)
+#define MPP10_SSP_SCLK          MPP(10, 0x5, 0, 0)
+
+#define MPP11_GPIO11            MPP(11, 0x0, 1, 1)
+#define MPP11_SATA_PRESENT      MPP(11, 0x1, 0, 0)
+#define MPP11_SATA_ACT          MPP(11, 0x2, 0, 0)
+#define MPP11_SDIO0_LED_CTRL    MPP(11, 0x3, 0, 0)
+#define MPP11_SDIO1_LED_CTRL    MPP(11, 0x4, 0, 0)
+#define MPP11_PEX0_CLKREQn      MPP(11, 0x5, 0, 0)
+
+#define MPP12_GPIO12            MPP(12, 0x0, 1, 1)
+#define MPP12_SATA_ACT          MPP(12, 0x1, 0, 0)
+#define MPP12_UA2_RTSn          MPP(12, 0x2, 0, 0)
+#define MPP12_AD0_I2S_EXT_MCLK  MPP(12, 0x3, 0, 0)
+#define MPP12_SDIO1_CD          MPP(12, 0x4, 0, 0)
+
+#define MPP13_GPIO13            MPP(13, 0x0, 1, 1)
+#define MPP13_UA2_CTSn          MPP(13, 0x2, 0, 0)
+#define MPP13_AD1_I2S_EXT_MCLK  MPP(13, 0x3, 0, 0)
+#define MPP13_SDIO1WP           MPP(13, 0x4, 0, 0)
+#define MPP13_SSP_EXTCLK        MPP(13, 0x5, 0, 0)
+
+#define MPP14_GPIO14            MPP(14, 0x0, 1, 1)
+#define MPP14_UA2_TXD           MPP(14, 0x2, 0, 0)
+#define MPP14_SDIO1_BUS_POWER   MPP(14, 0x4, 0, 0)
+#define MPP14_SSP_RXD           MPP(14, 0x5, 0, 0)
+
+#define MPP15_GPIO15            MPP(15, 0x0, 1, 1)
+#define MPP15_UA2_RXD           MPP(15, 0x2, 0, 0)
+#define MPP15_SDIO1_LED_CTRL    MPP(15, 0x4, 0, 0)
+#define MPP15_SSP_SFRM          MPP(15, 0x5, 0, 0)
+
+#define MPP16_GPIO16            MPP(16, 0x0, 1, 1)
+#define MPP16_UA3_RTSn          MPP(16, 0x2, 0, 0)
+#define MPP16_SDIO0_CD          MPP(16, 0x3, 0, 0)
+#define MPP16_SPI_LCD_CS1       MPP(16, 0x4, 0, 0)
+#define MPP16_AC97_SDATA_IN1    MPP(16, 0x5, 0, 0)
+
+#define MPP17_GPIO17            MPP(17, 0x0, 1, 1)
+#define MPP17_AC97_SYSCLK_OUT   MPP(17, 0x1, 0, 0)
+#define MPP17_UA3_CTSn          MPP(17, 0x2, 0, 0)
+#define MPP17_SDIO0_WP          MPP(17, 0x3, 0, 0)
+#define MPP17_TW_SDA2           MPP(17, 0x4, 0, 0)
+#define MPP17_AC97_SDATA_IN2    MPP(17, 0x5, 0, 0)
+
+#define MPP18_GPIO18            MPP(18, 0x0, 1, 1)
+#define MPP18_UA3_TXD           MPP(18, 0x2, 0, 0)
+#define MPP18_SDIO0_BUS_POWER   MPP(18, 0x3, 0, 0)
+#define MPP18_LCD0_PWM          MPP(18, 0x4, 0, 0)
+#define MPP18_AC_SDATA_IN3      MPP(18, 0x5, 0, 0)
+
+#define MPP19_GPIO19            MPP(19, 0x0, 1, 1)
+#define MPP19_UA3_RXD           MPP(19, 0x2, 0, 0)
+#define MPP19_SDIO0_LED_CTRL    MPP(19, 0x3, 0, 0)
+#define MPP19_TW_SCK2           MPP(19, 0x4, 0, 0)
+
+#define MPP20_GPIO20            MPP(20, 0x0, 1, 1)
+#define MPP20_AC97_SYSCLK_OUT   MPP(20, 0x1, 0, 0)
+#define MPP20_SPI_LCD_MISO      MPP(20, 0x2, 0, 0)
+#define MPP20_SDIO1_CD          MPP(20, 0x3, 0, 0)
+#define MPP20_SDIO0_CD          MPP(20, 0x5, 0, 0)
+#define MPP20_SPI_1_MISO        MPP(20, 0x6, 0, 0)
+
+#define MPP21_GPIO21            MPP(21, 0x0, 1, 1)
+#define MPP21_UA1_RTSn          MPP(21, 0x1, 0, 0)
+#define MPP21_SPI_LCD_CS0       MPP(21, 0x2, 0, 0)
+#define MPP21_SDIO1_WP          MPP(21, 0x3, 0, 0)
+#define MPP21_SSP_SFRM          MPP(21, 0x4, 0, 0)
+#define MPP21_SDIO0_WP          MPP(21, 0x5, 0, 0)
+#define MPP21_SPI_1_CS          MPP(21, 0x6, 0, 0)
+
+#define MPP22_GPIO22            MPP(22, 0x0, 1, 1)
+#define MPP22_UA1_CTSn          MPP(22, 0x1, 0, 0)
+#define MPP22_SPI_LCD_MOSI      MPP(22, 0x2, 0, 0)
+#define MPP22_SDIO1_BUS_POWER   MPP(22, 0x3, 0, 0)
+#define MPP22_SSP_TXD           MPP(22, 0x4, 0, 0)
+#define MPP22_SDIO0_BUS_POWER   MPP(22, 0x5, 0, 0)
+#define MPP22_SPI_1_MOSI        MPP(22, 0x6, 0, 0)
+
+#define MPP23_GPIO23            MPP(23, 0x0, 1, 1)
+#define MPP23_SPI_LCD_SCK       MPP(23, 0x2, 0, 0)
+#define MPP23_SDIO1_LED_CTRL    MPP(23, 0x3, 0, 0)
+#define MPP23_SSP_SCLK          MPP(23, 0x4, 0, 0)
+#define MPP23_SDIO0_LED_CTRL    MPP(23, 0x5, 0, 0)
+#define MPP23_SPI_1_SCK         MPP(23, 0x6, 0, 0)
+
+#define MPP_MAX                 23
+
+#define MPP_GRP(_grp, _mode)    MPP((_grp), (_mode), 0, 0)
 
 /* for MPP groups _num is a group index */
 enum dove_mpp_grp_idx {
@@ -181,40 +153,44 @@ enum dove_mpp_grp_idx {
         MPP_46_51 = 1,
         MPP_58_61 = 5,
         MPP_62_63 = 4,
+        MPP_GRP_MAX = 5,
 };
 
-#define MPP24_39_GPIO           MPP_GRP(MPP_24_39, 0x1)
-#define MPP24_39_CAM            MPP_GRP(MPP_24_39, 0x0)
+#define MPP_GRP_24_39_GPIO              MPP_GRP(MPP_24_39, 0x1)
+#define MPP_GRP_24_39_CAM               MPP_GRP(MPP_24_39, 0x0)
 
-#define MPP40_45_GPIO           MPP_GRP(MPP_40_45, 0x1)
-#define MPP40_45_SD0            MPP_GRP(MPP_40_45, 0x0)
+#define MPP_GRP_40_45_GPIO              MPP_GRP(MPP_40_45, 0x1)
+#define MPP_GRP_40_45_SD0               MPP_GRP(MPP_40_45, 0x0)
 
-#define MPP46_51_GPIO           MPP_GRP(MPP_46_51, 0x1)
-#define MPP46_51_SD1            MPP_GRP(MPP_46_51, 0x0)
+#define MPP_GRP_46_51_GPIO              MPP_GRP(MPP_46_51, 0x1)
+#define MPP_GRP_46_51_SD1               MPP_GRP(MPP_46_51, 0x0)
 
-#define MPP58_61_GPIO           MPP_GRP(MPP_58_61, 0x1)
-#define MPP58_61_SPI            MPP_GRP(MPP_58_61, 0x0)
+#define MPP_GRP_58_61_GPIO              MPP_GRP(MPP_58_61, 0x1)
+#define MPP_GRP_58_61_SPI               MPP_GRP(MPP_58_61, 0x0)
 
-#define MPP62_63_GPIO           MPP_GRP(MPP_62_63, 0x1)
-#define MPP62_63_UA1            MPP_GRP(MPP_62_63, 0x0)
+#define MPP_GRP_62_63_GPIO              MPP_GRP(MPP_62_63, 0x1)
+#define MPP_GRP_62_63_UA1               MPP_GRP(MPP_62_63, 0x0)
 
 /* The MPP[64:71] control differs from other groups */
-#define MPP64_71_GPO            MPP_GRP_NFC(0x1)
-#define MPP64_71_NFC            MPP_GRP_NFC(0x0)
+#define MPP_GRP_NFC_64_71_GPO           0x1
+#define MPP_GRP_NFC_64_71_NFC           0x0
 
 /*
  * The MPP[52:57] functionality is encoded by 4 bits in different
  * registers. The _num field in this case encodes those bits in
  * correspodence with Table 135 of 88AP510 Functional specification
  */
-#define MPP52_57_AU1            MPP_GRP_AU1(0x0)
-#define MPP52_57_AU1_GPIO57     MPP_GRP_AU1(0x2)
-#define MPP52_57_GPIO           MPP_GRP_AU1(0xa)
-#define MPP52_57_TW_GPIO        MPP_GRP_AU1(0xb)
-#define MPP52_57_AU1_SSP        MPP_GRP_AU1(0xc)
-#define MPP52_57_SSP_GPIO       MPP_GRP_AU1(0xe)
-#define MPP52_57_SSP_TW         MPP_GRP_AU1(0xf)
-
-void dove_mpp_conf(unsigned int *mpp_list);
+#define MPP_GRP_AU1_52_57_AU1           0x0
+#define MPP_GRP_AU1_52_57_AU1_GPIO57    0x2
+#define MPP_GRP_AU1_52_57_GPIO          0xa
+#define MPP_GRP_AU1_52_57_TW_GPIO       0xb
+#define MPP_GRP_AU1_52_57_AU1_SSP       0xc
+#define MPP_GRP_AU1_52_57_SSP_GPIO      0xe
+#define MPP_GRP_AU1_52_57_SSP_TW        0xf
+
+void dove_mpp_conf(unsigned int *mpp_list,
+                   unsigned int *mpp_grp_list,
+                   unsigned int grp_au1_52_57,
+                   unsigned int grp_nfc_64_71);
 
 #endif  /* __ARCH_DOVE_MPP_CODED_H */
diff --git a/arch/arm/mach-exynos4/irq-combiner.c b/arch/arm/mach-exynos4/irq-combiner.c
index f488b66d680..5a2758ab055 100644
--- a/arch/arm/mach-exynos4/irq-combiner.c
+++ b/arch/arm/mach-exynos4/irq-combiner.c
@@ -59,8 +59,7 @@ static void combiner_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
         unsigned int cascade_irq, combiner_irq;
         unsigned long status;
 
-        /* primary controller ack'ing */
-        chip->irq_ack(&desc->irq_data);
+        chained_irq_enter(chip, desc);
 
         spin_lock(&irq_controller_lock);
         status = __raw_readl(chip_data->base + COMBINER_INT_STATUS);
@@ -79,8 +78,7 @@ static void combiner_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
                 generic_handle_irq(cascade_irq);
 
  out:
-        /* primary controller unmasking */
-        chip->irq_unmask(&desc->irq_data);
+        chained_irq_exit(chip, desc);
 }
 
 static struct irq_chip combiner_chip = {
diff --git a/arch/arm/mach-gemini/include/mach/uncompress.h b/arch/arm/mach-gemini/include/mach/uncompress.h
index 5483f61a806..0efa2624723 100644
--- a/arch/arm/mach-gemini/include/mach/uncompress.h
+++ b/arch/arm/mach-gemini/include/mach/uncompress.h
@@ -16,7 +16,7 @@
 #include <linux/serial_reg.h>
 #include <mach/hardware.h>
 
-static volatile unsigned long *UART = (unsigned long *)GEMINI_UART_BASE;
+static volatile unsigned long * const UART = (unsigned long *)GEMINI_UART_BASE;
 
 /*
  * The following code assumes the serial port has already been
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index 56b930a1344..59c97a33113 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -1,5 +1,15 @@
 config IMX_HAVE_DMA_V1
         bool
+#
+# ARCH_MX31 and ARCH_MX35 are left for compatibility
+# Some usages assume that having one of them implies not having (e.g.) ARCH_MX2.
+# To easily distinguish good and reviewed from unreviewed usages new (and IMHO
+# more sensible) names are used: SOC_IMX31 and SOC_IMX35
+config ARCH_MX31
+        bool
+
+config ARCH_MX35
+        bool
 
 config SOC_IMX1
         bool
@@ -31,6 +41,24 @@ config SOC_IMX27
         select IMX_HAVE_IOMUX_V1
         select MXC_AVIC
 
+config SOC_IMX31
+        bool
+        select CPU_V6
+        select IMX_HAVE_PLATFORM_MXC_RNGA
+        select ARCH_MXC_AUDMUX_V2
+        select ARCH_MX31
+        select MXC_AVIC
+
+config SOC_IMX35
+        bool
+        select CPU_V6
+        select ARCH_MXC_IOMUX_V3
+        select ARCH_MXC_AUDMUX_V2
+        select HAVE_EPIT
+        select ARCH_MX35
+        select MXC_AVIC
+
+
 if ARCH_MX1
 
 comment "MX1 platforms:"
@@ -40,6 +68,7 @@ config MACH_MXLADS
 config ARCH_MX1ADS
         bool "MX1ADS platform"
         select MACH_MXLADS
+        select SOC_IMX1
         select IMX_HAVE_PLATFORM_IMX_I2C
         select IMX_HAVE_PLATFORM_IMX_UART
         help
@@ -51,6 +80,13 @@ config MACH_SCB9328
         help
           Say Y here if you are using a Synertronixx scb9328 board
 
+config MACH_APF9328
+        bool "APF9328"
+        select SOC_IMX1
+        select IMX_HAVE_PLATFORM_IMX_UART
+        help
+          Say Yes here if you are using the Armadeus APF9328 development board
+
 endif
 
 if ARCH_MX2
@@ -129,6 +165,7 @@ choice
 
 config MACH_EUKREA_MBIMXSD25_BASEBOARD
         bool "Eukrea MBIMXSD development board"
+        select IMX_HAVE_PLATFORM_GPIO_KEYS
         select IMX_HAVE_PLATFORM_IMX_SSI
         help
           This adds board specific devices that can be found on Eukrea's
@@ -254,6 +291,7 @@ config MACH_MX27_3DS
 config MACH_IMX27_VISSTRIM_M10
         bool "Vista Silicon i.MX27 Visstrim_m10"
         select SOC_IMX27
+        select IMX_HAVE_PLATFORM_GPIO_KEYS
         select IMX_HAVE_PLATFORM_IMX_I2C
         select IMX_HAVE_PLATFORM_IMX_SSI
         select IMX_HAVE_PLATFORM_IMX_UART
@@ -314,3 +352,251 @@ config MACH_IMX27IPCAM
           configurations for the board and its peripherals.
 
 endif
+
+if ARCH_MX3
+
+comment "MX31 platforms:"
+
+config MACH_MX31ADS
+        bool "Support MX31ADS platforms"
+        select SOC_IMX31
+        select IMX_HAVE_PLATFORM_IMX_I2C
+        select IMX_HAVE_PLATFORM_IMX_SSI
+        select IMX_HAVE_PLATFORM_IMX_UART
+        default y
+        help
+          Include support for MX31ADS platform. This includes specific
+          configurations for the board and its peripherals.
+
+config MACH_MX31ADS_WM1133_EV1
+        bool "Support Wolfson Microelectronics 1133-EV1 module"
+        depends on MACH_MX31ADS
+        depends on MFD_WM8350_I2C
+        depends on REGULATOR_WM8350
+        select MFD_WM8350_CONFIG_MODE_0
+        select MFD_WM8352_CONFIG_MODE_0
+        help
+          Include support for the Wolfson Microelectronics 1133-EV1 PMU
+          and audio module for the MX31ADS platform.
+
+config MACH_MX31LILLY
+        bool "Support MX31 LILLY-1131 platforms (INCO startec)"
+        select SOC_IMX31
+        select IMX_HAVE_PLATFORM_IMX_UART
+        select IMX_HAVE_PLATFORM_IPU_CORE
+        select IMX_HAVE_PLATFORM_MXC_EHCI
+        select IMX_HAVE_PLATFORM_MXC_MMC
+        select IMX_HAVE_PLATFORM_SPI_IMX
+        select MXC_ULPI if USB_ULPI
+        help
+          Include support for mx31 based LILLY1131 modules. This includes
+          specific configurations for the board and its peripherals.
+
+config MACH_MX31LITE
+        bool "Support MX31 LITEKIT (LogicPD)"
+        select SOC_IMX31
+        select MXC_ULPI if USB_ULPI
+        select IMX_HAVE_PLATFORM_IMX2_WDT
+        select IMX_HAVE_PLATFORM_IMX_UART
+        select IMX_HAVE_PLATFORM_MXC_EHCI
+        select IMX_HAVE_PLATFORM_MXC_MMC
+        select IMX_HAVE_PLATFORM_MXC_NAND
+        select IMX_HAVE_PLATFORM_MXC_RTC
+        select IMX_HAVE_PLATFORM_SPI_IMX
+        help
+          Include support for MX31 LITEKIT platform. This includes specific
+          configurations for the board and its peripherals.
+
+config MACH_PCM037
+        bool "Support Phytec pcm037 (i.MX31) platforms"
+        select SOC_IMX31
+        select IMX_HAVE_PLATFORM_FSL_USB2_UDC
+        select IMX_HAVE_PLATFORM_IMX2_WDT
+        select IMX_HAVE_PLATFORM_IMX_I2C
+        select IMX_HAVE_PLATFORM_IMX_UART
+        select IMX_HAVE_PLATFORM_IPU_CORE
+        select IMX_HAVE_PLATFORM_MXC_EHCI
+        select IMX_HAVE_PLATFORM_MXC_MMC
+        select IMX_HAVE_PLATFORM_MXC_NAND
+        select IMX_HAVE_PLATFORM_MXC_W1
+        select MXC_ULPI if USB_ULPI
+        help
+          Include support for Phytec pcm037 platform. This includes
+          specific configurations for the board and its peripherals.
+
+config MACH_PCM037_EET
+        bool "Support pcm037 EET board extensions"
+        depends on MACH_PCM037
+        select IMX_HAVE_PLATFORM_GPIO_KEYS
+        select IMX_HAVE_PLATFORM_SPI_IMX
+        help
+          Add support for PCM037 EET baseboard extensions. If you are using the
+          OLED display with EET, use "video=mx3fb:CMEL-OLED" kernel
+          command-line parameter.
+
+config MACH_MX31_3DS
+        bool "Support MX31PDK (3DS)"
+        select SOC_IMX31
+        select MXC_DEBUG_BOARD
+        select IMX_HAVE_PLATFORM_FSL_USB2_UDC
+        select IMX_HAVE_PLATFORM_IMX2_WDT
+        select IMX_HAVE_PLATFORM_IMX_I2C
+        select IMX_HAVE_PLATFORM_IMX_KEYPAD
+        select IMX_HAVE_PLATFORM_IMX_UART
+        select IMX_HAVE_PLATFORM_IPU_CORE
+        select IMX_HAVE_PLATFORM_MXC_EHCI
+        select IMX_HAVE_PLATFORM_MXC_NAND
+        select IMX_HAVE_PLATFORM_SPI_IMX
+        select MXC_ULPI if USB_ULPI
+        help
+          Include support for MX31PDK (3DS) platform. This includes specific
+          configurations for the board and its peripherals.
+
+config MACH_MX31_3DS_MXC_NAND_USE_BBT
+        bool "Make the MXC NAND driver use the in flash Bad Block Table"
+        depends on MACH_MX31_3DS
+        depends on MTD_NAND_MXC
+        help
+          Enable this if you want that the MXC NAND driver uses the in flash
+          Bad Block Table to know what blocks are bad instead of scanning the
+          entire flash looking for bad block markers.
+
+config MACH_MX31MOBOARD
+        bool "Support mx31moboard platforms (EPFL Mobots group)"
+        select SOC_IMX31
+        select IMX_HAVE_PLATFORM_FSL_USB2_UDC
+        select IMX_HAVE_PLATFORM_IMX_I2C
+        select IMX_HAVE_PLATFORM_IMX_UART
+        select IMX_HAVE_PLATFORM_IPU_CORE
+        select IMX_HAVE_PLATFORM_MXC_EHCI
+        select IMX_HAVE_PLATFORM_MXC_MMC
+        select IMX_HAVE_PLATFORM_SPI_IMX
+        select MXC_ULPI if USB_ULPI
+        help
+          Include support for mx31moboard platform. This includes specific
+          configurations for the board and its peripherals.
+
+config MACH_QONG
+        bool "Support Dave/DENX QongEVB-LITE platform"
+        select SOC_IMX31
+        select IMX_HAVE_PLATFORM_IMX_UART
+        help
+          Include support for Dave/DENX QongEVB-LITE platform. This includes
+          specific configurations for the board and its peripherals.
+
+config MACH_ARMADILLO5X0
+        bool "Support Atmark Armadillo-500 Development Base Board"
+        select SOC_IMX31
+        select IMX_HAVE_PLATFORM_GPIO_KEYS
+        select IMX_HAVE_PLATFORM_IMX_I2C
+        select IMX_HAVE_PLATFORM_IMX_UART
+        select IMX_HAVE_PLATFORM_IPU_CORE
+        select IMX_HAVE_PLATFORM_MXC_EHCI
+        select IMX_HAVE_PLATFORM_MXC_MMC
+        select IMX_HAVE_PLATFORM_MXC_NAND
+        select MXC_ULPI if USB_ULPI
+        help
+          Include support for Atmark Armadillo-500 platform. This includes
+          specific configurations for the board and its peripherals.
+
+config MACH_KZM_ARM11_01
+        bool "Support KZM-ARM11-01(Kyoto Microcomputer)"
+        select SOC_IMX31
+        select IMX_HAVE_PLATFORM_IMX_UART
+        help
+          Include support for KZM-ARM11-01. This includes specific
+          configurations for the board and its peripherals.
+
+config MACH_BUG
+        bool "Support Buglabs BUGBase platform"
+        select SOC_IMX31
+        select IMX_HAVE_PLATFORM_IMX_UART
+        default y
+        help
+          Include support for BUGBase 1.3 platform. This includes specific
+          configurations for the board and its peripherals.
+
+comment "MX35 platforms:"
+
+config MACH_PCM043
+        bool "Support Phytec pcm043 (i.MX35) platforms"
+        select SOC_IMX35
+        select IMX_HAVE_PLATFORM_FLEXCAN
+        select IMX_HAVE_PLATFORM_FSL_USB2_UDC
+        select IMX_HAVE_PLATFORM_IMX2_WDT
+        select IMX_HAVE_PLATFORM_IMX_I2C
+        select IMX_HAVE_PLATFORM_IMX_SSI
+        select IMX_HAVE_PLATFORM_IMX_UART
+        select IMX_HAVE_PLATFORM_IPU_CORE
+        select IMX_HAVE_PLATFORM_MXC_EHCI
+        select IMX_HAVE_PLATFORM_MXC_NAND
+        select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
+        select MXC_ULPI if USB_ULPI
+        help
+          Include support for Phytec pcm043 platform. This includes
+          specific configurations for the board and its peripherals.
+
+config MACH_MX35_3DS
+        bool "Support MX35PDK platform"
+        select SOC_IMX35
+        select MXC_DEBUG_BOARD
+        select IMX_HAVE_PLATFORM_FSL_USB2_UDC
+        select IMX_HAVE_PLATFORM_IMX2_WDT
+        select IMX_HAVE_PLATFORM_IMX_I2C
+        select IMX_HAVE_PLATFORM_IMX_UART
+        select IMX_HAVE_PLATFORM_MXC_EHCI
+        select IMX_HAVE_PLATFORM_MXC_NAND
+        select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
+        help
+          Include support for MX35PDK platform. This includes specific
+          configurations for the board and its peripherals.
+
+config MACH_EUKREA_CPUIMX35
+        bool "Support Eukrea CPUIMX35 Platform"
+        select SOC_IMX35
+        select IMX_HAVE_PLATFORM_FLEXCAN
+        select IMX_HAVE_PLATFORM_FSL_USB2_UDC
+        select IMX_HAVE_PLATFORM_IMX2_WDT
+        select IMX_HAVE_PLATFORM_IMX_I2C
+        select IMX_HAVE_PLATFORM_IMX_UART
+        select IMX_HAVE_PLATFORM_MXC_EHCI
+        select IMX_HAVE_PLATFORM_MXC_NAND
+        select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
+        select MXC_ULPI if USB_ULPI
+        help
+          Include support for Eukrea CPUIMX35 platform. This includes
+          specific configurations for the board and its peripherals.
+
+choice
+        prompt "Baseboard"
+        depends on MACH_EUKREA_CPUIMX35
+        default MACH_EUKREA_MBIMXSD35_BASEBOARD
+
+config MACH_EUKREA_MBIMXSD35_BASEBOARD
+        bool "Eukrea MBIMXSD development board"
+        select IMX_HAVE_PLATFORM_GPIO_KEYS
+        select IMX_HAVE_PLATFORM_IMX_SSI
+        select IMX_HAVE_PLATFORM_IPU_CORE
+        help
+          This adds board specific devices that can be found on Eukrea's
+          MBIMXSD evaluation board.
+
+endchoice
+
+config MACH_VPR200
+        bool "Support VPR200 platform"
+        select SOC_IMX35
+        select IMX_HAVE_PLATFORM_FSL_USB2_UDC
+        select IMX_HAVE_PLATFORM_GPIO_KEYS
+        select IMX_HAVE_PLATFORM_IMX2_WDT
+        select IMX_HAVE_PLATFORM_IMX_UART
+        select IMX_HAVE_PLATFORM_IMX_I2C
+        select IMX_HAVE_PLATFORM_IPU_CORE
+        select IMX_HAVE_PLATFORM_MXC_EHCI
+        select IMX_HAVE_PLATFORM_MXC_NAND
+        select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
+        help
+          Include support for VPR200 platform. This includes specific
+          configurations for the board and its peripherals.
+
+endif
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index b85794d2799..e9eb36dad88 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -1,9 +1,3 @@
-#
-# Makefile for the linux kernel.
-#
-
-# Object file lists.
-
 obj-$(CONFIG_IMX_HAVE_DMA_V1) += dma-v1.o
 
 obj-$(CONFIG_ARCH_MX1) += clock-imx1.o mm-imx1.o
@@ -14,18 +8,27 @@ obj-$(CONFIG_ARCH_MX25) += clock-imx25.o mm-imx25.o ehci-imx25.o
 obj-$(CONFIG_MACH_MX27) += cpu-imx27.o pm-imx27.o
 obj-$(CONFIG_MACH_MX27) += clock-imx27.o mm-imx27.o ehci-imx27.o
 
+obj-$(CONFIG_SOC_IMX31) += mm-imx31.o cpu-imx31.o clock-imx31.o iomux-imx31.o ehci-imx31.o
+obj-$(CONFIG_SOC_IMX35) += mm-imx35.o cpu-imx35.o clock-imx35.o ehci-imx35.o
+obj-$(CONFIG_CACHE_L2X0) += cache-l2x0.o
+
 # Support for CMOS sensor interface
-obj-$(CONFIG_MX1_VIDEO) += mx1-camera-fiq.o mx1-camera-fiq-ksym.o
+obj-$(CONFIG_MX1_VIDEO) += mx1-camera-fiq.o mx1-camera-fiq-ksym.o
 
+# i.MX1 based machines
 obj-$(CONFIG_ARCH_MX1ADS) += mach-mx1ads.o
 obj-$(CONFIG_MACH_SCB9328) += mach-scb9328.o
+obj-$(CONFIG_MACH_APF9328) += mach-apf9328.o
 
+# i.MX21 based machines
 obj-$(CONFIG_MACH_MX21ADS) += mach-mx21ads.o
 
+# i.MX25 based machines
 obj-$(CONFIG_MACH_MX25_3DS) += mach-mx25_3ds.o
 obj-$(CONFIG_MACH_EUKREA_CPUIMX25) += mach-eukrea_cpuimx25.o
 obj-$(CONFIG_MACH_EUKREA_MBIMXSD25_BASEBOARD) += eukrea_mbimxsd25-baseboard.o
 
+# i.MX27 based machines
 obj-$(CONFIG_MACH_MX27ADS) += mach-mx27ads.o
 obj-$(CONFIG_MACH_PCM038) += mach-pcm038.o
 obj-$(CONFIG_MACH_PCM970_BASEBOARD) += pcm970-baseboard.o
@@ -37,3 +40,24 @@ obj-$(CONFIG_MACH_EUKREA_MBIMX27_BASEBOARD) += eukrea_mbimx27-baseboard.o
 obj-$(CONFIG_MACH_PCA100) += mach-pca100.o
 obj-$(CONFIG_MACH_MXT_TD60) += mach-mxt_td60.o
 obj-$(CONFIG_MACH_IMX27IPCAM) += mach-imx27ipcam.o
+
+# i.MX31 based machines
+obj-$(CONFIG_MACH_MX31ADS) += mach-mx31ads.o
+obj-$(CONFIG_MACH_MX31LILLY) += mach-mx31lilly.o mx31lilly-db.o
+obj-$(CONFIG_MACH_MX31LITE) += mach-mx31lite.o mx31lite-db.o
+obj-$(CONFIG_MACH_PCM037) += mach-pcm037.o
+obj-$(CONFIG_MACH_PCM037_EET) += mach-pcm037_eet.o
+obj-$(CONFIG_MACH_MX31_3DS) += mach-mx31_3ds.o
+obj-$(CONFIG_MACH_MX31MOBOARD) += mach-mx31moboard.o mx31moboard-devboard.o \
+                mx31moboard-marxbot.o mx31moboard-smartbot.o
+obj-$(CONFIG_MACH_QONG) += mach-qong.o
+obj-$(CONFIG_MACH_ARMADILLO5X0) += mach-armadillo5x0.o
+obj-$(CONFIG_MACH_KZM_ARM11_01) += mach-kzm_arm11_01.o
+obj-$(CONFIG_MACH_BUG) += mach-bug.o
+
+# i.MX35 based machines
+obj-$(CONFIG_MACH_PCM043) += mach-pcm043.o
+obj-$(CONFIG_MACH_MX35_3DS) += mach-mx35_3ds.o
+obj-$(CONFIG_MACH_EUKREA_CPUIMX35) += mach-cpuimx35.o
+obj-$(CONFIG_MACH_EUKREA_MBIMXSD35_BASEBOARD) += eukrea_mbimxsd35-baseboard.o
+obj-$(CONFIG_MACH_VPR200) += mach-vpr200.o
diff --git a/arch/arm/mach-imx/Makefile.boot b/arch/arm/mach-imx/Makefile.boot
index 3953d60bff0..ebee18b3884 100644
--- a/arch/arm/mach-imx/Makefile.boot
+++ b/arch/arm/mach-imx/Makefile.boot
@@ -13,3 +13,7 @@ initrd_phys-$(CONFIG_ARCH_MX25)	:= 0x80800000
 zreladdr-$(CONFIG_MACH_MX27)    := 0xA0008000
 params_phys-$(CONFIG_MACH_MX27) := 0xA0000100
 initrd_phys-$(CONFIG_MACH_MX27) := 0xA0800000
+
+zreladdr-$(CONFIG_ARCH_MX3)     := 0x80008000
+params_phys-$(CONFIG_ARCH_MX3)  := 0x80000100
+initrd_phys-$(CONFIG_ARCH_MX3)  := 0x80800000
diff --git a/arch/arm/mach-imx/cache-l2x0.c b/arch/arm/mach-imx/cache-l2x0.c
new file mode 100644
index 00000000000..69d1322add3
--- /dev/null
+++ b/arch/arm/mach-imx/cache-l2x0.c
@@ -0,0 +1,56 @@
+/*
+ * Copyright (C) 2009-2010 Pengutronix
+ * Sascha Hauer <s.hauer@pengutronix.de>
+ * Juergen Beisert <j.beisert@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify it under
+ * the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation.
+ */
+
+#include <linux/init.h>
+#include <linux/err.h>
+#include <linux/kernel.h>
+
+#include <asm/hardware/cache-l2x0.h>
+
+#include <mach/hardware.h>
+
+static int mxc_init_l2x0(void)
+{
+        void __iomem *l2x0_base;
+        void __iomem *clkctl_base;
+
+        if (!cpu_is_mx31() && !cpu_is_mx35())
+                return 0;
+
+/*
+ * First of all, we must repair broken chip settings. There are some
+ * i.MX35 CPUs in the wild, comming with bogus L2 cache settings. These
+ * misconfigured CPUs will run amok immediately when the L2 cache gets enabled.
+ * Workaraound is to setup the correct register setting prior enabling the
+ * L2 cache. This should not hurt already working CPUs, as they are using the
+ * same value.
+ */
+#define L2_MEM_VAL 0x10
+
+        clkctl_base = ioremap(MX35_CLKCTL_BASE_ADDR, 4096);
+        if (clkctl_base != NULL) {
+                writel(0x00000515, clkctl_base + L2_MEM_VAL);
+                iounmap(clkctl_base);
+        } else {
+                pr_err("L2 cache: Cannot fix timing. Trying to continue without\n");
+        }
+
+        l2x0_base = ioremap(MX3x_L2CC_BASE_ADDR, 4096);
+        if (IS_ERR(l2x0_base)) {
+                printk(KERN_ERR "remapping L2 cache area failed with %ld\n",
+                                PTR_ERR(l2x0_base));
+                return 0;
+        }
+
+        l2x0_init(l2x0_base, 0x00030024, 0x00000000);
+
+        return 0;
+}
+arch_initcall(mxc_init_l2x0);
diff --git a/arch/arm/mach-mx3/clock-imx31.c b/arch/arm/mach-imx/clock-imx31.c
index d423cac8cab..25f343fca2b 100644
--- a/arch/arm/mach-mx3/clock-imx31.c
+++ b/arch/arm/mach-imx/clock-imx31.c
@@ -32,7 +32,7 @@
 #include <mach/mx31.h>
 #include <mach/common.h>
 
-#include "crm_regs.h"
+#include "crmregs-imx31.h"
 
 #define PRE_DIV_MIN_FREQ    10000000 /* Minimum Frequency after Predivider */
 
@@ -627,4 +627,3 @@ int __init mx31_clocks_init(unsigned long fref)
 
         return 0;
 }
-
diff --git a/arch/arm/mach-mx3/clock-imx35.c b/arch/arm/mach-imx/clock-imx35.c
index 448a038cd1e..5a4cc1ea405 100644
--- a/arch/arm/mach-mx3/clock-imx35.c
+++ b/arch/arm/mach-imx/clock-imx35.c
@@ -547,4 +547,3 @@ int __init mx35_clocks_init()
 
         return 0;
 }
-
diff --git a/arch/arm/mach-mx3/cpu.c b/arch/arm/mach-imx/cpu-imx31.c
index d1d339576fd..a3780700a88 100644
--- a/arch/arm/mach-mx3/cpu.c
+++ b/arch/arm/mach-imx/cpu-imx31.c
@@ -1,5 +1,5 @@
 /*
- * MX3 CPU type detection
+ * MX31 CPU type detection
  *
  * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de>
  *
@@ -17,14 +17,12 @@
 unsigned int mx31_cpu_rev;
 EXPORT_SYMBOL(mx31_cpu_rev);
 
-struct mx3_cpu_type {
+static struct {
         u8 srev;
         const char *name;
         const char *v;
         unsigned int rev;
-};
-
-static struct mx3_cpu_type mx31_cpu_type[] __initdata = {
+} mx31_cpu_type[] __initdata = {
         { .srev = 0x00, .name = "i.MX31(L)", .v = "1.0",  .rev = IMX_CHIP_REVISION_1_0  },
         { .srev = 0x10, .name = "i.MX31",    .v = "1.1",  .rev = IMX_CHIP_REVISION_1_1  },
         { .srev = 0x11, .name = "i.MX31L",   .v = "1.1",  .rev = IMX_CHIP_REVISION_1_1  },
@@ -57,33 +55,3 @@ void __init mx31_read_cpu_rev(void)
 
         printk(KERN_WARNING "Unknown CPU identifier. srev = %02x\n", srev);
 }
-
-unsigned int mx35_cpu_rev;
-EXPORT_SYMBOL(mx35_cpu_rev);
-
-void __init mx35_read_cpu_rev(void)
-{
-        u32 rev;
-        char *srev;
-
-        rev = __raw_readl(MX35_IO_ADDRESS(MX35_IIM_BASE_ADDR + MXC_IIMSREV));
-        switch (rev) {
-        case 0x00:
-                mx35_cpu_rev = IMX_CHIP_REVISION_1_0;
-                srev = "1.0";
-                break;
-        case 0x10:
-                mx35_cpu_rev = IMX_CHIP_REVISION_2_0;
-                srev = "2.0";
-                break;
-        case 0x11:
-                mx35_cpu_rev = IMX_CHIP_REVISION_2_1;
-                srev = "2.1";
-                break;
-        default:
-                mx35_cpu_rev = IMX_CHIP_REVISION_UNKNOWN;
-                srev = "unknown";
-        }
-
-        printk(KERN_INFO "CPU identified as i.MX35, silicon rev %s\n", srev);
-}
diff --git a/arch/arm/mach-imx/cpu-imx35.c b/arch/arm/mach-imx/cpu-imx35.c
new file mode 100644
index 00000000000..6637cd819ec
--- /dev/null
+++ b/arch/arm/mach-imx/cpu-imx35.c
@@ -0,0 +1,44 @@
+/*
+ * MX35 CPU type detection
+ *
+ * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+#include <linux/module.h>
+#include <linux/io.h>
+#include <mach/hardware.h>
+#include <mach/iim.h>
+
+unsigned int mx35_cpu_rev;
+EXPORT_SYMBOL(mx35_cpu_rev);
+
+void __init mx35_read_cpu_rev(void)
+{
+        u32 rev;
+        char *srev;
+
+        rev = __raw_readl(MX35_IO_ADDRESS(MX35_IIM_BASE_ADDR + MXC_IIMSREV));
+        switch (rev) {
+        case 0x00:
+                mx35_cpu_rev = IMX_CHIP_REVISION_1_0;
+                srev = "1.0";
+                break;
+        case 0x10:
+                mx35_cpu_rev = IMX_CHIP_REVISION_2_0;
+                srev = "2.0";
+                break;
+        case 0x11:
+                mx35_cpu_rev = IMX_CHIP_REVISION_2_1;
+                srev = "2.1";
+                break;
+        default:
+                mx35_cpu_rev = IMX_CHIP_REVISION_UNKNOWN;
+                srev = "unknown";
+        }
+
+        printk(KERN_INFO "CPU identified as i.MX35, silicon rev %s\n", srev);
+}
diff --git a/arch/arm/mach-mx3/crm_regs.h b/arch/arm/mach-imx/crmregs-imx31.h
index 37a8a07beda..37a8a07beda 100644
--- a/arch/arm/mach-mx3/crm_regs.h
+++ b/arch/arm/mach-imx/crmregs-imx31.h
diff --git a/arch/arm/mach-imx/devices-imx1.h b/arch/arm/mach-imx/devices-imx1.h
index da593657ff3..3aad1e70de9 100644
--- a/arch/arm/mach-imx/devices-imx1.h
+++ b/arch/arm/mach-imx/devices-imx1.h
@@ -9,21 +9,21 @@
 #include <mach/mx1.h>
 #include <mach/devices-common.h>
 
-extern const struct imx_imx_fb_data imx1_imx_fb_data __initconst;
+extern const struct imx_imx_fb_data imx1_imx_fb_data;
 #define imx1_add_imx_fb(pdata) \
     imx_add_imx_fb(&imx1_imx_fb_data, pdata)
 
-extern const struct imx_imx_i2c_data imx1_imx_i2c_data __initconst;
+extern const struct imx_imx_i2c_data imx1_imx_i2c_data;
 #define imx1_add_imx_i2c(pdata)         \
         imx_add_imx_i2c(&imx1_imx_i2c_data, pdata)
 
-extern const struct imx_imx_uart_3irq_data imx1_imx_uart_data[] __initconst;
+extern const struct imx_imx_uart_3irq_data imx1_imx_uart_data[];
 #define imx1_add_imx_uart(id, pdata)    \
         imx_add_imx_uart_3irq(&imx1_imx_uart_data[id], pdata)
 #define imx1_add_imx_uart0(pdata)       imx1_add_imx_uart(0, pdata)
 #define imx1_add_imx_uart1(pdata)       imx1_add_imx_uart(1, pdata)
 
-extern const struct imx_spi_imx_data imx1_cspi_data[] __initconst;
+extern const struct imx_spi_imx_data imx1_cspi_data[];
 #define imx1_add_cspi(id, pdata)   \
         imx_add_spi_imx(&imx1_cspi_data[id], pdata)
 
diff --git a/arch/arm/mach-imx/devices-imx21.h b/arch/arm/mach-imx/devices-imx21.h
index 16744d2d9b8..2628e0c474d 100644
--- a/arch/arm/mach-imx/devices-imx21.h
+++ b/arch/arm/mach-imx/devices-imx21.h
@@ -9,31 +9,31 @@
 #include <mach/mx21.h>
 #include <mach/devices-common.h>
 
-extern const struct imx_imx21_hcd_data imx21_imx21_hcd_data __initconst;
+extern const struct imx_imx21_hcd_data imx21_imx21_hcd_data;
 #define imx21_add_imx21_hcd(pdata)      \
         imx_add_imx21_hcd(&imx21_imx21_hcd_data, pdata)
 
-extern const struct imx_imx2_wdt_data imx21_imx2_wdt_data __initconst;
+extern const struct imx_imx2_wdt_data imx21_imx2_wdt_data;
 #define imx21_add_imx2_wdt(pdata)       \
         imx_add_imx2_wdt(&imx21_imx2_wdt_data)
 
-extern const struct imx_imx_fb_data imx21_imx_fb_data __initconst;
+extern const struct imx_imx_fb_data imx21_imx_fb_data;
 #define imx21_add_imx_fb(pdata) \
         imx_add_imx_fb(&imx21_imx_fb_data, pdata)
 
-extern const struct imx_imx_i2c_data imx21_imx_i2c_data __initconst;
+extern const struct imx_imx_i2c_data imx21_imx_i2c_data;
 #define imx21_add_imx_i2c(pdata)        \
         imx_add_imx_i2c(&imx21_imx_i2c_data, pdata)
 
-extern const struct imx_imx_keypad_data imx21_imx_keypad_data __initconst;
+extern const struct imx_imx_keypad_data imx21_imx_keypad_data;
 #define imx21_add_imx_keypad(pdata)     \
         imx_add_imx_keypad(&imx21_imx_keypad_data, pdata)
 
-extern const struct imx_imx_ssi_data imx21_imx_ssi_data[] __initconst;
+extern const struct imx_imx_ssi_data imx21_imx_ssi_data[];
 #define imx21_add_imx_ssi(id, pdata)    \
         imx_add_imx_ssi(&imx21_imx_ssi_data[id], pdata)
 
-extern const struct imx_imx_uart_1irq_data imx21_imx_uart_data[] __initconst;
+extern const struct imx_imx_uart_1irq_data imx21_imx_uart_data[];
 #define imx21_add_imx_uart(id, pdata)   \
         imx_add_imx_uart_1irq(&imx21_imx_uart_data[id], pdata)
 #define imx21_add_imx_uart0(pdata)      imx21_add_imx_uart(0, pdata)
@@ -41,19 +41,19 @@ extern const struct imx_imx_uart_1irq_data imx21_imx_uart_data[] __initconst;
 #define imx21_add_imx_uart2(pdata)      imx21_add_imx_uart(2, pdata)
 #define imx21_add_imx_uart3(pdata)      imx21_add_imx_uart(3, pdata)
 
-extern const struct imx_mxc_mmc_data imx21_mxc_mmc_data[] __initconst;
+extern const struct imx_mxc_mmc_data imx21_mxc_mmc_data[];
 #define imx21_add_mxc_mmc(id, pdata)    \
         imx_add_mxc_mmc(&imx21_mxc_mmc_data[id], pdata)
 
-extern const struct imx_mxc_nand_data imx21_mxc_nand_data __initconst;
+extern const struct imx_mxc_nand_data imx21_mxc_nand_data;
 #define imx21_add_mxc_nand(pdata)       \
         imx_add_mxc_nand(&imx21_mxc_nand_data, pdata)
 
-extern const struct imx_mxc_w1_data imx21_mxc_w1_data __initconst;
+extern const struct imx_mxc_w1_data imx21_mxc_w1_data;
 #define imx21_add_mxc_w1(pdata) \
         imx_add_mxc_w1(&imx21_mxc_w1_data)
 
-extern const struct imx_spi_imx_data imx21_cspi_data[] __initconst;
+extern const struct imx_spi_imx_data imx21_cspi_data[];
 #define imx21_add_cspi(id, pdata)       \
         imx_add_spi_imx(&imx21_cspi_data[id], pdata)
 #define imx21_add_spi_imx0(pdata)       imx21_add_cspi(0, pdata)
diff --git a/arch/arm/mach-imx/devices-imx25.h b/arch/arm/mach-imx/devices-imx25.h
index b591d72f603..efa0761c508 100644
--- a/arch/arm/mach-imx/devices-imx25.h
+++ b/arch/arm/mach-imx/devices-imx25.h
@@ -9,48 +9,48 @@
 #include <mach/mx25.h>
 #include <mach/devices-common.h>
 
-extern const struct imx_fec_data imx25_fec_data __initconst;
+extern const struct imx_fec_data imx25_fec_data;
 #define imx25_add_fec(pdata)    \
         imx_add_fec(&imx25_fec_data, pdata)
 
-extern const struct imx_flexcan_data imx25_flexcan_data[] __initconst;
+extern const struct imx_flexcan_data imx25_flexcan_data[];
 #define imx25_add_flexcan(id, pdata)    \
         imx_add_flexcan(&imx25_flexcan_data[id], pdata)
 #define imx25_add_flexcan0(pdata)       imx25_add_flexcan(0, pdata)
 #define imx25_add_flexcan1(pdata)       imx25_add_flexcan(1, pdata)
 
-extern const struct imx_fsl_usb2_udc_data imx25_fsl_usb2_udc_data __initconst;
+extern const struct imx_fsl_usb2_udc_data imx25_fsl_usb2_udc_data;
 #define imx25_add_fsl_usb2_udc(pdata)   \
         imx_add_fsl_usb2_udc(&imx25_fsl_usb2_udc_data, pdata)
 
-extern struct imx_imxdi_rtc_data imx25_imxdi_rtc_data __initconst;
+extern struct imx_imxdi_rtc_data imx25_imxdi_rtc_data;
 #define imx25_add_imxdi_rtc(pdata)      \
         imx_add_imxdi_rtc(&imx25_imxdi_rtc_data)
 
-extern const struct imx_imx2_wdt_data imx25_imx2_wdt_data __initconst;
+extern const struct imx_imx2_wdt_data imx25_imx2_wdt_data;
 #define imx25_add_imx2_wdt(pdata)       \
         imx_add_imx2_wdt(&imx25_imx2_wdt_data)
 
-extern const struct imx_imx_fb_data imx25_imx_fb_data __initconst;
+extern const struct imx_imx_fb_data imx25_imx_fb_data;
 #define imx25_add_imx_fb(pdata) \
         imx_add_imx_fb(&imx25_imx_fb_data, pdata)
 
-extern const struct imx_imx_i2c_data imx25_imx_i2c_data[] __initconst;
+extern const struct imx_imx_i2c_data imx25_imx_i2c_data[];
 #define imx25_add_imx_i2c(id, pdata)    \
         imx_add_imx_i2c(&imx25_imx_i2c_data[id], pdata)
 #define imx25_add_imx_i2c0(pdata)       imx25_add_imx_i2c(0, pdata)
 #define imx25_add_imx_i2c1(pdata)       imx25_add_imx_i2c(1, pdata)
 #define imx25_add_imx_i2c2(pdata)       imx25_add_imx_i2c(2, pdata)
 
-extern const struct imx_imx_keypad_data imx25_imx_keypad_data __initconst;
+extern const struct imx_imx_keypad_data imx25_imx_keypad_data;
 #define imx25_add_imx_keypad(pdata)     \
         imx_add_imx_keypad(&imx25_imx_keypad_data, pdata)
 
-extern const struct imx_imx_ssi_data imx25_imx_ssi_data[] __initconst;
+extern const struct imx_imx_ssi_data imx25_imx_ssi_data[];
 #define imx25_add_imx_ssi(id, pdata)    \
         imx_add_imx_ssi(&imx25_imx_ssi_data[id], pdata)
 
-extern const struct imx_imx_uart_1irq_data imx25_imx_uart_data[] __initconst;
+extern const struct imx_imx_uart_1irq_data imx25_imx_uart_data[];
 #define imx25_add_imx_uart(id, pdata)   \
         imx_add_imx_uart_1irq(&imx25_imx_uart_data[id], pdata)
 #define imx25_add_imx_uart0(pdata)      imx25_add_imx_uart(0, pdata)
@@ -59,33 +59,32 @@ extern const struct imx_imx_uart_1irq_data imx25_imx_uart_data[] __initconst;
 #define imx25_add_imx_uart3(pdata)      imx25_add_imx_uart(3, pdata)
 #define imx25_add_imx_uart4(pdata)      imx25_add_imx_uart(4, pdata)
 
-extern const struct imx_mx2_camera_data imx25_mx2_camera_data __initconst;
+extern const struct imx_mx2_camera_data imx25_mx2_camera_data;
 #define imx25_add_mx2_camera(pdata)     \
         imx_add_mx2_camera(&imx25_mx2_camera_data, pdata)
 
-extern const struct imx_mxc_ehci_data imx25_mxc_ehci_otg_data __initconst;
+extern const struct imx_mxc_ehci_data imx25_mxc_ehci_otg_data;
 #define imx25_add_mxc_ehci_otg(pdata)   \
         imx_add_mxc_ehci(&imx25_mxc_ehci_otg_data, pdata)
-extern const struct imx_mxc_ehci_data imx25_mxc_ehci_hs_data __initconst;
+extern const struct imx_mxc_ehci_data imx25_mxc_ehci_hs_data;
 #define imx25_add_mxc_ehci_hs(pdata)    \
         imx_add_mxc_ehci(&imx25_mxc_ehci_hs_data, pdata)
 
-extern const struct imx_mxc_nand_data imx25_mxc_nand_data __initconst;
+extern const struct imx_mxc_nand_data imx25_mxc_nand_data;
 #define imx25_add_mxc_nand(pdata)       \
         imx_add_mxc_nand(&imx25_mxc_nand_data, pdata)
 
-extern const struct imx_sdhci_esdhc_imx_data
-imx25_sdhci_esdhc_imx_data[] __initconst;
+extern const struct imx_sdhci_esdhc_imx_data imx25_sdhci_esdhc_imx_data[];
 #define imx25_add_sdhci_esdhc_imx(id, pdata)    \
         imx_add_sdhci_esdhc_imx(&imx25_sdhci_esdhc_imx_data[id], pdata)
 
-extern const struct imx_spi_imx_data imx25_cspi_data[] __initconst;
+extern const struct imx_spi_imx_data imx25_cspi_data[];
 #define imx25_add_spi_imx(id, pdata)    \
         imx_add_spi_imx(&imx25_cspi_data[id], pdata)
 #define imx25_add_spi_imx0(pdata)       imx25_add_spi_imx(0, pdata)
 #define imx25_add_spi_imx1(pdata)       imx25_add_spi_imx(1, pdata)
 #define imx25_add_spi_imx2(pdata)       imx25_add_spi_imx(2, pdata)
 
-extern struct imx_mxc_pwm_data imx25_mxc_pwm_data[] __initconst;
+extern struct imx_mxc_pwm_data imx25_mxc_pwm_data[];
 #define imx25_add_mxc_pwm(id)   \
         imx_add_mxc_pwm(&imx25_mxc_pwm_data[id])
diff --git a/arch/arm/mach-imx/devices-imx27.h b/arch/arm/mach-imx/devices-imx27.h
index f1272d4b5a3..7f97a3cdd41 100644
--- a/arch/arm/mach-imx/devices-imx27.h
+++ b/arch/arm/mach-imx/devices-imx27.h
@@ -9,35 +9,35 @@
 #include <mach/mx27.h>
 #include <mach/devices-common.h>
 
-extern const struct imx_fec_data imx27_fec_data __initconst;
+extern const struct imx_fec_data imx27_fec_data;
 #define imx27_add_fec(pdata)    \
         imx_add_fec(&imx27_fec_data, pdata)
 
-extern const struct imx_fsl_usb2_udc_data imx27_fsl_usb2_udc_data __initconst;
+extern const struct imx_fsl_usb2_udc_data imx27_fsl_usb2_udc_data;
 #define imx27_add_fsl_usb2_udc(pdata)   \
         imx_add_fsl_usb2_udc(&imx27_fsl_usb2_udc_data, pdata)
 
-extern const struct imx_imx2_wdt_data imx27_imx2_wdt_data __initconst;
+extern const struct imx_imx2_wdt_data imx27_imx2_wdt_data;
 #define imx27_add_imx2_wdt(pdata)       \
         imx_add_imx2_wdt(&imx27_imx2_wdt_data)
 
-extern const struct imx_imx_fb_data imx27_imx_fb_data __initconst;
+extern const struct imx_imx_fb_data imx27_imx_fb_data;
 #define imx27_add_imx_fb(pdata) \
         imx_add_imx_fb(&imx27_imx_fb_data, pdata)
 
-extern const struct imx_imx_i2c_data imx27_imx_i2c_data[] __initconst;
+extern const struct imx_imx_i2c_data imx27_imx_i2c_data[];
 #define imx27_add_imx_i2c(id, pdata)    \
         imx_add_imx_i2c(&imx27_imx_i2c_data[id], pdata)
 
-extern const struct imx_imx_keypad_data imx27_imx_keypad_data __initconst;
+extern const struct imx_imx_keypad_data imx27_imx_keypad_data;
 #define imx27_add_imx_keypad(pdata)     \
         imx_add_imx_keypad(&imx27_imx_keypad_data, pdata)
 
-extern const struct imx_imx_ssi_data imx27_imx_ssi_data[] __initconst;
+extern const struct imx_imx_ssi_data imx27_imx_ssi_data[];
 #define imx27_add_imx_ssi(id, pdata)    \
         imx_add_imx_ssi(&imx27_imx_ssi_data[id], pdata)
 
-extern const struct imx_imx_uart_1irq_data imx27_imx_uart_data[] __initconst;
+extern const struct imx_imx_uart_1irq_data imx27_imx_uart_data[];
 #define imx27_add_imx_uart(id, pdata)   \
         imx_add_imx_uart_1irq(&imx27_imx_uart_data[id], pdata)
 #define imx27_add_imx_uart0(pdata)      imx27_add_imx_uart(0, pdata)
@@ -47,30 +47,30 @@ extern const struct imx_imx_uart_1irq_data imx27_imx_uart_data[] __initconst;
 #define imx27_add_imx_uart4(pdata)      imx27_add_imx_uart(4, pdata)
 #define imx27_add_imx_uart5(pdata)      imx27_add_imx_uart(5, pdata)
 
-extern const struct imx_mx2_camera_data imx27_mx2_camera_data __initconst;
+extern const struct imx_mx2_camera_data imx27_mx2_camera_data;
 #define imx27_add_mx2_camera(pdata)     \
         imx_add_mx2_camera(&imx27_mx2_camera_data, pdata)
 
-extern const struct imx_mxc_ehci_data imx27_mxc_ehci_otg_data __initconst;
+extern const struct imx_mxc_ehci_data imx27_mxc_ehci_otg_data;
 #define imx27_add_mxc_ehci_otg(pdata)   \
         imx_add_mxc_ehci(&imx27_mxc_ehci_otg_data, pdata)
-extern const struct imx_mxc_ehci_data imx27_mxc_ehci_hs_data[] __initconst;
+extern const struct imx_mxc_ehci_data imx27_mxc_ehci_hs_data[];
 #define imx27_add_mxc_ehci_hs(id, pdata)        \
         imx_add_mxc_ehci(&imx27_mxc_ehci_hs_data[id - 1], pdata)
 
-extern const struct imx_mxc_mmc_data imx27_mxc_mmc_data[] __initconst;
+extern const struct imx_mxc_mmc_data imx27_mxc_mmc_data[];
 #define imx27_add_mxc_mmc(id, pdata)    \
         imx_add_mxc_mmc(&imx27_mxc_mmc_data[id], pdata)
 
-extern const struct imx_mxc_nand_data imx27_mxc_nand_data __initconst;
+extern const struct imx_mxc_nand_data imx27_mxc_nand_data;
 #define imx27_add_mxc_nand(pdata)       \
         imx_add_mxc_nand(&imx27_mxc_nand_data, pdata)
 
-extern const struct imx_mxc_w1_data imx27_mxc_w1_data __initconst;
+extern const struct imx_mxc_w1_data imx27_mxc_w1_data;
 #define imx27_add_mxc_w1(pdata) \
         imx_add_mxc_w1(&imx27_mxc_w1_data)
 
-extern const struct imx_spi_imx_data imx27_cspi_data[] __initconst;
+extern const struct imx_spi_imx_data imx27_cspi_data[];
 #define imx27_add_cspi(id, pdata)       \
         imx_add_spi_imx(&imx27_cspi_data[id], pdata)
 #define imx27_add_spi_imx0(pdata)       imx27_add_cspi(0, pdata)
diff --git a/arch/arm/mach-mx3/devices-imx31.h b/arch/arm/mach-imx/devices-imx31.h
index 40f4e848a67..dbe940d9c53 100644
--- a/arch/arm/mach-mx3/devices-imx31.h
+++ b/arch/arm/mach-imx/devices-imx31.h
@@ -9,30 +9,30 @@
 #include <mach/mx31.h>
 #include <mach/devices-common.h>
 
-extern const struct imx_fsl_usb2_udc_data imx31_fsl_usb2_udc_data __initconst;
+extern const struct imx_fsl_usb2_udc_data imx31_fsl_usb2_udc_data;
 #define imx31_add_fsl_usb2_udc(pdata)   \
         imx_add_fsl_usb2_udc(&imx31_fsl_usb2_udc_data, pdata)
 
-extern const struct imx_imx2_wdt_data imx31_imx2_wdt_data __initconst;
+extern const struct imx_imx2_wdt_data imx31_imx2_wdt_data;
 #define imx31_add_imx2_wdt(pdata)       \
         imx_add_imx2_wdt(&imx31_imx2_wdt_data)
 
-extern const struct imx_imx_i2c_data imx31_imx_i2c_data[] __initconst;
+extern const struct imx_imx_i2c_data imx31_imx_i2c_data[];
 #define imx31_add_imx_i2c(id, pdata)    \
         imx_add_imx_i2c(&imx31_imx_i2c_data[id], pdata)
 #define imx31_add_imx_i2c0(pdata)       imx31_add_imx_i2c(0, pdata)
 #define imx31_add_imx_i2c1(pdata)       imx31_add_imx_i2c(1, pdata)
 #define imx31_add_imx_i2c2(pdata)       imx31_add_imx_i2c(2, pdata)
 
-extern const struct imx_imx_keypad_data imx31_imx_keypad_data __initconst;
+extern const struct imx_imx_keypad_data imx31_imx_keypad_data;
 #define imx31_add_imx_keypad(pdata)     \
         imx_add_imx_keypad(&imx31_imx_keypad_data, pdata)
 
-extern const struct imx_imx_ssi_data imx31_imx_ssi_data[] __initconst;
+extern const struct imx_imx_ssi_data imx31_imx_ssi_data[];
 #define imx31_add_imx_ssi(id, pdata)    \
         imx_add_imx_ssi(&imx31_imx_ssi_data[id], pdata)
 
-extern const struct imx_imx_uart_1irq_data imx31_imx_uart_data[] __initconst;
+extern const struct imx_imx_uart_1irq_data imx31_imx_uart_data[];
 #define imx31_add_imx_uart(id, pdata)   \
         imx_add_imx_uart_1irq(&imx31_imx_uart_data[id], pdata)
 #define imx31_add_imx_uart0(pdata)      imx31_add_imx_uart(0, pdata)
@@ -41,26 +41,38 @@ extern const struct imx_imx_uart_1irq_data imx31_imx_uart_data[] __initconst;
 #define imx31_add_imx_uart3(pdata)      imx31_add_imx_uart(3, pdata)
 #define imx31_add_imx_uart4(pdata)      imx31_add_imx_uart(4, pdata)
 
-extern const struct imx_mxc_ehci_data imx31_mxc_ehci_otg_data __initconst;
+extern const struct imx_ipu_core_data imx31_ipu_core_data;
+#define imx31_add_ipu_core(pdata)       \
+        imx_add_ipu_core(&imx31_ipu_core_data, pdata)
+#define imx31_alloc_mx3_camera(pdata)   \
+        imx_alloc_mx3_camera(&imx31_ipu_core_data, pdata)
+#define imx31_add_mx3_sdc_fb(pdata)     \
+        imx_add_mx3_sdc_fb(&imx31_ipu_core_data, pdata)
+
+extern const struct imx_mxc_ehci_data imx31_mxc_ehci_otg_data;
 #define imx31_add_mxc_ehci_otg(pdata)   \
         imx_add_mxc_ehci(&imx31_mxc_ehci_otg_data, pdata)
-extern const struct imx_mxc_ehci_data imx31_mxc_ehci_hs_data[] __initconst;
+extern const struct imx_mxc_ehci_data imx31_mxc_ehci_hs_data[];
 #define imx31_add_mxc_ehci_hs(id, pdata)        \
         imx_add_mxc_ehci(&imx31_mxc_ehci_hs_data[id - 1], pdata)
 
-extern const struct imx_mxc_mmc_data imx31_mxc_mmc_data[] __initconst;
+extern const struct imx_mxc_mmc_data imx31_mxc_mmc_data[];
 #define imx31_add_mxc_mmc(id, pdata)    \
         imx_add_mxc_mmc(&imx31_mxc_mmc_data[id], pdata)
 
-extern const struct imx_mxc_nand_data imx31_mxc_nand_data __initconst;
+extern const struct imx_mxc_nand_data imx31_mxc_nand_data;
 #define imx31_add_mxc_nand(pdata)       \
         imx_add_mxc_nand(&imx31_mxc_nand_data, pdata)
 
-extern const struct imx_mxc_w1_data imx31_mxc_w1_data __initconst;
+extern const struct imx_mxc_rtc_data imx31_mxc_rtc_data;
+#define imx31_add_mxc_rtc(pdata)        \
+        imx_add_mxc_rtc(&imx31_mxc_rtc_data)
+
+extern const struct imx_mxc_w1_data imx31_mxc_w1_data;
 #define imx31_add_mxc_w1(pdata) \
         imx_add_mxc_w1(&imx31_mxc_w1_data)
 
-extern const struct imx_spi_imx_data imx31_cspi_data[] __initconst;
+extern const struct imx_spi_imx_data imx31_cspi_data[];
 #define imx31_add_cspi(id, pdata)       \
         imx_add_spi_imx(&imx31_cspi_data[id], pdata)
 #define imx31_add_spi_imx0(pdata)       imx31_add_cspi(0, pdata)
diff --git a/arch/arm/mach-mx3/devices-imx35.h b/arch/arm/mach-imx/devices-imx35.h
index d545d86cc20..234cbd3c18a 100644
--- a/arch/arm/mach-mx3/devices-imx35.h
+++ b/arch/arm/mach-imx/devices-imx35.h
@@ -9,67 +9,74 @@
 #include <mach/mx35.h>
 #include <mach/devices-common.h>
 
-extern const struct imx_fec_data imx35_fec_data __initconst;
+extern const struct imx_fec_data imx35_fec_data;
 #define imx35_add_fec(pdata)    \
         imx_add_fec(&imx35_fec_data, pdata)
 
-extern const struct imx_fsl_usb2_udc_data imx35_fsl_usb2_udc_data __initconst;
+extern const struct imx_fsl_usb2_udc_data imx35_fsl_usb2_udc_data;
 #define imx35_add_fsl_usb2_udc(pdata)   \
         imx_add_fsl_usb2_udc(&imx35_fsl_usb2_udc_data, pdata)
 
-extern const struct imx_flexcan_data imx35_flexcan_data[] __initconst;
+extern const struct imx_flexcan_data imx35_flexcan_data[];
 #define imx35_add_flexcan(id, pdata)    \
         imx_add_flexcan(&imx35_flexcan_data[id], pdata)
 #define imx35_add_flexcan0(pdata)       imx35_add_flexcan(0, pdata)
 #define imx35_add_flexcan1(pdata)       imx35_add_flexcan(1, pdata)
 
-extern const struct imx_imx2_wdt_data imx35_imx2_wdt_data __initconst;
+extern const struct imx_imx2_wdt_data imx35_imx2_wdt_data;
 #define imx35_add_imx2_wdt(pdata)       \
         imx_add_imx2_wdt(&imx35_imx2_wdt_data)
 
-extern const struct imx_imx_i2c_data imx35_imx_i2c_data[] __initconst;
+extern const struct imx_imx_i2c_data imx35_imx_i2c_data[];
 #define imx35_add_imx_i2c(id, pdata)    \
         imx_add_imx_i2c(&imx35_imx_i2c_data[id], pdata)
 #define imx35_add_imx_i2c0(pdata)       imx35_add_imx_i2c(0, pdata)
 #define imx35_add_imx_i2c1(pdata)       imx35_add_imx_i2c(1, pdata)
 #define imx35_add_imx_i2c2(pdata)       imx35_add_imx_i2c(2, pdata)
 
-extern const struct imx_imx_keypad_data imx35_imx_keypad_data __initconst;
+extern const struct imx_imx_keypad_data imx35_imx_keypad_data;
 #define imx35_add_imx_keypad(pdata)     \
         imx_add_imx_keypad(&imx35_imx_keypad_data, pdata)
 
-extern const struct imx_imx_ssi_data imx35_imx_ssi_data[] __initconst;
+extern const struct imx_imx_ssi_data imx35_imx_ssi_data[];
 #define imx35_add_imx_ssi(id, pdata)    \
         imx_add_imx_ssi(&imx35_imx_ssi_data[id], pdata)
 
-extern const struct imx_imx_uart_1irq_data imx35_imx_uart_data[] __initconst;
+extern const struct imx_imx_uart_1irq_data imx35_imx_uart_data[];
 #define imx35_add_imx_uart(id, pdata)   \
         imx_add_imx_uart_1irq(&imx35_imx_uart_data[id], pdata)
 #define imx35_add_imx_uart0(pdata)      imx35_add_imx_uart(0, pdata)
 #define imx35_add_imx_uart1(pdata)      imx35_add_imx_uart(1, pdata)
 #define imx35_add_imx_uart2(pdata)      imx35_add_imx_uart(2, pdata)
 
-extern const struct imx_mxc_ehci_data imx35_mxc_ehci_otg_data __initconst;
+extern const struct imx_ipu_core_data imx35_ipu_core_data;
+#define imx35_add_ipu_core(pdata)       \
+        imx_add_ipu_core(&imx35_ipu_core_data, pdata)
+#define imx35_alloc_mx3_camera(pdata)   \
+        imx_alloc_mx3_camera(&imx35_ipu_core_data, pdata)
+#define imx35_add_mx3_sdc_fb(pdata)     \
+        imx_add_mx3_sdc_fb(&imx35_ipu_core_data, pdata)
+
+extern const struct imx_mxc_ehci_data imx35_mxc_ehci_otg_data;
 #define imx35_add_mxc_ehci_otg(pdata)   \
         imx_add_mxc_ehci(&imx35_mxc_ehci_otg_data, pdata)
-extern const struct imx_mxc_ehci_data imx35_mxc_ehci_hs_data __initconst;
+extern const struct imx_mxc_ehci_data imx35_mxc_ehci_hs_data;
 #define imx35_add_mxc_ehci_hs(pdata)    \
         imx_add_mxc_ehci(&imx35_mxc_ehci_hs_data, pdata)
 
-extern const struct imx_mxc_nand_data imx35_mxc_nand_data __initconst;
+extern const struct imx_mxc_nand_data imx35_mxc_nand_data;
 #define imx35_add_mxc_nand(pdata)       \
         imx_add_mxc_nand(&imx35_mxc_nand_data, pdata)
 
-extern const struct imx_mxc_w1_data imx35_mxc_w1_data __initconst;
+extern const struct imx_mxc_w1_data imx35_mxc_w1_data;
 #define imx35_add_mxc_w1(pdata) \
         imx_add_mxc_w1(&imx35_mxc_w1_data)
 
-extern const struct imx_sdhci_esdhc_imx_data
-imx35_sdhci_esdhc_imx_data[] __initconst;
+extern const struct imx_sdhci_esdhc_imx_data imx35_sdhci_esdhc_imx_data[];
 #define imx35_add_sdhci_esdhc_imx(id, pdata)    \
         imx_add_sdhci_esdhc_imx(&imx35_sdhci_esdhc_imx_data[id], pdata)
 
-extern const struct imx_spi_imx_data imx35_cspi_data[] __initconst;
+extern const struct imx_spi_imx_data imx35_cspi_data[];
 #define imx35_add_cspi(id, pdata)       \
         imx_add_spi_imx(&imx35_cspi_data[id], pdata)
 #define imx35_add_spi_imx0(pdata)       imx35_add_cspi(0, pdata)
diff --git a/arch/arm/mach-mx3/ehci-imx31.c b/arch/arm/mach-imx/ehci-imx31.c
index 314a983ac61..faad0f15ac7 100644
--- a/arch/arm/mach-mx3/ehci-imx31.c
+++ b/arch/arm/mach-imx/ehci-imx31.c
@@ -80,4 +80,3 @@ int mx31_initialize_usb_hw(int port, unsigned int flags)
 
         return 0;
 }
-
diff --git a/arch/arm/mach-mx3/ehci-imx35.c b/arch/arm/mach-imx/ehci-imx35.c
index 33983a478c6..001ec3971f5 100644
--- a/arch/arm/mach-mx3/ehci-imx35.c
+++ b/arch/arm/mach-imx/ehci-imx35.c
@@ -77,4 +77,3 @@ int mx35_initialize_usb_hw(int port, unsigned int flags)
 
         return 0;
 }
-
diff --git a/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c b/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c
index fa5288018ba..5911281da5f 100644
--- a/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c
+++ b/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c
@@ -32,7 +32,6 @@
 #include <mach/common.h>
 #include <mach/iomux-mx27.h>
 #include <mach/hardware.h>
-#include <mach/spi.h>
 #include <mach/audmux.h>
 
 #include "devices-imx27.h"
diff --git a/arch/arm/mach-imx/eukrea_mbimxsd25-baseboard.c b/arch/arm/mach-imx/eukrea_mbimxsd25-baseboard.c
index 6269053505f..f9ef04acdab 100644
--- a/arch/arm/mach-imx/eukrea_mbimxsd25-baseboard.c
+++ b/arch/arm/mach-imx/eukrea_mbimxsd25-baseboard.c
@@ -22,7 +22,6 @@
 #include <linux/gpio.h>
 #include <linux/leds.h>
 #include <linux/platform_device.h>
-#include <linux/gpio_keys.h>
 #include <linux/input.h>
 #include <video/platform_lcd.h>
 
@@ -32,9 +31,7 @@
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <mach/mx25.h>
-#include <mach/imx-uart.h>
 #include <mach/audmux.h>
-#include <mach/esdhc.h>
 
 #include "devices-imx25.h"
 
@@ -208,23 +205,14 @@ static struct gpio_keys_button eukrea_mbimxsd_gpio_buttons[] = {
         },
 };
 
-static struct gpio_keys_platform_data eukrea_mbimxsd_button_data = {
+static const struct gpio_keys_platform_data
+                eukrea_mbimxsd_button_data __initconst = {
         .buttons        = eukrea_mbimxsd_gpio_buttons,
         .nbuttons       = ARRAY_SIZE(eukrea_mbimxsd_gpio_buttons),
 };
 
-static struct platform_device eukrea_mbimxsd_button_device = {
-        .name           = "gpio-keys",
-        .id             = -1,
-        .num_resources  = 0,
-        .dev            = {
-                .platform_data  = &eukrea_mbimxsd_button_data,
-        }
-};
-
 static struct platform_device *platform_devices[] __initdata = {
         &eukrea_mbimxsd_leds_gpio,
-        &eukrea_mbimxsd_button_device,
         &eukrea_mbimxsd_lcd_powerdev,
 };
 
@@ -299,4 +287,5 @@ void __init eukrea_mbimxsd25_baseboard_init(void)
                                 ARRAY_SIZE(eukrea_mbimxsd_i2c_devices));
 
         platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
+        imx_add_gpio_keys(&eukrea_mbimxsd_button_data);
 }
diff --git a/arch/arm/mach-mx3/eukrea_mbimxsd-baseboard.c b/arch/arm/mach-imx/eukrea_mbimxsd35-baseboard.c
index 2e288b38b4a..4909ea05855 100644
--- a/arch/arm/mach-mx3/eukrea_mbimxsd-baseboard.c
+++ b/arch/arm/mach-imx/eukrea_mbimxsd35-baseboard.c
@@ -26,7 +26,6 @@
 #include <linux/interrupt.h>
 #include <linux/leds.h>
 #include <linux/platform_device.h>
-#include <linux/gpio_keys.h>
 #include <linux/input.h>
 #include <video/platform_lcd.h>
 #include <linux/i2c.h>
@@ -38,15 +37,10 @@
 
 #include <mach/hardware.h>
 #include <mach/common.h>
-#include <mach/imx-uart.h>
 #include <mach/iomux-mx35.h>
-#include <mach/ipu.h>
-#include <mach/mx3fb.h>
 #include <mach/audmux.h>
-#include <mach/esdhc.h>
 
 #include "devices-imx35.h"
-#include "devices.h"
 
 static const struct fb_videomode fb_modedb[] = {
         {
@@ -101,12 +95,11 @@ static const struct fb_videomode fb_modedb[] = {
         },
 };
 
-static struct ipu_platform_data mx3_ipu_data = {
+static const struct ipu_platform_data mx3_ipu_data __initconst = {
         .irq_base = MXC_IPU_IRQ_START,
 };
 
-static struct mx3fb_platform_data mx3fb_pdata = {
-        .dma_dev        = &mx3_ipu.dev,
+static struct mx3fb_platform_data mx3fb_pdata __initdata = {
         .name           = "CMO-QVGA",
         .mode           = fb_modedb,
         .num_modes      = ARRAY_SIZE(fb_modedb),
@@ -223,23 +216,14 @@ static struct gpio_keys_button eukrea_mbimxsd_gpio_buttons[] = {
         },
 };
 
-static struct gpio_keys_platform_data eukrea_mbimxsd_button_data = {
+static const struct gpio_keys_platform_data
+                eukrea_mbimxsd_button_data __initconst = {
         .buttons        = eukrea_mbimxsd_gpio_buttons,
         .nbuttons       = ARRAY_SIZE(eukrea_mbimxsd_gpio_buttons),
 };
 
-static struct platform_device eukrea_mbimxsd_button_device = {
-        .name           = "gpio-keys",
-        .id             = -1,
-        .num_resources  = 0,
-        .dev            = {
-                .platform_data  = &eukrea_mbimxsd_button_data,
-        }
-};
-
 static struct platform_device *platform_devices[] __initdata = {
         &eukrea_mbimxsd_leds_gpio,
-        &eukrea_mbimxsd_button_device,
         &eukrea_mbimxsd_lcd_powerdev,
 };
 
@@ -292,8 +276,8 @@ void __init eukrea_mbimxsd35_baseboard_init(void)
 #endif
 
         imx35_add_imx_uart1(&uart_pdata);
-        mxc_register_device(&mx3_ipu, &mx3_ipu_data);
-        mxc_register_device(&mx3_fb, &mx3fb_pdata);
+        imx35_add_ipu_core(&mx3_ipu_data);
+        imx35_add_mx3_sdc_fb(&mx3fb_pdata);
 
         imx35_add_imx_ssi(0, &eukrea_mbimxsd_ssi_pdata);
 
@@ -315,4 +299,5 @@ void __init eukrea_mbimxsd35_baseboard_init(void)
                                 ARRAY_SIZE(eukrea_mbimxsd_i2c_devices));
 
         platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
+        imx_add_gpio_keys(&eukrea_mbimxsd_button_data);
 }
diff --git a/arch/arm/mach-mx3/iomux-imx31.c b/arch/arm/mach-imx/iomux-imx31.c
index cf8f8099ebd..cf8f8099ebd 100644
--- a/arch/arm/mach-mx3/iomux-imx31.c
+++ b/arch/arm/mach-imx/iomux-imx31.c
diff --git a/arch/arm/mach-imx/mach-apf9328.c b/arch/arm/mach-imx/mach-apf9328.c
new file mode 100644
index 00000000000..15e45c84e37
--- /dev/null
+++ b/arch/arm/mach-imx/mach-apf9328.c
@@ -0,0 +1,144 @@
+/*
+ * linux/arch/arm/mach-imx/mach-apf9328.c
+ *
+ * Copyright (c) 2005-2011 ARMadeus systems <support@armadeus.com>
+ *
+ * This work is based on mach-scb9328.c which is:
+ * Copyright (c) 2004 Sascha Hauer <saschahauer@web.de>
+ * Copyright (c) 2006-2008 Juergen Beisert <jbeisert@netscape.net>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/platform_device.h>
+#include <linux/mtd/physmap.h>
+#include <linux/dm9000.h>
+
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/time.h>
+
+#include <mach/common.h>
+#include <mach/hardware.h>
+#include <mach/irqs.h>
+#include <mach/iomux-mx1.h>
+
+#include "devices-imx1.h"
+
+static const int apf9328_pins[] __initconst = {
+        /* UART1 */
+        PC9_PF_UART1_CTS,
+        PC10_PF_UART1_RTS,
+        PC11_PF_UART1_TXD,
+        PC12_PF_UART1_RXD,
+        /* UART2 */
+        PB28_PF_UART2_CTS,
+        PB29_PF_UART2_RTS,
+        PB30_PF_UART2_TXD,
+        PB31_PF_UART2_RXD,
+};
+
+/*
+ * The APF9328 can have up to 32MB NOR Flash
+ */
+static struct resource flash_resource = {
+        .start  = MX1_CS0_PHYS,
+        .end    = MX1_CS0_PHYS + SZ_32M - 1,
+        .flags  = IORESOURCE_MEM,
+};
+
+static struct physmap_flash_data apf9328_flash_data = {
+        .width  = 2,
+};
+
+static struct platform_device apf9328_flash_device = {
+        .name           = "physmap-flash",
+        .id             = 0,
+        .dev = {
+                .platform_data = &apf9328_flash_data,
+        },
+        .resource = &flash_resource,
+        .num_resources = 1,
+};
+
+/*
+ * APF9328 has a DM9000 Ethernet controller
+ */
+static struct dm9000_plat_data dm9000_setup = {
+        .flags          = DM9000_PLATF_16BITONLY
+};
+
+static struct resource dm9000_resources[] = {
+        {
+                .start  = MX1_CS4_PHYS + 0x00C00000,
+                .end    = MX1_CS4_PHYS + 0x00C00001,
+                .flags  = IORESOURCE_MEM,
+        }, {
+                .start  = MX1_CS4_PHYS + 0x00C00002,
+                .end    = MX1_CS4_PHYS + 0x00C00003,
+                .flags  = IORESOURCE_MEM,
+        }, {
+                .start  = IRQ_GPIOB(14),
+                .end    = IRQ_GPIOB(14),
+                .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
+        },
+};
+
+static struct platform_device dm9000x_device = {
+        .name           = "dm9000",
+        .id             = 0,
+        .num_resources  = ARRAY_SIZE(dm9000_resources),
+        .resource       = dm9000_resources,
+        .dev            = {
+                .platform_data = &dm9000_setup,
+        }
+};
+
+/* --- SERIAL RESSOURCE --- */
+static const struct imxuart_platform_data uart0_pdata __initconst = {
+        .flags = 0,
+};
+
+static const struct imxuart_platform_data uart1_pdata __initconst = {
+        .flags = IMXUART_HAVE_RTSCTS,
+};
+
+static struct platform_device *devices[] __initdata = {
+        &apf9328_flash_device,
+        &dm9000x_device,
+};
+
+static void __init apf9328_init(void)
+{
+        mxc_gpio_setup_multiple_pins(apf9328_pins,
+                        ARRAY_SIZE(apf9328_pins),
+                        "APF9328");
+
+        imx1_add_imx_uart0(&uart0_pdata);
+        imx1_add_imx_uart1(&uart1_pdata);
+
+        platform_add_devices(devices, ARRAY_SIZE(devices));
+}
+
+static void __init apf9328_timer_init(void)
+{
+        mx1_clocks_init(32768);
+}
+
+static struct sys_timer apf9328_timer = {
+        .init   = apf9328_timer_init,
+};
+
+MACHINE_START(APF9328, "Armadeus APF9328")
+        /* Maintainer: Gwenhael Goavec-Merou, ARMadeus Systems */
+        .map_io       = mx1_map_io,
+        .init_early   = imx1_init_early,
+        .init_irq     = mx1_init_irq,
+        .timer        = &apf9328_timer,
+        .init_machine = apf9328_init,
+MACHINE_END
diff --git a/arch/arm/mach-mx3/mach-armadillo5x0.c b/arch/arm/mach-imx/mach-armadillo5x0.c
index 226829bf7c2..ffb40ff619b 100644
--- a/arch/arm/mach-mx3/mach-armadillo5x0.c
+++ b/arch/arm/mach-imx/mach-armadillo5x0.c
@@ -34,7 +34,6 @@
 #include <linux/mtd/physmap.h>
 #include <linux/io.h>
 #include <linux/input.h>
-#include <linux/gpio_keys.h>
 #include <linux/i2c.h>
 #include <linux/usb/otg.h>
 #include <linux/usb/ulpi.h>
@@ -49,13 +48,10 @@
 
 #include <mach/common.h>
 #include <mach/iomux-mx3.h>
-#include <mach/ipu.h>
-#include <mach/mx3fb.h>
 #include <mach/ulpi.h>
 
 #include "devices-imx31.h"
-#include "devices.h"
-#include "crm_regs.h"
+#include "crmregs-imx31.h"
 
 static int armadillo5x0_pins[] = {
         /* UART1 */
@@ -280,20 +276,12 @@ static struct gpio_keys_button armadillo5x0_buttons[] = {
         }
 };
 
-static struct gpio_keys_platform_data armadillo5x0_button_data = {
+static const struct gpio_keys_platform_data
+                armadillo5x0_button_data __initconst = {
         .buttons        = armadillo5x0_buttons,
         .nbuttons       = ARRAY_SIZE(armadillo5x0_buttons),
 };
 
-static struct platform_device armadillo5x0_button_device = {
-        .name           = "gpio-keys",
-        .id             = -1,
-        .num_resources  = 0,
-        .dev            = {
-                .platform_data  = &armadillo5x0_button_data,
-        }
-};
-
 /*
  * NAND Flash
  */
@@ -383,12 +371,11 @@ static const struct fb_videomode fb_modedb[] = {
         },
 };
 
-static struct ipu_platform_data mx3_ipu_data = {
+static const struct ipu_platform_data mx3_ipu_data __initconst = {
         .irq_base = MXC_IPU_IRQ_START,
 };
 
-static struct mx3fb_platform_data mx3fb_pdata = {
-        .dma_dev        = &mx3_ipu.dev,
+static struct mx3fb_platform_data mx3fb_pdata __initdata = {
         .name           = "CRT-VGA",
         .mode           = fb_modedb,
         .num_modes      = ARRAY_SIZE(fb_modedb),
@@ -496,7 +483,6 @@ static const struct imxuart_platform_data uart_pdata __initconst = {
 
 static struct platform_device *devices[] __initdata = {
         &armadillo5x0_smc911x_device,
-        &armadillo5x0_button_device,
 };
 
 /*
@@ -508,6 +494,7 @@ static void __init armadillo5x0_init(void)
                         ARRAY_SIZE(armadillo5x0_pins), "armadillo5x0");
 
         platform_add_devices(devices, ARRAY_SIZE(devices));
+        imx_add_gpio_keys(&armadillo5x0_button_data);
         imx31_add_imx_i2c1(NULL);
 
         /* Register UART */
@@ -521,8 +508,8 @@ static void __init armadillo5x0_init(void)
         imx31_add_mxc_mmc(0, &sdhc_pdata);
 
         /* Register FB */
-        mxc_register_device(&mx3_ipu, &mx3_ipu_data);
-        mxc_register_device(&mx3_fb, &mx3fb_pdata);
+        imx31_add_ipu_core(&mx3_ipu_data);
+        imx31_add_mx3_sdc_fb(&mx3fb_pdata);
 
         /* Register NOR Flash */
         mxc_register_device(&armadillo5x0_nor_flash,
diff --git a/arch/arm/mach-mx3/mach-bug.c b/arch/arm/mach-imx/mach-bug.c
index d137d7078ee..42e4f078a19 100644
--- a/arch/arm/mach-mx3/mach-bug.c
+++ b/arch/arm/mach-imx/mach-bug.c
@@ -20,7 +20,6 @@
 #include <linux/platform_device.h>
 
 #include <mach/iomux-mx3.h>
-#include <mach/imx-uart.h>
 #include <mach/hardware.h>
 #include <mach/common.h>
 
diff --git a/arch/arm/mach-imx/mach-cpuimx27.c b/arch/arm/mach-imx/mach-cpuimx27.c
index 759299bb035..46a2e41d43d 100644
--- a/arch/arm/mach-imx/mach-cpuimx27.c
+++ b/arch/arm/mach-imx/mach-cpuimx27.c
@@ -38,7 +38,6 @@
 #include <mach/common.h>
 #include <mach/hardware.h>
 #include <mach/iomux-mx27.h>
-#include <mach/mxc_nand.h>
 #include <mach/ulpi.h>
 
 #include "devices-imx27.h"
diff --git a/arch/arm/mach-mx3/mach-cpuimx35.c b/arch/arm/mach-imx/mach-cpuimx35.c
index ec63d998f64..3f8ef825fa6 100644
--- a/arch/arm/mach-mx3/mach-cpuimx35.c
+++ b/arch/arm/mach-imx/mach-cpuimx35.c
@@ -41,10 +41,8 @@
 #include <mach/hardware.h>
 #include <mach/common.h>
 #include <mach/iomux-mx35.h>
-#include <mach/mxc_nand.h>
 
 #include "devices-imx35.h"
-#include "devices.h"
 
 static const struct imxuart_platform_data uart_pdata __initconst = {
         .flags = IMXUART_HAVE_RTSCTS,
diff --git a/arch/arm/mach-imx/mach-eukrea_cpuimx25.c b/arch/arm/mach-imx/mach-eukrea_cpuimx25.c
index 9da8d18eeb0..148cff2819b 100644
--- a/arch/arm/mach-imx/mach-eukrea_cpuimx25.c
+++ b/arch/arm/mach-imx/mach-eukrea_cpuimx25.c
@@ -36,8 +36,6 @@
 #include <asm/mach/map.h>
 #include <mach/common.h>
 #include <mach/mx25.h>
-#include <mach/mxc_nand.h>
-#include <mach/imxfb.h>
 #include <mach/iomux-mx25.h>
 
 #include "devices-imx25.h"
diff --git a/arch/arm/mach-imx/mach-imx27_visstrim_m10.c b/arch/arm/mach-imx/mach-imx27_visstrim_m10.c
index d7e0d219726..7ae43b1ec51 100644
--- a/arch/arm/mach-imx/mach-imx27_visstrim_m10.c
+++ b/arch/arm/mach-imx/mach-imx27_visstrim_m10.c
@@ -27,7 +27,6 @@
 #include <linux/mtd/physmap.h>
 #include <linux/i2c.h>
 #include <linux/i2c/pca953x.h>
-#include <linux/gpio_keys.h>
 #include <linux/input.h>
 #include <linux/gpio.h>
 #include <linux/delay.h>
@@ -130,19 +129,12 @@ static struct gpio_keys_button visstrim_gpio_keys[] = {
         }
 };
 
-static struct gpio_keys_platform_data visstrim_gpio_keys_platform_data = {
+static const struct gpio_keys_platform_data
+                visstrim_gpio_keys_platform_data __initconst = {
         .buttons        = visstrim_gpio_keys,
         .nbuttons       = ARRAY_SIZE(visstrim_gpio_keys),
 };
 
-static struct platform_device visstrim_gpio_keys_device = {
-        .name   = "gpio-keys",
-        .id     = -1,
-        .dev    = {
-                .platform_data  = &visstrim_gpio_keys_platform_data,
-        },
-};
-
 /* Visstrim_SM10 has a microSD slot connected to sdhc1 */
 static int visstrim_m10_sdhc1_init(struct device *dev,
                 irq_handler_t detect_irq, void *data)
@@ -186,7 +178,6 @@ static struct platform_device visstrim_m10_nor_mtd_device = {
 };
 
 static struct platform_device *platform_devices[] __initdata = {
-        &visstrim_gpio_keys_device,
         &visstrim_m10_nor_mtd_device,
 };
 
@@ -255,6 +246,7 @@ static void __init visstrim_m10_board_init(void)
         imx27_add_mxc_mmc(0, &visstrim_m10_sdhc_pdata);
         imx27_add_mxc_ehci_otg(&visstrim_m10_usbotg_pdata);
         imx27_add_fec(NULL);
+        imx_add_gpio_keys(&visstrim_gpio_keys_platform_data);
         platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
 }
 
diff --git a/arch/arm/mach-mx3/mach-kzm_arm11_01.c b/arch/arm/mach-imx/mach-kzm_arm11_01.c
index d35621d62b4..1ecae20cf4e 100644
--- a/arch/arm/mach-mx3/mach-kzm_arm11_01.c
+++ b/arch/arm/mach-imx/mach-kzm_arm11_01.c
@@ -39,7 +39,6 @@
 #include <mach/iomux-mx3.h>
 
 #include "devices-imx31.h"
-#include "devices.h"
 
 #define KZM_ARM11_IO_ADDRESS(x) (IOMEM(                                 \
         IMX_IO_P2V_MODULE(x, MX31_CS4) ?:                               \
diff --git a/arch/arm/mach-imx/mach-mx1ads.c b/arch/arm/mach-imx/mach-mx1ads.c
index 47cf56ac6d5..38ec5cbbda9 100644
--- a/arch/arm/mach-imx/mach-mx1ads.c
+++ b/arch/arm/mach-imx/mach-mx1ads.c
@@ -25,7 +25,6 @@
 
 #include <mach/common.h>
 #include <mach/hardware.h>
-#include <mach/i2c.h>
 #include <mach/iomux-mx1.h>
 #include <mach/irqs.h>
 
diff --git a/arch/arm/mach-imx/mach-mx21ads.c b/arch/arm/mach-imx/mach-mx21ads.c
index fa52a1086ea..74ac88978dd 100644
--- a/arch/arm/mach-imx/mach-mx21ads.c
+++ b/arch/arm/mach-imx/mach-mx21ads.c
@@ -25,7 +25,6 @@
 #include <asm/mach/time.h>
 #include <asm/mach/map.h>
 #include <mach/iomux-mx21.h>
-#include <mach/mxc_nand.h>
 
 #include "devices-imx21.h"
 
diff --git a/arch/arm/mach-imx/mach-mx25_3ds.c b/arch/arm/mach-imx/mach-mx25_3ds.c
index 06da438282a..58ea3fdf091 100644
--- a/arch/arm/mach-imx/mach-mx25_3ds.c
+++ b/arch/arm/mach-imx/mach-mx25_3ds.c
@@ -29,7 +29,6 @@
 #include <linux/irq.h>
 #include <linux/gpio.h>
 #include <linux/platform_device.h>
-#include <linux/input/matrix_keypad.h>
 #include <linux/usb/otg.h>
 
 #include <mach/hardware.h>
@@ -103,6 +102,8 @@ static iomux_v3_cfg_t mx25pdk_pads[] = {
         MX25_PAD_SD1_DATA1__SD1_DATA1,
         MX25_PAD_SD1_DATA2__SD1_DATA2,
         MX25_PAD_SD1_DATA3__SD1_DATA3,
+        MX25_PAD_A14__GPIO_2_0, /* WriteProtect */
+        MX25_PAD_A15__GPIO_2_1, /* CardDetect */
 
         /* I2C1 */
         MX25_PAD_I2C1_CLK__I2C1_CLK,
@@ -208,6 +209,14 @@ static const struct imxi2c_platform_data mx25_3ds_i2c0_data __initconst = {
         .bitrate = 100000,
 };
 
+#define SD1_GPIO_WP     IMX_GPIO_NR(2, 0)
+#define SD1_GPIO_CD     IMX_GPIO_NR(2, 1)
+
+static const struct esdhc_platform_data mx25pdk_esdhc_pdata __initconst = {
+        .wp_gpio = SD1_GPIO_WP,
+        .cd_gpio = SD1_GPIO_CD,
+};
+
 static void __init mx25pdk_init(void)
 {
         mxc_iomux_v3_setup_multiple_pads(mx25pdk_pads,
@@ -225,7 +234,7 @@ static void __init mx25pdk_init(void)
         imx25_add_fec(&mx25_fec_pdata);
         imx25_add_imx_keypad(&mx25pdk_keymap_data);
 
-        imx25_add_sdhci_esdhc_imx(0, NULL);
+        imx25_add_sdhci_esdhc_imx(0, &mx25pdk_esdhc_pdata);
         imx25_add_imx_i2c0(&mx25_3ds_i2c0_data);
 }
 
diff --git a/arch/arm/mach-imx/mach-mx27ads.c b/arch/arm/mach-imx/mach-mx27ads.c
index 367d1e4384c..1db79506f5e 100644
--- a/arch/arm/mach-imx/mach-mx27ads.c
+++ b/arch/arm/mach-imx/mach-mx27ads.c
@@ -29,7 +29,6 @@
 #include <asm/mach/map.h>
 #include <mach/gpio.h>
 #include <mach/iomux-mx27.h>
-#include <mach/mxc_nand.h>
 
 #include "devices-imx27.h"
 
diff --git a/arch/arm/mach-mx3/mach-mx31_3ds.c b/arch/arm/mach-imx/mach-mx31_3ds.c
index 034be624d35..9b982449cb5 100644
--- a/arch/arm/mach-mx3/mach-mx31_3ds.c
+++ b/arch/arm/mach-imx/mach-mx31_3ds.c
@@ -39,13 +39,8 @@
 #include <mach/iomux-mx3.h>
 #include <mach/3ds_debugboard.h>
 #include <mach/ulpi.h>
-#include <mach/mmc.h>
-#include <mach/ipu.h>
-#include <mach/mx3fb.h>
-#include <mach/mx3_camera.h>
 
 #include "devices-imx31.h"
-#include "devices.h"
 
 /* CPLD IRQ line for external uart, external ethernet etc */
 #define EXPIO_PARENT_INT        IOMUX_TO_IRQ(MX31_PIN_GPIO1_1)
@@ -178,22 +173,37 @@ static struct gpio mx31_3ds_camera_gpios[] = {
         { MX31_3DS_GPIO_CAMERA_RST, GPIOF_OUT_INIT_HIGH, "camera-reset" },
 };
 
-static int __init mx31_3ds_camera_alloc_dma(void)
+static const struct mx3_camera_pdata mx31_3ds_camera_pdata __initconst = {
+        .flags = MX3_CAMERA_DATAWIDTH_10,
+        .mclk_10khz = 2600,
+};
+
+static int __init mx31_3ds_init_camera(void)
 {
-        int dma;
+        int dma, ret = -ENOMEM;
+        struct platform_device *pdev =
+                imx31_alloc_mx3_camera(&mx31_3ds_camera_pdata);
+
+        if (IS_ERR(pdev))
+                return PTR_ERR(pdev);
 
         if (!mx3_camera_base)
-                return -ENOMEM;
+                goto err;
 
-        dma = dma_declare_coherent_memory(&mx3_camera.dev,
+        dma = dma_declare_coherent_memory(&pdev->dev,
                                         mx3_camera_base, mx3_camera_base,
                                         MX31_3DS_CAMERA_BUF_SIZE,
                                         DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE);
 
         if (!(dma & DMA_MEMORY_MAP))
-                return -ENOMEM;
+                goto err;
 
-        return 0;
+        ret = platform_device_add(pdev);
+        if (ret)
+err:
+                platform_device_put(pdev);
+
+        return ret;
 }
 
 static int mx31_3ds_camera_power(struct device *dev, int on)
@@ -241,12 +251,6 @@ static struct platform_device mx31_3ds_ov2640 = {
         },
 };
 
-struct mx3_camera_pdata mx31_3ds_camera_pdata = {
-        .dma_dev        = &mx3_ipu.dev,
-        .flags          = MX3_CAMERA_DATAWIDTH_10,
-        .mclk_10khz     = 2600,
-};
-
 /*
  * FB support
  */
@@ -273,8 +277,7 @@ static struct ipu_platform_data mx3_ipu_data = {
         .irq_base = MXC_IPU_IRQ_START,
 };
 
-static struct mx3fb_platform_data mx3fb_pdata = {
-        .dma_dev        = &mx3_ipu.dev,
+static struct mx3fb_platform_data mx3fb_pdata __initdata = {
         .name           = "Epson-VGA",
         .mode           = fb_modedb,
         .num_modes      = ARRAY_SIZE(fb_modedb),
@@ -723,8 +726,8 @@ static void __init mx31_3ds_init(void)
         imx31_add_mxc_mmc(0, &sdhc1_pdata);
 
         imx31_add_spi_imx0(&spi0_pdata);
-        mxc_register_device(&mx3_ipu, &mx3_ipu_data);
-        mxc_register_device(&mx3_fb, &mx3fb_pdata);
+        imx31_add_ipu_core(&mx3_ipu_data);
+        imx31_add_mx3_sdc_fb(&mx3fb_pdata);
 
         /* CSI */
         /* Camera power: default - off */
@@ -735,10 +738,7 @@ static void __init mx31_3ds_init(void)
                 iclink_ov2640.power = NULL;
         }
 
-        if (!mx31_3ds_camera_alloc_dma())
-                mxc_register_device(&mx3_camera, &mx31_3ds_camera_pdata);
-        else
-                pr_err("Failed to allocate dma memory for camera");
+        mx31_3ds_init_camera();
 }
 
 static void __init mx31_3ds_timer_init(void)
diff --git a/arch/arm/mach-mx3/mach-mx31ads.c b/arch/arm/mach-imx/mach-mx31ads.c
index 3d095d69bc6..f4dee025463 100644
--- a/arch/arm/mach-mx3/mach-mx31ads.c
+++ b/arch/arm/mach-imx/mach-mx31ads.c
@@ -38,7 +38,6 @@
 #endif
 
 #include "devices-imx31.h"
-#include "devices.h"
 
 /* PBC Board interrupt status register */
 #define PBC_INTSTATUS           0x000016
diff --git a/arch/arm/mach-mx3/mach-mx31lilly.c b/arch/arm/mach-imx/mach-mx31lilly.c
index ed95745163b..410e676ae08 100644
--- a/arch/arm/mach-mx3/mach-mx31lilly.c
+++ b/arch/arm/mach-imx/mach-mx31lilly.c
@@ -46,7 +46,6 @@
 #include <mach/ulpi.h>
 
 #include "devices-imx31.h"
-#include "devices.h"
 
 /*
  * This file contains module-specific initialization routines for LILLY-1131.
diff --git a/arch/arm/mach-mx3/mach-mx31lite.c b/arch/arm/mach-imx/mach-mx31lite.c
index 24a21a384bf..ac9b4cad320 100644
--- a/arch/arm/mach-mx3/mach-mx31lite.c
+++ b/arch/arm/mach-imx/mach-mx31lite.c
@@ -44,7 +44,6 @@
 #include <mach/ulpi.h>
 
 #include "devices-imx31.h"
-#include "devices.h"
 
 /*
  * This file contains the module-specific initialization routines.
diff --git a/arch/arm/mach-mx3/mach-mx31moboard.c b/arch/arm/mach-imx/mach-mx31moboard.c
index 3a021b01161..eaa51e49ca9 100644
--- a/arch/arm/mach-mx3/mach-mx31moboard.c
+++ b/arch/arm/mach-imx/mach-mx31moboard.c
@@ -27,6 +27,7 @@
 #include <linux/mfd/mc13783.h>
 #include <linux/spi/spi.h>
 #include <linux/types.h>
+#include <linux/memblock.h>
 
 #include <linux/usb/otg.h>
 #include <linux/usb/ulpi.h>
@@ -39,13 +40,9 @@
 #include <mach/common.h>
 #include <mach/hardware.h>
 #include <mach/iomux-mx3.h>
-#include <mach/ipu.h>
-#include <mach/mx3_camera.h>
-#include <mach/spi.h>
 #include <mach/ulpi.h>
 
 #include "devices-imx31.h"
-#include "devices.h"
 
 static unsigned int moboard_pins[] = {
         /* UART0 */
@@ -102,7 +99,7 @@ static unsigned int moboard_pins[] = {
 };
 
 static struct physmap_flash_data mx31moboard_flash_data = {
-        .width          = 2,
+        .width  = 2,
 };
 
 static struct resource mx31moboard_flash_resource = {
@@ -194,8 +191,8 @@ static struct regulator_init_data sdhc_vreg_data = {
 
 static struct regulator_consumer_supply cam_consumers[] = {
         {
-                .dev    = &mx3_camera.dev,
-                .supply = "cam_vcc",
+                .dev_name = "mx3_camera.0",
+                .supply = "cam_vcc",
         },
 };
 
@@ -430,9 +427,9 @@ static int __init moboard_usbh2_init(void)
 
 static struct gpio_led mx31moboard_leds[] = {
         {
-                .name   = "coreboard-led-0:red:running",
+                .name   = "coreboard-led-0:red:running",
                 .default_trigger = "heartbeat",
-                .gpio   = IOMUX_TO_GPIO(MX31_PIN_SVEN0),
+                .gpio   = IOMUX_TO_GPIO(MX31_PIN_SVEN0),
         }, {
                 .name   = "coreboard-led-1:red",
                 .gpio   = IOMUX_TO_GPIO(MX31_PIN_STX0),
@@ -446,7 +443,7 @@ static struct gpio_led mx31moboard_leds[] = {
 };
 
 static struct gpio_led_platform_data mx31moboard_led_pdata = {
-        .num_leds       = ARRAY_SIZE(mx31moboard_leds),
+        .num_leds       = ARRAY_SIZE(mx31moboard_leds),
         .leds           = mx31moboard_leds,
 };
 
@@ -458,7 +455,7 @@ static struct platform_device mx31moboard_leds_device = {
         },
 };
 
-static struct ipu_platform_data mx3_ipu_data = {
+static const struct ipu_platform_data mx3_ipu_data __initconst = {
         .irq_base = MXC_IPU_IRQ_START,
 };
 
@@ -467,37 +464,39 @@ static struct platform_device *devices[] __initdata = {
         &mx31moboard_leds_device,
 };
 
-static struct mx3_camera_pdata camera_pdata = {
-        .dma_dev        = &mx3_ipu.dev,
+static struct mx3_camera_pdata camera_pdata __initdata = {
         .flags          = MX3_CAMERA_DATAWIDTH_8 | MX3_CAMERA_DATAWIDTH_10,
         .mclk_10khz     = 4800,
 };
 
-#define CAMERA_BUF_SIZE (4*1024*1024)
+static phys_addr_t mx3_camera_base __initdata;
+#define MX3_CAMERA_BUF_SIZE SZ_4M
 
-static int __init mx31moboard_cam_alloc_dma(const size_t buf_size)
+static int __init mx31moboard_init_cam(void)
 {
-        dma_addr_t dma_handle;
-        void *buf;
-        int dma;
-
-        if (buf_size < 2 * 1024 * 1024)
-                return -EINVAL;
+        int dma, ret = -ENOMEM;
+        struct platform_device *pdev;
 
-        buf = dma_alloc_coherent(NULL, buf_size, &dma_handle, GFP_KERNEL);
-        if (!buf) {
-                pr_err("%s: cannot allocate camera buffer-memory\n", __func__);
-                return -ENOMEM;
-        }
+        imx31_add_ipu_core(&mx3_ipu_data);
 
-        memset(buf, 0, buf_size);
+        pdev = imx31_alloc_mx3_camera(&camera_pdata);
+        if (IS_ERR(pdev))
+                return PTR_ERR(pdev);
 
-        dma = dma_declare_coherent_memory(&mx3_camera.dev,
-                                        dma_handle, dma_handle, buf_size,
+        dma = dma_declare_coherent_memory(&pdev->dev,
+                                        mx3_camera_base, mx3_camera_base,
+                                        MX3_CAMERA_BUF_SIZE,
                                         DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE);
+        if (!(dma & DMA_MEMORY_MAP))
+                goto err;
+
+        ret = platform_device_add(pdev);
+        if (ret)
+err:
+                platform_device_put(pdev);
+
+        return ret;
 
-        /* The way we call dma_declare_coherent_memory only a malloc can fail */
-        return dma & DMA_MEMORY_MAP ? 0 : -ENOMEM;
 }
 
 static int mx31moboard_baseboard;
@@ -529,9 +528,7 @@ static void __init mx31moboard_init(void)
 
         imx31_add_mxc_mmc(0, &sdhc1_pdata);
 
-        mxc_register_device(&mx3_ipu, &mx3_ipu_data);
-        if (!mx31moboard_cam_alloc_dma(CAMERA_BUF_SIZE))
-                mxc_register_device(&mx3_camera, &camera_pdata);
+        mx31moboard_init_cam();
 
         usb_xcvr_reset();
 
@@ -565,9 +562,19 @@ struct sys_timer mx31moboard_timer = {
         .init   = mx31moboard_timer_init,
 };
 
+static void __init mx31moboard_reserve(void)
+{
+        /* reserve 4 MiB for mx3-camera */
+        mx3_camera_base = memblock_alloc(MX3_CAMERA_BUF_SIZE,
+                        MX3_CAMERA_BUF_SIZE);
+        memblock_free(mx3_camera_base, MX3_CAMERA_BUF_SIZE);
+        memblock_remove(mx3_camera_base, MX3_CAMERA_BUF_SIZE);
+}
+
 MACHINE_START(MX31MOBOARD, "EPFL Mobots mx31moboard")
         /* Maintainer: Valentin Longchamp, EPFL Mobots group */
         .boot_params = MX3x_PHYS_OFFSET + 0x100,
+        .reserve = mx31moboard_reserve,
         .map_io = mx31_map_io,
         .init_early = imx31_init_early,
         .init_irq = mx31_init_irq,
diff --git a/arch/arm/mach-mx3/mach-mx35_3ds.c b/arch/arm/mach-imx/mach-mx35_3ds.c
index ff5fe231b8d..882880ac1bb 100644
--- a/arch/arm/mach-mx3/mach-mx35_3ds.c
+++ b/arch/arm/mach-imx/mach-mx35_3ds.c
@@ -42,7 +42,6 @@
 #include <mach/3ds_debugboard.h>
 
 #include "devices-imx35.h"
-#include "devices.h"
 
 #define EXPIO_PARENT_INT        (MXC_INTERNAL_IRQS + GPIO_PORTA + 1)
 
diff --git a/arch/arm/mach-imx/mach-mxt_td60.c b/arch/arm/mach-imx/mach-mxt_td60.c
index 69787c30c32..2774541511e 100644
--- a/arch/arm/mach-imx/mach-mxt_td60.c
+++ b/arch/arm/mach-imx/mach-mxt_td60.c
@@ -29,7 +29,6 @@
 #include <asm/mach/map.h>
 #include <linux/gpio.h>
 #include <mach/iomux-mx27.h>
-#include <mach/mxc_nand.h>
 #include <linux/i2c/pca953x.h>
 
 #include "devices-imx27.h"
diff --git a/arch/arm/mach-imx/mach-pca100.c b/arch/arm/mach-imx/mach-pca100.c
index 63e18255677..bbddc5a11c4 100644
--- a/arch/arm/mach-imx/mach-pca100.c
+++ b/arch/arm/mach-imx/mach-pca100.c
@@ -37,7 +37,6 @@
 #include <mach/iomux-mx27.h>
 #include <asm/mach/time.h>
 #include <mach/audmux.h>
-#include <mach/mxc_nand.h>
 #include <mach/irqs.h>
 #include <mach/ulpi.h>
 
diff --git a/arch/arm/mach-mx3/mach-pcm037.c b/arch/arm/mach-imx/mach-pcm037.c
index f07d3bded67..89c213b8129 100644
--- a/arch/arm/mach-mx3/mach-pcm037.c
+++ b/arch/arm/mach-imx/mach-pcm037.c
@@ -31,6 +31,7 @@
 #include <linux/usb/otg.h>
 #include <linux/usb/ulpi.h>
 #include <linux/gfp.h>
+#include <linux/memblock.h>
 
 #include <media/soc_camera.h>
 
@@ -41,13 +42,9 @@
 #include <mach/common.h>
 #include <mach/hardware.h>
 #include <mach/iomux-mx3.h>
-#include <mach/ipu.h>
-#include <mach/mx3_camera.h>
-#include <mach/mx3fb.h>
 #include <mach/ulpi.h>
 
 #include "devices-imx31.h"
-#include "devices.h"
 #include "pcm037.h"
 
 static enum pcm037_board_variant pcm037_instance = PCM037_PCM970;
@@ -404,35 +401,35 @@ static const struct imxmmc_platform_data sdhc_pdata __initconst = {
         .exit = pcm970_sdhc1_exit,
 };
 
-struct mx3_camera_pdata camera_pdata = {
-        .dma_dev        = &mx3_ipu.dev,
+struct mx3_camera_pdata camera_pdata __initdata = {
         .flags          = MX3_CAMERA_DATAWIDTH_8 | MX3_CAMERA_DATAWIDTH_10,
         .mclk_10khz     = 2000,
 };
 
-static int __init pcm037_camera_alloc_dma(const size_t buf_size)
-{
-        dma_addr_t dma_handle;
-        void *buf;
-        int dma;
-
-        if (buf_size < 2 * 1024 * 1024)
-                return -EINVAL;
+static phys_addr_t mx3_camera_base __initdata;
+#define MX3_CAMERA_BUF_SIZE SZ_4M
 
-        buf = dma_alloc_coherent(NULL, buf_size, &dma_handle, GFP_KERNEL);
-        if (!buf) {
-                pr_err("%s: cannot allocate camera buffer-memory\n", __func__);
-                return -ENOMEM;
-        }
+static int __init pcm037_init_camera(void)
+{
+        int dma, ret = -ENOMEM;
+        struct platform_device *pdev = imx31_alloc_mx3_camera(&camera_pdata);
 
-        memset(buf, 0, buf_size);
+        if (IS_ERR(pdev))
+                return PTR_ERR(pdev);
 
-        dma = dma_declare_coherent_memory(&mx3_camera.dev,
-                                        dma_handle, dma_handle, buf_size,
+        dma = dma_declare_coherent_memory(&pdev->dev,
+                                        mx3_camera_base, mx3_camera_base,
+                                        MX3_CAMERA_BUF_SIZE,
                                         DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE);
+        if (!(dma & DMA_MEMORY_MAP))
+                goto err;
+
+        ret = platform_device_add(pdev);
+        if (ret)
+err:
+                platform_device_put(pdev);
 
-        /* The way we call dma_declare_coherent_memory only a malloc can fail */
-        return dma & DMA_MEMORY_MAP ? 0 : -ENOMEM;
+        return ret;
 }
 
 static struct platform_device *devices[] __initdata = {
@@ -442,7 +439,7 @@ static struct platform_device *devices[] __initdata = {
         &pcm037_mt9v022,
 };
 
-static struct ipu_platform_data mx3_ipu_data = {
+static const struct ipu_platform_data mx3_ipu_data __initconst = {
         .irq_base = MXC_IPU_IRQ_START,
 };
 
@@ -500,7 +497,6 @@ static const struct fb_videomode fb_modedb[] = {
 };
 
 static struct mx3fb_platform_data mx3fb_pdata = {
-        .dma_dev        = &mx3_ipu.dev,
         .name           = "Sharp-LQ035Q7DH06-QVGA",
         .mode           = fb_modedb,
         .num_modes      = ARRAY_SIZE(fb_modedb),
@@ -638,8 +634,8 @@ static void __init pcm037_init(void)
 
         imx31_add_mxc_nand(&pcm037_nand_board_info);
         imx31_add_mxc_mmc(0, &sdhc_pdata);
-        mxc_register_device(&mx3_ipu, &mx3_ipu_data);
-        mxc_register_device(&mx3_fb, &mx3fb_pdata);
+        imx31_add_ipu_core(&mx3_ipu_data);
+        imx31_add_mx3_sdc_fb(&mx3fb_pdata);
 
         /* CSI */
         /* Camera power: default - off */
@@ -649,8 +645,7 @@ static void __init pcm037_init(void)
         else
                 iclink_mt9t031.power = NULL;
 
-        if (!pcm037_camera_alloc_dma(4 * 1024 * 1024))
-                mxc_register_device(&mx3_camera, &camera_pdata);
+        pcm037_init_camera();
 
         platform_device_register(&pcm970_sja1000);
 
@@ -680,9 +675,19 @@ struct sys_timer pcm037_timer = {
         .init   = pcm037_timer_init,
 };
 
+static void __init pcm037_reserve(void)
+{
+        /* reserve 4 MiB for mx3-camera */
+        mx3_camera_base = memblock_alloc(MX3_CAMERA_BUF_SIZE,
+                        MX3_CAMERA_BUF_SIZE);
+        memblock_free(mx3_camera_base, MX3_CAMERA_BUF_SIZE);
+        memblock_remove(mx3_camera_base, MX3_CAMERA_BUF_SIZE);
+}
+
 MACHINE_START(PCM037, "Phytec Phycore pcm037")
         /* Maintainer: Pengutronix */
         .boot_params = MX3x_PHYS_OFFSET + 0x100,
+        .reserve = pcm037_reserve,
         .map_io = mx31_map_io,
         .init_early = imx31_init_early,
         .init_irq = mx31_init_irq,
diff --git a/arch/arm/mach-mx3/mach-pcm037_eet.c b/arch/arm/mach-imx/mach-pcm037_eet.c
index df6fb07d037..1b7606bef8f 100644
--- a/arch/arm/mach-mx3/mach-pcm037_eet.c
+++ b/arch/arm/mach-imx/mach-pcm037_eet.c
@@ -7,19 +7,16 @@
  * published by the Free Software Foundation.
  */
 #include <linux/gpio.h>
-#include <linux/gpio_keys.h>
 #include <linux/input.h>
 #include <linux/platform_device.h>
 #include <linux/spi/spi.h>
 
 #include <mach/common.h>
 #include <mach/iomux-mx3.h>
-#include <mach/spi.h>
 
 #include <asm/mach-types.h>
 
 #include "pcm037.h"
-#include "devices.h"
 #include "devices-imx31.h"
 
 static unsigned int pcm037_eet_pins[] = {
@@ -156,20 +153,13 @@ static struct gpio_keys_button pcm037_gpio_keys[] = {
         },
 };
 
-static struct gpio_keys_platform_data pcm037_gpio_keys_platform_data = {
+static const struct gpio_keys_platform_data
+                pcm037_gpio_keys_platform_data __initconst = {
         .buttons        = pcm037_gpio_keys,
         .nbuttons       = ARRAY_SIZE(pcm037_gpio_keys),
         .rep            = 0, /* No auto-repeat */
 };
 
-static struct platform_device pcm037_gpio_keys_device = {
-        .name   = "gpio-keys",
-        .id     = -1,
-        .dev    = {
-                .platform_data  = &pcm037_gpio_keys_platform_data,
-        },
-};
-
 static int __init eet_init_devices(void)
 {
         if (!machine_is_pcm037() || pcm037_variant() != PCM037_EET)
@@ -182,9 +172,8 @@ static int __init eet_init_devices(void)
         spi_register_board_info(pcm037_spi_dev, ARRAY_SIZE(pcm037_spi_dev));
         imx31_add_spi_imx0(&pcm037_spi1_pdata);
 
-        platform_device_register(&pcm037_gpio_keys_device);
+        imx_add_gpio_keys(&pcm037_gpio_keys_platform_data);
 
         return 0;
 }
-
 late_initcall(eet_init_devices);
diff --git a/arch/arm/mach-imx/mach-pcm038.c b/arch/arm/mach-imx/mach-pcm038.c
index 4cbce6d0fef..853bb871c7e 100644
--- a/arch/arm/mach-imx/mach-pcm038.c
+++ b/arch/arm/mach-imx/mach-pcm038.c
@@ -36,7 +36,6 @@
 #include <mach/common.h>
 #include <mach/hardware.h>
 #include <mach/iomux-mx27.h>
-#include <mach/mxc_nand.h>
 #include <mach/ulpi.h>
 
 #include "devices-imx27.h"
diff --git a/arch/arm/mach-mx3/mach-pcm043.c b/arch/arm/mach-imx/mach-pcm043.c
index 036ba1a4704..026441628df 100644
--- a/arch/arm/mach-mx3/mach-pcm043.c
+++ b/arch/arm/mach-imx/mach-pcm043.c
@@ -36,14 +36,10 @@
 #include <mach/hardware.h>
 #include <mach/common.h>
 #include <mach/iomux-mx35.h>
-#include <mach/ipu.h>
-#include <mach/mx3fb.h>
 #include <mach/ulpi.h>
 #include <mach/audmux.h>
-#include <mach/esdhc.h>
 
 #include "devices-imx35.h"
-#include "devices.h"
 
 static const struct fb_videomode fb_modedb[] = {
         {
@@ -81,12 +77,11 @@ static const struct fb_videomode fb_modedb[] = {
         },
 };
 
-static struct ipu_platform_data mx3_ipu_data = {
+static const struct ipu_platform_data mx3_ipu_data __initconst = {
         .irq_base = MXC_IPU_IRQ_START,
 };
 
-static struct mx3fb_platform_data mx3fb_pdata = {
-        .dma_dev        = &mx3_ipu.dev,
+static struct mx3fb_platform_data mx3fb_pdata __initdata = {
         .name           = "Sharp-LQ035Q7",
         .mode           = fb_modedb,
         .num_modes      = ARRAY_SIZE(fb_modedb),
@@ -127,12 +122,12 @@ static struct at24_platform_data board_eeprom = {
 };
 
 static struct i2c_board_info pcm043_i2c_devices[] = {
-       {
+        {
                 I2C_BOARD_INFO("at24", 0x52), /* E0=0, E1=1, E2=0 */
                 .platform_data = &board_eeprom,
         }, {
                 I2C_BOARD_INFO("pcf8563", 0x51),
-        }
+        },
 };
 
 static struct platform_device *devices[] __initdata = {
@@ -390,8 +385,8 @@ static void __init pcm043_init(void)
 
         imx35_add_imx_i2c0(&pcm043_i2c0_data);
 
-        mxc_register_device(&mx3_ipu, &mx3_ipu_data);
-        mxc_register_device(&mx3_fb, &mx3fb_pdata);
+        imx35_add_ipu_core(&mx3_ipu_data);
+        imx35_add_mx3_sdc_fb(&mx3fb_pdata);
 
         if (otg_mode_host) {
                 otg_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
diff --git a/arch/arm/mach-mx3/mach-qong.c b/arch/arm/mach-imx/mach-qong.c
index 17f758b7762..c1632871593 100644
--- a/arch/arm/mach-mx3/mach-qong.c
+++ b/arch/arm/mach-imx/mach-qong.c
@@ -33,24 +33,23 @@
 #include <mach/iomux-mx3.h>
 
 #include "devices-imx31.h"
-#include "devices.h"
 
 /* FPGA defines */
 #define QONG_FPGA_VERSION(major, minor, rev)    \
         (((major & 0xF) << 12) | ((minor & 0xF) << 8) | (rev & 0xFF))
 
-#define QONG_FPGA_BASEADDR              MX31_CS1_BASE_ADDR
-#define QONG_FPGA_PERIPH_SIZE           (1 << 24)
+#define QONG_FPGA_BASEADDR              MX31_CS1_BASE_ADDR
+#define QONG_FPGA_PERIPH_SIZE           (1 << 24)
 
 #define QONG_FPGA_CTRL_BASEADDR         QONG_FPGA_BASEADDR
-#define QONG_FPGA_CTRL_SIZE             0x10
+#define QONG_FPGA_CTRL_SIZE             0x10
 /* FPGA control registers */
 #define QONG_FPGA_CTRL_VERSION          0x00
 
 #define QONG_DNET_ID            1
 #define QONG_DNET_BASEADDR      \
         (QONG_FPGA_BASEADDR + QONG_DNET_ID * QONG_FPGA_PERIPH_SIZE)
-#define QONG_DNET_SIZE          0x00001000
+#define QONG_DNET_SIZE          0x00001000
 
 #define QONG_FPGA_IRQ           IOMUX_TO_IRQ(MX31_PIN_DTR_DCE1)
 
@@ -166,15 +165,15 @@ static struct platform_nand_data qong_nand_data = {
                 .options                = 0,
         },
         .ctrl = {
-                .cmd_ctrl               = qong_nand_cmd_ctrl,
+                .cmd_ctrl               = qong_nand_cmd_ctrl,
                 .dev_ready              = qong_nand_device_ready,
                 .select_chip            = qong_nand_select_chip,
         }
 };
 
 static struct resource qong_nand_resource = {
-        .start          = MX31_CS3_BASE_ADDR,
-        .end            = MX31_CS3_BASE_ADDR + SZ_32M - 1,
+        .start          = MX31_CS3_BASE_ADDR,
+        .end            = MX31_CS3_BASE_ADDR + SZ_32M - 1,
         .flags          = IORESOURCE_MEM,
 };
 
diff --git a/arch/arm/mach-mx3/mach-vpr200.c b/arch/arm/mach-imx/mach-vpr200.c
index 47a69cbc31a..d74e3473d23 100644
--- a/arch/arm/mach-mx3/mach-vpr200.c
+++ b/arch/arm/mach-imx/mach-vpr200.c
@@ -32,16 +32,12 @@
 #include <mach/common.h>
 #include <mach/iomux-mx35.h>
 #include <mach/irqs.h>
-#include <mach/ipu.h>
-#include <mach/mx3fb.h>
 
 #include <linux/i2c.h>
 #include <linux/i2c/at24.h>
 #include <linux/mfd/mc13xxx.h>
-#include <linux/gpio_keys.h>
 
 #include "devices-imx35.h"
-#include "devices.h"
 
 #define GPIO_LCDPWR     IMX_GPIO_NR(1, 2)
 #define GPIO_PMIC_INT   IMX_GPIO_NR(2, 0)
@@ -91,12 +87,11 @@ static const struct fb_videomode fb_modedb[] = {
         }
 };
 
-static struct ipu_platform_data mx3_ipu_data = {
+static const struct ipu_platform_data mx3_ipu_data __initconst = {
         .irq_base = MXC_IPU_IRQ_START,
 };
 
-static struct mx3fb_platform_data mx3fb_pdata = {
-        .dma_dev        = &mx3_ipu.dev,
+static struct mx3fb_platform_data mx3fb_pdata __initdata = {
         .name           = "PT0708048",
         .mode           = fb_modedb,
         .num_modes      = ARRAY_SIZE(fb_modedb),
@@ -141,18 +136,12 @@ static struct gpio_keys_button vpr200_gpio_keys_table[] = {
         {KEY_F9, GPIO_BUTTON8, 1, "vpr-keys: F9", 1, VPR_KEY_DEBOUNCE},
 };
 
-static struct gpio_keys_platform_data vpr200_gpio_keys_data = {
+static const struct gpio_keys_platform_data
+                vpr200_gpio_keys_data __initconst = {
         .buttons = vpr200_gpio_keys_table,
         .nbuttons = ARRAY_SIZE(vpr200_gpio_keys_table),
 };
 
-static struct platform_device vpr200_device_gpiokeys = {
-        .name = "gpio-keys",
-        .dev = {
-                .platform_data = &vpr200_gpio_keys_data,
-        }
-};
-
 static struct mc13xxx_platform_data vpr200_pmic = {
         .flags = MC13XXX_USE_ADC | MC13XXX_USE_TOUCHSCREEN,
 };
@@ -271,7 +260,6 @@ static const struct mxc_usbh_platform_data usb_host_pdata __initconst = {
 
 static struct platform_device *devices[] __initdata = {
         &vpr200_flash,
-        &vpr200_device_gpiokeys,
 };
 
 /*
@@ -283,6 +271,7 @@ static void __init vpr200_board_init(void)
 
         imx35_add_fec(NULL);
         imx35_add_imx2_wdt(NULL);
+        imx_add_gpio_keys(&vpr200_gpio_keys_data);
 
         platform_add_devices(devices, ARRAY_SIZE(devices));
 
@@ -299,8 +288,8 @@ static void __init vpr200_board_init(void)
         imx35_add_imx_uart0(NULL);
         imx35_add_imx_uart2(NULL);
 
-        mxc_register_device(&mx3_ipu, &mx3_ipu_data);
-        mxc_register_device(&mx3_fb, &mx3fb_pdata);
+        imx35_add_ipu_core(&mx3_ipu_data);
+        imx35_add_mx3_sdc_fb(&mx3fb_pdata);
 
         imx35_add_fsl_usb2_udc(&otg_device_pdata);
         imx35_add_mxc_ehci_hs(&usb_host_pdata);
diff --git a/arch/arm/mach-imx/mm-imx31.c b/arch/arm/mach-imx/mm-imx31.c
new file mode 100644
index 00000000000..86b9b45864d
--- /dev/null
+++ b/arch/arm/mach-imx/mm-imx31.c
@@ -0,0 +1,66 @@
+/*
+ *  Copyright (C) 1999,2000 Arm Limited
+ *  Copyright (C) 2000 Deep Blue Solutions Ltd
+ *  Copyright (C) 2002 Shane Nay (shane@minirl.com)
+ *  Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ *    - add MX31 specific definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/mm.h>
+#include <linux/init.h>
+#include <linux/err.h>
+
+#include <asm/pgtable.h>
+#include <asm/mach/map.h>
+
+#include <mach/common.h>
+#include <mach/hardware.h>
+#include <mach/iomux-v3.h>
+#include <mach/gpio.h>
+#include <mach/irqs.h>
+
+static struct map_desc mx31_io_desc[] __initdata = {
+        imx_map_entry(MX31, X_MEMC, MT_DEVICE),
+        imx_map_entry(MX31, AVIC, MT_DEVICE_NONSHARED),
+        imx_map_entry(MX31, AIPS1, MT_DEVICE_NONSHARED),
+        imx_map_entry(MX31, AIPS2, MT_DEVICE_NONSHARED),
+        imx_map_entry(MX31, SPBA0, MT_DEVICE_NONSHARED),
+};
+
+/*
+ * This function initializes the memory map. It is called during the
+ * system startup to create static physical to virtual memory mappings
+ * for the IO modules.
+ */
+void __init mx31_map_io(void)
+{
+        iotable_init(mx31_io_desc, ARRAY_SIZE(mx31_io_desc));
+}
+
+void __init imx31_init_early(void)
+{
+        mxc_set_cpu_type(MXC_CPU_MX31);
+        mxc_arch_reset_init(MX31_IO_ADDRESS(MX31_WDOG_BASE_ADDR));
+}
+
+static struct mxc_gpio_port imx31_gpio_ports[] = {
+        DEFINE_IMX_GPIO_PORT_IRQ(MX31, 0, 1, MX31_INT_GPIO1),
+        DEFINE_IMX_GPIO_PORT_IRQ(MX31, 1, 2, MX31_INT_GPIO2),
+        DEFINE_IMX_GPIO_PORT_IRQ(MX31, 2, 3, MX31_INT_GPIO3),
+};
+
+void __init mx31_init_irq(void)
+{
+        mxc_init_irq(MX31_IO_ADDRESS(MX31_AVIC_BASE_ADDR));
+        mxc_gpio_init(imx31_gpio_ports, ARRAY_SIZE(imx31_gpio_ports));
+}
diff --git a/arch/arm/mach-imx/mm-imx35.c b/arch/arm/mach-imx/mm-imx35.c
new file mode 100644
index 00000000000..c880e6d1ae5
--- /dev/null
+++ b/arch/arm/mach-imx/mm-imx35.c
@@ -0,0 +1,63 @@
+/*
+ *  Copyright (C) 1999,2000 Arm Limited
+ *  Copyright (C) 2000 Deep Blue Solutions Ltd
+ *  Copyright (C) 2002 Shane Nay (shane@minirl.com)
+ *  Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ *    - add MX31 specific definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/mm.h>
+#include <linux/init.h>
+#include <linux/err.h>
+
+#include <asm/pgtable.h>
+#include <asm/mach/map.h>
+#include <asm/hardware/cache-l2x0.h>
+
+#include <mach/common.h>
+#include <mach/hardware.h>
+#include <mach/iomux-v3.h>
+#include <mach/gpio.h>
+#include <mach/irqs.h>
+
+static struct map_desc mx35_io_desc[] __initdata = {
+        imx_map_entry(MX35, X_MEMC, MT_DEVICE),
+        imx_map_entry(MX35, AVIC, MT_DEVICE_NONSHARED),
+        imx_map_entry(MX35, AIPS1, MT_DEVICE_NONSHARED),
+        imx_map_entry(MX35, AIPS2, MT_DEVICE_NONSHARED),
+        imx_map_entry(MX35, SPBA0, MT_DEVICE_NONSHARED),
+};
+
+void __init mx35_map_io(void)
+{
+        iotable_init(mx35_io_desc, ARRAY_SIZE(mx35_io_desc));
+}
+
+void __init imx35_init_early(void)
+{
+        mxc_set_cpu_type(MXC_CPU_MX35);
+        mxc_iomux_v3_init(MX35_IO_ADDRESS(MX35_IOMUXC_BASE_ADDR));
+        mxc_arch_reset_init(MX35_IO_ADDRESS(MX35_WDOG_BASE_ADDR));
+}
+
+static struct mxc_gpio_port imx35_gpio_ports[] = {
+        DEFINE_IMX_GPIO_PORT_IRQ(MX35, 0, 1, MX35_INT_GPIO1),
+        DEFINE_IMX_GPIO_PORT_IRQ(MX35, 1, 2, MX35_INT_GPIO2),
+        DEFINE_IMX_GPIO_PORT_IRQ(MX35, 2, 3, MX35_INT_GPIO3),
+};
+
+void __init mx35_init_irq(void)
+{
+        mxc_init_irq(MX35_IO_ADDRESS(MX35_AVIC_BASE_ADDR));
+        mxc_gpio_init(imx35_gpio_ports, ARRAY_SIZE(imx35_gpio_ports));
+}
diff --git a/arch/arm/mach-mx3/mx31lilly-db.c b/arch/arm/mach-imx/mx31lilly-db.c
index 8f1a38ebf5c..7d26f766a4e 100644
--- a/arch/arm/mach-mx3/mx31lilly-db.c
+++ b/arch/arm/mach-imx/mx31lilly-db.c
@@ -34,11 +34,8 @@
 #include <mach/common.h>
 #include <mach/iomux-mx3.h>
 #include <mach/board-mx31lilly.h>
-#include <mach/mx3fb.h>
-#include <mach/ipu.h>
 
 #include "devices-imx31.h"
-#include "devices.h"
 
 /*
  * This file contains board-specific initialization routines for the
@@ -164,13 +161,13 @@ static const struct imxmmc_platform_data mmc_pdata __initconst = {
 };
 
 /* Framebuffer support */
-static struct ipu_platform_data ipu_data __initdata = {
+static const struct ipu_platform_data ipu_data __initconst = {
         .irq_base = MXC_IPU_IRQ_START,
 };
 
 static const struct fb_videomode fb_modedb = {
         /* 640x480 TFT panel (IPS-056T) */
-        .name           = "CRT-VGA",
+        .name           = "CRT-VGA",
         .refresh        = 64,
         .xres           = 640,
         .yres           = 480,
@@ -187,7 +184,6 @@ static const struct fb_videomode fb_modedb = {
 };
 
 static struct mx3fb_platform_data fb_pdata __initdata = {
-        .dma_dev        = &mx3_ipu.dev,
         .name           = "CRT-VGA",
         .mode           = &fb_modedb,
         .num_modes      = 1,
@@ -202,8 +198,8 @@ static void __init mx31lilly_init_fb(void)
                 return;
         }
 
-        mxc_register_device(&mx3_ipu, &ipu_data);
-        mxc_register_device(&mx3_fb, &fb_pdata);
+        imx31_add_ipu_core(&ipu_data);
+        imx31_add_mx3_sdc_fb(&fb_pdata);
         gpio_direction_output(LCD_VCC_EN_GPIO, 1);
 }
 
@@ -218,4 +214,3 @@ void __init mx31lilly_db_init(void)
         imx31_add_mxc_mmc(0, &mmc_pdata);
         mx31lilly_init_fb();
 }
-
diff --git a/arch/arm/mach-mx3/mx31lite-db.c b/arch/arm/mach-imx/mx31lite-db.c
index 3124ea837ac..5aa053edc17 100644
--- a/arch/arm/mach-mx3/mx31lite-db.c
+++ b/arch/arm/mach-imx/mx31lite-db.c
@@ -37,7 +37,6 @@
 #include <mach/board-mx31lite.h>
 
 #include "devices-imx31.h"
-#include "devices.h"
 
 /*
  * This file contains board-specific initialization routines for the
@@ -200,5 +199,5 @@ void __init mx31lite_db_init(void)
         imx31_add_spi_imx0(&spi0_pdata);
         platform_device_register(&litekit_led_device);
         imx31_add_imx2_wdt(NULL);
-        mxc_register_device(&imx_rtc_device0, NULL);
+        imx31_add_mxc_rtc(NULL);
 }
diff --git a/arch/arm/mach-mx3/mx31moboard-devboard.c b/arch/arm/mach-imx/mx31moboard-devboard.c
index 6410b9c48a0..0aa25364360 100644
--- a/arch/arm/mach-mx3/mx31moboard-devboard.c
+++ b/arch/arm/mach-imx/mx31moboard-devboard.c
@@ -28,7 +28,6 @@
 #include <mach/ulpi.h>
 
 #include "devices-imx31.h"
-#include "devices.h"
 
 static unsigned int devboard_pins[] = {
         /* UART1 */
diff --git a/arch/arm/mach-mx3/mx31moboard-marxbot.c b/arch/arm/mach-imx/mx31moboard-marxbot.c
index 57f7b00cb70..bb639cbda4e 100644
--- a/arch/arm/mach-mx3/mx31moboard-marxbot.c
+++ b/arch/arm/mach-imx/mx31moboard-marxbot.c
@@ -26,14 +26,12 @@
 
 #include <mach/common.h>
 #include <mach/hardware.h>
-#include <mach/imx-uart.h>
 #include <mach/iomux-mx3.h>
 #include <mach/ulpi.h>
 
 #include <media/soc_camera.h>
 
 #include "devices-imx31.h"
-#include "devices.h"
 
 static unsigned int marxbot_pins[] = {
         /* SDHC2 */
diff --git a/arch/arm/mach-mx3/mx31moboard-smartbot.c b/arch/arm/mach-imx/mx31moboard-smartbot.c
index 35f806e737c..fabb801e799 100644
--- a/arch/arm/mach-mx3/mx31moboard-smartbot.c
+++ b/arch/arm/mach-imx/mx31moboard-smartbot.c
@@ -32,7 +32,6 @@
 #include <media/soc_camera.h>
 
 #include "devices-imx31.h"
-#include "devices.h"
 
 static unsigned int smartbot_pins[] = {
         /* UART1 */
diff --git a/arch/arm/mach-mx3/pcm037.h b/arch/arm/mach-imx/pcm037.h
index d6929721a5f..d6929721a5f 100644
--- a/arch/arm/mach-mx3/pcm037.h
+++ b/arch/arm/mach-imx/pcm037.h
diff --git a/arch/arm/mach-iop32x/include/mach/uncompress.h b/arch/arm/mach-iop32x/include/mach/uncompress.h
index b247551b6f5..4fd715496f4 100644
--- a/arch/arm/mach-iop32x/include/mach/uncompress.h
+++ b/arch/arm/mach-iop32x/include/mach/uncompress.h
@@ -7,7 +7,7 @@
 #include <linux/serial_reg.h>
 #include <mach/hardware.h>
 
-static volatile u8 *uart_base;
+volatile u8 *uart_base;
 
 #define TX_DONE         (UART_LSR_TEMT | UART_LSR_THRE)
 
diff --git a/arch/arm/mach-iop33x/include/mach/uncompress.h b/arch/arm/mach-iop33x/include/mach/uncompress.h
index b42423f6330..f99bb848c5a 100644
--- a/arch/arm/mach-iop33x/include/mach/uncompress.h
+++ b/arch/arm/mach-iop33x/include/mach/uncompress.h
@@ -7,7 +7,7 @@
 #include <linux/serial_reg.h>
 #include <mach/hardware.h>
 
-static volatile u32 *uart_base;
+volatile u32 *uart_base;
 
 #define TX_DONE         (UART_LSR_TEMT | UART_LSR_THRE)
 
diff --git a/arch/arm/mach-ixp4xx/include/mach/uncompress.h b/arch/arm/mach-ixp4xx/include/mach/uncompress.h
index 2db0078a8cf..219d7c1dcdb 100644
--- a/arch/arm/mach-ixp4xx/include/mach/uncompress.h
+++ b/arch/arm/mach-ixp4xx/include/mach/uncompress.h
@@ -19,7 +19,7 @@
 
 #define TX_DONE (UART_LSR_TEMT|UART_LSR_THRE)
 
-static volatile u32* uart_base;
+volatile u32* uart_base;
 
 static inline void putc(int c)
 {
diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c
index 20e71df3e3b..f3248cfbe51 100644
--- a/arch/arm/mach-kirkwood/common.c
+++ b/arch/arm/mach-kirkwood/common.c
@@ -13,11 +13,9 @@
 #include <linux/platform_device.h>
 #include <linux/serial_8250.h>
 #include <linux/mbus.h>
-#include <linux/mv643xx_eth.h>
-#include <linux/mv643xx_i2c.h>
 #include <linux/ata_platform.h>
 #include <linux/mtd/nand.h>
-#include <linux/spi/orion_spi.h>
+#include <linux/dma-mapping.h>
 #include <net/dsa.h>
 #include <asm/page.h>
 #include <asm/timex.h>
@@ -28,11 +26,9 @@
 #include <mach/bridge-regs.h>
 #include <plat/audio.h>
 #include <plat/cache-feroceon-l2.h>
-#include <plat/ehci-orion.h>
 #include <plat/mvsdio.h>
-#include <plat/mv_xor.h>
 #include <plat/orion_nand.h>
-#include <plat/orion_wdt.h>
+#include <plat/common.h>
 #include <plat/time.h>
 #include "common.h"
 
@@ -69,210 +65,52 @@ void __init kirkwood_map_io(void)
  * registered.  Some reserved bits must be set to 1.
  */
 unsigned int kirkwood_clk_ctrl = CGC_DUNIT | CGC_RESERVED;
-        
-
-/*****************************************************************************
- * EHCI
- ****************************************************************************/
-static struct orion_ehci_data kirkwood_ehci_data = {
-        .dram           = &kirkwood_mbus_dram_info,
-        .phy_version    = EHCI_PHY_NA,
-};
-
-static u64 ehci_dmamask = 0xffffffffUL;
 
 
 /*****************************************************************************
  * EHCI0
  ****************************************************************************/
-static struct resource kirkwood_ehci_resources[] = {
-        {
-                .start  = USB_PHYS_BASE,
-                .end    = USB_PHYS_BASE + 0x0fff,
-                .flags  = IORESOURCE_MEM,
-        }, {
-                .start  = IRQ_KIRKWOOD_USB,
-                .end    = IRQ_KIRKWOOD_USB,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device kirkwood_ehci = {
-        .name           = "orion-ehci",
-        .id             = 0,
-        .dev            = {
-                .dma_mask               = &ehci_dmamask,
-                .coherent_dma_mask      = 0xffffffff,
-                .platform_data          = &kirkwood_ehci_data,
-        },
-        .resource       = kirkwood_ehci_resources,
-        .num_resources  = ARRAY_SIZE(kirkwood_ehci_resources),
-};
-
 void __init kirkwood_ehci_init(void)
 {
         kirkwood_clk_ctrl |= CGC_USB0;
-        platform_device_register(&kirkwood_ehci);
+        orion_ehci_init(&kirkwood_mbus_dram_info,
+                        USB_PHYS_BASE, IRQ_KIRKWOOD_USB);
 }
 
 
 /*****************************************************************************
  * GE00
  ****************************************************************************/
-struct mv643xx_eth_shared_platform_data kirkwood_ge00_shared_data = {
-        .dram           = &kirkwood_mbus_dram_info,
-};
-
-static struct resource kirkwood_ge00_shared_resources[] = {
-        {
-                .name   = "ge00 base",
-                .start  = GE00_PHYS_BASE + 0x2000,
-                .end    = GE00_PHYS_BASE + 0x3fff,
-                .flags  = IORESOURCE_MEM,
-        }, {
-                .name   = "ge00 err irq",
-                .start  = IRQ_KIRKWOOD_GE00_ERR,
-                .end    = IRQ_KIRKWOOD_GE00_ERR,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device kirkwood_ge00_shared = {
-        .name           = MV643XX_ETH_SHARED_NAME,
-        .id             = 0,
-        .dev            = {
-                .platform_data  = &kirkwood_ge00_shared_data,
-        },
-        .num_resources  = ARRAY_SIZE(kirkwood_ge00_shared_resources),
-        .resource       = kirkwood_ge00_shared_resources,
-};
-
-static struct resource kirkwood_ge00_resources[] = {
-        {
-                .name   = "ge00 irq",
-                .start  = IRQ_KIRKWOOD_GE00_SUM,
-                .end    = IRQ_KIRKWOOD_GE00_SUM,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device kirkwood_ge00 = {
-        .name           = MV643XX_ETH_NAME,
-        .id             = 0,
-        .num_resources  = 1,
-        .resource       = kirkwood_ge00_resources,
-        .dev            = {
-                .coherent_dma_mask      = 0xffffffff,
-        },
-};
-
 void __init kirkwood_ge00_init(struct mv643xx_eth_platform_data *eth_data)
 {
         kirkwood_clk_ctrl |= CGC_GE0;
-        eth_data->shared = &kirkwood_ge00_shared;
-        kirkwood_ge00.dev.platform_data = eth_data;
 
-        platform_device_register(&kirkwood_ge00_shared);
-        platform_device_register(&kirkwood_ge00);
+        orion_ge00_init(eth_data, &kirkwood_mbus_dram_info,
+                        GE00_PHYS_BASE, IRQ_KIRKWOOD_GE00_SUM,
+                        IRQ_KIRKWOOD_GE00_ERR, kirkwood_tclk);
 }
 
 
 /*****************************************************************************
  * GE01
  ****************************************************************************/
-struct mv643xx_eth_shared_platform_data kirkwood_ge01_shared_data = {
-        .dram           = &kirkwood_mbus_dram_info,
-        .shared_smi     = &kirkwood_ge00_shared,
-};
-
-static struct resource kirkwood_ge01_shared_resources[] = {
-        {
-                .name   = "ge01 base",
-                .start  = GE01_PHYS_BASE + 0x2000,
-                .end    = GE01_PHYS_BASE + 0x3fff,
-                .flags  = IORESOURCE_MEM,
-        }, {
-                .name   = "ge01 err irq",
-                .start  = IRQ_KIRKWOOD_GE01_ERR,
-                .end    = IRQ_KIRKWOOD_GE01_ERR,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device kirkwood_ge01_shared = {
-        .name           = MV643XX_ETH_SHARED_NAME,
-        .id             = 1,
-        .dev            = {
-                .platform_data  = &kirkwood_ge01_shared_data,
-        },
-        .num_resources  = ARRAY_SIZE(kirkwood_ge01_shared_resources),
-        .resource       = kirkwood_ge01_shared_resources,
-};
-
-static struct resource kirkwood_ge01_resources[] = {
-        {
-                .name   = "ge01 irq",
-                .start  = IRQ_KIRKWOOD_GE01_SUM,
-                .end    = IRQ_KIRKWOOD_GE01_SUM,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device kirkwood_ge01 = {
-        .name           = MV643XX_ETH_NAME,
-        .id             = 1,
-        .num_resources  = 1,
-        .resource       = kirkwood_ge01_resources,
-        .dev            = {
-                .coherent_dma_mask      = 0xffffffff,
-        },
-};
-
 void __init kirkwood_ge01_init(struct mv643xx_eth_platform_data *eth_data)
 {
+
         kirkwood_clk_ctrl |= CGC_GE1;
-        eth_data->shared = &kirkwood_ge01_shared;
-        kirkwood_ge01.dev.platform_data = eth_data;
 
-        platform_device_register(&kirkwood_ge01_shared);
-        platform_device_register(&kirkwood_ge01);
+        orion_ge01_init(eth_data, &kirkwood_mbus_dram_info,
+                        GE01_PHYS_BASE, IRQ_KIRKWOOD_GE01_SUM,
+                        IRQ_KIRKWOOD_GE01_ERR, kirkwood_tclk);
 }
 
 
 /*****************************************************************************
  * Ethernet switch
  ****************************************************************************/
-static struct resource kirkwood_switch_resources[] = {
-        {
-                .start  = 0,
-                .end    = 0,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device kirkwood_switch_device = {
-        .name           = "dsa",
-        .id             = 0,
-        .num_resources  = 0,
-        .resource       = kirkwood_switch_resources,
-};
-
 void __init kirkwood_ge00_switch_init(struct dsa_platform_data *d, int irq)
 {
-        int i;
-
-        if (irq != NO_IRQ) {
-                kirkwood_switch_resources[0].start = irq;
-                kirkwood_switch_resources[0].end = irq;
-                kirkwood_switch_device.num_resources = 1;
-        }
-
-        d->netdev = &kirkwood_ge00.dev;
-        for (i = 0; i < d->nr_chips; i++)
-                d->chip[i].mii_bus = &kirkwood_ge00_shared.dev;
-        kirkwood_switch_device.dev.platform_data = d;
-
-        platform_device_register(&kirkwood_switch_device);
+        orion_ge00_switch_init(d, irq);
 }
 
 
@@ -325,53 +163,23 @@ void __init kirkwood_nand_init_rnb(struct mtd_partition *parts, int nr_parts,
 /*****************************************************************************
  * SoC RTC
  ****************************************************************************/
-static struct resource kirkwood_rtc_resource = {
-        .start  = RTC_PHYS_BASE,
-        .end    = RTC_PHYS_BASE + SZ_16 - 1,
-        .flags  = IORESOURCE_MEM,
-};
-
 static void __init kirkwood_rtc_init(void)
 {
-        platform_device_register_simple("rtc-mv", -1, &kirkwood_rtc_resource, 1);
+        orion_rtc_init(RTC_PHYS_BASE, IRQ_KIRKWOOD_RTC);
 }
 
 
 /*****************************************************************************
  * SATA
  ****************************************************************************/
-static struct resource kirkwood_sata_resources[] = {
-        {
-                .name   = "sata base",
-                .start  = SATA_PHYS_BASE,
-                .end    = SATA_PHYS_BASE + 0x5000 - 1,
-                .flags  = IORESOURCE_MEM,
-        }, {
-                .name   = "sata irq",
-                .start  = IRQ_KIRKWOOD_SATA,
-                .end    = IRQ_KIRKWOOD_SATA,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device kirkwood_sata = {
-        .name           = "sata_mv",
-        .id             = 0,
-        .dev            = {
-                .coherent_dma_mask      = 0xffffffff,
-        },
-        .num_resources  = ARRAY_SIZE(kirkwood_sata_resources),
-        .resource       = kirkwood_sata_resources,
-};
-
 void __init kirkwood_sata_init(struct mv_sata_platform_data *sata_data)
 {
         kirkwood_clk_ctrl |= CGC_SATA0;
         if (sata_data->n_ports > 1)
                 kirkwood_clk_ctrl |= CGC_SATA1;
-        sata_data->dram = &kirkwood_mbus_dram_info;
-        kirkwood_sata.dev.platform_data = sata_data;
-        platform_device_register(&kirkwood_sata);
+
+        orion_sata_init(sata_data, &kirkwood_mbus_dram_info,
+                        SATA_PHYS_BASE, IRQ_KIRKWOOD_SATA);
 }
 
 
@@ -391,14 +199,14 @@ static struct resource mvsdio_resources[] = {
         },
 };
 
-static u64 mvsdio_dmamask = 0xffffffffUL;
+static u64 mvsdio_dmamask = DMA_BIT_MASK(32);
 
 static struct platform_device kirkwood_sdio = {
         .name           = "mvsdio",
         .id             = -1,
         .dev            = {
                 .dma_mask = &mvsdio_dmamask,
-                .coherent_dma_mask = 0xffffffff,
+                .coherent_dma_mask = DMA_BIT_MASK(32),
         },
         .num_resources  = ARRAY_SIZE(mvsdio_resources),
         .resource       = mvsdio_resources,
@@ -423,424 +231,84 @@ void __init kirkwood_sdio_init(struct mvsdio_platform_data *mvsdio_data)
 /*****************************************************************************
  * SPI
  ****************************************************************************/
-static struct orion_spi_info kirkwood_spi_plat_data = {
-};
-
-static struct resource kirkwood_spi_resources[] = {
-        {
-                .start  = SPI_PHYS_BASE,
-                .end    = SPI_PHYS_BASE + SZ_512 - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-};
-
-static struct platform_device kirkwood_spi = {
-        .name           = "orion_spi",
-        .id             = 0,
-        .resource       = kirkwood_spi_resources,
-        .dev            = {
-                .platform_data  = &kirkwood_spi_plat_data,
-        },
-        .num_resources  = ARRAY_SIZE(kirkwood_spi_resources),
-};
-
 void __init kirkwood_spi_init()
 {
         kirkwood_clk_ctrl |= CGC_RUNIT;
-        platform_device_register(&kirkwood_spi);
+        orion_spi_init(SPI_PHYS_BASE, kirkwood_tclk);
 }
 
 
 /*****************************************************************************
  * I2C
  ****************************************************************************/
-static struct mv64xxx_i2c_pdata kirkwood_i2c_pdata = {
-        .freq_m         = 8, /* assumes 166 MHz TCLK */
-        .freq_n         = 3,
-        .timeout        = 1000, /* Default timeout of 1 second */
-};
-
-static struct resource kirkwood_i2c_resources[] = {
-        {
-                .start  = I2C_PHYS_BASE,
-                .end    = I2C_PHYS_BASE + 0x1f,
-                .flags  = IORESOURCE_MEM,
-        }, {
-                .start  = IRQ_KIRKWOOD_TWSI,
-                .end    = IRQ_KIRKWOOD_TWSI,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device kirkwood_i2c = {
-        .name           = MV64XXX_I2C_CTLR_NAME,
-        .id             = 0,
-        .num_resources  = ARRAY_SIZE(kirkwood_i2c_resources),
-        .resource       = kirkwood_i2c_resources,
-        .dev            = {
-                .platform_data  = &kirkwood_i2c_pdata,
-        },
-};
-
 void __init kirkwood_i2c_init(void)
 {
-        platform_device_register(&kirkwood_i2c);
+        orion_i2c_init(I2C_PHYS_BASE, IRQ_KIRKWOOD_TWSI, 8);
 }
 
 
 /*****************************************************************************
  * UART0
  ****************************************************************************/
-static struct plat_serial8250_port kirkwood_uart0_data[] = {
-        {
-                .mapbase        = UART0_PHYS_BASE,
-                .membase        = (char *)UART0_VIRT_BASE,
-                .irq            = IRQ_KIRKWOOD_UART_0,
-                .flags          = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
-                .iotype         = UPIO_MEM,
-                .regshift       = 2,
-                .uartclk        = 0,
-        }, {
-        },
-};
-
-static struct resource kirkwood_uart0_resources[] = {
-        {
-                .start          = UART0_PHYS_BASE,
-                .end            = UART0_PHYS_BASE + 0xff,
-                .flags          = IORESOURCE_MEM,
-        }, {
-                .start          = IRQ_KIRKWOOD_UART_0,
-                .end            = IRQ_KIRKWOOD_UART_0,
-                .flags          = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device kirkwood_uart0 = {
-        .name                   = "serial8250",
-        .id                     = 0,
-        .dev                    = {
-                .platform_data  = kirkwood_uart0_data,
-        },
-        .resource               = kirkwood_uart0_resources,
-        .num_resources          = ARRAY_SIZE(kirkwood_uart0_resources),
-};
 
 void __init kirkwood_uart0_init(void)
 {
-        platform_device_register(&kirkwood_uart0);
+        orion_uart0_init(UART0_VIRT_BASE, UART0_PHYS_BASE,
+                         IRQ_KIRKWOOD_UART_0, kirkwood_tclk);
 }
 
 
 /*****************************************************************************
  * UART1
  ****************************************************************************/
-static struct plat_serial8250_port kirkwood_uart1_data[] = {
-        {
-                .mapbase        = UART1_PHYS_BASE,
-                .membase        = (char *)UART1_VIRT_BASE,
-                .irq            = IRQ_KIRKWOOD_UART_1,
-                .flags          = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
-                .iotype         = UPIO_MEM,
-                .regshift       = 2,
-                .uartclk        = 0,
-        }, {
-        },
-};
-
-static struct resource kirkwood_uart1_resources[] = {
-        {
-                .start          = UART1_PHYS_BASE,
-                .end            = UART1_PHYS_BASE + 0xff,
-                .flags          = IORESOURCE_MEM,
-        }, {
-                .start          = IRQ_KIRKWOOD_UART_1,
-                .end            = IRQ_KIRKWOOD_UART_1,
-                .flags          = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device kirkwood_uart1 = {
-        .name                   = "serial8250",
-        .id                     = 1,
-        .dev                    = {
-                .platform_data  = kirkwood_uart1_data,
-        },
-        .resource               = kirkwood_uart1_resources,
-        .num_resources          = ARRAY_SIZE(kirkwood_uart1_resources),
-};
-
 void __init kirkwood_uart1_init(void)
 {
-        platform_device_register(&kirkwood_uart1);
+        orion_uart1_init(UART1_VIRT_BASE, UART1_PHYS_BASE,
+                         IRQ_KIRKWOOD_UART_1, kirkwood_tclk);
 }
 
-
 /*****************************************************************************
  * Cryptographic Engines and Security Accelerator (CESA)
  ****************************************************************************/
-
-static struct resource kirkwood_crypto_res[] = {
-        {
-                .name   = "regs",
-                .start  = CRYPTO_PHYS_BASE,
-                .end    = CRYPTO_PHYS_BASE + 0xffff,
-                .flags  = IORESOURCE_MEM,
-        }, {
-                .name   = "sram",
-                .start  = KIRKWOOD_SRAM_PHYS_BASE,
-                .end    = KIRKWOOD_SRAM_PHYS_BASE + KIRKWOOD_SRAM_SIZE - 1,
-                .flags  = IORESOURCE_MEM,
-        }, {
-                .name   = "crypto interrupt",
-                .start  = IRQ_KIRKWOOD_CRYPTO,
-                .end    = IRQ_KIRKWOOD_CRYPTO,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device kirkwood_crypto_device = {
-        .name           = "mv_crypto",
-        .id             = -1,
-        .num_resources  = ARRAY_SIZE(kirkwood_crypto_res),
-        .resource       = kirkwood_crypto_res,
-};
-
 void __init kirkwood_crypto_init(void)
 {
         kirkwood_clk_ctrl |= CGC_CRYPTO;
-        platform_device_register(&kirkwood_crypto_device);
+        orion_crypto_init(CRYPTO_PHYS_BASE, KIRKWOOD_SRAM_PHYS_BASE,
+                          KIRKWOOD_SRAM_SIZE, IRQ_KIRKWOOD_CRYPTO);
 }
 
 
 /*****************************************************************************
- * XOR
- ****************************************************************************/
-static struct mv_xor_platform_shared_data kirkwood_xor_shared_data = {
-        .dram           = &kirkwood_mbus_dram_info,
-};
-
-static u64 kirkwood_xor_dmamask = DMA_BIT_MASK(32);
-
-
-/*****************************************************************************
  * XOR0
  ****************************************************************************/
-static struct resource kirkwood_xor0_shared_resources[] = {
-        {
-                .name   = "xor 0 low",
-                .start  = XOR0_PHYS_BASE,
-                .end    = XOR0_PHYS_BASE + 0xff,
-                .flags  = IORESOURCE_MEM,
-        }, {
-                .name   = "xor 0 high",
-                .start  = XOR0_HIGH_PHYS_BASE,
-                .end    = XOR0_HIGH_PHYS_BASE + 0xff,
-                .flags  = IORESOURCE_MEM,
-        },
-};
-
-static struct platform_device kirkwood_xor0_shared = {
-        .name           = MV_XOR_SHARED_NAME,
-        .id             = 0,
-        .dev            = {
-                .platform_data = &kirkwood_xor_shared_data,
-        },
-        .num_resources  = ARRAY_SIZE(kirkwood_xor0_shared_resources),
-        .resource       = kirkwood_xor0_shared_resources,
-};
-
-static struct resource kirkwood_xor00_resources[] = {
-        [0] = {
-                .start  = IRQ_KIRKWOOD_XOR_00,
-                .end    = IRQ_KIRKWOOD_XOR_00,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct mv_xor_platform_data kirkwood_xor00_data = {
-        .shared         = &kirkwood_xor0_shared,
-        .hw_id          = 0,
-        .pool_size      = PAGE_SIZE,
-};
-
-static struct platform_device kirkwood_xor00_channel = {
-        .name           = MV_XOR_NAME,
-        .id             = 0,
-        .num_resources  = ARRAY_SIZE(kirkwood_xor00_resources),
-        .resource       = kirkwood_xor00_resources,
-        .dev            = {
-                .dma_mask               = &kirkwood_xor_dmamask,
-                .coherent_dma_mask      = DMA_BIT_MASK(64),
-                .platform_data          = &kirkwood_xor00_data,
-        },
-};
-
-static struct resource kirkwood_xor01_resources[] = {
-        [0] = {
-                .start  = IRQ_KIRKWOOD_XOR_01,
-                .end    = IRQ_KIRKWOOD_XOR_01,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct mv_xor_platform_data kirkwood_xor01_data = {
-        .shared         = &kirkwood_xor0_shared,
-        .hw_id          = 1,
-        .pool_size      = PAGE_SIZE,
-};
-
-static struct platform_device kirkwood_xor01_channel = {
-        .name           = MV_XOR_NAME,
-        .id             = 1,
-        .num_resources  = ARRAY_SIZE(kirkwood_xor01_resources),
-        .resource       = kirkwood_xor01_resources,
-        .dev            = {
-                .dma_mask               = &kirkwood_xor_dmamask,
-                .coherent_dma_mask      = DMA_BIT_MASK(64),
-                .platform_data          = &kirkwood_xor01_data,
-        },
-};
-
 static void __init kirkwood_xor0_init(void)
 {
         kirkwood_clk_ctrl |= CGC_XOR0;
-        platform_device_register(&kirkwood_xor0_shared);
 
-        /*
-         * two engines can't do memset simultaneously, this limitation
-         * satisfied by removing memset support from one of the engines.
-         */
-        dma_cap_set(DMA_MEMCPY, kirkwood_xor00_data.cap_mask);
-        dma_cap_set(DMA_XOR, kirkwood_xor00_data.cap_mask);
-        platform_device_register(&kirkwood_xor00_channel);
-
-        dma_cap_set(DMA_MEMCPY, kirkwood_xor01_data.cap_mask);
-        dma_cap_set(DMA_MEMSET, kirkwood_xor01_data.cap_mask);
-        dma_cap_set(DMA_XOR, kirkwood_xor01_data.cap_mask);
-        platform_device_register(&kirkwood_xor01_channel);
+        orion_xor0_init(&kirkwood_mbus_dram_info,
+                        XOR0_PHYS_BASE, XOR0_HIGH_PHYS_BASE,
+                        IRQ_KIRKWOOD_XOR_00, IRQ_KIRKWOOD_XOR_01);
 }
 
 
 /*****************************************************************************
  * XOR1
  ****************************************************************************/
-static struct resource kirkwood_xor1_shared_resources[] = {
-        {
-                .name   = "xor 1 low",
-                .start  = XOR1_PHYS_BASE,
-                .end    = XOR1_PHYS_BASE + 0xff,
-                .flags  = IORESOURCE_MEM,
-        }, {
-                .name   = "xor 1 high",
-                .start  = XOR1_HIGH_PHYS_BASE,
-                .end    = XOR1_HIGH_PHYS_BASE + 0xff,
-                .flags  = IORESOURCE_MEM,
-        },
-};
-
-static struct platform_device kirkwood_xor1_shared = {
-        .name           = MV_XOR_SHARED_NAME,
-        .id             = 1,
-        .dev            = {
-                .platform_data = &kirkwood_xor_shared_data,
-        },
-        .num_resources  = ARRAY_SIZE(kirkwood_xor1_shared_resources),
-        .resource       = kirkwood_xor1_shared_resources,
-};
-
-static struct resource kirkwood_xor10_resources[] = {
-        [0] = {
-                .start  = IRQ_KIRKWOOD_XOR_10,
-                .end    = IRQ_KIRKWOOD_XOR_10,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct mv_xor_platform_data kirkwood_xor10_data = {
-        .shared         = &kirkwood_xor1_shared,
-        .hw_id          = 0,
-        .pool_size      = PAGE_SIZE,
-};
-
-static struct platform_device kirkwood_xor10_channel = {
-        .name           = MV_XOR_NAME,
-        .id             = 2,
-        .num_resources  = ARRAY_SIZE(kirkwood_xor10_resources),
-        .resource       = kirkwood_xor10_resources,
-        .dev            = {
-                .dma_mask               = &kirkwood_xor_dmamask,
-                .coherent_dma_mask      = DMA_BIT_MASK(64),
-                .platform_data          = &kirkwood_xor10_data,
-        },
-};
-
-static struct resource kirkwood_xor11_resources[] = {
-        [0] = {
-                .start  = IRQ_KIRKWOOD_XOR_11,
-                .end    = IRQ_KIRKWOOD_XOR_11,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct mv_xor_platform_data kirkwood_xor11_data = {
-        .shared         = &kirkwood_xor1_shared,
-        .hw_id          = 1,
-        .pool_size      = PAGE_SIZE,
-};
-
-static struct platform_device kirkwood_xor11_channel = {
-        .name           = MV_XOR_NAME,
-        .id             = 3,
-        .num_resources  = ARRAY_SIZE(kirkwood_xor11_resources),
-        .resource       = kirkwood_xor11_resources,
-        .dev            = {
-                .dma_mask               = &kirkwood_xor_dmamask,
-                .coherent_dma_mask      = DMA_BIT_MASK(64),
-                .platform_data          = &kirkwood_xor11_data,
-        },
-};
-
 static void __init kirkwood_xor1_init(void)
 {
         kirkwood_clk_ctrl |= CGC_XOR1;
-        platform_device_register(&kirkwood_xor1_shared);
 
-        /*
-         * two engines can't do memset simultaneously, this limitation
-         * satisfied by removing memset support from one of the engines.
-         */
-        dma_cap_set(DMA_MEMCPY, kirkwood_xor10_data.cap_mask);
-        dma_cap_set(DMA_XOR, kirkwood_xor10_data.cap_mask);
-        platform_device_register(&kirkwood_xor10_channel);
-
-        dma_cap_set(DMA_MEMCPY, kirkwood_xor11_data.cap_mask);
-        dma_cap_set(DMA_MEMSET, kirkwood_xor11_data.cap_mask);
-        dma_cap_set(DMA_XOR, kirkwood_xor11_data.cap_mask);
-        platform_device_register(&kirkwood_xor11_channel);
+        orion_xor1_init(XOR1_PHYS_BASE, XOR1_HIGH_PHYS_BASE,
+                        IRQ_KIRKWOOD_XOR_10, IRQ_KIRKWOOD_XOR_11);
 }
 
 
 /*****************************************************************************
  * Watchdog
  ****************************************************************************/
-static struct orion_wdt_platform_data kirkwood_wdt_data = {
-        .tclk           = 0,
-};
-
-static struct platform_device kirkwood_wdt_device = {
-        .name           = "orion_wdt",
-        .id             = -1,
-        .dev            = {
-                .platform_data  = &kirkwood_wdt_data,
-        },
-        .num_resources  = 0,
-};
-
 static void __init kirkwood_wdt_init(void)
 {
-        kirkwood_wdt_data.tclk = kirkwood_tclk;
-        platform_device_register(&kirkwood_wdt_device);
+        orion_wdt_init(kirkwood_tclk);
 }
 
 
@@ -984,11 +452,6 @@ void __init kirkwood_init(void)
 {
         printk(KERN_INFO "Kirkwood: %s, TCLK=%d.\n",
                 kirkwood_id(), kirkwood_tclk);
-        kirkwood_ge00_shared_data.t_clk = kirkwood_tclk;
-        kirkwood_ge01_shared_data.t_clk = kirkwood_tclk;
-        kirkwood_spi_plat_data.tclk = kirkwood_tclk;
-        kirkwood_uart0_data[0].uartclk = kirkwood_tclk;
-        kirkwood_uart1_data[0].uartclk = kirkwood_tclk;
         kirkwood_i2s_data.tclk = kirkwood_tclk;
 
         /*
diff --git a/arch/arm/mach-kirkwood/include/mach/irqs.h b/arch/arm/mach-kirkwood/include/mach/irqs.h
index 9da2eb59180..2bf8161e3b5 100644
--- a/arch/arm/mach-kirkwood/include/mach/irqs.h
+++ b/arch/arm/mach-kirkwood/include/mach/irqs.h
@@ -51,6 +51,7 @@
 #define IRQ_KIRKWOOD_GPIO_HIGH_16_23    41
 #define IRQ_KIRKWOOD_GE00_ERR   46
 #define IRQ_KIRKWOOD_GE01_ERR   47
+#define IRQ_KIRKWOOD_RTC        53
 
 /*
  * KIRKWOOD General Purpose Pins
diff --git a/arch/arm/mach-kirkwood/mpp.c b/arch/arm/mach-kirkwood/mpp.c
index 7ce20184806..b0a7d979a8e 100644
--- a/arch/arm/mach-kirkwood/mpp.c
+++ b/arch/arm/mach-kirkwood/mpp.c
@@ -14,6 +14,7 @@
 #include <linux/io.h>
 #include <asm/gpio.h>
 #include <mach/hardware.h>
+#include <plat/mpp.h>
 #include "common.h"
 #include "mpp.h"
 
@@ -36,61 +37,8 @@ static unsigned int __init kirkwood_variant(void)
         return 0;
 }
 
-#define MPP_CTRL(i)     (DEV_BUS_VIRT_BASE + (i) * 4)
-#define MPP_NR_REGS     (1 + MPP_MAX/8)
-
 void __init kirkwood_mpp_conf(unsigned int *mpp_list)
 {
-        u32 mpp_ctrl[MPP_NR_REGS];
-        unsigned int variant_mask;
-        int i;
-
-        variant_mask = kirkwood_variant();
-        if (!variant_mask)
-                return;
-
-        printk(KERN_DEBUG "initial MPP regs:");
-        for (i = 0; i < MPP_NR_REGS; i++) {
-                mpp_ctrl[i] = readl(MPP_CTRL(i));
-                printk(" %08x", mpp_ctrl[i]);
-        }
-        printk("\n");
-
-        for ( ; *mpp_list; mpp_list++) {
-                unsigned int num = MPP_NUM(*mpp_list);
-                unsigned int sel = MPP_SEL(*mpp_list);
-                int shift, gpio_mode;
-
-                if (num > MPP_MAX) {
-                        printk(KERN_ERR "kirkwood_mpp_conf: invalid MPP "
-                                        "number (%u)\n", num);
-                        continue;
-                }
-                if (!(*mpp_list & variant_mask)) {
-                        printk(KERN_WARNING
-                               "kirkwood_mpp_conf: requested MPP%u config "
-                               "unavailable on this hardware\n", num);
-                        continue;
-                }
-
-                shift = (num & 7) << 2;
-                mpp_ctrl[num / 8] &= ~(0xf << shift);
-                mpp_ctrl[num / 8] |= sel << shift;
-
-                gpio_mode = 0;
-                if (*mpp_list & MPP_INPUT_MASK)
-                        gpio_mode |= GPIO_INPUT_OK;
-                if (*mpp_list & MPP_OUTPUT_MASK)
-                        gpio_mode |= GPIO_OUTPUT_OK;
-                if (sel != 0)
-                        gpio_mode = 0;
-                orion_gpio_set_valid(num, gpio_mode);
-        }
-
-        printk(KERN_DEBUG "  final MPP regs:");
-        for (i = 0; i < MPP_NR_REGS; i++) {
-                writel(mpp_ctrl[i], MPP_CTRL(i));
-                printk(" %08x", mpp_ctrl[i]);
-        }
-        printk("\n");
+        orion_mpp_conf(mpp_list, kirkwood_variant(),
+                       MPP_MAX, DEV_BUS_VIRT_BASE);
 }
diff --git a/arch/arm/mach-kirkwood/mpp.h b/arch/arm/mach-kirkwood/mpp.h
index 9b0a94d85c3..ac787957e2d 100644
--- a/arch/arm/mach-kirkwood/mpp.h
+++ b/arch/arm/mach-kirkwood/mpp.h
@@ -22,14 +22,8 @@
         /* available on F6281 */        ((!!(_F6281)) << 17) | \
         /* available on F6282 */        ((!!(_F6282)) << 18))
 
-#define MPP_NUM(x)      ((x) & 0xff)
-#define MPP_SEL(x)      (((x) >> 8) & 0xf)
-
                                 /*   num sel  i  o  6180 6190 6192 6281 6282 */
 
-#define MPP_INPUT_MASK          MPP(  0, 0x0, 1, 0, 0,   0,   0,   0,   0 )
-#define MPP_OUTPUT_MASK         MPP(  0, 0x0, 0, 1, 0,   0,   0,   0,   0 )
-
 #define MPP_F6180_MASK          MPP(  0, 0x0, 0, 0, 1,   0,   0,   0,   0 )
 #define MPP_F6190_MASK          MPP(  0, 0x0, 0, 0, 0,   1,   0,   0,   0 )
 #define MPP_F6192_MASK          MPP(  0, 0x0, 0, 0, 0,   0,   1,   0,   0 )
diff --git a/arch/arm/mach-loki/common.c b/arch/arm/mach-loki/common.c
index e41e909cf8f..5f02664db81 100644
--- a/arch/arm/mach-loki/common.c
+++ b/arch/arm/mach-loki/common.c
@@ -13,7 +13,7 @@
 #include <linux/platform_device.h>
 #include <linux/serial_8250.h>
 #include <linux/mbus.h>
-#include <linux/mv643xx_eth.h>
+#include <linux/dma-mapping.h>
 #include <asm/page.h>
 #include <asm/timex.h>
 #include <asm/mach/map.h>
@@ -22,6 +22,7 @@
 #include <mach/loki.h>
 #include <plat/orion_nand.h>
 #include <plat/time.h>
+#include <plat/common.h>
 #include "common.h"
 
 /*****************************************************************************
@@ -43,116 +44,28 @@ void __init loki_map_io(void)
 
 
 /*****************************************************************************
- * GE0
+ * GE00
  ****************************************************************************/
-struct mv643xx_eth_shared_platform_data loki_ge0_shared_data = {
-        .t_clk          = LOKI_TCLK,
-        .dram           = &loki_mbus_dram_info,
-};
-
-static struct resource loki_ge0_shared_resources[] = {
-        {
-                .name   = "ge0 base",
-                .start  = GE0_PHYS_BASE + 0x2000,
-                .end    = GE0_PHYS_BASE + 0x3fff,
-                .flags  = IORESOURCE_MEM,
-        },
-};
-
-static struct platform_device loki_ge0_shared = {
-        .name           = MV643XX_ETH_SHARED_NAME,
-        .id             = 0,
-        .dev            = {
-                .platform_data  = &loki_ge0_shared_data,
-        },
-        .num_resources  = 1,
-        .resource       = loki_ge0_shared_resources,
-};
-
-static struct resource loki_ge0_resources[] = {
-        {
-                .name   = "ge0 irq",
-                .start  = IRQ_LOKI_GBE_A_INT,
-                .end    = IRQ_LOKI_GBE_A_INT,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device loki_ge0 = {
-        .name           = MV643XX_ETH_NAME,
-        .id             = 0,
-        .num_resources  = 1,
-        .resource       = loki_ge0_resources,
-        .dev            = {
-                .coherent_dma_mask      = 0xffffffff,
-        },
-};
-
 void __init loki_ge0_init(struct mv643xx_eth_platform_data *eth_data)
 {
-        eth_data->shared = &loki_ge0_shared;
-        loki_ge0.dev.platform_data = eth_data;
-
         writel(0x00079220, GE0_VIRT_BASE + 0x20b0);
-        platform_device_register(&loki_ge0_shared);
-        platform_device_register(&loki_ge0);
+
+        orion_ge00_init(eth_data, &loki_mbus_dram_info,
+                        GE0_PHYS_BASE, IRQ_LOKI_GBE_A_INT,
+                        0, LOKI_TCLK);
 }
 
 
 /*****************************************************************************
- * GE1
+ * GE01
  ****************************************************************************/
-struct mv643xx_eth_shared_platform_data loki_ge1_shared_data = {
-        .t_clk          = LOKI_TCLK,
-        .dram           = &loki_mbus_dram_info,
-};
-
-static struct resource loki_ge1_shared_resources[] = {
-        {
-                .name   = "ge1 base",
-                .start  = GE1_PHYS_BASE + 0x2000,
-                .end    = GE1_PHYS_BASE + 0x3fff,
-                .flags  = IORESOURCE_MEM,
-        },
-};
-
-static struct platform_device loki_ge1_shared = {
-        .name           = MV643XX_ETH_SHARED_NAME,
-        .id             = 1,
-        .dev            = {
-                .platform_data  = &loki_ge1_shared_data,
-        },
-        .num_resources  = 1,
-        .resource       = loki_ge1_shared_resources,
-};
-
-static struct resource loki_ge1_resources[] = {
-        {
-                .name   = "ge1 irq",
-                .start  = IRQ_LOKI_GBE_B_INT,
-                .end    = IRQ_LOKI_GBE_B_INT,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device loki_ge1 = {
-        .name           = MV643XX_ETH_NAME,
-        .id             = 1,
-        .num_resources  = 1,
-        .resource       = loki_ge1_resources,
-        .dev            = {
-                .coherent_dma_mask      = 0xffffffff,
-        },
-};
-
 void __init loki_ge1_init(struct mv643xx_eth_platform_data *eth_data)
 {
-        eth_data->shared = &loki_ge1_shared;
-        loki_ge1.dev.platform_data = eth_data;
-
         writel(0x00079220, GE1_VIRT_BASE + 0x20b0);
-        platform_device_register(&loki_ge1_shared);
-        platform_device_register(&loki_ge1);
+
+        orion_ge01_init(eth_data, &loki_mbus_dram_info,
+                        GE1_PHYS_BASE, IRQ_LOKI_GBE_B_INT,
+                        0, LOKI_TCLK);
 }
 
 
@@ -187,7 +100,7 @@ static struct platform_device loki_sas = {
         .name           = "mvsas",
         .id             = 0,
         .dev            = {
-                .coherent_dma_mask      = 0xffffffff,
+                .coherent_dma_mask      = DMA_BIT_MASK(32),
         },
         .num_resources  = ARRAY_SIZE(loki_sas_resources),
         .resource       = loki_sas_resources,
@@ -203,88 +116,19 @@ void __init loki_sas_init(void)
 /*****************************************************************************
  * UART0
  ****************************************************************************/
-static struct plat_serial8250_port loki_uart0_data[] = {
-        {
-                .mapbase        = UART0_PHYS_BASE,
-                .membase        = (char *)UART0_VIRT_BASE,
-                .irq            = IRQ_LOKI_UART0,
-                .flags          = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
-                .iotype         = UPIO_MEM,
-                .regshift       = 2,
-                .uartclk        = LOKI_TCLK,
-        }, {
-        },
-};
-
-static struct resource loki_uart0_resources[] = {
-        {
-                .start          = UART0_PHYS_BASE,
-                .end            = UART0_PHYS_BASE + 0xff,
-                .flags          = IORESOURCE_MEM,
-        }, {
-                .start          = IRQ_LOKI_UART0,
-                .end            = IRQ_LOKI_UART0,
-                .flags          = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device loki_uart0 = {
-        .name                   = "serial8250",
-        .id                     = 0,
-        .dev                    = {
-                .platform_data  = loki_uart0_data,
-        },
-        .resource               = loki_uart0_resources,
-        .num_resources          = ARRAY_SIZE(loki_uart0_resources),
-};
-
 void __init loki_uart0_init(void)
 {
-        platform_device_register(&loki_uart0);
+        orion_uart0_init(UART0_VIRT_BASE, UART0_PHYS_BASE,
+                         IRQ_LOKI_UART0, LOKI_TCLK);
 }
 
-
 /*****************************************************************************
  * UART1
  ****************************************************************************/
-static struct plat_serial8250_port loki_uart1_data[] = {
-        {
-                .mapbase        = UART1_PHYS_BASE,
-                .membase        = (char *)UART1_VIRT_BASE,
-                .irq            = IRQ_LOKI_UART1,
-                .flags          = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
-                .iotype         = UPIO_MEM,
-                .regshift       = 2,
-                .uartclk        = LOKI_TCLK,
-        }, {
-        },
-};
-
-static struct resource loki_uart1_resources[] = {
-        {
-                .start          = UART1_PHYS_BASE,
-                .end            = UART1_PHYS_BASE + 0xff,
-                .flags          = IORESOURCE_MEM,
-        }, {
-                .start          = IRQ_LOKI_UART1,
-                .end            = IRQ_LOKI_UART1,
-                .flags          = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device loki_uart1 = {
-        .name                   = "serial8250",
-        .id                     = 1,
-        .dev                    = {
-                .platform_data  = loki_uart1_data,
-        },
-        .resource               = loki_uart1_resources,
-        .num_resources          = ARRAY_SIZE(loki_uart1_resources),
-};
-
 void __init loki_uart1_init(void)
 {
-        platform_device_register(&loki_uart1);
+        orion_uart1_init(UART1_VIRT_BASE, UART1_PHYS_BASE,
+                         IRQ_LOKI_UART1, LOKI_TCLK);
 }
 
 
diff --git a/arch/arm/mach-mmp/include/mach/uncompress.h b/arch/arm/mach-mmp/include/mach/uncompress.h
index 85bd8a2d84b..d6daeb7e4ef 100644
--- a/arch/arm/mach-mmp/include/mach/uncompress.h
+++ b/arch/arm/mach-mmp/include/mach/uncompress.h
@@ -14,7 +14,7 @@
 #define UART2_BASE      (APB_PHYS_BASE + 0x17000)
 #define UART3_BASE      (APB_PHYS_BASE + 0x18000)
 
-static volatile unsigned long *UART;
+volatile unsigned long *UART;
 
 static inline void putc(char c)
 {
diff --git a/arch/arm/mach-msm/gpio-v2.c b/arch/arm/mach-msm/gpio-v2.c
index 56a964e52ad..cc9c4fd7ccc 100644
--- a/arch/arm/mach-msm/gpio-v2.c
+++ b/arch/arm/mach-msm/gpio-v2.c
@@ -27,6 +27,9 @@
 #include <linux/module.h>
 #include <linux/platform_device.h>
 #include <linux/spinlock.h>
+
+#include <asm/mach/irq.h>
+
 #include <mach/msm_iomap.h>
 #include "gpiomux.h"
 
@@ -309,8 +312,10 @@ static int msm_gpio_irq_set_type(struct irq_data *d, unsigned int flow_type)
  */
 static void msm_summary_irq_handler(unsigned int irq, struct irq_desc *desc)
 {
-        struct irq_data *data = irq_desc_get_irq_data(desc);
         unsigned long i;
+        struct irq_chip *chip = irq_desc_get_chip(desc);
+
+        chained_irq_enter(chip, desc);
 
         for (i = find_first_bit(msm_gpio.enabled_irqs, NR_GPIO_IRQS);
              i < NR_GPIO_IRQS;
@@ -319,7 +324,8 @@ static void msm_summary_irq_handler(unsigned int irq, struct irq_desc *desc)
                         generic_handle_irq(msm_gpio_to_irq(&msm_gpio.gpio_chip,
                                                            i));
         }
-        data->chip->irq_ack(data);
+
+        chained_irq_exit(chip, desc);
 }
 
 static int msm_gpio_irq_set_wake(struct irq_data *d, unsigned int on)
diff --git a/arch/arm/mach-mv78xx0/common.c b/arch/arm/mach-mv78xx0/common.c
index 44fb4e55be0..23d3980ef59 100644
--- a/arch/arm/mach-mv78xx0/common.c
+++ b/arch/arm/mach-mv78xx0/common.c
@@ -13,8 +13,6 @@
 #include <linux/platform_device.h>
 #include <linux/serial_8250.h>
 #include <linux/mbus.h>
-#include <linux/mv643xx_eth.h>
-#include <linux/mv643xx_i2c.h>
 #include <linux/ata_platform.h>
 #include <linux/ethtool.h>
 #include <asm/mach/map.h>
@@ -22,11 +20,12 @@
 #include <mach/mv78xx0.h>
 #include <mach/bridge-regs.h>
 #include <plat/cache-feroceon-l2.h>
-#include <plat/ehci-orion.h>
 #include <plat/orion_nand.h>
 #include <plat/time.h>
+#include <plat/common.h>
 #include "common.h"
 
+static int get_tclk(void);
 
 /*****************************************************************************
  * Common bits
@@ -168,285 +167,62 @@ void __init mv78xx0_map_io(void)
 /*****************************************************************************
  * EHCI
  ****************************************************************************/
-static struct orion_ehci_data mv78xx0_ehci_data = {
-        .dram           = &mv78xx0_mbus_dram_info,
-        .phy_version    = EHCI_PHY_NA,
-};
-
-static u64 ehci_dmamask = 0xffffffffUL;
-
-
-/*****************************************************************************
- * EHCI0
- ****************************************************************************/
-static struct resource mv78xx0_ehci0_resources[] = {
-        {
-                .start  = USB0_PHYS_BASE,
-                .end    = USB0_PHYS_BASE + 0x0fff,
-                .flags  = IORESOURCE_MEM,
-        }, {
-                .start  = IRQ_MV78XX0_USB_0,
-                .end    = IRQ_MV78XX0_USB_0,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device mv78xx0_ehci0 = {
-        .name           = "orion-ehci",
-        .id             = 0,
-        .dev            = {
-                .dma_mask               = &ehci_dmamask,
-                .coherent_dma_mask      = 0xffffffff,
-                .platform_data          = &mv78xx0_ehci_data,
-        },
-        .resource       = mv78xx0_ehci0_resources,
-        .num_resources  = ARRAY_SIZE(mv78xx0_ehci0_resources),
-};
-
 void __init mv78xx0_ehci0_init(void)
 {
-        platform_device_register(&mv78xx0_ehci0);
+        orion_ehci_init(&mv78xx0_mbus_dram_info,
+                        USB0_PHYS_BASE, IRQ_MV78XX0_USB_0);
 }
 
 
 /*****************************************************************************
  * EHCI1
  ****************************************************************************/
-static struct resource mv78xx0_ehci1_resources[] = {
-        {
-                .start  = USB1_PHYS_BASE,
-                .end    = USB1_PHYS_BASE + 0x0fff,
-                .flags  = IORESOURCE_MEM,
-        }, {
-                .start  = IRQ_MV78XX0_USB_1,
-                .end    = IRQ_MV78XX0_USB_1,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device mv78xx0_ehci1 = {
-        .name           = "orion-ehci",
-        .id             = 1,
-        .dev            = {
-                .dma_mask               = &ehci_dmamask,
-                .coherent_dma_mask      = 0xffffffff,
-                .platform_data          = &mv78xx0_ehci_data,
-        },
-        .resource       = mv78xx0_ehci1_resources,
-        .num_resources  = ARRAY_SIZE(mv78xx0_ehci1_resources),
-};
-
 void __init mv78xx0_ehci1_init(void)
 {
-        platform_device_register(&mv78xx0_ehci1);
+        orion_ehci_1_init(&mv78xx0_mbus_dram_info,
+                          USB1_PHYS_BASE, IRQ_MV78XX0_USB_1);
 }
 
 
 /*****************************************************************************
  * EHCI2
  ****************************************************************************/
-static struct resource mv78xx0_ehci2_resources[] = {
-        {
-                .start  = USB2_PHYS_BASE,
-                .end    = USB2_PHYS_BASE + 0x0fff,
-                .flags  = IORESOURCE_MEM,
-        }, {
-                .start  = IRQ_MV78XX0_USB_2,
-                .end    = IRQ_MV78XX0_USB_2,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device mv78xx0_ehci2 = {
-        .name           = "orion-ehci",
-        .id             = 2,
-        .dev            = {
-                .dma_mask               = &ehci_dmamask,
-                .coherent_dma_mask      = 0xffffffff,
-                .platform_data          = &mv78xx0_ehci_data,
-        },
-        .resource       = mv78xx0_ehci2_resources,
-        .num_resources  = ARRAY_SIZE(mv78xx0_ehci2_resources),
-};
-
 void __init mv78xx0_ehci2_init(void)
 {
-        platform_device_register(&mv78xx0_ehci2);
+        orion_ehci_2_init(&mv78xx0_mbus_dram_info,
+                          USB2_PHYS_BASE, IRQ_MV78XX0_USB_2);
 }
 
 
 /*****************************************************************************
  * GE00
  ****************************************************************************/
-struct mv643xx_eth_shared_platform_data mv78xx0_ge00_shared_data = {
-        .t_clk          = 0,
-        .dram           = &mv78xx0_mbus_dram_info,
-};
-
-static struct resource mv78xx0_ge00_shared_resources[] = {
-        {
-                .name   = "ge00 base",
-                .start  = GE00_PHYS_BASE + 0x2000,
-                .end    = GE00_PHYS_BASE + 0x3fff,
-                .flags  = IORESOURCE_MEM,
-        }, {
-                .name   = "ge err irq",
-                .start  = IRQ_MV78XX0_GE_ERR,
-                .end    = IRQ_MV78XX0_GE_ERR,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device mv78xx0_ge00_shared = {
-        .name           = MV643XX_ETH_SHARED_NAME,
-        .id             = 0,
-        .dev            = {
-                .platform_data  = &mv78xx0_ge00_shared_data,
-        },
-        .num_resources  = ARRAY_SIZE(mv78xx0_ge00_shared_resources),
-        .resource       = mv78xx0_ge00_shared_resources,
-};
-
-static struct resource mv78xx0_ge00_resources[] = {
-        {
-                .name   = "ge00 irq",
-                .start  = IRQ_MV78XX0_GE00_SUM,
-                .end    = IRQ_MV78XX0_GE00_SUM,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device mv78xx0_ge00 = {
-        .name           = MV643XX_ETH_NAME,
-        .id             = 0,
-        .num_resources  = 1,
-        .resource       = mv78xx0_ge00_resources,
-        .dev            = {
-                .coherent_dma_mask      = 0xffffffff,
-        },
-};
-
 void __init mv78xx0_ge00_init(struct mv643xx_eth_platform_data *eth_data)
 {
-        eth_data->shared = &mv78xx0_ge00_shared;
-        mv78xx0_ge00.dev.platform_data = eth_data;
-
-        platform_device_register(&mv78xx0_ge00_shared);
-        platform_device_register(&mv78xx0_ge00);
+        orion_ge00_init(eth_data, &mv78xx0_mbus_dram_info,
+                        GE00_PHYS_BASE, IRQ_MV78XX0_GE00_SUM,
+                        IRQ_MV78XX0_GE_ERR, get_tclk());
 }
 
 
 /*****************************************************************************
  * GE01
  ****************************************************************************/
-struct mv643xx_eth_shared_platform_data mv78xx0_ge01_shared_data = {
-        .t_clk          = 0,
-        .dram           = &mv78xx0_mbus_dram_info,
-        .shared_smi     = &mv78xx0_ge00_shared,
-};
-
-static struct resource mv78xx0_ge01_shared_resources[] = {
-        {
-                .name   = "ge01 base",
-                .start  = GE01_PHYS_BASE + 0x2000,
-                .end    = GE01_PHYS_BASE + 0x3fff,
-                .flags  = IORESOURCE_MEM,
-        },
-};
-
-static struct platform_device mv78xx0_ge01_shared = {
-        .name           = MV643XX_ETH_SHARED_NAME,
-        .id             = 1,
-        .dev            = {
-                .platform_data  = &mv78xx0_ge01_shared_data,
-        },
-        .num_resources  = 1,
-        .resource       = mv78xx0_ge01_shared_resources,
-};
-
-static struct resource mv78xx0_ge01_resources[] = {
-        {
-                .name   = "ge01 irq",
-                .start  = IRQ_MV78XX0_GE01_SUM,
-                .end    = IRQ_MV78XX0_GE01_SUM,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device mv78xx0_ge01 = {
-        .name           = MV643XX_ETH_NAME,
-        .id             = 1,
-        .num_resources  = 1,
-        .resource       = mv78xx0_ge01_resources,
-        .dev            = {
-                .coherent_dma_mask      = 0xffffffff,
-        },
-};
-
 void __init mv78xx0_ge01_init(struct mv643xx_eth_platform_data *eth_data)
 {
-        eth_data->shared = &mv78xx0_ge01_shared;
-        mv78xx0_ge01.dev.platform_data = eth_data;
-
-        platform_device_register(&mv78xx0_ge01_shared);
-        platform_device_register(&mv78xx0_ge01);
+        orion_ge01_init(eth_data, &mv78xx0_mbus_dram_info,
+                        GE01_PHYS_BASE, IRQ_MV78XX0_GE01_SUM,
+                        NO_IRQ, get_tclk());
 }
 
 
 /*****************************************************************************
  * GE10
  ****************************************************************************/
-struct mv643xx_eth_shared_platform_data mv78xx0_ge10_shared_data = {
-        .t_clk          = 0,
-        .dram           = &mv78xx0_mbus_dram_info,
-        .shared_smi     = &mv78xx0_ge00_shared,
-};
-
-static struct resource mv78xx0_ge10_shared_resources[] = {
-        {
-                .name   = "ge10 base",
-                .start  = GE10_PHYS_BASE + 0x2000,
-                .end    = GE10_PHYS_BASE + 0x3fff,
-                .flags  = IORESOURCE_MEM,
-        },
-};
-
-static struct platform_device mv78xx0_ge10_shared = {
-        .name           = MV643XX_ETH_SHARED_NAME,
-        .id             = 2,
-        .dev            = {
-                .platform_data  = &mv78xx0_ge10_shared_data,
-        },
-        .num_resources  = 1,
-        .resource       = mv78xx0_ge10_shared_resources,
-};
-
-static struct resource mv78xx0_ge10_resources[] = {
-        {
-                .name   = "ge10 irq",
-                .start  = IRQ_MV78XX0_GE10_SUM,
-                .end    = IRQ_MV78XX0_GE10_SUM,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device mv78xx0_ge10 = {
-        .name           = MV643XX_ETH_NAME,
-        .id             = 2,
-        .num_resources  = 1,
-        .resource       = mv78xx0_ge10_resources,
-        .dev            = {
-                .coherent_dma_mask      = 0xffffffff,
-        },
-};
-
 void __init mv78xx0_ge10_init(struct mv643xx_eth_platform_data *eth_data)
 {
         u32 dev, rev;
 
-        eth_data->shared = &mv78xx0_ge10_shared;
-        mv78xx0_ge10.dev.platform_data = eth_data;
-
         /*
          * On the Z0, ge10 and ge11 are internally connected back
          * to back, and not brought out.
@@ -458,65 +234,19 @@ void __init mv78xx0_ge10_init(struct mv643xx_eth_platform_data *eth_data)
                 eth_data->duplex = DUPLEX_FULL;
         }
 
-        platform_device_register(&mv78xx0_ge10_shared);
-        platform_device_register(&mv78xx0_ge10);
+        orion_ge10_init(eth_data, &mv78xx0_mbus_dram_info,
+                        GE10_PHYS_BASE, IRQ_MV78XX0_GE10_SUM,
+                        NO_IRQ, get_tclk());
 }
 
 
 /*****************************************************************************
  * GE11
  ****************************************************************************/
-struct mv643xx_eth_shared_platform_data mv78xx0_ge11_shared_data = {
-        .t_clk          = 0,
-        .dram           = &mv78xx0_mbus_dram_info,
-        .shared_smi     = &mv78xx0_ge00_shared,
-};
-
-static struct resource mv78xx0_ge11_shared_resources[] = {
-        {
-                .name   = "ge11 base",
-                .start  = GE11_PHYS_BASE + 0x2000,
-                .end    = GE11_PHYS_BASE + 0x3fff,
-                .flags  = IORESOURCE_MEM,
-        },
-};
-
-static struct platform_device mv78xx0_ge11_shared = {
-        .name           = MV643XX_ETH_SHARED_NAME,
-        .id             = 3,
-        .dev            = {
-                .platform_data  = &mv78xx0_ge11_shared_data,
-        },
-        .num_resources  = 1,
-        .resource       = mv78xx0_ge11_shared_resources,
-};
-
-static struct resource mv78xx0_ge11_resources[] = {
-        {
-                .name   = "ge11 irq",
-                .start  = IRQ_MV78XX0_GE11_SUM,
-                .end    = IRQ_MV78XX0_GE11_SUM,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device mv78xx0_ge11 = {
-        .name           = MV643XX_ETH_NAME,
-        .id             = 3,
-        .num_resources  = 1,
-        .resource       = mv78xx0_ge11_resources,
-        .dev            = {
-                .coherent_dma_mask      = 0xffffffff,
-        },
-};
-
 void __init mv78xx0_ge11_init(struct mv643xx_eth_platform_data *eth_data)
 {
         u32 dev, rev;
 
-        eth_data->shared = &mv78xx0_ge11_shared;
-        mv78xx0_ge11.dev.platform_data = eth_data;
-
         /*
          * On the Z0, ge10 and ge11 are internally connected back
          * to back, and not brought out.
@@ -528,293 +258,68 @@ void __init mv78xx0_ge11_init(struct mv643xx_eth_platform_data *eth_data)
                 eth_data->duplex = DUPLEX_FULL;
         }
 
-        platform_device_register(&mv78xx0_ge11_shared);
-        platform_device_register(&mv78xx0_ge11);
+        orion_ge11_init(eth_data, &mv78xx0_mbus_dram_info,
+                        GE11_PHYS_BASE, IRQ_MV78XX0_GE11_SUM,
+                        NO_IRQ, get_tclk());
 }
 
 /*****************************************************************************
- * I2C bus 0
- ****************************************************************************/
-
-static struct mv64xxx_i2c_pdata mv78xx0_i2c_0_pdata = {
-        .freq_m         = 8, /* assumes 166 MHz TCLK */
-        .freq_n         = 3,
-        .timeout        = 1000, /* Default timeout of 1 second */
-};
-
-static struct resource mv78xx0_i2c_0_resources[] = {
-        {
-                .start  = I2C_0_PHYS_BASE,
-                .end    = I2C_0_PHYS_BASE + 0x1f,
-                .flags  = IORESOURCE_MEM,
-        }, {
-                .start  = IRQ_MV78XX0_I2C_0,
-                .end    = IRQ_MV78XX0_I2C_0,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-
-static struct platform_device mv78xx0_i2c_0 = {
-        .name           = MV64XXX_I2C_CTLR_NAME,
-        .id             = 0,
-        .num_resources  = ARRAY_SIZE(mv78xx0_i2c_0_resources),
-        .resource       = mv78xx0_i2c_0_resources,
-        .dev            = {
-                .platform_data  = &mv78xx0_i2c_0_pdata,
-        },
-};
-
-/*****************************************************************************
- * I2C bus 1
+ * I2C
  ****************************************************************************/
-
-static struct mv64xxx_i2c_pdata mv78xx0_i2c_1_pdata = {
-        .freq_m         = 8, /* assumes 166 MHz TCLK */
-        .freq_n         = 3,
-        .timeout        = 1000, /* Default timeout of 1 second */
-};
-
-static struct resource mv78xx0_i2c_1_resources[] = {
-        {
-                .start  = I2C_1_PHYS_BASE,
-                .end    = I2C_1_PHYS_BASE + 0x1f,
-                .flags  = IORESOURCE_MEM,
-        }, {
-                .start  = IRQ_MV78XX0_I2C_1,
-                .end    = IRQ_MV78XX0_I2C_1,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-
-static struct platform_device mv78xx0_i2c_1 = {
-        .name           = MV64XXX_I2C_CTLR_NAME,
-        .id             = 1,
-        .num_resources  = ARRAY_SIZE(mv78xx0_i2c_1_resources),
-        .resource       = mv78xx0_i2c_1_resources,
-        .dev            = {
-                .platform_data  = &mv78xx0_i2c_1_pdata,
-        },
-};
-
 void __init mv78xx0_i2c_init(void)
 {
-        platform_device_register(&mv78xx0_i2c_0);
-        platform_device_register(&mv78xx0_i2c_1);
+        orion_i2c_init(I2C_0_PHYS_BASE, IRQ_MV78XX0_I2C_0, 8);
+        orion_i2c_1_init(I2C_1_PHYS_BASE, IRQ_MV78XX0_I2C_1, 8);
 }
 
 /*****************************************************************************
  * SATA
  ****************************************************************************/
-static struct resource mv78xx0_sata_resources[] = {
-        {
-                .name   = "sata base",
-                .start  = SATA_PHYS_BASE,
-                .end    = SATA_PHYS_BASE + 0x5000 - 1,
-                .flags  = IORESOURCE_MEM,
-        }, {
-                .name   = "sata irq",
-                .start  = IRQ_MV78XX0_SATA,
-                .end    = IRQ_MV78XX0_SATA,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device mv78xx0_sata = {
-        .name           = "sata_mv",
-        .id             = 0,
-        .dev            = {
-                .coherent_dma_mask      = 0xffffffff,
-        },
-        .num_resources  = ARRAY_SIZE(mv78xx0_sata_resources),
-        .resource       = mv78xx0_sata_resources,
-};
-
 void __init mv78xx0_sata_init(struct mv_sata_platform_data *sata_data)
 {
-        sata_data->dram = &mv78xx0_mbus_dram_info;
-        mv78xx0_sata.dev.platform_data = sata_data;
-        platform_device_register(&mv78xx0_sata);
+        orion_sata_init(sata_data, &mv78xx0_mbus_dram_info,
+                        SATA_PHYS_BASE, IRQ_MV78XX0_SATA);
 }
 
 
 /*****************************************************************************
  * UART0
  ****************************************************************************/
-static struct plat_serial8250_port mv78xx0_uart0_data[] = {
-        {
-                .mapbase        = UART0_PHYS_BASE,
-                .membase        = (char *)UART0_VIRT_BASE,
-                .irq            = IRQ_MV78XX0_UART_0,
-                .flags          = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
-                .iotype         = UPIO_MEM,
-                .regshift       = 2,
-                .uartclk        = 0,
-        }, {
-        },
-};
-
-static struct resource mv78xx0_uart0_resources[] = {
-        {
-                .start          = UART0_PHYS_BASE,
-                .end            = UART0_PHYS_BASE + 0xff,
-                .flags          = IORESOURCE_MEM,
-        }, {
-                .start          = IRQ_MV78XX0_UART_0,
-                .end            = IRQ_MV78XX0_UART_0,
-                .flags          = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device mv78xx0_uart0 = {
-        .name                   = "serial8250",
-        .id                     = 0,
-        .dev                    = {
-                .platform_data  = mv78xx0_uart0_data,
-        },
-        .resource               = mv78xx0_uart0_resources,
-        .num_resources          = ARRAY_SIZE(mv78xx0_uart0_resources),
-};
-
 void __init mv78xx0_uart0_init(void)
 {
-        platform_device_register(&mv78xx0_uart0);
+        orion_uart0_init(UART0_VIRT_BASE, UART0_PHYS_BASE,
+                         IRQ_MV78XX0_UART_0, get_tclk());
 }
 
 
 /*****************************************************************************
  * UART1
  ****************************************************************************/
-static struct plat_serial8250_port mv78xx0_uart1_data[] = {
-        {
-                .mapbase        = UART1_PHYS_BASE,
-                .membase        = (char *)UART1_VIRT_BASE,
-                .irq            = IRQ_MV78XX0_UART_1,
-                .flags          = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
-                .iotype         = UPIO_MEM,
-                .regshift       = 2,
-                .uartclk        = 0,
-        }, {
-        },
-};
-
-static struct resource mv78xx0_uart1_resources[] = {
-        {
-                .start          = UART1_PHYS_BASE,
-                .end            = UART1_PHYS_BASE + 0xff,
-                .flags          = IORESOURCE_MEM,
-        }, {
-                .start          = IRQ_MV78XX0_UART_1,
-                .end            = IRQ_MV78XX0_UART_1,
-                .flags          = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device mv78xx0_uart1 = {
-        .name                   = "serial8250",
-        .id                     = 1,
-        .dev                    = {
-                .platform_data  = mv78xx0_uart1_data,
-        },
-        .resource               = mv78xx0_uart1_resources,
-        .num_resources          = ARRAY_SIZE(mv78xx0_uart1_resources),
-};
-
 void __init mv78xx0_uart1_init(void)
 {
-        platform_device_register(&mv78xx0_uart1);
+        orion_uart1_init(UART1_VIRT_BASE, UART1_PHYS_BASE,
+                         IRQ_MV78XX0_UART_1, get_tclk());
 }
 
 
 /*****************************************************************************
  * UART2
  ****************************************************************************/
-static struct plat_serial8250_port mv78xx0_uart2_data[] = {
-        {
-                .mapbase        = UART2_PHYS_BASE,
-                .membase        = (char *)UART2_VIRT_BASE,
-                .irq            = IRQ_MV78XX0_UART_2,
-                .flags          = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
-                .iotype         = UPIO_MEM,
-                .regshift       = 2,
-                .uartclk        = 0,
-        }, {
-        },
-};
-
-static struct resource mv78xx0_uart2_resources[] = {
-        {
-                .start          = UART2_PHYS_BASE,
-                .end            = UART2_PHYS_BASE + 0xff,
-                .flags          = IORESOURCE_MEM,
-        }, {
-                .start          = IRQ_MV78XX0_UART_2,
-                .end            = IRQ_MV78XX0_UART_2,
-                .flags          = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device mv78xx0_uart2 = {
-        .name                   = "serial8250",
-        .id                     = 2,
-        .dev                    = {
-                .platform_data  = mv78xx0_uart2_data,
-        },
-        .resource               = mv78xx0_uart2_resources,
-        .num_resources          = ARRAY_SIZE(mv78xx0_uart2_resources),
-};
-
 void __init mv78xx0_uart2_init(void)
 {
-        platform_device_register(&mv78xx0_uart2);
+        orion_uart2_init(UART2_VIRT_BASE, UART2_PHYS_BASE,
+                         IRQ_MV78XX0_UART_2, get_tclk());
 }
 
-
 /*****************************************************************************
  * UART3
  ****************************************************************************/
-static struct plat_serial8250_port mv78xx0_uart3_data[] = {
-        {
-                .mapbase        = UART3_PHYS_BASE,
-                .membase        = (char *)UART3_VIRT_BASE,
-                .irq            = IRQ_MV78XX0_UART_3,
-                .flags          = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
-                .iotype         = UPIO_MEM,
-                .regshift       = 2,
-                .uartclk        = 0,
-        }, {
-        },
-};
-
-static struct resource mv78xx0_uart3_resources[] = {
-        {
-                .start          = UART3_PHYS_BASE,
-                .end            = UART3_PHYS_BASE + 0xff,
-                .flags          = IORESOURCE_MEM,
-        }, {
-                .start          = IRQ_MV78XX0_UART_3,
-                .end            = IRQ_MV78XX0_UART_3,
-                .flags          = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device mv78xx0_uart3 = {
-        .name                   = "serial8250",
-        .id                     = 3,
-        .dev                    = {
-                .platform_data  = mv78xx0_uart3_data,
-        },
-        .resource               = mv78xx0_uart3_resources,
-        .num_resources          = ARRAY_SIZE(mv78xx0_uart3_resources),
-};
-
 void __init mv78xx0_uart3_init(void)
 {
-        platform_device_register(&mv78xx0_uart3);
+        orion_uart3_init(UART3_VIRT_BASE, UART3_PHYS_BASE,
+                         IRQ_MV78XX0_UART_3, get_tclk());
 }
 
-
 /*****************************************************************************
  * Time handling
  ****************************************************************************/
@@ -895,13 +400,4 @@ void __init mv78xx0_init(void)
 #ifdef CONFIG_CACHE_FEROCEON_L2
         feroceon_l2_init(is_l2_writethrough());
 #endif
-
-        mv78xx0_ge00_shared_data.t_clk = tclk;
-        mv78xx0_ge01_shared_data.t_clk = tclk;
-        mv78xx0_ge10_shared_data.t_clk = tclk;
-        mv78xx0_ge11_shared_data.t_clk = tclk;
-        mv78xx0_uart0_data[0].uartclk = tclk;
-        mv78xx0_uart1_data[0].uartclk = tclk;
-        mv78xx0_uart2_data[0].uartclk = tclk;
-        mv78xx0_uart3_data[0].uartclk = tclk;
 }
diff --git a/arch/arm/mach-mv78xx0/mpp.c b/arch/arm/mach-mv78xx0/mpp.c
index 65b72c454cb..59b7686b920 100644
--- a/arch/arm/mach-mv78xx0/mpp.c
+++ b/arch/arm/mach-mv78xx0/mpp.c
@@ -12,6 +12,7 @@
 #include <linux/init.h>
 #include <linux/mbus.h>
 #include <linux/io.h>
+#include <plat/mpp.h>
 #include <asm/gpio.h>
 #include <mach/hardware.h>
 #include "common.h"
@@ -31,61 +32,8 @@ static unsigned int __init mv78xx0_variant(void)
         return 0;
 }
 
-#define MPP_CTRL(i)     (DEV_BUS_VIRT_BASE + (i) * 4)
-#define MPP_NR_REGS     (1 + MPP_MAX/8)
-
 void __init mv78xx0_mpp_conf(unsigned int *mpp_list)
 {
-        u32 mpp_ctrl[MPP_NR_REGS];
-        unsigned int variant_mask;
-        int i;
-
-        variant_mask = mv78xx0_variant();
-        if (!variant_mask)
-                return;
-
-        printk(KERN_DEBUG "initial MPP regs:");
-        for (i = 0; i < MPP_NR_REGS; i++) {
-                mpp_ctrl[i] = readl(MPP_CTRL(i));
-                printk(" %08x", mpp_ctrl[i]);
-        }
-        printk("\n");
-
-        for ( ; *mpp_list; mpp_list++) {
-                unsigned int num = MPP_NUM(*mpp_list);
-                unsigned int sel = MPP_SEL(*mpp_list);
-                int shift, gpio_mode;
-
-                if (num > MPP_MAX) {
-                        printk(KERN_ERR "mv78xx0_mpp_conf: invalid MPP "
-                                        "number (%u)\n", num);
-                        continue;
-                }
-                if (!(*mpp_list & variant_mask)) {
-                        printk(KERN_WARNING
-                                        "mv78xx0_mpp_conf: requested MPP%u config "
-                                        "unavailable on this hardware\n", num);
-                        continue;
-                }
-
-                shift = (num & 7) << 2;
-                mpp_ctrl[num / 8] &= ~(0xf << shift);
-                mpp_ctrl[num / 8] |= sel << shift;
-
-                gpio_mode = 0;
-                if (*mpp_list & MPP_INPUT_MASK)
-                        gpio_mode |= GPIO_INPUT_OK;
-                if (*mpp_list & MPP_OUTPUT_MASK)
-                        gpio_mode |= GPIO_OUTPUT_OK;
-                if (sel != 0)
-                        gpio_mode = 0;
-                orion_gpio_set_valid(num, gpio_mode);
-        }
-
-        printk(KERN_DEBUG "  final MPP regs:");
-        for (i = 0; i < MPP_NR_REGS; i++) {
-                writel(mpp_ctrl[i], MPP_CTRL(i));
-                printk(" %08x", mpp_ctrl[i]);
-        }
-        printk("\n");
+        orion_mpp_conf(mpp_list, mv78xx0_variant(),
+                       MPP_MAX, DEV_BUS_VIRT_BASE);
 }
diff --git a/arch/arm/mach-mv78xx0/mpp.h b/arch/arm/mach-mv78xx0/mpp.h
index 80840b781ea..b61b5092712 100644
--- a/arch/arm/mach-mv78xx0/mpp.h
+++ b/arch/arm/mach-mv78xx0/mpp.h
@@ -19,14 +19,8 @@
     /* may be output signal */    ((!!(_out)) << 13) | \
     /* available on A0 */    ((!!(_78100_A0)) << 14))
 
-#define MPP_NUM(x)    ((x) & 0xff)
-#define MPP_SEL(x)    (((x) >> 8) & 0xf)
-
                 /*   num sel  i  o  78100_A0  */
 
-#define MPP_INPUT_MASK        MPP(0, 0x0, 1, 0, 0)
-#define MPP_OUTPUT_MASK        MPP(0, 0x0, 0, 1, 0)
-
 #define MPP_78100_A0_MASK    MPP(0, 0x0, 0, 0, 1)
 
 #define MPP0_GPIO        MPP(0, 0x0, 1, 1, 1)
diff --git a/arch/arm/mach-mx3/Kconfig b/arch/arm/mach-mx3/Kconfig
deleted file mode 100644
index 340809a7d23..00000000000
--- a/arch/arm/mach-mx3/Kconfig
+++ /dev/null
@@ -1,257 +0,0 @@
-if ARCH_MX3
-
-# ARCH_MX31 and ARCH_MX35 are left for compatibility
-# Some usages assume that having one of them implies not having (e.g.) ARCH_MX2.
-# To easily distinguish good and reviewed from unreviewed usages new (and IMHO
-# more sensible) names are used: SOC_IMX31 and SOC_IMX35
-config ARCH_MX31
-        bool
-
-config ARCH_MX35
-        bool
-
-config SOC_IMX31
-        bool
-        select IMX_HAVE_PLATFORM_MXC_RNGA
-        select ARCH_MXC_AUDMUX_V2
-        select ARCH_MX31
-        select MXC_AVIC
-
-config SOC_IMX35
-        bool
-        select ARCH_MXC_IOMUX_V3
-        select ARCH_MXC_AUDMUX_V2
-        select HAVE_EPIT
-        select ARCH_MX35
-        select MXC_AVIC
-
-comment "MX3 platforms:"
-
-config MACH_MX31ADS
-        bool "Support MX31ADS platforms"
-        select SOC_IMX31
-        select IMX_HAVE_PLATFORM_IMX_I2C
-        select IMX_HAVE_PLATFORM_IMX_SSI
-        select IMX_HAVE_PLATFORM_IMX_UART
-        default y
-        help
-          Include support for MX31ADS platform. This includes specific
-          configurations for the board and its peripherals.
-
-config MACH_MX31ADS_WM1133_EV1
-        bool "Support Wolfson Microelectronics 1133-EV1 module"
-        depends on MACH_MX31ADS
-        depends on MFD_WM8350_I2C
-        depends on REGULATOR_WM8350
-        select MFD_WM8350_CONFIG_MODE_0
-        select MFD_WM8352_CONFIG_MODE_0
-        help
-          Include support for the Wolfson Microelectronics 1133-EV1 PMU
-          and audio module for the MX31ADS platform.
-
-config MACH_PCM037
-        bool "Support Phytec pcm037 (i.MX31) platforms"
-        select SOC_IMX31
-        select IMX_HAVE_PLATFORM_FSL_USB2_UDC
-        select IMX_HAVE_PLATFORM_IMX2_WDT
-        select IMX_HAVE_PLATFORM_IMX_I2C
-        select IMX_HAVE_PLATFORM_IMX_UART
-        select IMX_HAVE_PLATFORM_MXC_EHCI
-        select IMX_HAVE_PLATFORM_MXC_MMC
-        select IMX_HAVE_PLATFORM_MXC_NAND
-        select IMX_HAVE_PLATFORM_MXC_W1
-        select MXC_ULPI if USB_ULPI
-        help
-          Include support for Phytec pcm037 platform. This includes
-          specific configurations for the board and its peripherals.
-
-config MACH_PCM037_EET
-        bool "Support pcm037 EET board extensions"
-        depends on MACH_PCM037
-        select IMX_HAVE_PLATFORM_SPI_IMX
-        help
-          Add support for PCM037 EET baseboard extensions. If you are using the
-          OLED display with EET, use "video=mx3fb:CMEL-OLED" kernel
-          command-line parameter.
-
-config MACH_MX31LITE
-        bool "Support MX31 LITEKIT (LogicPD)"
-        select SOC_IMX31
-        select MXC_ULPI if USB_ULPI
-        select IMX_HAVE_PLATFORM_IMX2_WDT
-        select IMX_HAVE_PLATFORM_IMX_UART
-        select IMX_HAVE_PLATFORM_MXC_EHCI
-        select IMX_HAVE_PLATFORM_MXC_MMC
-        select IMX_HAVE_PLATFORM_MXC_NAND
-        select IMX_HAVE_PLATFORM_SPI_IMX
-        help
-          Include support for MX31 LITEKIT platform. This includes specific
-          configurations for the board and its peripherals.
-
-config MACH_MX31_3DS
-        bool "Support MX31PDK (3DS)"
-        select SOC_IMX31
-        select MXC_DEBUG_BOARD
-        select IMX_HAVE_PLATFORM_FSL_USB2_UDC
-        select IMX_HAVE_PLATFORM_IMX2_WDT
-        select IMX_HAVE_PLATFORM_IMX_I2C
-        select IMX_HAVE_PLATFORM_IMX_KEYPAD
-        select IMX_HAVE_PLATFORM_IMX_UART
-        select IMX_HAVE_PLATFORM_MXC_EHCI
-        select IMX_HAVE_PLATFORM_MXC_NAND
-        select IMX_HAVE_PLATFORM_SPI_IMX
-        select MXC_ULPI if USB_ULPI
-        help
-          Include support for MX31PDK (3DS) platform. This includes specific
-          configurations for the board and its peripherals.
-
-config MACH_MX31_3DS_MXC_NAND_USE_BBT
-        bool "Make the MXC NAND driver use the in flash Bad Block Table"
-        depends on MACH_MX31_3DS
-        depends on MTD_NAND_MXC
-        help
-          Enable this if you want that the MXC NAND driver uses the in flash
-          Bad Block Table to know what blocks are bad instead of scanning the
-          entire flash looking for bad block markers.
-
-config MACH_MX31MOBOARD
-        bool "Support mx31moboard platforms (EPFL Mobots group)"
-        select SOC_IMX31
-        select IMX_HAVE_PLATFORM_FSL_USB2_UDC
-        select IMX_HAVE_PLATFORM_IMX_I2C
-        select IMX_HAVE_PLATFORM_IMX_UART
-        select IMX_HAVE_PLATFORM_MXC_EHCI
-        select IMX_HAVE_PLATFORM_MXC_MMC
-        select IMX_HAVE_PLATFORM_SPI_IMX
-        select MXC_ULPI if USB_ULPI
-        help
-          Include support for mx31moboard platform. This includes specific
-          configurations for the board and its peripherals.
-
-config MACH_MX31LILLY
-        bool "Support MX31 LILLY-1131 platforms (INCO startec)"
-        select SOC_IMX31
-        select IMX_HAVE_PLATFORM_IMX_UART
-        select IMX_HAVE_PLATFORM_MXC_EHCI
-        select IMX_HAVE_PLATFORM_MXC_MMC
-        select IMX_HAVE_PLATFORM_SPI_IMX
-        select MXC_ULPI if USB_ULPI
-        help
-          Include support for mx31 based LILLY1131 modules. This includes
-          specific configurations for the board and its peripherals.
-
-config MACH_QONG
-        bool "Support Dave/DENX QongEVB-LITE platform"
-        select SOC_IMX31
-        select IMX_HAVE_PLATFORM_IMX_UART
-        help
-          Include support for Dave/DENX QongEVB-LITE platform. This includes
-          specific configurations for the board and its peripherals.
-
-config MACH_PCM043
-        bool "Support Phytec pcm043 (i.MX35) platforms"
-        select SOC_IMX35
-        select IMX_HAVE_PLATFORM_FLEXCAN
-        select IMX_HAVE_PLATFORM_FSL_USB2_UDC
-        select IMX_HAVE_PLATFORM_IMX2_WDT
-        select IMX_HAVE_PLATFORM_IMX_I2C
-        select IMX_HAVE_PLATFORM_IMX_SSI
-        select IMX_HAVE_PLATFORM_IMX_UART
-        select IMX_HAVE_PLATFORM_MXC_EHCI
-        select IMX_HAVE_PLATFORM_MXC_NAND
-        select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
-        select MXC_ULPI if USB_ULPI
-        help
-          Include support for Phytec pcm043 platform. This includes
-          specific configurations for the board and its peripherals.
-
-config MACH_ARMADILLO5X0
-        bool "Support Atmark Armadillo-500 Development Base Board"
-        select SOC_IMX31
-        select IMX_HAVE_PLATFORM_IMX_I2C
-        select IMX_HAVE_PLATFORM_IMX_UART
-        select IMX_HAVE_PLATFORM_MXC_EHCI
-        select IMX_HAVE_PLATFORM_MXC_MMC
-        select IMX_HAVE_PLATFORM_MXC_NAND
-        select MXC_ULPI if USB_ULPI
-        help
-          Include support for Atmark Armadillo-500 platform. This includes
-          specific configurations for the board and its peripherals.
-
-config MACH_MX35_3DS
-        bool "Support MX35PDK platform"
-        select SOC_IMX35
-        select MXC_DEBUG_BOARD
-        select IMX_HAVE_PLATFORM_FSL_USB2_UDC
-        select IMX_HAVE_PLATFORM_IMX2_WDT
-        select IMX_HAVE_PLATFORM_IMX_I2C
-        select IMX_HAVE_PLATFORM_IMX_UART
-        select IMX_HAVE_PLATFORM_MXC_EHCI
-        select IMX_HAVE_PLATFORM_MXC_NAND
-        select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
-        help
-          Include support for MX35PDK platform. This includes specific
-          configurations for the board and its peripherals.
-
-config MACH_KZM_ARM11_01
-        bool "Support KZM-ARM11-01(Kyoto Microcomputer)"
-        select SOC_IMX31
-        select IMX_HAVE_PLATFORM_IMX_UART
-        help
-          Include support for KZM-ARM11-01. This includes specific
-          configurations for the board and its peripherals.
-
-config MACH_BUG
-        bool "Support Buglabs BUGBase platform"
-        select SOC_IMX31
-        select IMX_HAVE_PLATFORM_IMX_UART
-        default y
-        help
-          Include support for BUGBase 1.3 platform. This includes specific
-          configurations for the board and its peripherals.
-
-config MACH_EUKREA_CPUIMX35
-        bool "Support Eukrea CPUIMX35 Platform"
-        select SOC_IMX35
-        select IMX_HAVE_PLATFORM_FLEXCAN
-        select IMX_HAVE_PLATFORM_FSL_USB2_UDC
-        select IMX_HAVE_PLATFORM_IMX2_WDT
-        select IMX_HAVE_PLATFORM_IMX_I2C
-        select IMX_HAVE_PLATFORM_IMX_UART
-        select IMX_HAVE_PLATFORM_MXC_EHCI
-        select IMX_HAVE_PLATFORM_MXC_NAND
-        select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
-        select MXC_ULPI if USB_ULPI
-        help
-          Include support for Eukrea CPUIMX35 platform. This includes
-          specific configurations for the board and its peripherals.
-
-choice
-        prompt "Baseboard"
-        depends on MACH_EUKREA_CPUIMX35
-        default MACH_EUKREA_MBIMXSD35_BASEBOARD
-
-config MACH_EUKREA_MBIMXSD35_BASEBOARD
-        bool "Eukrea MBIMXSD development board"
-        select IMX_HAVE_PLATFORM_IMX_SSI
-        help
-          This adds board specific devices that can be found on Eukrea's
-          MBIMXSD evaluation board.
-
-endchoice
-
-config MACH_VPR200
-        bool "Support VPR200 platform"
-        select SOC_IMX35
-        select IMX_HAVE_PLATFORM_FSL_USB2_UDC
-        select IMX_HAVE_PLATFORM_IMX2_WDT
-        select IMX_HAVE_PLATFORM_IMX_UART
-        select IMX_HAVE_PLATFORM_IMX_I2C
-        select IMX_HAVE_PLATFORM_MXC_EHCI
-        select IMX_HAVE_PLATFORM_MXC_NAND
-        select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
-        help
-          Include support for VPR200 platform. This includes specific
-          configurations for the board and its peripherals.
-
-endif
diff --git a/arch/arm/mach-mx3/Makefile b/arch/arm/mach-mx3/Makefile
deleted file mode 100644
index a54faf2cf5f..00000000000
--- a/arch/arm/mach-mx3/Makefile
+++ /dev/null
@@ -1,26 +0,0 @@
-#
-# Makefile for the linux kernel.
-#
-
-# Object file lists.
-
-obj-y                           := mm.o devices.o cpu.o
-obj-$(CONFIG_SOC_IMX31)         += clock-imx31.o iomux-imx31.o ehci-imx31.o
-obj-$(CONFIG_SOC_IMX35)         += clock-imx35.o ehci-imx35.o
-obj-$(CONFIG_MACH_MX31ADS)      += mach-mx31ads.o
-obj-$(CONFIG_MACH_MX31LILLY)    += mach-mx31lilly.o mx31lilly-db.o
-obj-$(CONFIG_MACH_MX31LITE)     += mach-mx31lite.o mx31lite-db.o
-obj-$(CONFIG_MACH_PCM037)       += mach-pcm037.o
-obj-$(CONFIG_MACH_PCM037_EET)   += mach-pcm037_eet.o
-obj-$(CONFIG_MACH_MX31_3DS)     += mach-mx31_3ds.o
-obj-$(CONFIG_MACH_MX31MOBOARD)  += mach-mx31moboard.o mx31moboard-devboard.o \
-                                   mx31moboard-marxbot.o mx31moboard-smartbot.o
-obj-$(CONFIG_MACH_QONG)         += mach-qong.o
-obj-$(CONFIG_MACH_PCM043)       += mach-pcm043.o
-obj-$(CONFIG_MACH_ARMADILLO5X0) += mach-armadillo5x0.o
-obj-$(CONFIG_MACH_MX35_3DS)     += mach-mx35_3ds.o
-obj-$(CONFIG_MACH_KZM_ARM11_01) += mach-kzm_arm11_01.o
-obj-$(CONFIG_MACH_BUG)          += mach-bug.o
-obj-$(CONFIG_MACH_EUKREA_CPUIMX35)      += mach-cpuimx35.o
-obj-$(CONFIG_MACH_EUKREA_MBIMXSD35_BASEBOARD)   += eukrea_mbimxsd-baseboard.o
-obj-$(CONFIG_MACH_VPR200)       += mach-vpr200.o
diff --git a/arch/arm/mach-mx3/Makefile.boot b/arch/arm/mach-mx3/Makefile.boot
deleted file mode 100644
index e1dd366f836..00000000000
--- a/arch/arm/mach-mx3/Makefile.boot
+++ /dev/null
@@ -1,3 +0,0 @@
-   zreladdr-y   := 0x80008000
-params_phys-y   := 0x80000100
-initrd_phys-y   := 0x80800000
diff --git a/arch/arm/mach-mx3/devices.c b/arch/arm/mach-mx3/devices.c
deleted file mode 100644
index b6672db788f..00000000000
--- a/arch/arm/mach-mx3/devices.c
+++ /dev/null
@@ -1,115 +0,0 @@
-/*
- * Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
- * Copyright 2008 Sascha Hauer, kernel@pengutronix.de
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor,
- * Boston, MA  02110-1301, USA.
- */
-
-#include <linux/dma-mapping.h>
-#include <linux/module.h>
-#include <linux/platform_device.h>
-#include <linux/serial.h>
-#include <linux/gpio.h>
-#include <mach/hardware.h>
-#include <mach/irqs.h>
-#include <mach/common.h>
-#include <mach/mx3_camera.h>
-
-#include "devices.h"
-
-/* i.MX31 Image Processing Unit */
-
-/* The resource order is important! */
-static struct resource mx3_ipu_rsrc[] = {
-        {
-                .start = MX3x_IPU_CTRL_BASE_ADDR,
-                .end = MX3x_IPU_CTRL_BASE_ADDR + 0x5F,
-                .flags = IORESOURCE_MEM,
-        }, {
-                .start = MX3x_IPU_CTRL_BASE_ADDR + 0x88,
-                .end = MX3x_IPU_CTRL_BASE_ADDR + 0xB3,
-                .flags = IORESOURCE_MEM,
-        }, {
-                .start = MX3x_INT_IPU_SYN,
-                .end = MX3x_INT_IPU_SYN,
-                .flags = IORESOURCE_IRQ,
-        }, {
-                .start = MX3x_INT_IPU_ERR,
-                .end = MX3x_INT_IPU_ERR,
-                .flags = IORESOURCE_IRQ,
-        },
-};
-
-struct platform_device mx3_ipu = {
-        .name = "ipu-core",
-        .id = -1,
-        .num_resources = ARRAY_SIZE(mx3_ipu_rsrc),
-        .resource = mx3_ipu_rsrc,
-};
-
-static struct resource fb_resources[] = {
-        {
-                .start  = MX3x_IPU_CTRL_BASE_ADDR + 0xB4,
-                .end    = MX3x_IPU_CTRL_BASE_ADDR + 0x1BF,
-                .flags  = IORESOURCE_MEM,
-        },
-};
-
-struct platform_device mx3_fb = {
-        .name           = "mx3_sdc_fb",
-        .id             = -1,
-        .num_resources  = ARRAY_SIZE(fb_resources),
-        .resource       = fb_resources,
-        .dev            = {
-                .coherent_dma_mask = DMA_BIT_MASK(32),
-       },
-};
-
-static struct resource camera_resources[] = {
-        {
-                .start  = MX3x_IPU_CTRL_BASE_ADDR + 0x60,
-                .end    = MX3x_IPU_CTRL_BASE_ADDR + 0x87,
-                .flags  = IORESOURCE_MEM,
-        },
-};
-
-struct platform_device mx3_camera = {
-        .name           = "mx3-camera",
-        .id             = 0,
-        .num_resources  = ARRAY_SIZE(camera_resources),
-        .resource       = camera_resources,
-        .dev            = {
-                .coherent_dma_mask = DMA_BIT_MASK(32),
-        },
-};
-
-static struct resource imx_rtc_resources[] = {
-        {
-                .start  = MX31_RTC_BASE_ADDR,
-                .end    = MX31_RTC_BASE_ADDR + 0x3fff,
-                .flags  = IORESOURCE_MEM,
-        },
-        {
-                .start  = MX31_INT_RTC,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-struct platform_device imx_rtc_device0 = {
-        .name           = "mxc_rtc",
-        .id             = -1,
-        .num_resources  = ARRAY_SIZE(imx_rtc_resources),
-        .resource       = imx_rtc_resources,
-};
diff --git a/arch/arm/mach-mx3/devices.h b/arch/arm/mach-mx3/devices.h
deleted file mode 100644
index 121962c568d..00000000000
--- a/arch/arm/mach-mx3/devices.h
+++ /dev/null
@@ -1,4 +0,0 @@
-extern struct platform_device mx3_ipu;
-extern struct platform_device mx3_fb;
-extern struct platform_device mx3_camera;
-extern struct platform_device imx_rtc_device0;
diff --git a/arch/arm/mach-mx3/mm.c b/arch/arm/mach-mx3/mm.c
deleted file mode 100644
index 54d7174b420..00000000000
--- a/arch/arm/mach-mx3/mm.c
+++ /dev/null
@@ -1,141 +0,0 @@
-/*
- *  Copyright (C) 1999,2000 Arm Limited
- *  Copyright (C) 2000 Deep Blue Solutions Ltd
- *  Copyright (C) 2002 Shane Nay (shane@minirl.com)
- *  Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
- *    - add MX31 specific definitions
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <linux/mm.h>
-#include <linux/init.h>
-#include <linux/err.h>
-
-#include <asm/pgtable.h>
-#include <asm/mach/map.h>
-#include <asm/hardware/cache-l2x0.h>
-
-#include <mach/common.h>
-#include <mach/hardware.h>
-#include <mach/iomux-v3.h>
-#include <mach/gpio.h>
-#include <mach/irqs.h>
-
-#ifdef CONFIG_SOC_IMX31
-static struct map_desc mx31_io_desc[] __initdata = {
-        imx_map_entry(MX31, X_MEMC, MT_DEVICE),
-        imx_map_entry(MX31, AVIC, MT_DEVICE_NONSHARED),
-        imx_map_entry(MX31, AIPS1, MT_DEVICE_NONSHARED),
-        imx_map_entry(MX31, AIPS2, MT_DEVICE_NONSHARED),
-        imx_map_entry(MX31, SPBA0, MT_DEVICE_NONSHARED),
-};
-
-/*
- * This function initializes the memory map. It is called during the
- * system startup to create static physical to virtual memory mappings
- * for the IO modules.
- */
-void __init mx31_map_io(void)
-{
-        iotable_init(mx31_io_desc, ARRAY_SIZE(mx31_io_desc));
-}
-
-void __init imx31_init_early(void)
-{
-        mxc_set_cpu_type(MXC_CPU_MX31);
-        mxc_arch_reset_init(MX31_IO_ADDRESS(MX31_WDOG_BASE_ADDR));
-}
-
-static struct mxc_gpio_port imx31_gpio_ports[] = {
-        DEFINE_IMX_GPIO_PORT_IRQ(MX31, 0, 1, MX31_INT_GPIO1),
-        DEFINE_IMX_GPIO_PORT_IRQ(MX31, 1, 2, MX31_INT_GPIO2),
-        DEFINE_IMX_GPIO_PORT_IRQ(MX31, 2, 3, MX31_INT_GPIO3),
-};
-
-void __init mx31_init_irq(void)
-{
-        mxc_init_irq(MX31_IO_ADDRESS(MX31_AVIC_BASE_ADDR));
-        mxc_gpio_init(imx31_gpio_ports, ARRAY_SIZE(imx31_gpio_ports));
-}
-#endif /* ifdef CONFIG_SOC_IMX31 */
-
-#ifdef CONFIG_SOC_IMX35
-static struct map_desc mx35_io_desc[] __initdata = {
-        imx_map_entry(MX35, X_MEMC, MT_DEVICE),
-        imx_map_entry(MX35, AVIC, MT_DEVICE_NONSHARED),
-        imx_map_entry(MX35, AIPS1, MT_DEVICE_NONSHARED),
-        imx_map_entry(MX35, AIPS2, MT_DEVICE_NONSHARED),
-        imx_map_entry(MX35, SPBA0, MT_DEVICE_NONSHARED),
-};
-
-void __init mx35_map_io(void)
-{
-        iotable_init(mx35_io_desc, ARRAY_SIZE(mx35_io_desc));
-}
-
-void __init imx35_init_early(void)
-{
-        mxc_set_cpu_type(MXC_CPU_MX35);
-        mxc_iomux_v3_init(MX35_IO_ADDRESS(MX35_IOMUXC_BASE_ADDR));
-        mxc_arch_reset_init(MX35_IO_ADDRESS(MX35_WDOG_BASE_ADDR));
-}
-
-static struct mxc_gpio_port imx35_gpio_ports[] = {
-        DEFINE_IMX_GPIO_PORT_IRQ(MX35, 0, 1, MX35_INT_GPIO1),
-        DEFINE_IMX_GPIO_PORT_IRQ(MX35, 1, 2, MX35_INT_GPIO2),
-        DEFINE_IMX_GPIO_PORT_IRQ(MX35, 2, 3, MX35_INT_GPIO3),
-};
-
-void __init mx35_init_irq(void)
-{
-        mxc_init_irq(MX35_IO_ADDRESS(MX35_AVIC_BASE_ADDR));
-        mxc_gpio_init(imx35_gpio_ports, ARRAY_SIZE(imx35_gpio_ports));
-}
-#endif /* ifdef CONFIG_SOC_IMX35 */
-
-#ifdef CONFIG_CACHE_L2X0
-static int mxc_init_l2x0(void)
-{
-        void __iomem *l2x0_base;
-        void __iomem *clkctl_base;
-/*
- * First of all, we must repair broken chip settings. There are some
- * i.MX35 CPUs in the wild, comming with bogus L2 cache settings. These
- * misconfigured CPUs will run amok immediately when the L2 cache gets enabled.
- * Workaraound is to setup the correct register setting prior enabling the
- * L2 cache. This should not hurt already working CPUs, as they are using the
- * same value
- */
-#define L2_MEM_VAL 0x10
-
-        clkctl_base = ioremap(MX35_CLKCTL_BASE_ADDR, 4096);
-        if (clkctl_base != NULL) {
-                writel(0x00000515, clkctl_base + L2_MEM_VAL);
-                iounmap(clkctl_base);
-        } else {
-                pr_err("L2 cache: Cannot fix timing. Trying to continue without\n");
-        }
-
-        l2x0_base = ioremap(MX3x_L2CC_BASE_ADDR, 4096);
-        if (IS_ERR(l2x0_base)) {
-                printk(KERN_ERR "remapping L2 cache area failed with %ld\n",
-                                PTR_ERR(l2x0_base));
-                return 0;
-        }
-
-        l2x0_init(l2x0_base, 0x00030024, 0x00000000);
-
-        return 0;
-}
-
-arch_initcall(mxc_init_l2x0);
-#endif
diff --git a/arch/arm/mach-mx5/Kconfig b/arch/arm/mach-mx5/Kconfig
index 159340da919..799fbc40e53 100644
--- a/arch/arm/mach-mx5/Kconfig
+++ b/arch/arm/mach-mx5/Kconfig
@@ -1,11 +1,11 @@
-if ARCH_MX5
-# ARCH_MX50/51/53 are left to mark places where prevent multi-soc in single
+if ARCH_MX503 || ARCH_MX51
+# ARCH_MX5/50/53 are left to mark places where prevent multi-soc in single
 # image. So for most time, SOC_IMX50/51/53 should be used.
 
-config ARCH_MX50
+config ARCH_MX5
         bool
 
-config ARCH_MX51
+config ARCH_MX50
         bool
 
 config ARCH_MX53
@@ -13,27 +13,54 @@ config ARCH_MX53
 
 config SOC_IMX50
         bool
+        select CPU_V7
+        select ARM_L1_CACHE_SHIFT_6
         select MXC_TZIC
         select ARCH_MXC_IOMUX_V3
         select ARCH_MXC_AUDMUX_V2
         select ARCH_HAS_CPUFREQ
+        select ARCH_MX5
         select ARCH_MX50
 
 config  SOC_IMX51
         bool
+        select CPU_V7
+        select ARM_L1_CACHE_SHIFT_6
         select MXC_TZIC
         select ARCH_MXC_IOMUX_V3
         select ARCH_MXC_AUDMUX_V2
         select ARCH_HAS_CPUFREQ
-        select ARCH_MX51
+        select ARCH_MX5
 
 config  SOC_IMX53
         bool
+        select CPU_V7
+        select ARM_L1_CACHE_SHIFT_6
         select MXC_TZIC
         select ARCH_MXC_IOMUX_V3
+        select ARCH_MX5
         select ARCH_MX53
 
-comment "MX5 platforms:"
+if ARCH_MX50_SUPPORTED
+#comment "i.MX50 machines:"
+
+config MACH_MX50_RDP
+        bool "Support MX50 reference design platform"
+        depends on BROKEN
+        select SOC_IMX50
+        select IMX_HAVE_PLATFORM_IMX_I2C
+        select IMX_HAVE_PLATFORM_IMX_UART
+        select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
+        select IMX_HAVE_PLATFORM_SPI_IMX
+        select IMX_HAVE_PLATFORM_FEC
+        help
+          Include support for MX50 reference design platform (RDP) board. This
+          includes specific configurations for the board and its peripherals.
+
+endif # ARCH_MX50_SUPPORTED
+
+if ARCH_MX51
+comment "i.MX51 machines:"
 
 config MACH_MX51_BABBAGE
         bool "Support MX51 BABBAGE platforms"
@@ -136,6 +163,11 @@ config MACH_MX51_EFIKASB
           Include support for Genesi Efika Smartbook. This includes specific
           configurations for the board and its peripherals.
 
+endif # ARCH_MX51
+
+if ARCH_MX53_SUPPORTED
+comment "i.MX53 machines:"
+
 config MACH_MX53_EVK
         bool "Support MX53 EVK platforms"
         select SOC_IMX53
@@ -154,6 +186,7 @@ config MACH_MX53_SMD
         select IMX_HAVE_PLATFORM_IMX2_WDT
         select IMX_HAVE_PLATFORM_IMX_I2C
         select IMX_HAVE_PLATFORM_IMX_UART
+        select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
         help
           Include support for MX53 SMD platform. This includes specific
           configurations for the board and its peripherals.
@@ -170,17 +203,6 @@ config MACH_MX53_LOCO
           Include support for MX53 LOCO platform. This includes specific
           configurations for the board and its peripherals.
 
-config MACH_MX50_RDP
-        bool "Support MX50 reference design platform"
-        depends on BROKEN
-        select SOC_IMX50
-        select IMX_HAVE_PLATFORM_IMX_I2C
-        select IMX_HAVE_PLATFORM_IMX_UART
-        select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
-        select IMX_HAVE_PLATFORM_SPI_IMX
-        select IMX_HAVE_PLATFORM_FEC
-        help
-          Include support for MX50 reference design platform (RDP) board. This
-          includes specific configurations for the board and its peripherals.
+endif # ARCH_MX53_SUPPORTED
 
 endif
diff --git a/arch/arm/mach-mx5/board-cpuimx51.c b/arch/arm/mach-mx5/board-cpuimx51.c
index d0296a94c47..4efa02ee163 100644
--- a/arch/arm/mach-mx5/board-cpuimx51.c
+++ b/arch/arm/mach-mx5/board-cpuimx51.c
@@ -23,13 +23,11 @@
 #include <linux/io.h>
 #include <linux/interrupt.h>
 #include <linux/irq.h>
-#include <linux/fsl_devices.h>
 
 #include <mach/eukrea-baseboards.h>
 #include <mach/common.h>
 #include <mach/hardware.h>
 #include <mach/iomux-mx51.h>
-#include <mach/mxc_ehci.h>
 
 #include <asm/irq.h>
 #include <asm/setup.h>
diff --git a/arch/arm/mach-mx5/board-cpuimx51sd.c b/arch/arm/mach-mx5/board-cpuimx51sd.c
index 29b180823bf..5ef25a59614 100644
--- a/arch/arm/mach-mx5/board-cpuimx51sd.c
+++ b/arch/arm/mach-mx5/board-cpuimx51sd.c
@@ -23,7 +23,6 @@
 #include <linux/io.h>
 #include <linux/interrupt.h>
 #include <linux/irq.h>
-#include <linux/fsl_devices.h>
 #include <linux/i2c-gpio.h>
 #include <linux/spi/spi.h>
 #include <linux/can/platform/mcp251x.h>
@@ -32,7 +31,6 @@
 #include <mach/common.h>
 #include <mach/hardware.h>
 #include <mach/iomux-mx51.h>
-#include <mach/mxc_ehci.h>
 
 #include <asm/irq.h>
 #include <asm/setup.h>
diff --git a/arch/arm/mach-mx5/board-mx50_rdp.c b/arch/arm/mach-mx5/board-mx50_rdp.c
index dedf7f2d6d0..11210e1ae42 100644
--- a/arch/arm/mach-mx5/board-mx50_rdp.c
+++ b/arch/arm/mach-mx5/board-mx50_rdp.c
@@ -23,7 +23,6 @@
 #include <linux/gpio.h>
 #include <linux/delay.h>
 #include <linux/io.h>
-#include <linux/fsl_devices.h>
 
 #include <mach/common.h>
 #include <mach/hardware.h>
diff --git a/arch/arm/mach-mx5/board-mx51_babbage.c b/arch/arm/mach-mx5/board-mx51_babbage.c
index bea4e4135f9..c7b3fabf50f 100644
--- a/arch/arm/mach-mx5/board-mx51_babbage.c
+++ b/arch/arm/mach-mx5/board-mx51_babbage.c
@@ -16,9 +16,6 @@
 #include <linux/gpio.h>
 #include <linux/delay.h>
 #include <linux/io.h>
-#include <linux/fsl_devices.h>
-#include <linux/fec.h>
-#include <linux/gpio_keys.h>
 #include <linux/input.h>
 #include <linux/spi/flash.h>
 #include <linux/spi/spi.h>
@@ -26,7 +23,6 @@
 #include <mach/common.h>
 #include <mach/hardware.h>
 #include <mach/iomux-mx51.h>
-#include <mach/mxc_ehci.h>
 
 #include <asm/irq.h>
 #include <asm/setup.h>
@@ -208,18 +204,16 @@ static inline void babbage_usbhub_reset(void)
 {
         int ret;
 
-        /* Bring USB hub out of reset */
-        ret = gpio_request(BABBAGE_USB_HUB_RESET, "GPIO1_7");
+        /* Reset USB hub */
+        ret = gpio_request_one(BABBAGE_USB_HUB_RESET,
+                                        GPIOF_OUT_INIT_LOW, "GPIO1_7");
         if (ret) {
                 printk(KERN_ERR"failed to get GPIO_USB_HUB_RESET: %d\n", ret);
                 return;
         }
-        gpio_direction_output(BABBAGE_USB_HUB_RESET, 0);
 
-        /* USB HUB RESET - De-assert USB HUB RESET_N */
-        msleep(1);
-        gpio_set_value(BABBAGE_USB_HUB_RESET, 0);
-        msleep(1);
+        msleep(2);
+        /* Deassert reset */
         gpio_set_value(BABBAGE_USB_HUB_RESET, 1);
 }
 
@@ -361,7 +355,7 @@ static void __init mx51_babbage_init(void)
 
         /* Set the PAD settings for the pwr key. */
         mxc_iomux_v3_setup_pad(power_key);
-        imx51_add_gpio_keys(&imx_button_data);
+        imx_add_gpio_keys(&imx_button_data);
 
         imx51_add_imx_i2c(0, &babbage_i2c_data);
         imx51_add_imx_i2c(1, &babbage_i2c_data);
diff --git a/arch/arm/mach-mx5/board-mx51_efikamx.c b/arch/arm/mach-mx5/board-mx51_efikamx.c
index acab1911cb3..6e362315291 100644
--- a/arch/arm/mach-mx5/board-mx51_efikamx.c
+++ b/arch/arm/mach-mx5/board-mx51_efikamx.c
@@ -22,7 +22,6 @@
 #include <linux/input.h>
 #include <linux/delay.h>
 #include <linux/io.h>
-#include <linux/fsl_devices.h>
 #include <linux/spi/flash.h>
 #include <linux/spi/spi.h>
 #include <linux/mfd/mc13892.h>
@@ -32,8 +31,6 @@
 #include <mach/common.h>
 #include <mach/hardware.h>
 #include <mach/iomux-mx51.h>
-#include <mach/i2c.h>
-#include <mach/mxc_ehci.h>
 
 #include <asm/irq.h>
 #include <asm/setup.h>
@@ -252,7 +249,7 @@ static void __init mx51_efikamx_init(void)
         }
 
         platform_device_register(&mx51_efikamx_leds_device);
-        imx51_add_gpio_keys(&mx51_efikamx_powerkey_data);
+        imx_add_gpio_keys(&mx51_efikamx_powerkey_data);
 
         if (system_rev == 0x11) {
                 gpio_request(EFIKAMX_RESET1_1, "reset");
diff --git a/arch/arm/mach-mx5/board-mx51_efikasb.c b/arch/arm/mach-mx5/board-mx51_efikasb.c
index db04ce8462d..474fc6e4c6d 100644
--- a/arch/arm/mach-mx5/board-mx51_efikasb.c
+++ b/arch/arm/mach-mx5/board-mx51_efikasb.c
@@ -22,7 +22,6 @@
 #include <linux/input.h>
 #include <linux/delay.h>
 #include <linux/io.h>
-#include <linux/fsl_devices.h>
 #include <linux/spi/flash.h>
 #include <linux/spi/spi.h>
 #include <linux/mfd/mc13892.h>
@@ -35,8 +34,6 @@
 #include <mach/common.h>
 #include <mach/hardware.h>
 #include <mach/iomux-mx51.h>
-#include <mach/i2c.h>
-#include <mach/mxc_ehci.h>
 
 #include <asm/irq.h>
 #include <asm/setup.h>
@@ -260,7 +257,7 @@ static void __init efikasb_board_init(void)
         imx51_add_sdhci_esdhc_imx(1, NULL);
 
         platform_device_register(&mx51_efikasb_leds_device);
-        imx51_add_gpio_keys(&mx51_efikasb_keys_data);
+        imx_add_gpio_keys(&mx51_efikasb_keys_data);
 
 }
 
diff --git a/arch/arm/mach-mx5/board-mx53_evk.c b/arch/arm/mach-mx5/board-mx53_evk.c
index 2af3f43f74d..f87d571882c 100644
--- a/arch/arm/mach-mx5/board-mx53_evk.c
+++ b/arch/arm/mach-mx5/board-mx53_evk.c
@@ -21,7 +21,6 @@
 
 #include <linux/init.h>
 #include <linux/clk.h>
-#include <linux/fec.h>
 #include <linux/delay.h>
 #include <linux/gpio.h>
 #include <linux/spi/flash.h>
@@ -31,7 +30,6 @@
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
-#include <mach/imx-uart.h>
 #include <mach/iomux-mx53.h>
 
 #define MX53_EVK_FEC_PHY_RST    IMX_GPIO_NR(7, 6)
diff --git a/arch/arm/mach-mx5/board-mx53_loco.c b/arch/arm/mach-mx5/board-mx53_loco.c
index 6206b1191fe..1b947e8c9c0 100644
--- a/arch/arm/mach-mx5/board-mx53_loco.c
+++ b/arch/arm/mach-mx5/board-mx53_loco.c
@@ -20,13 +20,11 @@
 
 #include <linux/init.h>
 #include <linux/clk.h>
-#include <linux/fec.h>
 #include <linux/delay.h>
 #include <linux/gpio.h>
 
 #include <mach/common.h>
 #include <mach/hardware.h>
-#include <mach/imx-uart.h>
 #include <mach/iomux-mx53.h>
 
 #include <asm/mach-types.h>
diff --git a/arch/arm/mach-mx5/board-mx53_smd.c b/arch/arm/mach-mx5/board-mx53_smd.c
index 31e173267ed..817c08938f5 100644
--- a/arch/arm/mach-mx5/board-mx53_smd.c
+++ b/arch/arm/mach-mx5/board-mx53_smd.c
@@ -20,13 +20,11 @@
 
 #include <linux/init.h>
 #include <linux/clk.h>
-#include <linux/fec.h>
 #include <linux/delay.h>
 #include <linux/gpio.h>
 
 #include <mach/common.h>
 #include <mach/hardware.h>
-#include <mach/imx-uart.h>
 #include <mach/iomux-mx53.h>
 
 #include <asm/mach-types.h>
@@ -52,6 +50,31 @@ static iomux_v3_cfg_t mx53_smd_pads[] = {
         /* I2C1 */
         MX53_PAD_CSI0_DAT8__I2C1_SDA,
         MX53_PAD_CSI0_DAT9__I2C1_SCL,
+        /* SD1 */
+        MX53_PAD_SD1_CMD__ESDHC1_CMD,
+        MX53_PAD_SD1_CLK__ESDHC1_CLK,
+        MX53_PAD_SD1_DATA0__ESDHC1_DAT0,
+        MX53_PAD_SD1_DATA1__ESDHC1_DAT1,
+        MX53_PAD_SD1_DATA2__ESDHC1_DAT2,
+        MX53_PAD_SD1_DATA3__ESDHC1_DAT3,
+        /* SD2 */
+        MX53_PAD_SD2_CMD__ESDHC2_CMD,
+        MX53_PAD_SD2_CLK__ESDHC2_CLK,
+        MX53_PAD_SD2_DATA0__ESDHC2_DAT0,
+        MX53_PAD_SD2_DATA1__ESDHC2_DAT1,
+        MX53_PAD_SD2_DATA2__ESDHC2_DAT2,
+        MX53_PAD_SD2_DATA3__ESDHC2_DAT3,
+        /* SD3 */
+        MX53_PAD_PATA_DATA8__ESDHC3_DAT0,
+        MX53_PAD_PATA_DATA9__ESDHC3_DAT1,
+        MX53_PAD_PATA_DATA10__ESDHC3_DAT2,
+        MX53_PAD_PATA_DATA11__ESDHC3_DAT3,
+        MX53_PAD_PATA_DATA0__ESDHC3_DAT4,
+        MX53_PAD_PATA_DATA1__ESDHC3_DAT5,
+        MX53_PAD_PATA_DATA2__ESDHC3_DAT6,
+        MX53_PAD_PATA_DATA3__ESDHC3_DAT7,
+        MX53_PAD_PATA_IORDY__ESDHC3_CLK,
+        MX53_PAD_PATA_RESET_B__ESDHC3_CMD,
 };
 
 static const struct imxuart_platform_data mx53_smd_uart_data __initconst = {
@@ -97,6 +120,9 @@ static void __init mx53_smd_board_init(void)
         imx53_add_fec(&mx53_smd_fec_data);
         imx53_add_imx2_wdt(0, NULL);
         imx53_add_imx_i2c(0, &mx53_smd_i2c_data);
+        imx53_add_sdhci_esdhc_imx(0, NULL);
+        imx53_add_sdhci_esdhc_imx(1, NULL);
+        imx53_add_sdhci_esdhc_imx(2, NULL);
 }
 
 static void __init mx53_smd_timer_init(void)
diff --git a/arch/arm/mach-mx5/clock-mx51-mx53.c b/arch/arm/mach-mx5/clock-mx51-mx53.c
index fdbc05ed551..6b89c1bf4eb 100644
--- a/arch/arm/mach-mx5/clock-mx51-mx53.c
+++ b/arch/arm/mach-mx5/clock-mx51-mx53.c
@@ -1563,6 +1563,7 @@ int __init mx53_clocks_init(unsigned long ckil, unsigned long osc,
         clk_enable(&iim_clk);
         mx53_revision();
         clk_disable(&iim_clk);
+        mx53_display_revision();
 
         /* Set SDHC parents to be PLL2 */
         clk_set_parent(&esdhc1_clk, &pll2_sw_clk);
diff --git a/arch/arm/mach-mx5/cpu.c b/arch/arm/mach-mx5/cpu.c
index 472bdfab2e5..86f87da59c6 100644
--- a/arch/arm/mach-mx5/cpu.c
+++ b/arch/arm/mach-mx5/cpu.c
@@ -166,6 +166,29 @@ int mx50_revision(void)
 }
 EXPORT_SYMBOL(mx50_revision);
 
+void mx53_display_revision(void)
+{
+        int rev;
+        char *srev;
+        rev = mx53_revision();
+
+        switch (rev) {
+        case IMX_CHIP_REVISION_1_0:
+                srev = IMX_CHIP_REVISION_1_0_STRING;
+                break;
+        case IMX_CHIP_REVISION_2_0:
+                srev = IMX_CHIP_REVISION_2_0_STRING;
+                break;
+        case IMX_CHIP_REVISION_2_1:
+                srev = IMX_CHIP_REVISION_2_1_STRING;
+                break;
+        default:
+                srev = IMX_CHIP_REVISION_UNKNOWN_STRING;
+        }
+        printk(KERN_INFO "CPU identified as i.MX53, silicon rev %s\n", srev);
+}
+EXPORT_SYMBOL(mx53_display_revision);
+
 static int __init post_cpu_init(void)
 {
         unsigned int reg;
diff --git a/arch/arm/mach-mx5/devices-imx50.h b/arch/arm/mach-mx5/devices-imx50.h
index c9e42823c7e..7216667eaaf 100644
--- a/arch/arm/mach-mx5/devices-imx50.h
+++ b/arch/arm/mach-mx5/devices-imx50.h
@@ -21,14 +21,14 @@
 #include <mach/mx50.h>
 #include <mach/devices-common.h>
 
-extern const struct imx_imx_uart_1irq_data imx50_imx_uart_data[] __initconst;
+extern const struct imx_imx_uart_1irq_data imx50_imx_uart_data[];
 #define imx50_add_imx_uart(id, pdata)   \
         imx_add_imx_uart_1irq(&imx50_imx_uart_data[id], pdata)
 
-extern const struct imx_fec_data imx50_fec_data __initconst;
+extern const struct imx_fec_data imx50_fec_data;
 #define imx50_add_fec(pdata)    \
         imx_add_fec(&imx50_fec_data, pdata)
 
-extern const struct imx_imx_i2c_data imx50_imx_i2c_data[] __initconst;
+extern const struct imx_imx_i2c_data imx50_imx_i2c_data[];
 #define imx50_add_imx_i2c(id, pdata)    \
         imx_add_imx_i2c(&imx50_imx_i2c_data[id], pdata)
diff --git a/arch/arm/mach-mx5/devices-imx51.h b/arch/arm/mach-mx5/devices-imx51.h
index 7fff485e560..e11bc0e0ec4 100644
--- a/arch/arm/mach-mx5/devices-imx51.h
+++ b/arch/arm/mach-mx5/devices-imx51.h
@@ -9,49 +9,46 @@
 #include <mach/mx51.h>
 #include <mach/devices-common.h>
 
-extern const struct imx_fec_data imx51_fec_data __initconst;
+extern const struct imx_fec_data imx51_fec_data;
 #define imx51_add_fec(pdata)    \
         imx_add_fec(&imx51_fec_data, pdata)
 
-#define imx51_add_gpio_keys(pdata) imx_add_gpio_keys(pdata)
-
-extern const struct imx_imx_i2c_data imx51_imx_i2c_data[] __initconst;
+extern const struct imx_imx_i2c_data imx51_imx_i2c_data[];
 #define imx51_add_imx_i2c(id, pdata)    \
         imx_add_imx_i2c(&imx51_imx_i2c_data[id], pdata)
 
-extern const struct imx_imx_ssi_data imx51_imx_ssi_data[] __initconst;
+extern const struct imx_imx_ssi_data imx51_imx_ssi_data[];
 #define imx51_add_imx_ssi(id, pdata)    \
         imx_add_imx_ssi(&imx51_imx_ssi_data[id], pdata)
 
-extern const struct imx_imx_uart_1irq_data imx51_imx_uart_data[] __initconst;
+extern const struct imx_imx_uart_1irq_data imx51_imx_uart_data[];
 #define imx51_add_imx_uart(id, pdata)   \
         imx_add_imx_uart_1irq(&imx51_imx_uart_data[id], pdata)
 
-extern const struct imx_mxc_nand_data imx51_mxc_nand_data __initconst;
+extern const struct imx_mxc_nand_data imx51_mxc_nand_data;
 #define imx51_add_mxc_nand(pdata)       \
         imx_add_mxc_nand(&imx51_mxc_nand_data, pdata)
 
-extern const struct imx_sdhci_esdhc_imx_data
-imx51_sdhci_esdhc_imx_data[] __initconst;
+extern const struct imx_sdhci_esdhc_imx_data imx51_sdhci_esdhc_imx_data[];
 #define imx51_add_sdhci_esdhc_imx(id, pdata)    \
         imx_add_sdhci_esdhc_imx(&imx51_sdhci_esdhc_imx_data[id], pdata)
 
-extern const struct imx_spi_imx_data imx51_cspi_data __initconst;
+extern const struct imx_spi_imx_data imx51_cspi_data;
 #define imx51_add_cspi(pdata)   \
         imx_add_spi_imx(&imx51_cspi_data, pdata)
 
-extern const struct imx_spi_imx_data imx51_ecspi_data[] __initconst;
+extern const struct imx_spi_imx_data imx51_ecspi_data[];
 #define imx51_add_ecspi(id, pdata)      \
         imx_add_spi_imx(&imx51_ecspi_data[id], pdata)
 
-extern const struct imx_imx2_wdt_data imx51_imx2_wdt_data[] __initconst;
+extern const struct imx_imx2_wdt_data imx51_imx2_wdt_data[];
 #define imx51_add_imx2_wdt(id, pdata)   \
         imx_add_imx2_wdt(&imx51_imx2_wdt_data[id])
 
-extern const struct imx_mxc_pwm_data imx51_mxc_pwm_data[] __initconst;
+extern const struct imx_mxc_pwm_data imx51_mxc_pwm_data[];
 #define imx51_add_mxc_pwm(id)   \
         imx_add_mxc_pwm(&imx51_mxc_pwm_data[id])
 
-extern const struct imx_imx_keypad_data imx51_imx_keypad_data __initconst;
+extern const struct imx_imx_keypad_data imx51_imx_keypad_data;
 #define imx51_add_imx_keypad(pdata)     \
         imx_add_imx_keypad(&imx51_imx_keypad_data, pdata)
diff --git a/arch/arm/mach-mx5/devices-imx53.h b/arch/arm/mach-mx5/devices-imx53.h
index 9251008dad1..48f4c8cc42f 100644
--- a/arch/arm/mach-mx5/devices-imx53.h
+++ b/arch/arm/mach-mx5/devices-imx53.h
@@ -8,28 +8,27 @@
 #include <mach/mx53.h>
 #include <mach/devices-common.h>
 
-extern const struct imx_fec_data imx53_fec_data __initconst;
+extern const struct imx_fec_data imx53_fec_data;
 #define imx53_add_fec(pdata)   \
         imx_add_fec(&imx53_fec_data, pdata)
 
-extern const struct imx_imx_uart_1irq_data imx53_imx_uart_data[] __initconst;
+extern const struct imx_imx_uart_1irq_data imx53_imx_uart_data[];
 #define imx53_add_imx_uart(id, pdata)   \
         imx_add_imx_uart_1irq(&imx53_imx_uart_data[id], pdata)
 
 
-extern const struct imx_imx_i2c_data imx53_imx_i2c_data[] __initconst;
+extern const struct imx_imx_i2c_data imx53_imx_i2c_data[];
 #define imx53_add_imx_i2c(id, pdata)    \
         imx_add_imx_i2c(&imx53_imx_i2c_data[id], pdata)
 
-extern const struct imx_sdhci_esdhc_imx_data
-imx53_sdhci_esdhc_imx_data[] __initconst;
+extern const struct imx_sdhci_esdhc_imx_data imx53_sdhci_esdhc_imx_data[];
 #define imx53_add_sdhci_esdhc_imx(id, pdata)    \
         imx_add_sdhci_esdhc_imx(&imx53_sdhci_esdhc_imx_data[id], pdata)
 
-extern const struct imx_spi_imx_data imx53_ecspi_data[] __initconst;
+extern const struct imx_spi_imx_data imx53_ecspi_data[];
 #define imx53_add_ecspi(id, pdata)      \
         imx_add_spi_imx(&imx53_ecspi_data[id], pdata)
 
-extern const struct imx_imx2_wdt_data imx53_imx2_wdt_data[] __initconst;
+extern const struct imx_imx2_wdt_data imx53_imx2_wdt_data[];
 #define imx53_add_imx2_wdt(id, pdata)   \
         imx_add_imx2_wdt(&imx53_imx2_wdt_data[id])
diff --git a/arch/arm/mach-mx5/eukrea_mbimx51-baseboard.c b/arch/arm/mach-mx5/eukrea_mbimx51-baseboard.c
index 4a8550529b0..97292d20f1f 100644
--- a/arch/arm/mach-mx5/eukrea_mbimx51-baseboard.c
+++ b/arch/arm/mach-mx5/eukrea_mbimx51-baseboard.c
@@ -18,13 +18,11 @@
 #include <linux/io.h>
 #include <linux/interrupt.h>
 #include <linux/irq.h>
-#include <linux/fsl_devices.h>
 #include <linux/i2c/tsc2007.h>
 #include <linux/leds.h>
 
 #include <mach/common.h>
 #include <mach/hardware.h>
-#include <mach/imx-uart.h>
 #include <mach/iomux-mx51.h>
 
 #include <asm/mach/arch.h>
diff --git a/arch/arm/mach-mx5/eukrea_mbimxsd-baseboard.c b/arch/arm/mach-mx5/eukrea_mbimxsd-baseboard.c
index e6c1119c20a..31c871ec46a 100644
--- a/arch/arm/mach-mx5/eukrea_mbimxsd-baseboard.c
+++ b/arch/arm/mach-mx5/eukrea_mbimxsd-baseboard.c
@@ -27,7 +27,6 @@
 #include <linux/irq.h>
 #include <linux/leds.h>
 #include <linux/platform_device.h>
-#include <linux/gpio_keys.h>
 #include <linux/input.h>
 #include <linux/i2c.h>
 
@@ -38,7 +37,6 @@
 
 #include <mach/hardware.h>
 #include <mach/common.h>
-#include <mach/imx-uart.h>
 #include <mach/iomux-mx51.h>
 #include <mach/audmux.h>
 
@@ -108,23 +106,14 @@ static struct gpio_keys_button eukrea_mbimxsd_gpio_buttons[] = {
         },
 };
 
-static struct gpio_keys_platform_data eukrea_mbimxsd_button_data = {
+static const struct gpio_keys_platform_data
+                eukrea_mbimxsd_button_data __initconst = {
         .buttons        = eukrea_mbimxsd_gpio_buttons,
         .nbuttons       = ARRAY_SIZE(eukrea_mbimxsd_gpio_buttons),
 };
 
-static struct platform_device eukrea_mbimxsd_button_device = {
-        .name           = "gpio-keys",
-        .id             = -1,
-        .num_resources  = 0,
-        .dev            = {
-                .platform_data  = &eukrea_mbimxsd_button_data,
-        }
-};
-
 static struct platform_device *platform_devices[] __initdata = {
         &eukrea_mbimxsd_leds_gpio,
-        &eukrea_mbimxsd_button_device,
 };
 
 static const struct imxuart_platform_data uart_pdata __initconst = {
@@ -166,4 +155,5 @@ void __init eukrea_mbimxsd51_baseboard_init(void)
                                 ARRAY_SIZE(eukrea_mbimxsd_i2c_devices));
 
         platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
+        imx_add_gpio_keys(&eukrea_mbimxsd_button_data);
 }
diff --git a/arch/arm/mach-mx5/mx51_efika.c b/arch/arm/mach-mx5/mx51_efika.c
index d0c7075937c..56739c23aca 100644
--- a/arch/arm/mach-mx5/mx51_efika.c
+++ b/arch/arm/mach-mx5/mx51_efika.c
@@ -20,7 +20,6 @@
 #include <linux/input.h>
 #include <linux/delay.h>
 #include <linux/io.h>
-#include <linux/fsl_devices.h>
 #include <linux/spi/flash.h>
 #include <linux/spi/spi.h>
 #include <linux/mfd/mc13892.h>
@@ -30,8 +29,6 @@
 #include <mach/common.h>
 #include <mach/hardware.h>
 #include <mach/iomux-mx51.h>
-#include <mach/i2c.h>
-#include <mach/mxc_ehci.h>
 
 #include <linux/usb/otg.h>
 #include <linux/usb/ulpi.h>
diff --git a/arch/arm/mach-mxc91231/Kconfig b/arch/arm/mach-mxc91231/Kconfig
deleted file mode 100644
index 8e5fa38ebb6..00000000000
--- a/arch/arm/mach-mxc91231/Kconfig
+++ /dev/null
@@ -1,11 +0,0 @@
-if ARCH_MXC91231
-
-comment "MXC91231 platforms:"
-
-config MACH_MAGX_ZN5
-        bool "Support Motorola Zn5 GSM phone"
-        default n
-        help
-          Include support for Motorola Zn5 GSM phone.
-
-endif
diff --git a/arch/arm/mach-mxc91231/Makefile b/arch/arm/mach-mxc91231/Makefile
deleted file mode 100644
index 011d5e19712..00000000000
--- a/arch/arm/mach-mxc91231/Makefile
+++ /dev/null
@@ -1,2 +0,0 @@
-obj-y   := mm.o clock.o devices.o system.o iomux.o
-obj-$(CONFIG_MACH_MAGX_ZN5) += magx-zn5.o
diff --git a/arch/arm/mach-mxc91231/Makefile.boot b/arch/arm/mach-mxc91231/Makefile.boot
deleted file mode 100644
index 9939a19d99a..00000000000
--- a/arch/arm/mach-mxc91231/Makefile.boot
+++ /dev/null
@@ -1,3 +0,0 @@
-   zreladdr-y   := 0x90008000
-params_phys-y   := 0x90000100
-initrd_phys-y   := 0x90800000
diff --git a/arch/arm/mach-mxc91231/clock.c b/arch/arm/mach-mxc91231/clock.c
deleted file mode 100644
index 9fab505f1eb..00000000000
--- a/arch/arm/mach-mxc91231/clock.c
+++ /dev/null
@@ -1,640 +0,0 @@
-#include <linux/clk.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/io.h>
-#include <linux/clkdev.h>
-
-#include <mach/clock.h>
-#include <mach/hardware.h>
-#include <mach/common.h>
-
-#include <asm/bug.h>
-#include <asm/div64.h>
-
-#include "crm_regs.h"
-
-#define CRM_SMALL_DIVIDER(base, name) \
-        crm_small_divider(base, \
-                          base ## _ ## name ## _OFFSET, \
-                          base ## _ ## name ## _MASK)
-#define CRM_1DIVIDER(base, name) \
-        crm_divider(base, \
-                    base ## _ ## name ## _OFFSET, \
-                    base ## _ ## name ## _MASK, 1)
-#define CRM_16DIVIDER(base, name) \
-        crm_divider(base, \
-                    base ## _ ## name ## _OFFSET, \
-                    base ## _ ## name ## _MASK, 16)
-
-static u32 crm_small_divider(void __iomem *reg, u8 offset, u32 mask)
-{
-        static const u32 crm_small_dividers[] = {
-                2, 3, 4, 5, 6, 8, 10, 12
-        };
-        u8 idx;
-
-        idx = (__raw_readl(reg) & mask) >> offset;
-        if (idx > 7)
-                return 1;
-
-        return crm_small_dividers[idx];
-}
-
-static u32 crm_divider(void __iomem *reg, u8 offset, u32 mask, u32 z)
-{
-        u32 div;
-        div = (__raw_readl(reg) & mask) >> offset;
-        return div ? div : z;
-}
-
-static int _clk_1bit_enable(struct clk *clk)
-{
-        u32 reg;
-
-        reg = __raw_readl(clk->enable_reg);
-        reg |= 1 << clk->enable_shift;
-        __raw_writel(reg, clk->enable_reg);
-
-        return 0;
-}
-
-static void _clk_1bit_disable(struct clk *clk)
-{
-        u32 reg;
-
-        reg = __raw_readl(clk->enable_reg);
-        reg &= ~(1 << clk->enable_shift);
-        __raw_writel(reg, clk->enable_reg);
-}
-
-static int _clk_3bit_enable(struct clk *clk)
-{
-        u32 reg;
-
-        reg = __raw_readl(clk->enable_reg);
-        reg |= 0x7 << clk->enable_shift;
-        __raw_writel(reg, clk->enable_reg);
-
-        return 0;
-}
-
-static void _clk_3bit_disable(struct clk *clk)
-{
-        u32 reg;
-
-        reg = __raw_readl(clk->enable_reg);
-        reg &= ~(0x7 << clk->enable_shift);
-        __raw_writel(reg, clk->enable_reg);
-}
-
-static unsigned long ckih_rate;
-
-static unsigned long clk_ckih_get_rate(struct clk *clk)
-{
-        return ckih_rate;
-}
-
-static struct clk ckih_clk = {
-        .get_rate = clk_ckih_get_rate,
-};
-
-static unsigned long clk_ckih_x2_get_rate(struct clk *clk)
-{
-        return 2 * clk_get_rate(clk->parent);
-}
-
-static struct clk ckih_x2_clk = {
-        .parent = &ckih_clk,
-        .get_rate = clk_ckih_x2_get_rate,
-};
-
-static unsigned long clk_ckil_get_rate(struct clk *clk)
-{
-        return CKIL_CLK_FREQ;
-}
-
-static struct clk ckil_clk = {
-        .get_rate = clk_ckil_get_rate,
-};
-
-/* plls stuff */
-static struct clk mcu_pll_clk;
-static struct clk dsp_pll_clk;
-static struct clk usb_pll_clk;
-
-static struct clk *pll_clk(u8 sel)
-{
-        switch (sel) {
-        case 0:
-                return &mcu_pll_clk;
-        case 1:
-                return &dsp_pll_clk;
-        case 2:
-                return &usb_pll_clk;
-        }
-        BUG();
-}
-
-static void __iomem *pll_base(struct clk *clk)
-{
-        if (clk == &mcu_pll_clk)
-                return MXC_PLL0_BASE;
-        else if (clk == &dsp_pll_clk)
-                return MXC_PLL1_BASE;
-        else if (clk == &usb_pll_clk)
-                return MXC_PLL2_BASE;
-        BUG();
-}
-
-static unsigned long clk_pll_get_rate(struct clk *clk)
-{
-        const void __iomem *pllbase;
-        unsigned long dp_op, dp_mfd, dp_mfn, pll_hfsm, ref_clk, mfi;
-        long mfn, mfn_abs, mfd, pdf;
-        s64 temp;
-        pllbase = pll_base(clk);
-
-        pll_hfsm = __raw_readl(pllbase + MXC_PLL_DP_CTL) & MXC_PLL_DP_CTL_HFSM;
-        if (pll_hfsm == 0) {
-                dp_op = __raw_readl(pllbase + MXC_PLL_DP_OP);
-                dp_mfd = __raw_readl(pllbase + MXC_PLL_DP_MFD);
-                dp_mfn = __raw_readl(pllbase + MXC_PLL_DP_MFN);
-        } else {
-                dp_op = __raw_readl(pllbase + MXC_PLL_DP_HFS_OP);
-                dp_mfd = __raw_readl(pllbase + MXC_PLL_DP_HFS_MFD);
-                dp_mfn = __raw_readl(pllbase + MXC_PLL_DP_HFS_MFN);
-        }
-
-        pdf = dp_op & MXC_PLL_DP_OP_PDF_MASK;
-        mfi = (dp_op >> MXC_PLL_DP_OP_MFI_OFFSET) & MXC_PLL_DP_OP_PDF_MASK;
-        mfi = (mfi <= 5) ? 5 : mfi;
-        mfd = dp_mfd & MXC_PLL_DP_MFD_MASK;
-        mfn = dp_mfn & MXC_PLL_DP_MFN_MASK;
-        mfn = (mfn <= 0x4000000) ? mfn : (mfn - 0x10000000);
-
-        if (mfn < 0)
-                mfn_abs = -mfn;
-        else
-                mfn_abs = mfn;
-
-/* XXX: actually this asumes that ckih is fed to pll, but spec says
- * that ckih_x2 is also possible. need to check this out.
- */
-        ref_clk = clk_get_rate(&ckih_clk);
-
-        ref_clk *= 2;
-        ref_clk /= pdf + 1;
-
-        temp = (u64) ref_clk * mfn_abs;
-        do_div(temp, mfd);
-        if (mfn < 0)
-                temp = -temp;
-        temp += ref_clk * mfi;
-
-        return temp;
-}
-
-static int clk_pll_enable(struct clk *clk)
-{
-        void __iomem *ctl;
-        u32 reg;
-
-        ctl = pll_base(clk);
-        reg = __raw_readl(ctl);
-        reg |= (MXC_PLL_DP_CTL_RST | MXC_PLL_DP_CTL_UPEN);
-        __raw_writel(reg, ctl);
-        do {
-                reg = __raw_readl(ctl);
-        } while ((reg & MXC_PLL_DP_CTL_LRF) != MXC_PLL_DP_CTL_LRF);
-        return 0;
-}
-
-static void clk_pll_disable(struct clk *clk)
-{
-        void __iomem *ctl;
-        u32 reg;
-
-        ctl = pll_base(clk);
-        reg = __raw_readl(ctl);
-        reg &= ~(MXC_PLL_DP_CTL_RST | MXC_PLL_DP_CTL_UPEN);
-        __raw_writel(reg, ctl);
-}
-
-static struct clk mcu_pll_clk = {
-        .parent = &ckih_clk,
-        .get_rate = clk_pll_get_rate,
-        .enable = clk_pll_enable,
-        .disable = clk_pll_disable,
-};
-
-static struct clk dsp_pll_clk = {
-        .parent = &ckih_clk,
-        .get_rate = clk_pll_get_rate,
-        .enable = clk_pll_enable,
-        .disable = clk_pll_disable,
-};
-
-static struct clk usb_pll_clk = {
-        .parent = &ckih_clk,
-        .get_rate = clk_pll_get_rate,
-        .enable = clk_pll_enable,
-        .disable = clk_pll_disable,
-};
-/* plls stuff end */
-
-/* ap_ref_clk stuff */
-static struct clk ap_ref_clk;
-
-static unsigned long clk_ap_ref_get_rate(struct clk *clk)
-{
-        u32 ascsr, acsr;
-        u8 ap_pat_ref_div_2, ap_isel, acs, ads;
-
-        ascsr = __raw_readl(MXC_CRMAP_ASCSR);
-        acsr = __raw_readl(MXC_CRMAP_ACSR);
-
-        /* 0 for ckih, 1 for ckih*2 */
-        ap_isel = ascsr & MXC_CRMAP_ASCSR_APISEL;
-        /* reg divider */
-        ap_pat_ref_div_2 = (ascsr >> MXC_CRMAP_ASCSR_AP_PATDIV2_OFFSET) & 0x1;
-        /* undocumented, 1 for disabling divider */
-        ads = (acsr >> MXC_CRMAP_ACSR_ADS_OFFSET) & 0x1;
-        /* 0 for pat_ref, 1 for divider out */
-        acs = acsr & MXC_CRMAP_ACSR_ACS;
-
-        if (acs & !ads)
-                /* use divided clock */
-                return clk_get_rate(clk->parent) / (ap_pat_ref_div_2 ? 2 : 1);
-
-        return clk_get_rate(clk->parent) * (ap_isel ? 2 : 1);
-}
-
-static struct clk ap_ref_clk = {
-        .parent = &ckih_clk,
-        .get_rate = clk_ap_ref_get_rate,
-};
-/* ap_ref_clk stuff end */
-
-/* ap_pre_dfs_clk stuff */
-static struct clk ap_pre_dfs_clk;
-
-static unsigned long clk_ap_pre_dfs_get_rate(struct clk *clk)
-{
-        u32 acsr, ascsr;
-
-        acsr = __raw_readl(MXC_CRMAP_ACSR);
-        ascsr = __raw_readl(MXC_CRMAP_ASCSR);
-
-        if (acsr & MXC_CRMAP_ACSR_ACS) {
-                u8 sel;
-                sel = (ascsr & MXC_CRMAP_ASCSR_APSEL_MASK) >>
-                        MXC_CRMAP_ASCSR_APSEL_OFFSET;
-                return clk_get_rate(pll_clk(sel)) /
-                        CRM_SMALL_DIVIDER(MXC_CRMAP_ACDR, ARMDIV);
-        }
-        return clk_get_rate(&ap_ref_clk);
-}
-
-static struct clk ap_pre_dfs_clk = {
-        .get_rate = clk_ap_pre_dfs_get_rate,
-};
-/* ap_pre_dfs_clk stuff end */
-
-/* usb_clk stuff */
-static struct clk usb_clk;
-
-static struct clk *clk_usb_parent(struct clk *clk)
-{
-        u32 acsr, ascsr;
-
-        acsr = __raw_readl(MXC_CRMAP_ACSR);
-        ascsr = __raw_readl(MXC_CRMAP_ASCSR);
-
-        if (acsr & MXC_CRMAP_ACSR_ACS) {
-                u8 sel;
-                sel = (ascsr & MXC_CRMAP_ASCSR_USBSEL_MASK) >>
-                        MXC_CRMAP_ASCSR_USBSEL_OFFSET;
-                return pll_clk(sel);
-        }
-        return &ap_ref_clk;
-}
-
-static unsigned long clk_usb_get_rate(struct clk *clk)
-{
-        return clk_get_rate(clk->parent) /
-                CRM_SMALL_DIVIDER(MXC_CRMAP_ACDER2, USBDIV);
-}
-
-static struct clk usb_clk = {
-        .enable_reg = MXC_CRMAP_ACDER2,
-        .enable_shift = MXC_CRMAP_ACDER2_USBEN_OFFSET,
-        .get_rate = clk_usb_get_rate,
-        .enable = _clk_1bit_enable,
-        .disable = _clk_1bit_disable,
-};
-/* usb_clk stuff end */
-
-static unsigned long clk_ipg_get_rate(struct clk *clk)
-{
-        return clk_get_rate(clk->parent) / CRM_16DIVIDER(MXC_CRMAP_ACDR, IPDIV);
-}
-
-static unsigned long clk_ahb_get_rate(struct clk *clk)
-{
-        return clk_get_rate(clk->parent) /
-                CRM_16DIVIDER(MXC_CRMAP_ACDR, AHBDIV);
-}
-
-static struct clk ipg_clk = {
-        .parent = &ap_pre_dfs_clk,
-        .get_rate = clk_ipg_get_rate,
-};
-
-static struct clk ahb_clk = {
-        .parent = &ap_pre_dfs_clk,
-        .get_rate = clk_ahb_get_rate,
-};
-
-/* perclk_clk stuff */
-static struct clk perclk_clk;
-
-static unsigned long clk_perclk_get_rate(struct clk *clk)
-{
-        u32 acder2;
-
-        acder2 = __raw_readl(MXC_CRMAP_ACDER2);
-        if (acder2 & MXC_CRMAP_ACDER2_BAUD_ISEL_MASK)
-                return 2 * clk_get_rate(clk->parent);
-
-        return clk_get_rate(clk->parent);
-}
-
-static struct clk perclk_clk = {
-        .parent = &ckih_clk,
-        .get_rate = clk_perclk_get_rate,
-};
-/* perclk_clk stuff end */
-
-/* uart_clk stuff */
-static struct clk uart_clk[];
-
-static unsigned long clk_uart_get_rate(struct clk *clk)
-{
-        u32 div;
-
-        switch (clk->id) {
-        case 0:
-        case 1:
-                div = CRM_SMALL_DIVIDER(MXC_CRMAP_ACDER2, BAUDDIV);
-                break;
-        case 2:
-                div = CRM_SMALL_DIVIDER(MXC_CRMAP_APRA, UART3DIV);
-                break;
-        default:
-                BUG();
-        }
-        return clk_get_rate(clk->parent) / div;
-}
-
-static struct clk uart_clk[] = {
-        {
-                .id = 0,
-                .parent = &perclk_clk,
-                .enable_reg = MXC_CRMAP_APRA,
-                .enable_shift = MXC_CRMAP_APRA_UART1EN_OFFSET,
-                .get_rate = clk_uart_get_rate,
-                .enable = _clk_1bit_enable,
-                .disable = _clk_1bit_disable,
-        }, {
-                .id = 1,
-                .parent = &perclk_clk,
-                .enable_reg = MXC_CRMAP_APRA,
-                .enable_shift = MXC_CRMAP_APRA_UART2EN_OFFSET,
-                .get_rate = clk_uart_get_rate,
-                .enable = _clk_1bit_enable,
-                .disable = _clk_1bit_disable,
-        }, {
-                .id = 2,
-                .parent = &perclk_clk,
-                .enable_reg = MXC_CRMAP_APRA,
-                .enable_shift = MXC_CRMAP_APRA_UART3EN_OFFSET,
-                .get_rate = clk_uart_get_rate,
-                .enable = _clk_1bit_enable,
-                .disable = _clk_1bit_disable,
-        },
-};
-/* uart_clk stuff end */
-
-/* sdhc_clk stuff */
-static struct clk nfc_clk;
-
-static unsigned long clk_nfc_get_rate(struct clk *clk)
-{
-        return clk_get_rate(clk->parent) /
-                CRM_1DIVIDER(MXC_CRMAP_ACDER2, NFCDIV);
-}
-
-static struct clk nfc_clk = {
-        .parent = &ahb_clk,
-        .enable_reg = MXC_CRMAP_ACDER2,
-        .enable_shift = MXC_CRMAP_ACDER2_NFCEN_OFFSET,
-        .get_rate = clk_nfc_get_rate,
-        .enable = _clk_1bit_enable,
-        .disable = _clk_1bit_disable,
-};
-/* sdhc_clk stuff end */
-
-/* sdhc_clk stuff */
-static struct clk sdhc_clk[];
-
-static struct clk *clk_sdhc_parent(struct clk *clk)
-{
-        u32 aprb;
-        u8 sel;
-        u32 mask;
-        int offset;
-
-        aprb = __raw_readl(MXC_CRMAP_APRB);
-
-        switch (clk->id) {
-        case 0:
-                mask = MXC_CRMAP_APRB_SDHC1_ISEL_MASK;
-                offset = MXC_CRMAP_APRB_SDHC1_ISEL_OFFSET;
-                break;
-        case 1:
-                mask = MXC_CRMAP_APRB_SDHC2_ISEL_MASK;
-                offset = MXC_CRMAP_APRB_SDHC2_ISEL_OFFSET;
-                break;
-        default:
-                BUG();
-        }
-        sel = (aprb & mask) >> offset;
-
-        switch (sel) {
-        case 0:
-                return &ckih_clk;
-        case 1:
-                return &ckih_x2_clk;
-        }
-        return &usb_clk;
-}
-
-static unsigned long clk_sdhc_get_rate(struct clk *clk)
-{
-        u32 div;
-
-        switch (clk->id) {
-        case 0:
-                div = CRM_SMALL_DIVIDER(MXC_CRMAP_APRB, SDHC1_DIV);
-                break;
-        case 1:
-                div = CRM_SMALL_DIVIDER(MXC_CRMAP_APRB, SDHC2_DIV);
-                break;
-        default:
-                BUG();
-        }
-
-        return clk_get_rate(clk->parent) / div;
-}
-
-static int clk_sdhc_enable(struct clk *clk)
-{
-        u32 amlpmre1, aprb;
-
-        amlpmre1 = __raw_readl(MXC_CRMAP_AMLPMRE1);
-        aprb = __raw_readl(MXC_CRMAP_APRB);
-        switch (clk->id) {
-        case 0:
-                amlpmre1 |= (0x7 << MXC_CRMAP_AMLPMRE1_MLPME4_OFFSET);
-                aprb |= (0x1 << MXC_CRMAP_APRB_SDHC1EN_OFFSET);
-                break;
-        case 1:
-                amlpmre1 |= (0x7 << MXC_CRMAP_AMLPMRE1_MLPME5_OFFSET);
-                aprb |= (0x1 << MXC_CRMAP_APRB_SDHC2EN_OFFSET);
-                break;
-        }
-        __raw_writel(amlpmre1, MXC_CRMAP_AMLPMRE1);
-        __raw_writel(aprb, MXC_CRMAP_APRB);
-        return 0;
-}
-
-static void clk_sdhc_disable(struct clk *clk)
-{
-        u32 amlpmre1, aprb;
-
-        amlpmre1 = __raw_readl(MXC_CRMAP_AMLPMRE1);
-        aprb = __raw_readl(MXC_CRMAP_APRB);
-        switch (clk->id) {
-        case 0:
-                amlpmre1 &= ~(0x7 << MXC_CRMAP_AMLPMRE1_MLPME4_OFFSET);
-                aprb &= ~(0x1 << MXC_CRMAP_APRB_SDHC1EN_OFFSET);
-                break;
-        case 1:
-                amlpmre1 &= ~(0x7 << MXC_CRMAP_AMLPMRE1_MLPME5_OFFSET);
-                aprb &= ~(0x1 << MXC_CRMAP_APRB_SDHC2EN_OFFSET);
-                break;
-        }
-        __raw_writel(amlpmre1, MXC_CRMAP_AMLPMRE1);
-        __raw_writel(aprb, MXC_CRMAP_APRB);
-}
-
-static struct clk sdhc_clk[] = {
-        {
-                .id = 0,
-                .get_rate = clk_sdhc_get_rate,
-                .enable = clk_sdhc_enable,
-                .disable = clk_sdhc_disable,
-        }, {
-                .id = 1,
-                .get_rate = clk_sdhc_get_rate,
-                .enable = clk_sdhc_enable,
-                .disable = clk_sdhc_disable,
-        },
-};
-/* sdhc_clk stuff end */
-
-/* wdog_clk stuff */
-static struct clk wdog_clk[] = {
-        {
-                .id = 0,
-                .parent = &ipg_clk,
-                .enable_reg = MXC_CRMAP_AMLPMRD,
-                .enable_shift = MXC_CRMAP_AMLPMRD_MLPMD7_OFFSET,
-                .enable = _clk_3bit_enable,
-                .disable = _clk_3bit_disable,
-        }, {
-                .id = 1,
-                .parent = &ipg_clk,
-                .enable_reg = MXC_CRMAP_AMLPMRD,
-                .enable_shift = MXC_CRMAP_AMLPMRD_MLPMD3_OFFSET,
-                .enable = _clk_3bit_enable,
-                .disable = _clk_3bit_disable,
-        },
-};
-/* wdog_clk stuff end */
-
-/* gpt_clk stuff */
-static struct clk gpt_clk = {
-        .parent = &ipg_clk,
-        .enable_reg = MXC_CRMAP_AMLPMRC,
-        .enable_shift = MXC_CRMAP_AMLPMRC_MLPMC4_OFFSET,
-        .enable = _clk_3bit_enable,
-        .disable = _clk_3bit_disable,
-};
-/* gpt_clk stuff end */
-
-/* cspi_clk stuff */
-static struct clk cspi_clk[] = {
-        {
-                .id = 0,
-                .parent = &ipg_clk,
-                .enable_reg = MXC_CRMAP_AMLPMRE2,
-                .enable_shift = MXC_CRMAP_AMLPMRE2_MLPME0_OFFSET,
-                .enable = _clk_3bit_enable,
-                .disable = _clk_3bit_disable,
-        }, {
-                .id = 1,
-                .parent = &ipg_clk,
-                .enable_reg = MXC_CRMAP_AMLPMRE1,
-                .enable_shift = MXC_CRMAP_AMLPMRE1_MLPME6_OFFSET,
-                .enable = _clk_3bit_enable,
-                .disable = _clk_3bit_disable,
-        },
-};
-/* cspi_clk stuff end */
-
-#define _REGISTER_CLOCK(d, n, c) \
-        { \
-                .dev_id = d, \
-                .con_id = n, \
-                .clk = &c, \
-        },
-
-static struct clk_lookup lookups[] = {
-        _REGISTER_CLOCK("imx-uart.0", NULL, uart_clk[0])
-        _REGISTER_CLOCK("imx-uart.1", NULL, uart_clk[1])
-        _REGISTER_CLOCK("imx-uart.2", NULL, uart_clk[2])
-        _REGISTER_CLOCK("mxc-mmc.0", NULL, sdhc_clk[0])
-        _REGISTER_CLOCK("mxc-mmc.1", NULL, sdhc_clk[1])
-        _REGISTER_CLOCK("mxc-wdt.0", NULL, wdog_clk[0])
-        _REGISTER_CLOCK("spi_imx.0", NULL, cspi_clk[0])
-        _REGISTER_CLOCK("spi_imx.1", NULL, cspi_clk[1])
-};
-
-int __init mxc91231_clocks_init(unsigned long fref)
-{
-        void __iomem *gpt_base;
-
-        ckih_rate = fref;
-
-        usb_clk.parent = clk_usb_parent(&usb_clk);
-        sdhc_clk[0].parent = clk_sdhc_parent(&sdhc_clk[0]);
-        sdhc_clk[1].parent = clk_sdhc_parent(&sdhc_clk[1]);
-
-        clkdev_add_table(lookups, ARRAY_SIZE(lookups));
-
-        gpt_base = MXC91231_IO_ADDRESS(MXC91231_GPT1_BASE_ADDR);
-        mxc_timer_init(&gpt_clk, gpt_base, MXC91231_INT_GPT);
-
-        return 0;
-}
diff --git a/arch/arm/mach-mxc91231/crm_regs.h b/arch/arm/mach-mxc91231/crm_regs.h
deleted file mode 100644
index b989baccd67..00000000000
--- a/arch/arm/mach-mxc91231/crm_regs.h
+++ /dev/null
@@ -1,394 +0,0 @@
-/*
- * Copyright 2006 Freescale Semiconductor, Inc.
- * Copyright 2006-2007 Motorola, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#ifndef _ARCH_ARM_MACH_MXC91231_CRM_REGS_H_
-#define _ARCH_ARM_MACH_MXC91231_CRM_REGS_H_
-
-#define CKIL_CLK_FREQ                   32768
-
-#define MXC_CRM_AP_BASE                 MXC91231_IO_ADDRESS(MXC91231_CRM_AP_BASE_ADDR)
-#define MXC_CRM_COM_BASE                MXC91231_IO_ADDRESS(MXC91231_CRM_COM_BASE_ADDR)
-#define MXC_DSM_BASE                    MXC91231_IO_ADDRESS(MXC91231_DSM_BASE_ADDR)
-#define MXC_PLL0_BASE                   MXC91231_IO_ADDRESS(MXC91231_PLL0_BASE_ADDR)
-#define MXC_PLL1_BASE                   MXC91231_IO_ADDRESS(MXC91231_PLL1_BASE_ADDR)
-#define MXC_PLL2_BASE                   MXC91231_IO_ADDRESS(MXC91231_PLL2_BASE_ADDR)
-#define MXC_CLKCTL_BASE                 MXC91231_IO_ADDRESS(MXC91231_CLKCTL_BASE_ADDR)
-
-/* PLL Register Offsets */
-#define MXC_PLL_DP_CTL                  0x00
-#define MXC_PLL_DP_CONFIG               0x04
-#define MXC_PLL_DP_OP                   0x08
-#define MXC_PLL_DP_MFD                  0x0C
-#define MXC_PLL_DP_MFN                  0x10
-#define MXC_PLL_DP_HFS_OP               0x1C
-#define MXC_PLL_DP_HFS_MFD              0x20
-#define MXC_PLL_DP_HFS_MFN              0x24
-
-/* PLL Register Bit definitions */
-#define MXC_PLL_DP_CTL_DPDCK0_2_EN      0x1000
-#define MXC_PLL_DP_CTL_ADE              0x800
-#define MXC_PLL_DP_CTL_REF_CLK_DIV      0x400
-#define MXC_PLL_DP_CTL_HFSM             0x80
-#define MXC_PLL_DP_CTL_PRE              0x40
-#define MXC_PLL_DP_CTL_UPEN             0x20
-#define MXC_PLL_DP_CTL_RST              0x10
-#define MXC_PLL_DP_CTL_RCP              0x8
-#define MXC_PLL_DP_CTL_PLM              0x4
-#define MXC_PLL_DP_CTL_BRM0             0x2
-#define MXC_PLL_DP_CTL_LRF              0x1
-
-#define MXC_PLL_DP_OP_MFI_OFFSET        4
-#define MXC_PLL_DP_OP_MFI_MASK          0xF
-#define MXC_PLL_DP_OP_PDF_OFFSET        0
-#define MXC_PLL_DP_OP_PDF_MASK          0xF
-
-#define MXC_PLL_DP_MFD_OFFSET           0
-#define MXC_PLL_DP_MFD_MASK             0x7FFFFFF
-
-#define MXC_PLL_DP_MFN_OFFSET           0
-#define MXC_PLL_DP_MFN_MASK             0x7FFFFFF
-
-/* CRM AP Register Offsets */
-#define MXC_CRMAP_ASCSR                 (MXC_CRM_AP_BASE + 0x00)
-#define MXC_CRMAP_ACDR                  (MXC_CRM_AP_BASE + 0x04)
-#define MXC_CRMAP_ACDER1                (MXC_CRM_AP_BASE + 0x08)
-#define MXC_CRMAP_ACDER2                (MXC_CRM_AP_BASE + 0x0C)
-#define MXC_CRMAP_ACGCR                 (MXC_CRM_AP_BASE + 0x10)
-#define MXC_CRMAP_ACCGCR                (MXC_CRM_AP_BASE + 0x14)
-#define MXC_CRMAP_AMLPMRA               (MXC_CRM_AP_BASE + 0x18)
-#define MXC_CRMAP_AMLPMRB               (MXC_CRM_AP_BASE + 0x1C)
-#define MXC_CRMAP_AMLPMRC               (MXC_CRM_AP_BASE + 0x20)
-#define MXC_CRMAP_AMLPMRD               (MXC_CRM_AP_BASE + 0x24)
-#define MXC_CRMAP_AMLPMRE1              (MXC_CRM_AP_BASE + 0x28)
-#define MXC_CRMAP_AMLPMRE2              (MXC_CRM_AP_BASE + 0x2C)
-#define MXC_CRMAP_AMLPMRF               (MXC_CRM_AP_BASE + 0x30)
-#define MXC_CRMAP_AMLPMRG               (MXC_CRM_AP_BASE + 0x34)
-#define MXC_CRMAP_APGCR                 (MXC_CRM_AP_BASE + 0x38)
-#define MXC_CRMAP_ACSR                  (MXC_CRM_AP_BASE + 0x3C)
-#define MXC_CRMAP_ADCR                  (MXC_CRM_AP_BASE + 0x40)
-#define MXC_CRMAP_ACR                   (MXC_CRM_AP_BASE + 0x44)
-#define MXC_CRMAP_AMCR                  (MXC_CRM_AP_BASE + 0x48)
-#define MXC_CRMAP_APCR                  (MXC_CRM_AP_BASE + 0x4C)
-#define MXC_CRMAP_AMORA                 (MXC_CRM_AP_BASE + 0x50)
-#define MXC_CRMAP_AMORB                 (MXC_CRM_AP_BASE + 0x54)
-#define MXC_CRMAP_AGPR                  (MXC_CRM_AP_BASE + 0x58)
-#define MXC_CRMAP_APRA                  (MXC_CRM_AP_BASE + 0x5C)
-#define MXC_CRMAP_APRB                  (MXC_CRM_AP_BASE + 0x60)
-#define MXC_CRMAP_APOR                  (MXC_CRM_AP_BASE + 0x64)
-#define MXC_CRMAP_ADFMR                 (MXC_CRM_AP_BASE + 0x68)
-
-/* CRM AP Register Bit definitions */
-#define MXC_CRMAP_ASCSR_CRS                     0x10000
-#define MXC_CRMAP_ASCSR_AP_PATDIV2_OFFSET       15
-#define MXC_CRMAP_ASCSR_AP_PATREF_DIV2          0x8000
-#define MXC_CRMAP_ASCSR_USBSEL_OFFSET           13
-#define MXC_CRMAP_ASCSR_USBSEL_MASK             (0x3 << 13)
-#define MXC_CRMAP_ASCSR_CSISEL_OFFSET           11
-#define MXC_CRMAP_ASCSR_CSISEL_MASK             (0x3 << 11)
-#define MXC_CRMAP_ASCSR_SSI2SEL_OFFSET          7
-#define MXC_CRMAP_ASCSR_SSI2SEL_MASK            (0x3 << 7)
-#define MXC_CRMAP_ASCSR_SSI1SEL_OFFSET          5
-#define MXC_CRMAP_ASCSR_SSI1SEL_MASK            (0x3 << 5)
-#define MXC_CRMAP_ASCSR_APSEL_OFFSET            3
-#define MXC_CRMAP_ASCSR_APSEL_MASK              (0x3 << 3)
-#define MXC_CRMAP_ASCSR_AP_PATDIV1_OFFSET       2
-#define MXC_CRMAP_ASCSR_AP_PATREF_DIV1          0x4
-#define MXC_CRMAP_ASCSR_APISEL                  0x1
-
-#define MXC_CRMAP_ACDR_ARMDIV_OFFSET            8
-#define MXC_CRMAP_ACDR_ARMDIV_MASK              (0xF << 8)
-#define MXC_CRMAP_ACDR_AHBDIV_OFFSET            4
-#define MXC_CRMAP_ACDR_AHBDIV_MASK              (0xF << 4)
-#define MXC_CRMAP_ACDR_IPDIV_OFFSET             0
-#define MXC_CRMAP_ACDR_IPDIV_MASK               0xF
-
-#define MXC_CRMAP_ACDER1_CSIEN_OFFSET           30
-#define MXC_CRMAP_ACDER1_CSIDIV_OFFSET          24
-#define MXC_CRMAP_ACDER1_CSIDIV_MASK            (0x3F << 24)
-#define MXC_CRMAP_ACDER1_SSI2EN_OFFSET          14
-#define MXC_CRMAP_ACDER1_SSI2DIV_OFFSET         8
-#define MXC_CRMAP_ACDER1_SSI2DIV_MASK           (0x3F << 8)
-#define MXC_CRMAP_ACDER1_SSI1EN_OFFSET          6
-#define MXC_CRMAP_ACDER1_SSI1DIV_OFFSET         0
-#define MXC_CRMAP_ACDER1_SSI1DIV_MASK           0x3F
-
-#define MXC_CRMAP_ACDER2_CRCT_CLK_DIV_OFFSET    24
-#define MXC_CRMAP_ACDER2_CRCT_CLK_DIV_MASK      (0x7 << 24)
-#define MXC_CRMAP_ACDER2_NFCEN_OFFSET           20
-#define MXC_CRMAP_ACDER2_NFCDIV_OFFSET          16
-#define MXC_CRMAP_ACDER2_NFCDIV_MASK            (0xF << 16)
-#define MXC_CRMAP_ACDER2_USBEN_OFFSET           12
-#define MXC_CRMAP_ACDER2_USBDIV_OFFSET          8
-#define MXC_CRMAP_ACDER2_USBDIV_MASK            (0xF << 8)
-#define MXC_CRMAP_ACDER2_BAUD_ISEL_OFFSET       5
-#define MXC_CRMAP_ACDER2_BAUD_ISEL_MASK         (0x3 << 5)
-#define MXC_CRMAP_ACDER2_BAUDDIV_OFFSET         0
-#define MXC_CRMAP_ACDER2_BAUDDIV_MASK           0xF
-
-#define MXC_CRMAP_AMLPMRA_MLPMA7_OFFSET         22
-#define MXC_CRMAP_AMLPMRA_MLPMA7_MASK           (0x7 << 22)
-#define MXC_CRMAP_AMLPMRA_MLPMA6_OFFSET         19
-#define MXC_CRMAP_AMLPMRA_MLPMA6_MASK           (0x7 << 19)
-#define MXC_CRMAP_AMLPMRA_MLPMA4_OFFSET         12
-#define MXC_CRMAP_AMLPMRA_MLPMA4_MASK           (0x7 << 12)
-#define MXC_CRMAP_AMLPMRA_MLPMA3_OFFSET         9
-#define MXC_CRMAP_AMLPMRA_MLPMA3_MASK           (0x7 << 9)
-#define MXC_CRMAP_AMLPMRA_MLPMA2_OFFSET         6
-#define MXC_CRMAP_AMLPMRA_MLPMA2_MASK           (0x7 << 6)
-#define MXC_CRMAP_AMLPMRA_MLPMA1_OFFSET         3
-#define MXC_CRMAP_AMLPMRA_MLPMA1_MASK           (0x7 << 3)
-
-#define MXC_CRMAP_AMLPMRB_MLPMB0_OFFSET         0
-#define MXC_CRMAP_AMLPMRB_MLPMB0_MASK           0x7
-
-#define MXC_CRMAP_AMLPMRC_MLPMC9_OFFSET         28
-#define MXC_CRMAP_AMLPMRC_MLPMC9_MASK           (0x7 << 28)
-#define MXC_CRMAP_AMLPMRC_MLPMC7_OFFSET         22
-#define MXC_CRMAP_AMLPMRC_MLPMC7_MASK           (0x7 << 22)
-#define MXC_CRMAP_AMLPMRC_MLPMC5_OFFSET         16
-#define MXC_CRMAP_AMLPMRC_MLPMC5_MASK           (0x7 << 16)
-#define MXC_CRMAP_AMLPMRC_MLPMC4_OFFSET         12
-#define MXC_CRMAP_AMLPMRC_MLPMC4_MASK           (0x7 << 12)
-#define MXC_CRMAP_AMLPMRC_MLPMC3_OFFSET         9
-#define MXC_CRMAP_AMLPMRC_MLPMC3_MASK           (0x7 << 9)
-#define MXC_CRMAP_AMLPMRC_MLPMC2_OFFSET         6
-#define MXC_CRMAP_AMLPMRC_MLPMC2_MASK           (0x7 << 6)
-#define MXC_CRMAP_AMLPMRC_MLPMC1_OFFSET         3
-#define MXC_CRMAP_AMLPMRC_MLPMC1_MASK           (0x7 << 3)
-#define MXC_CRMAP_AMLPMRC_MLPMC0_OFFSET         0
-#define MXC_CRMAP_AMLPMRC_MLPMC0_MASK           0x7
-
-#define MXC_CRMAP_AMLPMRD_MLPMD7_OFFSET         22
-#define MXC_CRMAP_AMLPMRD_MLPMD7_MASK           (0x7 << 22)
-#define MXC_CRMAP_AMLPMRD_MLPMD4_OFFSET         12
-#define MXC_CRMAP_AMLPMRD_MLPMD4_MASK           (0x7 << 12)
-#define MXC_CRMAP_AMLPMRD_MLPMD3_OFFSET         9
-#define MXC_CRMAP_AMLPMRD_MLPMD3_MASK           (0x7 << 9)
-#define MXC_CRMAP_AMLPMRD_MLPMD2_OFFSET         6
-#define MXC_CRMAP_AMLPMRD_MLPMD2_MASK           (0x7 << 6)
-#define MXC_CRMAP_AMLPMRD_MLPMD0_OFFSET         0
-#define MXC_CRMAP_AMLPMRD_MLPMD0_MASK           0x7
-
-#define MXC_CRMAP_AMLPMRE1_MLPME9_OFFSET        28
-#define MXC_CRMAP_AMLPMRE1_MLPME9_MASK          (0x7 << 28)
-#define MXC_CRMAP_AMLPMRE1_MLPME8_OFFSET        25
-#define MXC_CRMAP_AMLPMRE1_MLPME8_MASK          (0x7 << 25)
-#define MXC_CRMAP_AMLPMRE1_MLPME7_OFFSET        22
-#define MXC_CRMAP_AMLPMRE1_MLPME7_MASK          (0x7 << 22)
-#define MXC_CRMAP_AMLPMRE1_MLPME6_OFFSET        19
-#define MXC_CRMAP_AMLPMRE1_MLPME6_MASK          (0x7 << 19)
-#define MXC_CRMAP_AMLPMRE1_MLPME5_OFFSET        16
-#define MXC_CRMAP_AMLPMRE1_MLPME5_MASK          (0x7 << 16)
-#define MXC_CRMAP_AMLPMRE1_MLPME4_OFFSET        12
-#define MXC_CRMAP_AMLPMRE1_MLPME4_MASK          (0x7 << 12)
-#define MXC_CRMAP_AMLPMRE1_MLPME3_OFFSET        9
-#define MXC_CRMAP_AMLPMRE1_MLPME3_MASK          (0x7 << 9)
-#define MXC_CRMAP_AMLPMRE1_MLPME2_OFFSET        6
-#define MXC_CRMAP_AMLPMRE1_MLPME2_MASK          (0x7 << 6)
-#define MXC_CRMAP_AMLPMRE1_MLPME1_OFFSET        3
-#define MXC_CRMAP_AMLPMRE1_MLPME1_MASK          (0x7 << 3)
-#define MXC_CRMAP_AMLPMRE1_MLPME0_OFFSET        0
-#define MXC_CRMAP_AMLPMRE1_MLPME0_MASK          0x7
-
-#define MXC_CRMAP_AMLPMRE2_MLPME0_OFFSET        0
-#define MXC_CRMAP_AMLPMRE2_MLPME0_MASK          0x7
-
-#define MXC_CRMAP_AMLPMRF_MLPMF6_OFFSET         19
-#define MXC_CRMAP_AMLPMRF_MLPMF6_MASK           (0x7 << 19)
-#define MXC_CRMAP_AMLPMRF_MLPMF5_OFFSET         16
-#define MXC_CRMAP_AMLPMRF_MLPMF5_MASK           (0x7 << 16)
-#define MXC_CRMAP_AMLPMRF_MLPMF3_OFFSET         9
-#define MXC_CRMAP_AMLPMRF_MLPMF3_MASK           (0x7 << 9)
-#define MXC_CRMAP_AMLPMRF_MLPMF2_OFFSET         6
-#define MXC_CRMAP_AMLPMRF_MLPMF2_MASK           (0x7 << 6)
-#define MXC_CRMAP_AMLPMRF_MLPMF1_OFFSET         3
-#define MXC_CRMAP_AMLPMRF_MLPMF1_MASK           (0x7 << 3)
-#define MXC_CRMAP_AMLPMRF_MLPMF0_OFFSET         0
-#define MXC_CRMAP_AMLPMRF_MLPMF0_MASK           (0x7 << 0)
-
-#define MXC_CRMAP_AMLPMRG_MLPMG9_OFFSET         28
-#define MXC_CRMAP_AMLPMRG_MLPMG9_MASK           (0x7 << 28)
-#define MXC_CRMAP_AMLPMRG_MLPMG7_OFFSET         22
-#define MXC_CRMAP_AMLPMRG_MLPMG7_MASK           (0x7 << 22)
-#define MXC_CRMAP_AMLPMRG_MLPMG6_OFFSET         19
-#define MXC_CRMAP_AMLPMRG_MLPMG6_MASK           (0x7 << 19)
-#define MXC_CRMAP_AMLPMRG_MLPMG5_OFFSET         16
-#define MXC_CRMAP_AMLPMRG_MLPMG5_MASK           (0x7 << 16)
-#define MXC_CRMAP_AMLPMRG_MLPMG4_OFFSET         12
-#define MXC_CRMAP_AMLPMRG_MLPMG4_MASK           (0x7 << 12)
-#define MXC_CRMAP_AMLPMRG_MLPMG3_OFFSET         9
-#define MXC_CRMAP_AMLPMRG_MLPMG3_MASK           (0x7 << 9)
-#define MXC_CRMAP_AMLPMRG_MLPMG2_OFFSET         6
-#define MXC_CRMAP_AMLPMRG_MLPMG2_MASK           (0x7 << 6)
-#define MXC_CRMAP_AMLPMRG_MLPMG1_OFFSET         3
-#define MXC_CRMAP_AMLPMRG_MLPMG1_MASK           (0x7 << 3)
-#define MXC_CRMAP_AMLPMRG_MLPMG0_OFFSET         0
-#define MXC_CRMAP_AMLPMRG_MLPMG0_MASK           0x7
-
-#define MXC_CRMAP_AGPR_IPUPAD_OFFSET            20
-#define MXC_CRMAP_AGPR_IPUPAD_MASK              (0x7 << 20)
-
-#define MXC_CRMAP_APRA_EL1TEN_OFFSET            29
-#define MXC_CRMAP_APRA_SIMEN_OFFSET             24
-#define MXC_CRMAP_APRA_UART3DIV_OFFSET          17
-#define MXC_CRMAP_APRA_UART3DIV_MASK            (0xF << 17)
-#define MXC_CRMAP_APRA_UART3EN_OFFSET           16
-#define MXC_CRMAP_APRA_SAHARA_DIV2_CLKEN_OFFSET 14
-#define MXC_CRMAP_APRA_MQSPIEN_OFFSET           13
-#define MXC_CRMAP_APRA_UART2EN_OFFSET           8
-#define MXC_CRMAP_APRA_UART1EN_OFFSET           0
-
-#define MXC_CRMAP_APRB_SDHC2_ISEL_OFFSET        13
-#define MXC_CRMAP_APRB_SDHC2_ISEL_MASK          (0x7 << 13)
-#define MXC_CRMAP_APRB_SDHC2_DIV_OFFSET         9
-#define MXC_CRMAP_APRB_SDHC2_DIV_MASK           (0xF << 9)
-#define MXC_CRMAP_APRB_SDHC2EN_OFFSET           8
-#define MXC_CRMAP_APRB_SDHC1_ISEL_OFFSET        5
-#define MXC_CRMAP_APRB_SDHC1_ISEL_MASK          (0x7 << 5)
-#define MXC_CRMAP_APRB_SDHC1_DIV_OFFSET         1
-#define MXC_CRMAP_APRB_SDHC1_DIV_MASK           (0xF << 1)
-#define MXC_CRMAP_APRB_SDHC1EN_OFFSET           0
-
-#define MXC_CRMAP_ACSR_ADS_OFFSET               8
-#define MXC_CRMAP_ACSR_ADS                      (0x1 << 8)
-#define MXC_CRMAP_ACSR_ACS                      0x1
-
-#define MXC_CRMAP_ADCR_LFDF_0                   (0x0 << 8)
-#define MXC_CRMAP_ADCR_LFDF_2                   (0x1 << 8)
-#define MXC_CRMAP_ADCR_LFDF_4                   (0x2 << 8)
-#define MXC_CRMAP_ADCR_LFDF_8                   (0x3 << 8)
-#define MXC_CRMAP_ADCR_LFDF_OFFSET              8
-#define MXC_CRMAP_ADCR_LFDF_MASK                (0x3 << 8)
-#define MXC_CRMAP_ADCR_ALT_PLL                  0x80
-#define MXC_CRMAP_ADCR_DFS_DIVEN                0x20
-#define MXC_CRMAP_ADCR_DIV_BYP                  0x2
-#define MXC_CRMAP_ADCR_VSTAT                    0x8
-#define MXC_CRMAP_ADCR_TSTAT                    0x10
-#define MXC_CRMAP_ADCR_DVFS_VCTRL               0x10
-#define MXC_CRMAP_ADCR_CLK_ON                   0x40
-
-#define MXC_CRMAP_ADFMR_FC_OFFSET               16
-#define MXC_CRMAP_ADFMR_FC_MASK                 (0x1F << 16)
-#define MXC_CRMAP_ADFMR_MF_OFFSET               1
-#define MXC_CRMAP_ADFMR_MF_MASK                 (0x3FF << 1)
-#define MXC_CRMAP_ADFMR_DFM_CLK_READY           0x1
-#define MXC_CRMAP_ADFMR_DFM_PWR_DOWN            0x8000
-
-#define MXC_CRMAP_ACR_CKOHS_HIGH                (1 << 18)
-#define MXC_CRMAP_ACR_CKOS_HIGH                 (1 << 16)
-#define MXC_CRMAP_ACR_CKOHS_MASK                (0x7 << 12)
-#define MXC_CRMAP_ACR_CKOHD                     (1 << 11)
-#define MXC_CRMAP_ACR_CKOHDIV_MASK              (0xF << 8)
-#define MXC_CRMAP_ACR_CKOHDIV_OFFSET            8
-#define MXC_CRMAP_ACR_CKOD                      (1 << 7)
-#define MXC_CRMAP_ACR_CKOS_MASK                 (0x7 << 4)
-
-/* AP Warm reset */
-#define MXC_CRMAP_AMCR_SW_AP                    (1 << 14)
-
-/* Bit definitions of ACGCR in CRM_AP for tree level clock gating */
-#define MXC_CRMAP_ACGCR_ACG0_STOP_WAIT          0x00000001
-#define MXC_CRMAP_ACGCR_ACG0_STOP               0x00000003
-#define MXC_CRMAP_ACGCR_ACG0_RUN                0x00000007
-#define MXC_CRMAP_ACGCR_ACG0_DISABLED           0x00000000
-
-#define MXC_CRMAP_ACGCR_ACG1_STOP_WAIT          0x00000008
-#define MXC_CRMAP_ACGCR_ACG1_STOP               0x00000018
-#define MXC_CRMAP_ACGCR_ACG1_RUN                0x00000038
-#define MXC_CRMAP_ACGCR_ACG1_DISABLED           0x00000000
-
-#define MXC_CRMAP_ACGCR_ACG2_STOP_WAIT          0x00000040
-#define MXC_CRMAP_ACGCR_ACG2_STOP               0x000000C0
-#define MXC_CRMAP_ACGCR_ACG2_RUN                0x000001C0
-#define MXC_CRMAP_ACGCR_ACG2_DISABLED           0x00000000
-
-#define MXC_CRMAP_ACGCR_ACG3_STOP_WAIT          0x00000200
-#define MXC_CRMAP_ACGCR_ACG3_STOP               0x00000600
-#define MXC_CRMAP_ACGCR_ACG3_RUN                0x00000E00
-#define MXC_CRMAP_ACGCR_ACG3_DISABLED           0x00000000
-
-#define MXC_CRMAP_ACGCR_ACG4_STOP_WAIT          0x00001000
-#define MXC_CRMAP_ACGCR_ACG4_STOP               0x00003000
-#define MXC_CRMAP_ACGCR_ACG4_RUN                0x00007000
-#define MXC_CRMAP_ACGCR_ACG4_DISABLED           0x00000000
-
-#define MXC_CRMAP_ACGCR_ACG5_STOP_WAIT          0x00010000
-#define MXC_CRMAP_ACGCR_ACG5_STOP               0x00030000
-#define MXC_CRMAP_ACGCR_ACG5_RUN                0x00070000
-#define MXC_CRMAP_ACGCR_ACG5_DISABLED           0x00000000
-
-#define MXC_CRMAP_ACGCR_ACG6_STOP_WAIT          0x00080000
-#define MXC_CRMAP_ACGCR_ACG6_STOP               0x00180000
-#define MXC_CRMAP_ACGCR_ACG6_RUN                0x00380000
-#define MXC_CRMAP_ACGCR_ACG6_DISABLED           0x00000000
-
-#define NUM_GATE_CTRL                           6
-
-/* CRM COM Register Offsets */
-#define MXC_CRMCOM_CSCR                         (MXC_CRM_COM_BASE + 0x0C)
-#define MXC_CRMCOM_CCCR                         (MXC_CRM_COM_BASE + 0x10)
-
-/* CRM COM Bit Definitions */
-#define MXC_CRMCOM_CSCR_PPD1                    0x08000000
-#define MXC_CRMCOM_CSCR_CKOHSEL                 (1 << 18)
-#define MXC_CRMCOM_CSCR_CKOSEL                  (1 << 17)
-#define MXC_CRMCOM_CCCR_CC_DIV_OFFSET           8
-#define MXC_CRMCOM_CCCR_CC_DIV_MASK             (0x1F << 8)
-#define MXC_CRMCOM_CCCR_CC_SEL_OFFSET           0
-#define MXC_CRMCOM_CCCR_CC_SEL_MASK             0x3
-
-/* DSM Register Offsets */
-#define MXC_DSM_SLEEP_TIME                      (MXC_DSM_BASE + 0x0c)
-#define MXC_DSM_CONTROL0                        (MXC_DSM_BASE + 0x20)
-#define MXC_DSM_CONTROL1                        (MXC_DSM_BASE + 0x24)
-#define MXC_DSM_CTREN                           (MXC_DSM_BASE + 0x28)
-#define MXC_DSM_WARM_PER                        (MXC_DSM_BASE + 0x40)
-#define MXC_DSM_LOCK_PER                        (MXC_DSM_BASE + 0x44)
-#define MXC_DSM_MGPER                           (MXC_DSM_BASE + 0x4c)
-#define MXC_DSM_CRM_CONTROL                     (MXC_DSM_BASE + 0x50)
-
-/* Bit definitions of various registers in DSM */
-#define MXC_DSM_CRM_CTRL_DVFS_BYP               0x00000008
-#define MXC_DSM_CRM_CTRL_DVFS_VCTRL             0x00000004
-#define MXC_DSM_CRM_CTRL_LPMD1                  0x00000002
-#define MXC_DSM_CRM_CTRL_LPMD0                  0x00000001
-#define MXC_DSM_CRM_CTRL_LPMD_STOP_MODE         0x00000000
-#define MXC_DSM_CRM_CTRL_LPMD_WAIT_MODE         0x00000001
-#define MXC_DSM_CRM_CTRL_LPMD_RUN_MODE          0x00000003
-#define MXC_DSM_CONTROL0_STBY_COMMIT_EN         0x00000200
-#define MXC_DSM_CONTROL0_MSTR_EN                0x00000001
-#define MXC_DSM_CONTROL0_RESTART                0x00000010
-/* Counter Block reset */
-#define MXC_DSM_CONTROL1_CB_RST                 0x00000002
-/* State Machine reset */
-#define MXC_DSM_CONTROL1_SM_RST                 0x00000004
-/* Bit needed to reset counter block */
-#define MXC_CONTROL1_RST_CNT32                  0x00000008
-#define MXC_DSM_CONTROL1_RST_CNT32_EN           0x00000800
-#define MXC_DSM_CONTROL1_SLEEP                  0x00000100
-#define MXC_DSM_CONTROL1_WAKEUP_DISABLE         0x00004000
-#define MXC_DSM_CTREN_CNT32                     0x00000001
-
-/* Magic Fix enable bit */
-#define MXC_DSM_MGPER_EN_MGFX                   0x80000000
-#define MXC_DSM_MGPER_PER_MASK                  0x000003FF
-#define MXC_DSM_MGPER_PER(n)                    (MXC_DSM_MGPER_PER_MASK & n)
-
-/* Address offsets of the CLKCTL registers */
-#define MXC_CLKCTL_GP_CTRL      (MXC_CLKCTL_BASE + 0x00)
-#define MXC_CLKCTL_GP_SER       (MXC_CLKCTL_BASE + 0x04)
-#define MXC_CLKCTL_GP_CER       (MXC_CLKCTL_BASE + 0x08)
-
-#endif /* _ARCH_ARM_MACH_MXC91231_CRM_REGS_H_ */
diff --git a/arch/arm/mach-mxc91231/devices.c b/arch/arm/mach-mxc91231/devices.c
deleted file mode 100644
index 027af4f0d18..00000000000
--- a/arch/arm/mach-mxc91231/devices.c
+++ /dev/null
@@ -1,251 +0,0 @@
-/*
- * Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
- * Copyright 2008 Sascha Hauer, kernel@pengutronix.de
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor,
- * Boston, MA  02110-1301, USA.
- */
-
-#include <linux/module.h>
-#include <linux/platform_device.h>
-#include <linux/serial.h>
-#include <linux/gpio.h>
-#include <mach/hardware.h>
-#include <mach/irqs.h>
-#include <mach/imx-uart.h>
-
-static struct resource uart0[] = {
-        {
-                .start = MXC91231_UART1_BASE_ADDR,
-                .end = MXC91231_UART1_BASE_ADDR + 0x0B5,
-                .flags = IORESOURCE_MEM,
-        }, {
-                .start = MXC91231_INT_UART1_RX,
-                .end = MXC91231_INT_UART1_RX,
-                .flags = IORESOURCE_IRQ,
-        }, {
-                .start = MXC91231_INT_UART1_TX,
-                .end = MXC91231_INT_UART1_TX,
-                .flags = IORESOURCE_IRQ,
-        }, {
-                .start = MXC91231_INT_UART1_MINT,
-                .end = MXC91231_INT_UART1_MINT,
-                .flags = IORESOURCE_IRQ,
-        },
-};
-
-struct platform_device mxc_uart_device0 = {
-        .name = "imx-uart",
-        .id = 0,
-        .resource = uart0,
-        .num_resources = ARRAY_SIZE(uart0),
-};
-
-static struct resource uart1[] = {
-        {
-                .start = MXC91231_UART2_BASE_ADDR,
-                .end = MXC91231_UART2_BASE_ADDR + 0x0B5,
-                .flags = IORESOURCE_MEM,
-        }, {
-                .start = MXC91231_INT_UART2_RX,
-                .end = MXC91231_INT_UART2_RX,
-                .flags = IORESOURCE_IRQ,
-        }, {
-                .start = MXC91231_INT_UART2_TX,
-                .end = MXC91231_INT_UART2_TX,
-                .flags = IORESOURCE_IRQ,
-        }, {
-                .start = MXC91231_INT_UART2_MINT,
-                .end = MXC91231_INT_UART2_MINT,
-                .flags = IORESOURCE_IRQ,
-        },
-};
-
-struct platform_device mxc_uart_device1 = {
-        .name = "imx-uart",
-        .id = 1,
-        .resource = uart1,
-        .num_resources = ARRAY_SIZE(uart1),
-};
-
-static struct resource uart2[] = {
-        {
-                .start = MXC91231_UART3_BASE_ADDR,
-                .end = MXC91231_UART3_BASE_ADDR + 0x0B5,
-                .flags = IORESOURCE_MEM,
-        }, {
-                .start = MXC91231_INT_UART3_RX,
-                .end = MXC91231_INT_UART3_RX,
-                .flags = IORESOURCE_IRQ,
-        }, {
-                .start = MXC91231_INT_UART3_TX,
-                .end = MXC91231_INT_UART3_TX,
-                .flags = IORESOURCE_IRQ,
-        }, {
-                .start = MXC91231_INT_UART3_MINT,
-                .end = MXC91231_INT_UART3_MINT,
-                .flags = IORESOURCE_IRQ,
-
-        },
-};
-
-struct platform_device mxc_uart_device2 = {
-        .name = "imx-uart",
-        .id = 2,
-        .resource = uart2,
-        .num_resources = ARRAY_SIZE(uart2),
-};
-
-/* GPIO port description */
-static struct mxc_gpio_port mxc_gpio_ports[] = {
-        [0] = {
-                .chip.label = "gpio-0",
-                .base = MXC91231_IO_ADDRESS(MXC91231_GPIO1_AP_BASE_ADDR),
-                .irq = MXC91231_INT_GPIO1,
-                .virtual_irq_start = MXC_GPIO_IRQ_START,
-        },
-        [1] = {
-                .chip.label = "gpio-1",
-                .base = MXC91231_IO_ADDRESS(MXC91231_GPIO2_AP_BASE_ADDR),
-                .irq = MXC91231_INT_GPIO2,
-                .virtual_irq_start = MXC_GPIO_IRQ_START + 32,
-        },
-        [2] = {
-                .chip.label = "gpio-2",
-                .base = MXC91231_IO_ADDRESS(MXC91231_GPIO3_AP_BASE_ADDR),
-                .irq = MXC91231_INT_GPIO3,
-                .virtual_irq_start = MXC_GPIO_IRQ_START + 64,
-        },
-        [3] = {
-                .chip.label = "gpio-3",
-                .base = MXC91231_IO_ADDRESS(MXC91231_GPIO4_SH_BASE_ADDR),
-                .irq = MXC91231_INT_GPIO4,
-                .virtual_irq_start = MXC_GPIO_IRQ_START + 96,
-        },
-};
-
-int __init mxc91231_register_gpios(void)
-{
-        return mxc_gpio_init(mxc_gpio_ports, ARRAY_SIZE(mxc_gpio_ports));
-}
-
-static struct resource mxc_nand_resources[] = {
-        {
-                .start  = MXC91231_NFC_BASE_ADDR,
-                .end    = MXC91231_NFC_BASE_ADDR + 0xfff,
-                .flags  = IORESOURCE_MEM
-        }, {
-                .start  = MXC91231_INT_NANDFC,
-                .end    = MXC91231_INT_NANDFC,
-                .flags  = IORESOURCE_IRQ
-        },
-};
-
-struct platform_device mxc_nand_device = {
-        .name = "mxc_nand",
-        .id = 0,
-        .num_resources = ARRAY_SIZE(mxc_nand_resources),
-        .resource = mxc_nand_resources,
-};
-
-static struct resource mxc_sdhc0_resources[] = {
-        {
-                .start = MXC91231_MMC_SDHC1_BASE_ADDR,
-                .end = MXC91231_MMC_SDHC1_BASE_ADDR + SZ_16K - 1,
-                .flags = IORESOURCE_MEM,
-        }, {
-                .start = MXC91231_INT_MMC_SDHC1,
-                .end = MXC91231_INT_MMC_SDHC1,
-                .flags = IORESOURCE_IRQ,
-        },
-};
-
-static struct resource mxc_sdhc1_resources[] = {
-        {
-                .start = MXC91231_MMC_SDHC2_BASE_ADDR,
-                .end = MXC91231_MMC_SDHC2_BASE_ADDR + SZ_16K - 1,
-                .flags = IORESOURCE_MEM,
-        }, {
-                .start = MXC91231_INT_MMC_SDHC2,
-                .end = MXC91231_INT_MMC_SDHC2,
-                .flags = IORESOURCE_IRQ,
-        },
-};
-
-struct platform_device mxc_sdhc_device0 = {
-        .name = "mxc-mmc",
-        .id = 0,
-        .num_resources = ARRAY_SIZE(mxc_sdhc0_resources),
-        .resource = mxc_sdhc0_resources,
-};
-
-struct platform_device mxc_sdhc_device1 = {
-        .name = "mxc-mmc",
-        .id = 1,
-        .num_resources = ARRAY_SIZE(mxc_sdhc1_resources),
-        .resource = mxc_sdhc1_resources,
-};
-
-static struct resource mxc_cspi0_resources[] = {
-        {
-                .start = MXC91231_CSPI1_BASE_ADDR,
-                .end = MXC91231_CSPI1_BASE_ADDR + 0x20,
-                .flags = IORESOURCE_MEM,
-        }, {
-                .start = MXC91231_INT_CSPI1,
-                .end = MXC91231_INT_CSPI1,
-                .flags = IORESOURCE_IRQ,
-        },
-};
-
-struct platform_device mxc_cspi_device0 = {
-        .name = "spi_imx",
-        .id = 0,
-        .num_resources = ARRAY_SIZE(mxc_cspi0_resources),
-        .resource = mxc_cspi0_resources,
-};
-
-static struct resource mxc_cspi1_resources[] = {
-        {
-                .start = MXC91231_CSPI2_BASE_ADDR,
-                .end = MXC91231_CSPI2_BASE_ADDR + 0x20,
-                .flags = IORESOURCE_MEM,
-        }, {
-                .start = MXC91231_INT_CSPI2,
-                .end = MXC91231_INT_CSPI2,
-                .flags = IORESOURCE_IRQ,
-        },
-};
-
-struct platform_device mxc_cspi_device1 = {
-        .name = "spi_imx",
-        .id = 1,
-        .num_resources = ARRAY_SIZE(mxc_cspi1_resources),
-        .resource = mxc_cspi1_resources,
-};
-
-static struct resource mxc_wdog0_resources[] = {
-        {
-                .start = MXC91231_WDOG1_BASE_ADDR,
-                .end = MXC91231_WDOG1_BASE_ADDR + 0x10,
-                .flags = IORESOURCE_MEM,
-        },
-};
-
-struct platform_device mxc_wdog_device0 = {
-        .name = "mxc-wdt",
-        .id = 0,
-        .num_resources = ARRAY_SIZE(mxc_wdog0_resources),
-        .resource = mxc_wdog0_resources,
-};
diff --git a/arch/arm/mach-mxc91231/devices.h b/arch/arm/mach-mxc91231/devices.h
deleted file mode 100644
index 72a2136ce27..00000000000
--- a/arch/arm/mach-mxc91231/devices.h
+++ /dev/null
@@ -1,13 +0,0 @@
-extern struct platform_device mxc_uart_device0;
-extern struct platform_device mxc_uart_device1;
-extern struct platform_device mxc_uart_device2;
-
-extern struct platform_device mxc_nand_device;
-
-extern struct platform_device mxc_sdhc_device0;
-extern struct platform_device mxc_sdhc_device1;
-
-extern struct platform_device mxc_cspi_device0;
-extern struct platform_device mxc_cspi_device1;
-
-extern struct platform_device mxc_wdog_device0;
diff --git a/arch/arm/mach-mxc91231/iomux.c b/arch/arm/mach-mxc91231/iomux.c
deleted file mode 100644
index 66fc41cbf2c..00000000000
--- a/arch/arm/mach-mxc91231/iomux.c
+++ /dev/null
@@ -1,177 +0,0 @@
-/*
- * Copyright 2004-2006 Freescale Semiconductor, Inc. All Rights Reserved.
- * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de>
- * Copyright (C) 2009 by Valentin Longchamp <valentin.longchamp@epfl.ch>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301, USA.
- */
-
-#include <linux/module.h>
-#include <linux/spinlock.h>
-#include <linux/io.h>
-#include <linux/kernel.h>
-#include <mach/hardware.h>
-#include <mach/gpio.h>
-#include <mach/iomux-mxc91231.h>
-
-/*
- * IOMUX register (base) addresses
- */
-#define IOMUX_AP_BASE           MXC91231_IO_ADDRESS(MXC91231_IOMUX_AP_BASE_ADDR)
-#define IOMUX_COM_BASE          MXC91231_IO_ADDRESS(MXC91231_IOMUX_COM_BASE_ADDR)
-#define IOMUXSW_AP_MUX_CTL      (IOMUX_AP_BASE + 0x000)
-#define IOMUXSW_SP_MUX_CTL      (IOMUX_COM_BASE + 0x000)
-#define IOMUXSW_PAD_CTL         (IOMUX_COM_BASE + 0x200)
-
-#define IOMUXINT_OBS1           (IOMUX_AP_BASE + 0x600)
-#define IOMUXINT_OBS2           (IOMUX_AP_BASE + 0x004)
-
-static DEFINE_SPINLOCK(gpio_mux_lock);
-
-#define NB_PORTS                        ((PIN_MAX + 32) / 32)
-#define PIN_GLOBAL_NUM(pin) \
-        (((pin & MUX_SIDE_MASK) >> MUX_SIDE_SHIFT)*PIN_AP_MAX + \
-         ((pin & MUX_REG_MASK) >> MUX_REG_SHIFT)*4 +            \
-         ((pin & MUX_FIELD_MASK) >> MUX_FIELD_SHIFT))
-
-unsigned long mxc_pin_alloc_map[NB_PORTS * 32 / BITS_PER_LONG];
-/*
- * set the mode for a IOMUX pin.
- */
-int mxc_iomux_mode(unsigned int pin_mode)
-{
-        u32 side, field, l, mode, ret = 0;
-        void __iomem *reg;
-
-        side = (pin_mode & MUX_SIDE_MASK) >> MUX_SIDE_SHIFT;
-        switch (side) {
-        case MUX_SIDE_AP:
-                reg = IOMUXSW_AP_MUX_CTL;
-                break;
-        case MUX_SIDE_SP:
-                reg = IOMUXSW_SP_MUX_CTL;
-                break;
-        default:
-                return -EINVAL;
-        }
-        reg += ((pin_mode & MUX_REG_MASK) >> MUX_REG_SHIFT) * 4;
-        field = (pin_mode & MUX_FIELD_MASK) >> MUX_FIELD_SHIFT;
-        mode = (pin_mode & MUX_MODE_MASK) >> MUX_MODE_SHIFT;
-
-        spin_lock(&gpio_mux_lock);
-
-        l = __raw_readl(reg);
-        l &= ~(0xff << (field * 8));
-        l |= mode << (field * 8);
-        __raw_writel(l, reg);
-
-        spin_unlock(&gpio_mux_lock);
-
-        return ret;
-}
-EXPORT_SYMBOL(mxc_iomux_mode);
-
-/*
- * This function configures the pad value for a IOMUX pin.
- */
-void mxc_iomux_set_pad(enum iomux_pins pin, u32 config)
-{
-        u32 padgrp, field, l;
-        void __iomem *reg;
-
-        padgrp = (pin & MUX_PADGRP_MASK) >> MUX_PADGRP_SHIFT;
-        reg = IOMUXSW_PAD_CTL + (pin + 2) / 3 * 4;
-        field = (pin + 2) % 3;
-
-        pr_debug("%s: reg offset = 0x%x, field = %d\n",
-                        __func__, (pin + 2) / 3, field);
-
-        spin_lock(&gpio_mux_lock);
-
-        l = __raw_readl(reg);
-        l &= ~(0x1ff << (field * 10));
-        l |= config << (field * 10);
-        __raw_writel(l, reg);
-
-        spin_unlock(&gpio_mux_lock);
-}
-EXPORT_SYMBOL(mxc_iomux_set_pad);
-
-/*
- * allocs a single pin:
- *      - reserves the pin so that it is not claimed by another driver
- *      - setups the iomux according to the configuration
- */
-int mxc_iomux_alloc_pin(unsigned int pin_mode, const char *label)
-{
-        unsigned pad = PIN_GLOBAL_NUM(pin_mode);
-        if (pad >= (PIN_MAX + 1)) {
-                printk(KERN_ERR "mxc_iomux: Attempt to request nonexistant pin %u for \"%s\"\n",
-                        pad, label ? label : "?");
-                return -EINVAL;
-        }
-
-        if (test_and_set_bit(pad, mxc_pin_alloc_map)) {
-                printk(KERN_ERR "mxc_iomux: pin %u already used. Allocation for \"%s\" failed\n",
-                        pad, label ? label : "?");
-                return -EBUSY;
-        }
-        mxc_iomux_mode(pin_mode);
-
-        return 0;
-}
-EXPORT_SYMBOL(mxc_iomux_alloc_pin);
-
-int mxc_iomux_setup_multiple_pins(const unsigned int *pin_list, unsigned count,
-                const char *label)
-{
-        const unsigned int *p = pin_list;
-        int i;
-        int ret = -EINVAL;
-
-        for (i = 0; i < count; i++) {
-                ret = mxc_iomux_alloc_pin(*p, label);
-                if (ret)
-                        goto setup_error;
-                p++;
-        }
-        return 0;
-
-setup_error:
-        mxc_iomux_release_multiple_pins(pin_list, i);
-        return ret;
-}
-EXPORT_SYMBOL(mxc_iomux_setup_multiple_pins);
-
-void mxc_iomux_release_pin(unsigned int pin_mode)
-{
-        unsigned pad = PIN_GLOBAL_NUM(pin_mode);
-
-        if (pad < (PIN_MAX + 1))
-                clear_bit(pad, mxc_pin_alloc_map);
-}
-EXPORT_SYMBOL(mxc_iomux_release_pin);
-
-void mxc_iomux_release_multiple_pins(const unsigned int *pin_list, int count)
-{
-        const unsigned int *p = pin_list;
-        int i;
-
-        for (i = 0; i < count; i++) {
-                mxc_iomux_release_pin(*p);
-                p++;
-        }
-}
-EXPORT_SYMBOL(mxc_iomux_release_multiple_pins);
diff --git a/arch/arm/mach-mxc91231/magx-zn5.c b/arch/arm/mach-mxc91231/magx-zn5.c
deleted file mode 100644
index f31a45e5a0b..00000000000
--- a/arch/arm/mach-mxc91231/magx-zn5.c
+++ /dev/null
@@ -1,62 +0,0 @@
-/*
- * Copyright 2009 Dmitriy Taychenachev <dimichxp@gmail.com>
- *
- * This file is released under the GPLv2 or later.
- */
-
-#include <linux/irq.h>
-#include <linux/init.h>
-#include <linux/device.h>
-
-#include <asm/mach-types.h>
-#include <asm/mach/time.h>
-#include <asm/mach/arch.h>
-
-#include <mach/common.h>
-#include <mach/hardware.h>
-#include <mach/iomux-mxc91231.h>
-#include <mach/mmc.h>
-#include <mach/imx-uart.h>
-
-#include "devices.h"
-
-static struct imxuart_platform_data uart_pdata = {
-};
-
-static struct imxmmc_platform_data sdhc_pdata = {
-};
-
-static void __init zn5_init(void)
-{
-        pm_power_off = mxc91231_power_off;
-
-        mxc_iomux_alloc_pin(MXC91231_PIN_SP_USB_DAT_VP__RXD2, "uart2-rx");
-        mxc_iomux_alloc_pin(MXC91231_PIN_SP_USB_SE0_VM__TXD2, "uart2-tx");
-
-        mxc_register_device(&mxc_uart_device1, &uart_pdata);
-        mxc_register_device(&mxc_uart_device0, &uart_pdata);
-
-        mxc_register_device(&mxc_sdhc_device0, &sdhc_pdata);
-
-        mxc_register_device(&mxc_wdog_device0, NULL);
-
-        return;
-}
-
-static void __init zn5_timer_init(void)
-{
-        mxc91231_clocks_init(26000000); /* 26mhz ckih */
-}
-
-struct sys_timer zn5_timer = {
-        .init = zn5_timer_init,
-};
-
-MACHINE_START(MAGX_ZN5, "Motorola Zn5")
-        .boot_params = MXC91231_PHYS_OFFSET + 0x100,
-        .map_io = mxc91231_map_io,
-        .init_early = mxc91231_init_early,
-        .init_irq = mxc91231_init_irq,
-        .timer = &zn5_timer,
-        .init_machine = zn5_init,
-MACHINE_END
diff --git a/arch/arm/mach-mxc91231/mm.c b/arch/arm/mach-mxc91231/mm.c
deleted file mode 100644
index a77f6daf6a2..00000000000
--- a/arch/arm/mach-mxc91231/mm.c
+++ /dev/null
@@ -1,62 +0,0 @@
-/*
- *  Copyright (C) 1999,2000 Arm Limited
- *  Copyright (C) 2000 Deep Blue Solutions Ltd
- *  Copyright (C) 2002 Shane Nay (shane@minirl.com)
- *  Copyright 2004-2005 Freescale Semiconductor, Inc. All Rights Reserved.
- *    - add MXC specific definitions
- *  Copyright 2006 Motorola, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <linux/mm.h>
-#include <linux/init.h>
-#include <mach/hardware.h>
-#include <mach/common.h>
-#include <asm/pgtable.h>
-#include <asm/mach/map.h>
-
-/*
- * This structure defines the MXC memory map.
- */
-static struct map_desc mxc91231_io_desc[] __initdata = {
-        imx_map_entry(MXC91231, L2CC, MT_DEVICE),
-        imx_map_entry(MXC91231, X_MEMC, MT_DEVICE),
-        imx_map_entry(MXC91231, ROMP, MT_DEVICE),
-        imx_map_entry(MXC91231, AVIC, MT_DEVICE),
-        imx_map_entry(MXC91231, AIPS1, MT_DEVICE),
-        imx_map_entry(MXC91231, SPBA0, MT_DEVICE),
-        imx_map_entry(MXC91231, SPBA1, MT_DEVICE),
-        imx_map_entry(MXC91231, AIPS2, MT_DEVICE),
-};
-
-/*
- * This function initializes the memory map. It is called during the
- * system startup to create static physical to virtual memory map for
- * the IO modules.
- */
-void __init mxc91231_map_io(void)
-{
-        iotable_init(mxc91231_io_desc, ARRAY_SIZE(mxc91231_io_desc));
-}
-
-void __init mxc91231_init_early(void)
-{
-        mxc_set_cpu_type(MXC_CPU_MXC91231);
-}
-
-int mxc91231_register_gpios(void);
-
-void __init mxc91231_init_irq(void)
-{
-        mxc91231_register_gpios();
-        mxc_init_irq(MXC91231_IO_ADDRESS(MXC91231_AVIC_BASE_ADDR));
-}
diff --git a/arch/arm/mach-mxc91231/system.c b/arch/arm/mach-mxc91231/system.c
deleted file mode 100644
index 736f7efd874..00000000000
--- a/arch/arm/mach-mxc91231/system.c
+++ /dev/null
@@ -1,51 +0,0 @@
-/*
- * Copyright 2009 Dmitriy Taychenachev <dimichxp@gmail.com>
- *
- * This file is released under the GPLv2 or later.
- */
-
-#include <linux/delay.h>
-#include <linux/io.h>
-
-#include <asm/proc-fns.h>
-#include <mach/hardware.h>
-
-#include "crm_regs.h"
-
-#define WDOG_WCR                MXC91231_IO_ADDRESS(MXC91231_WDOG1_BASE_ADDR)
-#define WDOG_WCR_OUT_ENABLE     (1 << 6)
-#define WDOG_WCR_ASSERT         (1 << 5)
-
-void mxc91231_power_off(void)
-{
-        u16 wcr;
-
-        wcr = __raw_readw(WDOG_WCR);
-        wcr |= WDOG_WCR_OUT_ENABLE;
-        wcr &= ~WDOG_WCR_ASSERT;
-        __raw_writew(wcr, WDOG_WCR);
-}
-
-void mxc91231_arch_reset(char mode, const char *cmd)
-{
-        u32 amcr;
-
-        /* Reset the AP using CRM */
-        amcr = __raw_readl(MXC_CRMAP_AMCR);
-        amcr &= ~MXC_CRMAP_AMCR_SW_AP;
-        __raw_writel(amcr, MXC_CRMAP_AMCR);
-
-        mdelay(10);
-        cpu_reset(0);
-}
-
-void mxc91231_prepare_idle(void)
-{
-        u32 crm_ctl;
-
-        /* Go to WAIT mode after WFI */
-        crm_ctl = __raw_readl(MXC_DSM_CRM_CONTROL);
-        crm_ctl &= ~(MXC_DSM_CRM_CTRL_LPMD0 | MXC_DSM_CRM_CTRL_LPMD1);
-        crm_ctl |=  MXC_DSM_CRM_CTRL_LPMD_WAIT_MODE;
-        __raw_writel(crm_ctl, MXC_DSM_CRM_CONTROL);
-}
diff --git a/arch/arm/mach-mxs/Kconfig b/arch/arm/mach-mxs/Kconfig
index edacefac227..f114960622e 100644
--- a/arch/arm/mach-mxs/Kconfig
+++ b/arch/arm/mach-mxs/Kconfig
@@ -34,7 +34,6 @@ config MACH_MX23EVK
         select MXS_HAVE_PLATFORM_AUART
         select MXS_HAVE_PLATFORM_MXS_MMC
         select MXS_HAVE_PLATFORM_MXSFB
-        default y
         help
           Include support for MX23EVK platform. This includes specific
           configurations for the board and its peripherals.
@@ -49,7 +48,6 @@ config MACH_MX28EVK
         select MXS_HAVE_PLATFORM_MXS_MMC
         select MXS_HAVE_PLATFORM_MXSFB
         select MXS_OCOTP
-        default y
         help
           Include support for MX28EVK platform. This includes specific
           configurations for the board and its peripherals.
diff --git a/arch/arm/mach-mxs/clock-mx23.c b/arch/arm/mach-mxs/clock-mx23.c
index c3577ea789a..0163b6d8377 100644
--- a/arch/arm/mach-mxs/clock-mx23.c
+++ b/arch/arm/mach-mxs/clock-mx23.c
@@ -446,6 +446,8 @@ static struct clk_lookup lookups[] = {
         _REGISTER_CLOCK("rtc", NULL, rtc_clk)
         _REGISTER_CLOCK("mxs-dma-apbh", NULL, hbus_clk)
         _REGISTER_CLOCK("mxs-dma-apbx", NULL, xbus_clk)
+        _REGISTER_CLOCK("mxs-mmc.0", NULL, ssp_clk)
+        _REGISTER_CLOCK("mxs-mmc.1", NULL, ssp_clk)
         _REGISTER_CLOCK(NULL, "usb", usb_clk)
         _REGISTER_CLOCK(NULL, "audio", audio_clk)
         _REGISTER_CLOCK("mxs-pwm.0", NULL, pwm_clk)
diff --git a/arch/arm/mach-mxs/devices-mx28.h b/arch/arm/mach-mxs/devices-mx28.h
index c473eddce8c..79b94523954 100644
--- a/arch/arm/mach-mxs/devices-mx28.h
+++ b/arch/arm/mach-mxs/devices-mx28.h
@@ -34,7 +34,7 @@ extern const struct mxs_flexcan_data mx28_flexcan_data[] __initconst;
 #define mx28_add_flexcan0(pdata)        mx28_add_flexcan(0, pdata)
 #define mx28_add_flexcan1(pdata)        mx28_add_flexcan(1, pdata)
 
-extern const struct mxs_i2c_data mx28_mxs_i2c_data[] __initconst;
+extern const struct mxs_mxs_i2c_data mx28_mxs_i2c_data[] __initconst;
 #define mx28_add_mxs_i2c(id)            mxs_add_mxs_i2c(&mx28_mxs_i2c_data[id])
 
 extern const struct mxs_mxs_mmc_data mx28_mxs_mmc_data[] __initconst;
diff --git a/arch/arm/mach-mxs/devices/platform-mxs-i2c.c b/arch/arm/mach-mxs/devices/platform-mxs-i2c.c
index eab3a06836d..79222ec8ede 100644
--- a/arch/arm/mach-mxs/devices/platform-mxs-i2c.c
+++ b/arch/arm/mach-mxs/devices/platform-mxs-i2c.c
@@ -22,13 +22,14 @@
         [_id] = mxs_i2c_data_entry_single(soc, _id)
 
 #ifdef CONFIG_SOC_IMX28
-const struct mxs_i2c_data mx28_mxs_i2c_data[] __initconst = {
+const struct mxs_mxs_i2c_data mx28_mxs_i2c_data[] __initconst = {
         mxs_i2c_data_entry(MX28, 0),
         mxs_i2c_data_entry(MX28, 1),
 };
 #endif
 
-struct platform_device *__init mxs_add_mxs_i2c(const struct mxs_i2c_data *data)
+struct platform_device *__init mxs_add_mxs_i2c(
+                const struct mxs_mxs_i2c_data *data)
 {
         struct resource res[] = {
                 {
diff --git a/arch/arm/mach-mxs/include/mach/devices-common.h b/arch/arm/mach-mxs/include/mach/devices-common.h
index c5137f14c36..7a37469ed5b 100644
--- a/arch/arm/mach-mxs/include/mach/devices-common.h
+++ b/arch/arm/mach-mxs/include/mach/devices-common.h
@@ -65,13 +65,14 @@ struct platform_device *__init mxs_add_flexcan(
                 const struct flexcan_platform_data *pdata);
 
 /* i2c */
-struct mxs_i2c_data {
+struct mxs_mxs_i2c_data {
         int id;
         resource_size_t iobase;
         resource_size_t errirq;
         resource_size_t dmairq;
 };
-struct platform_device * __init mxs_add_mxs_i2c(const struct mxs_i2c_data *data);
+struct platform_device * __init mxs_add_mxs_i2c(
+                const struct mxs_mxs_i2c_data *data);
 
 /* mmc */
 #include <mach/mmc.h>
diff --git a/arch/arm/mach-mxs/include/mach/mx23.h b/arch/arm/mach-mxs/include/mach/mx23.h
index c0a18c23084..599094bc99d 100644
--- a/arch/arm/mach-mxs/include/mach/mx23.h
+++ b/arch/arm/mach-mxs/include/mach/mx23.h
@@ -57,7 +57,7 @@
 #define MX23_AUDIOIN_BASE_ADDR          (MX23_IO_BASE_ADDR + 0x04c000)
 #define MX23_LRADC_BASE_ADDR            (MX23_IO_BASE_ADDR + 0x050000)
 #define MX23_SPDIF_BASE_ADDR            (MX23_IO_BASE_ADDR + 0x054000)
-#define MX23_I2C0_BASE_ADDR             (MX23_IO_BASE_ADDR + 0x058000)
+#define MX23_I2C_BASE_ADDR              (MX23_IO_BASE_ADDR + 0x058000)
 #define MX23_RTC_BASE_ADDR              (MX23_IO_BASE_ADDR + 0x05c000)
 #define MX23_PWM_BASE_ADDR              (MX23_IO_BASE_ADDR + 0x064000)
 #define MX23_TIMROT_BASE_ADDR           (MX23_IO_BASE_ADDR + 0x068000)
diff --git a/arch/arm/mach-mxs/include/mach/uncompress.h b/arch/arm/mach-mxs/include/mach/uncompress.h
index f12a1732d8b..7f8bf653964 100644
--- a/arch/arm/mach-mxs/include/mach/uncompress.h
+++ b/arch/arm/mach-mxs/include/mach/uncompress.h
@@ -20,7 +20,7 @@
 
 #include <asm/mach-types.h>
 
-static unsigned long mxs_duart_base;
+unsigned long mxs_duart_base;
 
 #define MXS_DUART(x)    (*(volatile unsigned long *)(mxs_duart_base + (x)))
 
diff --git a/arch/arm/mach-mxs/mach-mx23evk.c b/arch/arm/mach-mxs/mach-mx23evk.c
index 214e5b641bb..3c2de33803a 100644
--- a/arch/arm/mach-mxs/mach-mx23evk.c
+++ b/arch/arm/mach-mxs/mach-mx23evk.c
@@ -148,7 +148,7 @@ static void __init mx23evk_init(void)
         mx23_add_auart0();
 
         /* power on mmc slot by writing 0 to the gpio */
-        ret = gpio_request_one(MX23EVK_MMC0_SLOT_POWER, GPIOF_DIR_OUT,
+        ret = gpio_request_one(MX23EVK_MMC0_SLOT_POWER, GPIOF_OUT_INIT_LOW,
                                "mmc0-slot-power");
         if (ret)
                 pr_warn("failed to request gpio mmc0-slot-power: %d\n", ret);
diff --git a/arch/arm/mach-mxs/mach-mx28evk.c b/arch/arm/mach-mxs/mach-mx28evk.c
index bb329b9a260..eacdc6b0e70 100644
--- a/arch/arm/mach-mxs/mach-mx28evk.c
+++ b/arch/arm/mach-mxs/mach-mx28evk.c
@@ -375,13 +375,13 @@ static void __init mx28evk_init(void)
         mx28_add_mxsfb(&mx28evk_mxsfb_pdata);
 
         /* power on mmc slot by writing 0 to the gpio */
-        ret = gpio_request_one(MX28EVK_MMC0_SLOT_POWER, GPIOF_DIR_OUT,
+        ret = gpio_request_one(MX28EVK_MMC0_SLOT_POWER, GPIOF_OUT_INIT_LOW,
                                "mmc0-slot-power");
         if (ret)
                 pr_warn("failed to request gpio mmc0-slot-power: %d\n", ret);
         mx28_add_mxs_mmc(0, &mx28evk_mmc_pdata[0]);
 
-        ret = gpio_request_one(MX28EVK_MMC1_SLOT_POWER, GPIOF_DIR_OUT,
+        ret = gpio_request_one(MX28EVK_MMC1_SLOT_POWER, GPIOF_OUT_INIT_LOW,
                                "mmc1-slot-power");
         if (ret)
                 pr_warn("failed to request gpio mmc1-slot-power: %d\n", ret);
diff --git a/arch/arm/mach-nuc93x/include/mach/uncompress.h b/arch/arm/mach-nuc93x/include/mach/uncompress.h
index 73082cd61e8..381cb9baadd 100644
--- a/arch/arm/mach-nuc93x/include/mach/uncompress.h
+++ b/arch/arm/mach-nuc93x/include/mach/uncompress.h
@@ -27,7 +27,7 @@
 #define arch_decomp_wdog()
 
 #define TX_DONE (UART_LSR_TEMT | UART_LSR_THRE)
-static u32 * uart_base = (u32 *)UART0_PA;
+static u32 * const uart_base = (u32 *)UART0_PA;
 
 static void putc(int ch)
 {
diff --git a/arch/arm/mach-omap2/irq.c b/arch/arm/mach-omap2/irq.c
index 237e4530abf..3af2b7a1045 100644
--- a/arch/arm/mach-omap2/irq.c
+++ b/arch/arm/mach-omap2/irq.c
@@ -73,83 +73,18 @@ static u32 intc_bank_read_reg(struct omap_irq_bank *bank, u16 reg)
         return __raw_readl(bank->base_reg + reg);
 }
 
-static int previous_irq;
-
-/*
- * On 34xx we can get occasional spurious interrupts if the ack from
- * an interrupt handler does not get posted before we unmask. Warn about
- * the interrupt handlers that need to flush posted writes.
- */
-static int omap_check_spurious(unsigned int irq)
-{
-        u32 sir, spurious;
-
-        sir = intc_bank_read_reg(&irq_banks[0], INTC_SIR);
-        spurious = sir >> 7;
-
-        if (spurious) {
-                printk(KERN_WARNING "Spurious irq %i: 0x%08x, please flush "
-                                        "posted write for irq %i\n",
-                                        irq, sir, previous_irq);
-                return spurious;
-        }
-
-        return 0;
-}
-
 /* XXX: FIQ and additional INTC support (only MPU at the moment) */
 static void omap_ack_irq(struct irq_data *d)
 {
         intc_bank_write_reg(0x1, &irq_banks[0], INTC_CONTROL);
 }
 
-static void omap_mask_irq(struct irq_data *d)
-{
-        unsigned int irq = d->irq;
-        int offset = irq & (~(IRQ_BITS_PER_REG - 1));
-
-        if (cpu_is_omap34xx() && !cpu_is_ti816x()) {
-                int spurious = 0;
-
-                /*
-                 * INT_34XX_GPT12_IRQ is also the spurious irq. Maybe because
-                 * it is the highest irq number?
-                 */
-                if (irq == INT_34XX_GPT12_IRQ)
-                        spurious = omap_check_spurious(irq);
-
-                if (!spurious)
-                        previous_irq = irq;
-        }
-
-        irq &= (IRQ_BITS_PER_REG - 1);
-
-        intc_bank_write_reg(1 << irq, &irq_banks[0], INTC_MIR_SET0 + offset);
-}
-
-static void omap_unmask_irq(struct irq_data *d)
-{
-        unsigned int irq = d->irq;
-        int offset = irq & (~(IRQ_BITS_PER_REG - 1));
-
-        irq &= (IRQ_BITS_PER_REG - 1);
-
-        intc_bank_write_reg(1 << irq, &irq_banks[0], INTC_MIR_CLEAR0 + offset);
-}
-
 static void omap_mask_ack_irq(struct irq_data *d)
 {
-        omap_mask_irq(d);
+        irq_gc_mask_disable_reg(d);
         omap_ack_irq(d);
 }
 
-static struct irq_chip omap_irq_chip = {
-        .name           = "INTC",
-        .irq_ack        = omap_mask_ack_irq,
-        .irq_mask       = omap_mask_irq,
-        .irq_unmask     = omap_unmask_irq,
-};
-
 static void __init omap_irq_bank_init_one(struct omap_irq_bank *bank)
 {
         unsigned long tmp;
@@ -186,11 +121,31 @@ int omap_irq_pending(void)
         return 0;
 }
 
+static __init void
+omap_alloc_gc(void __iomem *base, unsigned int irq_start, unsigned int num)
+{
+        struct irq_chip_generic *gc;
+        struct irq_chip_type *ct;
+
+        gc = irq_alloc_generic_chip("INTC", 1, irq_start, base,
+                                        handle_level_irq);
+        ct = gc->chip_types;
+        ct->chip.irq_ack = omap_mask_ack_irq;
+        ct->chip.irq_mask = irq_gc_mask_disable_reg;
+        ct->chip.irq_unmask = irq_gc_unmask_enable_reg;
+
+        ct->regs.ack = INTC_CONTROL;
+        ct->regs.enable = INTC_MIR_CLEAR0;
+        ct->regs.disable = INTC_MIR_SET0;
+        irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE,
+                                IRQ_NOREQUEST | IRQ_NOPROBE, 0);
+}
+
 void __init omap_init_irq(void)
 {
         unsigned long nr_of_irqs = 0;
         unsigned int nr_banks = 0;
-        int i;
+        int i, j;
 
         for (i = 0; i < ARRAY_SIZE(irq_banks); i++) {
                 unsigned long base = 0;
@@ -215,17 +170,15 @@ void __init omap_init_irq(void)
 
                 omap_irq_bank_init_one(bank);
 
+                for (i = 0, j = 0; i < bank->nr_irqs; i += 32, j += 0x20)
+                        omap_alloc_gc(bank->base_reg + j, i, 32);
+
                 nr_of_irqs += bank->nr_irqs;
                 nr_banks++;
         }
 
         printk(KERN_INFO "Total of %ld interrupts on %d active controller%s\n",
                nr_of_irqs, nr_banks, nr_banks > 1 ? "s" : "");
-
-        for (i = 0; i < nr_of_irqs; i++) {
-                irq_set_chip_and_handler(i, &omap_irq_chip, handle_level_irq);
-                set_irq_flags(i, IRQF_VALID);
-        }
 }
 
 #ifdef CONFIG_ARCH_OMAP3
diff --git a/arch/arm/mach-orion5x/common.c b/arch/arm/mach-orion5x/common.c
index 986c3bf4e6b..0ab531d047f 100644
--- a/arch/arm/mach-orion5x/common.c
+++ b/arch/arm/mach-orion5x/common.c
@@ -13,12 +13,11 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/platform_device.h>
+#include <linux/dma-mapping.h>
 #include <linux/serial_8250.h>
 #include <linux/mbus.h>
-#include <linux/mv643xx_eth.h>
 #include <linux/mv643xx_i2c.h>
 #include <linux/ata_platform.h>
-#include <linux/spi/orion_spi.h>
 #include <net/dsa.h>
 #include <asm/page.h>
 #include <asm/setup.h>
@@ -29,11 +28,9 @@
 #include <mach/bridge-regs.h>
 #include <mach/hardware.h>
 #include <mach/orion5x.h>
-#include <plat/ehci-orion.h>
-#include <plat/mv_xor.h>
 #include <plat/orion_nand.h>
-#include <plat/orion_wdt.h>
 #include <plat/time.h>
+#include <plat/common.h>
 #include "common.h"
 
 /*****************************************************************************
@@ -70,530 +67,124 @@ void __init orion5x_map_io(void)
 
 
 /*****************************************************************************
- * EHCI
- ****************************************************************************/
-static struct orion_ehci_data orion5x_ehci_data = {
-        .dram           = &orion5x_mbus_dram_info,
-        .phy_version    = EHCI_PHY_ORION,
-};
-
-static u64 ehci_dmamask = 0xffffffffUL;
-
-
-/*****************************************************************************
  * EHCI0
  ****************************************************************************/
-static struct resource orion5x_ehci0_resources[] = {
-        {
-                .start  = ORION5X_USB0_PHYS_BASE,
-                .end    = ORION5X_USB0_PHYS_BASE + SZ_4K - 1,
-                .flags  = IORESOURCE_MEM,
-        }, {
-                .start  = IRQ_ORION5X_USB0_CTRL,
-                .end    = IRQ_ORION5X_USB0_CTRL,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device orion5x_ehci0 = {
-        .name           = "orion-ehci",
-        .id             = 0,
-        .dev            = {
-                .dma_mask               = &ehci_dmamask,
-                .coherent_dma_mask      = 0xffffffff,
-                .platform_data          = &orion5x_ehci_data,
-        },
-        .resource       = orion5x_ehci0_resources,
-        .num_resources  = ARRAY_SIZE(orion5x_ehci0_resources),
-};
-
 void __init orion5x_ehci0_init(void)
 {
-        platform_device_register(&orion5x_ehci0);
+        orion_ehci_init(&orion5x_mbus_dram_info,
+                        ORION5X_USB0_PHYS_BASE, IRQ_ORION5X_USB0_CTRL);
 }
 
 
 /*****************************************************************************
  * EHCI1
  ****************************************************************************/
-static struct resource orion5x_ehci1_resources[] = {
-        {
-                .start  = ORION5X_USB1_PHYS_BASE,
-                .end    = ORION5X_USB1_PHYS_BASE + SZ_4K - 1,
-                .flags  = IORESOURCE_MEM,
-        }, {
-                .start  = IRQ_ORION5X_USB1_CTRL,
-                .end    = IRQ_ORION5X_USB1_CTRL,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device orion5x_ehci1 = {
-        .name           = "orion-ehci",
-        .id             = 1,
-        .dev            = {
-                .dma_mask               = &ehci_dmamask,
-                .coherent_dma_mask      = 0xffffffff,
-                .platform_data          = &orion5x_ehci_data,
-        },
-        .resource       = orion5x_ehci1_resources,
-        .num_resources  = ARRAY_SIZE(orion5x_ehci1_resources),
-};
-
 void __init orion5x_ehci1_init(void)
 {
-        platform_device_register(&orion5x_ehci1);
+        orion_ehci_1_init(&orion5x_mbus_dram_info,
+                          ORION5X_USB1_PHYS_BASE, IRQ_ORION5X_USB1_CTRL);
 }
 
 
 /*****************************************************************************
- * GigE
+ * GE00
  ****************************************************************************/
-struct mv643xx_eth_shared_platform_data orion5x_eth_shared_data = {
-        .dram           = &orion5x_mbus_dram_info,
-};
-
-static struct resource orion5x_eth_shared_resources[] = {
-        {
-                .start  = ORION5X_ETH_PHYS_BASE + 0x2000,
-                .end    = ORION5X_ETH_PHYS_BASE + 0x3fff,
-                .flags  = IORESOURCE_MEM,
-        }, {
-                .start  = IRQ_ORION5X_ETH_ERR,
-                .end    = IRQ_ORION5X_ETH_ERR,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device orion5x_eth_shared = {
-        .name           = MV643XX_ETH_SHARED_NAME,
-        .id             = 0,
-        .dev            = {
-                .platform_data  = &orion5x_eth_shared_data,
-        },
-        .num_resources  = ARRAY_SIZE(orion5x_eth_shared_resources),
-        .resource       = orion5x_eth_shared_resources,
-};
-
-static struct resource orion5x_eth_resources[] = {
-        {
-                .name   = "eth irq",
-                .start  = IRQ_ORION5X_ETH_SUM,
-                .end    = IRQ_ORION5X_ETH_SUM,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device orion5x_eth = {
-        .name           = MV643XX_ETH_NAME,
-        .id             = 0,
-        .num_resources  = 1,
-        .resource       = orion5x_eth_resources,
-        .dev            = {
-                .coherent_dma_mask      = 0xffffffff,
-        },
-};
-
 void __init orion5x_eth_init(struct mv643xx_eth_platform_data *eth_data)
 {
-        eth_data->shared = &orion5x_eth_shared;
-        orion5x_eth.dev.platform_data = eth_data;
-
-        platform_device_register(&orion5x_eth_shared);
-        platform_device_register(&orion5x_eth);
+        orion_ge00_init(eth_data, &orion5x_mbus_dram_info,
+                        ORION5X_ETH_PHYS_BASE, IRQ_ORION5X_ETH_SUM,
+                        IRQ_ORION5X_ETH_ERR, orion5x_tclk);
 }
 
 
 /*****************************************************************************
  * Ethernet switch
  ****************************************************************************/
-static struct resource orion5x_switch_resources[] = {
-        {
-                .start  = 0,
-                .end    = 0,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device orion5x_switch_device = {
-        .name           = "dsa",
-        .id             = 0,
-        .num_resources  = 0,
-        .resource       = orion5x_switch_resources,
-};
-
 void __init orion5x_eth_switch_init(struct dsa_platform_data *d, int irq)
 {
-        int i;
-
-        if (irq != NO_IRQ) {
-                orion5x_switch_resources[0].start = irq;
-                orion5x_switch_resources[0].end = irq;
-                orion5x_switch_device.num_resources = 1;
-        }
-
-        d->netdev = &orion5x_eth.dev;
-        for (i = 0; i < d->nr_chips; i++)
-                d->chip[i].mii_bus = &orion5x_eth_shared.dev;
-        orion5x_switch_device.dev.platform_data = d;
-
-        platform_device_register(&orion5x_switch_device);
+        orion_ge00_switch_init(d, irq);
 }
 
 
 /*****************************************************************************
  * I2C
  ****************************************************************************/
-static struct mv64xxx_i2c_pdata orion5x_i2c_pdata = {
-        .freq_m         = 8, /* assumes 166 MHz TCLK */
-        .freq_n         = 3,
-        .timeout        = 1000, /* Default timeout of 1 second */
-};
-
-static struct resource orion5x_i2c_resources[] = {
-        {
-                .start  = I2C_PHYS_BASE,
-                .end    = I2C_PHYS_BASE + 0x1f,
-                .flags  = IORESOURCE_MEM,
-        }, {
-                .start  = IRQ_ORION5X_I2C,
-                .end    = IRQ_ORION5X_I2C,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device orion5x_i2c = {
-        .name           = MV64XXX_I2C_CTLR_NAME,
-        .id             = 0,
-        .num_resources  = ARRAY_SIZE(orion5x_i2c_resources),
-        .resource       = orion5x_i2c_resources,
-        .dev            = {
-                .platform_data  = &orion5x_i2c_pdata,
-        },
-};
-
 void __init orion5x_i2c_init(void)
 {
-        platform_device_register(&orion5x_i2c);
+        orion_i2c_init(I2C_PHYS_BASE, IRQ_ORION5X_I2C, 8);
+
 }
 
 
 /*****************************************************************************
  * SATA
  ****************************************************************************/
-static struct resource orion5x_sata_resources[] = {
-        {
-                .name   = "sata base",
-                .start  = ORION5X_SATA_PHYS_BASE,
-                .end    = ORION5X_SATA_PHYS_BASE + 0x5000 - 1,
-                .flags  = IORESOURCE_MEM,
-        }, {
-                .name   = "sata irq",
-                .start  = IRQ_ORION5X_SATA,
-                .end    = IRQ_ORION5X_SATA,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device orion5x_sata = {
-        .name           = "sata_mv",
-        .id             = 0,
-        .dev            = {
-                .coherent_dma_mask      = 0xffffffff,
-        },
-        .num_resources  = ARRAY_SIZE(orion5x_sata_resources),
-        .resource       = orion5x_sata_resources,
-};
-
 void __init orion5x_sata_init(struct mv_sata_platform_data *sata_data)
 {
-        sata_data->dram = &orion5x_mbus_dram_info;
-        orion5x_sata.dev.platform_data = sata_data;
-        platform_device_register(&orion5x_sata);
+        orion_sata_init(sata_data, &orion5x_mbus_dram_info,
+                        ORION5X_SATA_PHYS_BASE, IRQ_ORION5X_SATA);
 }
 
 
 /*****************************************************************************
  * SPI
  ****************************************************************************/
-static struct orion_spi_info orion5x_spi_plat_data = {
-        .tclk                   = 0,
-        .enable_clock_fix       = 1,
-};
-
-static struct resource orion5x_spi_resources[] = {
-        {
-                .name   = "spi base",
-                .start  = SPI_PHYS_BASE,
-                .end    = SPI_PHYS_BASE + 0x1f,
-                .flags  = IORESOURCE_MEM,
-        },
-};
-
-static struct platform_device orion5x_spi = {
-        .name           = "orion_spi",
-        .id             = 0,
-        .dev            = {
-                .platform_data  = &orion5x_spi_plat_data,
-        },
-        .num_resources  = ARRAY_SIZE(orion5x_spi_resources),
-        .resource       = orion5x_spi_resources,
-};
-
 void __init orion5x_spi_init()
 {
-        platform_device_register(&orion5x_spi);
+        orion_spi_init(SPI_PHYS_BASE, orion5x_tclk);
 }
 
 
 /*****************************************************************************
  * UART0
  ****************************************************************************/
-static struct plat_serial8250_port orion5x_uart0_data[] = {
-        {
-                .mapbase        = UART0_PHYS_BASE,
-                .membase        = (char *)UART0_VIRT_BASE,
-                .irq            = IRQ_ORION5X_UART0,
-                .flags          = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
-                .iotype         = UPIO_MEM,
-                .regshift       = 2,
-                .uartclk        = 0,
-        }, {
-        },
-};
-
-static struct resource orion5x_uart0_resources[] = {
-        {
-                .start          = UART0_PHYS_BASE,
-                .end            = UART0_PHYS_BASE + 0xff,
-                .flags          = IORESOURCE_MEM,
-        }, {
-                .start          = IRQ_ORION5X_UART0,
-                .end            = IRQ_ORION5X_UART0,
-                .flags          = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device orion5x_uart0 = {
-        .name                   = "serial8250",
-        .id                     = PLAT8250_DEV_PLATFORM,
-        .dev                    = {
-                .platform_data  = orion5x_uart0_data,
-        },
-        .resource               = orion5x_uart0_resources,
-        .num_resources          = ARRAY_SIZE(orion5x_uart0_resources),
-};
-
 void __init orion5x_uart0_init(void)
 {
-        platform_device_register(&orion5x_uart0);
+        orion_uart0_init(UART0_VIRT_BASE, UART0_PHYS_BASE,
+                         IRQ_ORION5X_UART0, orion5x_tclk);
 }
 
-
 /*****************************************************************************
  * UART1
  ****************************************************************************/
-static struct plat_serial8250_port orion5x_uart1_data[] = {
-        {
-                .mapbase        = UART1_PHYS_BASE,
-                .membase        = (char *)UART1_VIRT_BASE,
-                .irq            = IRQ_ORION5X_UART1,
-                .flags          = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
-                .iotype         = UPIO_MEM,
-                .regshift       = 2,
-                .uartclk        = 0,
-        }, {
-        },
-};
-
-static struct resource orion5x_uart1_resources[] = {
-        {
-                .start          = UART1_PHYS_BASE,
-                .end            = UART1_PHYS_BASE + 0xff,
-                .flags          = IORESOURCE_MEM,
-        }, {
-                .start          = IRQ_ORION5X_UART1,
-                .end            = IRQ_ORION5X_UART1,
-                .flags          = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device orion5x_uart1 = {
-        .name                   = "serial8250",
-        .id                     = PLAT8250_DEV_PLATFORM1,
-        .dev                    = {
-                .platform_data  = orion5x_uart1_data,
-        },
-        .resource               = orion5x_uart1_resources,
-        .num_resources          = ARRAY_SIZE(orion5x_uart1_resources),
-};
-
 void __init orion5x_uart1_init(void)
 {
-        platform_device_register(&orion5x_uart1);
+        orion_uart1_init(UART1_VIRT_BASE, UART1_PHYS_BASE,
+                         IRQ_ORION5X_UART1, orion5x_tclk);
 }
 
-
 /*****************************************************************************
  * XOR engine
  ****************************************************************************/
-struct mv_xor_platform_shared_data orion5x_xor_shared_data = {
-        .dram           = &orion5x_mbus_dram_info,
-};
-
-static struct resource orion5x_xor_shared_resources[] = {
-        {
-                .name   = "xor low",
-                .start  = ORION5X_XOR_PHYS_BASE,
-                .end    = ORION5X_XOR_PHYS_BASE + 0xff,
-                .flags  = IORESOURCE_MEM,
-        }, {
-                .name   = "xor high",
-                .start  = ORION5X_XOR_PHYS_BASE + 0x200,
-                .end    = ORION5X_XOR_PHYS_BASE + 0x2ff,
-                .flags  = IORESOURCE_MEM,
-        },
-};
-
-static struct platform_device orion5x_xor_shared = {
-        .name           = MV_XOR_SHARED_NAME,
-        .id             = 0,
-        .dev            = {
-                .platform_data  = &orion5x_xor_shared_data,
-        },
-        .num_resources  = ARRAY_SIZE(orion5x_xor_shared_resources),
-        .resource       = orion5x_xor_shared_resources,
-};
-
-static u64 orion5x_xor_dmamask = DMA_BIT_MASK(32);
-
-static struct resource orion5x_xor0_resources[] = {
-        [0] = {
-                .start  = IRQ_ORION5X_XOR0,
-                .end    = IRQ_ORION5X_XOR0,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct mv_xor_platform_data orion5x_xor0_data = {
-        .shared         = &orion5x_xor_shared,
-        .hw_id          = 0,
-        .pool_size      = PAGE_SIZE,
-};
-
-static struct platform_device orion5x_xor0_channel = {
-        .name           = MV_XOR_NAME,
-        .id             = 0,
-        .num_resources  = ARRAY_SIZE(orion5x_xor0_resources),
-        .resource       = orion5x_xor0_resources,
-        .dev            = {
-                .dma_mask               = &orion5x_xor_dmamask,
-                .coherent_dma_mask      = DMA_BIT_MASK(64),
-                .platform_data          = &orion5x_xor0_data,
-        },
-};
-
-static struct resource orion5x_xor1_resources[] = {
-        [0] = {
-                .start  = IRQ_ORION5X_XOR1,
-                .end    = IRQ_ORION5X_XOR1,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct mv_xor_platform_data orion5x_xor1_data = {
-        .shared         = &orion5x_xor_shared,
-        .hw_id          = 1,
-        .pool_size      = PAGE_SIZE,
-};
-
-static struct platform_device orion5x_xor1_channel = {
-        .name           = MV_XOR_NAME,
-        .id             = 1,
-        .num_resources  = ARRAY_SIZE(orion5x_xor1_resources),
-        .resource       = orion5x_xor1_resources,
-        .dev            = {
-                .dma_mask               = &orion5x_xor_dmamask,
-                .coherent_dma_mask      = DMA_BIT_MASK(64),
-                .platform_data          = &orion5x_xor1_data,
-        },
-};
-
 void __init orion5x_xor_init(void)
 {
-        platform_device_register(&orion5x_xor_shared);
-
-        /*
-         * two engines can't do memset simultaneously, this limitation
-         * satisfied by removing memset support from one of the engines.
-         */
-        dma_cap_set(DMA_MEMCPY, orion5x_xor0_data.cap_mask);
-        dma_cap_set(DMA_XOR, orion5x_xor0_data.cap_mask);
-        platform_device_register(&orion5x_xor0_channel);
-
-        dma_cap_set(DMA_MEMCPY, orion5x_xor1_data.cap_mask);
-        dma_cap_set(DMA_MEMSET, orion5x_xor1_data.cap_mask);
-        dma_cap_set(DMA_XOR, orion5x_xor1_data.cap_mask);
-        platform_device_register(&orion5x_xor1_channel);
+        orion_xor0_init(&orion5x_mbus_dram_info,
+                        ORION5X_XOR_PHYS_BASE,
+                        ORION5X_XOR_PHYS_BASE + 0x200,
+                        IRQ_ORION5X_XOR0, IRQ_ORION5X_XOR1);
 }
 
-static struct resource orion5x_crypto_res[] = {
-        {
-                .name   = "regs",
-                .start  = ORION5X_CRYPTO_PHYS_BASE,
-                .end    = ORION5X_CRYPTO_PHYS_BASE + 0xffff,
-                .flags  = IORESOURCE_MEM,
-        }, {
-                .name   = "sram",
-                .start  = ORION5X_SRAM_PHYS_BASE,
-                .end    = ORION5X_SRAM_PHYS_BASE + SZ_8K - 1,
-                .flags  = IORESOURCE_MEM,
-        }, {
-                .name   = "crypto interrupt",
-                .start  = IRQ_ORION5X_CESA,
-                .end    = IRQ_ORION5X_CESA,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device orion5x_crypto_device = {
-        .name           = "mv_crypto",
-        .id             = -1,
-        .num_resources  = ARRAY_SIZE(orion5x_crypto_res),
-        .resource       = orion5x_crypto_res,
-};
-
-static int __init orion5x_crypto_init(void)
+/*****************************************************************************
+ * Cryptographic Engines and Security Accelerator (CESA)
+ ****************************************************************************/
+static void __init orion5x_crypto_init(void)
 {
         int ret;
 
         ret = orion5x_setup_sram_win();
         if (ret)
-                return ret;
+                return;
 
-        return platform_device_register(&orion5x_crypto_device);
+        orion_crypto_init(ORION5X_CRYPTO_PHYS_BASE, ORION5X_SRAM_PHYS_BASE,
+                          SZ_8K, IRQ_ORION5X_CESA);
 }
 
 /*****************************************************************************
  * Watchdog
  ****************************************************************************/
-static struct orion_wdt_platform_data orion5x_wdt_data = {
-        .tclk                   = 0,
-};
-
-static struct platform_device orion5x_wdt_device = {
-        .name           = "orion_wdt",
-        .id             = -1,
-        .dev            = {
-                .platform_data  = &orion5x_wdt_data,
-        },
-        .num_resources  = 0,
-};
-
 void __init orion5x_wdt_init(void)
 {
-        orion5x_wdt_data.tclk = orion5x_tclk;
-        platform_device_register(&orion5x_wdt_device);
+        orion_wdt_init(orion5x_tclk);
 }
 
 
@@ -685,11 +276,6 @@ void __init orion5x_init(void)
         orion5x_id(&dev, &rev, &dev_name);
         printk(KERN_INFO "Orion ID: %s. TCLK=%d.\n", dev_name, orion5x_tclk);
 
-        orion5x_eth_shared_data.t_clk = orion5x_tclk;
-        orion5x_spi_plat_data.tclk = orion5x_tclk;
-        orion5x_uart0_data[0].uartclk = orion5x_tclk;
-        orion5x_uart1_data[0].uartclk = orion5x_tclk;
-
         /*
          * Setup Orion address map
          */
diff --git a/arch/arm/mach-orion5x/d2net-setup.c b/arch/arm/mach-orion5x/d2net-setup.c
index 42580757930..19cf5bf99f1 100644
--- a/arch/arm/mach-orion5x/d2net-setup.c
+++ b/arch/arm/mach-orion5x/d2net-setup.c
@@ -267,28 +267,28 @@ static struct platform_device d2net_gpio_buttons = {
  * General Setup
  ****************************************************************************/
 
-static struct orion5x_mpp_mode d2net_mpp_modes[] __initdata = {
-        {  0, MPP_GPIO },       /* Board ID (bit 0) */
-        {  1, MPP_GPIO },       /* Board ID (bit 1) */
-        {  2, MPP_GPIO },       /* Board ID (bit 2) */
-        {  3, MPP_GPIO },       /* SATA 0 power */
-        {  4, MPP_UNUSED },
-        {  5, MPP_GPIO },       /* Fan fail detection */
-        {  6, MPP_GPIO },       /* Red front LED */
-        {  7, MPP_UNUSED },
-        {  8, MPP_GPIO },       /* Rear power switch (on|auto) */
-        {  9, MPP_GPIO },       /* Rear power switch (auto|off) */
-        { 10, MPP_UNUSED },
-        { 11, MPP_UNUSED },
-        { 12, MPP_GPIO },       /* SATA 1 power */
-        { 13, MPP_UNUSED },
-        { 14, MPP_SATA_LED },   /* SATA 0 active */
-        { 15, MPP_SATA_LED },   /* SATA 1 active */
-        { 16, MPP_GPIO },       /* Blue front LED blink control */
-        { 17, MPP_UNUSED },
-        { 18, MPP_GPIO },       /* Front button (0 = Released, 1 = Pushed ) */
-        { 19, MPP_UNUSED },
-        { -1 }
+static unsigned int d2net_mpp_modes[] __initdata = {
+        MPP0_GPIO,      /* Board ID (bit 0) */
+        MPP1_GPIO,      /* Board ID (bit 1) */
+        MPP2_GPIO,      /* Board ID (bit 2) */
+        MPP3_GPIO,      /* SATA 0 power */
+        MPP4_UNUSED,
+        MPP5_GPIO,      /* Fan fail detection */
+        MPP6_GPIO,      /* Red front LED */
+        MPP7_UNUSED,
+        MPP8_GPIO,      /* Rear power switch (on|auto) */
+        MPP9_GPIO,      /* Rear power switch (auto|off) */
+        MPP10_UNUSED,
+        MPP11_UNUSED,
+        MPP12_GPIO,     /* SATA 1 power */
+        MPP13_UNUSED,
+        MPP14_SATA_LED, /* SATA 0 active */
+        MPP15_SATA_LED, /* SATA 1 active */
+        MPP16_GPIO,     /* Blue front LED blink control */
+        MPP17_UNUSED,
+        MPP18_GPIO,     /* Front button (0 = Released, 1 = Pushed ) */
+        MPP19_UNUSED,
+        0,
         /* 22: USB port 1 fuse (0 = Fail, 1 = Ok) */
         /* 23: Blue front LED off */
         /* 24: Inhibit board power off (0 = Disabled, 1 = Enabled) */
diff --git a/arch/arm/mach-orion5x/db88f5281-setup.c b/arch/arm/mach-orion5x/db88f5281-setup.c
index b7d4591214e..f95d3cb01cb 100644
--- a/arch/arm/mach-orion5x/db88f5281-setup.c
+++ b/arch/arm/mach-orion5x/db88f5281-setup.c
@@ -298,28 +298,28 @@ static struct i2c_board_info __initdata db88f5281_i2c_rtc = {
 /*****************************************************************************
  * General Setup
  ****************************************************************************/
-static struct orion5x_mpp_mode db88f5281_mpp_modes[] __initdata = {
-        {  0, MPP_GPIO },               /* USB Over Current */
-        {  1, MPP_GPIO },               /* USB Vbat input */
-        {  2, MPP_PCI_ARB },            /* PCI_REQn[2] */
-        {  3, MPP_PCI_ARB },            /* PCI_GNTn[2] */
-        {  4, MPP_PCI_ARB },            /* PCI_REQn[3] */
-        {  5, MPP_PCI_ARB },            /* PCI_GNTn[3] */
-        {  6, MPP_GPIO },               /* JP0, CON17.2 */
-        {  7, MPP_GPIO },               /* JP1, CON17.1 */
-        {  8, MPP_GPIO },               /* JP2, CON11.2 */
-        {  9, MPP_GPIO },               /* JP3, CON11.3 */
-        { 10, MPP_GPIO },               /* RTC int */
-        { 11, MPP_GPIO },               /* Baud Rate Generator */
-        { 12, MPP_GPIO },               /* PCI int 1 */
-        { 13, MPP_GPIO },               /* PCI int 2 */
-        { 14, MPP_NAND },               /* NAND_REn[2] */
-        { 15, MPP_NAND },               /* NAND_WEn[2] */
-        { 16, MPP_UART },               /* UART1_RX */
-        { 17, MPP_UART },               /* UART1_TX */
-        { 18, MPP_UART },               /* UART1_CTSn */
-        { 19, MPP_UART },               /* UART1_RTSn */
-        { -1 },
+static unsigned int db88f5281_mpp_modes[] __initdata = {
+        MPP0_GPIO,              /* USB Over Current */
+        MPP1_GPIO,              /* USB Vbat input */
+        MPP2_PCI_ARB,           /* PCI_REQn[2] */
+        MPP3_PCI_ARB,           /* PCI_GNTn[2] */
+        MPP4_PCI_ARB,           /* PCI_REQn[3] */
+        MPP5_PCI_ARB,           /* PCI_GNTn[3] */
+        MPP6_GPIO,              /* JP0, CON17.2 */
+        MPP7_GPIO,              /* JP1, CON17.1 */
+        MPP8_GPIO,              /* JP2, CON11.2 */
+        MPP9_GPIO,              /* JP3, CON11.3 */
+        MPP10_GPIO,             /* RTC int */
+        MPP11_GPIO,             /* Baud Rate Generator */
+        MPP12_GPIO,             /* PCI int 1 */
+        MPP13_GPIO,             /* PCI int 2 */
+        MPP14_NAND,             /* NAND_REn[2] */
+        MPP15_NAND,             /* NAND_WEn[2] */
+        MPP16_UART,             /* UART1_RX */
+        MPP17_UART,             /* UART1_TX */
+        MPP18_UART,             /* UART1_CTSn */
+        MPP19_UART,             /* UART1_RTSn */
+        0,
 };
 
 static void __init db88f5281_init(void)
diff --git a/arch/arm/mach-orion5x/dns323-setup.c b/arch/arm/mach-orion5x/dns323-setup.c
index 90ab022eabe..855e0e77d56 100644
--- a/arch/arm/mach-orion5x/dns323-setup.c
+++ b/arch/arm/mach-orion5x/dns323-setup.c
@@ -385,76 +385,76 @@ static struct mv_sata_platform_data dns323_sata_data = {
 /****************************************************************************
  * General Setup
  */
-static struct orion5x_mpp_mode dns323a_mpp_modes[] __initdata = {
-        {  0, MPP_PCIE_RST_OUTn },
-        {  1, MPP_GPIO },               /* right amber LED (sata ch0) */
-        {  2, MPP_GPIO },               /* left amber LED (sata ch1) */
-        {  3, MPP_UNUSED },
-        {  4, MPP_GPIO },               /* power button LED */
-        {  5, MPP_GPIO },               /* power button LED */
-        {  6, MPP_GPIO },               /* GMT G751-2f overtemp */
-        {  7, MPP_GPIO },               /* M41T80 nIRQ/OUT/SQW */
-        {  8, MPP_GPIO },               /* triggers power off */
-        {  9, MPP_GPIO },               /* power button switch */
-        { 10, MPP_GPIO },               /* reset button switch */
-        { 11, MPP_UNUSED },
-        { 12, MPP_UNUSED },
-        { 13, MPP_UNUSED },
-        { 14, MPP_UNUSED },
-        { 15, MPP_UNUSED },
-        { 16, MPP_UNUSED },
-        { 17, MPP_UNUSED },
-        { 18, MPP_UNUSED },
-        { 19, MPP_UNUSED },
-        { -1 },
+static unsigned int dns323a_mpp_modes[] __initdata = {
+        MPP0_PCIE_RST_OUTn,
+        MPP1_GPIO,              /* right amber LED (sata ch0) */
+        MPP2_GPIO,              /* left amber LED (sata ch1) */
+        MPP3_UNUSED,
+        MPP4_GPIO,              /* power button LED */
+        MPP5_GPIO,              /* power button LED */
+        MPP6_GPIO,              /* GMT G751-2f overtemp */
+        MPP7_GPIO,              /* M41T80 nIRQ/OUT/SQW */
+        MPP8_GPIO,              /* triggers power off */
+        MPP9_GPIO,              /* power button switch */
+        MPP10_GPIO,             /* reset button switch */
+        MPP11_UNUSED,
+        MPP12_UNUSED,
+        MPP13_UNUSED,
+        MPP14_UNUSED,
+        MPP15_UNUSED,
+        MPP16_UNUSED,
+        MPP17_UNUSED,
+        MPP18_UNUSED,
+        MPP19_UNUSED,
+        0,
 };
 
-static struct orion5x_mpp_mode dns323b_mpp_modes[] __initdata = {
-        {  0, MPP_UNUSED },
-        {  1, MPP_GPIO },               /* right amber LED (sata ch0) */
-        {  2, MPP_GPIO },               /* left amber LED (sata ch1) */
-        {  3, MPP_GPIO },               /* system up flag */
-        {  4, MPP_GPIO },               /* power button LED */
-        {  5, MPP_GPIO },               /* power button LED */
-        {  6, MPP_GPIO },               /* GMT G751-2f overtemp */
-        {  7, MPP_GPIO },               /* M41T80 nIRQ/OUT/SQW */
-        {  8, MPP_GPIO },               /* triggers power off */
-        {  9, MPP_GPIO },               /* power button switch */
-        { 10, MPP_GPIO },               /* reset button switch */
-        { 11, MPP_UNUSED },
-        { 12, MPP_SATA_LED },
-        { 13, MPP_SATA_LED },
-        { 14, MPP_SATA_LED },
-        { 15, MPP_SATA_LED },
-        { 16, MPP_UNUSED },
-        { 17, MPP_UNUSED },
-        { 18, MPP_UNUSED },
-        { 19, MPP_UNUSED },
-        { -1 },
+static unsigned int dns323b_mpp_modes[] __initdata = {
+        MPP0_UNUSED,
+        MPP1_GPIO,              /* right amber LED (sata ch0) */
+        MPP2_GPIO,              /* left amber LED (sata ch1) */
+        MPP3_GPIO,              /* system up flag */
+        MPP4_GPIO,              /* power button LED */
+        MPP5_GPIO,              /* power button LED */
+        MPP6_GPIO,              /* GMT G751-2f overtemp */
+        MPP7_GPIO,              /* M41T80 nIRQ/OUT/SQW */
+        MPP8_GPIO,              /* triggers power off */
+        MPP9_GPIO,              /* power button switch */
+        MPP10_GPIO,             /* reset button switch */
+        MPP11_UNUSED,
+        MPP12_SATA_LED,
+        MPP13_SATA_LED,
+        MPP14_SATA_LED,
+        MPP15_SATA_LED,
+        MPP16_UNUSED,
+        MPP17_UNUSED,
+        MPP18_UNUSED,
+        MPP19_UNUSED,
+        0,
 };
 
-static struct orion5x_mpp_mode dns323c_mpp_modes[] __initdata = {
-        {  0, MPP_GPIO },               /* ? input */
-        {  1, MPP_GPIO },               /* input power switch (0 = pressed) */
-        {  2, MPP_GPIO },               /* output power off */
-        {  3, MPP_UNUSED },             /* ? output */
-        {  4, MPP_UNUSED },             /* ? output */
-        {  5, MPP_UNUSED },             /* ? output */
-        {  6, MPP_UNUSED },             /* ? output */
-        {  7, MPP_UNUSED },             /* ? output */
-        {  8, MPP_GPIO },               /* i/o right amber LED */
-        {  9, MPP_GPIO },               /* i/o left amber LED */
-        { 10, MPP_GPIO },               /* input */
-        { 11, MPP_UNUSED },
-        { 12, MPP_SATA_LED },
-        { 13, MPP_SATA_LED },
-        { 14, MPP_SATA_LED },
-        { 15, MPP_SATA_LED },
-        { 16, MPP_UNUSED },
-        { 17, MPP_GPIO },               /* power button LED */
-        { 18, MPP_GPIO },               /* fan speed bit 0 */
-        { 19, MPP_GPIO },               /* fan speed bit 1 */
-        { -1 },
+static unsigned int dns323c_mpp_modes[] __initdata = {
+        MPP0_GPIO,              /* ? input */
+        MPP1_GPIO,              /* input power switch (0 = pressed) */
+        MPP2_GPIO,              /* output power off */
+        MPP3_UNUSED,            /* ? output */
+        MPP4_UNUSED,            /* ? output */
+        MPP5_UNUSED,            /* ? output */
+        MPP6_UNUSED,            /* ? output */
+        MPP7_UNUSED,            /* ? output */
+        MPP8_GPIO,              /* i/o right amber LED */
+        MPP9_GPIO,              /* i/o left amber LED */
+        MPP10_GPIO,             /* input */
+        MPP11_UNUSED,
+        MPP12_SATA_LED,
+        MPP13_SATA_LED,
+        MPP14_SATA_LED,
+        MPP15_SATA_LED,
+        MPP16_UNUSED,
+        MPP17_GPIO,             /* power button LED */
+        MPP18_GPIO,             /* fan speed bit 0 */
+        MPP19_GPIO,             /* fan speed bit 1 */
+        0,
 };
 
 /* Rev C1 Fan speed notes:
diff --git a/arch/arm/mach-orion5x/edmini_v2-setup.c b/arch/arm/mach-orion5x/edmini_v2-setup.c
index d037a90c216..b67cff0d4cf 100644
--- a/arch/arm/mach-orion5x/edmini_v2-setup.c
+++ b/arch/arm/mach-orion5x/edmini_v2-setup.c
@@ -180,31 +180,31 @@ static struct platform_device edmini_v2_gpio_buttons = {
 /*****************************************************************************
  * General Setup
  ****************************************************************************/
-static struct orion5x_mpp_mode edminiv2_mpp_modes[] __initdata = {
-        {  0, MPP_UNUSED },
-        {  1, MPP_UNUSED },
-        {  2, MPP_UNUSED },
-        {  3, MPP_GPIO },       /* RTC interrupt */
-        {  4, MPP_UNUSED },
-        {  5, MPP_UNUSED },
-        {  6, MPP_UNUSED },
-        {  7, MPP_UNUSED },
-        {  8, MPP_UNUSED },
-        {  9, MPP_UNUSED },
-        { 10, MPP_UNUSED },
-        { 11, MPP_UNUSED },
-        { 12, MPP_SATA_LED },   /* SATA 0 presence */
-        { 13, MPP_SATA_LED },   /* SATA 1 presence */
-        { 14, MPP_SATA_LED },   /* SATA 0 active */
-        { 15, MPP_SATA_LED },   /* SATA 1 active */
+static unsigned int edminiv2_mpp_modes[] __initdata = {
+        MPP0_UNUSED,
+        MPP1_UNUSED,
+        MPP2_UNUSED,
+        MPP3_GPIO,      /* RTC interrupt */
+        MPP4_UNUSED,
+        MPP5_UNUSED,
+        MPP6_UNUSED,
+        MPP7_UNUSED,
+        MPP8_UNUSED,
+        MPP9_UNUSED,
+        MPP10_UNUSED,
+        MPP11_UNUSED,
+        MPP12_SATA_LED, /* SATA 0 presence */
+        MPP13_SATA_LED, /* SATA 1 presence */
+        MPP14_SATA_LED, /* SATA 0 active */
+        MPP15_SATA_LED, /* SATA 1 active */
         /* 16: Power LED control (0 = On, 1 = Off) */
-        { 16, MPP_GPIO },
+        MPP16_GPIO,
         /* 17: Power LED control select (0 = CPLD, 1 = GPIO16) */
-        { 17, MPP_GPIO },
+        MPP17_GPIO,
         /* 18: Power button status (0 = Released, 1 = Pressed) */
-        { 18, MPP_GPIO },
-        { 19, MPP_UNUSED },
-        { -1 }
+        MPP18_GPIO,
+        MPP19_UNUSED,
+        0,
 };
 
 static void __init edmini_v2_init(void)
diff --git a/arch/arm/mach-orion5x/kurobox_pro-setup.c b/arch/arm/mach-orion5x/kurobox_pro-setup.c
index 47497c76162..c0eb6462633 100644
--- a/arch/arm/mach-orion5x/kurobox_pro-setup.c
+++ b/arch/arm/mach-orion5x/kurobox_pro-setup.c
@@ -315,28 +315,28 @@ static void kurobox_pro_power_off(void)
 /*****************************************************************************
  * General Setup
  ****************************************************************************/
-static struct orion5x_mpp_mode kurobox_pro_mpp_modes[] __initdata = {
-        {  0, MPP_UNUSED },
-        {  1, MPP_UNUSED },
-        {  2, MPP_GPIO },               /* GPIO Micon */
-        {  3, MPP_GPIO },               /* GPIO Rtc */
-        {  4, MPP_UNUSED },
-        {  5, MPP_UNUSED },
-        {  6, MPP_NAND },               /* NAND Flash REn */
-        {  7, MPP_NAND },               /* NAND Flash WEn */
-        {  8, MPP_UNUSED },
-        {  9, MPP_UNUSED },
-        { 10, MPP_UNUSED },
-        { 11, MPP_UNUSED },
-        { 12, MPP_SATA_LED },           /* SATA 0 presence */
-        { 13, MPP_SATA_LED },           /* SATA 1 presence */
-        { 14, MPP_SATA_LED },           /* SATA 0 active */
-        { 15, MPP_SATA_LED },           /* SATA 1 active */
-        { 16, MPP_UART },               /* UART1 RXD */
-        { 17, MPP_UART },               /* UART1 TXD */
-        { 18, MPP_UART },               /* UART1 CTSn */
-        { 19, MPP_UART },               /* UART1 RTSn */
-        { -1 },
+static unsigned int kurobox_pro_mpp_modes[] __initdata = {
+        MPP0_UNUSED,
+        MPP1_UNUSED,
+        MPP2_GPIO,              /* GPIO Micon */
+        MPP3_GPIO,              /* GPIO Rtc */
+        MPP4_UNUSED,
+        MPP5_UNUSED,
+        MPP6_NAND,              /* NAND Flash REn */
+        MPP7_NAND,              /* NAND Flash WEn */
+        MPP8_UNUSED,
+        MPP9_UNUSED,
+        MPP10_UNUSED,
+        MPP11_UNUSED,
+        MPP12_SATA_LED,         /* SATA 0 presence */
+        MPP13_SATA_LED,         /* SATA 1 presence */
+        MPP14_SATA_LED,         /* SATA 0 active */
+        MPP15_SATA_LED,         /* SATA 1 active */
+        MPP16_UART,             /* UART1 RXD */
+        MPP17_UART,             /* UART1 TXD */
+        MPP18_UART,             /* UART1 CTSn */
+        MPP19_UART,             /* UART1 RTSn */
+        0,
 };
 
 static void __init kurobox_pro_init(void)
diff --git a/arch/arm/mach-orion5x/ls-chl-setup.c b/arch/arm/mach-orion5x/ls-chl-setup.c
index 6ae12aa6d75..5065803ca82 100644
--- a/arch/arm/mach-orion5x/ls-chl-setup.c
+++ b/arch/arm/mach-orion5x/ls-chl-setup.c
@@ -251,28 +251,28 @@ static struct platform_device lschl_fan_device = {
  * GPIO Data
  ****************************************************************************/
 
-static struct orion5x_mpp_mode lschl_mpp_modes[] __initdata = {
-        {  0, MPP_GPIO }, /* LED POWER */
-        {  1, MPP_GPIO }, /* HDD POWER */
-        {  2, MPP_GPIO }, /* LED ALARM */
-        {  3, MPP_GPIO }, /* LED INFO */
-        {  4, MPP_UNUSED },
-        {  5, MPP_UNUSED },
-        {  6, MPP_GPIO }, /* FAN LOCK */
-        {  7, MPP_GPIO }, /* SW INIT */
-        {  8, MPP_GPIO }, /* SW POWER */
-        {  9, MPP_GPIO }, /* USB POWER */
-        { 10, MPP_GPIO }, /* SW AUTO POWER */
-        { 11, MPP_UNUSED },
-        { 12, MPP_UNUSED },
-        { 13, MPP_UNUSED },
-        { 14, MPP_GPIO }, /* FAN HIGH */
-        { 15, MPP_GPIO }, /* SW FUNC */
-        { 16, MPP_GPIO }, /* FAN LOW */
-        { 17, MPP_GPIO }, /* LED FUNC */
-        { 18, MPP_UNUSED },
-        { 19, MPP_UNUSED },
-        { -1 },
+static unsigned int lschl_mpp_modes[] __initdata = {
+        MPP0_GPIO, /* LED POWER */
+        MPP1_GPIO, /* HDD POWER */
+        MPP2_GPIO, /* LED ALARM */
+        MPP3_GPIO, /* LED INFO */
+        MPP4_UNUSED,
+        MPP5_UNUSED,
+        MPP6_GPIO, /* FAN LOCK */
+        MPP7_GPIO, /* SW INIT */
+        MPP8_GPIO, /* SW POWER */
+        MPP9_GPIO, /* USB POWER */
+        MPP10_GPIO, /* SW AUTO POWER */
+        MPP11_UNUSED,
+        MPP12_UNUSED,
+        MPP13_UNUSED,
+        MPP14_GPIO, /* FAN HIGH */
+        MPP15_GPIO, /* SW FUNC */
+        MPP16_GPIO, /* FAN LOW */
+        MPP17_GPIO, /* LED FUNC */
+        MPP18_UNUSED,
+        MPP19_UNUSED,
+        0,
 };
 
 static void __init lschl_init(void)
diff --git a/arch/arm/mach-orion5x/ls_hgl-setup.c b/arch/arm/mach-orion5x/ls_hgl-setup.c
index 7adafd79cf9..8503d0a42d4 100644
--- a/arch/arm/mach-orion5x/ls_hgl-setup.c
+++ b/arch/arm/mach-orion5x/ls_hgl-setup.c
@@ -200,28 +200,28 @@ static void ls_hgl_power_off(void)
 
 #define LS_HGL_GPIO_HDD_POWER   1
 
-static struct orion5x_mpp_mode ls_hgl_mpp_modes[] __initdata = {
-        {  0, MPP_GPIO }, /* LED_PWR */
-        {  1, MPP_GPIO }, /* HDD_PWR */
-        {  2, MPP_GPIO }, /* LED_ALARM */
-        {  3, MPP_GPIO }, /* LED_INFO */
-        {  4, MPP_UNUSED },
-        {  5, MPP_UNUSED },
-        {  6, MPP_GPIO }, /* FAN_LCK */
-        {  7, MPP_GPIO }, /* INIT */
-        {  8, MPP_GPIO }, /* POWER */
-        {  9, MPP_GPIO }, /* USB_PWR */
-        { 10, MPP_GPIO }, /* AUTO_POWER */
-        { 11, MPP_UNUSED }, /* LED_ETH (dummy) */
-        { 12, MPP_UNUSED },
-        { 13, MPP_UNUSED },
-        { 14, MPP_UNUSED },
-        { 15, MPP_GPIO }, /* FUNC */
-        { 16, MPP_UNUSED },
-        { 17, MPP_GPIO }, /* LED_FUNC */
-        { 18, MPP_UNUSED },
-        { 19, MPP_UNUSED },
-        { -1 },
+static unsigned int ls_hgl_mpp_modes[] __initdata = {
+        MPP0_GPIO, /* LED_PWR */
+        MPP1_GPIO, /* HDD_PWR */
+        MPP2_GPIO, /* LED_ALARM */
+        MPP3_GPIO, /* LED_INFO */
+        MPP4_UNUSED,
+        MPP5_UNUSED,
+        MPP6_GPIO, /* FAN_LCK */
+        MPP7_GPIO, /* INIT */
+        MPP8_GPIO, /* POWER */
+        MPP9_GPIO, /* USB_PWR */
+        MPP10_GPIO, /* AUTO_POWER */
+        MPP11_UNUSED, /* LED_ETH (dummy) */
+        MPP12_UNUSED,
+        MPP13_UNUSED,
+        MPP14_UNUSED,
+        MPP15_GPIO, /* FUNC */
+        MPP16_UNUSED,
+        MPP17_GPIO, /* LED_FUNC */
+        MPP18_UNUSED,
+        MPP19_UNUSED,
+        0,
 };
 
 static void __init ls_hgl_init(void)
diff --git a/arch/arm/mach-orion5x/lsmini-setup.c b/arch/arm/mach-orion5x/lsmini-setup.c
index 869958f5c39..9c82723c05c 100644
--- a/arch/arm/mach-orion5x/lsmini-setup.c
+++ b/arch/arm/mach-orion5x/lsmini-setup.c
@@ -201,28 +201,28 @@ static void lsmini_power_off(void)
 #define LSMINI_GPIO_HDD_POWER0  1
 #define LSMINI_GPIO_HDD_POWER1  19
 
-static struct orion5x_mpp_mode lsmini_mpp_modes[] __initdata = {
-        {  0, MPP_UNUSED }, /* LED_RESERVE1 (unused) */
-        {  1, MPP_GPIO }, /* HDD_PWR */
-        {  2, MPP_GPIO }, /* LED_ALARM */
-        {  3, MPP_GPIO }, /* LED_INFO */
-        {  4, MPP_UNUSED },
-        {  5, MPP_UNUSED },
-        {  6, MPP_UNUSED },
-        {  7, MPP_UNUSED },
-        {  8, MPP_UNUSED },
-        {  9, MPP_GPIO }, /* LED_FUNC */
-        { 10, MPP_UNUSED },
-        { 11, MPP_UNUSED }, /* LED_ETH (dummy) */
-        { 12, MPP_UNUSED },
-        { 13, MPP_UNUSED },
-        { 14, MPP_GPIO }, /* LED_PWR */
-        { 15, MPP_GPIO }, /* FUNC */
-        { 16, MPP_GPIO }, /* USB_PWR */
-        { 17, MPP_GPIO }, /* AUTO_POWER */
-        { 18, MPP_GPIO }, /* POWER */
-        { 19, MPP_GPIO }, /* HDD_PWR1 */
-        { -1 },
+static unsigned int lsmini_mpp_modes[] __initdata = {
+        MPP0_UNUSED, /* LED_RESERVE1 (unused) */
+        MPP1_GPIO, /* HDD_PWR */
+        MPP2_GPIO, /* LED_ALARM */
+        MPP3_GPIO, /* LED_INFO */
+        MPP4_UNUSED,
+        MPP5_UNUSED,
+        MPP6_UNUSED,
+        MPP7_UNUSED,
+        MPP8_UNUSED,
+        MPP9_GPIO, /* LED_FUNC */
+        MPP10_UNUSED,
+        MPP11_UNUSED, /* LED_ETH (dummy) */
+        MPP12_UNUSED,
+        MPP13_UNUSED,
+        MPP14_GPIO, /* LED_PWR */
+        MPP15_GPIO, /* FUNC */
+        MPP16_GPIO, /* USB_PWR */
+        MPP17_GPIO, /* AUTO_POWER */
+        MPP18_GPIO, /* POWER */
+        MPP19_GPIO, /* HDD_PWR1 */
+        0,
 };
 
 static void __init lsmini_init(void)
diff --git a/arch/arm/mach-orion5x/mpp.c b/arch/arm/mach-orion5x/mpp.c
index 2288207726e..f12c41b98d4 100644
--- a/arch/arm/mach-orion5x/mpp.c
+++ b/arch/arm/mach-orion5x/mpp.c
@@ -12,154 +12,34 @@
 #include <linux/init.h>
 #include <linux/mbus.h>
 #include <linux/io.h>
-#include <asm/gpio.h>
 #include <mach/hardware.h>
-#include "common.h"
+#include <plat/mpp.h>
 #include "mpp.h"
+#include "common.h"
 
-static int is_5181l(void)
-{
-        u32 dev;
-        u32 rev;
-
-        orion5x_pcie_id(&dev, &rev);
-
-        return !!(dev == MV88F5181_DEV_ID && rev >= MV88F5181L_REV_A0);
-}
-
-static int is_5182(void)
+static unsigned int __init orion5x_variant(void)
 {
         u32 dev;
         u32 rev;
 
         orion5x_pcie_id(&dev, &rev);
 
-        return !!(dev == MV88F5182_DEV_ID);
-}
+        if (dev == MV88F5181_DEV_ID && rev >= MV88F5181L_REV_A0)
+                return MPP_F5181_MASK;
 
-static int is_5281(void)
-{
-        u32 dev;
-        u32 rev;
+        if (dev == MV88F5182_DEV_ID)
+                return MPP_F5182_MASK;
 
-        orion5x_pcie_id(&dev, &rev);
+        if (dev == MV88F5281_DEV_ID)
+                return MPP_F5281_MASK;
 
-        return !!(dev == MV88F5281_DEV_ID);
+        printk(KERN_ERR "MPP setup: unknown orion5x variant "
+               "(dev %#x rev %#x)\n", dev, rev);
+        return 0;
 }
 
-static int __init determine_type_encoding(int mpp, enum orion5x_mpp_type type)
+void __init orion5x_mpp_conf(unsigned int *mpp_list)
 {
-        switch (type) {
-        case MPP_UNUSED:
-        case MPP_GPIO:
-                if (mpp == 0)
-                        return 3;
-                if (mpp >= 1 && mpp <= 15)
-                        return 0;
-                if (mpp >= 16 && mpp <= 19) {
-                        if (is_5182())
-                                return 5;
-                        if (type == MPP_UNUSED)
-                                return 0;
-                }
-                return -1;
-
-        case MPP_PCIE_RST_OUTn:
-                if (mpp == 0)
-                        return 0;
-                return -1;
-
-        case MPP_PCI_ARB:
-                if (mpp >= 0 && mpp <= 7)
-                        return 2;
-                return -1;
-
-        case MPP_PCI_PMEn:
-                if (mpp == 2)
-                        return 3;
-                return -1;
-
-        case MPP_GIGE:
-                if (mpp >= 8 && mpp <= 19)
-                        return 1;
-                return -1;
-
-        case MPP_NAND:
-                if (is_5182() || is_5281()) {
-                        if (mpp >= 4 && mpp <= 7)
-                                return 4;
-                        if (mpp >= 12 && mpp <= 17)
-                                return 4;
-                }
-                return -1;
-
-        case MPP_PCI_CLK:
-                if (is_5181l() && mpp >= 6 && mpp <= 7)
-                        return 5;
-                return -1;
-
-        case MPP_SATA_LED:
-                if (is_5182()) {
-                        if (mpp >= 4 && mpp <= 7)
-                                return 5;
-                        if (mpp >= 12 && mpp <= 15)
-                                return 5;
-                }
-                return -1;
-
-        case MPP_UART:
-                if (mpp >= 16 && mpp <= 19)
-                        return 0;
-                return -1;
-        }
-
-        printk(KERN_INFO "unknown MPP type %d\n", type);
-
-        return -1;
-}
-
-void __init orion5x_mpp_conf(struct orion5x_mpp_mode *mode)
-{
-        u32 mpp_0_7_ctrl = readl(MPP_0_7_CTRL);
-        u32 mpp_8_15_ctrl = readl(MPP_8_15_CTRL);
-        u32 mpp_16_19_ctrl = readl(MPP_16_19_CTRL);
-
-        for ( ; mode->mpp >= 0; mode++) {
-                u32 *reg;
-                int num_type;
-                int shift;
-
-                if (mode->mpp >= 0 && mode->mpp <= 7)
-                        reg = &mpp_0_7_ctrl;
-                else if (mode->mpp >= 8 && mode->mpp <= 15)
-                        reg = &mpp_8_15_ctrl;
-                else if (mode->mpp >= 16 && mode->mpp <= 19)
-                        reg = &mpp_16_19_ctrl;
-                else {
-                        printk(KERN_ERR "orion5x_mpp_conf: invalid MPP "
-                                        "(%d)\n", mode->mpp);
-                        continue;
-                }
-
-                num_type = determine_type_encoding(mode->mpp, mode->type);
-                if (num_type < 0) {
-                        printk(KERN_ERR "orion5x_mpp_conf: invalid MPP "
-                                        "combination (%d, %d)\n", mode->mpp,
-                                        mode->type);
-                        continue;
-                }
-
-                shift = (mode->mpp & 7) << 2;
-                *reg &= ~(0xf << shift);
-                *reg |= (num_type & 0xf) << shift;
-
-                if (mode->type == MPP_UNUSED && (mode->mpp < 16 || is_5182()))
-                        orion_gpio_set_unused(mode->mpp);
-
-                orion_gpio_set_valid(mode->mpp, !!(mode->type == MPP_GPIO));
-        }
-
-        writel(mpp_0_7_ctrl, MPP_0_7_CTRL);
-        writel(mpp_8_15_ctrl, MPP_8_15_CTRL);
-        writel(mpp_16_19_ctrl, MPP_16_19_CTRL);
+        orion_mpp_conf(mpp_list, orion5x_variant(),
+                       MPP_MAX, ORION5X_DEV_BUS_VIRT_BASE);
 }
diff --git a/arch/arm/mach-orion5x/mpp.h b/arch/arm/mach-orion5x/mpp.h
index 290e610dc01..eac68978a2c 100644
--- a/arch/arm/mach-orion5x/mpp.h
+++ b/arch/arm/mach-orion5x/mpp.h
@@ -1,74 +1,129 @@
 #ifndef __ARCH_ORION5X_MPP_H
 #define __ARCH_ORION5X_MPP_H
 
-enum orion5x_mpp_type {
-        /*
-         * This MPP is unused.
-         */
-        MPP_UNUSED,
-
-        /*
-         * This MPP pin is used as a generic GPIO pin.  Valid for
-         * MPPs 0-15 and device bus data pins 16-31.  On 5182, also
-         * valid for MPPs 16-19.
-         */
-        MPP_GPIO,
-
-        /*
-         * This MPP is used as PCIe_RST_OUTn pin.  Valid for
-         * MPP 0 only.
-         */
-        MPP_PCIE_RST_OUTn,
-
-        /*
-         * This MPP is used as PCI arbiter pin (REQn/GNTn).
-         * Valid for MPPs 0-7 only.
-         */
-        MPP_PCI_ARB,
-
-        /*
-         * This MPP is used as PCI_PMEn pin.  Valid for MPP 2 only.
-         */
-        MPP_PCI_PMEn,
-
-        /*
-         * This MPP is used as GigE half-duplex (COL, CRS) or GMII
-         * (RXERR, CRS, TXERR, TXD[7:4], RXD[7:4]) pin.  Valid for
-         * MPPs 8-19 only.
-         */
-        MPP_GIGE,
-
-        /*
-         * This MPP is used as NAND REn/WEn pin.  Valid for MPPs
-         * 4-7 and 12-17 only, and only on the 5181l/5182/5281.
-         */
-        MPP_NAND,
-
-        /*
-         * This MPP is used as a PCI clock output pin.  Valid for
-         * MPPs 6-7 only, and only on the 5181l.
-         */
-        MPP_PCI_CLK,
-
-        /*
-         * This MPP is used as a SATA presence/activity LED.
-         * Valid for MPPs 4-7 and 12-15 only, and only on the 5182.
-         */
-        MPP_SATA_LED,
-
-        /*
-         * This MPP is used as UART1 RXD/TXD/CTSn/RTSn pin.
-         * Valid for MPPs 16-19 only.
-         */
-        MPP_UART,
-};
-
-struct orion5x_mpp_mode {
-        int                     mpp;
-        enum orion5x_mpp_type   type;
-};
-
-void orion5x_mpp_conf(struct orion5x_mpp_mode *mode);
+#define MPP(_num, _sel, _in, _out, _F5181l, _F5182, _F5281) ( \
+        /* MPP number */                ((_num) & 0xff) | \
+        /* MPP select value */          (((_sel) & 0xf) << 8) | \
+        /* may be input signal */       ((!!(_in)) << 12) | \
+        /* may be output signal */      ((!!(_out)) << 13) | \
+        /* available on F5181l */       ((!!(_F5181l)) << 14) | \
+        /* available on F5182 */        ((!!(_F5182)) << 15) | \
+        /* available on F5281 */        ((!!(_F5281)) << 16))
 
+                                /* num sel  i  o  5181 5182 5281 */
+
+#define MPP_F5181_MASK          MPP(0,  0x0, 0, 0, 1,   0,   0)
+#define MPP_F5182_MASK          MPP(0,  0x0, 0, 0, 0,   1,   0)
+#define MPP_F5281_MASK          MPP(0,  0x0, 0, 0, 0,   0,   1)
+
+#define MPP0_UNUSED             MPP(0,  0x3, 0, 0, 1,   1,   1)
+#define MPP0_GPIO               MPP(0,  0x3, 1, 1, 1,   1,   1)
+#define MPP0_PCIE_RST_OUTn      MPP(0,  0x0, 0, 0, 1,   1,   1)
+#define MPP0_PCI_ARB            MPP(0,  0x2, 0, 0, 1,   1,   1)
+
+#define MPP1_UNUSED             MPP(1,  0x0, 0, 0, 1,   1,   1)
+#define MPP1_GPIO               MPP(1,  0x0, 1, 1, 1,   1,   1)
+#define MPP1_PCI_ARB            MPP(1,  0x2, 0, 0, 1,   1,   1)
+
+#define MPP2_UNUSED             MPP(2,  0x0, 0, 0, 1,   1,   1)
+#define MPP2_GPIO               MPP(2,  0x0, 1, 1, 1,   1,   1)
+#define MPP2_PCI_ARB            MPP(2,  0x2, 0, 0, 1,   1,   1)
+#define MPP2_PCI_PMEn           MPP(2,  0x3, 0, 0, 1,   1,   1)
+
+#define MPP3_UNUSED             MPP(3,  0x0, 0, 0, 1,   1,   1)
+#define MPP3_GPIO               MPP(3,  0x0, 1, 1, 1,   1,   1)
+#define MPP3_PCI_ARB            MPP(3,  0x2, 0, 0, 1,   1,   1)
+
+#define MPP4_UNUSED             MPP(4,  0x0, 0, 0, 1,   1,   1)
+#define MPP4_GPIO               MPP(4,  0x0, 1, 1, 1,   1,   1)
+#define MPP4_PCI_ARB            MPP(4,  0x2, 0, 0, 1,   1,   1)
+#define MPP4_NAND               MPP(4,  0x4, 0, 0, 0,   1,   1)
+#define MPP4_SATA_LED           MPP(4,  0x5, 0, 0, 0,   1,   0)
+
+#define MPP5_UNUSED             MPP(5,  0x0, 0, 0, 1,   1,   1)
+#define MPP5_GPIO               MPP(5,  0x0, 1, 1, 1,   1,   1)
+#define MPP5_PCI_ARB            MPP(5,  0x2, 0, 0, 1,   1,   1)
+#define MPP5_NAND               MPP(5,  0x4, 0, 0, 0,   1,   1)
+#define MPP5_SATA_LED           MPP(5,  0x5, 0, 0, 0,   1,   0)
+
+#define MPP6_UNUSED             MPP(6,  0x0, 0, 0, 1,   1,   1)
+#define MPP6_GPIO               MPP(6,  0x0, 1, 1, 1,   1,   1)
+#define MPP6_PCI_ARB            MPP(6,  0x2, 0, 0, 1,   1,   1)
+#define MPP6_NAND               MPP(6,  0x4, 0, 0, 0,   1,   1)
+#define MPP6_PCI_CLK            MPP(6,  0x5, 0, 0, 1,   0,   0)
+#define MPP6_SATA_LED           MPP(6,  0x5, 0, 0, 0,   1,   0)
+
+#define MPP7_UNUSED             MPP(7,  0x0, 0, 0, 1,   1,   1)
+#define MPP7_GPIO               MPP(7,  0x0, 1, 1, 1,   1,   1)
+#define MPP7_PCI_ARB            MPP(7,  0x2, 0, 0, 1,   1,   1)
+#define MPP7_NAND               MPP(7,  0x4, 0, 0, 0,   1,   1)
+#define MPP7_PCI_CLK            MPP(7,  0x5, 0, 0, 1,   0,   0)
+#define MPP7_SATA_LED           MPP(7,  0x5, 0, 0, 0,   1,   0)
+
+#define MPP8_UNUSED             MPP(8,  0x0, 0, 0, 1,   1,   1)
+#define MPP8_GPIO               MPP(8,  0x0, 1, 1, 1,   1,   1)
+#define MPP8_GIGE               MPP(8,  0x1, 0, 0, 1,   1,   1)
+
+#define MPP9_UNUSED             MPP(9,  0x0, 0, 0, 1,   1,   1)
+#define MPP9_GPIO               MPP(9,  0x0, 0, 0, 1,   1,   1)
+#define MPP9_GIGE               MPP(9,  0x1, 1, 1, 1,   1,   1)
+
+#define MPP10_UNUSED            MPP(10, 0x0, 0, 0, 1,   1,   1)
+#define MPP10_GPIO              MPP(10, 0x0, 1, 1, 1,   1,   1)
+#define MPP10_GIGE              MPP(10, 0x1, 0, 0, 1,   1,   1)
+
+#define MPP11_UNUSED            MPP(11, 0x0, 0, 0, 1,   1,   1)
+#define MPP11_GPIO              MPP(11, 0x0, 1, 1, 1,   1,   1)
+#define MPP11_GIGE              MPP(11, 0x1, 0, 0, 1,   1,   1)
+
+#define MPP12_UNUSED            MPP(12, 0x0, 0, 0, 1,   1,   1)
+#define MPP12_GPIO              MPP(12, 0x0, 1, 1, 1,   1,   1)
+#define MPP12_GIGE              MPP(12, 0x1, 0, 0, 1,   1,   1)
+#define MPP12_NAND              MPP(12, 0x4, 0, 0, 0,   1,   1)
+#define MPP12_SATA_LED          MPP(12, 0x5, 0, 0, 0,   1,   0)
+
+#define MPP13_UNUSED            MPP(13, 0x0, 0, 0, 1,   1,   1)
+#define MPP13_GPIO              MPP(13, 0x0, 1, 1, 1,   1,   1)
+#define MPP13_GIGE              MPP(13, 0x1, 0, 0, 1,   1,   1)
+#define MPP13_NAND              MPP(13, 0x4, 0, 0, 0,   1,   1)
+#define MPP13_SATA_LED          MPP(13, 0x5, 0, 0, 0,   1,   0)
+
+#define MPP14_UNUSED            MPP(14, 0x0, 0, 0, 1,   1,   1)
+#define MPP14_GPIO              MPP(14, 0x0, 1, 1, 1,   1,   1)
+#define MPP14_GIGE              MPP(14, 0x1, 0, 0, 1,   1,   1)
+#define MPP14_NAND              MPP(14, 0x4, 0, 0, 0,   1,   1)
+#define MPP14_SATA_LED          MPP(14, 0x5, 0, 0, 0,   1,   0)
+
+#define MPP15_UNUSED            MPP(15, 0x0, 0, 0, 1,   1,   1)
+#define MPP15_GPIO              MPP(15, 0x0, 1, 1, 1,   1,   1)
+#define MPP15_GIGE              MPP(15, 0x1, 0, 0, 1,   1,   1)
+#define MPP15_NAND              MPP(15, 0x4, 0, 0, 0,   1,   1)
+#define MPP15_SATA_LED          MPP(15, 0x5, 0, 0, 0,   1,   0)
+
+#define MPP16_UNUSED            MPP(16, 0x0, 0, 0, 1,   1,   1)
+#define MPP16_GPIO              MPP(16, 0x5, 1, 1, 0,   1,   0)
+#define MPP16_GIGE              MPP(16, 0x1, 0, 0, 1,   1,   1)
+#define MPP16_NAND              MPP(16, 0x4, 0, 0, 0,   1,   1)
+#define MPP16_UART              MPP(16, 0x0, 0, 0, 0,   1,   1)
+
+#define MPP17_UNUSED            MPP(17, 0x0, 0, 0, 1,   1,   1)
+#define MPP17_GPIO              MPP(17, 0x5, 1, 1, 0,   1,   0)
+#define MPP17_GIGE              MPP(17, 0x1, 0, 0, 1,   1,   1)
+#define MPP17_NAND              MPP(17, 0x4, 0, 0, 0,   1,   1)
+#define MPP17_UART              MPP(17, 0x0, 0, 0, 0,   1,   1)
+
+#define MPP18_UNUSED            MPP(18, 0x0, 0, 0, 1,   1,   1)
+#define MPP18_GPIO              MPP(18, 0x5, 1, 1, 0,   1,   0)
+#define MPP18_GIGE              MPP(18, 0x1, 0, 0, 1,   1,   1)
+#define MPP18_UART              MPP(18, 0x0, 0, 0, 0,   1,   1)
+
+#define MPP19_UNUSED            MPP(19, 0x0, 0, 0, 1,   1,   1)
+#define MPP19_GPIO              MPP(19, 0x5, 1, 1, 0,   1,   0)
+#define MPP19_GIGE              MPP(19, 0x1, 0, 0, 1,   1,   1)
+#define MPP19_UART              MPP(19, 0x0, 0, 0, 0,   1,   1)
+
+#define MPP_MAX                 19
+
+void orion5x_mpp_conf(unsigned int *mpp_list);
 
 #endif
diff --git a/arch/arm/mach-orion5x/mss2-setup.c b/arch/arm/mach-orion5x/mss2-setup.c
index b43b208153c..59263b73d1e 100644
--- a/arch/arm/mach-orion5x/mss2-setup.c
+++ b/arch/arm/mach-orion5x/mss2-setup.c
@@ -193,28 +193,28 @@ static void mss2_power_off(void)
 /****************************************************************************
  * General Setup
  ****************************************************************************/
-static struct orion5x_mpp_mode mss2_mpp_modes[] __initdata = {
-        {  0, MPP_GPIO },               /* Power LED */
-        {  1, MPP_GPIO },               /* Error LED */
-        {  2, MPP_UNUSED },
-        {  3, MPP_GPIO },               /* RTC interrupt */
-        {  4, MPP_GPIO },               /* HDD ind. (Single/Dual)*/
-        {  5, MPP_GPIO },               /* HD0 5V control */
-        {  6, MPP_GPIO },               /* HD0 12V control */
-        {  7, MPP_GPIO },               /* HD1 5V control */
-        {  8, MPP_GPIO },               /* HD1 12V control */
-        {  9, MPP_UNUSED },
-        { 10, MPP_GPIO },               /* Fan control */
-        { 11, MPP_GPIO },               /* Power button */
-        { 12, MPP_GPIO },               /* Reset button */
-        { 13, MPP_UNUSED },
-        { 14, MPP_SATA_LED },           /* SATA 0 active */
-        { 15, MPP_SATA_LED },           /* SATA 1 active */
-        { 16, MPP_UNUSED },
-        { 17, MPP_UNUSED },
-        { 18, MPP_UNUSED },
-        { 19, MPP_UNUSED },
-        { -1 },
+static unsigned int mss2_mpp_modes[] __initdata = {
+        MPP0_GPIO,              /* Power LED */
+        MPP1_GPIO,              /* Error LED */
+        MPP2_UNUSED,
+        MPP3_GPIO,              /* RTC interrupt */
+        MPP4_GPIO,              /* HDD ind. (Single/Dual)*/
+        MPP5_GPIO,              /* HD0 5V control */
+        MPP6_GPIO,              /* HD0 12V control */
+        MPP7_GPIO,              /* HD1 5V control */
+        MPP8_GPIO,              /* HD1 12V control */
+        MPP9_UNUSED,
+        MPP10_GPIO,             /* Fan control */
+        MPP11_GPIO,             /* Power button */
+        MPP12_GPIO,             /* Reset button */
+        MPP13_UNUSED,
+        MPP14_SATA_LED,         /* SATA 0 active */
+        MPP15_SATA_LED,         /* SATA 1 active */
+        MPP16_UNUSED,
+        MPP17_UNUSED,
+        MPP18_UNUSED,
+        MPP19_UNUSED,
+        0,
 };
 
 static void __init mss2_init(void)
diff --git a/arch/arm/mach-orion5x/mv2120-setup.c b/arch/arm/mach-orion5x/mv2120-setup.c
index c55d071707f..63ff10c3c46 100644
--- a/arch/arm/mach-orion5x/mv2120-setup.c
+++ b/arch/arm/mach-orion5x/mv2120-setup.c
@@ -108,28 +108,28 @@ static struct platform_device mv2120_button_device = {
 /****************************************************************************
  * General Setup
  ****************************************************************************/
-static struct orion5x_mpp_mode mv2120_mpp_modes[] __initdata = {
-        {  0, MPP_GPIO },               /* Sys status LED */
-        {  1, MPP_GPIO },               /* Sys error LED */
-        {  2, MPP_GPIO },               /* OverTemp interrupt */
-        {  3, MPP_GPIO },               /* RTC interrupt */
-        {  4, MPP_GPIO },               /* V_LED 5V */
-        {  5, MPP_GPIO },               /* V_LED 3.3V */
-        {  6, MPP_UNUSED },
-        {  7, MPP_UNUSED },
-        {  8, MPP_GPIO },               /* SATA 0 fail LED */
-        {  9, MPP_GPIO },               /* SATA 1 fail LED */
-        { 10, MPP_UNUSED },
-        { 11, MPP_UNUSED },
-        { 12, MPP_SATA_LED },           /* SATA 0 presence */
-        { 13, MPP_SATA_LED },           /* SATA 1 presence */
-        { 14, MPP_SATA_LED },           /* SATA 0 active */
-        { 15, MPP_SATA_LED },           /* SATA 1 active */
-        { 16, MPP_UNUSED },
-        { 17, MPP_GPIO },               /* Reset button */
-        { 18, MPP_GPIO },               /* Power button */
-        { 19, MPP_GPIO },               /* Power off */
-        { -1 },
+static unsigned int mv2120_mpp_modes[] __initdata = {
+        MPP0_GPIO,              /* Sys status LED */
+        MPP1_GPIO,              /* Sys error LED */
+        MPP2_GPIO,              /* OverTemp interrupt */
+        MPP3_GPIO,              /* RTC interrupt */
+        MPP4_GPIO,              /* V_LED 5V */
+        MPP5_GPIO,              /* V_LED 3.3V */
+        MPP6_UNUSED,
+        MPP7_UNUSED,
+        MPP8_GPIO,              /* SATA 0 fail LED */
+        MPP9_GPIO,              /* SATA 1 fail LED */
+        MPP10_UNUSED,
+        MPP11_UNUSED,
+        MPP12_SATA_LED,         /* SATA 0 presence */
+        MPP13_SATA_LED,         /* SATA 1 presence */
+        MPP14_SATA_LED,         /* SATA 0 active */
+        MPP15_SATA_LED,         /* SATA 1 active */
+        MPP16_UNUSED,
+        MPP17_GPIO,             /* Reset button */
+        MPP18_GPIO,             /* Power button */
+        MPP19_GPIO,             /* Power off */
+        0,
 };
 
 static struct i2c_board_info __initdata mv2120_i2c_rtc = {
diff --git a/arch/arm/mach-orion5x/net2big-setup.c b/arch/arm/mach-orion5x/net2big-setup.c
index a5930f83958..e43b39cc7fe 100644
--- a/arch/arm/mach-orion5x/net2big-setup.c
+++ b/arch/arm/mach-orion5x/net2big-setup.c
@@ -339,28 +339,28 @@ static struct platform_device net2big_gpio_buttons = {
  * General Setup
  ****************************************************************************/
 
-static struct orion5x_mpp_mode net2big_mpp_modes[] __initdata = {
-        {  0, MPP_GPIO },       /* Raid mode (bit 0) */
-        {  1, MPP_GPIO },       /* USB port 2 fuse (0 = Fail, 1 = Ok) */
-        {  2, MPP_GPIO },       /* Raid mode (bit 1) */
-        {  3, MPP_GPIO },       /* Board ID (bit 0) */
-        {  4, MPP_GPIO },       /* Fan activity (0 = Off, 1 = On) */
-        {  5, MPP_GPIO },       /* Fan fail detection */
-        {  6, MPP_GPIO },       /* Red front LED (0 = Off, 1 = On) */
-        {  7, MPP_GPIO },       /* Disable initial blinking on front LED */
-        {  8, MPP_GPIO },       /* Rear power switch (on|auto) */
-        {  9, MPP_GPIO },       /* Rear power switch (auto|off) */
-        { 10, MPP_GPIO },       /* SATA 1 red LED (0 = Off, 1 = On) */
-        { 11, MPP_GPIO },       /* SATA 0 red LED (0 = Off, 1 = On) */
-        { 12, MPP_GPIO },       /* Board ID (bit 1) */
-        { 13, MPP_GPIO },       /* SATA 1 blue LED blink control */
-        { 14, MPP_SATA_LED },
-        { 15, MPP_SATA_LED },
-        { 16, MPP_GPIO },       /* Blue front LED control */
-        { 17, MPP_GPIO },       /* SATA 0 blue LED blink control */
-        { 18, MPP_GPIO },       /* Front button (0 = Released, 1 = Pushed ) */
-        { 19, MPP_GPIO },       /* SATA{0,1} power On/Off request */
-        { -1 }
+static unsigned int net2big_mpp_modes[] __initdata = {
+        MPP0_GPIO,      /* Raid mode (bit 0) */
+        MPP1_GPIO,      /* USB port 2 fuse (0 = Fail, 1 = Ok) */
+        MPP2_GPIO,      /* Raid mode (bit 1) */
+        MPP3_GPIO,      /* Board ID (bit 0) */
+        MPP4_GPIO,      /* Fan activity (0 = Off, 1 = On) */
+        MPP5_GPIO,      /* Fan fail detection */
+        MPP6_GPIO,      /* Red front LED (0 = Off, 1 = On) */
+        MPP7_GPIO,      /* Disable initial blinking on front LED */
+        MPP8_GPIO,      /* Rear power switch (on|auto) */
+        MPP9_GPIO,      /* Rear power switch (auto|off) */
+        MPP10_GPIO,     /* SATA 1 red LED (0 = Off, 1 = On) */
+        MPP11_GPIO,     /* SATA 0 red LED (0 = Off, 1 = On) */
+        MPP12_GPIO,     /* Board ID (bit 1) */
+        MPP13_GPIO,     /* SATA 1 blue LED blink control */
+        MPP14_SATA_LED,
+        MPP15_SATA_LED,
+        MPP16_GPIO,     /* Blue front LED control */
+        MPP17_GPIO,     /* SATA 0 blue LED blink control */
+        MPP18_GPIO,     /* Front button (0 = Released, 1 = Pushed ) */
+        MPP19_GPIO,     /* SATA{0,1} power On/Off request */
+        0,
         /* 22: USB port 1 fuse (0 = Fail, 1 = Ok) */
         /* 23: SATA 0 power status */
         /* 24: Board power off */
diff --git a/arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c b/arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c
index 34310ab56e2..9eec7c2375e 100644
--- a/arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c
+++ b/arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c
@@ -64,28 +64,28 @@ static struct platform_device rd88f5181l_fxo_nor_boot_flash = {
 /*****************************************************************************
  * General Setup
  ****************************************************************************/
-static struct orion5x_mpp_mode rd88f5181l_fxo_mpp_modes[] __initdata = {
-        {  0, MPP_GPIO },               /* LED1 CardBus LED (front panel) */
-        {  1, MPP_GPIO },               /* PCI_intA */
-        {  2, MPP_GPIO },               /* Hard Reset / Factory Init*/
-        {  3, MPP_GPIO },               /* FXS or DAA select */
-        {  4, MPP_GPIO },               /* LED6 - phone LED (front panel) */
-        {  5, MPP_GPIO },               /* LED5 - phone LED (front panel) */
-        {  6, MPP_PCI_CLK },            /* CPU PCI refclk */
-        {  7, MPP_PCI_CLK },            /* PCI/PCIe refclk */
-        {  8, MPP_GPIO },               /* CardBus reset */
-        {  9, MPP_GPIO },               /* GE_RXERR */
-        { 10, MPP_GPIO },               /* LED2 MiniPCI LED (front panel) */
-        { 11, MPP_GPIO },               /* Lifeline control */
-        { 12, MPP_GIGE },               /* GE_TXD[4] */
-        { 13, MPP_GIGE },               /* GE_TXD[5] */
-        { 14, MPP_GIGE },               /* GE_TXD[6] */
-        { 15, MPP_GIGE },               /* GE_TXD[7] */
-        { 16, MPP_GIGE },               /* GE_RXD[4] */
-        { 17, MPP_GIGE },               /* GE_RXD[5] */
-        { 18, MPP_GIGE },               /* GE_RXD[6] */
-        { 19, MPP_GIGE },               /* GE_RXD[7] */
-        { -1 },
+static unsigned int rd88f5181l_fxo_mpp_modes[] __initdata = {
+        MPP0_GPIO,              /* LED1 CardBus LED (front panel) */
+        MPP1_GPIO,              /* PCI_intA */
+        MPP2_GPIO,              /* Hard Reset / Factory Init*/
+        MPP3_GPIO,              /* FXS or DAA select */
+        MPP4_GPIO,              /* LED6 - phone LED (front panel) */
+        MPP5_GPIO,              /* LED5 - phone LED (front panel) */
+        MPP6_PCI_CLK,           /* CPU PCI refclk */
+        MPP7_PCI_CLK,           /* PCI/PCIe refclk */
+        MPP8_GPIO,              /* CardBus reset */
+        MPP9_GPIO,              /* GE_RXERR */
+        MPP10_GPIO,             /* LED2 MiniPCI LED (front panel) */
+        MPP11_GPIO,             /* Lifeline control */
+        MPP12_GIGE,             /* GE_TXD[4] */
+        MPP13_GIGE,             /* GE_TXD[5] */
+        MPP14_GIGE,             /* GE_TXD[6] */
+        MPP15_GIGE,             /* GE_TXD[7] */
+        MPP16_GIGE,             /* GE_RXD[4] */
+        MPP17_GIGE,             /* GE_RXD[5] */
+        MPP18_GIGE,             /* GE_RXD[6] */
+        MPP19_GIGE,             /* GE_RXD[7] */
+        0,
 };
 
 static struct mv643xx_eth_platform_data rd88f5181l_fxo_eth_data = {
diff --git a/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c b/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c
index c1f79fa014e..0cc90bbfd32 100644
--- a/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c
+++ b/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c
@@ -65,28 +65,28 @@ static struct platform_device rd88f5181l_ge_nor_boot_flash = {
 /*****************************************************************************
  * General Setup
  ****************************************************************************/
-static struct orion5x_mpp_mode rd88f5181l_ge_mpp_modes[] __initdata = {
-        {  0, MPP_GPIO },               /* LED1 */
-        {  1, MPP_GPIO },               /* LED5 */
-        {  2, MPP_GPIO },               /* LED4 */
-        {  3, MPP_GPIO },               /* LED3 */
-        {  4, MPP_GPIO },               /* PCI_intA */
-        {  5, MPP_GPIO },               /* RTC interrupt */
-        {  6, MPP_PCI_CLK },            /* CPU PCI refclk */
-        {  7, MPP_PCI_CLK },            /* PCI/PCIe refclk */
-        {  8, MPP_GPIO },               /* 88e6131 interrupt */
-        {  9, MPP_GPIO },               /* GE_RXERR */
-        { 10, MPP_GPIO },               /* PCI_intB */
-        { 11, MPP_GPIO },               /* LED2 */
-        { 12, MPP_GIGE },               /* GE_TXD[4] */
-        { 13, MPP_GIGE },               /* GE_TXD[5] */
-        { 14, MPP_GIGE },               /* GE_TXD[6] */
-        { 15, MPP_GIGE },               /* GE_TXD[7] */
-        { 16, MPP_GIGE },               /* GE_RXD[4] */
-        { 17, MPP_GIGE },               /* GE_RXD[5] */
-        { 18, MPP_GIGE },               /* GE_RXD[6] */
-        { 19, MPP_GIGE },               /* GE_RXD[7] */
-        { -1 },
+static unsigned int rd88f5181l_ge_mpp_modes[] __initdata = {
+        MPP0_GPIO,              /* LED1 */
+        MPP1_GPIO,              /* LED5 */
+        MPP2_GPIO,              /* LED4 */
+        MPP3_GPIO,              /* LED3 */
+        MPP4_GPIO,              /* PCI_intA */
+        MPP5_GPIO,              /* RTC interrupt */
+        MPP6_PCI_CLK,           /* CPU PCI refclk */
+        MPP7_PCI_CLK,           /* PCI/PCIe refclk */
+        MPP8_GPIO,              /* 88e6131 interrupt */
+        MPP9_GPIO,              /* GE_RXERR */
+        MPP10_GPIO,             /* PCI_intB */
+        MPP11_GPIO,             /* LED2 */
+        MPP12_GIGE,             /* GE_TXD[4] */
+        MPP13_GIGE,             /* GE_TXD[5] */
+        MPP14_GIGE,             /* GE_TXD[6] */
+        MPP15_GIGE,             /* GE_TXD[7] */
+        MPP16_GIGE,             /* GE_RXD[4] */
+        MPP17_GIGE,             /* GE_RXD[5] */
+        MPP18_GIGE,             /* GE_RXD[6] */
+        MPP19_GIGE,             /* GE_RXD[7] */
+        0,
 };
 
 static struct mv643xx_eth_platform_data rd88f5181l_ge_eth_data = {
diff --git a/arch/arm/mach-orion5x/rd88f5182-setup.c b/arch/arm/mach-orion5x/rd88f5182-setup.c
index 4fc46772a08..48da39b9bdb 100644
--- a/arch/arm/mach-orion5x/rd88f5182-setup.c
+++ b/arch/arm/mach-orion5x/rd88f5182-setup.c
@@ -241,28 +241,28 @@ static struct mv_sata_platform_data rd88f5182_sata_data = {
 /*****************************************************************************
  * General Setup
  ****************************************************************************/
-static struct orion5x_mpp_mode rd88f5182_mpp_modes[] __initdata = {
-        {  0, MPP_GPIO },               /* Debug Led */
-        {  1, MPP_GPIO },               /* Reset Switch */
-        {  2, MPP_UNUSED },
-        {  3, MPP_GPIO },               /* RTC Int */
-        {  4, MPP_GPIO },
-        {  5, MPP_GPIO },
-        {  6, MPP_GPIO },               /* PCI_intA */
-        {  7, MPP_GPIO },               /* PCI_intB */
-        {  8, MPP_UNUSED },
-        {  9, MPP_UNUSED },
-        { 10, MPP_UNUSED },
-        { 11, MPP_UNUSED },
-        { 12, MPP_SATA_LED },           /* SATA 0 presence */
-        { 13, MPP_SATA_LED },           /* SATA 1 presence */
-        { 14, MPP_SATA_LED },           /* SATA 0 active */
-        { 15, MPP_SATA_LED },           /* SATA 1 active */
-        { 16, MPP_UNUSED },
-        { 17, MPP_UNUSED },
-        { 18, MPP_UNUSED },
-        { 19, MPP_UNUSED },
-        { -1 },
+static unsigned int rd88f5182_mpp_modes[] __initdata = {
+        MPP0_GPIO,              /* Debug Led */
+        MPP1_GPIO,              /* Reset Switch */
+        MPP2_UNUSED,
+        MPP3_GPIO,              /* RTC Int */
+        MPP4_GPIO,
+        MPP5_GPIO,
+        MPP6_GPIO,              /* PCI_intA */
+        MPP7_GPIO,              /* PCI_intB */
+        MPP8_UNUSED,
+        MPP9_UNUSED,
+        MPP10_UNUSED,
+        MPP11_UNUSED,
+        MPP12_SATA_LED,         /* SATA 0 presence */
+        MPP13_SATA_LED,         /* SATA 1 presence */
+        MPP14_SATA_LED,         /* SATA 0 active */
+        MPP15_SATA_LED,         /* SATA 1 active */
+        MPP16_UNUSED,
+        MPP17_UNUSED,
+        MPP18_UNUSED,
+        MPP19_UNUSED,
+        0,
 };
 
 static void __init rd88f5182_init(void)
diff --git a/arch/arm/mach-orion5x/rd88f6183ap-ge-setup.c b/arch/arm/mach-orion5x/rd88f6183ap-ge-setup.c
index b080c6966d1..ad2eba9286a 100644
--- a/arch/arm/mach-orion5x/rd88f6183ap-ge-setup.c
+++ b/arch/arm/mach-orion5x/rd88f6183ap-ge-setup.c
@@ -27,7 +27,6 @@
 #include <asm/mach/pci.h>
 #include <mach/orion5x.h>
 #include "common.h"
-#include "mpp.h"
 
 static struct mv643xx_eth_platform_data rd88f6183ap_ge_eth_data = {
         .phy_addr       = -1,
diff --git a/arch/arm/mach-orion5x/terastation_pro2-setup.c b/arch/arm/mach-orion5x/terastation_pro2-setup.c
index 61600414391..29ce826c3c2 100644
--- a/arch/arm/mach-orion5x/terastation_pro2-setup.c
+++ b/arch/arm/mach-orion5x/terastation_pro2-setup.c
@@ -295,28 +295,28 @@ static void tsp2_power_off(void)
 /*****************************************************************************
  * General Setup
  ****************************************************************************/
-static struct orion5x_mpp_mode tsp2_mpp_modes[] __initdata = {
-        {  0, MPP_PCIE_RST_OUTn },
-        {  1, MPP_UNUSED },
-        {  2, MPP_UNUSED },
-        {  3, MPP_UNUSED },
-        {  4, MPP_NAND },               /* BOOT NAND Flash REn */
-        {  5, MPP_NAND },               /* BOOT NAND Flash WEn */
-        {  6, MPP_NAND },               /* BOOT NAND Flash HREn[0] */
-        {  7, MPP_NAND },               /* BOOT NAND Flash WEn[0] */
-        {  8, MPP_GPIO },               /* MICON int */
-        {  9, MPP_GPIO },               /* RTC int */
-        { 10, MPP_UNUSED },
-        { 11, MPP_GPIO },               /* PCI Int A */
-        { 12, MPP_UNUSED },
-        { 13, MPP_GPIO },               /* UPS on UART0 enable */
-        { 14, MPP_GPIO },               /* UPS low battery detection */
-        { 15, MPP_UNUSED },
-        { 16, MPP_UART },               /* UART1 RXD */
-        { 17, MPP_UART },               /* UART1 TXD */
-        { 18, MPP_UART },               /* UART1 CTSn */
-        { 19, MPP_UART },               /* UART1 RTSn */
-        { -1 },
+static unsigned int tsp2_mpp_modes[] __initdata = {
+        MPP0_PCIE_RST_OUTn,
+        MPP1_UNUSED,
+        MPP2_UNUSED,
+        MPP3_UNUSED,
+        MPP4_NAND,              /* BOOT NAND Flash REn */
+        MPP5_NAND,              /* BOOT NAND Flash WEn */
+        MPP6_NAND,              /* BOOT NAND Flash HREn[0] */
+        MPP7_NAND,              /* BOOT NAND Flash WEn[0] */
+        MPP8_GPIO,              /* MICON int */
+        MPP9_GPIO,              /* RTC int */
+        MPP10_UNUSED,
+        MPP11_GPIO,             /* PCI Int A */
+        MPP12_UNUSED,
+        MPP13_GPIO,             /* UPS on UART0 enable */
+        MPP14_GPIO,             /* UPS low battery detection */
+        MPP15_UNUSED,
+        MPP16_UART,             /* UART1 RXD */
+        MPP17_UART,             /* UART1 TXD */
+        MPP18_UART,             /* UART1 CTSn */
+        MPP19_UART,             /* UART1 RTSn */
+        0,
 };
 
 static void __init tsp2_init(void)
diff --git a/arch/arm/mach-orion5x/ts209-setup.c b/arch/arm/mach-orion5x/ts209-setup.c
index e6d64494d3d..47162fd5f04 100644
--- a/arch/arm/mach-orion5x/ts209-setup.c
+++ b/arch/arm/mach-orion5x/ts209-setup.c
@@ -244,28 +244,28 @@ static struct mv_sata_platform_data qnap_ts209_sata_data = {
 
  * General Setup
  ****************************************************************************/
-static struct orion5x_mpp_mode ts209_mpp_modes[] __initdata = {
-        {  0, MPP_UNUSED },
-        {  1, MPP_GPIO },               /* USB copy button */
-        {  2, MPP_GPIO },               /* Load defaults button */
-        {  3, MPP_GPIO },               /* GPIO RTC */
-        {  4, MPP_UNUSED },
-        {  5, MPP_UNUSED },
-        {  6, MPP_GPIO },               /* PCI Int A */
-        {  7, MPP_GPIO },               /* PCI Int B */
-        {  8, MPP_UNUSED },
-        {  9, MPP_UNUSED },
-        { 10, MPP_UNUSED },
-        { 11, MPP_UNUSED },
-        { 12, MPP_SATA_LED },           /* SATA 0 presence */
-        { 13, MPP_SATA_LED },           /* SATA 1 presence */
-        { 14, MPP_SATA_LED },           /* SATA 0 active */
-        { 15, MPP_SATA_LED },           /* SATA 1 active */
-        { 16, MPP_UART },               /* UART1 RXD */
-        { 17, MPP_UART },               /* UART1 TXD */
-        { 18, MPP_GPIO },               /* SW_RST */
-        { 19, MPP_UNUSED },
-        { -1 },
+static unsigned int ts209_mpp_modes[] __initdata = {
+        MPP0_UNUSED,
+        MPP1_GPIO,              /* USB copy button */
+        MPP2_GPIO,              /* Load defaults button */
+        MPP3_GPIO,              /* GPIO RTC */
+        MPP4_UNUSED,
+        MPP5_UNUSED,
+        MPP6_GPIO,              /* PCI Int A */
+        MPP7_GPIO,              /* PCI Int B */
+        MPP8_UNUSED,
+        MPP9_UNUSED,
+        MPP10_UNUSED,
+        MPP11_UNUSED,
+        MPP12_SATA_LED,         /* SATA 0 presence */
+        MPP13_SATA_LED,         /* SATA 1 presence */
+        MPP14_SATA_LED,         /* SATA 0 active */
+        MPP15_SATA_LED,         /* SATA 1 active */
+        MPP16_UART,             /* UART1 RXD */
+        MPP17_UART,             /* UART1 TXD */
+        MPP18_GPIO,             /* SW_RST */
+        MPP19_UNUSED,
+        0,
 };
 
 static void __init qnap_ts209_init(void)
diff --git a/arch/arm/mach-orion5x/ts409-setup.c b/arch/arm/mach-orion5x/ts409-setup.c
index 9eac8192d92..5aacc7ac5cf 100644
--- a/arch/arm/mach-orion5x/ts409-setup.c
+++ b/arch/arm/mach-orion5x/ts409-setup.c
@@ -242,28 +242,28 @@ static struct platform_device qnap_ts409_button_device = {
 /*****************************************************************************
  * General Setup
  ****************************************************************************/
-static struct orion5x_mpp_mode ts409_mpp_modes[] __initdata = {
-        {  0, MPP_UNUSED },
-        {  1, MPP_UNUSED },
-        {  2, MPP_UNUSED },
-        {  3, MPP_UNUSED },
-        {  4, MPP_GPIO },               /* HDD 1 status */
-        {  5, MPP_GPIO },               /* HDD 2 status */
-        {  6, MPP_GPIO },               /* HDD 3 status */
-        {  7, MPP_GPIO },               /* HDD 4 status */
-        {  8, MPP_UNUSED },
-        {  9, MPP_UNUSED },
-        { 10, MPP_GPIO },               /* RTC int */
-        { 11, MPP_UNUSED },
-        { 12, MPP_UNUSED },
-        { 13, MPP_UNUSED },
-        { 14, MPP_GPIO },               /* SW_RST */
-        { 15, MPP_GPIO },               /* USB copy button */
-        { 16, MPP_UART },               /* UART1 RXD */
-        { 17, MPP_UART },               /* UART1 TXD */
-        { 18, MPP_UNUSED },
-        { 19, MPP_UNUSED },
-        { -1 },
+static unsigned int ts409_mpp_modes[] __initdata = {
+        MPP0_UNUSED,
+        MPP1_UNUSED,
+        MPP2_UNUSED,
+        MPP3_UNUSED,
+        MPP4_GPIO,              /* HDD 1 status */
+        MPP5_GPIO,              /* HDD 2 status */
+        MPP6_GPIO,              /* HDD 3 status */
+        MPP7_GPIO,              /* HDD 4 status */
+        MPP8_UNUSED,
+        MPP9_UNUSED,
+        MPP10_GPIO,             /* RTC int */
+        MPP11_UNUSED,
+        MPP12_UNUSED,
+        MPP13_UNUSED,
+        MPP14_GPIO,             /* SW_RST */
+        MPP15_GPIO,             /* USB copy button */
+        MPP16_UART,             /* UART1 RXD */
+        MPP17_UART,             /* UART1 TXD */
+        MPP18_UNUSED,
+        MPP19_UNUSED,
+        0,
 };
 
 static void __init qnap_ts409_init(void)
diff --git a/arch/arm/mach-orion5x/ts78xx-setup.c b/arch/arm/mach-orion5x/ts78xx-setup.c
index edb1dd2d161..6b7b54116f3 100644
--- a/arch/arm/mach-orion5x/ts78xx-setup.c
+++ b/arch/arm/mach-orion5x/ts78xx-setup.c
@@ -557,27 +557,27 @@ static struct kobj_attribute ts78xx_fpga_attr =
 /*****************************************************************************
  * General Setup
  ****************************************************************************/
-static struct orion5x_mpp_mode ts78xx_mpp_modes[] __initdata = {
-        {  0, MPP_UNUSED },
-        {  1, MPP_GPIO },               /* JTAG Clock */
-        {  2, MPP_GPIO },               /* JTAG Data In */
-        {  3, MPP_GPIO },               /* Lat ECP2 256 FPGA - PB2B */
-        {  4, MPP_GPIO },               /* JTAG Data Out */
-        {  5, MPP_GPIO },               /* JTAG TMS */
-        {  6, MPP_GPIO },               /* Lat ECP2 256 FPGA - PB31A_CLK4+ */
-        {  7, MPP_GPIO },               /* Lat ECP2 256 FPGA - PB22B */
-        {  8, MPP_UNUSED },
-        {  9, MPP_UNUSED },
-        { 10, MPP_UNUSED },
-        { 11, MPP_UNUSED },
-        { 12, MPP_UNUSED },
-        { 13, MPP_UNUSED },
-        { 14, MPP_UNUSED },
-        { 15, MPP_UNUSED },
-        { 16, MPP_UART },
-        { 17, MPP_UART },
-        { 18, MPP_UART },
-        { 19, MPP_UART },
+static unsigned int ts78xx_mpp_modes[] __initdata = {
+        MPP0_UNUSED,
+        MPP1_GPIO,              /* JTAG Clock */
+        MPP2_GPIO,              /* JTAG Data In */
+        MPP3_GPIO,              /* Lat ECP2 256 FPGA - PB2B */
+        MPP4_GPIO,              /* JTAG Data Out */
+        MPP5_GPIO,              /* JTAG TMS */
+        MPP6_GPIO,              /* Lat ECP2 256 FPGA - PB31A_CLK4+ */
+        MPP7_GPIO,              /* Lat ECP2 256 FPGA - PB22B */
+        MPP8_UNUSED,
+        MPP9_UNUSED,
+        MPP10_UNUSED,
+        MPP11_UNUSED,
+        MPP12_UNUSED,
+        MPP13_UNUSED,
+        MPP14_UNUSED,
+        MPP15_UNUSED,
+        MPP16_UART,
+        MPP17_UART,
+        MPP18_UART,
+        MPP19_UART,
         /*
          * MPP[20] PCI Clock Out 1
          * MPP[21] PCI Clock Out 0
@@ -586,7 +586,7 @@ static struct orion5x_mpp_mode ts78xx_mpp_modes[] __initdata = {
          * MPP[24] Unused
          * MPP[25] Unused
          */
-        { -1 },
+        0,
 };
 
 static void __init ts78xx_init(void)
diff --git a/arch/arm/mach-orion5x/wnr854t-setup.c b/arch/arm/mach-orion5x/wnr854t-setup.c
index 4e5216be074..444a1c7fdfd 100644
--- a/arch/arm/mach-orion5x/wnr854t-setup.c
+++ b/arch/arm/mach-orion5x/wnr854t-setup.c
@@ -24,28 +24,28 @@
 #include "common.h"
 #include "mpp.h"
 
-static struct orion5x_mpp_mode wnr854t_mpp_modes[] __initdata = {
-        {  0, MPP_GPIO },               /* Power LED green (0=on) */
-        {  1, MPP_GPIO },               /* Reset Button (0=off) */
-        {  2, MPP_GPIO },               /* Power LED blink (0=off) */
-        {  3, MPP_GPIO },               /* WAN Status LED amber (0=off) */
-        {  4, MPP_GPIO },               /* PCI int */
-        {  5, MPP_GPIO },               /* ??? */
-        {  6, MPP_GPIO },               /* ??? */
-        {  7, MPP_GPIO },               /* ??? */
-        {  8, MPP_UNUSED },             /* ??? */
-        {  9, MPP_GIGE },               /* GE_RXERR */
-        { 10, MPP_UNUSED },             /* ??? */
-        { 11, MPP_UNUSED },             /* ??? */
-        { 12, MPP_GIGE },               /* GE_TXD[4] */
-        { 13, MPP_GIGE },               /* GE_TXD[5] */
-        { 14, MPP_GIGE },               /* GE_TXD[6] */
-        { 15, MPP_GIGE },               /* GE_TXD[7] */
-        { 16, MPP_GIGE },               /* GE_RXD[4] */
-        { 17, MPP_GIGE },               /* GE_RXD[5] */
-        { 18, MPP_GIGE },               /* GE_RXD[6] */
-        { 19, MPP_GIGE },               /* GE_RXD[7] */
-        { -1 },
+static unsigned int wnr854t_mpp_modes[] __initdata = {
+        MPP0_GPIO,              /* Power LED green (0=on) */
+        MPP1_GPIO,              /* Reset Button (0=off) */
+        MPP2_GPIO,              /* Power LED blink (0=off) */
+        MPP3_GPIO,              /* WAN Status LED amber (0=off) */
+        MPP4_GPIO,              /* PCI int */
+        MPP5_GPIO,              /* ??? */
+        MPP6_GPIO,              /* ??? */
+        MPP7_GPIO,              /* ??? */
+        MPP8_UNUSED,            /* ??? */
+        MPP9_GIGE,              /* GE_RXERR */
+        MPP10_UNUSED,           /* ??? */
+        MPP11_UNUSED,           /* ??? */
+        MPP12_GIGE,             /* GE_TXD[4] */
+        MPP13_GIGE,             /* GE_TXD[5] */
+        MPP14_GIGE,             /* GE_TXD[6] */
+        MPP15_GIGE,             /* GE_TXD[7] */
+        MPP16_GIGE,             /* GE_RXD[4] */
+        MPP17_GIGE,             /* GE_RXD[5] */
+        MPP18_GIGE,             /* GE_RXD[6] */
+        MPP19_GIGE,             /* GE_RXD[7] */
+        0,
 };
 
 /*
diff --git a/arch/arm/mach-orion5x/wrt350n-v2-setup.c b/arch/arm/mach-orion5x/wrt350n-v2-setup.c
index fab79d09cc5..d1952be0ae1 100644
--- a/arch/arm/mach-orion5x/wrt350n-v2-setup.c
+++ b/arch/arm/mach-orion5x/wrt350n-v2-setup.c
@@ -101,28 +101,28 @@ static struct platform_device wrt350n_v2_button_device = {
 /*
  * General setup
  */
-static struct orion5x_mpp_mode wrt350n_v2_mpp_modes[] __initdata = {
-        {  0, MPP_GPIO },               /* Power LED green (0=on) */
-        {  1, MPP_GPIO },               /* Security LED (0=on) */
-        {  2, MPP_GPIO },               /* Internal Button (0=on) */
-        {  3, MPP_GPIO },               /* Reset Button (0=on) */
-        {  4, MPP_GPIO },               /* PCI int */
-        {  5, MPP_GPIO },               /* Power LED orange (0=on) */
-        {  6, MPP_GPIO },               /* USB LED (0=on) */
-        {  7, MPP_GPIO },               /* Wireless LED (0=on) */
-        {  8, MPP_UNUSED },             /* ??? */
-        {  9, MPP_GIGE },               /* GE_RXERR */
-        { 10, MPP_UNUSED },             /* ??? */
-        { 11, MPP_UNUSED },             /* ??? */
-        { 12, MPP_GIGE },               /* GE_TXD[4] */
-        { 13, MPP_GIGE },               /* GE_TXD[5] */
-        { 14, MPP_GIGE },               /* GE_TXD[6] */
-        { 15, MPP_GIGE },               /* GE_TXD[7] */
-        { 16, MPP_GIGE },               /* GE_RXD[4] */
-        { 17, MPP_GIGE },               /* GE_RXD[5] */
-        { 18, MPP_GIGE },               /* GE_RXD[6] */
-        { 19, MPP_GIGE },               /* GE_RXD[7] */
-        { -1 },
+static unsigned int wrt350n_v2_mpp_modes[] __initdata = {
+        MPP0_GPIO,              /* Power LED green (0=on) */
+        MPP1_GPIO,              /* Security LED (0=on) */
+        MPP2_GPIO,              /* Internal Button (0=on) */
+        MPP3_GPIO,              /* Reset Button (0=on) */
+        MPP4_GPIO,              /* PCI int */
+        MPP5_GPIO,              /* Power LED orange (0=on) */
+        MPP6_GPIO,              /* USB LED (0=on) */
+        MPP7_GPIO,              /* Wireless LED (0=on) */
+        MPP8_UNUSED,            /* ??? */
+        MPP9_GIGE,              /* GE_RXERR */
+        MPP10_UNUSED,           /* ??? */
+        MPP11_UNUSED,           /* ??? */
+        MPP12_GIGE,             /* GE_TXD[4] */
+        MPP13_GIGE,             /* GE_TXD[5] */
+        MPP14_GIGE,             /* GE_TXD[6] */
+        MPP15_GIGE,             /* GE_TXD[7] */
+        MPP16_GIGE,             /* GE_RXD[4] */
+        MPP17_GIGE,             /* GE_RXD[5] */
+        MPP18_GIGE,             /* GE_RXD[6] */
+        MPP19_GIGE,             /* GE_RXD[7] */
+        0,
 };
 
 /*
diff --git a/arch/arm/mach-pxa/include/mach/uncompress.h b/arch/arm/mach-pxa/include/mach/uncompress.h
index 759b851ec98..5519a34b667 100644
--- a/arch/arm/mach-pxa/include/mach/uncompress.h
+++ b/arch/arm/mach-pxa/include/mach/uncompress.h
@@ -16,9 +16,9 @@
 #define BTUART_BASE     (0x40200000)
 #define STUART_BASE     (0x40700000)
 
-static unsigned long uart_base;
-static unsigned int uart_shift;
-static unsigned int uart_is_pxa;
+unsigned long uart_base;
+unsigned int uart_shift;
+unsigned int uart_is_pxa;
 
 static inline unsigned char uart_read(int offset)
 {
diff --git a/arch/arm/mach-rpc/include/mach/uncompress.h b/arch/arm/mach-rpc/include/mach/uncompress.h
index 8c9e2c7161c..9cd9bcdad6c 100644
--- a/arch/arm/mach-rpc/include/mach/uncompress.h
+++ b/arch/arm/mach-rpc/include/mach/uncompress.h
@@ -66,12 +66,12 @@ extern __attribute__((pure)) struct param_struct *params(void);
 #define params (params())
 
 #ifndef STANDALONE_DEBUG 
-static unsigned long video_num_cols;
-static unsigned long video_num_rows;
-static unsigned long video_x;
-static unsigned long video_y;
-static unsigned char bytes_per_char_v;
-static int white;
+unsigned long video_num_cols;
+unsigned long video_num_rows;
+unsigned long video_x;
+unsigned long video_y;
+unsigned char bytes_per_char_v;
+int white;
 
 /*
  * This does not append a newline
diff --git a/arch/arm/mach-s3c64xx/irq.c b/arch/arm/mach-s3c64xx/irq.c
index 67a145d440f..97660c8141a 100644
--- a/arch/arm/mach-s3c64xx/irq.c
+++ b/arch/arm/mach-s3c64xx/irq.c
@@ -58,12 +58,7 @@ void __init s3c64xx_init_irq(u32 vic0_valid, u32 vic1_valid)
         vic_init(VA_VIC1, IRQ_VIC1_BASE, vic1_valid, 0);
 
         /* add the timer sub-irqs */
-
-        s3c_init_vic_timer_irq(IRQ_TIMER0_VIC, IRQ_TIMER0);
-        s3c_init_vic_timer_irq(IRQ_TIMER1_VIC, IRQ_TIMER1);
-        s3c_init_vic_timer_irq(IRQ_TIMER2_VIC, IRQ_TIMER2);
-        s3c_init_vic_timer_irq(IRQ_TIMER3_VIC, IRQ_TIMER3);
-        s3c_init_vic_timer_irq(IRQ_TIMER4_VIC, IRQ_TIMER4);
+        s3c_init_vic_timer_irq(5, IRQ_TIMER0);
 
         s3c_init_uart_irqs(uart_irqs, ARRAY_SIZE(uart_irqs));
 }
diff --git a/arch/arm/mach-s5p64x0/include/mach/uncompress.h b/arch/arm/mach-s5p64x0/include/mach/uncompress.h
index c65b229aab2..1608faf870f 100644
--- a/arch/arm/mach-s5p64x0/include/mach/uncompress.h
+++ b/arch/arm/mach-s5p64x0/include/mach/uncompress.h
@@ -24,8 +24,8 @@ typedef unsigned int upf_t;	/* cannot include linux/serial_core.h */
 
 /* uart setup */
 
-static unsigned int fifo_mask;
-static unsigned int fifo_max;
+unsigned int fifo_mask;
+unsigned int fifo_max;
 
 /* forward declerations */
 
@@ -43,7 +43,7 @@ static void arch_detect_cpu(void);
 /* how many bytes we allow into the FIFO at a time in FIFO mode */
 #define FIFO_MAX         (14)
 
-static unsigned long uart_base;
+unsigned long uart_base;
 
 static __inline__ void get_uart_base(void)
 {
diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile
index 1afe05038c2..823c703e573 100644
--- a/arch/arm/mach-tegra/Makefile
+++ b/arch/arm/mach-tegra/Makefile
@@ -1,7 +1,7 @@
 obj-y                                   += common.o
 obj-y                                   += devices.o
 obj-y                                   += io.o
-obj-y                                   += irq.o legacy_irq.o
+obj-y                                   += irq.o
 obj-y                                   += clock.o
 obj-y                                   += timer.o
 obj-y                                   += gpio.o
diff --git a/arch/arm/mach-tegra/gpio.c b/arch/arm/mach-tegra/gpio.c
index 65a1aba6823..919d6383773 100644
--- a/arch/arm/mach-tegra/gpio.c
+++ b/arch/arm/mach-tegra/gpio.c
@@ -24,6 +24,8 @@
 #include <linux/io.h>
 #include <linux/gpio.h>
 
+#include <asm/mach/irq.h>
+
 #include <mach/iomap.h>
 #include <mach/suspend.h>
 
@@ -221,8 +223,9 @@ static void tegra_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
         int port;
         int pin;
         int unmasked = 0;
+        struct irq_chip *chip = irq_desc_get_chip(desc);
 
-        desc->irq_data.chip->irq_ack(&desc->irq_data);
+        chained_irq_enter(chip, desc);
 
         bank = irq_get_handler_data(irq);
 
@@ -241,7 +244,7 @@ static void tegra_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
                          */
                         if (lvl & (0x100 << pin)) {
                                 unmasked = 1;
-                                desc->irq_data.chip->irq_unmask(&desc->irq_data);
+                                chained_irq_exit(chip, desc);
                         }
 
                         generic_handle_irq(gpio_to_irq(gpio + pin));
@@ -249,7 +252,7 @@ static void tegra_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
         }
 
         if (!unmasked)
-                desc->irq_data.chip->irq_unmask(&desc->irq_data);
+                chained_irq_exit(chip, desc);
 
 }
 
diff --git a/arch/arm/mach-tegra/include/mach/legacy_irq.h b/arch/arm/mach-tegra/include/mach/legacy_irq.h
deleted file mode 100644
index d898c0e3d90..00000000000
--- a/arch/arm/mach-tegra/include/mach/legacy_irq.h
+++ /dev/null
@@ -1,35 +0,0 @@
-/*
- * arch/arm/mach-tegra/include/mach/legacy_irq.h
- *
- * Copyright (C) 2010 Google, Inc.
- * Author: Colin Cross <ccross@android.com>
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#ifndef _ARCH_ARM_MACH_TEGRA_LEGARY_IRQ_H
-#define _ARCH_ARM_MACH_TEGRA_LEGARY_IRQ_H
-
-void tegra_legacy_mask_irq(unsigned int irq);
-void tegra_legacy_unmask_irq(unsigned int irq);
-void tegra_legacy_select_fiq(unsigned int irq, bool fiq);
-void tegra_legacy_force_irq_set(unsigned int irq);
-void tegra_legacy_force_irq_clr(unsigned int irq);
-int tegra_legacy_force_irq_status(unsigned int irq);
-void tegra_legacy_select_fiq(unsigned int irq, bool fiq);
-unsigned long tegra_legacy_vfiq(int nr);
-unsigned long tegra_legacy_class(int nr);
-int tegra_legacy_irq_set_wake(int irq, int enable);
-void tegra_legacy_irq_set_lp1_wake_mask(void);
-void tegra_legacy_irq_restore_mask(void);
-void tegra_init_legacy_irq(void);
-
-#endif
diff --git a/arch/arm/mach-tegra/irq.c b/arch/arm/mach-tegra/irq.c
index 4330d8995b2..4956c3cea73 100644
--- a/arch/arm/mach-tegra/irq.c
+++ b/arch/arm/mach-tegra/irq.c
@@ -1,8 +1,8 @@
 /*
- * Copyright (C) 2010 Google, Inc.
+ * Copyright (C) 2011 Google, Inc.
  *
  * Author:
- *      Colin Cross <ccross@google.com>
+ *      Colin Cross <ccross@android.com>
  *
  * Copyright (C) 2010, NVIDIA Corporation
  *
@@ -18,8 +18,6 @@
  */
 
 #include <linux/kernel.h>
-#include <linux/delay.h>
-#include <linux/init.h>
 #include <linux/interrupt.h>
 #include <linux/irq.h>
 #include <linux/io.h>
@@ -27,134 +25,110 @@
 #include <asm/hardware/gic.h>
 
 #include <mach/iomap.h>
-#include <mach/legacy_irq.h>
-#include <mach/suspend.h>
 
 #include "board.h"
 
-#define PMC_CTRL                0x0
-#define PMC_CTRL_LATCH_WAKEUPS  (1 << 5)
-#define PMC_WAKE_MASK           0xc
-#define PMC_WAKE_LEVEL          0x10
-#define PMC_WAKE_STATUS         0x14
-#define PMC_SW_WAKE_STATUS      0x18
-#define PMC_DPD_SAMPLE          0x20
+#define INT_SYS_NR      (INT_GPIO_BASE - INT_PRI_BASE)
+#define INT_SYS_SZ      (INT_SEC_BASE - INT_PRI_BASE)
+#define PPI_NR          ((INT_SYS_NR+INT_SYS_SZ-1)/INT_SYS_SZ)
+
+#define ICTLR_CPU_IEP_VFIQ      0x08
+#define ICTLR_CPU_IEP_FIR       0x14
+#define ICTLR_CPU_IEP_FIR_SET   0x18
+#define ICTLR_CPU_IEP_FIR_CLR   0x1c
+
+#define ICTLR_CPU_IER           0x20
+#define ICTLR_CPU_IER_SET       0x24
+#define ICTLR_CPU_IER_CLR       0x28
+#define ICTLR_CPU_IEP_CLASS     0x2C
+
+#define ICTLR_COP_IER           0x30
+#define ICTLR_COP_IER_SET       0x34
+#define ICTLR_COP_IER_CLR       0x38
+#define ICTLR_COP_IEP_CLASS     0x3c
+
+#define NUM_ICTLRS 4
+#define FIRST_LEGACY_IRQ 32
+
+static void __iomem *ictlr_reg_base[] = {
+        IO_ADDRESS(TEGRA_PRIMARY_ICTLR_BASE),
+        IO_ADDRESS(TEGRA_SECONDARY_ICTLR_BASE),
+        IO_ADDRESS(TEGRA_TERTIARY_ICTLR_BASE),
+        IO_ADDRESS(TEGRA_QUATERNARY_ICTLR_BASE),
+};
 
-static void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE);
+static inline void tegra_irq_write_mask(unsigned int irq, unsigned long reg)
+{
+        void __iomem *base;
+        u32 mask;
 
-static u32 tegra_lp0_wake_enb;
-static u32 tegra_lp0_wake_level;
-static u32 tegra_lp0_wake_level_any;
+        BUG_ON(irq < FIRST_LEGACY_IRQ ||
+                irq >= FIRST_LEGACY_IRQ + NUM_ICTLRS * 32);
 
-static void (*tegra_gic_mask_irq)(struct irq_data *d);
-static void (*tegra_gic_unmask_irq)(struct irq_data *d);
-static void (*tegra_gic_ack_irq)(struct irq_data *d);
+        base = ictlr_reg_base[(irq - FIRST_LEGACY_IRQ) / 32];
+        mask = BIT((irq - FIRST_LEGACY_IRQ) % 32);
 
-/* ensures that sufficient time is passed for a register write to
- * serialize into the 32KHz domain */
-static void pmc_32kwritel(u32 val, unsigned long offs)
-{
-        writel(val, pmc + offs);
-        udelay(130);
+        __raw_writel(mask, base + reg);
 }
 
-int tegra_set_lp1_wake(int irq, int enable)
+static void tegra_mask(struct irq_data *d)
 {
-        return tegra_legacy_irq_set_wake(irq, enable);
+        if (d->irq < FIRST_LEGACY_IRQ)
+                return;
+
+        tegra_irq_write_mask(d->irq, ICTLR_CPU_IER_CLR);
 }
 
-void tegra_set_lp0_wake_pads(u32 wake_enb, u32 wake_level, u32 wake_any)
+static void tegra_unmask(struct irq_data *d)
 {
-        u32 temp;
-        u32 status;
-        u32 lvl;
-
-        wake_level &= wake_enb;
-        wake_any &= wake_enb;
+        if (d->irq < FIRST_LEGACY_IRQ)
+                return;
 
-        wake_level |= (tegra_lp0_wake_level & tegra_lp0_wake_enb);
-        wake_any |= (tegra_lp0_wake_level_any & tegra_lp0_wake_enb);
-
-        wake_enb |= tegra_lp0_wake_enb;
-
-        pmc_32kwritel(0, PMC_SW_WAKE_STATUS);
-        temp = readl(pmc + PMC_CTRL);
-        temp |= PMC_CTRL_LATCH_WAKEUPS;
-        pmc_32kwritel(temp, PMC_CTRL);
-        temp &= ~PMC_CTRL_LATCH_WAKEUPS;
-        pmc_32kwritel(temp, PMC_CTRL);
-        status = readl(pmc + PMC_SW_WAKE_STATUS);
-        lvl = readl(pmc + PMC_WAKE_LEVEL);
-
-        /* flip the wakeup trigger for any-edge triggered pads
-         * which are currently asserting as wakeups */
-        lvl ^= status;
-        lvl &= wake_any;
-
-        wake_level |= lvl;
-
-        writel(wake_level, pmc + PMC_WAKE_LEVEL);
-        /* Enable DPD sample to trigger sampling pads data and direction
-         * in which pad will be driven during lp0 mode*/
-        writel(0x1, pmc + PMC_DPD_SAMPLE);
-
-        writel(wake_enb, pmc + PMC_WAKE_MASK);
+        tegra_irq_write_mask(d->irq, ICTLR_CPU_IER_SET);
 }
 
-static void tegra_mask(struct irq_data *d)
+static void tegra_ack(struct irq_data *d)
 {
-        tegra_gic_mask_irq(d);
-        tegra_legacy_mask_irq(d->irq);
-}
+        if (d->irq < FIRST_LEGACY_IRQ)
+                return;
 
-static void tegra_unmask(struct irq_data *d)
-{
-        tegra_gic_unmask_irq(d);
-        tegra_legacy_unmask_irq(d->irq);
+        tegra_irq_write_mask(d->irq, ICTLR_CPU_IEP_FIR_CLR);
 }
 
-static void tegra_ack(struct irq_data *d)
+static void tegra_eoi(struct irq_data *d)
 {
-        tegra_legacy_force_irq_clr(d->irq);
-        tegra_gic_ack_irq(d);
+        if (d->irq < FIRST_LEGACY_IRQ)
+                return;
+
+        tegra_irq_write_mask(d->irq, ICTLR_CPU_IEP_FIR_CLR);
 }
 
 static int tegra_retrigger(struct irq_data *d)
 {
-        tegra_legacy_force_irq_set(d->irq);
+        if (d->irq < FIRST_LEGACY_IRQ)
+                return 0;
+
+        tegra_irq_write_mask(d->irq, ICTLR_CPU_IEP_FIR_SET);
+
         return 1;
 }
 
-static struct irq_chip tegra_irq = {
-        .name                   = "PPI",
-        .irq_ack                = tegra_ack,
-        .irq_mask               = tegra_mask,
-        .irq_unmask             = tegra_unmask,
-        .irq_retrigger          = tegra_retrigger,
-};
-
 void __init tegra_init_irq(void)
 {
-        struct irq_chip *gic;
-        unsigned int i;
-        int irq;
+        int i;
 
-        tegra_init_legacy_irq();
+        for (i = 0; i < NUM_ICTLRS; i++) {
+                void __iomem *ictlr = ictlr_reg_base[i];
+                writel(~0, ictlr + ICTLR_CPU_IER_CLR);
+                writel(0, ictlr + ICTLR_CPU_IEP_CLASS);
+        }
+
+        gic_arch_extn.irq_ack = tegra_ack;
+        gic_arch_extn.irq_eoi = tegra_eoi;
+        gic_arch_extn.irq_mask = tegra_mask;
+        gic_arch_extn.irq_unmask = tegra_unmask;
+        gic_arch_extn.irq_retrigger = tegra_retrigger;
 
         gic_init(0, 29, IO_ADDRESS(TEGRA_ARM_INT_DIST_BASE),
                  IO_ADDRESS(TEGRA_ARM_PERIF_BASE + 0x100));
-
-        gic = irq_get_chip(29);
-        tegra_gic_unmask_irq = gic->irq_unmask;
-        tegra_gic_mask_irq = gic->irq_mask;
-        tegra_gic_ack_irq = gic->irq_ack;
-#ifdef CONFIG_SMP
-        tegra_irq.irq_set_affinity = gic->irq_set_affinity;
-#endif
-
-        for (i = 0; i < INT_MAIN_NR; i++) {
-                irq = INT_PRI_BASE + i;
-                irq_set_chip_and_handler(irq, &tegra_irq, handle_level_irq);
-                set_irq_flags(irq, IRQF_VALID);
-        }
 }
diff --git a/arch/arm/mach-tegra/legacy_irq.c b/arch/arm/mach-tegra/legacy_irq.c
deleted file mode 100644
index 38eb719a4f5..00000000000
--- a/arch/arm/mach-tegra/legacy_irq.c
+++ /dev/null
@@ -1,215 +0,0 @@
-/*
- * arch/arm/mach-tegra/legacy_irq.c
- *
- * Copyright (C) 2010 Google, Inc.
- * Author: Colin Cross <ccross@android.com>
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#include <linux/io.h>
-#include <linux/kernel.h>
-#include <mach/iomap.h>
-#include <mach/irqs.h>
-#include <mach/legacy_irq.h>
-
-#define INT_SYS_NR      (INT_GPIO_BASE - INT_PRI_BASE)
-#define INT_SYS_SZ      (INT_SEC_BASE - INT_PRI_BASE)
-#define PPI_NR          ((INT_SYS_NR+INT_SYS_SZ-1)/INT_SYS_SZ)
-
-#define ICTLR_CPU_IEP_VFIQ      0x08
-#define ICTLR_CPU_IEP_FIR       0x14
-#define ICTLR_CPU_IEP_FIR_SET   0x18
-#define ICTLR_CPU_IEP_FIR_CLR   0x1c
-
-#define ICTLR_CPU_IER           0x20
-#define ICTLR_CPU_IER_SET       0x24
-#define ICTLR_CPU_IER_CLR       0x28
-#define ICTLR_CPU_IEP_CLASS     0x2C
-
-#define ICTLR_COP_IER           0x30
-#define ICTLR_COP_IER_SET       0x34
-#define ICTLR_COP_IER_CLR       0x38
-#define ICTLR_COP_IEP_CLASS     0x3c
-
-#define NUM_ICTLRS 4
-
-static void __iomem *ictlr_reg_base[] = {
-        IO_ADDRESS(TEGRA_PRIMARY_ICTLR_BASE),
-        IO_ADDRESS(TEGRA_SECONDARY_ICTLR_BASE),
-        IO_ADDRESS(TEGRA_TERTIARY_ICTLR_BASE),
-        IO_ADDRESS(TEGRA_QUATERNARY_ICTLR_BASE),
-};
-
-static u32 tegra_legacy_wake_mask[4];
-static u32 tegra_legacy_saved_mask[4];
-
-/* When going into deep sleep, the CPU is powered down, taking the GIC with it
-   In order to wake, the wake interrupts need to be enabled in the legacy
-   interrupt controller. */
-void tegra_legacy_unmask_irq(unsigned int irq)
-{
-        void __iomem *base;
-        pr_debug("%s: %d\n", __func__, irq);
-
-        irq -= 32;
-        base = ictlr_reg_base[irq>>5];
-        writel(1 << (irq & 31), base + ICTLR_CPU_IER_SET);
-}
-
-void tegra_legacy_mask_irq(unsigned int irq)
-{
-        void __iomem *base;
-        pr_debug("%s: %d\n", __func__, irq);
-
-        irq -= 32;
-        base = ictlr_reg_base[irq>>5];
-        writel(1 << (irq & 31), base + ICTLR_CPU_IER_CLR);
-}
-
-void tegra_legacy_force_irq_set(unsigned int irq)
-{
-        void __iomem *base;
-        pr_debug("%s: %d\n", __func__, irq);
-
-        irq -= 32;
-        base = ictlr_reg_base[irq>>5];
-        writel(1 << (irq & 31), base + ICTLR_CPU_IEP_FIR_SET);
-}
-
-void tegra_legacy_force_irq_clr(unsigned int irq)
-{
-        void __iomem *base;
-        pr_debug("%s: %d\n", __func__, irq);
-
-        irq -= 32;
-        base = ictlr_reg_base[irq>>5];
-        writel(1 << (irq & 31), base + ICTLR_CPU_IEP_FIR_CLR);
-}
-
-int tegra_legacy_force_irq_status(unsigned int irq)
-{
-        void __iomem *base;
-        pr_debug("%s: %d\n", __func__, irq);
-
-        irq -= 32;
-        base = ictlr_reg_base[irq>>5];
-        return !!(readl(base + ICTLR_CPU_IEP_FIR) & (1 << (irq & 31)));
-}
-
-void tegra_legacy_select_fiq(unsigned int irq, bool fiq)
-{
-        void __iomem *base;
-        pr_debug("%s: %d\n", __func__, irq);
-
-        irq -= 32;
-        base = ictlr_reg_base[irq>>5];
-        writel(fiq << (irq & 31), base + ICTLR_CPU_IEP_CLASS);
-}
-
-unsigned long tegra_legacy_vfiq(int nr)
-{
-        void __iomem *base;
-        base = ictlr_reg_base[nr];
-        return readl(base + ICTLR_CPU_IEP_VFIQ);
-}
-
-unsigned long tegra_legacy_class(int nr)
-{
-        void __iomem *base;
-        base = ictlr_reg_base[nr];
-        return readl(base + ICTLR_CPU_IEP_CLASS);
-}
-
-int tegra_legacy_irq_set_wake(int irq, int enable)
-{
-        irq -= 32;
-        if (enable)
-                tegra_legacy_wake_mask[irq >> 5] |= 1 << (irq & 31);
-        else
-                tegra_legacy_wake_mask[irq >> 5] &= ~(1 << (irq & 31));
-
-        return 0;
-}
-
-void tegra_legacy_irq_set_lp1_wake_mask(void)
-{
-        void __iomem *base;
-        int i;
-
-        for (i = 0; i < NUM_ICTLRS; i++) {
-                base = ictlr_reg_base[i];
-                tegra_legacy_saved_mask[i] = readl(base + ICTLR_CPU_IER);
-                writel(tegra_legacy_wake_mask[i], base + ICTLR_CPU_IER);
-        }
-}
-
-void tegra_legacy_irq_restore_mask(void)
-{
-        void __iomem *base;
-        int i;
-
-        for (i = 0; i < NUM_ICTLRS; i++) {
-                base = ictlr_reg_base[i];
-                writel(tegra_legacy_saved_mask[i], base + ICTLR_CPU_IER);
-        }
-}
-
-void tegra_init_legacy_irq(void)
-{
-        int i;
-
-        for (i = 0; i < NUM_ICTLRS; i++) {
-                void __iomem *ictlr = ictlr_reg_base[i];
-                writel(~0, ictlr + ICTLR_CPU_IER_CLR);
-                writel(0, ictlr + ICTLR_CPU_IEP_CLASS);
-        }
-}
-
-#ifdef CONFIG_PM
-static u32 cop_ier[NUM_ICTLRS];
-static u32 cpu_ier[NUM_ICTLRS];
-static u32 cpu_iep[NUM_ICTLRS];
-
-void tegra_irq_suspend(void)
-{
-        unsigned long flags;
-        int i;
-
-        local_irq_save(flags);
-        for (i = 0; i < NUM_ICTLRS; i++) {
-                void __iomem *ictlr = ictlr_reg_base[i];
-                cpu_ier[i] = readl(ictlr + ICTLR_CPU_IER);
-                cpu_iep[i] = readl(ictlr + ICTLR_CPU_IEP_CLASS);
-                cop_ier[i] = readl(ictlr + ICTLR_COP_IER);
-                writel(~0, ictlr + ICTLR_COP_IER_CLR);
-        }
-        local_irq_restore(flags);
-}
-
-void tegra_irq_resume(void)
-{
-        unsigned long flags;
-        int i;
-
-        local_irq_save(flags);
-        for (i = 0; i < NUM_ICTLRS; i++) {
-                void __iomem *ictlr = ictlr_reg_base[i];
-                writel(cpu_iep[i], ictlr + ICTLR_CPU_IEP_CLASS);
-                writel(~0ul, ictlr + ICTLR_CPU_IER_CLR);
-                writel(cpu_ier[i], ictlr + ICTLR_CPU_IER_SET);
-                writel(0, ictlr + ICTLR_COP_IEP_CLASS);
-                writel(~0ul, ictlr + ICTLR_COP_IER_CLR);
-                writel(cop_ier[i], ictlr + ICTLR_COP_IER_SET);
-        }
-        local_irq_restore(flags);
-}
-#endif
diff --git a/arch/arm/mach-ux500/include/mach/uncompress.h b/arch/arm/mach-ux500/include/mach/uncompress.h
index ab0fe1432fa..088b550c40d 100644
--- a/arch/arm/mach-ux500/include/mach/uncompress.h
+++ b/arch/arm/mach-ux500/include/mach/uncompress.h
@@ -24,7 +24,7 @@
 #include <linux/amba/serial.h>
 #include <mach/hardware.h>
 
-static u32 ux500_uart_base;
+u32 ux500_uart_base;
 
 static void putc(const char c)
 {
diff --git a/arch/arm/mach-w90x900/include/mach/uncompress.h b/arch/arm/mach-w90x900/include/mach/uncompress.h
index 56f1a74d701..03130212ace 100644
--- a/arch/arm/mach-w90x900/include/mach/uncompress.h
+++ b/arch/arm/mach-w90x900/include/mach/uncompress.h
@@ -27,7 +27,7 @@
 #define arch_decomp_wdog()
 
 #define TX_DONE (UART_LSR_TEMT | UART_LSR_THRE)
-static volatile u32 * uart_base = (u32 *)UART0_PA;
+static volatile u32 * const uart_base = (u32 *)UART0_PA;
 
 static void putc(int ch)
 {
diff --git a/arch/arm/mm/proc-v6.S b/arch/arm/mm/proc-v6.S
index 7c99cb4c8e4..ab17cc0d3fa 100644
--- a/arch/arm/mm/proc-v6.S
+++ b/arch/arm/mm/proc-v6.S
@@ -175,11 +175,6 @@ cpu_v6_name:
         .asciz  "ARMv6-compatible processor"
         .size   cpu_v6_name, . - cpu_v6_name
 
-        .type   cpu_pj4_name, #object
-cpu_pj4_name:
-        .asciz  "Marvell PJ4 processor"
-        .size   cpu_pj4_name, . - cpu_pj4_name
-
         .align
 
         __CPUINIT
@@ -305,32 +300,3 @@ __v6_proc_info:
         .long   v6_user_fns
         .long   v6_cache_fns
         .size   __v6_proc_info, . - __v6_proc_info
-
-        .type   __pj4_v6_proc_info, #object
-__pj4_v6_proc_info:
-        .long   0x560f5810
-        .long   0xff0ffff0
-        ALT_SMP(.long \
-                PMD_TYPE_SECT | \
-                PMD_SECT_AP_WRITE | \
-                PMD_SECT_AP_READ | \
-                PMD_FLAGS_SMP)
-        ALT_UP(.long \
-                PMD_TYPE_SECT | \
-                PMD_SECT_AP_WRITE | \
-                PMD_SECT_AP_READ | \
-                PMD_FLAGS_UP)
-        .long   PMD_TYPE_SECT | \
-                PMD_SECT_XN | \
-                PMD_SECT_AP_WRITE | \
-                PMD_SECT_AP_READ
-        b       __v6_setup
-        .long   cpu_arch_name
-        .long   cpu_elf_name
-        .long   HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP|HWCAP_TLS
-        .long   cpu_pj4_name
-        .long   v6_processor_functions
-        .long   v6wbi_tlb_fns
-        .long   v6_user_fns
-        .long   v6_cache_fns
-        .size   __pj4_v6_proc_info, . - __pj4_v6_proc_info
diff --git a/arch/arm/plat-mxc/Kconfig b/arch/arm/plat-mxc/Kconfig
index b0cb4258e38..a5353fc0793 100644
--- a/arch/arm/plat-mxc/Kconfig
+++ b/arch/arm/plat-mxc/Kconfig
@@ -4,13 +4,18 @@ source "arch/arm/plat-mxc/devices/Kconfig"
 
 menu "Freescale MXC Implementations"
 
+config ARCH_MX50_SUPPORTED
+        bool
+
+config ARCH_MX53_SUPPORTED
+        bool
+
 choice
         prompt "Freescale CPU family:"
         default ARCH_MX3
 
 config ARCH_MX1
         bool "MX1-based"
-        select SOC_IMX1
         help
           This enables support for systems based on the Freescale i.MX1 family
 
@@ -26,29 +31,26 @@ config ARCH_MX25
 
 config ARCH_MX3
         bool "MX3-based"
-        select CPU_V6
         help
           This enables support for systems based on the Freescale i.MX3 family
 
-config ARCH_MXC91231
-        bool "MXC91231-based"
-        select CPU_V6
-        select MXC_AVIC
+config ARCH_MX503
+        bool "i.MX50 + i.MX53"
+        select ARCH_MX50_SUPPORTED
+        select ARCH_MX53_SUPPORTED
         help
-          This enables support for systems based on the Freescale MXC91231 family
+          This enables support for machines using Freescale's i.MX50 and i.MX51
+          processors.
 
-config ARCH_MX5
-        bool "MX5-based"
-        select CPU_V7
-        select ARM_L1_CACHE_SHIFT_6
+config ARCH_MX51
+        bool "i.MX51"
+        select ARCH_MX51_SUPPORTED
         help
           This enables support for systems based on the Freescale i.MX51 family
 
 endchoice
 
 source "arch/arm/mach-imx/Kconfig"
-source "arch/arm/mach-mx3/Kconfig"
-source "arch/arm/mach-mxc91231/Kconfig"
 source "arch/arm/mach-mx5/Kconfig"
 
 endmenu
diff --git a/arch/arm/plat-mxc/devices/Kconfig b/arch/arm/plat-mxc/devices/Kconfig
index b9ab1d58b5e..bd294add932 100644
--- a/arch/arm/plat-mxc/devices/Kconfig
+++ b/arch/arm/plat-mxc/devices/Kconfig
@@ -24,7 +24,6 @@ config IMX_HAVE_PLATFORM_IMXDI_RTC
 
 config IMX_HAVE_PLATFORM_IMX_FB
         bool
-        select HAVE_FB_IMX
 
 config IMX_HAVE_PLATFORM_IMX_I2C
         bool
@@ -41,6 +40,9 @@ config IMX_HAVE_PLATFORM_IMX_UART
 config IMX_HAVE_PLATFORM_IMX_UDC
         bool
 
+config IMX_HAVE_PLATFORM_IPU_CORE
+        bool
+
 config IMX_HAVE_PLATFORM_MX1_CAMERA
         bool
 
@@ -63,6 +65,9 @@ config IMX_HAVE_PLATFORM_MXC_RNGA
         bool
         select ARCH_HAS_RNGA
 
+config IMX_HAVE_PLATFORM_MXC_RTC
+        bool
+
 config IMX_HAVE_PLATFORM_MXC_W1
         bool
 
diff --git a/arch/arm/plat-mxc/devices/Makefile b/arch/arm/plat-mxc/devices/Makefile
index 75cd2ece905..ad2922acf48 100644
--- a/arch/arm/plat-mxc/devices/Makefile
+++ b/arch/arm/plat-mxc/devices/Makefile
@@ -12,6 +12,7 @@ obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_KEYPAD) += platform-imx-keypad.o
 obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_SSI) += platform-imx-ssi.o
 obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_UART) += platform-imx-uart.o
 obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_UDC) += platform-imx_udc.o
+obj-$(CONFIG_IMX_HAVE_PLATFORM_IPU_CORE) += platform-ipu-core.o
 obj-$(CONFIG_IMX_HAVE_PLATFORM_MX1_CAMERA) += platform-mx1-camera.o
 obj-$(CONFIG_IMX_HAVE_PLATFORM_MX2_CAMERA) += platform-mx2-camera.o
 obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_EHCI) += platform-mxc-ehci.o
@@ -19,6 +20,7 @@ obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_MMC) += platform-mxc-mmc.o
 obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_NAND) += platform-mxc_nand.o
 obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_PWM) += platform-mxc_pwm.o
 obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_RNGA) += platform-mxc_rnga.o
+obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_RTC) += platform-mxc_rtc.o
 obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_W1) += platform-mxc_w1.o
 obj-$(CONFIG_IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX) += platform-sdhci-esdhc-imx.o
 obj-$(CONFIG_IMX_HAVE_PLATFORM_SPI_IMX) +=  platform-spi_imx.o
diff --git a/arch/arm/plat-mxc/devices/platform-ipu-core.c b/arch/arm/plat-mxc/devices/platform-ipu-core.c
new file mode 100644
index 00000000000..edf65034aea
--- /dev/null
+++ b/arch/arm/plat-mxc/devices/platform-ipu-core.c
@@ -0,0 +1,129 @@
+/*
+ * Copyright (C) 2011 Pengutronix
+ * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify it under
+ * the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation.
+ */
+#include <mach/hardware.h>
+#include <mach/devices-common.h>
+
+#define imx_ipu_core_entry_single(soc)                                  \
+{                                                                       \
+        .iobase = soc ## _IPU_CTRL_BASE_ADDR,                           \
+        .synirq = soc ## _INT_IPU_SYN,                                  \
+        .errirq = soc ## _INT_IPU_ERR,                                  \
+}
+
+#ifdef CONFIG_SOC_IMX31
+const struct imx_ipu_core_data imx31_ipu_core_data __initconst =
+        imx_ipu_core_entry_single(MX31);
+#endif
+
+#ifdef CONFIG_SOC_IMX35
+const struct imx_ipu_core_data imx35_ipu_core_data __initconst =
+        imx_ipu_core_entry_single(MX35);
+#endif
+
+static struct platform_device *imx_ipu_coredev __initdata;
+
+struct platform_device *__init imx_add_ipu_core(
+                const struct imx_ipu_core_data *data,
+                const struct ipu_platform_data *pdata)
+{
+        /* The resource order is important! */
+        struct resource res[] = {
+                {
+                        .start = data->iobase,
+                        .end = data->iobase + 0x5f,
+                        .flags = IORESOURCE_MEM,
+                }, {
+                        .start = data->iobase + 0x88,
+                        .end = data->iobase + 0xb3,
+                        .flags = IORESOURCE_MEM,
+                }, {
+                        .start = data->synirq,
+                        .end = data->synirq,
+                        .flags = IORESOURCE_IRQ,
+                }, {
+                        .start = data->errirq,
+                        .end = data->errirq,
+                        .flags = IORESOURCE_IRQ,
+                },
+        };
+
+        return imx_ipu_coredev = imx_add_platform_device("ipu-core", -1,
+                        res, ARRAY_SIZE(res), pdata, sizeof(*pdata));
+}
+
+struct platform_device *__init imx_alloc_mx3_camera(
+                const struct imx_ipu_core_data *data,
+                const struct mx3_camera_pdata *pdata)
+{
+        struct resource res[] = {
+                {
+                        .start = data->iobase + 0x60,
+                        .end = data->iobase + 0x87,
+                        .flags = IORESOURCE_MEM,
+                },
+        };
+        int ret = -ENOMEM;
+        struct platform_device *pdev;
+
+        if (IS_ERR_OR_NULL(imx_ipu_coredev))
+                return ERR_PTR(-ENODEV);
+
+        pdev = platform_device_alloc("mx3-camera", 0);
+        if (!pdev)
+                goto err;
+
+        pdev->dev.dma_mask = kmalloc(sizeof(*pdev->dev.dma_mask), GFP_KERNEL);
+        if (!pdev->dev.dma_mask)
+                goto err;
+
+        *pdev->dev.dma_mask = DMA_BIT_MASK(32);
+        pdev->dev.coherent_dma_mask = DMA_BIT_MASK(32);
+
+        ret = platform_device_add_resources(pdev, res, ARRAY_SIZE(res));
+        if (ret)
+                goto err;
+
+        if (pdata) {
+                struct mx3_camera_pdata *copied_pdata;
+
+                ret = platform_device_add_data(pdev, pdata, sizeof(*pdata));
+                if (ret) {
+err:
+                        kfree(pdev->dev.dma_mask);
+                        platform_device_put(pdev);
+                        return ERR_PTR(-ENODEV);
+                }
+                copied_pdata = dev_get_platdata(&pdev->dev);
+                copied_pdata->dma_dev = &imx_ipu_coredev->dev;
+        }
+
+        return pdev;
+}
+
+struct platform_device *__init imx_add_mx3_sdc_fb(
+                const struct imx_ipu_core_data *data,
+                struct mx3fb_platform_data *pdata)
+{
+        struct resource res[] = {
+                {
+                        .start = data->iobase + 0xb4,
+                        .end = data->iobase + 0x1bf,
+                        .flags = IORESOURCE_MEM,
+                },
+        };
+
+        if (IS_ERR_OR_NULL(imx_ipu_coredev))
+                return ERR_PTR(-ENODEV);
+
+        pdata->dma_dev = &imx_ipu_coredev->dev;
+
+        return imx_add_platform_device_dmamask("mx3_sdc_fb", -1,
+                        res, ARRAY_SIZE(res), pdata, sizeof(*pdata),
+                        DMA_BIT_MASK(32));
+}
diff --git a/arch/arm/plat-mxc/devices/platform-mxc_rtc.c b/arch/arm/plat-mxc/devices/platform-mxc_rtc.c
new file mode 100644
index 00000000000..16d0ec4df5f
--- /dev/null
+++ b/arch/arm/plat-mxc/devices/platform-mxc_rtc.c
@@ -0,0 +1,40 @@
+/*
+ * Copyright (C) 2010-2011 Pengutronix
+ * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify it under
+ * the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation.
+ */
+#include <mach/hardware.h>
+#include <mach/devices-common.h>
+
+#define imx_mxc_rtc_data_entry_single(soc)                              \
+        {                                                               \
+                .iobase = soc ## _RTC_BASE_ADDR,                        \
+                .irq = soc ## _INT_RTC,                                 \
+        }
+
+#ifdef CONFIG_SOC_IMX31
+const struct imx_mxc_rtc_data imx31_mxc_rtc_data __initconst =
+        imx_mxc_rtc_data_entry_single(MX31);
+#endif /* ifdef CONFIG_SOC_IMX31 */
+
+struct platform_device *__init imx_add_mxc_rtc(
+                const struct imx_mxc_rtc_data *data)
+{
+        struct resource res[] = {
+                {
+                        .start = data->iobase,
+                        .end = data->iobase + SZ_16K - 1,
+                        .flags = IORESOURCE_MEM,
+                }, {
+                        .start = data->irq,
+                        .end = data->irq,
+                        .flags = IORESOURCE_IRQ,
+                },
+        };
+
+        return imx_add_platform_device("mxc_rtc", -1,
+                        res, ARRAY_SIZE(res), NULL, 0);
+}
diff --git a/arch/arm/plat-mxc/devices/platform-spi_imx.c b/arch/arm/plat-mxc/devices/platform-spi_imx.c
index f4a60ab6763..f97eb3615b2 100644
--- a/arch/arm/plat-mxc/devices/platform-spi_imx.c
+++ b/arch/arm/plat-mxc/devices/platform-spi_imx.c
@@ -80,7 +80,7 @@ const struct imx_spi_imx_data imx35_cspi_data[] __initconst = {
 
 #ifdef CONFIG_SOC_IMX51
 const struct imx_spi_imx_data imx51_cspi_data __initconst =
-        imx_spi_imx_data_entry_single(MX51, CSPI, "imx51-cspi", 0, , SZ_4K);
+        imx_spi_imx_data_entry_single(MX51, CSPI, "imx51-cspi", 2, , SZ_4K);
 
 const struct imx_spi_imx_data imx51_ecspi_data[] __initconst = {
 #define imx51_ecspi_data_entry(_id, _hwid)                              \
diff --git a/arch/arm/plat-mxc/include/mach/common.h b/arch/arm/plat-mxc/include/mach/common.h
index a22ebe11a60..da7991832af 100644
--- a/arch/arm/plat-mxc/include/mach/common.h
+++ b/arch/arm/plat-mxc/include/mach/common.h
@@ -23,7 +23,6 @@ extern void mx35_map_io(void);
 extern void mx50_map_io(void);
 extern void mx51_map_io(void);
 extern void mx53_map_io(void);
-extern void mxc91231_map_io(void);
 extern void imx1_init_early(void);
 extern void imx21_init_early(void);
 extern void imx25_init_early(void);
@@ -33,7 +32,6 @@ extern void imx35_init_early(void);
 extern void imx50_init_early(void);
 extern void imx51_init_early(void);
 extern void imx53_init_early(void);
-extern void mxc91231_init_early(void);
 extern void mxc_init_irq(void __iomem *);
 extern void tzic_init_irq(void __iomem *);
 extern void mx1_init_irq(void);
@@ -45,7 +43,6 @@ extern void mx35_init_irq(void);
 extern void mx50_init_irq(void);
 extern void mx51_init_irq(void);
 extern void mx53_init_irq(void);
-extern void mxc91231_init_irq(void);
 extern void epit_timer_init(struct clk *timer_clk, void __iomem *base, int irq);
 extern void mxc_timer_init(struct clk *timer_clk, void __iomem *, int);
 extern int mx1_clocks_init(unsigned long fref);
@@ -58,14 +55,11 @@ extern int mx51_clocks_init(unsigned long ckil, unsigned long osc,
                         unsigned long ckih1, unsigned long ckih2);
 extern int mx53_clocks_init(unsigned long ckil, unsigned long osc,
                         unsigned long ckih1, unsigned long ckih2);
-extern int mxc91231_clocks_init(unsigned long fref);
 extern int mxc_register_gpios(void);
 extern int mxc_register_device(struct platform_device *pdev, void *data);
 extern void mxc_set_cpu_type(unsigned int type);
 extern void mxc_arch_reset_init(void __iomem *);
-extern void mxc91231_power_off(void);
-extern void mxc91231_arch_reset(int, const char *);
-extern void mxc91231_prepare_idle(void);
 extern void mx51_efikamx_reset(void);
 extern int mx53_revision(void);
+extern int mx53_display_revision(void);
 #endif
diff --git a/arch/arm/plat-mxc/include/mach/debug-macro.S b/arch/arm/plat-mxc/include/mach/debug-macro.S
index 3b3a37c25c5..8e8d175e507 100644
--- a/arch/arm/plat-mxc/include/mach/debug-macro.S
+++ b/arch/arm/plat-mxc/include/mach/debug-macro.S
@@ -44,13 +44,6 @@
 #define UART_PADDR      MX51_UART1_BASE_ADDR
 #endif
 
-#ifdef CONFIG_ARCH_MXC91231
-#ifdef UART_PADDR
-#error "CONFIG_DEBUG_LL is incompatible with multiple archs"
-#endif
-#define UART_PADDR      MXC91231_UART2_BASE_ADDR
-#endif
-
 #define UART_VADDR      IMX_IO_ADDRESS(UART_PADDR)
 
                 .macro  addruart, rp, rv
diff --git a/arch/arm/plat-mxc/include/mach/devices-common.h b/arch/arm/plat-mxc/include/mach/devices-common.h
index 8658c9caa65..fa8477337f9 100644
--- a/arch/arm/plat-mxc/include/mach/devices-common.h
+++ b/arch/arm/plat-mxc/include/mach/devices-common.h
@@ -166,6 +166,24 @@ struct platform_device *__init imx_add_imx_udc(
                 const struct imx_imx_udc_data *data,
                 const struct imxusb_platform_data *pdata);
 
+#include <mach/ipu.h>
+#include <mach/mx3fb.h>
+#include <mach/mx3_camera.h>
+struct imx_ipu_core_data {
+        resource_size_t iobase;
+        resource_size_t synirq;
+        resource_size_t errirq;
+};
+struct platform_device *__init imx_add_ipu_core(
+                const struct imx_ipu_core_data *data,
+                const struct ipu_platform_data *pdata);
+struct platform_device *__init imx_alloc_mx3_camera(
+                const struct imx_ipu_core_data *data,
+                const struct mx3_camera_pdata *pdata);
+struct platform_device *__init imx_add_mx3_sdc_fb(
+                const struct imx_ipu_core_data *data,
+                struct mx3fb_platform_data *pdata);
+
 #include <mach/mx1_camera.h>
 struct imx_mx1_camera_data {
         resource_size_t iobase;
@@ -237,6 +255,15 @@ struct imx_mxc_pwm_data {
 struct platform_device *__init imx_add_mxc_pwm(
                 const struct imx_mxc_pwm_data *data);
 
+/* mxc_rtc */
+struct imx_mxc_rtc_data {
+        resource_size_t iobase;
+        resource_size_t irq;
+};
+struct platform_device *__init imx_add_mxc_rtc(
+                const struct imx_mxc_rtc_data *data);
+
+/* mxc_w1 */
 struct imx_mxc_w1_data {
         resource_size_t iobase;
 };
diff --git a/arch/arm/plat-mxc/include/mach/hardware.h b/arch/arm/plat-mxc/include/mach/hardware.h
index 26bb1bab4ae..67d3e2bed06 100644
--- a/arch/arm/plat-mxc/include/mach/hardware.h
+++ b/arch/arm/plat-mxc/include/mach/hardware.h
@@ -86,15 +86,6 @@
  *      SPBA0   0x70000000+0x100000     ->      0xf5400000+0x100000
  *      AIPS1   0x73f00000+0x100000     ->      0xf5700000+0x100000
  *      AIPS2   0x83f00000+0x100000     ->      0xf4300000+0x100000
- * mxc91231:
- *      L2CC    0x30000000+0x010000     ->      0xf4400000+0x010000
- *      X_MEMC  0xb8000000+0x010000     ->      0xf4c00000+0x010000
- *      ROMP    0x60000000+0x010000     ->      0xf5000000+0x010000
- *      AVIC    0x68000000+0x010000     ->      0xf5800000+0x010000
- *      AIPS1   0x43f00000+0x100000     ->      0xf5300000+0x100000
- *      SPBA0   0x50000000+0x100000     ->      0xf5400000+0x100000
- *      SPBA1   0x52000000+0x100000     ->      0xf5600000+0x100000
- *      AIPS2   0x53f00000+0x100000     ->      0xf5700000+0x100000
  */
 #define IMX_IO_P2V(x)   (                                               \
                         0xf4000000 +                                    \
@@ -104,6 +95,8 @@
 
 #define IMX_IO_ADDRESS(x)       IOMEM(IMX_IO_P2V(x))
 
+#include <mach/mxc.h>
+
 #ifdef CONFIG_ARCH_MX5
 #include <mach/mx50.h>
 #include <mach/mx51.h>
@@ -134,12 +127,6 @@
 # include <mach/mx25.h>
 #endif
 
-#ifdef CONFIG_ARCH_MXC91231
-# include <mach/mxc91231.h>
-#endif
-
-#include <mach/mxc.h>
-
 #define imx_map_entry(soc, name, _type) {                               \
         .virtual = soc ## _IO_P2V(soc ## _ ## name ## _BASE_ADDR),      \
         .pfn = __phys_to_pfn(soc ## _ ## name ## _BASE_ADDR),           \
diff --git a/arch/arm/plat-mxc/include/mach/io.h b/arch/arm/plat-mxc/include/mach/io.h
index b4f2de76946..4347a87d2bb 100644
--- a/arch/arm/plat-mxc/include/mach/io.h
+++ b/arch/arm/plat-mxc/include/mach/io.h
@@ -14,19 +14,26 @@
 /* Allow IO space to be anywhere in the memory */
 #define IO_SPACE_LIMIT 0xffffffff
 
-#ifdef CONFIG_ARCH_MX3
-#define __arch_ioremap __mx3_ioremap
+#if defined(CONFIG_SOC_IMX31) || defined(CONFIG_SOC_IMX35)
+#include <mach/hardware.h>
+
+#define __arch_ioremap __imx_ioremap
 #define __arch_iounmap __iounmap
 
+#define addr_in_module(addr, mod) \
+        ((unsigned long)(addr) - mod ## _BASE_ADDR < mod ## _SIZE)
+
 static inline void __iomem *
-__mx3_ioremap(unsigned long phys_addr, size_t size, unsigned int mtype)
+__imx_ioremap(unsigned long phys_addr, size_t size, unsigned int mtype)
 {
-        if (mtype == MT_DEVICE) {
-                /* Access all peripherals below 0x80000000 as nonshared device
-                 * but leave l2cc alone.
+        if (mtype == MT_DEVICE && (cpu_is_mx31() || cpu_is_mx35())) {
+                /*
+                 * Access all peripherals below 0x80000000 as nonshared device
+                 * on mx3, but leave l2cc alone.  Otherwise cache corruptions
+                 * can occur.
                  */
-                if ((phys_addr < 0x80000000) && ((phys_addr < 0x30000000) ||
-                        (phys_addr >= 0x30000000 + SZ_1M)))
+                if (phys_addr < 0x80000000 &&
+                                !addr_in_module(phys_addr, MX3x_L2CC))
                         mtype = MT_DEVICE_NONSHARED;
         }
 
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx25.h b/arch/arm/plat-mxc/include/mach/iomux-mx25.h
index d7f52c91f82..2e5244de7ff 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-mx25.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-mx25.h
@@ -89,13 +89,16 @@
 #define MX25_PAD_CS0__GPIO_4_2          IOMUX_PAD(0x000, 0x04c, 0x05, 0, 0, NO_PAD_CTRL)
 
 #define MX25_PAD_CS1__CS1               IOMUX_PAD(0x000, 0x050, 0x00, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_CS1__NF_CE3            IOMUX_PAD(0x000, 0x050, 0x01, 0, 0, NO_PAD_CTRL)
 #define MX25_PAD_CS1__GPIO_4_3          IOMUX_PAD(0x000, 0x050, 0x05, 0, 0, NO_PAD_CTRL)
 
 #define MX25_PAD_CS4__CS4               IOMUX_PAD(0x264, 0x054, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_CS4__NF_CE1            IOMUX_PAD(0x264, 0x054, 0x01, 0, 0, NO_PAD_CTRL)
 #define MX25_PAD_CS4__UART5_CTS         IOMUX_PAD(0x264, 0x054, 0x13, 0, 0, NO_PAD_CTRL)
 #define MX25_PAD_CS4__GPIO_3_20         IOMUX_PAD(0x264, 0x054, 0x15, 0, 0, NO_PAD_CTRL)
 
 #define MX25_PAD_CS5__CS5               IOMUX_PAD(0x268, 0x058, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_CS5__NF_CE2            IOMUX_PAD(0x268, 0x058, 0x01, 0, 0, NO_PAD_CTRL)
 #define MX25_PAD_CS5__UART5_RTS         IOMUX_PAD(0x268, 0x058, 0x13, 0x574, 0, NO_PAD_CTRL)
 #define MX25_PAD_CS5__GPIO_3_21         IOMUX_PAD(0x268, 0x058, 0x15, 0, 0, NO_PAD_CTRL)
 
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mxc91231.h b/arch/arm/plat-mxc/include/mach/iomux-mxc91231.h
deleted file mode 100644
index bf28df0d58b..00000000000
--- a/arch/arm/plat-mxc/include/mach/iomux-mxc91231.h
+++ /dev/null
@@ -1,283 +0,0 @@
-/*
- * Copyright 2004-2006 Freescale Semiconductor, Inc. All Rights Reserved.
- * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de>
- * Copyright (C) 2009 by Dmitriy Taychenachev <dimichxp@gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#ifndef __MACH_IOMUX_MXC91231_H__
-#define __MACH_IOMUX_MXC91231_H__
-
-/*
- * various IOMUX output functions
- */
-
-#define IOMUX_OCONFIG_GPIO (0 << 4)     /* used as GPIO */
-#define IOMUX_OCONFIG_FUNC (1 << 4)     /* used as function */
-#define IOMUX_OCONFIG_ALT1 (2 << 4)     /* used as alternate function 1 */
-#define IOMUX_OCONFIG_ALT2 (3 << 4)     /* used as alternate function 2 */
-#define IOMUX_OCONFIG_ALT3 (4 << 4)     /* used as alternate function 3 */
-#define IOMUX_OCONFIG_ALT4 (5 << 4)     /* used as alternate function 4 */
-#define IOMUX_OCONFIG_ALT5 (6 << 4)     /* used as alternate function 5 */
-#define IOMUX_OCONFIG_ALT6 (7 << 4)     /* used as alternate function 6 */
-#define IOMUX_ICONFIG_NONE  0           /* not configured for input */
-#define IOMUX_ICONFIG_GPIO  1           /* used as GPIO */
-#define IOMUX_ICONFIG_FUNC  2           /* used as function */
-#define IOMUX_ICONFIG_ALT1  4           /* used as alternate function 1 */
-#define IOMUX_ICONFIG_ALT2  8           /* used as alternate function 2 */
-
-#define IOMUX_CONFIG_GPIO (IOMUX_OCONFIG_GPIO | IOMUX_ICONFIG_GPIO)
-#define IOMUX_CONFIG_FUNC (IOMUX_OCONFIG_FUNC | IOMUX_ICONFIG_FUNC)
-#define IOMUX_CONFIG_ALT1 (IOMUX_OCONFIG_ALT1 | IOMUX_ICONFIG_ALT1)
-#define IOMUX_CONFIG_ALT2 (IOMUX_OCONFIG_ALT2 | IOMUX_ICONFIG_ALT2)
-
-/*
- * setups a single pin:
- *      - reserves the pin so that it is not claimed by another driver
- *      - setups the iomux according to the configuration
- *      - if the pin is configured as a GPIO, we claim it through kernel gpiolib
- */
-int mxc_iomux_alloc_pin(unsigned int pin_mode, const char *label);
-/*
- * setups mutliple pins
- * convenient way to call the above function with tables
- */
-int mxc_iomux_setup_multiple_pins(const unsigned int *pin_list, unsigned count,
-                const char *label);
-
-/*
- * releases a single pin:
- *      - make it available for a future use by another driver
- *      - frees the GPIO if the pin was configured as GPIO
- *      - DOES NOT reconfigure the IOMUX in its reset state
- */
-void mxc_iomux_release_pin(unsigned int pin_mode);
-/*
- * releases multiple pins
- * convenvient way to call the above function with tables
- */
-void mxc_iomux_release_multiple_pins(const unsigned int *pin_list, int count);
-
-#define MUX_SIDE_AP             (0)
-#define MUX_SIDE_SP             (1)
-
-#define MUX_SIDE_SHIFT          (26)
-#define MUX_SIDE_MASK           (0x1 << MUX_SIDE_SHIFT)
-
-#define MUX_GPIO_PORT_SHIFT     (23)
-#define MUX_GPIO_PORT_MASK      (0x7 << MUX_GPIO_PORT_SHIFT)
-
-#define MUX_GPIO_PIN_SHIFT      (20)
-#define MUX_GPIO_PIN_MASK       (0x1f << MUX_GPIO_PIN_SHIFT)
-
-#define MUX_REG_SHIFT           (15)
-#define MUX_REG_MASK            (0x1f << MUX_REG_SHIFT)
-
-#define MUX_FIELD_SHIFT         (13)
-#define MUX_FIELD_MASK          (0x3 << MUX_FIELD_SHIFT)
-
-#define MUX_PADGRP_SHIFT        (8)
-#define MUX_PADGRP_MASK         (0x1f << MUX_PADGRP_SHIFT)
-
-#define MUX_PIN_MASK            (0xffffff << 8)
-
-#define GPIO_PORT_MAX           (3)
-
-#define IOMUX_PIN(side, gport, gpin, ctlreg, ctlfield, padgrp) \
-        (((side) << MUX_SIDE_SHIFT) |             \
-         (gport << MUX_GPIO_PORT_SHIFT) |               \
-         ((gpin) << MUX_GPIO_PIN_SHIFT) |               \
-         ((ctlreg) << MUX_REG_SHIFT) |          \
-         ((ctlfield) << MUX_FIELD_SHIFT) |              \
-         ((padgrp) << MUX_PADGRP_SHIFT))
-
-#define MUX_MODE_OUT_SHIFT      (4)
-#define MUX_MODE_IN_SHIFT       (0)
-#define MUX_MODE_SHIFT          (0)
-#define MUX_MODE_MASK           (0xff << MUX_MODE_SHIFT)
-
-#define IOMUX_MODE(pin, mode) \
-        (pin | (mode << MUX_MODE_SHIFT))
-
-enum iomux_pins {
-        /* AP Side pins */
-        MXC91231_PIN_AP_CLE             = IOMUX_PIN(0, 0,  0,  0, 0, 24),
-        MXC91231_PIN_AP_ALE             = IOMUX_PIN(0, 0,  1,  0, 1, 24),
-        MXC91231_PIN_AP_CE_B            = IOMUX_PIN(0, 0,  2,  0, 2, 24),
-        MXC91231_PIN_AP_RE_B            = IOMUX_PIN(0, 0,  3,  0, 3, 24),
-        MXC91231_PIN_AP_WE_B            = IOMUX_PIN(0, 0,  4,  1, 0, 24),
-        MXC91231_PIN_AP_WP_B            = IOMUX_PIN(0, 0,  5,  1, 1, 24),
-        MXC91231_PIN_AP_BSY_B           = IOMUX_PIN(0, 0,  6,  1, 2, 24),
-        MXC91231_PIN_AP_U1_TXD          = IOMUX_PIN(0, 0,  7,  1, 3, 28),
-        MXC91231_PIN_AP_U1_RXD          = IOMUX_PIN(0, 0,  8,  2, 0, 28),
-        MXC91231_PIN_AP_U1_RTS_B        = IOMUX_PIN(0, 0,  9,  2, 1, 28),
-        MXC91231_PIN_AP_U1_CTS_B        = IOMUX_PIN(0, 0, 10,  2, 2, 28),
-        MXC91231_PIN_AP_AD1_TXD         = IOMUX_PIN(0, 0, 11,  2, 3,  9),
-        MXC91231_PIN_AP_AD1_RXD         = IOMUX_PIN(0, 0, 12,  3, 0,  9),
-        MXC91231_PIN_AP_AD1_TXC         = IOMUX_PIN(0, 0, 13,  3, 1,  9),
-        MXC91231_PIN_AP_AD1_TXFS        = IOMUX_PIN(0, 0, 14,  3, 2,  9),
-        MXC91231_PIN_AP_AD2_TXD         = IOMUX_PIN(0, 0, 15,  3, 3,  9),
-        MXC91231_PIN_AP_AD2_RXD         = IOMUX_PIN(0, 0, 16,  4, 0,  9),
-        MXC91231_PIN_AP_AD2_TXC         = IOMUX_PIN(0, 0, 17,  4, 1,  9),
-        MXC91231_PIN_AP_AD2_TXFS        = IOMUX_PIN(0, 0, 18,  4, 2,  9),
-        MXC91231_PIN_AP_OWDAT           = IOMUX_PIN(0, 0, 19,  4, 3, 28),
-        MXC91231_PIN_AP_IPU_LD17        = IOMUX_PIN(0, 0, 20,  5, 0, 28),
-        MXC91231_PIN_AP_IPU_D3_VSYNC    = IOMUX_PIN(0, 0, 21,  5, 1, 28),
-        MXC91231_PIN_AP_IPU_D3_HSYNC    = IOMUX_PIN(0, 0, 22,  5, 2, 28),
-        MXC91231_PIN_AP_IPU_D3_CLK      = IOMUX_PIN(0, 0, 23,  5, 3, 28),
-        MXC91231_PIN_AP_IPU_D3_DRDY     = IOMUX_PIN(0, 0, 24,  6, 0, 28),
-        MXC91231_PIN_AP_IPU_D3_CONTR    = IOMUX_PIN(0, 0, 25,  6, 1, 28),
-        MXC91231_PIN_AP_IPU_D0_CS       = IOMUX_PIN(0, 0, 26,  6, 2, 28),
-        MXC91231_PIN_AP_IPU_LD16        = IOMUX_PIN(0, 0, 27,  6, 3, 28),
-        MXC91231_PIN_AP_IPU_D2_CS       = IOMUX_PIN(0, 0, 28,  7, 0, 28),
-        MXC91231_PIN_AP_IPU_PAR_RS      = IOMUX_PIN(0, 0, 29,  7, 1, 28),
-        MXC91231_PIN_AP_IPU_D3_PS       = IOMUX_PIN(0, 0, 30,  7, 2, 28),
-        MXC91231_PIN_AP_IPU_D3_CLS      = IOMUX_PIN(0, 0, 31,  7, 3, 28),
-        MXC91231_PIN_AP_IPU_RD          = IOMUX_PIN(0, 1,  0,  8, 0, 28),
-        MXC91231_PIN_AP_IPU_WR          = IOMUX_PIN(0, 1,  1,  8, 1, 28),
-        MXC91231_PIN_AP_IPU_LD0         = IOMUX_PIN(0, 7,  0,  8, 2, 28),
-        MXC91231_PIN_AP_IPU_LD1         = IOMUX_PIN(0, 7,  0,  8, 3, 28),
-        MXC91231_PIN_AP_IPU_LD2         = IOMUX_PIN(0, 7,  0,  9, 0, 28),
-        MXC91231_PIN_AP_IPU_LD3         = IOMUX_PIN(0, 1,  2,  9, 1, 28),
-        MXC91231_PIN_AP_IPU_LD4         = IOMUX_PIN(0, 1,  3,  9, 2, 28),
-        MXC91231_PIN_AP_IPU_LD5         = IOMUX_PIN(0, 1,  4,  9, 3, 28),
-        MXC91231_PIN_AP_IPU_LD6         = IOMUX_PIN(0, 1,  5, 10, 0, 28),
-        MXC91231_PIN_AP_IPU_LD7         = IOMUX_PIN(0, 1,  6, 10, 1, 28),
-        MXC91231_PIN_AP_IPU_LD8         = IOMUX_PIN(0, 1,  7, 10, 2, 28),
-        MXC91231_PIN_AP_IPU_LD9         = IOMUX_PIN(0, 1,  8, 10, 3, 28),
-        MXC91231_PIN_AP_IPU_LD10        = IOMUX_PIN(0, 1,  9, 11, 0, 28),
-        MXC91231_PIN_AP_IPU_LD11        = IOMUX_PIN(0, 1, 10, 11, 1, 28),
-        MXC91231_PIN_AP_IPU_LD12        = IOMUX_PIN(0, 1, 11, 11, 2, 28),
-        MXC91231_PIN_AP_IPU_LD13        = IOMUX_PIN(0, 1, 12, 11, 3, 28),
-        MXC91231_PIN_AP_IPU_LD14        = IOMUX_PIN(0, 1, 13, 12, 0, 28),
-        MXC91231_PIN_AP_IPU_LD15        = IOMUX_PIN(0, 1, 14, 12, 1, 28),
-        MXC91231_PIN_AP_KPROW4          = IOMUX_PIN(0, 7,  0, 12, 2, 10),
-        MXC91231_PIN_AP_KPROW5          = IOMUX_PIN(0, 1, 16, 12, 3, 10),
-        MXC91231_PIN_AP_GPIO_AP_B17     = IOMUX_PIN(0, 1, 17, 13, 0, 10),
-        MXC91231_PIN_AP_GPIO_AP_B18     = IOMUX_PIN(0, 1, 18, 13, 1, 10),
-        MXC91231_PIN_AP_KPCOL3          = IOMUX_PIN(0, 1, 19, 13, 2, 11),
-        MXC91231_PIN_AP_KPCOL4          = IOMUX_PIN(0, 1, 20, 13, 3, 11),
-        MXC91231_PIN_AP_KPCOL5          = IOMUX_PIN(0, 1, 21, 14, 0, 11),
-        MXC91231_PIN_AP_GPIO_AP_B22     = IOMUX_PIN(0, 1, 22, 14, 1, 11),
-        MXC91231_PIN_AP_GPIO_AP_B23     = IOMUX_PIN(0, 1, 23, 14, 2, 11),
-        MXC91231_PIN_AP_CSI_D0          = IOMUX_PIN(0, 1, 24, 14, 3, 21),
-        MXC91231_PIN_AP_CSI_D1          = IOMUX_PIN(0, 1, 25, 15, 0, 21),
-        MXC91231_PIN_AP_CSI_D2          = IOMUX_PIN(0, 1, 26, 15, 1, 21),
-        MXC91231_PIN_AP_CSI_D3          = IOMUX_PIN(0, 1, 27, 15, 2, 21),
-        MXC91231_PIN_AP_CSI_D4          = IOMUX_PIN(0, 1, 28, 15, 3, 21),
-        MXC91231_PIN_AP_CSI_D5          = IOMUX_PIN(0, 1, 29, 16, 0, 21),
-        MXC91231_PIN_AP_CSI_D6          = IOMUX_PIN(0, 1, 30, 16, 1, 21),
-        MXC91231_PIN_AP_CSI_D7          = IOMUX_PIN(0, 1, 31, 16, 2, 21),
-        MXC91231_PIN_AP_CSI_D8          = IOMUX_PIN(0, 2,  0, 16, 3, 21),
-        MXC91231_PIN_AP_CSI_D9          = IOMUX_PIN(0, 2,  1, 17, 0, 21),
-        MXC91231_PIN_AP_CSI_MCLK        = IOMUX_PIN(0, 2,  2, 17, 1, 21),
-        MXC91231_PIN_AP_CSI_VSYNC       = IOMUX_PIN(0, 2,  3, 17, 2, 21),
-        MXC91231_PIN_AP_CSI_HSYNC       = IOMUX_PIN(0, 2,  4, 17, 3, 21),
-        MXC91231_PIN_AP_CSI_PIXCLK      = IOMUX_PIN(0, 2,  5, 18, 0, 21),
-        MXC91231_PIN_AP_I2CLK           = IOMUX_PIN(0, 2,  6, 18, 1, 12),
-        MXC91231_PIN_AP_I2DAT           = IOMUX_PIN(0, 2,  7, 18, 2, 12),
-        MXC91231_PIN_AP_GPIO_AP_C8      = IOMUX_PIN(0, 2,  8, 18, 3,  9),
-        MXC91231_PIN_AP_GPIO_AP_C9      = IOMUX_PIN(0, 2,  9, 19, 0,  9),
-        MXC91231_PIN_AP_GPIO_AP_C10     = IOMUX_PIN(0, 2, 10, 19, 1,  9),
-        MXC91231_PIN_AP_GPIO_AP_C11     = IOMUX_PIN(0, 2, 11, 19, 2,  9),
-        MXC91231_PIN_AP_GPIO_AP_C12     = IOMUX_PIN(0, 2, 12, 19, 3,  9),
-        MXC91231_PIN_AP_GPIO_AP_C13     = IOMUX_PIN(0, 2, 13, 20, 0, 28),
-        MXC91231_PIN_AP_GPIO_AP_C14     = IOMUX_PIN(0, 2, 14, 20, 1, 28),
-        MXC91231_PIN_AP_GPIO_AP_C15     = IOMUX_PIN(0, 2, 15, 20, 2,  9),
-        MXC91231_PIN_AP_GPIO_AP_C16     = IOMUX_PIN(0, 2, 16, 20, 3,  9),
-        MXC91231_PIN_AP_GPIO_AP_C17     = IOMUX_PIN(0, 2, 17, 21, 0,  9),
-        MXC91231_PIN_AP_ED_INT0         = IOMUX_PIN(0, 2, 18, 21, 1, 22),
-        MXC91231_PIN_AP_ED_INT1         = IOMUX_PIN(0, 2, 19, 21, 2, 22),
-        MXC91231_PIN_AP_ED_INT2         = IOMUX_PIN(0, 2, 20, 21, 3, 22),
-        MXC91231_PIN_AP_ED_INT3         = IOMUX_PIN(0, 2, 21, 22, 0, 22),
-        MXC91231_PIN_AP_ED_INT4         = IOMUX_PIN(0, 2, 22, 22, 1, 23),
-        MXC91231_PIN_AP_ED_INT5         = IOMUX_PIN(0, 2, 23, 22, 2, 23),
-        MXC91231_PIN_AP_ED_INT6         = IOMUX_PIN(0, 2, 24, 22, 3, 23),
-        MXC91231_PIN_AP_ED_INT7         = IOMUX_PIN(0, 2, 25, 23, 0, 23),
-        MXC91231_PIN_AP_U2_DSR_B        = IOMUX_PIN(0, 2, 26, 23, 1, 28),
-        MXC91231_PIN_AP_U2_RI_B         = IOMUX_PIN(0, 2, 27, 23, 2, 28),
-        MXC91231_PIN_AP_U2_CTS_B        = IOMUX_PIN(0, 2, 28, 23, 3, 28),
-        MXC91231_PIN_AP_U2_DTR_B        = IOMUX_PIN(0, 2, 29, 24, 0, 28),
-        MXC91231_PIN_AP_KPROW0          = IOMUX_PIN(0, 7,  0, 24, 1, 10),
-        MXC91231_PIN_AP_KPROW1          = IOMUX_PIN(0, 1, 15, 24, 2, 10),
-        MXC91231_PIN_AP_KPROW2          = IOMUX_PIN(0, 7,  0, 24, 3, 10),
-        MXC91231_PIN_AP_KPROW3          = IOMUX_PIN(0, 7,  0, 25, 0, 10),
-        MXC91231_PIN_AP_KPCOL0          = IOMUX_PIN(0, 7,  0, 25, 1, 11),
-        MXC91231_PIN_AP_KPCOL1          = IOMUX_PIN(0, 7,  0, 25, 2, 11),
-        MXC91231_PIN_AP_KPCOL2          = IOMUX_PIN(0, 7,  0, 25, 3, 11),
-
-        /* Shared pins */
-        MXC91231_PIN_SP_U3_TXD          = IOMUX_PIN(1, 3,  0,  0, 0, 28),
-        MXC91231_PIN_SP_U3_RXD          = IOMUX_PIN(1, 3,  1,  0, 1, 28),
-        MXC91231_PIN_SP_U3_RTS_B        = IOMUX_PIN(1, 3,  2,  0, 2, 28),
-        MXC91231_PIN_SP_U3_CTS_B        = IOMUX_PIN(1, 3,  3,  0, 3, 28),
-        MXC91231_PIN_SP_USB_TXOE_B      = IOMUX_PIN(1, 3,  4,  1, 0, 28),
-        MXC91231_PIN_SP_USB_DAT_VP      = IOMUX_PIN(1, 3,  5,  1, 1, 28),
-        MXC91231_PIN_SP_USB_SE0_VM      = IOMUX_PIN(1, 3,  6,  1, 2, 28),
-        MXC91231_PIN_SP_USB_RXD         = IOMUX_PIN(1, 3,  7,  1, 3, 28),
-        MXC91231_PIN_SP_UH2_TXOE_B      = IOMUX_PIN(1, 3,  8,  2, 0, 28),
-        MXC91231_PIN_SP_UH2_SPEED       = IOMUX_PIN(1, 3,  9,  2, 1, 28),
-        MXC91231_PIN_SP_UH2_SUSPEN      = IOMUX_PIN(1, 3, 10,  2, 2, 28),
-        MXC91231_PIN_SP_UH2_TXDP        = IOMUX_PIN(1, 3, 11,  2, 3, 28),
-        MXC91231_PIN_SP_UH2_RXDP        = IOMUX_PIN(1, 3, 12,  3, 0, 28),
-        MXC91231_PIN_SP_UH2_RXDM        = IOMUX_PIN(1, 3, 13,  3, 1, 28),
-        MXC91231_PIN_SP_UH2_OVR         = IOMUX_PIN(1, 3, 14,  3, 2, 28),
-        MXC91231_PIN_SP_UH2_PWR         = IOMUX_PIN(1, 3, 15,  3, 3, 28),
-        MXC91231_PIN_SP_SD1_DAT0        = IOMUX_PIN(1, 3, 16,  4, 0, 25),
-        MXC91231_PIN_SP_SD1_DAT1        = IOMUX_PIN(1, 3, 17,  4, 1, 25),
-        MXC91231_PIN_SP_SD1_DAT2        = IOMUX_PIN(1, 3, 18,  4, 2, 25),
-        MXC91231_PIN_SP_SD1_DAT3        = IOMUX_PIN(1, 3, 19,  4, 3, 25),
-        MXC91231_PIN_SP_SD1_CMD         = IOMUX_PIN(1, 3, 20,  5, 0, 25),
-        MXC91231_PIN_SP_SD1_CLK         = IOMUX_PIN(1, 3, 21,  5, 1, 25),
-        MXC91231_PIN_SP_SD2_DAT0        = IOMUX_PIN(1, 3, 22,  5, 2, 26),
-        MXC91231_PIN_SP_SD2_DAT1        = IOMUX_PIN(1, 3, 23,  5, 3, 26),
-        MXC91231_PIN_SP_SD2_DAT2        = IOMUX_PIN(1, 3, 24,  6, 0, 26),
-        MXC91231_PIN_SP_SD2_DAT3        = IOMUX_PIN(1, 3, 25,  6, 1, 26),
-        MXC91231_PIN_SP_GPIO_SP_A26     = IOMUX_PIN(1, 3, 26,  6, 2, 28),
-        MXC91231_PIN_SP_SPI1_CLK        = IOMUX_PIN(1, 3, 27,  6, 3, 13),
-        MXC91231_PIN_SP_SPI1_MOSI       = IOMUX_PIN(1, 3, 28,  7, 0, 13),
-        MXC91231_PIN_SP_SPI1_MISO       = IOMUX_PIN(1, 3, 29,  7, 1, 13),
-        MXC91231_PIN_SP_SPI1_SS0        = IOMUX_PIN(1, 3, 30,  7, 2, 13),
-        MXC91231_PIN_SP_SPI1_SS1        = IOMUX_PIN(1, 3, 31,  7, 3, 13),
-        MXC91231_PIN_SP_SD2_CMD         = IOMUX_PIN(1, 7,  0,  8, 0, 26),
-        MXC91231_PIN_SP_SD2_CLK         = IOMUX_PIN(1, 7,  0,  8, 1, 26),
-        MXC91231_PIN_SP_SIM1_RST_B      = IOMUX_PIN(1, 2, 30,  8, 2, 28),
-        MXC91231_PIN_SP_SIM1_SVEN       = IOMUX_PIN(1, 7,  0,  8, 3, 28),
-        MXC91231_PIN_SP_SIM1_CLK        = IOMUX_PIN(1, 7,  0,  9, 0, 28),
-        MXC91231_PIN_SP_SIM1_TRXD       = IOMUX_PIN(1, 7,  0,  9, 1, 28),
-        MXC91231_PIN_SP_SIM1_PD         = IOMUX_PIN(1, 2, 31,  9, 2, 28),
-        MXC91231_PIN_SP_UH2_TXDM        = IOMUX_PIN(1, 7,  0,  9, 3, 28),
-        MXC91231_PIN_SP_UH2_RXD         = IOMUX_PIN(1, 7,  0, 10, 0, 28),
-};
-
-#define PIN_AP_MAX      (104)
-#define PIN_SP_MAX      (41)
-
-#define PIN_MAX         (PIN_AP_MAX + PIN_SP_MAX)
-
-/*
- * Convenience values for use with mxc_iomux_mode()
- *
- * Format here is MXC91231_PIN_(pin name)__(function)
- */
-
-#define MXC91231_PIN_SP_USB_DAT_VP__USB_DAT_VP \
-        IOMUX_MODE(MXC91231_PIN_SP_USB_DAT_VP, IOMUX_CONFIG_FUNC)
-#define MXC91231_PIN_SP_USB_SE0_VM__USB_SE0_VM \
-        IOMUX_MODE(MXC91231_PIN_SP_USB_SE0_VM, IOMUX_CONFIG_FUNC)
-#define MXC91231_PIN_SP_USB_DAT_VP__RXD2 \
-        IOMUX_MODE(MXC91231_PIN_SP_USB_DAT_VP, IOMUX_CONFIG_ALT1)
-#define MXC91231_PIN_SP_USB_SE0_VM__TXD2 \
-        IOMUX_MODE(MXC91231_PIN_SP_USB_SE0_VM, IOMUX_CONFIG_ALT1)
-
-
-#endif /* __MACH_IOMUX_MXC91231_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/irqs.h b/arch/arm/plat-mxc/include/mach/irqs.h
index a3d930d3e65..35c89bcdf75 100644
--- a/arch/arm/plat-mxc/include/mach/irqs.h
+++ b/arch/arm/plat-mxc/include/mach/irqs.h
@@ -35,8 +35,6 @@
 #define MXC_GPIO_IRQS           (32 * 4)
 #elif defined CONFIG_SOC_IMX51
 #define MXC_GPIO_IRQS           (32 * 4)
-#elif defined CONFIG_ARCH_MXC91231
-#define MXC_GPIO_IRQS           (32 * 4)
 #elif defined CONFIG_ARCH_MX3
 #define MXC_GPIO_IRQS           (32 * 3)
 #endif
diff --git a/arch/arm/plat-mxc/include/mach/memory.h b/arch/arm/plat-mxc/include/mach/memory.h
index 5d51cbb9889..11be5cdbdd1 100644
--- a/arch/arm/plat-mxc/include/mach/memory.h
+++ b/arch/arm/plat-mxc/include/mach/memory.h
@@ -19,7 +19,6 @@
 #define MX50_PHYS_OFFSET        UL(0x70000000)
 #define MX51_PHYS_OFFSET        UL(0x90000000)
 #define MX53_PHYS_OFFSET        UL(0x70000000)
-#define MXC91231_PHYS_OFFSET    UL(0x90000000)
 
 #if !defined(CONFIG_RUNTIME_PHYS_OFFSET)
 # if defined CONFIG_ARCH_MX1
@@ -32,8 +31,6 @@
 #  define PLAT_PHYS_OFFSET              MX27_PHYS_OFFSET
 # elif defined CONFIG_ARCH_MX3
 #  define PLAT_PHYS_OFFSET              MX3x_PHYS_OFFSET
-# elif defined CONFIG_ARCH_MXC91231
-#  define PLAT_PHYS_OFFSET              MXC91231_PHYS_OFFSET
 # elif defined CONFIG_ARCH_MX50
 #  define PLAT_PHYS_OFFSET              MX50_PHYS_OFFSET
 # elif defined CONFIG_ARCH_MX51
diff --git a/arch/arm/plat-mxc/include/mach/mx27.h b/arch/arm/plat-mxc/include/mach/mx27.h
index cbc43ad5ef4..1dc1c522601 100644
--- a/arch/arm/plat-mxc/include/mach/mx27.h
+++ b/arch/arm/plat-mxc/include/mach/mx27.h
@@ -60,8 +60,8 @@
 #define MX27_AUDMUX_BASE_ADDR                   (MX27_AIPI_BASE_ADDR + 0x16000)
 #define MX27_CSPI3_BASE_ADDR                    (MX27_AIPI_BASE_ADDR + 0x17000)
 #define MX27_MSHC_BASE_ADDR                     (MX27_AIPI_BASE_ADDR + 0x18000)
-#define MX27_GPT5_BASE_ADDR                     (MX27_AIPI_BASE_ADDR + 0x19000)
-#define MX27_GPT4_BASE_ADDR                     (MX27_AIPI_BASE_ADDR + 0x1a000)
+#define MX27_GPT4_BASE_ADDR                     (MX27_AIPI_BASE_ADDR + 0x19000)
+#define MX27_GPT5_BASE_ADDR                     (MX27_AIPI_BASE_ADDR + 0x1a000)
 #define MX27_UART5_BASE_ADDR                    (MX27_AIPI_BASE_ADDR + 0x1b000)
 #define MX27_UART6_BASE_ADDR                    (MX27_AIPI_BASE_ADDR + 0x1c000)
 #define MX27_I2C2_BASE_ADDR                     (MX27_AIPI_BASE_ADDR + 0x1d000)
diff --git a/arch/arm/plat-mxc/include/mach/mx53.h b/arch/arm/plat-mxc/include/mach/mx53.h
index ace17864575..9d2a1ef84de 100644
--- a/arch/arm/plat-mxc/include/mach/mx53.h
+++ b/arch/arm/plat-mxc/include/mach/mx53.h
@@ -337,17 +337,4 @@
 #define MX53_INT_GPIO7_LOW      107
 #define MX53_INT_GPIO7_HIGH     108
 
-/* silicon revisions specific to i.MX53 */
-#define MX53_CHIP_REV_1_0               0x10
-#define MX53_CHIP_REV_1_1               0x11
-#define MX53_CHIP_REV_1_2               0x12
-#define MX53_CHIP_REV_1_3               0x13
-#define MX53_CHIP_REV_2_0               0x20
-#define MX53_CHIP_REV_2_1               0x21
-#define MX53_CHIP_REV_2_2               0x22
-#define MX53_CHIP_REV_2_3               0x23
-#define MX53_CHIP_REV_3_0               0x30
-#define MX53_CHIP_REV_3_1               0x31
-#define MX53_CHIP_REV_3_2               0x32
-
 #endif /* ifndef __MACH_MX53_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/mxc.h b/arch/arm/plat-mxc/include/mach/mxc.h
index 1aea818d9d3..4ac53ce97c2 100644
--- a/arch/arm/plat-mxc/include/mach/mxc.h
+++ b/arch/arm/plat-mxc/include/mach/mxc.h
@@ -35,7 +35,6 @@
 #define MXC_CPU_MX50            50
 #define MXC_CPU_MX51            51
 #define MXC_CPU_MX53            53
-#define MXC_CPU_MXC91231        91231
 
 #define IMX_CHIP_REVISION_1_0           0x10
 #define IMX_CHIP_REVISION_1_1           0x11
@@ -177,18 +176,6 @@ extern unsigned int __mxc_cpu_type;
 # define cpu_is_mx53()          (0)
 #endif
 
-#ifdef CONFIG_ARCH_MXC91231
-# ifdef mxc_cpu_type
-#  undef mxc_cpu_type
-#  define mxc_cpu_type __mxc_cpu_type
-# else
-#  define mxc_cpu_type MXC_CPU_MXC91231
-# endif
-# define cpu_is_mxc91231()      (mxc_cpu_type == MXC_CPU_MXC91231)
-#else
-# define cpu_is_mxc91231()      (0)
-#endif
-
 #ifndef __ASSEMBLY__
 
 struct cpu_op {
@@ -207,14 +194,7 @@ enum mxc_cpu_pwr_mode {
 extern struct cpu_op *(*get_cpu_op)(int *op);
 #endif
 
-#if defined(CONFIG_ARCH_MX3) || defined(CONFIG_ARCH_MX2)
-/* These are deprecated, use mx[23][157]_setup_weimcs instead. */
-#define CSCR_U(n) (IO_ADDRESS(WEIM_BASE_ADDR + n * 0x10))
-#define CSCR_L(n) (IO_ADDRESS(WEIM_BASE_ADDR + n * 0x10 + 0x4))
-#define CSCR_A(n) (IO_ADDRESS(WEIM_BASE_ADDR + n * 0x10 + 0x8))
-#endif
-
-#define cpu_is_mx3()    (cpu_is_mx31() || cpu_is_mx35() || cpu_is_mxc91231())
+#define cpu_is_mx3()    (cpu_is_mx31() || cpu_is_mx35())
 #define cpu_is_mx2()    (cpu_is_mx21() || cpu_is_mx27())
 
 #endif /*  __ASM_ARCH_MXC_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/mxc91231.h b/arch/arm/plat-mxc/include/mach/mxc91231.h
deleted file mode 100644
index 765190fe633..00000000000
--- a/arch/arm/plat-mxc/include/mach/mxc91231.h
+++ /dev/null
@@ -1,256 +0,0 @@
-/*
- *  Copyright 2004-2006 Freescale Semiconductor, Inc. All Rights Reserved.
- *    - Platform specific register memory map
- *
- *  Copyright 2005-2007 Motorola, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-#ifndef __MACH_MXC91231_H__
-#define __MACH_MXC91231_H__
-
-/*
- * L2CC
- */
-#define MXC91231_L2CC_BASE_ADDR         0x30000000
-#define MXC91231_L2CC_SIZE              SZ_64K
-
-/*
- * AIPS 1
- */
-#define MXC91231_AIPS1_BASE_ADDR        0x43F00000
-#define MXC91231_AIPS1_SIZE             SZ_1M
-
-#define MXC91231_AIPS1_CTRL_BASE_ADDR   MXC91231_AIPS1_BASE_ADDR
-#define MXC91231_MAX_BASE_ADDR          (MXC91231_AIPS1_BASE_ADDR + 0x04000)
-#define MXC91231_EVTMON_BASE_ADDR       (MXC91231_AIPS1_BASE_ADDR + 0x08000)
-#define MXC91231_CLKCTL_BASE_ADDR       (MXC91231_AIPS1_BASE_ADDR + 0x0C000)
-#define MXC91231_ETB_SLOT4_BASE_ADDR    (MXC91231_AIPS1_BASE_ADDR + 0x10000)
-#define MXC91231_ETB_SLOT5_BASE_ADDR    (MXC91231_AIPS1_BASE_ADDR + 0x14000)
-#define MXC91231_ECT_CTIO_BASE_ADDR     (MXC91231_AIPS1_BASE_ADDR + 0x18000)
-#define MXC91231_I2C_BASE_ADDR          (MXC91231_AIPS1_BASE_ADDR + 0x80000)
-#define MXC91231_MU_BASE_ADDR           (MXC91231_AIPS1_BASE_ADDR + 0x88000)
-#define MXC91231_UART1_BASE_ADDR        (MXC91231_AIPS1_BASE_ADDR + 0x90000)
-#define MXC91231_UART2_BASE_ADDR        (MXC91231_AIPS1_BASE_ADDR + 0x94000)
-#define MXC91231_DSM_BASE_ADDR          (MXC91231_AIPS1_BASE_ADDR + 0x98000)
-#define MXC91231_OWIRE_BASE_ADDR        (MXC91231_AIPS1_BASE_ADDR + 0x9C000)
-#define MXC91231_SSI1_BASE_ADDR         (MXC91231_AIPS1_BASE_ADDR + 0xA0000)
-#define MXC91231_KPP_BASE_ADDR          (MXC91231_AIPS1_BASE_ADDR + 0xA8000)
-#define MXC91231_IOMUX_AP_BASE_ADDR     (MXC91231_AIPS1_BASE_ADDR + 0xAC000)
-#define MXC91231_CTI_AP_BASE_ADDR       (MXC91231_AIPS1_BASE_ADDR + 0xB8000)
-
-/*
- * AIPS 2
- */
-#define MXC91231_AIPS2_BASE_ADDR        0x53F00000
-#define MXC91231_AIPS2_SIZE             SZ_1M
-
-#define MXC91231_GEMK_BASE_ADDR         (MXC91231_AIPS2_BASE_ADDR + 0x8C000)
-#define MXC91231_GPT1_BASE_ADDR         (MXC91231_AIPS2_BASE_ADDR + 0x90000)
-#define MXC91231_EPIT1_AP_BASE_ADDR     (MXC91231_AIPS2_BASE_ADDR + 0x94000)
-#define MXC91231_SCC_BASE_ADDR          (MXC91231_AIPS2_BASE_ADDR + 0xAC000)
-#define MXC91231_RNGA_BASE_ADDR         (MXC91231_AIPS2_BASE_ADDR + 0xB0000)
-#define MXC91231_IPU_CTRL_BASE_ADDR     (MXC91231_AIPS2_BASE_ADDR + 0xC0000)
-#define MXC91231_AUDMUX_BASE_ADDR       (MXC91231_AIPS2_BASE_ADDR + 0xC4000)
-#define MXC91231_EDIO_BASE_ADDR         (MXC91231_AIPS2_BASE_ADDR + 0xC8000)
-#define MXC91231_GPIO1_AP_BASE_ADDR     (MXC91231_AIPS2_BASE_ADDR + 0xCC000)
-#define MXC91231_GPIO2_AP_BASE_ADDR     (MXC91231_AIPS2_BASE_ADDR + 0xD0000)
-#define MXC91231_SDMA_BASE_ADDR         (MXC91231_AIPS2_BASE_ADDR + 0xD4000)
-#define MXC91231_RTC_BASE_ADDR          (MXC91231_AIPS2_BASE_ADDR + 0xD8000)
-#define MXC91231_WDOG1_BASE_ADDR        (MXC91231_AIPS2_BASE_ADDR + 0xDC000)
-#define MXC91231_PWM_BASE_ADDR          (MXC91231_AIPS2_BASE_ADDR + 0xE0000)
-#define MXC91231_GPIO3_AP_BASE_ADDR     (MXC91231_AIPS2_BASE_ADDR + 0xE4000)
-#define MXC91231_WDOG2_BASE_ADDR        (MXC91231_AIPS2_BASE_ADDR + 0xE8000)
-#define MXC91231_RTIC_BASE_ADDR         (MXC91231_AIPS2_BASE_ADDR + 0xEC000)
-#define MXC91231_LPMC_BASE_ADDR         (MXC91231_AIPS2_BASE_ADDR + 0xF0000)
-
-/*
- * SPBA global module 0
- */
-#define MXC91231_SPBA0_BASE_ADDR        0x50000000
-#define MXC91231_SPBA0_SIZE             SZ_1M
-
-#define MXC91231_MMC_SDHC1_BASE_ADDR    (MXC91231_SPBA0_BASE_ADDR + 0x04000)
-#define MXC91231_MMC_SDHC2_BASE_ADDR    (MXC91231_SPBA0_BASE_ADDR + 0x08000)
-#define MXC91231_UART3_BASE_ADDR        (MXC91231_SPBA0_BASE_ADDR + 0x0C000)
-#define MXC91231_CSPI2_BASE_ADDR        (MXC91231_SPBA0_BASE_ADDR + 0x10000)
-#define MXC91231_SSI2_BASE_ADDR         (MXC91231_SPBA0_BASE_ADDR + 0x14000)
-#define MXC91231_SIM_BASE_ADDR          (MXC91231_SPBA0_BASE_ADDR + 0x18000)
-#define MXC91231_IIM_BASE_ADDR          (MXC91231_SPBA0_BASE_ADDR + 0x1C000)
-#define MXC91231_CTI_SDMA_BASE_ADDR     (MXC91231_SPBA0_BASE_ADDR + 0x20000)
-#define MXC91231_USBOTG_CTRL_BASE_ADDR  (MXC91231_SPBA0_BASE_ADDR + 0x24000)
-#define MXC91231_USBOTG_DATA_BASE_ADDR  (MXC91231_SPBA0_BASE_ADDR + 0x28000)
-#define MXC91231_CSPI1_BASE_ADDR        (MXC91231_SPBA0_BASE_ADDR + 0x30000)
-#define MXC91231_SPBA_CTRL_BASE_ADDR    (MXC91231_SPBA0_BASE_ADDR + 0x3C000)
-#define MXC91231_IOMUX_COM_BASE_ADDR    (MXC91231_SPBA0_BASE_ADDR + 0x40000)
-#define MXC91231_CRM_COM_BASE_ADDR      (MXC91231_SPBA0_BASE_ADDR + 0x44000)
-#define MXC91231_CRM_AP_BASE_ADDR       (MXC91231_SPBA0_BASE_ADDR + 0x48000)
-#define MXC91231_PLL0_BASE_ADDR         (MXC91231_SPBA0_BASE_ADDR + 0x4C000)
-#define MXC91231_PLL1_BASE_ADDR         (MXC91231_SPBA0_BASE_ADDR + 0x50000)
-#define MXC91231_PLL2_BASE_ADDR         (MXC91231_SPBA0_BASE_ADDR + 0x54000)
-#define MXC91231_GPIO4_SH_BASE_ADDR     (MXC91231_SPBA0_BASE_ADDR + 0x58000)
-#define MXC91231_HAC_BASE_ADDR          (MXC91231_SPBA0_BASE_ADDR + 0x5C000)
-#define MXC91231_SAHARA_BASE_ADDR       (MXC91231_SPBA0_BASE_ADDR + 0x5C000)
-#define MXC91231_PLL3_BASE_ADDR         (MXC91231_SPBA0_BASE_ADDR + 0x60000)
-
-/*
- * SPBA global module 1
- */
-#define MXC91231_SPBA1_BASE_ADDR        0x52000000
-#define MXC91231_SPBA1_SIZE             SZ_1M
-
-#define MXC91231_MQSPI_BASE_ADDR        (MXC91231_SPBA1_BASE_ADDR + 0x34000)
-#define MXC91231_EL1T_BASE_ADDR         (MXC91231_SPBA1_BASE_ADDR + 0x38000)
-
-/*!
- * Defines for SPBA modules
- */
-#define MXC91231_SPBA_SDHC1             0x04
-#define MXC91231_SPBA_SDHC2             0x08
-#define MXC91231_SPBA_UART3             0x0C
-#define MXC91231_SPBA_CSPI2             0x10
-#define MXC91231_SPBA_SSI2              0x14
-#define MXC91231_SPBA_SIM               0x18
-#define MXC91231_SPBA_IIM               0x1C
-#define MXC91231_SPBA_CTI_SDMA          0x20
-#define MXC91231_SPBA_USBOTG_CTRL_REGS  0x24
-#define MXC91231_SPBA_USBOTG_DATA_REGS  0x28
-#define MXC91231_SPBA_CSPI1             0x30
-#define MXC91231_SPBA_MQSPI             0x34
-#define MXC91231_SPBA_EL1T              0x38
-#define MXC91231_SPBA_IOMUX             0x40
-#define MXC91231_SPBA_CRM_COM           0x44
-#define MXC91231_SPBA_CRM_AP            0x48
-#define MXC91231_SPBA_PLL0              0x4C
-#define MXC91231_SPBA_PLL1              0x50
-#define MXC91231_SPBA_PLL2              0x54
-#define MXC91231_SPBA_GPIO4             0x58
-#define MXC91231_SPBA_SAHARA            0x5C
-
-/*
- * ROMP and AVIC
- */
-#define MXC91231_ROMP_BASE_ADDR         0x60000000
-#define MXC91231_ROMP_SIZE              SZ_64K
-
-#define MXC91231_AVIC_BASE_ADDR         0x68000000
-#define MXC91231_AVIC_SIZE              SZ_64K
-
-/*
- * NAND, SDRAM, WEIM, M3IF, EMI controllers
- */
-#define MXC91231_X_MEMC_BASE_ADDR       0xB8000000
-#define MXC91231_X_MEMC_SIZE            SZ_64K
-
-#define MXC91231_NFC_BASE_ADDR          (MXC91231_X_MEMC_BASE_ADDR + 0x0000)
-#define MXC91231_ESDCTL_BASE_ADDR       (MXC91231_X_MEMC_BASE_ADDR + 0x1000)
-#define MXC91231_WEIM_BASE_ADDR         (MXC91231_X_MEMC_BASE_ADDR + 0x2000)
-#define MXC91231_M3IF_BASE_ADDR         (MXC91231_X_MEMC_BASE_ADDR + 0x3000)
-#define MXC91231_EMI_CTL_BASE_ADDR      (MXC91231_X_MEMC_BASE_ADDR + 0x4000)
-
-/*
- * Memory regions and CS
- * CPLD is connected on CS4
- * CS5 is TP1021 or it is not connected
- * */
-#define MXC91231_FB_RAM_BASE_ADDR       0x78000000
-#define MXC91231_FB_RAM_SIZE            SZ_256K
-#define MXC91231_CSD0_BASE_ADDR         0x80000000
-#define MXC91231_CSD1_BASE_ADDR         0x90000000
-#define MXC91231_CS0_BASE_ADDR          0xA0000000
-#define MXC91231_CS1_BASE_ADDR          0xA8000000
-#define MXC91231_CS2_BASE_ADDR          0xB0000000
-#define MXC91231_CS3_BASE_ADDR          0xB2000000
-#define MXC91231_CS4_BASE_ADDR          0xB4000000
-#define MXC91231_CS5_BASE_ADDR          0xB6000000
-
-/*
- * This macro defines the physical to virtual address mapping for all the
- * peripheral modules. It is used by passing in the physical address as x
- * and returning the virtual address.
- */
-#define MXC91231_IO_P2V(x)              IMX_IO_P2V(x)
-#define MXC91231_IO_ADDRESS(x)          IOMEM(MXC91231_IO_P2V(x))
-
-/*
- * Interrupt numbers
- */
-#define MXC91231_INT_GPIO3              0
-#define MXC91231_INT_EL1T_CI            1
-#define MXC91231_INT_EL1T_RFCI          2
-#define MXC91231_INT_EL1T_RFI           3
-#define MXC91231_INT_EL1T_MCU           4
-#define MXC91231_INT_EL1T_IPI           5
-#define MXC91231_INT_MU_GEN             6
-#define MXC91231_INT_GPIO4              7
-#define MXC91231_INT_MMC_SDHC2          8
-#define MXC91231_INT_MMC_SDHC1          9
-#define MXC91231_INT_I2C                10
-#define MXC91231_INT_SSI2               11
-#define MXC91231_INT_SSI1               12
-#define MXC91231_INT_CSPI2              13
-#define MXC91231_INT_CSPI1              14
-#define MXC91231_INT_RTIC               15
-#define MXC91231_INT_SAHARA             15
-#define MXC91231_INT_HAC                15
-#define MXC91231_INT_UART3_RX           16
-#define MXC91231_INT_UART3_TX           17
-#define MXC91231_INT_UART3_MINT         18
-#define MXC91231_INT_ECT                19
-#define MXC91231_INT_SIM_IPB            20
-#define MXC91231_INT_SIM_DATA           21
-#define MXC91231_INT_RNGA               22
-#define MXC91231_INT_DSM_AP             23
-#define MXC91231_INT_KPP                24
-#define MXC91231_INT_RTC                25
-#define MXC91231_INT_PWM                26
-#define MXC91231_INT_GEMK_AP            27
-#define MXC91231_INT_EPIT               28
-#define MXC91231_INT_GPT                29
-#define MXC91231_INT_UART2_RX           30
-#define MXC91231_INT_UART2_TX           31
-#define MXC91231_INT_UART2_MINT         32
-#define MXC91231_INT_NANDFC             33
-#define MXC91231_INT_SDMA               34
-#define MXC91231_INT_USB_WAKEUP         35
-#define MXC91231_INT_USB_SOF            36
-#define MXC91231_INT_PMU_EVTMON         37
-#define MXC91231_INT_USB_FUNC           38
-#define MXC91231_INT_USB_DMA            39
-#define MXC91231_INT_USB_CTRL           40
-#define MXC91231_INT_IPU_ERR            41
-#define MXC91231_INT_IPU_SYN            42
-#define MXC91231_INT_UART1_RX           43
-#define MXC91231_INT_UART1_TX           44
-#define MXC91231_INT_UART1_MINT         45
-#define MXC91231_INT_IIM                46
-#define MXC91231_INT_MU_RX_OR           47
-#define MXC91231_INT_MU_TX_OR           48
-#define MXC91231_INT_SCC_SCM            49
-#define MXC91231_INT_SCC_SMN            50
-#define MXC91231_INT_GPIO2              51
-#define MXC91231_INT_GPIO1              52
-#define MXC91231_INT_MQSPI1             53
-#define MXC91231_INT_MQSPI2             54
-#define MXC91231_INT_WDOG2              55
-#define MXC91231_INT_EXT_INT7           56
-#define MXC91231_INT_EXT_INT6           57
-#define MXC91231_INT_EXT_INT5           58
-#define MXC91231_INT_EXT_INT4           59
-#define MXC91231_INT_EXT_INT3           60
-#define MXC91231_INT_EXT_INT2           61
-#define MXC91231_INT_EXT_INT1           62
-#define MXC91231_INT_EXT_INT0           63
-
-#define MXC91231_MAX_INT_LINES          63
-#define MXC91231_MAX_EXT_LINES          8
-
-#endif /* __MACH_MXC91231_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/system.h b/arch/arm/plat-mxc/include/mach/system.h
index 0417da9f710..51f02a9d41a 100644
--- a/arch/arm/plat-mxc/include/mach/system.h
+++ b/arch/arm/plat-mxc/include/mach/system.h
@@ -24,12 +24,6 @@ extern void mx5_cpu_lp_set(enum mxc_cpu_pwr_mode mode);
 
 static inline void arch_idle(void)
 {
-#ifdef CONFIG_ARCH_MXC91231
-        if (cpu_is_mxc91231()) {
-                /* Need this to set DSM low-power mode */
-                mxc91231_prepare_idle();
-        }
-#endif
         /* fix i.MX31 errata TLSbo65953 and i.MX35 errata ENGcm09472 */
         if (cpu_is_mx31() || cpu_is_mx35()) {
                 unsigned long reg = 0;
diff --git a/arch/arm/plat-mxc/include/mach/timex.h b/arch/arm/plat-mxc/include/mach/timex.h
index 2d9624697cc..d61d5c74817 100644
--- a/arch/arm/plat-mxc/include/mach/timex.h
+++ b/arch/arm/plat-mxc/include/mach/timex.h
@@ -26,8 +26,6 @@
 #define CLOCK_TICK_RATE         16000000
 #elif defined CONFIG_ARCH_MX5
 #define CLOCK_TICK_RATE         8000000
-#elif defined CONFIG_ARCH_MXC91231
-#define CLOCK_TICK_RATE         13000000
 #endif
 
 #endif                          /* __ASM_ARCH_MXC_TIMEX_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/uncompress.h b/arch/arm/plat-mxc/include/mach/uncompress.h
index 4864b0afd44..d85e2d1c032 100644
--- a/arch/arm/plat-mxc/include/mach/uncompress.h
+++ b/arch/arm/plat-mxc/include/mach/uncompress.h
@@ -21,7 +21,7 @@
 
 #include <asm/mach-types.h>
 
-static unsigned long uart_base;
+unsigned long uart_base;
 
 #define UART(x) (*(volatile unsigned long *)(uart_base + (x)))
 
diff --git a/arch/arm/plat-mxc/system.c b/arch/arm/plat-mxc/system.c
index 3455fc0575a..8024f2ac177 100644
--- a/arch/arm/plat-mxc/system.c
+++ b/arch/arm/plat-mxc/system.c
@@ -37,12 +37,6 @@ void arch_reset(char mode, const char *cmd)
 {
         unsigned int wcr_enable;
 
-#ifdef CONFIG_ARCH_MXC91231
-        if (cpu_is_mxc91231()) {
-                mxc91231_arch_reset(mode, cmd);
-                return;
-        }
-#endif
 #ifdef CONFIG_MACH_MX51_EFIKAMX
         if (machine_is_mx51_efikamx()) {
                 mx51_efikamx_reset();
diff --git a/arch/arm/plat-mxc/time.c b/arch/arm/plat-mxc/time.c
index e4ac94a8683..4b0fe285e83 100644
--- a/arch/arm/plat-mxc/time.c
+++ b/arch/arm/plat-mxc/time.c
@@ -54,7 +54,7 @@
 #define MX2_TSTAT_CAPT          (1 << 1)
 #define MX2_TSTAT_COMP          (1 << 0)
 
-/* MX31, MX35, MX25, MXC91231, MX5 */
+/* MX31, MX35, MX25, MX5 */
 #define V2_TCTL_WAITEN          (1 << 3) /* Wait enable mode */
 #define V2_TCTL_CLK_IPG         (1 << 6)
 #define V2_TCTL_FRR             (1 << 9)
diff --git a/arch/arm/plat-nomadik/gpio.c b/arch/arm/plat-nomadik/gpio.c
index f49748eca1a..307b8131aa8 100644
--- a/arch/arm/plat-nomadik/gpio.c
+++ b/arch/arm/plat-nomadik/gpio.c
@@ -23,6 +23,8 @@
 #include <linux/irq.h>
 #include <linux/slab.h>
 
+#include <asm/mach/irq.h>
+
 #include <plat/pincfg.h>
 #include <mach/hardware.h>
 #include <mach/gpio.h>
@@ -681,13 +683,7 @@ static void __nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc,
         struct irq_chip *host_chip = irq_get_chip(irq);
         unsigned int first_irq;
 
-        if (host_chip->irq_mask_ack)
-                host_chip->irq_mask_ack(&desc->irq_data);
-        else {
-                host_chip->irq_mask(&desc->irq_data);
-                if (host_chip->irq_ack)
-                        host_chip->irq_ack(&desc->irq_data);
-        }
+        chained_irq_enter(host_chip, desc);
 
         nmk_chip = irq_get_handler_data(irq);
         first_irq = NOMADIK_GPIO_TO_IRQ(nmk_chip->chip.base);
@@ -698,7 +694,7 @@ static void __nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc,
                 status &= ~BIT(bit);
         }
 
-        host_chip->irq_unmask(&desc->irq_data);
+        chained_irq_exit(host_chip, desc);
 }
 
 static void nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
diff --git a/arch/arm/plat-omap/Kconfig b/arch/arm/plat-omap/Kconfig
index e9c0efc5d4a..49a4c75243f 100644
--- a/arch/arm/plat-omap/Kconfig
+++ b/arch/arm/plat-omap/Kconfig
@@ -19,6 +19,7 @@ config ARCH_OMAP1
 config ARCH_OMAP2PLUS
         bool "TI OMAP2/3/4"
         select CLKDEV_LOOKUP
+        select GENERIC_IRQ_CHIP
         select OMAP_DM_TIMER
         help
           "Systems based on OMAP2, OMAP3 or OMAP4"
diff --git a/arch/arm/plat-omap/gpio.c b/arch/arm/plat-omap/gpio.c
index bd9e32187ea..efb86939019 100644
--- a/arch/arm/plat-omap/gpio.c
+++ b/arch/arm/plat-omap/gpio.c
@@ -1137,8 +1137,9 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
         struct gpio_bank *bank;
         u32 retrigger = 0;
         int unmasked = 0;
+        struct irq_chip *chip = irq_desc_get_chip(desc);
 
-        desc->irq_data.chip->irq_ack(&desc->irq_data);
+        chained_irq_enter(chip, desc);
 
         bank = irq_get_handler_data(irq);
 #ifdef CONFIG_ARCH_OMAP1
@@ -1195,7 +1196,7 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
                 configured, we could unmask GPIO bank interrupt immediately */
                 if (!level_mask && !unmasked) {
                         unmasked = 1;
-                        desc->irq_data.chip->irq_unmask(&desc->irq_data);
+                        chained_irq_exit(chip, desc);
                 }
 
                 isr |= retrigger;
@@ -1231,7 +1232,7 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
         interrupt */
 exit:
         if (!unmasked)
-                desc->irq_data.chip->irq_unmask(&desc->irq_data);
+                chained_irq_exit(chip, desc);
 }
 
 static void gpio_irq_shutdown(struct irq_data *d)
diff --git a/arch/arm/plat-omap/include/plat/uncompress.h b/arch/arm/plat-omap/include/plat/uncompress.h
index 30b891c4a93..565d2664f5a 100644
--- a/arch/arm/plat-omap/include/plat/uncompress.h
+++ b/arch/arm/plat-omap/include/plat/uncompress.h
@@ -27,8 +27,8 @@
 
 #define MDR1_MODE_MASK                  0x07
 
-static volatile u8 *uart_base;
-static int uart_shift;
+volatile u8 *uart_base;
+int uart_shift;
 
 /*
  * Store the DEBUG_LL uart number into memory.
diff --git a/arch/arm/plat-orion/Makefile b/arch/arm/plat-orion/Makefile
index 56021a72e10..95a5fc53b6d 100644
--- a/arch/arm/plat-orion/Makefile
+++ b/arch/arm/plat-orion/Makefile
@@ -2,7 +2,7 @@
 # Makefile for the linux kernel.
 #
 
-obj-y   := irq.o pcie.o time.o
+obj-y   := irq.o pcie.o time.o common.o mpp.o
 obj-m   :=
 obj-n   :=
 obj-    :=
diff --git a/arch/arm/plat-orion/common.c b/arch/arm/plat-orion/common.c
new file mode 100644
index 00000000000..9e5451b3c8e
--- /dev/null
+++ b/arch/arm/plat-orion/common.c
@@ -0,0 +1,957 @@
+/*
+ * arch/arm/plat-orion/common.c
+ *
+ * Marvell Orion SoC common setup code used by multiple mach-/common.c
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/dma-mapping.h>
+#include <linux/serial_8250.h>
+#include <linux/mbus.h>
+#include <linux/ata_platform.h>
+#include <linux/mv643xx_eth.h>
+#include <linux/mv643xx_i2c.h>
+#include <net/dsa.h>
+#include <linux/spi/orion_spi.h>
+#include <plat/orion_wdt.h>
+#include <plat/mv_xor.h>
+#include <plat/ehci-orion.h>
+
+/* Fill in the resources structure and link it into the platform
+   device structure. There is always a memory region, and nearly
+   always an interrupt.*/
+static void fill_resources(struct platform_device *device,
+                           struct resource *resources,
+                           resource_size_t mapbase,
+                           resource_size_t size,
+                           unsigned int irq)
+{
+        device->resource = resources;
+        device->num_resources = 1;
+        resources[0].flags = IORESOURCE_MEM;
+        resources[0].start = mapbase;
+        resources[0].end = mapbase + size;
+
+        if (irq != NO_IRQ) {
+                device->num_resources++;
+                resources[1].flags = IORESOURCE_IRQ;
+                resources[1].start = irq;
+                resources[1].end = irq;
+        }
+}
+
+/*****************************************************************************
+ * UART
+ ****************************************************************************/
+static void __init uart_complete(
+        struct platform_device *orion_uart,
+        struct plat_serial8250_port *data,
+        struct resource *resources,
+        unsigned int membase,
+        resource_size_t mapbase,
+        unsigned int irq,
+        unsigned int uartclk)
+{
+        data->mapbase = mapbase;
+        data->membase = (void __iomem *)membase;
+        data->irq = irq;
+        data->uartclk = uartclk;
+        orion_uart->dev.platform_data = data;
+
+        fill_resources(orion_uart, resources, mapbase, 0xff, irq);
+        platform_device_register(orion_uart);
+}
+
+/*****************************************************************************
+ * UART0
+ ****************************************************************************/
+static struct plat_serial8250_port orion_uart0_data[] = {
+        {
+                .flags          = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
+                .iotype         = UPIO_MEM,
+                .regshift       = 2,
+        }, {
+        },
+};
+
+static struct resource orion_uart0_resources[2];
+
+static struct platform_device orion_uart0 = {
+        .name                   = "serial8250",
+        .id                     = PLAT8250_DEV_PLATFORM,
+};
+
+void __init orion_uart0_init(unsigned int membase,
+                             resource_size_t mapbase,
+                             unsigned int irq,
+                             unsigned int uartclk)
+{
+        uart_complete(&orion_uart0, orion_uart0_data, orion_uart0_resources,
+                      membase, mapbase, irq, uartclk);
+}
+
+/*****************************************************************************
+ * UART1
+ ****************************************************************************/
+static struct plat_serial8250_port orion_uart1_data[] = {
+        {
+                .flags          = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
+                .iotype         = UPIO_MEM,
+                .regshift       = 2,
+        }, {
+        },
+};
+
+static struct resource orion_uart1_resources[2];
+
+static struct platform_device orion_uart1 = {
+        .name                   = "serial8250",
+        .id                     = PLAT8250_DEV_PLATFORM1,
+};
+
+void __init orion_uart1_init(unsigned int membase,
+                             resource_size_t mapbase,
+                             unsigned int irq,
+                             unsigned int uartclk)
+{
+        uart_complete(&orion_uart1, orion_uart1_data, orion_uart1_resources,
+                      membase, mapbase, irq, uartclk);
+}
+
+/*****************************************************************************
+ * UART2
+ ****************************************************************************/
+static struct plat_serial8250_port orion_uart2_data[] = {
+        {
+                .flags          = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
+                .iotype         = UPIO_MEM,
+                .regshift       = 2,
+        }, {
+        },
+};
+
+static struct resource orion_uart2_resources[2];
+
+static struct platform_device orion_uart2 = {
+        .name                   = "serial8250",
+        .id                     = PLAT8250_DEV_PLATFORM2,
+};
+
+void __init orion_uart2_init(unsigned int membase,
+                             resource_size_t mapbase,
+                             unsigned int irq,
+                             unsigned int uartclk)
+{
+        uart_complete(&orion_uart2, orion_uart2_data, orion_uart2_resources,
+                      membase, mapbase, irq, uartclk);
+}
+
+/*****************************************************************************
+ * UART3
+ ****************************************************************************/
+static struct plat_serial8250_port orion_uart3_data[] = {
+        {
+                .flags          = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
+                .iotype         = UPIO_MEM,
+                .regshift       = 2,
+        }, {
+        },
+};
+
+static struct resource orion_uart3_resources[2];
+
+static struct platform_device orion_uart3 = {
+        .name                   = "serial8250",
+        .id                     = 3,
+};
+
+void __init orion_uart3_init(unsigned int membase,
+                             resource_size_t mapbase,
+                             unsigned int irq,
+                             unsigned int uartclk)
+{
+        uart_complete(&orion_uart3, orion_uart3_data, orion_uart3_resources,
+                      membase, mapbase, irq, uartclk);
+}
+
+/*****************************************************************************
+ * SoC RTC
+ ****************************************************************************/
+static struct resource orion_rtc_resource[2];
+
+void __init orion_rtc_init(unsigned long mapbase,
+                           unsigned long irq)
+{
+        orion_rtc_resource[0].start = mapbase;
+        orion_rtc_resource[0].end = mapbase + SZ_32 - 1;
+        orion_rtc_resource[0].flags = IORESOURCE_MEM;
+        orion_rtc_resource[1].start = irq;
+        orion_rtc_resource[1].end = irq;
+        orion_rtc_resource[1].flags = IORESOURCE_IRQ;
+
+        platform_device_register_simple("rtc-mv", -1, orion_rtc_resource, 2);
+}
+
+/*****************************************************************************
+ * GE
+ ****************************************************************************/
+static __init void ge_complete(
+        struct mv643xx_eth_shared_platform_data *orion_ge_shared_data,
+        struct mbus_dram_target_info *mbus_dram_info, int tclk,
+        struct resource *orion_ge_resource, unsigned long irq,
+        struct platform_device *orion_ge_shared,
+        struct mv643xx_eth_platform_data *eth_data,
+        struct platform_device *orion_ge)
+{
+        orion_ge_shared_data->dram = mbus_dram_info;
+        orion_ge_shared_data->t_clk = tclk;
+        orion_ge_resource->start = irq;
+        orion_ge_resource->end = irq;
+        eth_data->shared = orion_ge_shared;
+        orion_ge->dev.platform_data = eth_data;
+
+        platform_device_register(orion_ge_shared);
+        platform_device_register(orion_ge);
+}
+
+/*****************************************************************************
+ * GE00
+ ****************************************************************************/
+struct mv643xx_eth_shared_platform_data orion_ge00_shared_data;
+
+static struct resource orion_ge00_shared_resources[] = {
+        {
+                .name   = "ge00 base",
+        }, {
+                .name   = "ge00 err irq",
+        },
+};
+
+static struct platform_device orion_ge00_shared = {
+        .name           = MV643XX_ETH_SHARED_NAME,
+        .id             = 0,
+        .dev            = {
+                .platform_data  = &orion_ge00_shared_data,
+        },
+};
+
+static struct resource orion_ge00_resources[] = {
+        {
+                .name   = "ge00 irq",
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device orion_ge00 = {
+        .name           = MV643XX_ETH_NAME,
+        .id             = 0,
+        .num_resources  = 1,
+        .resource       = orion_ge00_resources,
+        .dev            = {
+                .coherent_dma_mask      = DMA_BIT_MASK(32),
+        },
+};
+
+void __init orion_ge00_init(struct mv643xx_eth_platform_data *eth_data,
+                            struct mbus_dram_target_info *mbus_dram_info,
+                            unsigned long mapbase,
+                            unsigned long irq,
+                            unsigned long irq_err,
+                            int tclk)
+{
+        fill_resources(&orion_ge00_shared, orion_ge00_shared_resources,
+                       mapbase + 0x2000, SZ_16K - 1, irq_err);
+        ge_complete(&orion_ge00_shared_data, mbus_dram_info, tclk,
+                    orion_ge00_resources, irq, &orion_ge00_shared,
+                    eth_data, &orion_ge00);
+}
+
+/*****************************************************************************
+ * GE01
+ ****************************************************************************/
+struct mv643xx_eth_shared_platform_data orion_ge01_shared_data = {
+        .shared_smi     = &orion_ge00_shared,
+};
+
+static struct resource orion_ge01_shared_resources[] = {
+        {
+                .name   = "ge01 base",
+        }, {
+                .name   = "ge01 err irq",
+        },
+};
+
+static struct platform_device orion_ge01_shared = {
+        .name           = MV643XX_ETH_SHARED_NAME,
+        .id             = 1,
+        .dev            = {
+                .platform_data  = &orion_ge01_shared_data,
+        },
+};
+
+static struct resource orion_ge01_resources[] = {
+        {
+                .name   = "ge01 irq",
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device orion_ge01 = {
+        .name           = MV643XX_ETH_NAME,
+        .id             = 1,
+        .num_resources  = 1,
+        .resource       = orion_ge01_resources,
+        .dev            = {
+                .coherent_dma_mask      = DMA_BIT_MASK(32),
+        },
+};
+
+void __init orion_ge01_init(struct mv643xx_eth_platform_data *eth_data,
+                            struct mbus_dram_target_info *mbus_dram_info,
+                            unsigned long mapbase,
+                            unsigned long irq,
+                            unsigned long irq_err,
+                            int tclk)
+{
+        fill_resources(&orion_ge01_shared, orion_ge01_shared_resources,
+                       mapbase + 0x2000, SZ_16K - 1, irq_err);
+        ge_complete(&orion_ge01_shared_data, mbus_dram_info, tclk,
+                    orion_ge01_resources, irq, &orion_ge01_shared,
+                    eth_data, &orion_ge01);
+}
+
+/*****************************************************************************
+ * GE10
+ ****************************************************************************/
+struct mv643xx_eth_shared_platform_data orion_ge10_shared_data = {
+        .shared_smi     = &orion_ge00_shared,
+};
+
+static struct resource orion_ge10_shared_resources[] = {
+        {
+                .name   = "ge10 base",
+        }, {
+                .name   = "ge10 err irq",
+        },
+};
+
+static struct platform_device orion_ge10_shared = {
+        .name           = MV643XX_ETH_SHARED_NAME,
+        .id             = 1,
+        .dev            = {
+                .platform_data  = &orion_ge10_shared_data,
+        },
+};
+
+static struct resource orion_ge10_resources[] = {
+        {
+                .name   = "ge10 irq",
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device orion_ge10 = {
+        .name           = MV643XX_ETH_NAME,
+        .id             = 1,
+        .num_resources  = 2,
+        .resource       = orion_ge10_resources,
+        .dev            = {
+                .coherent_dma_mask      = DMA_BIT_MASK(32),
+        },
+};
+
+void __init orion_ge10_init(struct mv643xx_eth_platform_data *eth_data,
+                            struct mbus_dram_target_info *mbus_dram_info,
+                            unsigned long mapbase,
+                            unsigned long irq,
+                            unsigned long irq_err,
+                            int tclk)
+{
+        fill_resources(&orion_ge10_shared, orion_ge10_shared_resources,
+                       mapbase + 0x2000, SZ_16K - 1, irq_err);
+        ge_complete(&orion_ge10_shared_data, mbus_dram_info, tclk,
+                    orion_ge10_resources, irq, &orion_ge10_shared,
+                    eth_data, &orion_ge10);
+}
+
+/*****************************************************************************
+ * GE11
+ ****************************************************************************/
+struct mv643xx_eth_shared_platform_data orion_ge11_shared_data = {
+        .shared_smi     = &orion_ge00_shared,
+};
+
+static struct resource orion_ge11_shared_resources[] = {
+        {
+                .name   = "ge11 base",
+        }, {
+                .name   = "ge11 err irq",
+        },
+};
+
+static struct platform_device orion_ge11_shared = {
+        .name           = MV643XX_ETH_SHARED_NAME,
+        .id             = 1,
+        .dev            = {
+                .platform_data  = &orion_ge11_shared_data,
+        },
+};
+
+static struct resource orion_ge11_resources[] = {
+        {
+                .name   = "ge11 irq",
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device orion_ge11 = {
+        .name           = MV643XX_ETH_NAME,
+        .id             = 1,
+        .num_resources  = 2,
+        .resource       = orion_ge11_resources,
+        .dev            = {
+                .coherent_dma_mask      = DMA_BIT_MASK(32),
+        },
+};
+
+void __init orion_ge11_init(struct mv643xx_eth_platform_data *eth_data,
+                            struct mbus_dram_target_info *mbus_dram_info,
+                            unsigned long mapbase,
+                            unsigned long irq,
+                            unsigned long irq_err,
+                            int tclk)
+{
+        fill_resources(&orion_ge11_shared, orion_ge11_shared_resources,
+                       mapbase + 0x2000, SZ_16K - 1, irq_err);
+        ge_complete(&orion_ge11_shared_data, mbus_dram_info, tclk,
+                    orion_ge11_resources, irq, &orion_ge11_shared,
+                    eth_data, &orion_ge11);
+}
+
+/*****************************************************************************
+ * Ethernet switch
+ ****************************************************************************/
+static struct resource orion_switch_resources[] = {
+        {
+                .start  = 0,
+                .end    = 0,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device orion_switch_device = {
+        .name           = "dsa",
+        .id             = 0,
+        .num_resources  = 0,
+        .resource       = orion_switch_resources,
+};
+
+void __init orion_ge00_switch_init(struct dsa_platform_data *d, int irq)
+{
+        int i;
+
+        if (irq != NO_IRQ) {
+                orion_switch_resources[0].start = irq;
+                orion_switch_resources[0].end = irq;
+                orion_switch_device.num_resources = 1;
+        }
+
+        d->netdev = &orion_ge00.dev;
+        for (i = 0; i < d->nr_chips; i++)
+                d->chip[i].mii_bus = &orion_ge00_shared.dev;
+        orion_switch_device.dev.platform_data = d;
+
+        platform_device_register(&orion_switch_device);
+}
+
+/*****************************************************************************
+ * I2C
+ ****************************************************************************/
+static struct mv64xxx_i2c_pdata orion_i2c_pdata = {
+        .freq_n         = 3,
+        .timeout        = 1000, /* Default timeout of 1 second */
+};
+
+static struct resource orion_i2c_resources[2];
+
+static struct platform_device orion_i2c = {
+        .name           = MV64XXX_I2C_CTLR_NAME,
+        .id             = 0,
+        .dev            = {
+                .platform_data  = &orion_i2c_pdata,
+        },
+};
+
+static struct mv64xxx_i2c_pdata orion_i2c_1_pdata = {
+        .freq_n         = 3,
+        .timeout        = 1000, /* Default timeout of 1 second */
+};
+
+static struct resource orion_i2c_1_resources[2];
+
+static struct platform_device orion_i2c_1 = {
+        .name           = MV64XXX_I2C_CTLR_NAME,
+        .id             = 1,
+        .dev            = {
+                .platform_data  = &orion_i2c_1_pdata,
+        },
+};
+
+void __init orion_i2c_init(unsigned long mapbase,
+                           unsigned long irq,
+                           unsigned long freq_m)
+{
+        orion_i2c_pdata.freq_m = freq_m;
+        fill_resources(&orion_i2c, orion_i2c_resources, mapbase,
+                       SZ_32 - 1, irq);
+        platform_device_register(&orion_i2c);
+}
+
+void __init orion_i2c_1_init(unsigned long mapbase,
+                             unsigned long irq,
+                             unsigned long freq_m)
+{
+        orion_i2c_1_pdata.freq_m = freq_m;
+        fill_resources(&orion_i2c_1, orion_i2c_1_resources, mapbase,
+                       SZ_32 - 1, irq);
+        platform_device_register(&orion_i2c_1);
+}
+
+/*****************************************************************************
+ * SPI
+ ****************************************************************************/
+static struct orion_spi_info orion_spi_plat_data;
+static struct resource orion_spi_resources;
+
+static struct platform_device orion_spi = {
+        .name           = "orion_spi",
+        .id             = 0,
+        .dev            = {
+                .platform_data  = &orion_spi_plat_data,
+        },
+};
+
+static struct orion_spi_info orion_spi_1_plat_data;
+static struct resource orion_spi_1_resources;
+
+static struct platform_device orion_spi_1 = {
+        .name           = "orion_spi",
+        .id             = 1,
+        .dev            = {
+                .platform_data  = &orion_spi_1_plat_data,
+        },
+};
+
+/* Note: The SPI silicon core does have interrupts. However the
+ * current Linux software driver does not use interrupts. */
+
+void __init orion_spi_init(unsigned long mapbase,
+                           unsigned long tclk)
+{
+        orion_spi_plat_data.tclk = tclk;
+        fill_resources(&orion_spi, &orion_spi_resources,
+                       mapbase, SZ_512 - 1, NO_IRQ);
+        platform_device_register(&orion_spi);
+}
+
+void __init orion_spi_1_init(unsigned long mapbase,
+                             unsigned long tclk)
+{
+        orion_spi_1_plat_data.tclk = tclk;
+        fill_resources(&orion_spi_1, &orion_spi_1_resources,
+                       mapbase, SZ_512 - 1, NO_IRQ);
+        platform_device_register(&orion_spi_1);
+}
+
+/*****************************************************************************
+ * Watchdog
+ ****************************************************************************/
+static struct orion_wdt_platform_data orion_wdt_data;
+
+static struct platform_device orion_wdt_device = {
+        .name           = "orion_wdt",
+        .id             = -1,
+        .dev            = {
+                .platform_data  = &orion_wdt_data,
+        },
+        .num_resources  = 0,
+};
+
+void __init orion_wdt_init(unsigned long tclk)
+{
+        orion_wdt_data.tclk = tclk;
+        platform_device_register(&orion_wdt_device);
+}
+
+/*****************************************************************************
+ * XOR
+ ****************************************************************************/
+static struct mv_xor_platform_shared_data orion_xor_shared_data;
+
+static u64 orion_xor_dmamask = DMA_BIT_MASK(32);
+
+void __init orion_xor_init_channels(
+        struct mv_xor_platform_data *orion_xor0_data,
+        struct platform_device *orion_xor0_channel,
+        struct mv_xor_platform_data *orion_xor1_data,
+        struct platform_device *orion_xor1_channel)
+{
+        /*
+         * two engines can't do memset simultaneously, this limitation
+         * satisfied by removing memset support from one of the engines.
+         */
+        dma_cap_set(DMA_MEMCPY, orion_xor0_data->cap_mask);
+        dma_cap_set(DMA_XOR, orion_xor0_data->cap_mask);
+        platform_device_register(orion_xor0_channel);
+
+        dma_cap_set(DMA_MEMCPY, orion_xor1_data->cap_mask);
+        dma_cap_set(DMA_MEMSET, orion_xor1_data->cap_mask);
+        dma_cap_set(DMA_XOR, orion_xor1_data->cap_mask);
+        platform_device_register(orion_xor1_channel);
+}
+
+/*****************************************************************************
+ * XOR0
+ ****************************************************************************/
+static struct resource orion_xor0_shared_resources[] = {
+        {
+                .name   = "xor 0 low",
+                .flags  = IORESOURCE_MEM,
+        }, {
+                .name   = "xor 0 high",
+                .flags  = IORESOURCE_MEM,
+        },
+};
+
+static struct platform_device orion_xor0_shared = {
+        .name           = MV_XOR_SHARED_NAME,
+        .id             = 0,
+        .dev            = {
+                .platform_data = &orion_xor_shared_data,
+        },
+        .num_resources  = ARRAY_SIZE(orion_xor0_shared_resources),
+        .resource       = orion_xor0_shared_resources,
+};
+
+static struct resource orion_xor00_resources[] = {
+        [0] = {
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct mv_xor_platform_data orion_xor00_data = {
+        .shared         = &orion_xor0_shared,
+        .hw_id          = 0,
+        .pool_size      = PAGE_SIZE,
+};
+
+static struct platform_device orion_xor00_channel = {
+        .name           = MV_XOR_NAME,
+        .id             = 0,
+        .num_resources  = ARRAY_SIZE(orion_xor00_resources),
+        .resource       = orion_xor00_resources,
+        .dev            = {
+                .dma_mask               = &orion_xor_dmamask,
+                .coherent_dma_mask      = DMA_BIT_MASK(64),
+                .platform_data          = &orion_xor00_data,
+        },
+};
+
+static struct resource orion_xor01_resources[] = {
+        [0] = {
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct mv_xor_platform_data orion_xor01_data = {
+        .shared         = &orion_xor0_shared,
+        .hw_id          = 1,
+        .pool_size      = PAGE_SIZE,
+};
+
+static struct platform_device orion_xor01_channel = {
+        .name           = MV_XOR_NAME,
+        .id             = 1,
+        .num_resources  = ARRAY_SIZE(orion_xor01_resources),
+        .resource       = orion_xor01_resources,
+        .dev            = {
+                .dma_mask               = &orion_xor_dmamask,
+                .coherent_dma_mask      = DMA_BIT_MASK(64),
+                .platform_data          = &orion_xor01_data,
+        },
+};
+
+void __init orion_xor0_init(struct mbus_dram_target_info *mbus_dram_info,
+                            unsigned long mapbase_low,
+                            unsigned long mapbase_high,
+                            unsigned long irq_0,
+                            unsigned long irq_1)
+{
+        orion_xor_shared_data.dram = mbus_dram_info;
+
+        orion_xor0_shared_resources[0].start = mapbase_low;
+        orion_xor0_shared_resources[0].end = mapbase_low + 0xff;
+        orion_xor0_shared_resources[1].start = mapbase_high;
+        orion_xor0_shared_resources[1].end = mapbase_high + 0xff;
+
+        orion_xor00_resources[0].start = irq_0;
+        orion_xor00_resources[0].end = irq_0;
+        orion_xor01_resources[0].start = irq_1;
+        orion_xor01_resources[0].end = irq_1;
+
+        platform_device_register(&orion_xor0_shared);
+
+        orion_xor_init_channels(&orion_xor00_data, &orion_xor00_channel,
+                                &orion_xor01_data, &orion_xor01_channel);
+}
+
+/*****************************************************************************
+ * XOR1
+ ****************************************************************************/
+static struct resource orion_xor1_shared_resources[] = {
+        {
+                .name   = "xor 1 low",
+                .flags  = IORESOURCE_MEM,
+        }, {
+                .name   = "xor 1 high",
+                .flags  = IORESOURCE_MEM,
+        },
+};
+
+static struct platform_device orion_xor1_shared = {
+        .name           = MV_XOR_SHARED_NAME,
+        .id             = 1,
+        .dev            = {
+                .platform_data = &orion_xor_shared_data,
+        },
+        .num_resources  = ARRAY_SIZE(orion_xor1_shared_resources),
+        .resource       = orion_xor1_shared_resources,
+};
+
+static struct resource orion_xor10_resources[] = {
+        [0] = {
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct mv_xor_platform_data orion_xor10_data = {
+        .shared         = &orion_xor1_shared,
+        .hw_id          = 0,
+        .pool_size      = PAGE_SIZE,
+};
+
+static struct platform_device orion_xor10_channel = {
+        .name           = MV_XOR_NAME,
+        .id             = 2,
+        .num_resources  = ARRAY_SIZE(orion_xor10_resources),
+        .resource       = orion_xor10_resources,
+        .dev            = {
+                .dma_mask               = &orion_xor_dmamask,
+                .coherent_dma_mask      = DMA_BIT_MASK(64),
+                .platform_data          = &orion_xor10_data,
+        },
+};
+
+static struct resource orion_xor11_resources[] = {
+        [0] = {
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct mv_xor_platform_data orion_xor11_data = {
+        .shared         = &orion_xor1_shared,
+        .hw_id          = 1,
+        .pool_size      = PAGE_SIZE,
+};
+
+static struct platform_device orion_xor11_channel = {
+        .name           = MV_XOR_NAME,
+        .id             = 3,
+        .num_resources  = ARRAY_SIZE(orion_xor11_resources),
+        .resource       = orion_xor11_resources,
+        .dev            = {
+                .dma_mask               = &orion_xor_dmamask,
+                .coherent_dma_mask      = DMA_BIT_MASK(64),
+                .platform_data          = &orion_xor11_data,
+        },
+};
+
+void __init orion_xor1_init(unsigned long mapbase_low,
+                            unsigned long mapbase_high,
+                            unsigned long irq_0,
+                            unsigned long irq_1)
+{
+        orion_xor1_shared_resources[0].start = mapbase_low;
+        orion_xor1_shared_resources[0].end = mapbase_low + 0xff;
+        orion_xor1_shared_resources[1].start = mapbase_high;
+        orion_xor1_shared_resources[1].end = mapbase_high + 0xff;
+
+        orion_xor10_resources[0].start = irq_0;
+        orion_xor10_resources[0].end = irq_0;
+        orion_xor11_resources[0].start = irq_1;
+        orion_xor11_resources[0].end = irq_1;
+
+        platform_device_register(&orion_xor1_shared);
+
+        orion_xor_init_channels(&orion_xor10_data, &orion_xor10_channel,
+                                &orion_xor11_data, &orion_xor11_channel);
+}
+
+/*****************************************************************************
+ * EHCI
+ ****************************************************************************/
+static struct orion_ehci_data orion_ehci_data = {
+        .phy_version    = EHCI_PHY_NA,
+};
+
+static u64 ehci_dmamask = DMA_BIT_MASK(32);
+
+
+/*****************************************************************************
+ * EHCI0
+ ****************************************************************************/
+static struct resource orion_ehci_resources[2];
+
+static struct platform_device orion_ehci = {
+        .name           = "orion-ehci",
+        .id             = 0,
+        .dev            = {
+                .dma_mask               = &ehci_dmamask,
+                .coherent_dma_mask      = DMA_BIT_MASK(32),
+                .platform_data          = &orion_ehci_data,
+        },
+};
+
+void __init orion_ehci_init(struct mbus_dram_target_info *mbus_dram_info,
+                            unsigned long mapbase,
+                            unsigned long irq)
+{
+        orion_ehci_data.dram = mbus_dram_info;
+        fill_resources(&orion_ehci, orion_ehci_resources, mapbase, SZ_4K - 1,
+                       irq);
+
+        platform_device_register(&orion_ehci);
+}
+
+/*****************************************************************************
+ * EHCI1
+ ****************************************************************************/
+static struct resource orion_ehci_1_resources[2];
+
+static struct platform_device orion_ehci_1 = {
+        .name           = "orion-ehci",
+        .id             = 1,
+        .dev            = {
+                .dma_mask               = &ehci_dmamask,
+                .coherent_dma_mask      = DMA_BIT_MASK(32),
+                .platform_data          = &orion_ehci_data,
+        },
+};
+
+void __init orion_ehci_1_init(struct mbus_dram_target_info *mbus_dram_info,
+                              unsigned long mapbase,
+                              unsigned long irq)
+{
+        orion_ehci_data.dram = mbus_dram_info;
+        fill_resources(&orion_ehci_1, orion_ehci_1_resources,
+                       mapbase, SZ_4K - 1, irq);
+
+        platform_device_register(&orion_ehci_1);
+}
+
+/*****************************************************************************
+ * EHCI2
+ ****************************************************************************/
+static struct resource orion_ehci_2_resources[2];
+
+static struct platform_device orion_ehci_2 = {
+        .name           = "orion-ehci",
+        .id             = 2,
+        .dev            = {
+                .dma_mask               = &ehci_dmamask,
+                .coherent_dma_mask      = DMA_BIT_MASK(32),
+                .platform_data          = &orion_ehci_data,
+        },
+};
+
+void __init orion_ehci_2_init(struct mbus_dram_target_info *mbus_dram_info,
+                              unsigned long mapbase,
+                              unsigned long irq)
+{
+        orion_ehci_data.dram = mbus_dram_info;
+        fill_resources(&orion_ehci_2, orion_ehci_2_resources,
+                       mapbase, SZ_4K - 1, irq);
+
+        platform_device_register(&orion_ehci_2);
+}
+
+/*****************************************************************************
+ * SATA
+ ****************************************************************************/
+static struct resource orion_sata_resources[2] = {
+        {
+                .name   = "sata base",
+        }, {
+                .name   = "sata irq",
+        },
+};
+
+static struct platform_device orion_sata = {
+        .name           = "sata_mv",
+        .id             = 0,
+        .dev            = {
+                .coherent_dma_mask      = DMA_BIT_MASK(32),
+        },
+};
+
+void __init orion_sata_init(struct mv_sata_platform_data *sata_data,
+                            struct mbus_dram_target_info *mbus_dram_info,
+                            unsigned long mapbase,
+                            unsigned long irq)
+{
+        sata_data->dram = mbus_dram_info;
+        orion_sata.dev.platform_data = sata_data;
+        fill_resources(&orion_sata, orion_sata_resources,
+                       mapbase, 0x5000 - 1, irq);
+
+        platform_device_register(&orion_sata);
+}
+
+/*****************************************************************************
+ * Cryptographic Engines and Security Accelerator (CESA)
+ ****************************************************************************/
+static struct resource orion_crypto_resources[] = {
+        {
+                .name   = "regs",
+        }, {
+                .name   = "crypto interrupt",
+        }, {
+                .name   = "sram",
+                .flags  = IORESOURCE_MEM,
+        },
+};
+
+static struct platform_device orion_crypto = {
+        .name           = "mv_crypto",
+        .id             = -1,
+};
+
+void __init orion_crypto_init(unsigned long mapbase,
+                              unsigned long srambase,
+                              unsigned long sram_size,
+                              unsigned long irq)
+{
+        fill_resources(&orion_crypto, orion_crypto_resources,
+                       mapbase, 0xffff, irq);
+        orion_crypto.num_resources = 3;
+        orion_crypto_resources[2].start = srambase;
+        orion_crypto_resources[2].end = srambase + sram_size - 1;
+
+        platform_device_register(&orion_crypto);
+}
diff --git a/arch/arm/plat-orion/gpio.c b/arch/arm/plat-orion/gpio.c
index a431a138f40..5b4fffab1eb 100644
--- a/arch/arm/plat-orion/gpio.c
+++ b/arch/arm/plat-orion/gpio.c
@@ -321,59 +321,16 @@ EXPORT_SYMBOL(orion_gpio_set_blink);
  *        polarity    LEVEL          mask
  *
  ****************************************************************************/
-static void gpio_irq_ack(struct irq_data *d)
-{
-        struct orion_gpio_chip *ochip = irq_data_get_irq_chip_data(d);
-        int type = irqd_get_trigger_type(d);
-
-        if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
-                int pin = d->irq - ochip->secondary_irq_base;
-
-                writel(~(1 << pin), GPIO_EDGE_CAUSE(ochip));
-        }
-}
-
-static void gpio_irq_mask(struct irq_data *d)
-{
-        struct orion_gpio_chip *ochip = irq_data_get_irq_chip_data(d);
-        int type = irqd_get_trigger_type(d);
-        void __iomem *reg;
-        int pin;
-
-        if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
-                reg = GPIO_EDGE_MASK(ochip);
-        else
-                reg = GPIO_LEVEL_MASK(ochip);
-
-        pin = d->irq - ochip->secondary_irq_base;
-
-        writel(readl(reg) & ~(1 << pin), reg);
-}
-
-static void gpio_irq_unmask(struct irq_data *d)
-{
-        struct orion_gpio_chip *ochip = irq_data_get_irq_chip_data(d);
-        int type = irqd_get_trigger_type(d);
-        void __iomem *reg;
-        int pin;
-
-        if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
-                reg = GPIO_EDGE_MASK(ochip);
-        else
-                reg = GPIO_LEVEL_MASK(ochip);
-
-        pin = d->irq - ochip->secondary_irq_base;
-
-        writel(readl(reg) | (1 << pin), reg);
-}
 
 static int gpio_irq_set_type(struct irq_data *d, u32 type)
 {
-        struct orion_gpio_chip *ochip = irq_data_get_irq_chip_data(d);
+        struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
+        struct irq_chip_type *ct = irq_data_get_chip_type(d);
+        struct orion_gpio_chip *ochip = gc->private;
         int pin;
         u32 u;
 
-        pin = d->irq - ochip->secondary_irq_base;
+        pin = d->irq - gc->irq_base;
 
         u = readl(GPIO_IO_CONF(ochip)) & (1 << pin);
         if (!u) {
@@ -382,18 +339,14 @@ static int gpio_irq_set_type(struct irq_data *d, u32 type)
                 return -EINVAL;
         }
 
-        /*
-         * Set edge/level type.
-         */
-        if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
-                __irq_set_handler_locked(d->irq, handle_edge_irq);
-        } else if (type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
-                __irq_set_handler_locked(d->irq, handle_level_irq);
-        } else {
-                printk(KERN_ERR "failed to set irq=%d (type=%d)\n",
-                       d->irq, type);
+        type &= IRQ_TYPE_SENSE_MASK;
+        if (type == IRQ_TYPE_NONE)
                 return -EINVAL;
-        }
+
+        /* Check if we need to change chip and handler */
+        if (!(ct->type & type))
+                if (irq_setup_alt_chip(d, type))
+                        return -EINVAL;
 
         /*
          * Configure interrupt polarity.
@@ -425,19 +378,12 @@ static int gpio_irq_set_type(struct irq_data *d, u32 type)
         return 0;
 }
 
-struct irq_chip orion_gpio_irq_chip = {
-        .name           = "orion_gpio_irq",
-        .irq_ack        = gpio_irq_ack,
-        .irq_mask       = gpio_irq_mask,
-        .irq_unmask     = gpio_irq_unmask,
-        .irq_set_type   = gpio_irq_set_type,
-};
-
 void __init orion_gpio_init(int gpio_base, int ngpio,
                             u32 base, int mask_offset, int secondary_irq_base)
 {
         struct orion_gpio_chip *ochip;
-        int i;
+        struct irq_chip_generic *gc;
+        struct irq_chip_type *ct;
 
         if (orion_gpio_chip_count == ARRAY_SIZE(orion_gpio_chips))
                 return;
@@ -471,15 +417,29 @@ void __init orion_gpio_init(int gpio_base, int ngpio,
         writel(0, GPIO_EDGE_MASK(ochip));
         writel(0, GPIO_LEVEL_MASK(ochip));
 
-        for (i = 0; i < ngpio; i++) {
-                unsigned int irq = secondary_irq_base + i;
-
-                irq_set_chip_and_handler(irq, &orion_gpio_irq_chip,
-                                         handle_level_irq);
-                irq_set_chip_data(irq, ochip);
-                irq_set_status_flags(irq, IRQ_LEVEL);
-                set_irq_flags(irq, IRQF_VALID);
-        }
+        gc = irq_alloc_generic_chip("orion_gpio_irq", 2, secondary_irq_base,
+                                    ochip->base, handle_level_irq);
+        gc->private = ochip;
+
+        ct = gc->chip_types;
+        ct->regs.mask = ochip->mask_offset + GPIO_LEVEL_MASK_OFF;
+        ct->type = IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW;
+        ct->chip.irq_mask = irq_gc_mask_clr_bit;
+        ct->chip.irq_unmask = irq_gc_mask_set_bit;
+        ct->chip.irq_set_type = gpio_irq_set_type;
+
+        ct++;
+        ct->regs.mask = ochip->mask_offset + GPIO_EDGE_MASK_OFF;
+        ct->regs.ack = GPIO_EDGE_CAUSE_OFF;
+        ct->type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
+        ct->chip.irq_ack = irq_gc_ack;
+        ct->chip.irq_mask = irq_gc_mask_clr_bit;
+        ct->chip.irq_unmask = irq_gc_mask_set_bit;
+        ct->chip.irq_set_type = gpio_irq_set_type;
+        ct->handler = handle_edge_irq;
+
+        irq_setup_generic_chip(gc, IRQ_MSK(ngpio), IRQ_GC_INIT_MASK_CACHE,
+                               IRQ_NOREQUEST, IRQ_LEVEL | IRQ_NOPROBE);
 }
 
 void orion_gpio_irq_handler(int pinoff)
diff --git a/arch/arm/plat-orion/include/plat/common.h b/arch/arm/plat-orion/include/plat/common.h
new file mode 100644
index 00000000000..a63c357e2ab
--- /dev/null
+++ b/arch/arm/plat-orion/include/plat/common.h
@@ -0,0 +1,117 @@
+/*
+ * arch/arm/plat-orion/include/plat/common.h
+ *
+ * Marvell Orion SoC common setup code used by different mach-/common.c
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __PLAT_COMMON_H
+#include <linux/mv643xx_eth.h>
+
+struct dsa_platform_data;
+
+void __init orion_uart0_init(unsigned int membase,
+                             resource_size_t mapbase,
+                             unsigned int irq,
+                             unsigned int uartclk);
+
+void __init orion_uart1_init(unsigned int membase,
+                             resource_size_t mapbase,
+                             unsigned int irq,
+                             unsigned int uartclk);
+
+void __init orion_uart2_init(unsigned int membase,
+                             resource_size_t mapbase,
+                             unsigned int irq,
+                             unsigned int uartclk);
+
+void __init orion_uart3_init(unsigned int membase,
+                             resource_size_t mapbase,
+                             unsigned int irq,
+                             unsigned int uartclk);
+
+void __init orion_rtc_init(unsigned long mapbase,
+                           unsigned long irq);
+
+void __init orion_ge00_init(struct mv643xx_eth_platform_data *eth_data,
+                            struct mbus_dram_target_info *mbus_dram_info,
+                            unsigned long mapbase,
+                            unsigned long irq,
+                            unsigned long irq_err,
+                            int tclk);
+
+void __init orion_ge01_init(struct mv643xx_eth_platform_data *eth_data,
+                            struct mbus_dram_target_info *mbus_dram_info,
+                            unsigned long mapbase,
+                            unsigned long irq,
+                            unsigned long irq_err,
+                            int tclk);
+
+void __init orion_ge10_init(struct mv643xx_eth_platform_data *eth_data,
+                            struct mbus_dram_target_info *mbus_dram_info,
+                            unsigned long mapbase,
+                            unsigned long irq,
+                            unsigned long irq_err,
+                            int tclk);
+
+void __init orion_ge11_init(struct mv643xx_eth_platform_data *eth_data,
+                            struct mbus_dram_target_info *mbus_dram_info,
+                            unsigned long mapbase,
+                            unsigned long irq,
+                            unsigned long irq_err,
+                            int tclk);
+
+void __init orion_ge00_switch_init(struct dsa_platform_data *d,
+                                   int irq);
+void __init orion_i2c_init(unsigned long mapbase,
+                           unsigned long irq,
+                           unsigned long freq_m);
+
+void __init orion_i2c_1_init(unsigned long mapbase,
+                             unsigned long irq,
+                             unsigned long freq_m);
+
+void __init orion_spi_init(unsigned long mapbase,
+                           unsigned long tclk);
+
+void __init orion_spi_1_init(unsigned long mapbase,
+                             unsigned long tclk);
+
+void __init orion_wdt_init(unsigned long tclk);
+
+void __init orion_xor0_init(struct mbus_dram_target_info *mbus_dram_info,
+                            unsigned long mapbase_low,
+                            unsigned long mapbase_high,
+                            unsigned long irq_0,
+                            unsigned long irq_1);
+
+void __init orion_xor1_init(unsigned long mapbase_low,
+                            unsigned long mapbase_high,
+                            unsigned long irq_0,
+                            unsigned long irq_1);
+
+void __init orion_ehci_init(struct mbus_dram_target_info *mbus_dram_info,
+                            unsigned long mapbase,
+                            unsigned long irq);
+
+void __init orion_ehci_1_init(struct mbus_dram_target_info *mbus_dram_info,
+                              unsigned long mapbase,
+                              unsigned long irq);
+
+void __init orion_ehci_2_init(struct mbus_dram_target_info *mbus_dram_info,
+                              unsigned long mapbase,
+                              unsigned long irq);
+
+void __init orion_sata_init(struct mv_sata_platform_data *sata_data,
+                            struct mbus_dram_target_info *mbus_dram_info,
+                            unsigned long mapbase,
+                            unsigned long irq);
+
+void __init orion_crypto_init(unsigned long mapbase,
+                              unsigned long srambase,
+                              unsigned long sram_size,
+                              unsigned long irq);
+#endif
diff --git a/arch/arm/plat-orion/include/plat/gpio.h b/arch/arm/plat-orion/include/plat/gpio.h
index 5578b9803fc..3075b9fdde8 100644
--- a/arch/arm/plat-orion/include/plat/gpio.h
+++ b/arch/arm/plat-orion/include/plat/gpio.h
@@ -39,7 +39,6 @@ void __init orion_gpio_init(int gpio_base, int ngpio,
 /*
  * GPIO interrupt handling.
  */
-extern struct irq_chip orion_gpio_irq_chip;
 void orion_gpio_irq_handler(int irqoff);
 
 
diff --git a/arch/arm/plat-orion/include/plat/mpp.h b/arch/arm/plat-orion/include/plat/mpp.h
new file mode 100644
index 00000000000..723adce99f4
--- /dev/null
+++ b/arch/arm/plat-orion/include/plat/mpp.h
@@ -0,0 +1,34 @@
+/*
+ * arch/arm/plat-orion/include/plat/mpp.h
+ *
+ * Marvell Orion SoC MPP handling.
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __PLAT_MPP_H
+#define __PLAT_MPP_H
+
+#define MPP_NUM(x)      ((x) & 0xff)
+#define MPP_SEL(x)      (((x) >> 8) & 0xf)
+
+/* This is the generic MPP macro, without any variant information.
+   Each machine architecture is expected to extend this with further
+   bit fields indicating which MPP configurations are valid for a
+   specific variant. */
+
+#define GENERIC_MPP(_num, _sel, _in, _out) ( \
+        /* MPP number */                ((_num) & 0xff) | \
+        /* MPP select value */          (((_sel) & 0xf) << 8) | \
+        /* may be input signal */       ((!!(_in)) << 12) | \
+        /* may be output signal */      ((!!(_out)) << 13))
+
+#define MPP_INPUT_MASK          GENERIC_MPP(0, 0x0, 1, 0)
+#define MPP_OUTPUT_MASK         GENERIC_MPP(0, 0x0, 0, 1)
+
+void __init orion_mpp_conf(unsigned int *mpp_list, unsigned int variant_mask,
+                           unsigned int mpp_max, unsigned int dev_bus);
+
+#endif
diff --git a/arch/arm/plat-orion/irq.c b/arch/arm/plat-orion/irq.c
index d8d638e09f8..2d5b9c1ef38 100644
--- a/arch/arm/plat-orion/irq.c
+++ b/arch/arm/plat-orion/irq.c
@@ -14,52 +14,21 @@
 #include <linux/io.h>
 #include <plat/irq.h>
 
-static void orion_irq_mask(struct irq_data *d)
-{
-        void __iomem *maskaddr = irq_data_get_irq_chip_data(d);
-        u32 mask;
-
-        mask = readl(maskaddr);
-        mask &= ~(1 << (d->irq & 31));
-        writel(mask, maskaddr);
-}
-
-static void orion_irq_unmask(struct irq_data *d)
-{
-        void __iomem *maskaddr = irq_data_get_irq_chip_data(d);
-        u32 mask;
-
-        mask = readl(maskaddr);
-        mask |= 1 << (d->irq & 31);
-        writel(mask, maskaddr);
-}
-
-static struct irq_chip orion_irq_chip = {
-        .name           = "orion_irq",
-        .irq_mask       = orion_irq_mask,
-        .irq_mask_ack   = orion_irq_mask,
-        .irq_unmask     = orion_irq_unmask,
-};
-
 void __init orion_irq_init(unsigned int irq_start, void __iomem *maskaddr)
 {
-        unsigned int i;
+        struct irq_chip_generic *gc;
+        struct irq_chip_type *ct;
 
         /*
          * Mask all interrupts initially.
          */
         writel(0, maskaddr);
 
-        /*
-         * Register IRQ sources.
-         */
-        for (i = 0; i < 32; i++) {
-                unsigned int irq = irq_start + i;
-
-                irq_set_chip_and_handler(irq, &orion_irq_chip,
-                                         handle_level_irq);
-                irq_set_chip_data(irq, maskaddr);
-                irq_set_status_flags(irq, IRQ_LEVEL);
-                set_irq_flags(irq, IRQF_VALID);
-        }
+        gc = irq_alloc_generic_chip("orion_irq", 1, irq_start, maskaddr,
+                                    handle_level_irq);
+        ct = gc->chip_types;
+        ct->chip.irq_mask = irq_gc_mask_clr_bit;
+        ct->chip.irq_unmask = irq_gc_mask_set_bit;
+        irq_setup_generic_chip(gc, IRQ_MSK(32), IRQ_GC_INIT_MASK_CACHE,
+                               IRQ_NOREQUEST, IRQ_LEVEL | IRQ_NOPROBE);
 }
diff --git a/arch/arm/plat-orion/mpp.c b/arch/arm/plat-orion/mpp.c
new file mode 100644
index 00000000000..91553432711
--- /dev/null
+++ b/arch/arm/plat-orion/mpp.c
@@ -0,0 +1,78 @@
+/*
+ * arch/arm/plat-orion/mpp.c
+ *
+ * MPP functions for Marvell orion SoCs
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/mbus.h>
+#include <linux/io.h>
+#include <linux/gpio.h>
+#include <mach/hardware.h>
+#include <plat/mpp.h>
+
+/* Address of the ith MPP control register */
+static __init unsigned long mpp_ctrl_addr(unsigned int i,
+                                          unsigned long dev_bus)
+{
+        return dev_bus + (i) * 4;
+}
+
+
+void __init orion_mpp_conf(unsigned int *mpp_list, unsigned int variant_mask,
+                           unsigned int mpp_max, unsigned int dev_bus)
+{
+        unsigned int mpp_nr_regs = (1 + mpp_max/8);
+        u32 mpp_ctrl[mpp_nr_regs];
+        int i;
+
+        printk(KERN_DEBUG "initial MPP regs:");
+        for (i = 0; i < mpp_nr_regs; i++) {
+                mpp_ctrl[i] = readl(mpp_ctrl_addr(i, dev_bus));
+                printk(" %08x", mpp_ctrl[i]);
+        }
+        printk("\n");
+
+        for ( ; *mpp_list; mpp_list++) {
+                unsigned int num = MPP_NUM(*mpp_list);
+                unsigned int sel = MPP_SEL(*mpp_list);
+                int shift, gpio_mode;
+
+                if (num > mpp_max) {
+                        printk(KERN_ERR "orion_mpp_conf: invalid MPP "
+                                        "number (%u)\n", num);
+                        continue;
+                }
+                if (variant_mask & !(*mpp_list & variant_mask)) {
+                        printk(KERN_WARNING
+                               "orion_mpp_conf: requested MPP%u config "
+                               "unavailable on this hardware\n", num);
+                        continue;
+                }
+
+                shift = (num & 7) << 2;
+                mpp_ctrl[num / 8] &= ~(0xf << shift);
+                mpp_ctrl[num / 8] |= sel << shift;
+
+                gpio_mode = 0;
+                if (*mpp_list & MPP_INPUT_MASK)
+                        gpio_mode |= GPIO_INPUT_OK;
+                if (*mpp_list & MPP_OUTPUT_MASK)
+                        gpio_mode |= GPIO_OUTPUT_OK;
+                if (sel != 0)
+                        gpio_mode = 0;
+                orion_gpio_set_valid(num, gpio_mode);
+        }
+
+        printk(KERN_DEBUG "  final MPP regs:");
+        for (i = 0; i < mpp_nr_regs; i++) {
+                writel(mpp_ctrl[i], mpp_ctrl_addr(i, dev_bus));
+                printk(" %08x", mpp_ctrl[i]);
+        }
+        printk("\n");
+}
diff --git a/arch/arm/plat-s5p/irq-gpioint.c b/arch/arm/plat-s5p/irq-gpioint.c
index cd6d67c8382..135abda31c9 100644
--- a/arch/arm/plat-s5p/irq-gpioint.c
+++ b/arch/arm/plat-s5p/irq-gpioint.c
@@ -41,72 +41,11 @@ struct s5p_gpioint_bank {
 
 LIST_HEAD(banks);
 
-static int s5p_gpioint_get_offset(struct irq_data *data)
+static int s5p_gpioint_set_type(struct irq_data *d, unsigned int type)
 {
-        struct s3c_gpio_chip *chip = irq_data_get_irq_handler_data(data);
-        return data->irq - chip->irq_base;
-}
-
-static void s5p_gpioint_ack(struct irq_data *data)
-{
-        struct s3c_gpio_chip *chip = irq_data_get_irq_handler_data(data);
-        int group, offset, pend_offset;
-        unsigned int value;
-
-        group = chip->group;
-        offset = s5p_gpioint_get_offset(data);
-        pend_offset = REG_OFFSET(group);
-
-        value = __raw_readl(GPIO_BASE(chip) + PEND_OFFSET + pend_offset);
-        value |= BIT(offset);
-        __raw_writel(value, GPIO_BASE(chip) + PEND_OFFSET + pend_offset);
-}
-
-static void s5p_gpioint_mask(struct irq_data *data)
-{
-        struct s3c_gpio_chip *chip = irq_data_get_irq_handler_data(data);
-        int group, offset, mask_offset;
-        unsigned int value;
-
-        group = chip->group;
-        offset = s5p_gpioint_get_offset(data);
-        mask_offset = REG_OFFSET(group);
-
-        value = __raw_readl(GPIO_BASE(chip) + MASK_OFFSET + mask_offset);
-        value |= BIT(offset);
-        __raw_writel(value, GPIO_BASE(chip) + MASK_OFFSET + mask_offset);
-}
-
-static void s5p_gpioint_unmask(struct irq_data *data)
-{
-        struct s3c_gpio_chip *chip = irq_data_get_irq_handler_data(data);
-        int group, offset, mask_offset;
-        unsigned int value;
-
-        group = chip->group;
-        offset = s5p_gpioint_get_offset(data);
-        mask_offset = REG_OFFSET(group);
-
-        value = __raw_readl(GPIO_BASE(chip) + MASK_OFFSET + mask_offset);
-        value &= ~BIT(offset);
-        __raw_writel(value, GPIO_BASE(chip) + MASK_OFFSET + mask_offset);
-}
-
-static void s5p_gpioint_mask_ack(struct irq_data *data)
-{
-        s5p_gpioint_mask(data);
-        s5p_gpioint_ack(data);
-}
-
-static int s5p_gpioint_set_type(struct irq_data *data, unsigned int type)
-{
-        struct s3c_gpio_chip *chip = irq_data_get_irq_handler_data(data);
-        int group, offset, con_offset;
-        unsigned int value;
-
-        group = chip->group;
-        offset = s5p_gpioint_get_offset(data);
-        con_offset = REG_OFFSET(group);
+        struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
+        struct irq_chip_type *ct = gc->chip_types;
+        unsigned int shift = (d->irq - gc->irq_base) << 2;
 
         switch (type) {
         case IRQ_TYPE_EDGE_RISING:
@@ -130,23 +69,12 @@ static int s5p_gpioint_set_type(struct irq_data *data, unsigned int type)
                 return -EINVAL;
         }
 
-        value = __raw_readl(GPIO_BASE(chip) + CON_OFFSET + con_offset);
-        value &= ~(0x7 << (offset * 0x4));
-        value |= (type << (offset * 0x4));
-        __raw_writel(value, GPIO_BASE(chip) + CON_OFFSET + con_offset);
-
+        gc->type_cache &= ~(0x7 << shift);
+        gc->type_cache |= type << shift;
+        writel(gc->type_cache, gc->reg_base + ct->regs.type);
         return 0;
 }
 
-static struct irq_chip s5p_gpioint = {
-        .name           = "s5p_gpioint",
-        .irq_ack        = s5p_gpioint_ack,
-        .irq_mask       = s5p_gpioint_mask,
-        .irq_mask_ack   = s5p_gpioint_mask_ack,
-        .irq_unmask     = s5p_gpioint_unmask,
-        .irq_set_type   = s5p_gpioint_set_type,
-};
-
 static void s5p_gpioint_handler(unsigned int irq, struct irq_desc *desc)
 {
         struct s5p_gpioint_bank *bank = irq_get_handler_data(irq);
@@ -179,9 +107,10 @@ static void s5p_gpioint_handler(unsigned int irq, struct irq_desc *desc)
 static __init int s5p_gpioint_add(struct s3c_gpio_chip *chip)
 {
         static int used_gpioint_groups = 0;
-        int irq, group = chip->group;
-        int i;
+        int group = chip->group;
         struct s5p_gpioint_bank *bank = NULL;
+        struct irq_chip_generic *gc;
+        struct irq_chip_type *ct;
 
         if (used_gpioint_groups >= S5P_GPIOINT_GROUP_COUNT)
                 return -ENOMEM;
@@ -211,19 +140,28 @@ static __init int s5p_gpioint_add(struct s3c_gpio_chip *chip)
          * chained GPIO irq has been successfully registered, allocate new gpio
          * int group and assign irq nubmers
          */
-
         chip->irq_base = S5P_GPIOINT_BASE +
                          used_gpioint_groups * S5P_GPIOINT_GROUP_SIZE;
         used_gpioint_groups++;
 
         bank->chips[group - bank->start] = chip;
-        for (i = 0; i < chip->chip.ngpio; i++) {
-                irq = chip->irq_base + i;
-                irq_set_chip(irq, &s5p_gpioint);
-                irq_set_handler_data(irq, chip);
-                irq_set_handler(irq, handle_level_irq);
-                set_irq_flags(irq, IRQF_VALID);
-        }
+
+        gc = irq_alloc_generic_chip("s5p_gpioint", 1, chip->irq_base,
+                                    (void __iomem *)GPIO_BASE(chip),
+                                    handle_level_irq);
+        if (!gc)
+                return -ENOMEM;
+        ct = gc->chip_types;
+        ct->chip.irq_ack = irq_gc_ack;
+        ct->chip.irq_mask = irq_gc_mask_set_bit;
+        ct->chip.irq_unmask = irq_gc_mask_clr_bit;
+        ct->chip.irq_set_type = s5p_gpioint_set_type,
+        ct->regs.ack = PEND_OFFSET + REG_OFFSET(chip->group);
+        ct->regs.mask = MASK_OFFSET + REG_OFFSET(chip->group);
+        ct->regs.type = CON_OFFSET + REG_OFFSET(chip->group);
+        irq_setup_generic_chip(gc, IRQ_MSK(chip->chip.ngpio),
+                               IRQ_GC_INIT_MASK_CACHE,
+                               IRQ_NOREQUEST | IRQ_NOPROBE, 0);
         return 0;
 }
 
diff --git a/arch/arm/plat-s5p/irq.c b/arch/arm/plat-s5p/irq.c
index 5560b12035d..a97c08957f4 100644
--- a/arch/arm/plat-s5p/irq.c
+++ b/arch/arm/plat-s5p/irq.c
@@ -64,11 +64,7 @@ void __init s5p_init_irq(u32 *vic, u32 num_vic)
                 vic_init(VA_VIC(irq), VIC_BASE(irq), vic[irq], 0);
 #endif
 
-        s3c_init_vic_timer_irq(IRQ_TIMER0_VIC, IRQ_TIMER0);
-        s3c_init_vic_timer_irq(IRQ_TIMER1_VIC, IRQ_TIMER1);
-        s3c_init_vic_timer_irq(IRQ_TIMER2_VIC, IRQ_TIMER2);
-        s3c_init_vic_timer_irq(IRQ_TIMER3_VIC, IRQ_TIMER3);
-        s3c_init_vic_timer_irq(IRQ_TIMER4_VIC, IRQ_TIMER4);
+        s3c_init_vic_timer_irq(5, IRQ_TIMER0);
 
         s3c_init_uart_irqs(uart_irqs, ARRAY_SIZE(uart_irqs));
 }
diff --git a/arch/arm/plat-samsung/Kconfig b/arch/arm/plat-samsung/Kconfig
index be72100b81b..4d79519d19a 100644
--- a/arch/arm/plat-samsung/Kconfig
+++ b/arch/arm/plat-samsung/Kconfig
@@ -8,6 +8,7 @@ config PLAT_SAMSUNG
         bool
         depends on PLAT_S3C24XX || ARCH_S3C64XX || PLAT_S5P
         select NO_IOPORT
+        select GENERIC_IRQ_CHIP
         default y
         help
           Base platform code for all Samsung SoC based systems
diff --git a/arch/arm/plat-samsung/include/plat/irq-vic-timer.h b/arch/arm/plat-samsung/include/plat/irq-vic-timer.h
index a90b53431b5..5b9c42fd32d 100644
--- a/arch/arm/plat-samsung/include/plat/irq-vic-timer.h
+++ b/arch/arm/plat-samsung/include/plat/irq-vic-timer.h
@@ -10,4 +10,4 @@
  * published by the Free Software Foundation.
 */
 
-extern void s3c_init_vic_timer_irq(unsigned int vic, unsigned int timer);
+extern void s3c_init_vic_timer_irq(unsigned int num, unsigned int timer_irq);
diff --git a/arch/arm/plat-samsung/include/plat/uncompress.h b/arch/arm/plat-samsung/include/plat/uncompress.h
index 7d6ed7263d5..ee48e12a1e7 100644
--- a/arch/arm/plat-samsung/include/plat/uncompress.h
+++ b/arch/arm/plat-samsung/include/plat/uncompress.h
@@ -18,8 +18,8 @@ typedef unsigned int upf_t;	/* cannot include linux/serial_core.h */
 
 /* uart setup */
 
-static unsigned int fifo_mask;
-static unsigned int fifo_max;
+unsigned int fifo_mask;
+unsigned int fifo_max;
 
 /* forward declerations */
 
diff --git a/arch/arm/plat-samsung/irq-uart.c b/arch/arm/plat-samsung/irq-uart.c
index 4d4e571af55..32582c0958e 100644
--- a/arch/arm/plat-samsung/irq-uart.c
+++ b/arch/arm/plat-samsung/irq-uart.c
@@ -27,60 +27,6 @@
 /* Note, we make use of the fact that the parent IRQs, IRQ_UART[0..3]
  * are consecutive when looking up the interrupt in the demux routines.
  */
-
-static inline void __iomem *s3c_irq_uart_base(struct irq_data *data)
-{
-        struct s3c_uart_irq *uirq = irq_data_get_irq_chip_data(data);
-        return uirq->regs;
-}
-
-static inline unsigned int s3c_irq_uart_bit(unsigned int irq)
-{
-        return irq & 3;
-}
-
-static void s3c_irq_uart_mask(struct irq_data *data)
-{
-        void __iomem *regs = s3c_irq_uart_base(data);
-        unsigned int bit = s3c_irq_uart_bit(data->irq);
-        u32 reg;
-
-        reg = __raw_readl(regs + S3C64XX_UINTM);
-        reg |= (1 << bit);
-        __raw_writel(reg, regs + S3C64XX_UINTM);
-}
-
-static void s3c_irq_uart_maskack(struct irq_data *data)
-{
-        void __iomem *regs = s3c_irq_uart_base(data);
-        unsigned int bit = s3c_irq_uart_bit(data->irq);
-        u32 reg;
-
-        reg = __raw_readl(regs + S3C64XX_UINTM);
-        reg |= (1 << bit);
-        __raw_writel(reg, regs + S3C64XX_UINTM);
-        __raw_writel(1 << bit, regs + S3C64XX_UINTP);
-}
-
-static void s3c_irq_uart_unmask(struct irq_data *data)
-{
-        void __iomem *regs = s3c_irq_uart_base(data);
-        unsigned int bit = s3c_irq_uart_bit(data->irq);
-        u32 reg;
-
-        reg = __raw_readl(regs + S3C64XX_UINTM);
-        reg &= ~(1 << bit);
-        __raw_writel(reg, regs + S3C64XX_UINTM);
-}
-
-static void s3c_irq_uart_ack(struct irq_data *data)
-{
-        void __iomem *regs = s3c_irq_uart_base(data);
-        unsigned int bit = s3c_irq_uart_bit(data->irq);
-
-        __raw_writel(1 << bit, regs + S3C64XX_UINTP);
-}
-
 static void s3c_irq_demux_uart(unsigned int irq, struct irq_desc *desc)
 {
         struct s3c_uart_irq *uirq = desc->irq_data.handler_data;
@@ -97,30 +43,25 @@ static void s3c_irq_demux_uart(unsigned int irq, struct irq_desc *desc)
                 generic_handle_irq(base + 3);
 }
 
-static struct irq_chip s3c_irq_uart = {
-        .name           = "s3c-uart",
-        .irq_mask       = s3c_irq_uart_mask,
-        .irq_unmask     = s3c_irq_uart_unmask,
-        .irq_mask_ack   = s3c_irq_uart_maskack,
-        .irq_ack        = s3c_irq_uart_ack,
-};
-
 static void __init s3c_init_uart_irq(struct s3c_uart_irq *uirq)
 {
         void __iomem *reg_base = uirq->regs;
-        unsigned int irq;
-        int offs;
+        struct irq_chip_generic *gc;
+        struct irq_chip_type *ct;
 
         /* mask all interrupts at the start. */
         __raw_writel(0xf, reg_base + S3C64XX_UINTM);
 
-        for (offs = 0; offs < 3; offs++) {
-                irq = uirq->base_irq + offs;
-
-                irq_set_chip_and_handler(irq, &s3c_irq_uart, handle_level_irq);
-                irq_set_chip_data(irq, uirq);
-                set_irq_flags(irq, IRQF_VALID);
-        }
+        gc = irq_alloc_generic_chip("s3c-uart", 1, uirq->base_irq, reg_base,
+                                    handle_level_irq);
+        ct = gc->chip_types;
+        ct->chip.irq_ack = irq_gc_ack;
+        ct->chip.irq_mask = irq_gc_mask_set_bit;
+        ct->chip.irq_unmask = irq_gc_mask_clr_bit;
+        ct->regs.ack = S3C64XX_UINTP;
+        ct->regs.mask = S3C64XX_UINTM;
+        irq_setup_generic_chip(gc, IRQ_MSK(4), IRQ_GC_INIT_MASK_CACHE,
+                               IRQ_NOREQUEST | IRQ_NOPROBE, 0);
 
         irq_set_handler_data(uirq->parent_irq, uirq);
         irq_set_chained_handler(uirq->parent_irq, s3c_irq_demux_uart);
diff --git a/arch/arm/plat-samsung/irq-vic-timer.c b/arch/arm/plat-samsung/irq-vic-timer.c
index d6ad66ab929..a607546ddbd 100644
--- a/arch/arm/plat-samsung/irq-vic-timer.c
+++ b/arch/arm/plat-samsung/irq-vic-timer.c
@@ -28,60 +28,43 @@ static void s3c_irq_demux_vic_timer(unsigned int irq, struct irq_desc *desc)
 }
 
 /* We assume the IRQ_TIMER0..IRQ_TIMER4 range is continuous. */
-
-static void s3c_irq_timer_mask(struct irq_data *data)
-{
-        u32 reg = __raw_readl(S3C64XX_TINT_CSTAT);
-        u32 mask = (u32)data->chip_data;
-
-        reg &= 0x1f;  /* mask out pending interrupts */
-        reg &= ~mask;
-        __raw_writel(reg, S3C64XX_TINT_CSTAT);
-}
-
-static void s3c_irq_timer_unmask(struct irq_data *data)
+static void s3c_irq_timer_ack(struct irq_data *d)
 {
-        u32 reg = __raw_readl(S3C64XX_TINT_CSTAT);
-        u32 mask = (u32)data->chip_data;
+        struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
+        u32 mask = (1 << 5) << (d->irq - gc->irq_base);
 
-        reg &= 0x1f;  /* mask out pending interrupts */
-        reg |= mask;
-        __raw_writel(reg, S3C64XX_TINT_CSTAT);
+        irq_reg_writel(mask | gc->mask_cache, gc->reg_base);
 }
 
-static void s3c_irq_timer_ack(struct irq_data *data)
-{
-        u32 reg = __raw_readl(S3C64XX_TINT_CSTAT);
-        u32 mask = (u32)data->chip_data;
-
-        reg &= 0x1f;
-        reg |= mask << 5;
-        __raw_writel(reg, S3C64XX_TINT_CSTAT);
-}
-
-static struct irq_chip s3c_irq_timer = {
-        .name           = "s3c-timer",
-        .irq_mask       = s3c_irq_timer_mask,
-        .irq_unmask     = s3c_irq_timer_unmask,
-        .irq_ack        = s3c_irq_timer_ack,
-};
-
 /**
  * s3c_init_vic_timer_irq() - initialise timer irq chanined off VIC.\
- * @parent_irq: The parent IRQ on the VIC for the timer.
- * @timer_irq: The IRQ to be used for the timer.
+ * @num: Number of timers to initialize
+ * @timer_irq: Base IRQ number to be used for the timers.
  *
  * Register the necessary IRQ chaining and support for the timer IRQs
  * chained of the VIC.
  */
-void __init s3c_init_vic_timer_irq(unsigned int parent_irq,
-                                   unsigned int timer_irq)
+void __init s3c_init_vic_timer_irq(unsigned int num, unsigned int timer_irq)
 {
+        unsigned int pirq[5] = { IRQ_TIMER0_VIC, IRQ_TIMER1_VIC, IRQ_TIMER2_VIC,
+                                 IRQ_TIMER3_VIC, IRQ_TIMER4_VIC };
+        struct irq_chip_generic *s3c_tgc;
+        struct irq_chip_type *ct;
+        unsigned int i;
 
-        irq_set_chained_handler(parent_irq, s3c_irq_demux_vic_timer);
-        irq_set_handler_data(parent_irq, (void *)timer_irq);
+        s3c_tgc = irq_alloc_generic_chip("s3c-timer", 1, timer_irq,
+                                         S3C64XX_TINT_CSTAT, handle_level_irq);
+        ct = s3c_tgc->chip_types;
+        ct->chip.irq_mask = irq_gc_mask_clr_bit;
+        ct->chip.irq_unmask = irq_gc_mask_set_bit;
+        ct->chip.irq_ack = s3c_irq_timer_ack;
+        irq_setup_generic_chip(s3c_tgc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE,
+                               IRQ_NOREQUEST | IRQ_NOPROBE, 0);
+        /* Clear the upper bits of the mask_cache*/
+        s3c_tgc->mask_cache &= 0x1f;
 
-        irq_set_chip_and_handler(timer_irq, &s3c_irq_timer, handle_level_irq);
-        irq_set_chip_data(timer_irq, (void *)(1 << (timer_irq - IRQ_TIMER0)));
-        set_irq_flags(timer_irq, IRQF_VALID);
+        for (i = 0; i < num; i++, timer_irq++) {
+                irq_set_chained_handler(pirq[i], s3c_irq_demux_vic_timer);
+                irq_set_handler_data(pirq[i], (void *)timer_irq);
+        }
 }