6 files changed, 393 insertions, 0 deletions

diff --git a/arch/powerpc/boot/dts/p1022rdk.dts b/arch/powerpc/boot/dts/p1022rdk.dts
new file mode 100644
index 00000000000..51d82de223f
--- /dev/null
+++ b/arch/powerpc/boot/dts/p1022rdk.dts
@@ -0,0 +1,188 @@
+/*
+ * P1022 RDK 32-bit Physical Address Map Device Tree Source
+ *
+ * Copyright 2012 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/include/ "fsl/p1022si-pre.dtsi"
+/ {
+        model = "fsl,P1022RDK";
+        compatible = "fsl,P1022RDK";
+
+        memory {
+                device_type = "memory";
+        };
+
+        board_lbc: lbc: localbus@ffe05000 {
+                /* The P1022 RDK does not have any localbus devices */
+                status = "disabled";
+        };
+
+        board_soc: soc: soc@ffe00000 {
+                ranges = <0x0 0x0 0xffe00000 0x100000>;
+
+                i2c@3100 {
+                        wm8960:codec@1a {
+                                compatible = "wlf,wm8960";
+                                reg = <0x1a>;
+                                /* MCLK source is a stand-alone oscillator */
+                                clock-frequency = <12288000>;
+                        };
+                        rtc@68 {
+                                compatible = "stm,m41t62";
+                                reg = <0x68>;
+                        };
+                        adt7461@4c{
+                                compatible = "adi,adt7461";
+                                reg = <0x4c>;
+                        };
+                        zl6100@21{
+                                compatible = "isil,zl6100";
+                                reg = <0x21>;
+                        };
+                        zl6100@24{
+                                compatible = "isil,zl6100";
+                                reg = <0x24>;
+                        };
+                        zl6100@26{
+                                compatible = "isil,zl6100";
+                                reg = <0x26>;
+                        };
+                        zl6100@29{
+                                compatible = "isil,zl6100";
+                                reg = <0x29>;
+                        };
+                };
+
+                spi@7000 {
+                        flash@0 {
+                                #address-cells = <1>;
+                                #size-cells = <1>;
+                                compatible = "spansion,m25p80";
+                                reg = <0>;
+                                spi-max-frequency = <1000000>;
+                                partition@0 {
+                                        label = "full-spi-flash";
+                                        reg = <0x00000000 0x00100000>;
+                                };
+                        };
+                };
+
+                ssi@15000 {
+                        fsl,mode = "i2s-slave";
+                        codec-handle = <&wm8960>;
+                };
+
+                usb@22000 {
+                        phy_type = "ulpi";
+                };
+
+                usb@23000 {
+                        phy_type = "ulpi";
+                };
+
+                mdio@24000 {
+                        phy0: ethernet-phy@0 {
+                                interrupts = <3 1 0 0>;
+                                reg = <0x1>;
+                        };
+                        phy1: ethernet-phy@1 {
+                                interrupts = <9 1 0 0>;
+                                reg = <0x2>;
+                        };
+                };
+
+                mdio@25000 {
+                        tbi0: tbi-phy@11 {
+                                reg = <0x11>;
+                                device_type = "tbi-phy";
+                        };
+                };
+
+                ethernet@b0000 {
+                        phy-handle = <&phy0>;
+                        phy-connection-type = "rgmii-id";
+                };
+
+                ethernet@b1000 {
+                        phy-handle = <&phy1>;
+                        tbi-handle = <&tbi0>;
+                        phy-connection-type = "sgmii";
+                };
+        };
+
+        pci0: pcie@ffe09000 {
+                ranges = <0x2000000 0x0 0xe0000000 0 0xa0000000 0x0 0x20000000
+                          0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
+                reg = <0x0 0xffe09000 0 0x1000>;
+                pcie@0 {
+                        ranges = <0x2000000 0x0 0xe0000000
+                                  0x2000000 0x0 0xe0000000
+                                  0x0 0x20000000
+
+                                  0x1000000 0x0 0x0
+                                  0x1000000 0x0 0x0
+                                  0x0 0x100000>;
+                };
+        };
+
+        pci1: pcie@ffe0a000 {
+                ranges = <0x2000000 0x0 0xe0000000 0 0xc0000000 0x0 0x20000000
+                          0x1000000 0x0 0x00000000 0 0xffc20000 0x0 0x10000>;
+                reg = <0 0xffe0a000 0 0x1000>;
+                pcie@0 {
+                        ranges = <0x2000000 0x0 0xe0000000
+                                  0x2000000 0x0 0xe0000000
+                                  0x0 0x20000000
+
+                                  0x1000000 0x0 0x0
+                                  0x1000000 0x0 0x0
+                                  0x0 0x100000>;
+                };
+        };
+
+        pci2: pcie@ffe0b000 {
+                ranges = <0x2000000 0x0 0xe0000000 0 0x80000000 0x0 0x20000000
+                          0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
+                reg = <0 0xffe0b000 0 0x1000>;
+                pcie@0 {
+                        ranges = <0x2000000 0x0 0xe0000000
+                                  0x2000000 0x0 0xe0000000
+                                  0x0 0x20000000
+
+                                  0x1000000 0x0 0x0
+                                  0x1000000 0x0 0x0
+                                  0x0 0x100000>;
+                };
+        };
+};
+
+/include/ "fsl/p1022si-post.dtsi"
diff --git a/arch/powerpc/configs/mpc85xx_defconfig b/arch/powerpc/configs/mpc85xx_defconfig
index 8b5bda27d24..cf815e847cd 100644
--- a/arch/powerpc/configs/mpc85xx_defconfig
+++ b/arch/powerpc/configs/mpc85xx_defconfig
@@ -30,6 +30,7 @@ CONFIG_MPC85xx_DS=y
 CONFIG_MPC85xx_RDB=y
 CONFIG_P1010_RDB=y
 CONFIG_P1022_DS=y
+CONFIG_P1022_RDK=y
 CONFIG_P1023_RDS=y
 CONFIG_SOCRATES=y
 CONFIG_KSI8560=y
diff --git a/arch/powerpc/configs/mpc85xx_smp_defconfig b/arch/powerpc/configs/mpc85xx_smp_defconfig
index b0974e7e98a..502cd9e027e 100644
--- a/arch/powerpc/configs/mpc85xx_smp_defconfig
+++ b/arch/powerpc/configs/mpc85xx_smp_defconfig
@@ -32,6 +32,7 @@ CONFIG_MPC85xx_DS=y
 CONFIG_MPC85xx_RDB=y
 CONFIG_P1010_RDB=y
 CONFIG_P1022_DS=y
+CONFIG_P1022_RDK=y
 CONFIG_P1023_RDS=y
 CONFIG_SOCRATES=y
 CONFIG_KSI8560=y
diff --git a/arch/powerpc/platforms/85xx/Kconfig b/arch/powerpc/platforms/85xx/Kconfig
index 31f0618ec67..02d02a09942 100644
--- a/arch/powerpc/platforms/85xx/Kconfig
+++ b/arch/powerpc/platforms/85xx/Kconfig
@@ -104,6 +104,13 @@ config P1022_DS
         help
           This option enables support for the Freescale P1022DS reference board.
 
+config P1022_RDK
+        bool "Freescale / iVeia P1022 RDK"
+        select DEFAULT_UIMAGE
+        help
+          This option enables support for the Freescale / iVeia P1022RDK
+          reference board.
+
 config P1023_RDS
         bool "Freescale P1023 RDS"
         select DEFAULT_UIMAGE
diff --git a/arch/powerpc/platforms/85xx/Makefile b/arch/powerpc/platforms/85xx/Makefile
index d99268aef55..76f679cb04a 100644
--- a/arch/powerpc/platforms/85xx/Makefile
+++ b/arch/powerpc/platforms/85xx/Makefile
@@ -15,6 +15,7 @@ obj-$(CONFIG_MPC85xx_MDS) += mpc85xx_mds.o
 obj-$(CONFIG_MPC85xx_RDB) += mpc85xx_rdb.o
 obj-$(CONFIG_P1010_RDB)   += p1010rdb.o
 obj-$(CONFIG_P1022_DS)    += p1022_ds.o
+obj-$(CONFIG_P1022_RDK)   += p1022_rdk.o
 obj-$(CONFIG_P1023_RDS)   += p1023_rds.o
 obj-$(CONFIG_P2041_RDB)   += p2041_rdb.o corenet_ds.o
 obj-$(CONFIG_P3041_DS)    += p3041_ds.o corenet_ds.o
diff --git a/arch/powerpc/platforms/85xx/p1022_rdk.c b/arch/powerpc/platforms/85xx/p1022_rdk.c
new file mode 100644
index 00000000000..b3cf11b92e7
--- /dev/null
+++ b/arch/powerpc/platforms/85xx/p1022_rdk.c
@@ -0,0 +1,195 @@
+/*
+ * P1022 RDK board specific routines
+ *
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ *
+ * Author: Timur Tabi <timur@freescale.com>
+ *
+ * Based on p1022_ds.c
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2.  This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+#include <linux/pci.h>
+#include <linux/of_platform.h>
+#include <linux/memblock.h>
+#include <asm/div64.h>
+#include <asm/mpic.h>
+#include <asm/swiotlb.h>
+
+#include <sysdev/fsl_soc.h>
+#include <sysdev/fsl_pci.h>
+#include <asm/udbg.h>
+#include <asm/fsl_guts.h>
+#include "smp.h"
+
+#include "mpc85xx.h"
+
+#if defined(CONFIG_FB_FSL_DIU) || defined(CONFIG_FB_FSL_DIU_MODULE)
+
+/* DIU Pixel Clock bits of the CLKDVDR Global Utilities register */
+#define CLKDVDR_PXCKEN          0x80000000
+#define CLKDVDR_PXCKINV         0x10000000
+#define CLKDVDR_PXCKDLY         0x06000000
+#define CLKDVDR_PXCLK_MASK      0x00FF0000
+
+/**
+ * p1022rdk_set_monitor_port: switch the output to a different monitor port
+ */
+static void p1022rdk_set_monitor_port(enum fsl_diu_monitor_port port)
+{
+        if (port != FSL_DIU_PORT_DVI) {
+                pr_err("p1022rdk: unsupported monitor port %i\n", port);
+                return;
+        }
+}
+
+/**
+ * p1022rdk_set_pixel_clock: program the DIU's clock
+ *
+ * @pixclock: the wavelength, in picoseconds, of the clock
+ */
+void p1022rdk_set_pixel_clock(unsigned int pixclock)
+{
+        struct device_node *guts_np = NULL;
+        struct ccsr_guts __iomem *guts;
+        unsigned long freq;
+        u64 temp;
+        u32 pxclk;
+
+        /* Map the global utilities registers. */
+        guts_np = of_find_compatible_node(NULL, NULL, "fsl,p1022-guts");
+        if (!guts_np) {
+                pr_err("p1022rdk: missing global utilties device node\n");
+                return;
+        }
+
+        guts = of_iomap(guts_np, 0);
+        of_node_put(guts_np);
+        if (!guts) {
+                pr_err("p1022rdk: could not map global utilties device\n");
+                return;
+        }
+
+        /* Convert pixclock from a wavelength to a frequency */
+        temp = 1000000000000ULL;
+        do_div(temp, pixclock);
+        freq = temp;
+
+        /*
+         * 'pxclk' is the ratio of the platform clock to the pixel clock.
+         * This number is programmed into the CLKDVDR register, and the valid
+         * range of values is 2-255.
+         */
+        pxclk = DIV_ROUND_CLOSEST(fsl_get_sys_freq(), freq);
+        pxclk = clamp_t(u32, pxclk, 2, 255);
+
+        /* Disable the pixel clock, and set it to non-inverted and no delay */
+        clrbits32(&guts->clkdvdr,
+                  CLKDVDR_PXCKEN | CLKDVDR_PXCKDLY | CLKDVDR_PXCLK_MASK);
+
+        /* Enable the clock and set the pxclk */
+        setbits32(&guts->clkdvdr, CLKDVDR_PXCKEN | (pxclk << 16));
+
+        iounmap(guts);
+}
+
+/**
+ * p1022rdk_valid_monitor_port: set the monitor port for sysfs
+ */
+enum fsl_diu_monitor_port
+p1022rdk_valid_monitor_port(enum fsl_diu_monitor_port port)
+{
+        return FSL_DIU_PORT_DVI;
+}
+
+#endif
+
+void __init p1022_rdk_pic_init(void)
+{
+        struct mpic *mpic = mpic_alloc(NULL, 0, MPIC_BIG_ENDIAN |
+                MPIC_SINGLE_DEST_CPU,
+                0, 256, " OpenPIC  ");
+        BUG_ON(mpic == NULL);
+        mpic_init(mpic);
+}
+
+/*
+ * Setup the architecture
+ */
+static void __init p1022_rdk_setup_arch(void)
+{
+#ifdef CONFIG_PCI
+        struct device_node *np;
+#endif
+        dma_addr_t max = 0xffffffff;
+
+        if (ppc_md.progress)
+                ppc_md.progress("p1022_rdk_setup_arch()", 0);
+
+#ifdef CONFIG_PCI
+        for_each_compatible_node(np, "pci", "fsl,p1022-pcie") {
+                struct resource rsrc;
+                struct pci_controller *hose;
+
+                of_address_to_resource(np, 0, &rsrc);
+
+                if ((rsrc.start & 0xfffff) == 0x8000)
+                        fsl_add_bridge(np, 1);
+                else
+                        fsl_add_bridge(np, 0);
+
+                hose = pci_find_hose_for_OF_device(np);
+                max = min(max, hose->dma_window_base_cur +
+                          hose->dma_window_size);
+        }
+#endif
+
+#if defined(CONFIG_FB_FSL_DIU) || defined(CONFIG_FB_FSL_DIU_MODULE)
+        diu_ops.set_monitor_port        = p1022rdk_set_monitor_port;
+        diu_ops.set_pixel_clock         = p1022rdk_set_pixel_clock;
+        diu_ops.valid_monitor_port      = p1022rdk_valid_monitor_port;
+#endif
+
+        mpc85xx_smp_init();
+
+#ifdef CONFIG_SWIOTLB
+        if ((memblock_end_of_DRAM() - 1) > max) {
+                ppc_swiotlb_enable = 1;
+                set_pci_dma_ops(&swiotlb_dma_ops);
+                ppc_md.pci_dma_dev_setup = pci_dma_dev_setup_swiotlb;
+        }
+#endif
+
+        pr_info("Freescale / iVeia P1022 RDK reference board\n");
+}
+
+machine_device_initcall(p1022_rdk, mpc85xx_common_publish_devices);
+
+machine_arch_initcall(p1022_rdk, swiotlb_setup_bus_notifier);
+
+/*
+ * Called very early, device-tree isn't unflattened
+ */
+static int __init p1022_rdk_probe(void)
+{
+        unsigned long root = of_get_flat_dt_root();
+
+        return of_flat_dt_is_compatible(root, "fsl,p1022rdk");
+}
+
+define_machine(p1022_rdk) {
+        .name                   = "P1022 RDK",
+        .probe                  = p1022_rdk_probe,
+        .setup_arch             = p1022_rdk_setup_arch,
+        .init_IRQ               = p1022_rdk_pic_init,
+#ifdef CONFIG_PCI
+        .pcibios_fixup_bus      = fsl_pcibios_fixup_bus,
+#endif
+        .get_irq                = mpic_get_irq,
+        .restart                = fsl_rstcr_restart,
+        .calibrate_decr         = generic_calibrate_decr,
+        .progress               = udbg_progress,
+};